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Add initial Sonata board support
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This includes:
- Pin definitions in XDC file
- Modified build rules for FuseSoC
- A clock generator
- A top-level for Sonata
- A TCL file for Sonata

Co-authored-by: Marno van der Maas <[email protected]>
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@GregAC @marnovandermaas
GregAC and marnovandermaas committed Jan 25, 2024
1 parent af43c85 commit d9ec0d0
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85 changes: 85 additions & 0 deletions data/pins_sonata.xdc
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## Copyright lowRISC contributors.
## Licensed under the Apache License, Version 2.0, see LICENSE for details.
## SPDX-License-Identifier: Apache-2.0

## Clocks
create_clock -period 40.000 -name mainclk -waveform {0.000 20.000} [get_ports main_clk]
create_clock -period 100.000 -name tck -waveform {0.000 50.000} [get_ports tck_i]

## Reset
set_property PACKAGE_PIN R11 [get_ports {nrst_btn}]
set_property IOSTANDARD LVCMOS33 [get_ports {nrst_btn}]

## General purpose LEDs
set_property -dict { PACKAGE_PIN B13 IOSTANDARD LVCMOS33 } [get_ports {led_user[0]}];
set_property -dict { PACKAGE_PIN B14 IOSTANDARD LVCMOS33 } [get_ports {led_user[1]}];
set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS33 } [get_ports {led_user[2]}];
set_property -dict { PACKAGE_PIN B12 IOSTANDARD LVCMOS33 } [get_ports {led_user[3]}];
set_property -dict { PACKAGE_PIN B11 IOSTANDARD LVCMOS33 } [get_ports {led_user[4]}];
set_property -dict { PACKAGE_PIN A11 IOSTANDARD LVCMOS33 } [get_ports {led_user[5]}];
set_property -dict { PACKAGE_PIN F13 IOSTANDARD LVCMOS33 } [get_ports {led_user[6]}];
set_property -dict { PACKAGE_PIN F14 IOSTANDARD LVCMOS33 } [get_ports {led_user[7]}];

## JTAG test
set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports tck_i];
set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports td_i];
set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports td_o];
set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports tms_i];

## Switch and button input
set_property -dict { PACKAGE_PIN D12 IOSTANDARD LVCMOS33 } [get_ports {user_sw[0]}];
set_property -dict { PACKAGE_PIN D13 IOSTANDARD LVCMOS33 } [get_ports {user_sw[1]}];
set_property -dict { PACKAGE_PIN B16 IOSTANDARD LVCMOS33 } [get_ports {user_sw[2]}];
set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVCMOS33 } [get_ports {user_sw[3]}];
set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVCMOS33 } [get_ports {user_sw[4]}];
set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVCMOS33 } [get_ports {user_sw[5]}];
set_property -dict { PACKAGE_PIN A13 IOSTANDARD LVCMOS33 } [get_ports {user_sw[6]}];
set_property -dict { PACKAGE_PIN A14 IOSTANDARD LVCMOS33 } [get_ports {user_sw[7]}];
set_property -dict { PACKAGE_PIN F5 IOSTANDARD LVCMOS18 } [get_ports {nav_sw[0]}];
set_property -dict { PACKAGE_PIN D8 IOSTANDARD LVCMOS18 } [get_ports {nav_sw[1]}];
set_property -dict { PACKAGE_PIN C7 IOSTANDARD LVCMOS18 } [get_ports {nav_sw[2]}];
set_property -dict { PACKAGE_PIN E7 IOSTANDARD LVCMOS18 } [get_ports {nav_sw[3]}];
set_property -dict { PACKAGE_PIN D7 IOSTANDARD LVCMOS18 } [get_ports {nav_sw[4]}];

## CHERI error LEDs
set_property -dict { PACKAGE_PIN K6 IOSTANDARD LVCMOS33 } [get_ports {led_cherierr[0]}];
set_property -dict { PACKAGE_PIN L1 IOSTANDARD LVCMOS33 } [get_ports {led_cherierr[1]}];
set_property -dict { PACKAGE_PIN M1 IOSTANDARD LVCMOS33 } [get_ports {led_cherierr[2]}];
set_property -dict { PACKAGE_PIN K3 IOSTANDARD LVCMOS33 } [get_ports {led_cherierr[3]}];
set_property -dict { PACKAGE_PIN L3 IOSTANDARD LVCMOS33 } [get_ports {led_cherierr[4]}];
set_property -dict { PACKAGE_PIN N2 IOSTANDARD LVCMOS33 } [get_ports {led_cherierr[5]}];
set_property -dict { PACKAGE_PIN N1 IOSTANDARD LVCMOS33 } [get_ports {led_cherierr[6]}];
set_property -dict { PACKAGE_PIN M3 IOSTANDARD LVCMOS33 } [get_ports {led_cherierr[7]}];
set_property -dict { PACKAGE_PIN M2 IOSTANDARD LVCMOS33 } [get_ports {led_cherierr[8]}];

## Status LEDs
set_property -dict { PACKAGE_PIN K5 IOSTANDARD LVCMOS33 } [get_ports led_legacy];
set_property -dict { PACKAGE_PIN L4 IOSTANDARD LVCMOS33 } [get_ports led_cheri];
set_property -dict { PACKAGE_PIN L6 IOSTANDARD LVCMOS33 } [get_ports led_halted];
set_property -dict { PACKAGE_PIN L5 IOSTANDARD LVCMOS33 } [get_ports led_bootok];

## LCD display
set_property -dict { PACKAGE_PIN R6 IOSTANDARD LVCMOS33 } [get_ports lcd_rst];
set_property -dict { PACKAGE_PIN U4 IOSTANDARD LVCMOS33 } [get_ports lcd_dc];
set_property -dict { PACKAGE_PIN R3 IOSTANDARD LVCMOS33 } [get_ports lcd_copi];
set_property -dict { PACKAGE_PIN R5 IOSTANDARD LVCMOS33 } [get_ports lcd_clk];
set_property -dict { PACKAGE_PIN P5 IOSTANDARD LVCMOS33 } [get_ports lcd_cs];

## UART
set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports ser0_tx];
set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports ser0_rx];

## Switches
set_property PULLTYPE PULLUP [get_ports user_sw[*]]
set_property PULLTYPE PULLUP [get_ports nav_sw[*]]


set_output_delay -clock main_clk 0.000 [get_ports led_user]

set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports main_clk];

set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]

set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets tck_i]
27 changes: 26 additions & 1 deletion ibex_demo_system.core
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Expand Up @@ -33,6 +33,15 @@ filesets:
- rtl/fpga/top_cw312a35.sv
file_type: systemVerilogSource

files_sonata:
depend:
- lowrisc:ibex:rv_timer
- lowrisc:ibex:fpga_xilinx_shared
files:
- rtl/fpga/top_sonata.sv
- rtl/fpga/clkgen_sonata.sv
file_type: systemVerilogSource

files_verilator:
depend:
- lowrisc:ibex:sim_shared
Expand Down Expand Up @@ -60,7 +69,10 @@ filesets:
- data/pins_cw312a35.xdc
file_type: xdc


files_constraints_sonata:
files:
- data/pins_sonata.xdc
file_type: xdc

parameters:
# XXX: This parameter needs to be absolute, or relative to the *.runs/synth_1
Expand Down Expand Up @@ -131,6 +143,19 @@ targets:
- PRIM_DEFAULT_IMPL=prim_pkg::ImplXilinx
flags:
use_bscane_tap: true
synth_sonata:
<<: *default_target
default_tool: vivado
filesets_append:
- files_sonata
- files_constraints_sonata
toplevel: top_sonata
tools:
vivado:
part: "xc7a50tcsg324-1"
parameters:
- SRAMInitFile
- PRIM_DEFAULT_IMPL=prim_pkg::ImplXilinx

sim:
<<: *default_target
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83 changes: 83 additions & 0 deletions rtl/fpga/clkgen_sonata.sv
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// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0

module clkgen_sonata (
input IO_CLK,
output IO_CLK_BUF,
input IO_RST_N,
output clk_sys,
output rst_sys_n
);
logic locked_pll;
logic io_clk_buf;
logic clk_50_buf;
logic clk_50_unbuf;
logic clk_fb_buf;
logic clk_fb_unbuf;

// input buffer
IBUF io_clk_ibuf(
.I (IO_CLK),
.O (io_clk_buf)
);

PLLE2_ADV #(
.BANDWIDTH ("OPTIMIZED"),
.COMPENSATION ("ZHOLD"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT (34),
.CLKFBOUT_PHASE (0.000),
.CLKOUT0_DIVIDE (17),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKIN1_PERIOD (40.000)
) pll (
.CLKFBOUT (clk_fb_unbuf),
.CLKOUT0 (clk_50_unbuf),
.CLKOUT1 (),
.CLKOUT2 (),
.CLKOUT3 (),
.CLKOUT4 (),
.CLKOUT5 (),
// Input clock control
.CLKFBIN (clk_fb_buf),
.CLKIN1 (io_clk_buf),
.CLKIN2 (1'b0),
// Tied to always select the primary input clock
.CLKINSEL (1'b1),
// Ports for dynamic reconfiguration
.DADDR (7'h0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'h0),
.DO (),
.DRDY (),
.DWE (1'b0),
// Other control and status signals
.LOCKED (locked_pll),
.PWRDWN (1'b0),
// Do not reset PLL on external reset, otherwise ILA disconnects at a reset
.RST (1'b0));

// output buffering
BUFG clk_fb_bufg (
.I (clk_fb_unbuf),
.O (clk_fb_buf)
);

BUFG clk_50_bufg (
.I (clk_50_unbuf),
.O (clk_50_buf)
);

assign IO_CLK_BUF = io_clk_buf;

// outputs
// clock
assign clk_sys = clk_50_buf;

// reset
assign rst_sys_n = locked_pll & IO_RST_N;
endmodule
105 changes: 105 additions & 0 deletions rtl/fpga/top_sonata.sv
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// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0

// Ibex demo system top level for the Sonata board
module top_sonata (
input main_clk,
input nrst_btn,

output logic [7:0] led_user,
output logic led_bootok,
output logic led_halted,
output logic led_cheri,
output logic led_legacy,
output logic [8:0] led_cherierr,

input logic [4:0] nav_sw,
input logic [7:0] user_sw,

output logic lcd_rst,
output logic lcd_dc,
output logic lcd_copi,
output logic lcd_clk,
output logic lcd_cs,

output logic ser0_tx,
input logic ser0_rx,

input logic tck_i,
input logic tms_i,
input logic td_i,
output logic td_o
);
parameter SRAMInitFile = "";

logic top_rst_n;
logic mainclk_buf;
logic clk_sys, rst_sys_n;
logic [7:0] reset_counter;

logic [4:0] nav_sw_n;
logic [7:0] user_sw_n;

initial begin
reset_counter = 0;
end

always_ff @(posedge mainclk_buf) begin
if (reset_counter != 8'hff) begin
reset_counter <= reset_counter + 8'd1;
end
end

assign top_rst_n = reset_counter < 8'd5 ? 1'b1 :
reset_counter < 8'd200 ? 1'b0 :
nrst_btn;

assign led_bootok = 1'b1;

// Switch inputs have pull-ups and switches pull to ground when on. Invert here so CPU sees 1 for
// on and 0 for off.
assign nav_sw_n = ~nav_sw;
assign user_sw_n = ~user_sw;

// No LCD backlight FPGA IO on v0.2 board, so leave this unconnected
logic lcd_backlight;

ibex_demo_system #(
.GpiWidth(13),
.GpoWidth(12),
.PwmWidth(12),
.SRAMInitFile(SRAMInitFile)
) u_ibex_demo_system (
.clk_sys_i(clk_sys),
.rst_sys_ni(rst_sys_n),

.gp_i({user_sw_n, nav_sw_n}),
.gp_o({led_user, lcd_backlight, lcd_dc, lcd_rst, lcd_cs}),

.uart_rx_i(ser0_rx),
.uart_tx_o(ser0_tx),

.pwm_o({led_cherierr, led_legacy, led_cheri, led_halted}),

.spi_rx_i(1'b0),
.spi_tx_o(lcd_copi),
.spi_sck_o(lcd_clk),

.trst_ni(rst_sys_n),
.tms_i,
.tck_i,
.td_i,
.td_o
);

// Produce 50 MHz system clock from 25 MHz Sonata board clock
clkgen_sonata clkgen(
.IO_CLK(main_clk),
.IO_CLK_BUF(mainclk_buf),
.IO_RST_N(top_rst_n),
.clk_sys,
.rst_sys_n
);

endmodule
33 changes: 33 additions & 0 deletions util/sonata-openocd-cfg.tcl
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# Copyright lowRISC contributors.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0

adapter driver ftdi
transport select jtag

ftdi_vid_pid 0x0403 0x6011
ftdi_channel 1
ftdi_layout_init 0x0088 0x008b
reset_config none

# Configure JTAG chain and the target processor
set _CHIPNAME riscv

# Ibex Demo System JTAG IDCODE
set _EXPECTED_ID 0x11001CDF

jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id $_EXPECTED_ID -ignore-version
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME riscv -chain-position $_TARGETNAME

adapter speed 10000

riscv set_prefer_sba on
gdb_report_data_abort enable
gdb_report_register_access_error enable
gdb_breakpoint_override hard

reset_config none

init
halt

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