From 49996e63ea13dbf15ac1746f323648b5d04b9cfd Mon Sep 17 00:00:00 2001
From: Marno van der Maas <mvdmaas+git@lowrisc.org>
Date: Thu, 12 Oct 2023 17:17:59 +0100
Subject: [PATCH] Update feature list

---
 README.md | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/README.md b/README.md
index c57d6b86..ff896bea 100644
--- a/README.md
+++ b/README.md
@@ -7,8 +7,8 @@ This an example RISC-V SoC targeting the Arty-A7 FPGA board. It comprises the
 following features:
 
 * RISC-V debug support (using the [PULP RISC-V Debug Module](https://github.com/pulp-platform/riscv-dbg))
-* A UART
-* GPIO (output only for now)
+* UART
+* GPIO
 * Timer
 * SPI
 * A basic peripheral to write ASCII output to a file and halt simulation from software