diff --git a/dv/verilator/demo_system_verilator_lint.vlt b/dv/verilator/demo_system_verilator_lint.vlt index fa85196f..de875f9e 100644 --- a/dv/verilator/demo_system_verilator_lint.vlt +++ b/dv/verilator/demo_system_verilator_lint.vlt @@ -23,3 +23,6 @@ lint_off -rule IMPERFECTSCH -file "*pulp_riscv_dbg*" lint_off -rule DECLFILENAME -file "*pulp_riscv_dbg*" lint_off -rule PINMISSING -file "*pulp_riscv_dbg*" lint_off -rule UNUSED -file "*ibex_register_file_fpga*" + +lint_off -rule UNOPTFLAT -file "*/lowrisc_prim_fifo_0/rtl/prim_fifo_async_simple.sv" +lint_off -rule WIDTHEXPAND -file "*pulp_riscv_dbg/src/dm_mem.sv" diff --git a/ibex_demo_system.core b/ibex_demo_system.core index a74a12bf..667bbb8b 100644 --- a/ibex_demo_system.core +++ b/ibex_demo_system.core @@ -98,6 +98,8 @@ targets: parameters: - SRAMInitFile - PRIM_DEFAULT_IMPL=prim_pkg::ImplXilinx + flags: + use_bscane_tap: true synth_cw305: <<: *default_target default_tool: vivado @@ -112,6 +114,8 @@ targets: parameters: - SRAMInitFile - PRIM_DEFAULT_IMPL=prim_pkg::ImplXilinx + flags: + use_bscane_tap: true synth_cw312a35: <<: *default_target default_tool: vivado @@ -125,6 +129,8 @@ targets: parameters: - SRAMInitFile - PRIM_DEFAULT_IMPL=prim_pkg::ImplXilinx + flags: + use_bscane_tap: true sim: <<: *default_target diff --git a/ibex_demo_system_core.core b/ibex_demo_system_core.core index bca488ee..dbcb9834 100644 --- a/ibex_demo_system_core.core +++ b/ibex_demo_system_core.core @@ -10,6 +10,7 @@ filesets: - lowrisc:ibex:ibex_top - pulp:riscv:debug_module files: + - rtl/system/jtag_id_pkg.sv - rtl/system/ibex_demo_system.sv - rtl/system/dm_top.sv - rtl/system/debounce.sv @@ -21,7 +22,12 @@ filesets: - rtl/system/spi_top.sv file_type: systemVerilogSource + files_lint_verilator: + files: + - lint/verilator_waiver.vlt: {file_type: vlt} + targets: default: filesets: + - tool_verilator ? (files_lint_verilator) - files_rtl_demo_system diff --git a/pulp_riscv_dbg.core b/pulp_riscv_dbg.core index f6dbdb33..c0ce0bb0 100644 --- a/pulp_riscv_dbg.core +++ b/pulp_riscv_dbg.core @@ -19,24 +19,28 @@ filesets: - vendor/pulp_riscv_dbg/src/dm_mem.sv - vendor/pulp_riscv_dbg/src/dmi_cdc.sv - vendor/pulp_riscv_dbg/src/dmi_jtag.sv + - vendor/lowrisc_ip/ip/prim/rtl/prim_sync_reqack.sv file_type: systemVerilogSource - files_vivado: + files_xilinx_bscane_tap: files: - vendor/pulp_riscv_dbg/src/dmi_bscane_tap.sv file_type: systemVerilogSource + files_jtag_tap: + files: + - vendor/pulp_riscv_dbg/src/dmi_jtag_tap.sv + file_type: systemVerilogSource + files_verilator: depend: # common waivers - lowrisc:lint:common - files: - - vendor/pulp_riscv_dbg/src/dmi_jtag_tap.sv - file_type: systemVerilogSource targets: default: filesets: - files_src - tool_verilator ? (files_verilator) - - tool_vivado ? (files_vivado) + - "use_bscane_tap ? (files_xilinx_bscane_tap)" + - "!use_bscane_tap ? (files_jtag_tap)" diff --git a/rtl/fpga/top_artya7.sv b/rtl/fpga/top_artya7.sv index a01a3915..ffc5beaa 100644 --- a/rtl/fpga/top_artya7.sv +++ b/rtl/fpga/top_artya7.sv @@ -42,7 +42,13 @@ module top_artya7 ( .spi_rx_i(SPI_RX), .spi_tx_o(SPI_TX), - .spi_sck_o(SPI_SCK) + .spi_sck_o(SPI_SCK), + + .trst_ni(1'b1), + .tms_i(1'b0), + .tck_i(1'b0), + .td_i(1'b0), + .td_o() ); // Generating the system clock and reset for the FPGA. diff --git a/rtl/fpga/top_cw305.sv b/rtl/fpga/top_cw305.sv index 4b66fdbc..adecb388 100644 --- a/rtl/fpga/top_cw305.sv +++ b/rtl/fpga/top_cw305.sv @@ -49,7 +49,13 @@ module top_cw305 ( .spi_rx_i(1'b0), .spi_tx_o(), - .spi_sck_o() + .spi_sck_o(), + + .trst_ni(1'b1), + .tms_i(1'b0), + .tck_i(1'b0), + .td_i(1'b0), + .td_o() ); // clock source select: diff --git a/rtl/fpga/top_cw312a35.sv b/rtl/fpga/top_cw312a35.sv index 0562fd69..a94faf28 100644 --- a/rtl/fpga/top_cw312a35.sv +++ b/rtl/fpga/top_cw312a35.sv @@ -44,7 +44,13 @@ module top_cw312a35 ( .spi_rx_i(1'b0), .spi_tx_o(), - .spi_sck_o() + .spi_sck_o(), + + .trst_ni(1'b1), + .tms_i(1'b0), + .tck_i(1'b0), + .td_i(1'b0), + .td_o() ); // Generating the system clock and reset for the FPGA. diff --git a/rtl/system/dm_top.sv b/rtl/system/dm_top.sv index 20bde253..4de15a7e 100644 --- a/rtl/system/dm_top.sv +++ b/rtl/system/dm_top.sv @@ -43,7 +43,13 @@ module dm_top #( output logic [BusWidth/8-1:0] host_be_o, input logic host_gnt_i, input logic host_r_valid_i, - input logic [BusWidth-1:0] host_r_rdata_i + input logic [BusWidth-1:0] host_r_rdata_i, + + input logic tck_i, // JTAG test clock pad + input logic tms_i, // JTAG test mode select pad + input logic trst_ni, // JTAG test reset pad + input logic td_i, // JTAG test data input pad + output logic td_o // JTAG test data output pad ); `ASSERT_INIT(paramCheckNrHarts, NrHarts > 0) @@ -171,6 +177,8 @@ module dm_top #( .master_be_o ( host_be_o ), .master_gnt_i ( host_gnt_i ), .master_r_valid_i ( host_r_valid_i ), + .master_r_err_i ( 1'b0 ), + .master_r_other_err_i ( 1'b0 ), .master_r_rdata_i ( host_r_rdata_i ), .dmactive_i ( dmactive_o ), .sbaddress_i ( sbaddress_csrs_sba ), @@ -228,8 +236,6 @@ module dm_top #( .rdata_o ( device_rdata_o ) ); - // Bound-in DPI module replaces the TAP -`ifndef DMIDirectTAP // JTAG TAP dmi_jtag #( .IdcodeValue ( IdcodeValue ) @@ -237,6 +243,7 @@ module dm_top #( .clk_i (clk_i ), .rst_ni (rst_ni ), .testmode_i (testmode_i ), + .test_rst_ni (1'b1 ), .dmi_rst_no (dmi_rst_n ), .dmi_req_o (dmi_req ), @@ -248,13 +255,12 @@ module dm_top #( .dmi_resp_valid_i (dmi_rsp_valid), //JTAG - .tck_i (1'b0), - .tms_i (1'b0), - .trst_ni (1'b0), - .td_i (1'b0), - .td_o (), - .tdo_oe_o () + .tck_i, + .tms_i, + .trst_ni, + .td_i, + .td_o, + .tdo_oe_o () ); -`endif endmodule diff --git a/rtl/system/ibex_demo_system.sv b/rtl/system/ibex_demo_system.sv index 6e572307..2188a286 100644 --- a/rtl/system/ibex_demo_system.sv +++ b/rtl/system/ibex_demo_system.sv @@ -27,7 +27,13 @@ module ibex_demo_system #( output logic uart_tx_o, input logic spi_rx_i, output logic spi_tx_o, - output logic spi_sck_o + output logic spi_sck_o, + + input logic tck_i, // JTAG test clock pad + input logic tms_i, // JTAG test mode select pad + input logic trst_ni, // JTAG test reset pad + input logic td_i, // JTAG test data input pad + output logic td_o // JTAG test data output pad ); localparam logic [31:0] MEM_SIZE = 64 * 1024; // 64 KiB localparam logic [31:0] MEM_START = 32'h00100000; @@ -444,7 +450,8 @@ module ibex_demo_system #( if (DBG) begin : gen_dm_top dm_top #( - .NrHarts ( 1 ) + .NrHarts ( 1 ), + .IdcodeValue ( jtag_id_pkg::RV_DM_JTAG_IDCODE ) ) u_dm_top ( .clk_i (clk_sys_i), .rst_ni (rst_sys_ni), @@ -470,7 +477,13 @@ module ibex_demo_system #( .host_be_o (host_be[DbgHost]), .host_gnt_i (host_gnt[DbgHost]), .host_r_valid_i (host_rvalid[DbgHost]), - .host_r_rdata_i (host_rdata[DbgHost]) + .host_r_rdata_i (host_rdata[DbgHost]), + + .tck_i, + .tms_i, + .trst_ni, + .td_i, + .td_o ); end else begin : gen_no_dm assign dm_debug_req = 1'b0; diff --git a/rtl/system/jtag_id_pkg.sv b/rtl/system/jtag_id_pkg.sv new file mode 100644 index 00000000..a80d7389 --- /dev/null +++ b/rtl/system/jtag_id_pkg.sv @@ -0,0 +1,19 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// + +package jtag_id_pkg; + + // lowRISC JEDEC Manufacturer ID, bank 13 0xEF + localparam logic [10:0] JEDEC_MANUFACTURER_ID = {4'd12, 7'b110_1111}; + localparam logic [3:0] JTAG_VERSION = 4'h1; + + localparam logic [31:0] RV_DM_JTAG_IDCODE = { + JTAG_VERSION, // Version + {12'h100,4'h1}, // Part Number + JEDEC_MANUFACTURER_ID, // Manufacturer ID + 1'b1 // (fixed) + }; + +endpackage : jtag_id_pkg