diff --git a/timingApp/Db/eve.db b/timingApp/Db/eve.db
index deb84c1..2079468 100644
--- a/timingApp/Db/eve.db
+++ b/timingApp/Db/eve.db
@@ -3,10 +3,11 @@
 
 record(ai, "$(P)$(R)FPGAClk-Cte") {
   field(DESC, "FPGA Clock from EVG")
+  field(EGU, "Hz")
   field(SCAN, "1 second")
   field(PINI, "1")
   field(VAL, "124914500")
-  field(INP, "RA-RaMO:TI-EVG:FPGAClk-Cte")
+  field(INP, "AS-RaMO:TI-EVG:FPGAClk-Cte")
 }
 
 record(stringout, "$(P)$(R)IPAddr-Mon"){
@@ -29,6 +30,7 @@ record(bo, "$(P)$(R)DevEnbl-Sel") {
   field(ZNAM, "Dsbl")
   field(ONAM, "Enbl")
   field(OUT, "@timing.proto evre_ctrl_set($(P),$(R)) $(PORT)")
+  field(PINI, YES)
 }
 
 record(mbbiDirect, "$(P)$(R)DevEnblRaw") {
diff --git a/timingApp/Db/evg.db b/timingApp/Db/evg.db
index 25f3931..4b6c724 100644
--- a/timingApp/Db/evg.db
+++ b/timingApp/Db/evg.db
@@ -191,6 +191,7 @@ record(bo, "$(P)$(R)DevEnbl-Sel"){
   field(ZNAM, "Dsbl")
   field(ONAM, "Enbl")
   field(FLNK, "$(P)$(R)EVGEN")
+  field(PINI, YES)
 }
 
 record(longout, "$(P)$(R)cmd_ctrl_get") {
@@ -766,15 +767,6 @@ record(longout, "$(P)$(R)cmd_diginp_get1") {
 ########################################################################
 # Interlock map [56]
 
-record(mbboDirect, "$(P)$(R)ilock_mbbo") {
-  field(DESC, "interlock input to output map")
-}
-
-record(mbbiDirect, "$(P)$(R)ilock_mbbi") {
-  field(DESC, "interlock input to output map")
-  field(VAL, "1")
-}
-
 record(seq, "$(P)$(R)ilock_seq1") {
   field(DESC, "interlock input to output map")
   field(DOL1, "$(P)$(R)IntlkTbl0to15-Sts.B0")
@@ -1019,6 +1011,7 @@ record(bo, "$(P)$(R)IntlkCtrlEnbl-Sel") {
   field(ZNAM, "Dsbl")
   field(ONAM, "Enbl")
   field(FLNK, "$(P)$(R)IntlkCtrlEnblCalc")
+  field(PINI, YES)
 }
 
 record(bo, "$(P)$(R)IntlkCtrlRst-Sel") {
diff --git a/timingApp/Db/evr.db b/timingApp/Db/evr.db
index 0b66233..0e38fc1 100644
--- a/timingApp/Db/evr.db
+++ b/timingApp/Db/evr.db
@@ -3,10 +3,11 @@
 
 record(ai, "$(P)$(R)FPGAClk-Cte") {
   field(DESC, "FPGA Clock from EVG")
+  field(EGU, "Hz")
   field(SCAN, "1 second")
   field(PINI, "1")
   field(VAL, "124914500")
-  field(INP, "RA-RaMO:TI-EVG:FPGAClk-Cte")
+  field(INP, "AS-RaMO:TI-EVG:FPGAClk-Cte")
 }
 
 record(stringout, "$(P)$(R)IPAddr-Mon"){
@@ -29,6 +30,7 @@ record(bo, "$(P)$(R)DevEnbl-Sel") {
   field(ZNAM, "Dsbl")
   field(ONAM, "Enbl")
   field(OUT, "@timing.proto evre_ctrl_set($(P),$(R)) $(PORT)")
+  field(PINI, YES)
 }
 
 record(mbbiDirect, "$(P)$(R)DevEnblRaw") {
diff --git a/timingApp/Db/evre_otp.db b/timingApp/Db/evre_otp.db
index 447dfc0..432f95f 100644
--- a/timingApp/Db/evre_otp.db
+++ b/timingApp/Db/evre_otp.db
@@ -97,6 +97,7 @@ record(bo, "$(P)$(R)OTP$(num)State-Sel") {
   field(ZNAM, "Dsbl")
   field(ONAM, "Enbl")
   field(FLNK, "$(P)$(R)OTP$(num)RegAByte3")
+  field(PINI, YES)
 }
 
 record(bo, "$(P)$(R)OTP$(num)Polarity-Sel") {
diff --git a/timingApp/Db/fout.db b/timingApp/Db/fout.db
index 1fbef2d..c630794 100644
--- a/timingApp/Db/fout.db
+++ b/timingApp/Db/fout.db
@@ -75,6 +75,7 @@ record(bo, "$(P)$(R)DevEnbl-Sel"){
   field(ZNAM, "Dsbl")
   field(ONAM, "Enbl")
   field(OUT, "@timing.proto fout_ctrl_set($(P),$(R)) $(PORT)")
+  field(PINI, YES)
 }
 
 record(longout, "$(P)$(R)cmd_ctrl_get") {