From 1314d681edd8b3d42001607209956f7122a5b32f Mon Sep 17 00:00:00 2001 From: Augusto Fraga Giachero Date: Wed, 19 Jul 2023 14:10:40 -0300 Subject: [PATCH 01/43] Add script to automate generating binaries for all targets --- scripts/make-release.sh | 51 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) create mode 100755 scripts/make-release.sh diff --git a/scripts/make-release.sh b/scripts/make-release.sh new file mode 100755 index 000000000..93fe66124 --- /dev/null +++ b/scripts/make-release.sh @@ -0,0 +1,51 @@ +#!/bin/sh + +openmmc_root=$(realpath ..) +afc_timing_build_dir="${openmmc_root}/build/releases/afcv3.1-timing" +afc_bpm_build_dir="${openmmc_root}/build/releases/afcv3.1-bpm" +afc_v4_build_dir="${openmmc_root}/build/releases/afcv4" +bin_dir="${openmmc_root}/build/releases/binaries" +tag=$(git describe --tags) + +set -e + +rm -rf "${openmmc_root}/build/releases/" +mkdir -p "$bin_dir" +mkdir -p "$afc_timing_build_dir" +mkdir -p "$afc_bpm_build_dir" +mkdir -p "$afc_v4_build_dir" + +cd "$afc_timing_build_dir" +cmake "$openmmc_root" -DBOARD=afc-timing -DBOARD_RTM=8sfp -DCMAKE_BUILD_TYPE=RelWithDebInfo -DDISABLE_WATCHDOG=OFF +make + +cd "$afc_bpm_build_dir" +cmake "$openmmc_root" -DBOARD=afc-bpm -DVERSION=3.1 -DCMAKE_BUILD_TYPE=RelWithDebInfo -DDISABLE_WATCHDOG=OFF +make + +cd "$afc_v4_build_dir" +cmake "$openmmc_root" -DBOARD=afc-v4 -DCMAKE_BUILD_TYPE=RelWithDebInfo -DDISABLE_WATCHDOG=OFF +make + +cp "${afc_timing_build_dir}/out/openMMC.elf" "${bin_dir}/openMMC-afcv3.1-timing-${tag}.elf" +cp "${afc_timing_build_dir}/out/openMMC.bin" "${bin_dir}/openMMC-afcv3.1-timing-${tag}.bin" +cp "${afc_timing_build_dir}/out/openMMC.hpm" "${bin_dir}/openMMC-afcv3.1-timing-${tag}.hpm" + +cp "${afc_bpm_build_dir}/out/openMMC.elf" "${bin_dir}/openMMC-afcv3.1-bpm-${tag}.elf" +cp "${afc_bpm_build_dir}/out/openMMC.bin" "${bin_dir}/openMMC-afcv3.1-bpm-${tag}.bin" +cp "${afc_bpm_build_dir}/out/openMMC.hpm" "${bin_dir}/openMMC-afcv3.1-bpm-${tag}.hpm" + +cp "${afc_bpm_build_dir}/out/newboot.elf" "${bin_dir}/newboot-afcv3.1-${tag}.elf" +cp "${afc_bpm_build_dir}/out/newboot.bin" "${bin_dir}/newboot-afcv3.1-${tag}.bin" +cp "${afc_bpm_build_dir}/out/newboot.hpm" "${bin_dir}/newboot-afcv3.1-${tag}.hpm" + +cp "${afc_v4_build_dir}/out/openMMC.elf" "${bin_dir}/openMMC-afcv4-${tag}.elf" +cp "${afc_v4_build_dir}/out/openMMC.bin" "${bin_dir}/openMMC-afcv4-${tag}.bin" +cp "${afc_v4_build_dir}/out/openMMC.hpm" "${bin_dir}/openMMC-afcv4-${tag}.hpm" + +cp "${afc_v4_build_dir}/out/newboot.elf" "${bin_dir}/newboot-afcv4-${tag}.elf" +cp "${afc_v4_build_dir}/out/newboot.bin" "${bin_dir}/newboot-afcv4-${tag}.bin" +cp "${afc_v4_build_dir}/out/newboot.hpm" "${bin_dir}/newboot-afcv4-${tag}.hpm" + +cd "${bin_dir}" +sha256sum * > SHA256SUMS From 23d25904e6c164f09d15aebfcd1852d9d0754c5b Mon Sep 17 00:00:00 2001 From: Gustavo de Souza dos Reis Date: Thu, 3 Aug 2023 10:54:04 -0300 Subject: [PATCH 02/43] Add instructions to update firmware via serial port using nxpprog --- README.md | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/README.md b/README.md index b1544c88e..6c751d14a 100644 --- a/README.md +++ b/README.md @@ -103,6 +103,18 @@ To upgrade the bootloader, use ipmitool -I lan -H host_name_mch -A none -T 0x82 -m 0x20 -t (112 + num_slot*2 in hexadecimal) hpm upgrade newboot.hpm activate +### nxpprog +> :warning: **Disclaimer:** Only supported in AFCv4.0.2 + +In AFCv4, it's possible to program the firmware and bootloader via serial port using [nxpprog](https://github.com/lnls-dig/nxpprog). In order to use it, install nxpprog and then execute the following commands: +To upgrade the application, use + + ./nxpprog.py --addr 0x20000 --control + +To upgrade the bootloader, use + + ./nxpprog.py --control + ## Debugging It is possible to debug the MMC firmware using OpenOCD and GDB. First, connect OpenOCD with the debug probe using the `out/openocd.cfg` file generated by cmake in the build directory: From 90428cff3308c7c1b6eb20292d00c628eccf1b3e Mon Sep 17 00:00:00 2001 From: Gustavo de Souza dos Reis Date: Mon, 21 Aug 2023 14:06:54 -0300 Subject: [PATCH 03/43] Fix IPMI FRU Write command returning invalid data --- modules/fru.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/modules/fru.c b/modules/fru.c index 2a22a43aa..c4a469207 100644 --- a/modules/fru.c +++ b/modules/fru.c @@ -260,7 +260,7 @@ size_t fru_write( uint8_t id, uint8_t *tx_buff, uint16_t offset, size_t len ) memcpy( &fru[id].buffer[offset], tx_buff, len ); ret_val = len; } else { - ret_val = fru[id].cfg.write_f( fru[id].cfg.eeprom_id, offset, tx_buff, len, 0 ); + ret_val = fru[id].cfg.write_f( fru[id].cfg.eeprom_id, offset, tx_buff, len, 10 ); } return ret_val; } @@ -341,5 +341,15 @@ IPMI_HANDLER(ipmi_storage_write_fru_data_cmd, NETFN_STORAGE, IPMI_WRITE_FRU_DATA rsp->data[len++] = 0; rsp->completion_code = IPMI_CC_PARAM_OUT_OF_RANGE; } + + /* + * If count == 0, it may indicate that the fru_write function + * failed somehow. + */ + + if (count == 0) { + rsp->completion_code = IPMI_CC_UNSPECIFIED_ERROR; + return ; + } rsp->data_len = len; } From 0b6193ab3357083b5d13f32993d800d14f2ad937 Mon Sep 17 00:00:00 2001 From: Gustavo de Souza dos Reis Date: Thu, 17 Aug 2023 14:13:05 -0300 Subject: [PATCH 04/43] Implement EEPROM 24xx02 interface module --- modules/CMakeLists.txt | 6 +++ modules/eeprom_24xx02.c | 95 +++++++++++++++++++++++++++++++++++++++++ modules/eeprom_24xx02.h | 65 ++++++++++++++++++++++++++++ 3 files changed, 166 insertions(+) create mode 100644 modules/eeprom_24xx02.c create mode 100644 modules/eeprom_24xx02.h diff --git a/modules/CMakeLists.txt b/modules/CMakeLists.txt index a79c739a1..f27bc838a 100644 --- a/modules/CMakeLists.txt +++ b/modules/CMakeLists.txt @@ -9,6 +9,7 @@ set(PROJ_SRCS ${PROJ_SRCS} ${MODULE_PATH}/led.c) set(PROJ_SRCS ${PROJ_SRCS} ${MODULE_PATH}/ipmb.c ${MODULE_PATH}/ipmi.c) set(PROJ_SRCS ${PROJ_SRCS} ${MODULE_PATH}/printf-stdarg.c) set(PROJ_SRCS ${PROJ_SRCS} ${MODULE_PATH}/error.c) +set(PROJ_SRCS ${PROJ_SRCS} ${MODULE_PATH}/eeprom_24xx02.c) message(STATUS "Selected modules to compile: ${TARGET_MODULES}") @@ -24,6 +25,11 @@ if (";${TARGET_MODULES};" MATCHES ";FRU;") set(MODULES_FLAGS "${MODULES_FLAGS} -DMODULE_FRU") endif() +if (";${TARGET_MODULES};" MATCHES ";EEPROM_24XX02;") + set(PROJ_SRCS ${PROJ_SRCS} ${MODULE_PATH}/eeprom_24xx02.c ) + set(MODULES_FLAGS "${MODULES_FLAGS} -DMODULE_EEPROM_24XX02") +endif() + if (";${TARGET_MODULES};" MATCHES ";SDR;") set(PROJ_SRCS ${PROJ_SRCS} ${MODULE_PATH}/sdr.c ) set(MODULES_FLAGS "${MODULES_FLAGS} -DMODULE_SDR") diff --git a/modules/eeprom_24xx02.c b/modules/eeprom_24xx02.c new file mode 100644 index 000000000..ad1d7c7ff --- /dev/null +++ b/modules/eeprom_24xx02.c @@ -0,0 +1,95 @@ +/* + * openMMC -- Open Source modular IPM Controller firmware + * + * Copyright (C) 2023 Gustavo Reis + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + * + * @license GPL-3.0+ + */ + +/** + * @file eeprom_24xx02.c + * @author Gustavo Reis + * + * @brief 24xx02 EEPROM module interface implementation + * + * @ingroup 24xx02 + */ + +/* FreeRTOS includes */ +#include "FreeRTOS.h" +#include "string.h" + +/* Project Includes */ +#include "eeprom_24xx02.h" +#include "port.h" +#include "i2c.h" + +size_t eeprom_24xx02_read( uint8_t id, uint16_t address, uint8_t *rx_data, size_t buf_len, TickType_t timeout ) +{ + uint8_t i2c_addr; + uint8_t i2c_interface; + uint8_t rx_len = 0; + + if ( rx_data == NULL ) { + return 0; + } + + if (i2c_take_by_chipid( id, &i2c_addr, &i2c_interface, timeout ) ) { + rx_len = xI2CMasterWriteRead( i2c_interface, i2c_addr, address, rx_data, buf_len ); + i2c_give( i2c_interface ); + } + + return rx_len; +} + +size_t eeprom_24xx02_write( uint8_t id, uint16_t address, uint8_t *tx_data, size_t buf_len, TickType_t timeout ) +{ + uint8_t i2c_addr; + uint8_t i2c_interface; + uint8_t bytes_to_write; + uint8_t page_buf[9]; + uint16_t curr_addr; + + size_t tx_len = 0; + + if ( tx_data == NULL ) { + return 0; + } + + if (i2c_take_by_chipid( id, &i2c_addr, &i2c_interface, timeout)) { + curr_addr = address; + + while (tx_len < buf_len) { + bytes_to_write = 8 - (curr_addr % 8); + + if (bytes_to_write > ( buf_len - tx_len )) { + bytes_to_write = ( buf_len - tx_len ); + } + page_buf[0] = (curr_addr) & 0xFF; + + memcpy(&page_buf[1], tx_data+tx_len, bytes_to_write); + + /* Write the data */ + tx_len += xI2CMasterWrite( i2c_interface, i2c_addr, &page_buf[0] , bytes_to_write+1 ); + vTaskDelay(10); + tx_len -= 1; /* Remove the page byte from the count */ + curr_addr += bytes_to_write; + } + i2c_give( i2c_interface ); + } + + return tx_len; +} diff --git a/modules/eeprom_24xx02.h b/modules/eeprom_24xx02.h new file mode 100644 index 000000000..c576b8e82 --- /dev/null +++ b/modules/eeprom_24xx02.h @@ -0,0 +1,65 @@ +/* + * openMMC -- Open Source modular IPM Controller firmware + * + * Copyright (C) 2023 Gustavo Reis + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + * + * @license GPL-3.0+ + */ + +/** + * @defgroup 24xx02 24xx02 2kbit Serial EEPROM + * @ingroup PERIPH_IC + */ + +/** + * @file eeprom_24xx02.h + * @author Gustavo Reis + * + * @brief 24xx02 EEPROM module interface declarations + * + * @ingroup 24xx02 + */ + +#ifndef EEPROM_24XX02_H_ +#define EEPROM_24XX02_H_ + +/** + * @brief Read serial data from EEPROM_24XX02 EEPROM + * + * @param id EEPROM chip id + * @param address Starting read address + * @param rx_data Buffer to store the data + * @param buf_len Buffer max length + * @param timeout Read timeout + * + * @return Number of bytes actually received + */ +size_t eeprom_24xx02_read( uint8_t id, uint16_t address, uint8_t *rx_data, size_t buf_len, uint32_t timeout ); + +/** + * @brief Write serial data to EEPROM + * + * @param id EEPROM chip id + * @param address Write start address + * @param tx_data Buffer holding the data to write + * @param buf_len Buffer max len + * @param timeout Write timout + * + * @return Number of bytes actually written + */ +size_t eeprom_24xx02_write( uint8_t id, uint16_t address, uint8_t *tx_data, size_t buf_len, uint32_t timeout ); + +#endif From 467a8260b898c1fe8262db2893ea25b6a0564746 Mon Sep 17 00:00:00 2001 From: Gustavo de Souza dos Reis Date: Mon, 7 Aug 2023 14:28:09 -0300 Subject: [PATCH 05/43] Add ipmi command to configure clock switch and save it in eeprom --- README.md | 24 +++++ modules/CMakeLists.txt | 5 ++ modules/adn4604.c | 62 ------------- modules/adn4604.h | 8 -- modules/clock_config.c | 26 ++++++ modules/clock_config.h | 7 ++ modules/ipmi.h | 2 + port/board/afc-bpm/v3_1/CMakeLists.txt | 2 + port/board/afc-bpm/v3_1/adn4604_usercfg.h | 63 ------------- port/board/afc-bpm/v3_1/payload.c | 105 +++++++++++++++++++--- port/board/afc-bpm/v3_1/payload.h | 7 ++ port/board/afc-timing/CMakeLists.txt | 2 + port/board/afc-timing/adn4604_usercfg.h | 63 ------------- port/board/afc-timing/payload.c | 91 +++++++++++++++++-- port/board/afc-timing/payload.h | 8 ++ port/board/afc-v4/CMakeLists.txt | 2 + port/board/afc-v4/board_config.c | 6 -- port/board/afc-v4/payload.c | 38 +++++--- port/board/afc-v4/payload.h | 1 + 19 files changed, 294 insertions(+), 228 deletions(-) create mode 100644 modules/clock_config.c create mode 100644 modules/clock_config.h delete mode 100644 port/board/afc-bpm/v3_1/adn4604_usercfg.h delete mode 100644 port/board/afc-timing/adn4604_usercfg.h diff --git a/README.md b/README.md index 6c751d14a..205a16eae 100644 --- a/README.md +++ b/README.md @@ -130,3 +130,27 @@ Now you can use the typical GDB commands to inspect the program flow and variabl (gdb) monitor reset halt # Resets the microcontroller and immediately halts (gdb) monitor reset run # Resets the microcontroller and starts executing (gdb) load # Reload the firmware into flash + + +## IPMI Custom Commands +The IPMI allow us to create custom commands according to the project needs. [ipmitool](https://codeberg.org/IPMITool/ipmitool) can be used to send the commands + +### Clock switch configuration +It's possible to configure the clock switch. For the AFC v3.1 (ADN4604ASVZ) you can use the following scheme: +- **Port I/O (bit 7)**: Use it to configure the port as an input ('0') or output ('1'). Unused ports should be left configured as inputs; +- **Output Port Signal Source (bits 0 to 3)**: Select the input port for the respective output port. + +For the AFC v4 (IDT 8V54816) you can use the following scheme: +- **Port I/O (bit 7)**: Use it to configure the port as an input ('0') or output ('1'). Unused ports should be left configured as inputs; +- **Termination On/Off (bit 6)**: Use to set the internal termination. '0' is off (high-impedance), '1' is on (100 $\Omega$) +- **Polarity (bit 5)**: Set the channel polarity. '0' for inverted, '1' for non-inverted +- **Output Port Signal Source (bits 0 to 3)**: Select the input port for the respective output port. + + +The command to write the configuration is the above: + + ipmitool -I lan -H mch_host_name -A none -T 0x82 -m 0x20 -t (112 + num_slot*2) raw 0x32 0x03 + +To read the actual configuration, use: + + ipmitool -I lan -H mch_host_name -A none -T 0x82 -m 0x20 -t (112 + num_slot*2) raw 0x32 0x04 diff --git a/modules/CMakeLists.txt b/modules/CMakeLists.txt index f27bc838a..dd36ea369 100644 --- a/modules/CMakeLists.txt +++ b/modules/CMakeLists.txt @@ -25,6 +25,11 @@ if (";${TARGET_MODULES};" MATCHES ";FRU;") set(MODULES_FLAGS "${MODULES_FLAGS} -DMODULE_FRU") endif() +if (";${TARGET_MODULES};" MATCHES ";CLOCK_CONFIG;") + set(PROJ_SRCS ${PROJ_SRCS} ${MODULE_PATH}/clock_config.c ) + set(MODULES_FLAGS "${MODULES_FLAGS} -DMODULE_CLOCK_CONFIG") +endif() + if (";${TARGET_MODULES};" MATCHES ";EEPROM_24XX02;") set(PROJ_SRCS ${PROJ_SRCS} ${MODULE_PATH}/eeprom_24xx02.c ) set(MODULES_FLAGS "${MODULES_FLAGS} -DMODULE_EEPROM_24XX02") diff --git a/modules/adn4604.c b/modules/adn4604.c index 564f10521..21d1baca3 100644 --- a/modules/adn4604.c +++ b/modules/adn4604.c @@ -34,73 +34,11 @@ /* Project Includes */ #include "port.h" #include "adn4604.h" -#include "adn4604_usercfg.h" #include "i2c.h" #include "i2c_mapping.h" adn_connect_map_t con; -void adn4604_init( void ) -{ - uint16_t out_enable_flag = { - ADN4604_EN_OUT_0 << 0 | - ADN4604_EN_OUT_1 << 1 | - ADN4604_EN_OUT_2 << 2 | - ADN4604_EN_OUT_3 << 3 | - ADN4604_EN_OUT_4 << 4 | - ADN4604_EN_OUT_5 << 5 | - ADN4604_EN_OUT_6 << 6 | - ADN4604_EN_OUT_7 << 7 | - ADN4604_EN_OUT_8 << 8 | - ADN4604_EN_OUT_9 << 9 | - ADN4604_EN_OUT_10 << 10 | - ADN4604_EN_OUT_11 << 11 | - ADN4604_EN_OUT_12 << 12 | - ADN4604_EN_OUT_13 << 13 | - ADN4604_EN_OUT_14 << 14 | - ADN4604_EN_OUT_15 << 15 - }; - - /* Disable UPDATE' pin by pulling it GPIO_LEVEL_HIGH */ - gpio_set_pin_state( PIN_PORT(GPIO_ADN_UPDATE), PIN_NUMBER(GPIO_ADN_UPDATE), GPIO_LEVEL_HIGH ); - - /* There's a delay circuit in the Reset pin of the clock switch, we must wait until it clears out */ - while( gpio_read_pin( PIN_PORT(GPIO_ADN_RESETN), PIN_NUMBER(GPIO_ADN_RESETN) ) == 0 ) { - vTaskDelay( 50 ); - } - - /* Configure the interconnects */ - con.out0 = ADN4604_CFG_OUT_0; - con.out1 = ADN4604_CFG_OUT_1; - con.out2 = ADN4604_CFG_OUT_2; - con.out3 = ADN4604_CFG_OUT_3; - con.out4 = ADN4604_CFG_OUT_4; - con.out5 = ADN4604_CFG_OUT_5; - con.out6 = ADN4604_CFG_OUT_6; - con.out7 = ADN4604_CFG_OUT_7; - con.out8 = ADN4604_CFG_OUT_8; - con.out9 = ADN4604_CFG_OUT_9; - con.out10 = ADN4604_CFG_OUT_10; - con.out11 = ADN4604_CFG_OUT_11; - con.out12 = ADN4604_CFG_OUT_12; - con.out13 = ADN4604_CFG_OUT_13; - con.out14 = ADN4604_CFG_OUT_14; - con.out15 = ADN4604_CFG_OUT_15; - - adn4604_xpt_config( ADN_XPT_MAP0_CON_REG, con ); - - /* Enable desired outputs */ - for ( uint8_t i = 0; i < 16; i++ ) { - if ( ( out_enable_flag >> i ) & 0x1 ) { - adn4604_tx_control( i, TX_ENABLED ); - } - } - - adn4604_active_map( ADN_XPT_MAP0 ); - - adn4604_update(); -} - void adn4604_tx_control( uint8_t output, uint8_t tx_mode ) { uint8_t i2c_addr, i2c_interf; diff --git a/modules/adn4604.h b/modules/adn4604.h index 04ecb9e81..f6b01ea99 100644 --- a/modules/adn4604.h +++ b/modules/adn4604.h @@ -112,14 +112,6 @@ enum adn4604_tx_ctl { TX_ENABLED }; -/** - * @brief Initializes the ADN4604 Clock switch hardware - * - * This IC starts with a pre-defined configuration provided by the board port in the adn4604_usercfg.h file. - * The current port status may be changed with OEM IPMI commands. - */ -void adn4604_init( void ); - /** * @brief Sets the output status * diff --git a/modules/clock_config.c b/modules/clock_config.c new file mode 100644 index 000000000..f6af30603 --- /dev/null +++ b/modules/clock_config.c @@ -0,0 +1,26 @@ +#include "clock_config.h" + +uint8_t clock_config[16]; + +/* + * Function to configure the clock switch via ipmi. + * The configuration is sent as an array in the data field. + * +*/ +IPMI_HANDLER(ipmi_custom_cmd_write_clock_config, NETFN_CUSTOM, IPMI_CUSTOM_CMD_WRITE_CLOCK_CONFIG, ipmi_msg *req, ipmi_msg *rsp) +{ + memcpy(clock_config, req->data, req->data_len); + payload_send_message(FRU_AMC, PAYLOAD_MESSAGE_CLOCK_CONFIG); + rsp->completion_code = IPMI_CC_OK; +} + + +/* + * Function to read the clock switch configuration via ipmi. + */ +IPMI_HANDLER(ipmi_custom_cmd_read_clock_config, NETFN_CUSTOM, IPMI_CUSTOM_CMD_READ_CLOCK_CONFIG, ipmi_msg *req, ipmi_msg *rsp) +{ + rsp->data_len = 16; + memcpy(rsp->data, clock_config, rsp->data_len); + rsp->completion_code = IPMI_CC_OK; +} diff --git a/modules/clock_config.h b/modules/clock_config.h new file mode 100644 index 000000000..c2769419d --- /dev/null +++ b/modules/clock_config.h @@ -0,0 +1,7 @@ +#include +#include +#include "ipmi.h" +#include "fru.h" +#include "payload.h" + +extern uint8_t clock_config[16]; diff --git a/modules/ipmi.h b/modules/ipmi.h index 74057f311..4a363d917 100644 --- a/modules/ipmi.h +++ b/modules/ipmi.h @@ -468,6 +468,8 @@ */ #define IPMI_CUSTOM_CMD_MMC_GET_FREE_HEAP 0x01 #define IPMI_CUSTOM_CMD_GET_GIT_HASH 0x02 +#define IPMI_CUSTOM_CMD_WRITE_CLOCK_CONFIG 0x03 +#define IPMI_CUSTOM_CMD_READ_CLOCK_CONFIG 0x04 /** * @} */ diff --git a/port/board/afc-bpm/v3_1/CMakeLists.txt b/port/board/afc-bpm/v3_1/CMakeLists.txt index 456ea228b..05759cd2e 100644 --- a/port/board/afc-bpm/v3_1/CMakeLists.txt +++ b/port/board/afc-bpm/v3_1/CMakeLists.txt @@ -10,6 +10,7 @@ endif() #List all modules used by this board set(TARGET_MODULES "FRU" + "CLOCK_CONFIG" "PAYLOAD" "SDR" "SCANSTA1101" @@ -18,6 +19,7 @@ set(TARGET_MODULES "DAC_AD84XX" "EEPROM_AT24MAC" "EEPROM_24XX64" + "EEPROM_24XX02" "HOTSWAP_SENSOR" "LM75" "MAX6642" diff --git a/port/board/afc-bpm/v3_1/adn4604_usercfg.h b/port/board/afc-bpm/v3_1/adn4604_usercfg.h deleted file mode 100644 index f0279d532..000000000 --- a/port/board/afc-bpm/v3_1/adn4604_usercfg.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - * openMMC -- Open Source modular IPM Controller firmware - * - * Copyright (C) 2015 Henrique Silva - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - * - * @license GPL-3.0+ - */ - -#ifdef ADN4604_USERCFG_H_ -#error "User configuration for ADN4604 Clock switch already defined by other board port, check the build chain!" -#else -#define ADN4604_USERCFG_H_ - -/* User configuration defines for ADN4604 Clock switch output config */ -#define ADN4604_CFG_OUT_0 0 /* TCLKD_OUT */ -#define ADN4604_CFG_OUT_1 0 /* TCLKC_OUT */ -#define ADN4604_CFG_OUT_2 0 /* TCLKA_OUT */ -#define ADN4604_CFG_OUT_3 0 /* TCLKB_OUT */ -#define ADN4604_CFG_OUT_4 13 /* FPGA_CCLK */ -#define ADN4604_CFG_OUT_5 8 /* FP2_CLK2 */ -#define ADN4604_CFG_OUT_6 5 /* LINK01_CLK */ -#define ADN4604_CFG_OUT_7 15 /* FP2_CLK1 */ -#define ADN4604_CFG_OUT_8 8 /* PCIE_CLK1 */ -#define ADN4604_CFG_OUT_9 5 /* LINK23_CLK */ -#define ADN4604_CFG_OUT_10 5 /* FIN1_CLK3 */ -#define ADN4604_CFG_OUT_11 5 /* FIN1_CLK2 */ -#define ADN4604_CFG_OUT_12 14 /* RTM_SYNC_CLK */ -#define ADN4604_CFG_OUT_13 5 /* OP15C (Aux U-Fl connector) */ -#define ADN4604_CFG_OUT_14 5 /* FIN2_CLK2 */ -#define ADN4604_CFG_OUT_15 5 /* FIN2_CLK3 */ - -/* Output enable flags */ -#define ADN4604_EN_OUT_0 0 /* TCLKD_OUT */ -#define ADN4604_EN_OUT_1 0 /* TCLKC_OUT */ -#define ADN4604_EN_OUT_2 0 /* TCLKA_OUT */ -#define ADN4604_EN_OUT_3 0 /* TCLKB_OUT */ -#define ADN4604_EN_OUT_4 1 /* FPGA_CCLK */ -#define ADN4604_EN_OUT_5 0 /* FP2_CLK2 */ -#define ADN4604_EN_OUT_6 1 /* LINK01_CLK */ -#define ADN4604_EN_OUT_7 1 /* FP2_CLK1 */ -#define ADN4604_EN_OUT_8 1 /* PCIE_CLK1 */ -#define ADN4604_EN_OUT_9 0 /* LINK23_CLK */ -#define ADN4604_EN_OUT_10 1 /* FIN1_CLK3 */ -#define ADN4604_EN_OUT_11 1 /* FIN1_CLK2 */ -#define ADN4604_EN_OUT_12 0 /* RTM_SYNC_CLK */ -#define ADN4604_EN_OUT_13 1 /* OP15C (Aux U-Fl connector) */ -#define ADN4604_EN_OUT_14 1 /* FIN2_CLK2 */ -#define ADN4604_EN_OUT_15 1 /* FIN2_CLK3 */ - -#endif diff --git a/port/board/afc-bpm/v3_1/payload.c b/port/board/afc-bpm/v3_1/payload.c index 68ecb10d0..75af95f38 100644 --- a/port/board/afc-bpm/v3_1/payload.c +++ b/port/board/afc-bpm/v3_1/payload.c @@ -38,6 +38,9 @@ #include "fru.h" #include "led.h" #include "board_led.h" +#include "clock_config.h" +#include "i2c_mapping.h" +#include "eeprom_24xx02.h" /* payload states * 0 - No power @@ -190,7 +193,7 @@ void payload_init( void ) while ( gpio_read_pin( PIN_PORT(GPIO_MMC_ENABLE), PIN_NUMBER(GPIO_MMC_ENABLE) ) == 1 ) {}; } - xTaskCreate( vTaskPayload, "Payload", 120, NULL, tskPAYLOAD_PRIORITY, &vTaskPayload_Handle ); + xTaskCreate( vTaskPayload, "Payload", 256, NULL, tskPAYLOAD_PRIORITY, &vTaskPayload_Handle ); amc_payload_evt = xEventGroupCreate(); #ifdef MODULE_RTM @@ -239,18 +242,31 @@ void vTaskPayload( void *pvParameters ) current_evt = xEventGroupGetBits( amc_payload_evt ); + /* + * When receive a PAYLOAD_MESSAGE_CLOCK_CONFIG command, write the new configuration + * in EEPROM memory, reset the clock configuration and perform the new configuration. + */ + if( current_evt & PAYLOAD_MESSAGE_CLOCK_CONFIG ){ + eeprom_24xx02_write(CHIP_ID_RTC_EEPROM, 0x0, clock_config, 16, 10); + if (PAYLOAD_FPGA_ON) { + adn4604_reset(); + clock_configuration(); + } + xEventGroupClearBits(amc_payload_evt, PAYLOAD_MESSAGE_CLOCK_CONFIG); + } + if ( current_evt & PAYLOAD_MESSAGE_QUIESCE ) { - + /* - * If you issue a shutdown fru command in the MCH shell, the payload power - * task will receive a PAYLOAD_MESSAGE_QUIESCE message and set the - * QUIESCED_req flag to '1' and the MCH will shutdown the 12VP0 power, - * making the payload power task go to PAYLOAD_NO_POWER state. + * If you issue a shutdown fru command in the MCH shell, the payload power + * task will receive a PAYLOAD_MESSAGE_QUIESCE message and set the + * QUIESCED_req flag to '1' and the MCH will shutdown the 12VP0 power, + * making the payload power task go to PAYLOAD_NO_POWER state. * So, if we are in the PAYLOAD_QUIESCED state and receive a - * PAYLOAD_MESSAGE_QUIESCE message, the QUIESCED_req flag + * PAYLOAD_MESSAGE_QUIESCE message, the QUIESCED_req flag * should be '0' */ - + if (state == PAYLOAD_QUIESCED) { QUIESCED_req = 0; } else { @@ -298,7 +314,7 @@ void vTaskPayload( void *pvParameters ) case PAYLOAD_STATE_FPGA_SETUP: #ifdef MODULE_ADN4604 /* Configure clock switch */ - adn4604_init(); + clock_configuration(); #endif new_state = PAYLOAD_FPGA_ON; break; @@ -328,7 +344,7 @@ void vTaskPayload( void *pvParameters ) new_state = PAYLOAD_NO_POWER; } break; - + case PAYLOAD_RESET: /*Reset DCDC converters*/ setDC_DC_ConvertersON( false ); @@ -461,4 +477,73 @@ uint8_t payload_hpm_activate_firmware( void ) return IPMI_CC_OK; } + +void clock_configuration() +{ + adn_connect_map_t con; + + /* Read the clock configuration from the eeprom */ + eeprom_24xx02_read(CHIP_ID_RTC_EEPROM, 0x0, clock_config, 16, 10); + + /* Translate the configuration to enable or disable the outputs */ + uint16_t out_enable_flag = { + ((clock_config[0] & 0x80) >> 7) << 0 | + ((clock_config[1] & 0x80) >> 7) << 1 | + ((clock_config[2] & 0x80) >> 7) << 2 | + ((clock_config[3] & 0x80) >> 7) << 3 | + ((clock_config[4] & 0x80) >> 7) << 4 | + ((clock_config[5] & 0x80) >> 7) << 5 | + ((clock_config[6] & 0x80) >> 7) << 6 | + ((clock_config[7] & 0x80) >> 7) << 7 | + ((clock_config[8] & 0x80) >> 7) << 8 | + ((clock_config[9] & 0x80) >> 7) << 9 | + ((clock_config[10] & 0x80) >> 7) << 10 | + ((clock_config[11] & 0x80) >> 7) << 11 | + ((clock_config[12] & 0x80) >> 7) << 12 | + ((clock_config[13] & 0x80) >> 7) << 13 | + ((clock_config[14] & 0x80) >> 7) << 14 | + ((clock_config[15] & 0x80) >> 7) << 15 + }; + + /* Disable UPDATE' pin by pulling it GPIO_LEVEL_HIGH */ + gpio_set_pin_state( PIN_PORT(GPIO_ADN_UPDATE), PIN_NUMBER(GPIO_ADN_UPDATE), GPIO_LEVEL_HIGH ); + + /* There's a delay circuit in the Reset pin of the clock switch, we must wait until it clears out */ + while( gpio_read_pin( PIN_PORT(GPIO_ADN_RESETN), PIN_NUMBER(GPIO_ADN_RESETN) ) == 0 ) { + vTaskDelay( 50 ); + } + + /* Configure the interconnects*/ + con.out0 = clock_config[0] & 0x0F; + con.out1 = clock_config[1] & 0x0F; + con.out2 = clock_config[2] & 0x0F; + con.out3 = clock_config[3] & 0x0F; + con.out4 = clock_config[4] & 0x0F; + con.out5 = clock_config[5] & 0x0F; + con.out6 = clock_config[6] & 0x0F; + con.out7 = clock_config[7] & 0x0F; + con.out8 = clock_config[8] & 0x0F; + con.out9 = clock_config[9] & 0x0F; + con.out10 = clock_config[10] & 0x0F; + con.out11 = clock_config[11] & 0x0F; + con.out12 = clock_config[12] & 0x0F; + con.out13 = clock_config[13] & 0x0F; + con.out14 = clock_config[14] & 0x0F; + con.out15 = clock_config[15] & 0x0F; + + adn4604_xpt_config( ADN_XPT_MAP0_CON_REG, con ); + + /* Enable desired outputs */ + for ( uint8_t i = 0; i < 16; i++ ) { + if ( ( out_enable_flag >> i ) & 0x1 ) { + adn4604_tx_control( i, TX_ENABLED ); + } else { + adn4604_tx_control( i, TX_DISABLED ); + } + } + + adn4604_active_map( ADN_XPT_MAP0 ); + + adn4604_update(); +} #endif diff --git a/port/board/afc-bpm/v3_1/payload.h b/port/board/afc-bpm/v3_1/payload.h index 3aec34f29..37c466376 100644 --- a/port/board/afc-bpm/v3_1/payload.h +++ b/port/board/afc-bpm/v3_1/payload.h @@ -61,6 +61,7 @@ extern enum { #define PAYLOAD_MESSAGE_WARM_RST (1 << 1) #define PAYLOAD_MESSAGE_REBOOT (1 << 2) #define PAYLOAD_MESSAGE_QUIESCE (1 << 3) +#define PAYLOAD_MESSAGE_CLOCK_CONFIG (1 << 4) /** * @} */ @@ -108,6 +109,12 @@ uint8_t payload_hpm_get_upgrade_status( void ); uint8_t payload_hpm_activate_firmware( void ); #endif +/** + * @brief Configure the clock switch interconects according to the configuration + * saved in EEPROM + */ +void clock_configuration(); + #endif /* IPMI_PAYLOAD_H_ */ /** diff --git a/port/board/afc-timing/CMakeLists.txt b/port/board/afc-timing/CMakeLists.txt index 788115b62..c22a95f1b 100644 --- a/port/board/afc-timing/CMakeLists.txt +++ b/port/board/afc-timing/CMakeLists.txt @@ -10,6 +10,7 @@ endif() #List all modules used by this board set(TARGET_MODULES "FRU" + "CLOCK_CONFIG" "PAYLOAD" "SDR" "SCANSTA1101" @@ -17,6 +18,7 @@ set(TARGET_MODULES "DAC_AD84XX" "HOTSWAP_SENSOR" "EEPROM_AT24MAC" + "EEPROM_24XX02" "LM75" "MAX6642" "INA220_VOLTAGE" diff --git a/port/board/afc-timing/adn4604_usercfg.h b/port/board/afc-timing/adn4604_usercfg.h deleted file mode 100644 index e30678288..000000000 --- a/port/board/afc-timing/adn4604_usercfg.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - * openMMC -- Open Source modular IPM Controller firmware - * - * Copyright (C) 2015 Henrique Silva - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - * - * @license GPL-3.0+ - */ - -#ifdef ADN4604_USERCFG_H_ -#error "User configuration for ADN4604 Clock switch already defined by other board port, check the build chain!" -#else -#define ADN4604_USERCFG_H_ - -/* User configuration defines for ADN4604 Clock switch output config */ -#define ADN4604_CFG_OUT_0 0 /* TCLKD_OUT */ -#define ADN4604_CFG_OUT_1 0 /* TCLKC_OUT */ -#define ADN4604_CFG_OUT_2 0 /* TCLKA_OUT */ -#define ADN4604_CFG_OUT_3 15 /* TCLKB_OUT */ -#define ADN4604_CFG_OUT_4 15 /* FPGA_CCLK */ -#define ADN4604_CFG_OUT_5 8 /* FP2_CLK2 */ -#define ADN4604_CFG_OUT_6 13 /* LINK01_CLK */ -#define ADN4604_CFG_OUT_7 8 /* FP2_CLK1 */ -#define ADN4604_CFG_OUT_8 8 /* PCIE_CLK1 */ -#define ADN4604_CFG_OUT_9 13 /* LINK23_CLK */ -#define ADN4604_CFG_OUT_10 14 /* FIN1_CLK3 */ -#define ADN4604_CFG_OUT_11 14 /* FIN1_CLK2 */ -#define ADN4604_CFG_OUT_12 14 /* RTM_SYNC_CLK */ -#define ADN4604_CFG_OUT_13 15 /* OP15C (Aux U-Fl connector) */ -#define ADN4604_CFG_OUT_14 14 /* FIN2_CLK2 */ -#define ADN4604_CFG_OUT_15 3 /* FIN2_CLK3 */ - -/* Output enable flags */ -#define ADN4604_EN_OUT_0 0 /* TCLKD_OUT */ -#define ADN4604_EN_OUT_1 0 /* TCLKC_OUT */ -#define ADN4604_EN_OUT_2 0 /* TCLKA_OUT */ -#define ADN4604_EN_OUT_3 1 /* TCLKB_OUT */ -#define ADN4604_EN_OUT_4 1 /* FPGA_CCLK */ -#define ADN4604_EN_OUT_5 0 /* FP2_CLK2 */ -#define ADN4604_EN_OUT_6 1 /* LINK01_CLK */ -#define ADN4604_EN_OUT_7 0 /* FP2_CLK1 */ -#define ADN4604_EN_OUT_8 1 /* PCIE_CLK1 */ -#define ADN4604_EN_OUT_9 0 /* LINK23_CLK */ -#define ADN4604_EN_OUT_10 0 /* FIN1_CLK3 */ -#define ADN4604_EN_OUT_11 0 /* FIN1_CLK2 */ -#define ADN4604_EN_OUT_12 0 /* RTM_SYNC_CLK */ -#define ADN4604_EN_OUT_13 1 /* OP15C (Aux U-Fl connector) */ -#define ADN4604_EN_OUT_14 0 /* FIN2_CLK2 */ -#define ADN4604_EN_OUT_15 0 /* FIN2_CLK3 */ - -#endif diff --git a/port/board/afc-timing/payload.c b/port/board/afc-timing/payload.c index 07994fb45..ef22c9c6e 100644 --- a/port/board/afc-timing/payload.c +++ b/port/board/afc-timing/payload.c @@ -38,6 +38,9 @@ #include "fru.h" #include "led.h" #include "board_led.h" +#include "clock_config.h" +#include "i2c_mapping.h" +#include "eeprom_24xx02.h" /* payload states * 0 - No power @@ -178,8 +181,6 @@ TaskHandle_t vTaskPayload_Handle; void payload_init( void ) { - - /* Set standalone mode if the module is disconnected from a create*/ bool standalone_mode = false; @@ -192,8 +193,7 @@ void payload_init( void ) while ( gpio_read_pin( PIN_PORT(GPIO_MMC_ENABLE), PIN_NUMBER(GPIO_MMC_ENABLE) ) == 1 ) {}; } - - xTaskCreate( vTaskPayload, "Payload", 120, NULL, tskPAYLOAD_PRIORITY, &vTaskPayload_Handle ); + xTaskCreate( vTaskPayload, "Payload", 256, NULL, tskPAYLOAD_PRIORITY, &vTaskPayload_Handle ); amc_payload_evt = xEventGroupCreate(); #ifdef MODULE_RTM @@ -242,6 +242,18 @@ void vTaskPayload( void *pvParameters ) current_evt = xEventGroupGetBits( amc_payload_evt ); + /* + * When receive a PAYLOAD_MESSAGE_CLOCK_CONFIG command, write the new configuration + * in EEPROM memory, reset the clock configuration and perform the new configuration. + */ + if( current_evt & PAYLOAD_MESSAGE_CLOCK_CONFIG ){ + eeprom_24xx02_write(CHIP_ID_RTC_EEPROM, 0x0, clock_config, 16, 10); + if (PAYLOAD_FPGA_ON){ + adn4604_reset(); + clock_configuration(); + } + xEventGroupClearBits(amc_payload_evt, PAYLOAD_MESSAGE_CLOCK_CONFIG); + } if ( current_evt & PAYLOAD_MESSAGE_QUIESCE ) { /* @@ -301,7 +313,7 @@ void vTaskPayload( void *pvParameters ) case PAYLOAD_STATE_FPGA_SETUP: #ifdef MODULE_ADN4604 /* Configure clock switch */ - adn4604_init(); + clock_configuration(); #endif new_state = PAYLOAD_FPGA_ON; break; @@ -464,4 +476,73 @@ uint8_t payload_hpm_activate_firmware( void ) return IPMI_CC_OK; } + +void clock_configuration() +{ + adn_connect_map_t con; + + /* Read the clock configuration from the eeprom */ + eeprom_24xx02_read(CHIP_ID_RTC_EEPROM, 0x0, clock_config, 16, 10); + + /* Translate the configuration to enable or disable the outputs */ + uint16_t out_enable_flag = { + ((clock_config[0] & 0x80) >> 7) << 0 | + ((clock_config[1] & 0x80) >> 7) << 1 | + ((clock_config[2] & 0x80) >> 7) << 2 | + ((clock_config[3] & 0x80) >> 7) << 3 | + ((clock_config[4] & 0x80) >> 7) << 4 | + ((clock_config[5] & 0x80) >> 7) << 5 | + ((clock_config[6] & 0x80) >> 7) << 6 | + ((clock_config[7] & 0x80) >> 7) << 7 | + ((clock_config[8] & 0x80) >> 7) << 8 | + ((clock_config[9] & 0x80) >> 7) << 9 | + ((clock_config[10] & 0x80) >> 7) << 10 | + ((clock_config[11] & 0x80) >> 7) << 11 | + ((clock_config[12] & 0x80) >> 7) << 12 | + ((clock_config[13] & 0x80) >> 7) << 13 | + ((clock_config[14] & 0x80) >> 7) << 14 | + ((clock_config[15] & 0x80) >> 7) << 15 + }; + + /* Disable UPDATE' pin by pulling it GPIO_LEVEL_HIGH */ + gpio_set_pin_state( PIN_PORT(GPIO_ADN_UPDATE), PIN_NUMBER(GPIO_ADN_UPDATE), GPIO_LEVEL_HIGH ); + + /* There's a delay circuit in the Reset pin of the clock switch, we must wait until it clears out */ + while( gpio_read_pin( PIN_PORT(GPIO_ADN_RESETN), PIN_NUMBER(GPIO_ADN_RESETN) ) == 0 ) { + vTaskDelay( 50 ); + } + + /* Configure the interconnects*/ + con.out0 = clock_config[0] & 0x0F; + con.out1 = clock_config[1] & 0x0F; + con.out2 = clock_config[2] & 0x0F; + con.out3 = clock_config[3] & 0x0F; + con.out4 = clock_config[4] & 0x0F; + con.out5 = clock_config[5] & 0x0F; + con.out6 = clock_config[6] & 0x0F; + con.out7 = clock_config[7] & 0x0F; + con.out8 = clock_config[8] & 0x0F; + con.out9 = clock_config[9] & 0x0F; + con.out10 = clock_config[10] & 0x0F; + con.out11 = clock_config[11] & 0x0F; + con.out12 = clock_config[12] & 0x0F; + con.out13 = clock_config[13] & 0x0F; + con.out14 = clock_config[14] & 0x0F; + con.out15 = clock_config[15] & 0x0F; + + adn4604_xpt_config( ADN_XPT_MAP0_CON_REG, con ); + + /* Enable desired outputs */ + for ( uint8_t i = 0; i < 16; i++ ) { + if ( ( out_enable_flag >> i ) & 0x1 ) { + adn4604_tx_control( i, TX_ENABLED ); + } else { + adn4604_tx_control( i, TX_DISABLED ); + } + } + + adn4604_active_map( ADN_XPT_MAP0 ); + + adn4604_update(); +} #endif diff --git a/port/board/afc-timing/payload.h b/port/board/afc-timing/payload.h index 03ff35e3b..3746e8e2e 100644 --- a/port/board/afc-timing/payload.h +++ b/port/board/afc-timing/payload.h @@ -62,6 +62,7 @@ extern enum { #define PAYLOAD_MESSAGE_REBOOT (1 << 2) #define PAYLOAD_MESSAGE_QUIESCE (1 << 3) #define PAYLOAD_MESSAGE_RTM_ENABLE (1 << 4) +#define PAYLOAD_MESSAGE_CLOCK_CONFIG (1 << 5) /** * @} */ @@ -109,6 +110,13 @@ uint8_t payload_hpm_get_upgrade_status( void ); uint8_t payload_hpm_activate_firmware( void ); #endif +/** + * @brief Configure the clock switch interconects according to the configuration + * saved in EEPROM + */ +void clock_configuration(); + + #endif /* IPMI_PAYLOAD_H_ */ /** diff --git a/port/board/afc-v4/CMakeLists.txt b/port/board/afc-v4/CMakeLists.txt index 1ae65a93f..a858f51ff 100644 --- a/port/board/afc-v4/CMakeLists.txt +++ b/port/board/afc-v4/CMakeLists.txt @@ -10,6 +10,8 @@ endif() #List all modules used by this board set(TARGET_MODULES "FRU" + "CLOCK_CONFIG" + "EEPROM_24XX02" "PAYLOAD" "SDR" "DAC_AD84XX" diff --git a/port/board/afc-v4/board_config.c b/port/board/afc-v4/board_config.c index 19e996c38..00eba0b0d 100644 --- a/port/board/afc-v4/board_config.c +++ b/port/board/afc-v4/board_config.c @@ -22,11 +22,6 @@ /* Project Includes */ #include "port.h" - -uint8_t clock_switch_default_config() { - -} - void board_init() { /* I2C MUX Init */ gpio_set_pin_state(PIN_PORT(GPIO_I2C_MUX_ADDR1), PIN_NUMBER(GPIO_I2C_MUX_ADDR1), GPIO_LEVEL_LOW); @@ -35,5 +30,4 @@ void board_init() { } void board_config() { - clock_switch_default_config(); } diff --git a/port/board/afc-v4/payload.c b/port/board/afc-v4/payload.c index af86bf4e4..4d1e8fffe 100644 --- a/port/board/afc-v4/payload.c +++ b/port/board/afc-v4/payload.c @@ -35,12 +35,16 @@ #include "task_priorities.h" #include "mcp23016.h" #include "ad84xx.h" +#include "idt_8v54816.h" #include "hotswap.h" #include "utils.h" #include "fru.h" #include "led.h" #include "board_led.h" - +#include "board_config.h" +#include "clock_config.h" +#include "eeprom_24xx02.h" +#include "i2c_mapping.h" /* payload states * 0 - No power @@ -233,7 +237,7 @@ void payload_init( void ) while ( gpio_read_pin( PIN_PORT(GPIO_MMC_ENABLE), PIN_NUMBER(GPIO_MMC_ENABLE) ) == 1 ) {}; } - xTaskCreate( vTaskPayload, "Payload", 120, NULL, tskPAYLOAD_PRIORITY, &vTaskPayload_Handle ); + xTaskCreate( vTaskPayload, "Payload", 256, NULL, tskPAYLOAD_PRIORITY, &vTaskPayload_Handle ); amc_payload_evt = xEventGroupCreate(); #ifdef MODULE_RTM @@ -328,19 +332,18 @@ void vTaskPayload( void *pvParameters ) new_state = state; current_evt = xEventGroupGetBits( amc_payload_evt ); - if ( current_evt & PAYLOAD_MESSAGE_QUIESCE ) { - + /* - * If you issue a shutdown fru command in the MCH shell, the payload power - * task will receive a PAYLOAD_MESSAGE_QUIESCE message and set the - * QUIESCED_req flag to '1' and the MCH will shutdown the 12VP0 power, - * making the payload power task go to PAYLOAD_NO_POWER state. + * If you issue a shutdown fru command in the MCH shell, the payload power + * task will receive a PAYLOAD_MESSAGE_QUIESCE message and set the + * QUIESCED_req flag to '1' and the MCH will shutdown the 12VP0 power, + * making the payload power task go to PAYLOAD_NO_POWER state. * So, if we are in the PAYLOAD_QUIESCED state and receive a - * PAYLOAD_MESSAGE_QUIESCE message, the QUIESCED_req flag + * PAYLOAD_MESSAGE_QUIESCE message, the QUIESCED_req flag * should be '0' */ - + if (state == PAYLOAD_QUIESCED) { QUIESCED_req = 0; } else { @@ -349,6 +352,17 @@ void vTaskPayload( void *pvParameters ) xEventGroupClearBits( amc_payload_evt, PAYLOAD_MESSAGE_QUIESCE ); } + /* + * When receive a PAYLOAD_MESSAGE_CLOCK_CONFIG message, configure the clock switch + * and write the new configuration in EEPROM + */ + if( current_evt & PAYLOAD_MESSAGE_CLOCK_CONFIG ){ + clock_switch_write_reg(clock_config); + if (PAYLOAD_FPGA_ON) { + eeprom_24xx02_write(CHIP_ID_RTC_EEPROM, 0x0, clock_config, 16, 10); + } + xEventGroupClearBits(amc_payload_evt, PAYLOAD_MESSAGE_CLOCK_CONFIG); + } if ( current_evt & PAYLOAD_MESSAGE_COLD_RST ) { state = PAYLOAD_RESET; xEventGroupClearBits( amc_payload_evt, PAYLOAD_MESSAGE_COLD_RST ); @@ -397,7 +411,9 @@ void vTaskPayload( void *pvParameters ) break; case PAYLOAD_STATE_FPGA_SETUP: - + /* Configure the clock switch according to the configuration saved in EEPROM*/ + eeprom_24xx02_read(CHIP_ID_RTC_EEPROM, 0x0, clock_config, 16, 10); + clock_switch_write_reg(clock_config); new_state = PAYLOAD_FPGA_ON; break; diff --git a/port/board/afc-v4/payload.h b/port/board/afc-v4/payload.h index 432fe18c4..291c927fc 100644 --- a/port/board/afc-v4/payload.h +++ b/port/board/afc-v4/payload.h @@ -64,6 +64,7 @@ extern enum { #define PAYLOAD_MESSAGE_QUIESCE (1 << 3) #define PAYLOAD_MESSAGE_DCDC_PGOOD (1 << 4) #define PAYLOAD_MESSAGE_DCDC_PGOODn (1 << 5) +#define PAYLOAD_MESSAGE_CLOCK_CONFIG (1 << 6) /** * @} */ From f5cb4229f899f0bb29ef0c6f864f49830d4a5aa1 Mon Sep 17 00:00:00 2001 From: Gustavo de Souza dos Reis Date: Fri, 29 Sep 2023 13:25:03 -0300 Subject: [PATCH 06/43] Remove deprecated code for clock switch configuration --- port/board/afc-bpm/v3_1/ipmi_oem.c | 51 ------------------------------ port/board/afc-bpm/v3_1/ipmi_oem.h | 5 --- port/board/afc-timing/ipmi_oem.c | 51 ------------------------------ port/board/afc-timing/ipmi_oem.h | 5 --- 4 files changed, 112 deletions(-) diff --git a/port/board/afc-bpm/v3_1/ipmi_oem.c b/port/board/afc-bpm/v3_1/ipmi_oem.c index 156342f05..7d8382b1f 100644 --- a/port/board/afc-bpm/v3_1/ipmi_oem.c +++ b/port/board/afc-bpm/v3_1/ipmi_oem.c @@ -163,54 +163,3 @@ IPMI_HANDLER(ipmi_oem_cmd_gpio_pin, NETFN_CUSTOM_OEM, IPMI_OEM_CMD_GPIO_PIN, ipm rsp->data_len = len; } - -/* ADN4604 IPMI Control commands */ -#ifdef MODULE_ADN4604 - -#include "adn4604.h" - -/* This command may take a while to execute and hold the IPMI transaction */ -IPMI_HANDLER(ipmi_oem_adn4604_cfg_output, NETFN_CUSTOM_OEM, IPMI_OEM_CMD_ADN4604_SET_OUTPUT_CFG, ipmi_msg *req, ipmi_msg* rsp) -{ - int len = rsp->data_len = 0; - - /* @todo Read port status before setting the new configuration */ - extern adn_connect_map_t con; - uint8_t map; - uint8_t output = req->data[1]; - uint8_t input = req->data[2]; - uint8_t enable = req->data[3]; - - if (output % 2) { - *((uint8_t *)&con+(output/2)) &= 0x0F; - *((uint8_t *)&con+(output/2)) |= (input << 4) & 0xF0; - } else { - *((uint8_t *)&con+(output/2)) &= 0xF0; - *((uint8_t *)&con+(output/2)) |= input & 0x0F; - } - - map = ( req->data[0] == 0 ) ? ADN_XPT_MAP0_CON_REG : ADN_XPT_MAP1_CON_REG; - - adn4604_xpt_config( map , con ); - - if ( enable ) { - adn4604_tx_control( output, TX_ENABLED ); - } else { - adn4604_tx_control( output, TX_DISABLED ); - } - - adn4604_update(); - - rsp->data_len = len; - rsp->completion_code = IPMI_CC_OK; -} - -IPMI_HANDLER(ipmi_oem_adn4604_reset, NETFN_CUSTOM_OEM, IPMI_OEM_CMD_ADN4604_RESET, ipmi_msg *req, ipmi_msg* rsp) -{ - adn4604_reset(); - - rsp->data_len = 0; - rsp->completion_code = IPMI_CC_OK; -} - -#endif diff --git a/port/board/afc-bpm/v3_1/ipmi_oem.h b/port/board/afc-bpm/v3_1/ipmi_oem.h index 304806e27..495985399 100644 --- a/port/board/afc-bpm/v3_1/ipmi_oem.h +++ b/port/board/afc-bpm/v3_1/ipmi_oem.h @@ -44,11 +44,6 @@ #define NETFN_CUSTOM_OEM 0x30 #define IPMI_OEM_CMD_I2C_TRANSFER 0x00 - -#define IPMI_OEM_CMD_ADN4604_SET_OUTPUT_CFG 0x01 -#define IPMI_OEM_CMD_ADN4604_GET_OUTPUT_CFG 0x02 -#define IPMI_OEM_CMD_ADN4604_RESET 0x03 - #define IPMI_OEM_CMD_GPIO_PIN 0x04 /** * @} diff --git a/port/board/afc-timing/ipmi_oem.c b/port/board/afc-timing/ipmi_oem.c index bc3780cbe..969379480 100644 --- a/port/board/afc-timing/ipmi_oem.c +++ b/port/board/afc-timing/ipmi_oem.c @@ -163,54 +163,3 @@ IPMI_HANDLER(ipmi_oem_cmd_gpio_pin, NETFN_CUSTOM_OEM, IPMI_OEM_CMD_GPIO_PIN, ipm rsp->data_len = len; } - -/* ADN4604 IPMI Control commands */ -#ifdef MODULE_ADN4604 - -#include "adn4604.h" - -/* This command may take a while to execute and hold the IPMI transaction */ -IPMI_HANDLER(ipmi_oem_adn4604_cfg_output, NETFN_CUSTOM_OEM, IPMI_OEM_CMD_ADN4604_SET_OUTPUT_CFG, ipmi_msg *req, ipmi_msg* rsp) -{ - int len = rsp->data_len = 0; - - /* @todo Read port status before setting the new configuration */ - extern adn_connect_map_t con; - uint8_t map; - uint8_t output = req->data[1]; - uint8_t input = req->data[2]; - uint8_t enable = req->data[3]; - - if (output % 2) { - *((uint8_t *)&con+(output/2)) &= 0x0F; - *((uint8_t *)&con+(output/2)) |= (input << 4) & 0xF0; - } else { - *((uint8_t *)&con+(output/2)) &= 0xF0; - *((uint8_t *)&con+(output/2)) |= input & 0x0F; - } - - map = ( req->data[0] == 0 ) ? ADN_XPT_MAP0_CON_REG : ADN_XPT_MAP1_CON_REG; - - adn4604_xpt_config( map , con ); - - if ( enable ) { - adn4604_tx_control( output, TX_ENABLED ); - } else { - adn4604_tx_control( output, TX_DISABLED ); - } - - adn4604_update(); - - rsp->data_len = len; - rsp->completion_code = IPMI_CC_OK; -} - -IPMI_HANDLER(ipmi_oem_adn4604_reset, NETFN_CUSTOM_OEM, IPMI_OEM_CMD_ADN4604_RESET, ipmi_msg *req, ipmi_msg* rsp) -{ - adn4604_reset(); - - rsp->data_len = 0; - rsp->completion_code = IPMI_CC_OK; -} - -#endif diff --git a/port/board/afc-timing/ipmi_oem.h b/port/board/afc-timing/ipmi_oem.h index 3db59ba5f..312d21546 100644 --- a/port/board/afc-timing/ipmi_oem.h +++ b/port/board/afc-timing/ipmi_oem.h @@ -44,11 +44,6 @@ #define NETFN_CUSTOM_OEM 0x30 #define IPMI_OEM_CMD_I2C_TRANSFER 0x00 - -#define IPMI_OEM_CMD_ADN4604_SET_OUTPUT_CFG 0x01 -#define IPMI_OEM_CMD_ADN4604_GET_OUTPUT_CFG 0x02 -#define IPMI_OEM_CMD_ADN4604_RESET 0x03 - #define IPMI_OEM_CMD_GPIO_PIN 0x04 /** * @} From fff54dc26ca9e53d29031d2cf718ffe096e236bb Mon Sep 17 00:00:00 2001 From: Gustavo de Souza dos Reis Date: Mon, 2 Oct 2023 10:11:29 -0300 Subject: [PATCH 07/43] Unify AFCv3.1 BPM and Timing hardware support Now that the clock switch can be configured via IPMI it is possible to use a unified firmware binary for AFCv3.1 Timing and BPM. --- .github/workflows/build.yml | 11 +- README.md | 6 +- port/board/CMakeLists.txt | 20 +- port/board/afc-bpm/v3_1/CMakeLists.txt | 62 - port/board/afc-bpm/v3_1/i2c_mapping.h | 72 -- port/board/afc-bpm/v3_1/ipmi_oem.c | 165 --- port/board/afc-bpm/v3_1/ipmi_oem.h | 52 - port/board/afc-bpm/v3_1/payload.c | 549 --------- port/board/afc-bpm/v3_1/payload.h | 122 -- port/board/afc-bpm/v3_1/pin_mapping.h | 240 ---- port/board/afc-bpm/v3_1/sdr_list.c | 1056 ----------------- port/board/afc-bpm/v3_1/user_amc_fru.h | 72 -- port/board/afc-timing/i2c_mapping.c | 91 -- .../{afc-timing => afc-v3}/CMakeLists.txt | 0 .../{afc-bpm/v3_1 => afc-v3}/i2c_mapping.c | 0 .../{afc-timing => afc-v3}/i2c_mapping.h | 0 port/board/{afc-timing => afc-v3}/ipmi_oem.c | 0 port/board/{afc-timing => afc-v3}/ipmi_oem.h | 0 port/board/{afc-timing => afc-v3}/payload.c | 0 port/board/{afc-timing => afc-v3}/payload.h | 0 .../{afc-timing => afc-v3}/pin_mapping.h | 0 port/board/{afc-timing => afc-v3}/sdr_list.c | 0 .../{afc-timing => afc-v3}/user_amc_fru.h | 0 scripts/make-release.sh | 32 +- 24 files changed, 23 insertions(+), 2527 deletions(-) delete mode 100644 port/board/afc-bpm/v3_1/CMakeLists.txt delete mode 100644 port/board/afc-bpm/v3_1/i2c_mapping.h delete mode 100644 port/board/afc-bpm/v3_1/ipmi_oem.c delete mode 100644 port/board/afc-bpm/v3_1/ipmi_oem.h delete mode 100644 port/board/afc-bpm/v3_1/payload.c delete mode 100644 port/board/afc-bpm/v3_1/payload.h delete mode 100644 port/board/afc-bpm/v3_1/pin_mapping.h delete mode 100644 port/board/afc-bpm/v3_1/sdr_list.c delete mode 100644 port/board/afc-bpm/v3_1/user_amc_fru.h delete mode 100644 port/board/afc-timing/i2c_mapping.c rename port/board/{afc-timing => afc-v3}/CMakeLists.txt (100%) rename port/board/{afc-bpm/v3_1 => afc-v3}/i2c_mapping.c (100%) rename port/board/{afc-timing => afc-v3}/i2c_mapping.h (100%) rename port/board/{afc-timing => afc-v3}/ipmi_oem.c (100%) rename port/board/{afc-timing => afc-v3}/ipmi_oem.h (100%) rename port/board/{afc-timing => afc-v3}/payload.c (100%) rename port/board/{afc-timing => afc-v3}/payload.h (100%) rename port/board/{afc-timing => afc-v3}/pin_mapping.h (100%) rename port/board/{afc-timing => afc-v3}/sdr_list.c (100%) rename port/board/{afc-timing => afc-v3}/user_amc_fru.h (100%) diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index e7475401a..8a7888952 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -14,12 +14,11 @@ jobs: strategy: matrix: build-flags: - - { flags: -DBOARD=afc-bpm -DVERSION=3.1 } - - { flags: -DBOARD=afc-timing -DBOARD_RTM=8sfp } - - { flags: -DBOARD=afc-v4 } - - { flags: -DBOARD=afc-v4 -DDEBUG_PROBE=jlink -DOPENOCD_TRANSPORT=swd } - - { flags: -DBOARD=afc-v4 -DDEBUG_PROBE=cmsis-dap -DOPENOCD_TRANSPORT=swd } - - { flags: -DBOARD=afc-v4 -DDEBUG_PROBE=digilent_jtag_hs3 -DOPENOCD_TRANSPORT=jtag } + - { flags: -DBOARD=afc -DVERSION=3.1 -DBOARD_RTM=8sfp } + - { flags: -DBOARD=afc -DVERSION=4.0} + - { flags: -DBOARD=afc -DVERSION=4.0 -DDEBUG_PROBE=jlink -DOPENOCD_TRANSPORT=swd } + - { flags: -DBOARD=afc -DVERSION=4.0 -DDEBUG_PROBE=cmsis-dap -DOPENOCD_TRANSPORT=swd } + - { flags: -DBOARD=afc -DVERSION=4.0 -DDEBUG_PROBE=digilent_jtag_hs3 -DOPENOCD_TRANSPORT=jtag } steps: - uses: actions/checkout@v3 with: diff --git a/README.md b/README.md index 205a16eae..65c758447 100644 --- a/README.md +++ b/README.md @@ -27,13 +27,13 @@ Create a new folder wherever is suitable cd -Run CMake using the path to the repository folder as an direct argument and the flag `-DBOARD=` and `-DVERSION=` to configure the compilation scripts to your specific board hardware +Run CMake using the path to the repository folder as an direct argument and the flag `-DBOARD=`(at this moment, only `afc` can be selected) ,`-DVERSION=` (`3.1` or `4.0`) and `-DBOARD_RTM=` (for now, only RTM `8sfp` for AFCv3.1 is supported) to configure the compilation scripts to your specific board hardware. - cmake -DBOARD= -DVERSION= + cmake -DBOARD= -DVERSION= -DBOARD_RTM= Example: - cmake ~/openmmc/ -DBOARD=afc -DVERSION=3.1 + cmake ~/openmmc/ -DBOARD=afc -DVERSION=3.1 -DBOARD_RTM=8sfp After creating the build files with CMake, you can compile the firmware using `make`, optionally setting the VERBOSE flag to 1 if you wish to see all the compilation commands diff --git a/port/board/CMakeLists.txt b/port/board/CMakeLists.txt index 2f548cd9c..a60c53c0c 100644 --- a/port/board/CMakeLists.txt +++ b/port/board/CMakeLists.txt @@ -4,7 +4,7 @@ if(NOT BOARD) message(FATAL_ERROR "${BoldRed}Target board was not selected! You must pass the flag -DBOARD=${ColourReset}") endif() -if(${BOARD} MATCHES "^(afc-bpm)$") +if(${BOARD} MATCHES "^(afc)$") if(NOT VERSION) message(FATAL_ERROR "${BoldRed}AFC board version was not selected! You must pass the flag -DVERSION=.${ColourReset}") @@ -14,23 +14,11 @@ if(${BOARD} MATCHES "^(afc-bpm)$") if(${VERSION} MATCHES "(3.0)") message(FATAL_ERROR "${BoldRed}AFCv3.0 is not supported anymore. Use -DVERSION=3.1 instead.${ColourReset}") elseif(${VERSION} MATCHES "(3.1)") - add_subdirectory(afc-bpm/v3_1) + add_subdirectory(afc-v3) + elseif(${VERSION} MATCHES "(4.0)") + add_subdirectory(afc-v4) endif() -elseif(${BOARD} MATCHES "^(afc-fofb-ctrl)$") - - if(NOT VERSION) - message(FATAL_ERROR "${BoldRed}AFC board version was not selected! You must pass the flag -DVERSION=.${ColourReset}") - endif() - - message(STATUS "Selected Board version: ${VERSION}") - if(${VERSION} MATCHES "(3.1)") - add_subdirectory(afc-fofb-ctrl/v3_1) - endif() - -elseif(${BOARD} MATCHES "^(afc-timing)$" ) - add_subdirectory(afc-timing) - elseif(${BOARD} MATCHES "^(afc-v4)$" ) add_subdirectory(afc-v4) diff --git a/port/board/afc-bpm/v3_1/CMakeLists.txt b/port/board/afc-bpm/v3_1/CMakeLists.txt deleted file mode 100644 index 05759cd2e..000000000 --- a/port/board/afc-bpm/v3_1/CMakeLists.txt +++ /dev/null @@ -1,62 +0,0 @@ -#Select which microcontroller and board are being used -if (NOT TARGET_CONTROLLER) - set(TARGET_CONTROLLER "LPC1764" CACHE STRING "Target MMC Controller") -endif() - -if (NOT TARGET_BOARD_NAME) - set(TARGET_BOARD_NAME "AFC 3.1" CACHE STRING "Board Name") -endif() - -#List all modules used by this board -set(TARGET_MODULES - "FRU" - "CLOCK_CONFIG" - "PAYLOAD" - "SDR" - "SCANSTA1101" - "ADN4604" - "FPGA_SPI" - "DAC_AD84XX" - "EEPROM_AT24MAC" - "EEPROM_24XX64" - "EEPROM_24XX02" - "HOTSWAP_SENSOR" - "LM75" - "MAX6642" - "INA220_VOLTAGE" - "INA220_CURRENT" - "HPM" - "UART_DEBUG" - "SYSUTILS" - "FLASH_SPI" - ) - -if (NOT DISABLE_WATCHDOG) - list(APPEND TARGET_MODULES "WATCHDOG") -endif() - -set(BOARD_PATH ${CMAKE_CURRENT_SOURCE_DIR}) - -#Include the modules sources -set(PROJ_SRCS ${PROJ_SRCS} ${BOARD_PATH}/sdr_list.c) -set(PROJ_SRCS ${PROJ_SRCS} ${BOARD_PATH}/i2c_mapping.c) -set(PROJ_SRCS ${PROJ_SRCS} ${BOARD_PATH}/ipmi_oem.c) - -if (";${TARGET_MODULES};" MATCHES ";PAYLOAD;") - set(PROJ_SRCS ${PROJ_SRCS} ${BOARD_PATH}/payload.c) - set(MODULES_FLAGS "${MODULES_FLAGS} -DMODULE_PAYLOAD") -endif() - -#Extra definitions -if (FRU_WRITE_EEPROM) - message(STATUS "FRU EEPROM will be written if no valid data is found!") - set(MODULES_FLAGS "${MODULES_FLAGS} -DFRU_WRITE_EEPROM") - set(FRU_WRITE_EEPROM false CACHE BOOL "Set this flag to enable writing the board ID on the EEPROM" FORCE) -endif() - -#Set the variables in the main scope -set(TARGET_MODULES ${TARGET_MODULES} PARENT_SCOPE) -set(MODULES_FLAGS ${MODULES_FLAGS} PARENT_SCOPE) -set(PROJ_SRCS ${PROJ_SRCS} PARENT_SCOPE) -set(PROJ_HDRS ${PROJ_HDRS} ${BOARD_PATH}) -set(PROJ_HDRS ${PROJ_HDRS} PARENT_SCOPE) diff --git a/port/board/afc-bpm/v3_1/i2c_mapping.h b/port/board/afc-bpm/v3_1/i2c_mapping.h deleted file mode 100644 index 8210289d3..000000000 --- a/port/board/afc-bpm/v3_1/i2c_mapping.h +++ /dev/null @@ -1,72 +0,0 @@ -#ifndef I2C_MAPPING_H_ -#define I2C_MAPPING_H_ - -#include "i2c.h" - -#define I2CMODE_POOLING 1 -#define I2CMODE_INTERRUPT 0 -#define SPEED_100KHZ 100000 - -// BUS_ID -// 0 - FMC1 -// 1 - FMC2 -// 3 - CPU_ID -// -/////////////////////// - -enum { - CARRIER_TYPE_AFC = 0x01, - CARRIER_TYPE_AFCK, - CARRIER_TYPE_UNKNOWN = 0xFF -}; - -enum { - I2C_BUS_UNKNOWN_ID = 0x00, - I2C_BUS_FMC1_ID, - I2C_BUS_FMC2_ID, - I2C_BUS_CPU_ID, - I2C_BUS_RTM_ID, - I2C_BUS_CLOCK_ID, - I2C_BUS_FPGA_ID -}; - -enum { - CHIP_ID_MUX = 0, - CHIP_ID_LM75AIM_0, - CHIP_ID_LM75AIM_1, - CHIP_ID_LM75AIM_2, - CHIP_ID_LM75AIM_3, - CHIP_ID_MAX6642, - CHIP_ID_RTC, - CHIP_ID_RTC_EEPROM, - CHIP_ID_EEPROM, - CHIP_ID_EEPROM_ID, - CHIP_ID_INA_0, - CHIP_ID_INA_1, - CHIP_ID_INA_2, - CHIP_ID_INA_3, - CHIP_ID_INA_4, - CHIP_ID_INA_5, - CHIP_ID_ADN, - CHIP_ID_SI57x, - CHIP_ID_FMC1_EEPROM, - CHIP_ID_FMC1_LM75_1, - CHIP_ID_FMC1_LM75_0, - CHIP_ID_FMC2_EEPROM, - CHIP_ID_FMC2_LM75_1, - CHIP_ID_FMC2_LM75_0, - CHIP_ID_RTM_PCA9554, - CHIP_ID_RTM_EEPROM, - CHIP_ID_RTM_LM75_0, - CHIP_ID_RTM_LM75_1 -}; - -#define I2C_MUX_CNT 2 -#define I2C_BUS_CNT 7 -#define I2C_CHIP_CNT 28 - -extern i2c_mux_state_t i2c_mux[]; -extern i2c_bus_mapping_t i2c_bus_map[]; -extern i2c_chip_mapping_t i2c_chip_map[]; - -#endif diff --git a/port/board/afc-bpm/v3_1/ipmi_oem.c b/port/board/afc-bpm/v3_1/ipmi_oem.c deleted file mode 100644 index 7d8382b1f..000000000 --- a/port/board/afc-bpm/v3_1/ipmi_oem.c +++ /dev/null @@ -1,165 +0,0 @@ -/* - * openMMC -- Open Source modular IPM Controller firmware - * - * Copyright (C) 2016 Henrique Silva - * Copyright (C) 2015 Piotr Miedzik - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - * - * @license GPL-3.0+ - */ - -#include "ipmi_oem.h" - -#include "port.h" -#include "i2c.h" - -/** @brief Handler for IPMI_OEM_CMD_I2C_TRANSFER IPMI command - * - * Performs a raw I2C master read on the selected bus and return the data - * Req data: - * [0] - Bus ID @see i2c_mapping.h - * [1] - #Chip/Address identification - (0) = ChipID identification on byte 2 - * (1) = I2C Address identification on byte 2 - * [2] - ChipID/I2C_Address - 8 bit address - * [3] - Data Write len (n) - * [4] - Data to Write - * [4+n] - Data Read len (m) - * - * @param req[in] - * @param rsp[out] - * - * @return - */ -IPMI_HANDLER(ipmi_oem_cmd_i2c_transfer, NETFN_CUSTOM_OEM, IPMI_OEM_CMD_I2C_TRANSFER, ipmi_msg *req, ipmi_msg* rsp) -{ - uint8_t bus_id = req->data[0]; - uint8_t chipid_sel = req->data[1]; - uint8_t chipid_i2caddr = req->data[2]; - uint8_t write_len = req->data[3]; - uint8_t read_len = req->data[4+write_len]; - uint8_t *read_data; - - uint8_t semph_err; - - uint8_t i2c_interf; - uint8_t i2c_addr; - - if ( chipid_sel == 0 ) { - /* Use chip id to take the bus */ - semph_err = i2c_take_by_chipid( chipid_i2caddr, &i2c_addr, &i2c_interf, (TickType_t)10); - } else { - semph_err = i2c_take_by_busid( bus_id, &i2c_interf, (TickType_t)10 ); - i2c_addr = chipid_i2caddr; - } - - if ( semph_err == 0 ) { - rsp->completion_code = IPMI_CC_UNSPECIFIED_ERROR; - return; - } - - if ( write_len > 0 ) { - if (xI2CMasterWrite( i2c_interf, i2c_addr, &req->data[4], write_len ) == write_len) { - rsp->completion_code = IPMI_CC_OK; - } else { - rsp->completion_code = IPMI_CC_UNSPECIFIED_ERROR; - return; - } - } - - if ( read_len > 0 ) { - read_data = pvPortMalloc( read_len ); - memset( read_data, 0, read_len ); - - if ( xI2CMasterRead( i2c_interf, i2c_addr, read_data, read_len ) == read_len ) { - rsp->data[0] = read_len; - memcpy( &rsp->data[1], read_data, read_len ); - rsp->data_len = read_len+1; - rsp->completion_code = IPMI_CC_OK; - } else { - rsp->data_len = 0; - rsp->completion_code = IPMI_CC_UNSPECIFIED_ERROR; - } - - vPortFree( read_data ); - } - - i2c_give( i2c_interf ); -} - -/* GPIO Access IPMI commands */ -/** @brief Handler for IPMI_OEM_CMD_GPIO IPMI command - * - * Access and configure the controller's GPIO - * - * Req data: - * [0] - Mode - (0) = Read port status (direction and value) - * (1) = Set pin as input - * (2) = Set pin as output (pin value is on byte 3) - * [1] - GPIO Port number - * [2] - GPIO Pin number - * [3] - Output pin value (optional) - * - * @param req[in] - * @param rsp[out] - * - * @return - */ -IPMI_HANDLER(ipmi_oem_cmd_gpio_pin, NETFN_CUSTOM_OEM, IPMI_OEM_CMD_GPIO_PIN, ipmi_msg *req, ipmi_msg* rsp) -{ - uint8_t mode = req->data[0]; - uint8_t port = req->data[1]; - uint8_t pin = req->data[2]; - uint8_t pin_state; - - uint8_t len = 0; - - rsp->completion_code = IPMI_CC_OK; - - switch (mode) { - case 0: - /* Port read, returns port direction and read value*/ - rsp->data[len++] = ( gpio_get_port_dir( port ) >> 24 ) & 0xFF; - rsp->data[len++] = ( gpio_get_port_dir( port ) >> 16 ) & 0xFF; - rsp->data[len++] = ( gpio_get_port_dir( port ) >> 8 ) & 0xFF; - rsp->data[len++] = ( gpio_get_port_dir( port ) >> 0 ) & 0xFF; - rsp->data[len++] = ( gpio_read_port( port ) >> 24 ) & 0xFF; - rsp->data[len++] = ( gpio_read_port( port ) >> 16 ) & 0xFF; - rsp->data[len++] = ( gpio_read_port( port ) >> 8 ) & 0xFF; - rsp->data[len++] = ( gpio_read_port( port ) >> 0 ) & 0xFF; - break; - - case 1: - /* Set pin as input */ - gpio_set_pin_dir( port, pin, GPIO_DIR_INPUT ); - break; - - case 2: - /* Set pin as output */ - gpio_set_pin_dir( port, pin, GPIO_DIR_OUTPUT ); - - /* If given, set the pin output value */ - if (req->data_len > 3) { - pin_state = req->data[3]; - gpio_set_pin_state( port, pin, pin_state ); - } - break; - - default: - rsp->completion_code = IPMI_CC_INV_DATA_FIELD_IN_REQ; - break; - } - - rsp->data_len = len; -} diff --git a/port/board/afc-bpm/v3_1/ipmi_oem.h b/port/board/afc-bpm/v3_1/ipmi_oem.h deleted file mode 100644 index 495985399..000000000 --- a/port/board/afc-bpm/v3_1/ipmi_oem.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * openMMC -- Open Source modular IPM Controller firmware - * - * Copyright (C) 2016 Henrique Silva - * Copyright (C) 2015 Piotr Miedzik - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - * - * @license GPL-3.0+ - */ - -#ifndef IPMI_OEM_H_ -#define IPMI_OEM_H_ - -/** - * @file afc-bpm/v3_1/ipmi_oem.h - * @brief Custom IPMI commands for AFC - * - * @ingroup AFC_V3_1_IPMI_OEM - */ - -/** - * @defgroup AFC_V3_1_IPMI_OEM AFCv3.1 IPMI OEM Commands - * @ingroup AFC_V3_1 - * @{ - */ - -#include "ipmi.h" - -/** - * @brief Custom NetFN (User defined, value greater than 0x2C) - */ -#define NETFN_CUSTOM_OEM 0x30 - -#define IPMI_OEM_CMD_I2C_TRANSFER 0x00 -#define IPMI_OEM_CMD_GPIO_PIN 0x04 -/** - * @} - */ - -#endif diff --git a/port/board/afc-bpm/v3_1/payload.c b/port/board/afc-bpm/v3_1/payload.c deleted file mode 100644 index 75af95f38..000000000 --- a/port/board/afc-bpm/v3_1/payload.c +++ /dev/null @@ -1,549 +0,0 @@ -/* - * openMMC -- Open Source modular IPM Controller firmware - * - * Copyright (C) 2015 Piotr Miedzik - * Copyright (C) 2015-2016 Henrique Silva - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - * - * @license GPL-3.0+ - */ - -/* FreeRTOS Includes */ -#include "FreeRTOS.h" -#include "task.h" -#include "semphr.h" -#include "event_groups.h" - -/* Project Includes */ -#include "port.h" -#include "payload.h" -#include "ipmi.h" -#include "task_priorities.h" -#include "adn4604.h" -#include "ad84xx.h" -#include "hotswap.h" -#include "utils.h" -#include "fru.h" -#include "led.h" -#include "board_led.h" -#include "clock_config.h" -#include "i2c_mapping.h" -#include "eeprom_24xx02.h" - -/* payload states - * 0 - No power - * - * 1 - Power Good wait - * Enable DCDC Converters - * Hotswap backend power failure and shutdown status clear - * - * 2 - FPGA setup - * One-time configurations (clock switch - ADN4604) - * - * 3 - FPGA on - * - * 4 - Power switching off - * Disable DCDC Converters - * Send "quiesced" event if requested - * - * 5 - Power quiesced - * Payload was safely turned off - * Wait until payload power goes down to restart the cycle - */ - -static void fpga_soft_reset( void ) -{ - gpio_set_pin_low( PIN_PORT(GPIO_FPGA_RESET), PIN_NUMBER(GPIO_FPGA_RESET) ); - asm("NOP"); - gpio_set_pin_high( PIN_PORT(GPIO_FPGA_RESET), PIN_NUMBER(GPIO_FPGA_RESET) ); - - /* Blink RED LED to indicate to the user that the Reset was performed */ - LEDUpdate( FRU_AMC, LED1, LEDMODE_LAMPTEST, LEDINIT_ON, 5, 0 ); -} - -static void check_fpga_reset( void ) -{ - static TickType_t edge_time; - static uint8_t reset_lock; - static uint8_t last_state = 1; - - TickType_t diff; - TickType_t cur_time = xTaskGetTickCount(); - - uint8_t cur_state = gpio_read_pin( PIN_PORT(GPIO_FRONT_BUTTON), PIN_NUMBER(GPIO_FRONT_BUTTON)); - - if ( (cur_state == 0) && (last_state == 1) ) { - /* Detects the falling edge of the front panel button */ - edge_time = cur_time; - reset_lock = 0; - } - - diff = getTickDifference( cur_time, edge_time ); - - if ( (diff > pdMS_TO_TICKS(2000)) && (reset_lock == 0) && (cur_state == 0) ) { - fpga_soft_reset(); - /* If the user continues to press the button after the 2s, prevent this action to be repeated */ - reset_lock = 1; - } - - last_state = cur_state; -} - -uint8_t payload_check_pgood( uint8_t *pgood_flag ) -{ - sensor_t * p_sensor; - SDR_type_01h_t *sdr; - - extern const SDR_type_01h_t SDR_FMC1_12V; - - /* Iterate through the SDR Table to find all the LM75 entries */ - for ( p_sensor = sdr_head; (p_sensor != NULL) || (p_sensor->task_handle == NULL); p_sensor = p_sensor->next) { - if (p_sensor->sdr == &SDR_FMC1_12V) { - sdr = ( SDR_type_01h_t * ) p_sensor->sdr; - *pgood_flag = ( ( p_sensor->readout_value >= (sdr->lower_critical_thr ) ) && - ( p_sensor->readout_value <= (sdr->upper_critical_thr ) ) ); - return 1; - } - } - - return 0; -} - -/** - * @brief Set AFC's DCDC Converters state - * - * @param on DCDCs state - * - * @warning The FMC1_P12V DCDC is not affected by this function since it has to be always on in order to measure the Payload power status on the AFC board. - */ -void setDC_DC_ConvertersON( bool on ) -{ - gpio_set_pin_state( PIN_PORT(GPIO_EN_FMC1_PVADJ), PIN_NUMBER(GPIO_EN_FMC1_PVADJ), on ); - //gpio_set_pin_state( PIN_PORT(GPIO_EN_FMC1_P12V), PIN_NUMBER(GPIO_EN_FMC1_P12V), on ); - gpio_set_pin_state( PIN_PORT(GPIO_EN_FMC1_P3V3), PIN_NUMBER(GPIO_EN_FMC1_P3V3), on ); - - gpio_set_pin_state( PIN_PORT(GPIO_EN_FMC2_PVADJ), PIN_NUMBER(GPIO_EN_FMC2_PVADJ), on ); - gpio_set_pin_state( PIN_PORT(GPIO_EN_FMC2_P12V), PIN_NUMBER(GPIO_EN_FMC2_P12V), on ); - gpio_set_pin_state( PIN_PORT(GPIO_EN_FMC2_P3V3), PIN_NUMBER(GPIO_EN_FMC2_P3V3), on ); - - gpio_set_pin_state( PIN_PORT(GPIO_EN_P1V0), PIN_NUMBER(GPIO_EN_P1V0), on ); - gpio_set_pin_state( PIN_PORT(GPIO_EN_P1V8), PIN_NUMBER(GPIO_EN_P1V8), on ); // <- this one causes problems if not switched off before power loss - gpio_set_pin_state( PIN_PORT(GPIO_EN_P1V2), PIN_NUMBER(GPIO_EN_P1V2), on ); - gpio_set_pin_state( PIN_PORT(GPIO_EN_P1V5_VTT), PIN_NUMBER(GPIO_EN_P1V5_VTT), on ); - gpio_set_pin_state( PIN_PORT(GPIO_EN_P3V3), PIN_NUMBER(GPIO_EN_P3V3), on ); -} - -#ifdef MODULE_DAC_AD84XX -void set_vadj_volt( uint8_t fmc_slot, float v ) -{ - uint32_t res_total; - uint32_t res_dac; - - res_total = (uint32_t) (1162.5/(v-0.775)) - 453; - res_dac = (1800*res_total)/(1800-res_total); - - /* Use only the lower 8-bits (the dac only has 256 steps) */ - res_dac &= 0xFF; - - dac_ad84xx_set_res( fmc_slot, res_dac ); -} -#endif - -EventGroupHandle_t amc_payload_evt = NULL; -#ifdef MODULE_RTM -EventGroupHandle_t rtm_payload_evt = NULL; -#endif - -void payload_send_message( uint8_t fru_id, EventBits_t msg) -{ - if ( (fru_id == FRU_AMC) && amc_payload_evt ) { - xEventGroupSetBits( amc_payload_evt, msg ); -#ifdef MODULE_RTM - } else if ( (fru_id == FRU_RTM) && rtm_payload_evt ) { - xEventGroupSetBits( rtm_payload_evt, msg ); -#endif - } -} - -TaskHandle_t vTaskPayload_Handle; - -void payload_init( void ) -{ - /* Set standalone mode if the module is disconnected from a create*/ - bool standalone_mode = false; - - if (get_ipmb_addr() == IPMB_ADDR_DISCONNECTED) { - standalone_mode = true; - } - - if (!standalone_mode) { - /* Wait until ENABLE# signal is asserted ( ENABLE == 0) */ - while ( gpio_read_pin( PIN_PORT(GPIO_MMC_ENABLE), PIN_NUMBER(GPIO_MMC_ENABLE) ) == 1 ) {}; - } - - xTaskCreate( vTaskPayload, "Payload", 256, NULL, tskPAYLOAD_PRIORITY, &vTaskPayload_Handle ); - - amc_payload_evt = xEventGroupCreate(); -#ifdef MODULE_RTM - rtm_payload_evt = xEventGroupCreate(); -#endif - -#ifdef MODULE_DAC_AD84XX - /* Configure the PVADJ DAC */ - dac_ad84xx_init(); - set_vadj_volt( 0, 2.5 ); - set_vadj_volt( 1, 2.5 ); -#endif - - gpio_set_pin_state( PIN_PORT(GPIO_FPGA_RESET), PIN_NUMBER(GPIO_FPGA_RESET), GPIO_LEVEL_HIGH ); -} - -void vTaskPayload( void *pvParameters ) -{ - uint8_t state = PAYLOAD_NO_POWER; - /* Use arbitrary state value to force the first state update */ - uint8_t new_state = -1; - - /* Payload power good flag */ - uint8_t PP_good = 0; - - /* Payload DCDCs good flag */ - uint8_t DCDC_good = 0; - - uint8_t QUIESCED_req = 0; - EventBits_t current_evt; - - extern sensor_t * hotswap_amc_sensor; - - TickType_t xLastWakeTime; - xLastWakeTime = xTaskGetTickCount(); - - gpio_set_pin_state( PIN_PORT(GPIO_FPGA_PROGRAM_B), PIN_NUMBER(GPIO_FPGA_PROGRAM_B), GPIO_LEVEL_HIGH ); - - for ( ;; ) { - check_fpga_reset(); - - /* Initialize one of the FMC's DCDC so we can measure when the Payload Power is present */ - gpio_set_pin_state( PIN_PORT(GPIO_EN_FMC1_P12V), PIN_NUMBER(GPIO_EN_FMC1_P12V), GPIO_LEVEL_HIGH ); - - new_state = state; - - current_evt = xEventGroupGetBits( amc_payload_evt ); - - /* - * When receive a PAYLOAD_MESSAGE_CLOCK_CONFIG command, write the new configuration - * in EEPROM memory, reset the clock configuration and perform the new configuration. - */ - if( current_evt & PAYLOAD_MESSAGE_CLOCK_CONFIG ){ - eeprom_24xx02_write(CHIP_ID_RTC_EEPROM, 0x0, clock_config, 16, 10); - if (PAYLOAD_FPGA_ON) { - adn4604_reset(); - clock_configuration(); - } - xEventGroupClearBits(amc_payload_evt, PAYLOAD_MESSAGE_CLOCK_CONFIG); - } - - if ( current_evt & PAYLOAD_MESSAGE_QUIESCE ) { - - /* - * If you issue a shutdown fru command in the MCH shell, the payload power - * task will receive a PAYLOAD_MESSAGE_QUIESCE message and set the - * QUIESCED_req flag to '1' and the MCH will shutdown the 12VP0 power, - * making the payload power task go to PAYLOAD_NO_POWER state. - * So, if we are in the PAYLOAD_QUIESCED state and receive a - * PAYLOAD_MESSAGE_QUIESCE message, the QUIESCED_req flag - * should be '0' - */ - - if (state == PAYLOAD_QUIESCED) { - QUIESCED_req = 0; - } else { - QUIESCED_req = 1; - } - xEventGroupClearBits( amc_payload_evt, PAYLOAD_MESSAGE_QUIESCE ); - } - - if ( current_evt & PAYLOAD_MESSAGE_COLD_RST ) { - state = PAYLOAD_RESET; - xEventGroupClearBits( amc_payload_evt, PAYLOAD_MESSAGE_COLD_RST ); - } - - if ( (current_evt & PAYLOAD_MESSAGE_REBOOT) || (current_evt & PAYLOAD_MESSAGE_WARM_RST) ) { - fpga_soft_reset(); - xEventGroupClearBits(amc_payload_evt, PAYLOAD_MESSAGE_REBOOT | PAYLOAD_MESSAGE_WARM_RST); - } - - payload_check_pgood(&PP_good); - DCDC_good = gpio_read_pin( PIN_PORT(GPIO_DCDC_PGOOD), PIN_NUMBER(GPIO_DCDC_PGOOD) ); - - switch(state) { - - case PAYLOAD_NO_POWER: - if (PP_good) { - new_state = PAYLOAD_POWER_GOOD_WAIT; - } - break; - - case PAYLOAD_POWER_GOOD_WAIT: - /* Turn DDC converters on */ - setDC_DC_ConvertersON( true ); - - /* Clear hotswap sensor backend power failure bits */ - hotswap_clear_mask_bit( HOTSWAP_AMC, HOTSWAP_BACKEND_PWR_SHUTDOWN_MASK ); - hotswap_clear_mask_bit( HOTSWAP_AMC, HOTSWAP_BACKEND_PWR_FAILURE_MASK ); - - if ( QUIESCED_req || ( PP_good == 0 ) ) { - new_state = PAYLOAD_SWITCHING_OFF; - } else if ( DCDC_good == 1 ) { - new_state = PAYLOAD_STATE_FPGA_SETUP; - } - break; - - case PAYLOAD_STATE_FPGA_SETUP: -#ifdef MODULE_ADN4604 - /* Configure clock switch */ - clock_configuration(); -#endif - new_state = PAYLOAD_FPGA_ON; - break; - - case PAYLOAD_FPGA_ON: - if ( QUIESCED_req == 1 || PP_good == 0 || DCDC_good == 0 ) { - new_state = PAYLOAD_SWITCHING_OFF; - } - break; - - case PAYLOAD_SWITCHING_OFF: - setDC_DC_ConvertersON( false ); - - /* Respond to quiesce event if any */ - if ( QUIESCED_req ) { - hotswap_set_mask_bit( HOTSWAP_AMC, HOTSWAP_QUIESCED_MASK ); - hotswap_send_event( hotswap_amc_sensor, HOTSWAP_STATE_QUIESCED ); - hotswap_clear_mask_bit( HOTSWAP_AMC, HOTSWAP_QUIESCED_MASK ); - QUIESCED_req = 0; - } - new_state = PAYLOAD_QUIESCED; - break; - - case PAYLOAD_QUIESCED: - /* Wait until power goes down to restart the cycle */ - if (PP_good == 0 && DCDC_good == 0) { - new_state = PAYLOAD_NO_POWER; - } - break; - - case PAYLOAD_RESET: - /*Reset DCDC converters*/ - setDC_DC_ConvertersON( false ); - new_state = PAYLOAD_NO_POWER; - break; - - default: - break; - } - - state = new_state; - vTaskDelayUntil( &xLastWakeTime, PAYLOAD_BASE_DELAY ); - } -} - -/* HPM Functions */ -#ifdef MODULE_HPM - -#include "flash_spi.h" -#include "string.h" - -uint8_t *hpm_page = NULL; -uint8_t hpm_pg_index; -uint32_t hpm_page_addr; - -uint8_t payload_hpm_prepare_comp( void ) -{ - /* Initialize variables */ - if (hpm_page != NULL) { - vPortFree(hpm_page); - } - - hpm_page = (uint8_t *) pvPortMalloc(PAYLOAD_HPM_PAGE_SIZE); - - if (hpm_page == NULL) { - /* Malloc failed */ - return IPMI_CC_OUT_OF_SPACE; - } - - memset(hpm_page, 0xFF, PAYLOAD_HPM_PAGE_SIZE); - - hpm_pg_index = 0; - hpm_page_addr = 0; - - /* Initialize flash */ - ssp_init( FLASH_SPI, FLASH_SPI_BITRATE, FLASH_SPI_FRAME_SIZE, SSP_MASTER, SSP_INTERRUPT ); - - /* Prevent the FPGA from accessing the Flash to configure itself now */ - gpio_set_pin_state( PIN_PORT(GPIO_FPGA_PROGRAM_B), PIN_NUMBER(GPIO_FPGA_PROGRAM_B), GPIO_LEVEL_HIGH ); - gpio_set_pin_state( PIN_PORT(GPIO_FPGA_PROGRAM_B), PIN_NUMBER(GPIO_FPGA_PROGRAM_B), GPIO_LEVEL_LOW ); - gpio_set_pin_state( PIN_PORT(GPIO_FPGA_PROGRAM_B), PIN_NUMBER(GPIO_FPGA_PROGRAM_B), GPIO_LEVEL_HIGH ); - gpio_set_pin_state( PIN_PORT(GPIO_FPGA_PROGRAM_B), PIN_NUMBER(GPIO_FPGA_PROGRAM_B), GPIO_LEVEL_LOW ); - - /* Erase FLASH */ - flash_bulk_erase(); - - return IPMI_CC_COMMAND_IN_PROGRESS; -} - -uint8_t payload_hpm_upload_block( uint8_t * block, uint16_t size ) -{ - /* TODO: Check DONE pin before accessing the SPI bus, since the FPGA may be reading it in order to boot */ - uint8_t remaining_bytes_start; - - if ( PAYLOAD_HPM_PAGE_SIZE - hpm_pg_index > size ) { - /* Our page is not full yet, just append the new data */ - memcpy(&hpm_page[hpm_pg_index], block, size); - hpm_pg_index += size; - - return IPMI_CC_OK; - - } else { - /* Complete the remaining bytes on the buffer */ - memcpy(&hpm_page[hpm_pg_index], block, (PAYLOAD_HPM_PAGE_SIZE - hpm_pg_index)); - remaining_bytes_start = (PAYLOAD_HPM_PAGE_SIZE - hpm_pg_index); - - /* Program the complete page in the Flash */ - flash_program_page( hpm_page_addr, &hpm_page[0], PAYLOAD_HPM_PAGE_SIZE); - - hpm_page_addr += PAYLOAD_HPM_PAGE_SIZE; - - /* Empty our buffer and reset the index */ - memset(hpm_page, 0xFF, PAYLOAD_HPM_PAGE_SIZE); - hpm_pg_index = 0; - - /* Save the trailing bytes */ - memcpy(&hpm_page[hpm_pg_index], block+remaining_bytes_start, size-remaining_bytes_start); - - hpm_pg_index = size-remaining_bytes_start; - - return IPMI_CC_COMMAND_IN_PROGRESS; - } -} - -uint8_t payload_hpm_finish_upload( uint32_t image_size ) -{ - uint8_t cc = IPMI_CC_OK; - - /* Check if the last page was already programmed */ - if (!hpm_pg_index) { - /* Program the complete page in the Flash */ - flash_program_page( hpm_page_addr, &hpm_page[0], (PAYLOAD_HPM_PAGE_SIZE-hpm_pg_index)); - hpm_pg_index = 0; - hpm_page_addr = 0; - - cc = IPMI_CC_COMMAND_IN_PROGRESS; - } - - /* Free page buffer */ - vPortFree(hpm_page); - hpm_page = NULL; - - return cc; -} - -uint8_t payload_hpm_get_upgrade_status( void ) -{ - if (is_flash_busy()) { - return IPMI_CC_COMMAND_IN_PROGRESS; - } else { - return IPMI_CC_OK; - } -} - -uint8_t payload_hpm_activate_firmware( void ) -{ - /* Reset FPGA - Pulse PROGRAM_B pin */ - gpio_set_pin_state( PIN_PORT(GPIO_FPGA_PROGRAM_B), PIN_NUMBER(GPIO_FPGA_PROGRAM_B), GPIO_LEVEL_LOW); - gpio_set_pin_state( PIN_PORT(GPIO_FPGA_PROGRAM_B), PIN_NUMBER(GPIO_FPGA_PROGRAM_B), GPIO_LEVEL_HIGH); - - return IPMI_CC_OK; -} - -void clock_configuration() -{ - adn_connect_map_t con; - - /* Read the clock configuration from the eeprom */ - eeprom_24xx02_read(CHIP_ID_RTC_EEPROM, 0x0, clock_config, 16, 10); - - /* Translate the configuration to enable or disable the outputs */ - uint16_t out_enable_flag = { - ((clock_config[0] & 0x80) >> 7) << 0 | - ((clock_config[1] & 0x80) >> 7) << 1 | - ((clock_config[2] & 0x80) >> 7) << 2 | - ((clock_config[3] & 0x80) >> 7) << 3 | - ((clock_config[4] & 0x80) >> 7) << 4 | - ((clock_config[5] & 0x80) >> 7) << 5 | - ((clock_config[6] & 0x80) >> 7) << 6 | - ((clock_config[7] & 0x80) >> 7) << 7 | - ((clock_config[8] & 0x80) >> 7) << 8 | - ((clock_config[9] & 0x80) >> 7) << 9 | - ((clock_config[10] & 0x80) >> 7) << 10 | - ((clock_config[11] & 0x80) >> 7) << 11 | - ((clock_config[12] & 0x80) >> 7) << 12 | - ((clock_config[13] & 0x80) >> 7) << 13 | - ((clock_config[14] & 0x80) >> 7) << 14 | - ((clock_config[15] & 0x80) >> 7) << 15 - }; - - /* Disable UPDATE' pin by pulling it GPIO_LEVEL_HIGH */ - gpio_set_pin_state( PIN_PORT(GPIO_ADN_UPDATE), PIN_NUMBER(GPIO_ADN_UPDATE), GPIO_LEVEL_HIGH ); - - /* There's a delay circuit in the Reset pin of the clock switch, we must wait until it clears out */ - while( gpio_read_pin( PIN_PORT(GPIO_ADN_RESETN), PIN_NUMBER(GPIO_ADN_RESETN) ) == 0 ) { - vTaskDelay( 50 ); - } - - /* Configure the interconnects*/ - con.out0 = clock_config[0] & 0x0F; - con.out1 = clock_config[1] & 0x0F; - con.out2 = clock_config[2] & 0x0F; - con.out3 = clock_config[3] & 0x0F; - con.out4 = clock_config[4] & 0x0F; - con.out5 = clock_config[5] & 0x0F; - con.out6 = clock_config[6] & 0x0F; - con.out7 = clock_config[7] & 0x0F; - con.out8 = clock_config[8] & 0x0F; - con.out9 = clock_config[9] & 0x0F; - con.out10 = clock_config[10] & 0x0F; - con.out11 = clock_config[11] & 0x0F; - con.out12 = clock_config[12] & 0x0F; - con.out13 = clock_config[13] & 0x0F; - con.out14 = clock_config[14] & 0x0F; - con.out15 = clock_config[15] & 0x0F; - - adn4604_xpt_config( ADN_XPT_MAP0_CON_REG, con ); - - /* Enable desired outputs */ - for ( uint8_t i = 0; i < 16; i++ ) { - if ( ( out_enable_flag >> i ) & 0x1 ) { - adn4604_tx_control( i, TX_ENABLED ); - } else { - adn4604_tx_control( i, TX_DISABLED ); - } - } - - adn4604_active_map( ADN_XPT_MAP0 ); - - adn4604_update(); -} -#endif diff --git a/port/board/afc-bpm/v3_1/payload.h b/port/board/afc-bpm/v3_1/payload.h deleted file mode 100644 index 37c466376..000000000 --- a/port/board/afc-bpm/v3_1/payload.h +++ /dev/null @@ -1,122 +0,0 @@ -/* - * openMMC -- Open Source modular IPM Controller firmware - * - * Copyright (C) 2015 Piotr Miedzik - * Copyright (C) 2015-2016 Henrique Silva - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - * - * @license GPL-3.0+ - */ - -/** - * @file afc/v3_1/payload.h - * @brief Payload control module definitions for AFCv3.1 - * - * @ingroup AFC_V3_1_PAYLOAD - */ - -/** - * @defgroup AFC_V3_1_PAYLOAD AFCv3.1 Payload Control - * @ingroup AFC_V3_1 - * @{ - */ - -#ifndef PAYLOAD_H_ -#define PAYLOAD_H_ - -#include "event_groups.h" - -/** - * @brief Payload state machine state numbers - */ -extern enum { - PAYLOAD_NO_POWER = 0, - PAYLOAD_POWER_GOOD_WAIT, - PAYLOAD_STATE_FPGA_SETUP, - PAYLOAD_FPGA_ON, - PAYLOAD_SWITCHING_OFF, - PAYLOAD_QUIESCED, - PAYLOAD_RESET, - PAYLOAD_MAX_STATES -} payload_state; - -/** - * @defgroup AFC_V3_1_PAYLOAD_MSG Payload Messages Codes - * @ingroup AFC_V3_1_PAYLOAD - * @{ - */ -#define PAYLOAD_MESSAGE_COLD_RST (1 << 0) -#define PAYLOAD_MESSAGE_WARM_RST (1 << 1) -#define PAYLOAD_MESSAGE_REBOOT (1 << 2) -#define PAYLOAD_MESSAGE_QUIESCE (1 << 3) -#define PAYLOAD_MESSAGE_CLOCK_CONFIG (1 << 4) -/** - * @} - */ - -/** - * @brief Payload task unblock delay - */ -#define PAYLOAD_BASE_DELAY 100 - -/** - * @brief Payload task handle variable - */ -extern TaskHandle_t vTaskPayload_Handle; - -/** - * @brief Sends a message to the payload task - * - * This function basically sets a flag that the Payload task reads and advances (or not) on the state machine - * - * @param fru_id Target FRU ID (0:AMC 1:RTM) - * @param msg Message to send, using @ref AFC_V3_1_PAYLOAD_MSG definitions - */ -void payload_send_message( uint8_t fru_id, EventBits_t msg ); - -/** - * @brief Payload Control task - * - * @param pvParameters Pointer to buffer holding parameters passed to task upon initialization - */ -void vTaskPayload( void *pvParameters ); - -/** - * @brief Creates Payload Control task and initializes the board's needed hardware - */ -void payload_init( void ); - -#ifdef MODULE_HPM - -#define PAYLOAD_HPM_PAGE_SIZE 256 - -uint8_t payload_hpm_prepare_comp( void ); -uint8_t payload_hpm_upload_block( uint8_t * block, uint16_t size ); -uint8_t payload_hpm_finish_upload( uint32_t image_size ); -uint8_t payload_hpm_get_upgrade_status( void ); -uint8_t payload_hpm_activate_firmware( void ); -#endif - -/** - * @brief Configure the clock switch interconects according to the configuration - * saved in EEPROM - */ -void clock_configuration(); - -#endif /* IPMI_PAYLOAD_H_ */ - -/** - * @} - */ diff --git a/port/board/afc-bpm/v3_1/pin_mapping.h b/port/board/afc-bpm/v3_1/pin_mapping.h deleted file mode 100644 index a39868b9f..000000000 --- a/port/board/afc-bpm/v3_1/pin_mapping.h +++ /dev/null @@ -1,240 +0,0 @@ -/* - * openMMC -- Open Source modular IPM Controller firmware - * - * Copyright (C) 2016 Henrique Silva - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - * - * @license GPL-3.0+ - */ - -/** - * @defgroup AFC_V3_1 AFCv3.1 Board Port - * @ingroup BOARD_PORTS - */ - -/** - * @file afc-bpm/v3_1/pin_mapping.h - * @brief Hardware pin definitions for AFCv3.1 - * - * @ingroup AFC_V3_1_PIN_MAPPING - */ - -/** - * @defgroup AFC_V3_1_PIN_MAPPING AFCv3.1 Pin Mapping - * @ingroup AFC_V3_1 - * @{ - */ - -#ifndef PIN_MAPPING_H_ -#define PIN_MAPPING_H_ - -/* SPI Interfaces */ -#define FPGA_SPI 0 -#define FLASH_SPI 1 - -/* UART Interfaces */ -#define UART_DEBUG 3 - -/* Pin definitions */ - -/* I2C ports */ -#define I2C0_SDA PIN_DEF( PORT0, 27, (IOCON_FUNC1 | IOCON_MODE_INACT), NON_GPIO ) -#define I2C0_SCL PIN_DEF( PORT0, 28, (IOCON_FUNC1 | IOCON_MODE_INACT), NON_GPIO ) -#define I2C1_SDA PIN_DEF( PORT0, 0, (IOCON_FUNC3 | IOCON_MODE_INACT), NON_GPIO ) -#define I2C1_SCL PIN_DEF( PORT0, 1, (IOCON_FUNC3 | IOCON_MODE_INACT), NON_GPIO ) -#define I2C2_SDA PIN_DEF( PORT0, 10, (IOCON_FUNC2 | IOCON_MODE_INACT), NON_GPIO ) -#define I2C2_SCL PIN_DEF( PORT0, 11, (IOCON_FUNC2 | IOCON_MODE_INACT), NON_GPIO ) - -/* UART Debug port */ -#define UART_DEBUG_TXD PIN_DEF( PORT4, 28, (IOCON_FUNC3 | IOCON_MODE_INACT), NON_GPIO ) -#define UART_DEBUG_RXD PIN_DEF( PORT4, 29, (IOCON_FUNC3 | IOCON_MODE_INACT), NON_GPIO ) - -/* SSP Ports */ -/* FPGA SPI Port (SSEL is GPIO for word transfers larger than 8bits) */ -#define SSP0_SCK PIN_DEF( PORT1, 20, (IOCON_FUNC3 | IOCON_MODE_INACT), NON_GPIO ) -#define SSP0_SSEL PIN_DEF( PORT1, 21, (IOCON_FUNC0 | IOCON_MODE_INACT), GPIO_DIR_OUTPUT ) -#define SSP0_MISO PIN_DEF( PORT1, 23, (IOCON_FUNC3 | IOCON_MODE_INACT), NON_GPIO ) -#define SSP0_MOSI PIN_DEF( PORT1, 24, (IOCON_FUNC3 | IOCON_MODE_INACT), NON_GPIO ) -/* Flash SPI Port (SSEL is GPIO for word transfers larger than 8bits) */ -#define SSP1_SCK PIN_DEF( PORT0, 7, (IOCON_FUNC2 | IOCON_MODE_INACT), NON_GPIO ) -#define SSP1_SSEL PIN_DEF( PORT0, 6, (IOCON_FUNC0 | IOCON_MODE_INACT), GPIO_DIR_OUTPUT ) -#define SSP1_MISO PIN_DEF( PORT0, 8, (IOCON_FUNC2 | IOCON_MODE_INACT), NON_GPIO ) -#define SSP1_MOSI PIN_DEF( PORT0, 9, (IOCON_FUNC2 | IOCON_MODE_INACT), NON_GPIO ) - -/* SPI Legacy port - should be updated to SSP interface */ -/* DAC SPI Port (SSEL is GPIO for word transfers larger than 8bits) */ -#define SPI_SCK PIN_DEF( PORT0, 15, (IOCON_FUNC3 | IOCON_MODE_INACT), NON_GPIO ) -#define SPI_SSEL PIN_DEF( PORT0, 16, (IOCON_FUNC0 | IOCON_MODE_INACT), GPIO_DIR_OUTPUT ) -//#define SPI_MISO PIN_DEF( PORT0, 17, (IOCON_FUNC3 | IOCON_MODE_INACT), NON_GPIO ) -#define SPI_MOSI PIN_DEF( PORT0, 18, (IOCON_FUNC3 | IOCON_MODE_INACT), NON_GPIO ) - -/* GPIO definitions */ -/* Geographic Address pin definitions */ -#define GPIO_GA0 PIN_DEF( PORT1, 0, (IOCON_FUNC0 | IOCON_MODE_INACT), GPIO_DIR_INPUT ) -#define GPIO_GA1 PIN_DEF( PORT1, 1, (IOCON_FUNC0 | IOCON_MODE_INACT), GPIO_DIR_INPUT ) -#define GPIO_GA2 PIN_DEF( PORT1, 4, (IOCON_FUNC0 | IOCON_MODE_INACT), GPIO_DIR_INPUT ) -#define GPIO_GA_TEST PIN_DEF( PORT1, 8, (IOCON_FUNC0 | IOCON_MODE_INACT), GPIO_DIR_OUTPUT ) - -/* Board LEDs */ -#define GPIO_LEDBLUE PIN_DEF( PORT1, 9, (IOCON_FUNC0 | IOCON_MODE_PULLUP), GPIO_DIR_OUTPUT ) -#define GPIO_LEDGREEN PIN_DEF( PORT1, 10, (IOCON_FUNC0 | IOCON_MODE_PULLDOWN), GPIO_DIR_OUTPUT ) -#define GPIO_LEDRED PIN_DEF( PORT1, 25, (IOCON_FUNC0 | IOCON_MODE_PULLDOWN), GPIO_DIR_OUTPUT ) - -/* Front Panel BUTTON */ -#define GPIO_FRONT_BUTTON PIN_DEF( PORT2, 12, (IOCON_FUNC0 | IOCON_MODE_PULLUP), GPIO_DIR_INPUT ) - -/* Hot swap handle */ -#define GPIO_HOT_SWAP_HANDLE PIN_DEF( PORT2, 13, (IOCON_FUNC0 | IOCON_MODE_PULLUP), GPIO_DIR_INPUT ) - -/* FPGA DCDC converters */ -#define GPIO_EN_P1V0 PIN_DEF( PORT3, 25, (IOCON_FUNC0 | IOCON_MODE_PULLDOWN), GPIO_DIR_OUTPUT ) -#define GPIO_EN_P1V2 PIN_DEF( PORT0, 23, (IOCON_FUNC0 | IOCON_MODE_PULLDOWN), GPIO_DIR_OUTPUT ) -#define GPIO_EN_P1V8 PIN_DEF( PORT0, 24, (IOCON_FUNC0 | IOCON_MODE_PULLDOWN), GPIO_DIR_OUTPUT ) -#define GPIO_EN_P3V3 PIN_DEF( PORT1, 27, (IOCON_FUNC0 | IOCON_MODE_PULLDOWN), GPIO_DIR_OUTPUT ) -#define GPIO_EN_P1V5_VTT PIN_DEF( PORT1, 29, (IOCON_FUNC0 | IOCON_MODE_PULLDOWN), GPIO_DIR_OUTPUT ) -#define GPIO_DCDC_PGOOD PIN_DEF( PORT3, 26, (IOCON_FUNC0 | IOCON_MODE_PULLDOWN), GPIO_DIR_INPUT ) - -/* FMC1 DCDC Converters */ -#define GPIO_EN_FMC1_P12V PIN_DEF( PORT0, 4, (IOCON_FUNC0 | IOCON_MODE_PULLDOWN), GPIO_DIR_OUTPUT ) -#define GPIO_EN_FMC1_P3V3 PIN_DEF( PORT0, 25, (IOCON_FUNC0 | IOCON_MODE_PULLDOWN), GPIO_DIR_OUTPUT ) -#define GPIO_EN_FMC1_PVADJ PIN_DEF( PORT1, 31, (IOCON_FUNC0 | IOCON_MODE_PULLDOWN), GPIO_DIR_OUTPUT ) - -/* FMC2 DCDC Converters */ -#define GPIO_EN_FMC2_P12V PIN_DEF( PORT0, 5, (IOCON_FUNC0 | IOCON_MODE_PULLDOWN), GPIO_DIR_OUTPUT ) -#define GPIO_EN_FMC2_P3V3 PIN_DEF( PORT0, 26, (IOCON_FUNC0 | IOCON_MODE_PULLDOWN), GPIO_DIR_OUTPUT ) -#define GPIO_EN_FMC2_PVADJ PIN_DEF( PORT1, 28, (IOCON_FUNC0 | IOCON_MODE_PULLDOWN), GPIO_DIR_OUTPUT ) - -/* RTM */ -#define GPIO_EN_RTM_PWR PIN_DEF( PORT1, 30, (IOCON_FUNC0 | IOCON_MODE_PULLDOWN), GPIO_DIR_OUTPUT ) -/* NOTE: Due to a hardware limitation, pins 29 and 30 from port 0 will have the same direction, even if set differently in the register */ -#define GPIO_RTM_PS PIN_DEF( PORT0, 29, (IOCON_FUNC0 | IOCON_MODE_PULLUP), GPIO_DIR_INPUT ) -#define GPIO_EN_RTM_I2C PIN_DEF( PORT0, 30, (IOCON_FUNC0 | IOCON_MODE_PULLDOWN), GPIO_DIR_OUTPUT ) - -/* FPGA Control */ -#define GPIO_FPGA_PROGRAM_B PIN_DEF( PORT0, 17, (IOCON_FUNC0 | IOCON_MODE_PULLDOWN), GPIO_DIR_OUTPUT ) -#define GPIO_FPGA_DONE_B PIN_DEF( PORT0, 22, (IOCON_FUNC0 | IOCON_MODE_INACT), GPIO_DIR_INPUT ) -#define GPIO_FPGA_RESET PIN_DEF( PORT2, 9, (IOCON_FUNC0 | IOCON_MODE_PULLDOWN), GPIO_DIR_OUTPUT ) -#define GPIO_FLASH_CS_MUX PIN_DEF( PORT0, 19, (IOCON_FUNC0 | IOCON_MODE_INACT), GPIO_DIR_INPUT ) -#define GPIO_FPGA_INITB PIN_DEF( PORT0, 20, (IOCON_FUNC0 | IOCON_MODE_INACT), GPIO_DIR_INPUT ) - -/* VADJ DAC */ -#define GPIO_DAC_VADJ_RST PIN_DEF( PORT0, 21, (IOCON_FUNC0 | IOCON_MODE_PULLUP), GPIO_DIR_OUTPUT ) -#define GPIO_DAC_VADJ_CSN PIN_DEF( PORT0, 16, (IOCON_FUNC0 | IOCON_MODE_PULLUP), GPIO_DIR_OUTPUT ) - -/* ADN4604 Clock Switch */ -#define GPIO_ADN_UPDATE PIN_DEF( PORT1, 26, (IOCON_FUNC0 | IOCON_MODE_PULLUP), GPIO_DIR_OUTPUT ) -#define GPIO_ADN_RESETN PIN_DEF( PORT1, 22, (IOCON_FUNC0 | IOCON_MODE_PULLUP), GPIO_DIR_INPUT ) - -/* SCANSTA1101 JTAG Switch */ -#define GPIO_SCANSTA1101_ADDR0 PIN_DEF( PORT2, 0, (IOCON_FUNC0 | IOCON_MODE_PULLDOWN), GPIO_DIR_OUTPUT ) -#define GPIO_SCANSTA1101_ADDR1 PIN_DEF( PORT2, 1, (IOCON_FUNC0 | IOCON_MODE_PULLDOWN), GPIO_DIR_OUTPUT ) -#define GPIO_SCANSTA1101_ADDR2 PIN_DEF( PORT2, 2, (IOCON_FUNC0 | IOCON_MODE_PULLDOWN), GPIO_DIR_OUTPUT ) -#define GPIO_SCANSTA1101_ADDR3 PIN_DEF( PORT2, 3, (IOCON_FUNC0 | IOCON_MODE_PULLDOWN), GPIO_DIR_OUTPUT ) -#define GPIO_SCANSTA1101_ADDR4 PIN_DEF( PORT2, 4, (IOCON_FUNC0 | IOCON_MODE_PULLDOWN), GPIO_DIR_OUTPUT ) -#define GPIO_SCANSTA1101_ADDR5 PIN_DEF( PORT2, 5, (IOCON_FUNC0 | IOCON_MODE_PULLDOWN), GPIO_DIR_OUTPUT ) -#define GPIO_SCANSTA1101_ADDR6 PIN_DEF( PORT2, 6, (IOCON_FUNC0 | IOCON_MODE_PULLDOWN), GPIO_DIR_OUTPUT ) -#define GPIO_SCANSTA1101_TRIST_B PIN_DEF( PORT2, 7, (IOCON_FUNC0 | IOCON_MODE_INACT), GPIO_DIR_INPUT ) - -/* MMC ENABLE# */ -#define GPIO_MMC_ENABLE PIN_DEF( PORT2, 8, (IOCON_FUNC0 | IOCON_MODE_PULLUP), GPIO_DIR_INPUT ) - -/* Overtemp signal */ -#define GPIO_OVERTEMPn PIN_DEF( PORT2, 10, (IOCON_FUNC0 | IOCON_MODE_PULLUP), GPIO_DIR_INPUT ) - -/* FMC Present signals */ -#define GPIO_FMC1_PRSNT_M2C PIN_DEF( PORT1, 14, (IOCON_FUNC0 | IOCON_MODE_PULLUP), GPIO_DIR_INPUT ) -#define GPIO_FMC2_PRSNT_M2C PIN_DEF( PORT1, 15, (IOCON_FUNC0 | IOCON_MODE_PULLUP), GPIO_DIR_INPUT ) - -/* FMC Power Good signals */ -#define GPIO_FMC1_PG_M2C PIN_DEF( PORT1, 16, (IOCON_FUNC0 | IOCON_MODE_PULLUP), GPIO_DIR_INPUT ) -#define GPIO_FMC2_PG_M2C PIN_DEF( PORT1, 17, (IOCON_FUNC0 | IOCON_MODE_PULLUP), GPIO_DIR_INPUT ) -#define GPIO_FMC1_PG_C2M PIN_DEF( PORT1, 18, (IOCON_FUNC0 | IOCON_MODE_PULLUP), GPIO_DIR_OUTPUT ) -#define GPIO_FMC2_PG_C2M PIN_DEF( PORT1, 19, (IOCON_FUNC0 | IOCON_MODE_PULLUP), GPIO_DIR_OUTPUT ) - -/* Pin initialization (config) list */ -#define PIN_CFG_LIST \ - I2C0_SDA, \ - I2C0_SCL, \ - I2C1_SDA, \ - I2C1_SCL, \ - I2C2_SDA, \ - I2C2_SCL, \ - UART_DEBUG_TXD, \ - UART_DEBUG_RXD, \ - SSP0_SCK, \ - SSP0_SSEL, \ - SSP0_MISO, \ - SSP0_MOSI, \ - SSP1_SCK, \ - SSP1_SSEL, \ - SSP1_MISO, \ - SSP1_MOSI, \ - SPI_SCK, \ - SPI_SSEL, \ - SPI_MOSI, \ - GPIO_GA0, \ - GPIO_GA1, \ - GPIO_GA2, \ - GPIO_GA_TEST, \ - GPIO_LEDBLUE, \ - GPIO_LEDGREEN, \ - GPIO_LEDRED, \ - GPIO_FRONT_BUTTON, \ - GPIO_HOT_SWAP_HANDLE, \ - GPIO_EN_P1V0, \ - GPIO_EN_P1V2, \ - GPIO_EN_P1V8, \ - GPIO_EN_P3V3, \ - GPIO_EN_P1V5_VTT, \ - GPIO_DCDC_PGOOD, \ - GPIO_EN_FMC1_P12V, \ - GPIO_EN_FMC1_P3V3, \ - GPIO_EN_FMC1_PVADJ, \ - GPIO_EN_FMC2_P12V, \ - GPIO_EN_FMC2_P3V3, \ - GPIO_EN_FMC2_PVADJ, \ - GPIO_EN_RTM_PWR, \ - GPIO_RTM_PS, \ - GPIO_EN_RTM_I2C, \ - GPIO_FPGA_PROGRAM_B, \ - GPIO_FPGA_DONE_B, \ - GPIO_FPGA_RESET, \ - GPIO_FPGA_INITB, \ - GPIO_FLASH_CS_MUX, \ - GPIO_DAC_VADJ_RST, \ - GPIO_DAC_VADJ_CSN, \ - GPIO_ADN_UPDATE, \ - GPIO_ADN_RESETN, \ - GPIO_SCANSTA1101_ADDR0, \ - GPIO_SCANSTA1101_ADDR1, \ - GPIO_SCANSTA1101_ADDR2, \ - GPIO_SCANSTA1101_ADDR3, \ - GPIO_SCANSTA1101_ADDR4, \ - GPIO_SCANSTA1101_ADDR5, \ - GPIO_SCANSTA1101_ADDR6, \ - GPIO_SCANSTA1101_TRIST_B, \ - GPIO_MMC_ENABLE, \ - GPIO_FMC1_PRSNT_M2C, \ - GPIO_FMC2_PRSNT_M2C, \ - GPIO_FMC1_PG_M2C, \ - GPIO_FMC2_PG_M2C, \ - GPIO_FMC1_PG_C2M, \ - GPIO_FMC2_PG_C2M - -#endif - -/** - * @} - */ diff --git a/port/board/afc-bpm/v3_1/sdr_list.c b/port/board/afc-bpm/v3_1/sdr_list.c deleted file mode 100644 index 6f0915d91..000000000 --- a/port/board/afc-bpm/v3_1/sdr_list.c +++ /dev/null @@ -1,1056 +0,0 @@ -/* - * openMMC -- Open Source modular IPM Controller firmware - * - * Copyright (C) 2015-2016 Henrique Silva - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - * - * @license GPL-3.0+ - */ - -/* Project Includes */ -#include "sdr.h" -#include "utils.h" -#include "i2c_mapping.h" - -/* Sensors includes */ -#include "sensors.h" -#include "fpga_spi.h" - -/* SDR List */ -#ifdef MODULE_INA220_VOLTAGE -#include "ina220.h" -#define SDR_FMC1_12V_ID "FMC1 +12V" -#define SDR_FMC1_VADJ_ID "FMC1 VADJ" -#define SDR_FMC1_P3V3_ID "FMC1 +3.3V" -#define SDR_FMC2_12V_ID "FMC2 +12V" -#define SDR_FMC2_VADJ_ID "FMC2 VADJ" -#define SDR_FMC2_P3V3_ID "FMC2 +3.3V" -#endif -#ifdef MODULE_INA220_CURRENT -#include "ina220.h" -#define SDR_FMC1_VADJ_CURR_ID "FMC1 +12V Curr" -#define SDR_FMC1_12V_CURR_ID "FMC1 VADJ Curr" -#define SDR_FMC1_P3V3_CURR_ID "FMC1 +3.3V Curr" -#define SDR_FMC2_VADJ_CURR_ID "FMC2 +12V Curr" -#define SDR_FMC2_12V_CURR_ID "FMC2 VADJ Curr" -#define SDR_FMC2_P3V3_CURR_ID "FMC2 +3.3V Curr" -#endif - -#ifdef MODULE_HOTSWAP -/* AMC Hot-Swap sensor SDR */ -const SDR_type_02h_t SDR_HOTSWAP_AMC = { - - .hdr.recID_LSB = 0x00, /* Filled by sdr_insert_entry() */ - .hdr.recID_MSB = 0x00, - .hdr.SDRversion = 0x51, - .hdr.rectype = TYPE_02, - .hdr.reclength = sizeof(SDR_type_02h_t) - sizeof(SDR_entry_hdr_t), - - .ownerID = 0x00, /* i2c address, -> SDR_Init */ - .ownerLUN = 0x00, /* sensor owner LUN */ - .sensornum = 0x00, /* Filled by sdr_insert_entry() */ - -/* record body bytes */ - .entityID = 0xC1, /* entity id: AMC Module */ - .entityinstance = 0x00, /* entity instance -> SDR_Init */ - .sensorinit = 0x03, /* init: event generation + scanning enabled */ - .sensorcap = 0xc1, /* capabilities: auto re-arm,*/ - .sensortype = SENSOR_TYPE_HOT_SWAP, /* sensor type: HOT SWAP*/ - .event_reading_type = 0x6f, /* sensor reading*/ - .assertion_event_mask = 0x0000, /* assertion event mask */ - .deassertion_event_mask = 0x0000, /* deassertion event mask */ - .readable_threshold_mask = 0x00, /* LSB: readable Threshold mask: no thresholds are readable: */ - .settable_threshold_mask = 0x00, /* MSB: setable Threshold mask: no thresholds are setable: */ - .sensor_units_1 = 0xc0, /* sensor units 1 : Does not return analog reading*/ - .sensor_units_2 = 0x00, /* sensor units 2 :*/ - .sensor_units_3 = 0x00, /* sensor units 3 :*/ - .record_sharing[0] = 0x00, - .record_sharing[1] = 0x00, - .pos_thr_hysteresis = 0x00, /* positive going Threshold hysteresis value */ - .neg_thr_hysteresis = 0x00, /* negative going Threshold hysteresis value */ - .reserved1 = 0x00, /* reserved */ - .reserved2 = 0x00, /* reserved */ - .reserved3 = 0x00, /* reserved */ - .OEM = 0x00, /* OEM reserved */ - .IDtypelen = 0xc0 | STR_SIZE("HOTSWAP AMC"), /* 8 bit ASCII, number of bytes */ - .IDstring = "HOTSWAP AMC" /* sensor string */ -}; -#endif - -#ifdef MODULE_INA220_VOLTAGE -/* FMC1 12V */ -const SDR_type_01h_t SDR_FMC1_12V = { - - .hdr.recID_LSB = 0x00, /* Filled by sdr_insert_entry() */ - .hdr.recID_MSB = 0x00, - .hdr.SDRversion = 0x51, - .hdr.rectype = TYPE_01, - .hdr.reclength = sizeof(SDR_type_01h_t) - sizeof(SDR_entry_hdr_t), - - .ownerID = 0x00, /* i2c address, -> SDR_Init */ - .ownerLUN = 0x00, /* sensor owner LUN */ - .sensornum = 0x00, /* Filled by sdr_insert_entry() */ - - /* record body bytes */ - .entityID = 0xC1, /* entity id: AMC Module */ - .entityinstance = 0x00, /* entity instance -> SDR_Init */ - .sensorinit = 0x7F, /* init: event generation + scanning enabled */ - .sensorcap = 0x56, /* capabilities: auto re-arm,*/ - .sensortype = SENSOR_TYPE_VOLTAGE, /* sensor type: Voltage*/ - .event_reading_type = 0x01, /* sensor reading*/ - .assertion_event_mask = 0x7A95, /* assertion event mask (All upper going-high and lower going-low events) */ - .deassertion_event_mask = 0x7A95, /* deassertion event mask (All upper going-high and lower going-low events) */ - .readable_threshold_mask = 0x3F, /* LSB: readable Threshold mask: all thresholds are readable: */ - .settable_threshold_mask = 0x00, /* MSB: setable Threshold mask: none of the thresholds are setable: */ - .sensor_units_1 = 0x00, /* sensor units 1 :*/ - .sensor_units_2 = 0x04, /* sensor units 2 :*/ - .sensor_units_3 = 0x00, /* sensor units 3 :*/ - .linearization = 0x00, /* Linearization */ - .M = 64, /* M */ - .M_tol = 0x00, /* M - Tolerance */ - .B = 0x00, /* B */ - .B_accuracy = 0x00, /* B - Accuracy */ - .acc_exp_sensor_dir = 0x02, /* Sensor direction */ - .Rexp_Bexp = 0xD0, /* R-Exp = -3 , B-Exp = 0 */ - .analog_flags = 0x03, /* Analogue characteristics flags */ - .nominal_reading = 190, /* Nominal reading = 12.285V */ - .normal_max = 200, /* Normal maximum */ - .normal_min = 0, /* Normal minimum */ - .sensor_max_reading = 0xFF, /* Sensor Maximum reading */ - .sensor_min_reading = 0x00, /* Sensor Minimum reading */ - .upper_nonrecover_thr = 205, /* Upper non-recoverable Threshold */ - .upper_critical_thr = 200, /* Upper critical Threshold */ - .upper_noncritical_thr = 195, /* Upper non critical Threshold */ - .lower_nonrecover_thr = 170, /* Lower non-recoverable Threshold */ - .lower_critical_thr = 175, /* Lower critical Threshold */ - .lower_noncritical_thr = 180, /* Lower non-critical Threshold */ - .pos_thr_hysteresis = 2, /* positive going Threshold hysteresis value */ - .neg_thr_hysteresis = 2, /* negative going Threshold hysteresis value */ - .reserved1 = 0x00, /* reserved */ - .reserved2 = 0x00, /* reserved */ - .OEM = 0x00, /* OEM reserved */ - .IDtypelen = 0xc0 | STR_SIZE(SDR_FMC1_12V_ID) , /* 8 bit ASCII, number of bytes */ - .IDstring = SDR_FMC1_12V_ID /* sensor string */ -}; - -/* FMC1 PVADJ */ -const SDR_type_01h_t SDR_FMC1_VADJ = { - .hdr.recID_LSB = 0x00, /* Filled by sdr_insert_entry() */ - .hdr.recID_MSB = 0x00, - .hdr.SDRversion = 0x51, - .hdr.rectype = TYPE_01, - .hdr.reclength = sizeof(SDR_type_01h_t) - sizeof(SDR_entry_hdr_t), - - .ownerID = 0x00, /* i2c address, -> SDR_Init */ - .ownerLUN = 0x00, /* sensor owner LUN */ - .sensornum = 0x00, /* Filled by sdr_insert_entry() */ - - /* record body bytes */ - .entityID = 0xC1, /* entity id: AMC Module */ - .entityinstance = 0x00, /* entity instance -> SDR_Init */ - .sensorinit = 0x7F, /* init: event generation + scanning enabled */ - .sensorcap = 0x56, /* capabilities: auto re-arm,*/ - .sensortype = SENSOR_TYPE_VOLTAGE, /* sensor type: voltage*/ - .event_reading_type = 0x01, /* sensor reading*/ - .assertion_event_mask = 0x7A95, /* assertion event mask (All upper going-high and lower going-low events) */ - .deassertion_event_mask = 0x7A95, /* deassertion event mask (All upper going-high and lower going-low events) */ - .readable_threshold_mask = 0x3F, /* LSB: readable Threshold mask: all thresholds are readable: */ - .settable_threshold_mask = 0x00, /* MSB: setable Threshold mask: none of the thresholds are setable: */ - .sensor_units_1 = 0x00, /* sensor units 1 :*/ - .sensor_units_2 = 0x04, /* sensor units 2 :*/ - .sensor_units_3 = 0x00, /* sensor units 3 :*/ - .linearization = 0x00, /* Linearization */ - .M = 64, /* M */ - .M_tol = 0x00, /* M - Tolerance */ - .B = 0x00, /* B */ - .B_accuracy = 0x00, /* B - Accuracy */ - .acc_exp_sensor_dir = 0x00, /* Sensor direction */ - .Rexp_Bexp = 0xD0, /* R-Exp , B-Exp */ - .analog_flags = 0x00, /* Analogue characteristics flags */ - .nominal_reading = 39, /* Nominal reading */ - .normal_max = 47, /* Normal maximum */ - .normal_min = 0, /* Normal minimum */ - .sensor_max_reading = 0xFF, /* Sensor Maximum reading */ - .sensor_min_reading = 0x00, /* Sensor Minimum reading */ - .upper_nonrecover_thr = 51, /* Upper non-recoverable Threshold */ - .upper_critical_thr = 46, /* Upper critical Threshold */ - .upper_noncritical_thr = 43, /* Upper non critical Threshold */ - .lower_nonrecover_thr = 28, /* Lower non-recoverable Threshold */ - .lower_critical_thr = 32, /* Lower critical Threshold */ - .lower_noncritical_thr = 36, /* Lower non-critical Threshold */ - .pos_thr_hysteresis = 1, /* positive going Threshold hysteresis value */ - .neg_thr_hysteresis = 1, /* negative going Threshold hysteresis value */ - .reserved1 = 0x00, /* reserved */ - .reserved2 = 0x00, /* reserved */ - .OEM = 0x00, /* OEM reserved */ - .IDtypelen = 0xc0 | STR_SIZE(SDR_FMC1_VADJ_ID), /* 8 bit ASCII, number of bytes */ - .IDstring = SDR_FMC1_VADJ_ID /* sensor string */ -}; - -/* FMC1 P3V3 */ -const SDR_type_01h_t SDR_FMC1_P3V3 = { - .hdr.recID_LSB = 0x00, /* Filled by sdr_insert_entry() */ - .hdr.recID_MSB = 0x00, - .hdr.SDRversion = 0x51, - .hdr.rectype = TYPE_01, - .hdr.reclength = sizeof(SDR_type_01h_t) - sizeof(SDR_entry_hdr_t), - - .ownerID = 0x00, /* i2c address, -> SDR_Init */ - .ownerLUN = 0x00, /* sensor owner LUN */ - .sensornum = 0x00, /* Filled by sdr_insert_entry() */ - - /* record body bytes */ - .entityID = 0xC1, /* entity id: AMC Module */ - .entityinstance = 0x00, /* entity instance -> SDR_Init */ - .sensorinit = 0x7F, /* init: event generation + scanning enabled */ - .sensorcap = 0x56, /* capabilities: auto re-arm,*/ - .sensortype = SENSOR_TYPE_VOLTAGE, /* sensor type: VOLTAGE*/ - .event_reading_type = 0x01, /* sensor reading*/ - .assertion_event_mask = 0x7A95, /* assertion event mask (All upper going-high and lower going-low events) */ - .deassertion_event_mask = 0x7A95, /* deassertion event mask (All upper going-high and lower going-low events) */ - .readable_threshold_mask = 0x3F, /* LSB: readable Threshold mask: all thresholds are readable: */ - .settable_threshold_mask = 0x00, /* MSB: setable Threshold mask: none of the thresholds are setable: */ - .sensor_units_1 = 0x00, /* sensor units 1 :*/ - .sensor_units_2 = 0x04, /* sensor units 2 :*/ - .sensor_units_3 = 0x00, /* sensor units 3 :*/ - .M = 64, /* M */ - .M_tol = 0x00, /* M - Tolerance */ - .B = 0x00, /* B */ - .B_accuracy = 0x00, /* B - Accuracy */ - .acc_exp_sensor_dir = 0x00, /* Sensor direction */ - .Rexp_Bexp = 0xD0, /* R-Exp , B-Exp */ - .analog_flags = 0x00, /* Analogue characteristics flags */ - .nominal_reading = 52, /* Nominal reading */ - .normal_max = 59, /* Normal maximum */ - .normal_min = 45, /* Normal minimum */ - .sensor_max_reading = 0xFF, /* Sensor Maximum reading */ - .sensor_min_reading = 0x00, /* Sensor Minimum reading */ - .upper_nonrecover_thr = 62, /* Upper non-recoverable Threshold */ - .upper_critical_thr = 59, /* Upper critical Threshold */ - .upper_noncritical_thr = 55, /* Upper non critical Threshold */ - .lower_nonrecover_thr = 42, /* Lower non-recoverable Threshold */ - .lower_critical_thr = 45, /* Lower critical Threshold */ - .lower_noncritical_thr = 48, /* Lower non-critical Threshold */ - .pos_thr_hysteresis = 2, /* positive going Threshold hysteresis value */ - .neg_thr_hysteresis = 2, /* negative going Threshold hysteresis value */ - .reserved1 = 0x00, /* reserved */ - .reserved2 = 0x00, /* reserved */ - .OEM = 0x00, /* OEM reserved */ - .IDtypelen = 0xc0 | STR_SIZE(SDR_FMC1_P3V3_ID), /* 8 bit ASCII, number of bytes */ - .IDstring = SDR_FMC1_P3V3_ID /* sensor string */ -}; - -/* FMC2 12V */ -const SDR_type_01h_t SDR_FMC2_12V = { - .hdr.recID_LSB = 0x00, /* Filled by sdr_insert_entry() */ - .hdr.recID_MSB = 0x00, - .hdr.SDRversion = 0x51, - .hdr.rectype = TYPE_01, - .hdr.reclength = sizeof(SDR_type_01h_t) - sizeof(SDR_entry_hdr_t), - - .ownerID = 0x00, /* i2c address, -> SDR_Init */ - .ownerLUN = 0x00, /* sensor owner LUN */ - .sensornum = 0x00, /* Filled by sdr_insert_entry() */ - - /* record body bytes */ - .entityID = 0xC1, /* entity id: AMC Module */ - .entityinstance = 0x00, /* entity instance -> SDR_Init */ - .sensorinit = 0x7F, /* init: event generation + scanning enabled */ - .sensorcap = 0x56, /* capabilities: auto re-arm,*/ - .sensortype = SENSOR_TYPE_VOLTAGE, /* sensor type: Voltage*/ - .event_reading_type = 0x01, /* sensor reading*/ - .assertion_event_mask = 0x7A95, /* assertion event mask (All upper going-high and lower going-low events) */ - .deassertion_event_mask = 0x7A95, /* deassertion event mask (All upper going-high and lower going-low events) */ - .readable_threshold_mask = 0x3F, /* LSB: readable Threshold mask: all thresholds are readable: */ - .settable_threshold_mask = 0x00, /* MSB: setable Threshold mask: none of the thresholds are setable: */ - .sensor_units_1 = 0x00, /* sensor units 1 :*/ - .sensor_units_2 = 0x04, /* sensor units 2 :*/ - .sensor_units_3 = 0x00, /* sensor units 3 :*/ - .linearization = 0x00, /* Linearization */ - .M = 64, /* M */ - .M_tol = 0x00, /* M - Tolerance */ - .B = 0x00, /* B */ - .B_accuracy = 0x00, /* B - Accuracy */ - .acc_exp_sensor_dir = 0x02, /* Sensor direction */ - .Rexp_Bexp = 0xD0, /* R-Exp = -3 , B-Exp = 0 */ - .analog_flags = 0x03, /* Analogue characteristics flags */ - .nominal_reading = 190, /* Nominal reading = 12.285V */ - .normal_max = 200, /* Normal maximum */ - .normal_min = 0, /* Normal minimum */ - .sensor_max_reading = 0xFF, /* Sensor Maximum reading */ - .sensor_min_reading = 0x00, /* Sensor Minimum reading */ - .upper_nonrecover_thr = 205, /* Upper non-recoverable Threshold */ - .upper_critical_thr = 200, /* Upper critical Threshold */ - .upper_noncritical_thr = 195, /* Upper non critical Threshold */ - .lower_nonrecover_thr = 170, /* Lower non-recoverable Threshold */ - .lower_critical_thr = 175, /* Lower critical Threshold */ - .lower_noncritical_thr = 180, /* Lower non-critical Threshold */ - .pos_thr_hysteresis = 2, /* positive going Threshold hysteresis value */ - .neg_thr_hysteresis = 2, /* negative going Threshold hysteresis value */ - .reserved1 = 0x00, /* reserved */ - .reserved2 = 0x00, /* reserved */ - .OEM = 0x00, /* OEM reserved */ - .IDtypelen = 0xc0 | STR_SIZE(SDR_FMC2_12V_ID), /* 8 bit ASCII, number of bytes */ - .IDstring = SDR_FMC2_12V_ID /* sensor string */ -}; - -/* FMC2 PVADJ */ -const SDR_type_01h_t SDR_FMC2_VADJ = { - .hdr.recID_LSB = 0x00, /* Filled by sdr_insert_entry() */ - .hdr.recID_MSB = 0x00, - .hdr.SDRversion = 0x51, - .hdr.rectype = TYPE_01, - .hdr.reclength = sizeof(SDR_type_01h_t) - sizeof(SDR_entry_hdr_t), - - .ownerID = 0x00, /* i2c address, -> SDR_Init */ - .ownerLUN = 0x00, /* sensor owner LUN */ - .sensornum = 0x00, /* Filled by sdr_insert_entry() */ - - /* record body bytes */ - .entityID = 0xC1, /* entity id: AMC Module */ - .entityinstance = 0x00, /* entity instance -> SDR_Init */ - .sensorinit = 0x7F, /* init: event generation + scanning enabled */ - .sensorcap = 0x56, /* capabilities: auto re-arm,*/ - .sensortype = SENSOR_TYPE_VOLTAGE, /* sensor type: voltage*/ - .event_reading_type = 0x01, /* sensor reading*/ - .assertion_event_mask = 0x7A95, /* assertion event mask (All upper going-high and lower going-low events) */ - .deassertion_event_mask = 0x7A95, /* deassertion event mask (All upper going-high and lower going-low events) */ - .readable_threshold_mask = 0x3F, /* LSB: readable Threshold mask: all thresholds are readable: */ - .settable_threshold_mask = 0x00, /* MSB: setable Threshold mask: none of the thresholds are setable: */ - .sensor_units_1 = 0x00, /* sensor units 1 :*/ - .sensor_units_2 = 0x04, /* sensor units 2 :*/ - .sensor_units_3 = 0x00, /* sensor units 3 :*/ - .linearization = 0x00, /* Linearization */ - .M = 64, /* M */ - .M_tol = 0x00, /* M - Tolerance */ - .B = 0x00, /* B */ - .B_accuracy = 0x00, /* B - Accuracy */ - .acc_exp_sensor_dir = 0x00, /* Sensor direction */ - .Rexp_Bexp = 0xD0, /* R-Exp , B-Exp */ - .analog_flags = 0x00, /* Analogue characteristics flags */ - .nominal_reading = 39, /* Nominal reading */ - .normal_max = 47, /* Normal maximum */ - .normal_min = 0, /* Normal minimum */ - .sensor_max_reading = 0xFF, /* Sensor Maximum reading */ - .sensor_min_reading = 0x00, /* Sensor Minimum reading */ - .upper_nonrecover_thr = 51, /* Upper non-recoverable Threshold */ - .upper_critical_thr = 46, /* Upper critical Threshold */ - .upper_noncritical_thr = 43, /* Upper non critical Threshold */ - .lower_nonrecover_thr = 28, /* Lower non-recoverable Threshold */ - .lower_critical_thr = 32, /* Lower critical Threshold */ - .lower_noncritical_thr = 36, /* Lower non-critical Threshold */ - .pos_thr_hysteresis = 1, /* positive going Threshold hysteresis value */ - .neg_thr_hysteresis = 1, /* negative going Threshold hysteresis value */ - .reserved1 = 0x00, /* reserved */ - .reserved2 = 0x00, /* reserved */ - .OEM = 0x00, /* OEM reserved */ - .IDtypelen = 0xc0 | STR_SIZE(SDR_FMC2_VADJ_ID), /* 8 bit ASCII, number of bytes */ - .IDstring = SDR_FMC2_VADJ_ID /* sensor string */ -}; - -/* FMC2 P3V3 */ -const SDR_type_01h_t SDR_FMC2_P3V3 = { - - .hdr.recID_LSB = 0x00, /* Filled by sdr_insert_entry() */ - .hdr.recID_MSB = 0x00, - .hdr.SDRversion = 0x51, - .hdr.rectype = TYPE_01, - .hdr.reclength = sizeof(SDR_type_01h_t) - sizeof(SDR_entry_hdr_t), - - .ownerID = 0x00, /* i2c address, -> SDR_Init */ - .ownerLUN = 0x00, /* sensor owner LUN */ - .sensornum = 0x00, /* Filled by sdr_insert_entry() */ - - /* record body bytes */ - .entityID = 0xC1, /* entity id: AMC Module */ - .entityinstance = 0x00, /* entity instance -> SDR_Init */ - .sensorinit = 0x7F, /* init: event generation + scanning enabled */ - .sensorcap = 0x56, /* capabilities: auto re-arm,*/ - .sensortype = SENSOR_TYPE_VOLTAGE, /* sensor type: VOLTAGE*/ - .event_reading_type = 0x01, /* sensor reading*/ - .assertion_event_mask = 0x7A95, /* assertion event mask (All upper going-high and lower going-low events) */ - .deassertion_event_mask = 0x7A95, /* deassertion event mask (All upper going-high and lower going-low events) */ - .readable_threshold_mask = 0x3F, /* LSB: readable Threshold mask: all thresholds are readable: */ - .settable_threshold_mask = 0x00, /* MSB: setable Threshold mask: none of the thresholds are setable: */ - .sensor_units_1 = 0x00, /* sensor units 1 :*/ - .sensor_units_2 = 0x04, /* sensor units 2 :*/ - .sensor_units_3 = 0x00, /* sensor units 3 :*/ - .linearization = 0x00, /* Linearization */ - .M = 64, /* M */ - .M_tol = 0x00, /* M - Tolerance */ - .B = 0x00, /* B */ - .B_accuracy = 0x00, /* B - Accuracy */ - .acc_exp_sensor_dir = 0x00, /* Sensor direction */ - .Rexp_Bexp = 0xD0, /* R-Exp , B-Exp */ - .analog_flags = 0x00, /* Analogue characteristics flags */ - .nominal_reading = 52, /* Nominal reading */ - .normal_max = 59, /* Normal maximum */ - .normal_min = 45, /* Normal minimum */ - .sensor_max_reading = 0xFF, /* Sensor Maximum reading */ - .sensor_min_reading = 0x00, /* Sensor Minimum reading */ - .upper_nonrecover_thr = 62, /* Upper non-recoverable Threshold */ - .upper_critical_thr = 59, /* Upper critical Threshold */ - .upper_noncritical_thr = 55, /* Upper non critical Threshold */ - .lower_nonrecover_thr = 42, /* Lower non-recoverable Threshold */ - .lower_critical_thr = 45, /* Lower critical Threshold */ - .lower_noncritical_thr = 48, /* Lower non-critical Threshold */ - .pos_thr_hysteresis = 2, /* positive going Threshold hysteresis value */ - .neg_thr_hysteresis = 2, /* negative going Threshold hysteresis value */ - .reserved1 = 0x00, /* reserved */ - .reserved2 = 0x00, /* reserved */ - .OEM = 0x00, /* OEM reserved */ - .IDtypelen = 0xc0 | STR_SIZE(SDR_FMC2_P3V3_ID), /* 8 bit ASCII, number of bytes */ - .IDstring = SDR_FMC2_P3V3_ID /* sensor string */ -}; -#endif - -#ifdef MODULE_INA220_CURRENT -/* FMC1 12V Current */ -const SDR_type_01h_t SDR_FMC1_12V_CURR = { - - .hdr.recID_LSB = 0x00, /* Filled by sdr_insert_entry() */ - .hdr.recID_MSB = 0x00, - .hdr.SDRversion = 0x51, - .hdr.rectype = TYPE_01, - .hdr.reclength = sizeof(SDR_type_01h_t) - sizeof(SDR_entry_hdr_t), - - .ownerID = 0x00, /* i2c address, -> SDR_Init */ - .ownerLUN = 0x00, /* sensor owner LUN */ - .sensornum = 0x00, /* Filled by sdr_insert_entry() */ - - /* record body bytes */ - .entityID = 0xC1, /* entity id: AMC Module */ - .entityinstance = 0x00, /* entity instance -> SDR_Init */ - .sensorinit = 0x7F, /* init: event generation + scanning enabled */ - .sensorcap = 0x56, /* capabilities: auto re-arm */ - .sensortype = SENSOR_TYPE_CURRENT, /* sensor type: Current */ - .event_reading_type = 0x01, /* sensor reading*/ - .assertion_event_mask = 0x0A80, /* assertion event mask (All upper going-high and lower going-low events) */ - .deassertion_event_mask = 0x7A80, /* deassertion event mask (All upper going-high and lower going-low events) */ - .readable_threshold_mask = 0x3F, /* LSB: readable Threshold mask: all thresholds are readable: */ - .settable_threshold_mask = 0x00, /* MSB: setable Threshold mask: none of the thresholds are setable: */ - .sensor_units_1 = 0x80, /* sensor units 1 :*/ - .sensor_units_2 = 0x05, /* sensor units 2 :*/ - .sensor_units_3 = 0x00, /* sensor units 3 :*/ - .linearization = 0x00, /* Linearization */ - .M = 32, /* M */ - .M_tol = 0x00, /* M - Tolerance */ - .B = 0x00, /* B */ - .B_accuracy = 0x00, /* B - Accuracy */ - .acc_exp_sensor_dir = 0x02, /* Sensor direction */ - .Rexp_Bexp = 0xD0, /* R-Exp = -3 , B-Exp = 0 */ - .analog_flags = 0x03, /* Analogue characteristics flags */ - .nominal_reading = 32, /* Nominal reading = 1A */ - .normal_max = 125, /* Normal maximum */ - .normal_min = 0, /* Normal minimum */ - .sensor_max_reading = 0xFF, /* Sensor Maximum reading */ - .sensor_min_reading = 0x00, /* Sensor Minimum reading */ - .upper_nonrecover_thr = 125, /* Upper non-recoverable Threshold - 4A */ - .upper_critical_thr = 110, /* Upper critical Threshold - 3.5A */ - .upper_noncritical_thr = 95, /* Upper non critical Threshold - 3A */ - .lower_nonrecover_thr = -15, /* Lower non-recoverable Threshold - -0.1A */ - .lower_critical_thr = -10, /* Lower critical Threshold - 0.32A */ - .lower_noncritical_thr = -5, /* Lower non-critical Threshold - 0.5A */ - .pos_thr_hysteresis = 2, /* positive going Threshold hysteresis value */ - .neg_thr_hysteresis = 2, /* negative going Threshold hysteresis value */ - .reserved1 = 0x00, /* reserved */ - .reserved2 = 0x00, /* reserved */ - .OEM = 0x00, /* OEM reserved */ - .IDtypelen = 0xc0 | STR_SIZE(SDR_FMC1_12V_CURR_ID) , /* 8 bit ASCII, number of bytes */ - .IDstring = SDR_FMC1_12V_CURR_ID /* sensor string */ -}; - -/* FMC1 PVADJ Current */ -const SDR_type_01h_t SDR_FMC1_VADJ_CURR = { - .hdr.recID_LSB = 0x00, /* Filled by sdr_insert_entry() */ - .hdr.recID_MSB = 0x00, - .hdr.SDRversion = 0x51, - .hdr.rectype = TYPE_01, - .hdr.reclength = sizeof(SDR_type_01h_t) - sizeof(SDR_entry_hdr_t), - - .ownerID = 0x00, /* i2c address, -> SDR_Init */ - .ownerLUN = 0x00, /* sensor owner LUN */ - .sensornum = 0x00, /* Filled by sdr_insert_entry() */ - - /* record body bytes */ - .entityID = 0xC1, /* entity id: AMC Module */ - .entityinstance = 0x00, /* entity instance -> SDR_Init */ - .sensorinit = 0x7F, /* init: event generation + scanning enabled */ - .sensorcap = 0x56, /* capabilities: auto re-arm */ - .sensortype = SENSOR_TYPE_CURRENT, /* sensor type: CURRENT */ - .event_reading_type = 0x01, /* sensor reading*/ - .assertion_event_mask = 0x0A80, /* assertion event mask (All upper going-high and lower going-low events) */ - .deassertion_event_mask = 0x7A80, /* deassertion event mask (All upper going-high and lower going-low events) */ - .readable_threshold_mask = 0x3F, /* LSB: readable Threshold mask: all thresholds are readable: */ - .settable_threshold_mask = 0x00, /* MSB: setable Threshold mask: none of the thresholds are setable: */ - .sensor_units_1 = 0x80, /* sensor units 1 :*/ - .sensor_units_2 = 0x05, /* sensor units 2 :*/ - .sensor_units_3 = 0x00, /* sensor units 3 :*/ - .linearization = 0x00, /* Linearization */ - .M = 32, /* M */ - .M_tol = 0x00, /* M - Tolerance */ - .B = 0x00, /* B */ - .B_accuracy = 0x00, /* B - Accuracy */ - .acc_exp_sensor_dir = 0x00, /* Sensor direction */ - .Rexp_Bexp = 0xD0, /* R-Exp , B-Exp */ - .analog_flags = 0x00, /* Analogue characteristics flags */ - .nominal_reading = 39, /* Nominal reading - 1.24A */ - .normal_max = 47, /* Normal maximum - 1.5A*/ - .normal_min = 0, /* Normal minimum - 0A */ - .sensor_max_reading = 0x7F, /* Sensor Maximum reading */ - .sensor_min_reading = 0x80, /* Sensor Minimum reading */ - .upper_nonrecover_thr = 125, /* Upper non-recoverable Threshold - 4A */ - .upper_critical_thr = 110, /* Upper critical Threshold - 3.5A */ - .upper_noncritical_thr = 94, /* Upper non critical Threshold - 3A */ - .lower_nonrecover_thr = -15, /* Lower non-recoverable Threshold - -0.32A */ - .lower_critical_thr = -10, /* Lower critical Threshold - 0A */ - .lower_noncritical_thr = -5, /* Lower non-critical Threshold - 0.16A */ - .pos_thr_hysteresis = 2, /* positive going Threshold hysteresis value */ - .neg_thr_hysteresis = 2, /* negative going Threshold hysteresis value */ - .reserved1 = 0x00, /* reserved */ - .reserved2 = 0x00, /* reserved */ - .OEM = 0x00, /* OEM reserved */ - .IDtypelen = 0xc0 | STR_SIZE(SDR_FMC1_VADJ_CURR_ID), /* 8 bit ASCII, number of bytes */ - .IDstring = SDR_FMC1_VADJ_CURR_ID /* sensor string */ -}; - -/* FMC1 P3V3 Current */ -const SDR_type_01h_t SDR_FMC1_P3V3_CURR = { - .hdr.recID_LSB = 0x00, /* Filled by sdr_insert_entry() */ - .hdr.recID_MSB = 0x00, - .hdr.SDRversion = 0x51, - .hdr.rectype = TYPE_01, - .hdr.reclength = sizeof(SDR_type_01h_t) - sizeof(SDR_entry_hdr_t), - - .ownerID = 0x00, /* i2c address, -> SDR_Init */ - .ownerLUN = 0x00, /* sensor owner LUN */ - .sensornum = 0x00, /* Filled by sdr_insert_entry() */ - - /* record body bytes */ - .entityID = 0xC1, /* entity id: AMC Module */ - .entityinstance = 0x00, /* entity instance -> SDR_Init */ - .sensorinit = 0x7F, /* init: event generation + scanning enabled */ - .sensorcap = 0x56, /* capabilities: auto re-arm,*/ - .sensortype = SENSOR_TYPE_CURRENT, /* sensor type: CURRENT */ - .event_reading_type = 0x01, /* sensor reading */ - .assertion_event_mask = 0x0A80, /* assertion event mask (All upper going-high and lower going-low events) */ - .deassertion_event_mask = 0x7A80, /* deassertion event mask (All upper going-high and lower going-low events) */ - .readable_threshold_mask = 0x3F, /* LSB: readable Threshold mask: all thresholds are readable: */ - .settable_threshold_mask = 0x00, /* MSB: setable Threshold mask: none of the thresholds are setable: */ - .sensor_units_1 = 0x80, /* sensor units 1 :*/ - .sensor_units_2 = 0x05, /* sensor units 2 :*/ - .sensor_units_3 = 0x00, /* sensor units 3 :*/ - .M = 32, /* M */ - .M_tol = 0x00, /* M - Tolerance */ - .B = 0x00, /* B */ - .B_accuracy = 0x00, /* B - Accuracy */ - .acc_exp_sensor_dir = 0x00, /* Sensor direction */ - .Rexp_Bexp = 0xD0, /* R-Exp , B-Exp */ - .analog_flags = 0x00, /* Analogue characteristics flags */ - .nominal_reading = 85, /* Nominal reading */ - .normal_max = 94, /* Normal maximum - 3A */ - .normal_min = 32, /* Normal minimum - 1A */ - .sensor_max_reading = 0xFF, /* Sensor Maximum reading */ - .sensor_min_reading = 0x00, /* Sensor Minimum reading */ - .upper_nonrecover_thr = 125, /* Upper non-recoverable Threshold - 4A */ - .upper_critical_thr = 110, /* Upper critical Threshold - 3.5A */ - .upper_noncritical_thr = 94, /* Upper non critical Threshold - 3A */ - .lower_nonrecover_thr = -15, /* Lower non-recoverable Threshold - -0.1A */ - .lower_critical_thr = -10, /* Lower critical Threshold - 0.32A */ - .lower_noncritical_thr = -5, /* Lower non-critical Threshold - 1A */ - .pos_thr_hysteresis = 2, /* positive going Threshold hysteresis value */ - .neg_thr_hysteresis = 2, /* negative going Threshold hysteresis value */ - .reserved1 = 0x00, /* reserved */ - .reserved2 = 0x00, /* reserved */ - .OEM = 0x00, /* OEM reserved */ - .IDtypelen = 0xc0 | STR_SIZE(SDR_FMC1_P3V3_CURR_ID), /* 8 bit ASCII, number of bytes */ - .IDstring = SDR_FMC1_P3V3_CURR_ID /* sensor string */ -}; - -/* FMC2 12V Current */ -const SDR_type_01h_t SDR_FMC2_12V_CURR = { - .hdr.recID_LSB = 0x00, /* Filled by sdr_insert_entry() */ - .hdr.recID_MSB = 0x00, - .hdr.SDRversion = 0x51, - .hdr.rectype = TYPE_01, - .hdr.reclength = sizeof(SDR_type_01h_t) - sizeof(SDR_entry_hdr_t), - - .ownerID = 0x00, /* i2c address, -> SDR_Init */ - .ownerLUN = 0x00, /* sensor owner LUN */ - .sensornum = 0x00, /* Filled by sdr_insert_entry() */ - - /* record body bytes */ - .entityID = 0xC1, /* entity id: AMC Module */ - .entityinstance = 0x00, /* entity instance -> SDR_Init */ - .sensorinit = 0x7F, /* init: event generation + scanning enabled */ - .sensorcap = 0x56, /* capabilities: auto re-arm,*/ - .sensortype = SENSOR_TYPE_CURRENT, /* sensor type: Current */ - .event_reading_type = 0x01, /* sensor reading */ - .assertion_event_mask = 0x0A80, /* assertion event mask (All upper going-high and lower going-low events) */ - .deassertion_event_mask = 0x7A80, /* deassertion event mask (All upper going-high and lower going-low events) */ - .readable_threshold_mask = 0x3F, /* LSB: readable Threshold mask: all thresholds are readable: */ - .settable_threshold_mask = 0x00, /* MSB: setable Threshold mask: none of the thresholds are setable: */ - .sensor_units_1 = 0x80, /* sensor units 1 :*/ - .sensor_units_2 = 0x05, /* sensor units 2 :*/ - .sensor_units_3 = 0x00, /* sensor units 3 :*/ - .linearization = 0x00, /* Linearization */ - .M = 32, /* M */ - .M_tol = 0x00, /* M - Tolerance */ - .B = 0x00, /* B */ - .B_accuracy = 0x00, /* B - Accuracy */ - .acc_exp_sensor_dir = 0x02, /* Sensor direction */ - .Rexp_Bexp = 0xD0, /* R-Exp = -3 , B-Exp = 0 */ - .analog_flags = 0x03, /* Analogue characteristics flags */ - .nominal_reading = 32, /* Nominal reading = 1A */ - .normal_max = 125, /* Normal maximum */ - .normal_min = 0, /* Normal minimum */ - .sensor_max_reading = 0xFF, /* Sensor Maximum reading */ - .sensor_min_reading = 0x00, /* Sensor Minimum reading */ - .upper_nonrecover_thr = 125, /* Upper non-recoverable Threshold - 4A */ - .upper_critical_thr = 110, /* Upper critical Threshold - 3.5A */ - .upper_noncritical_thr = 95, /* Upper non critical Threshold - 3A */ - .lower_nonrecover_thr = -15, /* Lower non-recoverable Threshold - -0.1A */ - .lower_critical_thr = -10, /* Lower critical Threshold - 0.32A */ - .lower_noncritical_thr = -5, /* Lower non-critical Threshold - 0.5A */ - .pos_thr_hysteresis = 2, /* positive going Threshold hysteresis value */ - .neg_thr_hysteresis = 2, /* negative going Threshold hysteresis value */ - .reserved1 = 0x00, /* reserved */ - .reserved2 = 0x00, /* reserved */ - .OEM = 0x00, /* OEM reserved */ - .IDtypelen = 0xc0 | STR_SIZE(SDR_FMC2_12V_CURR_ID) , /* 8 bit ASCII, number of bytes */ - .IDstring = SDR_FMC2_12V_CURR_ID /* sensor string */ -}; - -/* FMC2 PVADJ Current */ -const SDR_type_01h_t SDR_FMC2_VADJ_CURR = { - .hdr.recID_LSB = 0x00, /* Filled by sdr_insert_entry() */ - .hdr.recID_MSB = 0x00, - .hdr.SDRversion = 0x51, - .hdr.rectype = TYPE_01, - .hdr.reclength = sizeof(SDR_type_01h_t) - sizeof(SDR_entry_hdr_t), - - .ownerID = 0x00, /* i2c address, -> SDR_Init */ - .ownerLUN = 0x00, /* sensor owner LUN */ - .sensornum = 0x00, /* Filled by sdr_insert_entry() */ - - /* record body bytes */ - .entityID = 0xC1, /* entity id: AMC Module */ - .entityinstance = 0x00, /* entity instance -> SDR_Init */ - .sensorinit = 0x7F, /* init: event generation + scanning enabled */ - .sensorcap = 0x56, /* capabilities: auto re-arm,*/ - .sensortype = SENSOR_TYPE_CURRENT, /* sensor type: voltage*/ - .event_reading_type = 0x01, /* sensor reading*/ - .assertion_event_mask = 0x0A80, /* assertion event mask (All upper going-high and lower going-low events) */ - .deassertion_event_mask = 0x7A80, /* deassertion event mask (All upper going-high and lower going-low events) */ - .readable_threshold_mask = 0x3F, /* LSB: readable Threshold mask: all thresholds are readable: */ - .settable_threshold_mask = 0x00, /* MSB: setable Threshold mask: none of the thresholds are setable: */ - .sensor_units_1 = 0x80, /* sensor units 1 :*/ - .sensor_units_2 = 0x05, /* sensor units 2 :*/ - .sensor_units_3 = 0x00, /* sensor units 3 :*/ - .linearization = 0x00, /* Linearization */ - .M = 32, /* M */ - .M_tol = 0x00, /* M - Tolerance */ - .B = 0x00, /* B */ - .B_accuracy = 0x00, /* B - Accuracy */ - .acc_exp_sensor_dir = 0x00, /* Sensor direction */ - .Rexp_Bexp = 0xD0, /* R-Exp , B-Exp */ - .analog_flags = 0x00, /* Analogue characteristics flags */ - .nominal_reading = 39, /* Nominal reading - 1.24A */ - .normal_max = 47, /* Normal maximum - 1.5A*/ - .normal_min = 0, /* Normal minimum - 0A */ - .sensor_max_reading = 0x7F, /* Sensor Maximum reading */ - .sensor_min_reading = 0x80, /* Sensor Minimum reading */ - .upper_nonrecover_thr = 125, /* Upper non-recoverable Threshold - 4A */ - .upper_critical_thr = 110, /* Upper critical Threshold - 3.5A */ - .upper_noncritical_thr = 94, /* Upper non critical Threshold - 3A */ - .lower_nonrecover_thr = -15, /* Lower non-recoverable Threshold - -0.32A */ - .lower_critical_thr = -10, /* Lower critical Threshold - 0A */ - .lower_noncritical_thr = -5, /* Lower non-critical Threshold - 0.16A */ - .pos_thr_hysteresis = 2, /* positive going Threshold hysteresis value */ - .neg_thr_hysteresis = 2, /* negative going Threshold hysteresis value */ - .reserved1 = 0x00, /* reserved */ - .reserved2 = 0x00, /* reserved */ - .OEM = 0x00, /* OEM reserved */ - .IDtypelen = 0xc0 | STR_SIZE(SDR_FMC2_VADJ_CURR_ID), /* 8 bit ASCII, number of bytes */ - .IDstring = SDR_FMC2_VADJ_CURR_ID /* sensor string */ -}; - -/* FMC2 P3V3 Current */ -const SDR_type_01h_t SDR_FMC2_P3V3_CURR = { - .hdr.recID_LSB = 0x00, /* Filled by sdr_insert_entry() */ - .hdr.recID_MSB = 0x00, - .hdr.SDRversion = 0x51, - .hdr.rectype = TYPE_01, - .hdr.reclength = sizeof(SDR_type_01h_t) - sizeof(SDR_entry_hdr_t), - - .ownerID = 0x00, /* i2c address, -> SDR_Init */ - .ownerLUN = 0x00, /* sensor owner LUN */ - .sensornum = 0x00, /* Filled by sdr_insert_entry() */ - - /* record body bytes */ - .entityID = 0xC1, /* entity id: AMC Module */ - .entityinstance = 0x00, /* entity instance -> SDR_Init */ - .sensorinit = 0x7F, /* init: event generation + scanning enabled */ - .sensorcap = 0x56, /* capabilities: auto re-arm */ - .sensortype = SENSOR_TYPE_CURRENT, /* sensor type: CURRENT */ - .event_reading_type = 0x01, /* sensor reading*/ - .assertion_event_mask = 0x0A80, /* assertion event mask (All upper going-high and lower going-low events) */ - .deassertion_event_mask = 0x7A80, /* deassertion event mask (All upper going-high and lower going-low events) */ - .readable_threshold_mask = 0x3F, /* LSB: readable Threshold mask: all thresholds are readable: */ - .settable_threshold_mask = 0x00, /* MSB: setable Threshold mask: none of the thresholds are setable: */ - .sensor_units_1 = 0x80, /* sensor units 1 :*/ - .sensor_units_2 = 0x05, /* sensor units 2 :*/ - .sensor_units_3 = 0x00, /* sensor units 3 :*/ - .M = 32, /* M */ - .M_tol = 0x00, /* M - Tolerance */ - .B = 0x00, /* B */ - .B_accuracy = 0x00, /* B - Accuracy */ - .acc_exp_sensor_dir = 0x00, /* Sensor direction */ - .Rexp_Bexp = 0xD0, /* R-Exp , B-Exp */ - .analog_flags = 0x00, /* Analogue characteristics flags */ - .nominal_reading = 85, /* Nominal reading */ - .normal_max = 94, /* Normal maximum - 3A */ - .normal_min = 32, /* Normal minimum - 1A */ - .sensor_max_reading = 0xFF, /* Sensor Maximum reading */ - .sensor_min_reading = 0x00, /* Sensor Minimum reading */ - .upper_nonrecover_thr = 125, /* Upper non-recoverable Threshold - 4A */ - .upper_critical_thr = 110, /* Upper critical Threshold - 3.5A */ - .upper_noncritical_thr = 94, /* Upper non critical Threshold - 3A */ - .lower_nonrecover_thr = -15, /* Lower non-recoverable Threshold - -0.1A */ - .lower_critical_thr = -10, /* Lower critical Threshold - 0.32A */ - .lower_noncritical_thr = -5, /* Lower non-critical Threshold - 1A */ - .pos_thr_hysteresis = 2, /* positive going Threshold hysteresis value */ - .neg_thr_hysteresis = 2, /* negative going Threshold hysteresis value */ - .reserved1 = 0x00, /* reserved */ - .reserved2 = 0x00, /* reserved */ - .OEM = 0x00, /* OEM reserved */ - .IDtypelen = 0xc0 | STR_SIZE(SDR_FMC2_P3V3_CURR_ID), /* 8 bit ASCII, number of bytes */ - .IDstring = SDR_FMC2_P3V3_CURR_ID /* sensor string */ -}; -#endif - -#ifdef MODULE_LM75 -/* LM75 SDR List */ -const SDR_type_01h_t SDR_LM75_uC = { - .hdr.recID_LSB = 0x00, /* Filled by sdr_insert_entry() */ - .hdr.recID_MSB = 0x00, - .hdr.SDRversion = 0x51, - .hdr.rectype = TYPE_01, - .hdr.reclength = sizeof(SDR_type_01h_t) - sizeof(SDR_entry_hdr_t), - - .ownerID = 0x00, /* i2c address, -> SDR_Init */ - .ownerLUN = 0x00, /* sensor owner LUN */ - .sensornum = 0x00, /* Filled by sdr_insert_entry() */ - - /* record body bytes */ - .entityID = 0xC1, /* entity id: AMC Module */ - .entityinstance = 0x00, /* entity instance -> SDR_Init */ - .sensorinit = 0x7F, /* init: event generation + scanning enabled */ - .sensorcap = 0x56, /* capabilities: auto re-arm,*/ - .sensortype = SENSOR_TYPE_TEMPERATURE, /* sensor type */ - .event_reading_type = 0x01, /* sensor reading*/ - .assertion_event_mask = 0x7A95, /* assertion event mask (All upper going-high and lower going-low events) */ - .deassertion_event_mask = 0x7A95, /* deassertion event mask (All upper going-high and lower going-low events) */ - .readable_threshold_mask = 0x3F, /* LSB: readable Threshold mask: all thresholds are readable: */ - .settable_threshold_mask = 0x00, /* MSB: setable Threshold mask: none of the thresholds are setable: */ - .sensor_units_1 = 0x00, /* sensor units 1 :*/ - .sensor_units_2 = 0x01, /* sensor units 2 :*/ - .sensor_units_3 = 0x00, /* sensor units 3 :*/ - .linearization = 0x00, /* Linearization */ - .M = 5, /* M */ - .M_tol = 0x00, /* M - Tolerance */ - .B = 0x00, /* B */ - .B_accuracy = 0x00, /* B - Accuracy */ - .acc_exp_sensor_dir = 0x00, /* Sensor direction */ - .Rexp_Bexp = 0xF0, /* R-Exp , B-Exp */ - .analog_flags = 0x03, /* Analogue characteristics flags */ - .nominal_reading = (20 << 1), /* Nominal reading */ - .normal_max = (50 << 1), /* Normal maximum */ - .normal_min = (10 << 1), /* Normal minimum */ - .sensor_max_reading = 0xFF, /* Sensor Maximum reading */ - .sensor_min_reading = 0x00, /* Sensor Minimum reading */ - .upper_nonrecover_thr = (80 << 1), /* Upper non-recoverable Threshold */ - .upper_critical_thr = (75 << 1), /* Upper critical Threshold */ - .upper_noncritical_thr = (65 << 1), /* Upper non critical Threshold */ - .lower_nonrecover_thr = (0 << 1), /* Lower non-recoverable Threshold */ - .lower_critical_thr = (5 << 1), /* Lower critical Threshold */ - .lower_noncritical_thr = (10 << 1), /* Lower non-critical Threshold */ - .pos_thr_hysteresis = 2, /* positive going Threshold hysteresis value */ - .neg_thr_hysteresis = 2, /* negative going Threshold hysteresis value */ - .reserved1 = 0x00, /* reserved */ - .reserved2 = 0x00, /* reserved */ - .OEM = 0x00, /* OEM reserved */ - .IDtypelen = 0xc0 | STR_SIZE("TEMP UC"), /* 8 bit ASCII, number of bytes */ - .IDstring = "TEMP UC" /* sensor string */ -}; - -const SDR_type_01h_t SDR_LM75_ADN4604 = { - .hdr.recID_LSB = 0x00, /* Filled by sdr_insert_entry() */ - .hdr.recID_MSB = 0x00, - .hdr.SDRversion = 0x51, - .hdr.rectype = TYPE_01, - .hdr.reclength = sizeof(SDR_type_01h_t) - sizeof(SDR_entry_hdr_t), - - .ownerID = 0x00, /* i2c address, -> SDR_Init */ - .ownerLUN = 0x00, /* sensor owner LUN */ - .sensornum = 0x00, /* Filled by sdr_insert_entry() */ - - /* record body bytes */ - .entityID = 0xC1, /* entity id: AMC Module */ - .entityinstance = 0x00, /* entity instance -> SDR_Init */ - .sensorinit = 0x7F, /* init: event generation + scanning enabled */ - .sensorcap = 0x56, /* capabilities: auto re-arm,*/ - .sensortype = SENSOR_TYPE_TEMPERATURE, /* sensor type */ - .event_reading_type = 0x01, /* sensor reading*/ - .assertion_event_mask = 0x7A95, /* assertion event mask (All upper going-high and lower going-low events) */ - .deassertion_event_mask = 0x7A95, /* deassertion event mask (All upper going-high and lower going-low events) */ - .readable_threshold_mask = 0x3F, /* LSB: readable Threshold mask: all thresholds are readable: */ - .settable_threshold_mask = 0x00, /* MSB: setable Threshold mask: none of the thresholds are setable: */ - .sensor_units_1 = 0x00, /* sensor units 1 :*/ - .sensor_units_2 = 0x01, /* sensor units 2 :*/ - .sensor_units_3 = 0x00, /* sensor units 3 :*/ - .linearization = 0x00, /* Linearization */ - .M = 5, /* M */ - .M_tol = 0x00, /* M - Tolerance */ - .B = 0x00, /* B */ - .B_accuracy = 0x00, /* B - Accuracy */ - .acc_exp_sensor_dir = 0x00, /* Sensor direction */ - .Rexp_Bexp = 0xF0, /* R-Exp , B-Exp */ - .analog_flags = 0x03, /* Analogue characteristics flags */ - .nominal_reading = (20 << 1), /* Nominal reading */ - .normal_max = (50 << 1), /* Normal maximum */ - .normal_min = (10 << 1), /* Normal minimum */ - .sensor_max_reading = 0xFF, /* Sensor Maximum reading */ - .sensor_min_reading = 0x00, /* Sensor Minimum reading */ - .upper_nonrecover_thr = (80 << 1), /* Upper non-recoverable Threshold */ - .upper_critical_thr = (75 << 1), /* Upper critical Threshold */ - .upper_noncritical_thr = (65 << 1), /* Upper non critical Threshold */ - .lower_nonrecover_thr = (0 << 1), /* Lower non-recoverable Threshold */ - .lower_critical_thr = (5 << 1), /* Lower critical Threshold */ - .lower_noncritical_thr = (10 << 1), /* Lower non-critical Threshold */ - .pos_thr_hysteresis = 2, /* positive going Threshold hysteresis value */ - .neg_thr_hysteresis = 2, /* negative going Threshold hysteresis value */ - .reserved1 = 0x00, /* reserved */ - .reserved2 = 0x00, /* reserved */ - .OEM = 0x00, /* OEM reserved */ - .IDtypelen = 0xc0 | STR_SIZE("TEMP CLK SWITCH"), /* 8 bit ASCII, number of bytes */ - .IDstring = "TEMP CLK SWITCH" /* sensor string */ -}; - -const SDR_type_01h_t SDR_LM75_DCDC = { - .hdr.recID_LSB = 0x00, /* Filled by sdr_insert_entry() */ - .hdr.recID_MSB = 0x00, - .hdr.SDRversion = 0x51, - .hdr.rectype = TYPE_01, - .hdr.reclength = sizeof(SDR_type_01h_t) - sizeof(SDR_entry_hdr_t), - - .ownerID = 0x00, /* i2c address, -> SDR_Init */ - .ownerLUN = 0x00, /* sensor owner LUN */ - .sensornum = 0x00, /* Filled by sdr_insert_entry() */ - - /* record body bytes */ - .entityID = 0xC1, /* entity id: AMC Module */ - .entityinstance = 0x00, /* entity instance -> SDR_Init */ - .sensorinit = 0x7F, /* init: event generation + scanning enabled */ - .sensorcap = 0x56, /* capabilities: auto re-arm,*/ - .sensortype = SENSOR_TYPE_TEMPERATURE, /* sensor type */ - .event_reading_type = 0x01, /* sensor reading*/ - .assertion_event_mask = 0x7A95, /* assertion event mask (All upper going-high and lower going-low events) */ - .deassertion_event_mask = 0x7A95, /* deassertion event mask (All upper going-high and lower going-low events) */ - .readable_threshold_mask = 0x3F, /* LSB: readable Threshold mask: all thresholds are readable: */ - .settable_threshold_mask = 0x00, /* MSB: setable Threshold mask: none of the thresholds are setable: */ - .sensor_units_1 = 0x00, /* sensor units 1 :*/ - .sensor_units_2 = 0x01, /* sensor units 2 :*/ - .sensor_units_3 = 0x00, /* sensor units 3 :*/ - .linearization = 0x00, /* Linearization */ - .M = 5, /* M */ - .M_tol = 0x00, /* M - Tolerance */ - .B = 0x00, /* B */ - .B_accuracy = 0x00, /* B - Accuracy */ - .acc_exp_sensor_dir = 0x00, /* Sensor direction */ - .Rexp_Bexp = 0xF0, /* R-Exp , B-Exp */ - .analog_flags = 0x03, /* Analogue characteristics flags */ - .nominal_reading = (20 << 1), /* Nominal reading */ - .normal_max = (50 << 1), /* Normal maximum */ - .normal_min = (10 << 1), /* Normal minimum */ - .sensor_max_reading = 0xFF, /* Sensor Maximum reading */ - .sensor_min_reading = 0x00, /* Sensor Minimum reading */ - .upper_nonrecover_thr = (80 << 1), /* Upper non-recoverable Threshold */ - .upper_critical_thr = (75 << 1), /* Upper critical Threshold */ - .upper_noncritical_thr = (65 << 1), /* Upper non critical Threshold */ - .lower_nonrecover_thr = (0 << 1), /* Lower non-recoverable Threshold */ - .lower_critical_thr = (5 << 1), /* Lower critical Threshold */ - .lower_noncritical_thr = (10 << 1), /* Lower non-critical Threshold */ - .pos_thr_hysteresis = 2, /* positive going Threshold hysteresis value */ - .neg_thr_hysteresis = 2, /* negative going Threshold hysteresis value */ - .reserved1 = 0x00, /* reserved */ - .reserved2 = 0x00, /* reserved */ - .OEM = 0x00, /* OEM reserved */ - .IDtypelen = 0xc0 | STR_SIZE("TEMP DCDC"), /* 8 bit ASCII, number of bytes */ - .IDstring = "TEMP DCDC" /* sensor string */ -}; - -const SDR_type_01h_t SDR_LM75_RAM = { - .hdr.recID_LSB = 0x00, /* Filled by sdr_insert_entry() */ - .hdr.recID_MSB = 0x00, - .hdr.SDRversion = 0x51, - .hdr.rectype = TYPE_01, - .hdr.reclength = sizeof(SDR_type_01h_t) - sizeof(SDR_entry_hdr_t), - - .ownerID = 0x00, /* i2c address, -> SDR_Init */ - .ownerLUN = 0x00, /* sensor owner LUN */ - .sensornum = 0x00, /* Filled by sdr_insert_entry() */ - - /* record body bytes */ - .entityID = 0xC1, /* entity id: AMC Module */ - .entityinstance = 0x00, /* entity instance -> SDR_Init */ - .sensorinit = 0x7F, /* init: event generation + scanning enabled */ - .sensorcap = 0x56, /* capabilities: auto re-arm,*/ - .sensortype = SENSOR_TYPE_TEMPERATURE, /* sensor type */ - .event_reading_type = 0x01, /* sensor reading*/ - .assertion_event_mask = 0x7A95, /* assertion event mask (All upper going-high and lower going-low events) */ - .deassertion_event_mask = 0x7A95, /* deassertion event mask (All upper going-high and lower going-low events) */ - .readable_threshold_mask = 0x3F, /* LSB: readable Threshold mask: all thresholds are readable: */ - .settable_threshold_mask = 0x00, /* MSB: setable Threshold mask: none of the thresholds are setable: */ - .sensor_units_1 = 0x00, /* sensor units 1 :*/ - .sensor_units_2 = 0x01, /* sensor units 2 :*/ - .sensor_units_3 = 0x00, /* sensor units 3 :*/ - .linearization = 0x00, /* Linearization */ - .M = 5, /* M */ - .M_tol = 0x00, /* M - Tolerance */ - .B = 0x00, /* B */ - .B_accuracy = 0x00, /* B - Accuracy */ - .acc_exp_sensor_dir = 0x00, /* Sensor direction */ - .Rexp_Bexp = 0xF0, /* R-Exp , B-Exp */ - .analog_flags = 0x03, /* Analogue characteristics flags */ - .nominal_reading = (20 << 1), /* Nominal reading */ - .normal_max = (50 << 1), /* Normal maximum */ - .normal_min = (10 << 1), /* Normal minimum */ - .sensor_max_reading = 0xFF, /* Sensor Maximum reading */ - .sensor_min_reading = 0x00, /* Sensor Minimum reading */ - .upper_nonrecover_thr = (80 << 1), /* Upper non-recoverable Threshold */ - .upper_critical_thr = (75 << 1), /* Upper critical Threshold */ - .upper_noncritical_thr = (65 << 1), /* Upper non critical Threshold */ - .lower_nonrecover_thr = (0 << 1), /* Lower non-recoverable Threshold */ - .lower_critical_thr = (5 << 1), /* Lower critical Threshold */ - .lower_noncritical_thr = (10 << 1), /* Lower non-critical Threshold */ - .pos_thr_hysteresis = 2, /* positive going Threshold hysteresis value */ - .neg_thr_hysteresis = 2, /* negative going Threshold hysteresis value */ - .reserved1 = 0x00, /* reserved */ - .reserved2 = 0x00, /* reserved */ - .OEM = 0x00, /* OEM reserved */ - .IDtypelen = 0xc0 | STR_SIZE("TEMP RAM"), /* 8 bit ASCII, number of bytes */ - .IDstring = "TEMP RAM" /* sensor string */ -}; -#endif - -#ifdef MODULE_MAX6642 -const SDR_type_01h_t SDR_MAX6642_FPGA = { - .hdr.recID_LSB = 0x00, /* Filled by sdr_insert_entry() */ - .hdr.recID_MSB = 0x00, - .hdr.SDRversion = 0x51, - .hdr.rectype = TYPE_01, - .hdr.reclength = sizeof(SDR_type_01h_t) - sizeof(SDR_entry_hdr_t), - - .ownerID = 0x00, /* i2c address, -> SDR_Init */ - .ownerLUN = 0x00, /* sensor owner LUN */ - .sensornum = 0x00, /* Filled by sdr_insert_entry() */ - - /* record body bytes */ - .entityID = 0xC1, /* entity id: AMC Module */ - .entityinstance = 0x00, /* entity instance -> SDR_Init */ - .sensorinit = 0x7F, /* init: event generation + scanning enabled */ - .sensorcap = 0x56, /* capabilities: auto re-arm,*/ - .sensortype = SENSOR_TYPE_TEMPERATURE, /* sensor type */ - .event_reading_type = 0x01, /* sensor reading*/ - .assertion_event_mask = 0x7A95, /* assertion event mask (All upper going-high and lower going-low events) */ - .deassertion_event_mask = 0x7A95, /* deassertion event mask (All upper going-high and lower going-low events) */ - .readable_threshold_mask = 0x3F, /* LSB: readable Threshold mask: all thresholds are readable: */ - .settable_threshold_mask = 0x0, /* MSB: setable Threshold mask: none of the thresholds are setable: */ - .sensor_units_1 = 0x00, /* sensor units 1 :*/ - .sensor_units_2 = 0x01, /* sensor units 2 :*/ - .sensor_units_3 = 0x00, /* sensor units 3 :*/ - .linearization = 0x00, /* Linearization */ - .M = 1, /* M */ - .M_tol = 0x00, /* M - Tolerance */ - .B = 0x00, /* B */ - .B_accuracy = 0x00, /* B - Accuracy */ - .acc_exp_sensor_dir = 0x00, /* Sensor direction */ - .Rexp_Bexp = 0x00, /* R-Exp , B-Exp */ - .analog_flags = 0x03, /* Analogue characteristics flags */ - .nominal_reading = (20 << 1), /* Nominal reading */ - .normal_max = (50 << 1), /* Normal maximum */ - .normal_min = (10 << 1), /* Normal minimum */ - .sensor_max_reading = 0xFF, /* Sensor Maximum reading */ - .sensor_min_reading = 0x00, /* Sensor Minimum reading */ - .upper_nonrecover_thr = (80 << 1), /* Upper non-recoverable Threshold */ - .upper_critical_thr = (75 << 1), /* Upper critical Threshold */ - .upper_noncritical_thr = (65 << 1), /* Upper non critical Threshold */ - .lower_nonrecover_thr = (0 << 1), /* Lower non-recoverable Threshold */ - .lower_critical_thr = (5 << 1), /* Lower critical Threshold */ - .lower_noncritical_thr = (10 << 1), /* Lower non-critical Threshold */ - .pos_thr_hysteresis = 2, /* positive going Threshold hysteresis value */ - .neg_thr_hysteresis = 2, /* negative going Threshold hysteresis value */ - .reserved1 = 0x00, /* reserved */ - .reserved2 = 0x00, /* reserved */ - .OEM = 0x00, /* OEM reserved */ - .IDtypelen = 0xc0 | STR_SIZE("TEMP FPGA"), /* 8 bit ASCII, number of bytes */ - .IDstring = "TEMP FPGA" /* sensor string */ -}; -#endif - -void amc_sdr_init( void ) -{ - /* Hotswap Sensor */ - sdr_insert_entry( TYPE_02, (void *) &SDR_HOTSWAP_AMC, &vTaskHotSwap_Handle, 0, 0 ); - - /* INA220 sensors */ -#ifdef MODULE_INA220_VOLTAGE - /* FMC1 Voltage */ - sdr_insert_entry( TYPE_01, (void *) &SDR_FMC1_12V, &vTaskINA220_Handle, FMC1_12V_DEVID, CHIP_ID_INA_5 ); - sdr_insert_entry( TYPE_01, (void *) &SDR_FMC1_VADJ, &vTaskINA220_Handle, FMC1_VADJ_DEVID, CHIP_ID_INA_2 ); - sdr_insert_entry( TYPE_01, (void *) &SDR_FMC1_P3V3, &vTaskINA220_Handle, FMC1_P3V3_DEVID, CHIP_ID_INA_4 ); - - /* FMC2 Voltage */ - sdr_insert_entry( TYPE_01, (void *) &SDR_FMC2_12V, &vTaskINA220_Handle, FMC2_12V_DEVID, CHIP_ID_INA_0 ); - sdr_insert_entry( TYPE_01, (void *) &SDR_FMC2_VADJ, &vTaskINA220_Handle, FMC2_VADJ_DEVID, CHIP_ID_INA_1 ); - sdr_insert_entry( TYPE_01, (void *) &SDR_FMC2_P3V3, &vTaskINA220_Handle, FMC2_P3V3_DEVID, CHIP_ID_INA_3 ); -#endif - -#ifdef MODULE_INA220_CURRENT - /* FMC1 Current */ - sdr_insert_entry( TYPE_01, (void *) &SDR_FMC1_12V_CURR, &vTaskINA220_Handle, FMC1_12V_CURR_DEVID, CHIP_ID_INA_5 ); - sdr_insert_entry( TYPE_01, (void *) &SDR_FMC1_VADJ_CURR, &vTaskINA220_Handle, FMC1_VADJ_CURR_DEVID, CHIP_ID_INA_2 ); - sdr_insert_entry( TYPE_01, (void *) &SDR_FMC1_P3V3_CURR, &vTaskINA220_Handle, FMC1_P3V3_CURR_DEVID, CHIP_ID_INA_4 ); - - /* FMC2 Current */ - sdr_insert_entry( TYPE_01, (void *) &SDR_FMC2_12V_CURR, &vTaskINA220_Handle, FMC2_12V_CURR_DEVID, CHIP_ID_INA_0 ); - sdr_insert_entry( TYPE_01, (void *) &SDR_FMC2_VADJ_CURR, &vTaskINA220_Handle, FMC2_VADJ_CURR_DEVID, CHIP_ID_INA_1 ); - sdr_insert_entry( TYPE_01, (void *) &SDR_FMC2_P3V3_CURR, &vTaskINA220_Handle, FMC2_P3V3_CURR_DEVID, CHIP_ID_INA_3 ); -#endif - -#ifdef MODULE_MAX6642 - /* FPGA Die Temperature */ - sdr_insert_entry( TYPE_01, (void *) &SDR_MAX6642_FPGA, &vTaskMAX6642_Handle, 0, CHIP_ID_MAX6642 ); -#endif - -#ifdef MODULE_LM75 - /* Board Temperature */ - sdr_insert_entry( TYPE_01, (void *) &SDR_LM75_uC, &vTaskLM75_Handle, 0, CHIP_ID_LM75AIM_0 ); - sdr_insert_entry( TYPE_01, (void *) &SDR_LM75_ADN4604, &vTaskLM75_Handle, 0, CHIP_ID_LM75AIM_1 ); - sdr_insert_entry( TYPE_01, (void *) &SDR_LM75_DCDC, &vTaskLM75_Handle, 0, CHIP_ID_LM75AIM_2 ); - sdr_insert_entry( TYPE_01, (void *) &SDR_LM75_RAM, &vTaskLM75_Handle, 0, CHIP_ID_LM75AIM_3 ); -#endif -} diff --git a/port/board/afc-bpm/v3_1/user_amc_fru.h b/port/board/afc-bpm/v3_1/user_amc_fru.h deleted file mode 100644 index 8be4510ec..000000000 --- a/port/board/afc-bpm/v3_1/user_amc_fru.h +++ /dev/null @@ -1,72 +0,0 @@ -/* - * openMMC -- Open Source modular IPM Controller firmware - * - * Copyright (C) 2015 Julian Mendez - * Copyright (C) 2015-2016 Henrique Silva - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - * - * @license GPL-3.0+ - */ - -#include "fru_editor.h" - -/********************************************* - * Common defines - *********************************************/ -#define AMC_LANG_CODE 0 -#define AMC_FRU_FILE_ID "AFCFRU" //Allows knowing the source of the FRU present in the memory - -/********************************************* - * Board information area - *********************************************/ -#define AMC_BOARD_MANUFACTURING_TIME 10463040 /* Amount of minutes since 0:00 1/1/96 */ -#define AMC_BOARD_MANUFACTURER "Creotech" -#define AMC_BOARD_NAME "AMC-FMC-Carrier" -#define AMC_BOARD_SN "CNxxxxx" -#define AMC_BOARD_PN "AFC" - -/********************************************* - * Product information area - *********************************************/ -#define AMC_PRODUCT_MANUFACTURER "LNLS" -#define AMC_PRODUCT_NAME "AFC BPM" -#define AMC_PRODUCT_PN "AFC:3.1" -#define AMC_PRODUCT_VERSION "3.1" -#define AMC_PRODUCT_SN "CNxxxxx" -#define AMC_PRODUCT_ASSET_TAG "Generic FRU" - -/********************************************* - * AMC: Point to point connectivity record - *********************************************/ -#define AMC_POINT_TO_POINT_RECORD_LIST \ - GENERIC_POINT_TO_POINT_RECORD(0, PORT(4), PORT(5), PORT(6), PORT(7), PCIE, GEN1_NO_SSC, MATCHES_01) - -/********************************************* - * AMC: Point to point clock record - *********************************************/ -/* Example: - DIRECT_CLOCK_CONNECTION(CLOCK_ID, ACTIVATION, PLL_USE, SOURCE/RECEIVER, CLOCK_FAMILY, ACCURACY, FREQUENCY, MIN FREQUENCY, MAX FREQUENCY) */ -#define AMC_CLOCK_CONFIGURATION_LIST \ - DIRECT_CLOCK_CONNECTION(FCLKA, CIPMC, NO_PLL, RECEIVER, PCI_RESERVED, 0, MHz(100), MHz(99), MHz(101)) \ - DIRECT_CLOCK_CONNECTION(TCLKA, APP, NO_PLL, RECEIVER, UNSPEC_FAMILY, 0, KHz(62500), KHz(62450), KHz(62550)) -/********************************************** - * PICMG: Module current record - **********************************************/ -#define AMC_MODULE_CURRENT_RECORD current_in_ma(4000) - -/********************************************* - * RTM Compatibility Record - *********************************************/ -#define AMC_COMPATIBILITY_CODE 0x11223344 diff --git a/port/board/afc-timing/i2c_mapping.c b/port/board/afc-timing/i2c_mapping.c deleted file mode 100644 index e979a3cdf..000000000 --- a/port/board/afc-timing/i2c_mapping.c +++ /dev/null @@ -1,91 +0,0 @@ -#include "i2c.h" -#include "i2c_mapping.h" -#include "port.h" - -i2c_mux_state_t i2c_mux[I2C_MUX_CNT] = { - { I2C1, -1, 0 }, - { I2C2, -1, 0 } -}; - -i2c_bus_mapping_t i2c_bus_map[I2C_BUS_CNT] = { - [I2C_BUS_UNKNOWN_ID] = { I2C1, -1, 0 }, - [I2C_BUS_FMC1_ID] = { I2C2, 0, 1 }, - [I2C_BUS_FMC2_ID] = { I2C2, 1, 1 }, - [I2C_BUS_CPU_ID] = { I2C1, -1, 1 }, - [I2C_BUS_RTM_ID] = { I2C2, 3, 1 }, - [I2C_BUS_CLOCK_ID] = { I2C2, 2, 1 }, - [I2C_BUS_FPGA_ID] = { I2C2, -1, 1 }, -}; - -i2c_chip_mapping_t i2c_chip_map[I2C_CHIP_CNT] = { - [CHIP_ID_MUX] = { I2C_BUS_FPGA_ID, 0x70 }, - [CHIP_ID_LM75AIM_0] = { I2C_BUS_CPU_ID, 0x4C }, - [CHIP_ID_LM75AIM_1] = { I2C_BUS_CPU_ID, 0x4D }, - [CHIP_ID_LM75AIM_2] = { I2C_BUS_CPU_ID, 0x4E }, - [CHIP_ID_LM75AIM_3] = { I2C_BUS_CPU_ID, 0x4F }, - [CHIP_ID_MAX6642] = { I2C_BUS_CPU_ID, 0x48 }, - - [CHIP_ID_RTC] = { I2C_BUS_CPU_ID, 0x9F }, - [CHIP_ID_RTC_EEPROM] = { I2C_BUS_CPU_ID, 0x57 }, - [CHIP_ID_EEPROM] = { I2C_BUS_CPU_ID, 0x50 }, - [CHIP_ID_EEPROM_ID] = { I2C_BUS_CPU_ID, 0x58 }, - - [CHIP_ID_INA_0] = { I2C_BUS_CPU_ID, 0x40 }, - [CHIP_ID_INA_1] = { I2C_BUS_CPU_ID, 0x41 }, - [CHIP_ID_INA_2] = { I2C_BUS_CPU_ID, 0x42 }, - [CHIP_ID_INA_3] = { I2C_BUS_CPU_ID, 0x43 }, - [CHIP_ID_INA_4] = { I2C_BUS_CPU_ID, 0x44 }, - [CHIP_ID_INA_5] = { I2C_BUS_CPU_ID, 0x45 }, - - [CHIP_ID_ADN] = { I2C_BUS_CPU_ID, 0x4B }, - [CHIP_ID_SI57x] = { I2C_BUS_CLOCK_ID, 0x30 }, - - [CHIP_ID_FMC1_EEPROM] = { I2C_BUS_FMC1_ID, 0x50 }, - [CHIP_ID_FMC1_LM75_0] = { I2C_BUS_FMC1_ID, 0x48 }, - [CHIP_ID_FMC1_LM75_1] = { I2C_BUS_FMC1_ID, 0x49 }, - - [CHIP_ID_FMC2_EEPROM] = { I2C_BUS_FMC2_ID, 0x52 }, - [CHIP_ID_FMC2_LM75_0] = { I2C_BUS_FMC2_ID, 0x48 }, - [CHIP_ID_FMC2_LM75_1] = { I2C_BUS_FMC2_ID, 0x49 }, - - [CHIP_ID_RTM_PCA9554] = { I2C_BUS_RTM_ID, 0x20 }, - [CHIP_ID_RTM_EEPROM] = { I2C_BUS_RTM_ID, 0x50 }, - [CHIP_ID_RTM_LM75_0] = { I2C_BUS_RTM_ID, 0x48 }, - [CHIP_ID_RTM_LM75_1] = { I2C_BUS_RTM_ID, 0x49 }, -}; - -bool i2c_set_mux_bus( uint8_t bus_id, i2c_mux_state_t *i2c_mux, int8_t new_state ) -{ - portENABLE_INTERRUPTS(); - - if (i2c_mux->i2c_interface == i2c_bus_map[i2c_chip_map[CHIP_ID_MUX].bus_id].i2c_interface) { - /* Include enable bit (fourth bit) on channel selection byte */ - uint8_t pca_channel = new_state | (1 << 3); - - /* Select desired channel in the I2C switch */ - if( xI2CMasterWrite( i2c_bus_map[i2c_chip_map[CHIP_ID_MUX].bus_id].i2c_interface, i2c_chip_map[CHIP_ID_MUX].i2c_address, &pca_channel, 1 ) != 1 ) { - /* We failed to configure the I2C Mux, release the semaphore */ - xSemaphoreGive( i2c_mux->semaphore ); - return false; - } - } - - i2c_mux->state = new_state; - return true; -} - -uint8_t i2c_get_mux_bus( uint8_t bus_id, i2c_mux_state_t *i2c_mux ) -{ - if (i2c_mux->i2c_interface == i2c_bus_map[i2c_chip_map[CHIP_ID_MUX].bus_id].i2c_interface) { - /* Include enable bit (fourth bit) on channel selection byte */ - uint8_t pca_channel; - - portENABLE_INTERRUPTS(); - /* Read bus state (other master on the bus may have switched it */ - xI2CMasterRead( i2c_bus_map[i2c_chip_map[CHIP_ID_MUX].bus_id].i2c_interface, i2c_chip_map[CHIP_ID_MUX].i2c_address, &pca_channel, 1 ); - - return (pca_channel & 0x07); - } else { - return i2c_mux->state; - } -} diff --git a/port/board/afc-timing/CMakeLists.txt b/port/board/afc-v3/CMakeLists.txt similarity index 100% rename from port/board/afc-timing/CMakeLists.txt rename to port/board/afc-v3/CMakeLists.txt diff --git a/port/board/afc-bpm/v3_1/i2c_mapping.c b/port/board/afc-v3/i2c_mapping.c similarity index 100% rename from port/board/afc-bpm/v3_1/i2c_mapping.c rename to port/board/afc-v3/i2c_mapping.c diff --git a/port/board/afc-timing/i2c_mapping.h b/port/board/afc-v3/i2c_mapping.h similarity index 100% rename from port/board/afc-timing/i2c_mapping.h rename to port/board/afc-v3/i2c_mapping.h diff --git a/port/board/afc-timing/ipmi_oem.c b/port/board/afc-v3/ipmi_oem.c similarity index 100% rename from port/board/afc-timing/ipmi_oem.c rename to port/board/afc-v3/ipmi_oem.c diff --git a/port/board/afc-timing/ipmi_oem.h b/port/board/afc-v3/ipmi_oem.h similarity index 100% rename from port/board/afc-timing/ipmi_oem.h rename to port/board/afc-v3/ipmi_oem.h diff --git a/port/board/afc-timing/payload.c b/port/board/afc-v3/payload.c similarity index 100% rename from port/board/afc-timing/payload.c rename to port/board/afc-v3/payload.c diff --git a/port/board/afc-timing/payload.h b/port/board/afc-v3/payload.h similarity index 100% rename from port/board/afc-timing/payload.h rename to port/board/afc-v3/payload.h diff --git a/port/board/afc-timing/pin_mapping.h b/port/board/afc-v3/pin_mapping.h similarity index 100% rename from port/board/afc-timing/pin_mapping.h rename to port/board/afc-v3/pin_mapping.h diff --git a/port/board/afc-timing/sdr_list.c b/port/board/afc-v3/sdr_list.c similarity index 100% rename from port/board/afc-timing/sdr_list.c rename to port/board/afc-v3/sdr_list.c diff --git a/port/board/afc-timing/user_amc_fru.h b/port/board/afc-v3/user_amc_fru.h similarity index 100% rename from port/board/afc-timing/user_amc_fru.h rename to port/board/afc-v3/user_amc_fru.h diff --git a/scripts/make-release.sh b/scripts/make-release.sh index 93fe66124..c10e0a756 100755 --- a/scripts/make-release.sh +++ b/scripts/make-release.sh @@ -1,8 +1,7 @@ #!/bin/sh openmmc_root=$(realpath ..) -afc_timing_build_dir="${openmmc_root}/build/releases/afcv3.1-timing" -afc_bpm_build_dir="${openmmc_root}/build/releases/afcv3.1-bpm" +afc_v3.1_build_dir="${openmmc_root}/build/releases/afcv3.1" afc_v4_build_dir="${openmmc_root}/build/releases/afcv4" bin_dir="${openmmc_root}/build/releases/binaries" tag=$(git describe --tags) @@ -11,33 +10,24 @@ set -e rm -rf "${openmmc_root}/build/releases/" mkdir -p "$bin_dir" -mkdir -p "$afc_timing_build_dir" -mkdir -p "$afc_bpm_build_dir" +mkdir -p "$afc_v3.1_build_dir" mkdir -p "$afc_v4_build_dir" -cd "$afc_timing_build_dir" -cmake "$openmmc_root" -DBOARD=afc-timing -DBOARD_RTM=8sfp -DCMAKE_BUILD_TYPE=RelWithDebInfo -DDISABLE_WATCHDOG=OFF -make - -cd "$afc_bpm_build_dir" -cmake "$openmmc_root" -DBOARD=afc-bpm -DVERSION=3.1 -DCMAKE_BUILD_TYPE=RelWithDebInfo -DDISABLE_WATCHDOG=OFF +cd "$afc_v3.1_build_dir" +cmake "$openmmc_root" -DBOARD=afc -DVERSION=3.1 -DCMAKE_BUILD_TYPE=RelWithDebInfo -DDISABLE_WATCHDOG=OFF make cd "$afc_v4_build_dir" -cmake "$openmmc_root" -DBOARD=afc-v4 -DCMAKE_BUILD_TYPE=RelWithDebInfo -DDISABLE_WATCHDOG=OFF +cmake "$openmmc_root" -DBOARD=afc -DVERSION=4.0 -DCMAKE_BUILD_TYPE=RelWithDebInfo -DDISABLE_WATCHDOG=OFF make -cp "${afc_timing_build_dir}/out/openMMC.elf" "${bin_dir}/openMMC-afcv3.1-timing-${tag}.elf" -cp "${afc_timing_build_dir}/out/openMMC.bin" "${bin_dir}/openMMC-afcv3.1-timing-${tag}.bin" -cp "${afc_timing_build_dir}/out/openMMC.hpm" "${bin_dir}/openMMC-afcv3.1-timing-${tag}.hpm" - -cp "${afc_bpm_build_dir}/out/openMMC.elf" "${bin_dir}/openMMC-afcv3.1-bpm-${tag}.elf" -cp "${afc_bpm_build_dir}/out/openMMC.bin" "${bin_dir}/openMMC-afcv3.1-bpm-${tag}.bin" -cp "${afc_bpm_build_dir}/out/openMMC.hpm" "${bin_dir}/openMMC-afcv3.1-bpm-${tag}.hpm" +cp "${afc_v3.1_build_dir}/out/openMMC.elf" "${bin_dir}/openMMC-afcv3.1-${tag}.elf" +cp "${afc_v3.1_build_dir}/out/openMMC.bin" "${bin_dir}/openMMC-afcv3.1-${tag}.bin" +cp "${afc_v3.1_build_dir}/out/openMMC.hpm" "${bin_dir}/openMMC-afcv3.1-${tag}.hpm" -cp "${afc_bpm_build_dir}/out/newboot.elf" "${bin_dir}/newboot-afcv3.1-${tag}.elf" -cp "${afc_bpm_build_dir}/out/newboot.bin" "${bin_dir}/newboot-afcv3.1-${tag}.bin" -cp "${afc_bpm_build_dir}/out/newboot.hpm" "${bin_dir}/newboot-afcv3.1-${tag}.hpm" +cp "${afc_v3.1_build_dir}/out/newboot.elf" "${bin_dir}/newboot-afcv3.1-${tag}.elf" +cp "${afc_v3.1_build_dir}/out/newboot.bin" "${bin_dir}/newboot-afcv3.1-${tag}.bin" +cp "${afc_v3.1_build_dir}/out/newboot.hpm" "${bin_dir}/newboot-afcv3.1-${tag}.hpm" cp "${afc_v4_build_dir}/out/openMMC.elf" "${bin_dir}/openMMC-afcv4-${tag}.elf" cp "${afc_v4_build_dir}/out/openMMC.bin" "${bin_dir}/openMMC-afcv4-${tag}.bin" From f0d47798a0d86f81da2cd8bb618d310af7ae8e28 Mon Sep 17 00:00:00 2001 From: Gustavo de Souza dos Reis Date: Wed, 30 Aug 2023 12:50:27 -0300 Subject: [PATCH 08/43] Write address and read data should be done in a single I2C transaction When reading from an I2C EEPROM you need to write the address first, then send a restart, read the data and finish the transaction. Writing the address and reading the data in different transactions might work, but it seems to be a fragile assumption. --- modules/eeprom_24xx64.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/modules/eeprom_24xx64.c b/modules/eeprom_24xx64.c index dce2995b2..8765a7f80 100644 --- a/modules/eeprom_24xx64.c +++ b/modules/eeprom_24xx64.c @@ -52,11 +52,7 @@ size_t eeprom_24xx64_read( uint8_t id, uint16_t address, uint8_t *rx_data, size_ } if (i2c_take_by_chipid( id, &i2c_addr, &i2c_interface, timeout ) ) { - /* Sets address register */ - xI2CMasterWrite( i2c_interface, i2c_addr, addr8 , sizeof(addr8) ); - - /* Read data */ - rx_len = xI2CMasterRead( i2c_interface, i2c_addr, rx_data, buf_len ); + rx_len = xI2CMasterWriteRead (i2c_interface, i2c_addr, addr8, rx_data, buf_len); i2c_give( i2c_interface ); } From 1d3c051759cd883c3e3c4cf550baab3b973e7130 Mon Sep 17 00:00:00 2001 From: Gustavo de Souza dos Reis Date: Mon, 21 Aug 2023 14:24:48 -0300 Subject: [PATCH 09/43] Fix incorrect data write length [at24mac] Since the first byte of page_buf is the address, the real written data is the number of written bytes minus one. --- modules/at24mac.c | 1 + 1 file changed, 1 insertion(+) diff --git a/modules/at24mac.c b/modules/at24mac.c index 604cf578f..de54864f5 100644 --- a/modules/at24mac.c +++ b/modules/at24mac.c @@ -106,6 +106,7 @@ size_t at24mac_write( uint8_t id, uint16_t address, uint8_t *tx_data, size_t buf /* Write the data */ tx_len += xI2CMasterWrite( i2c_interface, i2c_addr, &page_buf[0] , bytes_to_write+1 ); + tx_len -= 1; /* Remove byte address from data written size */ curr_addr += bytes_to_write; } i2c_give( i2c_interface ); From 11bc629aef938e8a8c58255884188196e52df4d4 Mon Sep 17 00:00:00 2001 From: Gustavo de Souza dos Reis Date: Wed, 4 Oct 2023 08:52:03 -0300 Subject: [PATCH 10/43] Add suport for xvc probe --- .github/workflows/build.yml | 1 + README.md | 2 +- probe/openocd.cfg.in | 2 +- probe/openocd.cmake | 15 ++++++++++++--- 4 files changed, 15 insertions(+), 5 deletions(-) diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index 8a7888952..b3064c010 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -19,6 +19,7 @@ jobs: - { flags: -DBOARD=afc -DVERSION=4.0 -DDEBUG_PROBE=jlink -DOPENOCD_TRANSPORT=swd } - { flags: -DBOARD=afc -DVERSION=4.0 -DDEBUG_PROBE=cmsis-dap -DOPENOCD_TRANSPORT=swd } - { flags: -DBOARD=afc -DVERSION=4.0 -DDEBUG_PROBE=digilent_jtag_hs3 -DOPENOCD_TRANSPORT=jtag } + - { flags: -DBOARD=afc -DVERSION=4.0 -DDEBUG_PROBE=xvc -DOPENOCD_TRANSPORT=jtag -DXVC_HOST=host -DXVC_PORT=0000} steps: - uses: actions/checkout@v3 with: diff --git a/README.md b/README.md index 65c758447..d31c1e27e 100644 --- a/README.md +++ b/README.md @@ -52,7 +52,7 @@ To make a debug build (to include symbols into elf file, turn off optimizations, ## Programming ### OpenOCD -Flashing the MMC microcontroller via SWD/JTAG is supported for CMSIS-DAP and Jlink compatible probes through OpenOCD. You can specify the debug probe with the flag `-DDEBUG_PROBE=`, valid options are `cmsis-dap` (default) and `jlink`. +Flashing the MMC microcontroller via SWD/JTAG is supported for CMSIS-DAP and Jlink compatible probes through OpenOCD. You can specify the debug probe with the flag `-DDEBUG_PROBE=`, valid options are `cmsis-dap` (default), `jlink`, `digilent_jtag_hs3` and `xvc` (support is not merged to the official OpenOCD source yet, so you build our patched version: https://github.com/lnls-dig/openocd/tree/fix-afcv3-flashing). cmake ~/openmmc/ -DBOARD=afc -DVERSION=3.1 -DDEBUG_PROBE=cmsis-dap diff --git a/probe/openocd.cfg.in b/probe/openocd.cfg.in index 7ce39aabb..94a8e7c81 100644 --- a/probe/openocd.cfg.in +++ b/probe/openocd.cfg.in @@ -1,4 +1,4 @@ -source [find ${OPENOCD_DEBUG_PROBE_FILE}] +${OPENOCD_DEBUG_PROBE_CMD} transport select ${OPENOCD_TRANSPORT} diff --git a/probe/openocd.cmake b/probe/openocd.cmake index 6f8636b88..e8f8a552a 100644 --- a/probe/openocd.cmake +++ b/probe/openocd.cmake @@ -23,14 +23,23 @@ else() # Selects the OpenOCD debug probe file if(${DEBUG_PROBE} STREQUAL "digilent_jtag_hs3") - set(OPENOCD_DEBUG_PROBE_FILE "interface/ftdi/digilent_jtag_hs3.cfg") + set(OPENOCD_DEBUG_PROBE_CMD "source [find interface/ftdi/digilent_jtag_hs3.cfg]") check_probe_transport("jtag" ${OPENOCD_TRANSPORT}) elseif(${DEBUG_PROBE} STREQUAL "cmsis-dap") - set(OPENOCD_DEBUG_PROBE_FILE "interface/cmsis-dap.cfg") + set(OPENOCD_DEBUG_PROBE_CMD "source [find interface/cmsis-dap.cfg]") check_probe_transport("jtag;swd" ${OPENOCD_TRANSPORT}) elseif(${DEBUG_PROBE} STREQUAL "jlink") - set(OPENOCD_DEBUG_PROBE_FILE "interface/jlink.cfg") + set(OPENOCD_DEBUG_PROBE_CMD "source [find interface/jlink.cfg]") check_probe_transport("jtag;swd" ${OPENOCD_TRANSPORT}) + elseif(${DEBUG_PROBE} STREQUAL "xvc") + if(NOT XVC_HOST) + message(FATAL_ERROR "No xvc host selected, use -DXVC_HOST= to select it.") + elseif(NOT XVC_PORT) + message(FATAL_ERROR "No xvc port selected, use -DXVC_PORT= to select it.") + else() + set(OPENOCD_DEBUG_PROBE_CMD "adapter driver xvc\nxvc_host ${XVC_HOST}\nxvc_port ${XVC_PORT}\nreset_config none") + check_probe_transport("jtag" ${OPENOCD_TRANSPORT}) + endif() else() message(FATAL_ERROR "${DEBUG_PROBE} not supported!") endif() From 7a91948975f87f6613b28fc1ea562a2a7bb3c475 Mon Sep 17 00:00:00 2001 From: Augusto Fraga Giachero Date: Thu, 17 Aug 2023 15:15:37 -0300 Subject: [PATCH 11/43] Add script for decoding and encoding clock configuration --- config/lnls/afcv3.1-bpm-clk-cfg.json | 119 ++++++++++++++++++++++ config/lnls/afcv3.1-timing-clk-cfg.json | 119 ++++++++++++++++++++++ config/lnls/afcv4-fofb-clk-cfg.json | 101 +++++++++++++++++++ scripts/afcv3.1-clksw-config.py | 129 ++++++++++++++++++++++++ scripts/afcv4-clksw-config.py | 106 +++++++++++++++++++ 5 files changed, 574 insertions(+) create mode 100644 config/lnls/afcv3.1-bpm-clk-cfg.json create mode 100644 config/lnls/afcv3.1-timing-clk-cfg.json create mode 100644 config/lnls/afcv4-fofb-clk-cfg.json create mode 100755 scripts/afcv3.1-clksw-config.py create mode 100755 scripts/afcv4-clksw-config.py diff --git a/config/lnls/afcv3.1-bpm-clk-cfg.json b/config/lnls/afcv3.1-bpm-clk-cfg.json new file mode 100644 index 000000000..835b7e989 --- /dev/null +++ b/config/lnls/afcv3.1-bpm-clk-cfg.json @@ -0,0 +1,119 @@ +{ + "afc_ver": "3.1", + "in_cfg": { + "FMC2_CLK3_BIDIR": { + "POL": "POS" + }, + "FMC2_CLK1_M2": { + "POL": "POS" + }, + "FMC2_CLK0_M2C": { + "POL": "POS" + }, + "FMC2_CLK2_BIDIR": { + "POL": "POS" + }, + "TCLKB": { + "POL": "POS" + }, + "TCLKA": { + "POL": "POS" + }, + "TCLKC": { + "POL": "POS" + }, + "TCLKD": { + "POL": "POS" + }, + "FCLKA": { + "POL": "POS" + }, + "FMC1_CLK3_BIDIR": { + "POL": "POS" + }, + "FMC1_CLK1_M2C": { + "POL": "POS" + }, + "FMC1_CLK0_M2C": { + "POL": "POS" + }, + "FMC1_CLK2_BIDIR": { + "POL": "POS" + }, + "WR_PLL_CLK1": { + "POL": "POS" + }, + "CLK20_VCXO": { + "POL": "POS" + }, + "SI57X_CLK": { + "POL": "POS" + } + }, + "out_cfg": { + "TCLKD": { + "SRC": "FMC2_CLK3_BIDIR", + "EN": false + }, + "TCLKC": { + "SRC": "FMC2_CLK3_BIDIR", + "EN": false + }, + "TCLKA": { + "SRC": "FMC2_CLK3_BIDIR", + "EN": false + }, + "TCLKB": { + "SRC": "FMC2_CLK3_BIDIR", + "EN": false + }, + "FPGA_CLK1": { + "SRC": "WR_PLL_CLK1", + "EN": true + }, + "FP2_CLK2": { + "SRC": "FCLKA", + "EN": false + }, + "LINK01_CLK": { + "SRC": "TCLKA", + "EN": true + }, + "FP2_CLK1": { + "SRC": "SI57X_CLK", + "EN": true + }, + "PCIE_CLK1": { + "SRC": "FCLKA", + "EN": true + }, + "LINK23_CLK": { + "SRC": "TCLKA", + "EN": false + }, + "FIN1_CLK3": { + "SRC": "TCLKA", + "EN": true + }, + "FIN1_CLK2": { + "SRC": "TCLKA", + "EN": true + }, + "RTM_SYNC_CLK": { + "SRC": "CLK20_VCXO", + "EN": false + }, + "OP15C": { + "SRC": "TCLKA", + "EN": true + }, + "FIN2_CLK2": { + "SRC": "TCLKA", + "EN": true + }, + "FIN2_CLK3": { + "SRC": "TCLKA", + "EN": true + } + } +} diff --git a/config/lnls/afcv3.1-timing-clk-cfg.json b/config/lnls/afcv3.1-timing-clk-cfg.json new file mode 100644 index 000000000..0925ddc21 --- /dev/null +++ b/config/lnls/afcv3.1-timing-clk-cfg.json @@ -0,0 +1,119 @@ +{ + "afc_ver": "3.1", + "in_cfg": { + "FMC2_CLK3_BIDIR": { + "POL": "POS" + }, + "FMC2_CLK1_M2": { + "POL": "POS" + }, + "FMC2_CLK0_M2C": { + "POL": "POS" + }, + "FMC2_CLK2_BIDIR": { + "POL": "POS" + }, + "TCLKB": { + "POL": "POS" + }, + "TCLKA": { + "POL": "POS" + }, + "TCLKC": { + "POL": "POS" + }, + "TCLKD": { + "POL": "POS" + }, + "FCLKA": { + "POL": "POS" + }, + "FMC1_CLK3_BIDIR": { + "POL": "POS" + }, + "FMC1_CLK1_M2C": { + "POL": "POS" + }, + "FMC1_CLK0_M2C": { + "POL": "POS" + }, + "FMC1_CLK2_BIDIR": { + "POL": "POS" + }, + "WR_PLL_CLK1": { + "POL": "POS" + }, + "CLK20_VCXO": { + "POL": "POS" + }, + "SI57X_CLK": { + "POL": "POS" + } + }, + "out_cfg": { + "TCLKD": { + "SRC": "FMC2_CLK3_BIDIR", + "EN": false + }, + "TCLKC": { + "SRC": "FMC2_CLK3_BIDIR", + "EN": false + }, + "TCLKA": { + "SRC": "FMC2_CLK3_BIDIR", + "EN": false + }, + "TCLKB": { + "SRC": "SI57X_CLK", + "EN": true + }, + "FPGA_CLK1": { + "SRC": "SI57X_CLK", + "EN": true + }, + "FP2_CLK2": { + "SRC": "FCLKA", + "EN": false + }, + "LINK01_CLK": { + "SRC": "WR_PLL_CLK1", + "EN": true + }, + "FP2_CLK1": { + "SRC": "FCLKA", + "EN": false + }, + "PCIE_CLK1": { + "SRC": "FCLKA", + "EN": true + }, + "LINK23_CLK": { + "SRC": "WR_PLL_CLK1", + "EN": false + }, + "FIN1_CLK3": { + "SRC": "CLK20_VCXO", + "EN": false + }, + "FIN1_CLK2": { + "SRC": "CLK20_VCXO", + "EN": false + }, + "RTM_SYNC_CLK": { + "SRC": "CLK20_VCXO", + "EN": false + }, + "OP15C": { + "SRC": "SI57X_CLK", + "EN": true + }, + "FIN2_CLK2": { + "SRC": "CLK20_VCXO", + "EN": false + }, + "FMC2_CLK2_BIDIR": { + "SRC": "FMC2_CLK2_BIDIR", + "EN": false + } + } +} diff --git a/config/lnls/afcv4-fofb-clk-cfg.json b/config/lnls/afcv4-fofb-clk-cfg.json new file mode 100644 index 000000000..3b919acd9 --- /dev/null +++ b/config/lnls/afcv4-fofb-clk-cfg.json @@ -0,0 +1,101 @@ +{ + "afc_ver": "4.0", + "cfg": { + "AMC_CLK_RTM_CLK": { + "SRC": "TCLKA", + "POL": "POS", + "TERM": "OFF", + "DIR": "OUT" + }, + "FMC2_CLK1_M2C_FMC2_CLK3_BIDIR": { + "SRC": "AMC_CLK_RTM_CLK", + "POL": "POS", + "TERM": "OFF", + "DIR": "IN" + }, + "FMC1_CLK1_M2C_FMC1_CLK3_BIDIR": { + "SRC": "AMC_CLK_RTM_CLK", + "POL": "POS", + "TERM": "OFF", + "DIR": "IN" + }, + "FMC1_CLK0_M2C": { + "SRC": "AMC_CLK_RTM_CLK", + "POL": "POS", + "TERM": "OFF", + "DIR": "IN" + }, + "FMC1_CLK2_BIDIR": { + "SRC": "AMC_CLK_RTM_CLK", + "POL": "POS", + "TERM": "OFF", + "DIR": "IN" + }, + "SI57X_PRI": { + "SRC": "AMC_CLK_RTM_CLK", + "POL": "POS", + "TERM": "ON", + "DIR": "IN" + }, + "FMC2_CLK0_M2C": { + "SRC": "AMC_CLK_RTM_CLK", + "POL": "POS", + "TERM": "OFF", + "DIR": "IN" + }, + "FMC2_CLK2_BIDIR": { + "SRC": "TCLKA", + "POL": "POS", + "TERM": "OFF", + "DIR": "OUT" + }, + "TCLKD_FLEX_FPGA_CLK3": { + "SRC": "AMC_CLK_RTM_CLK", + "POL": "POS", + "TERM": "OFF", + "DIR": "IN" + }, + "TCLKC_FLEX_FPGA_CLK2": { + "SRC": "AMC_CLK_RTM_CLK", + "POL": "POS", + "TERM": "OFF", + "DIR": "IN" + }, + "TCLKA": { + "SRC": "AMC_CLK_RTM_CLK", + "POL": "POS", + "TERM": "ON", + "DIR": "IN" + }, + "TCLKB": { + "SRC": "AMC_CLK_RTM_CLK", + "POL": "POS", + "TERM": "OFF", + "DIR": "IN" + }, + "FLEX_GTP113_CLK0": { + "SRC": "AMC_CLK_RTM_CLK", + "POL": "POS", + "TERM": "OFF", + "DIR": "IN" + }, + "FLEX_GTP113_GTP216_CLK1": { + "SRC": "SI57X_PRI", + "POL": "POS", + "TERM": "OFF", + "DIR": "OUT" + }, + "FLEX_GTP116_CLK1_RTM_GTP03": { + "SRC": "AMC_CLK_RTM_CLK", + "POL": "POS", + "TERM": "OFF", + "DIR": "IN" + }, + "FLEX_GTP213_CLK1_RTM_GTP47": { + "SRC": "TCLKA", + "POL": "POS", + "TERM": "OFF", + "DIR": "OUT" + } + } +} \ No newline at end of file diff --git a/scripts/afcv3.1-clksw-config.py b/scripts/afcv3.1-clksw-config.py new file mode 100755 index 000000000..656eecaa1 --- /dev/null +++ b/scripts/afcv3.1-clksw-config.py @@ -0,0 +1,129 @@ +#!/usr/bin/env python3 +# +# AFCv3.1 clock switch config decoder / encoder +# Copyright (C) 2023 CNPEM LNLS +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . + +import argparse +import json +import sys + +parser = argparse.ArgumentParser(description="Decode AFCv3.1 clock configuration") +parser.add_argument("--json-out", type=str, help="Save clock configuration in a json file", required=False) +parser.add_argument("--print-reg-array", help="Print register configuration data", required=False, action="store_true") +parser.add_argument("--print-config", help="Pretty print clock configuration", required=False, action="store_true") +parser_data_in_grp = parser.add_mutually_exclusive_group(required=True) +parser_data_in_grp.add_argument("--bytes", metavar="byte", type=str, nargs=16, help="Byte array", required=False) +parser_data_in_grp.add_argument("--json-in", type=str, help="Decode clock configuration json file", required=False) + +args = parser.parse_args() + +afcv3_clk_in_names = [ + "FMC2_CLK3_BIDIR", + "FMC2_CLK1_M2", + "FMC2_CLK0_M2C", + "FMC2_CLK2_BIDIR", + "TCLKB", + "TCLKA", + "TCLKC", + "TCLKD", + "FCLKA", + "FMC1_CLK3_BIDIR", + "FMC1_CLK1_M2C", + "FMC1_CLK0_M2C", + "FMC1_CLK2_BIDIR", + "WR_PLL_CLK1", + "CLK20_VCXO", + "SI57X_CLK" +] + +afcv3_clk_out_names = [ + "TCLKD", + "TCLKC", + "TCLKA", + "TCLKB", + "FPGA_CLK1", + "FP2_CLK2", + "LINK01_CLK", + "FP2_CLK1", + "PCIE_CLK1", + "LINK23_CLK", + "FIN1_CLK3", + "FIN1_CLK2", + "RTM_SYNC_CLK", + "OP15C", + "FIN2_CLK2", + "FIN2_CLK3" +] + +afcv3_clk_in_names_dict = {afcv3_clk_in_names[i] : i for i in range(0, len(afcv3_clk_in_names))} + +def adn4604_decode(data): + adn4604_dict = {"afc_ver": "3.1"} + in_cfg = {} + out_cfg = {} + for ch_cfg_raw, ch_in_name, ch_out_name in zip(data, afcv3_clk_in_names, afcv3_clk_out_names): + ch_in_cfg = { + "POL": "POS" if (ch_cfg_raw & 0x20) != 0 else "NEG", + } + ch_out_cfg = { + "SRC": afcv3_clk_in_names[ch_cfg_raw & 0xF], + "EN": True if (ch_cfg_raw & 0x80) != 0 else False, + } + in_cfg[ch_in_name] = ch_in_cfg + out_cfg[ch_out_name] = ch_out_cfg + adn4604_dict["in_cfg"] = in_cfg + adn4604_dict["out_cfg"] = out_cfg + return adn4604_dict + +def adn4604_encode(adn4604_cfg): + data = bytearray() + for pin, pout in zip(afcv3_clk_in_names, afcv3_clk_out_names): + b = afcv3_clk_in_names_dict[adn4604_cfg["out_cfg"][pout]["SRC"]] + b = b | 0x20 if adn4604_cfg["in_cfg"][pin]["POL"] == "POS" else b + b = b | 0x80 if adn4604_cfg["out_cfg"][pout]["EN"] == True else b + data.append(b) + return data + +def print_adn4604(adn4604_cfg): + for ch_out_name, ch_out_cfg in adn4604_cfg["out_cfg"].items(): + if ch_out_cfg["EN"] == True: + ch_out_src = ch_out_cfg["SRC"] + print("{:<19} -> {}".format(ch_out_src, ch_out_name)) + print(" └─POL: {}".format(adn4604_cfg["in_cfg"][ch_out_src]["POL"])) + +if args.bytes != None: + adn4604_raw_data = bytearray([int(i, 16) for i in args.bytes]) + clk_cfg = adn4604_decode(adn4604_raw_data) +elif args.json_in != None: + with open(args.json_in, "r") as f: + clk_cfg = json.load(f) + if clk_cfg.get("afc_ver") != "3.1": + print("JSON input not compatible with AFCv3.1!", file=sys.stderr) + exit(1) + +if args.json_out != None: + with open(args.json_out, "w") as f: + json.dump(clk_cfg, f, indent=True) + +if args.print_config: + print_adn4604(clk_cfg) + +if args.print_reg_array: + reg_str = "" + reg_data = adn4604_encode(clk_cfg) + for b in reg_data: + reg_str = reg_str + "0x{:02X} ".format(b) + print(reg_str) diff --git a/scripts/afcv4-clksw-config.py b/scripts/afcv4-clksw-config.py new file mode 100755 index 000000000..f286b6ff5 --- /dev/null +++ b/scripts/afcv4-clksw-config.py @@ -0,0 +1,106 @@ +#!/usr/bin/env python3 +# +# AFCv4 clock switch config decoder / encoder +# Copyright (C) 2023 CNPEM LNLS +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . + +import argparse +import json +import sys + +parser = argparse.ArgumentParser(description="Decode AFCv4 clock configuration") +parser.add_argument("--json-out", type=str, help="Save clock configuration in a json file", required=False) +parser.add_argument("--print-reg-array", help="Print register configuration data", required=False, action="store_true") +parser.add_argument("--print-config", help="Pretty print clock configuration", required=False, action="store_true") +parser_data_in_grp = parser.add_mutually_exclusive_group(required=True) +parser_data_in_grp.add_argument("--bytes", metavar="byte", type=str, nargs=16, help="Byte array", required=False) +parser_data_in_grp.add_argument("--json-in", type=str, help="Decode clock configuration json file", required=False) + +args = parser.parse_args() + +afcv4_clk_names = [ + "AMC_CLK_RTM_CLK", + "FMC2_CLK1_M2C_FMC2_CLK3_BIDIR", + "FMC1_CLK1_M2C_FMC1_CLK3_BIDIR", + "FMC1_CLK0_M2C", + "FMC1_CLK2_BIDIR", + "SI57X_PRI", + "FMC2_CLK0_M2C", + "FMC2_CLK2_BIDIR", + "TCLKD_FLEX_FPGA_CLK3", + "TCLKC_FLEX_FPGA_CLK2", + "TCLKA", + "TCLKB", + "FLEX_GTP113_CLK0", + "FLEX_GTP113_GTP216_CLK1", + "FLEX_GTP116_CLK1_RTM_GTP03", + "FLEX_GTP213_CLK1_RTM_GTP47" +] + +afcv4_clk_names_dict = {afcv4_clk_names[i] : i for i in range(0, len(afcv4_clk_names))} + +def idt_decode(data): + idt_dict = {} + for ch_cfg_raw, ch_name in zip(data, afcv4_clk_names): + ch_cfg = { + "SRC": afcv4_clk_names[ch_cfg_raw & 0xF], + "POL": "POS" if (ch_cfg_raw & 0x20) != 0 else "NEG", + "TERM": "ON" if (ch_cfg_raw & 0x40) != 0 else "OFF", + "DIR": "OUT" if (ch_cfg_raw & 0x80) != 0 else "IN", + } + idt_dict[ch_name] = ch_cfg + return {"afc_ver": "4.0", "cfg": idt_dict} + +def idt_encode(idt_cfg): + data = bytearray() + for port in afcv4_clk_names: + b = afcv4_clk_names_dict[idt_cfg["cfg"][port]["SRC"]] + b = b | 0x20 if idt_cfg["cfg"][port]["POL"] == "POS" else b + b = b | 0x40 if idt_cfg["cfg"][port]["TERM"] == "ON" else b + b = b | 0x80 if idt_cfg["cfg"][port]["DIR"] == "OUT" else b + data.append(b) + return data + +def print_idt(idt_cfg): + for ch_name, ch_cfg in idt_cfg["cfg"].items(): + if ch_cfg["DIR"] == "OUT": + ch_src = ch_cfg["SRC"] + print("{:<29} -> {}".format(ch_src, ch_name)) + print(" ├─POL: {:<24} ├─POL: {}".format(idt_cfg["cfg"][ch_src]["POL"], ch_cfg["POL"])) + print(" └─TERM: {:<23} └─TERM: {}".format(idt_cfg["cfg"][ch_src]["TERM"], ch_cfg["TERM"])) + +if args.bytes != None: + idt_raw_data = bytearray([int(i, 16) for i in args.bytes]) + clk_cfg = idt_decode(idt_raw_data) +elif args.json_in != None: + with open(args.json_in, "r") as f: + clk_cfg = json.load(f) + if clk_cfg.get("afc_ver") != "4.0": + print("JSON input not compatible with AFCv4!", file=sys.stderr) + exit(1) + +if args.json_out != None: + with open(args.json_out, "w") as f: + json.dump(clk_cfg, f, indent=True) + +if args.print_config: + print_idt(clk_cfg) + +if args.print_reg_array: + reg_str = "" + reg_data = idt_encode(clk_cfg) + for b in reg_data: + reg_str = reg_str + "0x{:02X} ".format(b) + print(reg_str) From 2eb350d14faa7d00011efe299f0904fbb4dc9a47 Mon Sep 17 00:00:00 2001 From: Gustavo de Souza dos Reis Date: Tue, 17 Oct 2023 13:10:28 -0300 Subject: [PATCH 12/43] Separate the I2C chip_id map for AFC devices and RTM devices Create different i2c_chip_mapping_t arrays and reserve chip_id numbers between 0 and 63 to AFC devices and between 64 and 127 to the RTM devices. --- modules/i2c.c | 36 ++++++++++++++++++++++----- port/board/afc-common/board_fru.c | 5 +++- port/board/afc-v3/i2c_mapping.c | 5 ---- port/board/afc-v3/i2c_mapping.h | 6 +---- port/board/rtm-8sfp/CMakeLists.txt | 7 ++++++ port/board/rtm-8sfp/rtm_i2c_mapping.c | 11 ++++++++ port/board/rtm-8sfp/rtm_i2c_mapping.h | 17 +++++++++++++ port/board/rtm-8sfp/rtm_user.c | 1 + port/board/rtm-8sfp/sdr_list.c | 2 +- port/board/rtm-lamp/CMakeLists.txt | 8 ++++++ port/board/rtm-lamp/rtm_i2c_mapping.c | 15 +++++++++++ port/board/rtm-lamp/rtm_i2c_mapping.h | 21 ++++++++++++++++ port/board/rtm-lamp/rtm_user.c | 1 + port/board/rtm-lamp/sdr_list.c | 2 +- 14 files changed, 118 insertions(+), 19 deletions(-) create mode 100644 port/board/rtm-8sfp/rtm_i2c_mapping.c create mode 100644 port/board/rtm-8sfp/rtm_i2c_mapping.h create mode 100644 port/board/rtm-lamp/rtm_i2c_mapping.c create mode 100644 port/board/rtm-lamp/rtm_i2c_mapping.h diff --git a/modules/i2c.c b/modules/i2c.c index aa3ab7e7f..2831403ee 100644 --- a/modules/i2c.c +++ b/modules/i2c.c @@ -25,6 +25,10 @@ #include "i2c.h" #include "i2c_mapping.h" +#ifdef MODULE_RTM +#include "rtm_i2c_mapping.h" +#endif + void i2c_init( void ) { for ( uint8_t i = 0; i < I2C_MUX_CNT; i++ ) { @@ -85,13 +89,33 @@ bool i2c_take_by_busid( uint8_t bus_id, uint8_t *i2c_interface, TickType_t timeo bool i2c_take_by_chipid( uint8_t chip_id, uint8_t *i2c_address, uint8_t *i2c_interface, uint32_t timeout ) { - if ( chip_id > I2C_CHIP_CNT ) { - return false; - } - uint8_t bus_id = i2c_chip_map[chip_id].bus_id; - if ( i2c_address != NULL ) { - *i2c_address = i2c_chip_map[chip_id].i2c_address; + uint8_t bus_id; + + /*AFC devices*/ + if (chip_id <= 63) { + if ( chip_id > I2C_CHIP_CNT ) { + return false; + } + bus_id = i2c_chip_map[chip_id].bus_id; + if ( i2c_address != NULL ) { + *i2c_address = i2c_chip_map[chip_id].i2c_address; + } + +#ifdef MODULE_RTM + /*RTM devices*/ + } else if ((64 <= chip_id) && (chip_id <= 127)) { + if ( chip_id > 64+I2C_CHIP_RTM_CNT ) { + return false; + } + bus_id = i2c_chip_rtm_map[chip_id-64].bus_id; + if ( i2c_address != NULL ) { + *i2c_address = i2c_chip_map[chip_id-64].i2c_address; + } +#endif + + } else { + return false; } return i2c_take_by_busid( bus_id, i2c_interface, timeout ); diff --git a/port/board/afc-common/board_fru.c b/port/board/afc-common/board_fru.c index d0281aaf9..d10c93e65 100644 --- a/port/board/afc-common/board_fru.c +++ b/port/board/afc-common/board_fru.c @@ -28,7 +28,9 @@ #include "at24mac.h" #include "eeprom_24xx64.h" #include "i2c_mapping.h" - +#ifdef MODULE_RTM +#include "rtm_i2c_mapping.h" +#endif fru_data_t fru[FRU_COUNT] = { [FRU_AMC] = { .cfg = { @@ -40,6 +42,7 @@ fru_data_t fru[FRU_COUNT] = { .runtime = false }, #ifdef MODULE_RTM + [FRU_RTM] = { .cfg = { .eeprom_id = CHIP_ID_RTM_EEPROM, diff --git a/port/board/afc-v3/i2c_mapping.c b/port/board/afc-v3/i2c_mapping.c index e979a3cdf..d31f5f506 100644 --- a/port/board/afc-v3/i2c_mapping.c +++ b/port/board/afc-v3/i2c_mapping.c @@ -47,11 +47,6 @@ i2c_chip_mapping_t i2c_chip_map[I2C_CHIP_CNT] = { [CHIP_ID_FMC2_EEPROM] = { I2C_BUS_FMC2_ID, 0x52 }, [CHIP_ID_FMC2_LM75_0] = { I2C_BUS_FMC2_ID, 0x48 }, [CHIP_ID_FMC2_LM75_1] = { I2C_BUS_FMC2_ID, 0x49 }, - - [CHIP_ID_RTM_PCA9554] = { I2C_BUS_RTM_ID, 0x20 }, - [CHIP_ID_RTM_EEPROM] = { I2C_BUS_RTM_ID, 0x50 }, - [CHIP_ID_RTM_LM75_0] = { I2C_BUS_RTM_ID, 0x48 }, - [CHIP_ID_RTM_LM75_1] = { I2C_BUS_RTM_ID, 0x49 }, }; bool i2c_set_mux_bus( uint8_t bus_id, i2c_mux_state_t *i2c_mux, int8_t new_state ) diff --git a/port/board/afc-v3/i2c_mapping.h b/port/board/afc-v3/i2c_mapping.h index aaf5cb474..6613343a6 100644 --- a/port/board/afc-v3/i2c_mapping.h +++ b/port/board/afc-v3/i2c_mapping.h @@ -55,15 +55,11 @@ enum { CHIP_ID_FMC2_EEPROM, CHIP_ID_FMC2_LM75_1, CHIP_ID_FMC2_LM75_0, - CHIP_ID_RTM_PCA9554, - CHIP_ID_RTM_EEPROM, - CHIP_ID_RTM_LM75_0, - CHIP_ID_RTM_LM75_1 }; #define I2C_MUX_CNT 2 #define I2C_BUS_CNT 7 -#define I2C_CHIP_CNT 28 +#define I2C_CHIP_CNT 24 extern i2c_mux_state_t i2c_mux[I2C_MUX_CNT]; extern i2c_bus_mapping_t i2c_bus_map[I2C_BUS_CNT]; diff --git a/port/board/rtm-8sfp/CMakeLists.txt b/port/board/rtm-8sfp/CMakeLists.txt index 224b6917b..2504a6c5d 100644 --- a/port/board/rtm-8sfp/CMakeLists.txt +++ b/port/board/rtm-8sfp/CMakeLists.txt @@ -11,13 +11,20 @@ set(RTM_8SFP_PATH ${CMAKE_CURRENT_SOURCE_DIR}) set( PROJ_SRCS ${PROJ_SRCS} ${RTM_8SFP_PATH}/rtm_user.c ${RTM_8SFP_PATH}/sdr_list.c + ${RTM_8SFP_PATH}/rtm_i2c_mapping.c ) #Include headers path set(PROJ_HDRS ${PROJ_HDRS} ${RTM_8SFP_PATH}) +if(${TARGET_BOARD_NAME} MATCHES "afc-v3") + list(APPEND PROJ_HDRS ${RTM_8SFP_PATH}/../afc-v3/i2c_mapping.h) +elseif(${TARGET_BOARD_NAME} MATCHES "afc-v4") + list(APPEND PROJ_HDRS ${RTM_8SFP_PATH}/../afc-v4/i2c_mapping.h) +endif() #Set the variables in the main scope set(TARGET_MODULES ${TARGET_MODULES} ${RTM_8SFP_MODULES} PARENT_SCOPE) +#Set the variables in the main scope set(PROJ_SRCS ${PROJ_SRCS} PARENT_SCOPE) set(PROJ_HDRS ${PROJ_HDRS} PARENT_SCOPE) diff --git a/port/board/rtm-8sfp/rtm_i2c_mapping.c b/port/board/rtm-8sfp/rtm_i2c_mapping.c new file mode 100644 index 000000000..1c617534e --- /dev/null +++ b/port/board/rtm-8sfp/rtm_i2c_mapping.c @@ -0,0 +1,11 @@ +#include "i2c.h" +#include "rtm_i2c_mapping.h" +#include "i2c_mapping.h" +#include "port.h" + +i2c_chip_mapping_t i2c_chip_rtm_map[I2C_CHIP_RTM_CNT] = { + [CHIP_ID_RTM_PCA9554 - 64] = { I2C_BUS_RTM_ID, 0x20 }, + [CHIP_ID_RTM_EEPROM - 64] = { I2C_BUS_RTM_ID, 0x50 }, + [CHIP_ID_RTM_LM75_0 - 64] = { I2C_BUS_RTM_ID, 0x48 }, + [CHIP_ID_RTM_LM75_1 - 64] = { I2C_BUS_RTM_ID, 0x49 }, +}; diff --git a/port/board/rtm-8sfp/rtm_i2c_mapping.h b/port/board/rtm-8sfp/rtm_i2c_mapping.h new file mode 100644 index 000000000..e2de49b62 --- /dev/null +++ b/port/board/rtm-8sfp/rtm_i2c_mapping.h @@ -0,0 +1,17 @@ +#ifndef RTM_I2C_MAPPING_H_ +#define RTM_I2C_MAPPING_H_ + +#include "i2c.h" + +enum { + CHIP_ID_RTM_PCA9554 = 64, + CHIP_ID_RTM_EEPROM, + CHIP_ID_RTM_LM75_0, + CHIP_ID_RTM_LM75_1 +}; + +#define I2C_CHIP_RTM_CNT 4 + +extern i2c_chip_mapping_t i2c_chip_rtm_map[I2C_CHIP_RTM_CNT]; + +#endif diff --git a/port/board/rtm-8sfp/rtm_user.c b/port/board/rtm-8sfp/rtm_user.c index 9042a8be9..c1849335f 100644 --- a/port/board/rtm-8sfp/rtm_user.c +++ b/port/board/rtm-8sfp/rtm_user.c @@ -26,6 +26,7 @@ #include "pin_mapping.h" #include "hotswap.h" #include "i2c_mapping.h" +#include "rtm_i2c_mapping.h" #include "fru.h" #include "utils.h" #include "led.h" diff --git a/port/board/rtm-8sfp/sdr_list.c b/port/board/rtm-8sfp/sdr_list.c index 94aad3c6a..c60e15a36 100644 --- a/port/board/rtm-8sfp/sdr_list.c +++ b/port/board/rtm-8sfp/sdr_list.c @@ -23,7 +23,7 @@ #include "sdr.h" #include "utils.h" #include "sensors.h" -#include "i2c_mapping.h" +#include "rtm_i2c_mapping.h" /* Rename file to sdr_list.c */ #ifdef MODULE_HOTSWAP diff --git a/port/board/rtm-lamp/CMakeLists.txt b/port/board/rtm-lamp/CMakeLists.txt index 6b46c70bb..e4a1a0d75 100644 --- a/port/board/rtm-lamp/CMakeLists.txt +++ b/port/board/rtm-lamp/CMakeLists.txt @@ -13,13 +13,21 @@ set(RTM_LAMP_PATH ${CMAKE_CURRENT_SOURCE_DIR}) set( PROJ_SRCS ${PROJ_SRCS} ${RTM_LAMP_PATH}/rtm_user.c ${RTM_LAMP_PATH}/sdr_list.c + ${RTM_LAMP_PATH}/rtm_i2c_mapping.c ) #Include headers path set(PROJ_HDRS ${PROJ_HDRS} ${RTM_LAMP_PATH}) +if(${TARGET_BOARD_NAME} MATCHES "afc-v3") + list(APPEND PROJ_HDRS ${RTM_8SFP_PATH}/../afc-v3/i2c_mapping.h) +elseif(${TARGET_BOARD_NAME} MATCHES "afc-v4") + list(APPEND PROJ_HDRS ${RTM_8SFP_PATH}/../afc-v4/i2c_mapping.h) +endif() + #Set the variables in the main scope set(TARGET_MODULES ${TARGET_MODULES} ${RTM_LAMP_MODULES} PARENT_SCOPE) +#Set the variables in the main scope set(PROJ_SRCS ${PROJ_SRCS} PARENT_SCOPE) set(PROJ_HDRS ${PROJ_HDRS} PARENT_SCOPE) diff --git a/port/board/rtm-lamp/rtm_i2c_mapping.c b/port/board/rtm-lamp/rtm_i2c_mapping.c new file mode 100644 index 000000000..d2e8a9371 --- /dev/null +++ b/port/board/rtm-lamp/rtm_i2c_mapping.c @@ -0,0 +1,15 @@ +#include "i2c.h" +#include "rtm_i2c_mapping.h" +#include "i2c_mapping.h" +#include "port.h" + +i2c_chip_mapping_t i2c_chip_rtm_map[I2C_CHIP_RTM_CNT] = { + [CHIP_ID_RTM_PCA9554_LEDS - 64] = { I2C_BUS_RTM_ID, 0x20 }, + [CHIP_ID_RTM_PCA9554_PWR - 64] = { I2C_BUS_RTM_ID, 0x21 }, + [CHIP_ID_RTM_EEPROM - 64] = { I2C_BUS_RTM_ID, 0x50 }, + [CHIP_ID_RTM_LM75_0 - 64] = { I2C_BUS_RTM_ID, 0x48 }, + [CHIP_ID_RTM_LM75_1 - 64] = { I2C_BUS_RTM_ID, 0x49 }, + [CHIP_ID_RTM_LM75_2 - 64] = { I2C_BUS_RTM_ID, 0x4B }, + [CHIP_ID_RTM_MAX11609 - 64] = { I2C_BUS_RTM_ID, 0x33 }, + [CHIP_ID_RTM_CDCE906 - 64] = { I2C_BUS_RTM_ID, 0x69 }, +}; diff --git a/port/board/rtm-lamp/rtm_i2c_mapping.h b/port/board/rtm-lamp/rtm_i2c_mapping.h new file mode 100644 index 000000000..fb0171852 --- /dev/null +++ b/port/board/rtm-lamp/rtm_i2c_mapping.h @@ -0,0 +1,21 @@ +#ifndef RTM_I2C_MAPPING_H_ +#define RTM_I2C_MAPPING_H_ + +#include "i2c.h" + +enum { + CHIP_ID_RTM_PCA9554_LEDS = 64, + CHIP_ID_RTM_PCA9554_PWR, + CHIP_ID_RTM_EEPROM, + CHIP_ID_RTM_LM75_0, + CHIP_ID_RTM_LM75_1, + CHIP_ID_RTM_LM75_2, + CHIP_ID_RTM_MAX11609, + CHIP_ID_RTM_CDCE906, +}; + +#define I2C_CHIP_RTM_CNT 8 + +extern i2c_chip_mapping_t i2c_chip_rtm_map[I2C_CHIP_RTM_CNT]; + +#endif diff --git a/port/board/rtm-lamp/rtm_user.c b/port/board/rtm-lamp/rtm_user.c index 7bcab98a8..6d2d8ab08 100644 --- a/port/board/rtm-lamp/rtm_user.c +++ b/port/board/rtm-lamp/rtm_user.c @@ -26,6 +26,7 @@ #include "pin_mapping.h" #include "hotswap.h" #include "i2c_mapping.h" +#include "rtm_i2c_mapping.h" #include "fru.h" #include "utils.h" #include "led.h" diff --git a/port/board/rtm-lamp/sdr_list.c b/port/board/rtm-lamp/sdr_list.c index db7d705a5..8f1e63f16 100644 --- a/port/board/rtm-lamp/sdr_list.c +++ b/port/board/rtm-lamp/sdr_list.c @@ -23,7 +23,7 @@ #include "sdr.h" #include "utils.h" #include "sensors.h" -#include "i2c_mapping.h" +#include "rtm_i2c_mapping.h" /* Rename file to sdr_list.c */ #ifdef MODULE_HOTSWAP From f5d98bf4d956062c7f0d47b230362b829f931e8f Mon Sep 17 00:00:00 2001 From: Gustavo de Souza dos Reis Date: Thu, 26 Oct 2023 10:58:08 -0300 Subject: [PATCH 13/43] Read i2c address from i2c_chip_rtm_map instead of i2c_chip_map --- modules/i2c.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/modules/i2c.c b/modules/i2c.c index 2831403ee..2d33ebba8 100644 --- a/modules/i2c.c +++ b/modules/i2c.c @@ -110,7 +110,7 @@ bool i2c_take_by_chipid( uint8_t chip_id, uint8_t *i2c_address, uint8_t *i2c_int } bus_id = i2c_chip_rtm_map[chip_id-64].bus_id; if ( i2c_address != NULL ) { - *i2c_address = i2c_chip_map[chip_id-64].i2c_address; + *i2c_address = i2c_chip_rtm_map[chip_id-64].i2c_address; } #endif From 8ed196b61de2787da3c27b3de900f7b8e63ff852 Mon Sep 17 00:00:00 2001 From: Gustavo de Souza dos Reis Date: Thu, 26 Oct 2023 13:30:59 -0300 Subject: [PATCH 14/43] Change the fru runtime info to AFC v3 instead of AFC Timing --- port/board/afc-v3/user_amc_fru.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/port/board/afc-v3/user_amc_fru.h b/port/board/afc-v3/user_amc_fru.h index cc201670f..82b77bee5 100644 --- a/port/board/afc-v3/user_amc_fru.h +++ b/port/board/afc-v3/user_amc_fru.h @@ -41,7 +41,7 @@ * Product information area *********************************************/ #define AMC_PRODUCT_MANUFACTURER "LNLS" -#define AMC_PRODUCT_NAME "AFC Timing" +#define AMC_PRODUCT_NAME "AFC v3.1" #define AMC_PRODUCT_PN "" #define AMC_PRODUCT_VERSION "v3.1" #define AMC_PRODUCT_SN "" From d7c579f1021f424fa9ea3d730fa2b534498eb35b Mon Sep 17 00:00:00 2001 From: Gustavo de Souza dos Reis Date: Mon, 23 Oct 2023 14:32:03 -0300 Subject: [PATCH 15/43] Move to rtm_check_presence function to board specific directory --- modules/rtm.h | 10 ++++++++++ port/board/afc-v3/CMakeLists.txt | 5 +++++ port/board/afc-v3/rtm.c | 18 ++++++++++++++++++ port/board/afc-v4/rtm.c | 12 ++++++++++++ port/board/rtm-8sfp/rtm_user.c | 21 --------------------- port/board/rtm-8sfp/rtm_user.h | 1 - port/board/rtm-lamp/rtm_user.c | 21 --------------------- port/board/rtm-lamp/rtm_user.h | 1 - 8 files changed, 45 insertions(+), 44 deletions(-) create mode 100644 port/board/afc-v3/rtm.c create mode 100644 port/board/afc-v4/rtm.c diff --git a/modules/rtm.h b/modules/rtm.h index fa7c87559..ae06ed18b 100644 --- a/modules/rtm.h +++ b/modules/rtm.h @@ -44,4 +44,14 @@ extern volatile bool rtm_present; */ void rtm_manage_init( void ); +/** + * @brief Check RTM Presence + * + * This function is used to detect the RTM Board presence + * + * @return None + */ +void rtm_check_presence(uint8_t *status); + + #endif diff --git a/port/board/afc-v3/CMakeLists.txt b/port/board/afc-v3/CMakeLists.txt index c22a95f1b..60a0f91b8 100644 --- a/port/board/afc-v3/CMakeLists.txt +++ b/port/board/afc-v3/CMakeLists.txt @@ -46,6 +46,11 @@ if (";${TARGET_MODULES};" MATCHES ";PAYLOAD;") set(MODULES_FLAGS "${MODULES_FLAGS} -DMODULE_PAYLOAD") endif() +if (";${TARGET_MODULES};" MATCHES ";RTM;") + set(PROJ_SRCS ${PROJ_SRCS} ${BOARD_PATH}/rtm.c) + set(MODULES_FLAGS "${MODULES_FLAGS} -DMODULE_RTM") +endif() + #Extra definitions if (FRU_WRITE_EEPROM) message(STATUS "FRU EEPROM will be written if no valid data is found!") diff --git a/port/board/afc-v3/rtm.c b/port/board/afc-v3/rtm.c new file mode 100644 index 000000000..17d71295c --- /dev/null +++ b/port/board/afc-v3/rtm.c @@ -0,0 +1,18 @@ +#include "port.h" +#include "rtm_i2c_mapping.h" +#include "eeprom_24xx64.h" +#include "hotswap.h" + +void rtm_check_presence( uint8_t *status ) + { + /* Due to a hardware limitation in the AFC board, we can't rely on reading the PS signal + since this pin doesn't have a pull-up resistor, it's always read as 0. + A very dirty workaround is to 'ping' the RTM EEPROM, if it responds, then the board is connected */ + + uint8_t dumb; + *status = HOTSWAP_STATE_URTM_ABSENT; + + if(eeprom_24xx64_read(CHIP_ID_RTM_EEPROM, 0, &dumb, 1, 100)) { + *status = HOTSWAP_STATE_URTM_PRSENT; + } + } diff --git a/port/board/afc-v4/rtm.c b/port/board/afc-v4/rtm.c new file mode 100644 index 000000000..85ae468dc --- /dev/null +++ b/port/board/afc-v4/rtm.c @@ -0,0 +1,12 @@ +#include "i2c_mapping.h" +#include "port.h" +#include "hotswap.h" + +void rtm_check_presence( uint8_t *status ) + { + *status = HOTSWAP_STATE_URTM_ABSENT; + + if (!gpio_read_pin(PIN_PORT(GPIO_RTM_PS), PIN_NUMBER(GPIO_RTM_PS))) { + *status = HOTSWAP_STATE_URTM_PRSENT; + } + } diff --git a/port/board/rtm-8sfp/rtm_user.c b/port/board/rtm-8sfp/rtm_user.c index c1849335f..33406a933 100644 --- a/port/board/rtm-8sfp/rtm_user.c +++ b/port/board/rtm-8sfp/rtm_user.c @@ -65,27 +65,6 @@ uint8_t rtm_get_hotswap_handle_status( uint8_t *state ) return false; } -void rtm_check_presence( uint8_t *status ) -{ - /* Due to a hardware limitation in the AFC board, we can't rely on reading the PS signal - since this pin doesn't have a pull-up resistor, it's always read as 0. - A very dirty workaround is to 'ping' the RTM IO Expander(PCA9554), if it responds, then the board is connected */ - rtm_enable_i2c(); - - uint8_t i2c_addr, i2c_interface; - uint8_t dumb; - - /* Defaults to absent - in case of I2C failure */ - *status = HOTSWAP_STATE_URTM_ABSENT; - - if (i2c_take_by_chipid( CHIP_ID_RTM_PCA9554, &i2c_addr, &i2c_interface, 100)) { - if (xI2CMasterRead( i2c_interface, i2c_addr, &dumb, 1)) { - *status = HOTSWAP_STATE_URTM_PRSENT; - } - i2c_give(i2c_interface); - } -} - void rtm_hardware_init( void ) { rtm_enable_i2c(); diff --git a/port/board/rtm-8sfp/rtm_user.h b/port/board/rtm-8sfp/rtm_user.h index 9ceb47e3e..7cc352acd 100644 --- a/port/board/rtm-8sfp/rtm_user.h +++ b/port/board/rtm-8sfp/rtm_user.h @@ -33,7 +33,6 @@ void rtm_enable_payload_power( void ); void rtm_disable_payload_power( void ); uint8_t rtm_get_hotswap_handle_status( uint8_t *state ); -void rtm_check_presence( uint8_t *status ); void rtm_hardware_init( void ); void rtm_ctrl_led( uint8_t id, uint8_t state ); uint8_t rtm_read_led( uint8_t id ); diff --git a/port/board/rtm-lamp/rtm_user.c b/port/board/rtm-lamp/rtm_user.c index 6d2d8ab08..536eb1952 100644 --- a/port/board/rtm-lamp/rtm_user.c +++ b/port/board/rtm-lamp/rtm_user.c @@ -88,27 +88,6 @@ uint8_t rtm_get_hotswap_handle_status( uint8_t *state ) return false; } -void rtm_check_presence( uint8_t *status ) -{ - /* Due to a hardware limitation in the AFC board, we can't rely on reading the PS signal - since this pin doesn't have a pull-up resistor, it's always read as 0. - A very dirty workaround is to 'ping' the RTM IO Expander(PCA9554), if it responds, then the board is connected */ - rtm_enable_i2c(); - - uint8_t i2c_addr, i2c_interface; - uint8_t dumb; - - /* Defaults to absent - in case of I2C failure */ - *status = HOTSWAP_STATE_URTM_ABSENT; - - if (i2c_take_by_chipid( CHIP_ID_RTM_PCA9554_LEDS, &i2c_addr, &i2c_interface, 100)) { - if (xI2CMasterRead( i2c_interface, i2c_addr, &dumb, 1)) { - *status = HOTSWAP_STATE_URTM_PRSENT; - } - i2c_give(i2c_interface); - } -} - void rtm_hardware_init( void ) { rtm_enable_i2c(); diff --git a/port/board/rtm-lamp/rtm_user.h b/port/board/rtm-lamp/rtm_user.h index 269d2ca85..4717f39ae 100644 --- a/port/board/rtm-lamp/rtm_user.h +++ b/port/board/rtm-lamp/rtm_user.h @@ -39,7 +39,6 @@ void rtm_enable_payload_power( void ); void rtm_disable_payload_power( void ); uint8_t rtm_get_hotswap_handle_status( uint8_t *state ); -void rtm_check_presence( uint8_t *status ); void rtm_hardware_init( void ); void rtm_ctrl_led( uint8_t id, uint8_t state ); uint8_t rtm_read_led( uint8_t id ); From 6e529ad41d96a5d5466cddeece4bace45d63cdad Mon Sep 17 00:00:00 2001 From: Gustavo de Souza dos Reis Date: Thu, 14 Dec 2023 10:02:21 -0300 Subject: [PATCH 16/43] Only set the clock switch configuration when Payload Power is ON Also fix identation --- port/board/afc-v3/payload.c | 4 ++-- port/board/afc-v4/payload.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/port/board/afc-v3/payload.c b/port/board/afc-v3/payload.c index ef22c9c6e..2a3347a90 100644 --- a/port/board/afc-v3/payload.c +++ b/port/board/afc-v3/payload.c @@ -249,8 +249,8 @@ void vTaskPayload( void *pvParameters ) if( current_evt & PAYLOAD_MESSAGE_CLOCK_CONFIG ){ eeprom_24xx02_write(CHIP_ID_RTC_EEPROM, 0x0, clock_config, 16, 10); if (PAYLOAD_FPGA_ON){ - adn4604_reset(); - clock_configuration(); + adn4604_reset(); + clock_configuration(); } xEventGroupClearBits(amc_payload_evt, PAYLOAD_MESSAGE_CLOCK_CONFIG); } diff --git a/port/board/afc-v4/payload.c b/port/board/afc-v4/payload.c index 4d1e8fffe..7abac602a 100644 --- a/port/board/afc-v4/payload.c +++ b/port/board/afc-v4/payload.c @@ -357,9 +357,9 @@ void vTaskPayload( void *pvParameters ) * and write the new configuration in EEPROM */ if( current_evt & PAYLOAD_MESSAGE_CLOCK_CONFIG ){ - clock_switch_write_reg(clock_config); - if (PAYLOAD_FPGA_ON) { eeprom_24xx02_write(CHIP_ID_RTC_EEPROM, 0x0, clock_config, 16, 10); + if (PAYLOAD_FPGA_ON) { + clock_switch_write_reg(clock_config); } xEventGroupClearBits(amc_payload_evt, PAYLOAD_MESSAGE_CLOCK_CONFIG); } From 0a6e555ab1fff57b0163a86df331a4240c2d0d8c Mon Sep 17 00:00:00 2001 From: Gustavo de Souza dos Reis Date: Fri, 5 Jan 2024 08:51:14 -0300 Subject: [PATCH 17/43] Move the count check to be done after the fru_write call Since we are checking how many chars was writen and using this as diagnostics for the fru_write call, the count check must be made only if the function is called. In this way, the check must be in the same condition as the function call. --- modules/fru.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/modules/fru.c b/modules/fru.c index c4a469207..833bdba5b 100644 --- a/modules/fru.c +++ b/modules/fru.c @@ -334,6 +334,15 @@ IPMI_HANDLER(ipmi_storage_write_fru_data_cmd, NETFN_STORAGE, IPMI_WRITE_FRU_DATA /* Write data to the FRU */ count = fru_write( id, &req->data[3], offset, req->data_len - 3); + /* + * If count == 0, it may indicate that the fru_write function + * failed somehow. + */ + + if (count == 0) { + rsp->completion_code = IPMI_CC_UNSPECIFIED_ERROR; + return ; + } /* Count written (1 based) */ rsp->data[len++] = count +1; } else { @@ -342,14 +351,5 @@ IPMI_HANDLER(ipmi_storage_write_fru_data_cmd, NETFN_STORAGE, IPMI_WRITE_FRU_DATA rsp->completion_code = IPMI_CC_PARAM_OUT_OF_RANGE; } - /* - * If count == 0, it may indicate that the fru_write function - * failed somehow. - */ - - if (count == 0) { - rsp->completion_code = IPMI_CC_UNSPECIFIED_ERROR; - return ; - } rsp->data_len = len; } From c4983210b5b6e1146ee648d610de9e160c584404 Mon Sep 17 00:00:00 2001 From: Gustavo de Souza dos Reis Date: Fri, 5 Jan 2024 12:44:05 -0300 Subject: [PATCH 18/43] Check if the clock configuration is successfully applied before FPGA_ON --- port/board/afc-v4/payload.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/port/board/afc-v4/payload.c b/port/board/afc-v4/payload.c index 7abac602a..e18772865 100644 --- a/port/board/afc-v4/payload.c +++ b/port/board/afc-v4/payload.c @@ -345,10 +345,10 @@ void vTaskPayload( void *pvParameters ) */ if (state == PAYLOAD_QUIESCED) { - QUIESCED_req = 0; - } else { - QUIESCED_req = 1; - } + QUIESCED_req = 0; + } else { + QUIESCED_req = 1; + } xEventGroupClearBits( amc_payload_evt, PAYLOAD_MESSAGE_QUIESCE ); } @@ -413,8 +413,10 @@ void vTaskPayload( void *pvParameters ) case PAYLOAD_STATE_FPGA_SETUP: /* Configure the clock switch according to the configuration saved in EEPROM*/ eeprom_24xx02_read(CHIP_ID_RTC_EEPROM, 0x0, clock_config, 16, 10); - clock_switch_write_reg(clock_config); - new_state = PAYLOAD_FPGA_ON; + /* Only change the state if the clock config is efective*/ + if (clock_switch_write_reg(clock_config)) { + new_state = PAYLOAD_FPGA_ON; + } break; case PAYLOAD_FPGA_ON: From a539e69a26c5668f280a27840c0f0ecb7a90d3c4 Mon Sep 17 00:00:00 2001 From: Gustavo de Souza dos Reis Date: Tue, 9 Jan 2024 13:37:00 -0300 Subject: [PATCH 19/43] Rename error librarie to avoid conflicts --- modules/CMakeLists.txt | 2 +- modules/max116xx.h | 2 +- modules/mcp23016.h | 2 +- modules/{error.c => mmc_error.c} | 4 ++-- modules/{error.h => mmc_error.h} | 6 +++--- 5 files changed, 8 insertions(+), 8 deletions(-) rename modules/{error.c => mmc_error.c} (97%) rename modules/{error.h => mmc_error.h} (96%) diff --git a/modules/CMakeLists.txt b/modules/CMakeLists.txt index dd36ea369..59fb6814a 100644 --- a/modules/CMakeLists.txt +++ b/modules/CMakeLists.txt @@ -8,7 +8,7 @@ set(PROJ_SRCS ${PROJ_SRCS} ${MODULE_PATH}/i2c.c) set(PROJ_SRCS ${PROJ_SRCS} ${MODULE_PATH}/led.c) set(PROJ_SRCS ${PROJ_SRCS} ${MODULE_PATH}/ipmb.c ${MODULE_PATH}/ipmi.c) set(PROJ_SRCS ${PROJ_SRCS} ${MODULE_PATH}/printf-stdarg.c) -set(PROJ_SRCS ${PROJ_SRCS} ${MODULE_PATH}/error.c) +set(PROJ_SRCS ${PROJ_SRCS} ${MODULE_PATH}/mmc_error.c) set(PROJ_SRCS ${PROJ_SRCS} ${MODULE_PATH}/eeprom_24xx02.c) message(STATUS "Selected modules to compile: ${TARGET_MODULES}") diff --git a/modules/max116xx.h b/modules/max116xx.h index f03c81cc1..f205cf1a3 100644 --- a/modules/max116xx.h +++ b/modules/max116xx.h @@ -31,7 +31,7 @@ #ifndef MAX116XX_H_ #define MAX116XX_H_ -#include "error.h" +#include "mmc_error.h" #include "port.h" /** diff --git a/modules/mcp23016.h b/modules/mcp23016.h index d4bdb5e87..fd5b08a88 100644 --- a/modules/mcp23016.h +++ b/modules/mcp23016.h @@ -30,7 +30,7 @@ #ifndef MCP23016_H_ #define MCP23016_H_ -#include "error.h" +#include "mmc_error.h" #include "port.h" /** diff --git a/modules/error.c b/modules/mmc_error.c similarity index 97% rename from modules/error.c rename to modules/mmc_error.c index dbaf4fbd8..ccd687df5 100644 --- a/modules/error.c +++ b/modules/mmc_error.c @@ -20,7 +20,7 @@ */ /** - * @file error.c + * @file mmc_error.c * @author Augusto Fraga Giachero * * @brief Error handling functions @@ -28,7 +28,7 @@ * @ingroup error */ #include -#include "error.h" +#include "mmc_error.h" static const char* mmc_error_strings[] = { [MMC_OK] = "No error", diff --git a/modules/error.h b/modules/mmc_error.h similarity index 96% rename from modules/error.h rename to modules/mmc_error.h index acc144f8c..851dffb49 100644 --- a/modules/error.h +++ b/modules/mmc_error.h @@ -19,13 +19,13 @@ * @license GPL-3.0+ */ -#ifndef ERROR_H_ -#define ERROR_H_ +#ifndef MMC_ERROR_H_ +#define MMC_ERROR_H_ #include /** - * @file error.h + * @file mmc_error.h * @author Augusto Fraga Giachero * * @brief Error handling functions and codes From 0d9291663b3c0a4280c4b3cacbd2bf4b4bfeca55 Mon Sep 17 00:00:00 2001 From: Gustavo de Souza dos Reis Date: Wed, 17 Jan 2024 10:03:35 -0300 Subject: [PATCH 20/43] Always write fru info in eeprom --- modules/fru.c | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/modules/fru.c b/modules/fru.c index 833bdba5b..576c5c962 100644 --- a/modules/fru.c +++ b/modules/fru.c @@ -255,13 +255,7 @@ size_t fru_write( uint8_t id, uint8_t *tx_buff, uint16_t offset, size_t len ) if ( id >= FRU_COUNT ) { return 0; } - - if ( fru[id].runtime ) { - memcpy( &fru[id].buffer[offset], tx_buff, len ); - ret_val = len; - } else { - ret_val = fru[id].cfg.write_f( fru[id].cfg.eeprom_id, offset, tx_buff, len, 10 ); - } + ret_val = fru[id].cfg.write_f( fru[id].cfg.eeprom_id, offset, tx_buff, len, 10 ); return ret_val; } From 5d517dc2c9311cef3d91238a2bbc974d588e96e6 Mon Sep 17 00:00:00 2001 From: Gustavo de Souza dos Reis Date: Fri, 6 Oct 2023 12:44:05 -0300 Subject: [PATCH 21/43] Add script to set the Serial Number and standardize the other fields --- scripts/set-fru-info.py | 57 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 57 insertions(+) create mode 100755 scripts/set-fru-info.py diff --git a/scripts/set-fru-info.py b/scripts/set-fru-info.py new file mode 100755 index 000000000..502dc171e --- /dev/null +++ b/scripts/set-fru-info.py @@ -0,0 +1,57 @@ +#!/usr/bin/env python3 +# +# AFCv4 FRU fix (serial number and Zone3InterfaceCompatibility fields) +# Copyright (C) 2024 CNPEM LNLS +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . + +import frugy +from frugy.fru import Fru +import argparse + +parser = argparse.ArgumentParser(description="Corrects AFCv4 FRU records") +parser.add_argument("--bin-in", type=str, help="Binary file from FRU read", required=True) +parser.add_argument("--bin-out", type=str, help="Binary file for FRU write", required=True) +parser.add_argument("--set-serial-number", metavar="serial_number", type=str, help="Serial Number", required=False) +parser.add_argument("--set-board-version", metavar="board_version", type=str, help="Board Version", default='4.0.2' ,required=False) +parser.add_argument("--save-yml", type=str, help="Save YML configuration file", required=False) + +args= parser.parse_args() + +fru = Fru() +fru.load_bin(args.bin_in) +yaml = fru.to_dict() +yaml['BoardInfo']['manufacturer']='Creotech' +yaml['BoardInfo']['product_name']='AFC:' + args.set_board_version +yaml['BoardInfo']['part_number']='AFC' +yaml['BoardInfo']['fru_file_id']='AFCFRU' +yaml['BoardInfo']['manufacturer']='CNPEM' +yaml['ProductInfo']['manufacturer']='CNPEM' +yaml['ProductInfo']['product_name']='AFC' +yaml['ProductInfo']['part_number']='AFC' +yaml['ProductInfo']['version']=args.set_board_version +yaml['ProductInfo']['asset_tag']='No tag' +yaml['ProductInfo']['fru_file_id']='AFCFRU' +yaml['MultirecordArea'][3]['identifier_type'] = 'CLASS_ID' +yaml['MultirecordArea'][3]['identifier_body'] = ['D1.3'] +if(args.set_serial_number != None): + yaml['BoardInfo']['serial_number']=args.set_serial_number + yaml['ProductInfo']['serial_number']=args.set_serial_number + +fru.update(yaml) + +if(args.save_yml): + fru.save_yaml(args.save_yml) + +fru.save_bin(args.bin_out) From 8bb07f974f30f2d04f27ccd8c838346c943cdb31 Mon Sep 17 00:00:00 2001 From: Gustavo de Souza dos Reis Date: Mon, 8 Jan 2024 08:18:20 -0300 Subject: [PATCH 22/43] Modify adn4604 config functions to return error codes --- modules/adn4604.c | 45 +++++++++++++++++++++++++++---------- modules/adn4604.h | 14 +++++++----- port/board/afc-v3/payload.c | 30 ++++++++++++++++--------- port/board/afc-v3/payload.h | 3 ++- 4 files changed, 63 insertions(+), 29 deletions(-) diff --git a/modules/adn4604.c b/modules/adn4604.c index 21d1baca3..ca14313f5 100644 --- a/modules/adn4604.c +++ b/modules/adn4604.c @@ -39,10 +39,11 @@ adn_connect_map_t con; -void adn4604_tx_control( uint8_t output, uint8_t tx_mode ) +mmc_err adn4604_tx_control( uint8_t output, uint8_t tx_mode ) { uint8_t i2c_addr, i2c_interf; uint8_t enable[2]; + uint8_t tx_len = 0; /* TX Enable registers have an 0x20 offset from their value */ enable[0] = 0x20 + output; @@ -69,56 +70,72 @@ void adn4604_tx_control( uint8_t output, uint8_t tx_mode ) enable[1] = tx_mode << 4; if (i2c_take_by_chipid(CHIP_ID_ADN, &i2c_addr, &i2c_interf, (TickType_t)10) ) { - xI2CMasterWrite( i2c_interf, i2c_addr, enable, sizeof(enable) ); + tx_len = xI2CMasterWrite( i2c_interf, i2c_addr, enable, sizeof(enable) ); i2c_give(i2c_interf); } + + if (!tx_len) return MMC_TIMEOUT_ERR; + return MMC_OK; } -void adn4604_update( void ) +mmc_err adn4604_update( void ) { uint8_t i2c_addr, i2c_interf; uint8_t update[2] = { ADN_XPT_UPDATE_REG, 0x01 }; + uint8_t tx_len = 0; if (i2c_take_by_chipid(CHIP_ID_ADN, &i2c_addr, &i2c_interf, (TickType_t)10) ) { - xI2CMasterWrite( i2c_interf, i2c_addr, update, sizeof(update) ); + tx_len = xI2CMasterWrite( i2c_interf, i2c_addr, update, sizeof(update) ); i2c_give(i2c_interf); } + + if (!tx_len) return MMC_TIMEOUT_ERR; + return MMC_OK; } -void adn4604_reset( void ) +mmc_err adn4604_reset( void ) { uint8_t i2c_addr, i2c_interf; uint8_t update[2] = { ADN_RESET_REG, 0x01 }; + uint8_t tx_len = 0; if (i2c_take_by_chipid(CHIP_ID_ADN, &i2c_addr, &i2c_interf, (TickType_t)10) ) { - xI2CMasterWrite( i2c_interf, i2c_addr, update, sizeof(update) ); + tx_len = xI2CMasterWrite( i2c_interf, i2c_addr, update, sizeof(update) ); i2c_give(i2c_interf); } + if (!tx_len) return MMC_TIMEOUT_ERR; + return MMC_OK; } -void adn4604_xpt_config( uint8_t map, adn_connect_map_t xpt_con ) +mmc_err adn4604_xpt_config( uint8_t map, adn_connect_map_t xpt_con ) { uint8_t i2c_addr, i2c_interf; + uint8_t tx_len = 0; adn_connect_cfg_t cfg = { map, xpt_con }; if (i2c_take_by_chipid(CHIP_ID_ADN, &i2c_addr, &i2c_interf, (TickType_t)10) ) { - xI2CMasterWrite( i2c_interf, i2c_addr, (uint8_t *)&cfg, sizeof(cfg) ); + tx_len = xI2CMasterWrite( i2c_interf, i2c_addr, (uint8_t *)&cfg, sizeof(cfg) ); i2c_give(i2c_interf); } + if (!tx_len) return MMC_TIMEOUT_ERR; + return MMC_OK; } -void adn4604_active_map( uint8_t map ) +mmc_err adn4604_active_map( uint8_t map ) { uint8_t i2c_addr, i2c_interf; + uint8_t tx_len = 0; /* Select the active map */ uint8_t map_sel[2] = { ADN_XPT_MAP_TABLE_SEL_REG, map }; if ( i2c_take_by_chipid( CHIP_ID_ADN, &i2c_addr, &i2c_interf, (TickType_t)10 ) ) { - xI2CMasterWrite( i2c_interf, i2c_addr, map_sel, sizeof(map_sel) ); + tx_len = xI2CMasterWrite( i2c_interf, i2c_addr, map_sel, sizeof(map_sel) ); i2c_give( i2c_interf ); } + if (!tx_len) return MMC_TIMEOUT_ERR; + return MMC_OK; } adn_connect_map_t adn4604_out_status( void ) @@ -139,13 +156,17 @@ adn_connect_map_t adn4604_out_status( void ) return stat_map; } -void adn4604_termination_ctl( uint8_t cfg ) +mmc_err adn4604_termination_ctl( uint8_t cfg ) { uint8_t i2c_addr, i2c_interf; uint8_t msg[2] = { ADN_TERMINATION_CTL_REG, (cfg & 0xF0) }; + uint8_t tx_len = 0; if ( i2c_take_by_chipid( CHIP_ID_ADN, &i2c_addr, &i2c_interf, (TickType_t)10 ) ) { - xI2CMasterWrite( i2c_interf, i2c_addr, msg, sizeof(msg) ); + tx_len = xI2CMasterWrite( i2c_interf, i2c_addr, msg, sizeof(msg) ); i2c_give( i2c_interf ); } + if (!tx_len) return MMC_TIMEOUT_ERR; + return MMC_OK; + } diff --git a/modules/adn4604.h b/modules/adn4604.h index f6b01ea99..88dbe09a5 100644 --- a/modules/adn4604.h +++ b/modules/adn4604.h @@ -36,6 +36,8 @@ #ifndef ADN4604_H_ #define ADN4604_H_ +#include "mmc_error.h" + typedef struct __attribute__((__packed__)) { #if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ uint8_t out1:4, @@ -118,7 +120,7 @@ enum adn4604_tx_ctl { * @param output Output number (0 to 15) * @param tx_mode Selected mode: (TX_DISABLED, TX_STANDBY, TX_SQUELCHED or TX_ENABLED) */ -void adn4604_tx_control( uint8_t output, uint8_t tx_mode ); +mmc_err adn4604_tx_control( uint8_t output, uint8_t tx_mode ); /** * @brief Activates the current stored configuration @@ -126,12 +128,12 @@ void adn4604_tx_control( uint8_t output, uint8_t tx_mode ); * @note The Update pin has precedence over the software register, so if the Update pin is asserted, but the low-to-high step doesn't occur, you won't be able to update the IC configuration * */ -void adn4604_update( void ); +mmc_err adn4604_update( void ); /** * @brief ADN4604 Software Reset */ -void adn4604_reset( void ); +mmc_err adn4604_reset( void ); /** * @brief Configures the cross-connection map @@ -139,14 +141,14 @@ void adn4604_reset( void ); * @param map Selected map to configure (0 or 1) * @param xpt_con Outputs assignment */ -void adn4604_xpt_config( uint8_t map, adn_connect_map_t xpt_con ); +mmc_err adn4604_xpt_config( uint8_t map, adn_connect_map_t xpt_con ); /** * @brief Sets the active map on the IC * * @param map Selected map (0 or 1) */ -void adn4604_active_map( uint8_t map ); +mmc_err adn4604_active_map( uint8_t map ); /** * @brief Reads the outputs current connections @@ -160,6 +162,6 @@ adn_connect_map_t adn4604_out_status( void ); * * @param cfg Selected in/outputs (separated in quadrants defined in #adn4604_term_ctl) */ -void adn4604_termination_ctl( uint8_t cfg ); +mmc_err adn4604_termination_ctl( uint8_t cfg ); #endif diff --git a/port/board/afc-v3/payload.c b/port/board/afc-v3/payload.c index 2a3347a90..326e388de 100644 --- a/port/board/afc-v3/payload.c +++ b/port/board/afc-v3/payload.c @@ -267,10 +267,10 @@ void vTaskPayload( void *pvParameters ) */ if (state == PAYLOAD_QUIESCED) { - QUIESCED_req = 0; - } else { - QUIESCED_req = 1; - } + QUIESCED_req = 0; + } else { + QUIESCED_req = 1; + } xEventGroupClearBits( amc_payload_evt, PAYLOAD_MESSAGE_QUIESCE ); } @@ -313,9 +313,12 @@ void vTaskPayload( void *pvParameters ) case PAYLOAD_STATE_FPGA_SETUP: #ifdef MODULE_ADN4604 /* Configure clock switch */ - clock_configuration(); -#endif + if (clock_configuration() == MMC_OK) { + new_state = PAYLOAD_FPGA_ON; + } +#else new_state = PAYLOAD_FPGA_ON; +#endif break; case PAYLOAD_FPGA_ON: @@ -477,9 +480,10 @@ uint8_t payload_hpm_activate_firmware( void ) return IPMI_CC_OK; } -void clock_configuration() +mmc_err clock_configuration( void ) { adn_connect_map_t con; + mmc_err error; /* Read the clock configuration from the eeprom */ eeprom_24xx02_read(CHIP_ID_RTC_EEPROM, 0x0, clock_config, 16, 10); @@ -530,7 +534,10 @@ void clock_configuration() con.out14 = clock_config[14] & 0x0F; con.out15 = clock_config[15] & 0x0F; - adn4604_xpt_config( ADN_XPT_MAP0_CON_REG, con ); + error = adn4604_xpt_config( ADN_XPT_MAP0_CON_REG, con ); + if (error != MMC_OK) { + return error; + } /* Enable desired outputs */ for ( uint8_t i = 0; i < 16; i++ ) { @@ -541,8 +548,11 @@ void clock_configuration() } } - adn4604_active_map( ADN_XPT_MAP0 ); + error = adn4604_active_map( ADN_XPT_MAP0 ); + if (error != MMC_OK) { + return error; + } - adn4604_update(); + return adn4604_update(); } #endif diff --git a/port/board/afc-v3/payload.h b/port/board/afc-v3/payload.h index 3746e8e2e..1f7e68c6a 100644 --- a/port/board/afc-v3/payload.h +++ b/port/board/afc-v3/payload.h @@ -37,6 +37,7 @@ #define PAYLOAD_H_ #include "event_groups.h" +#include "mmc_error.h" /** * @brief Payload state machine state numbers @@ -114,7 +115,7 @@ uint8_t payload_hpm_activate_firmware( void ); * @brief Configure the clock switch interconects according to the configuration * saved in EEPROM */ -void clock_configuration(); +mmc_err clock_configuration( void ); #endif /* IPMI_PAYLOAD_H_ */ From 7a4d221aaae2fcba04b4c6b98552052e802a14a9 Mon Sep 17 00:00:00 2001 From: Gustavo de Souza dos Reis Date: Mon, 29 Jan 2024 13:10:01 -0300 Subject: [PATCH 23/43] Fix the if statement for correctly use the standalone mode --- modules/sensors/hotswap.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/modules/sensors/hotswap.c b/modules/sensors/hotswap.c index 4a5cdab6c..375733202 100644 --- a/modules/sensors/hotswap.c +++ b/modules/sensors/hotswap.c @@ -153,7 +153,7 @@ void vTaskHotSwap( void *Parameters ) hotswap_clear_mask_bit( HOTSWAP_AMC, 1 << (!new_state_amc) ); old_state_amc = new_state_amc; } - if (!standalone_mode) { + if (standalone_mode) { old_state_amc = new_state_amc; } } @@ -173,13 +173,13 @@ void vTaskHotSwap( void *Parameters ) if ( new_state_rtm == 0 ) { printf("RTM Hotswap handle pressed!\n"); - if (!standalone_mode) { + if (standalone_mode) { payload_send_message(FRU_RTM, PAYLOAD_MESSAGE_RTM_ENABLE); } } else { printf("RTM Hotswap handle released!\n"); - if (!standalone_mode) { + if (standalone_mode) { payload_send_message(FRU_RTM, PAYLOAD_MESSAGE_QUIESCE); } @@ -190,7 +190,7 @@ void vTaskHotSwap( void *Parameters ) old_state_rtm = new_state_rtm; } - if (!standalone_mode) { + if (standalone_mode) { old_state_rtm = new_state_rtm; } From 3f659b99614236f1789093f50c88363b098080cd Mon Sep 17 00:00:00 2001 From: Gustavo de Souza dos Reis Date: Fri, 26 Jan 2024 14:58:09 -0300 Subject: [PATCH 24/43] Fix FRU reading / writing operations Add a non zero timeout value so FRU read operations fail less often, fix FRU writing (at24mac) function to wait until the EEPROM is not busy before proceeding to the next block write. --- modules/at24mac.c | 28 ++++++++++++++++++++++------ modules/fru.c | 18 +++++++++--------- 2 files changed, 31 insertions(+), 15 deletions(-) diff --git a/modules/at24mac.c b/modules/at24mac.c index de54864f5..a0d8c5f10 100644 --- a/modules/at24mac.c +++ b/modules/at24mac.c @@ -43,6 +43,10 @@ size_t at24mac_read( uint8_t id, uint16_t address, uint8_t *rx_data, size_t buf_ uint8_t i2c_interface; uint8_t rx_len = 0; + if (rx_data == NULL) { + return 0; + } + if (i2c_take_by_chipid( id, &i2c_addr, &i2c_interface, timeout ) && ( rx_data != NULL ) ) { rx_len = xI2CMasterWriteRead( i2c_interface, i2c_addr, address, rx_data, buf_len ); i2c_give( i2c_interface ); @@ -88,11 +92,12 @@ size_t at24mac_write( uint8_t id, uint16_t address, uint8_t *tx_data, size_t buf uint8_t i2c_interface; uint8_t bytes_to_write; uint8_t curr_addr; + uint8_t i2c_written = 0; uint8_t page_buf[17]; size_t tx_len = 0; - if (i2c_take_by_chipid( id, &i2c_addr, &i2c_interface, timeout ) && ( tx_data != NULL ) ) { + if (tx_data != NULL) { curr_addr = address; while (tx_len < buf_len) { @@ -104,12 +109,23 @@ size_t at24mac_write( uint8_t id, uint16_t address, uint8_t *tx_data, size_t buf page_buf[0] = curr_addr; memcpy(&page_buf[1], tx_data+tx_len, bytes_to_write); - /* Write the data */ - tx_len += xI2CMasterWrite( i2c_interface, i2c_addr, &page_buf[0] , bytes_to_write+1 ); - tx_len -= 1; /* Remove byte address from data written size */ - curr_addr += bytes_to_write; + if (i2c_take_by_chipid( id, &i2c_addr, &i2c_interface, timeout )) { + /* Write the data */ + i2c_written = xI2CMasterWrite( i2c_interface, i2c_addr, &page_buf[0] , bytes_to_write+1 ); + /* When trying to write, the EEPROM will reply with NACKs if it's busy. + * If the i2c receives a NACK when trying to write, the function returns only + * the number of bytes successfully written, and we should increment only this value + * in tx_len and in curr_addr */ + + if (i2c_written) { + tx_len += i2c_written - 1; /* Remove byte address from data written size */ + curr_addr += i2c_written - 1; + i2c_written = 0; + } + i2c_give( i2c_interface ); + } + vTaskDelay(pdMS_TO_TICKS(1)); /* Avoid too much unnecessary I2C trafic*/ } - i2c_give( i2c_interface ); } return tx_len; diff --git a/modules/fru.c b/modules/fru.c index 576c5c962..400789250 100644 --- a/modules/fru.c +++ b/modules/fru.c @@ -70,7 +70,7 @@ uint8_t fru_check_integrity( uint8_t id, size_t *fru_size ) if (fru[id].runtime) { memcpy( &common_header[0], &fru[id].buffer[0], 8); } else { - fru[id].cfg.read_f( fru[id].cfg.eeprom_id, 0x00, &common_header[0], 8, 0 ); + fru[id].cfg.read_f( fru[id].cfg.eeprom_id, 0x00, &common_header[0], 8, 10 ); } printf("[FRU][%s] Asserting FRU information integrity\n", id == FRU_AMC ? "AMC" : "RTM"); @@ -91,14 +91,14 @@ uint8_t fru_check_integrity( uint8_t id, size_t *fru_size ) if (fru[id].runtime) { rec_len = fru[id].buffer[chassis_off+1]; } else { - fru[id].cfg.read_f( fru[id].cfg.eeprom_id, chassis_off+1, &rec_len, 1, 0 ); + fru[id].cfg.read_f( fru[id].cfg.eeprom_id, chassis_off+1, &rec_len, 1, 10 ); } rec_len *= 8; if (rec_len > 0) { if (fru[id].runtime) { memcpy( &rec_buff[0], &fru[id].buffer[chassis_off], rec_len); } else { - fru[id].cfg.read_f( fru[id].cfg.eeprom_id, chassis_off, &rec_buff[0], rec_len, 0 ); + fru[id].cfg.read_f( fru[id].cfg.eeprom_id, chassis_off, &rec_buff[0], rec_len, 10 ); } if ( !((calculate_chksum( &rec_buff[0], rec_len ) == 0) && rec_buff[0] == 1) ) { /* Wrong checksum */ @@ -116,7 +116,7 @@ uint8_t fru_check_integrity( uint8_t id, size_t *fru_size ) if (fru[id].runtime) { rec_len = fru[id].buffer[board_off+1]; } else { - fru[id].cfg.read_f( fru[id].cfg.eeprom_id, board_off+1, &rec_len, 1, 0 ); + fru[id].cfg.read_f( fru[id].cfg.eeprom_id, board_off+1, &rec_len, 1, 10 ); } rec_len *= 8; @@ -124,7 +124,7 @@ uint8_t fru_check_integrity( uint8_t id, size_t *fru_size ) if (fru[id].runtime) { memcpy( &rec_buff[0], &fru[id].buffer[board_off], rec_len); } else { - fru[id].cfg.read_f( fru[id].cfg.eeprom_id, board_off, &rec_buff[0], rec_len, 0 ); + fru[id].cfg.read_f( fru[id].cfg.eeprom_id, board_off, &rec_buff[0], rec_len, 10 ); } if ( !((calculate_chksum( &rec_buff[0], rec_len ) == 0) && rec_buff[0] == 1) ) { /* Wrong checksum */ @@ -142,7 +142,7 @@ uint8_t fru_check_integrity( uint8_t id, size_t *fru_size ) if (fru[id].runtime) { rec_len = fru[id].buffer[product_off+1]; } else { - fru[id].cfg.read_f( fru[id].cfg.eeprom_id, product_off+1, &rec_len, 1, 0 ); + fru[id].cfg.read_f( fru[id].cfg.eeprom_id, product_off+1, &rec_len, 1, 10 ); } rec_len *= 8; @@ -150,7 +150,7 @@ uint8_t fru_check_integrity( uint8_t id, size_t *fru_size ) if (fru[id].runtime) { memcpy( &rec_buff[0], &fru[id].buffer[product_off], rec_len); } else { - fru[id].cfg.read_f( fru[id].cfg.eeprom_id, product_off, &rec_buff[0], rec_len, 0 ); + fru[id].cfg.read_f( fru[id].cfg.eeprom_id, product_off, &rec_buff[0], rec_len, 10 ); } if ( !((calculate_chksum( &rec_buff[0], rec_len ) == 0 ) && rec_buff[0] == 1) ) { /* Wrong checksum */ @@ -172,7 +172,7 @@ uint8_t fru_check_integrity( uint8_t id, size_t *fru_size ) if (fru[id].runtime) { memcpy( &rec_buff[0], &fru[id].buffer[multirec_off], 5); } else { - fru[id].cfg.read_f( fru[id].cfg.eeprom_id, multirec_off, &rec_buff[0], 5, 0 ); + fru[id].cfg.read_f( fru[id].cfg.eeprom_id, multirec_off, &rec_buff[0], 5, 10 ); } /* Calculate Multirecord header checksum */ if ( !(calculate_chksum( &rec_buff[0], 5 ) == 0) ) { @@ -190,7 +190,7 @@ uint8_t fru_check_integrity( uint8_t id, size_t *fru_size ) if (fru[id].runtime) { memcpy( &rec_buff[0], &fru[id].buffer[multirec_off], rec_len ); } else { - fru[id].cfg.read_f( fru[id].cfg.eeprom_id, multirec_off, &rec_buff[0], rec_len, 0 ); + fru[id].cfg.read_f( fru[id].cfg.eeprom_id, multirec_off, &rec_buff[0], rec_len, 10 ); } if ( !((calculate_chksum( &rec_buff[0], rec_len ) == rec_chksum)) ) { /* Wrong checksum */ From 028b2531821d6fc505e41b1875c065f5d283a3d3 Mon Sep 17 00:00:00 2001 From: Gustavo de Souza dos Reis Date: Thu, 15 Feb 2024 10:14:27 -0300 Subject: [PATCH 25/43] Change lpc17 i2c driver to accept any size of command in MasterCmdRead --- modules/adn4604.c | 4 +++- modules/at24mac.c | 12 +++++------- modules/cdce906.c | 3 ++- modules/eeprom_24xx02.c | 2 +- modules/eeprom_24xx64.c | 2 +- modules/mcp23016.c | 4 ++-- modules/pca9554.c | 2 +- modules/sensors/ina220.c | 2 +- modules/sensors/ina3221.c | 2 +- modules/sensors/max6642.c | 19 ++++++++++++------- port/ucontroller/nxp/lpc17xx/lpc17_i2c.c | 12 ++++++++++++ port/ucontroller/nxp/lpc17xx/lpc17_i2c.h | 3 +-- 12 files changed, 42 insertions(+), 25 deletions(-) diff --git a/modules/adn4604.c b/modules/adn4604.c index ca14313f5..395fa2cb7 100644 --- a/modules/adn4604.c +++ b/modules/adn4604.c @@ -142,13 +142,15 @@ adn_connect_map_t adn4604_out_status( void ) { uint8_t i2c_addr, i2c_interf; uint8_t i; + uint8_t cmd; adn_connect_map_t stat_map = {0}; if ( i2c_take_by_chipid( CHIP_ID_ADN, &i2c_addr, &i2c_interf, (TickType_t)10 ) ) { /* Read all outputs status */ for ( i = 0; i < 8; i++ ) { - xI2CMasterWriteRead( i2c_interf, i2c_addr, ADN_XPT_STATUS_REG+i, (uint8_t *)(&stat_map)+i, 1 ); + cmd = ADN_XPT_STATUS_REG+i; + xI2CMasterWriteRead( i2c_interf, i2c_addr, &cmd, 1, (uint8_t *)(&stat_map)+i, 1 ); } i2c_give( i2c_interf ); } diff --git a/modules/at24mac.c b/modules/at24mac.c index a0d8c5f10..fdfb84871 100644 --- a/modules/at24mac.c +++ b/modules/at24mac.c @@ -43,12 +43,8 @@ size_t at24mac_read( uint8_t id, uint16_t address, uint8_t *rx_data, size_t buf_ uint8_t i2c_interface; uint8_t rx_len = 0; - if (rx_data == NULL) { - return 0; - } - if (i2c_take_by_chipid( id, &i2c_addr, &i2c_interface, timeout ) && ( rx_data != NULL ) ) { - rx_len = xI2CMasterWriteRead( i2c_interface, i2c_addr, address, rx_data, buf_len ); + rx_len = xI2CMasterWriteRead( i2c_interface, i2c_addr, (uint8_t *)&address, 1, rx_data, buf_len ); i2c_give( i2c_interface ); } @@ -60,9 +56,10 @@ size_t at24mac_read_serial_num( uint8_t id, uint8_t *rx_data, size_t buf_len, ui uint8_t i2c_addr; uint8_t i2c_interface; uint8_t rx_len = 0; + const uint8_t cmd = AT24MAC_ID_ADDR; if (i2c_take_by_chipid( id, &i2c_addr, &i2c_interface, timeout ) && ( rx_data != NULL ) ) { - rx_len = xI2CMasterWriteRead( i2c_interface, i2c_addr+8, AT24MAC_ID_ADDR, rx_data, buf_len); + rx_len = xI2CMasterWriteRead( i2c_interface, i2c_addr+8, &cmd, 1, rx_data, buf_len); i2c_give( i2c_interface ); } @@ -75,10 +72,11 @@ size_t at24mac_read_eui( uint8_t id, uint8_t *rx_data, size_t buf_len, uint32_t uint8_t i2c_addr; uint8_t i2c_interface; uint8_t rx_len = 0; + const uint8_t cmd = AT24MAC_EUI_ADDR; if (i2c_take_by_chipid( id, &i2c_addr, &i2c_interface, timeout ) && ( rx_data != NULL ) ) { - rx_len = xI2CMasterWriteRead( i2c_interface, i2c_addr+8, AT24MAC_EUI_ADDR, rx_data, buf_len); + rx_len = xI2CMasterWriteRead( i2c_interface, i2c_addr+8, &cmd, 1, rx_data, buf_len); i2c_give( i2c_interface ); } diff --git a/modules/cdce906.c b/modules/cdce906.c index a1fe628be..8e8367e8f 100644 --- a/modules/cdce906.c +++ b/modules/cdce906.c @@ -568,9 +568,10 @@ int cdce906_read_cfg(uint8_t chip_id, cdce906_cfg* cfg) uint8_t i2c_id; int i2c_trans = 0; int ret = 0; + const uint8_t cmd = 0x00; if (i2c_take_by_chipid(chip_id, &i2c_addr, &i2c_id, (TickType_t)10)) { - i2c_trans = xI2CMasterWriteRead(i2c_id, i2c_addr, 0x00, data, sizeof(data)); + i2c_trans = xI2CMasterWriteRead(i2c_id, i2c_addr, &cmd, 1, data, sizeof(data)); i2c_give(i2c_id); } diff --git a/modules/eeprom_24xx02.c b/modules/eeprom_24xx02.c index ad1d7c7ff..9fb16a3b2 100644 --- a/modules/eeprom_24xx02.c +++ b/modules/eeprom_24xx02.c @@ -48,7 +48,7 @@ size_t eeprom_24xx02_read( uint8_t id, uint16_t address, uint8_t *rx_data, size_ } if (i2c_take_by_chipid( id, &i2c_addr, &i2c_interface, timeout ) ) { - rx_len = xI2CMasterWriteRead( i2c_interface, i2c_addr, address, rx_data, buf_len ); + rx_len = xI2CMasterWriteRead( i2c_interface, i2c_addr, (uint8_t *)&address, 1, rx_data, buf_len ); i2c_give( i2c_interface ); } diff --git a/modules/eeprom_24xx64.c b/modules/eeprom_24xx64.c index 8765a7f80..74c4a9775 100644 --- a/modules/eeprom_24xx64.c +++ b/modules/eeprom_24xx64.c @@ -52,7 +52,7 @@ size_t eeprom_24xx64_read( uint8_t id, uint16_t address, uint8_t *rx_data, size_ } if (i2c_take_by_chipid( id, &i2c_addr, &i2c_interface, timeout ) ) { - rx_len = xI2CMasterWriteRead (i2c_interface, i2c_addr, addr8, rx_data, buf_len); + rx_len = xI2CMasterWriteRead (i2c_interface, i2c_addr, addr8, 2, rx_data, buf_len); i2c_give( i2c_interface ); } diff --git a/modules/mcp23016.c b/modules/mcp23016.c index 1e8c35074..0253be804 100644 --- a/modules/mcp23016.c +++ b/modules/mcp23016.c @@ -56,7 +56,7 @@ static mmc_err mcp23016_read_reg ( uint8_t reg, uint8_t *readout ) } if( i2c_take_by_chipid( CHIP_ID_MCP23016, &i2c_addr, &i2c_id, (TickType_t) 10) ) { - rx_len = xI2CMasterWriteRead(i2c_id, i2c_addr, reg, data, sizeof(data)); + rx_len = xI2CMasterWriteRead(i2c_id, i2c_addr, ®, 1, data, sizeof(data)); i2c_give(i2c_id); } else { return MMC_TIMEOUT_ERR; @@ -177,7 +177,7 @@ mmc_err mcp23016_read_reg_pair ( uint8_t reg, uint16_t *readout ) { uint8_t data[2] = {0}; if( i2c_take_by_chipid( CHIP_ID_MCP23016, &i2c_addr, &i2c_id, (TickType_t) 10) ) { - rx_len = xI2CMasterWriteRead(i2c_id, i2c_addr, reg, data, sizeof(data)); + rx_len = xI2CMasterWriteRead(i2c_id, i2c_addr, ®, 1, data, sizeof(data)); i2c_give(i2c_id); } else { return MMC_TIMEOUT_ERR; diff --git a/modules/pca9554.c b/modules/pca9554.c index be8922db8..bcf708eb4 100644 --- a/modules/pca9554.c +++ b/modules/pca9554.c @@ -57,7 +57,7 @@ static uint8_t pca9554_read_reg ( uint8_t chip_id, uint8_t reg, uint8_t *readout } if( i2c_take_by_chipid( chip_id, &i2c_addr, &i2c_id, (TickType_t) 10) ) { - rx_len = xI2CMasterWriteRead(i2c_id, i2c_addr, reg, readout, 1); + rx_len = xI2CMasterWriteRead(i2c_id, i2c_addr, ®, 1, readout, 1); i2c_give(i2c_id); } return rx_len; diff --git a/modules/sensors/ina220.c b/modules/sensors/ina220.c index be0890cfa..1353006fa 100644 --- a/modules/sensors/ina220.c +++ b/modules/sensors/ina220.c @@ -140,7 +140,7 @@ Bool ina220_readvalue( ina220_data_t * data, uint8_t reg, uint16_t *read ) if( i2c_take_by_chipid( data->sensor->chipid, &i2c_addr, &i2c_interf, portMAX_DELAY) == pdTRUE ) { - xI2CMasterWriteRead( i2c_interf, i2c_addr, reg, &val[0], sizeof(val)/sizeof(val[0]) ); + xI2CMasterWriteRead( i2c_interf, i2c_addr, ®, 1, &val[0], sizeof(val)/sizeof(val[0]) ); i2c_give( i2c_interf ); diff --git a/modules/sensors/ina3221.c b/modules/sensors/ina3221.c index c6f62898d..8c7d39a0e 100644 --- a/modules/sensors/ina3221.c +++ b/modules/sensors/ina3221.c @@ -113,7 +113,7 @@ uint8_t ina3221_read_reg( ina3221_data_t * data, uint8_t reg, uint16_t *read ) if( i2c_take_by_chipid( data->chipid, &i2c_addr, &i2c_interf, portMAX_DELAY) == pdTRUE ) { - rx_len = xI2CMasterWriteRead( i2c_interf, i2c_addr, reg, &val[0], sizeof(val)/sizeof(val[0]) ); + rx_len = xI2CMasterWriteRead( i2c_interf, i2c_addr, ®, 1, &val[0], sizeof(val)/sizeof(val[0]) ); i2c_give( i2c_interf ); diff --git a/modules/sensors/max6642.c b/modules/sensors/max6642.c index 6582cc4ff..b2bc9cb82 100644 --- a/modules/sensors/max6642.c +++ b/modules/sensors/max6642.c @@ -83,10 +83,10 @@ Bool max6642_read_local( sensor_t *sensor, uint8_t *temp ) { uint8_t i2c_interf, i2c_addr; uint8_t read = 0; - + const uint8_t cmd = MAX6642_CMD_READ_LOCAL; if ( i2c_take_by_chipid( sensor->chipid, &i2c_addr, &i2c_interf, portMAX_DELAY ) == pdTRUE ) { - xI2CMasterWriteRead( i2c_interf, i2c_addr, MAX6642_CMD_READ_LOCAL, &read, 1 ); + xI2CMasterWriteRead( i2c_interf, i2c_addr, &cmd, 1, &read, 1 ); i2c_give( i2c_interf ); *temp = read; @@ -100,10 +100,11 @@ Bool max6642_read_remote( sensor_t *sensor, uint8_t *temp ) { uint8_t i2c_interf, i2c_addr; uint8_t read = 0; + const uint8_t cmd = MAX6642_CMD_READ_REMOTE; if ( i2c_take_by_chipid( sensor->chipid, &i2c_addr, &i2c_interf, portMAX_DELAY ) == pdTRUE ) { - xI2CMasterWriteRead( i2c_interf, i2c_addr, MAX6642_CMD_READ_REMOTE, &read, 1 ); + xI2CMasterWriteRead( i2c_interf, i2c_addr, &cmd, 1, &read, 1 ); i2c_give( i2c_interf ); *temp = read; @@ -117,10 +118,11 @@ Bool max6642_read_local_extd( sensor_t *sensor, uint8_t *temp ) { uint8_t i2c_interf, i2c_addr; uint8_t read = 0; + const uint8_t cmd = MAX6642_CMD_READ_LOCAL_EXTD; if ( i2c_take_by_chipid( sensor->chipid, &i2c_addr, &i2c_interf, portMAX_DELAY ) == pdTRUE ) { - xI2CMasterWriteRead( i2c_interf, i2c_addr, MAX6642_CMD_READ_LOCAL_EXTD, &read, 1 ); + xI2CMasterWriteRead( i2c_interf, i2c_addr, &cmd, 1, &read, 1 ); i2c_give( i2c_interf ); *temp = read; @@ -134,10 +136,11 @@ Bool max6642_read_remote_extd( sensor_t *sensor, uint8_t *temp ) { uint8_t i2c_interf, i2c_addr; uint8_t read = 0; + const uint8_t cmd = MAX6642_CMD_READ_REMOTE_EXTD; if ( i2c_take_by_chipid( sensor->chipid, &i2c_addr, &i2c_interf, portMAX_DELAY ) == pdTRUE ) { - xI2CMasterWriteRead( i2c_interf, i2c_addr, MAX6642_CMD_READ_REMOTE_EXTD, &read, 1 ); + xI2CMasterWriteRead( i2c_interf, i2c_addr, &cmd, 1, &read, 1 ); i2c_give( i2c_interf ); *temp = read; @@ -151,10 +154,11 @@ uint8_t max6642_read_status( sensor_t *sensor ) { uint8_t i2c_interf, i2c_addr; uint8_t stat = 0; + const uint8_t cmd = MAX6642_CMD_READ_STATUS; if ( i2c_take_by_chipid( sensor->chipid, &i2c_addr, &i2c_interf, portMAX_DELAY ) == pdTRUE ) { - xI2CMasterWriteRead( i2c_interf, i2c_addr, MAX6642_CMD_READ_STATUS, &stat, 1 ); + xI2CMasterWriteRead( i2c_interf, i2c_addr, &cmd, 1, &stat, 1 ); i2c_give( i2c_interf ); } @@ -165,10 +169,11 @@ uint8_t max6642_read_cfg( sensor_t *sensor ) { uint8_t i2c_interf, i2c_addr; uint8_t cfg = 0; + const uint8_t cmd = MAX6642_CMD_READ_CONFIG; if ( i2c_take_by_chipid( sensor->chipid, &i2c_addr, &i2c_interf, portMAX_DELAY) == pdTRUE ) { - xI2CMasterWriteRead( i2c_interf, i2c_addr, MAX6642_CMD_READ_CONFIG, &cfg, 1 ); + xI2CMasterWriteRead( i2c_interf, i2c_addr, &cmd, 1, &cfg, 1 ); i2c_give( i2c_interf ); } diff --git a/port/ucontroller/nxp/lpc17xx/lpc17_i2c.c b/port/ucontroller/nxp/lpc17xx/lpc17_i2c.c index 2b01d0a12..8c365038d 100644 --- a/port/ucontroller/nxp/lpc17xx/lpc17_i2c.c +++ b/port/ucontroller/nxp/lpc17xx/lpc17_i2c.c @@ -150,3 +150,15 @@ void vI2CSlaveSetup ( I2C_ID_T id, uint8_t slave_addr ) slave_cfg.rxSz = (sizeof(recv_msg)/sizeof(recv_msg[0])); Chip_I2C_SlaveSetup( id, I2C_SLAVE_0, &slave_cfg, I2C_Slave_Event, SLAVE_MASK); } + +int xI2CMasterWriteRead(I2C_ID_T id, uint8_t addr, const uint8_t *tx_buff, int tx_len, uint8_t *rx_buff, int rx_len) +{ + I2C_XFER_T xfer = {0}; + xfer.slaveAddr = addr; + xfer.txBuff = tx_buff; + xfer.txSz = tx_len; + xfer.rxBuff = rx_buff; + xfer.rxSz = rx_len; + while (Chip_I2C_MasterTransfer(id, &xfer) == I2C_STATUS_ARBLOST) {} + return rx_len - xfer.rxSz; +} diff --git a/port/ucontroller/nxp/lpc17xx/lpc17_i2c.h b/port/ucontroller/nxp/lpc17xx/lpc17_i2c.h index 4f87c33b2..d28b96c62 100644 --- a/port/ucontroller/nxp/lpc17xx/lpc17_i2c.h +++ b/port/ucontroller/nxp/lpc17xx/lpc17_i2c.h @@ -30,9 +30,8 @@ #define xI2CMasterWrite(id, addr, tx_buff, tx_len) Chip_I2C_MasterSend(id, addr, tx_buff, tx_len) #define xI2CMasterRead(id, addr, rx_buff, rx_len) Chip_I2C_MasterRead(id, addr, rx_buff, rx_len) -#define xI2CMasterWriteRead(id, addr, cmd, rx_buff, rx_len) Chip_I2C_MasterCmdRead(id, addr, cmd, rx_buff, rx_len) uint8_t xI2CSlaveReceive( I2C_ID_T id, uint8_t * rx_buff, uint8_t buff_len, uint32_t timeout ); void vI2CSlaveSetup ( I2C_ID_T id, uint8_t slave_addr ); void vI2CConfig( I2C_ID_T id, uint32_t speed ); - +int xI2CMasterWriteRead(I2C_ID_T id, uint8_t addr, const uint8_t *tx_buff, int tx_len, uint8_t *rx_buff, int rx_len); From dd130a3883b7e18c85aaca433eedfe61c9d1dfbc Mon Sep 17 00:00:00 2001 From: Gustavo de Souza dos Reis Date: Wed, 21 Feb 2024 14:36:00 -0300 Subject: [PATCH 26/43] [RTM] Move 12V turn on/off to AFC specific code --- modules/pca9554.h | 1 - modules/rtm.c | 2 +- modules/rtm.h | 16 +++++++++++++ port/board/afc-v3/rtm.c | 13 +++++++++++ port/board/afc-v4/CMakeLists.txt | 1 + port/board/afc-v4/payload.c | 22 ++---------------- port/board/afc-v4/payload.h | 23 ------------------- port/board/afc-v4/pin_mapping.c | 28 +++++++++++++++++++++++ port/board/afc-v4/pin_mapping.h | 30 +++++++++++++++++++++++- port/board/afc-v4/rtm.c | 15 ++++++++++++ port/board/rtm-8sfp/rtm_user.c | 39 +++++++++----------------------- port/board/rtm-8sfp/rtm_user.h | 7 +++--- port/board/rtm-lamp/rtm_user.c | 35 +++++----------------------- port/board/rtm-lamp/rtm_user.h | 7 +++--- 14 files changed, 130 insertions(+), 109 deletions(-) create mode 100644 port/board/afc-v4/pin_mapping.c diff --git a/modules/pca9554.h b/modules/pca9554.h index c8cae6e7f..b2b3b63bb 100644 --- a/modules/pca9554.h +++ b/modules/pca9554.h @@ -70,7 +70,6 @@ * @} */ - /* Pins Read/Write */ /** * @brief Read all pins status diff --git a/modules/rtm.c b/modules/rtm.c index b95327743..024789396 100644 --- a/modules/rtm.c +++ b/modules/rtm.c @@ -127,7 +127,7 @@ void RTM_Manage( void * Parameters ) current_evt = xEventGroupGetBits( rtm_payload_evt ); if ( current_evt & PAYLOAD_MESSAGE_QUIESCE ) { - if ( rtm_quiesce() ) { + if ( rtm_disable_payload_power() ) { /* Quiesced event */ printf("[RTM] Quiesced RTM successfuly!\n"); hotswap_set_mask_bit( HOTSWAP_RTM, HOTSWAP_QUIESCED_MASK ); diff --git a/modules/rtm.h b/modules/rtm.h index ae06ed18b..01e4ded4a 100644 --- a/modules/rtm.h +++ b/modules/rtm.h @@ -53,5 +53,21 @@ void rtm_manage_init( void ); */ void rtm_check_presence(uint8_t *status); +/** + * @brief Enable payload power + * + * This function turn on the 12V payload power rail and initialise the RTM powered by it. + * + */ +mmc_err rtm_enable_payload_power( void ); + +/** + * @brief Disable payload power + * + * This function turn off the 12V payload power rail and de-initialise the RTM powered by it. + * + */ +mmc_err rtm_disable_payload_power( void ); + #endif diff --git a/port/board/afc-v3/rtm.c b/port/board/afc-v3/rtm.c index 17d71295c..f74885751 100644 --- a/port/board/afc-v3/rtm.c +++ b/port/board/afc-v3/rtm.c @@ -16,3 +16,16 @@ void rtm_check_presence( uint8_t *status ) *status = HOTSWAP_STATE_URTM_PRSENT; } } + +mmc_err rtm_enable_payload_power( void ) +{ + gpio_set_pin_state( PIN_PORT(GPIO_EN_RTM_PWR), PIN_NUMBER(GPIO_EN_RTM_PWR), 1 ); + return rtm_enable_payload_power_post(); +} + + mmc_err rtm_disable_payload_power( void ) +{ + mmc_err error = rtm_disable_payload_power_pre(); + gpio_set_pin_state( PIN_PORT(GPIO_EN_RTM_PWR), PIN_NUMBER(GPIO_EN_RTM_PWR), 0 ); + return error; +} diff --git a/port/board/afc-v4/CMakeLists.txt b/port/board/afc-v4/CMakeLists.txt index a858f51ff..5837e8201 100644 --- a/port/board/afc-v4/CMakeLists.txt +++ b/port/board/afc-v4/CMakeLists.txt @@ -40,6 +40,7 @@ set(BOARD_PATH ${CMAKE_CURRENT_SOURCE_DIR}) ##Sensors SDR list set( PROJ_SRCS ${PROJ_SRCS} ${BOARD_PATH}/sdr_list.c ) set( PROJ_SRCS ${PROJ_SRCS} ${BOARD_PATH}/i2c_mapping.c ) +set( PROJ_SRCS ${PROJ_SRCS} ${BOARD_PATH}/pin_mapping.c ) if (";${TARGET_MODULES};" MATCHES ";PAYLOAD;") set(PROJ_SRCS ${PROJ_SRCS} ${BOARD_PATH}/payload.c) diff --git a/port/board/afc-v4/payload.c b/port/board/afc-v4/payload.c index e18772865..16a29a8a0 100644 --- a/port/board/afc-v4/payload.c +++ b/port/board/afc-v4/payload.c @@ -45,6 +45,7 @@ #include "clock_config.h" #include "eeprom_24xx02.h" #include "i2c_mapping.h" +#include "pin_mapping.h" /* payload states * 0 - No power @@ -67,26 +68,6 @@ * Wait until payload power goes down to restart the cycle */ -const external_gpio_t ext_gpios[16] = { - [EXT_GPIO_P1V5_VTT_EN] = { 1, 7 }, - [EXT_GPIO_EN_P1V8] = { 1, 6 }, - [EXT_GPIO_EN_P1V2] = { 1, 5 }, - [EXT_GPIO_EN_FMC1_P12V] = { 1, 4 }, - [EXT_GPIO_EN_FMC2_P12V] = { 1, 3 }, - [EXT_GPIO_EN_FMC1_PVADJ] = { 1, 2 }, - [EXT_GPIO_EN_FMC2_PVADJ] = { 1, 1 }, - [EXT_GPIO_EN_FMC1_P3V3] = { 1, 0 }, - [EXT_GPIO_EN_FMC2_P3V3] = { 0, 7 }, - [EXT_GPIO_EN_P1V0] = { 0, 6 }, - [EXT_GPIO_EN_P3V3] = { 0, 5 }, - [EXT_GPIO_EN_RTM_PWR] = { 0, 4 }, - [EXT_GPIO_EN_RTM_MP] = { 0, 3 }, - [EXT_GPIO_FPGA_I2C_RESET] = { 0, 2 }, - [EXT_GPIO_DAC_VADJ_RSTn] = { 0, 1 }, - [EXT_GPIO_PROGRAM_B] = { 0, 0 } -}; - - /** * @brief Set AFC's DCDC Converters state * @@ -242,6 +223,7 @@ void payload_init( void ) amc_payload_evt = xEventGroupCreate(); #ifdef MODULE_RTM rtm_payload_evt = xEventGroupCreate(); + mcp23016_write_pin(ext_gpios[EXT_GPIO_EN_RTM_MP].port_num, ext_gpios[EXT_GPIO_EN_RTM_MP].pin_num, true); #endif #ifdef MODULE_ADC diff --git a/port/board/afc-v4/payload.h b/port/board/afc-v4/payload.h index 291c927fc..5ec6dca3b 100644 --- a/port/board/afc-v4/payload.h +++ b/port/board/afc-v4/payload.h @@ -68,29 +68,6 @@ extern enum { /** * @} */ -typedef struct external_gpio { - uint8_t port_num; - uint8_t pin_num; -} external_gpio_t; - -enum { - EXT_GPIO_EN_P1V0, - EXT_GPIO_EN_P1V8, - EXT_GPIO_EN_P3V3, - EXT_GPIO_EN_FMC1_PVADJ, - EXT_GPIO_EN_FMC2_PVADJ, - EXT_GPIO_P1V5_VTT_EN, - EXT_GPIO_EN_P1V2, - EXT_GPIO_EN_FMC1_P12V, - EXT_GPIO_EN_FMC1_P3V3, - EXT_GPIO_EN_FMC2_P12V, - EXT_GPIO_EN_FMC2_P3V3, - EXT_GPIO_EN_RTM_PWR, - EXT_GPIO_EN_RTM_MP, - EXT_GPIO_FPGA_I2C_RESET, - EXT_GPIO_DAC_VADJ_RSTn, - EXT_GPIO_PROGRAM_B, -}; /** * @brief Payload task unblock delay diff --git a/port/board/afc-v4/pin_mapping.c b/port/board/afc-v4/pin_mapping.c new file mode 100644 index 000000000..95bae5b6d --- /dev/null +++ b/port/board/afc-v4/pin_mapping.c @@ -0,0 +1,28 @@ +#include "pin_mapping.h" + +/** + * @defgroup AFC_V4_0_PIN_MAPPING AFCv4.0 Pin Mapping + * @ingroup AFC_V4_0 + * @{ + */ +const external_gpio_t ext_gpios[16] = { + [EXT_GPIO_P1V5_VTT_EN] = { 1, 7 }, + [EXT_GPIO_EN_P1V8] = { 1, 6 }, + [EXT_GPIO_EN_P1V2] = { 1, 5 }, + [EXT_GPIO_EN_FMC1_P12V] = { 1, 4 }, + [EXT_GPIO_EN_FMC2_P12V] = { 1, 3 }, + [EXT_GPIO_EN_FMC1_PVADJ] = { 1, 2 }, + [EXT_GPIO_EN_FMC2_PVADJ] = { 1, 1 }, + [EXT_GPIO_EN_FMC1_P3V3] = { 1, 0 }, + [EXT_GPIO_EN_FMC2_P3V3] = { 0, 7 }, + [EXT_GPIO_EN_P1V0] = { 0, 6 }, + [EXT_GPIO_EN_P3V3] = { 0, 5 }, + [EXT_GPIO_EN_RTM_PWR] = { 0, 4 }, + [EXT_GPIO_EN_RTM_MP] = { 0, 3 }, + [EXT_GPIO_FPGA_I2C_RESET] = { 0, 2 }, + [EXT_GPIO_DAC_VADJ_RSTn] = { 0, 1 }, + [EXT_GPIO_PROGRAM_B] = { 0, 0 } +}; +/** + * @} + */ diff --git a/port/board/afc-v4/pin_mapping.h b/port/board/afc-v4/pin_mapping.h index ce8430153..8c9376e17 100644 --- a/port/board/afc-v4/pin_mapping.h +++ b/port/board/afc-v4/pin_mapping.h @@ -239,8 +239,36 @@ GPIO_FMC1_PRSNT_M2C, \ GPIO_FMC2_PRSNT_M2C, \ GPIO_RTM_PS -#endif /** * @} */ +#include + +typedef struct external_gpio { + uint8_t port_num; + uint8_t pin_num; +} external_gpio_t; + +extern const external_gpio_t ext_gpios[16]; + +enum { + EXT_GPIO_EN_P1V0, + EXT_GPIO_EN_P1V8, + EXT_GPIO_EN_P3V3, + EXT_GPIO_EN_FMC1_PVADJ, + EXT_GPIO_EN_FMC2_PVADJ, + EXT_GPIO_P1V5_VTT_EN, + EXT_GPIO_EN_P1V2, + EXT_GPIO_EN_FMC1_P12V, + EXT_GPIO_EN_FMC1_P3V3, + EXT_GPIO_EN_FMC2_P12V, + EXT_GPIO_EN_FMC2_P3V3, + EXT_GPIO_EN_RTM_PWR, + EXT_GPIO_EN_RTM_MP, + EXT_GPIO_FPGA_I2C_RESET, + EXT_GPIO_DAC_VADJ_RSTn, + EXT_GPIO_PROGRAM_B, +}; + +#endif diff --git a/port/board/afc-v4/rtm.c b/port/board/afc-v4/rtm.c index 85ae468dc..06f89b7e5 100644 --- a/port/board/afc-v4/rtm.c +++ b/port/board/afc-v4/rtm.c @@ -1,6 +1,8 @@ #include "i2c_mapping.h" #include "port.h" #include "hotswap.h" +#include "pin_mapping.h" +#include "mcp23016.h" void rtm_check_presence( uint8_t *status ) { @@ -10,3 +12,16 @@ void rtm_check_presence( uint8_t *status ) *status = HOTSWAP_STATE_URTM_PRSENT; } } + +mmc_err rtm_enable_payload_power( void ) +{ + mmc_err err = mcp23016_write_pin(ext_gpios[EXT_GPIO_EN_RTM_PWR].port_num, ext_gpios[EXT_GPIO_EN_RTM_PWR].pin_num, true); + rtm_enable_payload_power_post(); + return err; +} + +mmc_err rtm_disable_payload_power( void ) +{ + rtm_disable_payload_power_pre(); + return mcp23016_write_pin(ext_gpios[EXT_GPIO_EN_RTM_PWR].port_num, ext_gpios[EXT_GPIO_EN_RTM_PWR].pin_num, false); +} diff --git a/port/board/rtm-8sfp/rtm_user.c b/port/board/rtm-8sfp/rtm_user.c index 33406a933..43ded24fa 100644 --- a/port/board/rtm-8sfp/rtm_user.c +++ b/port/board/rtm-8sfp/rtm_user.c @@ -32,16 +32,22 @@ #include "led.h" #include "board_led.h" #include "uart_debug.h" -/* RTM Management functions */ -void rtm_enable_payload_power( void ) + +/* RTM Management functions */ +/* + * This functions are not necessary for RTM-8SFP because it doesn't need any power up/down specific + * procedure other than controlling the 12V payload power rail. + * + */ +mmc_err rtm_enable_payload_power_post( void ) { - gpio_set_pin_state( PIN_PORT(GPIO_EN_RTM_PWR), PIN_NUMBER(GPIO_EN_RTM_PWR), 1 ); + return MMC_OK; } -void rtm_disable_payload_power( void ) +mmc_err rtm_disable_payload_power_pre( void ) { - gpio_set_pin_state( PIN_PORT(GPIO_EN_RTM_PWR), PIN_NUMBER(GPIO_EN_RTM_PWR), 0 ); + return MMC_OK; } uint8_t rtm_get_hotswap_handle_status( uint8_t *state ) @@ -49,8 +55,6 @@ uint8_t rtm_get_hotswap_handle_status( uint8_t *state ) static uint8_t falling, rising; uint8_t pin_read; - rtm_enable_i2c(); - if (pca9554_read_pin( CHIP_ID_RTM_PCA9554, RTM_GPIO_HOTSWAP_HANDLE, &pin_read ) == 0 ) { return false; } @@ -67,24 +71,9 @@ uint8_t rtm_get_hotswap_handle_status( uint8_t *state ) void rtm_hardware_init( void ) { - rtm_enable_i2c(); pca9554_set_port_dir( CHIP_ID_RTM_PCA9554, 0x1F ); } -void rtm_enable_i2c( void ) -{ - /* Enable I2C communication with RTM */ - gpio_set_pin_dir( PIN_PORT(GPIO_RTM_PS), PIN_NUMBER(GPIO_RTM_PS), GPIO_DIR_OUTPUT ); - gpio_set_pin_dir( PIN_PORT(GPIO_EN_RTM_I2C), PIN_NUMBER(GPIO_EN_RTM_I2C), GPIO_DIR_OUTPUT ); - gpio_set_pin_state( PIN_PORT(GPIO_EN_RTM_I2C), PIN_NUMBER(GPIO_EN_RTM_I2C), GPIO_LEVEL_HIGH ); -} - -void rtm_disable_i2c( void ) -{ - gpio_set_pin_dir( PIN_PORT(GPIO_RTM_PS), PIN_NUMBER(GPIO_RTM_PS), GPIO_DIR_INPUT ); - gpio_set_pin_dir( PIN_PORT(GPIO_EN_RTM_I2C), PIN_NUMBER(GPIO_EN_RTM_I2C), GPIO_DIR_INPUT ); -} - bool rtm_compatibility_check( void ) { uint8_t i; @@ -132,12 +121,6 @@ bool rtm_compatibility_check( void ) return false; } -bool rtm_quiesce( void ) -{ - /* In this board, no action is needed to quiesce */ - return true; -} - void rtm_ctrl_led( uint8_t id, uint8_t state ) { uint8_t pca_pin; diff --git a/port/board/rtm-8sfp/rtm_user.h b/port/board/rtm-8sfp/rtm_user.h index 7cc352acd..84bde2179 100644 --- a/port/board/rtm-8sfp/rtm_user.h +++ b/port/board/rtm-8sfp/rtm_user.h @@ -29,14 +29,15 @@ #define RTM_GPIO_LED_GREEN 6 #define RTM_GPIO_LED_BLUE 7 +#include "mmc_error.h" + /* Mandatory RTM module functions */ -void rtm_enable_payload_power( void ); -void rtm_disable_payload_power( void ); +mmc_err rtm_enable_payload_power_post( void ); +mmc_err rtm_disable_payload_power_pre( void ); uint8_t rtm_get_hotswap_handle_status( uint8_t *state ); void rtm_hardware_init( void ); void rtm_ctrl_led( uint8_t id, uint8_t state ); uint8_t rtm_read_led( uint8_t id ); -bool rtm_quiesce( void ); bool rtm_compatibility_check( void ); /* User defined functions */ diff --git a/port/board/rtm-lamp/rtm_user.c b/port/board/rtm-lamp/rtm_user.c index 536eb1952..6c62910a4 100644 --- a/port/board/rtm-lamp/rtm_user.c +++ b/port/board/rtm-lamp/rtm_user.c @@ -35,10 +35,8 @@ #include "cdce906_config.h" /* RTM Management functions */ -void rtm_enable_payload_power( void ) +mmc_err rtm_enable_payload_power_post( void ) { - gpio_set_pin_state( PIN_PORT(GPIO_EN_RTM_PWR), PIN_NUMBER(GPIO_EN_RTM_PWR), 1 ); - /* * RTM-LAMP power up sequence */ @@ -49,12 +47,12 @@ void rtm_enable_payload_power( void ) vTaskDelay(pdMS_TO_TICKS(10)); pca9554_write_pin(CHIP_ID_RTM_PCA9554_PWR, RTM_GPIO_VS1_EN, 1); pca9554_write_pin(CHIP_ID_RTM_PCA9554_PWR, RTM_GPIO_VS2_EN, 1); + + return MMC_OK; } -void rtm_disable_payload_power( void ) +mmc_err rtm_disable_payload_power_pre( void ) { - gpio_set_pin_state( PIN_PORT(GPIO_EN_RTM_PWR), PIN_NUMBER(GPIO_EN_RTM_PWR), 0 ); - /* * RTM-LAMP power down sequence */ @@ -65,6 +63,8 @@ void rtm_disable_payload_power( void ) pca9554_write_pin(CHIP_ID_RTM_PCA9554_PWR, RTM_GPIO_7V_EN, 1); vTaskDelay(pdMS_TO_TICKS(10)); pca9554_write_pin(CHIP_ID_RTM_PCA9554_PWR, RTM_GPIO_5V_EN, 0); + + return MMC_OK; } uint8_t rtm_get_hotswap_handle_status( uint8_t *state ) @@ -72,8 +72,6 @@ uint8_t rtm_get_hotswap_handle_status( uint8_t *state ) static uint8_t falling, rising; uint8_t pin_read; - rtm_enable_i2c(); - if (pca9554_read_pin( CHIP_ID_RTM_PCA9554_LEDS, RTM_GPIO_HOTSWAP_HANDLE, &pin_read ) == 0 ) { return false; } @@ -90,7 +88,6 @@ uint8_t rtm_get_hotswap_handle_status( uint8_t *state ) void rtm_hardware_init( void ) { - rtm_enable_i2c(); pca9554_set_port_dir( CHIP_ID_RTM_PCA9554_LEDS, 0x1F ); /* @@ -107,20 +104,6 @@ void rtm_hardware_init( void ) (0 << RTM_GPIO_VS2_EN) | (0 << RTM_GPIO_5V_EN)); } -void rtm_enable_i2c( void ) -{ - /* Enable I2C communication with RTM */ - gpio_set_pin_dir( PIN_PORT(GPIO_RTM_PS), PIN_NUMBER(GPIO_RTM_PS), GPIO_DIR_OUTPUT ); - gpio_set_pin_dir( PIN_PORT(GPIO_EN_RTM_I2C), PIN_NUMBER(GPIO_EN_RTM_I2C), GPIO_DIR_OUTPUT ); - gpio_set_pin_state( PIN_PORT(GPIO_EN_RTM_I2C), PIN_NUMBER(GPIO_EN_RTM_I2C), GPIO_LEVEL_HIGH ); -} - -void rtm_disable_i2c( void ) -{ - gpio_set_pin_dir( PIN_PORT(GPIO_RTM_PS), PIN_NUMBER(GPIO_RTM_PS), GPIO_DIR_INPUT ); - gpio_set_pin_dir( PIN_PORT(GPIO_EN_RTM_I2C), PIN_NUMBER(GPIO_EN_RTM_I2C), GPIO_DIR_INPUT ); -} - bool rtm_compatibility_check( void ) { uint8_t i; @@ -168,12 +151,6 @@ bool rtm_compatibility_check( void ) return false; } -bool rtm_quiesce( void ) -{ - /* In this board, no action is needed to quiesce */ - return true; -} - void rtm_ctrl_led( uint8_t id, uint8_t state ) { uint8_t pca_pin; diff --git a/port/board/rtm-lamp/rtm_user.h b/port/board/rtm-lamp/rtm_user.h index 4717f39ae..976c90e76 100644 --- a/port/board/rtm-lamp/rtm_user.h +++ b/port/board/rtm-lamp/rtm_user.h @@ -35,14 +35,15 @@ #define RTM_GPIO_5V_EN 3 #define RTM_GPIO_NEG_7V_EN 4 +#include "mmc_error.h" + /* Mandatory RTM module functions */ -void rtm_enable_payload_power( void ); -void rtm_disable_payload_power( void ); +mmc_err rtm_enable_payload_power_post( void ); +mmc_err rtm_disable_payload_power_pre( void ); uint8_t rtm_get_hotswap_handle_status( uint8_t *state ); void rtm_hardware_init( void ); void rtm_ctrl_led( uint8_t id, uint8_t state ); uint8_t rtm_read_led( uint8_t id ); -bool rtm_quiesce( void ); bool rtm_compatibility_check( void ); /* User defined functions */ From 12ab0f03ed8865dd358d41db31be041e326d08a3 Mon Sep 17 00:00:00 2001 From: Gustavo de Souza dos Reis Date: Thu, 22 Feb 2024 14:42:21 -0300 Subject: [PATCH 27/43] Correctly check Zone3 compatibility between AFCv4 and RTM-Lamp --- port/board/rtm-lamp/rtm_user.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/port/board/rtm-lamp/rtm_user.c b/port/board/rtm-lamp/rtm_user.c index 6c62910a4..a8bb16add 100644 --- a/port/board/rtm-lamp/rtm_user.c +++ b/port/board/rtm-lamp/rtm_user.c @@ -123,9 +123,18 @@ bool rtm_compatibility_check( void ) /* Read Multirecord header */ fru_read( i, multirec_hdr, multirec_off, 10 ); + if (multirec_hdr[8] == 0x30) { z3rec_found = true; - break; + + /* According to Plataform Management FRU Information Storage Definition v1.0, pg 19 + * multirec_hdr[1] >> 7 == 1 indicates the end of list, and for this reason, the loop + * should only break if this condition is satisfied to ensure that we have passed + * through all multirecord area. + */ + if ((multirec_hdr[1] >> 7) == 1) { + break; + } } /* Advance the offset pointer, adding the record length field to it */ multirec_off += multirec_hdr[2]+5; From 124adae69aa9a9e2239b45196606b74c58e88729 Mon Sep 17 00:00:00 2001 From: Gustavo de Souza dos Reis Date: Thu, 22 Feb 2024 14:43:12 -0300 Subject: [PATCH 28/43] Correctly check Zone3 compatibility between AFCv3 and RTM-8SFP --- port/board/rtm-8sfp/rtm_user.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/port/board/rtm-8sfp/rtm_user.c b/port/board/rtm-8sfp/rtm_user.c index 43ded24fa..7fb7169f0 100644 --- a/port/board/rtm-8sfp/rtm_user.c +++ b/port/board/rtm-8sfp/rtm_user.c @@ -95,7 +95,15 @@ bool rtm_compatibility_check( void ) if (multirec_hdr[8] == 0x30) { z3rec_found = true; - break; + + /* According to Plataform Management FRU Information Storage Definition v1.0, pg 19 + * multirec_hdr[1] >> 7 == 1 indicates the end of list, and for this reason, the loop + * should only break if this condition is satisfied to ensure that we have passed + * through all multirecord area. + */ + if ((multirec_hdr[1] >> 7) == 1) { + break; + } } /* Advance the offset pointer, adding the record length field to it */ multirec_off += multirec_hdr[2]+5; From 9dd567487e002af53e0a982cac21da40cd149f92 Mon Sep 17 00:00:00 2001 From: Gustavo de Souza dos Reis Date: Thu, 22 Feb 2024 14:44:25 -0300 Subject: [PATCH 29/43] Add support to RTM-Lamp with AFCv4 --- .github/workflows/build.yml | 10 +++++----- modules/rtm.h | 2 +- port/board/afc-v4/CMakeLists.txt | 6 ++++++ port/board/afc-v4/payload.h | 7 ++++--- 4 files changed, 16 insertions(+), 9 deletions(-) diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index b3064c010..70d31d052 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -15,11 +15,11 @@ jobs: matrix: build-flags: - { flags: -DBOARD=afc -DVERSION=3.1 -DBOARD_RTM=8sfp } - - { flags: -DBOARD=afc -DVERSION=4.0} - - { flags: -DBOARD=afc -DVERSION=4.0 -DDEBUG_PROBE=jlink -DOPENOCD_TRANSPORT=swd } - - { flags: -DBOARD=afc -DVERSION=4.0 -DDEBUG_PROBE=cmsis-dap -DOPENOCD_TRANSPORT=swd } - - { flags: -DBOARD=afc -DVERSION=4.0 -DDEBUG_PROBE=digilent_jtag_hs3 -DOPENOCD_TRANSPORT=jtag } - - { flags: -DBOARD=afc -DVERSION=4.0 -DDEBUG_PROBE=xvc -DOPENOCD_TRANSPORT=jtag -DXVC_HOST=host -DXVC_PORT=0000} + - { flags: -DBOARD=afc -DVERSION=4.0 -DBOARD_RTM=lamp} + - { flags: -DBOARD=afc -DVERSION=4.0 -DBOARD_RTM=lamp -DDEBUG_PROBE=jlink -DOPENOCD_TRANSPORT=swd } + - { flags: -DBOARD=afc -DVERSION=4.0 -DBOARD_RTM=lamp -DDEBUG_PROBE=cmsis-dap -DOPENOCD_TRANSPORT=swd } + - { flags: -DBOARD=afc -DVERSION=4.0 -DBOARD_RTM=lamp -DDEBUG_PROBE=digilent_jtag_hs3 -DOPENOCD_TRANSPORT=jtag } + - { flags: -DBOARD=afc -DVERSION=4.0 -DBOARD_RTM=lamp -DDEBUG_PROBE=xvc -DOPENOCD_TRANSPORT=jtag -DXVC_HOST=host -DXVC_PORT=0000} steps: - uses: actions/checkout@v3 with: diff --git a/modules/rtm.h b/modules/rtm.h index 01e4ded4a..b990d0f4e 100644 --- a/modules/rtm.h +++ b/modules/rtm.h @@ -47,7 +47,7 @@ void rtm_manage_init( void ); /** * @brief Check RTM Presence * - * This function is used to detect the RTM Board presence + * This task use some GPIO pins to detect the RTM Board presence * * @return None */ diff --git a/port/board/afc-v4/CMakeLists.txt b/port/board/afc-v4/CMakeLists.txt index 5837e8201..26dc10af2 100644 --- a/port/board/afc-v4/CMakeLists.txt +++ b/port/board/afc-v4/CMakeLists.txt @@ -28,6 +28,7 @@ set(TARGET_MODULES "IDT_8V54816" "HPM" "SYSUTILS" + "RTM" ) if (NOT DISABLE_WATCHDOG) @@ -47,6 +48,11 @@ if (";${TARGET_MODULES};" MATCHES ";PAYLOAD;") set(MODULES_FLAGS "${MODULES_FLAGS} -DMODULE_PAYLOAD") endif() +if (";${TARGET_MODULES};" MATCHES ";RTM;") + set(PROJ_SRCS ${PROJ_SRCS} ${BOARD_PATH}/rtm.c) + set(MODULES_FLAGS "${MODULES_FLAGS} -DMODULE_RTM") +endif() + if (";${TARGET_MODULES};" MATCHES ";ADC;") set(MODULES_FLAGS "${MODULES_FLAGS} -DMODULE_ADC") endif() diff --git a/port/board/afc-v4/payload.h b/port/board/afc-v4/payload.h index 5ec6dca3b..1523a1aba 100644 --- a/port/board/afc-v4/payload.h +++ b/port/board/afc-v4/payload.h @@ -62,9 +62,10 @@ extern enum { #define PAYLOAD_MESSAGE_WARM_RST (1 << 1) #define PAYLOAD_MESSAGE_REBOOT (1 << 2) #define PAYLOAD_MESSAGE_QUIESCE (1 << 3) -#define PAYLOAD_MESSAGE_DCDC_PGOOD (1 << 4) -#define PAYLOAD_MESSAGE_DCDC_PGOODn (1 << 5) -#define PAYLOAD_MESSAGE_CLOCK_CONFIG (1 << 6) +#define PAYLOAD_MESSAGE_RTM_ENABLE (1 << 4) +#define PAYLOAD_MESSAGE_DCDC_PGOOD (1 << 5) +#define PAYLOAD_MESSAGE_DCDC_PGOODn (1 << 6) +#define PAYLOAD_MESSAGE_CLOCK_CONFIG (1 << 7) /** * @} */ From a0942fd933e6d983057a8cb4eaabe0e3de098298 Mon Sep 17 00:00:00 2001 From: Augusto Fraga Giachero Date: Thu, 22 Feb 2024 15:19:36 -0300 Subject: [PATCH 30/43] Set RTM-LAMP ADC CNV retiming clock PLL config to AMC_CLK1 1:1 The clock signal used to synchronize the ADC CNV signal is the common timing clock (5*RF/36) that comes from the AFC Timing board. The CDCE906 configuration then should be: M = 2, N = 2: (AMC_CLK1 * 2) / 2 = (69.4 MHz * 2) / 2 This is necessary because the minimal frequency allowed for the internal VCO is 80 MHz. --- port/board/rtm-lamp/cdce906_config.h | 84 ++++++++++++++-------------- 1 file changed, 42 insertions(+), 42 deletions(-) diff --git a/port/board/rtm-lamp/cdce906_config.h b/port/board/rtm-lamp/cdce906_config.h index a155d643a..26129c574 100644 --- a/port/board/rtm-lamp/cdce906_config.h +++ b/port/board/rtm-lamp/cdce906_config.h @@ -32,54 +32,54 @@ static const cdce906_cfg cdce906_rtm_cfg = { - .clksrc = CDCE906_CLK_SRC_CLKIN_DIFF, - .pll_div_m = {1, 1, 1}, - .pll_div_n = {5, 1, 1}, - .pll_vco_mux = { - CDCE906_PLL_VCO_MUX_PLL, - CDCE906_PLL_VCO_MUX_PLL, - CDCE906_PLL_VCO_MUX_PLL, - }, - .pll_fvco = { - CDCE906_PLL_FVCO_80_200MHZ, - CDCE906_PLL_FVCO_80_200MHZ, - CDCE906_PLL_FVCO_80_200MHZ, - }, - .ssc_mod_amount = CDCE906_SSC_MOD_AMOUNT_OFF, + .clksrc = CDCE906_CLK_SRC_CLKIN_DIFF, + .pll_div_m = {2, 1, 1}, + .pll_div_n = {2, 1, 1}, + .pll_vco_mux = { + CDCE906_PLL_VCO_MUX_PLL, + CDCE906_PLL_VCO_MUX_PLL, + CDCE906_PLL_VCO_MUX_PLL, + }, + .pll_fvco = { + CDCE906_PLL_FVCO_80_200MHZ, + CDCE906_PLL_FVCO_80_200MHZ, + CDCE906_PLL_FVCO_80_200MHZ, + }, + .ssc_mod_amount = CDCE906_SSC_MOD_AMOUNT_OFF, .ssc_mod_freq = CDCE906_SSC_MOD_FREQ_3286, .s0_cfg = CDCE906_S0_CFG_POWER_DOWN_CTRL, .s1_cfg = CDCE906_S1_CFG_Yx_FIXED_OUTPUT_CTRL, .pll_sel = { - CDCE906_Px_PLL_SEL_PLL1, - CDCE906_Px_PLL_SEL_BYPASS, - CDCE906_Px_PLL_SEL_BYPASS, - CDCE906_Px_PLL_SEL_BYPASS, - CDCE906_Px_PLL_SEL_BYPASS, - CDCE906_Px_PLL_SEL_BYPASS, - }, + CDCE906_Px_PLL_SEL_PLL1, + CDCE906_Px_PLL_SEL_BYPASS, + CDCE906_Px_PLL_SEL_BYPASS, + CDCE906_Px_PLL_SEL_BYPASS, + CDCE906_Px_PLL_SEL_BYPASS, + CDCE906_Px_PLL_SEL_BYPASS, + }, .p_div = {1, 120, 30, 60, 1, 1}, .y_slew = { - CDCE906_Yx_SLEW_CFG_NOMINAL_1NS, - CDCE906_Yx_SLEW_CFG_NOMINAL_1NS, - CDCE906_Yx_SLEW_CFG_NOMINAL_1NS, - CDCE906_Yx_SLEW_CFG_NOMINAL_1NS, - CDCE906_Yx_SLEW_CFG_NOMINAL_1NS, - CDCE906_Yx_SLEW_CFG_NOMINAL_1NS, - }, + CDCE906_Yx_SLEW_CFG_NOMINAL_1NS, + CDCE906_Yx_SLEW_CFG_NOMINAL_1NS, + CDCE906_Yx_SLEW_CFG_NOMINAL_1NS, + CDCE906_Yx_SLEW_CFG_NOMINAL_1NS, + CDCE906_Yx_SLEW_CFG_NOMINAL_1NS, + CDCE906_Yx_SLEW_CFG_NOMINAL_1NS, + }, .y_p_sel = { - CDCE906_Yx_Px_SEL_P0, - CDCE906_Yx_Px_SEL_P1, - CDCE906_Yx_Px_SEL_P2, - CDCE906_Yx_Px_SEL_P3, - CDCE906_Yx_Px_SEL_P4, - CDCE906_Yx_Px_SEL_P5, - }, + CDCE906_Yx_Px_SEL_P0, + CDCE906_Yx_Px_SEL_P1, + CDCE906_Yx_Px_SEL_P2, + CDCE906_Yx_Px_SEL_P3, + CDCE906_Yx_Px_SEL_P4, + CDCE906_Yx_Px_SEL_P5, + }, .y_out = { - CDCE906_Yx_OUT_CFG_EN, - CDCE906_Yx_OUT_CFG_DIS_HIGH, - CDCE906_Yx_OUT_CFG_DIS_LOW, - CDCE906_Yx_OUT_CFG_DIS_LOW, - CDCE906_Yx_OUT_CFG_DIS_LOW, - CDCE906_Yx_OUT_CFG_DIS_LOW, - }, + CDCE906_Yx_OUT_CFG_EN, + CDCE906_Yx_OUT_CFG_DIS_HIGH, + CDCE906_Yx_OUT_CFG_DIS_LOW, + CDCE906_Yx_OUT_CFG_DIS_LOW, + CDCE906_Yx_OUT_CFG_DIS_LOW, + CDCE906_Yx_OUT_CFG_DIS_LOW, + }, }; From 944e621655329318623bc851ffc9d523b2593136 Mon Sep 17 00:00:00 2001 From: Gustavo de Souza dos Reis Date: Fri, 23 Feb 2024 10:26:34 -0300 Subject: [PATCH 31/43] Change delay counts from ticks to ms --- modules/adn4604.c | 14 +++++++------- modules/eeprom_24xx64.c | 2 +- modules/fpga_spi.c | 4 ++-- modules/fru.c | 22 +++++++++++----------- modules/max116xx.c | 6 +++--- modules/mcp23016.c | 8 ++++---- modules/rtm.c | 2 +- modules/sensors/ina3221.c | 2 +- modules/sensors/lm75.c | 2 +- modules/sensors/max6642.c | 2 +- modules/watchdog.c | 2 +- port/board/afc-v4/payload.c | 4 ++-- 12 files changed, 35 insertions(+), 35 deletions(-) diff --git a/modules/adn4604.c b/modules/adn4604.c index 395fa2cb7..20606df97 100644 --- a/modules/adn4604.c +++ b/modules/adn4604.c @@ -69,7 +69,7 @@ mmc_err adn4604_tx_control( uint8_t output, uint8_t tx_mode ) */ enable[1] = tx_mode << 4; - if (i2c_take_by_chipid(CHIP_ID_ADN, &i2c_addr, &i2c_interf, (TickType_t)10) ) { + if (i2c_take_by_chipid(CHIP_ID_ADN, &i2c_addr, &i2c_interf, pdMS_TO_TICKS(10)) ) { tx_len = xI2CMasterWrite( i2c_interf, i2c_addr, enable, sizeof(enable) ); i2c_give(i2c_interf); } @@ -84,7 +84,7 @@ mmc_err adn4604_update( void ) uint8_t update[2] = { ADN_XPT_UPDATE_REG, 0x01 }; uint8_t tx_len = 0; - if (i2c_take_by_chipid(CHIP_ID_ADN, &i2c_addr, &i2c_interf, (TickType_t)10) ) { + if (i2c_take_by_chipid(CHIP_ID_ADN, &i2c_addr, &i2c_interf, pdMS_TO_TICKS(10)) ) { tx_len = xI2CMasterWrite( i2c_interf, i2c_addr, update, sizeof(update) ); i2c_give(i2c_interf); } @@ -99,7 +99,7 @@ mmc_err adn4604_reset( void ) uint8_t update[2] = { ADN_RESET_REG, 0x01 }; uint8_t tx_len = 0; - if (i2c_take_by_chipid(CHIP_ID_ADN, &i2c_addr, &i2c_interf, (TickType_t)10) ) { + if (i2c_take_by_chipid(CHIP_ID_ADN, &i2c_addr, &i2c_interf, pdMS_TO_TICKS(10)) ) { tx_len = xI2CMasterWrite( i2c_interf, i2c_addr, update, sizeof(update) ); i2c_give(i2c_interf); } @@ -114,7 +114,7 @@ mmc_err adn4604_xpt_config( uint8_t map, adn_connect_map_t xpt_con ) adn_connect_cfg_t cfg = { map, xpt_con }; - if (i2c_take_by_chipid(CHIP_ID_ADN, &i2c_addr, &i2c_interf, (TickType_t)10) ) { + if (i2c_take_by_chipid(CHIP_ID_ADN, &i2c_addr, &i2c_interf, pdMS_TO_TICKS(10)) ) { tx_len = xI2CMasterWrite( i2c_interf, i2c_addr, (uint8_t *)&cfg, sizeof(cfg) ); i2c_give(i2c_interf); } @@ -130,7 +130,7 @@ mmc_err adn4604_active_map( uint8_t map ) /* Select the active map */ uint8_t map_sel[2] = { ADN_XPT_MAP_TABLE_SEL_REG, map }; - if ( i2c_take_by_chipid( CHIP_ID_ADN, &i2c_addr, &i2c_interf, (TickType_t)10 ) ) { + if ( i2c_take_by_chipid( CHIP_ID_ADN, &i2c_addr, &i2c_interf, pdMS_TO_TICKS(10) ) ) { tx_len = xI2CMasterWrite( i2c_interf, i2c_addr, map_sel, sizeof(map_sel) ); i2c_give( i2c_interf ); } @@ -145,7 +145,7 @@ adn_connect_map_t adn4604_out_status( void ) uint8_t cmd; adn_connect_map_t stat_map = {0}; - if ( i2c_take_by_chipid( CHIP_ID_ADN, &i2c_addr, &i2c_interf, (TickType_t)10 ) ) { + if ( i2c_take_by_chipid( CHIP_ID_ADN, &i2c_addr, &i2c_interf, pdMS_TO_TICKS(10) ) ) { /* Read all outputs status */ for ( i = 0; i < 8; i++ ) { @@ -164,7 +164,7 @@ mmc_err adn4604_termination_ctl( uint8_t cfg ) uint8_t msg[2] = { ADN_TERMINATION_CTL_REG, (cfg & 0xF0) }; uint8_t tx_len = 0; - if ( i2c_take_by_chipid( CHIP_ID_ADN, &i2c_addr, &i2c_interf, (TickType_t)10 ) ) { + if ( i2c_take_by_chipid( CHIP_ID_ADN, &i2c_addr, &i2c_interf, pdMS_TO_TICKS(10) ) ) { tx_len = xI2CMasterWrite( i2c_interf, i2c_addr, msg, sizeof(msg) ); i2c_give( i2c_interf ); } diff --git a/modules/eeprom_24xx64.c b/modules/eeprom_24xx64.c index 74c4a9775..78f056ace 100644 --- a/modules/eeprom_24xx64.c +++ b/modules/eeprom_24xx64.c @@ -89,7 +89,7 @@ size_t eeprom_24xx64_write( uint8_t id, uint16_t address, uint8_t *tx_data, size /* Write the data */ tx_len += xI2CMasterWrite( i2c_interface, i2c_addr, &page_buf[0] , bytes_to_write+2 ); - vTaskDelay(10); + vTaskDelay(pdMS_TO_TICKS(10)); tx_len -= 2; /* Remove the 2 page bytes from the count */ curr_addr += bytes_to_write; } diff --git a/modules/fpga_spi.c b/modules/fpga_spi.c index 0a852db95..aa8e405f3 100644 --- a/modules/fpga_spi.c +++ b/modules/fpga_spi.c @@ -72,7 +72,7 @@ void vTaskFPGA_COMM( void * Parameters ) /* Check if the FPGA has finished programming itself from the FLASH */ while (!gpio_read_pin( PIN_PORT(GPIO_FPGA_DONE_B), PIN_NUMBER(GPIO_FPGA_DONE_B))) { - vTaskDelay(FPGA_UPDATE_RATE); + vTaskDelay(pdMS_TO_TICKS(FPGA_UPDATE_RATE)); } ssp_init( FPGA_SPI, FPGA_SPI_BITRATE, FPGA_SPI_FRAME_SIZE, SSP_MASTER, SSP_POLLING ); @@ -119,7 +119,7 @@ void vTaskFPGA_COMM( void * Parameters ) /* Data Valid byte - indicates that the bus is idle */ write_fpga_dword( 0x05, 0xAAAAAAAA ); - vTaskDelay(FPGA_UPDATE_RATE); + vTaskDelay(pdMS_TO_TICKS(FPGA_UPDATE_RATE)); } } diff --git a/modules/fru.c b/modules/fru.c index 400789250..53b4a06e8 100644 --- a/modules/fru.c +++ b/modules/fru.c @@ -47,7 +47,7 @@ void fru_init( uint8_t id ) fru[id].fru_size = fru[id].cfg.build_f( &fru[id].buffer ); printf(" Writing FRU info to EEPROM... \n"); - fru[id].cfg.write_f( fru[id].cfg.eeprom_id, 0x00, fru[id].buffer, fru[id].fru_size, 10 ); + fru[id].cfg.write_f( fru[id].cfg.eeprom_id, 0x00, fru[id].buffer, fru[id].fru_size, pdMS_TO_TICKS(10) ); #endif /* Read FRU info Common Header */ @@ -91,14 +91,14 @@ uint8_t fru_check_integrity( uint8_t id, size_t *fru_size ) if (fru[id].runtime) { rec_len = fru[id].buffer[chassis_off+1]; } else { - fru[id].cfg.read_f( fru[id].cfg.eeprom_id, chassis_off+1, &rec_len, 1, 10 ); + fru[id].cfg.read_f( fru[id].cfg.eeprom_id, chassis_off+1, &rec_len, 1, pdMS_TO_TICKS(10) ); } rec_len *= 8; if (rec_len > 0) { if (fru[id].runtime) { memcpy( &rec_buff[0], &fru[id].buffer[chassis_off], rec_len); } else { - fru[id].cfg.read_f( fru[id].cfg.eeprom_id, chassis_off, &rec_buff[0], rec_len, 10 ); + fru[id].cfg.read_f( fru[id].cfg.eeprom_id, chassis_off, &rec_buff[0], rec_len, pdMS_TO_TICKS(10) ); } if ( !((calculate_chksum( &rec_buff[0], rec_len ) == 0) && rec_buff[0] == 1) ) { /* Wrong checksum */ @@ -116,7 +116,7 @@ uint8_t fru_check_integrity( uint8_t id, size_t *fru_size ) if (fru[id].runtime) { rec_len = fru[id].buffer[board_off+1]; } else { - fru[id].cfg.read_f( fru[id].cfg.eeprom_id, board_off+1, &rec_len, 1, 10 ); + fru[id].cfg.read_f( fru[id].cfg.eeprom_id, board_off+1, &rec_len, 1, pdMS_TO_TICKS(10) ); } rec_len *= 8; @@ -124,7 +124,7 @@ uint8_t fru_check_integrity( uint8_t id, size_t *fru_size ) if (fru[id].runtime) { memcpy( &rec_buff[0], &fru[id].buffer[board_off], rec_len); } else { - fru[id].cfg.read_f( fru[id].cfg.eeprom_id, board_off, &rec_buff[0], rec_len, 10 ); + fru[id].cfg.read_f( fru[id].cfg.eeprom_id, board_off, &rec_buff[0], rec_len, pdMS_TO_TICKS(10) ); } if ( !((calculate_chksum( &rec_buff[0], rec_len ) == 0) && rec_buff[0] == 1) ) { /* Wrong checksum */ @@ -142,7 +142,7 @@ uint8_t fru_check_integrity( uint8_t id, size_t *fru_size ) if (fru[id].runtime) { rec_len = fru[id].buffer[product_off+1]; } else { - fru[id].cfg.read_f( fru[id].cfg.eeprom_id, product_off+1, &rec_len, 1, 10 ); + fru[id].cfg.read_f( fru[id].cfg.eeprom_id, product_off+1, &rec_len, 1, pdMS_TO_TICKS(10) ); } rec_len *= 8; @@ -150,7 +150,7 @@ uint8_t fru_check_integrity( uint8_t id, size_t *fru_size ) if (fru[id].runtime) { memcpy( &rec_buff[0], &fru[id].buffer[product_off], rec_len); } else { - fru[id].cfg.read_f( fru[id].cfg.eeprom_id, product_off, &rec_buff[0], rec_len, 10 ); + fru[id].cfg.read_f( fru[id].cfg.eeprom_id, product_off, &rec_buff[0], rec_len, pdMS_TO_TICKS(10) ); } if ( !((calculate_chksum( &rec_buff[0], rec_len ) == 0 ) && rec_buff[0] == 1) ) { /* Wrong checksum */ @@ -172,7 +172,7 @@ uint8_t fru_check_integrity( uint8_t id, size_t *fru_size ) if (fru[id].runtime) { memcpy( &rec_buff[0], &fru[id].buffer[multirec_off], 5); } else { - fru[id].cfg.read_f( fru[id].cfg.eeprom_id, multirec_off, &rec_buff[0], 5, 10 ); + fru[id].cfg.read_f( fru[id].cfg.eeprom_id, multirec_off, &rec_buff[0], 5, pdMS_TO_TICKS(10) ); } /* Calculate Multirecord header checksum */ if ( !(calculate_chksum( &rec_buff[0], 5 ) == 0) ) { @@ -190,7 +190,7 @@ uint8_t fru_check_integrity( uint8_t id, size_t *fru_size ) if (fru[id].runtime) { memcpy( &rec_buff[0], &fru[id].buffer[multirec_off], rec_len ); } else { - fru[id].cfg.read_f( fru[id].cfg.eeprom_id, multirec_off, &rec_buff[0], rec_len, 10 ); + fru[id].cfg.read_f( fru[id].cfg.eeprom_id, multirec_off, &rec_buff[0], rec_len, pdMS_TO_TICKS(10) ); } if ( !((calculate_chksum( &rec_buff[0], rec_len ) == rec_chksum)) ) { /* Wrong checksum */ @@ -243,7 +243,7 @@ size_t fru_read( uint8_t id, uint8_t *rx_buff, uint16_t offset, size_t len ) * Read EEPROM FRU info */ } else { - ret_val = fru[id].cfg.read_f( fru[id].cfg.eeprom_id, offset, rx_buff, len, 10 ); + ret_val = fru[id].cfg.read_f( fru[id].cfg.eeprom_id, offset, rx_buff, len, pdMS_TO_TICKS(10) ); } return ret_val; } @@ -255,7 +255,7 @@ size_t fru_write( uint8_t id, uint8_t *tx_buff, uint16_t offset, size_t len ) if ( id >= FRU_COUNT ) { return 0; } - ret_val = fru[id].cfg.write_f( fru[id].cfg.eeprom_id, offset, tx_buff, len, 10 ); + ret_val = fru[id].cfg.write_f( fru[id].cfg.eeprom_id, offset, tx_buff, len, pdMS_TO_TICKS(10) ); return ret_val; } diff --git a/modules/max116xx.c b/modules/max116xx.c index bb0ce19cd..15288187d 100644 --- a/modules/max116xx.c +++ b/modules/max116xx.c @@ -45,7 +45,7 @@ mmc_err max116xx_set_config(uint8_t chip_id, const max116xx_cfg* cfg) setup_cfg[0] = 0x80 | cfg->ref_sel | cfg->clk_sel | cfg->pol_sel | 0b10; setup_cfg[1] = cfg->scan_mode | (cfg->channel_sel << 1) | cfg->diff_mode; - if (i2c_take_by_chipid(chip_id, &i2c_addr, &i2c_id, (TickType_t) 10)) { + if (i2c_take_by_chipid(chip_id, &i2c_addr, &i2c_id, pdMS_TO_TICKS(10))) { tx_len = xI2CMasterWrite(i2c_id, i2c_addr, setup_cfg, sizeof(setup_cfg)); i2c_give(i2c_id); } else { @@ -69,7 +69,7 @@ mmc_err max116xx_read_uni(uint8_t chip_id, int16_t data[], uint8_t samples) return MMC_INVALID_ARG_ERR; } - if (i2c_take_by_chipid(chip_id, &i2c_addr, &i2c_id, (TickType_t) 10)) { + if (i2c_take_by_chipid(chip_id, &i2c_addr, &i2c_id, pdMS_TO_TICKS(10))) { rx_len = xI2CMasterRead(i2c_id, i2c_addr, (uint8_t*)data, (samples * 2)); i2c_give(i2c_id); } else { @@ -101,7 +101,7 @@ mmc_err max116xx_read_bip(uint8_t chip_id, int16_t data[], uint8_t samples) return MMC_INVALID_ARG_ERR; } - if (i2c_take_by_chipid(chip_id, &i2c_addr, &i2c_id, (TickType_t) 10)) { + if (i2c_take_by_chipid(chip_id, &i2c_addr, &i2c_id, pdMS_TO_TICKS(10))) { rx_len = xI2CMasterRead(i2c_id, i2c_addr, (uint8_t*)data, (samples * 2)); i2c_give(i2c_id); } else { diff --git a/modules/mcp23016.c b/modules/mcp23016.c index 0253be804..1f63962a9 100644 --- a/modules/mcp23016.c +++ b/modules/mcp23016.c @@ -55,7 +55,7 @@ static mmc_err mcp23016_read_reg ( uint8_t reg, uint8_t *readout ) return MMC_INVALID_ARG_ERR; } - if( i2c_take_by_chipid( CHIP_ID_MCP23016, &i2c_addr, &i2c_id, (TickType_t) 10) ) { + if( i2c_take_by_chipid( CHIP_ID_MCP23016, &i2c_addr, &i2c_id, pdMS_TO_TICKS(10)) ) { rx_len = xI2CMasterWriteRead(i2c_id, i2c_addr, ®, 1, data, sizeof(data)); i2c_give(i2c_id); } else { @@ -90,7 +90,7 @@ static mmc_err mcp23016_write_reg (uint8_t reg, uint8_t data) { cmd_data[0] = reg; cmd_data[1] = data; - if( i2c_take_by_chipid( CHIP_ID_MCP23016, &i2c_addr, &i2c_id, (TickType_t) 10) ) { + if( i2c_take_by_chipid( CHIP_ID_MCP23016, &i2c_addr, &i2c_id, pdMS_TO_TICKS(10)) ) { tx_len = xI2CMasterWrite(i2c_id, i2c_addr, cmd_data, sizeof(cmd_data)); i2c_give(i2c_id); } else { @@ -176,7 +176,7 @@ mmc_err mcp23016_read_reg_pair ( uint8_t reg, uint16_t *readout ) { uint8_t rx_len = 0; uint8_t data[2] = {0}; - if( i2c_take_by_chipid( CHIP_ID_MCP23016, &i2c_addr, &i2c_id, (TickType_t) 10) ) { + if( i2c_take_by_chipid( CHIP_ID_MCP23016, &i2c_addr, &i2c_id, pdMS_TO_TICKS(10)) ) { rx_len = xI2CMasterWriteRead(i2c_id, i2c_addr, ®, 1, data, sizeof(data)); i2c_give(i2c_id); } else { @@ -203,7 +203,7 @@ mmc_err mcp23016_write_reg_pair ( uint8_t reg, uint16_t data ) }; uint8_t tx_len = 0; - if( i2c_take_by_chipid( CHIP_ID_MCP23016, &i2c_addr, &i2c_id, (TickType_t) 10) ) { + if( i2c_take_by_chipid( CHIP_ID_MCP23016, &i2c_addr, &i2c_id, pdMS_TO_TICKS(10)) ) { tx_len = xI2CMasterWrite(i2c_id, i2c_addr, cmd_data, sizeof(cmd_data)); i2c_give(i2c_id); } else { diff --git a/modules/rtm.c b/modules/rtm.c index 024789396..0b853cd51 100644 --- a/modules/rtm.c +++ b/modules/rtm.c @@ -57,7 +57,7 @@ void RTM_Manage( void * Parameters ) rtm_disable_payload_power(); for ( ;; ) { - vTaskDelay(500); + vTaskDelay(pdMS_TO_TICKS(500)); rtm_check_presence( &ps_new_state ); diff --git a/modules/sensors/ina3221.c b/modules/sensors/ina3221.c index 8c7d39a0e..d71b96f62 100644 --- a/modules/sensors/ina3221.c +++ b/modules/sensors/ina3221.c @@ -51,7 +51,7 @@ void vTaskINA3221( void *Parameters ) uint8_t channel; TickType_t xLastWakeTime; /* Task will run every 100ms */ - const TickType_t xFrequency = INA3221_UPDATE_RATE / portTICK_PERIOD_MS; + const TickType_t xFrequency = pdMS_TO_TICKS(INA3221_UPDATE_RATE); sensor_t * ina3221_sensor; ina3221_data_t * data_ptr; diff --git a/modules/sensors/lm75.c b/modules/sensors/lm75.c index 04b8389ec..ca6936ae0 100644 --- a/modules/sensors/lm75.c +++ b/modules/sensors/lm75.c @@ -46,7 +46,7 @@ TaskHandle_t vTaskLM75_Handle; void vTaskLM75( void* Parameters ) { - const TickType_t xFrequency = LM75_UPDATE_RATE; + const TickType_t xFrequency = pdMS_TO_TICKS(LM75_UPDATE_RATE); uint8_t i2c_addr, i2c_interf; sensor_t * temp_sensor; diff --git a/modules/sensors/max6642.c b/modules/sensors/max6642.c index b2bc9cb82..df37647ed 100644 --- a/modules/sensors/max6642.c +++ b/modules/sensors/max6642.c @@ -45,7 +45,7 @@ TaskHandle_t vTaskMAX6642_Handle; void vTaskMAX6642( void* Parameters ) { - const TickType_t xFrequency = MAX6642_UPDATE_RATE; + const TickType_t xFrequency = pdMS_TO_TICKS(MAX6642_UPDATE_RATE); sensor_t * temp_sensor; diff --git a/modules/watchdog.c b/modules/watchdog.c index f4c17b1e3..e5c6d3694 100644 --- a/modules/watchdog.c +++ b/modules/watchdog.c @@ -61,7 +61,7 @@ void WatchdogTask (void * Parameters) } wdt_feed(); //printf(" Watchdog fed (again) \n "); - vTaskDelay(WATCHDOG_FEED_DELAY); + vTaskDelay(pdMS_TO_TICKS(WATCHDOG_FEED_DELAY)); } } diff --git a/port/board/afc-v4/payload.c b/port/board/afc-v4/payload.c index 16a29a8a0..08fc3aa1d 100644 --- a/port/board/afc-v4/payload.c +++ b/port/board/afc-v4/payload.c @@ -98,7 +98,7 @@ uint8_t setDC_DC_ConvertersON(bool on) for (uint8_t i = 0; i < (sizeof(power_pins) / sizeof(power_pins[0])); i++) { pin = power_pins[i]; mcp23016_write_pin( ext_gpios[pin].port_num, ext_gpios[pin].pin_num, true ); - vTaskDelay(10); + vTaskDelay(pdMS_TO_TICKS(10)); } } else { printf("Disable Power\n"); @@ -106,7 +106,7 @@ uint8_t setDC_DC_ConvertersON(bool on) for (uint8_t i = (sizeof(power_pins) / sizeof(power_pins[0])); i > 0; i--) { pin = power_pins[i]; mcp23016_write_pin( ext_gpios[pin].port_num, ext_gpios[pin].pin_num, false ); - vTaskDelay(10); + vTaskDelay(pdMS_TO_TICKS(10)); } } return 1; From 37bdc294c896e1e8414328a1871e3d22c01d20e2 Mon Sep 17 00:00:00 2001 From: Gustavo de Souza dos Reis Date: Fri, 23 Feb 2024 14:15:50 -0300 Subject: [PATCH 32/43] Remove unnecessary functionality from the Watchdog module --- modules/watchdog.c | 16 ---------------- 1 file changed, 16 deletions(-) diff --git a/modules/watchdog.c b/modules/watchdog.c index e5c6d3694..80f4e40e9 100644 --- a/modules/watchdog.c +++ b/modules/watchdog.c @@ -37,18 +37,11 @@ #include "task_priorities.h" #include "uart_debug.h" -#define WATCHDOG_CLK_FREQ 8000000 -#define WATCHDOG_TIMEOUT 1000 /* in milisseconds */ -#define WATCHDOG_FEED_DELAY (WATCHDOG_TIMEOUT/3)*2 - -SemaphoreHandle_t watchdog_smphr; - void watchdog_init( void ) { wdt_init(); wdt_config(); wdt_set_timeout(((WATCHDOG_TIMEOUT/1000)*WATCHDOG_CLK_FREQ)); - watchdog_smphr = xSemaphoreCreateBinary(); xTaskCreate( WatchdogTask, (const char *) "Watchdog Task", 60, (void * ) NULL, tskWATCHDOG_PRIORITY, ( TaskHandle_t * ) NULL); } @@ -56,16 +49,7 @@ void WatchdogTask (void * Parameters) { wdt_start(); for ( ;; ) { - if (xSemaphoreTake(watchdog_smphr, 0)) { - NVIC_SystemReset(); - } wdt_feed(); - //printf(" Watchdog fed (again) \n "); vTaskDelay(pdMS_TO_TICKS(WATCHDOG_FEED_DELAY)); } } - -void watchdog_reset_mcu( void ) -{ - xSemaphoreGive(watchdog_smphr); -} From 37e2ad0a455ec083b97880bf4d86845af8102baa Mon Sep 17 00:00:00 2001 From: Gustavo de Souza dos Reis Date: Fri, 23 Feb 2024 13:20:40 -0300 Subject: [PATCH 33/43] Improve i2c eeprom write functions to only incremend addr if success --- modules/at24mac.c | 1 - modules/eeprom_24xx02.c | 28 +++++++++++++++++----------- modules/eeprom_24xx64.c | 27 +++++++++++++++++---------- 3 files changed, 34 insertions(+), 22 deletions(-) diff --git a/modules/at24mac.c b/modules/at24mac.c index fdfb84871..d840bd4b5 100644 --- a/modules/at24mac.c +++ b/modules/at24mac.c @@ -118,7 +118,6 @@ size_t at24mac_write( uint8_t id, uint16_t address, uint8_t *tx_data, size_t buf if (i2c_written) { tx_len += i2c_written - 1; /* Remove byte address from data written size */ curr_addr += i2c_written - 1; - i2c_written = 0; } i2c_give( i2c_interface ); } diff --git a/modules/eeprom_24xx02.c b/modules/eeprom_24xx02.c index 9fb16a3b2..11fc2fd90 100644 --- a/modules/eeprom_24xx02.c +++ b/modules/eeprom_24xx02.c @@ -60,16 +60,13 @@ size_t eeprom_24xx02_write( uint8_t id, uint16_t address, uint8_t *tx_data, size uint8_t i2c_addr; uint8_t i2c_interface; uint8_t bytes_to_write; + uint8_t i2c_written = 0; uint8_t page_buf[9]; uint16_t curr_addr; size_t tx_len = 0; - if ( tx_data == NULL ) { - return 0; - } - - if (i2c_take_by_chipid( id, &i2c_addr, &i2c_interface, timeout)) { + if ( tx_data != NULL ) { curr_addr = address; while (tx_len < buf_len) { @@ -82,13 +79,22 @@ size_t eeprom_24xx02_write( uint8_t id, uint16_t address, uint8_t *tx_data, size memcpy(&page_buf[1], tx_data+tx_len, bytes_to_write); - /* Write the data */ - tx_len += xI2CMasterWrite( i2c_interface, i2c_addr, &page_buf[0] , bytes_to_write+1 ); - vTaskDelay(10); - tx_len -= 1; /* Remove the page byte from the count */ - curr_addr += bytes_to_write; + if (i2c_take_by_chipid( id, &i2c_addr, &i2c_interface, timeout)) { + /* Write the data */ + i2c_written = xI2CMasterWrite( i2c_interface, i2c_addr, &page_buf[0] , bytes_to_write+1 ); + /* When trying to write, the EEPROM will reply with NACKs if it's busy. + * If the i2c receives a NACK when trying to write, the function returns only + * the number of bytes successfully written, and we should increment only this value + * in tx_len and in curr_addr */ + + if (i2c_written) { + tx_len += i2c_written - 1; /* Remove byte address from data written size */ + curr_addr += i2c_written - 1; + } + i2c_give( i2c_interface ); + } + vTaskDelay(pdMS_TO_TICKS(1)); /* Avoid too much unnecessary I2C trafic*/ } - i2c_give( i2c_interface ); } return tx_len; diff --git a/modules/eeprom_24xx64.c b/modules/eeprom_24xx64.c index 78f056ace..a51386c60 100644 --- a/modules/eeprom_24xx64.c +++ b/modules/eeprom_24xx64.c @@ -66,14 +66,12 @@ size_t eeprom_24xx64_write( uint8_t id, uint16_t address, uint8_t *tx_data, size uint8_t bytes_to_write; uint8_t page_buf[34]; uint16_t curr_addr; + uint8_t i2c_written = 0; size_t tx_len = 0; - if ( tx_data == NULL ) { - return 0; - } - if (i2c_take_by_chipid( id, &i2c_addr, &i2c_interface, timeout)) { + if ( tx_data != NULL ) { curr_addr = address; while (tx_len < buf_len) { @@ -87,13 +85,22 @@ size_t eeprom_24xx64_write( uint8_t id, uint16_t address, uint8_t *tx_data, size memcpy(&page_buf[2], tx_data+tx_len, bytes_to_write); - /* Write the data */ - tx_len += xI2CMasterWrite( i2c_interface, i2c_addr, &page_buf[0] , bytes_to_write+2 ); - vTaskDelay(pdMS_TO_TICKS(10)); - tx_len -= 2; /* Remove the 2 page bytes from the count */ - curr_addr += bytes_to_write; + if (i2c_take_by_chipid( id, &i2c_addr, &i2c_interface, timeout)) { + /* Write the data */ + i2c_written = xI2CMasterWrite( i2c_interface, i2c_addr, &page_buf[0] , bytes_to_write+2 ); + /* When trying to write, the EEPROM will reply with NACKs if it's busy. + * If the i2c receives a NACK when trying to write, the function returns only + * the number of bytes successfully written, and we should increment only this value + * in tx_len and in curr_addr */ + + if (i2c_written) { + tx_len += i2c_written - 2; /* Remove byte address from data written size */ + curr_addr += i2c_written - 2; + } + i2c_give( i2c_interface ); + } + vTaskDelay(pdMS_TO_TICKS(1)); /* Avoid too much unnecessary I2C trafic*/ } - i2c_give( i2c_interface ); } return tx_len; From e88b30b26c9dc05662d84e35b51fc81d7ecf7561 Mon Sep 17 00:00:00 2001 From: Gustavo de Souza dos Reis Date: Wed, 6 Mar 2024 13:28:57 -0300 Subject: [PATCH 34/43] Increase block_data size to allocate the uploaded firmware block Solve #194: the block_sz was reaching the value 23, and block_data had only 20 bytes allocated (HPM_BLOCK_SIZE), so the memcpy call was corrupting the stack. After returning from req_handler, the restored value of R4 got corrupted resulting in an invalid memory access in the xQueueReceive function. --- modules/hpm.c | 8 +++++++- modules/hpm.h | 4 ++-- 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/modules/hpm.c b/modules/hpm.c index 747931673..9ab734c41 100644 --- a/modules/hpm.c +++ b/modules/hpm.c @@ -216,7 +216,7 @@ IPMI_HANDLER(ipmi_picmg_initiate_upgrade_action, NETFN_GRPEXT, IPMI_PICMG_CMD_HP uint8_t len = rsp->data_len = 0; uint8_t comp_id; - + /* Set the component that'll be upgraded */ /* * As specified in the Hardware Platform Management IPM Controller Firmware Upgrade Specification, Table 3-4, @@ -310,6 +310,12 @@ IPMI_HANDLER(ipmi_picmg_upload_firmware_block, NETFN_GRPEXT, IPMI_PICMG_CMD_HPM_ uint8_t block_data[HPM_BLOCK_SIZE]; uint8_t block_sz = req->data_len-2; + if(block_sz > HPM_BLOCK_SIZE){ + rsp->data_len = len; + rsp->completion_code = IPMI_CC_UNSPECIFIED_ERROR; + return; + } + if (active_component == NULL) { /* Component ID out of range */ rsp->data[len++] = IPMI_PICMG_GRP_EXT; diff --git a/modules/hpm.h b/modules/hpm.h index 53b3af296..c68c08df6 100644 --- a/modules/hpm.h +++ b/modules/hpm.h @@ -36,7 +36,7 @@ #define HPM_ROLLBACK_TIMEOUT 10 /* in 5 seconds counts */ #define HPM_INACCESSIBILITY_TIMEOUT 10 /* in 5 seconds counts */ -#define HPM_BLOCK_SIZE 20 +#define HPM_BLOCK_SIZE 64 /* Components ID */ enum { @@ -54,7 +54,7 @@ typedef uint8_t (* t_hpm_activate_firmware)(void); /* - * Define the "Get target upgrade capabilities" message struct as define in the + * Define the "Get target upgrade capabilities" message struct as define in the * Hardware Platform Management IPM Controller Firmware Upgrade Specification, Table 3-3 */ typedef union { From 746fb2981ed2c79376f26333ecd0190dec24811d Mon Sep 17 00:00:00 2001 From: Gustavo de Souza dos Reis Date: Thu, 7 Mar 2024 13:25:54 -0300 Subject: [PATCH 35/43] Handle FMC power good signals --- port/board/afc-v3/payload.c | 5 +++++ port/board/afc-v4/payload.c | 6 ++++++ 2 files changed, 11 insertions(+) diff --git a/port/board/afc-v3/payload.c b/port/board/afc-v3/payload.c index 326e388de..7b73ed921 100644 --- a/port/board/afc-v3/payload.c +++ b/port/board/afc-v3/payload.c @@ -311,6 +311,8 @@ void vTaskPayload( void *pvParameters ) break; case PAYLOAD_STATE_FPGA_SETUP: + gpio_set_pin_state(PIN_PORT(GPIO_FMC1_PG_C2M), PIN_NUMBER(GPIO_FMC1_PG_C2M), GPIO_LEVEL_HIGH); + gpio_set_pin_state(PIN_PORT(GPIO_FMC2_PG_C2M), PIN_NUMBER(GPIO_FMC2_PG_C2M), GPIO_LEVEL_HIGH); #ifdef MODULE_ADN4604 /* Configure clock switch */ if (clock_configuration() == MMC_OK) { @@ -330,6 +332,9 @@ void vTaskPayload( void *pvParameters ) case PAYLOAD_SWITCHING_OFF: setDC_DC_ConvertersON( false ); + gpio_set_pin_state(PIN_PORT(GPIO_FMC1_PG_C2M), PIN_NUMBER(GPIO_FMC1_PG_C2M), GPIO_LEVEL_LOW); + gpio_set_pin_state(PIN_PORT(GPIO_FMC2_PG_C2M), PIN_NUMBER(GPIO_FMC2_PG_C2M), GPIO_LEVEL_LOW); + /* Respond to quiesce event if any */ if ( QUIESCED_req ) { hotswap_set_mask_bit( HOTSWAP_AMC, HOTSWAP_QUIESCED_MASK ); diff --git a/port/board/afc-v4/payload.c b/port/board/afc-v4/payload.c index 08fc3aa1d..438a9f90d 100644 --- a/port/board/afc-v4/payload.c +++ b/port/board/afc-v4/payload.c @@ -393,6 +393,9 @@ void vTaskPayload( void *pvParameters ) break; case PAYLOAD_STATE_FPGA_SETUP: + gpio_set_pin_state(PIN_PORT(GPIO_FMC1_PG_C2M), PIN_NUMBER(GPIO_FMC1_PG_C2M), GPIO_LEVEL_HIGH); + gpio_set_pin_state(PIN_PORT(GPIO_FMC2_PG_C2M), PIN_NUMBER(GPIO_FMC2_PG_C2M), GPIO_LEVEL_HIGH); + /* Configure the clock switch according to the configuration saved in EEPROM*/ eeprom_24xx02_read(CHIP_ID_RTC_EEPROM, 0x0, clock_config, 16, 10); /* Only change the state if the clock config is efective*/ @@ -412,6 +415,9 @@ void vTaskPayload( void *pvParameters ) gpio_set_pin_state(PIN_PORT(GPIO_FPGA_INITB), PIN_NUMBER(GPIO_FPGA_INITB), GPIO_LEVEL_LOW); err = mcp23016_write_pin( ext_gpios[EXT_GPIO_PROGRAM_B].port_num, ext_gpios[EXT_GPIO_PROGRAM_B].pin_num, false ); + gpio_set_pin_state(PIN_PORT(GPIO_FMC1_PG_C2M), PIN_NUMBER(GPIO_FMC1_PG_C2M), GPIO_LEVEL_LOW); + gpio_set_pin_state(PIN_PORT(GPIO_FMC2_PG_C2M), PIN_NUMBER(GPIO_FMC2_PG_C2M), GPIO_LEVEL_LOW); + if (err != MMC_OK) { PRINT_ERR_LINE(err); } From 3e0d9e7792508fa8c7e649a76399fc0eb20914a2 Mon Sep 17 00:00:00 2001 From: Gustavo de Souza dos Reis Date: Thu, 7 Mar 2024 10:04:05 -0300 Subject: [PATCH 36/43] Add support to bootloader self-update --- port/ucontroller/nxp/lpc17xx/lpc17_hpm.c | 97 ++++++++---------------- port/ucontroller/nxp/lpc17xx/lpc17_hpm.h | 8 +- 2 files changed, 35 insertions(+), 70 deletions(-) diff --git a/port/ucontroller/nxp/lpc17xx/lpc17_hpm.c b/port/ucontroller/nxp/lpc17xx/lpc17_hpm.c index 77204b5e9..656ecf121 100644 --- a/port/ucontroller/nxp/lpc17xx/lpc17_hpm.c +++ b/port/ucontroller/nxp/lpc17xx/lpc17_hpm.c @@ -82,7 +82,7 @@ static uint8_t get_sector_number(const void* flash_addr) return ret; } -uint8_t hpm_prepare_comp(enum memory_area area) +uint8_t hpm_prepare_comp( void ) { finish_upload_success = false; ipmc_image_size = 0; @@ -94,20 +94,9 @@ uint8_t hpm_prepare_comp(enum memory_area area) for (uint32_t i=0; i<(sizeof(ipmc_page)/sizeof(uint32_t)); i++) { ipmc_page[i] = 0xFFFFFFFF; } - const uint32_t *start, *end; - - if (area == BOOT_FLASH) { - start = boot_start_addr; - end = boot_end_addr; - } else if (area == FW_UPDATE_FLASH) { - start = update_start_addr; - end = update_end_addr; - } else { - return IPMI_CC_PARAM_OUT_OF_RANGE; - } /* Checks flash update region integrity */ - for (const uint32_t *ptr = start; ptr <= end; ptr++) { + for (const uint32_t *ptr = update_start_addr; ptr <= update_end_addr; ptr++){ if (*ptr != 0xFFFFFFFF) { const uint32_t sec = get_sector_number(ptr); @@ -132,15 +121,15 @@ uint8_t hpm_prepare_comp(enum memory_area area) uint8_t ipmc_hpm_prepare_comp(void) { - return hpm_prepare_comp(FW_UPDATE_FLASH); + return hpm_prepare_comp(); } uint8_t bootloader_hpm_prepare_comp(void) { - return hpm_prepare_comp(BOOT_FLASH); + return hpm_prepare_comp(); } -uint8_t hpm_upload_block(uint8_t *block, uint16_t size, enum memory_area area) +uint8_t hpm_upload_block(uint8_t *block, uint16_t size) { const uint32_t ipmc_page_available_bytes_n = sizeof(ipmc_page) - ipmc_page_byte_index; @@ -157,7 +146,7 @@ uint8_t hpm_upload_block(uint8_t *block, uint16_t size, enum memory_area area) ipmc_page_byte_index = 0; /* Program the complete page in the Flash */ - program_page(ipmc_page_addr, ipmc_page, sizeof(ipmc_page), area); + program_page(ipmc_page_addr, ipmc_page, sizeof(ipmc_page)); /* Advance the address counter */ ipmc_page_addr += sizeof(ipmc_page); @@ -177,20 +166,20 @@ uint8_t hpm_upload_block(uint8_t *block, uint16_t size, enum memory_area area) uint8_t ipmc_hpm_upload_block(uint8_t *block, uint16_t size) { - return hpm_upload_block(block, size, FW_UPDATE_FLASH); + return hpm_upload_block(block, size); } uint8_t bootloader_hpm_upload_block(uint8_t *block, uint16_t size) { - return hpm_upload_block(block, size, BOOT_FLASH); + return hpm_upload_block(block, size); } -uint8_t hpm_finish_upload(uint32_t image_size, enum memory_area area) +uint8_t hpm_finish_upload(uint32_t image_size) { /* Check if the last page was already programmed */ if(ipmc_page_byte_index != 0) { /* Program the complete page in the Flash */ - program_page( ipmc_page_addr, ipmc_page, sizeof(ipmc_page), area); + program_page(ipmc_page_addr, ipmc_page, sizeof(ipmc_page)); ipmc_image_size += ipmc_page_byte_index; ipmc_page_byte_index = 0; ipmc_page_addr = 0; @@ -210,12 +199,12 @@ uint8_t hpm_finish_upload(uint32_t image_size, enum memory_area area) uint8_t ipmc_hpm_finish_upload(uint32_t image_size) { - return hpm_finish_upload(image_size, FW_UPDATE_FLASH); + return hpm_finish_upload(image_size); } uint8_t bootloader_hpm_finish_upload(uint32_t image_size) { - return hpm_finish_upload(image_size, BOOT_FLASH); + return hpm_finish_upload(image_size); } uint8_t ipmc_hpm_get_upgrade_status(void) @@ -230,7 +219,7 @@ uint8_t bootloader_hpm_get_upgrade_status(void) return IPMI_CC_OK; } -uint8_t ipmc_hpm_activate_firmware(void) +uint8_t hpm_activate_firmware( enum fw_type type ) { /* * Doesn't write the magic word if the function hpm_finish_upload fails @@ -249,12 +238,12 @@ uint8_t ipmc_hpm_activate_firmware(void) * TODO: Write actual firmware ID */ fw_update_header.magic = 0xAAAAAAAA; - fw_update_header.fw_type = 1; // Update application + fw_update_header.fw_type = type; // 2 -> bootloader | 1 -> application fw_update_header.version[0] = 1; fw_update_header.version[1] = 4; fw_update_header.version[2] = 1; - program_page((uint32_t)fw_header - (uint32_t)update_start_addr, (uint32_t*)&fw_update_header, sizeof(fw_update_header), FW_UPDATE_FLASH); + program_page((uint32_t)fw_header - (uint32_t)update_start_addr, (uint32_t*)&fw_update_header, sizeof(fw_update_header)); /* * Schedule a reset to 500ms from now @@ -264,21 +253,17 @@ uint8_t ipmc_hpm_activate_firmware(void) return IPMI_CC_OK; } -uint8_t bootloader_hpm_activate_firmware(void) +uint8_t ipmc_hpm_activate_firmware(void) { - /* - * Doesn't activate the firmware if the function hpm_finish_upload fails - */ - - if (!finish_upload_success) { - return IPMI_CC_UNSPECIFIED_ERROR; - } + hpm_activate_firmware( APPLICATION ); +} - sys_schedule_reset(500); - return IPMI_CC_OK; +uint8_t bootloader_hpm_activate_firmware(void) +{ + hpm_activate_firmware( BOOTLOADER ); } -uint8_t program_page(uint32_t address, uint32_t *data, uint32_t size, enum memory_area area) +uint8_t program_page(uint32_t address, uint32_t *data, uint32_t size) { uint32_t update_start_sec, update_end_sec; @@ -289,37 +274,17 @@ uint8_t program_page(uint32_t address, uint32_t *data, uint32_t size, enum memor return IPMI_CC_PARAM_OUT_OF_RANGE; } - if (area == BOOT_FLASH) { - update_start_sec = get_sector_number(boot_start_addr); - update_end_sec = get_sector_number(boot_end_addr); - - if (Chip_IAP_PreSectorForReadWrite(update_start_sec, update_end_sec) != IAP_CMD_SUCCESS) { - portENABLE_INTERRUPTS(); - return IPMI_CC_UNSPECIFIED_ERROR; - } - - if (Chip_IAP_CopyRamToFlash((uint32_t)boot_start_addr + address, data, size)) { - portENABLE_INTERRUPTS(); - return IPMI_CC_UNSPECIFIED_ERROR; - } - - } else if (area == FW_UPDATE_FLASH) { - update_start_sec = get_sector_number(update_start_addr); - update_end_sec = get_sector_number(update_end_addr); - - if (Chip_IAP_PreSectorForReadWrite(update_start_sec, update_end_sec) != IAP_CMD_SUCCESS) { - portENABLE_INTERRUPTS(); - return IPMI_CC_UNSPECIFIED_ERROR; - } - - if (Chip_IAP_CopyRamToFlash((uint32_t)update_start_addr + address, data, size)) { - portENABLE_INTERRUPTS(); - return IPMI_CC_UNSPECIFIED_ERROR; - } + update_start_sec = get_sector_number(update_start_addr); + update_end_sec = get_sector_number(update_end_addr); + if (Chip_IAP_PreSectorForReadWrite(update_start_sec, update_end_sec) != IAP_CMD_SUCCESS) { + portENABLE_INTERRUPTS(); + return IPMI_CC_UNSPECIFIED_ERROR; + } - } else { - return IPMI_CC_PARAM_OUT_OF_RANGE; + if (Chip_IAP_CopyRamToFlash((uint32_t)update_start_addr + address, data, size)) { + portENABLE_INTERRUPTS(); + return IPMI_CC_UNSPECIFIED_ERROR; } portENABLE_INTERRUPTS(); diff --git a/port/ucontroller/nxp/lpc17xx/lpc17_hpm.h b/port/ucontroller/nxp/lpc17xx/lpc17_hpm.h index b3ff11ea8..5438e5553 100644 --- a/port/ucontroller/nxp/lpc17xx/lpc17_hpm.h +++ b/port/ucontroller/nxp/lpc17xx/lpc17_hpm.h @@ -34,9 +34,9 @@ #define IPMC_UPDATE_SECTOR_END 0x11 #define IPMC_UPDATE_ADDRESS_OFFSET (IPMC_UPDATE_SECTOR_START << 12) -enum memory_area { - BOOT_FLASH, - FW_UPDATE_FLASH +enum fw_type { + APPLICATION = 1, + BOOTLOADER = 2 }; uint8_t ipmc_hpm_prepare_comp(void); @@ -44,7 +44,7 @@ uint8_t ipmc_hpm_upload_block(uint8_t *block, uint16_t size); uint8_t ipmc_hpm_finish_upload(uint32_t image_size); uint8_t ipmc_hpm_activate_firmware(void); uint8_t ipmc_hpm_get_upgrade_status(void); -uint8_t program_page(uint32_t address, uint32_t *data, uint32_t size, enum memory_area area); +uint8_t program_page(uint32_t address, uint32_t *data, uint32_t size); uint8_t ipmc_erase_sector(uint32_t sector_start, uint32_t sector_end); From f952c426c4da18bb2bee4cfadc4ad02ccb9fe637 Mon Sep 17 00:00:00 2001 From: Gustavo de Souza dos Reis Date: Tue, 19 Mar 2024 14:38:10 -0300 Subject: [PATCH 37/43] Dummy handler to receive the I2CSlaveAddr when don't match the IPMBAddr When repeatedly upgrading and downgrading the openMMC via ipmitool, it crashes sporadically at Chip_I2C_SlaveStateHandler. This happens because for some motive, when calling startMasterXfer() sometimes an interrupt occurs for the I2C0 peripheral, and the Chip_I2C_SlaveStateHandler is called, dispatching the handling to the callback registered for I2C_SLAVE_GENERAL. But, this callback is not configured, resulting in a invalid memory access. It is not clear why this interrupt is generated for an I2C slave address other than the expected IPMB address obtained by get_ipmb_addr(), but this should be properly handled and not lead to a crash. Fixes #160. --- port/ucontroller/nxp/lpc17xx/lpc17_i2c.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/port/ucontroller/nxp/lpc17xx/lpc17_i2c.c b/port/ucontroller/nxp/lpc17xx/lpc17_i2c.c index 8c365038d..64d8aee88 100644 --- a/port/ucontroller/nxp/lpc17xx/lpc17_i2c.c +++ b/port/ucontroller/nxp/lpc17xx/lpc17_i2c.c @@ -96,7 +96,9 @@ void vI2CConfig( I2C_ID_T id, uint32_t speed ) static TaskHandle_t slave_task_id; I2C_XFER_T slave_cfg; +I2C_XFER_T slave_dummy; uint8_t recv_msg[i2cMAX_MSG_LENGTH]; +uint8_t recv_msg_dummy[i2cMAX_MSG_LENGTH]; uint8_t recv_bytes; uint8_t xI2CSlaveReceive( I2C_ID_T id, uint8_t * rx_buff, uint8_t buff_len, uint32_t timeout ) @@ -138,6 +140,13 @@ static void I2C_Slave_Event(I2C_ID_T id, I2C_EVENT_T event) } } +/* + * This stub functions is called when the received I2C Slave Address doesn't match the + * expected IPMB address. This seems to be necessary because the lpcopen library tries + * to handle the I2C Slave configuration for I2C_SLAVE_GENERAL even if it's not configured, + * thus dereferencing an invalid unitialized pointer generating a HardFault. + */ +static void I2C_Dummy_Event(I2C_ID_T id, I2C_EVENT_T event){} void vI2CSlaveSetup ( I2C_ID_T id, uint8_t slave_addr ) { @@ -149,6 +158,13 @@ void vI2CSlaveSetup ( I2C_ID_T id, uint8_t slave_addr ) slave_cfg.rxBuff = &recv_msg[0]; slave_cfg.rxSz = (sizeof(recv_msg)/sizeof(recv_msg[0])); Chip_I2C_SlaveSetup( id, I2C_SLAVE_0, &slave_cfg, I2C_Slave_Event, SLAVE_MASK); + + slave_dummy.slaveAddr = 0; + slave_dummy.txBuff = NULL; + slave_dummy.txSz = 0; + slave_dummy.rxBuff = recv_msg_dummy; + slave_dummy.rxSz =(sizeof(recv_msg_dummy)/sizeof(recv_msg_dummy[0])); + Chip_I2C_SlaveSetup( id, I2C_SLAVE_GENERAL, &slave_dummy, I2C_Dummy_Event, SLAVE_MASK); } int xI2CMasterWriteRead(I2C_ID_T id, uint8_t addr, const uint8_t *tx_buff, int tx_len, uint8_t *rx_buff, int rx_len) From 6c62bc76d563c44aa0013d963a0ad052030c8bac Mon Sep 17 00:00:00 2001 From: Gustavo de Souza dos Reis Date: Fri, 22 Mar 2024 14:03:55 -0300 Subject: [PATCH 38/43] Change the TARGET_BOARD_NAME from AFC Timing to AFC v3.1 Since the merge of afc-bpm and afc-timing in afcv3.1, there's no long needed to specify the target board. Also, standardize the AFC v4.0 field. --- port/board/afc-v3/CMakeLists.txt | 2 +- port/board/afc-v4/CMakeLists.txt | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/port/board/afc-v3/CMakeLists.txt b/port/board/afc-v3/CMakeLists.txt index 60a0f91b8..768bafbe8 100644 --- a/port/board/afc-v3/CMakeLists.txt +++ b/port/board/afc-v3/CMakeLists.txt @@ -4,7 +4,7 @@ if (NOT TARGET_CONTROLLER) endif() if (NOT TARGET_BOARD_NAME) - set(TARGET_BOARD_NAME "AFC Timing" CACHE STRING "Board Name") + set(TARGET_BOARD_NAME "AFC v3.1" CACHE STRING "Board Name") endif() #List all modules used by this board diff --git a/port/board/afc-v4/CMakeLists.txt b/port/board/afc-v4/CMakeLists.txt index 26dc10af2..7d39769ad 100644 --- a/port/board/afc-v4/CMakeLists.txt +++ b/port/board/afc-v4/CMakeLists.txt @@ -4,7 +4,7 @@ if (NOT TARGET_CONTROLLER) endif() if (NOT TARGET_BOARD_NAME) - set(TARGET_BOARD_NAME "AFC v4" CACHE STRING "Board Name") + set(TARGET_BOARD_NAME "AFC v4.0" CACHE STRING "Board Name") endif() #List all modules used by this board From 0d0747c4a24009c4faa08d0f25eee39af6d369a2 Mon Sep 17 00:00:00 2001 From: Gustavo de Souza dos Reis Date: Mon, 25 Mar 2024 10:23:06 -0300 Subject: [PATCH 39/43] Update README preparing for v1.6.0 release --- README.md | 21 +++++++++++++++++++-- 1 file changed, 19 insertions(+), 2 deletions(-) diff --git a/README.md b/README.md index d31c1e27e..bfc1354f7 100644 --- a/README.md +++ b/README.md @@ -27,7 +27,7 @@ Create a new folder wherever is suitable cd -Run CMake using the path to the repository folder as an direct argument and the flag `-DBOARD=`(at this moment, only `afc` can be selected) ,`-DVERSION=` (`3.1` or `4.0`) and `-DBOARD_RTM=` (for now, only RTM `8sfp` for AFCv3.1 is supported) to configure the compilation scripts to your specific board hardware. +Run CMake using the path to the repository folder as an direct argument and the flag `-DBOARD=`(at this moment, only `afc` can be selected) ,`-DVERSION=` (`3.1` or `4.0`) and `-DBOARD_RTM=` (`8sfp` or `lamp`) to configure the compilation scripts to your specific board hardware. cmake -DBOARD= -DVERSION= -DBOARD_RTM= @@ -93,6 +93,8 @@ It's also important to mention that you can use the `--help` command in case of ./bin/hpm-downloader --help ### ipmitool +> :warning: **Disclaimer:** Due to [e88b30b](https://github.com/lnls-dig/openMMC/tree/e88b30b26c9dc05662d84e35b51fc81d7ecf7561), the ipmitool fails when trying to upgrade the firmware from v1.5.0. For succeed in upgrade, you can use a modified ipmitool version, setting the variable [`max_rq_size`](https://codeberg.org/IPMITool/ipmitool/src/commit/137aeb64cbb493d61d6945cac156aba5f0510780/lib/ipmi_hpmfwupg.c#L1143) to 20. After this version, you can use the ipmitool normally. + After [5631857](https://github.com/lnls-dig/openMMC/commit/563185791c8b51ea026680c98ec0ea9587ea645b), it's possible to program the firmware and the bootloader through [ipmitool](https://codeberg.org/IPMITool/ipmitool), for previous releases, you still need to use [hpm-downloader](https://github.com/lnls-dig/hpm-downloader). In order to use it, you have to install the ipmitool, and then generate .hpm files from `OpenMMC.bin` and `newboot.bin`. To generate `.hpm` files, you will need to use [bin2hpm](https://github.com/MicroTCA-Tech-Lab/bin2hpm). If you have bin2hpm in your `$PATH`, the `.hpm` files will be automatically generated for you, provided you build from [0095b14](https://github.com/lnls-dig/openMMC/commit/0095b14667afe844113725228671d8810b45d9e0) or more recent versions. After generate the files, you can use the following commands to program the MMC microcontroller. To upgrade the firmware, use @@ -135,12 +137,27 @@ Now you can use the typical GDB commands to inspect the program flow and variabl ## IPMI Custom Commands The IPMI allow us to create custom commands according to the project needs. [ipmitool](https://codeberg.org/IPMITool/ipmitool) can be used to send the commands +### Get free heap memory +It is possible to monitor the MMC's memory usage via IPMI. To obtain the total free heap use command 0x01, netfn_id 0x32. The returned data will be the number of free heap bytes, encoded as a 32 bits unsigned integer, little-endian. + + ipmitool -I lan -H mch_host_name -A none -T 0x82 -m 0x20 -t (112 + num_slot*2) raw 0x32 0x01 + +### Commit Hash read +After loading a new firmware, you can use an ipmi command to read its commit hash to ensure that the running version is the one you want. +The command is the above: + + + ipmitool -I lan -H mch_host_name -A none -T 0x82 -m 0x20 -t (112 + num_slot*2) raw 0x32 0x02 + ### Clock switch configuration -It's possible to configure the clock switch. For the AFC v3.1 (ADN4604ASVZ) you can use the following scheme: +After [7a919489](https://github.com/lnls-dig/openMMC/tree/7a91948975f87f6613b28fc1ea562a2a7bb3c475) the clock switch configuration is no longer hardcoded for each board. Instead, it must be configured through an IPMI command. + +For the AFC v3.1 (ADN4604ASVZ) you can use the [script](/scripts/afcv3.1-clksw-config.py) for generate the configuration, and use the json configuration for [AFCv3.1-BPM](/config/lnls/afcv3.1-bpm-clk-cfg.json) or [AFCv3.1-Timing](/config/lnls/afcv3.1-timing-clk-cfg.json). If you want to generate a new configuration, use the following scheme: - **Port I/O (bit 7)**: Use it to configure the port as an input ('0') or output ('1'). Unused ports should be left configured as inputs; - **Output Port Signal Source (bits 0 to 3)**: Select the input port for the respective output port. For the AFC v4 (IDT 8V54816) you can use the following scheme: +For the AFC v4.0 (IDT 8V54816) you can use the [script](/scripts/afcv4-clksw-config.py) for generate the configuration, and use the json configuration for [AFCv4.0-FOFB](/config/lnls/afcv4-fofb-clk-cfg.json). If you want to generate a new configuration, use the following scheme: - **Port I/O (bit 7)**: Use it to configure the port as an input ('0') or output ('1'). Unused ports should be left configured as inputs; - **Termination On/Off (bit 6)**: Use to set the internal termination. '0' is off (high-impedance), '1' is on (100 $\Omega$) - **Polarity (bit 5)**: Set the channel polarity. '0' for inverted, '1' for non-inverted From 943db24ef4043cf3719b38f797901b006a80aa51 Mon Sep 17 00:00:00 2001 From: Augusto Fraga Giachero Date: Wed, 13 Mar 2024 13:57:32 -0300 Subject: [PATCH 40/43] Fix incorrect clock switch configuration for AFCv3.1 Timing --- config/lnls/afcv3.1-timing-clk-cfg.json | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/config/lnls/afcv3.1-timing-clk-cfg.json b/config/lnls/afcv3.1-timing-clk-cfg.json index 0925ddc21..66ad77b96 100644 --- a/config/lnls/afcv3.1-timing-clk-cfg.json +++ b/config/lnls/afcv3.1-timing-clk-cfg.json @@ -111,7 +111,7 @@ "SRC": "CLK20_VCXO", "EN": false }, - "FMC2_CLK2_BIDIR": { + "FIN2_CLK3": { "SRC": "FMC2_CLK2_BIDIR", "EN": false } From ba4cab68b2655544a349b985625494931277b8a7 Mon Sep 17 00:00:00 2001 From: Augusto Fraga Giachero Date: Wed, 8 May 2024 15:19:36 -0300 Subject: [PATCH 41/43] Load clock config data from EEPROM at payload initialization The 'clock_config' global buffer should be initialized with the contents of the EEPROM clock configuration segment at payload_init(), otherwise if the board starts at M1 after reset, reading the clock configuration via IPMI will return a zeroed array. --- port/board/afc-v3/payload.c | 76 ++++++++++++++++++------------------- port/board/afc-v3/payload.h | 3 +- port/board/afc-v4/payload.c | 11 ++++-- 3 files changed, 47 insertions(+), 43 deletions(-) diff --git a/port/board/afc-v3/payload.c b/port/board/afc-v3/payload.c index 7b73ed921..3abf9d158 100644 --- a/port/board/afc-v3/payload.c +++ b/port/board/afc-v3/payload.c @@ -193,6 +193,9 @@ void payload_init( void ) while ( gpio_read_pin( PIN_PORT(GPIO_MMC_ENABLE), PIN_NUMBER(GPIO_MMC_ENABLE) ) == 1 ) {}; } + /* Recover clock switch configuration saved in EEPROM */ + eeprom_24xx02_read(CHIP_ID_RTC_EEPROM, 0x0, clock_config, 16, 10); + xTaskCreate( vTaskPayload, "Payload", 256, NULL, tskPAYLOAD_PRIORITY, &vTaskPayload_Handle ); amc_payload_evt = xEventGroupCreate(); @@ -250,7 +253,7 @@ void vTaskPayload( void *pvParameters ) eeprom_24xx02_write(CHIP_ID_RTC_EEPROM, 0x0, clock_config, 16, 10); if (PAYLOAD_FPGA_ON){ adn4604_reset(); - clock_configuration(); + clock_configuration(clock_config); } xEventGroupClearBits(amc_payload_evt, PAYLOAD_MESSAGE_CLOCK_CONFIG); } @@ -315,7 +318,7 @@ void vTaskPayload( void *pvParameters ) gpio_set_pin_state(PIN_PORT(GPIO_FMC2_PG_C2M), PIN_NUMBER(GPIO_FMC2_PG_C2M), GPIO_LEVEL_HIGH); #ifdef MODULE_ADN4604 /* Configure clock switch */ - if (clock_configuration() == MMC_OK) { + if (clock_configuration(clock_config) == MMC_OK) { new_state = PAYLOAD_FPGA_ON; } #else @@ -485,32 +488,29 @@ uint8_t payload_hpm_activate_firmware( void ) return IPMI_CC_OK; } -mmc_err clock_configuration( void ) +mmc_err clock_configuration(const uint8_t clk_cfg[16]) { adn_connect_map_t con; mmc_err error; - /* Read the clock configuration from the eeprom */ - eeprom_24xx02_read(CHIP_ID_RTC_EEPROM, 0x0, clock_config, 16, 10); - /* Translate the configuration to enable or disable the outputs */ uint16_t out_enable_flag = { - ((clock_config[0] & 0x80) >> 7) << 0 | - ((clock_config[1] & 0x80) >> 7) << 1 | - ((clock_config[2] & 0x80) >> 7) << 2 | - ((clock_config[3] & 0x80) >> 7) << 3 | - ((clock_config[4] & 0x80) >> 7) << 4 | - ((clock_config[5] & 0x80) >> 7) << 5 | - ((clock_config[6] & 0x80) >> 7) << 6 | - ((clock_config[7] & 0x80) >> 7) << 7 | - ((clock_config[8] & 0x80) >> 7) << 8 | - ((clock_config[9] & 0x80) >> 7) << 9 | - ((clock_config[10] & 0x80) >> 7) << 10 | - ((clock_config[11] & 0x80) >> 7) << 11 | - ((clock_config[12] & 0x80) >> 7) << 12 | - ((clock_config[13] & 0x80) >> 7) << 13 | - ((clock_config[14] & 0x80) >> 7) << 14 | - ((clock_config[15] & 0x80) >> 7) << 15 + ((clk_cfg[0] & 0x80) >> 7) << 0 | + ((clk_cfg[1] & 0x80) >> 7) << 1 | + ((clk_cfg[2] & 0x80) >> 7) << 2 | + ((clk_cfg[3] & 0x80) >> 7) << 3 | + ((clk_cfg[4] & 0x80) >> 7) << 4 | + ((clk_cfg[5] & 0x80) >> 7) << 5 | + ((clk_cfg[6] & 0x80) >> 7) << 6 | + ((clk_cfg[7] & 0x80) >> 7) << 7 | + ((clk_cfg[8] & 0x80) >> 7) << 8 | + ((clk_cfg[9] & 0x80) >> 7) << 9 | + ((clk_cfg[10] & 0x80) >> 7) << 10 | + ((clk_cfg[11] & 0x80) >> 7) << 11 | + ((clk_cfg[12] & 0x80) >> 7) << 12 | + ((clk_cfg[13] & 0x80) >> 7) << 13 | + ((clk_cfg[14] & 0x80) >> 7) << 14 | + ((clk_cfg[15] & 0x80) >> 7) << 15 }; /* Disable UPDATE' pin by pulling it GPIO_LEVEL_HIGH */ @@ -522,22 +522,22 @@ mmc_err clock_configuration( void ) } /* Configure the interconnects*/ - con.out0 = clock_config[0] & 0x0F; - con.out1 = clock_config[1] & 0x0F; - con.out2 = clock_config[2] & 0x0F; - con.out3 = clock_config[3] & 0x0F; - con.out4 = clock_config[4] & 0x0F; - con.out5 = clock_config[5] & 0x0F; - con.out6 = clock_config[6] & 0x0F; - con.out7 = clock_config[7] & 0x0F; - con.out8 = clock_config[8] & 0x0F; - con.out9 = clock_config[9] & 0x0F; - con.out10 = clock_config[10] & 0x0F; - con.out11 = clock_config[11] & 0x0F; - con.out12 = clock_config[12] & 0x0F; - con.out13 = clock_config[13] & 0x0F; - con.out14 = clock_config[14] & 0x0F; - con.out15 = clock_config[15] & 0x0F; + con.out0 = clk_cfg[0] & 0x0F; + con.out1 = clk_cfg[1] & 0x0F; + con.out2 = clk_cfg[2] & 0x0F; + con.out3 = clk_cfg[3] & 0x0F; + con.out4 = clk_cfg[4] & 0x0F; + con.out5 = clk_cfg[5] & 0x0F; + con.out6 = clk_cfg[6] & 0x0F; + con.out7 = clk_cfg[7] & 0x0F; + con.out8 = clk_cfg[8] & 0x0F; + con.out9 = clk_cfg[9] & 0x0F; + con.out10 = clk_cfg[10] & 0x0F; + con.out11 = clk_cfg[11] & 0x0F; + con.out12 = clk_cfg[12] & 0x0F; + con.out13 = clk_cfg[13] & 0x0F; + con.out14 = clk_cfg[14] & 0x0F; + con.out15 = clk_cfg[15] & 0x0F; error = adn4604_xpt_config( ADN_XPT_MAP0_CON_REG, con ); if (error != MMC_OK) { diff --git a/port/board/afc-v3/payload.h b/port/board/afc-v3/payload.h index 1f7e68c6a..cd9794377 100644 --- a/port/board/afc-v3/payload.h +++ b/port/board/afc-v3/payload.h @@ -115,8 +115,7 @@ uint8_t payload_hpm_activate_firmware( void ); * @brief Configure the clock switch interconects according to the configuration * saved in EEPROM */ -mmc_err clock_configuration( void ); - +mmc_err clock_configuration(const uint8_t clk_cfg[16]); #endif /* IPMI_PAYLOAD_H_ */ diff --git a/port/board/afc-v4/payload.c b/port/board/afc-v4/payload.c index 438a9f90d..6f75200a0 100644 --- a/port/board/afc-v4/payload.c +++ b/port/board/afc-v4/payload.c @@ -218,6 +218,9 @@ void payload_init( void ) while ( gpio_read_pin( PIN_PORT(GPIO_MMC_ENABLE), PIN_NUMBER(GPIO_MMC_ENABLE) ) == 1 ) {}; } + /* Recover clock switch configuration saved in EEPROM */ + eeprom_24xx02_read(CHIP_ID_RTC_EEPROM, 0x0, clock_config, 16, 10); + xTaskCreate( vTaskPayload, "Payload", 256, NULL, tskPAYLOAD_PRIORITY, &vTaskPayload_Handle ); amc_payload_evt = xEventGroupCreate(); @@ -396,9 +399,11 @@ void vTaskPayload( void *pvParameters ) gpio_set_pin_state(PIN_PORT(GPIO_FMC1_PG_C2M), PIN_NUMBER(GPIO_FMC1_PG_C2M), GPIO_LEVEL_HIGH); gpio_set_pin_state(PIN_PORT(GPIO_FMC2_PG_C2M), PIN_NUMBER(GPIO_FMC2_PG_C2M), GPIO_LEVEL_HIGH); - /* Configure the clock switch according to the configuration saved in EEPROM*/ - eeprom_24xx02_read(CHIP_ID_RTC_EEPROM, 0x0, clock_config, 16, 10); - /* Only change the state if the clock config is efective*/ + + /* + * Only change the state if the clock switch configuration + * succeeds + */ if (clock_switch_write_reg(clock_config)) { new_state = PAYLOAD_FPGA_ON; } From fd76e226e8677c1d88f78f5ccf2dacbb743d55ac Mon Sep 17 00:00:00 2001 From: Augusto Fraga Giachero Date: Tue, 16 Jul 2024 17:02:15 -0300 Subject: [PATCH 42/43] Enable voltage and current sensors for AFCv4 Previously, the voltage and current sensors were disabled because it was causing the MCH to crash with a lot of 'AMC +12V Curr' assertion / deassertion messages and IPMB errors. The root cause for this behavior is not yet understood, but it is somewhat related to the voltage sensors SDR struct not been populated with the thresholds (they were all commented). I've updated all thresholds (voltages and currents) to reasonable defaults, but they might be wrong, so a more in depth study of the AFCv4 power rails should be conducted to obtain the correct values. It works for now, and the MCH doesn't crash, neither complain about out of range voltages or currents. --- port/board/afc-v4/CMakeLists.txt | 4 +- port/board/afc-v4/sdr_list.c | 263 ++++++++++++++++--------------- 2 files changed, 134 insertions(+), 133 deletions(-) diff --git a/port/board/afc-v4/CMakeLists.txt b/port/board/afc-v4/CMakeLists.txt index 7d39769ad..cd1a30fef 100644 --- a/port/board/afc-v4/CMakeLists.txt +++ b/port/board/afc-v4/CMakeLists.txt @@ -19,8 +19,8 @@ set(TARGET_MODULES "EEPROM_AT24MAC" "LM75" "MAX6642" -# "INA3221_VOLTAGE" -# "INA3221_CURRENT" + "INA3221_VOLTAGE" + "INA3221_CURRENT" "UART_DEBUG" "MCP23016" "ADC" diff --git a/port/board/afc-v4/sdr_list.c b/port/board/afc-v4/sdr_list.c index 6c5b69abc..a59ed52f3 100644 --- a/port/board/afc-v4/sdr_list.c +++ b/port/board/afc-v4/sdr_list.c @@ -298,17 +298,17 @@ const SDR_type_01h_t SDR_FMC1_VADJ = { .acc_exp_sensor_dir = 0x00, /* Sensor direction */ .Rexp_Bexp = 0xD0, /* R-Exp , B-Exp */ .analog_flags = 0x00, /* Analogue characteristics flags */ -// .nominal_reading = 39, /* Nominal reading */ -// .normal_max = 47, /* Normal maximum */ -// .normal_min = 0, /* Normal minimum */ -// .sensor_max_reading = 0xFF, /* Sensor Maximum reading */ -// .sensor_min_reading = 0x00, /* Sensor Minimum reading */ -// .upper_nonrecover_thr = 51, /* Upper non-recoverable Threshold */ -// .upper_critical_thr = 46, /* Upper critical Threshold */ -// .upper_noncritical_thr = 43, /* Upper non critical Threshold */ -// .lower_nonrecover_thr = 28, /* Lower non-recoverable Threshold */ -// .lower_critical_thr = 32, /* Lower critical Threshold */ -// .lower_noncritical_thr = 36, /* Lower non-critical Threshold */ + .nominal_reading = (2500 >> 6), /* Nominal reading */ + .normal_max = (3400 >> 6), /* Normal maximum */ + .normal_min = (1700 >> 6), /* Normal minimum */ + .sensor_max_reading = 0xFF, /* Sensor Maximum reading */ + .sensor_min_reading = 0x00, /* Sensor Minimum reading */ + .upper_nonrecover_thr = (3700 >> 6), /* Upper non-recoverable Threshold */ + .upper_critical_thr = (3600 >> 6), /* Upper critical Threshold */ + .upper_noncritical_thr = (3500 >> 6), /* Upper non critical Threshold */ + .lower_nonrecover_thr = (1500 >> 6), /* Lower non-recoverable Threshold */ + .lower_critical_thr = (1600 >> 6), /* Lower critical Threshold */ + .lower_noncritical_thr = (1700 >> 6), /* Lower non-critical Threshold */ .pos_thr_hysteresis = 1, /* positive going Threshold hysteresis value */ .neg_thr_hysteresis = 1, /* negative going Threshold hysteresis value */ .reserved1 = 0x00, /* reserved */ @@ -344,6 +344,7 @@ const SDR_type_01h_t SDR_FMC1_P3V3 = { .sensor_units_1 = 0x00, /* sensor units 1 :*/ .sensor_units_2 = 0x04, /* sensor units 2 :*/ .sensor_units_3 = 0x00, /* sensor units 3 :*/ + .linearization = 0x00, /* Linearization */ .M = 64, /* M */ .M_tol = 0x00, /* M - Tolerance */ .B = 0x00, /* B */ @@ -351,17 +352,17 @@ const SDR_type_01h_t SDR_FMC1_P3V3 = { .acc_exp_sensor_dir = 0x00, /* Sensor direction */ .Rexp_Bexp = 0xD0, /* R-Exp , B-Exp */ .analog_flags = 0x00, /* Analogue characteristics flags */ -// .nominal_reading = 52, /* Nominal reading */ -// .normal_max = 59, /* Normal maximum */ -// .normal_min = 45, /* Normal minimum */ -// .sensor_max_reading = 0xFF, /* Sensor Maximum reading */ -// .sensor_min_reading = 0x00, /* Sensor Minimum reading */ -// .upper_nonrecover_thr = 62, /* Upper non-recoverable Threshold */ -// .upper_critical_thr = 59, /* Upper critical Threshold */ -// .upper_noncritical_thr = 55, /* Upper non critical Threshold */ -// .lower_nonrecover_thr = 42, /* Lower non-recoverable Threshold */ -// .lower_critical_thr = 45, /* Lower critical Threshold */ -// .lower_noncritical_thr = 48, /* Lower non-critical Threshold */ + .nominal_reading = (3300 >> 6), /* Nominal reading */ + .normal_max = (3500 >> 6), /* Normal maximum */ + .normal_min = (3000 >> 6), /* Normal minimum */ + .sensor_max_reading = 0xFF, /* Sensor Maximum reading */ + .sensor_min_reading = 0x00, /* Sensor Minimum reading */ + .upper_nonrecover_thr = (3700 >> 6), /* Upper non-recoverable Threshold */ + .upper_critical_thr = (3600 >> 6), /* Upper critical Threshold */ + .upper_noncritical_thr = (3550 >> 6), /* Upper non critical Threshold */ + .lower_nonrecover_thr = (2800 >> 6), /* Lower non-recoverable Threshold */ + .lower_critical_thr = (2900 >> 6), /* Lower critical Threshold */ + .lower_noncritical_thr = (2950 >> 6), /* Lower non-critical Threshold */ .pos_thr_hysteresis = 2, /* positive going Threshold hysteresis value */ .neg_thr_hysteresis = 2, /* negative going Threshold hysteresis value */ .reserved1 = 0x00, /* reserved */ @@ -459,17 +460,17 @@ const SDR_type_01h_t SDR_FMC2_VADJ = { .acc_exp_sensor_dir = 0x00, /* Sensor direction */ .Rexp_Bexp = 0xD0, /* R-Exp , B-Exp */ .analog_flags = 0x00, /* Analogue characteristics flags */ -// .nominal_reading = 39, /* Nominal reading */ -// .normal_max = 47, /* Normal maximum */ -// .normal_min = 0, /* Normal minimum */ -// .sensor_max_reading = 0xFF, /* Sensor Maximum reading */ -// .sensor_min_reading = 0x00, /* Sensor Minimum reading */ -// .upper_nonrecover_thr = 51, /* Upper non-recoverable Threshold */ -// .upper_critical_thr = 46, /* Upper critical Threshold */ -// .upper_noncritical_thr = 43, /* Upper non critical Threshold */ -// .lower_nonrecover_thr = 28, /* Lower non-recoverable Threshold */ -// .lower_critical_thr = 32, /* Lower critical Threshold */ -// .lower_noncritical_thr = 36, /* Lower non-critical Threshold */ + .nominal_reading = (2500 >> 6), /* Nominal reading */ + .normal_max = (3400 >> 6), /* Normal maximum */ + .normal_min = (1700 >> 6), /* Normal minimum */ + .sensor_max_reading = 0xFF, /* Sensor Maximum reading */ + .sensor_min_reading = 0x00, /* Sensor Minimum reading */ + .upper_nonrecover_thr = (3700 >> 6), /* Upper non-recoverable Threshold */ + .upper_critical_thr = (3600 >> 6), /* Upper critical Threshold */ + .upper_noncritical_thr = (3500 >> 6), /* Upper non critical Threshold */ + .lower_nonrecover_thr = (1500 >> 6), /* Lower non-recoverable Threshold */ + .lower_critical_thr = (1600 >> 6), /* Lower critical Threshold */ + .lower_noncritical_thr = (1700 >> 6), /* Lower non-critical Threshold */ .pos_thr_hysteresis = 1, /* positive going Threshold hysteresis value */ .neg_thr_hysteresis = 1, /* negative going Threshold hysteresis value */ .reserved1 = 0x00, /* reserved */ @@ -514,17 +515,17 @@ const SDR_type_01h_t SDR_FMC2_P3V3 = { .acc_exp_sensor_dir = 0x00, /* Sensor direction */ .Rexp_Bexp = 0xD0, /* R-Exp , B-Exp */ .analog_flags = 0x00, /* Analogue characteristics flags */ -// .nominal_reading = 52, /* Nominal reading */ -// .normal_max = 59, /* Normal maximum */ -// .normal_min = 45, /* Normal minimum */ -// .sensor_max_reading = 0xFF, /* Sensor Maximum reading */ -// .sensor_min_reading = 0x00, /* Sensor Minimum reading */ -// .upper_nonrecover_thr = 62, /* Upper non-recoverable Threshold */ -// .upper_critical_thr = 59, /* Upper critical Threshold */ -// .upper_noncritical_thr = 55, /* Upper non critical Threshold */ -// .lower_nonrecover_thr = 42, /* Lower non-recoverable Threshold */ -// .lower_critical_thr = 45, /* Lower critical Threshold */ -// .lower_noncritical_thr = 48, /* Lower non-critical Threshold */ + .nominal_reading = (3300 >> 6), /* Nominal reading */ + .normal_max = (3500 >> 6), /* Normal maximum */ + .normal_min = (3000 >> 6), /* Normal minimum */ + .sensor_max_reading = 0xFF, /* Sensor Maximum reading */ + .sensor_min_reading = 0x00, /* Sensor Minimum reading */ + .upper_nonrecover_thr = (3700 >> 6), /* Upper non-recoverable Threshold */ + .upper_critical_thr = (3600 >> 6), /* Upper critical Threshold */ + .upper_noncritical_thr = (3550 >> 6), /* Upper non critical Threshold */ + .lower_nonrecover_thr = (2800 >> 6), /* Lower non-recoverable Threshold */ + .lower_critical_thr = (2900 >> 6), /* Lower critical Threshold */ + .lower_noncritical_thr = (2950 >> 6), /* Lower non-critical Threshold */ .pos_thr_hysteresis = 2, /* positive going Threshold hysteresis value */ .neg_thr_hysteresis = 2, /* negative going Threshold hysteresis value */ .reserved1 = 0x00, /* reserved */ @@ -572,17 +573,17 @@ const SDR_type_01h_t SDR_AMC_12V_CURR = { .acc_exp_sensor_dir = 0x02, /* Sensor direction */ .Rexp_Bexp = 0xD0, /* R-Exp = -3 , B-Exp = 0 */ .analog_flags = 0x03, /* Analogue characteristics flags */ - .nominal_reading = 62, /* Nominal reading [mA] */ - .normal_max = 100, /* Normal maximum */ + .nominal_reading = 2000 >> 5, /* Nominal reading */ + .normal_max = 3000 >> 5, /* Normal maximum */ .normal_min = 0, /* Normal minimum */ - .sensor_max_reading = 0xFF, /* Sensor Maximum reading */ - .sensor_min_reading = 0x00, /* Sensor Minimum reading */ - .upper_nonrecover_thr = 127, /* Upper non-recoverable Threshold - 4A */ - .upper_critical_thr = 127, /* Upper critical Threshold - 3.5A */ - .upper_noncritical_thr = 127, /* Upper non critical Threshold - 3A */ - .lower_nonrecover_thr = -15, /* Lower non-recoverable Threshold - -0.1A */ - .lower_critical_thr = -10, /* Lower critical Threshold - 0.32A */ - .lower_noncritical_thr = -5, /* Lower non-critical Threshold - 0.5A */ + .sensor_max_reading = 0x7F, /* Sensor Maximum reading */ + .sensor_min_reading = 0x80, /* Sensor Minimum reading */ + .upper_nonrecover_thr = (4000 >> 5), /* Upper non-recoverable Threshold */ + .upper_critical_thr = (3500 >> 5), /* Upper critical Threshold */ + .upper_noncritical_thr = (3000 >> 5), /* Upper non critical Threshold */ + .lower_nonrecover_thr = - (200 >> 5), /* Lower non-recoverable Threshold */ + .lower_critical_thr = - (150 >> 5), /* Lower critical Threshold */ + .lower_noncritical_thr = - (100 >> 5), /* Lower non-critical Threshold */ .pos_thr_hysteresis = 2, /* positive going Threshold hysteresis value */ .neg_thr_hysteresis = 2, /* negative going Threshold hysteresis value */ .reserved1 = 0x00, /* reserved */ @@ -627,17 +628,17 @@ const SDR_type_01h_t SDR_RTM_12V_CURR = { .acc_exp_sensor_dir = 0x02, /* Sensor direction */ .Rexp_Bexp = 0xD0, /* R-Exp = -3 , B-Exp = 0 */ .analog_flags = 0x03, /* Analogue characteristics flags */ -// .nominal_reading = 32, /* Nominal reading = 1A */ -// .normal_max = 125, /* Normal maximum */ -// .normal_min = 0, /* Normal minimum */ -// .sensor_max_reading = 0xFF, /* Sensor Maximum reading */ -// .sensor_min_reading = 0x00, /* Sensor Minimum reading */ -// .upper_nonrecover_thr = 125, /* Upper non-recoverable Threshold - 4A */ -// .upper_critical_thr = 110, /* Upper critical Threshold - 3.5A */ -// .upper_noncritical_thr = 95, /* Upper non critical Threshold - 3A */ -// .lower_nonrecover_thr = -15, /* Lower non-recoverable Threshold - -0.1A */ -// .lower_critical_thr = -10, /* Lower critical Threshold - 0.32A */ -// .lower_noncritical_thr = -5, /* Lower non-critical Threshold - 0.5A */ + .nominal_reading = (2000 >> 5), /* Nominal reading */ + .normal_max = (3000 >> 5), /* Normal maximum */ + .normal_min = 0, /* Normal minimum */ + .sensor_max_reading = 0x7F, /* Sensor Maximum reading */ + .sensor_min_reading = 0x80, /* Sensor Minimum reading */ + .upper_nonrecover_thr = (4000 >> 5), /* Upper non-recoverable Threshold */ + .upper_critical_thr = (3500 >> 5), /* Upper critical Threshold */ + .upper_noncritical_thr = (3000 >> 5), /* Upper non critical Threshold */ + .lower_nonrecover_thr = - (200 >> 5), /* Lower non-recoverable Threshold */ + .lower_critical_thr = - (150 >> 5), /* Lower critical Threshold */ + .lower_noncritical_thr = - (100 >> 5), /* Lower non-critical Threshold */ .pos_thr_hysteresis = 2, /* positive going Threshold hysteresis value */ .neg_thr_hysteresis = 2, /* negative going Threshold hysteresis value */ .reserved1 = 0x00, /* reserved */ @@ -682,17 +683,17 @@ const SDR_type_01h_t SDR_FMC1_12V_CURR = { .acc_exp_sensor_dir = 0x02, /* Sensor direction */ .Rexp_Bexp = 0xD0, /* R-Exp = -3 , B-Exp = 0 */ .analog_flags = 0x03, /* Analogue characteristics flags */ -// .nominal_reading = 32, /* Nominal reading = 1A */ -// .normal_max = 125, /* Normal maximum */ -// .normal_min = 0, /* Normal minimum */ -// .sensor_max_reading = 0xFF, /* Sensor Maximum reading */ -// .sensor_min_reading = 0x00, /* Sensor Minimum reading */ -// .upper_nonrecover_thr = 125, /* Upper non-recoverable Threshold - 4A */ -// .upper_critical_thr = 110, /* Upper critical Threshold - 3.5A */ -// .upper_noncritical_thr = 95, /* Upper non critical Threshold - 3A */ -// .lower_nonrecover_thr = -15, /* Lower non-recoverable Threshold - -0.1A */ -// .lower_critical_thr = -10, /* Lower critical Threshold - 0.32A */ -// .lower_noncritical_thr = -5, /* Lower non-critical Threshold - 0.5A */ + .nominal_reading = (1000 >> 5), /* Nominal reading */ + .normal_max = (3000 >> 5), /* Normal maximum */ + .normal_min = 0, /* Normal minimum */ + .sensor_max_reading = 0x7F, /* Sensor Maximum reading */ + .sensor_min_reading = 0x80, /* Sensor Minimum reading */ + .upper_nonrecover_thr = (4000 >> 5), /* Upper non-recoverable Threshold */ + .upper_critical_thr = (3500 >> 5), /* Upper critical Threshold */ + .upper_noncritical_thr = (3000 >> 5), /* Upper non critical Threshold */ + .lower_nonrecover_thr = - (200 >> 5), /* Lower non-recoverable Threshold */ + .lower_critical_thr = - (150 >> 5), /* Lower critical Threshold */ + .lower_noncritical_thr = - (100 >> 5), /* Lower non-critical Threshold */ .pos_thr_hysteresis = 2, /* positive going Threshold hysteresis value */ .neg_thr_hysteresis = 2, /* negative going Threshold hysteresis value */ .reserved1 = 0x00, /* reserved */ @@ -736,17 +737,17 @@ const SDR_type_01h_t SDR_FMC1_VADJ_CURR = { .acc_exp_sensor_dir = 0x00, /* Sensor direction */ .Rexp_Bexp = 0xD0, /* R-Exp , B-Exp */ .analog_flags = 0x00, /* Analogue characteristics flags */ -// .nominal_reading = 39, /* Nominal reading - 1.24A */ -// .normal_max = 47, /* Normal maximum - 1.5A*/ -// .normal_min = 0, /* Normal minimum - 0A */ -// .sensor_max_reading = 0x7F, /* Sensor Maximum reading */ -// .sensor_min_reading = 0x80, /* Sensor Minimum reading */ -// .upper_nonrecover_thr = 125, /* Upper non-recoverable Threshold - 4A */ -// .upper_critical_thr = 110, /* Upper critical Threshold - 3.5A */ -// .upper_noncritical_thr = 94, /* Upper non critical Threshold - 3A */ -// .lower_nonrecover_thr = -15, /* Lower non-recoverable Threshold - -0.32A */ -// .lower_critical_thr = -10, /* Lower critical Threshold - 0A */ -// .lower_noncritical_thr = -5, /* Lower non-critical Threshold - 0.16A */ + .nominal_reading = 1000 >> 5, /* Nominal reading */ + .normal_max = 1500 >> 5, /* Normal maximum */ + .normal_min = 0, /* Normal minimum - 0A */ + .sensor_max_reading = 0x7F, /* Sensor Maximum reading */ + .sensor_min_reading = 0x80, /* Sensor Minimum reading */ + .upper_nonrecover_thr = (2000 >> 5), /* Upper non-recoverable Threshold */ + .upper_critical_thr = (1700 >> 5), /* Upper critical Threshold */ + .upper_noncritical_thr = (1500 >> 5), /* Upper non critical Threshold */ + .lower_nonrecover_thr = - (200 >> 5), /* Lower non-recoverable Threshold */ + .lower_critical_thr = - (150 >> 5), /* Lower critical Threshold */ + .lower_noncritical_thr = - (100 >> 5), /* Lower non-critical Threshold */ .pos_thr_hysteresis = 2, /* positive going Threshold hysteresis value */ .neg_thr_hysteresis = 2, /* negative going Threshold hysteresis value */ .reserved1 = 0x00, /* reserved */ @@ -789,17 +790,17 @@ const SDR_type_01h_t SDR_FMC1_P3V3_CURR = { .acc_exp_sensor_dir = 0x00, /* Sensor direction */ .Rexp_Bexp = 0xD0, /* R-Exp , B-Exp */ .analog_flags = 0x00, /* Analogue characteristics flags */ -// .nominal_reading = 85, /* Nominal reading */ -// .normal_max = 94, /* Normal maximum - 3A */ -// .normal_min = 32, /* Normal minimum - 1A */ -// .sensor_max_reading = 0xFF, /* Sensor Maximum reading */ -// .sensor_min_reading = 0x00, /* Sensor Minimum reading */ -// .upper_nonrecover_thr = 125, /* Upper non-recoverable Threshold - 4A */ -// .upper_critical_thr = 110, /* Upper critical Threshold - 3.5A */ -// .upper_noncritical_thr = 94, /* Upper non critical Threshold - 3A */ -// .lower_nonrecover_thr = -15, /* Lower non-recoverable Threshold - -0.1A */ -// .lower_critical_thr = -10, /* Lower critical Threshold - 0.32A */ -// .lower_noncritical_thr = -5, /* Lower non-critical Threshold - 1A */ + .nominal_reading = (1500 >> 5), /* Nominal reading */ + .normal_max = (3000 >> 5), /* Normal maximum */ + .normal_min = 0, /* Normal minimum */ + .sensor_max_reading = 0x7F, /* Sensor Maximum reading */ + .sensor_min_reading = 0x80, /* Sensor Minimum reading */ + .upper_nonrecover_thr = (4000 >> 5), /* Upper non-recoverable Threshold */ + .upper_critical_thr = (3500 >> 5), /* Upper critical Threshold */ + .upper_noncritical_thr = (3000 >> 5), /* Upper non critical Threshold */ + .lower_nonrecover_thr = - (200 >> 5), /* Lower non-recoverable Threshold */ + .lower_critical_thr = - (150 >> 5), /* Lower critical Threshold */ + .lower_noncritical_thr = - (100 >> 5), /* Lower non-critical Threshold */ .pos_thr_hysteresis = 2, /* positive going Threshold hysteresis value */ .neg_thr_hysteresis = 2, /* negative going Threshold hysteresis value */ .reserved1 = 0x00, /* reserved */ @@ -843,17 +844,17 @@ const SDR_type_01h_t SDR_FMC2_12V_CURR = { .acc_exp_sensor_dir = 0x02, /* Sensor direction */ .Rexp_Bexp = 0xD0, /* R-Exp = -3 , B-Exp = 0 */ .analog_flags = 0x03, /* Analogue characteristics flags */ -// .nominal_reading = 32, /* Nominal reading = 1A */ -// .normal_max = 125, /* Normal maximum */ -// .normal_min = 0, /* Normal minimum */ -// .sensor_max_reading = 0xFF, /* Sensor Maximum reading */ -// .sensor_min_reading = 0x00, /* Sensor Minimum reading */ -// .upper_nonrecover_thr = 125, /* Upper non-recoverable Threshold - 4A */ -// .upper_critical_thr = 110, /* Upper critical Threshold - 3.5A */ -// .upper_noncritical_thr = 95, /* Upper non critical Threshold - 3A */ -// .lower_nonrecover_thr = -15, /* Lower non-recoverable Threshold - -0.1A */ -// .lower_critical_thr = -10, /* Lower critical Threshold - 0.32A */ -// .lower_noncritical_thr = -5, /* Lower non-critical Threshold - 0.5A */ + .nominal_reading = (1000 >> 5), /* Nominal reading */ + .normal_max = (3000 >> 5), /* Normal maximum */ + .normal_min = 0, /* Normal minimum */ + .sensor_max_reading = 0x7F, /* Sensor Maximum reading */ + .sensor_min_reading = 0x80, /* Sensor Minimum reading */ + .upper_nonrecover_thr = (4000 >> 5), /* Upper non-recoverable Threshold */ + .upper_critical_thr = (3500 >> 5), /* Upper critical Threshold */ + .upper_noncritical_thr = (3000 >> 5), /* Upper non critical Threshold */ + .lower_nonrecover_thr = - (200 >> 5), /* Lower non-recoverable Threshold */ + .lower_critical_thr = - (150 >> 5), /* Lower critical Threshold */ + .lower_noncritical_thr = - (100 >> 5), /* Lower non-critical Threshold */ .pos_thr_hysteresis = 2, /* positive going Threshold hysteresis value */ .neg_thr_hysteresis = 2, /* negative going Threshold hysteresis value */ .reserved1 = 0x00, /* reserved */ @@ -897,17 +898,17 @@ const SDR_type_01h_t SDR_FMC2_VADJ_CURR = { .acc_exp_sensor_dir = 0x00, /* Sensor direction */ .Rexp_Bexp = 0xD0, /* R-Exp , B-Exp */ .analog_flags = 0x00, /* Analogue characteristics flags */ -// .nominal_reading = 39, /* Nominal reading - 1.24A */ -// .normal_max = 47, /* Normal maximum - 1.5A*/ -// .normal_min = 0, /* Normal minimum - 0A */ -// .sensor_max_reading = 0x7F, /* Sensor Maximum reading */ -// .sensor_min_reading = 0x80, /* Sensor Minimum reading */ -// .upper_nonrecover_thr = 125, /* Upper non-recoverable Threshold - 4A */ -// .upper_critical_thr = 110, /* Upper critical Threshold - 3.5A */ -// .upper_noncritical_thr = 94, /* Upper non critical Threshold - 3A */ -// .lower_nonrecover_thr = -15, /* Lower non-recoverable Threshold - -0.32A */ -// .lower_critical_thr = -10, /* Lower critical Threshold - 0A */ -// .lower_noncritical_thr = -5, /* Lower non-critical Threshold - 0.16A */ + .nominal_reading = 1000 >> 5, /* Nominal reading */ + .normal_max = 1500 >> 5, /* Normal maximum */ + .normal_min = 0, /* Normal minimum - 0A */ + .sensor_max_reading = 0x7F, /* Sensor Maximum reading */ + .sensor_min_reading = 0x80, /* Sensor Minimum reading */ + .upper_nonrecover_thr = (2000 >> 5), /* Upper non-recoverable Threshold */ + .upper_critical_thr = (1700 >> 5), /* Upper critical Threshold */ + .upper_noncritical_thr = (1500 >> 5), /* Upper non critical Threshold */ + .lower_nonrecover_thr = - (200 >> 5), /* Lower non-recoverable Threshold */ + .lower_critical_thr = - (150 >> 5), /* Lower critical Threshold */ + .lower_noncritical_thr = - (100 >> 5), /* Lower non-critical Threshold */ .pos_thr_hysteresis = 2, /* positive going Threshold hysteresis value */ .neg_thr_hysteresis = 2, /* negative going Threshold hysteresis value */ .reserved1 = 0x00, /* reserved */ @@ -950,17 +951,17 @@ const SDR_type_01h_t SDR_FMC2_P3V3_CURR = { .acc_exp_sensor_dir = 0x00, /* Sensor direction */ .Rexp_Bexp = 0xD0, /* R-Exp , B-Exp */ .analog_flags = 0x00, /* Analogue characteristics flags */ -// .nominal_reading = 85, /* Nominal reading */ -// .normal_max = 94, /* Normal maximum - 3A */ -// .normal_min = 32, /* Normal minimum - 1A */ -// .sensor_max_reading = 0xFF, /* Sensor Maximum reading */ -// .sensor_min_reading = 0x00, /* Sensor Minimum reading */ -// .upper_nonrecover_thr = 125, /* Upper non-recoverable Threshold - 4A */ -// .upper_critical_thr = 110, /* Upper critical Threshold - 3.5A */ -// .upper_noncritical_thr = 94, /* Upper non critical Threshold - 3A */ -// .lower_nonrecover_thr = -15, /* Lower non-recoverable Threshold - -0.1A */ -// .lower_critical_thr = -10, /* Lower critical Threshold - 0.32A */ -// .lower_noncritical_thr = -5, /* Lower non-critical Threshold - 1A */ + .nominal_reading = (1500 >> 5), /* Nominal reading */ + .normal_max = (3000 >> 5), /* Normal maximum */ + .normal_min = 0, /* Normal minimum */ + .sensor_max_reading = 0x7F, /* Sensor Maximum reading */ + .sensor_min_reading = 0x80, /* Sensor Minimum reading */ + .upper_nonrecover_thr = (4000 >> 5), /* Upper non-recoverable Threshold */ + .upper_critical_thr = (3500 >> 5), /* Upper critical Threshold */ + .upper_noncritical_thr = (3000 >> 5), /* Upper non critical Threshold */ + .lower_nonrecover_thr = - (200 >> 5), /* Lower non-recoverable Threshold */ + .lower_critical_thr = - (150 >> 5), /* Lower critical Threshold */ + .lower_noncritical_thr = - (100 >> 5), /* Lower non-critical Threshold */ .pos_thr_hysteresis = 2, /* positive going Threshold hysteresis value */ .neg_thr_hysteresis = 2, /* negative going Threshold hysteresis value */ .reserved1 = 0x00, /* reserved */ From 3829dfe272ad7941fd71a5c370f2074f2a5f726d Mon Sep 17 00:00:00 2001 From: Augusto Fraga Giachero Date: Thu, 18 Jul 2024 14:14:05 -0300 Subject: [PATCH 43/43] Better wording of the workaround needed when upgrading from v1.5.0 --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index bfc1354f7..e79a55b77 100644 --- a/README.md +++ b/README.md @@ -93,7 +93,7 @@ It's also important to mention that you can use the `--help` command in case of ./bin/hpm-downloader --help ### ipmitool -> :warning: **Disclaimer:** Due to [e88b30b](https://github.com/lnls-dig/openMMC/tree/e88b30b26c9dc05662d84e35b51fc81d7ecf7561), the ipmitool fails when trying to upgrade the firmware from v1.5.0. For succeed in upgrade, you can use a modified ipmitool version, setting the variable [`max_rq_size`](https://codeberg.org/IPMITool/ipmitool/src/commit/137aeb64cbb493d61d6945cac156aba5f0510780/lib/ipmi_hpmfwupg.c#L1143) to 20. After this version, you can use the ipmitool normally. +> :warning: **Disclaimer:** Due to [e88b30b](https://github.com/lnls-dig/openMMC/tree/e88b30b26c9dc05662d84e35b51fc81d7ecf7561), the ipmitool may fail when trying to upgrade the firmware from v1.5.0. You can use a modified ipmitool utility as a workaround, setting the variable [`max_rq_size`](https://codeberg.org/IPMITool/ipmitool/src/commit/137aeb64cbb493d61d6945cac156aba5f0510780/lib/ipmi_hpmfwupg.c#L1143) to 20. After [5631857](https://github.com/lnls-dig/openMMC/commit/563185791c8b51ea026680c98ec0ea9587ea645b), it's possible to program the firmware and the bootloader through [ipmitool](https://codeberg.org/IPMITool/ipmitool), for previous releases, you still need to use [hpm-downloader](https://github.com/lnls-dig/hpm-downloader). In order to use it, you have to install the ipmitool, and then generate .hpm files from `OpenMMC.bin` and `newboot.bin`. To generate `.hpm` files, you will need to use [bin2hpm](https://github.com/MicroTCA-Tech-Lab/bin2hpm). If you have bin2hpm in your `$PATH`, the `.hpm` files will be automatically generated for you, provided you build from [0095b14](https://github.com/lnls-dig/openMMC/commit/0095b14667afe844113725228671d8810b45d9e0) or more recent versions. After generate the files, you can use the following commands to program the MMC microcontroller.