diff --git a/hdl/modules/wb_position_calc/cheby/doc/wb_pos_calc_regs_wb.html b/hdl/modules/wb_position_calc/cheby/doc/wb_pos_calc_regs_wb.html index 63b15596..68164267 100644 --- a/hdl/modules/wb_position_calc/cheby/doc/wb_pos_calc_regs_wb.html +++ b/hdl/modules/wb_position_calc/cheby/doc/wb_pos_calc_regs_wb.html @@ -766,16 +766,12 @@

2.1. ds_tbt_thres

val[7:0] - +
+
val [rw]
+
Config divisor threshold TBT

Minimum amplitude sum in which the position
calculation for TBT rate is performed, in FIX26_22
+
reserved [rw]
+
Reserved

Ignore on write, read as 0's
+

2.2. ds_fofb_thres

@@ -842,16 +838,12 @@

2.2. ds_fofb_thres

val[7:0]
- +
+
val [rw]
+
Config divisor threshold FOFB

Minimum amplitude sum in which the position
calculation for FOFB rate is performed, in FIX26_22
+
reserved [rw]
+
Reserved

Ignore on write, read as 0's
+

2.3. ds_monit_thres

@@ -918,16 +910,12 @@

2.3. ds_monit_thres

val[7:0]
- +
+
val [rw]
+
Config Divisor Threshold Monit.

Minimum amplitude sum in which the position
calculation for Monit. rate is performed, in FIX26_22
+
reserved [rw]
+
Reserved

Ignore on write, read as 0's
+

2.4. kx

@@ -994,16 +982,12 @@

2.4. kx

val[7:0]
- +
+
val [rw]
+
BPM sensitivity (X axis) parameter register

BPM sensitivity (X axis) parameter, in UFIX25_0.
It effectively multiplies the calculated position
with a determined value. Typical values lie around
10000000d
+
reserved [rw]
+
Reserved

Ignore on write, read as 0's
+

2.5. ky

@@ -1070,16 +1054,12 @@

2.5. ky

val[7:0]
- +
+
val [rw]
+
BPM sensitivity (Y axis) parameter register

BPM sensitivity (Y axis) parameter, in UFIX25_0.
It effectively multiplies the calculated position
with a determined value. Typical values lie around
10000000d
+
reserved [rw]
+
Reserved

Ignore on write, read as 0's
+

2.6. ksum

@@ -1146,16 +1126,12 @@

2.6. ksum

val[7:0]
- +
+
val [rw]
+
BPM sensitivity (Sum) parameter register

BPM sensitivity (Sum) parameter, in FIX25_24.
It effectively multiplies the calculated position
with a determined value. Typical values lie around
1.0d
+
reserved [rw]
+
Reserved

Ignore on write, read as 0's
+

2.7. dsp_ctnr_tbt

@@ -1221,16 +1197,12 @@

2.7. dsp_ctnr_tbt

ch01[7:0]
- +
+
ch01 [ro]
+
TBT incorrect counter for channels 0/1 (multiplexed)

This register holds the number of incorrect transfers
on TDM for channels 0/1 (multiplexed)
+
ch23 [ro]
+
TBT incorrect counter for channels 2/3 (multiplexed)

This register holds the number of incorrect transfers
on TDM for channels 2/3 (multiplexed)
+

2.8. dsp_ctnr_fofb

@@ -1296,16 +1268,12 @@

2.8. dsp_ctnr_fofb

ch01[7:0]
- +
+
ch01 [ro]
+
FOFB incorrect counter for channels 0/1 (multiplexed)

This register holds the number of incorrect transfers
on TDM for channels 0/1 (multiplexed)
+
ch23 [ro]
+
FOFB incorrect counter for channels 2/3 (multiplexed)

This register holds the number of incorrect transfers
on TDM for channels 2/3 (multiplexed)
+

2.9. dsp_ctnr1_monit

@@ -1371,16 +1339,12 @@

2.9. dsp_ctnr1_monit

cic[7:0]
- +
+
cic [ro]
+
Monit. CIC incorrect counter for channels 0/1/2/3 (multiplexed)

This register holds the number of incorrect transfers
on TDM for channels 0/1/2/3 (multiplexed)
+
cfir [ro]
+
Monit. CFIR incorrect counter for channels 0/1/2/3 (multiplexed)

This register holds the number of incorrect transfers
on TDM for channels 0/1/2/3 (multiplexed)
+

2.10. dsp_ctnr2_monit

@@ -1446,16 +1410,12 @@

2.10. dsp_ctnr2_monit

pfir[7:0]
- +
+
pfir [ro]
+
Monit. PFIR incorrect counter for channels 0/1/2/3 (multiplexed)

This register holds the number of incorrect transfers
on TDM for channels 0/1/2/3 (multiplexed) on Monit. chain
+
fir_01 [ro]
+
Monit. 0.1 Hz incorrect counter for channels 0/1/2/3 (multiplexed)

This register holds the number of incorrect transfers
on TDM for channels 0/1/2/3 (multiplexed) on Monit_01 chain
+

2.11. dsp_err_clr

@@ -1549,24 +1509,16 @@

2.11. dsp_err_clr

tbt
- +
+
tbt [wo]
+
Clear TBT error counters

This register clears the error counter for the TBT rate
write 0: no effect
write 1: clear error counter
+
fofb [wo]
+
Clear FOFB error counters

This register clears the error counter for the FOFB rate
write 0: no effect
write 1: clear error counter
+
monit_part1 [wo]
+
Clear Monit. CIC and CFIR error counters

This register clears the error counter for the CIC and CFIR rate
write 0: no effect
write 1: clear error counter
+
monit_part2 [wo]
+
Clear Monit. PFIR and Monit. 0.1 error counters

This register clears the error counter for the Monit. PFIR
and Monit. 0.1 rate
write 0: no effect
write 1: clear error counter
+

2.12. dds_cfg

@@ -1637,44 +1589,26 @@

2.12. dds_cfg

valid_ch0
- +
+
valid_ch0 [rw]
+
Valid signal for channel 0 DDS

Valid signal for channel 0 DDS:
write 0: no effect
write 1: write phase increment and offset into DDS
+
test_data [rw]
+
Test data counter for all channels

Test data counter for all channels:
write 0: real data
write 1: test counter data
+
reserved_ch0 [rw]
+
Reserved

Ignore on write, read as 0's
+
valid_ch1 [rw]
+
Valid signal for channel 1 DDS

Valid signal for channel 1 DDS:
write 0: no effect
write 1: write phase increment and offset into DDS
+
reserved_ch1 [rw]
+
Reserved

Ignore on write, read as 0's
+
valid_ch2 [rw]
+
Valid signal for channel 2 DDS

Valid signal for channel 2 DDS:
write 0: no effect
write 1: write phase increment and offset into DDS
+
reserved_ch2 [rw]
+
Reserved

Ignore on write, read as 0's
+
valid_ch3 [rw]
+
Valid signal for channel 3 DDS

Valid signal for channel 3 DDS:
write 0: no effect
write 1: write phase increment and offset into DDS
+
reserved_ch3 [rw]
+
Reserved

Ignore on write, read as 0's
+

2.13. dds_pinc_ch0

@@ -1741,16 +1675,12 @@

2.13. dds_pinc_ch0

val[7:0]
- +
+
val [rw]
+
DDS phase increment parameter register for channel 0

DDS phase increment parameter register for channel 0.
It can be calculated as phase_inc = f_out * 2^(B_theta) / f_clk,
in which B_theta = 30 and f_clk = adc_clk, f_out = desired frequency.
+
reserved [rw]
+
Reserved

Ignore on write, read as 0's
+

2.14. dds_pinc_ch1

@@ -1817,16 +1747,12 @@

2.14. dds_pinc_ch1

val[7:0]
- +
+
val [rw]
+
DDS phase increment parameter register for channel 1

DDS phase increment parameter register for channel 1.
It can be calculated as phase_inc = f_out * 2^(B_theta) / f_clk,
in which B_theta = 30 and f_clk = adc_clk, f_out = desired frequency.
+
reserved [rw]
+
Reserved

Ignore on write, read as 0's
+

2.15. dds_pinc_ch2

@@ -1893,16 +1819,12 @@

2.15. dds_pinc_ch2

val[7:0]
- +
+
val [rw]
+
DDS phase increment parameter register for channel 2

DDS phase increment parameter register for channel 2.
It can be calculated as phase_inc = f_out * 2^(B_theta) / f_clk,
in which B_theta = 30 and f_clk = adc_clk, f_out = desired frequency.
+
reserved [rw]
+
Reserved

Ignore on write, read as 0's
+

2.16. dds_pinc_ch3

@@ -1969,16 +1891,12 @@

2.16. dds_pinc_ch3

val[7:0]
- +
+
val [rw]
+
DDS phase increment parameter register for channel 3

DDS phase increment parameter register for channel 3.
It can be calculated as phase_inc = f_out * 2^(B_theta) / f_clk,
in which B_theta = 30 and f_clk = adc_clk, f_out = desired frequency.
+
reserved [rw]
+
Reserved

Ignore on write, read as 0's
+

2.17. dds_poff_ch0

@@ -2045,16 +1963,12 @@

2.17. dds_poff_ch0

val[7:0]
- +
+
val [rw]
+
DDS phase offset parameter register for channel 0

DDS phase offset parameter register for channel 0.
It is determined as a fraction of a cycle, in FIX30_29.
For instance, 0.5 = 180 deegres offset
+
reserved [rw]
+
Reserved

Ignore on write, read as 0's
+

2.18. dds_poff_ch1

@@ -2121,16 +2035,12 @@

2.18. dds_poff_ch1

val[7:0]
- +
+
val [rw]
+
DDS phase offset parameter register for channel 1

DDS phase offset parameter register for channel 1.
It is determined as a fraction of a cycle, in FIX30_29.
For instance, 0.5 = 180 deegres offset
+
reserved [rw]
+
Reserved

Ignore on write, read as 0's
+

2.19. dds_poff_ch2

@@ -2197,16 +2107,12 @@

2.19. dds_poff_ch2

val[7:0]
- +
+
val [rw]
+
DDS phase offset parameter register for channel 2

DDS phase offset parameter register for channel 2.
It is determined as a fraction of a cycle, in FIX30_29.
For instance, 0.5 = 180 deegres offset
+
reserved [rw]
+
Reserved

Ignore on write, read as 0's
+

2.20. dds_poff_ch3

@@ -2273,16 +2179,12 @@

2.20. dds_poff_ch3

val[7:0]
- +
+
val [rw]
+
DDS phase offset parameter register for channel 3

DDS phase offset parameter register for channel 2.
It is determined as a fraction of a cycle, in FIX30_29.
For instance, 0.5 = 180 deegres offset
+
reserved [rw]
+
Reserved

Ignore on write, read as 0's
+

2.21. dsp_monit_amp_ch0

@@ -2348,12 +2250,10 @@

2.21. dsp_monit_amp_ch0

dsp_monit_amp_ch0[7:0]
- +
+
dsp_monit_amp_ch0 [ro]
+
Monit. Amplitude Value for channel 0

Monit. Amplitude Value for channel 0
+

2.22. dsp_monit_amp_ch1

@@ -2419,12 +2319,10 @@

2.22. dsp_monit_amp_ch1

dsp_monit_amp_ch1[7:0]
- +
+
dsp_monit_amp_ch1 [ro]
+
Monit. Amplitude Value for channel 1

Monit. Amplitude Value for channel 1
+

2.23. dsp_monit_amp_ch2

@@ -2490,12 +2388,10 @@

2.23. dsp_monit_amp_ch2

dsp_monit_amp_ch2[7:0]
- +
+
dsp_monit_amp_ch2 [ro]
+
Monit. Amplitude Value for channel 2

Monit. Amplitude Value for channel 2
+

2.24. dsp_monit_amp_ch3

@@ -2561,12 +2457,10 @@

2.24. dsp_monit_amp_ch3

dsp_monit_amp_ch3[7:0]
- +
+
dsp_monit_amp_ch3 [ro]
+
Monit. Amplitude Value for channel 3

Monit. Amplitude Value for channel 3
+

2.25. dsp_monit_pos_x

@@ -2632,12 +2526,10 @@

2.25. dsp_monit_pos_x

dsp_monit_pos_x[7:0]
- +
+
dsp_monit_pos_x [ro]
+
Monit. X Position Value

Monit. X Position Value
+

2.26. dsp_monit_pos_y

@@ -2703,12 +2595,10 @@

2.26. dsp_monit_pos_y

dsp_monit_pos_y[7:0]
- +
+
dsp_monit_pos_y [ro]
+
Monit. Y Position Value

Monit. Y Position Value
+

2.27. dsp_monit_pos_q

@@ -2774,12 +2664,10 @@

2.27. dsp_monit_pos_q

dsp_monit_pos_q[7:0]
- +
+
dsp_monit_pos_q [ro]
+
Monit. Q Position Value

Monit. Q Position Value
+

2.28. dsp_monit_pos_sum

@@ -2845,12 +2733,10 @@

2.28. dsp_monit_pos_sum

dsp_monit_pos_sum[7:0]
- +
+
dsp_monit_pos_sum [ro]
+
Monit. Sum Position Value

Monit. Sum Position Value
+

2.29. dsp_monit_updt

@@ -2916,12 +2802,10 @@

2.29. dsp_monit_updt

dsp_monit_updt[7:0]
- +
+
dsp_monit_updt [wo]
+
Monit. Amp/Pos update trigger

Monit. Amp/Pos update trigger
+

2.30. dsp_monit1_amp_ch0

@@ -2987,12 +2871,10 @@

2.30. dsp_monit1_amp_ch0

dsp_monit1_amp_ch0[7:0]
- +
+
dsp_monit1_amp_ch0 [ro]
+
Monit. 1 Amplitude Value for channel 0

Monit. 1 Amplitude Value for channel 0
+

2.31. dsp_monit1_amp_ch1

@@ -3058,12 +2940,10 @@

2.31. dsp_monit1_amp_ch1

dsp_monit1_amp_ch1[7:0]
- +
+
dsp_monit1_amp_ch1 [ro]
+
Monit. 1 Amplitude Value for channel 1

Monit. 1 Amplitude Value for channel 1
+

2.32. dsp_monit1_amp_ch2

@@ -3129,12 +3009,10 @@

2.32. dsp_monit1_amp_ch2

dsp_monit1_amp_ch2[7:0]
- +
+
dsp_monit1_amp_ch2 [ro]
+
Monit. 1 Amplitude Value for channel 2

Monit. 1 Amplitude Value for channel 2
+

2.33. dsp_monit1_amp_ch3

@@ -3200,12 +3078,10 @@

2.33. dsp_monit1_amp_ch3

dsp_monit1_amp_ch3[7:0]
- +
+
dsp_monit1_amp_ch3 [ro]
+
Monit. 1 Amplitude Value for channel 3

Monit. 1 Amplitude Value for channel 3
+

2.34. dsp_monit1_pos_x

@@ -3271,12 +3147,10 @@

2.34. dsp_monit1_pos_x

dsp_monit1_pos_x[7:0]
- +
+
dsp_monit1_pos_x [ro]
+
Monit. 1 X Position Value

Monit. 1 X Position Value
+

2.35. dsp_monit1_pos_y

@@ -3342,12 +3216,10 @@

2.35. dsp_monit1_pos_y

dsp_monit1_pos_y[7:0]
- +
+
dsp_monit1_pos_y [ro]
+
Monit. 1 Y Position Value

Monit. 1 Y Position Value
+

2.36. dsp_monit1_pos_q

@@ -3413,12 +3285,10 @@

2.36. dsp_monit1_pos_q

dsp_monit1_pos_q[7:0]
- +
+
dsp_monit1_pos_q [ro]
+
Monit. 1 Q Position Value

Monit. 1 Q Position Value
+

2.37. dsp_monit1_pos_sum

@@ -3484,12 +3354,10 @@

2.37. dsp_monit1_pos_sum

dsp_monit1_pos_sum[7:0]
- +
+
dsp_monit1_pos_sum [ro]
+
Monit. 1 Sum Position Value

Monit. 1 Sum Position Value
+

2.38. dsp_monit1_updt

@@ -3555,12 +3423,10 @@

2.38. dsp_monit1_updt

dsp_monit1_updt[7:0]
- +
+
dsp_monit1_updt [wo]
+
Monit. 1 Amp/Pos update trigger

Monit. 1 Amp/Pos update trigger
+

2.39. ampfifo_monit.ampfifo_monit_r0

@@ -3626,11 +3492,10 @@

2.39. ampfifo_monit.ampfifo_monit_r0

amp_ch0[7:0]
- +
+
amp_ch0 [ro]
+
Channel 0 Amplitude
+

2.40. ampfifo_monit.ampfifo_monit_r1

@@ -3696,11 +3561,10 @@

2.40. ampfifo_monit.ampfifo_monit_r1

amp_ch1[7:0]
- +
+
amp_ch1 [ro]
+
Channel 1 Amplitude
+

2.41. ampfifo_monit.ampfifo_monit_r2

@@ -3766,11 +3630,10 @@

2.41. ampfifo_monit.ampfifo_monit_r2

amp_ch2[7:0]
- +
+
amp_ch2 [ro]
+
Channel 2 Amplitude
+

2.42. ampfifo_monit.ampfifo_monit_r3

@@ -3836,11 +3699,10 @@

2.42. ampfifo_monit.ampfifo_monit_r3

amp_ch3[7:0]
- +
+
amp_ch3 [ro]
+
Channel 3 Amplitude
+

2.43. ampfifo_monit.ampfifo_monit_csr

@@ -3931,20 +3793,14 @@

2.43. ampfifo_monit.ampfifo_monit_csr

count[3:0]
- +
+
full [ro]
+
FIFO full flag

1: FIFO 'AMP FIFO Monitoring' is full
0: FIFO is not full
+
empty [ro]
+
FIFO empty flag

1: FIFO 'AMP FIFO Monitoring' is empty
0: FIFO is not empty
+
count [ro]
+
FIFO counter

Number of data records currently being stored in FIFO 'AMP FIFO Monitoring'
+

2.44. posfifo_monit.posfifo_monit_r0

@@ -4010,11 +3866,10 @@

2.44. posfifo_monit.posfifo_monit_r0

pos_x[7:0]
- +
+
pos_x [ro]
+
Channel X Position
+

2.45. posfifo_monit.posfifo_monit_r1

@@ -4080,11 +3935,10 @@

2.45. posfifo_monit.posfifo_monit_r1

pos_y[7:0]
- +
+
pos_y [ro]
+
Channel Y Position
+

2.46. posfifo_monit.posfifo_monit_r2

@@ -4150,11 +4004,10 @@

2.46. posfifo_monit.posfifo_monit_r2

pos_q[7:0]
- +
+
pos_q [ro]
+
Channel Q Position
+

2.47. posfifo_monit.posfifo_monit_r3

@@ -4220,11 +4073,10 @@

2.47. posfifo_monit.posfifo_monit_r3

pos_sum[7:0]
- +
+
pos_sum [ro]
+
Channel Sum Position
+

2.48. posfifo_monit.posfifo_monit_csr

@@ -4315,20 +4167,14 @@

2.48. posfifo_monit.posfifo_monit_csr

count[3:0]
- +
+
full [ro]
+
FIFO full flag

1: FIFO 'POS FIFO Monitoring' is full
0: FIFO is not full
+
empty [ro]
+
FIFO empty flag

1: FIFO 'POS FIFO Monitoring' is empty
0: FIFO is not empty
+
count [ro]
+
FIFO counter

Number of data records currently being stored in FIFO 'POS FIFO Monitoring'
+

2.49. ampfifo_monit1.ampfifo_monit1_r0

@@ -4394,11 +4240,10 @@

2.49. ampfifo_monit1.ampfifo_monit1_r0

amp_ch0[7:0]
- +
+
amp_ch0 [ro]
+
Channel 0 Amplitude
+

2.50. ampfifo_monit1.ampfifo_monit1_r1

@@ -4464,11 +4309,10 @@

2.50. ampfifo_monit1.ampfifo_monit1_r1

amp_ch1[7:0]
- +
+
amp_ch1 [ro]
+
Channel 1 Amplitude
+

2.51. ampfifo_monit1.ampfifo_monit1_r2

@@ -4534,11 +4378,10 @@

2.51. ampfifo_monit1.ampfifo_monit1_r2

amp_ch2[7:0]
- +
+
amp_ch2 [ro]
+
Channel 2 Amplitude
+

2.52. ampfifo_monit1.ampfifo_monit1_r3

@@ -4604,11 +4447,10 @@

2.52. ampfifo_monit1.ampfifo_monit1_r3

amp_ch3[7:0]
- +
+
amp_ch3 [ro]
+
Channel 3 Amplitude
+

2.53. ampfifo_monit1.ampfifo_monit1_csr

@@ -4699,20 +4541,14 @@

2.53. ampfifo_monit1.ampfifo_monit1_csr

count[3:0]
- +
+
full [ro]
+
FIFO full flag

1: FIFO 'AMP FIFO Monitoring 1' is full
0: FIFO is not full
+
empty [ro]
+
FIFO empty flag

1: FIFO 'AMP FIFO Monitoring 1' is empty
0: FIFO is not empty
+
count [ro]
+
FIFO counter

Number of data records currently being stored in FIFO 'AMP FIFO Monitoring 1'
+

2.54. posfifo_monit1.posfifo_monit1_r0

@@ -4778,11 +4614,10 @@

2.54. posfifo_monit1.posfifo_monit1_r0

pos_x[7:0]
- +
+
pos_x [ro]
+
Channel X Position
+

2.55. posfifo_monit1.posfifo_monit1_r1

@@ -4848,11 +4683,10 @@

2.55. posfifo_monit1.posfifo_monit1_r1

pos_y[7:0]
- +
+
pos_y [ro]
+
Channel Y Position
+

2.56. posfifo_monit1.posfifo_monit1_r2

@@ -4918,11 +4752,10 @@

2.56. posfifo_monit1.posfifo_monit1_r2

pos_q[7:0]
- +
+
pos_q [ro]
+
Channel Q Position
+

2.57. posfifo_monit1.posfifo_monit1_r3

@@ -4988,11 +4821,10 @@

2.57. posfifo_monit1.posfifo_monit1_r3

pos_sum[7:0]
- +
+
pos_sum [ro]
+
Channel Sum Position
+

2.58. posfifo_monit1.posfifo_monit1_csr

@@ -5083,20 +4915,14 @@

2.58. posfifo_monit1.posfifo_monit1_csr

count[3:0]
- +
+
full [ro]
+
FIFO full flag

1: FIFO 'POS FIFO Monitoring 1' is full
0: FIFO is not full
+
empty [ro]
+
FIFO empty flag

1: FIFO 'POS FIFO Monitoring 1' is empty
0: FIFO is not empty
+
count [ro]
+
FIFO counter

Number of data records currently being stored in FIFO 'POS FIFO Monitoring 1'
+

2.59. sw_tag

@@ -5178,20 +5004,14 @@

2.59. sw_tag

en
- +
+
en [rw]
+
Tag Synchronization Enable

Switching Tag synchronization
write 0: disable tag synchronization
write 1: enable tag synchronization
+
desync_cnt_rst [rw]
+
Switching Desynchronization Counter Reset

Switching Desynchronization Counter Reset
write 0: no change
write 1: reset counter
+
desync_cnt [rw]
+
Switching Desynchronization Counter

Switching Desynchronization Counter
write: number of samples to delay trigger
read: number of samples being delayed
+

2.60. sw_data_mask

@@ -5272,16 +5092,12 @@

2.60. sw_data_mask

en
- +
+
en [rw]
+
Switching Data Mask Enable

Switching Data Mask Enable
write 0: disable data mask
write 1: enable data mask
+
samples [rw]
+
Switching Data Mask Samples

Switching Data Mask Samples
write: number of samples to mask
read: number of samples being masked
+

2.61. tbt_tag

@@ -5350,24 +5166,16 @@

2.61. tbt_tag

en
- +
+
en [rw]
+
TbT Synchronizing Trigger Enable

TbT Synchronizing Trigger Enable
write 0: disable trigger
write 1: enable trigger
+
dly [rw]
+
TbT Synchronizing Trigger Delay

TbT Synchronizing Trigger Delay
write: number of samples to delay trigger
read: number of samples being delayed
+
desync_cnt_rst [rw]
+
TbT Desynchronization Counter Reset

TbT Desynchronization Counter Reset
write 0: no change
write 1: reset counter
+
desync_cnt [rw]
+
TbT Desynchronization Counter

TbT Desynchronization Counter
write: number of samples to delay trigger
read: number of samples being delayed
+

2.62. tbt_data_mask_ctl

@@ -5461,12 +5269,10 @@

2.62. tbt_data_mask_ctl

en
- +
+
en [rw]
+
TbT Masking Enable

TbT Masking
write 0: disable data mask
write 1: enable data mask
+

2.63. tbt_data_mask_samples

@@ -5532,16 +5338,12 @@

2.63. tbt_data_mask_samples

beg[7:0]
- +
+
beg [rw]
+
TbT Beginning Data Masking Samples

Select the number of samples to mask at the beginning of the TbT cycle
write: number of samples to mask
read: number of samples being masked
+
end [rw]
+
TbT Beginning Data Masking Samples

Select the number of samples to mask at the ending of the TbT cycle
write: number of samples to mask
read: number of samples being masked
+

2.64. monit1_tag

@@ -5610,24 +5412,16 @@

2.64. monit1_tag

en
- +
+
en [rw]
+
MONIT1 Synchronizing Trigger Enable

MONIT1 Synchronizing Trigger Enable
write 0: disable trigger
write 1: enable trigger
+
dly [rw]
+
MONIT1 Synchronizing Trigger Delay

MONIT1 Synchronizing Trigger Delay
write: number of samples to delay trigger
read: number of samples being delayed
+
desync_cnt_rst [rw]
+
MONIT1 Desynchronization Counter Reset

MONIT1 Desynchronization Counter Reset
write 0: no change
write 1: reset counter
+
desync_cnt [rw]
+
MONIT1 Desynchronization Counter

MONIT1 Desynchronization Counter
write: number of samples to delay trigger
read: number of samples being delayed
+

2.65. monit1_data_mask_ctl

@@ -5721,12 +5515,10 @@

2.65. monit1_data_mask_ctl

en
- +
+
en [rw]
+
MONIT1 Masking Enable

MONIT1 Masking
write 0: disable data mask
write 1: enable data mask
+

2.66. monit1_data_mask_samples

@@ -5792,16 +5584,12 @@

2.66. monit1_data_mask_samples

beg[7:0]
- +
+
beg [rw]
+
MONIT1 Beginning Data Masking Samples

Select the number of samples to mask at the beginning of the MONIT1 cycle
write: number of samples to mask
read: number of samples being masked
+
end [rw]
+
MONIT1 Beginning Data Masking Samples

Select the number of samples to mask at the ending of the MONIT1 cycle
write: number of samples to mask
read: number of samples being masked
+

2.67. monit_tag

@@ -5870,24 +5658,16 @@

2.67. monit_tag

en
- +
+
en [rw]
+
MONIT Synchronizing Trigger Enable

MONIT Synchronizing Trigger Enable
write 0: disable trigger
write 1: enable trigger
+
dly [rw]
+
MONIT Synchronizing Trigger Delay

MONIT Synchronizing Trigger Delay
write: number of samples to delay trigger
read: number of samples being delayed
+
desync_cnt_rst [rw]
+
MONIT Desynchronization Counter Reset

MONIT Desynchronization Counter Reset
write 0: no change
write 1: reset counter
+
desync_cnt [rw]
+
MONIT Desynchronization Counter

MONIT Desynchronization Counter
write: number of samples to delay trigger
read: number of samples being delayed
+

2.68. monit_data_mask_ctl

@@ -5981,12 +5761,10 @@

2.68. monit_data_mask_ctl

en
- +
+
en [rw]
+
MONIT Masking Enable

MONIT Masking
write 0: disable data mask
write 1: enable data mask
+

2.69. monit_data_mask_samples

@@ -6052,16 +5830,12 @@

2.69. monit_data_mask_samples

beg[7:0]
- +
+
beg [rw]
+
MONIT Beginning Data Masking Samples

Select the number of samples to mask at the beginning of the MONIT cycle
write: number of samples to mask
read: number of samples being masked
+
end [rw]
+
MONIT Beginning Data Masking Samples

Select the number of samples to mask at the ending of the MONIT cycle
write: number of samples to mask
read: number of samples being masked
+

2.70. offset_x

@@ -6127,12 +5901,10 @@

2.70. offset_x

offset_x[7:0]
- +
+
offset_x [rw]
+
BPM X position offset parameter register

BPM X position offset to be subtracted from calculated positions
+

2.71. offset_y

@@ -6198,12 +5970,10 @@

2.71. offset_y

offset_y[7:0]
- +
+
offset_y [rw]
+
BPM Y position offset parameter register

BPM Y position offset to be subtracted from calculated positions
+

2.72. adc_gains_fixed_point_pos

@@ -6269,11 +6039,10 @@

2.72. adc_gains_fixed_point_pos

data[7:0]
- +
+
data [ro]
+
fixed-point position constant value
+

2.73. adc_ch0_swclk_0_gain

@@ -6339,12 +6108,10 @@

2.73. adc_ch0_swclk_0_gain

data[7:0]
- +
+
data [rw]
+
gain

SFIX32_31.
+

2.74. adc_ch1_swclk_0_gain

@@ -6410,12 +6177,10 @@

2.74. adc_ch1_swclk_0_gain

data[7:0]
- +
+
data [rw]
+
gain

SFIX32_31.
+

2.75. adc_ch2_swclk_0_gain

@@ -6481,12 +6246,10 @@

2.75. adc_ch2_swclk_0_gain

data[7:0]
- +
+
data [rw]
+
gain

SFIX32_31.
+

2.76. adc_ch3_swclk_0_gain

@@ -6552,12 +6315,10 @@

2.76. adc_ch3_swclk_0_gain

data[7:0]
- +
+
data [rw]
+
gain

SFIX32_31.
+

2.77. adc_ch0_swclk_1_gain

@@ -6623,12 +6384,10 @@

2.77. adc_ch0_swclk_1_gain

data[7:0]
- +
+
data [rw]
+
gain

SFIX32_31.
+

2.78. adc_ch1_swclk_1_gain

@@ -6694,12 +6453,10 @@

2.78. adc_ch1_swclk_1_gain

data[7:0]
- +
+
data [rw]
+
gain

SFIX32_31.
+

2.79. adc_ch2_swclk_1_gain

@@ -6765,12 +6522,10 @@

2.79. adc_ch2_swclk_1_gain

data[7:0]
- +
+
data [rw]
+
gain

SFIX32_31.
+

2.80. adc_ch3_swclk_1_gain

@@ -6836,12 +6591,10 @@

2.80. adc_ch3_swclk_1_gain

data[7:0]
- +
+
data [rw]
+
gain

SFIX32_31.
+

2.81. adc_ch0_swclk_0_offset

@@ -6921,11 +6674,10 @@

2.81. adc_ch0_swclk_0_offset

data[7:0]
- +
+
data [rw]
+
offset
+

2.82. adc_ch1_swclk_0_offset

@@ -7005,11 +6757,10 @@

2.82. adc_ch1_swclk_0_offset

data[7:0]
- +
+
data [rw]
+
offset
+

2.83. adc_ch2_swclk_0_offset

@@ -7089,11 +6840,10 @@

2.83. adc_ch2_swclk_0_offset

data[7:0]
- +
+
data [rw]
+
offset
+

2.84. adc_ch3_swclk_0_offset

@@ -7173,11 +6923,10 @@

2.84. adc_ch3_swclk_0_offset

data[7:0]
- +
+
data [rw]
+
offset
+

2.85. adc_ch0_swclk_1_offset

@@ -7257,11 +7006,10 @@

2.85. adc_ch0_swclk_1_offset

data[7:0]
- +
+
data [rw]
+
offset
+

2.86. adc_ch1_swclk_1_offset

@@ -7341,11 +7089,10 @@

2.86. adc_ch1_swclk_1_offset

data[7:0]
- +
+
data [rw]
+
offset
+

2.87. adc_ch2_swclk_1_offset

@@ -7425,11 +7172,10 @@

2.87. adc_ch2_swclk_1_offset

data[7:0]
- +
+
data [rw]
+
offset
+

2.88. adc_ch3_swclk_1_offset

@@ -7509,11 +7255,10 @@

2.88. adc_ch3_swclk_1_offset

data[7:0]
- +
+
data [rw]
+
offset
+
diff --git a/hdl/modules/wb_position_calc/cheby/wb_pos_calc_regs.cheby b/hdl/modules/wb_position_calc/cheby/wb_pos_calc_regs.cheby index 5e83a0e1..19f27dbc 100644 --- a/hdl/modules/wb_position_calc/cheby/wb_pos_calc_regs.cheby +++ b/hdl/modules/wb_position_calc/cheby/wb_pos_calc_regs.cheby @@ -2038,7 +2038,6 @@ memory-map: type: SLV access_dev: WRITE_ONLY access_bus: READ_ONLY - clock: fs_clk2x_i - reg: name: adc_ch0_swclk_0_gain address: 0x00000120 diff --git a/hdl/modules/wb_position_calc/cheby/wb_pos_calc_regs.h b/hdl/modules/wb_position_calc/cheby/wb_pos_calc_regs.h index 7a0a9559..01657839 100644 --- a/hdl/modules/wb_position_calc/cheby/wb_pos_calc_regs.h +++ b/hdl/modules/wb_position_calc/cheby/wb_pos_calc_regs.h @@ -1,5 +1,8 @@ #ifndef __CHEBY__POS_CALC__H__ #define __CHEBY__POS_CALC__H__ + +#include + #define POS_CALC_SIZE 352 /* 0x160 */ /* Config divisor threshold TBT register */ diff --git a/hdl/modules/wb_position_calc/cheby/wb_pos_calc_regs.vhd b/hdl/modules/wb_position_calc/cheby/wb_pos_calc_regs.vhd index 41d75bb9..676981c1 100644 --- a/hdl/modules/wb_position_calc/cheby/wb_pos_calc_regs.vhd +++ b/hdl/modules/wb_position_calc/cheby/wb_pos_calc_regs.vhd @@ -3,7 +3,7 @@ ------------------------------------------------------------------------------- -- File : wb_pos_calc_regs.vhdl -- Author : auto-generated by wbgen2 from wb_pos_calc_regs.wb --- Created : Mon Jul 22 15:19:13 2024 +-- Created : Thu Sep 12 09:17:58 2024 -- Standard : VHDL'87 ------------------------------------------------------------------------------- -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wb_pos_calc_regs.wb @@ -269,7 +269,7 @@ entity wb_pos_calc_regs is pos_calc_offset_x_o : out std_logic_vector(31 downto 0); -- Port for asynchronous (clock: fs_clk2x_i) std_logic_vector field: 'BPM Y position offset' in reg: 'BPM Y position offset parameter register' pos_calc_offset_y_o : out std_logic_vector(31 downto 0); - -- Port for asynchronous (clock: fs_clk2x_i) std_logic_vector field: 'fixed-point position constant value' in reg: 'ADC gains fixed-point position constant' + -- Port for std_logic_vector field: 'fixed-point position constant value' in reg: 'ADC gains fixed-point position constant' pos_calc_adc_gains_fixed_point_pos_data_i : in std_logic_vector(31 downto 0); -- Port for asynchronous (clock: fs_clk2x_i) std_logic_vector field: 'gain' in reg: 'ADC channel 0 gain on RFFE switch state 0 (direct)' pos_calc_adc_ch0_swclk_0_gain_data_o : out std_logic_vector(31 downto 0); @@ -671,13 +671,6 @@ architecture syn of wb_pos_calc_regs is signal pos_calc_offset_y_swb_s0 : std_logic; signal pos_calc_offset_y_swb_s1 : std_logic; signal pos_calc_offset_y_swb_s2 : std_logic; - signal pos_calc_adc_gains_fixed_point_pos_data_int : std_logic_vector(31 downto 0); - signal pos_calc_adc_gains_fixed_point_pos_data_lwb : std_logic; - signal pos_calc_adc_gains_fixed_point_pos_data_lwb_delay : std_logic; - signal pos_calc_adc_gains_fixed_point_pos_data_lwb_in_progress : std_logic; - signal pos_calc_adc_gains_fixed_point_pos_data_lwb_s0 : std_logic; - signal pos_calc_adc_gains_fixed_point_pos_data_lwb_s1 : std_logic; - signal pos_calc_adc_gains_fixed_point_pos_data_lwb_s2 : std_logic; signal pos_calc_adc_ch0_swclk_0_gain_data_int : std_logic_vector(31 downto 0); signal pos_calc_adc_ch0_swclk_0_gain_data_swb : std_logic; signal pos_calc_adc_ch0_swclk_0_gain_data_swb_delay : std_logic; @@ -962,9 +955,6 @@ begin pos_calc_offset_y_int <= "00000000000000000000000000000000"; pos_calc_offset_y_swb <= '0'; pos_calc_offset_y_swb_delay <= '0'; - pos_calc_adc_gains_fixed_point_pos_data_lwb <= '0'; - pos_calc_adc_gains_fixed_point_pos_data_lwb_delay <= '0'; - pos_calc_adc_gains_fixed_point_pos_data_lwb_in_progress <= '0'; pos_calc_adc_ch0_swclk_0_gain_data_int <= "00000000000000000000000000000000"; pos_calc_adc_ch0_swclk_0_gain_data_swb <= '0'; pos_calc_adc_ch0_swclk_0_gain_data_swb_delay <= '0'; @@ -1177,12 +1167,6 @@ begin pos_calc_offset_x_swb_delay <= '0'; pos_calc_offset_y_swb <= pos_calc_offset_y_swb_delay; pos_calc_offset_y_swb_delay <= '0'; - pos_calc_adc_gains_fixed_point_pos_data_lwb <= pos_calc_adc_gains_fixed_point_pos_data_lwb_delay; - pos_calc_adc_gains_fixed_point_pos_data_lwb_delay <= '0'; - if ((ack_sreg(1) = '1') and (pos_calc_adc_gains_fixed_point_pos_data_lwb_in_progress = '1')) then - rddata_reg(31 downto 0) <= pos_calc_adc_gains_fixed_point_pos_data_int; - pos_calc_adc_gains_fixed_point_pos_data_lwb_in_progress <= '0'; - end if; pos_calc_adc_ch0_swclk_0_gain_data_swb <= pos_calc_adc_ch0_swclk_0_gain_data_swb_delay; pos_calc_adc_ch0_swclk_0_gain_data_swb_delay <= '0'; pos_calc_adc_ch1_swclk_0_gain_data_swb <= pos_calc_adc_ch1_swclk_0_gain_data_swb_delay; @@ -1947,12 +1931,8 @@ begin when "1000111" => if (wb_we_i = '1') then end if; - if (wb_we_i = '0') then - pos_calc_adc_gains_fixed_point_pos_data_lwb <= '1'; - pos_calc_adc_gains_fixed_point_pos_data_lwb_delay <= '1'; - pos_calc_adc_gains_fixed_point_pos_data_lwb_in_progress <= '1'; - end if; - ack_sreg(5) <= '1'; + rddata_reg(31 downto 0) <= pos_calc_adc_gains_fixed_point_pos_data_i; + ack_sreg(0) <= '1'; ack_in_progress <= '1'; when "1001000" => if (wb_we_i = '1') then @@ -3744,25 +3724,6 @@ begin -- fixed-point position constant value - -- asynchronous std_logic_vector register : fixed-point position constant value (type RO/WO, fs_clk2x_i <-> clk_sys_i) - process (fs_clk2x_i, rst_n_i) - begin - if (rst_n_i = '0') then - pos_calc_adc_gains_fixed_point_pos_data_lwb_s0 <= '0'; - pos_calc_adc_gains_fixed_point_pos_data_lwb_s1 <= '0'; - pos_calc_adc_gains_fixed_point_pos_data_lwb_s2 <= '0'; - pos_calc_adc_gains_fixed_point_pos_data_int <= "00000000000000000000000000000000"; - elsif rising_edge(fs_clk2x_i) then - pos_calc_adc_gains_fixed_point_pos_data_lwb_s0 <= pos_calc_adc_gains_fixed_point_pos_data_lwb; - pos_calc_adc_gains_fixed_point_pos_data_lwb_s1 <= pos_calc_adc_gains_fixed_point_pos_data_lwb_s0; - pos_calc_adc_gains_fixed_point_pos_data_lwb_s2 <= pos_calc_adc_gains_fixed_point_pos_data_lwb_s1; - if ((pos_calc_adc_gains_fixed_point_pos_data_lwb_s1 = '1') and (pos_calc_adc_gains_fixed_point_pos_data_lwb_s2 = '0')) then - pos_calc_adc_gains_fixed_point_pos_data_int <= pos_calc_adc_gains_fixed_point_pos_data_i; - end if; - end if; - end process; - - -- gain -- asynchronous std_logic_vector register : gain (type RW/RO, fs_clk2x_i <-> clk_sys_i) process (fs_clk2x_i, rst_n_i) diff --git a/hdl/sim/regs/wb_pos_calc_regs.vh b/hdl/sim/regs/wb_pos_calc_regs.vh index c6dd103a..730e901d 100644 --- a/hdl/sim/regs/wb_pos_calc_regs.vh +++ b/hdl/sim/regs/wb_pos_calc_regs.vh @@ -1,124 +1,173 @@ -// Do not edit. Generated by cheby 1.6.dev0 using these options: +// Do not edit. Generated by cheby 1.6.0rc1 using these options: // -i wb_pos_calc_regs.cheby --hdl vhdl --gen-wbgen-hdl wb_pos_calc_regs.vhd --doc html --gen-doc doc/wb_pos_calc_regs_wb.html --gen-c wb_pos_calc_regs.h --consts-style verilog --gen-consts ../../../sim/regs/wb_pos_calc_regs.vh -// Generated on Mon Jul 22 15:19:13 2024 by guilherme.ricioli +// Generated on Thu Sep 12 09:17:58 2024 by augusto `define POS_CALC_SIZE 352 `define ADDR_POS_CALC_DS_TBT_THRES 'h0 +`define ADDR_POS_CALC_DS_TBT_THRES_VAL 'h0 `define POS_CALC_DS_TBT_THRES_VAL_OFFSET 0 `define POS_CALC_DS_TBT_THRES_VAL 'h3ffffff +`define ADDR_POS_CALC_DS_TBT_THRES_RESERVED 'h0 `define POS_CALC_DS_TBT_THRES_RESERVED_OFFSET 26 `define POS_CALC_DS_TBT_THRES_RESERVED 'hfc000000 `define ADDR_POS_CALC_DS_FOFB_THRES 'h4 +`define ADDR_POS_CALC_DS_FOFB_THRES_VAL 'h4 `define POS_CALC_DS_FOFB_THRES_VAL_OFFSET 0 `define POS_CALC_DS_FOFB_THRES_VAL 'h3ffffff +`define ADDR_POS_CALC_DS_FOFB_THRES_RESERVED 'h4 `define POS_CALC_DS_FOFB_THRES_RESERVED_OFFSET 26 `define POS_CALC_DS_FOFB_THRES_RESERVED 'hfc000000 `define ADDR_POS_CALC_DS_MONIT_THRES 'h8 +`define ADDR_POS_CALC_DS_MONIT_THRES_VAL 'h8 `define POS_CALC_DS_MONIT_THRES_VAL_OFFSET 0 `define POS_CALC_DS_MONIT_THRES_VAL 'h3ffffff +`define ADDR_POS_CALC_DS_MONIT_THRES_RESERVED 'h8 `define POS_CALC_DS_MONIT_THRES_RESERVED_OFFSET 26 `define POS_CALC_DS_MONIT_THRES_RESERVED 'hfc000000 `define ADDR_POS_CALC_KX 'hc +`define ADDR_POS_CALC_KX_VAL 'hc `define POS_CALC_KX_VAL_OFFSET 0 `define POS_CALC_KX_VAL 'h1ffffff +`define ADDR_POS_CALC_KX_RESERVED 'hc `define POS_CALC_KX_RESERVED_OFFSET 25 `define POS_CALC_KX_RESERVED 'hfe000000 `define ADDR_POS_CALC_KY 'h10 +`define ADDR_POS_CALC_KY_VAL 'h10 `define POS_CALC_KY_VAL_OFFSET 0 `define POS_CALC_KY_VAL 'h1ffffff +`define ADDR_POS_CALC_KY_RESERVED 'h10 `define POS_CALC_KY_RESERVED_OFFSET 25 `define POS_CALC_KY_RESERVED 'hfe000000 `define ADDR_POS_CALC_KSUM 'h14 +`define ADDR_POS_CALC_KSUM_VAL 'h14 `define POS_CALC_KSUM_VAL_OFFSET 0 `define POS_CALC_KSUM_VAL 'h1ffffff +`define ADDR_POS_CALC_KSUM_RESERVED 'h14 `define POS_CALC_KSUM_RESERVED_OFFSET 25 `define POS_CALC_KSUM_RESERVED 'hfe000000 `define ADDR_POS_CALC_DSP_CTNR_TBT 'h18 +`define ADDR_POS_CALC_DSP_CTNR_TBT_CH01 'h18 `define POS_CALC_DSP_CTNR_TBT_CH01_OFFSET 0 `define POS_CALC_DSP_CTNR_TBT_CH01 'hffff +`define ADDR_POS_CALC_DSP_CTNR_TBT_CH23 'h18 `define POS_CALC_DSP_CTNR_TBT_CH23_OFFSET 16 `define POS_CALC_DSP_CTNR_TBT_CH23 'hffff0000 `define ADDR_POS_CALC_DSP_CTNR_FOFB 'h1c +`define ADDR_POS_CALC_DSP_CTNR_FOFB_CH01 'h1c `define POS_CALC_DSP_CTNR_FOFB_CH01_OFFSET 0 `define POS_CALC_DSP_CTNR_FOFB_CH01 'hffff +`define ADDR_POS_CALC_DSP_CTNR_FOFB_CH23 'h1c `define POS_CALC_DSP_CTNR_FOFB_CH23_OFFSET 16 `define POS_CALC_DSP_CTNR_FOFB_CH23 'hffff0000 `define ADDR_POS_CALC_DSP_CTNR1_MONIT 'h20 +`define ADDR_POS_CALC_DSP_CTNR1_MONIT_CIC 'h20 `define POS_CALC_DSP_CTNR1_MONIT_CIC_OFFSET 0 `define POS_CALC_DSP_CTNR1_MONIT_CIC 'hffff +`define ADDR_POS_CALC_DSP_CTNR1_MONIT_CFIR 'h20 `define POS_CALC_DSP_CTNR1_MONIT_CFIR_OFFSET 16 `define POS_CALC_DSP_CTNR1_MONIT_CFIR 'hffff0000 `define ADDR_POS_CALC_DSP_CTNR2_MONIT 'h24 +`define ADDR_POS_CALC_DSP_CTNR2_MONIT_PFIR 'h24 `define POS_CALC_DSP_CTNR2_MONIT_PFIR_OFFSET 0 `define POS_CALC_DSP_CTNR2_MONIT_PFIR 'hffff +`define ADDR_POS_CALC_DSP_CTNR2_MONIT_FIR_01 'h24 `define POS_CALC_DSP_CTNR2_MONIT_FIR_01_OFFSET 16 `define POS_CALC_DSP_CTNR2_MONIT_FIR_01 'hffff0000 `define ADDR_POS_CALC_DSP_ERR_CLR 'h28 +`define ADDR_POS_CALC_DSP_ERR_CLR_TBT 'h28 `define POS_CALC_DSP_ERR_CLR_TBT_OFFSET 0 `define POS_CALC_DSP_ERR_CLR_TBT 'h1 +`define ADDR_POS_CALC_DSP_ERR_CLR_FOFB 'h28 `define POS_CALC_DSP_ERR_CLR_FOFB_OFFSET 1 `define POS_CALC_DSP_ERR_CLR_FOFB 'h2 +`define ADDR_POS_CALC_DSP_ERR_CLR_MONIT_PART1 'h28 `define POS_CALC_DSP_ERR_CLR_MONIT_PART1_OFFSET 2 `define POS_CALC_DSP_ERR_CLR_MONIT_PART1 'h4 +`define ADDR_POS_CALC_DSP_ERR_CLR_MONIT_PART2 'h28 `define POS_CALC_DSP_ERR_CLR_MONIT_PART2_OFFSET 3 `define POS_CALC_DSP_ERR_CLR_MONIT_PART2 'h8 `define ADDR_POS_CALC_DDS_CFG 'h2c +`define ADDR_POS_CALC_DDS_CFG_VALID_CH0 'h2c `define POS_CALC_DDS_CFG_VALID_CH0_OFFSET 0 `define POS_CALC_DDS_CFG_VALID_CH0 'h1 +`define ADDR_POS_CALC_DDS_CFG_TEST_DATA 'h2c `define POS_CALC_DDS_CFG_TEST_DATA_OFFSET 1 `define POS_CALC_DDS_CFG_TEST_DATA 'h2 +`define ADDR_POS_CALC_DDS_CFG_RESERVED_CH0 'h2c `define POS_CALC_DDS_CFG_RESERVED_CH0_OFFSET 2 `define POS_CALC_DDS_CFG_RESERVED_CH0 'hfc +`define ADDR_POS_CALC_DDS_CFG_VALID_CH1 'h2c `define POS_CALC_DDS_CFG_VALID_CH1_OFFSET 8 `define POS_CALC_DDS_CFG_VALID_CH1 'h100 +`define ADDR_POS_CALC_DDS_CFG_RESERVED_CH1 'h2c `define POS_CALC_DDS_CFG_RESERVED_CH1_OFFSET 9 `define POS_CALC_DDS_CFG_RESERVED_CH1 'hfe00 +`define ADDR_POS_CALC_DDS_CFG_VALID_CH2 'h2c `define POS_CALC_DDS_CFG_VALID_CH2_OFFSET 16 `define POS_CALC_DDS_CFG_VALID_CH2 'h10000 +`define ADDR_POS_CALC_DDS_CFG_RESERVED_CH2 'h2c `define POS_CALC_DDS_CFG_RESERVED_CH2_OFFSET 17 `define POS_CALC_DDS_CFG_RESERVED_CH2 'hfe0000 +`define ADDR_POS_CALC_DDS_CFG_VALID_CH3 'h2c `define POS_CALC_DDS_CFG_VALID_CH3_OFFSET 24 `define POS_CALC_DDS_CFG_VALID_CH3 'h1000000 +`define ADDR_POS_CALC_DDS_CFG_RESERVED_CH3 'h2c `define POS_CALC_DDS_CFG_RESERVED_CH3_OFFSET 25 `define POS_CALC_DDS_CFG_RESERVED_CH3 'hfe000000 `define ADDR_POS_CALC_DDS_PINC_CH0 'h30 +`define ADDR_POS_CALC_DDS_PINC_CH0_VAL 'h30 `define POS_CALC_DDS_PINC_CH0_VAL_OFFSET 0 `define POS_CALC_DDS_PINC_CH0_VAL 'h3fffffff +`define ADDR_POS_CALC_DDS_PINC_CH0_RESERVED 'h30 `define POS_CALC_DDS_PINC_CH0_RESERVED_OFFSET 30 `define POS_CALC_DDS_PINC_CH0_RESERVED 'hc0000000 `define ADDR_POS_CALC_DDS_PINC_CH1 'h34 +`define ADDR_POS_CALC_DDS_PINC_CH1_VAL 'h34 `define POS_CALC_DDS_PINC_CH1_VAL_OFFSET 0 `define POS_CALC_DDS_PINC_CH1_VAL 'h3fffffff +`define ADDR_POS_CALC_DDS_PINC_CH1_RESERVED 'h34 `define POS_CALC_DDS_PINC_CH1_RESERVED_OFFSET 30 `define POS_CALC_DDS_PINC_CH1_RESERVED 'hc0000000 `define ADDR_POS_CALC_DDS_PINC_CH2 'h38 +`define ADDR_POS_CALC_DDS_PINC_CH2_VAL 'h38 `define POS_CALC_DDS_PINC_CH2_VAL_OFFSET 0 `define POS_CALC_DDS_PINC_CH2_VAL 'h3fffffff +`define ADDR_POS_CALC_DDS_PINC_CH2_RESERVED 'h38 `define POS_CALC_DDS_PINC_CH2_RESERVED_OFFSET 30 `define POS_CALC_DDS_PINC_CH2_RESERVED 'hc0000000 `define ADDR_POS_CALC_DDS_PINC_CH3 'h3c +`define ADDR_POS_CALC_DDS_PINC_CH3_VAL 'h3c `define POS_CALC_DDS_PINC_CH3_VAL_OFFSET 0 `define POS_CALC_DDS_PINC_CH3_VAL 'h3fffffff +`define ADDR_POS_CALC_DDS_PINC_CH3_RESERVED 'h3c `define POS_CALC_DDS_PINC_CH3_RESERVED_OFFSET 30 `define POS_CALC_DDS_PINC_CH3_RESERVED 'hc0000000 `define ADDR_POS_CALC_DDS_POFF_CH0 'h40 +`define ADDR_POS_CALC_DDS_POFF_CH0_VAL 'h40 `define POS_CALC_DDS_POFF_CH0_VAL_OFFSET 0 `define POS_CALC_DDS_POFF_CH0_VAL 'h3fffffff +`define ADDR_POS_CALC_DDS_POFF_CH0_RESERVED 'h40 `define POS_CALC_DDS_POFF_CH0_RESERVED_OFFSET 30 `define POS_CALC_DDS_POFF_CH0_RESERVED 'hc0000000 `define ADDR_POS_CALC_DDS_POFF_CH1 'h44 +`define ADDR_POS_CALC_DDS_POFF_CH1_VAL 'h44 `define POS_CALC_DDS_POFF_CH1_VAL_OFFSET 0 `define POS_CALC_DDS_POFF_CH1_VAL 'h3fffffff +`define ADDR_POS_CALC_DDS_POFF_CH1_RESERVED 'h44 `define POS_CALC_DDS_POFF_CH1_RESERVED_OFFSET 30 `define POS_CALC_DDS_POFF_CH1_RESERVED 'hc0000000 `define ADDR_POS_CALC_DDS_POFF_CH2 'h48 +`define ADDR_POS_CALC_DDS_POFF_CH2_VAL 'h48 `define POS_CALC_DDS_POFF_CH2_VAL_OFFSET 0 `define POS_CALC_DDS_POFF_CH2_VAL 'h3fffffff +`define ADDR_POS_CALC_DDS_POFF_CH2_RESERVED 'h48 `define POS_CALC_DDS_POFF_CH2_RESERVED_OFFSET 30 `define POS_CALC_DDS_POFF_CH2_RESERVED 'hc0000000 `define ADDR_POS_CALC_DDS_POFF_CH3 'h4c +`define ADDR_POS_CALC_DDS_POFF_CH3_VAL 'h4c `define POS_CALC_DDS_POFF_CH3_VAL_OFFSET 0 `define POS_CALC_DDS_POFF_CH3_VAL 'h3fffffff +`define ADDR_POS_CALC_DDS_POFF_CH3_RESERVED 'h4c `define POS_CALC_DDS_POFF_CH3_RESERVED_OFFSET 30 `define POS_CALC_DDS_POFF_CH3_RESERVED 'hc0000000 `define ADDR_POS_CALC_DSP_MONIT_AMP_CH0 'h50 @@ -142,200 +191,271 @@ `define ADDR_POS_CALC_AMPFIFO_MONIT 'h98 `define POS_CALC_AMPFIFO_MONIT_SIZE 20 `define ADDR_POS_CALC_AMPFIFO_MONIT_AMPFIFO_MONIT_R0 'h98 +`define ADDR_POS_CALC_AMPFIFO_MONIT_AMPFIFO_MONIT_R0_AMP_CH0 'h98 `define POS_CALC_AMPFIFO_MONIT_AMPFIFO_MONIT_R0_AMP_CH0_OFFSET 0 `define POS_CALC_AMPFIFO_MONIT_AMPFIFO_MONIT_R0_AMP_CH0 'hffffffff `define ADDR_POS_CALC_AMPFIFO_MONIT_AMPFIFO_MONIT_R1 'h9c +`define ADDR_POS_CALC_AMPFIFO_MONIT_AMPFIFO_MONIT_R1_AMP_CH1 'h9c `define POS_CALC_AMPFIFO_MONIT_AMPFIFO_MONIT_R1_AMP_CH1_OFFSET 0 `define POS_CALC_AMPFIFO_MONIT_AMPFIFO_MONIT_R1_AMP_CH1 'hffffffff `define ADDR_POS_CALC_AMPFIFO_MONIT_AMPFIFO_MONIT_R2 'ha0 +`define ADDR_POS_CALC_AMPFIFO_MONIT_AMPFIFO_MONIT_R2_AMP_CH2 'ha0 `define POS_CALC_AMPFIFO_MONIT_AMPFIFO_MONIT_R2_AMP_CH2_OFFSET 0 `define POS_CALC_AMPFIFO_MONIT_AMPFIFO_MONIT_R2_AMP_CH2 'hffffffff `define ADDR_POS_CALC_AMPFIFO_MONIT_AMPFIFO_MONIT_R3 'ha4 +`define ADDR_POS_CALC_AMPFIFO_MONIT_AMPFIFO_MONIT_R3_AMP_CH3 'ha4 `define POS_CALC_AMPFIFO_MONIT_AMPFIFO_MONIT_R3_AMP_CH3_OFFSET 0 `define POS_CALC_AMPFIFO_MONIT_AMPFIFO_MONIT_R3_AMP_CH3 'hffffffff `define ADDR_POS_CALC_AMPFIFO_MONIT_AMPFIFO_MONIT_CSR 'ha8 +`define ADDR_POS_CALC_AMPFIFO_MONIT_AMPFIFO_MONIT_CSR_FULL 'ha8 `define POS_CALC_AMPFIFO_MONIT_AMPFIFO_MONIT_CSR_FULL_OFFSET 16 `define POS_CALC_AMPFIFO_MONIT_AMPFIFO_MONIT_CSR_FULL 'h10000 +`define ADDR_POS_CALC_AMPFIFO_MONIT_AMPFIFO_MONIT_CSR_EMPTY 'ha8 `define POS_CALC_AMPFIFO_MONIT_AMPFIFO_MONIT_CSR_EMPTY_OFFSET 17 `define POS_CALC_AMPFIFO_MONIT_AMPFIFO_MONIT_CSR_EMPTY 'h20000 +`define ADDR_POS_CALC_AMPFIFO_MONIT_AMPFIFO_MONIT_CSR_COUNT 'ha8 `define POS_CALC_AMPFIFO_MONIT_AMPFIFO_MONIT_CSR_COUNT_OFFSET 0 `define POS_CALC_AMPFIFO_MONIT_AMPFIFO_MONIT_CSR_COUNT 'hf `define ADDR_POS_CALC_POSFIFO_MONIT 'hac `define POS_CALC_POSFIFO_MONIT_SIZE 20 `define ADDR_POS_CALC_POSFIFO_MONIT_POSFIFO_MONIT_R0 'hac +`define ADDR_POS_CALC_POSFIFO_MONIT_POSFIFO_MONIT_R0_POS_X 'hac `define POS_CALC_POSFIFO_MONIT_POSFIFO_MONIT_R0_POS_X_OFFSET 0 `define POS_CALC_POSFIFO_MONIT_POSFIFO_MONIT_R0_POS_X 'hffffffff `define ADDR_POS_CALC_POSFIFO_MONIT_POSFIFO_MONIT_R1 'hb0 +`define ADDR_POS_CALC_POSFIFO_MONIT_POSFIFO_MONIT_R1_POS_Y 'hb0 `define POS_CALC_POSFIFO_MONIT_POSFIFO_MONIT_R1_POS_Y_OFFSET 0 `define POS_CALC_POSFIFO_MONIT_POSFIFO_MONIT_R1_POS_Y 'hffffffff `define ADDR_POS_CALC_POSFIFO_MONIT_POSFIFO_MONIT_R2 'hb4 +`define ADDR_POS_CALC_POSFIFO_MONIT_POSFIFO_MONIT_R2_POS_Q 'hb4 `define POS_CALC_POSFIFO_MONIT_POSFIFO_MONIT_R2_POS_Q_OFFSET 0 `define POS_CALC_POSFIFO_MONIT_POSFIFO_MONIT_R2_POS_Q 'hffffffff `define ADDR_POS_CALC_POSFIFO_MONIT_POSFIFO_MONIT_R3 'hb8 +`define ADDR_POS_CALC_POSFIFO_MONIT_POSFIFO_MONIT_R3_POS_SUM 'hb8 `define POS_CALC_POSFIFO_MONIT_POSFIFO_MONIT_R3_POS_SUM_OFFSET 0 `define POS_CALC_POSFIFO_MONIT_POSFIFO_MONIT_R3_POS_SUM 'hffffffff `define ADDR_POS_CALC_POSFIFO_MONIT_POSFIFO_MONIT_CSR 'hbc +`define ADDR_POS_CALC_POSFIFO_MONIT_POSFIFO_MONIT_CSR_FULL 'hbc `define POS_CALC_POSFIFO_MONIT_POSFIFO_MONIT_CSR_FULL_OFFSET 16 `define POS_CALC_POSFIFO_MONIT_POSFIFO_MONIT_CSR_FULL 'h10000 +`define ADDR_POS_CALC_POSFIFO_MONIT_POSFIFO_MONIT_CSR_EMPTY 'hbc `define POS_CALC_POSFIFO_MONIT_POSFIFO_MONIT_CSR_EMPTY_OFFSET 17 `define POS_CALC_POSFIFO_MONIT_POSFIFO_MONIT_CSR_EMPTY 'h20000 +`define ADDR_POS_CALC_POSFIFO_MONIT_POSFIFO_MONIT_CSR_COUNT 'hbc `define POS_CALC_POSFIFO_MONIT_POSFIFO_MONIT_CSR_COUNT_OFFSET 0 `define POS_CALC_POSFIFO_MONIT_POSFIFO_MONIT_CSR_COUNT 'hf `define ADDR_POS_CALC_AMPFIFO_MONIT1 'hc0 `define POS_CALC_AMPFIFO_MONIT1_SIZE 20 `define ADDR_POS_CALC_AMPFIFO_MONIT1_AMPFIFO_MONIT1_R0 'hc0 +`define ADDR_POS_CALC_AMPFIFO_MONIT1_AMPFIFO_MONIT1_R0_AMP_CH0 'hc0 `define POS_CALC_AMPFIFO_MONIT1_AMPFIFO_MONIT1_R0_AMP_CH0_OFFSET 0 `define POS_CALC_AMPFIFO_MONIT1_AMPFIFO_MONIT1_R0_AMP_CH0 'hffffffff `define ADDR_POS_CALC_AMPFIFO_MONIT1_AMPFIFO_MONIT1_R1 'hc4 +`define ADDR_POS_CALC_AMPFIFO_MONIT1_AMPFIFO_MONIT1_R1_AMP_CH1 'hc4 `define POS_CALC_AMPFIFO_MONIT1_AMPFIFO_MONIT1_R1_AMP_CH1_OFFSET 0 `define POS_CALC_AMPFIFO_MONIT1_AMPFIFO_MONIT1_R1_AMP_CH1 'hffffffff `define ADDR_POS_CALC_AMPFIFO_MONIT1_AMPFIFO_MONIT1_R2 'hc8 +`define ADDR_POS_CALC_AMPFIFO_MONIT1_AMPFIFO_MONIT1_R2_AMP_CH2 'hc8 `define POS_CALC_AMPFIFO_MONIT1_AMPFIFO_MONIT1_R2_AMP_CH2_OFFSET 0 `define POS_CALC_AMPFIFO_MONIT1_AMPFIFO_MONIT1_R2_AMP_CH2 'hffffffff `define ADDR_POS_CALC_AMPFIFO_MONIT1_AMPFIFO_MONIT1_R3 'hcc +`define ADDR_POS_CALC_AMPFIFO_MONIT1_AMPFIFO_MONIT1_R3_AMP_CH3 'hcc `define POS_CALC_AMPFIFO_MONIT1_AMPFIFO_MONIT1_R3_AMP_CH3_OFFSET 0 `define POS_CALC_AMPFIFO_MONIT1_AMPFIFO_MONIT1_R3_AMP_CH3 'hffffffff `define ADDR_POS_CALC_AMPFIFO_MONIT1_AMPFIFO_MONIT1_CSR 'hd0 +`define ADDR_POS_CALC_AMPFIFO_MONIT1_AMPFIFO_MONIT1_CSR_FULL 'hd0 `define POS_CALC_AMPFIFO_MONIT1_AMPFIFO_MONIT1_CSR_FULL_OFFSET 16 `define POS_CALC_AMPFIFO_MONIT1_AMPFIFO_MONIT1_CSR_FULL 'h10000 +`define ADDR_POS_CALC_AMPFIFO_MONIT1_AMPFIFO_MONIT1_CSR_EMPTY 'hd0 `define POS_CALC_AMPFIFO_MONIT1_AMPFIFO_MONIT1_CSR_EMPTY_OFFSET 17 `define POS_CALC_AMPFIFO_MONIT1_AMPFIFO_MONIT1_CSR_EMPTY 'h20000 +`define ADDR_POS_CALC_AMPFIFO_MONIT1_AMPFIFO_MONIT1_CSR_COUNT 'hd0 `define POS_CALC_AMPFIFO_MONIT1_AMPFIFO_MONIT1_CSR_COUNT_OFFSET 0 `define POS_CALC_AMPFIFO_MONIT1_AMPFIFO_MONIT1_CSR_COUNT 'hf `define ADDR_POS_CALC_POSFIFO_MONIT1 'hd4 `define POS_CALC_POSFIFO_MONIT1_SIZE 20 `define ADDR_POS_CALC_POSFIFO_MONIT1_POSFIFO_MONIT1_R0 'hd4 +`define ADDR_POS_CALC_POSFIFO_MONIT1_POSFIFO_MONIT1_R0_POS_X 'hd4 `define POS_CALC_POSFIFO_MONIT1_POSFIFO_MONIT1_R0_POS_X_OFFSET 0 `define POS_CALC_POSFIFO_MONIT1_POSFIFO_MONIT1_R0_POS_X 'hffffffff `define ADDR_POS_CALC_POSFIFO_MONIT1_POSFIFO_MONIT1_R1 'hd8 +`define ADDR_POS_CALC_POSFIFO_MONIT1_POSFIFO_MONIT1_R1_POS_Y 'hd8 `define POS_CALC_POSFIFO_MONIT1_POSFIFO_MONIT1_R1_POS_Y_OFFSET 0 `define POS_CALC_POSFIFO_MONIT1_POSFIFO_MONIT1_R1_POS_Y 'hffffffff `define ADDR_POS_CALC_POSFIFO_MONIT1_POSFIFO_MONIT1_R2 'hdc +`define ADDR_POS_CALC_POSFIFO_MONIT1_POSFIFO_MONIT1_R2_POS_Q 'hdc `define POS_CALC_POSFIFO_MONIT1_POSFIFO_MONIT1_R2_POS_Q_OFFSET 0 `define POS_CALC_POSFIFO_MONIT1_POSFIFO_MONIT1_R2_POS_Q 'hffffffff `define ADDR_POS_CALC_POSFIFO_MONIT1_POSFIFO_MONIT1_R3 'he0 +`define ADDR_POS_CALC_POSFIFO_MONIT1_POSFIFO_MONIT1_R3_POS_SUM 'he0 `define POS_CALC_POSFIFO_MONIT1_POSFIFO_MONIT1_R3_POS_SUM_OFFSET 0 `define POS_CALC_POSFIFO_MONIT1_POSFIFO_MONIT1_R3_POS_SUM 'hffffffff `define ADDR_POS_CALC_POSFIFO_MONIT1_POSFIFO_MONIT1_CSR 'he4 +`define ADDR_POS_CALC_POSFIFO_MONIT1_POSFIFO_MONIT1_CSR_FULL 'he4 `define POS_CALC_POSFIFO_MONIT1_POSFIFO_MONIT1_CSR_FULL_OFFSET 16 `define POS_CALC_POSFIFO_MONIT1_POSFIFO_MONIT1_CSR_FULL 'h10000 +`define ADDR_POS_CALC_POSFIFO_MONIT1_POSFIFO_MONIT1_CSR_EMPTY 'he4 `define POS_CALC_POSFIFO_MONIT1_POSFIFO_MONIT1_CSR_EMPTY_OFFSET 17 `define POS_CALC_POSFIFO_MONIT1_POSFIFO_MONIT1_CSR_EMPTY 'h20000 +`define ADDR_POS_CALC_POSFIFO_MONIT1_POSFIFO_MONIT1_CSR_COUNT 'he4 `define POS_CALC_POSFIFO_MONIT1_POSFIFO_MONIT1_CSR_COUNT_OFFSET 0 `define POS_CALC_POSFIFO_MONIT1_POSFIFO_MONIT1_CSR_COUNT 'hf `define ADDR_POS_CALC_SW_TAG 'he8 +`define ADDR_POS_CALC_SW_TAG_EN 'he8 `define POS_CALC_SW_TAG_EN_OFFSET 0 `define POS_CALC_SW_TAG_EN 'h1 +`define ADDR_POS_CALC_SW_TAG_DESYNC_CNT_RST 'he8 `define POS_CALC_SW_TAG_DESYNC_CNT_RST_OFFSET 8 `define POS_CALC_SW_TAG_DESYNC_CNT_RST 'h100 +`define ADDR_POS_CALC_SW_TAG_DESYNC_CNT 'he8 `define POS_CALC_SW_TAG_DESYNC_CNT_OFFSET 9 `define POS_CALC_SW_TAG_DESYNC_CNT 'h7ffe00 `define ADDR_POS_CALC_SW_DATA_MASK 'hec +`define ADDR_POS_CALC_SW_DATA_MASK_EN 'hec `define POS_CALC_SW_DATA_MASK_EN_OFFSET 0 `define POS_CALC_SW_DATA_MASK_EN 'h1 +`define ADDR_POS_CALC_SW_DATA_MASK_SAMPLES 'hec `define POS_CALC_SW_DATA_MASK_SAMPLES_OFFSET 1 `define POS_CALC_SW_DATA_MASK_SAMPLES 'h1fffe `define ADDR_POS_CALC_TBT_TAG 'hf0 +`define ADDR_POS_CALC_TBT_TAG_EN 'hf0 `define POS_CALC_TBT_TAG_EN_OFFSET 0 `define POS_CALC_TBT_TAG_EN 'h1 +`define ADDR_POS_CALC_TBT_TAG_DLY 'hf0 `define POS_CALC_TBT_TAG_DLY_OFFSET 1 `define POS_CALC_TBT_TAG_DLY 'h1fffe +`define ADDR_POS_CALC_TBT_TAG_DESYNC_CNT_RST 'hf0 `define POS_CALC_TBT_TAG_DESYNC_CNT_RST_OFFSET 17 `define POS_CALC_TBT_TAG_DESYNC_CNT_RST 'h20000 +`define ADDR_POS_CALC_TBT_TAG_DESYNC_CNT 'hf0 `define POS_CALC_TBT_TAG_DESYNC_CNT_OFFSET 18 `define POS_CALC_TBT_TAG_DESYNC_CNT 'hfffc0000 `define ADDR_POS_CALC_TBT_DATA_MASK_CTL 'hf4 +`define ADDR_POS_CALC_TBT_DATA_MASK_CTL_EN 'hf4 `define POS_CALC_TBT_DATA_MASK_CTL_EN_OFFSET 0 `define POS_CALC_TBT_DATA_MASK_CTL_EN 'h1 `define ADDR_POS_CALC_TBT_DATA_MASK_SAMPLES 'hf8 +`define ADDR_POS_CALC_TBT_DATA_MASK_SAMPLES_BEG 'hf8 `define POS_CALC_TBT_DATA_MASK_SAMPLES_BEG_OFFSET 0 `define POS_CALC_TBT_DATA_MASK_SAMPLES_BEG 'hffff +`define ADDR_POS_CALC_TBT_DATA_MASK_SAMPLES_END 'hf8 `define POS_CALC_TBT_DATA_MASK_SAMPLES_END_OFFSET 16 `define POS_CALC_TBT_DATA_MASK_SAMPLES_END 'hffff0000 `define ADDR_POS_CALC_MONIT1_TAG 'hfc +`define ADDR_POS_CALC_MONIT1_TAG_EN 'hfc `define POS_CALC_MONIT1_TAG_EN_OFFSET 0 `define POS_CALC_MONIT1_TAG_EN 'h1 +`define ADDR_POS_CALC_MONIT1_TAG_DLY 'hfc `define POS_CALC_MONIT1_TAG_DLY_OFFSET 1 `define POS_CALC_MONIT1_TAG_DLY 'h1fffe +`define ADDR_POS_CALC_MONIT1_TAG_DESYNC_CNT_RST 'hfc `define POS_CALC_MONIT1_TAG_DESYNC_CNT_RST_OFFSET 17 `define POS_CALC_MONIT1_TAG_DESYNC_CNT_RST 'h20000 +`define ADDR_POS_CALC_MONIT1_TAG_DESYNC_CNT 'hfc `define POS_CALC_MONIT1_TAG_DESYNC_CNT_OFFSET 18 `define POS_CALC_MONIT1_TAG_DESYNC_CNT 'hfffc0000 `define ADDR_POS_CALC_MONIT1_DATA_MASK_CTL 'h100 +`define ADDR_POS_CALC_MONIT1_DATA_MASK_CTL_EN 'h100 `define POS_CALC_MONIT1_DATA_MASK_CTL_EN_OFFSET 0 `define POS_CALC_MONIT1_DATA_MASK_CTL_EN 'h1 `define ADDR_POS_CALC_MONIT1_DATA_MASK_SAMPLES 'h104 +`define ADDR_POS_CALC_MONIT1_DATA_MASK_SAMPLES_BEG 'h104 `define POS_CALC_MONIT1_DATA_MASK_SAMPLES_BEG_OFFSET 0 `define POS_CALC_MONIT1_DATA_MASK_SAMPLES_BEG 'hffff +`define ADDR_POS_CALC_MONIT1_DATA_MASK_SAMPLES_END 'h104 `define POS_CALC_MONIT1_DATA_MASK_SAMPLES_END_OFFSET 16 `define POS_CALC_MONIT1_DATA_MASK_SAMPLES_END 'hffff0000 `define ADDR_POS_CALC_MONIT_TAG 'h108 +`define ADDR_POS_CALC_MONIT_TAG_EN 'h108 `define POS_CALC_MONIT_TAG_EN_OFFSET 0 `define POS_CALC_MONIT_TAG_EN 'h1 +`define ADDR_POS_CALC_MONIT_TAG_DLY 'h108 `define POS_CALC_MONIT_TAG_DLY_OFFSET 1 `define POS_CALC_MONIT_TAG_DLY 'h1fffe +`define ADDR_POS_CALC_MONIT_TAG_DESYNC_CNT_RST 'h108 `define POS_CALC_MONIT_TAG_DESYNC_CNT_RST_OFFSET 17 `define POS_CALC_MONIT_TAG_DESYNC_CNT_RST 'h20000 +`define ADDR_POS_CALC_MONIT_TAG_DESYNC_CNT 'h108 `define POS_CALC_MONIT_TAG_DESYNC_CNT_OFFSET 18 `define POS_CALC_MONIT_TAG_DESYNC_CNT 'hfffc0000 `define ADDR_POS_CALC_MONIT_DATA_MASK_CTL 'h10c +`define ADDR_POS_CALC_MONIT_DATA_MASK_CTL_EN 'h10c `define POS_CALC_MONIT_DATA_MASK_CTL_EN_OFFSET 0 `define POS_CALC_MONIT_DATA_MASK_CTL_EN 'h1 `define ADDR_POS_CALC_MONIT_DATA_MASK_SAMPLES 'h110 +`define ADDR_POS_CALC_MONIT_DATA_MASK_SAMPLES_BEG 'h110 `define POS_CALC_MONIT_DATA_MASK_SAMPLES_BEG_OFFSET 0 `define POS_CALC_MONIT_DATA_MASK_SAMPLES_BEG 'hffff +`define ADDR_POS_CALC_MONIT_DATA_MASK_SAMPLES_END 'h110 `define POS_CALC_MONIT_DATA_MASK_SAMPLES_END_OFFSET 16 `define POS_CALC_MONIT_DATA_MASK_SAMPLES_END 'hffff0000 `define ADDR_POS_CALC_OFFSET_X 'h114 `define ADDR_POS_CALC_OFFSET_Y 'h118 `define ADDR_POS_CALC_ADC_GAINS_FIXED_POINT_POS 'h11c +`define ADDR_POS_CALC_ADC_GAINS_FIXED_POINT_POS_DATA 'h11c `define POS_CALC_ADC_GAINS_FIXED_POINT_POS_DATA_OFFSET 0 `define POS_CALC_ADC_GAINS_FIXED_POINT_POS_DATA 'hffffffff `define ADDR_POS_CALC_ADC_CH0_SWCLK_0_GAIN 'h120 +`define ADDR_POS_CALC_ADC_CH0_SWCLK_0_GAIN_DATA 'h120 `define POS_CALC_ADC_CH0_SWCLK_0_GAIN_DATA_OFFSET 0 `define POS_CALC_ADC_CH0_SWCLK_0_GAIN_DATA 'hffffffff `define ADDR_POS_CALC_ADC_CH1_SWCLK_0_GAIN 'h124 +`define ADDR_POS_CALC_ADC_CH1_SWCLK_0_GAIN_DATA 'h124 `define POS_CALC_ADC_CH1_SWCLK_0_GAIN_DATA_OFFSET 0 `define POS_CALC_ADC_CH1_SWCLK_0_GAIN_DATA 'hffffffff `define ADDR_POS_CALC_ADC_CH2_SWCLK_0_GAIN 'h128 +`define ADDR_POS_CALC_ADC_CH2_SWCLK_0_GAIN_DATA 'h128 `define POS_CALC_ADC_CH2_SWCLK_0_GAIN_DATA_OFFSET 0 `define POS_CALC_ADC_CH2_SWCLK_0_GAIN_DATA 'hffffffff `define ADDR_POS_CALC_ADC_CH3_SWCLK_0_GAIN 'h12c +`define ADDR_POS_CALC_ADC_CH3_SWCLK_0_GAIN_DATA 'h12c `define POS_CALC_ADC_CH3_SWCLK_0_GAIN_DATA_OFFSET 0 `define POS_CALC_ADC_CH3_SWCLK_0_GAIN_DATA 'hffffffff `define ADDR_POS_CALC_ADC_CH0_SWCLK_1_GAIN 'h130 +`define ADDR_POS_CALC_ADC_CH0_SWCLK_1_GAIN_DATA 'h130 `define POS_CALC_ADC_CH0_SWCLK_1_GAIN_DATA_OFFSET 0 `define POS_CALC_ADC_CH0_SWCLK_1_GAIN_DATA 'hffffffff `define ADDR_POS_CALC_ADC_CH1_SWCLK_1_GAIN 'h134 +`define ADDR_POS_CALC_ADC_CH1_SWCLK_1_GAIN_DATA 'h134 `define POS_CALC_ADC_CH1_SWCLK_1_GAIN_DATA_OFFSET 0 `define POS_CALC_ADC_CH1_SWCLK_1_GAIN_DATA 'hffffffff `define ADDR_POS_CALC_ADC_CH2_SWCLK_1_GAIN 'h138 +`define ADDR_POS_CALC_ADC_CH2_SWCLK_1_GAIN_DATA 'h138 `define POS_CALC_ADC_CH2_SWCLK_1_GAIN_DATA_OFFSET 0 `define POS_CALC_ADC_CH2_SWCLK_1_GAIN_DATA 'hffffffff `define ADDR_POS_CALC_ADC_CH3_SWCLK_1_GAIN 'h13c +`define ADDR_POS_CALC_ADC_CH3_SWCLK_1_GAIN_DATA 'h13c `define POS_CALC_ADC_CH3_SWCLK_1_GAIN_DATA_OFFSET 0 `define POS_CALC_ADC_CH3_SWCLK_1_GAIN_DATA 'hffffffff `define ADDR_POS_CALC_ADC_CH0_SWCLK_0_OFFSET 'h140 +`define ADDR_POS_CALC_ADC_CH0_SWCLK_0_OFFSET_DATA 'h140 `define POS_CALC_ADC_CH0_SWCLK_0_OFFSET_DATA_OFFSET 0 `define POS_CALC_ADC_CH0_SWCLK_0_OFFSET_DATA 'hffff `define ADDR_POS_CALC_ADC_CH1_SWCLK_0_OFFSET 'h144 +`define ADDR_POS_CALC_ADC_CH1_SWCLK_0_OFFSET_DATA 'h144 `define POS_CALC_ADC_CH1_SWCLK_0_OFFSET_DATA_OFFSET 0 `define POS_CALC_ADC_CH1_SWCLK_0_OFFSET_DATA 'hffff `define ADDR_POS_CALC_ADC_CH2_SWCLK_0_OFFSET 'h148 +`define ADDR_POS_CALC_ADC_CH2_SWCLK_0_OFFSET_DATA 'h148 `define POS_CALC_ADC_CH2_SWCLK_0_OFFSET_DATA_OFFSET 0 `define POS_CALC_ADC_CH2_SWCLK_0_OFFSET_DATA 'hffff `define ADDR_POS_CALC_ADC_CH3_SWCLK_0_OFFSET 'h14c +`define ADDR_POS_CALC_ADC_CH3_SWCLK_0_OFFSET_DATA 'h14c `define POS_CALC_ADC_CH3_SWCLK_0_OFFSET_DATA_OFFSET 0 `define POS_CALC_ADC_CH3_SWCLK_0_OFFSET_DATA 'hffff `define ADDR_POS_CALC_ADC_CH0_SWCLK_1_OFFSET 'h150 +`define ADDR_POS_CALC_ADC_CH0_SWCLK_1_OFFSET_DATA 'h150 `define POS_CALC_ADC_CH0_SWCLK_1_OFFSET_DATA_OFFSET 0 `define POS_CALC_ADC_CH0_SWCLK_1_OFFSET_DATA 'hffff `define ADDR_POS_CALC_ADC_CH1_SWCLK_1_OFFSET 'h154 +`define ADDR_POS_CALC_ADC_CH1_SWCLK_1_OFFSET_DATA 'h154 `define POS_CALC_ADC_CH1_SWCLK_1_OFFSET_DATA_OFFSET 0 `define POS_CALC_ADC_CH1_SWCLK_1_OFFSET_DATA 'hffff `define ADDR_POS_CALC_ADC_CH2_SWCLK_1_OFFSET 'h158 +`define ADDR_POS_CALC_ADC_CH2_SWCLK_1_OFFSET_DATA 'h158 `define POS_CALC_ADC_CH2_SWCLK_1_OFFSET_DATA_OFFSET 0 `define POS_CALC_ADC_CH2_SWCLK_1_OFFSET_DATA 'hffff `define ADDR_POS_CALC_ADC_CH3_SWCLK_1_OFFSET 'h15c +`define ADDR_POS_CALC_ADC_CH3_SWCLK_1_OFFSET_DATA 'h15c `define POS_CALC_ADC_CH3_SWCLK_1_OFFSET_DATA_OFFSET 0 `define POS_CALC_ADC_CH3_SWCLK_1_OFFSET_DATA 'hffff