diff --git a/aps_.ip_user_files/mem_init_files/mem-init.txt b/aps_.ip_user_files/mem_init_files/mem-init.txt
new file mode 100644
index 0000000..7b9f56b
--- /dev/null
+++ b/aps_.ip_user_files/mem_init_files/mem-init.txt
@@ -0,0 +1,10 @@
+00000001
+00000004
+00000005
+00000008
+0000000b
+00000003
+00000001
+00000004
+00000002
+00000007
\ No newline at end of file
diff --git a/aps_.ip_user_files/mem_init_files/prog.txt b/aps_.ip_user_files/mem_init_files/prog.txt
index 078d41d..34b1f70 100644
--- a/aps_.ip_user_files/mem_init_files/prog.txt
+++ b/aps_.ip_user_files/mem_init_files/prog.txt
@@ -1,5 +1,4 @@
-10000417
-00040413
+00000413
00000493
00000913
00a00a13
diff --git a/aps_.srcs/sim_1/new/top_tb.sv b/aps_.srcs/sim_1/new/top_tb.sv
index e196710..6df690b 100644
--- a/aps_.srcs/sim_1/new/top_tb.sv
+++ b/aps_.srcs/sim_1/new/top_tb.sv
@@ -17,7 +17,7 @@ cpu_top dut(.CLK100MHZ(CLK), .rst(rst));
initial begin
rst <= 1;
- #10;
+ #20;
rst <= 0;
end
diff --git a/aps_.srcs/sources_1/new/cpu_top.sv b/aps_.srcs/sources_1/new/cpu_top.sv
index f1358fc..61adf58 100644
--- a/aps_.srcs/sources_1/new/cpu_top.sv
+++ b/aps_.srcs/sources_1/new/cpu_top.sv
@@ -53,19 +53,21 @@ logic [`WORD_LEN-1:0] imm_S;
assign imm_S = {{(`WORD_LEN - 12) {instruction[31]}}, instruction[`S_TYPE_IMM_11_5], instruction[`S_TYPE_IMM_4_0]};
logic [`WORD_LEN-1:0] imm_J;
-assign imm_J = {{(`WORD_LEN - 20) {instruction[31]}},
+assign imm_J = {{(`WORD_LEN - 21) {instruction[31]}},
instruction[`J_TYPE_IMM_20],
instruction[`J_TYPE_IMM_19_12],
instruction[`J_TYPE_IMM_11],
- instruction[`J_TYPE_IMM_10_1]
+ instruction[`J_TYPE_IMM_10_1],
+ 1'b0
};
logic [`WORD_LEN-1:0] imm_B;
-assign imm_B = {{(`WORD_LEN - 12) {instruction[31]}},
+assign imm_B = {{(`WORD_LEN - 13) {instruction[31]}},
instruction[`B_TYPE_IMM_12],
instruction[`B_TYPE_IMM_11],
instruction[`B_TYPE_IMM_10_5],
- instruction[`B_TYPE_IMM_4_1]
+ instruction[`B_TYPE_IMM_4_1],
+ 1'b0
};
// alu
diff --git a/aps_.srcs/sources_1/new/data_memory.sv b/aps_.srcs/sources_1/new/data_memory.sv
index b89ec86..38adc6b 100644
--- a/aps_.srcs/sources_1/new/data_memory.sv
+++ b/aps_.srcs/sources_1/new/data_memory.sv
@@ -12,6 +12,8 @@ module data_memory#(
);
logic [WIDTH-1:0] RAM [0:DEPTH-1];
+
+initial $readmemh("mem-init.txt", RAM, 0, DEPTH-1);
assign RD = RAM[A[9:2]];
diff --git a/aps_.srcs/sources_1/new/defines_riscv.v b/aps_.srcs/sources_1/new/defines_riscv.v
index 267fd32..fef3929 100644
--- a/aps_.srcs/sources_1/new/defines_riscv.v
+++ b/aps_.srcs/sources_1/new/defines_riscv.v
@@ -201,7 +201,6 @@
//I-type.4
`define SYSTEM_OPCODE 5'b11_100
-//?
`define MISC_MEM_OPCODE 5'b00_011
//----------------------------//
diff --git a/aps_.srcs/sources_1/new/mem-init.txt b/aps_.srcs/sources_1/new/mem-init.txt
new file mode 100644
index 0000000..7b9f56b
--- /dev/null
+++ b/aps_.srcs/sources_1/new/mem-init.txt
@@ -0,0 +1,10 @@
+00000001
+00000004
+00000005
+00000008
+0000000b
+00000003
+00000001
+00000004
+00000002
+00000007
\ No newline at end of file
diff --git a/aps_.srcs/sources_1/new/prog.txt b/aps_.srcs/sources_1/new/prog.txt
index 078d41d..34b1f70 100644
--- a/aps_.srcs/sources_1/new/prog.txt
+++ b/aps_.srcs/sources_1/new/prog.txt
@@ -1,5 +1,4 @@
-10000417
-00040413
+00000413
00000493
00000913
00a00a13
diff --git a/aps_.xpr b/aps_.xpr
index 43647f4..0023a68 100644
--- a/aps_.xpr
+++ b/aps_.xpr
@@ -32,7 +32,7 @@
-
+
@@ -123,6 +123,12 @@
+
+
+
+
+
+
@@ -222,7 +228,9 @@
-
+
+ Vivado Synthesis Defaults
+
@@ -231,7 +239,9 @@
-
+
+ Default settings for Implementation.
+