From 4fb050ca203dd72c3daaf97a565cc8deae68674c Mon Sep 17 00:00:00 2001 From: Alex Parfenov <90794457+jstalex@users.noreply.github.com> Date: Wed, 2 Nov 2022 15:27:42 +0300 Subject: [PATCH] Initial commit --- .gitattributes | 2 + .gitignore | 52 + LICENSE | 21 + README.md | 2 + aps_.cache/wt/gui_handlers.wdf | 122 + aps_.cache/wt/java_command_handlers.wdf | 38 + aps_.cache/wt/project.wpc | 4 + aps_.cache/wt/synthesis.wdf | 39 + aps_.cache/wt/synthesis_details.wdf | 3 + aps_.cache/wt/webtalk_pa.xml | 186 ++ aps_.cache/wt/xsim.wdf | 4 + aps_.hw/aps_.lpr | 8 + aps_.hw/hw_1/hw.xml | 17 + aps_.ip_user_files/README.txt | 1 + aps_.ip_user_files/mem_init_files/prog.txt | 4 + aps_.runs/.jobs/vrs_config_1.xml | 8 + aps_.runs/synth_1/.Vivado_Synthesis.queue.rst | 0 aps_.runs/synth_1/.Xil/top_propImpl.xdc | 111 + aps_.runs/synth_1/.vivado.begin.rst | 5 + aps_.runs/synth_1/.vivado.end.rst | 0 aps_.runs/synth_1/ISEWrap.js | 270 ++ aps_.runs/synth_1/ISEWrap.sh | 67 + aps_.runs/synth_1/__synthesis_is_complete__ | 0 aps_.runs/synth_1/gen_run.xml | 109 + aps_.runs/synth_1/htr.txt | 9 + aps_.runs/synth_1/prog.txt | 9 + aps_.runs/synth_1/project.wdf | 31 + aps_.runs/synth_1/rundef.js | 36 + aps_.runs/synth_1/runme.bat | 10 + aps_.runs/synth_1/runme.log | 509 ++++ aps_.runs/synth_1/runme.sh | 43 + aps_.runs/synth_1/top.dcp | Bin 0 -> 40299 bytes aps_.runs/synth_1/top.tcl | 64 + aps_.runs/synth_1/top.vds | 510 ++++ aps_.runs/synth_1/top_utilization_synth.pb | Bin 0 -> 242 bytes aps_.runs/synth_1/top_utilization_synth.rpt | 182 ++ aps_.runs/synth_1/vivado.jou | 12 + aps_.runs/synth_1/vivado.pb | Bin 0 -> 61465 bytes aps_.sim/sim_1/behav/xsim/alu_riscv_tb.tcl | 11 + .../sim_1/behav/xsim/alu_riscv_tb_behav.wdb | Bin 0 -> 10128 bytes .../sim_1/behav/xsim/alu_riscv_tb_vlog.prj | 10 + aps_.sim/sim_1/behav/xsim/compile.bat | 25 + aps_.sim/sim_1/behav/xsim/compile.log | 0 aps_.sim/sim_1/behav/xsim/elaborate.bat | 24 + aps_.sim/sim_1/behav/xsim/elaborate.log | 8 + aps_.sim/sim_1/behav/xsim/glbl.v | 71 + aps_.sim/sim_1/behav/xsim/im_tb.tcl | 11 + aps_.sim/sim_1/behav/xsim/im_tb_behav.wdb | Bin 0 -> 8225 bytes aps_.sim/sim_1/behav/xsim/im_tb_vlog.prj | 18 + aps_.sim/sim_1/behav/xsim/prog.txt | 4 + aps_.sim/sim_1/behav/xsim/rf_tb.tcl | 11 + aps_.sim/sim_1/behav/xsim/rf_tb_behav.wdb | Bin 0 -> 14202 bytes aps_.sim/sim_1/behav/xsim/rf_tb_vlog.prj | 10 + aps_.sim/sim_1/behav/xsim/simulate.bat | 24 + aps_.sim/sim_1/behav/xsim/simulate.log | 2 + aps_.sim/sim_1/behav/xsim/top_tb.tcl | 11 + aps_.sim/sim_1/behav/xsim/top_tb_behav.wdb | Bin 0 -> 14992 bytes aps_.sim/sim_1/behav/xsim/top_tb_vlog.prj | 16 + aps_.sim/sim_1/behav/xsim/webtalk.jou | 12 + aps_.sim/sim_1/behav/xsim/webtalk.log | 15 + .../sim_1/behav/xsim/webtalk_15744.backup.jou | 12 + .../sim_1/behav/xsim/webtalk_15744.backup.log | 13 + .../sim_1/behav/xsim/webtalk_19012.backup.jou | 12 + .../sim_1/behav/xsim/webtalk_19012.backup.log | 13 + .../sim_1/behav/xsim/webtalk_7268.backup.jou | 12 + .../sim_1/behav/xsim/webtalk_7268.backup.log | 13 + .../sim_1/behav/xsim/webtalk_9284.backup.jou | 12 + .../sim_1/behav/xsim/webtalk_9284.backup.log | 15 + .../sim_1/behav/xsim/webtalk_9300.backup.jou | 12 + .../sim_1/behav/xsim/webtalk_9300.backup.log | 14 + aps_.sim/sim_1/behav/xsim/xelab.pb | Bin 0 -> 1246 bytes .../xsim.dir/im_tb_behav/Compile_Options.txt | 1 + .../im_tb_behav/TempBreakPointFile.txt | 1 + .../xsim/xsim.dir/im_tb_behav/obj/xsim_1.c | 108 + .../im_tb_behav/webtalk/.xsim_webtallk.info | 5 + .../webtalk/usage_statistics_ext_xsim.html | 53 + .../webtalk/usage_statistics_ext_xsim.wdm | 38 + .../webtalk/usage_statistics_ext_xsim.xml | 44 + .../im_tb_behav/webtalk/xsim_webtalk.tcl | 44 + .../behav/xsim/xsim.dir/im_tb_behav/xsim.dbg | Bin 0 -> 5864 bytes .../behav/xsim/xsim.dir/im_tb_behav/xsim.mem | Bin 0 -> 2964 bytes .../xsim/xsim.dir/im_tb_behav/xsim.reloc | Bin 0 -> 1020 bytes .../behav/xsim/xsim.dir/im_tb_behav/xsim.rlx | 12 + .../behav/xsim/xsim.dir/im_tb_behav/xsim.rtti | Bin 0 -> 431 bytes .../xsim/xsim.dir/im_tb_behav/xsim.svtype | Bin 0 -> 120 bytes .../behav/xsim/xsim.dir/im_tb_behav/xsim.type | Bin 0 -> 24 bytes .../behav/xsim/xsim.dir/im_tb_behav/xsim.xdbg | Bin 0 -> 1944 bytes .../xsim.dir/im_tb_behav/xsimSettings.ini | 50 + .../xsim/xsim.dir/im_tb_behav/xsimcrash.log | 0 .../xsim/xsim.dir/im_tb_behav/xsimkernel.log | 7 + .../xsim.dir/top_tb_behav/Compile_Options.txt | 1 + .../top_tb_behav/TempBreakPointFile.txt | 1 + .../xsim/xsim.dir/top_tb_behav/obj/xsim_1.c | 132 + .../top_tb_behav/webtalk/.xsim_webtallk.info | 5 + .../webtalk/usage_statistics_ext_xsim.html | 53 + .../webtalk/usage_statistics_ext_xsim.xml | 44 + .../behav/xsim/xsim.dir/top_tb_behav/xsim.dbg | Bin 0 -> 10392 bytes .../behav/xsim/xsim.dir/top_tb_behav/xsim.mem | Bin 0 -> 4710 bytes .../xsim/xsim.dir/top_tb_behav/xsim.reloc | Bin 0 -> 2202 bytes .../behav/xsim/xsim.dir/top_tb_behav/xsim.rlx | 12 + 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vivado_pid22044.str | 2583 +++++++++++++++++ 141 files changed, 7736 insertions(+) create mode 100644 .gitattributes create mode 100644 .gitignore create mode 100644 LICENSE create mode 100644 README.md create mode 100644 aps_.cache/wt/gui_handlers.wdf create mode 100644 aps_.cache/wt/java_command_handlers.wdf create mode 100644 aps_.cache/wt/project.wpc create mode 100644 aps_.cache/wt/synthesis.wdf create mode 100644 aps_.cache/wt/synthesis_details.wdf create mode 100644 aps_.cache/wt/webtalk_pa.xml create mode 100644 aps_.cache/wt/xsim.wdf create mode 100644 aps_.hw/aps_.lpr create mode 100644 aps_.hw/hw_1/hw.xml create mode 100644 aps_.ip_user_files/README.txt create mode 100644 aps_.ip_user_files/mem_init_files/prog.txt create mode 100644 aps_.runs/.jobs/vrs_config_1.xml create mode 100644 aps_.runs/synth_1/.Vivado_Synthesis.queue.rst create mode 100644 aps_.runs/synth_1/.Xil/top_propImpl.xdc create mode 100644 aps_.runs/synth_1/.vivado.begin.rst create mode 100644 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aps_.srcs/sources_1/new/rf_riscv.sv create mode 100644 aps_.xpr create mode 100644 desktop.ini create mode 100644 top_tb_behav.wcfg create mode 100644 vivado.jou create mode 100644 vivado.log create mode 100644 vivado_pid22044.str diff --git a/.gitattributes b/.gitattributes new file mode 100644 index 0000000..dfe0770 --- /dev/null +++ b/.gitattributes @@ -0,0 +1,2 @@ +# Auto detect text files and perform LF normalization +* text=auto diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..c6127b3 --- /dev/null +++ b/.gitignore @@ -0,0 +1,52 @@ +# Prerequisites +*.d + +# Object files +*.o +*.ko +*.obj +*.elf + +# Linker output +*.ilk +*.map +*.exp + +# Precompiled Headers +*.gch +*.pch + +# Libraries +*.lib +*.a +*.la +*.lo + +# Shared objects (inc. Windows DLLs) +*.dll +*.so +*.so.* +*.dylib + +# Executables +*.exe +*.out +*.app +*.i*86 +*.x86_64 +*.hex + +# Debug files +*.dSYM/ +*.su +*.idb +*.pdb + +# Kernel Module Compile Results +*.mod* +*.cmd +.tmp_versions/ +modules.order +Module.symvers +Mkfile.old +dkms.conf diff --git a/LICENSE b/LICENSE new file mode 100644 index 0000000..9244f61 --- /dev/null +++ b/LICENSE @@ -0,0 +1,21 @@ +MIT License + +Copyright (c) 2022 Alex Parfenov + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in all +copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +SOFTWARE. diff --git a/README.md b/README.md new file mode 100644 index 0000000..9fa459e --- /dev/null +++ b/README.md @@ -0,0 +1,2 @@ +# RISC-V_CPU + diff --git a/aps_.cache/wt/gui_handlers.wdf b/aps_.cache/wt/gui_handlers.wdf new file mode 100644 index 0000000..515adb4 --- /dev/null +++ b/aps_.cache/wt/gui_handlers.wdf @@ -0,0 +1,122 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:61627374726163747361766561736469616c6f675f6e616d65:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:61646473726377697a6172645f737065636966795f68646c5f6e65746c6973745f626c6f636b5f64657369676e:33:00:00 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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + diff --git a/aps_.cache/wt/xsim.wdf b/aps_.cache/wt/xsim.wdf new file mode 100644 index 0000000..50afb2c --- /dev/null +++ b/aps_.cache/wt/xsim.wdf @@ -0,0 +1,4 @@ +version:1 +7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f6d6f6465:64656661756c743a3a6265686176696f72616c:00:00 +7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f74797065:64656661756c743a3a:00:00 +eof:241934075 diff --git a/aps_.hw/aps_.lpr b/aps_.hw/aps_.lpr new file mode 100644 index 0000000..ea70b5a --- /dev/null +++ b/aps_.hw/aps_.lpr @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/aps_.hw/hw_1/hw.xml b/aps_.hw/hw_1/hw.xml new file mode 100644 index 0000000..b472ba4 --- /dev/null +++ b/aps_.hw/hw_1/hw.xml @@ -0,0 +1,17 @@ + + + + + + + + + + + + + + + + + diff --git a/aps_.ip_user_files/README.txt b/aps_.ip_user_files/README.txt new file mode 100644 index 0000000..023052c --- /dev/null +++ b/aps_.ip_user_files/README.txt @@ -0,0 +1 @@ +The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended. diff --git a/aps_.ip_user_files/mem_init_files/prog.txt b/aps_.ip_user_files/mem_init_files/prog.txt new file mode 100644 index 0000000..80ff991 --- /dev/null +++ b/aps_.ip_user_files/mem_init_files/prog.txt @@ -0,0 +1,4 @@ +0_0_01_00000_00000_00000_00000000_00001 +0_0_10_00000_00000_00000_00000101_00010 +0_0_11_00000_00001_00010_00000000_00011 +1_0_00_00000_00011_00000_00000000_00000 diff --git a/aps_.runs/.jobs/vrs_config_1.xml b/aps_.runs/.jobs/vrs_config_1.xml new file mode 100644 index 0000000..4ed891f --- /dev/null +++ b/aps_.runs/.jobs/vrs_config_1.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/aps_.runs/synth_1/.Vivado_Synthesis.queue.rst b/aps_.runs/synth_1/.Vivado_Synthesis.queue.rst new file mode 100644 index 0000000..e69de29 diff --git a/aps_.runs/synth_1/.Xil/top_propImpl.xdc b/aps_.runs/synth_1/.Xil/top_propImpl.xdc new file mode 100644 index 0000000..a12dc30 --- /dev/null +++ b/aps_.runs/synth_1/.Xil/top_propImpl.xdc @@ -0,0 +1,111 @@ +set_property SRC_FILE_INFO {cfile:C:/Users/Alex/APS/aps_/aps_.srcs/constrs_1/imports/apsLabs/Nexys-A7-100T-Master.xdc rfile:../../../aps_.srcs/constrs_1/imports/apsLabs/Nexys-A7-100T-Master.xdc id:1} [current_design] +set_property src_info {type:XDC file:1 line:7 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { CLK100MHZ }]; #IO_L12P_T1_MRCC_35 Sch=clk100mhz +set_property src_info {type:XDC file:1 line:12 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { SW[0] }]; #IO_L24N_T3_RS0_15 Sch=sw[0] +set_property src_info {type:XDC file:1 line:13 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { SW[1] }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1] +set_property src_info {type:XDC file:1 line:14 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { SW[2] }]; #IO_L6N_T0_D08_VREF_14 Sch=sw[2] +set_property src_info {type:XDC file:1 line:15 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { SW[3] }]; #IO_L13N_T2_MRCC_14 Sch=sw[3] +set_property src_info {type:XDC file:1 line:16 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { SW[4] }]; #IO_L12N_T1_MRCC_14 Sch=sw[4] +set_property src_info {type:XDC file:1 line:17 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { SW[5] }]; #IO_L7N_T1_D10_14 Sch=sw[5] +set_property src_info {type:XDC file:1 line:18 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { SW[6] }]; #IO_L17N_T2_A13_D29_14 Sch=sw[6] +set_property src_info {type:XDC file:1 line:19 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { SW[7] }]; #IO_L5N_T0_D07_14 Sch=sw[7] +set_property src_info {type:XDC file:1 line:20 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN T8 IOSTANDARD LVCMOS18 } [get_ports { SW[8] }]; #IO_L24N_T3_34 Sch=sw[8] +set_property src_info {type:XDC file:1 line:21 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS18 } [get_ports { SW[9] }]; #IO_25_34 Sch=sw[9] +set_property src_info {type:XDC file:1 line:22 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { SW[10] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=sw[10] +set_property src_info {type:XDC file:1 line:23 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { SW[11] }]; #IO_L23P_T3_A03_D19_14 Sch=sw[11] +set_property src_info {type:XDC file:1 line:24 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN H6 IOSTANDARD LVCMOS33 } [get_ports { SW[12] }]; #IO_L24P_T3_35 Sch=sw[12] +set_property src_info {type:XDC file:1 line:25 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { SW[13] }]; #IO_L20P_T3_A08_D24_14 Sch=sw[13] +set_property src_info {type:XDC file:1 line:26 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports { SW[14] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=sw[14] +set_property src_info {type:XDC file:1 line:27 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { SW[15] }]; #IO_L21P_T3_DQS_14 Sch=sw[15] +set_property src_info {type:XDC file:1 line:30 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { LED[0] }]; #IO_L18P_T2_A24_15 Sch=led[0] +set_property src_info {type:XDC file:1 line:31 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { LED[1] }]; #IO_L24P_T3_RS1_15 Sch=led[1] +set_property src_info {type:XDC file:1 line:32 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { LED[2] }]; #IO_L17N_T2_A25_15 Sch=led[2] +set_property src_info {type:XDC file:1 line:33 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { LED[3] }]; #IO_L8P_T1_D11_14 Sch=led[3] +set_property src_info {type:XDC file:1 line:34 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { LED[4] }]; #IO_L7P_T1_D09_14 Sch=led[4] +set_property src_info {type:XDC file:1 line:35 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { LED[5] }]; #IO_L18N_T2_A11_D27_14 Sch=led[5] +set_property src_info {type:XDC file:1 line:36 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { LED[6] }]; #IO_L17P_T2_A14_D30_14 Sch=led[6] +set_property src_info {type:XDC file:1 line:37 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { LED[7] }]; #IO_L18P_T2_A12_D28_14 Sch=led[7] +set_property src_info {type:XDC file:1 line:38 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { LED[8] }]; #IO_L16N_T2_A15_D31_14 Sch=led[8] +set_property src_info {type:XDC file:1 line:39 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { LED[9] }]; #IO_L14N_T2_SRCC_14 Sch=led[9] +set_property src_info {type:XDC file:1 line:40 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { LED[10] }]; #IO_L22P_T3_A05_D21_14 Sch=led[10] +set_property src_info {type:XDC file:1 line:41 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { LED[11] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=led[11] +set_property src_info {type:XDC file:1 line:42 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { LED[12] }]; #IO_L16P_T2_CSI_B_14 Sch=led[12] +set_property src_info {type:XDC file:1 line:43 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { LED[13] }]; #IO_L22N_T3_A04_D20_14 Sch=led[13] +set_property src_info {type:XDC file:1 line:44 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { LED[14] }]; #IO_L20N_T3_A07_D23_14 Sch=led[14] +set_property src_info {type:XDC file:1 line:45 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { LED[15] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=led[15] +set_property src_info {type:XDC file:1 line:48 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN R12 IOSTANDARD LVCMOS33 } [get_ports { LED16_B }]; #IO_L5P_T0_D06_14 Sch=led16_b +set_property src_info {type:XDC file:1 line:49 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN M16 IOSTANDARD LVCMOS33 } [get_ports { LED16_G }]; #IO_L10P_T1_D14_14 Sch=led16_g +set_property src_info {type:XDC file:1 line:50 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { LED16_R }]; #IO_L11P_T1_SRCC_14 Sch=led16_r +set_property src_info {type:XDC file:1 line:51 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { LED17_B }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=led17_b +set_property src_info {type:XDC file:1 line:52 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN R11 IOSTANDARD LVCMOS33 } [get_ports { LED17_G }]; #IO_0_14 Sch=led17_g +set_property src_info {type:XDC file:1 line:53 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { LED17_R }]; #IO_L11N_T1_SRCC_14 Sch=led17_r +set_property src_info {type:XDC file:1 line:56 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { CA }]; #IO_L24N_T3_A00_D16_14 Sch=ca +set_property src_info {type:XDC file:1 line:57 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { CB }]; #IO_25_14 Sch=cb +set_property src_info {type:XDC file:1 line:58 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { CC }]; #IO_25_15 Sch=cc +set_property src_info {type:XDC file:1 line:59 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { CD }]; #IO_L17P_T2_A26_15 Sch=cd +set_property src_info {type:XDC file:1 line:60 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { CE }]; #IO_L13P_T2_MRCC_14 Sch=ce +set_property src_info {type:XDC file:1 line:61 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { CF }]; #IO_L19P_T3_A10_D26_14 Sch=cf +set_property src_info {type:XDC file:1 line:62 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { CG }]; #IO_L4P_T0_D04_14 Sch=cg +set_property src_info {type:XDC file:1 line:63 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { DP }]; #IO_L19N_T3_A21_VREF_15 Sch=dp +set_property src_info {type:XDC file:1 line:64 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { AN[0] }]; #IO_L23P_T3_FOE_B_15 Sch=an[0] +set_property src_info {type:XDC file:1 line:65 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { AN[1] }]; #IO_L23N_T3_FWE_B_15 Sch=an[1] +set_property src_info {type:XDC file:1 line:66 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { AN[2] }]; #IO_L24P_T3_A01_D17_14 Sch=an[2] +set_property src_info {type:XDC file:1 line:67 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { AN[3] }]; #IO_L19P_T3_A22_15 Sch=an[3] +set_property src_info {type:XDC file:1 line:68 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { AN[4] }]; #IO_L8N_T1_D12_14 Sch=an[4] +set_property src_info {type:XDC file:1 line:69 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { AN[5] }]; #IO_L14P_T2_SRCC_14 Sch=an[5] +set_property src_info {type:XDC file:1 line:70 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { AN[6] }]; #IO_L23P_T3_35 Sch=an[6] +set_property src_info {type:XDC file:1 line:71 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { AN[7] }]; #IO_L23N_T3_A02_D18_14 Sch=an[7] diff --git a/aps_.runs/synth_1/.vivado.begin.rst b/aps_.runs/synth_1/.vivado.begin.rst new file mode 100644 index 0000000..96b8049 --- /dev/null +++ b/aps_.runs/synth_1/.vivado.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/aps_.runs/synth_1/.vivado.end.rst b/aps_.runs/synth_1/.vivado.end.rst new file mode 100644 index 0000000..e69de29 diff --git a/aps_.runs/synth_1/ISEWrap.js b/aps_.runs/synth_1/ISEWrap.js new file mode 100644 index 0000000..97a2ecb --- /dev/null +++ b/aps_.runs/synth_1/ISEWrap.js @@ -0,0 +1,270 @@ +// +// Vivado(TM) +// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 +// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved. +// + +// GLOBAL VARIABLES +var ISEShell = new ActiveXObject( "WScript.Shell" ); +var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); +var ISERunDir = ""; +var ISELogFile = "runme.log"; +var ISELogFileStr = null; +var ISELogEcho = true; +var ISEOldVersionWSH = false; + + + +// BOOTSTRAP +ISEInit(); + + + +// +// ISE FUNCTIONS +// +function ISEInit() { + + // 1. RUN DIR setup + var ISEScrFP = WScript.ScriptFullName; + var ISEScrN = WScript.ScriptName; + ISERunDir = + ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); + + // 2. LOG file setup + ISELogFileStr = ISEOpenFile( ISELogFile ); + + // 3. LOG echo? + var ISEScriptArgs = WScript.Arguments; + for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; + ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); + ISELogFileStr = ISEOpenFile( ISELogFile ); + + } else { // WSH 5.6 + + // LAUNCH! + ISEShell.CurrentDirectory = ISERunDir; + + // Redirect STDERR to STDOUT + ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; + var ISEProcess = ISEShell.Exec( ISECmdLine ); + + // BEGIN file creation + var wbemFlagReturnImmediately = 0x10; + var wbemFlagForwardOnly = 0x20; + var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2"); + var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly); + var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly); + var NOC = 0; + var NOLP = 0; + var TPM = 0; + + var cpuInfos = new Enumerator(processor); + for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) { + var cpuInfo = cpuInfos.item(); + NOC += cpuInfo.NumberOfCores; + NOLP += cpuInfo.NumberOfLogicalProcessors; + } + var csInfos = new Enumerator(computerSystem); + for(;!csInfos.atEnd(); csInfos.moveNext()) { + var csInfo = csInfos.item(); + TPM += csInfo.TotalPhysicalMemory; + } + + var ISEHOSTCORE = NOLP + var ISEMEMTOTAL = TPM + + var ISENetwork = WScript.CreateObject( "WScript.Network" ); + var ISEHost = ISENetwork.ComputerName; + var ISEUser = ISENetwork.UserName; + var ISEPid = ISEProcess.ProcessID; + var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.Close(); + + var ISEOutStr = ISEProcess.StdOut; + var ISEErrStr = ISEProcess.StdErr; + + // WAIT for ISEStep to finish + while ( ISEProcess.Status == 0 ) { + + // dump stdout then stderr - feels a little arbitrary + while ( !ISEOutStr.AtEndOfStream ) { + ISEStdOut( ISEOutStr.ReadLine() ); + } + + WScript.Sleep( 100 ); + } + + ISEExitCode = ISEProcess.ExitCode; + } + + ISELogFileStr.Close(); + + // END/ERROR file creation + if ( ISEExitCode != 0 ) { + ISETouchFile( ISEStep, "error" ); + + } else { + ISETouchFile( ISEStep, "end" ); + } + + return ISEExitCode; +} + + +// +// UTILITIES +// +function ISEStdOut( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdOut.WriteLine( ISELine ); + } +} + +function ISEStdErr( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdErr.WriteLine( ISELine ); + } +} + +function ISETouchFile( ISERoot, ISEStatus ) { + + var ISETFile = + ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); + ISETFile.Close(); +} + +function ISEOpenFile( ISEFilename ) { + + // This function has been updated to deal with a problem seen in CR #870871. + // In that case the user runs a script that runs impl_1, and then turns around + // and runs impl_1 -to_step write_bitstream. That second run takes place in + // the same directory, which means we may hit some of the same files, and in + // particular, we will open the runme.log file. Even though this script closes + // the file (now), we see cases where a subsequent attempt to open the file + // fails. Perhaps the OS is slow to release the lock, or the disk comes into + // play? In any case, we try to work around this by first waiting if the file + // is already there for an arbitrary 5 seconds. Then we use a try-catch block + // and try to open the file 10 times with a one second delay after each attempt. + // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. + // If there is an unrecognized exception when trying to open the file, we output + // an error message and write details to an exception.log file. + var ISEFullPath = ISERunDir + "/" + ISEFilename; + if (ISEFileSys.FileExists(ISEFullPath)) { + // File is already there. This could be a problem. Wait in case it is still in use. + WScript.Sleep(5000); + } + var i; + for (i = 0; i < 10; ++i) { + try { + return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); + } catch (exception) { + var error_code = exception.number & 0xFFFF; // The other bits are a facility code. + if (error_code == 52) { // 52 is bad file name or number. + // Wait a second and try again. + WScript.Sleep(1000); + continue; + } else { + WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + var exceptionFilePath = ISERunDir + "/exception.log"; + if (!ISEFileSys.FileExists(exceptionFilePath)) { + WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); + var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); + exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + exceptionFile.WriteLine("\tException name: " + exception.name); + exceptionFile.WriteLine("\tException error code: " + error_code); + exceptionFile.WriteLine("\tException message: " + exception.message); + exceptionFile.Close(); + } + throw exception; + } + } + } + // If we reached this point, we failed to open the file after 10 attempts. + // We need to error out. + WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); + WScript.Quit(1); +} diff --git a/aps_.runs/synth_1/ISEWrap.sh b/aps_.runs/synth_1/ISEWrap.sh new file mode 100644 index 0000000..f679f2e --- /dev/null +++ b/aps_.runs/synth_1/ISEWrap.sh @@ -0,0 +1,67 @@ +#!/bin/sh + +# +# Vivado(TM) +# ISEWrap.sh: Vivado Runs Script for UNIX +# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. +# + +HD_LOG=$1 +shift + +# CHECK for a STOP FILE +if [ -f .stop.rst ] +then +echo "" >> $HD_LOG +echo "*** Halting run - EA reset detected ***" >> $HD_LOG +echo "" >> $HD_LOG +exit 1 +fi + +ISE_STEP=$1 +shift + +# WRITE STEP HEADER to LOG +echo "" >> $HD_LOG +echo "*** Running $ISE_STEP" >> $HD_LOG +echo " with args $@" >> $HD_LOG +echo "" >> $HD_LOG + +# LAUNCH! +$ISE_STEP "$@" >> $HD_LOG 2>&1 & + +# BEGIN file creation +ISE_PID=$! +if [ X != X$HOSTNAME ] +then +ISE_HOST=$HOSTNAME #bash +else +ISE_HOST=$HOST #csh +fi +ISE_USER=$USER + +ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l) +ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo) + +ISE_BEGINFILE=.$ISE_STEP.begin.rst +/bin/touch $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE + +# WAIT for ISEStep to finish +wait $ISE_PID + +# END/ERROR file creation +RETVAL=$? +if [ $RETVAL -eq 0 ] +then + /bin/touch .$ISE_STEP.end.rst +else + /bin/touch .$ISE_STEP.error.rst +fi + +exit $RETVAL + diff --git a/aps_.runs/synth_1/__synthesis_is_complete__ b/aps_.runs/synth_1/__synthesis_is_complete__ new file mode 100644 index 0000000..e69de29 diff --git a/aps_.runs/synth_1/gen_run.xml b/aps_.runs/synth_1/gen_run.xml new file mode 100644 index 0000000..aa18cab --- /dev/null +++ b/aps_.runs/synth_1/gen_run.xml @@ -0,0 +1,109 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/aps_.runs/synth_1/htr.txt b/aps_.runs/synth_1/htr.txt new file mode 100644 index 0000000..9ceec8d --- /dev/null +++ b/aps_.runs/synth_1/htr.txt @@ -0,0 +1,9 @@ +REM +REM Vivado(TM) +REM htr.txt: a Vivado-generated description of how-to-repeat the +REM the basic steps of a run. Note that runme.bat/sh needs +REM to be invoked for Vivado to track run status. +REM Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +REM + +vivado -log top.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source top.tcl diff --git a/aps_.runs/synth_1/prog.txt b/aps_.runs/synth_1/prog.txt new file mode 100644 index 0000000..a93e42e --- /dev/null +++ b/aps_.runs/synth_1/prog.txt @@ -0,0 +1,9 @@ +0_0_10_00000_00000_00000_00001101_00001 +0_0_10_00000_00000_00000_00000000_00100 +0_0_01_00000_00000_00000_00000000_00010 +0_0_10_00000_00000_00000_00000001_00011 +0_1_00_10000_00010_00000_00000100_00000 +0_0_11_00000_00100_00001_00000000_00100 +0_0_11_01000_00010_00011_00000000_00010 +1_0_00_00000_00000_00000_11111101_00000 +1_0_00_00000_00100_00000_00000000_00000 \ No newline at end of file diff --git a/aps_.runs/synth_1/project.wdf b/aps_.runs/synth_1/project.wdf new file mode 100644 index 0000000..ea0420b --- /dev/null +++ b/aps_.runs/synth_1/project.wdf @@ -0,0 +1,31 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:38:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e7473796e74686573697372756e:73796e74685f31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e74696d706c72756e:696d706c5f31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f72655f636f6e7461696e6572:66616c7365:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73696d756c61746f725f6c616e6775616765:4d69786564:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f6c616e6775616765:566572696c6f67:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64656661756c745f6c696272617279:78696c5f64656661756c746c6962:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f73696d756c61746f72:5853696d:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f7873696d:3334:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f717565737461:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f696573:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f766373:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f72697669657261:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f61637469766568646c:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00 +5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3838666431336334323465323431613262316437323639643933393630383265:506172656e742050412070726f6a656374204944:00 +eof:2853720970 diff --git a/aps_.runs/synth_1/rundef.js b/aps_.runs/synth_1/rundef.js new file mode 100644 index 0000000..fb556dd --- /dev/null +++ b/aps_.runs/synth_1/rundef.js @@ -0,0 +1,36 @@ +// +// Vivado(TM) +// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// + +var WshShell = new ActiveXObject( "WScript.Shell" ); +var ProcEnv = WshShell.Environment( "Process" ); +var PathVal = ProcEnv("PATH"); +if ( PathVal.length == 0 ) { + PathVal = "C:/Xilinx/SDK/2019.1/bin;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado/2019.1/bin;"; +} else { + PathVal = "C:/Xilinx/SDK/2019.1/bin;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado/2019.1/bin;" + PathVal; +} + +ProcEnv("PATH") = PathVal; + +var RDScrFP = WScript.ScriptFullName; +var RDScrN = WScript.ScriptName; +var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); +var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; +eval( EAInclude(ISEJScriptLib) ); + + +ISEStep( "vivado", + "-log top.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source top.tcl" ); + + + +function EAInclude( EAInclFilename ) { + var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); + var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); + var EAIFContents = EAInclFile.ReadAll(); + EAInclFile.Close(); + return EAIFContents; +} diff --git a/aps_.runs/synth_1/runme.bat b/aps_.runs/synth_1/runme.bat new file mode 100644 index 0000000..1760626 --- /dev/null +++ b/aps_.runs/synth_1/runme.bat @@ -0,0 +1,10 @@ +@echo off + +rem Vivado (TM) +rem runme.bat: a Vivado-generated Script +rem Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. + + +set HD_SDIR=%~dp0 +cd /d "%HD_SDIR%" +cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git a/aps_.runs/synth_1/runme.log b/aps_.runs/synth_1/runme.log new file mode 100644 index 0000000..ff8f3fc --- /dev/null +++ b/aps_.runs/synth_1/runme.log @@ -0,0 +1,509 @@ + +*** Running vivado + with args -log top.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source top.tcl + + +****** Vivado v2019.1 (64-bit) + **** SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 + **** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 + ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. + +source top.tcl -notrace +Command: synth_design -top top -part xc7a100tcsg324-1 +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7a100t' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a100t' +INFO: [Device 21-403] Loading part xc7a100tcsg324-1 +INFO: Launching helper process for spawning children vivado processes +INFO: Helper process launched with PID 1876 +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 693.348 ; gain = 177.703 +--------------------------------------------------------------------------------- +INFO: [Synth 8-6157] synthesizing module 'top' [C:/Users/Alex/APS/aps_/aps_.srcs/sources_1/new/top.sv:4] + Parameter COUNTER_WIDTH bound to: 5 - type: integer +WARNING: [Synth 8-311] ignoring non-constant assignment in initial block [C:/Users/Alex/APS/aps_/aps_.srcs/sources_1/new/top.sv:16] +INFO: [Synth 8-6157] synthesizing module 'SE' [C:/Users/Alex/APS/aps_/aps_.srcs/sources_1/new/SE.sv:5] +INFO: [Synth 8-6155] done synthesizing module 'SE' (1#1) [C:/Users/Alex/APS/aps_/aps_.srcs/sources_1/new/SE.sv:5] +WARNING: [Synth 8-689] width (8) of port connection 'extended_constant' does not match port width (32) of module 'SE' [C:/Users/Alex/APS/aps_/aps_.srcs/sources_1/new/top.sv:29] +INFO: [Synth 8-6157] synthesizing module 'instruction_memory' [C:/Users/Alex/APS/aps_/aps_.srcs/sources_1/new/instruction_memory.sv:3] + Parameter WIDTH bound to: 32'sb00000000000000000000000000100000 + Parameter DEPTH bound to: 32'sb00000000000000000000000001000000 +INFO: [Synth 8-3876] $readmem data file 'prog.txt' is read successfully [C:/Users/Alex/APS/aps_/aps_.srcs/sources_1/new/instruction_memory.sv:15] +INFO: [Synth 8-6155] done synthesizing module 'instruction_memory' (2#1) [C:/Users/Alex/APS/aps_/aps_.srcs/sources_1/new/instruction_memory.sv:3] +INFO: [Synth 8-6157] synthesizing module 'rf_riscv' [C:/Users/Alex/APS/aps_/aps_.srcs/sources_1/new/rf_riscv.sv:3] +INFO: [Synth 8-6155] done synthesizing module 'rf_riscv' (3#1) [C:/Users/Alex/APS/aps_/aps_.srcs/sources_1/new/rf_riscv.sv:3] +INFO: [Synth 8-6157] synthesizing module 'alu_riscv' [C:/Users/Alex/APS/aps_/aps_.srcs/sources_1/new/alu_riscv.sv:4] +WARNING: [Synth 8-151] case item 5'b11000 is unreachable [C:/Users/Alex/APS/aps_/aps_.srcs/sources_1/new/alu_riscv.sv:24] +WARNING: [Synth 8-151] case item 5'b11001 is unreachable [C:/Users/Alex/APS/aps_/aps_.srcs/sources_1/new/alu_riscv.sv:25] +WARNING: [Synth 8-151] case item 5'b11100 is unreachable [C:/Users/Alex/APS/aps_/aps_.srcs/sources_1/new/alu_riscv.sv:26] +WARNING: [Synth 8-151] case item 5'b11101 is unreachable [C:/Users/Alex/APS/aps_/aps_.srcs/sources_1/new/alu_riscv.sv:27] +WARNING: [Synth 8-151] case item 5'b11110 is unreachable [C:/Users/Alex/APS/aps_/aps_.srcs/sources_1/new/alu_riscv.sv:28] +WARNING: [Synth 8-151] case item 5'b11111 is unreachable [C:/Users/Alex/APS/aps_/aps_.srcs/sources_1/new/alu_riscv.sv:29] +INFO: [Synth 8-6155] done synthesizing module 'alu_riscv' (4#1) [C:/Users/Alex/APS/aps_/aps_.srcs/sources_1/new/alu_riscv.sv:4] +WARNING: [Synth 8-689] width (5) of port connection 'ALUOp' does not match port width (4) of module 'alu_riscv' [C:/Users/Alex/APS/aps_/aps_.srcs/sources_1/new/top.sv:94] +WARNING: [Synth 8-3848] Net extended_switch in module/entity top does not have driver. [C:/Users/Alex/APS/aps_/aps_.srcs/sources_1/new/top.sv:15] +INFO: [Synth 8-6155] done synthesizing module 'top' (5#1) [C:/Users/Alex/APS/aps_/aps_.srcs/sources_1/new/top.sv:4] +WARNING: [Synth 8-3917] design top has port pcc[5] driven by constant 0 +WARNING: [Synth 8-3917] design top has port inc[31] driven by constant 0 +WARNING: [Synth 8-3917] design top has port inc[30] driven by constant 0 +WARNING: [Synth 8-3917] design top has port inc[29] driven by constant 0 +WARNING: [Synth 8-3917] design top has port inc[28] driven by constant 0 +WARNING: [Synth 8-3917] design top has port inc[27] driven by constant 0 +WARNING: [Synth 8-3917] design top has port inc[26] driven by constant 0 +WARNING: [Synth 8-3917] design top has port inc[25] driven by constant 0 +WARNING: [Synth 8-3917] design top has port inc[24] driven by constant 0 +WARNING: [Synth 8-3917] design top has port inc[23] driven by constant 0 +WARNING: [Synth 8-3917] design top has port inc[22] driven by constant 0 +WARNING: [Synth 8-3917] design top has port inc[21] driven by constant 0 +WARNING: [Synth 8-3917] design top has port inc[20] driven by constant 0 +WARNING: [Synth 8-3917] design top has port inc[19] driven by constant 0 +WARNING: [Synth 8-3917] design top has port inc[18] driven by constant 0 +WARNING: [Synth 8-3917] design top has port inc[17] driven by constant 0 +WARNING: [Synth 8-3917] design top has port inc[16] driven by constant 0 +WARNING: [Synth 8-3917] design top has port inc[15] driven by constant 0 +WARNING: [Synth 8-3917] design top has port inc[14] driven by constant 0 +WARNING: [Synth 8-3917] design top has port inc[13] driven by constant 0 +WARNING: [Synth 8-3917] design top has port inc[12] driven by constant 0 +WARNING: [Synth 8-3917] design top has port inc[11] driven by constant 0 +WARNING: [Synth 8-3917] design top has port inc[10] driven by constant 0 +WARNING: [Synth 8-3917] design top has port inc[9] driven by constant 0 +WARNING: [Synth 8-3331] design top has unconnected port SW[15] +WARNING: [Synth 8-3331] design top has unconnected port SW[14] +WARNING: [Synth 8-3331] design top has unconnected port SW[13] +WARNING: [Synth 8-3331] design top has unconnected port SW[12] +WARNING: [Synth 8-3331] design top has unconnected port SW[11] +WARNING: [Synth 8-3331] design top has unconnected port SW[10] +WARNING: [Synth 8-3331] design top has unconnected port SW[9] +WARNING: [Synth 8-3331] design top has unconnected port SW[8] +WARNING: [Synth 8-3331] design top has unconnected port SW[7] +WARNING: [Synth 8-3331] design top has unconnected port SW[6] +WARNING: [Synth 8-3331] design top has unconnected port SW[5] +WARNING: [Synth 8-3331] design top has unconnected port SW[4] +WARNING: [Synth 8-3331] design top has unconnected port SW[3] +WARNING: [Synth 8-3331] design top has unconnected port SW[2] +WARNING: [Synth 8-3331] design top has unconnected port SW[1] +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 757.234 ; gain = 241.590 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 757.234 ; gain = 241.590 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 757.234 ; gain = 241.590 +--------------------------------------------------------------------------------- +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [C:/Users/Alex/APS/aps_/aps_.srcs/constrs_1/imports/apsLabs/Nexys-A7-100T-Master.xdc] +WARNING: [Vivado 12-584] No ports matched 'LED16_B'. [C:/Users/Alex/APS/aps_/aps_.srcs/constrs_1/imports/apsLabs/Nexys-A7-100T-Master.xdc:48] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Alex/APS/aps_/aps_.srcs/constrs_1/imports/apsLabs/Nexys-A7-100T-Master.xdc:48] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'LED16_G'. [C:/Users/Alex/APS/aps_/aps_.srcs/constrs_1/imports/apsLabs/Nexys-A7-100T-Master.xdc:49] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Alex/APS/aps_/aps_.srcs/constrs_1/imports/apsLabs/Nexys-A7-100T-Master.xdc:49] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'LED16_R'. [C:/Users/Alex/APS/aps_/aps_.srcs/constrs_1/imports/apsLabs/Nexys-A7-100T-Master.xdc:50] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Alex/APS/aps_/aps_.srcs/constrs_1/imports/apsLabs/Nexys-A7-100T-Master.xdc:50] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'LED17_B'. [C:/Users/Alex/APS/aps_/aps_.srcs/constrs_1/imports/apsLabs/Nexys-A7-100T-Master.xdc:51] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Alex/APS/aps_/aps_.srcs/constrs_1/imports/apsLabs/Nexys-A7-100T-Master.xdc:51] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'LED17_G'. [C:/Users/Alex/APS/aps_/aps_.srcs/constrs_1/imports/apsLabs/Nexys-A7-100T-Master.xdc:52] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Alex/APS/aps_/aps_.srcs/constrs_1/imports/apsLabs/Nexys-A7-100T-Master.xdc:52] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'LED17_R'. [C:/Users/Alex/APS/aps_/aps_.srcs/constrs_1/imports/apsLabs/Nexys-A7-100T-Master.xdc:53] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Alex/APS/aps_/aps_.srcs/constrs_1/imports/apsLabs/Nexys-A7-100T-Master.xdc:53] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'CA'. [C:/Users/Alex/APS/aps_/aps_.srcs/constrs_1/imports/apsLabs/Nexys-A7-100T-Master.xdc:56] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Alex/APS/aps_/aps_.srcs/constrs_1/imports/apsLabs/Nexys-A7-100T-Master.xdc:56] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'CB'. [C:/Users/Alex/APS/aps_/aps_.srcs/constrs_1/imports/apsLabs/Nexys-A7-100T-Master.xdc:57] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Alex/APS/aps_/aps_.srcs/constrs_1/imports/apsLabs/Nexys-A7-100T-Master.xdc:57] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'CC'. [C:/Users/Alex/APS/aps_/aps_.srcs/constrs_1/imports/apsLabs/Nexys-A7-100T-Master.xdc:58] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Alex/APS/aps_/aps_.srcs/constrs_1/imports/apsLabs/Nexys-A7-100T-Master.xdc:58] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'CD'. [C:/Users/Alex/APS/aps_/aps_.srcs/constrs_1/imports/apsLabs/Nexys-A7-100T-Master.xdc:59] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Alex/APS/aps_/aps_.srcs/constrs_1/imports/apsLabs/Nexys-A7-100T-Master.xdc:59] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'CE'. [C:/Users/Alex/APS/aps_/aps_.srcs/constrs_1/imports/apsLabs/Nexys-A7-100T-Master.xdc:60] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Alex/APS/aps_/aps_.srcs/constrs_1/imports/apsLabs/Nexys-A7-100T-Master.xdc:60] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'CF'. [C:/Users/Alex/APS/aps_/aps_.srcs/constrs_1/imports/apsLabs/Nexys-A7-100T-Master.xdc:61] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Alex/APS/aps_/aps_.srcs/constrs_1/imports/apsLabs/Nexys-A7-100T-Master.xdc:61] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'CG'. [C:/Users/Alex/APS/aps_/aps_.srcs/constrs_1/imports/apsLabs/Nexys-A7-100T-Master.xdc:62] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Alex/APS/aps_/aps_.srcs/constrs_1/imports/apsLabs/Nexys-A7-100T-Master.xdc:62] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'DP'. [C:/Users/Alex/APS/aps_/aps_.srcs/constrs_1/imports/apsLabs/Nexys-A7-100T-Master.xdc:63] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Alex/APS/aps_/aps_.srcs/constrs_1/imports/apsLabs/Nexys-A7-100T-Master.xdc:63] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'AN[0]'. [C:/Users/Alex/APS/aps_/aps_.srcs/constrs_1/imports/apsLabs/Nexys-A7-100T-Master.xdc:64] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Alex/APS/aps_/aps_.srcs/constrs_1/imports/apsLabs/Nexys-A7-100T-Master.xdc:64] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'AN[1]'. [C:/Users/Alex/APS/aps_/aps_.srcs/constrs_1/imports/apsLabs/Nexys-A7-100T-Master.xdc:65] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Alex/APS/aps_/aps_.srcs/constrs_1/imports/apsLabs/Nexys-A7-100T-Master.xdc:65] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'AN[2]'. [C:/Users/Alex/APS/aps_/aps_.srcs/constrs_1/imports/apsLabs/Nexys-A7-100T-Master.xdc:66] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Alex/APS/aps_/aps_.srcs/constrs_1/imports/apsLabs/Nexys-A7-100T-Master.xdc:66] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'AN[3]'. [C:/Users/Alex/APS/aps_/aps_.srcs/constrs_1/imports/apsLabs/Nexys-A7-100T-Master.xdc:67] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Alex/APS/aps_/aps_.srcs/constrs_1/imports/apsLabs/Nexys-A7-100T-Master.xdc:67] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'AN[4]'. [C:/Users/Alex/APS/aps_/aps_.srcs/constrs_1/imports/apsLabs/Nexys-A7-100T-Master.xdc:68] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Alex/APS/aps_/aps_.srcs/constrs_1/imports/apsLabs/Nexys-A7-100T-Master.xdc:68] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'AN[5]'. [C:/Users/Alex/APS/aps_/aps_.srcs/constrs_1/imports/apsLabs/Nexys-A7-100T-Master.xdc:69] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Alex/APS/aps_/aps_.srcs/constrs_1/imports/apsLabs/Nexys-A7-100T-Master.xdc:69] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'AN[6]'. [C:/Users/Alex/APS/aps_/aps_.srcs/constrs_1/imports/apsLabs/Nexys-A7-100T-Master.xdc:70] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Alex/APS/aps_/aps_.srcs/constrs_1/imports/apsLabs/Nexys-A7-100T-Master.xdc:70] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'AN[7]'. [C:/Users/Alex/APS/aps_/aps_.srcs/constrs_1/imports/apsLabs/Nexys-A7-100T-Master.xdc:71] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Alex/APS/aps_/aps_.srcs/constrs_1/imports/apsLabs/Nexys-A7-100T-Master.xdc:71] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +Finished Parsing XDC File [C:/Users/Alex/APS/aps_/aps_.srcs/constrs_1/imports/apsLabs/Nexys-A7-100T-Master.xdc] +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [C:/Users/Alex/APS/aps_/aps_.srcs/constrs_1/imports/apsLabs/Nexys-A7-100T-Master.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/top_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +Completed Processing XDC Constraints + +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 837.828 ; gain = 0.000 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 837.828 ; gain = 0.000 +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 837.828 ; gain = 322.184 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7a100tcsg324-1 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 837.828 ; gain = 322.184 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 837.828 ; gain = 322.184 +--------------------------------------------------------------------------------- +INFO: [Synth 8-5544] ROM "ROM" won't be mapped to Block RAM because address size (4) smaller than threshold (5) +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 837.828 ; gain = 322.184 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : ++---Adders : + 2 Input 32 Bit Adders := 1 + 3 Input 32 Bit Adders := 1 + 2 Input 5 Bit Adders := 1 ++---XORs : + 2 Input 32 Bit XORs := 1 ++---Registers : + 5 Bit Registers := 1 ++---RAMs : + 1024 Bit RAMs := 1 ++---Muxes : + 10 Input 32 Bit Muxes := 1 + 2 Input 32 Bit Muxes := 2 + 4 Input 32 Bit Muxes := 1 + 2 Input 8 Bit Muxes := 1 +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +Hierarchical RTL Component report +Module top +Detailed RTL Component Info : ++---Adders : + 2 Input 5 Bit Adders := 1 ++---Registers : + 5 Bit Registers := 1 ++---Muxes : + 4 Input 32 Bit Muxes := 1 + 2 Input 8 Bit Muxes := 1 +Module instruction_memory +Detailed RTL Component Info : ++---Muxes : + 10 Input 32 Bit Muxes := 1 +Module rf_riscv +Detailed RTL Component Info : ++---RAMs : + 1024 Bit RAMs := 1 ++---Muxes : + 2 Input 32 Bit Muxes := 2 +Module alu_riscv +Detailed RTL Component Info : ++---Adders : + 2 Input 32 Bit Adders := 1 + 3 Input 32 Bit Adders := 1 ++---XORs : + 2 Input 32 Bit XORs := 1 +--------------------------------------------------------------------------------- +Finished RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 240 (col length:80) +BRAMs: 270 (col length: RAMB18 80 RAMB36 40) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +Warning: Parallel synthesis criteria is not met +WARNING: [Synth 8-3917] design top has port pcc[5] driven by constant 0 +WARNING: [Synth 8-3917] design top has port inc[31] driven by constant 0 +WARNING: [Synth 8-3917] design top has port inc[30] driven by constant 0 +WARNING: [Synth 8-3917] design top has port inc[29] driven by constant 0 +WARNING: [Synth 8-3917] design top has port inc[28] driven by constant 0 +WARNING: [Synth 8-3917] design top has port inc[27] driven by constant 0 +WARNING: [Synth 8-3917] design top has port inc[26] driven by constant 0 +WARNING: [Synth 8-3917] design top has port inc[25] driven by constant 0 +WARNING: [Synth 8-3917] design top has port inc[24] driven by constant 0 +WARNING: [Synth 8-3917] design top has port inc[23] driven by constant 0 +WARNING: [Synth 8-3917] design top has port inc[22] driven by constant 0 +WARNING: [Synth 8-3917] design top has port inc[21] driven by constant 0 +WARNING: [Synth 8-3917] design top has port inc[20] driven by constant 0 +WARNING: [Synth 8-3917] design top has port inc[19] driven by constant 0 +WARNING: [Synth 8-3917] design top has port inc[18] driven by constant 0 +WARNING: [Synth 8-3917] design top has port inc[17] driven by constant 0 +WARNING: [Synth 8-3917] design top has port inc[16] driven by constant 0 +WARNING: [Synth 8-3917] design top has port inc[15] driven by constant 0 +WARNING: [Synth 8-3917] design top has port inc[14] driven by constant 0 +WARNING: [Synth 8-3917] design top has port inc[13] driven by constant 0 +WARNING: [Synth 8-3917] design top has port inc[12] driven by constant 0 +WARNING: [Synth 8-3917] design top has port inc[11] driven by constant 0 +WARNING: [Synth 8-3917] design top has port inc[10] driven by constant 0 +WARNING: [Synth 8-3917] design top has port inc[9] driven by constant 0 +WARNING: [Synth 8-3917] design top has port inc[8] driven by constant 0 +WARNING: [Synth 8-3331] design top has unconnected port SW[15] +WARNING: [Synth 8-3331] design top has unconnected port SW[14] +WARNING: [Synth 8-3331] design top has unconnected port SW[13] +WARNING: [Synth 8-3331] design top has unconnected port SW[12] +WARNING: [Synth 8-3331] design top has unconnected port SW[11] +WARNING: [Synth 8-3331] design top has unconnected port SW[10] +WARNING: [Synth 8-3331] design top has unconnected port SW[9] +WARNING: [Synth 8-3331] design top has unconnected port SW[8] +WARNING: [Synth 8-3331] design top has unconnected port SW[7] +WARNING: [Synth 8-3331] design top has unconnected port SW[6] +WARNING: [Synth 8-3331] design top has unconnected port SW[5] +WARNING: [Synth 8-3331] design top has unconnected port SW[4] +WARNING: [Synth 8-3331] design top has unconnected port SW[3] +WARNING: [Synth 8-3331] design top has unconnected port SW[2] +WARNING: [Synth 8-3331] design top has unconnected port SW[1] +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 837.828 ; gain = 322.184 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start ROM, RAM, DSP and Shift Register Reporting +--------------------------------------------------------------------------------- + +Distributed RAM: Preliminary Mapping Report (see note below) ++------------+------------+-----------+----------------------+---------------+ +|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | ++------------+------------+-----------+----------------------+---------------+ +|top | rf/RAM_reg | Implied | 32 x 32 | RAM32M x 12 | ++------------+------------+-----------+----------------------+---------------+ + +Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once. +--------------------------------------------------------------------------------- +Finished ROM, RAM, DSP and Shift Register Reporting +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:24 ; elapsed = 00:00:26 . Memory (MB): peak = 849.656 ; gain = 334.012 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:00:24 ; elapsed = 00:00:26 . Memory (MB): peak = 871.059 ; gain = 355.414 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start ROM, RAM, DSP and Shift Register Reporting +--------------------------------------------------------------------------------- + +Distributed RAM: Final Mapping Report ++------------+------------+-----------+----------------------+---------------+ +|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | ++------------+------------+-----------+----------------------+---------------+ +|top | rf/RAM_reg | Implied | 32 x 32 | RAM32M x 12 | ++------------+------------+-----------+----------------------+---------------+ + +--------------------------------------------------------------------------------- +Finished ROM, RAM, DSP and Shift Register Reporting +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:00:24 ; elapsed = 00:00:26 . Memory (MB): peak = 871.059 ; gain = 355.414 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:00:27 ; elapsed = 00:00:29 . Memory (MB): peak = 878.625 ; gain = 362.980 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:00:27 ; elapsed = 00:00:29 . Memory (MB): peak = 878.625 ; gain = 362.980 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:27 ; elapsed = 00:00:29 . Memory (MB): peak = 878.625 ; gain = 362.980 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:00:27 ; elapsed = 00:00:29 . Memory (MB): peak = 878.625 ; gain = 362.980 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:27 ; elapsed = 00:00:29 . Memory (MB): peak = 878.625 ; gain = 362.980 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:00:27 ; elapsed = 00:00:29 . Memory (MB): peak = 878.625 ; gain = 362.980 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+-------+------+ +| |Cell |Count | ++------+-------+------+ +|1 |BUFG | 1| +|2 |CARRY4 | 10| +|3 |LUT1 | 1| +|4 |LUT2 | 1| +|5 |LUT3 | 3| +|6 |LUT4 | 9| +|7 |LUT5 | 17| +|8 |LUT6 | 54| +|9 |RAM32M | 6| +|10 |FDRE | 5| +|11 |IBUF | 2| +|12 |OBUF | 54| ++------+-------+------+ + +Report Instance Areas: ++------+---------+----------+------+ +| |Instance |Module |Cells | ++------+---------+----------+------+ +|1 |top | | 163| +|2 | alu |alu_riscv | 28| +|3 | rf |rf_riscv | 67| ++------+---------+----------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:00:27 ; elapsed = 00:00:29 . Memory (MB): peak = 878.625 ; gain = 362.980 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 40 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 878.625 ; gain = 282.387 +Synthesis Optimization Complete : Time (s): cpu = 00:00:27 ; elapsed = 00:00:29 . Memory (MB): peak = 878.625 ; gain = 362.980 +INFO: [Project 1-571] Translating synthesized netlist +INFO: [Netlist 29-17] Analyzing 16 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 895.750 ; gain = 0.000 +INFO: [Project 1-111] Unisim Transformation Summary: + A total of 6 instances were transformed. + RAM32M => RAM32M (RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMS32, RAMS32): 6 instances + +INFO: [Common 17-83] Releasing license: Synthesis +24 Infos, 111 Warnings, 22 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:00:34 ; elapsed = 00:00:37 . Memory (MB): peak = 895.750 ; gain = 601.887 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 895.750 ; gain = 0.000 +WARNING: [Constraints 18-5210] No constraints selected for write. +Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. +INFO: [Common 17-1381] The checkpoint 'C:/Users/Alex/APS/aps_/aps_.runs/synth_1/top.dcp' has been generated. +INFO: [runtcl-4] Executing : report_utilization -file top_utilization_synth.rpt -pb top_utilization_synth.pb +INFO: [Common 17-206] Exiting Vivado at Wed Oct 19 19:58:15 2022... diff --git a/aps_.runs/synth_1/runme.sh b/aps_.runs/synth_1/runme.sh new file mode 100644 index 0000000..d0a7d7b --- /dev/null +++ b/aps_.runs/synth_1/runme.sh @@ -0,0 +1,43 @@ +#!/bin/sh + +# +# Vivado(TM) +# runme.sh: a Vivado-generated Runs Script for UNIX +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# + +echo "This script was generated under a different operating system." +echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script" +exit + +if [ -z "$PATH" ]; then + PATH=C:/Xilinx/SDK/2019.1/bin;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64:C:/Xilinx/Vivado/2019.1/bin +else + PATH=C:/Xilinx/SDK/2019.1/bin;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64:C:/Xilinx/Vivado/2019.1/bin:$PATH +fi +export PATH + +if [ -z "$LD_LIBRARY_PATH" ]; then + LD_LIBRARY_PATH= +else + LD_LIBRARY_PATH=:$LD_LIBRARY_PATH +fi +export LD_LIBRARY_PATH + +HD_PWD='C:/Users/Alex/APS/aps_/aps_.runs/synth_1' +cd "$HD_PWD" + +HD_LOG=runme.log +/bin/touch $HD_LOG + +ISEStep="./ISEWrap.sh" +EAStep() +{ + $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 + if [ $? -ne 0 ] + then + exit + fi +} + +EAStep vivado -log top.vds -m64 -product Vivado -mode batch -messageDb vivado.pb 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0000000..54c01ee --- /dev/null +++ b/aps_.runs/synth_1/top.tcl @@ -0,0 +1,64 @@ +# +# Synthesis run script generated by Vivado +# + +set TIME_start [clock seconds] +proc create_report { reportName command } { + set status "." + append status $reportName ".fail" + if { [file exists $status] } { + eval file delete [glob $status] + } + send_msg_id runtcl-4 info "Executing : $command" + set retval [eval catch { $command } msg] + if { $retval != 0 } { + set fp [open $status w] + close $fp + send_msg_id runtcl-5 warning "$msg" + } +} +create_project -in_memory -part xc7a100tcsg324-1 + +set_param project.singleFileAddWarning.threshold 0 +set_param project.compositeFile.enableAutoGeneration 0 +set_param synth.vivado.isSynthRun true +set_property webtalk.parent_dir C:/Users/Alex/APS/aps_/aps_.cache/wt [current_project] +set_property parent.project_path C:/Users/Alex/APS/aps_/aps_.xpr [current_project] +set_property default_lib xil_defaultlib [current_project] +set_property target_language Verilog [current_project] +set_property ip_cache_permissions {read write} [current_project] +read_verilog C:/Users/Alex/APS/aps_/aps_.srcs/sources_1/new/defines.v +set_property file_type "Verilog Header" [get_files C:/Users/Alex/APS/aps_/aps_.srcs/sources_1/new/defines.v] +read_mem C:/Users/Alex/APS/aps_/aps_.srcs/sources_1/new/prog.txt +read_verilog -library xil_defaultlib -sv { + C:/Users/Alex/APS/aps_/aps_.srcs/sources_1/new/top.sv + C:/Users/Alex/APS/aps_/aps_.srcs/sources_1/new/alu_riscv.sv + C:/Users/Alex/APS/aps_/aps_.srcs/sources_1/new/rf_riscv.sv + C:/Users/Alex/APS/aps_/aps_.srcs/sources_1/new/instruction_memory.sv + C:/Users/Alex/APS/aps_/aps_.srcs/sources_1/new/SE.sv + C:/Users/Alex/APS/aps_/aps_.srcs/sources_1/new/pc.sv +} +set_property is_global_include true [get_files C:/Users/Alex/APS/aps_/aps_.srcs/sources_1/new/top.sv] +# Mark all dcp files as not used in implementation to prevent them from being +# stitched into the results of this synthesis run. Any black boxes in the +# design are intentionally left as such for best results. Dcp files will be +# stitched into the design at a later time, either when this synthesis run is +# opened, or when it is stitched into a dependent implementation run. +foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { + set_property used_in_implementation false $dcp +} +read_xdc C:/Users/Alex/APS/aps_/aps_.srcs/constrs_1/imports/apsLabs/Nexys-A7-100T-Master.xdc +set_property used_in_implementation false [get_files C:/Users/Alex/APS/aps_/aps_.srcs/constrs_1/imports/apsLabs/Nexys-A7-100T-Master.xdc] + +set_param ips.enableIPCacheLiteLoad 1 +close [open __synthesis_is_running__ w] + +synth_design -top top -part xc7a100tcsg324-1 + + +# disable binary constraint mode for synth run checkpoints +set_param constraints.enableBinaryConstraints false +write_checkpoint -force -noxdef top.dcp +create_report "synth_1_synth_report_utilization_0" "report_utilization -file top_utilization_synth.rpt -pb top_utilization_synth.pb" +file delete __synthesis_is_running__ +close [open __synthesis_is_complete__ w] diff --git a/aps_.runs/synth_1/top.vds b/aps_.runs/synth_1/top.vds new file mode 100644 index 0000000..6ff603a --- /dev/null +++ b/aps_.runs/synth_1/top.vds @@ -0,0 +1,510 @@ +#----------------------------------------------------------- +# Vivado v2019.1 (64-bit) +# SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 +# IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 +# Start of session at: Wed Oct 19 19:57:34 2022 +# Process ID: 18728 +# Current directory: C:/Users/Alex/APS/aps_/aps_.runs/synth_1 +# Command line: vivado.exe -log top.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source top.tcl +# Log file: C:/Users/Alex/APS/aps_/aps_.runs/synth_1/top.vds +# Journal file: C:/Users/Alex/APS/aps_/aps_.runs/synth_1\vivado.jou +#----------------------------------------------------------- +source top.tcl -notrace +Command: synth_design -top top -part xc7a100tcsg324-1 +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7a100t' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a100t' +INFO: [Device 21-403] Loading part xc7a100tcsg324-1 +INFO: Launching helper process for spawning children vivado processes +INFO: Helper process launched with PID 1876 +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 693.348 ; gain = 177.703 +--------------------------------------------------------------------------------- +INFO: [Synth 8-6157] synthesizing module 'top' [C:/Users/Alex/APS/aps_/aps_.srcs/sources_1/new/top.sv:4] + Parameter COUNTER_WIDTH bound to: 5 - type: integer +WARNING: [Synth 8-311] ignoring non-constant assignment in initial block [C:/Users/Alex/APS/aps_/aps_.srcs/sources_1/new/top.sv:16] +INFO: [Synth 8-6157] synthesizing module 'SE' [C:/Users/Alex/APS/aps_/aps_.srcs/sources_1/new/SE.sv:5] +INFO: [Synth 8-6155] done synthesizing module 'SE' (1#1) [C:/Users/Alex/APS/aps_/aps_.srcs/sources_1/new/SE.sv:5] +WARNING: [Synth 8-689] width (8) of port connection 'extended_constant' does not match port width (32) of module 'SE' [C:/Users/Alex/APS/aps_/aps_.srcs/sources_1/new/top.sv:29] +INFO: [Synth 8-6157] synthesizing module 'instruction_memory' [C:/Users/Alex/APS/aps_/aps_.srcs/sources_1/new/instruction_memory.sv:3] + Parameter WIDTH bound to: 32'sb00000000000000000000000000100000 + Parameter DEPTH bound to: 32'sb00000000000000000000000001000000 +INFO: [Synth 8-3876] $readmem data file 'prog.txt' is read successfully [C:/Users/Alex/APS/aps_/aps_.srcs/sources_1/new/instruction_memory.sv:15] +INFO: [Synth 8-6155] done synthesizing module 'instruction_memory' (2#1) [C:/Users/Alex/APS/aps_/aps_.srcs/sources_1/new/instruction_memory.sv:3] +INFO: [Synth 8-6157] synthesizing module 'rf_riscv' [C:/Users/Alex/APS/aps_/aps_.srcs/sources_1/new/rf_riscv.sv:3] +INFO: [Synth 8-6155] done synthesizing module 'rf_riscv' (3#1) [C:/Users/Alex/APS/aps_/aps_.srcs/sources_1/new/rf_riscv.sv:3] +INFO: [Synth 8-6157] synthesizing module 'alu_riscv' [C:/Users/Alex/APS/aps_/aps_.srcs/sources_1/new/alu_riscv.sv:4] +WARNING: [Synth 8-151] case item 5'b11000 is unreachable [C:/Users/Alex/APS/aps_/aps_.srcs/sources_1/new/alu_riscv.sv:24] +WARNING: [Synth 8-151] case item 5'b11001 is unreachable [C:/Users/Alex/APS/aps_/aps_.srcs/sources_1/new/alu_riscv.sv:25] +WARNING: [Synth 8-151] case item 5'b11100 is unreachable [C:/Users/Alex/APS/aps_/aps_.srcs/sources_1/new/alu_riscv.sv:26] +WARNING: [Synth 8-151] case item 5'b11101 is unreachable [C:/Users/Alex/APS/aps_/aps_.srcs/sources_1/new/alu_riscv.sv:27] +WARNING: [Synth 8-151] case item 5'b11110 is unreachable [C:/Users/Alex/APS/aps_/aps_.srcs/sources_1/new/alu_riscv.sv:28] +WARNING: [Synth 8-151] case item 5'b11111 is unreachable [C:/Users/Alex/APS/aps_/aps_.srcs/sources_1/new/alu_riscv.sv:29] +INFO: [Synth 8-6155] done synthesizing module 'alu_riscv' (4#1) [C:/Users/Alex/APS/aps_/aps_.srcs/sources_1/new/alu_riscv.sv:4] +WARNING: [Synth 8-689] width (5) of port connection 'ALUOp' does not match port width (4) of module 'alu_riscv' [C:/Users/Alex/APS/aps_/aps_.srcs/sources_1/new/top.sv:94] +WARNING: [Synth 8-3848] Net extended_switch in module/entity top does not have driver. [C:/Users/Alex/APS/aps_/aps_.srcs/sources_1/new/top.sv:15] +INFO: [Synth 8-6155] done synthesizing module 'top' (5#1) [C:/Users/Alex/APS/aps_/aps_.srcs/sources_1/new/top.sv:4] +WARNING: [Synth 8-3917] design top has port pcc[5] driven by constant 0 +WARNING: [Synth 8-3917] design top has port inc[31] driven by constant 0 +WARNING: [Synth 8-3917] design top has port inc[30] driven by constant 0 +WARNING: [Synth 8-3917] design top has port inc[29] driven by constant 0 +WARNING: [Synth 8-3917] design top has port inc[28] driven by constant 0 +WARNING: [Synth 8-3917] design top has port inc[27] driven by constant 0 +WARNING: [Synth 8-3917] design top has port inc[26] driven by constant 0 +WARNING: [Synth 8-3917] design top has port inc[25] driven by constant 0 +WARNING: [Synth 8-3917] design top has port inc[24] driven by constant 0 +WARNING: [Synth 8-3917] design top has port inc[23] driven by constant 0 +WARNING: [Synth 8-3917] design top has port inc[22] driven by constant 0 +WARNING: [Synth 8-3917] design top has port inc[21] driven by constant 0 +WARNING: [Synth 8-3917] design top has port inc[20] driven by constant 0 +WARNING: [Synth 8-3917] design top has port inc[19] driven by constant 0 +WARNING: [Synth 8-3917] design top has port inc[18] driven by constant 0 +WARNING: [Synth 8-3917] design top has port inc[17] driven by constant 0 +WARNING: [Synth 8-3917] design top has port inc[16] driven by constant 0 +WARNING: [Synth 8-3917] design top has port inc[15] driven by constant 0 +WARNING: [Synth 8-3917] design top has port inc[14] driven by constant 0 +WARNING: [Synth 8-3917] design top has port inc[13] driven by constant 0 +WARNING: [Synth 8-3917] design top has port inc[12] driven by constant 0 +WARNING: [Synth 8-3917] design top has port inc[11] driven by constant 0 +WARNING: [Synth 8-3917] design top has port inc[10] driven by constant 0 +WARNING: [Synth 8-3917] design top has port inc[9] driven by constant 0 +WARNING: [Synth 8-3331] design top has unconnected port SW[15] +WARNING: [Synth 8-3331] design top has unconnected port SW[14] +WARNING: [Synth 8-3331] design top has unconnected port SW[13] +WARNING: [Synth 8-3331] design top has unconnected port SW[12] +WARNING: [Synth 8-3331] design top has unconnected port SW[11] +WARNING: [Synth 8-3331] design top has unconnected port SW[10] +WARNING: [Synth 8-3331] design top has unconnected port SW[9] +WARNING: [Synth 8-3331] design top has unconnected port SW[8] +WARNING: [Synth 8-3331] design top has unconnected port SW[7] +WARNING: [Synth 8-3331] design top has unconnected port SW[6] +WARNING: [Synth 8-3331] design top has unconnected port SW[5] +WARNING: [Synth 8-3331] design top has unconnected port SW[4] +WARNING: [Synth 8-3331] design top has unconnected port SW[3] +WARNING: [Synth 8-3331] design top has unconnected port SW[2] +WARNING: [Synth 8-3331] design top has unconnected port SW[1] +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 757.234 ; gain = 241.590 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 757.234 ; gain = 241.590 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 757.234 ; gain = 241.590 +--------------------------------------------------------------------------------- +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [C:/Users/Alex/APS/aps_/aps_.srcs/constrs_1/imports/apsLabs/Nexys-A7-100T-Master.xdc] +WARNING: [Vivado 12-584] No ports matched 'LED16_B'. [C:/Users/Alex/APS/aps_/aps_.srcs/constrs_1/imports/apsLabs/Nexys-A7-100T-Master.xdc:48] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Alex/APS/aps_/aps_.srcs/constrs_1/imports/apsLabs/Nexys-A7-100T-Master.xdc:48] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'LED16_G'. [C:/Users/Alex/APS/aps_/aps_.srcs/constrs_1/imports/apsLabs/Nexys-A7-100T-Master.xdc:49] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Alex/APS/aps_/aps_.srcs/constrs_1/imports/apsLabs/Nexys-A7-100T-Master.xdc:49] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'LED16_R'. [C:/Users/Alex/APS/aps_/aps_.srcs/constrs_1/imports/apsLabs/Nexys-A7-100T-Master.xdc:50] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Alex/APS/aps_/aps_.srcs/constrs_1/imports/apsLabs/Nexys-A7-100T-Master.xdc:50] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'LED17_B'. [C:/Users/Alex/APS/aps_/aps_.srcs/constrs_1/imports/apsLabs/Nexys-A7-100T-Master.xdc:51] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Alex/APS/aps_/aps_.srcs/constrs_1/imports/apsLabs/Nexys-A7-100T-Master.xdc:51] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'LED17_G'. [C:/Users/Alex/APS/aps_/aps_.srcs/constrs_1/imports/apsLabs/Nexys-A7-100T-Master.xdc:52] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Alex/APS/aps_/aps_.srcs/constrs_1/imports/apsLabs/Nexys-A7-100T-Master.xdc:52] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'LED17_R'. [C:/Users/Alex/APS/aps_/aps_.srcs/constrs_1/imports/apsLabs/Nexys-A7-100T-Master.xdc:53] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Alex/APS/aps_/aps_.srcs/constrs_1/imports/apsLabs/Nexys-A7-100T-Master.xdc:53] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'CA'. [C:/Users/Alex/APS/aps_/aps_.srcs/constrs_1/imports/apsLabs/Nexys-A7-100T-Master.xdc:56] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Alex/APS/aps_/aps_.srcs/constrs_1/imports/apsLabs/Nexys-A7-100T-Master.xdc:56] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'CB'. [C:/Users/Alex/APS/aps_/aps_.srcs/constrs_1/imports/apsLabs/Nexys-A7-100T-Master.xdc:57] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Alex/APS/aps_/aps_.srcs/constrs_1/imports/apsLabs/Nexys-A7-100T-Master.xdc:57] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'CC'. [C:/Users/Alex/APS/aps_/aps_.srcs/constrs_1/imports/apsLabs/Nexys-A7-100T-Master.xdc:58] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Alex/APS/aps_/aps_.srcs/constrs_1/imports/apsLabs/Nexys-A7-100T-Master.xdc:58] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'CD'. [C:/Users/Alex/APS/aps_/aps_.srcs/constrs_1/imports/apsLabs/Nexys-A7-100T-Master.xdc:59] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Alex/APS/aps_/aps_.srcs/constrs_1/imports/apsLabs/Nexys-A7-100T-Master.xdc:59] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'CE'. [C:/Users/Alex/APS/aps_/aps_.srcs/constrs_1/imports/apsLabs/Nexys-A7-100T-Master.xdc:60] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Alex/APS/aps_/aps_.srcs/constrs_1/imports/apsLabs/Nexys-A7-100T-Master.xdc:60] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'CF'. [C:/Users/Alex/APS/aps_/aps_.srcs/constrs_1/imports/apsLabs/Nexys-A7-100T-Master.xdc:61] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Alex/APS/aps_/aps_.srcs/constrs_1/imports/apsLabs/Nexys-A7-100T-Master.xdc:61] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'CG'. [C:/Users/Alex/APS/aps_/aps_.srcs/constrs_1/imports/apsLabs/Nexys-A7-100T-Master.xdc:62] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Alex/APS/aps_/aps_.srcs/constrs_1/imports/apsLabs/Nexys-A7-100T-Master.xdc:62] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'DP'. [C:/Users/Alex/APS/aps_/aps_.srcs/constrs_1/imports/apsLabs/Nexys-A7-100T-Master.xdc:63] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Alex/APS/aps_/aps_.srcs/constrs_1/imports/apsLabs/Nexys-A7-100T-Master.xdc:63] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'AN[0]'. [C:/Users/Alex/APS/aps_/aps_.srcs/constrs_1/imports/apsLabs/Nexys-A7-100T-Master.xdc:64] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Alex/APS/aps_/aps_.srcs/constrs_1/imports/apsLabs/Nexys-A7-100T-Master.xdc:64] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'AN[1]'. [C:/Users/Alex/APS/aps_/aps_.srcs/constrs_1/imports/apsLabs/Nexys-A7-100T-Master.xdc:65] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Alex/APS/aps_/aps_.srcs/constrs_1/imports/apsLabs/Nexys-A7-100T-Master.xdc:65] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'AN[2]'. [C:/Users/Alex/APS/aps_/aps_.srcs/constrs_1/imports/apsLabs/Nexys-A7-100T-Master.xdc:66] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Alex/APS/aps_/aps_.srcs/constrs_1/imports/apsLabs/Nexys-A7-100T-Master.xdc:66] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'AN[3]'. [C:/Users/Alex/APS/aps_/aps_.srcs/constrs_1/imports/apsLabs/Nexys-A7-100T-Master.xdc:67] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Alex/APS/aps_/aps_.srcs/constrs_1/imports/apsLabs/Nexys-A7-100T-Master.xdc:67] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'AN[4]'. [C:/Users/Alex/APS/aps_/aps_.srcs/constrs_1/imports/apsLabs/Nexys-A7-100T-Master.xdc:68] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Alex/APS/aps_/aps_.srcs/constrs_1/imports/apsLabs/Nexys-A7-100T-Master.xdc:68] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'AN[5]'. [C:/Users/Alex/APS/aps_/aps_.srcs/constrs_1/imports/apsLabs/Nexys-A7-100T-Master.xdc:69] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Alex/APS/aps_/aps_.srcs/constrs_1/imports/apsLabs/Nexys-A7-100T-Master.xdc:69] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'AN[6]'. [C:/Users/Alex/APS/aps_/aps_.srcs/constrs_1/imports/apsLabs/Nexys-A7-100T-Master.xdc:70] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Alex/APS/aps_/aps_.srcs/constrs_1/imports/apsLabs/Nexys-A7-100T-Master.xdc:70] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'AN[7]'. [C:/Users/Alex/APS/aps_/aps_.srcs/constrs_1/imports/apsLabs/Nexys-A7-100T-Master.xdc:71] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Alex/APS/aps_/aps_.srcs/constrs_1/imports/apsLabs/Nexys-A7-100T-Master.xdc:71] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +Finished Parsing XDC File [C:/Users/Alex/APS/aps_/aps_.srcs/constrs_1/imports/apsLabs/Nexys-A7-100T-Master.xdc] +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [C:/Users/Alex/APS/aps_/aps_.srcs/constrs_1/imports/apsLabs/Nexys-A7-100T-Master.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/top_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +Completed Processing XDC Constraints + +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 837.828 ; gain = 0.000 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 837.828 ; gain = 0.000 +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 837.828 ; gain = 322.184 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7a100tcsg324-1 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 837.828 ; gain = 322.184 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 837.828 ; gain = 322.184 +--------------------------------------------------------------------------------- +INFO: [Synth 8-5544] ROM "ROM" won't be mapped to Block RAM because address size (4) smaller than threshold (5) +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 837.828 ; gain = 322.184 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : ++---Adders : + 2 Input 32 Bit Adders := 1 + 3 Input 32 Bit Adders := 1 + 2 Input 5 Bit Adders := 1 ++---XORs : + 2 Input 32 Bit XORs := 1 ++---Registers : + 5 Bit Registers := 1 ++---RAMs : + 1024 Bit RAMs := 1 ++---Muxes : + 10 Input 32 Bit Muxes := 1 + 2 Input 32 Bit Muxes := 2 + 4 Input 32 Bit Muxes := 1 + 2 Input 8 Bit Muxes := 1 +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +Hierarchical RTL Component report +Module top +Detailed RTL Component Info : ++---Adders : + 2 Input 5 Bit Adders := 1 ++---Registers : + 5 Bit Registers := 1 ++---Muxes : + 4 Input 32 Bit Muxes := 1 + 2 Input 8 Bit Muxes := 1 +Module instruction_memory +Detailed RTL Component Info : ++---Muxes : + 10 Input 32 Bit Muxes := 1 +Module rf_riscv +Detailed RTL Component Info : ++---RAMs : + 1024 Bit RAMs := 1 ++---Muxes : + 2 Input 32 Bit Muxes := 2 +Module alu_riscv +Detailed RTL Component Info : ++---Adders : + 2 Input 32 Bit Adders := 1 + 3 Input 32 Bit Adders := 1 ++---XORs : + 2 Input 32 Bit XORs := 1 +--------------------------------------------------------------------------------- +Finished RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 240 (col length:80) +BRAMs: 270 (col length: RAMB18 80 RAMB36 40) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +Warning: Parallel synthesis criteria is not met +WARNING: [Synth 8-3917] design top has port pcc[5] driven by constant 0 +WARNING: [Synth 8-3917] design top has port inc[31] driven by constant 0 +WARNING: [Synth 8-3917] design top has port inc[30] driven by constant 0 +WARNING: [Synth 8-3917] design top has port inc[29] driven by constant 0 +WARNING: [Synth 8-3917] design top has port inc[28] driven by constant 0 +WARNING: [Synth 8-3917] design top has port inc[27] driven by constant 0 +WARNING: [Synth 8-3917] design top has port inc[26] driven by constant 0 +WARNING: [Synth 8-3917] design top has port inc[25] driven by constant 0 +WARNING: [Synth 8-3917] design top has port inc[24] driven by constant 0 +WARNING: [Synth 8-3917] design top has port inc[23] driven by constant 0 +WARNING: [Synth 8-3917] design top has port inc[22] driven by constant 0 +WARNING: [Synth 8-3917] design top has port inc[21] driven by constant 0 +WARNING: [Synth 8-3917] design top has port inc[20] driven by constant 0 +WARNING: [Synth 8-3917] design top has port inc[19] driven by constant 0 +WARNING: [Synth 8-3917] design top has port inc[18] driven by constant 0 +WARNING: [Synth 8-3917] design top has port inc[17] driven by constant 0 +WARNING: [Synth 8-3917] design top has port inc[16] driven by constant 0 +WARNING: [Synth 8-3917] design top has port inc[15] driven by constant 0 +WARNING: [Synth 8-3917] design top has port inc[14] driven by constant 0 +WARNING: [Synth 8-3917] design top has port inc[13] driven by constant 0 +WARNING: [Synth 8-3917] design top has port inc[12] driven by constant 0 +WARNING: [Synth 8-3917] design top has port inc[11] driven by constant 0 +WARNING: [Synth 8-3917] design top has port inc[10] driven by constant 0 +WARNING: [Synth 8-3917] design top has port inc[9] driven by constant 0 +WARNING: [Synth 8-3917] design top has port inc[8] driven by constant 0 +WARNING: [Synth 8-3331] design top has unconnected port SW[15] +WARNING: [Synth 8-3331] design top has unconnected port SW[14] +WARNING: [Synth 8-3331] design top has unconnected port SW[13] +WARNING: [Synth 8-3331] design top has unconnected port SW[12] +WARNING: [Synth 8-3331] design top has unconnected port SW[11] +WARNING: [Synth 8-3331] design top has unconnected port SW[10] +WARNING: [Synth 8-3331] design top has unconnected port SW[9] +WARNING: [Synth 8-3331] design top has unconnected port SW[8] +WARNING: [Synth 8-3331] design top has unconnected port SW[7] +WARNING: [Synth 8-3331] design top has unconnected port SW[6] +WARNING: [Synth 8-3331] design top has unconnected port SW[5] +WARNING: [Synth 8-3331] design top has unconnected port SW[4] +WARNING: [Synth 8-3331] design top has unconnected port SW[3] +WARNING: [Synth 8-3331] design top has unconnected port SW[2] +WARNING: [Synth 8-3331] design top has unconnected port SW[1] +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 837.828 ; gain = 322.184 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start ROM, RAM, DSP and Shift Register Reporting +--------------------------------------------------------------------------------- + +Distributed RAM: Preliminary Mapping Report (see note below) ++------------+------------+-----------+----------------------+---------------+ +|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | ++------------+------------+-----------+----------------------+---------------+ +|top | rf/RAM_reg | Implied | 32 x 32 | RAM32M x 12 | ++------------+------------+-----------+----------------------+---------------+ + +Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once. +--------------------------------------------------------------------------------- +Finished ROM, RAM, DSP and Shift Register Reporting +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:24 ; elapsed = 00:00:26 . Memory (MB): peak = 849.656 ; gain = 334.012 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:00:24 ; elapsed = 00:00:26 . Memory (MB): peak = 871.059 ; gain = 355.414 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start ROM, RAM, DSP and Shift Register Reporting +--------------------------------------------------------------------------------- + +Distributed RAM: Final Mapping Report ++------------+------------+-----------+----------------------+---------------+ +|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | ++------------+------------+-----------+----------------------+---------------+ +|top | rf/RAM_reg | Implied | 32 x 32 | RAM32M x 12 | ++------------+------------+-----------+----------------------+---------------+ + +--------------------------------------------------------------------------------- +Finished ROM, RAM, DSP and Shift Register Reporting +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:00:24 ; elapsed = 00:00:26 . Memory (MB): peak = 871.059 ; gain = 355.414 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:00:27 ; elapsed = 00:00:29 . Memory (MB): peak = 878.625 ; gain = 362.980 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:00:27 ; elapsed = 00:00:29 . Memory (MB): peak = 878.625 ; gain = 362.980 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:27 ; elapsed = 00:00:29 . Memory (MB): peak = 878.625 ; gain = 362.980 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:00:27 ; elapsed = 00:00:29 . Memory (MB): peak = 878.625 ; gain = 362.980 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:27 ; elapsed = 00:00:29 . Memory (MB): peak = 878.625 ; gain = 362.980 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:00:27 ; elapsed = 00:00:29 . Memory (MB): peak = 878.625 ; gain = 362.980 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+-------+------+ +| |Cell |Count | ++------+-------+------+ +|1 |BUFG | 1| +|2 |CARRY4 | 10| +|3 |LUT1 | 1| +|4 |LUT2 | 1| +|5 |LUT3 | 3| +|6 |LUT4 | 9| +|7 |LUT5 | 17| +|8 |LUT6 | 54| +|9 |RAM32M | 6| +|10 |FDRE | 5| +|11 |IBUF | 2| +|12 |OBUF | 54| ++------+-------+------+ + +Report Instance Areas: ++------+---------+----------+------+ +| |Instance |Module |Cells | ++------+---------+----------+------+ +|1 |top | | 163| +|2 | alu |alu_riscv | 28| +|3 | rf |rf_riscv | 67| ++------+---------+----------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:00:27 ; elapsed = 00:00:29 . Memory (MB): peak = 878.625 ; gain = 362.980 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 40 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 878.625 ; gain = 282.387 +Synthesis Optimization Complete : Time (s): cpu = 00:00:27 ; elapsed = 00:00:29 . Memory (MB): peak = 878.625 ; gain = 362.980 +INFO: [Project 1-571] Translating synthesized netlist +INFO: [Netlist 29-17] Analyzing 16 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 895.750 ; gain = 0.000 +INFO: [Project 1-111] Unisim Transformation Summary: + A total of 6 instances were transformed. + RAM32M => RAM32M (RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMS32, RAMS32): 6 instances + +INFO: [Common 17-83] Releasing license: Synthesis +24 Infos, 111 Warnings, 22 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:00:34 ; elapsed = 00:00:37 . Memory (MB): peak = 895.750 ; gain = 601.887 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 895.750 ; gain = 0.000 +WARNING: [Constraints 18-5210] No constraints selected for write. +Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. +INFO: [Common 17-1381] The checkpoint 'C:/Users/Alex/APS/aps_/aps_.runs/synth_1/top.dcp' has been generated. +INFO: [runtcl-4] Executing : report_utilization -file top_utilization_synth.rpt -pb top_utilization_synth.pb +INFO: [Common 17-206] Exiting Vivado at Wed Oct 19 19:58:15 2022... diff --git a/aps_.runs/synth_1/top_utilization_synth.pb b/aps_.runs/synth_1/top_utilization_synth.pb new file mode 100644 index 0000000000000000000000000000000000000000..0131a7e0f6cfbb5ab2206bcf682e6d8674852f9f GIT binary patch literal 242 zcmd;LGcqu=)H9sKtPxzAo10ivsgR$hP+F3ilUbEml9`_e;%28-Dioy_=a&{Grxxp- zr)vvB^Y@>Hs7W~C;6fm}C^ zRC9m3DjUk4N|UD6pzMFLA?YSPtP~_6oi;1RUPjC&1@T-}-j$j)v+RC&G>gkZX8(o8 z*~7EX5-(hwA!YK?mWf|0>K^qs&bmJ%WJ|vO*{?IA;Q#gSCde0-OjE8mtOiVt?#U*V zXicfesv*-|O{crEWHxn~UYR$pP$0L6YgPFvp0F-i9c9wRg}Dll*HrNnNWlQ2{MD`E-cJi>=fTkkVB8doA>X~ zwVJe}>5{2vDlOCdN?oQ`jca9EX*B8UG@UN9e_8rDD%YfjAy?ZMb2LTQ<+`RH(W~pr z_(?;Sp5S)Alu2c>Mf_w>QdC?J3WZc5ogrZc0n!VH7i=Q@bAnv5U<9Y%VWg;Q)n?6> z3X33Tv)NK%VOEojBSZWsIRjA-w_GJTB9 z2>D1l%@&jB7-X6|oU;-5r=A4hB{H+M7Un?&|G!AGJ@S8Rtqc2ek!W$)|0^@(N>x*3 z+n{o#n_itaK0R+-gW5AG&$;~Q4atv?1jovY5tm0ylAK>7el$Zi4wS07&k(;xwO!iK zFl0euRk>oBB5Qc4YO(=QHfdclEBp2{!JqkT1QX?avE-5tSQk0sF;9M6J~U;uDp$8% z1>rmf!e>POb*|J6T5-fuq=Z3nfTmw@{{W_dmS#Wy~>$?f^ znsa;r8Q7N$dy|F91Cs!i?i{gQ8G9cQyReo#WaD>XFOj)MrSdrUHb*`{2hPyKHcm4o zfo+_6JA&UE5_B(-^qlP%yqlPfqqlPfqqlPfqqlPfqqlPfqqlPfqqlPfqqlPfqqlPfqqlWODqs9=| zk!+>*oP)+8c{RAmZK{r|0sNUP&jV*^o5^@*2$5@kEN!*HFqAxQXf4cZX8KCV3*Lf6MNXFUJm8*m{t_AzuG+kZI6^B>Mf_zxFyg_M|K zF2|1lu$UE6xl)?%|LXY*bh%C#$OK#*Dl%gk!vs?V^CiYLXab`THyfn7Gg1K%yoRFX_#7_ zB922>cABPa#56d5l*SLipLIl8{APlDE8&^RXwpVUT;zEcvoKhTIexm0AA&#W;M{K{ z$T!=ZV*}hhn9{oPjvXPhfg@6x3a6cKZ<1>px{O#QE7rswSgq);nzpA@sOBRXVWCVJ zM2?+-T!D-NahM@tdYGSr8mecWJA}O6Ekb@%d0DNg&jKUh#xYo(6=*UHXCR` z%!_Eji(7l0ynNe^Yq4X87|YO-tnMkQY{!&ki-87mdFDg!HSk9X@)Ck_y#8-6FYCwi z#@lw}TcNb@0ecIfX(}~CRLEAWOQdyfuCsU|rOxId28%ViBkdTAcjdz)Be_&a!UgVr za$PbI2$VXkR(R1yMT8WI>7-Byfcu{b^3l7RwRd6I(GeI3S$yy!eiE*P@84RLG8x_LCoD9<83F~_`}UOas9S%P8QCu47p zAIoT`w-d|QXp{%W*v+vsHkXcc&OE7%?Sk@v7+aVCQ=Ah{A7i6Y9vEZCZ;Er`>0@j( z$^&EU1eoG3!C@zK@|254In3C9?P*qw7~hqp@ei-jktrv3c#TGR5Ii0KA}1Feo^xV( z8jbQGc)BuvJw1I3*IYEpgW&1v_<0(=fIG2z8jbQGc*@JjGTIHM{OMb+c0qX%JiRe? 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Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns diff --git a/aps_.sim/sim_1/behav/xsim/alu_riscv_tb_behav.wdb b/aps_.sim/sim_1/behav/xsim/alu_riscv_tb_behav.wdb new file mode 100644 index 0000000000000000000000000000000000000000..036fa08d92d68fe36d364e5c1884c4260872c7d4 GIT binary patch literal 10128 zcmeHNU2L0I89r&dl5S;9%NQAJ+1GYmv$4f?l6KuzN*u@eAx>j#XGyzBUmVv1#Mc3I&Xbhr8PU@ER3_6aIlj^{&WQ2DYQERo&W>*MvrVy= zmr=(8IOnmdE^bq*gibYXR_e@$-;d<2O0}c)mjsPlkp`Agj)2<(J1HHN+OI0s^%mOp zEy>~l5jjb7ao53L#~*K0ltL3%==OZjI?X%^%WL7R5ft)23NR9yw<;fkwGm)Ba%q$M zF@RhOHHJX#1?bxjkh=%a9GG5P?uRC42;iF72bdhTnVe4mtTzfUt%ZIH>o@?gP5pq4 z(+(f|aij)^E4LoV*Wk3lw+T2|gTwyZ41Bo;XFq)0y=QB1uv8S5mii8$=Ln`ZhU`1X zj((0i)0B_E{vhEP(oY|4juYovYtFa!?}Dx8S?fCkewJt5L9i@^d>x{;HNwzk$zfay^SDka%)0~7F__1;>G|Bk3{Zw%T|+pD5(vSbiUmEw1)u)(Dm}3 zppf$88a&<;6jELd@c5<+_Jj8Xg_PFsBKPcoghArP#@Bb_RdfR`!^HxRp^gRvay= zV>6YjxoWDEpUzeaQbrsHo33GjYO(*THQ!XbxxZbX|2kMJm^N+RJ3?9`(!!N;)e14(xIY>!GV(MDrU!2 zDqo%{R#bO7rMfd|)jbqf$yB0KmE4(>$yhX*8BE0k zIjML$9%Q6@db@(@!6g2gQ&nK_a3)?AG#yVw0uhmHsZO?5C))za!E`*u&IJSLykHca z7YwEIBwlJD<_`6CW_na+)yk?-EGw=lm7gu;bCvutciNxC)$|jbS&`Vop}}%~x*UoY z^RuC7G9AL~6V2u6Tsc%OOt_KIWd39*xR#sCCsd7sg$XG)njg=e2+bl$h^xQ3W+|__ zshR0qzHC;>`b2on1V!gR1cR6okVBu=v=0jSuI2lc?_iz-4zLs04craz9m6-uy#U`9 zd=K!h=RM9ln)hle!0#@8Tk-pkb@PqQIz9z_8fXVPfEW-5x_};_7w7{Lz+qqj_$=T8 zBS01y1#-YKAP+nNaMH$s0`NKDI8X#8fJuOTF98)`2H>F00#5;a=RO1Q8-ab|TgdDe z-xcf|zc+Q?biW=!p6*)|w(i$v*u3v}mu&$W0M@Y$;P`T^`F+5*Ki~EI#=8UHo1E|M z?Z6H|e?P%omG!F@{*J{!kOk3oeo_tpyp>J#n^->G@$QWnL(WZ_A3)VMre zN}|np(j4z^e~jyJ!XPG(Zzsx<_?Im_zMUwu^2nJJZN`&kD@PtVO`=VnG+Ql+f7!y5 z=BN@E8S58q#*^l#MlM8%BiiIiHEL1(OBS9~quRMxAw8nacv4(l6#pd)k9&i1nhPIt zMzk4^`-d_v1xlh#9`_ifK?*dAHhHpb)PndIEj-yaYD5B$i#FrQwo&yGxIwhZH&3HUtDB-(&eL%FylW9^H#Q&y+C)1?n96#PE z(Plhpwrbkx^TMJ{o<8rE#ec!Vljf+|U4Fbd(Plhpj&gSUye82mPpVN%;$OD#q#9M? zg$S7yZN`)0s&S9cb3~gwDXtFm`#k*{V#I8TT88tz}g7-@BX!MxN$~+=UMQ7aWw0T=EiB_T1(bO;D#B2(Ho{EYYpKD=<{o~ z?(O9tZJG-=Y*@T$--Rzu9C>-iOQ*Kp_Rl{&c+0yBuRPuVm!Dle`ocp;-gx$}2fz8u z-~OEb)3e84_;r2Vx()RWPWzm?rV;L%U-z4hTeGYudh=X(^M=LOWA8k9=vVI1Z)|#f x%jLE&G@K}(J+-pE@AFT+`p)lPeC&Jw_}Y7C)35aX2eGC8KW=UO$=*%d{tb{WRJi~E literal 0 HcmV?d00001 diff --git a/aps_.sim/sim_1/behav/xsim/alu_riscv_tb_vlog.prj b/aps_.sim/sim_1/behav/xsim/alu_riscv_tb_vlog.prj new file mode 100644 index 0000000..4efe5d1 --- /dev/null +++ b/aps_.sim/sim_1/behav/xsim/alu_riscv_tb_vlog.prj @@ -0,0 +1,10 @@ +# compile verilog/system verilog design source files +sv xil_defaultlib \ +"../../../../ALU.srcs/sources_1/new/alu_riscv.sv" \ +"../../../../ALU.srcs/sim_1/new/alu_riscv_tb.sv" \ + +# compile glbl module +verilog xil_defaultlib "glbl.v" + +# Do not sort compile order +nosort diff --git a/aps_.sim/sim_1/behav/xsim/compile.bat b/aps_.sim/sim_1/behav/xsim/compile.bat new file mode 100644 index 0000000..b99e8f5 --- /dev/null +++ b/aps_.sim/sim_1/behav/xsim/compile.bat @@ -0,0 +1,25 @@ +@echo off +REM **************************************************************************** +REM Vivado (TM) v2019.1 (64-bit) +REM +REM Filename : compile.bat +REM Simulator : Xilinx Vivado Simulator +REM Description : Script for compiling the simulation design source files +REM +REM Generated by Vivado on Sun Oct 23 17:26:07 +0300 2022 +REM SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 +REM +REM Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +REM +REM usage: compile.bat +REM +REM **************************************************************************** +echo "xvlog --incr --relax -prj top_tb_vlog.prj" +call xvlog --incr --relax -prj top_tb_vlog.prj -log xvlog.log +call type xvlog.log > compile.log +if "%errorlevel%"=="1" goto END +if "%errorlevel%"=="0" goto SUCCESS +:END +exit 1 +:SUCCESS +exit 0 diff --git a/aps_.sim/sim_1/behav/xsim/compile.log b/aps_.sim/sim_1/behav/xsim/compile.log new file mode 100644 index 0000000..e69de29 diff --git a/aps_.sim/sim_1/behav/xsim/elaborate.bat b/aps_.sim/sim_1/behav/xsim/elaborate.bat new file mode 100644 index 0000000..a2b2852 --- /dev/null +++ b/aps_.sim/sim_1/behav/xsim/elaborate.bat @@ -0,0 +1,24 @@ +@echo off +REM **************************************************************************** +REM Vivado (TM) v2019.1 (64-bit) +REM +REM Filename : elaborate.bat +REM Simulator : Xilinx Vivado Simulator +REM Description : Script for elaborating the compiled design +REM +REM Generated by Vivado on Sun Oct 23 17:26:09 +0300 2022 +REM SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 +REM +REM Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +REM +REM usage: elaborate.bat +REM +REM **************************************************************************** +echo "xelab -wto 88fd13c424e241a2b1d7269d9396082e --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_tb_behav xil_defaultlib.top_tb xil_defaultlib.glbl -log elaborate.log" +call xelab -wto 88fd13c424e241a2b1d7269d9396082e --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_tb_behav xil_defaultlib.top_tb xil_defaultlib.glbl -log elaborate.log +if "%errorlevel%"=="0" goto SUCCESS +if "%errorlevel%"=="1" goto END +:END +exit 1 +:SUCCESS +exit 0 diff --git a/aps_.sim/sim_1/behav/xsim/elaborate.log b/aps_.sim/sim_1/behav/xsim/elaborate.log new file mode 100644 index 0000000..db86c1b --- /dev/null +++ b/aps_.sim/sim_1/behav/xsim/elaborate.log @@ -0,0 +1,8 @@ +Vivado Simulator 2019.1 +Copyright 1986-1999, 2001-2019 Xilinx, Inc. All Rights Reserved. +Running: C:/Xilinx/Vivado/2019.1/bin/unwrapped/win64.o/xelab.exe -wto 88fd13c424e241a2b1d7269d9396082e --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_tb_behav xil_defaultlib.top_tb xil_defaultlib.glbl -log elaborate.log +Using 2 slave threads. +Starting static elaboration +WARNING: [VRFC 10-3091] actual bit length 5 differs from formal bit length 4 for port 'ALUOp' [C:/Users/Alex/APS/aps_/aps_.srcs/sources_1/new/cpu_top.sv:62] +Completed static elaboration +INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel diff --git a/aps_.sim/sim_1/behav/xsim/glbl.v b/aps_.sim/sim_1/behav/xsim/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/aps_.sim/sim_1/behav/xsim/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/aps_.sim/sim_1/behav/xsim/im_tb.tcl b/aps_.sim/sim_1/behav/xsim/im_tb.tcl new file mode 100644 index 0000000..1094e45 --- /dev/null +++ b/aps_.sim/sim_1/behav/xsim/im_tb.tcl @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns diff --git a/aps_.sim/sim_1/behav/xsim/im_tb_behav.wdb b/aps_.sim/sim_1/behav/xsim/im_tb_behav.wdb new file mode 100644 index 0000000000000000000000000000000000000000..27d3b612c3791769dc2f771c5c0ee78148a27761 GIT binary patch literal 8225 zcmeI0YiwLc6@bUCL!Hu6)23j|quV5H92&g4j+3V4k=?a7wi7pYch|8&NH>10oE7T_ z-gROGAx5ZCOZicUh~`f#gAfFSs3SqK1XUf7f+;GPA|MDM9DW6}JaZKmGlypH=5{Bzs_%`OmHOk(VlcU0k36rpH>|X(>+~G@t8O!`iD%dH?((*!+GSx|49ohe^nF3C-uNY!HjSOY`oWi@&Oh zj(eS#F1qt=*Td$uid)~NS!5J}w~H=AS{1hPTSTqjrez4)qUV$0nyt#!iY3-IQLk5$ z5TP&I#S%-V%zX&h)jzAY}%o}qY5hd+^z9>f#e5@O4Im^N@ z_XzXMI$0lOv`IOf-CyL{k73*$;zQu56UMy*NCb{^GK_mSkO-XrJfe*L(SQ24l>!ks z<~taV@xwKVB5*t-L5^~`2SpL`?D;UR4M+s;F3~Wq8%P9>v9s=WJ+QXjK1n0w-znz`aj2$WczaCq)tRcZ-H`r-4M^ zBBEj3SH*|G-6I;t%>#+RZ59pVUH}q-WA6kxe2n9lBt+ou6%FGq0g1rfCmP264M+s; zjqXl-v}@mQ;CLqri?>M~aGY~t+!h~qe+91D$L*-VC4JlnDsVkME?R*b_HnTaoPCdD zyzvU$7k%-XD{yndffA2*gNUeoE_wFwu^!*@al9WyL@kHka^EE(LS61S|G7(=c0iu< zalv+}2S@w`ALqWa3GD6<@lg*U|3l$GX%~&C72}?h_~3rzH)k2$0H(ecSonN)Fn=o9f~r`dFl70QKyVm#)=ZF<*k zXQxf?ZgE;{x~19KWe(=cnf%B=sZPhFMU`W zA>QKfzCxeP!0_;-Y0qX%doF9*`_iT-)754soT&+?JUU@|y1JaM?$!hCQr_L3a@xC6 zU8c3Q>p-`c+}D~-X|m1QPR}Jl-49#|>{&O161zcIVn`i!a-o zO=lRKKY%UsN3mu8P_|6tWx89PzRtE>hsmv`lBUgMx*s-Pd0V1eVi8y%P^IqpwWX>zC(Ey<>hN5}HVqVDc(Djls{r!cBj2J=S-jz*`Yev}>G zv`#&@t?{YJp?t}$CxEE-H_j{fR-uWI9{h;WFMENF7il#(cMTu+QgC)5t{z5vgw ziSL{YxR7y)!1<%gdN)wZVAYc}P8zED}*0R$-qbeo%gt#DXvFy89_5n7>EZII(xM)v3* zUGYeJesJzl8{~BQ%|-REgmBs&GxHv8Uu`g+ zcE>cn*W+SpgPb;FmeqeTgwtlsG#_UoGirnJw7QAti%z53Ag9&MlKPiJI4w345w}@0 ztu`1>i%tDK9v4v?U*kI57UjzyeafA&3C;UC#<5My=hopGZ9LuBb879mJ@ISrp4l$kqjHJp|Kjo& zw^mdmE?4@rBbV)iqUBLt(688q)$$wW#tht;0b>Sb5@v2p#Q)6+*IxheCy%fE a;Wz*J#}{VbRA1=tzf&tUFP^XY+J6C%X;#w! literal 0 HcmV?d00001 diff --git a/aps_.sim/sim_1/behav/xsim/im_tb_vlog.prj b/aps_.sim/sim_1/behav/xsim/im_tb_vlog.prj new file mode 100644 index 0000000..beb135b --- /dev/null +++ b/aps_.sim/sim_1/behav/xsim/im_tb_vlog.prj @@ -0,0 +1,18 @@ +# compile verilog/system verilog design source files +sv xil_defaultlib --include "../../../../aps_.srcs/sources_1/new" \ +"../../../../aps_.srcs/sources_1/new/top.sv" \ +"../../../../aps_.srcs/sources_1/new/alu_riscv.sv" \ +"../../../../aps_.srcs/sources_1/new/rf_riscv.sv" \ +"../../../../aps_.srcs/sources_1/new/instruction_memory.sv" \ +"../../../../aps_.srcs/sources_1/new/SE.sv" \ +"../../../../aps_.srcs/sources_1/new/pc.sv" \ +"../../../../aps_.srcs/sim_1/new/alu_riscv_tb.sv" \ +"../../../../aps_.srcs/sim_1/new/rf_tb.sv" \ +"../../../../aps_.srcs/sim_1/new/top_tb.sv" \ +"../../../../aps_.srcs/sim_1/new/im_tb.sv" \ + +# compile glbl module +verilog xil_defaultlib "glbl.v" + +# Do not sort compile order +nosort diff --git a/aps_.sim/sim_1/behav/xsim/prog.txt b/aps_.sim/sim_1/behav/xsim/prog.txt new file mode 100644 index 0000000..80ff991 --- /dev/null +++ b/aps_.sim/sim_1/behav/xsim/prog.txt @@ -0,0 +1,4 @@ +0_0_01_00000_00000_00000_00000000_00001 +0_0_10_00000_00000_00000_00000101_00010 +0_0_11_00000_00001_00010_00000000_00011 +1_0_00_00000_00011_00000_00000000_00000 diff --git a/aps_.sim/sim_1/behav/xsim/rf_tb.tcl b/aps_.sim/sim_1/behav/xsim/rf_tb.tcl new file mode 100644 index 0000000..1094e45 --- /dev/null +++ b/aps_.sim/sim_1/behav/xsim/rf_tb.tcl @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns diff --git a/aps_.sim/sim_1/behav/xsim/rf_tb_behav.wdb b/aps_.sim/sim_1/behav/xsim/rf_tb_behav.wdb new file mode 100644 index 0000000000000000000000000000000000000000..bcfeff9d3b951cf39a85b3254658f66bce5a7876 GIT binary patch literal 14202 zcmeHN3s{uZ*8bEKJBgy5LVq0@)WR+@+!Sz>J0gX`0Sr9a`9wt`5s(2!a{@hHvPT^} zUBpa;&Z)HeP0b9v4PMg0KQAbys563&iXLTf)N~Y-v)*s^M<4Sy)cK$1e@@Sn%V)9n zUh7?Juf6u=+fd2r8R?mGzyWa9@9X>V#B+P?3o7ZTP>FkPhq z{(x3@8*)*!O;*`N+fT6+4W3Lz<4mV!Qbd?%WPWO9ZX43p5b=FkV=S|?x<^yt<%tvH zBIRSEV`xEWMHYV$K{a&u{+QIab>}9HH zDH$m_d^)89I6>#Pwzd|+#hciLAW%}&GWsb1gg$g4JtU73;?bmNbLdPCok;;87;TZ@ zAZ^2$DkG#mHN7np!B0%wOIUc0^CKJv5i>?&z=-2Oio1-$3W){$Xgy5~t+nyxf)XO0V?U1-m8DvC=Vj;ml?PqI7tY+y`X4vhMNdlTE!c~Ue|P9HM^ z4JXt}tb?$gWbf1oiGw)~HHH+|TI@pyLJX0xPBayPfJYlqo)9#)AK1zw1K*7pSejm2 z{ovP=_&H+Oa44aZ5!w9eb-If9$J{?ATKs*|DEGvUfCp)K*$^!~u!*f&G{Kv47x0LXc=n z*GDd~0|UakU<~`S4;y?@R}gSGyN+;Tp1@(hz!z;P9y**Q5NtTZa@Gb;!~%zN00ItY zR2mOD5Ok;+2s*@;vo>O(W+33Ox1a+KeK~7GhdDw*Kady%9ma)TB-9fzfg8k>z+qfR zxMw9e+!2m&*qb24!#&{$rvQiuIO+ERI^>6%B0t>6AmFfX?Bn4+2QG{l1RU-Xdz?7m zaR3nkhnhRWB?CkR+*8DkaMJ)H0`6%hu{OXXFLB(N)CK{EHG~v#n1hH@Q5yt%KVtiF zVME+`Xb=JSU&M}Z3jrbmu0OFO+;V`3fWzLg$BFr^0f-1VH)2P)4FC}VCnt7<`-W^F z;M|EF;l2fk2srFnN4Oe*h=3bHY>$Ht^}B=y5pd5CJHq`45D{=V1CDTAnE^PD4scIP zaCnW25**Gl>r(5dyBl?$Bf)u5-w|%P z1n1oWu1tdaxwjs<3hVnd;Q+;Y;J%j=i|0-JP9Q&>1c&=xiW9#Rz*Qj_5zYZ(vMyA@ zeFZ&qhb1`pfyHsf_Xi*+BslR76LGlv#CYQO2z|7r@$mK$ak#rd=-ba1_rHik?jZD$ z4@(28cJru}ry`wme^p5iU zclD0q|9|WG+^lRaX9k};l}pQ*n!!!a%SAUQT{SJA3(LrwHq*zK_vJz})G2dS-u}Ed z7oC}&o1T(EY9FyZd;~vSY>)8cM~H1dAKsrEpPCz=nwFwcrKe>M_u;+mG`_rdKzocI z?;Y4qL&N%bu@ro~crSZndw=f$KG2rAuMdwWxIp1CFLUZtE@gTS%|<<)ix2hY;v=}Y z$oS~k2reoio{LIM;G&Wuxw!b42riq?%jR=uWpi;cF?>vH_{&kGkBtiBqhi8hxNwRV zYio`PPY7ep2vJ7cOcYf3qYwoaBmxVKml8vx_(TzI>xI8;b7D3Y!qyv?AhpFOBucvB zp>c^5;v*%R_{fAvDI#HP^cZP>LLB`$vYo?(@rjY`f+j@9cuOKu*Qb5gw|&=7(w&eH z8IQ?H1Bg0l6j3J)CF)qb_}FkhDLNu?ESK2UnwBwBSVV8(rw^Aiowg+X@SznQ$4yVk zP2tk9;1MGg0X|+{zJURXlx$T@%2bsiG-d+WQsK@Xyd&O z#$AIqG#J0L;oXh4oOlrN5MsQU@E*cj2k#iXQHBwF664)~Hvzumc-tce{PEsKU&Q0R z0v{2N_W^wTi1E8DeqRkF9!abu9z~2lXoeDp5r-2?NqPro<1tP&he`UZ2-N*Vf-`G! zcMEAweQmv=Oxokn2d@sJz7p}@uA(Lj{UBy6C#ZBsvl6yGJ?S(RLvw8!Bs0;*v4Jq~bqi-59) z#{sPellJlO76A=qj|ML$?QwXEfa;n3iUS;*9=8%3nrJnX_VHNSTnIKM(O4$!aV%}_ z2D4io;8;3b88$u91}5#}v2?gN94?|{Chc)-7;ZKD#lMV6dmI~v8|!9^7ssSMjt#?E znVpl{@b);ISAkfgJCpV}oN3TzX0LF7!|%|bDa_$DChg;~x;{mNY11^PF&V1X0LXDlM7MkJU(M<%xBU*9xDSk6c;{`7nAn5K{hj2 z%k1?IaBOG?e8P;2=MR4aTix7j+qv_T%Dx09wfo)Jk?> z>~Y>U7#F|}N(hsWG5u;*XCLb0`*wxdZ!js|pWOGh_3&jl_TK~PKkczVOmt#0izQMo z9(blNVuiRX7NouVqu!$m{H`mIOtZf(9^&71C4L)|$2U#-zyCbN?ky88%t!R70*@-t zt^#jRuULFsw6i?w{3j}4e}7eq57z%gGLOc5RDs`k1z!1$=l6R{55G_1{WYgkWAzqi zPVUk<?&8uHX*<<-3h9PcgLJI-&|a~pCOJ@Ik6+tp*v`^zt%QY~xlGkS)8L*BuO zH;3?xZv`A$+? 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All Rights Reserved. +REM +REM usage: simulate.bat +REM +REM **************************************************************************** +echo "xsim top_tb_behav -key {Behavioral:sim_1:Functional:top_tb} -tclbatch top_tb.tcl -log simulate.log" +call xsim top_tb_behav -key {Behavioral:sim_1:Functional:top_tb} -tclbatch top_tb.tcl -log simulate.log +if "%errorlevel%"=="0" goto SUCCESS +if "%errorlevel%"=="1" goto END +:END +exit 1 +:SUCCESS +exit 0 diff --git a/aps_.sim/sim_1/behav/xsim/simulate.log b/aps_.sim/sim_1/behav/xsim/simulate.log new file mode 100644 index 0000000..aa9a83c --- /dev/null +++ b/aps_.sim/sim_1/behav/xsim/simulate.log @@ -0,0 +1,2 @@ +Vivado Simulator 2019.1 +Time resolution is 1 ps diff --git a/aps_.sim/sim_1/behav/xsim/top_tb.tcl b/aps_.sim/sim_1/behav/xsim/top_tb.tcl new file mode 100644 index 0000000..1094e45 --- /dev/null +++ b/aps_.sim/sim_1/behav/xsim/top_tb.tcl @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns diff --git a/aps_.sim/sim_1/behav/xsim/top_tb_behav.wdb b/aps_.sim/sim_1/behav/xsim/top_tb_behav.wdb new file mode 100644 index 0000000000000000000000000000000000000000..1880698f044f33be5f70dec6835abe5e15316b6b GIT binary patch literal 14992 zcmeHOe|%KcmA@cVL@ANlC7{9(RA@nxNkS4BA-{j1aT1e2P*R7G3?Y(VWRgh`66ji2 z`caFmc7YF_O%}Qxwk(yO63UVSi!4zH(AYI0N~G4ne3}535yAjr&-cA^(9d(LPk#hdeet+{{NtuxZz4~ z4+ZdDw1%k8{!*gKBdX~8m8qH+!K#TurTjJd^hw!bMY`ACjcd>WfMX3iHHZ?hR*yh(m-~JSXNV+VS*D z_IgKNZc%Qzt&lJt;xl!65uPjeOTrw?8xWKY_DV7H6x{5L|_hBK<-7Un#?@{|7 zzRD*?3Xwiqh=vDM?jafVkPtD{4@{2=qa?sV#Cocrc$QK!@;I&`1OUe}P{|qD1`Gf| z1tGyOD>jny89LBlRVcq$BrphgxoGz(8uf>!C{T{*2Rqup-cPKKsKzvmo+q$v1W90N zntd2*DzP9Q^v4(|q>04R4>kK?9-wE8ivmL*N$>%}7*WKCDTdex0~_X%>IZ|ZhTLL1 z8TmmR_Yl9}2Q!syLy4FB!Qk|`m-uIXFvu@*R8Nd~f)LmDi7^Iphc@#54za{QQt655 z#K2%)INA;pOAPW&r77Zxfw2(dAUr`VG1Tl^3t+|((}or8#6}pzg}6KYU{D+29zPiD z4cb;>Cq#x84VnI$5{a}!r zK;mpa802OYaUo&Ui-#VFH=*femfc2l6E)d`Wu{+b|zsAdwqs z$K0{bT80gTxIpl$^{HC>+p#9l1FyGZTH|0nF$g%+ ziyj9(a7n}t5dnug19c(m06H+n%_j!o8Ed1(p)GMm)CS=h z_kw<0*x;`M4IEWQ zWq(CMKk_^U{C(X$BXP|dfBJg{&%hzxKWcFJj^IaX_0M0s z28S3-#B#ovKM3>tRD;7gj=4x2&SnsBof;g@XA`l+Ar265mo+$?yC!0ZleqwHAe2PN z3(hqYvBb%Ddf@KY;P6eU#o>Me0r!0k4(FPQSo*`fK){XC;Bc;)h$Rkd2m zIOI=@!#9=0$#sJ-eg1HNN?ex4AL`s_9@!ck>fA&O74WD>_``FK28Z=9u^u?wvl5r9 z!6|h~NtAP;Km90#XIU?Dt|rpSaZ$H&9(ML8Yf6hl-AY`61_vzGPWnS1i7VFNkUzvP z3G0hCAmtjI{+t}g9RQJgid9N2VgDHE5wn&srim1YPfO5a4n}$-KSp|^c#QN$ez100 zLY$~YBmC{A|EBTFxkhsX^%6sDG%u`~mXIHe`Azjk{=cbS#v=P6eiN~LmUhJXZS>!? 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For additional details about this file, please refer to the WebTalk help file at C:/Xilinx/Vivado/2019.1/doc/webtalk_introduction.html. +webtalk_transmit: Time (s): cpu = 00:00:00 ; elapsed = 00:00:06 . Memory (MB): peak = 91.477 ; gain = 0.000 +INFO: [Common 17-206] Exiting Webtalk at Sun Oct 23 17:29:15 2022... diff --git a/aps_.sim/sim_1/behav/xsim/webtalk_15744.backup.jou b/aps_.sim/sim_1/behav/xsim/webtalk_15744.backup.jou new file mode 100644 index 0000000..c3c2a22 --- /dev/null +++ b/aps_.sim/sim_1/behav/xsim/webtalk_15744.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2019.1 (64-bit) +# SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 +# IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 +# Start of session at: Wed Oct 19 20:13:22 2022 +# Process ID: 15744 +# Current directory: C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim/xsim.dir/top_tb_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim/webtalk.log +# Journal file: C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim/xsim.dir/top_tb_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/aps_.sim/sim_1/behav/xsim/webtalk_15744.backup.log b/aps_.sim/sim_1/behav/xsim/webtalk_15744.backup.log new file mode 100644 index 0000000..d48bdc0 --- /dev/null +++ b/aps_.sim/sim_1/behav/xsim/webtalk_15744.backup.log @@ -0,0 +1,13 @@ +#----------------------------------------------------------- +# Webtalk v2019.1 (64-bit) +# SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 +# IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 +# Start of session at: Wed Oct 19 20:13:22 2022 +# Process ID: 15744 +# Current directory: C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim/xsim.dir/top_tb_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim/webtalk.log +# Journal file: C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim/xsim.dir/top_tb_behav/webtalk/xsim_webtalk.tcl -notrace +INFO: [Common 17-206] Exiting Webtalk at Wed Oct 19 20:13:23 2022... diff --git a/aps_.sim/sim_1/behav/xsim/webtalk_19012.backup.jou b/aps_.sim/sim_1/behav/xsim/webtalk_19012.backup.jou new file mode 100644 index 0000000..ca40324 --- /dev/null +++ b/aps_.sim/sim_1/behav/xsim/webtalk_19012.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2019.1 (64-bit) +# SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 +# IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 +# Start of session at: Thu Oct 20 20:10:21 2022 +# Process ID: 19012 +# Current directory: C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim/xsim.dir/top_tb_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim/webtalk.log +# Journal file: C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim/xsim.dir/top_tb_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/aps_.sim/sim_1/behav/xsim/webtalk_19012.backup.log b/aps_.sim/sim_1/behav/xsim/webtalk_19012.backup.log new file mode 100644 index 0000000..5e97769 --- /dev/null +++ b/aps_.sim/sim_1/behav/xsim/webtalk_19012.backup.log @@ -0,0 +1,13 @@ +#----------------------------------------------------------- +# Webtalk v2019.1 (64-bit) +# SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 +# IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 +# Start of session at: Thu Oct 20 20:10:21 2022 +# Process ID: 19012 +# Current directory: C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim/xsim.dir/top_tb_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim/webtalk.log +# Journal file: C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim/xsim.dir/top_tb_behav/webtalk/xsim_webtalk.tcl -notrace +INFO: [Common 17-206] Exiting Webtalk at Thu Oct 20 20:10:22 2022... diff --git a/aps_.sim/sim_1/behav/xsim/webtalk_7268.backup.jou b/aps_.sim/sim_1/behav/xsim/webtalk_7268.backup.jou new file mode 100644 index 0000000..b9af85b --- /dev/null +++ b/aps_.sim/sim_1/behav/xsim/webtalk_7268.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2019.1 (64-bit) +# SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 +# IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 +# Start of session at: Thu Oct 20 20:14:13 2022 +# Process ID: 7268 +# Current directory: C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim/xsim.dir/top_tb_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim/webtalk.log +# Journal file: C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim/xsim.dir/top_tb_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/aps_.sim/sim_1/behav/xsim/webtalk_7268.backup.log b/aps_.sim/sim_1/behav/xsim/webtalk_7268.backup.log new file mode 100644 index 0000000..44cd4b8 --- /dev/null +++ b/aps_.sim/sim_1/behav/xsim/webtalk_7268.backup.log @@ -0,0 +1,13 @@ +#----------------------------------------------------------- +# Webtalk v2019.1 (64-bit) +# SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 +# IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 +# Start of session at: Thu Oct 20 20:14:13 2022 +# Process ID: 7268 +# Current directory: C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim/xsim.dir/top_tb_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim/webtalk.log +# Journal file: C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim/xsim.dir/top_tb_behav/webtalk/xsim_webtalk.tcl -notrace +INFO: [Common 17-206] Exiting Webtalk at Thu Oct 20 20:14:14 2022... diff --git a/aps_.sim/sim_1/behav/xsim/webtalk_9284.backup.jou b/aps_.sim/sim_1/behav/xsim/webtalk_9284.backup.jou new file mode 100644 index 0000000..d2e13cf --- /dev/null +++ b/aps_.sim/sim_1/behav/xsim/webtalk_9284.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2019.1 (64-bit) +# SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 +# IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 +# Start of session at: Thu Oct 20 17:08:12 2022 +# Process ID: 9284 +# Current directory: C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim/xsim.dir/im_tb_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim/webtalk.log +# Journal file: C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim/xsim.dir/im_tb_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/aps_.sim/sim_1/behav/xsim/webtalk_9284.backup.log b/aps_.sim/sim_1/behav/xsim/webtalk_9284.backup.log new file mode 100644 index 0000000..152e010 --- /dev/null +++ b/aps_.sim/sim_1/behav/xsim/webtalk_9284.backup.log @@ -0,0 +1,15 @@ +#----------------------------------------------------------- +# Webtalk v2019.1 (64-bit) +# SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 +# IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 +# Start of session at: Thu Oct 20 17:08:12 2022 +# Process ID: 9284 +# Current directory: C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim/xsim.dir/im_tb_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim/webtalk.log +# Journal file: C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim/xsim.dir/im_tb_behav/webtalk/xsim_webtalk.tcl -notrace +INFO: [Common 17-186] 'C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim/xsim.dir/im_tb_behav/webtalk/usage_statistics_ext_xsim.xml' has been successfully sent to Xilinx on Thu Oct 20 17:08:19 2022. For additional details about this file, please refer to the WebTalk help file at C:/Xilinx/Vivado/2019.1/doc/webtalk_introduction.html. +webtalk_transmit: Time (s): cpu = 00:00:00 ; elapsed = 00:00:07 . Memory (MB): peak = 109.355 ; gain = 23.625 +INFO: [Common 17-206] Exiting Webtalk at Thu Oct 20 17:08:19 2022... diff --git a/aps_.sim/sim_1/behav/xsim/webtalk_9300.backup.jou b/aps_.sim/sim_1/behav/xsim/webtalk_9300.backup.jou new file mode 100644 index 0000000..64e4055 --- /dev/null +++ b/aps_.sim/sim_1/behav/xsim/webtalk_9300.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2019.1 (64-bit) +# SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 +# IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 +# Start of session at: Thu Oct 20 17:08:36 2022 +# Process ID: 9300 +# Current directory: C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim/xsim.dir/im_tb_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim/webtalk.log +# Journal file: C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim/xsim.dir/im_tb_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/aps_.sim/sim_1/behav/xsim/webtalk_9300.backup.log b/aps_.sim/sim_1/behav/xsim/webtalk_9300.backup.log new file mode 100644 index 0000000..c04503f --- /dev/null +++ b/aps_.sim/sim_1/behav/xsim/webtalk_9300.backup.log @@ -0,0 +1,14 @@ +#----------------------------------------------------------- +# Webtalk v2019.1 (64-bit) +# SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 +# IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 +# Start of session at: Thu Oct 20 17:08:36 2022 +# Process ID: 9300 +# Current directory: C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim/xsim.dir/im_tb_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim/webtalk.log +# Journal file: C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim/xsim.dir/im_tb_behav/webtalk/xsim_webtalk.tcl -notrace +INFO: [Common 17-186] 'C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim/xsim.dir/im_tb_behav/webtalk/usage_statistics_ext_xsim.xml' has been successfully sent to Xilinx on Thu Oct 20 17:08:40 2022. For additional details about this file, please refer to the WebTalk help file at C:/Xilinx/Vivado/2019.1/doc/webtalk_introduction.html. +INFO: [Common 17-206] Exiting Webtalk at Thu Oct 20 17:08:40 2022... diff --git a/aps_.sim/sim_1/behav/xsim/xelab.pb b/aps_.sim/sim_1/behav/xsim/xelab.pb new file mode 100644 index 0000000000000000000000000000000000000000..a9272bf3f550349906da707fa64fb477a279a88a GIT binary patch literal 1246 zcmZ`(T~FIE6s4sU&6}paOxw^V-G?D0M3cq|ZNd{>nKUFcCO)Q#m&!@p*2A?k+bQ8+ z>}mgCPy18*DRT&*h{8*pd+nTi?>Q$%0<||aY--eLZL9`fZ~K{M^PCeS75;!a-`Ikr z5>D@P>nWX(oSVJ77rcSmxaUQVhwoDNdl&10-}R%xV78LAiq@~jN~ei_qSc#n^-5=G zeE zUYz7YFfrY`o7VUJdJlh_=y!9p=T?>6YI3(4&5fCGb8)3emeJI`Vxk{7(k&<_u|o?A z-76y@3@54QCjky94m^TmFCE~1ltzBk?}gZ&>N1fiyQDPEr(mu#mJn`ZWq}I2&JAGb z9zntQ_?BqS;xdy9W`)t?1-0MbgmaQ8c^7M%nMMk=zt_9w}i*c0H zn@p(EFi~<26RGA)Cu|ZjsSIpw>a9+DqlNpSxBa}Zida3^geBOHv%5S_nGPOFzeQ`q zqx0kJk*#ACSreXHS8I33Y2gmPp1M}i@y)~0D$%Z%xk{)Wd#<2YZj$9=tEZzEoyH@8 zZ&0(3JI&>tu(98`SoeBezZZFysdmw>{?HM6Ka%r|Q$y3I2*+Xls;CIJHm?&d(cu>f zqZtuX3QWM~gChryn7Ax;%oJTPnQMLxQz~d_wG?Fh115}9ZM_SLwT_{1NtK|yv$nCi e8-))w4t!iXWvy7NI)91KCz0AqA(1NWH2wqljd#QV literal 0 HcmV?d00001 diff --git a/aps_.sim/sim_1/behav/xsim/xsim.dir/im_tb_behav/Compile_Options.txt b/aps_.sim/sim_1/behav/xsim/xsim.dir/im_tb_behav/Compile_Options.txt new file mode 100644 index 0000000..26d648f --- /dev/null +++ b/aps_.sim/sim_1/behav/xsim/xsim.dir/im_tb_behav/Compile_Options.txt @@ -0,0 +1 @@ +-wto "88fd13c424e241a2b1d7269d9396082e" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" --snapshot "im_tb_behav" "xil_defaultlib.im_tb" "xil_defaultlib.glbl" -log "elaborate.log" diff --git a/aps_.sim/sim_1/behav/xsim/xsim.dir/im_tb_behav/TempBreakPointFile.txt b/aps_.sim/sim_1/behav/xsim/xsim.dir/im_tb_behav/TempBreakPointFile.txt new file mode 100644 index 0000000..fdbc612 --- /dev/null +++ b/aps_.sim/sim_1/behav/xsim/xsim.dir/im_tb_behav/TempBreakPointFile.txt @@ -0,0 +1 @@ +Breakpoint File Version 1.0 diff --git a/aps_.sim/sim_1/behav/xsim/xsim.dir/im_tb_behav/obj/xsim_1.c b/aps_.sim/sim_1/behav/xsim/xsim.dir/im_tb_behav/obj/xsim_1.c new file mode 100644 index 0000000..fb498d9 --- /dev/null +++ b/aps_.sim/sim_1/behav/xsim/xsim.dir/im_tb_behav/obj/xsim_1.c @@ -0,0 +1,108 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +typedef void (*funcp)(char *, char *); +extern int main(int, char**); +extern void execute_4(char*, char *); +extern void execute_11(char*, char *); +extern void execute_12(char*, char *); +extern void execute_3(char*, char *); +extern void execute_10(char*, char *); +extern void execute_7(char*, char *); +extern void execute_8(char*, char *); +extern void execute_9(char*, char *); +extern void execute_13(char*, char *); +extern void execute_14(char*, char *); +extern void execute_15(char*, char *); +extern void execute_16(char*, char *); +extern void execute_17(char*, char *); +extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +funcp funcTab[14] = {(funcp)execute_4, (funcp)execute_11, (funcp)execute_12, (funcp)execute_3, (funcp)execute_10, (funcp)execute_7, (funcp)execute_8, (funcp)execute_9, (funcp)execute_13, (funcp)execute_14, (funcp)execute_15, (funcp)execute_16, (funcp)execute_17, (funcp)vlog_transfunc_eventcallback}; +const int NumRelocateId= 14; + +void relocate(char *dp) +{ + iki_relocate(dp, "xsim.dir/im_tb_behav/xsim.reloc", (void **)funcTab, 14); + + /*Populate the transaction function pointer field in the whole net structure */ +} + +void sensitize(char *dp) +{ + iki_sensitize(dp, "xsim.dir/im_tb_behav/xsim.reloc"); +} + +void simulate(char *dp) +{ + iki_schedule_processes_at_time_zero(dp, "xsim.dir/im_tb_behav/xsim.reloc"); + // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net + iki_execute_processes(); + + // Schedule resolution functions for the multiply driven Verilog nets that have strength + // Schedule transaction functions for the singly driven Verilog nets that have strength + +} +#include "iki_bridge.h" +void relocate(char *); + +void sensitize(char *); + +void simulate(char *); + +extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); +extern void implicit_HDL_SCinstatiate(); + +extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ; +extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ; + +int main(int argc, char **argv) +{ + iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; + iki_set_sv_type_file_path_name("xsim.dir/im_tb_behav/xsim.svtype"); + iki_set_crvs_dump_file_path_name("xsim.dir/im_tb_behav/xsim.crvsdump"); + void* design_handle = iki_create_design("xsim.dir/im_tb_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv); + iki_set_rc_trial_count(100); + (void) design_handle; + return iki_simulate_design(); +} diff --git a/aps_.sim/sim_1/behav/xsim/xsim.dir/im_tb_behav/webtalk/.xsim_webtallk.info b/aps_.sim/sim_1/behav/xsim/xsim.dir/im_tb_behav/webtalk/.xsim_webtallk.info new file mode 100644 index 0000000..0365fa9 --- /dev/null +++ b/aps_.sim/sim_1/behav/xsim/xsim.dir/im_tb_behav/webtalk/.xsim_webtallk.info @@ -0,0 +1,5 @@ +1666274890 +1666274915 +5 +1 +88fd13c424e241a2b1d7269d9396082e diff --git a/aps_.sim/sim_1/behav/xsim/xsim.dir/im_tb_behav/webtalk/usage_statistics_ext_xsim.html b/aps_.sim/sim_1/behav/xsim/xsim.dir/im_tb_behav/webtalk/usage_statistics_ext_xsim.html new file mode 100644 index 0000000..2f8bab2 --- /dev/null +++ b/aps_.sim/sim_1/behav/xsim/xsim.dir/im_tb_behav/webtalk/usage_statistics_ext_xsim.html @@ -0,0 +1,53 @@ +Device Usage Statistics Report +

XSIM Usage Report


+ + + + + + + + + + + + + + + + + +
software_version_and_target_device
betaFALSEbuild_version2552052
date_generatedThu Oct 20 17:08:35 2022os_platformWIN64
product_versionXSIM v2019.1 (64-bit)project_id88fd13c424e241a2b1d7269d9396082e
project_iteration2random_idd9ce6c1c-2b3d-4d37-a5d5-eb6432f23822
registration_idd9ce6c1c-2b3d-4d37-a5d5-eb6432f23822route_designFALSE
target_devicenot_applicabletarget_familynot_applicable
target_packagenot_applicabletarget_speednot_applicable
tool_flowxsim_vivado

+ + + + + + + + +
user_environment
cpu_nameIntel(R) Xeon(R) CPU E5-2620 v3 @ 2.40GHzcpu_speed2400 MHz
os_nameWindows Server 2016 or Windows 10os_releasemajor release (build 9200)
system_ram17.000 GBtotal_processors1

+ + +
vivado_usage

+ + + + +
xsim
+ + + +
command_line_options
command=xsim
+
+ + + + + + + +
usage
iteration=0runtime=1 ussimulation_memory=7064_KBsimulation_time=0.05_sec
trace_waveform=true
+

+ + diff --git a/aps_.sim/sim_1/behav/xsim/xsim.dir/im_tb_behav/webtalk/usage_statistics_ext_xsim.wdm b/aps_.sim/sim_1/behav/xsim/xsim.dir/im_tb_behav/webtalk/usage_statistics_ext_xsim.wdm new file mode 100644 index 0000000..0410530 --- /dev/null +++ b/aps_.sim/sim_1/behav/xsim/xsim.dir/im_tb_behav/webtalk/usage_statistics_ext_xsim.wdm @@ -0,0 +1,38 @@ +version = "1.0"; +clients = +( + { client_name = "project"; + rules = ( + { + context="software_version_and_target_device"; + xml_map="software_version_and_target_device"; + html_map="software_version_and_target_device"; + html_format="UserEnvStyle"; + }, + { + context="user_environment"; + xml_map="user_environment"; + html_map="user_environment"; + html_format="UserEnvStyle"; + } + ); + }, + + { client_name = "xsim"; + rules = ( + { + context="xsim\\command_line_options"; + xml_map="xsim\\command_line_options"; + html_map="xsim\\command_line_options"; + html_format="UnisimStatsStyle"; + }, + { + context="xsim\\usage"; + xml_map="xsim\\usage"; + html_map="xsim\\usage"; + html_format="UnisimStatsStyle"; + } + ); + } +); + diff --git a/aps_.sim/sim_1/behav/xsim/xsim.dir/im_tb_behav/webtalk/usage_statistics_ext_xsim.xml b/aps_.sim/sim_1/behav/xsim/xsim.dir/im_tb_behav/webtalk/usage_statistics_ext_xsim.xml new file mode 100644 index 0000000..43f5807 --- /dev/null +++ b/aps_.sim/sim_1/behav/xsim/xsim.dir/im_tb_behav/webtalk/usage_statistics_ext_xsim.xml @@ -0,0 +1,44 @@ + + +
+
+ + + + + + + + + + + + + + + +
+
+ + + + + + +
+
+
+
+
+ +
+
+ + + + + +
+
+
+ diff --git a/aps_.sim/sim_1/behav/xsim/xsim.dir/im_tb_behav/webtalk/xsim_webtalk.tcl b/aps_.sim/sim_1/behav/xsim/xsim.dir/im_tb_behav/webtalk/xsim_webtalk.tcl new file mode 100644 index 0000000..d9fd2ad --- /dev/null +++ b/aps_.sim/sim_1/behav/xsim/xsim.dir/im_tb_behav/webtalk/xsim_webtalk.tcl @@ -0,0 +1,44 @@ +webtalk_init -webtalk_dir C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim/xsim.dir/im_tb_behav/webtalk/ +webtalk_register_client -client project +webtalk_add_data -client project -key date_generated -value "Thu Oct 20 17:09:59 2022" -context "software_version_and_target_device" +webtalk_add_data -client project -key product_version -value "XSIM v2019.1 (64-bit)" -context "software_version_and_target_device" +webtalk_add_data -client project -key build_version -value "2552052" -context "software_version_and_target_device" +webtalk_add_data -client project -key os_platform -value "WIN64" -context "software_version_and_target_device" +webtalk_add_data -client project -key registration_id -value "" -context "software_version_and_target_device" +webtalk_add_data -client project -key tool_flow -value "xsim_vivado" -context "software_version_and_target_device" +webtalk_add_data -client project -key beta -value "FALSE" -context "software_version_and_target_device" +webtalk_add_data -client project -key route_design -value "FALSE" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_family -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_device -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_package -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key random_id -value "d9ce6c1c-2b3d-4d37-a5d5-eb6432f23822" -context "software_version_and_target_device" +webtalk_add_data -client project -key project_id -value "88fd13c424e241a2b1d7269d9396082e" -context "software_version_and_target_device" +webtalk_add_data -client project -key project_iteration -value "4" -context "software_version_and_target_device" +webtalk_add_data -client project -key os_name -value "Windows Server 2016 or Windows 10" -context "user_environment" +webtalk_add_data -client project -key os_release -value "major release (build 9200)" -context "user_environment" +webtalk_add_data -client project -key cpu_name -value "Intel(R) Xeon(R) CPU E5-2620 v3 @ 2.40GHz" -context "user_environment" +webtalk_add_data -client project -key cpu_speed -value "2400 MHz" -context "user_environment" +webtalk_add_data -client project -key total_processors -value "1" -context "user_environment" +webtalk_add_data -client project -key system_ram -value "17.000 GB" -context "user_environment" +webtalk_register_client -client xsim +webtalk_add_data -client xsim -key runall -value "true" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key runall -value "true" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key runall -value "true" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key runall -value "true" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key runall -value "true" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key runall -value "true" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key runall -value "true" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key runall -value "true" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key runall -value "true" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key runall -value "true" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key runall -value "true" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key runall -value "true" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key Command -value "xsim" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key trace_waveform -value "true" -context "xsim\\usage" +webtalk_add_data -client xsim -key runtime -value "1 us" -context "xsim\\usage" +webtalk_add_data -client xsim -key iteration -value "0" -context "xsim\\usage" +webtalk_add_data -client xsim -key Simulation_Time -value "0.05_sec" -context "xsim\\usage" +webtalk_add_data -client xsim -key Simulation_Memory -value "6520_KB" -context "xsim\\usage" +webtalk_transmit -clientid 806496643 -regid "" -xml C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim/xsim.dir/im_tb_behav/webtalk/usage_statistics_ext_xsim.xml -html C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim/xsim.dir/im_tb_behav/webtalk/usage_statistics_ext_xsim.html -wdm C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim/xsim.dir/im_tb_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "

XSIM Usage Report


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+extern int main(int, char**); +extern void execute_2(char*, char *); +extern void execute_12(char*, char *); +extern void execute_35(char*, char *); +extern void execute_36(char*, char *); +extern void execute_37(char*, char *); +extern void execute_38(char*, char *); +extern void execute_6(char*, char *); +extern void execute_9(char*, char *); +extern void execute_17(char*, char *); +extern void execute_19(char*, char *); +extern void execute_22(char*, char *); +extern void execute_23(char*, char *); +extern void execute_24(char*, char *); +extern void execute_25(char*, char *); +extern void execute_26(char*, char *); +extern void execute_27(char*, char *); +extern void execute_28(char*, char *); +extern void execute_29(char*, char *); +extern void execute_30(char*, char *); +extern void execute_31(char*, char *); +extern void execute_32(char*, char *); +extern void execute_33(char*, char *); +extern void execute_34(char*, char *); +extern void execute_5(char*, char *); +extern void execute_18(char*, char *); +extern void execute_8(char*, char *); +extern void execute_20(char*, char *); +extern void execute_21(char*, char *); +extern void execute_11(char*, char *); +extern void execute_14(char*, char *); +extern void execute_15(char*, char *); +extern void execute_16(char*, char *); +extern void execute_39(char*, char *); +extern void execute_40(char*, char *); +extern void execute_41(char*, char *); +extern void execute_42(char*, char *); +extern void execute_43(char*, char *); +extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +funcp funcTab[38] = {(funcp)execute_2, (funcp)execute_12, (funcp)execute_35, (funcp)execute_36, (funcp)execute_37, (funcp)execute_38, (funcp)execute_6, (funcp)execute_9, (funcp)execute_17, (funcp)execute_19, (funcp)execute_22, (funcp)execute_23, (funcp)execute_24, (funcp)execute_25, (funcp)execute_26, (funcp)execute_27, (funcp)execute_28, (funcp)execute_29, (funcp)execute_30, (funcp)execute_31, (funcp)execute_32, (funcp)execute_33, (funcp)execute_34, (funcp)execute_5, (funcp)execute_18, (funcp)execute_8, (funcp)execute_20, (funcp)execute_21, (funcp)execute_11, (funcp)execute_14, (funcp)execute_15, (funcp)execute_16, (funcp)execute_39, (funcp)execute_40, (funcp)execute_41, (funcp)execute_42, (funcp)execute_43, (funcp)vlog_transfunc_eventcallback}; +const int NumRelocateId= 38; + +void relocate(char *dp) +{ + iki_relocate(dp, "xsim.dir/top_tb_behav/xsim.reloc", (void **)funcTab, 38); + + /*Populate the transaction function pointer field in the whole net structure */ +} + +void sensitize(char *dp) +{ + iki_sensitize(dp, "xsim.dir/top_tb_behav/xsim.reloc"); +} + +void simulate(char *dp) +{ + iki_schedule_processes_at_time_zero(dp, "xsim.dir/top_tb_behav/xsim.reloc"); + // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net + iki_execute_processes(); + + // Schedule resolution functions for the multiply driven Verilog nets that have strength + // Schedule transaction functions for the singly driven Verilog nets that have strength + +} +#include "iki_bridge.h" +void relocate(char *); + +void sensitize(char *); + +void simulate(char *); + +extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); +extern void implicit_HDL_SCinstatiate(); + +extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ; +extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ; + +int main(int argc, char **argv) +{ + iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; + iki_set_sv_type_file_path_name("xsim.dir/top_tb_behav/xsim.svtype"); + iki_set_crvs_dump_file_path_name("xsim.dir/top_tb_behav/xsim.crvsdump"); + void* design_handle = iki_create_design("xsim.dir/top_tb_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv); + iki_set_rc_trial_count(100); + (void) design_handle; + return iki_simulate_design(); +} diff --git a/aps_.sim/sim_1/behav/xsim/xsim.dir/top_tb_behav/webtalk/.xsim_webtallk.info b/aps_.sim/sim_1/behav/xsim/xsim.dir/top_tb_behav/webtalk/.xsim_webtallk.info new file mode 100644 index 0000000..c3c7afe --- /dev/null +++ b/aps_.sim/sim_1/behav/xsim/xsim.dir/top_tb_behav/webtalk/.xsim_webtallk.info @@ -0,0 +1,5 @@ +1666285819 +1666535348 +73 +1 +88fd13c424e241a2b1d7269d9396082e diff --git a/aps_.sim/sim_1/behav/xsim/xsim.dir/top_tb_behav/webtalk/usage_statistics_ext_xsim.html b/aps_.sim/sim_1/behav/xsim/xsim.dir/top_tb_behav/webtalk/usage_statistics_ext_xsim.html new file mode 100644 index 0000000..19f5342 --- /dev/null +++ b/aps_.sim/sim_1/behav/xsim/xsim.dir/top_tb_behav/webtalk/usage_statistics_ext_xsim.html @@ -0,0 +1,53 @@ +Device Usage Statistics Report +

XSIM Usage Report


+ + + + + + + + + + + + + + + + + +
software_version_and_target_device
betaFALSEbuild_version2552052
date_generatedSun Oct 23 17:29:08 2022os_platformWIN64
product_versionXSIM v2019.1 (64-bit)project_id88fd13c424e241a2b1d7269d9396082e
project_iteration72random_idd9ce6c1c-2b3d-4d37-a5d5-eb6432f23822
registration_idd9ce6c1c-2b3d-4d37-a5d5-eb6432f23822route_designFALSE
target_devicenot_applicabletarget_familynot_applicable
target_packagenot_applicabletarget_speednot_applicable
tool_flowxsim_vivado

+ + + + + + + + +
user_environment
cpu_nameIntel(R) Xeon(R) CPU E5-2620 v3 @ 2.40GHzcpu_speed2400 MHz
os_nameWindows Server 2016 or Windows 10os_releasemajor release (build 9200)
system_ram17.000 GBtotal_processors1

+ + +
vivado_usage

+ + + + +
xsim
+ + + +
command_line_options
command=xsim
+
+ + + + + + + +
usage
iteration=1runtime=1 ussimulation_memory=6576_KBsimulation_time=0.05_sec
trace_waveform=true
+

+ + diff --git a/aps_.sim/sim_1/behav/xsim/xsim.dir/top_tb_behav/webtalk/usage_statistics_ext_xsim.xml b/aps_.sim/sim_1/behav/xsim/xsim.dir/top_tb_behav/webtalk/usage_statistics_ext_xsim.xml new file mode 100644 index 0000000..5529fa1 --- /dev/null +++ b/aps_.sim/sim_1/behav/xsim/xsim.dir/top_tb_behav/webtalk/usage_statistics_ext_xsim.xml @@ -0,0 +1,44 @@ + + +
+
+ + + + + + + + + + + + + + + +
+
+ + + + + + +
+
+
+
+
+ +
+
+ + + + + +
+
+
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+LOCAL_VALUE_COLUMN_WIDTH=75 +LOCAL_DATA_TYPEPROTO_NAME_COLUMN_WIDTH=0 +PROTO_VALUE_COLUMN_WIDTH=0 +PROTO_DATA_TYPE_COLUMN_WIDTH=0 +INPUT_LOCAL_FILTER=1 +OUTPUT_LOCAL_FILTER=1 +INOUT_LOCAL_FILTER=1 +INTERNAL_LOCAL_FILTER=1 +CONSTANT_LOCAL_FILTER=1 +VARIABLE_LOCAL_FILTER=1 diff --git a/aps_.sim/sim_1/behav/xsim/xsim.dir/top_tb_behav/xsimcrash.log b/aps_.sim/sim_1/behav/xsim/xsim.dir/top_tb_behav/xsimcrash.log new file mode 100644 index 0000000..e69de29 diff --git a/aps_.sim/sim_1/behav/xsim/xsim.dir/top_tb_behav/xsimkernel.log b/aps_.sim/sim_1/behav/xsim/xsim.dir/top_tb_behav/xsimkernel.log new file mode 100644 index 0000000..086a52c --- /dev/null +++ b/aps_.sim/sim_1/behav/xsim/xsim.dir/top_tb_behav/xsimkernel.log @@ -0,0 +1,7 @@ +Running: xsim.dir/top_tb_behav/xsimk.exe -simmode gui -wdb top_tb_behav.wdb -simrunnum 0 -socket 57281 +Design successfully loaded +Design Loading Memory Usage: 5844 KB (Peak: 5844 KB) +Design Loading CPU Usage: 15 ms +Simulation completed +Simulation Memory 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b/aps_.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/top_tb.sdb new file mode 100644 index 0000000000000000000000000000000000000000..772bce980b0dd289cf5799735080036314d7dd3a GIT binary patch literal 1286 zcmZWpL2DCH5T3WYO|sjhY17se6dTZ^pogL$C=*J+R81{<^CC?N+t|C{DY1d}poSg< z6@=YHuoodz53Pq1kAlCUC-3?X)|q)P&C|Za^38nTd~e>o-7Rb_x;{VzwD8ySMb|s( ztko6FWdZ*j|NMq)FbKS<KIOe|rCJlFWmN=h)sK7s zl+Xc&1tIpgd1ic`GUd1<2srkXhqFcn{`K=0^7#@qgqKFS#2@p{*F%d4#)Lb&P_&py zi=mb*Cd+%$QlK*UXw(VC6h5Zefh2h>1RoMF5KoxmrIe42Qyovq=mZ)a-lIaD;KK^a z%ei#{8?jYjS@B?vl|b7{C)i4mw$cS`#8#7*72kxh5@>gyHM-kmmesn;r;v*1Xy)}v zvoX+%56Za4zB!H2C#@6Y-NfE!6rXhjp?yLT-{cf8Nta5<#O$_I> zh9{&U6;KCfC*> b; expected_flag = 0; end + `SRA: begin expected_result = $signed(A) >>> b; expected_flag = 0; end + `OR: begin expected_result = a | b; expected_flag = 0; end + `AND: begin expected_result = a & b; expected_flag = 0; end + `BEQ: begin expected_result = 0; expected_flag = (a == b); end + `BNE: begin expected_result = 0; expected_flag = (a != b); end + `BLT: begin expected_result = 0; expected_flag = $signed(a < b); end + `BGE: begin expected_result = 0; expected_flag = $signed(a >= b); end + `BLTU: begin expected_result = 0; expected_flag = (a < b); end + `BGEU: begin expected_result = 0; expected_flag = (a >= b); end + default: expected_flag = 0; + endcase + // ïîäñ÷åò ñ ïîìîùüþ ÀËÓ è ñðàâíåíèå + begin + A = a; + B = b; + ALUOp = option; + + #10; + + if (expected_result == Result && expected_flag == Flag) + $display("PASS"); + else + $display("FAIL"); + end +endtask + +endmodule diff --git a/aps_.srcs/sim_1/new/im_tb.sv b/aps_.srcs/sim_1/new/im_tb.sv new file mode 100644 index 0000000..0b6ac1d --- /dev/null +++ b/aps_.srcs/sim_1/new/im_tb.sv @@ -0,0 +1,16 @@ +`timescale 1ns / 1ps + +module im_tb(); + +logic [31:0] inst; +logic [5:0] addr; + +instruction_memory dut(addr, inst); + +initial begin + addr = 0; + for(integer i = 0; i < 8; i++) begin + addr = addr + 1; + end +end +endmodule diff --git a/aps_.srcs/sim_1/new/rf_tb.sv b/aps_.srcs/sim_1/new/rf_tb.sv new file mode 100644 index 0000000..96c6a93 --- /dev/null +++ b/aps_.srcs/sim_1/new/rf_tb.sv @@ -0,0 +1,49 @@ +`timescale 1ns / 1ps + +module rf_tb(); + +parameter PERIOD = 10; + +logic CLK; +logic we; +logic [4:0] adr_3; +logic [31:0] wd; + +logic [4:0] RA1; +logic [31:0] RD; + +rf_riscv dut(.clk(CLK), .adr_3(adr_3), .we(we), .adr_1(RA1), .wd(wd), .rd_1(RD)); + +always begin + CLK = 1'b0; + #(PERIOD/2) CLK = 1'b1; + #(PERIOD/2); +end + +initial begin + + int data; + + for(integer i = 1; i < 32; i++) begin + + @(posedge CLK); #1; + + data = $urandom(); + + we = 1; + wd = data; + adr_3 = i; + + @(posedge CLK); #1; + we = 0; + + RA1 = i; + @(posedge CLK); + if (RD != data) + $display("FAIL adress = %b ; rd = %d; wd = %d", adr_3, RD, data); + else + $display("PASS adress = %b ; rd = %d; wd = %d", adr_3, RD, data); + end +end + +endmodule diff --git a/aps_.srcs/sim_1/new/top_tb.sv b/aps_.srcs/sim_1/new/top_tb.sv new file mode 100644 index 0000000..fe23a77 --- /dev/null +++ b/aps_.srcs/sim_1/new/top_tb.sv @@ -0,0 +1,27 @@ +`timescale 1ns / 1ps + +module top_tb(); + +parameter PERIOD = 10; + +logic CLK; +logic [15:0] sw; +logic [15:0] leds; +logic rst; + +always begin + CLK = 1'b0; + #(PERIOD/2) CLK = 1'b1; + #(PERIOD/2); +end + +cpu_top dut(.CLK100MHZ(CLK), .SW(sw), .LED(leds), .rst(rst)); + +initial begin + rst <= 1; + #10; + rst <= 0; + sw <= 16'b0000_0000_0000_0100; +end + +endmodule diff --git a/aps_.srcs/sources_1/new/alu_riscv.sv b/aps_.srcs/sources_1/new/alu_riscv.sv new file mode 100644 index 0000000..7a85261 --- /dev/null +++ b/aps_.srcs/sources_1/new/alu_riscv.sv @@ -0,0 +1,33 @@ +`timescale 1ns / 1ps +`include "defines.v" + +module alu_riscv ( + input [31:0] A, + input [31:0] B, + input [3:0] ALUOp, + output reg Flag, + output reg [31:0] Result +); + +always @* begin + case (ALUOp) + `ADD: begin Result = A + B; Flag = 0; end + `SUB: begin Result = A - B; Flag = 0; end + `SLL: begin Result = A << B; Flag = 0; end + `SLT: begin Result = $signed(A < B); Flag = 0; end + `SLTU: begin Result = A < B; Flag = 0; end + `XOR: begin Result = A ^ B; Flag = 0; end + `SRL: begin Result = A >> B; Flag = 0; end + `SRA: begin Result = $signed(A) >>> B; Flag = 0; end + `OR: begin Result = A | B; Flag = 0; end + `AND: begin Result = A & B; Flag = 0; end + `BEQ: begin Result = 0; Flag = (A == B); end + `BNE: begin Result = 0; Flag = (A != B); end + `BLT: begin Result = 0; Flag = $signed(A < B); end + `BGE: begin Result = 0; Flag = $signed(A >= B); end + `BLTU: begin Result = 0; Flag = (A < B); end + `BGEU: begin Result = 0; Flag = (A >= B); end + default: begin Result = 0; Flag = 0; end + endcase +end +endmodule \ No newline at end of file diff --git a/aps_.srcs/sources_1/new/cpu_top.sv b/aps_.srcs/sources_1/new/cpu_top.sv new file mode 100644 index 0000000..370865a --- /dev/null +++ b/aps_.srcs/sources_1/new/cpu_top.sv @@ -0,0 +1,69 @@ +`timescale 1ns / 1ps +`include "defines.v" + +module cpu_top ( + input CLK100MHZ, + input [15:0] SW, + input rst, + output [15:0] LED +); +// alu +logic ALU_flag; +logic [`WORD_LEN-1:0] ALU_res; +// pc +parameter COUNTER_WIDTH = $clog2(`INSTR_DEPTH); +logic [COUNTER_WIDTH-1:0] PC; +// switches +logic [`WORD_LEN-1:0] extended_switch; +assign extended_switch = {{(`WORD_LEN - 15) {SW[14]}}, SW[14:0]}; +// instruction memory +logic [`WORD_LEN-1:0] instruction; +instruction_memory im( + .A(PC), + .D(instruction) +); +// constant +logic [`WORD_LEN-1:0] extended_const; +assign extended_const = {{(`WORD_LEN - `CONST_LEN) {instruction[`CONST+(`CONST_LEN-1)]}},instruction[`CONST]}; +// rf +logic [`WORD_LEN-1:0] rd1; +logic [`WORD_LEN-1:0] rd2; +logic [`WORD_LEN-1:0] wd; +// wd multiplexer +always_comb begin + case (instruction[`WS]) + 2'b01: wd = extended_switch; + 2'b10: wd = extended_const; + 2'b11: wd = ALU_res; + default: wd = 0; + endcase +end +// connection +rf_riscv rf ( + .clk (CLK100MHZ), + .adr_1(instruction[`RA1]), + .adr_2(instruction[`RA2]), + .adr_3(instruction[`WA]), + .wd (wd), + .we (instruction[29] | instruction[28]), + .rd_1(rd1), + .rd_2(rd2) +); +// PC +always_ff @(posedge CLK100MHZ) begin + if (rst)PC <= 0; + else if ((instruction[`C] & ALU_flag) | instruction[`B]) PC <= PC + extended_const; + else PC <= PC + 1; +end +// ALU +alu_riscv alu ( + .A(rd1), + .B(rd2), + .ALUOp(instruction[`ALUOp]), + .Flag (ALU_flag), + .Result(ALU_res) +); + +assign LED[15:0] = rd1[15:0]; + +endmodule diff --git a/aps_.srcs/sources_1/new/defines.v b/aps_.srcs/sources_1/new/defines.v new file mode 100644 index 0000000..522c642 --- /dev/null +++ b/aps_.srcs/sources_1/new/defines.v @@ -0,0 +1,54 @@ + +`define ADD 5'b00000 +`define SUB 5'b01000 +`define SLL 5'b00001 +`define SLT 5'b00010 +`define SLTU 5'b00011 +`define XOR 5'b00100 +`define SRL 5'b00101 +`define SRA 5'b01101 +`define OR 5'b00110 +`define AND 5'b00111 +`define BEQ 5'b11000 +`define BNE 5'b11001 +`define BLT 5'b11100 +`define BGE 5'b11101 +`define BLTU 5'b11110 +`define BGEU 5'b11111 + +//`define ADD 4'b0000 +//`define SUB 4'b0001 +//`define SLL 4'b0010 +//`define SLT 4'b0011 +//`define SLTU 4'b0100 +//`define XOR 4'b0101 +//`define SRL 4'b0110 +//`define SRA 4'b0111 +//`define OR 4'b1000 +//`define AND 4'b1001 +//`define BEQ 4'b1100 +//`define BNE 4'b1010 +//`define BLT 4'b1011 +//`define BGE 4'b1101 +//`define BLTU 4'b1110 +//`define BGEU 4'b1111 + +`define WORD_LEN 32 + +`define ALU_OP_LEN 4 +`define ALU_OP_NUM 16 + +`define INSTR_WIDTH 32 +`define INSTR_DEPTH 64 + +`define CONST_LEN 8 + +`define CONST 12:5 +`define WA 4:0 +`define RA1 22:18 +`define RA2 17:13 +`define ALUOp 27:23 +`define WS 29:28 +`define C 30 +`define B 31 + diff --git a/aps_.srcs/sources_1/new/instruction_memory.sv b/aps_.srcs/sources_1/new/instruction_memory.sv new file mode 100644 index 0000000..0b70acf --- /dev/null +++ b/aps_.srcs/sources_1/new/instruction_memory.sv @@ -0,0 +1,16 @@ +`timescale 1ns / 1ps + +module instruction_memory #( + int WIDTH = 32, + int DEPTH = 64 +)( + input [$clog2(DEPTH)-1:0] A, + output [WIDTH-1:0] D +); + + logic [WIDTH-1:0]ROM[0:DEPTH-1]; + initial $readmemb("prog.txt", ROM, 0, DEPTH-1); + + assign D = ROM[A]; + +endmodule diff --git a/aps_.srcs/sources_1/new/prog.txt b/aps_.srcs/sources_1/new/prog.txt new file mode 100644 index 0000000..80ff991 --- /dev/null +++ b/aps_.srcs/sources_1/new/prog.txt @@ -0,0 +1,4 @@ +0_0_01_00000_00000_00000_00000000_00001 +0_0_10_00000_00000_00000_00000101_00010 +0_0_11_00000_00001_00010_00000000_00011 +1_0_00_00000_00011_00000_00000000_00000 diff --git a/aps_.srcs/sources_1/new/rf_riscv.sv b/aps_.srcs/sources_1/new/rf_riscv.sv new file mode 100644 index 0000000..1aa9736 --- /dev/null +++ b/aps_.srcs/sources_1/new/rf_riscv.sv @@ -0,0 +1,23 @@ +`timescale 1ns / 1ps + +module rf_riscv( + input clk, + input [4:0] adr_1, + input [4:0] adr_2, + input [4:0] adr_3, + input [31:0] wd, + input we, + output [31:0] rd_1, + output [31:0] rd_2 +); +// indexing 0-31 or 31-0? +logic [31:0] RAM [0:31]; + +assign rd_1 = (adr_1 == 0) ? 0 : RAM[adr_1]; +assign rd_2 = (adr_2 == 0) ? 0 : RAM[adr_2]; + +always_ff @(posedge clk) begin + if (we && adr_3) RAM[adr_3] <= wd; +end + +endmodule diff --git a/aps_.xpr b/aps_.xpr new file mode 100644 index 0000000..7eab4a2 --- /dev/null +++ b/aps_.xpr @@ -0,0 +1,288 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/desktop.ini b/desktop.ini new file mode 100644 index 0000000..ab17096 --- /dev/null +++ b/desktop.ini @@ -0,0 +1,4 @@ +[ViewState] +Mode= +Vid= +FolderType=Documents diff --git a/top_tb_behav.wcfg b/top_tb_behav.wcfg new file mode 100644 index 0000000..51d78dd --- /dev/null +++ b/top_tb_behav.wcfg @@ -0,0 +1,47 @@ + + + + + + + + + + + + + + + + + + + + + + + + CLK + CLK + + + sw[15:0] + sw[15:0] + + + leds[15:0] + leds[15:0] + + + PERIOD[31:0] + PERIOD[31:0] + + + instruction[31:0] + instruction[31:0] + + + pc[4:0] + pc[4:0] + + diff --git a/vivado.jou b/vivado.jou new file mode 100644 index 0000000..8909100 --- /dev/null +++ b/vivado.jou @@ -0,0 +1,58 @@ +#----------------------------------------------------------- +# Vivado v2019.1 (64-bit) +# SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 +# IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 +# Start of session at: Thu Oct 20 20:09:12 2022 +# Process ID: 22044 +# Current directory: C:/Users/Alex/APS/aps_ +# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent21664 C:\Users\Alex\APS\aps_\aps_.xpr +# Log file: C:/Users/Alex/APS/aps_/vivado.log +# Journal file: C:/Users/Alex/APS/aps_\vivado.jou +#----------------------------------------------------------- +start_gui +open_project C:/Users/Alex/APS/aps_/aps_.xpr +launch_simulation +source top_tb.tcl +close_sim +launch_simulation +source top_tb.tcl +run all +run all +close_sim +launch_simulation +source top_tb.tcl +close_sim +launch_simulation +source top_tb.tcl +run all +close_sim +launch_simulation +source top_tb.tcl +run all +close_sim +launch_simulation +source top_tb.tcl +run 10 us +run 10 us +run 10 us +run 10 us +run 10 us +run 10 us +run 10 us +run 10 us +run 10 us +run 10 us +run 10 us +run 10 us +run 10 us +run 10 us +run 10 us +run 10 us +close_sim +launch_simulation +source top_tb.tcl +run all +close_sim +launch_simulation +source top_tb.tcl +close_sim diff --git a/vivado.log b/vivado.log new file mode 100644 index 0000000..3556dd2 --- /dev/null +++ b/vivado.log @@ -0,0 +1,537 @@ +#----------------------------------------------------------- +# Vivado v2019.1 (64-bit) +# SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 +# IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 +# Start of session at: Thu Oct 20 20:09:12 2022 +# Process ID: 22044 +# Current directory: C:/Users/Alex/APS/aps_ +# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent21664 C:\Users\Alex\APS\aps_\aps_.xpr +# Log file: C:/Users/Alex/APS/aps_/vivado.log +# Journal file: C:/Users/Alex/APS/aps_\vivado.jou +#----------------------------------------------------------- +start_gui +open_project C:/Users/Alex/APS/aps_/aps_.xpr +Scanning sources... +Finished scanning sources +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1704] No user IP repositories specified +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2019.1/data/ip'. +open_project: Time (s): cpu = 00:00:12 ; elapsed = 00:00:05 . Memory (MB): peak = 730.895 ; gain = 103.430 +launch_simulation +INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim' +INFO: [SIM-utils-51] Simulation object is 'sim_1' +INFO: [SIM-utils-54] Inspecting design source files for 'top_tb' in fileset 'sim_1'... +INFO: [SIM-utils-43] Exported 'C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim/prog.txt' +INFO: [USF-XSim-97] Finding global include files... +INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)... +INFO: [USF-XSim-101] Fetching design files from 'sim_1'... +INFO: [USF-XSim-2] XSim::Compile design +INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim' +"xvlog --incr --relax -prj top_tb_vlog.prj" +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/Users/Alex/APS/aps_/aps_.srcs/sources_1/new/alu_riscv.sv" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module alu_riscv +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/Users/Alex/APS/aps_/aps_.srcs/sources_1/new/rf_riscv.sv" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module rf_riscv +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/Users/Alex/APS/aps_/aps_.srcs/sources_1/new/instruction_memory.sv" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module instruction_memory +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/Users/Alex/APS/aps_/aps_.srcs/sources_1/new/cpu_top.sv" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module cpu_top +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/Users/Alex/APS/aps_/aps_.srcs/sim_1/new/alu_riscv_tb.sv" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module alu_riscv_tb +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/Users/Alex/APS/aps_/aps_.srcs/sim_1/new/rf_tb.sv" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module rf_tb +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/Users/Alex/APS/aps_/aps_.srcs/sim_1/new/top_tb.sv" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module top_tb +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/Users/Alex/APS/aps_/aps_.srcs/sim_1/new/im_tb.sv" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module im_tb +INFO: [USF-XSim-69] 'compile' step finished in '2' seconds +INFO: [USF-XSim-3] XSim::Elaborate design +INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim' +"xelab -wto 88fd13c424e241a2b1d7269d9396082e --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_tb_behav xil_defaultlib.top_tb xil_defaultlib.glbl -log elaborate.log" +Vivado Simulator 2019.1 +Copyright 1986-1999, 2001-2019 Xilinx, Inc. All Rights Reserved. +Running: C:/Xilinx/Vivado/2019.1/bin/unwrapped/win64.o/xelab.exe -wto 88fd13c424e241a2b1d7269d9396082e --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_tb_behav xil_defaultlib.top_tb xil_defaultlib.glbl -log elaborate.log +Using 2 slave threads. +Starting static elaboration +WARNING: [VRFC 10-3091] actual bit length 5 differs from formal bit length 4 for port 'ALUOp' [C:/Users/Alex/APS/aps_/aps_.srcs/sources_1/new/cpu_top.sv:62] +Completed static elaboration +Starting simulation data flow analysis +Completed simulation data flow analysis +Time Resolution for simulation is 1ps +Compiling module xil_defaultlib.instruction_memory +Compiling module xil_defaultlib.rf_riscv +Compiling module xil_defaultlib.alu_riscv +Compiling module xil_defaultlib.cpu_top +Compiling module xil_defaultlib.top_tb +Compiling module xil_defaultlib.glbl +Built simulation snapshot top_tb_behav + +****** Webtalk v2019.1 (64-bit) + **** SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 + **** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 + ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. + +source C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim/xsim.dir/top_tb_behav/webtalk/xsim_webtalk.tcl -notrace +INFO: [Common 17-206] Exiting Webtalk at Thu Oct 20 20:10:22 2022... +run_program: Time (s): cpu = 00:00:01 ; elapsed = 00:00:05 . Memory (MB): peak = 757.840 ; gain = 0.000 +INFO: [USF-XSim-69] 'elaborate' step finished in '5' seconds +INFO: [USF-XSim-4] XSim::Simulate design +INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim' +INFO: [USF-XSim-98] *** Running xsim + with args "top_tb_behav -key {Behavioral:sim_1:Functional:top_tb} -tclbatch {top_tb.tcl} -log {simulate.log}" +INFO: [USF-XSim-8] Loading simulator feature +Vivado Simulator 2019.1 +Time resolution is 1 ps +source top_tb.tcl +# set curr_wave [current_wave_config] +# if { [string length $curr_wave] == 0 } { +# if { [llength [get_objects]] > 0} { +# add_wave / +# set_property needs_save false [current_wave_config] +# } else { +# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." +# } +# } +# run 1000ns +INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_tb_behav' loaded. +INFO: [USF-XSim-97] XSim simulation ran for 1000ns +launch_simulation: Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 772.727 ; gain = 14.887 +WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [C:/Users/Alex/APS/aps_/aps_.srcs/sim_1/new/top_tb.sv:] +WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [C:/Users/Alex/APS/aps_/aps_.srcs/sources_1/new/cpu_top.sv:] +ERROR: [Common 17-180] Spawn failed: No error +close_sim +INFO: [Simtcl 6-16] Simulation closed +launch_simulation +INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim' +INFO: [SIM-utils-51] Simulation object is 'sim_1' +INFO: [SIM-utils-54] Inspecting design source files for 'top_tb' in fileset 'sim_1'... +INFO: [SIM-utils-43] Exported 'C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim/prog.txt' +INFO: [USF-XSim-97] Finding global include files... +INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)... +INFO: [USF-XSim-101] Fetching design files from 'sim_1'... +INFO: [USF-XSim-2] XSim::Compile design +INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim' +"xvlog --incr --relax -prj top_tb_vlog.prj" +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/Users/Alex/APS/aps_/aps_.srcs/sim_1/new/im_tb.sv" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module im_tb +INFO: [USF-XSim-69] 'compile' step finished in '2' seconds +INFO: [USF-XSim-3] XSim::Elaborate design +INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim' +"xelab -wto 88fd13c424e241a2b1d7269d9396082e --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_tb_behav xil_defaultlib.top_tb xil_defaultlib.glbl -log elaborate.log" +Vivado Simulator 2019.1 +Copyright 1986-1999, 2001-2019 Xilinx, Inc. All Rights Reserved. +Running: C:/Xilinx/Vivado/2019.1/bin/unwrapped/win64.o/xelab.exe -wto 88fd13c424e241a2b1d7269d9396082e --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_tb_behav xil_defaultlib.top_tb xil_defaultlib.glbl -log elaborate.log +Using 2 slave threads. +Starting static elaboration +WARNING: [VRFC 10-3091] actual bit length 5 differs from formal bit length 4 for port 'ALUOp' [C:/Users/Alex/APS/aps_/aps_.srcs/sources_1/new/cpu_top.sv:62] +Completed static elaboration +INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel +INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds +INFO: [USF-XSim-4] XSim::Simulate design +INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim' +INFO: [USF-XSim-98] *** Running xsim + with args "top_tb_behav -key {Behavioral:sim_1:Functional:top_tb} -tclbatch {top_tb.tcl} -log {simulate.log}" +INFO: [USF-XSim-8] Loading simulator feature +Vivado Simulator 2019.1 +Time resolution is 1 ps +source top_tb.tcl +# set curr_wave [current_wave_config] +# if { [string length $curr_wave] == 0 } { +# if { [llength [get_objects]] > 0} { +# add_wave / +# set_property needs_save false [current_wave_config] +# } else { +# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." +# } +# } +# run 1000ns +INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_tb_behav' loaded. +INFO: [USF-XSim-97] XSim simulation ran for 1000ns +launch_simulation: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 831.754 ; gain = 0.000 +run all +run: Time (s): cpu = 00:00:47 ; elapsed = 00:00:37 . Memory (MB): peak = 831.754 ; gain = 0.000 +run all +run: Time (s): cpu = 00:00:23 ; elapsed = 00:00:19 . Memory (MB): peak = 832.652 ; gain = 0.000 +close_sim +INFO: [Simtcl 6-16] Simulation closed +close_sim: Time (s): cpu = 00:00:02 ; elapsed = 00:00:06 . Memory (MB): peak = 833.211 ; gain = 0.000 +launch_simulation +INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim' +INFO: [SIM-utils-51] Simulation object is 'sim_1' +INFO: [SIM-utils-54] Inspecting design source files for 'top_tb' in fileset 'sim_1'... +INFO: [SIM-utils-43] Exported 'C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim/prog.txt' +INFO: [USF-XSim-97] Finding global include files... +INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)... +INFO: [USF-XSim-101] Fetching design files from 'sim_1'... +INFO: [USF-XSim-2] XSim::Compile design +INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim' +"xvlog --incr --relax -prj top_tb_vlog.prj" +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/Users/Alex/APS/aps_/aps_.srcs/sources_1/new/alu_riscv.sv" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module alu_riscv +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/Users/Alex/APS/aps_/aps_.srcs/sources_1/new/rf_riscv.sv" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module rf_riscv +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/Users/Alex/APS/aps_/aps_.srcs/sources_1/new/instruction_memory.sv" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module instruction_memory +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/Users/Alex/APS/aps_/aps_.srcs/sources_1/new/cpu_top.sv" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module cpu_top +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/Users/Alex/APS/aps_/aps_.srcs/sim_1/new/alu_riscv_tb.sv" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module alu_riscv_tb +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/Users/Alex/APS/aps_/aps_.srcs/sim_1/new/rf_tb.sv" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module rf_tb +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/Users/Alex/APS/aps_/aps_.srcs/sim_1/new/top_tb.sv" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module top_tb +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/Users/Alex/APS/aps_/aps_.srcs/sim_1/new/im_tb.sv" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module im_tb +INFO: [USF-XSim-69] 'compile' step finished in '2' seconds +INFO: [USF-XSim-3] XSim::Elaborate design +INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim' +"xelab -wto 88fd13c424e241a2b1d7269d9396082e --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_tb_behav xil_defaultlib.top_tb xil_defaultlib.glbl -log elaborate.log" +Vivado Simulator 2019.1 +Copyright 1986-1999, 2001-2019 Xilinx, Inc. All Rights Reserved. +Running: C:/Xilinx/Vivado/2019.1/bin/unwrapped/win64.o/xelab.exe -wto 88fd13c424e241a2b1d7269d9396082e --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_tb_behav xil_defaultlib.top_tb xil_defaultlib.glbl -log elaborate.log +Using 2 slave threads. +Starting static elaboration +WARNING: [VRFC 10-3091] actual bit length 5 differs from formal bit length 4 for port 'ALUOp' [C:/Users/Alex/APS/aps_/aps_.srcs/sources_1/new/cpu_top.sv:62] +Completed static elaboration +Starting simulation data flow analysis +Completed simulation data flow analysis +Time Resolution for simulation is 1ps +Compiling module xil_defaultlib.instruction_memory +Compiling module xil_defaultlib.rf_riscv +Compiling module xil_defaultlib.alu_riscv +Compiling module xil_defaultlib.cpu_top +Compiling module xil_defaultlib.top_tb +Compiling module xil_defaultlib.glbl +Built simulation snapshot top_tb_behav +INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds +INFO: [USF-XSim-4] XSim::Simulate design +INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim' +INFO: [USF-XSim-98] *** Running xsim + with args "top_tb_behav -key {Behavioral:sim_1:Functional:top_tb} -tclbatch {top_tb.tcl} -log {simulate.log}" +INFO: [USF-XSim-8] Loading simulator feature +Vivado Simulator 2019.1 +Time resolution is 1 ps +source top_tb.tcl +# set curr_wave [current_wave_config] +# if { [string length $curr_wave] == 0 } { +# if { [llength [get_objects]] > 0} { +# add_wave / +# set_property needs_save false [current_wave_config] +# } else { +# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." +# } +# } +# run 1000ns +INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_tb_behav' loaded. +INFO: [USF-XSim-97] XSim simulation ran for 1000ns +launch_simulation: Time (s): cpu = 00:00:05 ; elapsed = 00:00:07 . Memory (MB): peak = 833.211 ; gain = 0.000 +close_sim +INFO: [Simtcl 6-16] Simulation closed +launch_simulation +INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim' +INFO: [SIM-utils-51] Simulation object is 'sim_1' +INFO: [SIM-utils-54] Inspecting design source files for 'top_tb' in fileset 'sim_1'... +INFO: [SIM-utils-43] Exported 'C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim/prog.txt' +INFO: [USF-XSim-97] Finding global include files... +INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)... +INFO: [USF-XSim-101] Fetching design files from 'sim_1'... +INFO: [USF-XSim-2] XSim::Compile design +INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim' +"xvlog --incr --relax -prj top_tb_vlog.prj" +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/Users/Alex/APS/aps_/aps_.srcs/sources_1/new/alu_riscv.sv" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module alu_riscv +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/Users/Alex/APS/aps_/aps_.srcs/sources_1/new/rf_riscv.sv" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module rf_riscv +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/Users/Alex/APS/aps_/aps_.srcs/sources_1/new/instruction_memory.sv" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module instruction_memory +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/Users/Alex/APS/aps_/aps_.srcs/sources_1/new/cpu_top.sv" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module cpu_top +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/Users/Alex/APS/aps_/aps_.srcs/sim_1/new/alu_riscv_tb.sv" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module alu_riscv_tb +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/Users/Alex/APS/aps_/aps_.srcs/sim_1/new/rf_tb.sv" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module rf_tb +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/Users/Alex/APS/aps_/aps_.srcs/sim_1/new/top_tb.sv" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module top_tb +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/Users/Alex/APS/aps_/aps_.srcs/sim_1/new/im_tb.sv" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module im_tb +INFO: [USF-XSim-69] 'compile' step finished in '1' seconds +INFO: [USF-XSim-3] XSim::Elaborate design +INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim' +"xelab -wto 88fd13c424e241a2b1d7269d9396082e --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_tb_behav xil_defaultlib.top_tb xil_defaultlib.glbl -log elaborate.log" +Vivado Simulator 2019.1 +Copyright 1986-1999, 2001-2019 Xilinx, Inc. All Rights Reserved. +Running: C:/Xilinx/Vivado/2019.1/bin/unwrapped/win64.o/xelab.exe -wto 88fd13c424e241a2b1d7269d9396082e --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_tb_behav xil_defaultlib.top_tb xil_defaultlib.glbl -log elaborate.log +Using 2 slave threads. +Starting static elaboration +WARNING: [VRFC 10-3091] actual bit length 5 differs from formal bit length 4 for port 'ALUOp' [C:/Users/Alex/APS/aps_/aps_.srcs/sources_1/new/cpu_top.sv:62] +Completed static elaboration +Starting simulation data flow analysis +Completed simulation data flow analysis +Time Resolution for simulation is 1ps +Compiling module xil_defaultlib.instruction_memory +Compiling module xil_defaultlib.rf_riscv +Compiling module xil_defaultlib.alu_riscv +Compiling module xil_defaultlib.cpu_top +Compiling module xil_defaultlib.top_tb +Compiling module xil_defaultlib.glbl +Built simulation snapshot top_tb_behav +INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds +INFO: [USF-XSim-4] XSim::Simulate design +INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim' +INFO: [USF-XSim-98] *** Running xsim + with args "top_tb_behav -key {Behavioral:sim_1:Functional:top_tb} -tclbatch {top_tb.tcl} -log {simulate.log}" +INFO: [USF-XSim-8] Loading simulator feature +Vivado Simulator 2019.1 +Time resolution is 1 ps +source top_tb.tcl +# set curr_wave [current_wave_config] +# if { [string length $curr_wave] == 0 } { +# if { [llength [get_objects]] > 0} { +# add_wave / +# set_property needs_save false [current_wave_config] +# } else { +# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." +# } +# } +# run 1000ns +INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_tb_behav' loaded. +INFO: [USF-XSim-97] XSim simulation ran for 1000ns +launch_simulation: Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 835.363 ; gain = 0.000 +run all +run: Time (s): cpu = 00:00:18 ; elapsed = 00:00:15 . Memory (MB): peak = 835.363 ; gain = 0.000 +close_sim +INFO: [Simtcl 6-16] Simulation closed +launch_simulation +INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim' +INFO: [SIM-utils-51] Simulation object is 'sim_1' +INFO: [SIM-utils-54] Inspecting design source files for 'top_tb' in fileset 'sim_1'... +INFO: [SIM-utils-43] Exported 'C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim/prog.txt' +INFO: [USF-XSim-97] Finding global include files... +INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)... +INFO: [USF-XSim-101] Fetching design files from 'sim_1'... +INFO: [USF-XSim-2] XSim::Compile design +INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim' +"xvlog --incr --relax -prj top_tb_vlog.prj" +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/Users/Alex/APS/aps_/aps_.srcs/sources_1/new/alu_riscv.sv" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module alu_riscv +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/Users/Alex/APS/aps_/aps_.srcs/sources_1/new/rf_riscv.sv" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module rf_riscv +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/Users/Alex/APS/aps_/aps_.srcs/sources_1/new/instruction_memory.sv" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module instruction_memory +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/Users/Alex/APS/aps_/aps_.srcs/sources_1/new/cpu_top.sv" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module cpu_top +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/Users/Alex/APS/aps_/aps_.srcs/sim_1/new/alu_riscv_tb.sv" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module alu_riscv_tb +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/Users/Alex/APS/aps_/aps_.srcs/sim_1/new/rf_tb.sv" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module rf_tb +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/Users/Alex/APS/aps_/aps_.srcs/sim_1/new/top_tb.sv" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module top_tb +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/Users/Alex/APS/aps_/aps_.srcs/sim_1/new/im_tb.sv" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module im_tb +INFO: [USF-XSim-69] 'compile' step finished in '2' seconds +INFO: [USF-XSim-3] XSim::Elaborate design +INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim' +"xelab -wto 88fd13c424e241a2b1d7269d9396082e --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_tb_behav xil_defaultlib.top_tb xil_defaultlib.glbl -log elaborate.log" +Vivado Simulator 2019.1 +Copyright 1986-1999, 2001-2019 Xilinx, Inc. All Rights Reserved. +Running: C:/Xilinx/Vivado/2019.1/bin/unwrapped/win64.o/xelab.exe -wto 88fd13c424e241a2b1d7269d9396082e --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_tb_behav xil_defaultlib.top_tb xil_defaultlib.glbl -log elaborate.log +Using 2 slave threads. +Starting static elaboration +WARNING: [VRFC 10-3091] actual bit length 5 differs from formal bit length 4 for port 'ALUOp' [C:/Users/Alex/APS/aps_/aps_.srcs/sources_1/new/cpu_top.sv:62] +Completed static elaboration +Starting simulation data flow analysis +Completed simulation data flow analysis +Time Resolution for simulation is 1ps +Compiling module xil_defaultlib.instruction_memory +Compiling module xil_defaultlib.rf_riscv +Compiling module xil_defaultlib.alu_riscv +Compiling module xil_defaultlib.cpu_top +Compiling module xil_defaultlib.top_tb +Compiling module xil_defaultlib.glbl +Built simulation snapshot top_tb_behav +INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds +INFO: [USF-XSim-4] XSim::Simulate design +INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim' +INFO: [USF-XSim-98] *** Running xsim + with args "top_tb_behav -key {Behavioral:sim_1:Functional:top_tb} -tclbatch {top_tb.tcl} -log {simulate.log}" +INFO: [USF-XSim-8] Loading simulator feature +Vivado Simulator 2019.1 +Time resolution is 1 ps +source top_tb.tcl +# set curr_wave [current_wave_config] +# if { [string length $curr_wave] == 0 } { +# if { [llength [get_objects]] > 0} { +# add_wave / +# set_property needs_save false [current_wave_config] +# } else { +# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." +# } +# } +# run 1000ns +INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_tb_behav' loaded. +INFO: [USF-XSim-97] XSim simulation ran for 1000ns +launch_simulation: Time (s): cpu = 00:00:05 ; elapsed = 00:00:07 . Memory (MB): peak = 835.363 ; gain = 0.000 +run all +run: Time (s): cpu = 00:00:14 ; elapsed = 00:00:12 . Memory (MB): peak = 835.363 ; gain = 0.000 +close_sim +INFO: [Simtcl 6-16] Simulation closed +launch_simulation +INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim' +INFO: [SIM-utils-51] Simulation object is 'sim_1' +INFO: [SIM-utils-54] Inspecting design source files for 'top_tb' in fileset 'sim_1'... +INFO: [SIM-utils-43] Exported 'C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim/prog.txt' +INFO: [USF-XSim-97] Finding global include files... +INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)... +INFO: [USF-XSim-101] Fetching design files from 'sim_1'... +INFO: [USF-XSim-2] XSim::Compile design +INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim' +"xvlog --incr --relax -prj top_tb_vlog.prj" +INFO: [USF-XSim-69] 'compile' step finished in '2' seconds +INFO: [USF-XSim-3] XSim::Elaborate design +INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim' +"xelab -wto 88fd13c424e241a2b1d7269d9396082e --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_tb_behav xil_defaultlib.top_tb xil_defaultlib.glbl -log elaborate.log" +Vivado Simulator 2019.1 +Copyright 1986-1999, 2001-2019 Xilinx, Inc. All Rights Reserved. +Running: C:/Xilinx/Vivado/2019.1/bin/unwrapped/win64.o/xelab.exe -wto 88fd13c424e241a2b1d7269d9396082e --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_tb_behav xil_defaultlib.top_tb xil_defaultlib.glbl -log elaborate.log +Using 2 slave threads. +Starting static elaboration +WARNING: [VRFC 10-3091] actual bit length 5 differs from formal bit length 4 for port 'ALUOp' [C:/Users/Alex/APS/aps_/aps_.srcs/sources_1/new/cpu_top.sv:62] +Completed static elaboration +INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel +INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds +INFO: [USF-XSim-4] XSim::Simulate design +INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim' +INFO: [USF-XSim-98] *** Running xsim + with args "top_tb_behav -key {Behavioral:sim_1:Functional:top_tb} -tclbatch {top_tb.tcl} -log {simulate.log}" +INFO: [USF-XSim-8] Loading simulator feature +Vivado Simulator 2019.1 +Time resolution is 1 ps +source top_tb.tcl +# set curr_wave [current_wave_config] +# if { [string length $curr_wave] == 0 } { +# if { [llength [get_objects]] > 0} { +# add_wave / +# set_property needs_save false [current_wave_config] +# } else { +# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." +# } +# } +# run 1000ns +INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_tb_behav' loaded. +INFO: [USF-XSim-97] XSim simulation ran for 1000ns +launch_simulation: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 835.363 ; gain = 0.000 +run 10 us +run 10 us +run 10 us +run 10 us +run 10 us +run 10 us +run 10 us +run 10 us +run 10 us +run 10 us +run 10 us +run 10 us +run 10 us +run 10 us +run 10 us +run 10 us +close_sim +INFO: [Simtcl 6-16] Simulation closed +launch_simulation +INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim' +INFO: [SIM-utils-51] Simulation object is 'sim_1' +INFO: [SIM-utils-54] Inspecting design source files for 'top_tb' in fileset 'sim_1'... +INFO: [SIM-utils-43] Exported 'C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim/prog.txt' +INFO: [USF-XSim-97] Finding global include files... +INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)... +INFO: [USF-XSim-101] Fetching design files from 'sim_1'... +INFO: [USF-XSim-2] XSim::Compile design +INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim' +"xvlog --incr --relax -prj top_tb_vlog.prj" +INFO: [USF-XSim-69] 'compile' step finished in '2' seconds +INFO: [USF-XSim-3] XSim::Elaborate design +INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim' +"xelab -wto 88fd13c424e241a2b1d7269d9396082e --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_tb_behav xil_defaultlib.top_tb xil_defaultlib.glbl -log elaborate.log" +Vivado Simulator 2019.1 +Copyright 1986-1999, 2001-2019 Xilinx, Inc. All Rights Reserved. +Running: C:/Xilinx/Vivado/2019.1/bin/unwrapped/win64.o/xelab.exe -wto 88fd13c424e241a2b1d7269d9396082e --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_tb_behav xil_defaultlib.top_tb xil_defaultlib.glbl -log elaborate.log +Using 2 slave threads. +Starting static elaboration +WARNING: [VRFC 10-3091] actual bit length 5 differs from formal bit length 4 for port 'ALUOp' [C:/Users/Alex/APS/aps_/aps_.srcs/sources_1/new/cpu_top.sv:62] +Completed static elaboration +INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel +INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds +INFO: [USF-XSim-4] XSim::Simulate design +INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim' +INFO: [USF-XSim-98] *** Running xsim + with args "top_tb_behav -key {Behavioral:sim_1:Functional:top_tb} -tclbatch {top_tb.tcl} -log {simulate.log}" +INFO: [USF-XSim-8] Loading simulator feature +Vivado Simulator 2019.1 +Time resolution is 1 ps +source top_tb.tcl +# set curr_wave [current_wave_config] +# if { [string length $curr_wave] == 0 } { +# if { [llength [get_objects]] > 0} { +# add_wave / +# set_property needs_save false [current_wave_config] +# } else { +# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." +# } +# } +# run 1000ns +INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_tb_behav' loaded. +INFO: [USF-XSim-97] XSim simulation ran for 1000ns +launch_simulation: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 839.559 ; gain = 0.000 +run all +run: Time (s): cpu = 00:00:14 ; elapsed = 00:00:12 . Memory (MB): peak = 839.559 ; gain = 0.000 +close_sim +INFO: [Simtcl 6-16] Simulation closed +launch_simulation +INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim' +INFO: [SIM-utils-51] Simulation object is 'sim_1' +INFO: [SIM-utils-54] Inspecting design source files for 'top_tb' in fileset 'sim_1'... +INFO: [SIM-utils-43] Exported 'C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim/prog.txt' +INFO: [USF-XSim-97] Finding global include files... +INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)... +INFO: [USF-XSim-101] Fetching design files from 'sim_1'... +INFO: [USF-XSim-2] XSim::Compile design +INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim' +"xvlog --incr --relax -prj top_tb_vlog.prj" +INFO: [USF-XSim-69] 'compile' step finished in '2' seconds +INFO: [USF-XSim-3] XSim::Elaborate design +INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim' +"xelab -wto 88fd13c424e241a2b1d7269d9396082e --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_tb_behav xil_defaultlib.top_tb xil_defaultlib.glbl -log elaborate.log" +Vivado Simulator 2019.1 +Copyright 1986-1999, 2001-2019 Xilinx, Inc. All Rights Reserved. +Running: C:/Xilinx/Vivado/2019.1/bin/unwrapped/win64.o/xelab.exe -wto 88fd13c424e241a2b1d7269d9396082e --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_tb_behav xil_defaultlib.top_tb xil_defaultlib.glbl -log elaborate.log +Using 2 slave threads. +Starting static elaboration +WARNING: [VRFC 10-3091] actual bit length 5 differs from formal bit length 4 for port 'ALUOp' [C:/Users/Alex/APS/aps_/aps_.srcs/sources_1/new/cpu_top.sv:62] +Completed static elaboration +INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel +INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds +INFO: [USF-XSim-4] XSim::Simulate design +INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim' +INFO: [USF-XSim-98] *** Running xsim + with args "top_tb_behav -key {Behavioral:sim_1:Functional:top_tb} -tclbatch {top_tb.tcl} -log {simulate.log}" +INFO: [USF-XSim-8] Loading simulator feature +Vivado Simulator 2019.1 +Time resolution is 1 ps +source top_tb.tcl +# set curr_wave [current_wave_config] +# if { [string length $curr_wave] == 0 } { +# if { [llength [get_objects]] > 0} { +# add_wave / +# set_property needs_save false [current_wave_config] +# } else { +# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." +# } +# } +# run 1000ns +INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_tb_behav' loaded. +INFO: [USF-XSim-97] XSim simulation ran for 1000ns +launch_simulation: Time (s): cpu = 00:00:05 ; elapsed = 00:00:07 . Memory (MB): peak = 839.559 ; gain = 0.000 +close_sim +INFO: [Simtcl 6-16] Simulation closed +close_sim: Time (s): cpu = 00:00:04 ; elapsed = 00:00:10 . Memory (MB): peak = 839.988 ; gain = 0.430 diff --git a/vivado_pid22044.str b/vivado_pid22044.str new file mode 100644 index 0000000..74c6120 --- /dev/null +++ b/vivado_pid22044.str @@ -0,0 +1,2583 @@ +/* + +Xilinx Vivado v2019.1 (64-bit) [Major: 2019, Minor: 1] +SW Build: 2552052 on Fri May 24 14:49:42 MDT 2019 +IP Build: 2548770 on Fri May 24 18:01:18 MDT 2019 + +Process ID (PID): 22044 +License: Customer + +Current time: Thu Oct 20 20:09:28 MSK 2022 +Time zone: Moscow Standard Time (Europe/Moscow) + +OS: Windows 10 +OS Version: 10.0 +OS Architecture: amd64 +Available processors (cores): 12 + +Screen size: 1920x1080 +Screen resolution (DPI): 100 +Available screens: 1 +Available disk space: 56 GB +Default font: family=Dialog,name=Dialog,style=plain,size=12 + +Java version: 9.0.4 64-bit +Java home: C:/Xilinx/Vivado/2019.1/tps/win64/jre9.0.4 +Java executable location: C:/Xilinx/Vivado/2019.1/tps/win64/jre9.0.4/bin/java.exe +Java initial memory (-Xms): 128 MB +Java maximum memory (-Xmx): 3 GB + + +User name: Alex +User home directory: C:/Users/Alex +User working directory: C:/Users/Alex/APS/aps_ +User country: RU +User language: ru +User locale: ru_RU + +RDI_BASEROOT: C:/Xilinx/Vivado +HDI_APPROOT: C:/Xilinx/Vivado/2019.1 +RDI_DATADIR: C:/Xilinx/Vivado/2019.1/data +RDI_BINDIR: C:/Xilinx/Vivado/2019.1/bin + +Vivado preferences file location: C:/Users/Alex/AppData/Roaming/Xilinx/Vivado/2019.1/vivado.xml +Vivado preferences directory: C:/Users/Alex/AppData/Roaming/Xilinx/Vivado/2019.1/ +Vivado layouts directory: C:/Users/Alex/AppData/Roaming/Xilinx/Vivado/2019.1/layouts +PlanAhead jar file location: C:/Xilinx/Vivado/2019.1/lib/classes/planAhead.jar +Vivado log file location: C:/Users/Alex/APS/aps_/vivado.log +Vivado journal file location: C:/Users/Alex/APS/aps_/vivado.jou +Engine tmp dir: C:/Users/Alex/APS/aps_/.Xil/Vivado-22044-DESKTOP-G9CJ5KV + +Xilinx Environment Variables +---------------------------- +XILINX: C:/Xilinx/Vivado/2019.1/ids_lite/ISE +XILINX_DSP: C:/Xilinx/Vivado/2019.1/ids_lite/ISE +XILINX_PLANAHEAD: C:/Xilinx/Vivado/2019.1 +XILINX_SDK: C:/Xilinx/SDK/2019.1 +XILINX_VIVADO: C:/Xilinx/Vivado/2019.1 +XILINX_VIVADO_HLS: C:/Xilinx/Vivado/2019.1 + + +GUI allocated memory: 195 MB +GUI max memory: 3,072 MB +Engine allocated memory: 699 MB + +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. + +*/ + +// TclEventType: START_GUI +// Tcl Message: start_gui +// TclEventType: PROJECT_OPEN_DIALOG +// by (cl): Open Project : addNotify +// Opening Vivado Project: C:\Users\Alex\APS\aps_\aps_.xpr. Version: Vivado v2019.1 +// TclEventType: DEBUG_PROBE_SET_CHANGE +// Tcl Message: open_project C:/Users/Alex/APS/aps_/aps_.xpr +// TclEventType: MSGMGR_MOVEMSG +// TclEventType: FILE_SET_NEW +// TclEventType: RUN_COMPLETED +// TclEventType: RUN_STATUS_CHANGE +// TclEventType: RUN_CURRENT +// TclEventType: PROJECT_DASHBOARD_NEW +// TclEventType: PROJECT_DASHBOARD_GADGET_NEW +// TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE +// TclEventType: PROJECT_DASHBOARD_GADGET_NEW +// TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE +// TclEventType: PROJECT_DASHBOARD_GADGET_NEW +// TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE +// TclEventType: PROJECT_DASHBOARD_GADGET_NEW +// TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE +// TclEventType: PROJECT_DASHBOARD_GADGET_NEW +// TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE +// TclEventType: PROJECT_DASHBOARD_GADGET_NEW +// TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE +// TclEventType: PROJECT_NEW +// Tcl Message: open_project C:/Users/Alex/APS/aps_/aps_.xpr +// Tcl Message: Scanning sources... Finished scanning sources +// Tcl Message: INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified +// TclEventType: PROJECT_NEW +// [GUI Memory]: 94 MB (+96394kb) [00:00:09] +// [Engine Memory]: 639 MB (+518982kb) [00:00:09] +// [GUI Memory]: 110 MB (+11281kb) [00:00:09] +// [Engine Memory]: 684 MB (+13448kb) [00:00:11] +// WARNING: HEventQueue.dispatchEvent() is taking 3072 ms. +// Tcl Message: INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2019.1/data/ip'. +// HMemoryUtils.trashcanNow. Engine heap size: 699 MB. GUI used memory: 52 MB. Current time: 10/20/22, 8:09:29 PM MSK +// Tcl Message: open_project: Time (s): cpu = 00:00:12 ; elapsed = 00:00:05 . Memory (MB): peak = 730.895 ; gain = 103.430 +// Project name: aps_; location: C:/Users/Alex/APS/aps_; part: xc7a100tcsg324-1 +dismissDialog("Open Project"); // by (cl) +// PAPropertyPanels.initPanels (cpu_top.sv) elapsed time: 0.2s +selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, top_new (cpu_top.sv)]", 2, true); // B (F, cl) - Node +selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, top_new (cpu_top.sv)]", 2, true, false, false, false, false, true); // B (F, cl) - Double Click - Node +selectCodeEditor("cpu_top.sv", 99, 61); // cl (w, cl) +selectCodeEditor("cpu_top.sv", 705, 252); // cl (w, cl) +// TclEventType: DG_GRAPH_STALE +// TclEventType: FILE_SET_CHANGE +selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation Sources]", 8, true); // B (F, cl) - Node +selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation Sources]", 8, true, false, false, false, false, true); // B (F, cl) - Double Click - Node +selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation Sources, sim_1]", 9, true); // B (F, cl) - Node +expandTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation Sources, sim_1]", 6); // B (F, cl) +selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation Sources, sim_1, top_tb (top_tb.sv)]", 8, true); // B (F, cl) - Node +selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation Sources, sim_1, top_tb (top_tb.sv)]", 8, true, false, false, false, false, true); // B (F, cl) - Double Click - Node +selectCodeEditor("top_tb.sv", 90, 47); // cl (w, cl) +// HMemoryUtils.trashcanNow. Engine heap size: 729 MB. GUI used memory: 55 MB. Current time: 10/20/22, 8:09:57 PM MSK +selectCodeEditor("top_tb.sv", 215, 59); // cl (w, cl) +selectCodeEditor("top_tb.sv", 2, 299); // cl (w, cl) +// [Engine Memory]: 729 MB (+11315kb) [00:00:44] +selectCodeEditor("top_tb.sv", 562, 414); // cl (w, cl) +// TclEventType: DG_GRAPH_STALE +// TclEventType: FILE_SET_CHANGE +selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Simulation, Run Simulation]", 10, false); // u (O, cl) +selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Simulation, Run Simulation]", 10, false); // u (O, cl) +selectMenuItem(PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL, "Run Behavioral Simulation"); // ah (an, cl) +// Run Command: PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL +// e (cl): Run Simulation : addNotify +// TclEventType: LAUNCH_SIM +// TclEventType: FILE_SET_OPTIONS_CHANGE +// Tcl Message: launch_simulation +// Tcl Message: INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim' INFO: [SIM-utils-51] Simulation object is 'sim_1' INFO: [SIM-utils-54] Inspecting design source files for 'top_tb' in fileset 'sim_1'... INFO: [SIM-utils-43] Exported 'C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim/prog.txt' INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)... INFO: [USF-XSim-101] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design +// Tcl Message: INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim' +// Tcl Message: "xvlog --incr --relax -prj top_tb_vlog.prj" +// TclEventType: LAUNCH_SIM_LOG +// Tcl Message: INFO: [USF-XSim-69] 'compile' step finished in '2' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim' +// Tcl Message: "xelab -wto 88fd13c424e241a2b1d7269d9396082e --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_tb_behav xil_defaultlib.top_tb xil_defaultlib.glbl -log elaborate.log" +// TclEventType: LAUNCH_SIM +// TclEventType: LOAD_FEATURE +// Tcl Message: ****** Webtalk v2019.1 (64-bit) **** SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 **** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. source C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim/xsim.dir/top_tb_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Thu Oct 20 20:10:22 2022... +// Tcl Message: run_program: Time (s): cpu = 00:00:01 ; elapsed = 00:00:05 . Memory (MB): peak = 757.840 ; gain = 0.000 +// Tcl Message: INFO: [USF-XSim-69] 'elaborate' step finished in '5' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim' INFO: [USF-XSim-98] *** Running xsim +// Tcl Message: with args "top_tb_behav -key {Behavioral:sim_1:Functional:top_tb} -tclbatch {top_tb.tcl} -log {simulate.log}" +// Tcl Message: INFO: [USF-XSim-8] Loading simulator feature +// Tcl Message: Vivado Simulator 2019.1 +// TclEventType: SIMULATION_CREATE_SIMULATION_OBJECT +// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE +// TclEventType: SIMULATION_UPDATE_SCOPE_TREE +// TclEventType: SIMULATION_UPDATE_STACKS +// TclEventType: SIMULATION_UPDATE_OBJECT_TREE +// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE +// WARNING: HEventQueue.dispatchEvent() is taking 1236 ms. +// Tcl Message: Time resolution is 1 ps +// TclEventType: SIMULATION_UPDATE_SCOPE_TREE +// TclEventType: SIMULATION_UPDATE_STACKS +// TclEventType: SIMULATION_UPDATE_OBJECT_TREE +// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE +// TclEventType: SIMULATION_UPDATE_SCOPE_TREE +// TclEventType: SIMULATION_UPDATE_STACKS +// TclEventType: SIMULATION_UPDATE_OBJECT_TREE +// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE +// Elapsed time: 10 seconds +closeView(PAResourceOtoP.PAViews_PROJECT_SUMMARY, "Project Summary"); // v +// TclEventType: WAVEFORM_UPDATE_TITLE +// TclEventType: WAVEFORM_OPEN_WCFG +// TclEventType: SIMULATION_UPDATE_SCOPE_TREE +// TclEventType: SIMULATION_UPDATE_STACKS +// TclEventType: SIMULATION_UPDATE_OBJECT_TREE +// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE +// TclEventType: WAVEFORM_OPEN_WCFG +// TclEventType: WAVEFORM_DELAYED_MODEL_EVENT +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// Waveform: addNotify +// TclEventType: WAVEFORM_MODEL_EVENT +// Tcl Message: source top_tb.tcl +// Tcl Message: # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// HMemoryUtils.trashcanNow. Engine heap size: 738 MB. GUI used memory: 63 MB. Current time: 10/20/22, 8:10:26 PM MSK +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: WAVEFORM_UPDATE_TITLE +// TclEventType: WAVEFORM_DELAYED_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_TITLE +// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE +// TclEventType: SIMULATION_CLEAR_CURRENT_LINE +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// TclEventType: SIMULATION_OBJECT_TREE_RESTORED +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED +// TclEventType: SIMULATION_CURRENT_STACK_CHANGED +// TclEventType: SIMULATION_UPDATE_STACK_FRAMES +// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED +// TclEventType: SIMULATION_UPDATE_LOCALS +// TclEventType: SIMULATION_UPDATE_SCOPE_TREE +// TclEventType: SIMULATION_UPDATE_STACKS +// TclEventType: SIMULATION_UPDATE_OBJECT_TREE +// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE +// Tcl Message: # run 1000ns +// Tcl Message: INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_tb_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns +// Tcl Message: launch_simulation: Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 772.727 ; gain = 14.887 +// 'd' command handler elapsed time: 11 seconds +dismissDialog("Run Simulation"); // e (cl) +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// HMemoryUtils.trashcanNow. Engine heap size: 738 MB. GUI used memory: 110 MB. Current time: 10/20/22, 8:10:31 PM MSK +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// HMemoryUtils.trashcanNow. Engine heap size: 738 MB. GUI used memory: 63 MB. Current time: 10/20/22, 8:10:31 PM MSK +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// HMemoryUtils.trashcanNow. Engine heap size: 738 MB. GUI used memory: 63 MB. Current time: 10/20/22, 8:10:31 PM MSK +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// HMemoryUtils.trashcanNow. Engine heap size: 738 MB. GUI used memory: 63 MB. Current time: 10/20/22, 8:10:31 PM MSK +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// HMemoryUtils.trashcanNow. Engine heap size: 738 MB. GUI used memory: 63 MB. Current time: 10/20/22, 8:10:32 PM MSK +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +selectButton(RDIResource.GraphicalView_ZOOM_OUT, "Waveform Viewer_zoom_out"); // B (f, cl) +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// HMemoryUtils.trashcanNow. Engine heap size: 738 MB. GUI used memory: 63 MB. Current time: 10/20/22, 8:10:35 PM MSK +selectButton(RDIResource.GraphicalView_ZOOM_OUT, "Waveform Viewer_zoom_out"); // B (f, cl) +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// HMemoryUtils.trashcanNow. Engine heap size: 738 MB. GUI used memory: 63 MB. Current time: 10/20/22, 8:10:35 PM MSK +selectButton(RDIResource.GraphicalView_ZOOM_OUT, "Waveform Viewer_zoom_out"); // B (f, cl) +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +selectButton(RDIResource.GraphicalView_ZOOM_OUT, "Waveform Viewer_zoom_out"); // B (f, cl) +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// HMemoryUtils.trashcanNow. Engine heap size: 738 MB. GUI used memory: 63 MB. Current time: 10/20/22, 8:10:36 PM MSK +selectButton(RDIResource.GraphicalView_ZOOM_OUT, "Waveform Viewer_zoom_out"); // B (f, cl) +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +selectButton(RDIResource.GraphicalView_ZOOM_OUT, "Waveform Viewer_zoom_out"); // B (f, cl) +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +selectButton(RDIResource.GraphicalView_ZOOM_OUT, "Waveform Viewer_zoom_out"); // B (f, cl) +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// HMemoryUtils.trashcanNow. Engine heap size: 738 MB. GUI used memory: 63 MB. Current time: 10/20/22, 8:10:37 PM MSK +selectButton(RDIResource.GraphicalView_ZOOM_OUT, "Waveform Viewer_zoom_out"); // B (f, cl) +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// HMemoryUtils.trashcanNow. Engine heap size: 738 MB. GUI used memory: 78 MB. Current time: 10/20/22, 8:10:41 PM MSK +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// HMemoryUtils.trashcanNow. Engine heap size: 738 MB. GUI used memory: 63 MB. Current time: 10/20/22, 8:10:42 PM MSK +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// HMemoryUtils.trashcanNow. Engine heap size: 738 MB. GUI used memory: 63 MB. Current time: 10/20/22, 8:10:42 PM MSK +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// HMemoryUtils.trashcanNow. Engine heap size: 738 MB. GUI used memory: 68 MB. Current time: 10/20/22, 8:10:42 PM MSK +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// HMemoryUtils.trashcanNow. Engine heap size: 738 MB. GUI used memory: 63 MB. Current time: 10/20/22, 8:10:42 PM MSK +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// HMemoryUtils.trashcanNow. Engine heap size: 738 MB. GUI used memory: 63 MB. Current time: 10/20/22, 8:10:43 PM MSK +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// HMemoryUtils.trashcanNow. Engine heap size: 738 MB. GUI used memory: 63 MB. Current time: 10/20/22, 8:10:43 PM MSK +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// HMemoryUtils.trashcanNow. Engine heap size: 738 MB. GUI used memory: 63 MB. Current time: 10/20/22, 8:10:43 PM MSK +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// HMemoryUtils.trashcanNow. Engine heap size: 738 MB. GUI used memory: 68 MB. Current time: 10/20/22, 8:10:43 PM MSK +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// HMemoryUtils.trashcanNow. Engine heap size: 738 MB. GUI used memory: 63 MB. Current time: 10/20/22, 8:10:44 PM MSK +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// HMemoryUtils.trashcanNow. Engine heap size: 738 MB. GUI used memory: 63 MB. Current time: 10/20/22, 8:10:44 PM MSK +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// HMemoryUtils.trashcanNow. Engine heap size: 738 MB. GUI used memory: 68 MB. Current time: 10/20/22, 8:10:44 PM MSK +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// HMemoryUtils.trashcanNow. Engine heap size: 738 MB. GUI used memory: 63 MB. Current time: 10/20/22, 8:10:44 PM MSK +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// HMemoryUtils.trashcanNow. Engine heap size: 738 MB. GUI used memory: 63 MB. Current time: 10/20/22, 8:10:44 PM MSK +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// HMemoryUtils.trashcanNow. Engine heap size: 738 MB. GUI used memory: 63 MB. Current time: 10/20/22, 8:10:45 PM MSK +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// HMemoryUtils.trashcanNow. Engine heap size: 738 MB. GUI used memory: 63 MB. Current time: 10/20/22, 8:10:45 PM MSK +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// HMemoryUtils.trashcanNow. Engine heap size: 738 MB. GUI used memory: 63 MB. Current time: 10/20/22, 8:10:45 PM MSK +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// HMemoryUtils.trashcanNow. Engine heap size: 738 MB. GUI used memory: 63 MB. Current time: 10/20/22, 8:10:45 PM MSK +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// HMemoryUtils.trashcanNow. Engine heap size: 738 MB. GUI used memory: 63 MB. Current time: 10/20/22, 8:10:46 PM MSK +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// HMemoryUtils.trashcanNow. Engine heap size: 738 MB. GUI used memory: 69 MB. Current time: 10/20/22, 8:10:46 PM MSK +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// HMemoryUtils.trashcanNow. Engine heap size: 738 MB. GUI used memory: 63 MB. Current time: 10/20/22, 8:10:46 PM MSK +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// Elapsed time: 14 seconds +selectMenu(PAResourceItoN.MainMenuMgr_TOOLS, "Tools"); // Z (q, cl) +selectMenu(RDIResourceCommand.RDICommands_CUSTOM_COMMANDS, "Custom Commands"); // ae (cl) +selectMenuItem(RDIResourceCommand.RDICommands_SETTINGS, "Settings..."); // ah (cl) +dismissMenu(PAResourceItoN.MainMenuMgr_TOOLS, "Tools"); // Z (q, cl) +// Run Command: RDIResourceCommand.RDICommands_SETTINGS +// Tcl Command: 'rdi::info_commands {device::*}' +// Tcl Command: 'rdi::info_commands {debug::*}' +// Tcl Command: 'rdi::info_commands {*}' +// D (cl): Settings: addNotify +// WARNING: HEventQueue.dispatchEvent() is taking 1932 ms. +expandTree(PAResourceQtoS.SettingsDialog_OPTIONS_TREE, "[optionsRoot, Text Editor]", 7); // L (E, D) +selectTree(PAResourceQtoS.SettingsDialog_OPTIONS_TREE, "[optionsRoot, Text Editor, Fonts and Colors]", 11, false); // L (E, D) +selectButton(RDIResource.BaseDialog_APPLY, "Apply"); // a (D) +// [Engine Memory]: 784 MB (+18707kb) [00:01:56] +// [GUI Memory]: 132 MB (+17085kb) [00:01:56] +selectButton(RDIResource.BaseDialog_OK, "OK"); // a (D) +dismissDialog("Settings"); // D (cl) +selectButton(PAResourceTtoZ.TaskBanner_CLOSE, (String) null); // k (aA, cl) +closeTask("Simulation", "Behavioral Simulation - Functional - sim_1 - top_tb", "DesignTask.SIMULATION"); +// A (cl): Confirm Close: addNotify +selectCheckBox(RDIResource.MessageWithOptionDialog_DONT_SHOW_THIS_DIALOG_AGAIN, "Don't show this dialog again", true); // g (Q, A): TRUE +selectButton(RDIResource.BaseDialog_OK, "OK"); // a (A) +// [GUI Memory]: 148 MB (+10358kb) [00:02:03] +// by (cl): Close : addNotify +// TclEventType: WAVEFORM_CLOSE_WCFG +dismissDialog("Confirm Close"); // A (cl) +// TclEventType: SIMULATION_CLOSE_SIMULATION +// Tcl Message: close_sim +// Tcl Message: INFO: [Simtcl 6-16] Simulation closed +dismissDialog("Close"); // by (cl) +selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation Sources, sim_1, Memory Initialization Files]", 13, true); // B (F, cl) - Node +selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation Sources, sim_1, Memory Initialization Files]", 13, true, false, false, false, false, true); // B (F, cl) - Double Click - Node +selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation Sources, sim_1, Memory Initialization Files, prog.txt]", 14, false); // B (F, cl) +selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation Sources, sim_1, Memory Initialization Files, prog.txt]", 14, false, false, false, false, false, true); // B (F, cl) - Double Click +// ad (cl): Unable to Open File: addNotify +selectButton(PAResourceOtoP.OpenFileAction_OPEN_DIRECTORY, "Open Directory"); // a (ad) +dismissDialog("Unable to Open File"); // ad (cl) +// TclEventType: DG_GRAPH_STALE +// TclEventType: FILE_SET_CHANGE +// Elapsed time: 13 seconds +selectCodeEditor("top_tb.sv", 539, 125); // cl (w, cl) +selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "top_tb.sv", 2); // k (j, cl) +selectTab((HResource) null, "PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "top_tb.sv", 2, false, true); // k (j, cl) - Double Click +maximizeView(PAResourceOtoP.PAViews_BASE_WORKSPACE, "BaseWorkspace"); // O (aH, cl) +selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Simulation, Run Simulation]", 10, false); // u (O, cl) +selectMenuItem(PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL, "Run Behavioral Simulation"); // ah (an, cl) +// Run Command: PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL +// e (cl): Run Simulation : addNotify +// TclEventType: LAUNCH_SIM +// TclEventType: FILE_SET_OPTIONS_CHANGE +// Tcl Message: launch_simulation +// Tcl Message: INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim' INFO: [SIM-utils-51] Simulation object is 'sim_1' INFO: [SIM-utils-54] Inspecting design source files for 'top_tb' in fileset 'sim_1'... INFO: [SIM-utils-43] Exported 'C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim/prog.txt' INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)... INFO: [USF-XSim-101] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim' +// Tcl Message: "xvlog --incr --relax -prj top_tb_vlog.prj" +// TclEventType: LAUNCH_SIM_LOG +// Tcl Message: INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/Users/Alex/APS/aps_/aps_.srcs/sim_1/new/im_tb.sv" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module im_tb +// Tcl Message: INFO: [USF-XSim-69] 'compile' step finished in '2' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim' +// Tcl Message: "xelab -wto 88fd13c424e241a2b1d7269d9396082e --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_tb_behav xil_defaultlib.top_tb xil_defaultlib.glbl -log elaborate.log" +// TclEventType: LAUNCH_SIM +// Tcl Message: INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim' INFO: [USF-XSim-98] *** Running xsim +// Tcl Message: with args "top_tb_behav -key {Behavioral:sim_1:Functional:top_tb} -tclbatch {top_tb.tcl} -log {simulate.log}" +// Tcl Message: INFO: [USF-XSim-8] Loading simulator feature +// Tcl Message: Vivado Simulator 2019.1 +// TclEventType: SIMULATION_CREATE_SIMULATION_OBJECT +// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE +// TclEventType: SIMULATION_UPDATE_SCOPE_TREE +// TclEventType: SIMULATION_UPDATE_STACKS +// TclEventType: SIMULATION_UPDATE_OBJECT_TREE +// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE +// TclEventType: SIMULATION_UPDATE_SCOPE_TREE +// TclEventType: SIMULATION_UPDATE_STACKS +// TclEventType: SIMULATION_UPDATE_OBJECT_TREE +// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE +// TclEventType: SIMULATION_UPDATE_SCOPE_TREE +// TclEventType: SIMULATION_UPDATE_STACKS +// Tcl Message: Time resolution is 1 ps +// TclEventType: SIMULATION_UPDATE_OBJECT_TREE +// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE +closeView(PAResourceOtoP.PAViews_PROJECT_SUMMARY, "Project Summary"); // v +// TclEventType: WAVEFORM_UPDATE_TITLE +// TclEventType: WAVEFORM_OPEN_WCFG +// TclEventType: SIMULATION_UPDATE_SCOPE_TREE +// TclEventType: SIMULATION_UPDATE_STACKS +// TclEventType: SIMULATION_UPDATE_OBJECT_TREE +// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE +// TclEventType: WAVEFORM_OPEN_WCFG +// Waveform: addNotify +// TclEventType: WAVEFORM_DELAYED_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// HMemoryUtils.trashcanNow. Engine heap size: 793 MB. GUI used memory: 85 MB. Current time: 10/20/22, 8:11:52 PM MSK +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: WAVEFORM_UPDATE_TITLE +// TclEventType: WAVEFORM_DELAYED_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_TITLE +// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE +// TclEventType: SIMULATION_CLEAR_CURRENT_LINE +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// TclEventType: SIMULATION_OBJECT_TREE_RESTORED +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED +// TclEventType: SIMULATION_CURRENT_STACK_CHANGED +// TclEventType: SIMULATION_UPDATE_STACK_FRAMES +// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED +// TclEventType: SIMULATION_UPDATE_LOCALS +// TclEventType: SIMULATION_UPDATE_SCOPE_TREE +// TclEventType: SIMULATION_UPDATE_STACKS +// TclEventType: SIMULATION_UPDATE_OBJECT_TREE +// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE +// Tcl Message: source top_tb.tcl +// Tcl Message: # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns +// Tcl Message: INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_tb_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns +// Tcl Message: launch_simulation: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 831.754 ; gain = 0.000 +// 'd' command handler elapsed time: 7 seconds +dismissDialog("Run Simulation"); // e (cl) +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_MODEL_EVENT +selectButton(RDIResource.WaveformView_GOTO_TIME_0, "Waveform Viewer_RunReset"); // B (f, cl) +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// HMemoryUtils.trashcanNow. Engine heap size: 794 MB. GUI used memory: 85 MB. Current time: 10/20/22, 8:11:58 PM MSK +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// HMemoryUtils.trashcanNow. Engine heap size: 794 MB. GUI used memory: 85 MB. Current time: 10/20/22, 8:11:59 PM MSK +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// HMemoryUtils.trashcanNow. Engine heap size: 794 MB. GUI used memory: 85 MB. Current time: 10/20/22, 8:12:00 PM MSK +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// Elapsed time: 27 seconds +selectButton(PAResourceCommand.PACommandNames_SIMULATION_LIVE_RUN_ALL, "simulation_live_run_all"); // B (f, cl) +// Run Command: PAResourceCommand.PACommandNames_SIMULATION_LIVE_RUN_ALL +// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE +// TclEventType: SIMULATION_CLEAR_CURRENT_LINE +// Tcl Message: run all +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +selectButton(RDIResource.WaveformView_GOTO_LAST_TIME, "Waveform Viewer_RunAll"); // B (f, cl) +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// HMemoryUtils.trashcanNow. Engine heap size: 812 MB. GUI used memory: 84 MB. Current time: 10/20/22, 8:12:27 PM MSK +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// HMemoryUtils.trashcanNow. Engine heap size: 812 MB. GUI used memory: 84 MB. Current time: 10/20/22, 8:12:30 PM MSK +selectTreeTable(PAResourceQtoS.SimulationScopesPanel_SIMULATE_SCOPE_TABLE, "dut ; cpu_top ; Verilog Module", 1, "dut", 0, true); // c (c, cl) - Node +// TclEventType: SIMULATION_REQUEST_SELECT_SCOPES +// TclEventType: SIMULATION_UPDATE_SCOPE_TREE +// TclEventType: SIMULATION_UPDATE_STACKS +// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED +// TclEventType: SIMULATION_CURRENT_STACK_CHANGED +// TclEventType: SIMULATION_UPDATE_STACK_FRAMES +// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED +// TclEventType: SIMULATION_UPDATE_LOCALS +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// HMemoryUtils.trashcanNow. Engine heap size: 814 MB. GUI used memory: 85 MB. Current time: 10/20/22, 8:12:34 PM MSK +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// HMemoryUtils.trashcanNow. Engine heap size: 814 MB. GUI used memory: 85 MB. Current time: 10/20/22, 8:12:38 PM MSK +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: SIMULATION_UPDATE_OBJECT_TREE +// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE +// TclEventType: WAVEFORM_MODEL_EVENT +// HMemoryUtils.trashcanNow. Engine heap size: 814 MB. GUI used memory: 85 MB. Current time: 10/20/22, 8:12:40 PM MSK +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// HMemoryUtils.trashcanNow. Engine heap size: 814 MB. GUI used memory: 85 MB. Current time: 10/20/22, 8:12:43 PM MSK +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// HMemoryUtils.trashcanNow. Engine heap size: 814 MB. GUI used memory: 85 MB. Current time: 10/20/22, 8:12:47 PM MSK +// Elapsed time: 16 seconds +selectTreeTable(PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE, "PC[5:0] ; 02 ; Array", 6, "PC[5:0]", 0, true); // c (c, cl) - Node +// TclEventType: SIMULATION_UPDATE_OBJECT_TREE +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// TclEventType: SIMULATION_UPDATE_OBJECT_TREE +selectTreeTable(PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE, "PC[5:0] ; 02 ; Array", 6, "PC[5:0]", 0, true, false, false, false, false, true); // c (c, cl) - Double Click - Node +// TclEventType: SIMULATION_OPEN_SOURCE +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +selectTreeTable(PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE, "PC[5:0] ; 02 ; Array", 6, "02", 1, true); // c (c, cl) - Node +// TclEventType: SIMULATION_UPDATE_OBJECT_TREE +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +selectTreeTable(PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE, "PC[5:0] ; 02 ; Array", 6, "PC[5:0]", 0, true); // c (c, cl) - Node +// TclEventType: SIMULATION_UPDATE_OBJECT_TREE +selectTreeTable(PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE, "PC[5:0] ; 02 ; Array", 6, "PC[5:0]", 0, true, false, false, false, false, true); // c (c, cl) - Double Click - Node +// TclEventType: SIMULATION_OPEN_SOURCE +selectTreeTable(PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE, "PC[5:0] ; 02 ; Array", 6, "PC[5:0]", 0, true); // c (c, cl) - Node +// TclEventType: SIMULATION_UPDATE_OBJECT_TREE +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +selectTreeTable(PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE, "PC[5:0] ; 02 ; Array", 6, "PC[5:0]", 0, true); // c (c, cl) - Node +// TclEventType: SIMULATION_UPDATE_OBJECT_TREE +selectTreeTable(PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE, "PC[5:0] ; 02 ; Array", 6, "PC[5:0]", 0, true); // c (c, cl) - Node +selectTreeTable(PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE, "PC[5:0] ; 02 ; Array", 6, "PC[5:0]", 0, true); // c (c, cl) - Node +selectTreeTable(PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE, "PC[5:0] ; 02 ; Array", 6, "PC[5:0]", 0, true); // c (c, cl) - Node +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +selectTreeTable(PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE, "PC[5:0] ; 02 ; Array", 6, "PC[5:0]", 0, true); // c (c, cl) - Node +// TclEventType: SIMULATION_UPDATE_OBJECT_TREE +selectTreeTable(PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE, "PC[5:0] ; 02 ; Array", 6, "PC[5:0]", 0, true); // c (c, cl) - Node +selectTreeTable(PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE, "PC[5:0] ; 02 ; Array", 6, "PC[5:0]", 0, true); // c (c, cl) - Node +selectTreeTable(PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE, "PC[5:0] ; 02 ; Array", 6, "PC[5:0]", 0, true); // c (c, cl) - Node +selectTreeTable(PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE, "PC[5:0] ; 02 ; Array", 6, "PC[5:0]", 0, true); // c (c, cl) - Node +selectTreeTable(PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE, "PC[5:0] ; 02 ; Array", 6, "PC[5:0]", 0, true); // c (c, cl) - Node +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +selectTreeTable(PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE, "PC[5:0] ; 02 ; Array", 6, "PC[5:0]", 0, true); // c (c, cl) - Node +// TclEventType: SIMULATION_UPDATE_OBJECT_TREE +selectTreeTable(PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE, "PC[5:0] ; 02 ; Array", 6, "PC[5:0]", 0, true); // c (c, cl) - Node +selectTreeTable(PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE, "PC[5:0] ; 02 ; Array", 6, "PC[5:0]", 0, true); // c (c, cl) - Node +selectTreeTable(PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE, "PC[5:0] ; 02 ; Array", 6, "PC[5:0]", 0, true); // c (c, cl) - Node +selectTreeTable(PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE, "PC[5:0] ; 02 ; Array", 6, "PC[5:0]", 0, true); // c (c, cl) - Node +selectTreeTable(PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE, "PC[5:0] ; 02 ; Array", 6, "PC[5:0]", 0, true); // c (c, cl) - Node +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +selectTreeTable(PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE, "PC[5:0] ; 02 ; Array", 6, "PC[5:0]", 0, true); // c (c, cl) - Node +// TclEventType: SIMULATION_UPDATE_OBJECT_TREE +selectTreeTable(PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE, "PC[5:0] ; 02 ; Array", 6, "PC[5:0]", 0, true); // c (c, cl) - Node +selectTreeTable(PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE, "PC[5:0] ; 02 ; Array", 6, "PC[5:0]", 0, true); // c (c, cl) - Node +selectTreeTable(PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE, "PC[5:0] ; 02 ; Array", 6, "PC[5:0]", 0, true); // c (c, cl) - Node +selectTreeTable(PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE, "PC[5:0] ; 02 ; Array", 6, "PC[5:0]", 0, true); // c (c, cl) - Node +selectTreeTable(PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE, "PC[5:0] ; 02 ; Array", 6, "PC[5:0]", 0, true); // c (c, cl) - Node +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +selectButton(PAResourceTtoZ.TaskBanner_CLOSE, (String) null); // k (aA, cl) +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +selectButton(PAResourceCommand.PACommandNames_SIMULATION_LIVE_BREAK, "simulation_live_break"); // B (f, cl) +// Run Command: PAResourceCommand.PACommandNames_SIMULATION_LIVE_BREAK +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// TclEventType: SIMULATION_OBJECT_TREE_RESTORED +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_DELAYED_MODEL_EVENT +// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED +// TclEventType: SIMULATION_CURRENT_STACK_CHANGED +// TclEventType: SIMULATION_UPDATE_STACK_FRAMES +// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED +// TclEventType: SIMULATION_UPDATE_LOCALS +// TclEventType: SIMULATION_UPDATE_SCOPE_TREE +// TclEventType: SIMULATION_UPDATE_STACKS +// TclEventType: SIMULATION_UPDATE_OBJECT_TREE +// TclEventType: SIMULATION_STOPPED +// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE +// Tcl Message: run: Time (s): cpu = 00:00:47 ; elapsed = 00:00:37 . Memory (MB): peak = 831.754 ; gain = 0.000 +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_MODEL_EVENT +selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "Untitled 2", 2); // k (j, cl) +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +selectTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, PERIOD[31:0]]", 4, true, false, false, false, true, false); // a (r, cl) - Popup Trigger - Node +selectMenuItem((HResource) null, "New Virtual Bus"); // ah (an, Popup.HeavyWeightWindow) +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: WAVEFORM_UPDATE_TITLE +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_RENAME_COMMAND +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +expandTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, New Virtual Bus]", 5); // a (r, cl) +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +collapseTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, New Virtual Bus]", 5); // a (r, cl) +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +selectTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, New Virtual Bus]", 5, true, false, false, false, true, false); // a (r, cl) - Popup Trigger - Node +// TclEventType: WAVEFORM_UPDATE_COMMANDS +selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 23, 394); // n (o, cl) +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// HMemoryUtils.trashcanNow. Engine heap size: 820 MB. GUI used memory: 87 MB. Current time: 10/20/22, 8:13:17 PM MSK +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +selectTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, New Virtual Bus]", 5, true); // a (r, cl) - Node +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: WAVEFORM_UPDATE_TITLE +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +selectTreeTable(PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE, "we ; 1 ; Logic", 5, "1", 1, false); // c (c, cl) +// TclEventType: SIMULATION_UPDATE_OBJECT_TREE +selectTreeTable(PAResourceQtoS.SimulationScopesPanel_SIMULATE_SCOPE_TABLE, "dut ; cpu_top ; Verilog Module", 1, "dut", 0, true); // c (c, cl) - Node +// TclEventType: SIMULATION_REQUEST_SELECT_SCOPES +// TclEventType: SIMULATION_UPDATE_SCOPE_TREE +// TclEventType: SIMULATION_UPDATE_STACKS +// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED +// TclEventType: SIMULATION_CURRENT_STACK_CHANGED +// TclEventType: SIMULATION_UPDATE_STACK_FRAMES +// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED +// TclEventType: SIMULATION_UPDATE_LOCALS +selectTreeTable(PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE, "PC[5:0] ; 02 ; Array", 6, "PC[5:0]", 0, true); // c (c, cl) - Node +// TclEventType: SIMULATION_UPDATE_OBJECT_TREE +// [Engine Memory]: 823 MB (+548kb) [00:04:17] +// TclEventType: WAVEFORM_MODEL_EVENT +// by (cl): Add to Waveform : addNotify +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: WAVEFORM_UPDATE_TITLE +// TclEventType: WAVEFORM_DELAYED_MODEL_EVENT +dismissDialog("Add to Waveform"); // by (cl) +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_MODEL_EVENT +selectButton(PAResourceCommand.PACommandNames_SIMULATION_LIVE_RUN_ALL, "simulation_live_run_all"); // B (f, cl) +// Run Command: PAResourceCommand.PACommandNames_SIMULATION_LIVE_RUN_ALL +// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE +// TclEventType: SIMULATION_CLEAR_CURRENT_LINE +// Tcl Message: run all +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +selectButton(RDIResource.WaveformView_GOTO_LAST_TIME, "Waveform Viewer_RunAll"); // B (f, cl) +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// HMemoryUtils.trashcanNow. Engine heap size: 826 MB. GUI used memory: 87 MB. Current time: 10/20/22, 8:13:47 PM MSK +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// HMemoryUtils.trashcanNow. Engine heap size: 826 MB. GUI used memory: 87 MB. Current time: 10/20/22, 8:13:51 PM MSK +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// HMemoryUtils.trashcanNow. Engine heap size: 826 MB. GUI used memory: 87 MB. Current time: 10/20/22, 8:13:54 PM MSK +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// HMemoryUtils.trashcanNow. Engine heap size: 826 MB. GUI used memory: 87 MB. Current time: 10/20/22, 8:13:58 PM MSK +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// Elapsed time: 13 seconds +selectButton(PAResourceCommand.PACommandNames_SIMULATION_LIVE_BREAK, "simulation_live_break"); // B (f, cl) +// Run Command: PAResourceCommand.PACommandNames_SIMULATION_LIVE_BREAK +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// TclEventType: SIMULATION_OBJECT_TREE_RESTORED +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_DELAYED_MODEL_EVENT +// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED +// TclEventType: SIMULATION_CURRENT_STACK_CHANGED +// TclEventType: SIMULATION_UPDATE_STACK_FRAMES +// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED +// TclEventType: SIMULATION_UPDATE_LOCALS +// TclEventType: SIMULATION_UPDATE_SCOPE_TREE +// TclEventType: SIMULATION_UPDATE_STACKS +// TclEventType: SIMULATION_UPDATE_OBJECT_TREE +// TclEventType: SIMULATION_STOPPED +// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE +// Tcl Message: run: Time (s): cpu = 00:00:23 ; elapsed = 00:00:19 . Memory (MB): peak = 832.652 ; gain = 0.000 +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_MODEL_EVENT +selectButton(PAResourceTtoZ.TaskBanner_CLOSE, (String) null); // k (aA, cl) +closeTask("Simulation", "Behavioral Simulation - Functional - sim_1 - top_tb", "DesignTask.SIMULATION"); +// TclEventType: WAVEFORM_UPDATE_TITLE +// TclEventType: WAVEFORM_CLOSE_WCFG +// by (cl): Close : addNotify +selectButton("OptionPane.button", "Discard"); // JButton (A, G) +// TclEventType: SIMULATION_CLOSE_SIMULATION +// WARNING: HEventQueue.dispatchEvent() is taking 1096 ms. +// Tcl Message: close_sim +// Tcl Message: INFO: [Simtcl 6-16] Simulation closed +// Tcl Message: close_sim: Time (s): cpu = 00:00:02 ; elapsed = 00:00:06 . Memory (MB): peak = 833.211 ; gain = 0.000 +dismissDialog("Close"); // by (cl) +// Elapsed time: 34 seconds +selectCodeEditor("top_tb.sv", 477, 462); // cl (w, cl) +// Elapsed time: 15 seconds +selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "cpu_top.sv", 1); // k (j, cl) +// Elapsed time: 82 seconds +unMinimizeFrame(PAResourceOtoP.PAViews_SOURCES, "Sources"); // az (aK) +selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation Sources, sim_1, alu_riscv_tb (alu_riscv_tb.sv)]", 11, true); // B (F, cl) - Node +selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation Sources, sim_1, alu_riscv_tb (alu_riscv_tb.sv)]", 11, true, false, false, false, false, true); // B (F, cl) - Double Click - Node +selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation Sources, sim_1, top_tb (top_tb.sv), dut : cpu_top (cpu_top.sv)]", 10, true); // B (F, cl) - Node +selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation Sources, sim_1, top_tb (top_tb.sv), dut : cpu_top (cpu_top.sv)]", 10, true, false, false, false, false, true); // B (F, cl) - Double Click - Node +selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation Sources, sim_1, top_tb (top_tb.sv), dut : cpu_top (cpu_top.sv), alu : alu_riscv (alu_riscv.sv)]", 13, false); // B (F, cl) +selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation Sources, sim_1, top_tb (top_tb.sv), dut : cpu_top (cpu_top.sv), alu : alu_riscv (alu_riscv.sv)]", 13, false, false, false, false, false, true); // B (F, cl) - Double Click +closeView(PAResourceOtoP.PAViews_CODE, "Code"); // B +// Elapsed time: 10 seconds +selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "rf_riscv.sv", 3); // k (j, cl) +selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "top_tb.sv", 2); // k (j, cl) +selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "cpu_top.sv", 1); // k (j, cl) +// Elapsed time: 16 seconds +selectCodeEditor("cpu_top.sv", 519, 453); // cl (w, cl) +selectCodeEditor("cpu_top.sv", 678, 539); // cl (w, cl) +// TclEventType: DG_GRAPH_STALE +// TclEventType: FILE_SET_CHANGE +selectCodeEditor("cpu_top.sv", 678, 539); // cl (w, cl) +// Elapsed time: 50 seconds +selectCodeEditor("cpu_top.sv", 640, 614); // cl (w, cl) +// TclEventType: DG_GRAPH_STALE +// TclEventType: FILE_SET_CHANGE +// Elapsed time: 27 seconds +selectCodeEditor("cpu_top.sv", 728, 220); // cl (w, cl) +selectCodeEditor("cpu_top.sv", 766, 388); // cl (w, cl) +selectCodeEditor("cpu_top.sv", 457, 262); // cl (w, cl) +selectCodeEditor("cpu_top.sv", 457, 262); // cl (w, cl) +selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Simulation, Run Simulation]", 10, false); // u (O, cl) +selectMenuItem(PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL, "Run Behavioral Simulation"); // ah (an, cl) +// Run Command: PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL +// e (cl): Run Simulation : addNotify +// TclEventType: LAUNCH_SIM +// TclEventType: FILE_SET_OPTIONS_CHANGE +// Tcl Message: launch_simulation +// Tcl Message: INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim' INFO: [SIM-utils-51] Simulation object is 'sim_1' INFO: [SIM-utils-54] Inspecting design source files for 'top_tb' in fileset 'sim_1'... INFO: [SIM-utils-43] Exported 'C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim/prog.txt' INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)... INFO: [USF-XSim-101] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim' +// Tcl Message: "xvlog --incr --relax -prj top_tb_vlog.prj" +// TclEventType: LAUNCH_SIM_LOG +// Tcl Message: INFO: [USF-XSim-69] 'compile' step finished in '2' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim' +// Tcl Message: "xelab -wto 88fd13c424e241a2b1d7269d9396082e --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_tb_behav xil_defaultlib.top_tb xil_defaultlib.glbl -log elaborate.log" +// TclEventType: LAUNCH_SIM +// Tcl Message: INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim' INFO: [USF-XSim-98] *** Running xsim +// Tcl Message: with args "top_tb_behav -key {Behavioral:sim_1:Functional:top_tb} -tclbatch {top_tb.tcl} -log {simulate.log}" +// Tcl Message: INFO: [USF-XSim-8] Loading simulator feature +// Tcl Message: Vivado Simulator 2019.1 +// TclEventType: SIMULATION_CREATE_SIMULATION_OBJECT +// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE +// TclEventType: SIMULATION_UPDATE_SCOPE_TREE +// TclEventType: SIMULATION_UPDATE_STACKS +// TclEventType: SIMULATION_UPDATE_OBJECT_TREE +// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE +// TclEventType: SIMULATION_UPDATE_SCOPE_TREE +// TclEventType: SIMULATION_UPDATE_STACKS +// TclEventType: SIMULATION_UPDATE_OBJECT_TREE +// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE +// TclEventType: SIMULATION_UPDATE_SCOPE_TREE +// TclEventType: SIMULATION_UPDATE_STACKS +// TclEventType: SIMULATION_UPDATE_OBJECT_TREE +// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE +closeView(PAResourceOtoP.PAViews_PROJECT_SUMMARY, "Project Summary"); // v +// Tcl Message: Time resolution is 1 ps +// TclEventType: WAVEFORM_UPDATE_TITLE +// TclEventType: WAVEFORM_OPEN_WCFG +// TclEventType: SIMULATION_UPDATE_SCOPE_TREE +// TclEventType: SIMULATION_UPDATE_STACKS +// TclEventType: SIMULATION_UPDATE_OBJECT_TREE +// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE +// TclEventType: WAVEFORM_OPEN_WCFG +// Waveform: addNotify +// TclEventType: WAVEFORM_DELAYED_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// HMemoryUtils.trashcanNow. Engine heap size: 827 MB. GUI used memory: 91 MB. Current time: 10/20/22, 8:18:49 PM MSK +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: WAVEFORM_UPDATE_TITLE +// Tcl Message: source top_tb.tcl +// Tcl Message: # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } +// TclEventType: WAVEFORM_UPDATE_TITLE +// TclEventType: WAVEFORM_DELAYED_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_TITLE +// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE +// TclEventType: SIMULATION_CLEAR_CURRENT_LINE +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// TclEventType: SIMULATION_OBJECT_TREE_RESTORED +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED +// TclEventType: SIMULATION_CURRENT_STACK_CHANGED +// TclEventType: SIMULATION_UPDATE_STACK_FRAMES +// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED +// TclEventType: SIMULATION_UPDATE_LOCALS +// TclEventType: SIMULATION_UPDATE_SCOPE_TREE +// TclEventType: SIMULATION_UPDATE_STACKS +// TclEventType: SIMULATION_UPDATE_OBJECT_TREE +// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE +// Tcl Message: # run 1000ns +// Tcl Message: INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_tb_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns +// Tcl Message: launch_simulation: Time (s): cpu = 00:00:05 ; elapsed = 00:00:07 . Memory (MB): peak = 833.211 ; gain = 0.000 +// 'd' command handler elapsed time: 7 seconds +dismissDialog("Run Simulation"); // e (cl) +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_MODEL_EVENT +// Elapsed time: 30 seconds +selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 401, 223); // n (o, cl) +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 316, 255); // n (o, cl) +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// HMemoryUtils.trashcanNow. Engine heap size: 827 MB. GUI used memory: 91 MB. Current time: 10/20/22, 8:19:21 PM MSK +expandTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, leds[15:0]]", 2); // a (r, cl) +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +collapseTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, leds[15:0]]", 2); // a (r, cl) +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 583, 323); // n (o, cl) +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// HMemoryUtils.trashcanNow. Engine heap size: 827 MB. GUI used memory: 91 MB. Current time: 10/20/22, 8:19:27 PM MSK +// Run Command: RDIResourceCommand.RDICommands_WAVEFORM_SAVE_CONFIGURATION +dismissFileChooser(); +selectButton(PAResourceTtoZ.TaskBanner_CLOSE, (String) null); // k (aA, cl) +closeTask("Simulation", "Behavioral Simulation - Functional - sim_1 - top_tb", "DesignTask.SIMULATION"); +// by (cl): Close : addNotify +// TclEventType: WAVEFORM_CLOSE_WCFG +// TclEventType: SIMULATION_CLOSE_SIMULATION +// WARNING: HEventQueue.dispatchEvent() is taking 1101 ms. +// Tcl Message: close_sim +// Tcl Message: INFO: [Simtcl 6-16] Simulation closed +dismissDialog("Close"); // by (cl) +selectCodeEditor("cpu_top.sv", 608, 602); // cl (w, cl) +selectCodeEditor("cpu_top.sv", 763, 370); // cl (w, cl) +selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "top_tb.sv", 2); // k (j, cl) +selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "rf_riscv.sv", 3); // k (j, cl) +selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "alu_riscv.sv", 4); // k (j, cl) +selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "rf_riscv.sv", 3); // k (j, cl) +selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "cpu_top.sv", 1); // k (j, cl) +// Elapsed time: 53 seconds +selectCodeEditor("cpu_top.sv", 230, 432); // cl (w, cl) +selectCodeEditor("cpu_top.sv", 230, 432, false, false, false, false, true); // cl (w, cl) - Double Click +selectCodeEditor("cpu_top.sv", 498, 430); // cl (w, cl) +selectCodeEditor("cpu_top.sv", 498, 430, false, false, false, false, true); // cl (w, cl) - Double Click +selectCodeEditor("cpu_top.sv", 613, 511); // cl (w, cl) +// Elapsed time: 11 seconds +selectCodeEditor("cpu_top.sv", 649, 366); // cl (w, cl) +selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation Sources, sim_1, Memory Initialization Files, prog.txt]", 22, false); // B (F, cl) +selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation Sources, sim_1, Memory Initialization Files, prog.txt]", 22, false, false, false, false, false, true); // B (F, cl) - Double Click +// ad (cl): Unable to Open File: addNotify +selectButton(PAResourceOtoP.OpenFileAction_OPEN_DIRECTORY, "Open Directory"); // a (ad) +dismissDialog("Unable to Open File"); // ad (cl) +// TclEventType: DG_GRAPH_STALE +// TclEventType: FILE_SET_CHANGE +// Elapsed time: 16 seconds +selectCodeEditor("cpu_top.sv", 484, 164); // cl (w, cl) +selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Simulation, Run Simulation]", 10, false); // u (O, cl) +selectMenuItem(PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL, "Run Behavioral Simulation"); // ah (an, cl) +// Run Command: PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL +// al (cl): Save Project: addNotify +selectButton(PAResourceQtoS.SaveProjectUtils_SAVE, "Save"); // a (al) +// by (cl): Save Constraints : addNotify +// TclEventType: DG_GRAPH_STALE +// e (cl): Run Simulation : addNotify +dismissDialog("Save Project"); // al (cl) +// TclEventType: DG_GRAPH_STALE +// TclEventType: FILE_SET_CHANGE +// TclEventType: LAUNCH_SIM +// Tcl Message: launch_simulation +// TclEventType: FILE_SET_OPTIONS_CHANGE +// Tcl Message: INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim' INFO: [SIM-utils-51] Simulation object is 'sim_1' INFO: [SIM-utils-54] Inspecting design source files for 'top_tb' in fileset 'sim_1'... INFO: [SIM-utils-43] Exported 'C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim/prog.txt' INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)... INFO: [USF-XSim-101] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim' +// Tcl Message: "xvlog --incr --relax -prj top_tb_vlog.prj" +// TclEventType: LAUNCH_SIM_LOG +// Tcl Message: INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim' +// Tcl Message: "xelab -wto 88fd13c424e241a2b1d7269d9396082e --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_tb_behav xil_defaultlib.top_tb xil_defaultlib.glbl -log elaborate.log" +// TclEventType: LAUNCH_SIM +// Tcl Message: INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim' INFO: [USF-XSim-98] *** Running xsim +// Tcl Message: with args "top_tb_behav -key {Behavioral:sim_1:Functional:top_tb} -tclbatch {top_tb.tcl} -log {simulate.log}" +// Tcl Message: INFO: [USF-XSim-8] Loading simulator feature +// Tcl Message: Vivado Simulator 2019.1 +// TclEventType: SIMULATION_CREATE_SIMULATION_OBJECT +// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE +// TclEventType: SIMULATION_UPDATE_SCOPE_TREE +// TclEventType: SIMULATION_UPDATE_STACKS +// TclEventType: SIMULATION_UPDATE_OBJECT_TREE +// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE +// TclEventType: SIMULATION_UPDATE_SCOPE_TREE +// TclEventType: SIMULATION_UPDATE_STACKS +// TclEventType: SIMULATION_UPDATE_OBJECT_TREE +// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE +// TclEventType: SIMULATION_UPDATE_SCOPE_TREE +// TclEventType: SIMULATION_UPDATE_STACKS +// TclEventType: SIMULATION_UPDATE_OBJECT_TREE +// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE +closeView(PAResourceOtoP.PAViews_PROJECT_SUMMARY, "Project Summary"); // v +// Tcl Message: Time resolution is 1 ps +// TclEventType: WAVEFORM_UPDATE_TITLE +// TclEventType: WAVEFORM_OPEN_WCFG +// TclEventType: SIMULATION_UPDATE_SCOPE_TREE +// TclEventType: SIMULATION_UPDATE_STACKS +// TclEventType: SIMULATION_UPDATE_OBJECT_TREE +// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE +// TclEventType: WAVEFORM_OPEN_WCFG +// Waveform: addNotify +// TclEventType: WAVEFORM_DELAYED_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_DELAYED_MODEL_EVENT +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_MODEL_EVENT +// Tcl Message: source top_tb.tcl +// Tcl Message: # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// HMemoryUtils.trashcanNow. Engine heap size: 827 MB. GUI used memory: 95 MB. Current time: 10/20/22, 8:21:44 PM MSK +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: WAVEFORM_UPDATE_TITLE +// TclEventType: WAVEFORM_DELAYED_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_TITLE +// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE +// TclEventType: SIMULATION_CLEAR_CURRENT_LINE +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// TclEventType: SIMULATION_OBJECT_TREE_RESTORED +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED +// TclEventType: SIMULATION_CURRENT_STACK_CHANGED +// TclEventType: SIMULATION_UPDATE_STACK_FRAMES +// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED +// TclEventType: SIMULATION_UPDATE_LOCALS +// TclEventType: SIMULATION_UPDATE_SCOPE_TREE +// TclEventType: SIMULATION_UPDATE_STACKS +// TclEventType: SIMULATION_UPDATE_OBJECT_TREE +// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE +// Tcl Message: # run 1000ns +// Tcl Message: INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_tb_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns +// Tcl Message: launch_simulation: Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 835.363 ; gain = 0.000 +// 'd' command handler elapsed time: 10 seconds +dismissDialog("Run Simulation"); // e (cl) +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_MODEL_EVENT +selectButton(PAResourceCommand.PACommandNames_SIMULATION_LIVE_RUN_ALL, "simulation_live_run_all"); // B (f, cl) +// Run Command: PAResourceCommand.PACommandNames_SIMULATION_LIVE_RUN_ALL +// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE +// TclEventType: SIMULATION_CLEAR_CURRENT_LINE +// Tcl Message: run all +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// HMemoryUtils.trashcanNow. Engine heap size: 827 MB. GUI used memory: 95 MB. Current time: 10/20/22, 8:21:56 PM MSK +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// HMemoryUtils.trashcanNow. Engine heap size: 827 MB. GUI used memory: 95 MB. Current time: 10/20/22, 8:22:01 PM MSK +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// HMemoryUtils.trashcanNow. Engine heap size: 827 MB. GUI used memory: 95 MB. Current time: 10/20/22, 8:22:05 PM MSK +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// Elapsed time: 14 seconds +selectButton(PAResourceCommand.PACommandNames_SIMULATION_LIVE_BREAK, "simulation_live_break"); // B (f, cl) +// Run Command: PAResourceCommand.PACommandNames_SIMULATION_LIVE_BREAK +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// TclEventType: SIMULATION_OBJECT_TREE_RESTORED +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_DELAYED_MODEL_EVENT +// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED +// TclEventType: SIMULATION_CURRENT_STACK_CHANGED +// HMemoryUtils.trashcanNow. Engine heap size: 827 MB. GUI used memory: 96 MB. Current time: 10/20/22, 8:22:08 PM MSK +// TclEventType: SIMULATION_CURRENT_STACK_CHANGED +// TclEventType: SIMULATION_UPDATE_STACK_FRAMES +// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED +// TclEventType: SIMULATION_UPDATE_LOCALS +// TclEventType: SIMULATION_UPDATE_SCOPE_TREE +// TclEventType: SIMULATION_UPDATE_STACKS +// TclEventType: SIMULATION_UPDATE_OBJECT_TREE +// TclEventType: SIMULATION_STOPPED +// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE +// Tcl Message: run: Time (s): cpu = 00:00:18 ; elapsed = 00:00:15 . Memory (MB): peak = 835.363 ; gain = 0.000 +selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "Untitled 4", 4); // k (j, cl) +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_MODEL_EVENT +selectButton(RDIResource.WaveformView_GOTO_TIME_0, "Waveform Viewer_RunReset"); // B (f, cl) +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// HMemoryUtils.trashcanNow. Engine heap size: 827 MB. GUI used memory: 95 MB. Current time: 10/20/22, 8:22:15 PM MSK +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// HMemoryUtils.trashcanNow. Engine heap size: 827 MB. GUI used memory: 95 MB. Current time: 10/20/22, 8:22:15 PM MSK +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// HMemoryUtils.trashcanNow. Engine heap size: 827 MB. GUI used memory: 95 MB. Current time: 10/20/22, 8:22:16 PM MSK +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// HMemoryUtils.trashcanNow. Engine heap size: 827 MB. GUI used memory: 95 MB. Current time: 10/20/22, 8:22:19 PM MSK +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// HMemoryUtils.trashcanNow. Engine heap size: 827 MB. GUI used memory: 95 MB. Current time: 10/20/22, 8:22:25 PM MSK +// Elapsed time: 15 seconds +selectButton(PAResourceTtoZ.TaskBanner_CLOSE, (String) null); // k (aA, cl) +closeTask("Simulation", "Behavioral Simulation - Functional - sim_1 - top_tb", "DesignTask.SIMULATION"); +// by (cl): Close : addNotify +// TclEventType: WAVEFORM_CLOSE_WCFG +// TclEventType: SIMULATION_CLOSE_SIMULATION +// WARNING: HEventQueue.dispatchEvent() is taking 1094 ms. +// Tcl Message: close_sim +// Tcl Message: INFO: [Simtcl 6-16] Simulation closed +dismissDialog("Close"); // by (cl) +selectCodeEditor("cpu_top.sv", 796, 627); // cl (w, cl) +selectButton(PAResourceTtoZ.TaskBanner_CLOSE, (String) null); // k (aA, cl) +closeTask("Project Manager", "Project Manager", "DesignTask.PROJECT_MANAGER"); +// Run Command: PAResourceCommand.PACommandNames_CLOSE_PROJECT +// A (cl): Close Project: addNotify +selectCheckBox(RDIResource.MessageWithOptionDialog_DONT_SHOW_THIS_DIALOG_AGAIN, "Don't show this dialog again", true); // g (Q, A): TRUE +selectButton(RDIResource.BaseDialog_CANCEL, "Cancel"); // a (A) +// 'b' command handler elapsed time: 4 seconds +dismissDialog("Close Project"); // A (cl) +selectCodeEditor("cpu_top.sv", 637, 107); // cl (w, cl) +// Elapsed time: 16 seconds +selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, Verilog Header]", 1, true); // B (F, cl) - Node +expandTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, Verilog Header]", 1); // B (F, cl) +selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, Verilog Header, defines.v]", 2, false); // B (F, cl) +selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, Verilog Header, defines.v]", 2, false, false, false, false, false, true); // B (F, cl) - Double Click +selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "alu_riscv.sv", 4); // k (j, cl) +selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "rf_riscv.sv", 3); // k (j, cl) +selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "top_tb.sv", 2); // k (j, cl) +selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "cpu_top.sv", 1); // k (j, cl) +selectCodeEditor("cpu_top.sv", 230, 430); // cl (w, cl) +// Elapsed time: 15 seconds +selectCodeEditor("cpu_top.sv", 633, 509); // cl (w, cl) +// TclEventType: DG_GRAPH_STALE +// TclEventType: FILE_SET_CHANGE +// Elapsed time: 36 seconds +selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "defines.v", 5); // k (j, cl) +selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "rf_riscv.sv", 3); // k (j, cl) +selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "top_tb.sv", 2); // k (j, cl) +selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "cpu_top.sv", 1); // k (j, cl) +selectCodeEditor("cpu_top.sv", 224, 312); // cl (w, cl) +selectCodeEditor("cpu_top.sv", 642, 461); // cl (w, cl) +// TclEventType: DG_GRAPH_STALE +// TclEventType: FILE_SET_CHANGE +selectCodeEditor("cpu_top.sv", 638, 442); // cl (w, cl) +// Elapsed time: 10 seconds +selectCodeEditor("cpu_top.sv", 42, 292); // cl (w, cl) +// TclEventType: DG_GRAPH_STALE +// TclEventType: FILE_SET_CHANGE +selectCodeEditor("cpu_top.sv", 644, 271); // cl (w, cl) +// Elapsed time: 16 seconds +selectCodeEditor("cpu_top.sv", 257, 229); // cl (w, cl) +selectCodeEditor("cpu_top.sv", 257, 229, false, false, false, false, true); // cl (w, cl) - Double Click +selectCodeEditor("cpu_top.sv", 215, 233); // cl (w, cl) +selectCodeEditor("cpu_top.sv", 215, 233, false, false, false, false, true); // cl (w, cl) - Double Click +typeControlKey((HResource) null, "cpu_top.sv", 'c'); // cl (w, cl) +selectCodeEditor("cpu_top.sv", 158, 638); // cl (w, cl) +selectCodeEditor("cpu_top.sv", 158, 638, false, false, false, false, true); // cl (w, cl) - Double Click +typeControlKey((HResource) null, "cpu_top.sv", 'v'); // cl (w, cl) +selectCodeEditor("cpu_top.sv", 129, 551); // cl (w, cl) +selectCodeEditor("cpu_top.sv", 129, 551, false, false, false, false, true); // cl (w, cl) - Double Click +typeControlKey((HResource) null, "cpu_top.sv", 'v'); // cl (w, cl) +selectCodeEditor("cpu_top.sv", 413, 547); // cl (w, cl) +selectCodeEditor("cpu_top.sv", 494, 623); // cl (w, cl) +// TclEventType: DG_GRAPH_STALE +// TclEventType: FILE_SET_CHANGE +selectCodeEditor("cpu_top.sv", 528, 631); // cl (w, cl) +// Elapsed time: 50 seconds +selectCodeEditor("cpu_top.sv", 514, 519); // cl (w, cl) +closeView(PAResourceOtoP.PAViews_CODE, "Code"); // B +closeView(PAResourceOtoP.PAViews_CODE, "Code"); // B +selectTab((HResource) null, "PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "alu_riscv.sv", 2, false, true); // k (j, cl) - Double Click +unmaximizeView(PAResourceOtoP.PAViews_BASE_WORKSPACE, "BaseWorkspace"); // O (aH, cl) +closeView(PAResourceOtoP.PAViews_CODE, "Code"); // B +closeView(PAResourceOtoP.PAViews_CODE, "Code"); // B +selectCodeEditor("cpu_top.sv", 624, 353); // cl (w, cl) +selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Simulation, Run Simulation]", 10, false); // u (O, cl) +selectMenuItem(PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL, "Run Behavioral Simulation"); // ah (an, cl) +// Run Command: PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL +// e (cl): Run Simulation : addNotify +// TclEventType: LAUNCH_SIM +// TclEventType: FILE_SET_OPTIONS_CHANGE +// Tcl Message: launch_simulation +// Tcl Message: INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim' INFO: [SIM-utils-51] Simulation object is 'sim_1' INFO: [SIM-utils-54] Inspecting design source files for 'top_tb' in fileset 'sim_1'... INFO: [SIM-utils-43] Exported 'C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim/prog.txt' INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)... INFO: [USF-XSim-101] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim' +// Tcl Message: "xvlog --incr --relax -prj top_tb_vlog.prj" +// TclEventType: LAUNCH_SIM_LOG +// Tcl Message: INFO: [USF-XSim-69] 'compile' step finished in '2' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim' +// Tcl Message: "xelab -wto 88fd13c424e241a2b1d7269d9396082e --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_tb_behav xil_defaultlib.top_tb xil_defaultlib.glbl -log elaborate.log" +// TclEventType: LAUNCH_SIM +// Tcl Message: INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim' INFO: [USF-XSim-98] *** Running xsim +// Tcl Message: with args "top_tb_behav -key {Behavioral:sim_1:Functional:top_tb} -tclbatch {top_tb.tcl} -log {simulate.log}" +// Tcl Message: INFO: [USF-XSim-8] Loading simulator feature +// Tcl Message: Vivado Simulator 2019.1 +// TclEventType: SIMULATION_CREATE_SIMULATION_OBJECT +// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE +// TclEventType: SIMULATION_UPDATE_SCOPE_TREE +// TclEventType: SIMULATION_UPDATE_STACKS +// TclEventType: SIMULATION_UPDATE_OBJECT_TREE +// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE +// Tcl Message: Time resolution is 1 ps +// TclEventType: SIMULATION_UPDATE_SCOPE_TREE +// TclEventType: SIMULATION_UPDATE_STACKS +// TclEventType: SIMULATION_UPDATE_OBJECT_TREE +// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE +// TclEventType: SIMULATION_UPDATE_SCOPE_TREE +// TclEventType: SIMULATION_UPDATE_STACKS +// TclEventType: SIMULATION_UPDATE_OBJECT_TREE +// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE +closeView(PAResourceOtoP.PAViews_PROJECT_SUMMARY, "Project Summary"); // v +// TclEventType: WAVEFORM_UPDATE_TITLE +// TclEventType: WAVEFORM_OPEN_WCFG +// TclEventType: SIMULATION_UPDATE_SCOPE_TREE +// TclEventType: SIMULATION_UPDATE_STACKS +// TclEventType: SIMULATION_UPDATE_OBJECT_TREE +// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE +// TclEventType: WAVEFORM_OPEN_WCFG +// Waveform: addNotify +// TclEventType: WAVEFORM_DELAYED_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// HMemoryUtils.trashcanNow. Engine heap size: 827 MB. GUI used memory: 98 MB. Current time: 10/20/22, 8:26:22 PM MSK +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: WAVEFORM_UPDATE_TITLE +// Tcl Message: source top_tb.tcl +// Tcl Message: # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } +// TclEventType: WAVEFORM_UPDATE_TITLE +// TclEventType: WAVEFORM_DELAYED_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_TITLE +// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE +// TclEventType: SIMULATION_CLEAR_CURRENT_LINE +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// TclEventType: SIMULATION_OBJECT_TREE_RESTORED +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED +// TclEventType: SIMULATION_CURRENT_STACK_CHANGED +// TclEventType: SIMULATION_UPDATE_STACK_FRAMES +// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED +// TclEventType: SIMULATION_UPDATE_LOCALS +// TclEventType: SIMULATION_UPDATE_SCOPE_TREE +// TclEventType: SIMULATION_UPDATE_STACKS +// TclEventType: SIMULATION_UPDATE_OBJECT_TREE +// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE +// Tcl Message: # run 1000ns +// Tcl Message: INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_tb_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns +// Tcl Message: launch_simulation: Time (s): cpu = 00:00:05 ; elapsed = 00:00:07 . Memory (MB): peak = 835.363 ; gain = 0.000 +// 'd' command handler elapsed time: 7 seconds +dismissDialog("Run Simulation"); // e (cl) +selectButton(PAResourceCommand.PACommandNames_SIMULATION_LIVE_RUN_ALL, "simulation_live_run_all"); // B (f, cl) +// Run Command: PAResourceCommand.PACommandNames_SIMULATION_LIVE_RUN_ALL +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE +// TclEventType: SIMULATION_CLEAR_CURRENT_LINE +// Tcl Message: run all +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// [GUI Memory]: 159 MB (+3327kb) [00:17:09] +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// HMemoryUtils.trashcanNow. Engine heap size: 828 MB. GUI used memory: 98 MB. Current time: 10/20/22, 8:26:27 PM MSK +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// HMemoryUtils.trashcanNow. Engine heap size: 828 MB. GUI used memory: 98 MB. Current time: 10/20/22, 8:26:32 PM MSK +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// Elapsed time: 11 seconds +selectButton(PAResourceCommand.PACommandNames_SIMULATION_LIVE_BREAK, "simulation_live_break"); // B (f, cl) +// Run Command: PAResourceCommand.PACommandNames_SIMULATION_LIVE_BREAK +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// TclEventType: SIMULATION_OBJECT_TREE_RESTORED +// TclEventType: WAVEFORM_MODEL_EVENT +// HMemoryUtils.trashcanNow. Engine heap size: 828 MB. GUI used memory: 124 MB. Current time: 10/20/22, 8:26:35 PM MSK +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_DELAYED_MODEL_EVENT +// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED +// TclEventType: SIMULATION_CURRENT_STACK_CHANGED +// TclEventType: SIMULATION_UPDATE_STACK_FRAMES +// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED +// TclEventType: SIMULATION_UPDATE_LOCALS +// TclEventType: SIMULATION_UPDATE_SCOPE_TREE +// TclEventType: SIMULATION_UPDATE_STACKS +// TclEventType: SIMULATION_UPDATE_OBJECT_TREE +// TclEventType: SIMULATION_STOPPED +// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE +// Tcl Message: run: Time (s): cpu = 00:00:14 ; elapsed = 00:00:12 . Memory (MB): peak = 835.363 ; gain = 0.000 +selectTreeTable(PAResourceQtoS.SimulationScopesPanel_SIMULATE_SCOPE_TABLE, "dut ; cpu_top ; Verilog Module", 1, "cpu_top", 1, true); // c (c, cl) - Node +// TclEventType: SIMULATION_REQUEST_SELECT_SCOPES +// TclEventType: SIMULATION_UPDATE_SCOPE_TREE +// TclEventType: SIMULATION_UPDATE_STACKS +// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED +// TclEventType: SIMULATION_CURRENT_STACK_CHANGED +// TclEventType: SIMULATION_UPDATE_STACK_FRAMES +// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED +// TclEventType: SIMULATION_UPDATE_LOCALS +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_MODEL_EVENT +selectButton(PAResourceTtoZ.TaskBanner_CLOSE, (String) null); // k (aA, cl) +closeTask("Simulation", "Behavioral Simulation - Functional - sim_1 - top_tb", "DesignTask.SIMULATION"); +// by (cl): Close : addNotify +// TclEventType: WAVEFORM_CLOSE_WCFG +// TclEventType: SIMULATION_CLOSE_SIMULATION +// Tcl Message: close_sim +// Tcl Message: INFO: [Simtcl 6-16] Simulation closed +dismissDialog("Close"); // by (cl) +// Elapsed time: 698 seconds +selectCodeEditor("cpu_top.sv", 624, 426); // cl (w, cl) +// TclEventType: DG_GRAPH_STALE +// TclEventType: FILE_SET_CHANGE +// Elapsed time: 64 seconds +selectCodeEditor("cpu_top.sv", 364, 189); // cl (w, cl) +selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Simulation, Run Simulation]", 10, false); // u (O, cl) +selectMenuItem(PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL, "Run Behavioral Simulation"); // ah (an, cl) +// Run Command: PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL +// e (cl): Run Simulation : addNotify +// TclEventType: LAUNCH_SIM +// TclEventType: FILE_SET_OPTIONS_CHANGE +// Tcl Message: launch_simulation +// Tcl Message: INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim' INFO: [SIM-utils-51] Simulation object is 'sim_1' INFO: [SIM-utils-54] Inspecting design source files for 'top_tb' in fileset 'sim_1'... INFO: [SIM-utils-43] Exported 'C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim/prog.txt' INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)... INFO: [USF-XSim-101] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim' +// Tcl Message: "xvlog --incr --relax -prj top_tb_vlog.prj" +// TclEventType: LAUNCH_SIM_LOG +// Tcl Message: INFO: [USF-XSim-69] 'compile' step finished in '2' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim' +// Tcl Message: "xelab -wto 88fd13c424e241a2b1d7269d9396082e --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_tb_behav xil_defaultlib.top_tb xil_defaultlib.glbl -log elaborate.log" +// TclEventType: LAUNCH_SIM +// Tcl Message: INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim' INFO: [USF-XSim-98] *** Running xsim +// Tcl Message: with args "top_tb_behav -key {Behavioral:sim_1:Functional:top_tb} -tclbatch {top_tb.tcl} -log {simulate.log}" +// Tcl Message: INFO: [USF-XSim-8] Loading simulator feature +// Tcl Message: Vivado Simulator 2019.1 +// TclEventType: SIMULATION_CREATE_SIMULATION_OBJECT +// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE +// TclEventType: SIMULATION_UPDATE_SCOPE_TREE +// TclEventType: SIMULATION_UPDATE_STACKS +// TclEventType: SIMULATION_UPDATE_OBJECT_TREE +// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE +// Tcl Message: Time resolution is 1 ps +// TclEventType: SIMULATION_UPDATE_SCOPE_TREE +// TclEventType: SIMULATION_UPDATE_STACKS +// TclEventType: SIMULATION_UPDATE_OBJECT_TREE +// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE +// TclEventType: SIMULATION_UPDATE_SCOPE_TREE +// TclEventType: SIMULATION_UPDATE_STACKS +// TclEventType: SIMULATION_UPDATE_OBJECT_TREE +// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE +closeView(PAResourceOtoP.PAViews_PROJECT_SUMMARY, "Project Summary"); // v +// TclEventType: WAVEFORM_UPDATE_TITLE +// TclEventType: WAVEFORM_OPEN_WCFG +// TclEventType: SIMULATION_UPDATE_SCOPE_TREE +// TclEventType: SIMULATION_UPDATE_STACKS +// TclEventType: SIMULATION_UPDATE_OBJECT_TREE +// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE +// TclEventType: WAVEFORM_OPEN_WCFG +// Waveform: addNotify +// TclEventType: WAVEFORM_DELAYED_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_DELAYED_MODEL_EVENT +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// HMemoryUtils.trashcanNow. Engine heap size: 832 MB. GUI used memory: 102 MB. Current time: 10/20/22, 8:39:41 PM MSK +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: WAVEFORM_UPDATE_TITLE +// TclEventType: WAVEFORM_DELAYED_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_TITLE +// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE +// TclEventType: SIMULATION_CLEAR_CURRENT_LINE +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// TclEventType: SIMULATION_OBJECT_TREE_RESTORED +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED +// TclEventType: SIMULATION_CURRENT_STACK_CHANGED +// TclEventType: SIMULATION_UPDATE_STACK_FRAMES +// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED +// TclEventType: SIMULATION_UPDATE_LOCALS +// TclEventType: SIMULATION_UPDATE_SCOPE_TREE +// TclEventType: SIMULATION_UPDATE_STACKS +// TclEventType: SIMULATION_UPDATE_OBJECT_TREE +// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE +// Tcl Message: source top_tb.tcl +// Tcl Message: # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns +// Tcl Message: INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_tb_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns +// Tcl Message: launch_simulation: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 835.363 ; gain = 0.000 +// 'd' command handler elapsed time: 7 seconds +dismissDialog("Run Simulation"); // e (cl) +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: SIMULATION_UPDATE_SCOPE_TREE +// TclEventType: SIMULATION_UPDATE_STACKS +selectTreeTable(PAResourceQtoS.SimulationScopesPanel_SIMULATE_SCOPE_TABLE, "dut ; cpu_top ; Verilog Module", 1, "dut", 0, true); // c (c, cl) - Node +// TclEventType: SIMULATION_REQUEST_SELECT_SCOPES +// TclEventType: SIMULATION_UPDATE_SCOPE_TREE +// TclEventType: SIMULATION_UPDATE_STACKS +// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED +// TclEventType: SIMULATION_CURRENT_STACK_CHANGED +// TclEventType: SIMULATION_UPDATE_STACK_FRAMES +// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED +// TclEventType: SIMULATION_UPDATE_LOCALS +selectTreeTable(PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE, "PC[5:0] ; 07 ; Array", 6, "PC[5:0]", 0, true); // c (c, cl) - Node +// TclEventType: SIMULATION_UPDATE_OBJECT_TREE +selectTreeTable(PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE, "PC[5:0] ; 07 ; Array", 6, "PC[5:0]", 0, true, false, false, false, false, true); // c (c, cl) - Double Click - Node +// TclEventType: SIMULATION_OPEN_SOURCE +selectTreeTable(PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE, "extended_const[31:0] ; fffffffd ; Array", 15, "fffffffd", 1, true); // c (c, cl) - Node +// TclEventType: SIMULATION_UPDATE_OBJECT_TREE +selectTreeTable(PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE, "extended_const[31:0] ; fffffffd ; Array", 15, "fffffffd", 1, true, false, false, false, false, true); // c (c, cl) - Double Click - Node +// TclEventType: SIMULATION_OPEN_SOURCE +selectTreeTable(PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE, "extended_const[31:0] ; fffffffd ; Array", 15, "fffffffd", 1, true); // c (c, cl) - Node +// TclEventType: SIMULATION_UPDATE_OBJECT_TREE +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: SIMULATION_UPDATE_SCOPE_TREE +// TclEventType: SIMULATION_UPDATE_STACKS +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: SIMULATION_UPDATE_OBJECT_TREE +// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE +selectTreeTable(PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE, "[1] ; 1 ; Logic", 11, "1", 1, false); // c (c, cl) +// TclEventType: SIMULATION_UPDATE_OBJECT_TREE +selectTreeTable(PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE, "extended_const[31:0] ; fffffffd ; Array", 15, "extended_const[31:0]", 0, true); // c (c, cl) - Node +selectTreeTable(PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE, "extended_const[31:0] ; fffffffd ; Array", 15, "fffffffd", 1, true); // c (c, cl) - Node +selectTreeTable(PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE, "extended_const[31:0] ; fffffffd ; Array", 15, "fffffffd", 1, true, false, false, false, false, true); // c (c, cl) - Double Click - Node +// TclEventType: SIMULATION_OPEN_SOURCE +selectTreeTable(PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE, "extended_const[31:0] ; fffffffd ; Array", 15, "fffffffd", 1, true); // c (c, cl) - Node +// TclEventType: SIMULATION_UPDATE_OBJECT_TREE +selectTreeTable(PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE, "extended_const[31:0] ; fffffffd ; Array", 15, "extended_const[31:0]", 0, true); // c (c, cl) - Node +selectTreeTable(PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE, "instruction[31:0] ; 80001fa0 ; Array", 8, "instruction[31:0]", 0, true); // c (c, cl) - Node +// Elapsed time: 10 seconds +selectTreeTable(PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE, "COUNTER_WIDTH[31:0] ; 6 ; Array", 24, "COUNTER_WIDTH[31:0]", 0, true); // c (c, cl) - Node +selectTreeTable(PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE, "[7] ; 1 ; Logic", 13, "[7]", 0, false); // c (c, cl) +selectTreeTable(PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE, "PC[5:0] ; 07 ; Array", 6, "PC[5:0]", 0, true); // c (c, cl) - Node +selectTreeTable(PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE, "ALU_res[31:0] ; 00000000 ; Array", 5, "ALU_res[31:0]", 0, true); // c (c, cl) - Node +selectTreeTable(PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE, "ALU_res[31:0] ; 00000000 ; Array", 5, "ALU_res[31:0]", 0, true); // c (c, cl) - Node +selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "alu_riscv.sv", 1); // k (j, cl) +selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "Untitled 6", 2); // k (j, cl) +selectButton(PAResourceCommand.PACommandNames_SIMULATION_LIVE_RUN, "simulation_live_run_for_time"); // B (f, cl) +// Run Command: PAResourceCommand.PACommandNames_SIMULATION_LIVE_RUN +// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE +// TclEventType: SIMULATION_CLEAR_CURRENT_LINE +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// TclEventType: SIMULATION_OBJECT_TREE_RESTORED +// HMemoryUtils.trashcanNow. Engine heap size: 832 MB. GUI used memory: 101 MB. Current time: 10/20/22, 8:40:55 PM MSK +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_DELAYED_MODEL_EVENT +// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED +// TclEventType: SIMULATION_CURRENT_STACK_CHANGED +// TclEventType: SIMULATION_UPDATE_STACK_FRAMES +// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED +// TclEventType: SIMULATION_UPDATE_LOCALS +// TclEventType: SIMULATION_UPDATE_SCOPE_TREE +// TclEventType: SIMULATION_UPDATE_STACKS +// TclEventType: SIMULATION_UPDATE_OBJECT_TREE +// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE +// Tcl Message: run 10 us +selectButton(PAResourceCommand.PACommandNames_SIMULATION_LIVE_RUN, "simulation_live_run_for_time"); // B (f, cl) +// Run Command: PAResourceCommand.PACommandNames_SIMULATION_LIVE_RUN +// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE +// TclEventType: SIMULATION_CLEAR_CURRENT_LINE +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// TclEventType: SIMULATION_OBJECT_TREE_RESTORED +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED +// TclEventType: SIMULATION_CURRENT_STACK_CHANGED +// TclEventType: SIMULATION_UPDATE_STACK_FRAMES +// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED +// TclEventType: SIMULATION_UPDATE_LOCALS +// TclEventType: SIMULATION_UPDATE_SCOPE_TREE +// TclEventType: SIMULATION_UPDATE_STACKS +// TclEventType: SIMULATION_UPDATE_OBJECT_TREE +// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE +// Tcl Message: run 10 us +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_MODEL_EVENT +selectButton(PAResourceCommand.PACommandNames_SIMULATION_LIVE_RUN, "simulation_live_run_for_time"); // B (f, cl) +// Run Command: PAResourceCommand.PACommandNames_SIMULATION_LIVE_RUN +// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE +// TclEventType: SIMULATION_CLEAR_CURRENT_LINE +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// TclEventType: SIMULATION_OBJECT_TREE_RESTORED +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_DELAYED_MODEL_EVENT +// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED +// TclEventType: SIMULATION_CURRENT_STACK_CHANGED +// TclEventType: SIMULATION_UPDATE_STACK_FRAMES +// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED +// TclEventType: SIMULATION_UPDATE_LOCALS +// TclEventType: SIMULATION_UPDATE_SCOPE_TREE +// TclEventType: SIMULATION_UPDATE_STACKS +// TclEventType: SIMULATION_UPDATE_OBJECT_TREE +// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE +// Tcl Message: run 10 us +selectButton(PAResourceCommand.PACommandNames_SIMULATION_LIVE_RUN, "simulation_live_run_for_time"); // B (f, cl) +// Run Command: PAResourceCommand.PACommandNames_SIMULATION_LIVE_RUN +// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE +// TclEventType: SIMULATION_CLEAR_CURRENT_LINE +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// TclEventType: SIMULATION_OBJECT_TREE_RESTORED +// HMemoryUtils.trashcanNow. Engine heap size: 832 MB. GUI used memory: 101 MB. Current time: 10/20/22, 8:41:02 PM MSK +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_DELAYED_MODEL_EVENT +// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED +// TclEventType: SIMULATION_CURRENT_STACK_CHANGED +// TclEventType: SIMULATION_UPDATE_STACK_FRAMES +// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED +// TclEventType: SIMULATION_UPDATE_LOCALS +// TclEventType: SIMULATION_UPDATE_SCOPE_TREE +// TclEventType: SIMULATION_UPDATE_STACKS +// TclEventType: SIMULATION_UPDATE_OBJECT_TREE +// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE +// Tcl Message: run 10 us +selectButton(PAResourceCommand.PACommandNames_SIMULATION_LIVE_RUN, "simulation_live_run_for_time"); // B (f, cl) +// Run Command: PAResourceCommand.PACommandNames_SIMULATION_LIVE_RUN +// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE +// TclEventType: SIMULATION_CLEAR_CURRENT_LINE +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// TclEventType: SIMULATION_OBJECT_TREE_RESTORED +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED +// TclEventType: SIMULATION_CURRENT_STACK_CHANGED +// TclEventType: SIMULATION_UPDATE_STACK_FRAMES +// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED +// TclEventType: SIMULATION_UPDATE_LOCALS +// TclEventType: SIMULATION_UPDATE_SCOPE_TREE +// TclEventType: SIMULATION_UPDATE_STACKS +// TclEventType: SIMULATION_UPDATE_OBJECT_TREE +// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE +// Tcl Message: run 10 us +selectButton(PAResourceCommand.PACommandNames_SIMULATION_LIVE_RUN, "simulation_live_run_for_time"); // B (f, cl) +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_MODEL_EVENT +// Run Command: PAResourceCommand.PACommandNames_SIMULATION_LIVE_RUN +// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE +// TclEventType: SIMULATION_CLEAR_CURRENT_LINE +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// TclEventType: SIMULATION_OBJECT_TREE_RESTORED +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_DELAYED_MODEL_EVENT +// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED +// TclEventType: SIMULATION_CURRENT_STACK_CHANGED +// TclEventType: SIMULATION_UPDATE_STACK_FRAMES +// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED +// TclEventType: SIMULATION_UPDATE_LOCALS +// TclEventType: SIMULATION_UPDATE_SCOPE_TREE +// TclEventType: SIMULATION_UPDATE_STACKS +// TclEventType: SIMULATION_UPDATE_OBJECT_TREE +// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE +// Tcl Message: run 10 us +selectButton(PAResourceCommand.PACommandNames_SIMULATION_LIVE_RUN, "simulation_live_run_for_time"); // B (f, cl) +// Run Command: PAResourceCommand.PACommandNames_SIMULATION_LIVE_RUN +// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE +// TclEventType: SIMULATION_CLEAR_CURRENT_LINE +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// TclEventType: SIMULATION_OBJECT_TREE_RESTORED +// HMemoryUtils.trashcanNow. Engine heap size: 832 MB. GUI used memory: 101 MB. Current time: 10/20/22, 8:41:05 PM MSK +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED +// TclEventType: SIMULATION_CURRENT_STACK_CHANGED +// TclEventType: SIMULATION_UPDATE_STACK_FRAMES +selectButton(PAResourceCommand.PACommandNames_SIMULATION_LIVE_RUN, "simulation_live_run_for_time"); // B (f, cl) +// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED +// TclEventType: SIMULATION_UPDATE_LOCALS +// TclEventType: SIMULATION_UPDATE_SCOPE_TREE +// TclEventType: SIMULATION_UPDATE_STACKS +// TclEventType: SIMULATION_UPDATE_OBJECT_TREE +// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE +// Tcl Message: run 10 us +selectButton(PAResourceCommand.PACommandNames_SIMULATION_LIVE_RUN, "simulation_live_run_for_time"); // B (f, cl) +// Run Command: PAResourceCommand.PACommandNames_SIMULATION_LIVE_RUN +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE +// TclEventType: SIMULATION_CLEAR_CURRENT_LINE +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// TclEventType: SIMULATION_OBJECT_TREE_RESTORED +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_DELAYED_MODEL_EVENT +// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED +// TclEventType: SIMULATION_CURRENT_STACK_CHANGED +// TclEventType: SIMULATION_UPDATE_STACK_FRAMES +// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED +// TclEventType: SIMULATION_UPDATE_LOCALS +// TclEventType: SIMULATION_UPDATE_SCOPE_TREE +// TclEventType: SIMULATION_UPDATE_STACKS +// TclEventType: SIMULATION_UPDATE_OBJECT_TREE +// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE +// Tcl Message: run 10 us +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: SIMULATION_UPDATE_OBJECT_TREE +selectTreeTable(PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE, "SW[15:0] ; 0004 ; Array", 1, "SW[15:0]", 0, true); // c (c, cl) - Node +selectTreeTable(PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE, "SW[15:0] ; 0004 ; Array", 1, "SW[15:0]", 0, true); // c (c, cl) - Node +selectTreeTable(PAResourceQtoS.SimulationScopesPanel_SIMULATE_SCOPE_TABLE, "im ; instruction_memory ; Verilog Module", 2, "im", 0, false); // c (c, cl) +// TclEventType: SIMULATION_REQUEST_SELECT_SCOPES +// TclEventType: SIMULATION_UPDATE_SCOPE_TREE +// TclEventType: SIMULATION_UPDATE_STACKS +// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED +// TclEventType: SIMULATION_CURRENT_STACK_CHANGED +// TclEventType: SIMULATION_UPDATE_STACK_FRAMES +// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED +// TclEventType: SIMULATION_UPDATE_LOCALS +// TclEventType: SIMULATION_UPDATE_OBJECT_TREE +selectTreeTable(PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE, "D[31:0] ; 80001fa0 ; Array", 1, "D[31:0]", 0, true); // c (c, cl) - Node +selectTreeTable(PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE, "D[31:0] ; 80001fa0 ; Array", 1, "D[31:0]", 0, true); // c (c, cl) - Node +selectTreeTable(PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE, "ROM[0:63][31:0] ; 200001a1,20000004,10000002,20000023,48080080,30102004,34086002,80001fa0,80100000,XXXXXXXX,XXXXXXXX,XXXXXXXX,XXXXXXXX,XXXXXXXX,XXXXXXXX,XXXXXXXX,XXXXXXXX,XXXXXXXX,XXXXXXXX,XXXXXXXX,XXXXXXXX,XXXXXXXX,XXXXXXXX,XXXXXXXX,XXXXXXXX,XXXXXXXX,XXXXXXXX,XXXXXXXX,XXXXXXXX,XXXXXXXX,XXXXXXXX,XXXXXXXX,XXXXXXXX,XXXXXXXX,XXXXXXXX,XXXXXXXX,XXXXXXXX,XXXXXXXX,XXXXXXXX,XXXXXXXX,XXXXXXXX,XXXXXXXX,XXXXXXXX,XXXXXXXX,XXXXXXXX,XXXXXXXX,XXXXXXXX,XXXXXXXX,XXXXXXXX,XXXXXXXX,XXXXXXXX,XXXXXXXX,XXXXXXXX,XXXXXXXX,XXXXXXXX,XXXXXXXX,XXXXXXXX,XXXXXXXX,XXXXXXXX,XXXXXXXX,XXXXXXXX,XXXXXXXX,XXXXXXXX,XXXXXXXX ; Array", 2, "ROM[0:63][31:0]", 0, true); // c (c, cl) - Node +selectTreeTable(PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE, "ROM[0:63][31:0] ; 200001a1,20000004,10000002,20000023,48080080,30102004,34086002,80001fa0,80100000,XXXXXXXX,XXXXXXXX,XXXXXXXX,XXXXXXXX,XXXXXXXX,XXXXXXXX,XXXXXXXX,XXXXXXXX,XXXXXXXX,XXXXXXXX,XXXXXXXX,XXXXXXXX,XXXXXXXX,XXXXXXXX,XXXXXXXX,XXXXXXXX,XXXXXXXX,XXXXXXXX,XXXXXXXX,XXXXXXXX,XXXXXXXX,XXXXXXXX,XXXXXXXX,XXXXXXXX,XXXXXXXX,XXXXXXXX,XXXXXXXX,XXXXXXXX,XXXXXXXX,XXXXXXXX,XXXXXXXX,XXXXXXXX,XXXXXXXX,XXXXXXXX,XXXXXXXX,XXXXXXXX,XXXXXXXX,XXXXXXXX,XXXXXXXX,XXXXXXXX,XXXXXXXX,XXXXXXXX,XXXXXXXX,XXXXXXXX,XXXXXXXX,XXXXXXXX,XXXXXXXX,XXXXXXXX,XXXXXXXX,XXXXXXXX,XXXXXXXX,XXXXXXXX,XXXXXXXX,XXXXXXXX,XXXXXXXX ; Array", 2, "ROM[0:63][31:0]", 0, true); // c (c, cl) - Node +selectTreeTable(PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE, "[7][31:0] ; 80001fa0 ; Array", 10, "80001fa0", 1, true); // c (c, cl) - Node +selectTreeTable(PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE, "[8][31:0] ; 80100000 ; Array", 11, "80100000", 1, true); // c (c, cl) - Node +selectButton(PAResourceCommand.PACommandNames_SIMULATION_LIVE_RUN, "simulation_live_run_for_time"); // B (f, cl) +// Run Command: PAResourceCommand.PACommandNames_SIMULATION_LIVE_RUN +// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE +// TclEventType: SIMULATION_CLEAR_CURRENT_LINE +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// TclEventType: SIMULATION_OBJECT_TREE_RESTORED +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_DELAYED_MODEL_EVENT +// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED +// TclEventType: SIMULATION_CURRENT_STACK_CHANGED +// TclEventType: SIMULATION_UPDATE_STACK_FRAMES +// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED +// TclEventType: SIMULATION_UPDATE_LOCALS +// TclEventType: SIMULATION_UPDATE_SCOPE_TREE +// TclEventType: SIMULATION_UPDATE_STACKS +// TclEventType: SIMULATION_UPDATE_OBJECT_TREE +// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE +// Tcl Message: run 10 us +selectButton(PAResourceCommand.PACommandNames_SIMULATION_LIVE_RUN, "simulation_live_run_for_time"); // B (f, cl) +// Run Command: PAResourceCommand.PACommandNames_SIMULATION_LIVE_RUN +// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE +// TclEventType: SIMULATION_CLEAR_CURRENT_LINE +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// TclEventType: SIMULATION_OBJECT_TREE_RESTORED +// HMemoryUtils.trashcanNow. Engine heap size: 832 MB. GUI used memory: 101 MB. Current time: 10/20/22, 8:41:38 PM MSK +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED +// TclEventType: SIMULATION_CURRENT_STACK_CHANGED +// TclEventType: SIMULATION_UPDATE_STACK_FRAMES +// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED +// TclEventType: SIMULATION_UPDATE_LOCALS +// TclEventType: SIMULATION_UPDATE_SCOPE_TREE +// TclEventType: SIMULATION_UPDATE_STACKS +// TclEventType: SIMULATION_UPDATE_OBJECT_TREE +// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE +selectButton(PAResourceCommand.PACommandNames_SIMULATION_LIVE_RUN, "simulation_live_run_for_time"); // B (f, cl) +// Tcl Message: run 10 us +// Run Command: PAResourceCommand.PACommandNames_SIMULATION_LIVE_RUN +// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE +// TclEventType: SIMULATION_CLEAR_CURRENT_LINE +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// TclEventType: SIMULATION_OBJECT_TREE_RESTORED +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_DELAYED_MODEL_EVENT +// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED +// TclEventType: SIMULATION_CURRENT_STACK_CHANGED +// TclEventType: SIMULATION_UPDATE_STACK_FRAMES +// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED +// TclEventType: SIMULATION_UPDATE_LOCALS +// TclEventType: SIMULATION_UPDATE_SCOPE_TREE +// TclEventType: SIMULATION_UPDATE_STACKS +// TclEventType: SIMULATION_UPDATE_OBJECT_TREE +// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE +// Tcl Message: run 10 us +selectButton(PAResourceCommand.PACommandNames_SIMULATION_LIVE_RUN, "simulation_live_run_for_time"); // B (f, cl) +// Run Command: PAResourceCommand.PACommandNames_SIMULATION_LIVE_RUN +// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE +// TclEventType: SIMULATION_CLEAR_CURRENT_LINE +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// TclEventType: SIMULATION_OBJECT_TREE_RESTORED +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED +// TclEventType: SIMULATION_CURRENT_STACK_CHANGED +// TclEventType: SIMULATION_UPDATE_STACK_FRAMES +// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED +// TclEventType: SIMULATION_UPDATE_LOCALS +// TclEventType: SIMULATION_UPDATE_SCOPE_TREE +// TclEventType: SIMULATION_UPDATE_STACKS +// TclEventType: SIMULATION_UPDATE_OBJECT_TREE +// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE +// Tcl Message: run 10 us +selectButton(PAResourceCommand.PACommandNames_SIMULATION_LIVE_RUN, "simulation_live_run_for_time"); // B (f, cl) +// Run Command: PAResourceCommand.PACommandNames_SIMULATION_LIVE_RUN +// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE +// TclEventType: SIMULATION_CLEAR_CURRENT_LINE +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// TclEventType: SIMULATION_OBJECT_TREE_RESTORED +// HMemoryUtils.trashcanNow. Engine heap size: 832 MB. GUI used memory: 101 MB. Current time: 10/20/22, 8:41:40 PM MSK +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED +// TclEventType: SIMULATION_CURRENT_STACK_CHANGED +// TclEventType: SIMULATION_UPDATE_STACK_FRAMES +// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED +// TclEventType: SIMULATION_UPDATE_LOCALS +// TclEventType: SIMULATION_UPDATE_SCOPE_TREE +// TclEventType: SIMULATION_UPDATE_STACKS +// TclEventType: SIMULATION_UPDATE_OBJECT_TREE +// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE +selectButton(PAResourceCommand.PACommandNames_SIMULATION_LIVE_RUN, "simulation_live_run_for_time"); // B (f, cl) +// Tcl Message: run 10 us +selectButton(PAResourceCommand.PACommandNames_SIMULATION_LIVE_RUN, "simulation_live_run_for_time"); // B (f, cl) +// Run Command: PAResourceCommand.PACommandNames_SIMULATION_LIVE_RUN +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE +// TclEventType: SIMULATION_CLEAR_CURRENT_LINE +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// TclEventType: SIMULATION_OBJECT_TREE_RESTORED +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_DELAYED_MODEL_EVENT +// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED +// TclEventType: SIMULATION_CURRENT_STACK_CHANGED +// TclEventType: SIMULATION_UPDATE_STACK_FRAMES +// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED +// TclEventType: SIMULATION_UPDATE_LOCALS +// TclEventType: SIMULATION_UPDATE_SCOPE_TREE +// TclEventType: SIMULATION_UPDATE_STACKS +// TclEventType: SIMULATION_UPDATE_OBJECT_TREE +// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE +// Tcl Message: run 10 us +selectTreeTable(PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE, "[8][31:0] ; 80100000 ; Array", 11, "80100000", 1, true); // c (c, cl) - Node +// TclEventType: SIMULATION_UPDATE_OBJECT_TREE +selectTreeTable(PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE, "[8][31:0] ; 80100000 ; Array", 11, "[8][31:0]", 0, true); // c (c, cl) - Node +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: SIMULATION_UPDATE_OBJECT_TREE +selectTreeTable(PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE, "[8][31:0] ; 80100000 ; Array", 11, "80100000", 1, true); // c (c, cl) - Node +selectButton(PAResourceCommand.PACommandNames_SIMULATION_LIVE_RUN, "simulation_live_run_for_time"); // B (f, cl) +// Run Command: PAResourceCommand.PACommandNames_SIMULATION_LIVE_RUN +// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE +// TclEventType: SIMULATION_CLEAR_CURRENT_LINE +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// TclEventType: SIMULATION_OBJECT_TREE_RESTORED +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_DELAYED_MODEL_EVENT +// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED +// TclEventType: SIMULATION_CURRENT_STACK_CHANGED +// TclEventType: SIMULATION_UPDATE_STACK_FRAMES +// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED +// TclEventType: SIMULATION_UPDATE_LOCALS +// TclEventType: SIMULATION_UPDATE_SCOPE_TREE +// TclEventType: SIMULATION_UPDATE_STACKS +// TclEventType: SIMULATION_UPDATE_OBJECT_TREE +// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE +// Tcl Message: run 10 us +selectButton(PAResourceCommand.PACommandNames_SIMULATION_LIVE_RUN, "simulation_live_run_for_time"); // B (f, cl) +// Run Command: PAResourceCommand.PACommandNames_SIMULATION_LIVE_RUN +// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE +// TclEventType: SIMULATION_CLEAR_CURRENT_LINE +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// TclEventType: SIMULATION_OBJECT_TREE_RESTORED +// HMemoryUtils.trashcanNow. Engine heap size: 832 MB. GUI used memory: 101 MB. Current time: 10/20/22, 8:41:48 PM MSK +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED +// TclEventType: SIMULATION_CURRENT_STACK_CHANGED +// TclEventType: SIMULATION_UPDATE_STACK_FRAMES +// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED +// TclEventType: SIMULATION_UPDATE_LOCALS +// TclEventType: SIMULATION_UPDATE_SCOPE_TREE +// TclEventType: SIMULATION_UPDATE_STACKS +// TclEventType: SIMULATION_UPDATE_OBJECT_TREE +// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE +// Tcl Message: run 10 us +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_MODEL_EVENT +selectTreeTable(PAResourceQtoS.SimulationScopesPanel_SIMULATE_SCOPE_TABLE, "dut ; cpu_top ; Verilog Module", 1, "cpu_top", 1, true); // c (c, cl) - Node +// TclEventType: SIMULATION_REQUEST_SELECT_SCOPES +// TclEventType: SIMULATION_UPDATE_SCOPE_TREE +// TclEventType: SIMULATION_UPDATE_STACKS +// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED +// TclEventType: SIMULATION_CURRENT_STACK_CHANGED +// TclEventType: SIMULATION_UPDATE_STACK_FRAMES +// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED +// TclEventType: SIMULATION_UPDATE_LOCALS +selectTreeTable(PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE, "PC[5:0] ; 07 ; Array", 6, "PC[5:0]", 0, true); // c (c, cl) - Node +// TclEventType: SIMULATION_UPDATE_OBJECT_TREE +selectTreeTable(PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE, "PC[5:0] ; 07 ; Array", 6, "PC[5:0]", 0, true); // c (c, cl) - Node +selectTreeTable(PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE, "PC[5:0] ; 07 ; Array", 6, "PC[5:0]", 0, true); // c (c, cl) - Node +selectTreeTable(PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE, "extended_switch[31:0] ; 00000004 ; Array", 7, "00000004", 1, true); // c (c, cl) - Node +selectTreeTable(PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE, "instruction[31:0] ; 80001fa0 ; Array", 8, "80001fa0", 1, true); // c (c, cl) - Node +selectTreeTable(PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE, "instruction[31:0] ; 80001fa0 ; Array", 8, "80001fa0", 1, true); // c (c, cl) - Node +// Elapsed time: 15 seconds +selectTreeTable(PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE, "PC[5:0] ; 07 ; Array", 6, "PC[5:0]", 0, true); // c (c, cl) - Node +selectTreeTable(PAResourceQtoS.SimulationScopesPanel_SIMULATE_SCOPE_TABLE, "im ; instruction_memory ; Verilog Module", 2, "instruction_memory", 1, false); // c (c, cl) +// TclEventType: SIMULATION_REQUEST_SELECT_SCOPES +// TclEventType: SIMULATION_UPDATE_SCOPE_TREE +// TclEventType: SIMULATION_UPDATE_STACKS +// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED +// TclEventType: SIMULATION_CURRENT_STACK_CHANGED +// TclEventType: SIMULATION_UPDATE_STACK_FRAMES +// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED +// TclEventType: SIMULATION_UPDATE_LOCALS +// TclEventType: SIMULATION_UPDATE_SCOPE_TREE +// TclEventType: SIMULATION_UPDATE_STACKS +selectTreeTable(PAResourceQtoS.SimulationScopesPanel_SIMULATE_SCOPE_TABLE, "im ; instruction_memory ; Verilog Module", 2, "instruction_memory", 1, false, false, false, false, false, true); // c (c, cl) - Double Click +// TclEventType: SIMULATION_REQUEST_SELECT_SCOPES +// TclEventType: SIMULATION_UPDATE_SCOPE_TREE +// TclEventType: SIMULATION_UPDATE_STACKS +// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED +// TclEventType: SIMULATION_CURRENT_STACK_CHANGED +// TclEventType: SIMULATION_UPDATE_STACK_FRAMES +// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED +// TclEventType: SIMULATION_UPDATE_LOCALS +// TclEventType: SIMULATION_OPEN_SOURCE +selectTreeTable(PAResourceQtoS.SimulationScopesPanel_SIMULATE_SCOPE_TABLE, "rf ; rf_riscv ; Verilog Module", 3, "rf_riscv", 1, false); // c (c, cl) +// TclEventType: SIMULATION_REQUEST_SELECT_SCOPES +// TclEventType: SIMULATION_UPDATE_SCOPE_TREE +// TclEventType: SIMULATION_UPDATE_STACKS +// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED +// TclEventType: SIMULATION_CURRENT_STACK_CHANGED +// TclEventType: SIMULATION_UPDATE_STACK_FRAMES +// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED +// TclEventType: SIMULATION_UPDATE_LOCALS +selectTreeTable(PAResourceQtoS.SimulationScopesPanel_SIMULATE_SCOPE_TABLE, "alu ; alu_riscv ; Verilog Module", 4, "alu_riscv", 1, false); // c (c, cl) +// TclEventType: SIMULATION_REQUEST_SELECT_SCOPES +// TclEventType: SIMULATION_UPDATE_SCOPE_TREE +// TclEventType: SIMULATION_UPDATE_STACKS +// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED +// TclEventType: SIMULATION_CURRENT_STACK_CHANGED +// TclEventType: SIMULATION_UPDATE_STACK_FRAMES +// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED +// TclEventType: SIMULATION_UPDATE_LOCALS +selectTreeTable(PAResourceQtoS.SimulationScopesPanel_SIMULATE_SCOPE_TABLE, "dut ; cpu_top ; Verilog Module", 1, "dut", 0, true); // c (c, cl) - Node +// TclEventType: SIMULATION_REQUEST_SELECT_SCOPES +// TclEventType: SIMULATION_UPDATE_SCOPE_TREE +// TclEventType: SIMULATION_UPDATE_STACKS +// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED +// TclEventType: SIMULATION_CURRENT_STACK_CHANGED +// TclEventType: SIMULATION_UPDATE_STACK_FRAMES +// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED +// TclEventType: SIMULATION_UPDATE_LOCALS +// TclEventType: SIMULATION_UPDATE_OBJECT_TREE +selectTreeTable(PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE, "instruction[31:0] ; 80001fa0 ; Array", 8, "instruction[31:0]", 0, true); // c (c, cl) - Node +selectTreeTable(PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE, "extended_const[31:0] ; fffffffd ; Array", 9, "extended_const[31:0]", 0, true); // c (c, cl) - Node +selectButton(PAResourceTtoZ.TaskBanner_CLOSE, (String) null); // k (aA, cl) +closeTask("Simulation", "Behavioral Simulation - Functional - sim_1 - top_tb", "DesignTask.SIMULATION"); +// by (cl): Close : addNotify +// TclEventType: WAVEFORM_CLOSE_WCFG +// TclEventType: SIMULATION_CLOSE_SIMULATION +// Tcl Message: close_sim +// Tcl Message: INFO: [Simtcl 6-16] Simulation closed +dismissDialog("Close"); // by (cl) +// WARNING: HEventQueue.dispatchEvent() is taking 2051837 ms. +// HMemoryUtils.trashcanNow. Engine heap size: 832 MB. GUI used memory: 100 MB. Current time: 10/20/22, 9:18:51 PM MSK +// Elapsed time: 2642 seconds +selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "cpu_top.sv", 1); // k (j, cl) +selectTab((HResource) null, "PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "cpu_top.sv", 1, false, true); // k (j, cl) - Double Click +maximizeView(PAResourceOtoP.PAViews_BASE_WORKSPACE, "BaseWorkspace"); // O (aH, cl) +// Elapsed time: 13 seconds +selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Simulation, Run Simulation]", 10, false); // u (O, cl) +selectMenuItem(PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL, "Run Behavioral Simulation"); // ah (an, cl) +// Run Command: PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL +// e (cl): Run Simulation : addNotify +// TclEventType: LAUNCH_SIM +// TclEventType: FILE_SET_OPTIONS_CHANGE +// Tcl Message: launch_simulation +// Tcl Message: INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim' INFO: [SIM-utils-51] Simulation object is 'sim_1' INFO: [SIM-utils-54] Inspecting design source files for 'top_tb' in fileset 'sim_1'... INFO: [SIM-utils-43] Exported 'C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim/prog.txt' INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)... INFO: [USF-XSim-101] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim' +// Tcl Message: "xvlog --incr --relax -prj top_tb_vlog.prj" +// TclEventType: LAUNCH_SIM_LOG +// Tcl Message: INFO: [USF-XSim-69] 'compile' step finished in '2' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim' +// Tcl Message: "xelab -wto 88fd13c424e241a2b1d7269d9396082e --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_tb_behav xil_defaultlib.top_tb xil_defaultlib.glbl -log elaborate.log" +// TclEventType: LAUNCH_SIM +// Tcl Message: INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim' INFO: [USF-XSim-98] *** Running xsim +// Tcl Message: with args "top_tb_behav -key {Behavioral:sim_1:Functional:top_tb} -tclbatch {top_tb.tcl} -log {simulate.log}" +// Tcl Message: INFO: [USF-XSim-8] Loading simulator feature +// Tcl Message: Vivado Simulator 2019.1 +// TclEventType: SIMULATION_CREATE_SIMULATION_OBJECT +// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE +// TclEventType: SIMULATION_UPDATE_SCOPE_TREE +// TclEventType: SIMULATION_UPDATE_STACKS +// TclEventType: SIMULATION_UPDATE_OBJECT_TREE +// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE +// TclEventType: SIMULATION_UPDATE_SCOPE_TREE +// TclEventType: SIMULATION_UPDATE_STACKS +// TclEventType: SIMULATION_UPDATE_OBJECT_TREE +// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE +// TclEventType: SIMULATION_UPDATE_SCOPE_TREE +// TclEventType: SIMULATION_UPDATE_STACKS +// TclEventType: SIMULATION_UPDATE_OBJECT_TREE +// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE +// Tcl Message: Time resolution is 1 ps +closeView(PAResourceOtoP.PAViews_PROJECT_SUMMARY, "Project Summary"); // v +// TclEventType: WAVEFORM_UPDATE_TITLE +// TclEventType: WAVEFORM_OPEN_WCFG +// TclEventType: SIMULATION_UPDATE_SCOPE_TREE +// TclEventType: SIMULATION_UPDATE_STACKS +// TclEventType: SIMULATION_UPDATE_OBJECT_TREE +// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE +// TclEventType: WAVEFORM_OPEN_WCFG +// Waveform: addNotify +// TclEventType: WAVEFORM_DELAYED_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_DELAYED_MODEL_EVENT +// TclEventType: WAVEFORM_MODEL_EVENT +// Tcl Message: source top_tb.tcl +// Tcl Message: # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// HMemoryUtils.trashcanNow. Engine heap size: 832 MB. GUI used memory: 98 MB. Current time: 10/20/22, 9:27:04 PM MSK +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: WAVEFORM_UPDATE_TITLE +// TclEventType: WAVEFORM_DELAYED_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_TITLE +// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE +// TclEventType: SIMULATION_CLEAR_CURRENT_LINE +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// TclEventType: SIMULATION_OBJECT_TREE_RESTORED +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED +// TclEventType: SIMULATION_CURRENT_STACK_CHANGED +// TclEventType: SIMULATION_UPDATE_STACK_FRAMES +// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED +// TclEventType: SIMULATION_UPDATE_LOCALS +// TclEventType: SIMULATION_UPDATE_SCOPE_TREE +// TclEventType: SIMULATION_UPDATE_STACKS +// TclEventType: SIMULATION_UPDATE_OBJECT_TREE +// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE +// Tcl Message: # run 1000ns +// Tcl Message: INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_tb_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns +// Tcl Message: launch_simulation: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 839.559 ; gain = 0.000 +// 'd' command handler elapsed time: 6 seconds +dismissDialog("Run Simulation"); // e (cl) +selectTreeTable(PAResourceQtoS.SimulationScopesPanel_SIMULATE_SCOPE_TABLE, "dut ; cpu_top ; Verilog Module", 1, "dut", 0, true); // c (c, cl) - Node +// TclEventType: SIMULATION_REQUEST_SELECT_SCOPES +// TclEventType: SIMULATION_UPDATE_SCOPE_TREE +// TclEventType: SIMULATION_UPDATE_STACKS +// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED +// TclEventType: SIMULATION_CURRENT_STACK_CHANGED +// TclEventType: SIMULATION_UPDATE_STACK_FRAMES +// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED +// TclEventType: SIMULATION_UPDATE_LOCALS +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_MODEL_EVENT +selectTreeTable(PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE, "rst ; 0 ; Logic", 2, "rst", 0, false); // c (c, cl) +// TclEventType: SIMULATION_UPDATE_OBJECT_TREE +selectTreeTable(PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE, "PC[5:0] ; 07 ; Array", 6, "PC[5:0]", 0, true); // c (c, cl) - Node +selectTreeTable(PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE, "PC[5:0] ; 07 ; Array", 6, "PC[5:0]", 0, true); // c (c, cl) - Node +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: WAVEFORM_UPDATE_TITLE +// TclEventType: WAVEFORM_DELAYED_MODEL_EVENT +// by (cl): Add to Waveform : addNotify +// TclEventType: WAVEFORM_DELAYED_MODEL_EVENT +dismissDialog("Add to Waveform"); // by (cl) +selectButton(PAResourceCommand.PACommandNames_SIMULATION_LIVE_RUN_ALL, "simulation_live_run_all"); // B (f, cl) +// Run Command: PAResourceCommand.PACommandNames_SIMULATION_LIVE_RUN_ALL +// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE +// TclEventType: SIMULATION_CLEAR_CURRENT_LINE +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_MODEL_EVENT +// Tcl Message: run all +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// HMemoryUtils.trashcanNow. Engine heap size: 832 MB. GUI used memory: 97 MB. Current time: 10/20/22, 9:27:17 PM MSK +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// HMemoryUtils.trashcanNow. Engine heap size: 832 MB. GUI used memory: 97 MB. Current time: 10/20/22, 9:27:22 PM MSK +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// Elapsed time: 11 seconds +selectButton(PAResourceCommand.PACommandNames_SIMULATION_LIVE_BREAK, "simulation_live_break"); // B (f, cl) +// Run Command: PAResourceCommand.PACommandNames_SIMULATION_LIVE_BREAK +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// TclEventType: SIMULATION_OBJECT_TREE_RESTORED +// HMemoryUtils.trashcanNow. Engine heap size: 832 MB. GUI used memory: 97 MB. Current time: 10/20/22, 9:27:26 PM MSK +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_DELAYED_MODEL_EVENT +// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED +// TclEventType: SIMULATION_CURRENT_STACK_CHANGED +// TclEventType: SIMULATION_UPDATE_STACK_FRAMES +// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED +// TclEventType: SIMULATION_UPDATE_LOCALS +// TclEventType: SIMULATION_UPDATE_SCOPE_TREE +// TclEventType: SIMULATION_UPDATE_STACKS +// TclEventType: SIMULATION_UPDATE_OBJECT_TREE +// TclEventType: SIMULATION_STOPPED +// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE +// Tcl Message: run: Time (s): cpu = 00:00:14 ; elapsed = 00:00:12 . Memory (MB): peak = 839.559 ; gain = 0.000 +selectButton(PAResourceTtoZ.TaskBanner_CLOSE, (String) null); // k (aA, cl) +closeTask("Simulation", "Behavioral Simulation - Functional - sim_1 - top_tb", "DesignTask.SIMULATION"); +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_MODEL_EVENT +selectButton("OptionPane.button", "Cancel"); // JButton (A, G) +selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "Untitled 7*", 3); // k (j, cl) +selectButton(RDIResource.WaveformView_GOTO_TIME_0, "Waveform Viewer_RunReset"); // B (f, cl) +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// HMemoryUtils.trashcanNow. Engine heap size: 832 MB. GUI used memory: 97 MB. Current time: 10/20/22, 9:27:37 PM MSK +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// HMemoryUtils.trashcanNow. Engine heap size: 832 MB. GUI used memory: 97 MB. Current time: 10/20/22, 9:27:38 PM MSK +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// HMemoryUtils.trashcanNow. Engine heap size: 832 MB. GUI used memory: 97 MB. Current time: 10/20/22, 9:27:38 PM MSK +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// Elapsed time: 27 seconds +selectButton(PAResourceTtoZ.TaskBanner_CLOSE, (String) null); // k (aA, cl) +closeTask("Simulation", "Behavioral Simulation - Functional - sim_1 - top_tb", "DesignTask.SIMULATION"); +// TclEventType: WAVEFORM_UPDATE_TITLE +// TclEventType: WAVEFORM_CLOSE_WCFG +// by (cl): Close : addNotify +selectButton("OptionPane.button", "Discard"); // JButton (A, G) +// TclEventType: SIMULATION_CLOSE_SIMULATION +// Tcl Message: close_sim +// Tcl Message: INFO: [Simtcl 6-16] Simulation closed +dismissDialog("Close"); // by (cl) +unMinimizeFrame(PAResourceOtoP.PAViews_SOURCES, "Sources"); // az (aK) +selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation Sources, sim_1, top_tb (top_tb.sv)]", 13, true); // B (F, cl) - Node +selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation Sources, sim_1, top_tb (top_tb.sv)]", 13, true, false, false, false, false, true); // B (F, cl) - Double Click - Node +selectCodeEditor("top_tb.sv", 607, 489); // cl (w, cl) +// HMemoryUtils.trashcanNow. Engine heap size: 832 MB. GUI used memory: 97 MB. Current time: 10/20/22, 9:57:42 PM MSK +// HMemoryUtils.trashcanNow. Engine heap size: 832 MB. GUI used memory: 95 MB. Current time: 10/20/22, 10:27:42 PM MSK +// HMemoryUtils.trashcanNow. Engine heap size: 832 MB. GUI used memory: 95 MB. Current time: 10/20/22, 10:57:43 PM MSK +// WARNING: HTimer (ActiveMsgMonitor Process Messages Timer) is taking 36007450ms to process. Increasing delay to 2000 ms. +// WARNING: HEventQueue.dispatchEvent() is taking 36007474 ms. +// WARNING: HSwingWorker (Monitor File Timestamp Swing Worker) is taking 36007451 ms to process. Increasing delay to 2000 ms. +// WARNING: HSwingWorker (Monitor File Timestamp Swing Worker) is taking 36007486 ms to process. Increasing delay to 2000 ms. +// HMemoryUtils.trashcanNow. Engine heap size: 832 MB. GUI used memory: 95 MB. Current time: 10/21/22, 9:12:47 AM MSK +// HMemoryUtils.trashcanNow. Engine heap size: 832 MB. GUI used memory: 95 MB. Current time: 10/21/22, 9:42:47 AM MSK +// WARNING: HSwingWorker (Monitor File Timestamp Swing Worker) is taking 199362444 ms to process. Increasing delay to 3000 ms. +// WARNING: HSwingWorker (Monitor File Timestamp Swing Worker) is taking 199362434 ms to process. Increasing delay to 3000 ms. +// WARNING: HEventQueue.dispatchEvent() is taking 199362610 ms. +// HMemoryUtils.trashcanNow. Engine heap size: 832 MB. GUI used memory: 95 MB. Current time: 10/23/22, 5:20:38 PM MSK +// Elapsed time: 244353 seconds +selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation Sources, sim_1, Memory Initialization Files, prog.txt]", 19, false); // B (F, cl) +selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation Sources, sim_1, Memory Initialization Files, prog.txt]", 19, false, false, false, false, false, true); // B (F, cl) - Double Click +// ad (cl): Unable to Open File: addNotify +// WARNING: HEventQueue.dispatchEvent() is taking 12961 ms. +// Elapsed time: 37 seconds +selectButton(PAResourceOtoP.OpenFileAction_OPEN_DIRECTORY, "Open Directory"); // a (ad) +dismissDialog("Unable to Open File"); // ad (cl) +// Elapsed time: 255 seconds +selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation Sources, sim_1, Memory Initialization Files, prog.txt]", 19, false); // B (F, cl) +selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation Sources, sim_1, Memory Initialization Files, prog.txt]", 19, false, false, false, false, false, true); // B (F, cl) - Double Click +// ad (cl): Unable to Open File: addNotify +selectButton(PAResourceOtoP.OpenFileAction_OPEN_DIRECTORY, "Open Directory"); // a (ad) +dismissDialog("Unable to Open File"); // ad (cl) +// TclEventType: DG_GRAPH_STALE +// TclEventType: FILE_SET_CHANGE +// Elapsed time: 19 seconds +selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation Sources, sim_1, top_tb (top_tb.sv)]", 13, true); // B (F, cl) - Node +selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation Sources, sim_1, top_tb (top_tb.sv)]", 13, true); // B (F, cl) - Node +selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation Sources, sim_1, top_tb (top_tb.sv)]", 13, true, false, false, false, false, true); // B (F, cl) - Double Click - Node +selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Simulation, Run Simulation]", 10, false); // u (O, cl) +selectMenuItem(PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL, "Run Behavioral Simulation"); // ah (an, cl) +// Run Command: PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL +// e (cl): Run Simulation : addNotify +// TclEventType: LAUNCH_SIM +// TclEventType: FILE_SET_OPTIONS_CHANGE +// Tcl Message: launch_simulation +// Tcl Message: INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim' INFO: [SIM-utils-51] Simulation object is 'sim_1' INFO: [SIM-utils-54] Inspecting design source files for 'top_tb' in fileset 'sim_1'... INFO: [SIM-utils-43] Exported 'C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim/prog.txt' INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)... INFO: [USF-XSim-101] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim' +// Tcl Message: "xvlog --incr --relax -prj top_tb_vlog.prj" +// TclEventType: LAUNCH_SIM_LOG +// Tcl Message: INFO: [USF-XSim-69] 'compile' step finished in '2' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim' +// Tcl Message: "xelab -wto 88fd13c424e241a2b1d7269d9396082e --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_tb_behav xil_defaultlib.top_tb xil_defaultlib.glbl -log elaborate.log" +// TclEventType: LAUNCH_SIM +// Tcl Message: INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Alex/APS/aps_/aps_.sim/sim_1/behav/xsim' INFO: [USF-XSim-98] *** Running xsim +// Tcl Message: with args "top_tb_behav -key {Behavioral:sim_1:Functional:top_tb} -tclbatch {top_tb.tcl} -log {simulate.log}" +// Tcl Message: INFO: [USF-XSim-8] Loading simulator feature +// Tcl Message: Vivado Simulator 2019.1 +// TclEventType: SIMULATION_CREATE_SIMULATION_OBJECT +// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE +// TclEventType: SIMULATION_UPDATE_SCOPE_TREE +// TclEventType: SIMULATION_UPDATE_STACKS +// TclEventType: SIMULATION_UPDATE_OBJECT_TREE +// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE +// TclEventType: SIMULATION_UPDATE_SCOPE_TREE +// TclEventType: SIMULATION_UPDATE_STACKS +// TclEventType: SIMULATION_UPDATE_OBJECT_TREE +// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE +// TclEventType: SIMULATION_UPDATE_SCOPE_TREE +// TclEventType: SIMULATION_UPDATE_STACKS +// TclEventType: SIMULATION_UPDATE_OBJECT_TREE +// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE +closeView(PAResourceOtoP.PAViews_PROJECT_SUMMARY, "Project Summary"); // v +// Tcl Message: Time resolution is 1 ps +// TclEventType: WAVEFORM_UPDATE_TITLE +// TclEventType: WAVEFORM_OPEN_WCFG +// TclEventType: SIMULATION_UPDATE_SCOPE_TREE +// TclEventType: SIMULATION_UPDATE_STACKS +// TclEventType: SIMULATION_UPDATE_OBJECT_TREE +// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE +// TclEventType: WAVEFORM_OPEN_WCFG +// Waveform: addNotify +// TclEventType: WAVEFORM_DELAYED_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_DELAYED_MODEL_EVENT +// TclEventType: WAVEFORM_MODEL_EVENT +// Tcl Message: source top_tb.tcl +// Tcl Message: # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// HMemoryUtils.trashcanNow. Engine heap size: 832 MB. GUI used memory: 100 MB. Current time: 10/23/22, 5:26:14 PM MSK +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: WAVEFORM_UPDATE_TITLE +// TclEventType: WAVEFORM_DELAYED_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_TITLE +// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE +// TclEventType: SIMULATION_CLEAR_CURRENT_LINE +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// TclEventType: SIMULATION_OBJECT_TREE_RESTORED +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: SIMULATION_UPDATE_LATEST_TIME +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED +// TclEventType: SIMULATION_CURRENT_STACK_CHANGED +// TclEventType: SIMULATION_UPDATE_STACK_FRAMES +// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED +// TclEventType: SIMULATION_UPDATE_LOCALS +// TclEventType: SIMULATION_UPDATE_SCOPE_TREE +// TclEventType: SIMULATION_UPDATE_STACKS +// TclEventType: SIMULATION_UPDATE_OBJECT_TREE +// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE +// Tcl Message: # run 1000ns +// Tcl Message: INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_tb_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns +// Tcl Message: launch_simulation: Time (s): cpu = 00:00:05 ; elapsed = 00:00:07 . Memory (MB): peak = 839.559 ; gain = 0.000 +// 'd' command handler elapsed time: 7 seconds +dismissDialog("Run Simulation"); // e (cl) +// TclEventType: WAVEFORM_MODEL_EVENT +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_MODEL_EVENT +// Elapsed time: 85 seconds +selectButton(RDIResource.WaveformView_GOTO_TIME_0, "Waveform Viewer_RunReset"); // B (f, cl) +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +selectButton(RDIResource.GraphicalView_ZOOM_OUT, "Waveform Viewer_zoom_out"); // B (f, cl) +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// HMemoryUtils.trashcanNow. Engine heap size: 832 MB. GUI used memory: 100 MB. Current time: 10/23/22, 5:27:43 PM MSK +selectButton(RDIResource.GraphicalView_ZOOM_OUT, "Waveform Viewer_zoom_out"); // B (f, cl) +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +selectButton(RDIResource.GraphicalView_ZOOM_OUT, "Waveform Viewer_zoom_out"); // B (f, cl) +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// HMemoryUtils.trashcanNow. Engine heap size: 832 MB. GUI used memory: 100 MB. Current time: 10/23/22, 5:27:43 PM MSK +selectButton(RDIResource.GraphicalView_ZOOM_OUT, "Waveform Viewer_zoom_out"); // B (f, cl) +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +selectButton(RDIResource.GraphicalView_ZOOM_OUT, "Waveform Viewer_zoom_out"); // B (f, cl) +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +selectButton(RDIResource.GraphicalView_ZOOM_OUT, "Waveform Viewer_zoom_out"); // B (f, cl) +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// HMemoryUtils.trashcanNow. Engine heap size: 832 MB. GUI used memory: 100 MB. Current time: 10/23/22, 5:27:44 PM MSK +selectButton(RDIResource.GraphicalView_ZOOM_OUT, "Waveform Viewer_zoom_out"); // B (f, cl) +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +selectButton(RDIResource.GraphicalView_ZOOM_OUT, "Waveform Viewer_zoom_out"); // B (f, cl) +// TclEventType: WAVEFORM_UPDATE_WAVEFORM +// TclEventType: WAVEFORM_UPDATE_COMMANDS +// Elapsed time: 80 seconds +selectButton(PAResourceTtoZ.TaskBanner_CLOSE, (String) null); // k (aA, cl) +closeTask("Simulation", "Behavioral Simulation - Functional - sim_1 - top_tb", "DesignTask.SIMULATION"); +// by (cl): Close : addNotify +// TclEventType: WAVEFORM_CLOSE_WCFG +// TclEventType: SIMULATION_CLOSE_SIMULATION +// WARNING: HEventQueue.dispatchEvent() is taking 1120 ms. +// Tcl Message: close_sim +// Tcl Message: INFO: [Simtcl 6-16] Simulation closed +// Tcl Message: close_sim: Time (s): cpu = 00:00:04 ; elapsed = 00:00:10 . Memory (MB): peak = 839.988 ; gain = 0.430 +// Elapsed time: 10 seconds +dismissDialog("Close"); // by (cl) +selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "cpu_top.sv", 1); // k (j, cl) +selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "alu_riscv.sv", 2); // k (j, cl) +selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "instruction_memory.sv", 3); // k (j, cl) +selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "top_tb.sv", 4); // k (j, cl) +selectCodeEditor("top_tb.sv", 524, 543); // cl (w, cl) +selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "Project Summary", 0); // k (j, cl) +selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "cpu_top.sv", 1); // k (j, cl) +// HMemoryUtils.trashcanNow. Engine heap size: 832 MB. GUI used memory: 98 MB. Current time: 10/23/22, 5:57:46 PM MSK +// HMemoryUtils.trashcanNow. Engine heap size: 832 MB. GUI used memory: 98 MB. Current time: 10/23/22, 6:27:46 PM MSK +// HMemoryUtils.trashcanNow. Engine heap size: 832 MB. GUI used memory: 98 MB. Current time: 10/23/22, 6:57:46 PM MSK +// HMemoryUtils.trashcanNow. Engine heap size: 832 MB. GUI used memory: 98 MB. Current time: 10/23/22, 7:27:47 PM MSK +// HMemoryUtils.trashcanNow. Engine heap size: 832 MB. GUI used memory: 98 MB. Current time: 10/23/22, 7:57:47 PM MSK +// HMemoryUtils.trashcanNow. Engine heap size: 832 MB. GUI used memory: 98 MB. Current time: 10/23/22, 8:27:47 PM MSK +// HMemoryUtils.trashcanNow. Engine heap size: 832 MB. GUI used memory: 98 MB. Current time: 10/23/22, 8:57:47 PM MSK +// HMemoryUtils.trashcanNow. Engine heap size: 832 MB. GUI used memory: 98 MB. Current time: 10/23/22, 9:27:48 PM MSK +// HMemoryUtils.trashcanNow. Engine heap size: 832 MB. GUI used memory: 98 MB. Current time: 10/23/22, 9:57:48 PM MSK +// HMemoryUtils.trashcanNow. Engine heap size: 832 MB. GUI used memory: 98 MB. Current time: 10/23/22, 10:27:48 PM MSK +// HMemoryUtils.trashcanNow. Engine heap size: 832 MB. GUI used memory: 98 MB. Current time: 10/23/22, 10:57:48 PM MSK +// HMemoryUtils.trashcanNow. Engine heap size: 832 MB. GUI used memory: 98 MB. Current time: 10/23/22, 11:27:49 PM MSK +// HMemoryUtils.trashcanNow. Engine heap size: 832 MB. GUI used memory: 98 MB. Current time: 10/23/22, 11:57:49 PM MSK +// WARNING: HEventQueue.dispatchEvent() is taking 37154795 ms. +// HMemoryUtils.trashcanNow. Engine heap size: 832 MB. GUI used memory: 98 MB. Current time: 10/24/22, 10:19:17 AM MSK +// Elapsed time: 60644 seconds +selectCodeEditor("cpu_top.sv", 639, 251); // cl (w, cl)