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CQKC_D_34_40_45.txt
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CQKC_D_34_40_45.txt
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//
// From DCQKCD listing of 4-sep-74 11:53 contained in file:
// bitsavers.informatik.uni-stuttgart.de/pdf/dec/pdp11/xxdp/diag_listings/1140_45/028_MAINDEC-11-DCQKC-D_D_1140_1145_INSTRUCTION_EXERCISER_Sep74.pdf
//
// All values in octal unless otherwise noted.
//
//
// Syntax:
//
// = address set address origin
// nnnnnn [nnnnnn] [nnnnnn] one to three 16-bit octal word values (instructions, operands and data)
// b nnn single byte value, pc incremented by 1
// = nnnnnn set pc origin, subsequently incremented by 2/1 for word/byte values
// : nnnnnn consistency check: pc of the previous word must match this value
// :: nnnnnn consistency check: pc of the current word must match this value
//
//
// Process with txt2abs program to do consistency checks and generate .abs "absolute format" file
// for use by absolute loader (see Makefile) of various emulation program.
//
//
// Status:
//
// Untested on PDP-11/04 system (use "#define 11/04")
// Runs on 11/04 CPU board using PUniBone (use "#define PB_11/04")
//
// Runs on 11/05 emulator
// Untested on 11/05 hardware
//
// Runs on 11/20 emulator (cpu20 of UniBone, use "#define 11/20")
//
// Runs on 11/34 emulator (use "#define 11/34")
// Untested on 11/34 hardware
//
// Runs on 11/40 emulator
// Untested on 11/40 hardware
//
// Untested on 11/45 hardware
//
// Switch register options tested on 11/40,34 emulator:
// ok Relocation 28kW or below
// ok Relocation above 28kW using MMU
// ok Relocation via RK disk emulator (--swreg xxxx31)
// ok Tested with KW11-L (line clock) & KL11 (serial console) emulators
// untested Operation with emulated parity error etc.
// untested Operation with other disk devices (RF, RP, RC, RS04)
//
//
// Searching:
// Note that for each page number shown in the program listing of the PDF document
// the corresponding comment "// page NN" appears below.
//
//
// Memory map:
//
// 20 iot vec
// 24 p.fail vec
// 30 scopeA vec
// 34 .hlt vec
// 60 tk vec
// 114 parity vec
//
// 120 mamf
// 164
//
// 172 patch vars
// 176 psw save for later inspection
// 200
//
// 200 entry points
// 204
// 210
// 214
//
// 244 FIS vec
// 250 mem mgt vec
//
// 300 patch area start (grows up)
// 300 CQKC_E0_FIX
// 316 (first free)
//
// 320 PSW_USER
// 344 (first free)
//
// 332 PB_11/04 TTYCHK debug (NB: conflicts with PSW_USER above!)
// 354 or 362 (first free, depends on particular debug code varient)
//
// 362 LMA_HIGHER
// 400 (first free)
//
// 476
// 500 stkptr stack (grows down)
//
// 576
// 600 kptr stack (grows down)
//
// 610 pdwn
// ...
// 32436 end
//
//
// Conditional compilation: (can be set here with #define or with "--def xxx" arguments to txt2abs)
//
#define CQKC_E0_FIX
// A bug in the RESTPS entry point of the CLRTBIT routine is fixed by including a patch based on a
// correction included in the CQKC E0 revision.
//
// #define 11/20
// Changes to support running on the 11/20:
// SWAB insn does *not* change V-bit. Don't believe it? I didn't either until I read this:
// bitsavers.org/pdf/dec/pdp11/1173/EK-DCJ11-UG-PRE_J11ug_Oct83.pdf
// PDF page 230, Table C-1, item 6 "SWAB does *not* change V"
//
// #define 11/04
// Changes to support the 11/04:
// In cpchk make 11/04 look like an 11/05.
//
// #define 11/34
// Changes to support the 11/34:
// Stack overflow detection differences.
// Different illegal range definitions due to added MTPS=1064xx MFPS=1067xx insns.
//
// #define PSW_USER
// Begin pass #0000 in user mode instead of kernel mode (gets to failure quicker).
//
// #define LMA_HIGHER
// Start probe for last memory address at address higher than default of zero.
//
// #define START_TTYCHK
// Start with TTYCHK test.
//
// #define PB_11/04
// Changes to support 11/04 testing using PUniBone.
//
//
// 2019-2021
//
//
// Common switch register settings:
//
// 100000 15 halt on error
// 040000 14 loop current subtest
// 020000 13 inhibit error print
// 010000 12 inhibit relocation
// 004000 11 inhibit subtest iteration
// 002000 10 ring bell on error
//
// CQKC-specific:
// 001000 09 inhibit relocation above 28kW (set 12 or 09 or neither, but never both)
// 000400 08 load PDP-11/45 ubreak reg from swreg<7:0>
// 000200 07 enable end-of-pass typeout (value inverted in CQKC_G2)
// 000100 06 inhibit clock interrupts (after test completes)
// 000040 05 enable relocation via all available disks
// 000020 04 enable random disk relocation address (else always zero)
// 000010 03 enable relocation via i/o device
// 000007 field: relocation i/o device code
// 000001 RK disk
//
// Typical values used:
// 14200 // swreg: inh reloc, inh subtst iter, eo-pass-print, no i/o device (WORKS)
// 5200 // swreg: inh reloc > 28kW, inh subtst iter, eo-pass-print, no i/o device (WORKS)
// 4200 // swreg: inh subtst iter, eo-pass-print, no i/o device (WORKS)
// 4231 // swreg: inh subtst iter, eo-pass-print, use rk (WORKS)
//
// pick one, either here or via "--def xxx" argument to txt2abs in Makefile
//#define 11/20
//#define 11/04
//#define 11/34
//#define PB_11/04
#ifdef PB_11/04
#define 11/04
#endif
// page 7
// iotvec = .type, spl4
= 20
2564
200
#ifdef PB_11/04
// prereq #1
// p.fail 024 = start 0200, spl7
200
340
#else
// p.fail 024 = pdwn, spl7
610
340
#endif
// 030 = scopeA, spl4
1014
200
// 034 = .hlt, spl7
3212
340
: 36
// tkvec = tkisr, spl4
= 60
3130 // listing obscured, but = tkisr
200
:: 64
//#ifdef PB_11/04
#ifdef notdef
// catch lk interrupts if still enabled from previous testing
= 100
102
2
#endif
// parity & p.fail
// .mamf
= 120
12737 4356 114
12737 340 116
12737 6 4
12700 172100
12702 1
12720 1
6302
103374
207
: 162
// entry vectors
= 200
12707 5422 // start
12707 5532 // start1
12707 5600 // start3
: 212
// fis trap
= 244
246
2
: 246
// mmu psw
= 252
340
: 252
// pdwn
= 610
5737 764
100002
5037 177572
12737 632 24 // p.fail vec = pup @632
0
// pup
:: 632
12737 610 24 // p.fail vec = pdwn @610
12706 600
: 642
// page 8
5027
: 644
0
5267 177772
1375
4 666
137 5422
: 664
// .asciz
5015 47520 42527
20122 40506 46111
42105 5015
b 0
b 15
50012 51101
52111 20131 51105
47522 6522 12
// page 9
// memtbl
0
: 730
0
0
0
0
// .ascii
20040 42440 51122
51117
5015
b 0
b 134
b 0
b 0
b 0
b 0
= 762
// eabits
0
// opt.cp
//
// Values reported by CQKC OPT.CP=
//
// 100000 15 mmu
// 040000 14 eis (11/40 option)
// 020000 13 fpp 11/45
// 010000 12 fis 11/40
// 004000 11 stack lim (11/40 option)
// 002000 10 kw11-p
// 001000 09 kw11-l
// 000400 08 tty
// 000377 cp field: 06=11/45 04=11/40, 02=11/20, 00=11/05,04
400
: 764
// options
0
b 1
b 0
= 770
b 0
b 0
0
0
0
0
// $fills
// originally fill count = 1, fill char = 0
// we set count to zero
//1000
0
0
0
0
0
// scopea
122737 10 764
1005
: 1022
// page 10
5037 177766
: 1026
12737 177777 177744
32766 4000 2
1403
52737 4000 177776
32737 40000 177570 // swreg
1416
10116
10137 1006
163737 1004 1006
32737 400 177570 // swreg
1403
113737 177570 177770 // swreg
2
32737 4000 177570 // swreg
1006
5327
40
1353
113767 1150 177766
11601
746
40
: 1150
// page 11
// reloc
32737 10000 177570 // swreg
: 1156
1404
32737 1000 177570 // swreg
1465
105737 770
1062
13700 1010
10005
10204
160504
10203
5737 1004
1004
10237 1360
13702 1012
60204
20437 5504
101046
160204
5037 1004
32737 40 177570 // swreg
1007
32737 10 177570 // swreg
1410
113737 177570 757 // swreg
5037 762
4767 112
102003
12022
20003
1375
24042
1403
4767 1154
104400
20005
1371
162737 10 772
1742
105237 757
5037 772
10207
11707
0
: 1360
// waitio
13704
0
105737 770
1404
42704 160000
52704 40000
: 1402
// page 12
24414
1401
104400
62714 0
761
: 1416
// page 13
// iodev
4767 1106
: 1422
10546
52737 200 177776
142737 370 757
113705 757
6305
16505 2266
1005
4737 2556
12605
262
207
12737 6 4
261
: 1476
// page 14
5775 12
12737 5274 4
103020
32737 40 177570 // swreg
1403
105237 757
741
113705 757
6305
16567 4156 30602
4 32346
741
112737 3 760
10427
0
10446
6216
5416
12667 322
113737 757 772
13727 762
0
123727 757 4
3415
6367 177762
6367 177756
6367 177752
6367 177746
12735 21
12735 10000
12535
12546
12776 1732 0
62716 2
12736 240
4767 222
16735 306
16735 310
11537 1364
10035
16735 176
16535 2
614
12716 1740
2
15504
100011
104400
16535 6
162705 12
105337 760
: 1760
// page 15
1347
634
112737 3 760
162705 12
12735 2046
16735 204
16735 206
11537 1364
10235
16735 74
16746 177560
56516 4
12675 0
240
731
12716 2054
2
13504
100007
104400
16555 4
105337 760
1340
733
12605
66700 177460
66702 177454
4767 442
242
167 177344
0
// dskadr
32737 20 177570 // swreg
: 2130
1426
10046
13700 772
6300
6300
60146
5516
11667 36
46067 2226 30
60116
5516
12667 26
5720
46067 2226 16
12600
207
: 2206
// page 16
12727 0
0
12727 0
0
207
// adrtab
0
: 2226
0
163350
163350
177774
20000
177152
170370
176400
176400
177145
170370
170400
170400
177777
177777
// devtbl
0
: 2266
2306
2330
2352
2374
0
2450
0
// rk
220
: 2306
177412
177412
177410
177406
177404
503
505
1
// rf
204
: 2330
177470
177466
177464
177462
177460
103
105
1
: 2350
// page 17
// rp
254
: 2352
176722
176724
176720
176716
176714
103
105
1
// rc
210
: 2374
177442
177442
177452
177450
177446
103
105
1
// rp04
176700
: 2416
176732
0
0
254
176734
176706
176704
176702
176700
161
171
40011
// rs04
172040
: 2450
172040
0
0
204
172046
172046
172044
172042
172040
161
171
40011
: 2500
// savval
12737 10 772
10446
12704 730
: 2514
// page 18
10024
11024
10224
11224
12604
207
: 2530
// clrtbit
13746 177776
11627
// retpsw (2540)
0
: 2540
42716 20
// respsw (2546)
12746 2554
2
207
// Fixed bug in CQKC_D0. IODEV raises spl to 4 during operation. But when RESTPS is called to
// restore the spl it does so via an rti. An rti cannot change the spl psw field if used from user mode
// by definition. And IODEV is called is called in user mode as part of the overall strategy of running
// all tests in 4 different base psw modes: Kk0, Kk0T, Uu0 and Uu0T. After IODEV exits the psw ends up
// set to Uu4 instead of Uu0. This causes the subsequent test, TTYCHK, to fail. It spins waiting for the
// TTY tx to interrupt. And it never does because the spl is 4!
// The fix, which is present in CQKC_E0, is for RESTPS to force the psw back to Kk mode via a direct psw write.
// This is valid from user mode because the psw register is not protected against user writes (e.g. with MMU).
// Then the subsequent restore of the previous psw spl via the rti will work since it is always in Kk mode.
// restps
:: 2556
#ifdef CQKC_E0_FIX
12707 300 // jmp 300 ; patch location
#else
16746 177756 // mov retpsw, -(sp) ; original insn
#endif
#ifdef CQKC_E0_FIX
// patch is placed at 300 which shouldn't conflict with anything (usp is 600/576 and down, ksp is 500/476 and down)
= 300
42737 177400 177776 // bic #177400, psw ; from CQKC_E0: cm/pm = kernel mode
13746 2540 // mov retpsw, -(sp) ; original insn from above (but using mode 3 addressing)
12707 2546 // jmp respsw
:: 316
#endif
= 2562
771 // jmp respsw
// page 19
// .type
10046
: 2564
17600 2
62766 2 2
32737 400 764
1403
112046
1003
5726
12600
2
4767 26
122726 12
1366
16746 176142 // listing obscured, but $fills is at neg offset
105366 1
2770
4767 2
772
105737 177564
100375
116637 2 177566
207
: 2670
// cnvdat
4767 2226 // listing obscured, but $savr is at 5124 which is +2226 from here
: 2674
12704 3102
10201
5003
12700 6
167 100
// page 20
// cnvadr
4767 2202
: 2720
12704 3102
162701 2
10105
5003
105737 770
1423
42701 17777
6301
6101
6101
6101
6301
62701 172340
11101
12700 6
6301
6103
77003
42705 160000
60501
5503
12700 10
// cnvdig
12705 3
: 3020
5002
6203
6001
106002
5305
1373
12705 5
241
106002
5305
1374
62702 260
110244
5300
1355
4767 2054
207
: 3070
b 0
b 0
:: 3074
// blkb 6 (i.e. 6 bytes of zeros)
0
0
0
:: 3102
b 40
b 0
:: 3104
// page 21
// typdat
4767 177562
: 3106
4 3074
207
// typadr
4767 177574
: 3120
4 3072
207
// tkisr
240
: 3130
13746 177562
42716 177600
22716 3
1005
4 752
5726
0
2
122716 15
1004
4 752
5726
2
112667 175534
4 740
2
// page 22
// .hlt
5737 177570 // swreg
: 3214
100001
0
32737 20000 177570 // swreg
1117
4767 1666
13702 1000
4767 177424
16767 177624 320
16767 177620 314
4 3564
16602 16
124242
4 003601
4767 177600
16702 175462
1411
6302
16267 4156 175420
4 742
4767 424
454
4 3607
16602 20
4767 177534
122737 10 764
1014
4 3614
13702 177766
4767 177510
4 3621
13702 177744
4767 177474
16602 16
124242
105737 770
1012
5737 1004
1415
: 3430
4 3626
163702 1004
4767 177436
406
4 3633
16601 16
4767 177432
4767 1454
32737 2000 177570 // swreg
1402
: 3476
// page 23
4 3640 // listing obscured, but is bell
: 3502
5737 177570 // listing obscured, but is swreg
100001
0
5737 5322
1407
5037 5322
5000
5300
1376
137 5422
105737 761
1402
137 4402
2
: 3552
// digtab
30460
31462
32464
33466