From c0542fcd7549f406f8facfb8cb038949e5e8cf6e Mon Sep 17 00:00:00 2001 From: "Dementiev, Roman" Date: Wed, 20 Nov 2024 10:44:32 +0100 Subject: [PATCH] add ARL (Arrow Lake) support Change-Id: I0ecc9cfea908eec24442e7e2af78b5a738485f45 --- src/cpucounters.cpp | 18 +++++++++++++++++- src/cpucounters.h | 9 +++++++++ 2 files changed, 26 insertions(+), 1 deletion(-) diff --git a/src/cpucounters.cpp b/src/cpucounters.cpp index 60e52ade..3b186164 100644 --- a/src/cpucounters.cpp +++ b/src/cpucounters.cpp @@ -724,6 +724,7 @@ void PCM::initCStateSupportTables() case RPL: case MTL: case LNL: + case ARL: case SNOWRIDGE: case ELKHART_LAKE: case JASPER_LAKE: @@ -803,6 +804,7 @@ void PCM::initCStateSupportTables() case RPL: case MTL: case LNL: + case ARL: case SNOWRIDGE: case ELKHART_LAKE: case JASPER_LAKE: @@ -1662,6 +1664,7 @@ bool PCM::detectNominalFrequency() || cpu_family_model == RPL || cpu_family_model == MTL || cpu_family_model == LNL + || cpu_family_model == ARL || cpu_family_model == SKX || cpu_family_model == ICX || cpu_family_model == SPR @@ -1926,6 +1929,7 @@ void PCM::initUncoreObjects() case RPL: // TGLClientBW works fine for RPL case MTL: // TGLClientBW works fine for MTL case LNL: // TGLClientBW works fine for LNL + case ARL: // TGLClientBW works fine for ARL clientBW = std::make_shared(); break; /* Disabled since ADLClientBW requires 2x multiplier for BW on top @@ -3334,6 +3338,7 @@ bool PCM::isCPUModelSupported(const int model_) || model_ == RPL || model_ == MTL || model_ == LNL + || model_ == ARL || model_ == SKX || model_ == ICX || model_ == SPR @@ -3367,6 +3372,9 @@ bool PCM::checkModel() case CML_1: cpu_family_model = CML; break; + case ARL_1: + cpu_family_model = ARL; + break; case ICL_1: cpu_family_model = ICL; break; @@ -3510,7 +3518,12 @@ PCM::ErrorCode PCM::program(const PCM::ProgramMode mode_, const void * parameter canUsePerf = false; if (!silent) std::cerr << "Installed Linux kernel perf does not support hardware top-down level-1 counters. Using direct PMU programming instead.\n"; } - if (canUsePerf && (cpu_family_model == ADL || cpu_family_model == RPL || cpu_family_model == MTL || cpu_family_model == LNL)) + if (canUsePerf && (cpu_family_model == ADL + || cpu_family_model == RPL + || cpu_family_model == MTL + || cpu_family_model == LNL + || cpu_family_model == ARL + )) { canUsePerf = false; if (!silent) std::cerr << "Linux kernel perf rejects an architectural event on your platform. Using direct PMU programming instead.\n"; @@ -3598,6 +3611,7 @@ PCM::ErrorCode PCM::program(const PCM::ProgramMode mode_, const void * parameter case RPL: case MTL: case LNL: + case ARL: LLCArchEventInit(hybridAtomEventDesc); hybridAtomEventDesc[2].event_number = SKL_MEM_LOAD_RETIRED_L2_MISS_EVTNR; hybridAtomEventDesc[2].umask_value = SKL_MEM_LOAD_RETIRED_L2_MISS_UMASK; @@ -4957,6 +4971,8 @@ const char * PCM::getUArchCodename(const int32 cpu_family_model_param) const return "Meteor Lake"; case LNL: return "Lunar Lake"; + case ARL: + return "Arrow Lake"; case SKX: if (cpu_family_model_param >= 0) { diff --git a/src/cpucounters.h b/src/cpucounters.h index 2e65b908..6dc8043f 100644 --- a/src/cpucounters.h +++ b/src/cpucounters.h @@ -1639,6 +1639,7 @@ class PCM_API PCM case RPL: case MTL: case LNL: + case ARL: if (topology[coreID].core_type == TopologyEntry::Atom) { return std::make_pair(OFFCORE_RESPONSE_0_EVTNR, event + 1); @@ -1655,6 +1656,7 @@ class PCM_API PCM case RPL: case MTL: case LNL: + case ARL: useGLCOCREvent = true; break; } @@ -1892,6 +1894,8 @@ class PCM_API PCM RPL_3 = PCM_CPU_FAMILY_MODEL(6, 0xbe), MTL = PCM_CPU_FAMILY_MODEL(6, 0xAA), LNL = PCM_CPU_FAMILY_MODEL(6, 0xBD), + ARL = PCM_CPU_FAMILY_MODEL(6, 197), + ARL_1 = PCM_CPU_FAMILY_MODEL(6, 198), BDX = PCM_CPU_FAMILY_MODEL(6, 79), KNL = PCM_CPU_FAMILY_MODEL(6, 87), SKL = PCM_CPU_FAMILY_MODEL(6, 94), @@ -2128,6 +2132,7 @@ class PCM_API PCM case MTL: return 6; case LNL: + case ARL: return 12; case SNOWRIDGE: case ELKHART_LAKE: @@ -2477,6 +2482,7 @@ class PCM_API PCM || cpu_family_model == PCM::RPL || cpu_family_model == PCM::MTL || cpu_family_model == PCM::LNL + || cpu_family_model == PCM::ARL || cpu_family_model == PCM::SPR || cpu_family_model == PCM::EMR || cpu_family_model == PCM::GNR @@ -2789,6 +2795,7 @@ class PCM_API PCM || cpu_family_model == RPL || cpu_family_model == MTL || cpu_family_model == LNL + || cpu_family_model == ARL || useSKLPath() ; } @@ -4298,6 +4305,7 @@ uint64 getL2CacheMisses(const CounterStateType & before, const CounterStateType || cpu_family_model == PCM::RPL || cpu_family_model == PCM::MTL || cpu_family_model == PCM::LNL + || cpu_family_model == PCM::ARL ) { return after.Event[BasicCounterState::SKLL2MissPos] - before.Event[BasicCounterState::SKLL2MissPos]; } @@ -4413,6 +4421,7 @@ uint64 getL3CacheHitsSnoop(const CounterStateType & before, const CounterStateTy || cpu_family_model == PCM::RPL || cpu_family_model == PCM::MTL || cpu_family_model == PCM::LNL + || cpu_family_model == PCM::ARL ) { const int64 misses = getL3CacheMisses(before, after);