From c5b9392ae08cd282149135efb6d0361c63f91150 Mon Sep 17 00:00:00 2001
From: Philipp Wagner <mail@philipp-wagner.com>
Date: Mon, 19 Apr 2021 18:39:35 +0100
Subject: [PATCH] Add guidance for port expressions in module instantiations

Require expressions in port lists in a module instantiation to be
formatted in tabular style.

Fixes #48
---
 VerilogCodingStyle.md | 21 ++++++++++++++++++---
 1 file changed, 18 insertions(+), 3 deletions(-)

diff --git a/VerilogCodingStyle.md b/VerilogCodingStyle.md
index 9cbd14a..ab75d84 100644
--- a/VerilogCodingStyle.md
+++ b/VerilogCodingStyle.md
@@ -459,7 +459,7 @@ assign bus_concatenation = {
 };
 
 inst_type inst_name1 (
-  .clk_i    (clk),
+  .clk_i       (clk),
   .data_valid_i(data_valid),
   .data_value_i(data_value),
   .data_ready_o(data_ready)
@@ -532,10 +532,23 @@ Use spaces, not tabs.
 
 For example:
 
+:+1:
 ```systemverilog
 logic [7:0]  my_interface_data;
 logic [15:0] my_interface_address;
 logic        my_interface_enable;
+
+:+1:
+```systemverilog
+mod u_mod (
+  .clk_i,
+  .rst_ni,
+  .sig_i (my_signal_in),
+  .sig2_i(my_signal_out),
+
+  .in_another_block_i(my_signal_in),
+  .sig3_i            (something)
+);
 ```
 
 #### Expressions
@@ -933,8 +946,8 @@ module my_module #(
     .clk_i,
     .rst_ni,
     .req_valid_i,
-    .req_data_i    (req_data_masked),
-    .req_ready_o,
+    .req_data_i (req_data_masked),
+    .req_ready_o(req_ready),
     ...
   );
 
@@ -1507,6 +1520,8 @@ Do not use positional arguments to connect signals to ports.
 
 Instantiate ports in the same order as they are defined in the module.
 
+Align expressions in [tabular style](#tabular-alignment).
+
 ***Use named parameters for all instantiations.***
 
 When parameterizing an instance, specify the parameter using the named parameter