diff --git a/VerilogCodingStyle.md b/VerilogCodingStyle.md index 9cbd14a..4f970e1 100644 --- a/VerilogCodingStyle.md +++ b/VerilogCodingStyle.md @@ -459,7 +459,7 @@ assign bus_concatenation = { }; inst_type inst_name1 ( - .clk_i (clk), + .clk_i (clk), .data_valid_i(data_valid), .data_value_i(data_value), .data_ready_o(data_ready) @@ -532,10 +532,23 @@ Use spaces, not tabs. For example: +:+1: ```systemverilog logic [7:0] my_interface_data; logic [15:0] my_interface_address; logic my_interface_enable; + +:+1: +```systemverilog +mod u_mod ( + .clk_i, + .rst_ni, + .sig_i (my_signal_in), + .sig2_i(my_signal_out), + + .in_another_block_i(my_signal_in), + .sig3_i (something) +); ``` #### Expressions @@ -933,8 +946,8 @@ module my_module #( .clk_i, .rst_ni, .req_valid_i, - .req_data_i (req_data_masked), - .req_ready_o, + .req_data_i (req_data_masked), + .req_ready_o(req_ready), ... ); @@ -1507,6 +1520,8 @@ Do not use positional arguments to connect signals to ports. Instantiate ports in the same order as they are defined in the module. +Align port expressions in [tabular style](#tabular-alignment). + ***Use named parameters for all instantiations.*** When parameterizing an instance, specify the parameter using the named parameter @@ -1521,10 +1536,15 @@ my_module #( .Height(5), .Width(10) ) my_module ( - ...etc... - -my_reg #(16) my_reg0 (.clk_i, .rst_ni, .d_i(data_in), .q_o(data_out)); + // ... +); +my_reg #(16) my_reg0 ( + .clk_i, + .rst_ni, + .d_i (data_in), + .q_o (data_out) +); ``` Do not specify parameters positionally, unless there is only one parameter and the intent of that parameter is obvious, such as the width for a register