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vivado_14274.backup.log
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vivado_14274.backup.log
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#-----------------------------------------------------------
# Vivado v2019.1 (64-bit)
# SW Build 2552052 on Fri May 24 14:47:09 MDT 2019
# IP Build 2548770 on Fri May 24 18:01:18 MDT 2019
# Start of session at: Sat Oct 19 00:40:36 2019
# Process ID: 14274
# Current directory: /home/hello/32-Bit-ALU
# Command line: vivado
# Log file: /home/hello/32-Bit-ALU/vivado.log
# Journal file: /home/hello/32-Bit-ALU/vivado.jou
#-----------------------------------------------------------
start_gui
open_project /home/hello/32-Bit-ALU/32-Bit-ALU.xpr
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/home/neeraj/eda/Vivado/2019.1/data/ip'.
update_compile_order -fileset sources_1
synth_design -rtl -name rtl_1
Command: synth_design -rtl -name rtl_1
Starting synth_design
Using part: xc7k70tfbv676-1
Top: main
INFO: [Device 21-403] Loading part xc7k70tfbv676-1
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 6767.082 ; gain = 153.594 ; free physical = 4211 ; free virtual = 15080
---------------------------------------------------------------------------------
INFO: [Synth 8-6157] synthesizing module 'main' [/home/hello/32-Bit-ALU/32-Bit-ALU.srcs/sources_1/new/main.v:23]
INFO: [Synth 8-6157] synthesizing module 'fastAdder32' [/home/hello/32-Bit-ALU/32-Bit-ALU.srcs/sources_1/new/fastAdder32.v:23]
INFO: [Synth 8-6157] synthesizing module 'fastAdder4' [/home/hello/32-Bit-ALU/32-Bit-ALU.srcs/sources_1/new/fastAdder4.v:23]
INFO: [Synth 8-6155] done synthesizing module 'fastAdder4' (1#1) [/home/hello/32-Bit-ALU/32-Bit-ALU.srcs/sources_1/new/fastAdder4.v:23]
INFO: [Synth 8-6157] synthesizing module 'GenProp' [/home/hello/32-Bit-ALU/32-Bit-ALU.srcs/sources_1/new/GenProp.v:23]
INFO: [Synth 8-6155] done synthesizing module 'GenProp' (2#1) [/home/hello/32-Bit-ALU/32-Bit-ALU.srcs/sources_1/new/GenProp.v:23]
INFO: [Synth 8-6155] done synthesizing module 'fastAdder32' (3#1) [/home/hello/32-Bit-ALU/32-Bit-ALU.srcs/sources_1/new/fastAdder32.v:23]
INFO: [Synth 8-6157] synthesizing module 'multiplier32' [/home/hello/32-Bit-ALU/32-Bit-ALU.srcs/sources_1/new/multiplier32.v:23]
Parameter width bound to: 32 - type: integer
ERROR: [Synth 8-27] wand/wor/triand/trior declaration not supported [/home/hello/32-Bit-ALU/32-Bit-ALU.srcs/sources_1/new/multiplier32.v:31]
ERROR: [Synth 8-27] wand/wor/triand/trior declaration not supported [/home/hello/32-Bit-ALU/32-Bit-ALU.srcs/sources_1/new/multiplier32.v:31]
ERROR: [Synth 8-6156] failed synthesizing module 'multiplier32' [/home/hello/32-Bit-ALU/32-Bit-ALU.srcs/sources_1/new/multiplier32.v:23]
ERROR: [Synth 8-6156] failed synthesizing module 'main' [/home/hello/32-Bit-ALU/32-Bit-ALU.srcs/sources_1/new/main.v:23]
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 6798.020 ; gain = 184.531 ; free physical = 4243 ; free virtual = 15112
---------------------------------------------------------------------------------
RTL Elaboration failed
9 Infos, 0 Warnings, 0 Critical Warnings and 5 Errors encountered.
synth_design failed
ERROR: [Vivado_Tcl 4-5] Elaboration failed - please see the console for details
reset_run synth_1
launch_runs synth_1 -jobs 4
[Sat Oct 19 00:42:41 2019] Launched synth_1...
Run output will be captured here: /home/hello/32-Bit-ALU/32-Bit-ALU.runs/synth_1/runme.log
exit
INFO: [Common 17-206] Exiting Vivado at Sat Oct 19 00:46:27 2019...