From 2ff6b799a804add940b30e70a19f751a4aeff36b Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Fri, 4 Jun 2021 13:51:09 +0800 Subject: [PATCH 1/7] riscv: ae350: dts: Add SPDX license header The SPDX license header is currently missing. Add one. Signed-off-by: Bin Meng Reviewed-by: Leo Yu-Chi Liang Reviewed-by: Rick Chen --- arch/riscv/dts/ae350_32.dts | 2 ++ arch/riscv/dts/ae350_64.dts | 2 ++ 2 files changed, 4 insertions(+) diff --git a/arch/riscv/dts/ae350_32.dts b/arch/riscv/dts/ae350_32.dts index a0ab5e9be22..ef110c54aec 100644 --- a/arch/riscv/dts/ae350_32.dts +++ b/arch/riscv/dts/ae350_32.dts @@ -1,3 +1,5 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + /dts-v1/; #include "binman.dtsi" diff --git a/arch/riscv/dts/ae350_64.dts b/arch/riscv/dts/ae350_64.dts index f654f4809a2..6abf42e904d 100644 --- a/arch/riscv/dts/ae350_64.dts +++ b/arch/riscv/dts/ae350_64.dts @@ -1,3 +1,5 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + /dts-v1/; #include "binman.dtsi" From 5c267e00332473aeffd34d92d2f75558890de5d3 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Fri, 4 Jun 2021 13:51:10 +0800 Subject: [PATCH 2/7] riscv: ae350: dts: Remove the unnecessary space in bootargs There are two spaces before "debug' in bootargs. Drop one. Signed-off-by: Bin Meng Reviewed-by: Rick Chen Reviewed-by: Leo Yu-Chi Liang --- arch/riscv/dts/ae350_32.dts | 2 +- arch/riscv/dts/ae350_64.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/riscv/dts/ae350_32.dts b/arch/riscv/dts/ae350_32.dts index ef110c54aec..b90351e87bc 100644 --- a/arch/riscv/dts/ae350_32.dts +++ b/arch/riscv/dts/ae350_32.dts @@ -16,7 +16,7 @@ }; chosen { - bootargs = "console=ttyS0,38400n8 debug loglevel=7"; + bootargs = "console=ttyS0,38400n8 debug loglevel=7"; stdout-path = "uart0:38400n8"; }; diff --git a/arch/riscv/dts/ae350_64.dts b/arch/riscv/dts/ae350_64.dts index 6abf42e904d..27ac21c716f 100644 --- a/arch/riscv/dts/ae350_64.dts +++ b/arch/riscv/dts/ae350_64.dts @@ -16,7 +16,7 @@ }; chosen { - bootargs = "console=ttyS0,38400n8 debug loglevel=7"; + bootargs = "console=ttyS0,38400n8 debug loglevel=7"; stdout-path = "uart0:38400n8"; }; From f050dd2b26abb4b107c3cdf7a5f5c420a9e1d4b6 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Fri, 4 Jun 2021 13:51:11 +0800 Subject: [PATCH 3/7] riscv: ae350: dts: Remove the unnecessary #address-cells in plic nodes PLIC nodes don't have child nodes, so #address-cells is not needed. Signed-off-by: Bin Meng Reviewed-by: Rick Chen Reviewed-by: Leo Yu-Chi Liang --- arch/riscv/dts/ae350_32.dts | 2 -- arch/riscv/dts/ae350_64.dts | 2 -- 2 files changed, 4 deletions(-) diff --git a/arch/riscv/dts/ae350_32.dts b/arch/riscv/dts/ae350_32.dts index b90351e87bc..0917b831083 100644 --- a/arch/riscv/dts/ae350_32.dts +++ b/arch/riscv/dts/ae350_32.dts @@ -135,7 +135,6 @@ plic0: interrupt-controller@e4000000 { compatible = "riscv,plic0"; - #address-cells = <1>; #interrupt-cells = <1>; interrupt-controller; reg = <0xe4000000 0x2000000>; @@ -148,7 +147,6 @@ plic1: interrupt-controller@e6400000 { compatible = "riscv,plic1"; - #address-cells = <1>; #interrupt-cells = <1>; interrupt-controller; reg = <0xe6400000 0x400000>; diff --git a/arch/riscv/dts/ae350_64.dts b/arch/riscv/dts/ae350_64.dts index 27ac21c716f..564e94a1db8 100644 --- a/arch/riscv/dts/ae350_64.dts +++ b/arch/riscv/dts/ae350_64.dts @@ -135,7 +135,6 @@ plic0: interrupt-controller@e4000000 { compatible = "riscv,plic0"; - #address-cells = <2>; #interrupt-cells = <2>; interrupt-controller; reg = <0x0 0xe4000000 0x0 0x2000000>; @@ -148,7 +147,6 @@ plic1: interrupt-controller@e6400000 { compatible = "riscv,plic1"; - #address-cells = <2>; #interrupt-cells = <2>; interrupt-controller; reg = <0x0 0xe6400000 0x0 0x400000>; From 048aff6d2621df2654dce6f833a2cf843358486a Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Fri, 4 Jun 2021 13:51:12 +0800 Subject: [PATCH 4/7] riscv: ae350: dts: Fix #interrupt-cells for plic0 in 32-bit All the device nodes that refer to plic0 as their interrupt parent have 2 cells encoded in their interrupts property, but plic0 only provides 1 cell in #interrupt-cells which is incorrect. Signed-off-by: Bin Meng Reviewed-by: Rick Chen Reviewed-by: Leo Yu-Chi Liang --- arch/riscv/dts/ae350_32.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/dts/ae350_32.dts b/arch/riscv/dts/ae350_32.dts index 0917b831083..70576846f24 100644 --- a/arch/riscv/dts/ae350_32.dts +++ b/arch/riscv/dts/ae350_32.dts @@ -135,7 +135,7 @@ plic0: interrupt-controller@e4000000 { compatible = "riscv,plic0"; - #interrupt-cells = <1>; + #interrupt-cells = <2>; interrupt-controller; reg = <0xe4000000 0x2000000>; riscv,ndev=<71>; From 77eae0ebe6858805416cdc091975156a19185427 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Fri, 4 Jun 2021 13:51:13 +0800 Subject: [PATCH 5/7] riscv: ae350: dts: Add missing "u-boot, dm-spl" for SPL config At present the AE350 SPL defconfig is using OF_PRIOR_STAGE. The intention was to use gdb to load device tree before running U-Boot SPL/proper from RAM. When we switch to OF_SEPARATE we will have to use our own DT but without "u-boot,dm-spl" in several essential nodes, SPL does not boot. Let's add all the required "u-boot,dm-spl" for SPL config. Signed-off-by: Bin Meng Reviewed-by: Rick Chen --- arch/riscv/dts/ae350-u-boot.dtsi | 52 ++++++++++++++++++++++++++++++++ arch/riscv/dts/ae350_32.dts | 1 + arch/riscv/dts/ae350_64.dts | 1 + 3 files changed, 54 insertions(+) create mode 100644 arch/riscv/dts/ae350-u-boot.dtsi diff --git a/arch/riscv/dts/ae350-u-boot.dtsi b/arch/riscv/dts/ae350-u-boot.dtsi new file mode 100644 index 00000000000..0d4201cfae9 --- /dev/null +++ b/arch/riscv/dts/ae350-u-boot.dtsi @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/ { + cpus { + u-boot,dm-spl; + CPU0: cpu@0 { + u-boot,dm-spl; + CPU0_intc: interrupt-controller { + u-boot,dm-spl; + }; + }; + CPU1: cpu@1 { + u-boot,dm-spl; + CPU1_intc: interrupt-controller { + u-boot,dm-spl; + }; + }; + CPU2: cpu@2 { + u-boot,dm-spl; + CPU2_intc: interrupt-controller { + u-boot,dm-spl; + }; + }; + CPU3: cpu@3 { + u-boot,dm-spl; + CPU3_intc: interrupt-controller { + u-boot,dm-spl; + }; + }; + }; + + memory@0 { + u-boot,dm-spl; + }; + + soc { + u-boot,dm-spl; + + plic1: interrupt-controller@e6400000 { + u-boot,dm-spl; + }; + + plmt0@e6000000 { + u-boot,dm-spl; + }; + }; + + serial0: serial@f0300000 { + u-boot,dm-spl; + }; + +}; diff --git a/arch/riscv/dts/ae350_32.dts b/arch/riscv/dts/ae350_32.dts index 70576846f24..083f676333d 100644 --- a/arch/riscv/dts/ae350_32.dts +++ b/arch/riscv/dts/ae350_32.dts @@ -3,6 +3,7 @@ /dts-v1/; #include "binman.dtsi" +#include "ae350-u-boot.dtsi" / { #address-cells = <1>; diff --git a/arch/riscv/dts/ae350_64.dts b/arch/riscv/dts/ae350_64.dts index 564e94a1db8..74cff9122d4 100644 --- a/arch/riscv/dts/ae350_64.dts +++ b/arch/riscv/dts/ae350_64.dts @@ -3,6 +3,7 @@ /dts-v1/; #include "binman.dtsi" +#include "ae350-u-boot.dtsi" / { #address-cells = <2>; From 279de759bd2ceb1dad6ff30c7d27c8ff9c5706a3 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Sat, 5 Jun 2021 07:00:30 +0800 Subject: [PATCH 6/7] riscv: ae350: doc: Remove CONFIG_SKIP_LOWLEVEL_INIT The doc says CONFIG_SKIP_LOWLEVEL_INIT is in ax25-ae350.h, while actually it is not. Remove it. Signed-off-by: Bin Meng Reviewed-by: Rick Chen --- doc/board/AndesTech/ax25-ae350.rst | 19 ++++--------------- 1 file changed, 4 insertions(+), 15 deletions(-) diff --git a/doc/board/AndesTech/ax25-ae350.rst b/doc/board/AndesTech/ax25-ae350.rst index 923649240ec..b46f427f4b7 100644 --- a/doc/board/AndesTech/ax25-ae350.rst +++ b/doc/board/AndesTech/ax25-ae350.rst @@ -58,15 +58,6 @@ Platform Level Interrupt Controller (PLIC) - Configurable number of targets: 1-16 - Preempted interrupt priority stack -Configurations --------------- - -CONFIG_SKIP_LOWLEVEL_INIT: - -If you want to boot this system from SPI ROM and bypass e-bios (the -other boot loader on ROM). You should undefine CONFIG_SKIP_LOWLEVEL_INIT -in "include/configs/ax25-ae350.h". - Build and boot steps -------------------- @@ -89,12 +80,10 @@ Verification: Steps ----- -1. Define CONFIG_SKIP_LOWLEVEL_INIT to build u-boot which is loaded via gdb from ram. -2. Undefine CONFIG_SKIP_LOWLEVEL_INIT to build u-boot which is booted from spi rom. -3. Ping a server by mac driver -4. Scan sd card and copy u-boot image which is booted from flash to ram by sd driver. -5. Burn this u-boot image to spi rom by spi driver -6. Re-boot u-boot from spi flash with power off and power on. +1. Ping a server by mac driver +2. Scan sd card and copy u-boot image which is booted from flash to ram by sd driver +3. Burn this u-boot image to spi rom by spi driver +4. Re-boot u-boot from spi flash with power off and power on Messages of U-Boot boot on AE350 board -------------------------------------- From 62ce0a02f9e5bda51a05c5f735e5a75f6c4bbb54 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Tue, 15 Jun 2021 13:45:57 +0800 Subject: [PATCH 7/7] riscv: andes_plic: Fix riscv_get_ipi() mask Current logic in riscv_get_ipi() for Andes PLICSW does not look correct. The mask to test IPI pending bits for a hart should be left shifted by (8 * gd->arch.boot_hart), just the same as what is done in riscv_send_ipi(). Fixes: 8b3e97badf97 ("riscv: add functions for reading the IPI status") Signed-off-by: Bin Meng Reviewed-by: Rick Chen Tested-by: Rick Chen --- arch/riscv/lib/andes_plic.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/riscv/lib/andes_plic.c b/arch/riscv/lib/andes_plic.c index 221a5fe324e..5e113ee8c94 100644 --- a/arch/riscv/lib/andes_plic.c +++ b/arch/riscv/lib/andes_plic.c @@ -105,9 +105,11 @@ int riscv_clear_ipi(int hart) int riscv_get_ipi(int hart, int *pending) { + unsigned int ipi = (SEND_IPI_TO_HART(hart) << (8 * gd->arch.boot_hart)); + *pending = readl((void __iomem *)PENDING_REG(gd->arch.plic, gd->arch.boot_hart)); - *pending = !!(*pending & SEND_IPI_TO_HART(hart)); + *pending = !!(*pending & ipi); return 0; }