Merge tag 'dm-pull-28mar21' of git://git.denx.de/u-boot-dm into next

binman support for expanding entries, connections
misc fixes and improvements to sandbox, etc.
x86 CBFS improvements
x86 coreboot improvements

arch/riscv/cpu/ax25/Kconfig

@@ -6,7 +6,7 @@ config RISCV_NDS
 	imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE)
 	imply ANDES_PLIC if (RISCV_MMODE || SPL_RISCV_MMODE)
 	imply ANDES_PLMT_TIMER if (RISCV_MMODE || SPL_RISCV_MMODE)
-	imply SPL_CPU_SUPPORT
+	imply SPL_CPU
 	imply SPL_OPENSBI
 	imply SPL_LOAD_FIT
 	help

arch/riscv/cpu/fu540/Kconfig

@@ -13,7 +13,7 @@ config SIFIVE_FU540
 	imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE)
 	imply SIFIVE_CLINT if (RISCV_MMODE || SPL_RISCV_MMODE)
 	imply CMD_CPU
-	imply SPL_CPU_SUPPORT
+	imply SPL_CPU
 	imply SPL_OPENSBI
 	imply SPL_LOAD_FIT
 	imply SMP

arch/riscv/cpu/generic/Kconfig

@@ -10,6 +10,6 @@ config GENERIC_RISCV
 	imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE)
 	imply SIFIVE_CLINT if (RISCV_MMODE || SPL_RISCV_MMODE)
 	imply CMD_CPU
-	imply SPL_CPU_SUPPORT
+	imply SPL_CPU
 	imply SPL_OPENSBI
 	imply SPL_LOAD_FIT

arch/sandbox/cpu/cpu.c

@@ -6,7 +6,6 @@
 #include <common.h>
 #include <bootstage.h>
 #include <cpu_func.h>
-#include <dm.h>
 #include <errno.h>
 #include <log.h>
 #include <asm/global_data.h>
@@ -17,7 +16,6 @@
 #include <asm/malloc.h>
 #include <asm/setjmp.h>
 #include <asm/state.h>
-#include <dm/root.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -34,10 +32,8 @@ void sandbox_exit(void)
 {
 	/* Do this here while it still has an effect */
 	os_fd_restore();
-	if (state_uninit())
-		os_exit(2);
 
-	if (dm_uninit())
+	if (state_uninit())
 		os_exit(2);
 
 	/* This is considered normal termination for now */

arch/sandbox/cpu/os.c

@@ -711,7 +711,7 @@ static int add_args(char ***argvp, char *add_args[], int count)
  * @fname: Filename to exec
  * @return does not return on success, any return value is an error
  */
-static int os_jump_to_file(const char *fname)
+static int os_jump_to_file(const char *fname, bool delete_it)
 {
 	struct sandbox_state *state = state_get_current();
 	char mem_fname[30];
@@ -734,11 +734,13 @@ static int os_jump_to_file(const char *fname)
 
 	os_fd_restore();
 
-	extra_args[0] = "-j";
-	extra_args[1] = (char *)fname;
-	extra_args[2] = "-m";
-	extra_args[3] = mem_fname;
-	argc = 4;
+	argc = 0;
+	if (delete_it) {
+		extra_args[argc++] = "-j";
+		extra_args[argc++] = (char *)fname;
+	}
+	extra_args[argc++] = "-m";
+	extra_args[argc++] = mem_fname;
 	if (state->ram_buf_rm)
 		extra_args[argc++] = "--rm_memory";
 	err = add_args(&argv, extra_args, argc);
@@ -762,7 +764,10 @@ static int os_jump_to_file(const char *fname)
 		return err;
 	}
 
-	return unlink(fname);
+	if (delete_it)
+		return unlink(fname);
+
+	return -EFAULT;
 }
 
 int os_jump_to_image(const void *dest, int size)
@@ -774,7 +779,7 @@ int os_jump_to_image(const void *dest, int size)
 	if (err)
 		return err;
 
-	return os_jump_to_file(fname);
+	return os_jump_to_file(fname, true);
 }
 
 int os_find_u_boot(char *fname, int maxlen, bool use_img)
@@ -847,7 +852,8 @@ int os_spl_to_uboot(const char *fname)
 
 	/* U-Boot will delete ram buffer after read: "--rm_memory"*/
 	state->ram_buf_rm = true;
-	return os_jump_to_file(fname);
+
+	return os_jump_to_file(fname, false);
 }
 
 long os_get_time_offset(void)

arch/sandbox/cpu/u-boot.lds

@@ -44,6 +44,13 @@ SECTIONS
 	{
 		*(.__efi_runtime_rel_stop)
 	}
+
+	.dynsym :
+	{
+		__dyn_sym_start = .;
+		*(.dynsym)
+		__dyn_sym_end = .;
+	}
 }
 
 INSERT BEFORE .data;

arch/sandbox/dts/sandbox.dtsi

@@ -200,6 +200,10 @@
 		compatible = "sandbox,reset";
 	};
 
+	rng {
+		compatible = "sandbox,sandbox-rng";
+	};
+
 	sound {
 		compatible = "sandbox,sound";
 		cpu {

arch/x86/Kconfig

@@ -1047,4 +1047,25 @@ config INTEL_GMA_SWSMISCI
 
 endif # INTEL_SOC
 
+config COREBOOT_SYSINFO
+	bool "Support reading coreboot sysinfo"
+	default y if SYS_COREBOOT
+	help
+	  Select this option to read the coreboot sysinfo table on start-up,
+	  if present. This is written by coreboot before it exits and provides
+	  various pieces of information about the running system, including
+	  display, memory and build information. It is stored in
+	  struct sysinfo_t after parsing by get_coreboot_info().
+
+config SPL_COREBOOT_SYSINFO
+	bool "Support reading coreboot sysinfo"
+	depends on SPL
+	default y if COREBOOT_SYSINFO
+	help
+	  Select this option to read the coreboot sysinfo table in SPL,
+	  if present. This is written by coreboot before it exits and provides
+	  various pieces of information about the running system, including
+	  display, memory and build information. It is stored in
+	  struct sysinfo_t after parsing by get_coreboot_info().
+
 endmenu

arch/x86/cpu/apollolake/cpu.c

@@ -19,6 +19,7 @@
 #include <asm/arch/iomap.h>
 #include <dm/acpi.h>
 
+#ifdef CONFIG_ACPIGEN
 #define CSTATE_RES(address_space, width, offset, address)		\
 	{								\
 	.space_id = address_space,					\
@@ -57,11 +58,6 @@ static struct acpi_cstate cstate_map[] = {
 	},
 };
 
-static int apl_get_info(const struct udevice *dev, struct cpu_info *info)
-{
-	return cpu_intel_get_info(info, INTEL_BCLK_MHZ);
-}
-
 static int acpi_cpu_fill_ssdt(const struct udevice *dev, struct acpi_ctx *ctx)
 {
 	uint core_id = dev_seq(dev);
@@ -89,6 +85,12 @@ static int acpi_cpu_fill_ssdt(const struct udevice *dev, struct acpi_ctx *ctx)
 
 	return 0;
 }
+#endif /* CONFIG_ACPIGEN */
+
+static int apl_get_info(const struct udevice *dev, struct cpu_info *info)
+{
+	return cpu_intel_get_info(info, INTEL_BCLK_MHZ);
+}
 
 static void update_fixed_mtrrs(void)
 {
@@ -170,9 +172,11 @@ static int cpu_apl_probe(struct udevice *dev)
 	return 0;
 }
 
+#ifdef CONFIG_ACPIGEN
 struct acpi_ops apl_cpu_acpi_ops = {
 	.fill_ssdt	= acpi_cpu_fill_ssdt,
 };
+#endif
 
 static const struct cpu_ops cpu_x86_apl_ops = {
 	.get_desc	= cpu_x86_get_desc,

arch/x86/cpu/apollolake/cpu_common.c

@@ -7,11 +7,17 @@
 #include <dm.h>
 #include <log.h>
 #include <asm/cpu_common.h>
+#include <asm/io.h>
 #include <asm/msr.h>
+#include <asm/pci.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/iomap.h>
+#include <asm/arch/uart.h>
 #include <power/acpi_pmc.h>
 
+/* Define this here to avoid referencing any drivers for the debug UART 1 */
+#define PCH_DEV_P2SB	PCI_BDF(0, 0x0d, 0)
+
 void cpu_flush_l1d_to_l2(void)
 {
 	struct msr_t msr;
@@ -40,3 +46,57 @@ void enable_pm_timer_emulation(const struct udevice *pmc)
 	debug("PM timer %x %x\n", msr.hi, msr.lo);
 	msr_write(MSR_EMULATE_PM_TIMER, msr);
 }
+
+static void pch_uart_init(void)
+{
+	/*
+	 * Set up the pinmux so that the UART rx/tx signals are connected
+	 * outside the SoC.
+	 *
+	 * There are about 500 lines of code required to program the GPIO
+	 * configuration for the UARTs. But it boils down to four writes, and
+	 * for the debug UART we want the minimum possible amount of code before
+	 * the UART is running. So just add the magic writes here. See
+	 * apl_hostbridge_early_init_pinctrl() for the full horror.
+	 */
+	if (PCI_FUNC(PCH_DEV_UART) == 1) {
+		writel(0x40000402, 0xd0c50650);
+		writel(0x3c47, 0xd0c50654);
+		writel(0x40000400, 0xd0c50658);
+		writel(0x3c48, 0xd0c5065c);
+	} else { /* UART2 */
+		writel(0x40000402, 0xd0c50670);
+		writel(0x3c4b, 0xd0c50674);
+		writel(0x40000400, 0xd0c50678);
+		writel(0x3c4c, 0xd0c5067c);
+	}
+
+#ifdef CONFIG_DEBUG_UART
+	apl_uart_init(PCH_DEV_UART, CONFIG_DEBUG_UART_BASE);
+#endif
+}
+
+static void p2sb_enable_bar(ulong bar)
+{
+	/* Enable PCR Base address in PCH */
+	pci_x86_write_config(PCH_DEV_P2SB, PCI_BASE_ADDRESS_0, bar,
+			     PCI_SIZE_32);
+	pci_x86_write_config(PCH_DEV_P2SB, PCI_BASE_ADDRESS_1, 0, PCI_SIZE_32);
+
+	/* Enable P2SB MSE */
+	pci_x86_write_config(PCH_DEV_P2SB, PCI_COMMAND,
+			     PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY,
+			     PCI_SIZE_8);
+}
+
+/*
+ * board_debug_uart_init() - Init the debug UART ready for use
+ *
+ * This is the minimum init needed to get the UART running. It avoids any
+ * drivers or complex code, so that the UART is running as soon as possible.
+ */
+void board_debug_uart_init(void)
+{
+	p2sb_enable_bar(IOMAP_P2SB_BAR);
+	pch_uart_init();
+}

arch/x86/cpu/apollolake/cpu_spl.c

@@ -31,68 +31,10 @@
 #include <asm/arch/lpc.h>
 #include <asm/arch/pch.h>
 #include <asm/arch/systemagent.h>
-#include <asm/arch/uart.h>
 #include <asm/fsp2/fsp_api.h>
 #include <linux/sizes.h>
 #include <power/acpi_pmc.h>
 
-/* Define this here to avoid referencing any drivers for the debug UART 1 */
-#define PCH_DEV_P2SB	PCI_BDF(0, 0x0d, 0)
-
-static void pch_uart_init(void)
-{
-	/*
-	 * Set up the pinmux so that the UART rx/tx signals are connected
-	 * outside the SoC.
-	 *
-	 * There are about 500 lines of code required to program the GPIO
-	 * configuration for the UARTs. But it boils down to four writes, and
-	 * for the debug UART we want the minimum possible amount of code before
-	 * the UART is running. So just add the magic writes here. See
-	 * apl_hostbridge_early_init_pinctrl() for the full horror.
-	 */
-	if (PCI_FUNC(PCH_DEV_UART) == 1) {
-		writel(0x40000402, 0xd0c50650);
-		writel(0x3c47, 0xd0c50654);
-		writel(0x40000400, 0xd0c50658);
-		writel(0x3c48, 0xd0c5065c);
-	} else { /* UART2 */
-		writel(0x40000402, 0xd0c50670);
-		writel(0x3c4b, 0xd0c50674);
-		writel(0x40000400, 0xd0c50678);
-		writel(0x3c4c, 0xd0c5067c);
-	}
-
-#ifdef CONFIG_DEBUG_UART
-	apl_uart_init(PCH_DEV_UART, CONFIG_DEBUG_UART_BASE);
-#endif
-}
-
-static void p2sb_enable_bar(ulong bar)
-{
-	/* Enable PCR Base address in PCH */
-	pci_x86_write_config(PCH_DEV_P2SB, PCI_BASE_ADDRESS_0, bar,
-			     PCI_SIZE_32);
-	pci_x86_write_config(PCH_DEV_P2SB, PCI_BASE_ADDRESS_1, 0, PCI_SIZE_32);
-
-	/* Enable P2SB MSE */
-	pci_x86_write_config(PCH_DEV_P2SB, PCI_COMMAND,
-			     PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY,
-			     PCI_SIZE_8);
-}
-
-/*
- * board_debug_uart_init() - Init the debug UART ready for use
- *
- * This is the minimum init needed to get the UART running. It avoids any
- * drivers or complex code, so that the UART is running as soon as possible.
- */
-void board_debug_uart_init(void)
-{
-	p2sb_enable_bar(IOMAP_P2SB_BAR);
-	pch_uart_init();
-}
-
 static int fast_spi_cache_bios_region(void)
 {
 	uint map_size, offset;

arch/x86/cpu/coreboot/Makefile

@@ -20,5 +20,4 @@ else
 obj-y += sdram.o
 endif
 obj-y += coreboot.o
-obj-y += tables.o
 obj-y += timestamp.o

arch/x86/cpu/coreboot/coreboot.c

@@ -14,7 +14,7 @@
 #include <asm/io.h>
 #include <asm/msr.h>
 #include <asm/mtrr.h>
-#include <asm/arch/sysinfo.h>
+#include <asm/cb_sysinfo.h>
 #include <asm/arch/timestamp.h>
 
 DECLARE_GLOBAL_DATA_PTR;