diff --git a/test_pool/timer/operating_system/test_os_t003.c b/test_pool/timer/operating_system/test_os_t003.c index 11540805..ecb8e11d 100644 --- a/test_pool/timer/operating_system/test_os_t003.c +++ b/test_pool/timer/operating_system/test_os_t003.c @@ -45,13 +45,17 @@ payload() while (timer_num) { --timer_num; //array index starts from 0, so subtract 1 from count + val_print(ACS_PRINT_ERR, "\n timer_num 0x%lx", timer_num); if (val_timer_get_info(TIMER_INFO_IS_PLATFORM_TIMER_SECURE, timer_num)) continue; //Skip Secure Timer ns_timer++; + val_print(ACS_PRINT_ERR, "\n ns_timer++ 0x%x ", ns_timer); cnt_ctl_base = val_timer_get_info(TIMER_INFO_SYS_CNTL_BASE, timer_num); cnt_base_n = val_timer_get_info(TIMER_INFO_SYS_CNT_BASE_N, timer_num); + val_print(ACS_PRINT_ERR, "\n cnt_ctl_base 0x%x ", cnt_ctl_base); + val_print(ACS_PRINT_ERR, "\n cnt_base_n 0x%x ", cnt_base_n); if (cnt_ctl_base == 0) { val_print(ACS_PRINT_DEBUG, "\n CNTCTL BASE is zero ", 0); val_set_status(index, RESULT_SKIP(TEST_NUM, 2)); @@ -65,10 +69,13 @@ payload() val_set_status(index, RESULT_SKIP(TEST_NUM, 3)); return; } + val_print(ACS_PRINT_ERR, "\n val_timer_skip_if_cntbase_access_not_allowed done ", 0); // Read write check for a read only register CNTTIDR data = val_mmio_read(cnt_ctl_base + CNTTIDR); + val_print(ACS_PRINT_ERR, "\n val_mmio_read CNTTIDR done ", 0); val_mmio_write(cnt_ctl_base + CNTTIDR, 0xFFFFFFFF); + val_print(ACS_PRINT_ERR, "\n val_mmio_write CNTTIDR done ", 0); if (data != val_mmio_read(cnt_ctl_base + CNTTIDR)) { val_print(ACS_PRINT_DEBUG, "\n Read-write check failed for" " CNTCTLBase.CNTTIDR, expected value %x ", data); @@ -84,11 +91,15 @@ payload() // Read CNTPCT register data1 = val_mmio_read64(cnt_base_n + CNTPCT_LOWER); + val_print(ACS_PRINT_ERR, "\n val_mmio_read64 CNTPCT_LOWER done ", 0); + if (data != val_mmio_read(cnt_ctl_base + CNTTIDR)) { val_print(ACS_PRINT_DEBUG, "\n CNTPCT Read value = 0x%llx ", data1); + val_print(ACS_PRINT_ERR, "\n val_mmio_read CNTTIDR done ", 0); // Writes to Read-Only registers must be ignored val_mmio_write64(cnt_base_n + CNTPCT_LOWER, (data1 - ARBIT_VALUE)); + val_print(ACS_PRINT_ERR, "\n val_mmio_write64 CNTPCT_LOWER done ", 0); if (val_mmio_read64(cnt_base_n + CNTPCT_LOWER) < data1) { val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); val_print(ACS_PRINT_DEBUG, "\n CNTBaseN: CNTPCT reg must be read-only ", 0); @@ -99,32 +110,39 @@ payload() data1 = val_mmio_read64(cnt_base_n + CNTVCT_LOWER); val_print(ACS_PRINT_DEBUG, "\n CNTVCT Read value = 0x%llx ", data1); + val_print(ACS_PRINT_ERR, "\n val_mmio_read64 CNTVCT_LOWER done ", 0); // Writes to Read-Only registers must be ignored val_mmio_write64(cnt_base_n + CNTVCT_LOWER, (data1 - ARBIT_VALUE)); + val_print(ACS_PRINT_ERR, "\n val_mmio_write64 CNTVCT_LOWER done ", 0); if (val_mmio_read64(cnt_base_n + CNTVCT_LOWER) < data1) { val_set_status(index, RESULT_FAIL(TEST_NUM, 3)); val_print(ACS_PRINT_DEBUG, "\n CNTBaseN: CNTVCT reg must be read-only ", 0); return; } + val_print(ACS_PRINT_ERR, "\n val_mmio_read64 CNTVCT_LOWER done ", 0); // Read CNTFRQ register data = val_mmio_read(cnt_base_n + CNTBaseN_CNTFRQ); val_print(ACS_PRINT_DEBUG, "\n CNTFRQ Read value = 0x%x ", data); + val_print(ACS_PRINT_ERR, "\n val_mmio_read CNTBaseN_CNTFRQ done ", 0); // Writes to Read-Only registers must be ignored val_mmio_write(cnt_base_n + CNTBaseN_CNTFRQ, (data - ARBIT_VALUE)); + val_print(ACS_PRINT_ERR, "\n val_mmio_write CNTBaseN_CNTFRQ, done ", 0); if (val_mmio_read(cnt_base_n + CNTBaseN_CNTFRQ) != data) { val_set_status(index, RESULT_FAIL(TEST_NUM, 4)); val_print(ACS_PRINT_DEBUG, "\n CNTBaseN: CNTFRQ reg must be read-only ", 0); return; } + val_print(ACS_PRINT_ERR, "\n val_mmio_read CNTBaseN_CNTFRQ done ", 0); /* Write Read check for RW register*/ data = 0x3; val_mmio_write(cnt_base_n + CNTP_CTL, data); + val_print(ACS_PRINT_ERR, "\n val_mmio_write CNTP_CTL, done ", 0); if (data != (val_mmio_read(cnt_base_n + CNTP_CTL) & 0x3)) { val_print(ACS_PRINT_ERR, "\n Read-write check failed for " "CNTBaseN.CNTP_CTL, expected value %x ", data); @@ -134,13 +152,17 @@ payload() val_mmio_write(cnt_base_n + CNTP_CTL, 0x0); // Disable the timer before return return; } + val_print(ACS_PRINT_ERR, "\n val_mmio_read CNTP_CTL done ", 0); val_mmio_write(cnt_base_n + CNTP_CTL, 0x0); // Disable timer + val_print(ACS_PRINT_ERR, "\n val_mmio_write CNTP_CTL, done ", 0); data = 0xFF00FF00; /* Write a random value to CNTP_CVAL[31:0]*/ val_mmio_write(cnt_base_n + CNTP_CVAL_LOWER, data); + val_print(ACS_PRINT_ERR, "\n val_mmio_write CNTP_CVAL_LOWER, done ", 0); /* Write a random value to CNTP_CVAL[63:32]*/ val_mmio_write(cnt_base_n + CNTP_CVAL_HIGHER, data); + val_print(ACS_PRINT_ERR, "\n val_mmio_write CNTP_CVAL_HIGHER,, done ", 0); if (data != val_mmio_read(cnt_base_n + CNTP_CVAL_LOWER)) { val_print(ACS_PRINT_DEBUG, "\n Read-write check failed for " @@ -149,6 +171,7 @@ payload() val_set_status(index, RESULT_FAIL(TEST_NUM, 6)); return; } + val_print(ACS_PRINT_ERR, "\n val_mmio_read CNTP_CVAL_LOWER done ", 0); if (data != val_mmio_read(cnt_base_n + CNTP_CVAL_HIGHER)) { val_print(ACS_PRINT_DEBUG, "\n Read-write check failed for" @@ -157,6 +180,7 @@ payload() val_set_status(index, RESULT_FAIL(TEST_NUM, 7)); return; } + val_print(ACS_PRINT_ERR, "\n val_mmio_read CNTP_CVAL_HIGHER done ", 0); val_set_status(index, RESULT_PASS(TEST_NUM, 1)); }