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sdram_fail.txt
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sdram_fail.txt
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litex> -_)> <
/____/_/\__/\__/_/|_|
Build your hardware, easily!
(c) Copyright 2012-2022 Enjoy-Digital
(c) Copyright 2007-2015 M-Labs
BIOS built on Feb 2 2022 10:14:07
BIOS CRC passed (484f38b6)
Migen git sha1: ac70301
LiteX git sha1: 78ecf50a
--=============== SoC ==================--
CPU: VexRiscv @ 125MHz
BUS: WISHBONE 32-bit @ 4GiB
CSR: 32-bit data
ROM: 128KiB
SRAM: 8KiB
L2: 8KiB
SDRAM: 1048576KiB 64-bit @ 1000MT/s (CL-7 CWL-6)
--========== Initialization ============--
Initializing SDRAM @0x40000000...
Switching SDRAM to software control.
Write leveling:
tCK equivalent taps: 24
Cmd/Clk scan (0-12)
|011110010011| best: 2
Setting Cmd/Clk delay to 2 taps.
Data scan:
m0: |00000000000011111111111110| delay: 12
m1: |00000000000001111111111111| delay: 13
m2: |11000000000000011111111111| delay: 15
m3: |11100000000000001111111111| delay: 16
m4: |11111111100000000000001111| delay: 00
m5: |11111111000000000000011111| delay: 00
m6: |11111111110000000000000011| delay: 00
m7: |11111111110000000000000111| delay: 00
Write latency calibration:
m0:0 m1:0 m2:0 m3:0 m4:6 m5:6 m6:6 m7:6
Write DQ-DQS training:
m0: |00000001100110001000000000000000| delays: 08+-01
m1: |00000000111111111010000000000000| delays: 12+-04
m2: |00000000000101110111100000000000| delays: 11+-00
m3: |00000000001111111111100000000000| delays: 15+-05
m4: |11111000000000000000000000000000| delays: 02+-02
m5: |11111000000000000000000000000000| delays: 02+-02
m6: |11111000000000000000000000000000| delays: 02+-02
m7: |11111100000000000000000000000000| delays: 03+-03
Read leveling:
m0, b00: |00000000000000000000000000000000| delays: -
m0, b01: |00000000000000000000000000000000| delays: -
m0, b02: |00000000000000000000000000000000| delays: 00+-00
m0, b03: |00111111111111000000000000000000| delays: 08+-05
m0, b04: |00000000000000001111111111000000| delays: 15+-00
m0, b05: |00000000000000000000000000000111| delays: 30+-01
m0, b06: |00000000000000000000000000000000| delays: -
m0, b07: |00000000000000000000000000000000| delays: -
best: m0, b03 delays: 07+-05
m1, b00: |00000000000000000000000000000000| delays: -
m1, b01: |00000000000000000000000000000000| delays: -
m1, b02: |11000000000000000000000000000000| delays: 00+-00
m1, b03: |00001111111111100000000000000000| delays: 10+-05
m1, b04: |00000000000000000111111111101000| delays: 22+-05
m1, b05: |00000000000000000000000000000001| delays: 31+-00
m1, b06: |00000000000000000000000000000000| delays: -
m1, b07: |00000000000000000000000000000000| delays: -
best: m1, b04 delays: 22+-05
m2, b00: |00000000000000000000000000000000| delays: -
m2, b01: |00000000000000000000000000000000| delays: -
m2, b02: |00000000000000000000000000000000| delays: -
m2, b03: |01110111111110000000000000000000| delays: 08+-04
m2, b04: |00000000000000010111111110000000| delays: 21+-04
m2, b05: |00000000000000000000000000000111| delays: 30+-01
m2, b06: |00000000000000000000000000000000| delays: -
m2, b07: |00000000000000000000000000000000| delays: -
best: m2, b03 delays: 07+-05
m3, b00: |00000000000000000000000000000000| delays: -
m3, b01: |00000000000000000000000000000000| delays: -
m3, b02: |10000000000000000000000000000000| delays: -
m3, b03: |01111111111110000000000000000000| delays: 01+-00
m3, b04: |00000000000000111111111111000000| delays: 14+-00
m3, b05: |00000000000000000000000000001011| delays: 29+-00
m3, b06: |00000000000000000000000000000000| delays: -
m3, b07: |00000000000000000000000000000000| delays: -
best: m3, b04 delays: 21+-03
m4, b00: |00000000000000000000000000000000| delays: -
m4, b01: |00000000000000000000000000000000| delays: -
m4, b02: |00000000000000000000000000000000| delays: -
m4, b03: |11111110000000000000000000000000| delays: 03+-03
m4, b04: |00000000110111111111000000000000| delays: 09+-00
m4, b05: |00000000000000000000010111111111| delays: 26+-04
m4, b06: |00000000000000000000000000000000| delays: -
m4, b07: |00000000000000000000000000000000| delays: -
best: m4, b04 delays: 08+-00
m5, b00: |00000000000000000000000000000000| delays: -
m5, b01: |00000000000000000000000000000000| delays: -
m5, b02: |00000000000000000000000000000000| delays: -
m5, b03: |11111110000000000000000000000000| delays: 02+-02
m5, b04: |00000001111111111100000000000000| delays: 13+-05
m5, b05: |00000000000000000000110111111111| delays: 22+-01
m5, b06: |00000000000000000000000000000000| delays: -
m5, b07: |00000000000000000000000000000000| delays: -
best: m5, b05 delays: 26+-05
m6, b00: |00000000000000000000000000000000| delays: -
m6, b01: |00000000000000000000000000000000| delays: -
m6, b02: |00000000000000000000000000000000| delays: -
m6, b03: |11100000000000000000000000000000| delays: 02+-02
m6, b04: |00000011111111110100000000000000| delays: 07+-01
m6, b05: |00000000000000000001111111110100| delays: 20+-01
m6, b06: |00000000000000000000000000000000| delays: -
m6, b07: |00000000000000000000000000000000| delays: -
best: m6, b04 delays: 11+-05
m7, b00: |00000000000000000000000000000000| delays: -
m7, b01: |00000000000000000000000000000000| delays: -
m7, b02: |00000000000000000000000000000000| delays: -
m7, b03: |11110000000000000000000000000000| delays: 01+-01
m7, b04: |00000001111111111001000000000000| delays: 06+-00
m7, b05: |00000000000000000000111111111001| delays: 25+-05
m7, b06: |00000000000000000000000000000000| delays: -
m7, b07: |00000000000000000000000000000000| delays: -
best: m7, b04 delays: 11+-04
Switching SDRAM to hardware control.
Memtest at 0x40000000 (2.0MiB)...
Write: 0x40000000-0x40200000 2.0MiB
Read: 0x40000000-0x40200000 2.0MiB
bus errors: 0/256
addr errors: 2085/8192
data errors: 124175/524288
Memtest KO
Memory initialization failed
--============= Console ================--
litex>