mega65ram.a65

		.outfile "mega65ram.bin"

		.org $0000

		.scope

		.checkpc $8100
		.advance $8100,$00

		jmp simple_cpu_tests

		.checkpc $8200
		.advance $8200,$00

		ldy #$01
		ldx #$fd
l2:		lda $3000,x
		sta $4000,x
		inx
		bne l2
		jmp l2


		.checkpc $8300
		.advance $8300,$00

		ldy #$02
		ldx #$fd
l3:		lda $5000,x
		sta $6000,x
		inx
		bne l3
		jmp l3


		.checkpc $9000
		.advance $9000,$00

		; make destination address non-aligned to test non-aligned loading
		nop
		
simple_cpu_tests:
		; register loads and immediate mode compares
		lda #$01
		lda #$80
		cmp #$7f
		cmp #$80
		cmp #$81
		lda #$00
		ldx #$01
		cpx #$00
		cpx #$01
		cpx #$02
		ldy #$02
		cpy #$01
		cpy #$02
		cpy #$03
		ldz #$03
		cpz #$02
		cpz #$03
		cpz #$04

		; ADC / SBC immediate mode
		clc
		adc #$70
		sec
		adc #$00
		sec
		sbc #$10
		clc
		sbc #$10

		; some indirect addressing modes
		ldy #$23
		lda ($10),Y
		ldx #$07
		nop		
		lda ($20,X)
		; And test with several back to back, to make sure that pipeline
		; buffering of vector fetches works properly.
		lda ($30,X)
		lda ($40,X)
		lda ($50,X)
		lda ($60,X)
		lda ($70,X)


endlessloop:
		ldy #$00
		ldx #$fd
l1:		lda $1000,x
		sta $2000,x
		inx
		bne l1
		jmp l1



		.checkpc $20000
		.advance $20000

		.scend