pre-synthesis failure for Vitis

[PiDing]

I am trying to deploy a TensorFlow NN on FPGA by Vitis, but I encountered the following error. Could you provide any idea on this issue? Thanks.

ERROR: [HLS 214-384] in function 'void nnet::conv_2d_latency_cl<ap_uint<1>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, config15>(ap_uint<1>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, config15::weight_t*, config15::bias_t*) (.323)': Cannot apply array transformation pragma/directive because of full array load/store. (firmware/nnet_utils/nnet_conv2d_latency.h:82:11)
ERROR: [HLS 200-1715] Encountered problem during source synthesis
INFO: [HLS 200-111] Finished Command csynth_design CPU user time: 4605.13 seconds. CPU system time: 8.36 seconds. Elapsed time: 4624.67 seconds; current allocated memory: 7.852 MB.
Pre-synthesis failed.
while executing
"source build_prj.tcl"
("uplevel" body line 1)
invoked from within
"uplevel #0 [list source $arg] "