This repository contains the synthesizable Verilog code and the MATLAB m-file model for the "Approximate Booth Multiplier" described in this paper:
F. Farshchi, M. S. Abrishami, S. M. Fakhraie, "New approximate multiplier for low power digital signal processing," in CSI 17th Int. Symp. on Computer Architecture and Digital Systems (CADS), 2013. Paper PDF