diff --git a/drivers/gpu/drm/radeon/ps4_bridge.c b/drivers/gpu/drm/radeon/ps4_bridge.c
index 7bbba3ba0dcd3c..9156951e39b102 100644
--- a/drivers/gpu/drm/radeon/ps4_bridge.c
+++ b/drivers/gpu/drm/radeon/ps4_bridge.c
@@ -1,5 +1,5 @@
 /*
- * Panasonic mn864729 DP->HDMI bridge driver (via PS4 Aeolia ICC interface)
+ * Panasonic MN86471A / MN864729 DP->HDMI bridge driver (via PS4 Aeolia ICC interface)
  *
  * This software is licensed under the terms of the GNU General Public
  * License version 2, as published by the Free Software Foundation, and
@@ -96,6 +96,12 @@
 # define HDCPEN_ENC_DIS 0x05
 
 
+#define PCI_VENDOR_ID_AMD 0x1002
+#define PCI_DEVICE_ID_CUH_11XX 0x9920
+#define PCI_DEVICE_ID_CUH_12XX 0x9922
+#define PCI_DEVICE_ID_CUH_2XXX 0x9923
+#define PCI_DEVICE_ID_CUH_7XXX 0x9924
+
 struct i2c_cmd_hdr {
 	u8 major;
 	u8 length;
@@ -121,7 +127,7 @@ struct i2c_cmdqueue {
 	struct i2c_cmd_hdr *cmd;
 };
 
-struct mn864729_bridge {
+struct ps4_bridge {
 	struct drm_connector *connector;
 	struct drm_encoder *encoder;
 	struct drm_bridge bridge;
@@ -133,7 +139,7 @@ struct mn864729_bridge {
 
 /* this should really be taken care of by the connector, but that is currently
  * contained/owned by radeon_connector so just use a global for now */
-static struct mn864729_bridge g_bridge = {
+static struct ps4_bridge g_bridge = {
 	.mutex = __MUTEX_INITIALIZER(g_bridge.mutex)
 };
 
@@ -257,17 +263,17 @@ static void cq_wait_clear(struct i2c_cmdqueue *q, u16 addr, u8 mask)
 	*q->p++ = mask;
 }
 
-static inline struct mn864729_bridge *
-		bridge_to_mn864729(struct drm_bridge *bridge)
+static inline struct ps4_bridge *
+		bridge_to_ps4_bridge(struct drm_bridge *bridge)
 {
-	return container_of(bridge, struct mn864729_bridge, bridge);
+	return container_of(bridge, struct ps4_bridge, bridge);
 }
 
-static void mn864729_mode_set(struct drm_bridge *bridge,
+static void ps4_bridge_mode_set(struct drm_bridge *bridge,
 			      struct drm_display_mode *mode,
 			      struct drm_display_mode *adjusted_mode)
 {
-	struct mn864729_bridge *mn_bridge = bridge_to_mn864729(bridge);
+	struct ps4_bridge *mn_bridge = bridge_to_ps4_bridge(bridge);
 
 	/* This gets called before pre_enable/enable, so we just stash
 	 * the vic ID for later */
@@ -278,10 +284,10 @@ static void mn864729_mode_set(struct drm_bridge *bridge,
 	}
 }
 
-static void mn864729_pre_enable(struct drm_bridge *bridge)
+static void ps4_bridge_pre_enable(struct drm_bridge *bridge)
 {
-	struct mn864729_bridge *mn_bridge = bridge_to_mn864729(bridge);
-	DRM_DEBUG_KMS("mn864729_pre_enable\n");
+	struct ps4_bridge *mn_bridge = bridge_to_ps4_bridge(bridge);
+	DRM_DEBUG_KMS("ps4_bridge_pre_enable\n");
 
 	mutex_lock(&mn_bridge->mutex);
 	cq_init(&mn_bridge->cq, 4);
@@ -347,9 +353,12 @@ static void mn864729_pre_enable(struct drm_bridge *bridge)
 	mutex_unlock(&mn_bridge->mutex);
 }
 
-static void mn864729_enable(struct drm_bridge *bridge)
+static void ps4_bridge_enable(struct drm_bridge *bridge)
 {
-	struct mn864729_bridge *mn_bridge = bridge_to_mn864729(bridge);
+	struct ps4_bridge *mn_bridge = bridge_to_ps4_bridge(bridge);
+	struct drm_connector *connector = mn_bridge->connector;
+	struct drm_device *dev = connector->dev;
+	struct pci_dev *pdev = dev->pdev;
 	u8 dp[3];
 
 	if (!mn_bridge->mode) {
@@ -357,82 +366,171 @@ static void mn864729_enable(struct drm_bridge *bridge)
 		return;
 	}
 
-	DRM_DEBUG_KMS("mn864729_enable (mode: %d)\n", mn_bridge->mode);
+	if(pdev->vendor != PCI_VENDOR_ID_AMD) {
+		DRM_ERROR("Invalid vendor: %04x", pdev->vendor);
+		return;
+	}
 
-	/* Here come the dragons */
+	DRM_DEBUG_KMS("ps4_bridge_enable (mode: %d)\n", mn_bridge->mode);
 
-	mutex_lock(&mn_bridge->mutex);
-	cq_init(&mn_bridge->cq, 4);
+	/* Here come the dragons */
 
-	cq_mask(&mn_bridge->cq, 0x6005, 0x01, 0x01);
-	cq_writereg(&mn_bridge->cq, 0x6a03, 0x47);
-
-
-	/* Wait for DP lane status */
-
-	cq_wait_set(&mn_bridge->cq, 0x60f8, 0xff);
-	cq_wait_set(&mn_bridge->cq, 0x60f9, 0x01);
-	/* Wait for ?? */
-	cq_writereg(&mn_bridge->cq, 0x6a01, 0x4d);
-	cq_wait_set(&mn_bridge->cq, 0x60f9, 0x1a);
-
-
-	cq_mask(&mn_bridge->cq, 0x1e00, 0x00, 0x01);
-	cq_mask(&mn_bridge->cq, 0x1e02, 0x00, 0x70);
-
-	cq_writereg(&mn_bridge->cq, 0x6020, 0x00);
-	cq_writereg(&mn_bridge->cq, 0x7402, 0x1c);
-	cq_writereg(&mn_bridge->cq, 0x6020, 0x04);
-	cq_writereg(&mn_bridge->cq, TSYSCTRL, TSYSCTRL_HDMI);
-	cq_writereg(&mn_bridge->cq, 0x10c7, 0x38);
-	cq_writereg(&mn_bridge->cq, 0x1e02, 0x88);
-	cq_writereg(&mn_bridge->cq, 0x1e00, 0x66);
-	cq_writereg(&mn_bridge->cq, 0x100c, 0x01);
-	cq_writereg(&mn_bridge->cq, TSYSCTRL, TSYSCTRL_HDMI);
-
-	cq_writereg(&mn_bridge->cq, 0x7009, 0x00);
-	cq_writereg(&mn_bridge->cq, 0x7040, 0x42);
-	cq_writereg(&mn_bridge->cq, 0x7225, 0x28);
-	cq_writereg(&mn_bridge->cq, 0x7227, mn_bridge->mode);
-	cq_writereg(&mn_bridge->cq, 0x7228, 0x00);
-	cq_writereg(&mn_bridge->cq, 0x7070, mn_bridge->mode);
-	cq_writereg(&mn_bridge->cq, 0x7071, mn_bridge->mode | 0x80);
-	cq_writereg(&mn_bridge->cq, 0x7072, 0x00);
-	cq_writereg(&mn_bridge->cq, 0x7073, 0x00);
-	cq_writereg(&mn_bridge->cq, 0x7074, 0x00);
-	cq_writereg(&mn_bridge->cq, 0x7075, 0x00);
-	cq_writereg(&mn_bridge->cq, 0x70c4, 0x0a);
-	cq_writereg(&mn_bridge->cq, 0x70c5, 0x0a);
-	cq_writereg(&mn_bridge->cq, 0x70c2, 0x00);
-	cq_writereg(&mn_bridge->cq, 0x70fe, 0x12);
-	cq_writereg(&mn_bridge->cq, 0x70c3, 0x10);
-	cq_writereg(&mn_bridge->cq, 0x10c5, 0x00);
-	cq_writereg(&mn_bridge->cq, 0x10f6, 0xff);
-	cq_writereg(&mn_bridge->cq, 0x7202, 0x20);
-	cq_writereg(&mn_bridge->cq, 0x7203, 0x60);
-	cq_writereg(&mn_bridge->cq, 0x7011, 0xd5);
-	cq_writereg(&mn_bridge->cq, 0x7a00, 0x0e);
-	cq_wait_set(&mn_bridge->cq, 0x10f6, 0x80);
-	cq_mask(&mn_bridge->cq, 0x7226, 0x00, 0x80);
-	cq_mask(&mn_bridge->cq, 0x7228, 0x00, 0xFF);
-	cq_writereg(&mn_bridge->cq, 0x7204, 0x40);
-	cq_wait_clear(&mn_bridge->cq, 0x7204, 0x40);
-	cq_writereg(&mn_bridge->cq, 0x7a8b, 0x05);
-	cq_mask(&mn_bridge->cq, 0x1e02, 0x70, 0x70);
-	cq_mask(&mn_bridge->cq, 0x1034, 0x02, 0x02);
-	cq_mask(&mn_bridge->cq, 0x1e00, 0x01, 0x01);
-	cq_writereg(&mn_bridge->cq, VMUTECNT, VMUTECNT_LINEWIDTH_90);
-	if (cq_exec(&mn_bridge->cq) < 0) {
-		DRM_ERROR("Failed to configure bridge mode\n");
+	if(pdev->device == PCI_DEVICE_ID_CUH_11XX)
+	{
+		/* Panasonic MN86471A */
+		mutex_lock(&mn_bridge->mutex);
+		cq_init(&mn_bridge->cq, 4);
+
+		/* Read DisplayPort status (?) */
+		cq_read(&mn_bridge->cq, 0x76e1, 3);
+		if (cq_exec(&mn_bridge->cq) < 11) {
+			mutex_unlock(&mn_bridge->mutex);
+			DRM_ERROR("could not read DP status");
+		return;
+		}
+		memcpy(dp, &mn_bridge->cq.reply.databuf[3], 3);
+
+		cq_init(&mn_bridge->cq, 4);
+
+		/* Wait for DP lane status */
+		cq_wait_set(&mn_bridge->cq, 0x761e, 0x77);
+		cq_wait_set(&mn_bridge->cq, 0x761f, 0x77);
+		/* Wait for ?? */
+		cq_wait_set(&mn_bridge->cq, 0x7669, 0x01);
+		cq_writereg(&mn_bridge->cq, 0x76d9, (dp[0] & 0x1f) | (dp[0] << 5));
+		cq_writereg(&mn_bridge->cq, 0x76da, (dp[1] & 0x7c) | ((dp[0] >> 3) & 3) | ((dp[1] << 5) & 0x80));
+		cq_writereg(&mn_bridge->cq, 0x76db, 0x80 | ((dp[1] >> 3) & 0xf));
+		cq_writereg(&mn_bridge->cq, 0x76e4, 0x01);
+		cq_writereg(&mn_bridge->cq, TSYSCTRL, TSYSCTRL_HDMI);
+		cq_writereg(&mn_bridge->cq, VINCNT, VINCNT_VIF_FILEN);
+		cq_writereg(&mn_bridge->cq, 0x7071, 0);
+		cq_writereg(&mn_bridge->cq, 0x7062, mn_bridge->mode);
+		cq_writereg(&mn_bridge->cq, 0x765a, 0);
+		cq_writereg(&mn_bridge->cq, 0x7062, mn_bridge->mode | 0x80);
+		cq_writereg(&mn_bridge->cq, 0x7215, 0x28); /* aspect */
+		cq_writereg(&mn_bridge->cq, 0x7217, mn_bridge->mode);
+		cq_writereg(&mn_bridge->cq, 0x7218, 0);
+		cq_writereg(&mn_bridge->cq, CSCMOD, 0xdc);
+		cq_writereg(&mn_bridge->cq, C420SET, 0xaa);
+		cq_writereg(&mn_bridge->cq, TDPCMODE, 0x4a);
+		cq_writereg(&mn_bridge->cq, OUTWSET, 0x00);
+		cq_writereg(&mn_bridge->cq, 0x70c4, 0x08);
+		cq_writereg(&mn_bridge->cq, 0x70c5, 0x08);
+		cq_writereg(&mn_bridge->cq, 0x7096, 0xff);
+		cq_writereg(&mn_bridge->cq, 0x7027, 0x00);
+		cq_writereg(&mn_bridge->cq, 0x7020, 0x20);
+		cq_writereg(&mn_bridge->cq, 0x700b, 0x01);
+		cq_writereg(&mn_bridge->cq, PKTENA, 0x20);
+		cq_writereg(&mn_bridge->cq, 0x7096, 0xff);
+		cq_writereg(&mn_bridge->cq, INFENA, INFENA_AVIEN);
+		cq_writereg(&mn_bridge->cq, UPDCTRL, UPDCTRL_ALLUPD | UPDCTRL_AVIIUPD |
+						     UPDCTRL_CLKUPD | UPDCTRL_VIFUPD |
+						     UPDCTRL_CSCUPD);
+		cq_wait_set(&mn_bridge->cq, 0x7096, 0x80);
+
+		cq_mask(&mn_bridge->cq, 0x7216, 0x00, 0x80);
+		cq_writereg(&mn_bridge->cq, 0x7218, 0x00);
+
+		cq_writereg(&mn_bridge->cq, 0x7096, 0xff);
+		cq_writereg(&mn_bridge->cq, VMUTECNT, VMUTECNT_LINEWIDTH_90 | VMUTECNT_VMUTE_MUTE_NORMAL);
+		cq_writereg(&mn_bridge->cq, 0x7016, 0x04);
+		cq_writereg(&mn_bridge->cq, 0x7a88, 0xff);
+		cq_writereg(&mn_bridge->cq, 0x7a83, 0x88);
+		cq_writereg(&mn_bridge->cq, 0x7204, 0x40);
+
+		cq_wait_set(&mn_bridge->cq, 0x7096, 0x80);
+
+		cq_writereg(&mn_bridge->cq, 0x7006, 0x02);
+		cq_writereg(&mn_bridge->cq, 0x7020, 0x21);
+		cq_writereg(&mn_bridge->cq, 0x7a8b, 0x00);
+		cq_writereg(&mn_bridge->cq, 0x7020, 0x21);
+
+		cq_writereg(&mn_bridge->cq, VMUTECNT, VMUTECNT_LINEWIDTH_90);
+		if (cq_exec(&mn_bridge->cq) < 0) {
+			DRM_ERROR("Failed to configure ps4-bridge (MN86471A) mode\n");
+		}
+		mutex_unlock(&mn_bridge->mutex);
+	}
+	else
+	{
+		/* Panasonic MN864729 */
+		mutex_lock(&mn_bridge->mutex);
+		cq_init(&mn_bridge->cq, 4);
+		cq_mask(&mn_bridge->cq, 0x6005, 0x01, 0x01);
+		cq_writereg(&mn_bridge->cq, 0x6a03, 0x47);
+
+		/* Wait for DP lane status */
+		cq_wait_set(&mn_bridge->cq, 0x60f8, 0xff);
+		cq_wait_set(&mn_bridge->cq, 0x60f9, 0x01);
+		cq_writereg(&mn_bridge->cq, 0x6a01, 0x4d);
+		cq_wait_set(&mn_bridge->cq, 0x60f9, 0x1a);
+
+		cq_mask(&mn_bridge->cq, 0x1e00, 0x00, 0x21);
+		cq_mask(&mn_bridge->cq, 0x1e02, 0x00, 0x70);
+
+		cq_writereg(&mn_bridge->cq, 0x6020, 0x00);
+		cq_writereg(&mn_bridge->cq, 0x7402, 0x1c);
+		cq_writereg(&mn_bridge->cq, 0x6020, 0x04);
+		cq_writereg(&mn_bridge->cq, TSYSCTRL, TSYSCTRL_HDMI);
+		cq_writereg(&mn_bridge->cq, 0x10c7, 0x38);
+		cq_writereg(&mn_bridge->cq, 0x1e02, 0x88);
+		cq_writereg(&mn_bridge->cq, 0x1e00, 0x66);
+		cq_writereg(&mn_bridge->cq, 0x100c, 0x01);
+		cq_writereg(&mn_bridge->cq, TSYSCTRL, TSYSCTRL_HDMI);
+
+		cq_writereg(&mn_bridge->cq, 0x7009, 0x00);
+		cq_writereg(&mn_bridge->cq, 0x7040, 0x42);
+		cq_writereg(&mn_bridge->cq, 0x7225, 0x28);
+		cq_writereg(&mn_bridge->cq, 0x7227, mn_bridge->mode);
+		cq_writereg(&mn_bridge->cq, 0x7228, 0x00);
+		cq_writereg(&mn_bridge->cq, 0x7070, mn_bridge->mode);
+		cq_writereg(&mn_bridge->cq, 0x7071, mn_bridge->mode | 0x80);
+		cq_writereg(&mn_bridge->cq, 0x7072, 0x00);
+		cq_writereg(&mn_bridge->cq, 0x7073, 0x00);
+		cq_writereg(&mn_bridge->cq, 0x7074, 0x00);
+		cq_writereg(&mn_bridge->cq, 0x7075, 0x00);
+		cq_writereg(&mn_bridge->cq, 0x70c4, 0x0a);
+		cq_writereg(&mn_bridge->cq, 0x70c5, 0x0a);
+		cq_writereg(&mn_bridge->cq, 0x70c2, 0x00);
+		cq_writereg(&mn_bridge->cq, 0x70fe, 0x12);
+		cq_writereg(&mn_bridge->cq, 0x70c3, 0x10);
+
+		if(pdev->device == PCI_DEVICE_ID_CUH_12XX) {
+			/* newer ps4 phats need here 0x03 idk why. */
+			cq_writereg(&mn_bridge->cq, 0x10c5, 0x03);
+		} else {
+			cq_writereg(&mn_bridge->cq, 0x10c5, 0x00);
+		}
+
+		cq_writereg(&mn_bridge->cq, 0x10f6, 0xff);
+		cq_writereg(&mn_bridge->cq, 0x7202, 0x20);
+		cq_writereg(&mn_bridge->cq, 0x7203, 0x60);
+		cq_writereg(&mn_bridge->cq, 0x7011, 0xd5);
+		//cq_writereg(&mn_bridge->cq, 0x7a00, 0x0e);
+
+		cq_wait_set(&mn_bridge->cq, 0x10f6, 0x80);
+		cq_mask(&mn_bridge->cq, 0x7226, 0x00, 0x80);
+		cq_mask(&mn_bridge->cq, 0x7228, 0x00, 0xFF);
+		cq_writereg(&mn_bridge->cq, 0x7204, 0x40);
+		cq_wait_clear(&mn_bridge->cq, 0x7204, 0x40);
+		cq_writereg(&mn_bridge->cq, 0x7a8b, 0x05);
+		cq_mask(&mn_bridge->cq, 0x1e02, 0x70, 0x70);
+		cq_mask(&mn_bridge->cq, 0x1034, 0x02, 0x02);
+		cq_mask(&mn_bridge->cq, 0x1e00, 0x01, 0x01);
+		cq_writereg(&mn_bridge->cq, VMUTECNT, VMUTECNT_LINEWIDTH_90);
+		cq_writereg(&mn_bridge->cq, HDCPEN, 0x00);
+		if (cq_exec(&mn_bridge->cq) < 0) {
+			DRM_ERROR("Failed to configure ps4-bridge (MN864729) mode\n");
+		}
+		mutex_unlock(&mn_bridge->mutex);
 	}
 
-	mutex_unlock(&mn_bridge->mutex);
 }
 
-static void mn864729_disable(struct drm_bridge *bridge)
+static void ps4_bridge_disable(struct drm_bridge *bridge)
 {
-	struct mn864729_bridge *mn_bridge = bridge_to_mn864729(bridge);
-	DRM_DEBUG_KMS("mn864729_disable\n");
+	struct ps4_bridge *mn_bridge = bridge_to_ps4_bridge(bridge);
+	DRM_DEBUG_KMS("ps4_bridge_disable\n");
 
 	mutex_lock(&mn_bridge->mutex);
 	cq_init(&mn_bridge->cq, 4);
@@ -444,10 +542,10 @@ static void mn864729_disable(struct drm_bridge *bridge)
 	mutex_unlock(&mn_bridge->mutex);
 }
 
-static void mn864729_post_disable(struct drm_bridge *bridge)
+static void ps4_bridge_post_disable(struct drm_bridge *bridge)
 {
-	/* struct mn864729_bridge *mn_bridge = bridge_to_mn864729(bridge); */
-	DRM_DEBUG_KMS("mn864729_post_disable\n");
+	/* struct ps4_bridge *mn_bridge = bridge_to_mn864729(bridge); */
+	DRM_DEBUG_KMS("ps4_bridge_post_disable\n");
 }
 
 /* Hardcoded modes, since we don't really know how to do custom modes yet.
@@ -475,16 +573,17 @@ static const struct drm_display_mode mode_1080p = {
 	.vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9
 };
 
-int mn864729_get_modes(struct drm_connector *connector)
+int ps4_bridge_get_modes(struct drm_connector *connector)
 {
 	struct drm_device *dev = connector->dev;
 	struct drm_display_mode *newmode;
-	DRM_DEBUG_KMS("mn864729_get_modes\n");
+	DRM_DEBUG_KMS("ps4_bridge_get_modes\n");
 
 	newmode = drm_mode_duplicate(dev, &mode_1080p);
 	drm_mode_probed_add(connector, newmode);
-	//newmode = drm_mode_duplicate(dev, &mode_720p);
-	//drm_mode_probed_add(connector, newmode);
+
+	newmode = drm_mode_duplicate(dev, &mode_720p);
+	drm_mode_probed_add(connector, newmode);
 	//newmode = drm_mode_duplicate(dev, &mode_480p);
 	//drm_mode_probed_add(connector, newmode);
 
@@ -493,10 +592,10 @@ int mn864729_get_modes(struct drm_connector *connector)
 	return 0;
 }
 
-enum drm_connector_status mn864729_detect(struct drm_connector *connector,
+enum drm_connector_status ps4_bridge_detect(struct drm_connector *connector,
 		bool force)
 {
-	struct mn864729_bridge *mn_bridge = &g_bridge;
+	struct ps4_bridge *mn_bridge = &g_bridge;
 	u8 reg;
 
 	struct radeon_connector *radeon_connector = to_radeon_connector(connector);
@@ -524,45 +623,45 @@ enum drm_connector_status mn864729_detect(struct drm_connector *connector,
 		return connector_status_disconnected;
 }
 
-int mn864729_mode_valid(struct drm_connector *connector,
+int ps4_bridge_mode_valid(struct drm_connector *connector,
 				  struct drm_display_mode *mode)
 {
 	int vic = drm_match_cea_mode(mode);
 
 	/* Allow anything that we can match up to a VIC (CEA modes) */
-	if (!vic || vic != 16) {
+	if (!vic || (vic != 16 && vic != 4)) {
 		return MODE_BAD;
 	}
 
 	return MODE_OK;
 }
 
-static int mn864729_bridge_attach(struct drm_bridge *bridge)
+static int ps4_bridge_attach(struct drm_bridge *bridge)
 {
-	/* struct mn864729_bridge *mn_bridge = bridge_to_mn864729(bridge); */
+	/* struct ps4_bridge *mn_bridge = bridge_to_ps4_bridge(bridge); */
 
 	return 0;
 }
 
-static struct drm_bridge_funcs mn864729_bridge_funcs = {
-	.pre_enable = mn864729_pre_enable,
-	.enable = mn864729_enable,
-	.disable = mn864729_disable,
-	.post_disable = mn864729_post_disable,
-	.attach = mn864729_bridge_attach,
-	.mode_set = mn864729_mode_set
+static struct drm_bridge_funcs ps4_bridge_funcs = {
+	.pre_enable = ps4_bridge_pre_enable,
+	.enable = ps4_bridge_enable,
+	.disable = ps4_bridge_disable,
+	.post_disable = ps4_bridge_post_disable,
+	.attach = ps4_bridge_attach,
+	.mode_set = ps4_bridge_mode_set
 };
 
-int mn864729_bridge_register(struct drm_connector *connector,
+int ps4_bridge_register(struct drm_connector *connector,
 			     struct drm_encoder *encoder)
 {
 	int ret;
-	struct mn864729_bridge *mn_bridge = &g_bridge;
+	struct ps4_bridge *mn_bridge = &g_bridge;
 	struct drm_device *dev = connector->dev;
 
 	mn_bridge->encoder = encoder;
 	mn_bridge->connector = connector;
-	mn_bridge->bridge.funcs = &mn864729_bridge_funcs;
+	mn_bridge->bridge.funcs = &ps4_bridge_funcs;
 	ret = drm_bridge_attach(dev, &mn_bridge->bridge);
 	if (ret) {
 		DRM_ERROR("Failed to initialize bridge with drm\n");
diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c b/drivers/gpu/drm/radeon/radeon_connectors.c
index f928a41555f734..8002310e20b8b5 100644
--- a/drivers/gpu/drm/radeon/radeon_connectors.c
+++ b/drivers/gpu/drm/radeon/radeon_connectors.c
@@ -1852,21 +1852,21 @@ static const struct drm_connector_funcs radeon_dp_connector_funcs = {
 };
 
 #ifdef CONFIG_X86_PS4
-int mn864729_get_modes(struct drm_connector *connector);
-enum drm_connector_status mn864729_detect(struct drm_connector *connector,
+int ps4_bridge_get_modes(struct drm_connector *connector);
+enum drm_connector_status ps4_bridge_detect(struct drm_connector *connector,
 					  bool force);
-int mn864729_mode_valid(struct drm_connector *connector,
+int ps4_bridge_mode_valid(struct drm_connector *connector,
 			struct drm_display_mode *mode);
 
 static const struct drm_connector_helper_funcs radeon_ps4_dp_connector_helper_funcs = {
-	.get_modes = mn864729_get_modes,
-	.mode_valid = mn864729_mode_valid,
+	.get_modes = ps4_bridge_get_modes,
+	.mode_valid = ps4_bridge_mode_valid,
 	.best_encoder = radeon_dvi_encoder,
 };
 
 static const struct drm_connector_funcs radeon_ps4_dp_connector_funcs = {
 	.dpms = drm_helper_connector_dpms,
-	.detect = mn864729_detect,
+	.detect = ps4_bridge_detect,
 	.fill_modes = drm_helper_probe_single_connector_modes,
 	//.set_property = radeon_connector_set_property,
 	.destroy = radeon_connector_destroy,
diff --git a/drivers/gpu/drm/radeon/radeon_encoders.c b/drivers/gpu/drm/radeon/radeon_encoders.c
index af5eec17a29e01..cabc57eab5eaac 100644
--- a/drivers/gpu/drm/radeon/radeon_encoders.c
+++ b/drivers/gpu/drm/radeon/radeon_encoders.c
@@ -198,7 +198,7 @@ static void radeon_encoder_add_backlight(struct radeon_encoder *radeon_encoder,
 }
 
 #ifdef CONFIG_X86_PS4
-int mn864729_bridge_register(struct drm_connector *connector,
+int ps4_bridge_register(struct drm_connector *connector,
 			     struct drm_encoder *encoder);
 
 static void radeon_maybe_add_bridge(struct drm_connector *connector,
@@ -208,7 +208,7 @@ static void radeon_maybe_add_bridge(struct drm_connector *connector,
 	struct radeon_device *rdev = dev->dev_private;
 
 	if (rdev->family == CHIP_LIVERPOOL) {
-		mn864729_bridge_register(connector, encoder);
+		ps4_bridge_register(connector, encoder);
 	}
 }
 #endif
diff --git a/drivers/net/ethernet/marvell/sky2.c b/drivers/net/ethernet/marvell/sky2.c
index 0222bf0cbdd3a8..cc6abae6df0bbc 100644
--- a/drivers/net/ethernet/marvell/sky2.c
+++ b/drivers/net/ethernet/marvell/sky2.c
@@ -5047,7 +5047,7 @@ static int sky2_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 #ifdef CONFIG_X86_PS4
 	if (pdev->vendor == PCI_VENDOR_ID_SONY) {
 		if (pci_set_dma_mask(pdev, DMA_BIT_MASK(31)) < 0 ||
-		    pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(31) < 0)) {
+		    pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(31)) < 0) {
 			dev_err(&pdev->dev, "no usable DMA configuration\n");
 			goto err_out_free_regions;
 		}
diff --git a/include/drm/drm_pciids.h b/include/drm/drm_pciids.h
index 04d48f3b28d309..cab8d37de77b47 100644
--- a/include/drm/drm_pciids.h
+++ b/include/drm/drm_pciids.h
@@ -682,6 +682,7 @@
 	{0x1002, 0x9918, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARUBA|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
 	{0x1002, 0x9919, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARUBA|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
 	{0x1002, 0x9920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_LIVERPOOL|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
+	{0x1002, 0x9922, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_LIVERPOOL|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
 	{0x1002, 0x9923, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_LIVERPOOL|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
 	{0x1002, 0x9924, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_LIVERPOOL|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
 	{0x1002, 0x9990, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARUBA|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \