From b5589db377ebb2b0489593b82477bca6a53fa384 Mon Sep 17 00:00:00 2001 From: walerii Date: Sat, 30 Sep 2023 09:25:45 +0200 Subject: [PATCH] Update host-based-security-workflows.rst --- docs/en/security/host-based-security-workflows.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/en/security/host-based-security-workflows.rst b/docs/en/security/host-based-security-workflows.rst index caf5c99df4ab..5753572f92a9 100644 --- a/docs/en/security/host-based-security-workflows.rst +++ b/docs/en/security/host-based-security-workflows.rst @@ -8,7 +8,7 @@ Host-Based Security Workflows Introduction ------------ -It is recommended to have an uninterrupted power supply while enabling security features on ESP32 SoCs. Power failures during the process of secure boot enabling could cause issues that are hard to debug and, in some cases, may cause permanent boot-up failures. +It is recommended to have an uninterrupted power supply while enabling security features on ESP32 SoCs. Power failures during the secure manufacturing process could cause issues that are hard to debug and, in some cases, may cause permanent boot-up failures. This guide highlights an approach where security features are enabled with the assistance of an external host machine. Security workflows are broken down into various stages and key material is generated on the host machine; thus, allowing greater recovery chances in case of power or other failures. It also offers better timings for secure manufacturing, e.g., in the case of encryption of firmware on the host machine vs. on the device.