From 2159ec753959a5bc5f0cc81e594ca90842814da7 Mon Sep 17 00:00:00 2001 From: hongshuqing Date: Thu, 18 Apr 2024 14:52:08 +0800 Subject: [PATCH 001/472] fix(h2): modify wrong lslp drvb config --- .../esp_hw_support/port/esp32h2/private_include/pmu_param.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/components/esp_hw_support/port/esp32h2/private_include/pmu_param.h b/components/esp_hw_support/port/esp32h2/private_include/pmu_param.h index 58fbf97ff48..52ad70fa213 100644 --- a/components/esp_hw_support/port/esp32h2/private_include/pmu_param.h +++ b/components/esp_hw_support/port/esp32h2/private_include/pmu_param.h @@ -340,7 +340,7 @@ typedef struct { }, \ .lp_sys[PMU_MODE_LP_SLEEP] = { \ .analog = { \ - .drv_b = PMU_LP_DRVB_DEEPSLEEP, \ + .drv_b = PMU_LP_DRVB_LIGHTSLEEP, \ .pd_cur = PMU_PD_CUR_SLEEP_DEFAULT, \ .bias_sleep = PMU_BIASSLP_SLEEP_DEFAULT, \ .slp_xpd = PMU_LP_SLP_XPD_SLEEP_DEFAULT, \ @@ -407,7 +407,7 @@ typedef struct { typedef struct pmu_sleep_machine_constant { struct { - uint16_t min_slp_time_us; /* Mininum sleep protection time (unit: microsecond) */ + uint16_t min_slp_time_us; /* Minimum sleep protection time (unit: microsecond) */ uint8_t reserved0; uint16_t reserved1; uint16_t analog_wait_time_us; /* LP LDO power up wait time (unit: microsecond) */ @@ -418,7 +418,7 @@ typedef struct pmu_sleep_machine_constant { uint16_t power_up_wait_time_us; /* (unit: microsecond) */ } lp; struct { - uint16_t min_slp_time_us; /* Mininum sleep protection time (unit: microsecond) */ + uint16_t min_slp_time_us; /* Minimum sleep protection time (unit: microsecond) */ uint16_t analog_wait_time_us; /* HP LDO power up wait time (unit: microsecond) */ uint16_t power_supply_wait_time_us; /* (unit: microsecond) */ uint16_t power_up_wait_time_us; /* (unit: microsecond) */ From f3087c8fb04541d3b87684bc32ad1fa74da4259e Mon Sep 17 00:00:00 2001 From: hongshuqing Date: Thu, 6 Jun 2024 21:42:23 +0800 Subject: [PATCH 002/472] fix: fix pll low temp bug --- components/esp_hw_support/port/esp32h2/pmu_sleep.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/components/esp_hw_support/port/esp32h2/pmu_sleep.c b/components/esp_hw_support/port/esp32h2/pmu_sleep.c index ab32613ab59..60492aa4de1 100644 --- a/components/esp_hw_support/port/esp32h2/pmu_sleep.c +++ b/components/esp_hw_support/port/esp32h2/pmu_sleep.c @@ -20,6 +20,8 @@ #include "hal/efuse_ll.h" #include "hal/efuse_hal.h" #include "esp_hw_log.h" +#include "soc/regi2c_bias.h" +#include "regi2c_ctrl.h" static __attribute__((unused)) const char *TAG = "pmu_sleep"; @@ -264,6 +266,8 @@ uint32_t pmu_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt, uint32_t lslp bool pmu_sleep_finish(bool dslp) { (void)dslp; + // Restore registers lost during sleep + REGI2C_WRITE_MASK(I2C_BIAS, I2C_BIAS_DREG_0P8, 8); // fix low temp issue, need to increase this internal voltage return pmu_ll_hp_is_sleep_reject(PMU_instance()->hal->dev); } From 04a231f29769e553e9ac43869692156bcbfa0614 Mon Sep 17 00:00:00 2001 From: morris Date: Tue, 30 Jul 2024 14:38:28 +0800 Subject: [PATCH 003/472] feat(blink): support esp32 p4 core board --- examples/get-started/blink/sdkconfig.defaults.esp32p4 | 2 ++ 1 file changed, 2 insertions(+) create mode 100644 examples/get-started/blink/sdkconfig.defaults.esp32p4 diff --git a/examples/get-started/blink/sdkconfig.defaults.esp32p4 b/examples/get-started/blink/sdkconfig.defaults.esp32p4 new file mode 100644 index 00000000000..cc80f60a684 --- /dev/null +++ b/examples/get-started/blink/sdkconfig.defaults.esp32p4 @@ -0,0 +1,2 @@ +CONFIG_BLINK_GPIO=44 +CONFIG_BLINK_LED_STRIP=y From 4a185b824dfad3b33cc7c29695848965408561e2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Tom=C3=A1=C5=A1=20Rohl=C3=ADnek?= Date: Wed, 4 Sep 2024 12:11:43 +0200 Subject: [PATCH 004/472] fix(storage/vfs): fix incorrect test case configuration --- .../spiffs/host_test/main/host_test_spiffs.c | 40 +++++++++---------- 1 file changed, 19 insertions(+), 21 deletions(-) diff --git a/components/spiffs/host_test/main/host_test_spiffs.c b/components/spiffs/host_test/main/host_test_spiffs.c index 4fcfce13c1f..8a63c1316ac 100644 --- a/components/spiffs/host_test/main/host_test_spiffs.c +++ b/components/spiffs/host_test/main/host_test_spiffs.c @@ -281,29 +281,27 @@ TEST(spiffs, erase_check) init_spiffs(&fs, 5); - for (int boot_iter = 0; boot_iter <= 10000; ++boot_iter) { - for (int write_iter = 0; write_iter < 1000; ++write_iter) { - spiffs_file f = SPIFFS_open(&fs, "/test", SPIFFS_CREAT | SPIFFS_TRUNC | SPIFFS_RDWR, 0); - if (f < 0) { - fprintf(stderr, "Failed to open file\n"); + for (int write_iter = 0; write_iter < 100; ++write_iter) { + spiffs_file f = SPIFFS_open(&fs, "/test", SPIFFS_CREAT | SPIFFS_TRUNC | SPIFFS_RDWR, 0); + if (f < 0) { + fprintf(stderr, "Failed to open file\n"); #if !CONFIG_ESP_PARTITION_ERASE_CHECK - TEST_FAIL(); + TEST_FAIL(); #endif - return; - } - const int data_sz = 7 * 1024; - char data[data_sz]; - memset(data, 0x55, data_sz); - int cb = SPIFFS_write(&fs, f, data, data_sz); - if (cb != data_sz) { - fprintf(stderr, "Failed to write file\n"); - TEST_FAIL(); - } - int rc = SPIFFS_close(&fs, f); - if (rc < 0) { - fprintf(stderr, "Failed to close file\n"); - TEST_FAIL(); - } + return; + } + const int data_sz = 7 * 1024; + char data[data_sz]; + memset(data, 0x55, data_sz); + int cb = SPIFFS_write(&fs, f, data, data_sz); + if (cb != data_sz) { + fprintf(stderr, "Failed to write file\n"); + TEST_FAIL(); + } + int rc = SPIFFS_close(&fs, f); + if (rc < 0) { + fprintf(stderr, "Failed to close file\n"); + TEST_FAIL(); } } From 1f0763b9322702c033bd68a76ba8074e44cabbad Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Tom=C3=A1=C5=A1=20Rohl=C3=ADnek?= Date: Thu, 1 Aug 2024 11:38:21 +0200 Subject: [PATCH 005/472] fix(storage/example): correct alloc function --- .../perf_benchmark/main/perf_benchmark_example_tests.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/examples/storage/perf_benchmark/main/perf_benchmark_example_tests.c b/examples/storage/perf_benchmark/main/perf_benchmark_example_tests.c index 1e40685f15c..789e6ce305b 100644 --- a/examples/storage/perf_benchmark/main/perf_benchmark_example_tests.c +++ b/examples/storage/perf_benchmark/main/perf_benchmark_example_tests.c @@ -50,7 +50,7 @@ static void print_results(const char *name, double time, size_t size, int repeat void spiflash_speed_test_raw_run(size_t repeat_count) { const size_t buf_size = CONFIG_EXAMPLE_TARGET_RW_SIZE; - uint32_t* buf = (uint32_t*) calloc(1, buf_size); + uint32_t* buf = (uint32_t*) heap_caps_calloc(1, buf_size, MALLOC_CAP_INTERNAL | MALLOC_CAP_CACHE_ALIGNED | MALLOC_CAP_DMA); assert(buf != NULL); esp_fill_random(buf, buf_size); @@ -159,7 +159,7 @@ static void run_fs_tests(const char *base_path, const char *type, bool new_file, assert(tiny_size < less_than_target_size); const size_t buf_size = more_than_target_size; - uint32_t* buf = (uint32_t*) calloc(1, buf_size); + uint32_t* buf = (uint32_t*) heap_caps_calloc(1, buf_size, MALLOC_CAP_INTERNAL | MALLOC_CAP_CACHE_ALIGNED | MALLOC_CAP_DMA); assert(buf != NULL); esp_fill_random(buf, buf_size); @@ -219,7 +219,8 @@ void sdcard_speed_test_raw_run(sdmmc_card_t *card, size_t repeat_count) size_t sector_count = CONFIG_EXAMPLE_TARGET_RW_SIZE / sector_size; size_t subsection_sector_count = sector_count / 4; - char *buf = (char *) calloc(1, sector_count * sector_size); + // Best performance is achieved when the buffer is internal (not PSRAM) and aligned to RAM line size + char *buf = (char *) heap_caps_calloc(1, sector_count * sector_size, MALLOC_CAP_INTERNAL | MALLOC_CAP_CACHE_ALIGNED | MALLOC_CAP_DMA); assert(buf != NULL); struct timeval tv_start; From 4e76f8bdc19d3faf49f1ecfa2b0586c470b49b0d Mon Sep 17 00:00:00 2001 From: gaoxu Date: Wed, 18 Sep 2024 15:05:56 +0800 Subject: [PATCH 006/472] docs(adc): update adc oneshot/continuous docs on P4 --- docs/docs_not_updated/esp32p4.txt | 2 - .../peripherals/adc_continuous.rst | 46 ++++++------------- .../api-reference/peripherals/adc_oneshot.rst | 42 +++++------------ .../peripherals/adc_continuous.rst | 46 ++++++------------- .../api-reference/peripherals/adc_oneshot.rst | 42 +++++------------ 5 files changed, 50 insertions(+), 128 deletions(-) diff --git a/docs/docs_not_updated/esp32p4.txt b/docs/docs_not_updated/esp32p4.txt index e11054ce4e5..158999f510a 100644 --- a/docs/docs_not_updated/esp32p4.txt +++ b/docs/docs_not_updated/esp32p4.txt @@ -6,8 +6,6 @@ api-guides/usb-otg-console.rst api-guides/esp-wifi-mesh.rst api-guides/dfu.rst api-guides/wifi-security.rst -api-reference/peripherals/adc_continuous.rst -api-reference/peripherals/adc_oneshot.rst api-reference/peripherals/touch_element.rst api-reference/peripherals/touch_pad.rst api-reference/peripherals/adc_calibration.rst diff --git a/docs/en/api-reference/peripherals/adc_continuous.rst b/docs/en/api-reference/peripherals/adc_continuous.rst index 32dc9b5c7bf..853f82314d3 100644 --- a/docs/en/api-reference/peripherals/adc_continuous.rst +++ b/docs/en/api-reference/peripherals/adc_continuous.rst @@ -290,39 +290,19 @@ To do further calibration to convert the ADC raw result to voltage in mV, please Hardware Limitations ^^^^^^^^^^^^^^^^^^^^ -- A specific ADC unit can only work under one operating mode at any one time, either continuous mode or one-shot mode. :cpp:func:`adc_continuous_start` has provided the protection. - -- Random Number Generator (RNG) uses ADC as an input source. When ADC continuous mode driver works, the random number generated from RNG will be less random. - -.. only:: esp32 or esp32s2 - - - ADC2 is also used by Wi-Fi. :cpp:func:`adc_continuous_start` has provided the protection between Wi-Fi driver and ADC continuous mode driver. - -.. only:: esp32 - - - ADC continuous mode driver uses I2S0 peripheral as hardware DMA FIFO. Therefore, if I2S0 is in use already, the :cpp:func:`adc_continuous_new_handle` will return :c:macro:`ESP_ERR_NOT_FOUND`. - - - ESP32 DevKitC: GPIO 0 cannot be used due to external auto program circuits. - - - ESP-WROVER-KIT: GPIO 0, 2, 4, and 15 cannot be used due to external connections for different purposes. - -.. only:: esp32s2 - - - ADC continuous mode driver uses SPI3 peripheral as hardware DMA FIFO. Therefore, if SPI3 is in use already, the :cpp:func:`adc_continuous_new_handle` will return :c:macro:`ESP_ERR_NOT_FOUND`. - -.. only:: esp32c3 - - - ADC2 DMA functionality is no longer supported to retrieve ADC conversion results due to hardware limitations, as unstable results have been observed. This issue can be found in `ESP32C3 Errata `_. For compatibility, you can enable :ref:`CONFIG_ADC_CONTINUOUS_FORCE_USE_ADC2_ON_C3_S3` to force use ADC2. - -.. only:: esp32s3 - - - ADC2 DMA functionality is no longer supported to retrieve ADC conversion results due to hardware limitations, as unstable results have been observed. This issue can be found in `ESP32S3 Errata `_. For compatibility, you can enable :ref:`CONFIG_ADC_CONTINUOUS_FORCE_USE_ADC2_ON_C3_S3` to force use ADC2. - - .. _adc-continuous-power-management: - -.. only:: not esp32s3 - - .. _adc-continuous-power-management: +.. list:: + + - A specific ADC unit can only work under one operating mode at any one time, either continuous mode or one-shot mode. :cpp:func:`adc_continuous_start` has provided the protection. + - Random Number Generator (RNG) uses ADC as an input source. When ADC continuous mode driver works, the random number generated from RNG will be less random. + :esp32 or esp32s2: - ADC2 is also used by Wi-Fi. :cpp:func:`adc_continuous_start` has provided the protection between Wi-Fi driver and ADC continuous mode driver. + :esp32: - ADC continuous mode driver uses I2S0 peripheral as hardware DMA FIFO. Therefore, if I2S0 is in use already, the :cpp:func:`adc_continuous_new_handle` will return :c:macro:`ESP_ERR_NOT_FOUND`. + :esp32: - ESP32 DevKitC: GPIO 0 cannot be used due to external auto program circuits. + :esp32: - ESP-WROVER-KIT: GPIO 0, 2, 4, and 15 cannot be used due to external connections for different purposes. + :esp32s2: - ADC continuous mode driver uses SPI3 peripheral as hardware DMA FIFO. Therefore, if SPI3 is in use already, the :cpp:func:`adc_continuous_new_handle` will return :c:macro:`ESP_ERR_NOT_FOUND`. + :esp32c3: - ADC2 DMA functionality is no longer supported to retrieve ADC conversion results due to hardware limitations, as unstable results have been observed. This issue can be found in `ESP32C3 Errata `_. For compatibility, you can enable :ref:`CONFIG_ADC_CONTINUOUS_FORCE_USE_ADC2_ON_C3_S3` to force use ADC2. + :esp32s3: - ADC2 DMA functionality is no longer supported to retrieve ADC conversion results due to hardware limitations, as unstable results have been observed. This issue can be found in `ESP32S3 Errata `_. For compatibility, you can enable :ref:`CONFIG_ADC_CONTINUOUS_FORCE_USE_ADC2_ON_C3_S3` to force use ADC2. + +.. _adc-continuous-power-management: Power Management ^^^^^^^^^^^^^^^^ diff --git a/docs/en/api-reference/peripherals/adc_oneshot.rst b/docs/en/api-reference/peripherals/adc_oneshot.rst index c7dfec41d00..24fee32be51 100644 --- a/docs/en/api-reference/peripherals/adc_oneshot.rst +++ b/docs/en/api-reference/peripherals/adc_oneshot.rst @@ -3,20 +3,17 @@ Analog to Digital Converter (ADC) Oneshot Mode Driver :link_to_translation:`zh_CN:[中文]` -{IDF_TARGET_ADC_NUM:default="two", esp32c2="one", esp32c6="one", esp32h2="one", esp32c5="one"} - Introduction ------------ The Analog to Digital Converter is integrated on the chip and is capable of measuring analog signals from specific analog IO pins. -{IDF_TARGET_NAME} has {IDF_TARGET_ADC_NUM} ADC unit(s), which can be used in scenario(s) like: - -- Generate one-shot ADC conversion result +{IDF_TARGET_NAME} has {SOC_ADC_PERIPH_NUM} ADC unit(s), which can be used in scenario(s) like: -.. only:: SOC_ADC_DMA_SUPPORTED +.. list:: - - Generate continuous ADC conversion results + - Generate one-shot ADC conversion result + :SOC_ADC_DMA_SUPPORTED: - Generate continuous ADC conversion results This guide introduces ADC oneshot mode conversion. @@ -164,31 +161,16 @@ Read Raw Result Hardware Limitations ^^^^^^^^^^^^^^^^^^^^ -- Random Number Generator (RNG) uses ADC as an input source. When ADC :cpp:func:`adc_oneshot_read` works, the random number generated from RNG will be less random. - -.. only:: SOC_ADC_DMA_SUPPORTED - - - A specific ADC unit can only work under one operating mode at any one time, either continuous mode or oneshot mode. :cpp:func:`adc_oneshot_read` has provided the protection. - -.. only:: esp32 or esp32s2 or esp32s3 - - - ADC2 is also used by Wi-Fi. :cpp:func:`adc_oneshot_read` has provided protection between the Wi-Fi driver and ADC oneshot mode driver. - -.. only:: esp32c3 - - - ADC2 oneshot mode is no longer supported, due to hardware limitations. The results are not stable. This issue can be found in `ESP32-C3 Series SoC Errata `_. For compatibility, you can enable :ref:`CONFIG_ADC_ONESHOT_FORCE_USE_ADC2_ON_C3` to force use ADC2. - -.. only:: esp32 - - - ESP32-DevKitC: GPIO0 cannot be used in oneshot mode, because the DevKit has used it for auto-flash. - - - ESP-WROVER-KIT: GPIO 0, 2, 4, and 15 cannot be used due to external connections for different purposes. - - .. _adc-oneshot-power-management: +.. list:: -.. only:: not esp32 + - Random Number Generator (RNG) uses ADC as an input source. When ADC :cpp:func:`adc_oneshot_read` works, the random number generated from RNG will be less random. + :SOC_ADC_DMA_SUPPORTED: - A specific ADC unit can only work under one operating mode at any one time, either continuous mode or oneshot mode. :cpp:func:`adc_oneshot_read` has provided the protection. + :esp32 or esp32s2 or esp32s3: - ADC2 is also used by Wi-Fi. :cpp:func:`adc_oneshot_read` has provided protection between the Wi-Fi driver and ADC oneshot mode driver. + :esp32c3: - ADC2 oneshot mode is no longer supported, due to hardware limitations. The results are not stable. This issue can be found in `ESP32-C3 Series SoC Errata `_. For compatibility, you can enable :ref:`CONFIG_ADC_ONESHOT_FORCE_USE_ADC2_ON_C3` to force use ADC2. + :esp32: - ESP32-DevKitC: GPIO0 cannot be used in oneshot mode, because the DevKit has used it for auto-flash. + :esp32: - ESP-WROVER-KIT: GPIO 0, 2, 4, and 15 cannot be used due to external connections for different purposes. - .. _adc-oneshot-power-management: +.. _adc-oneshot-power-management: Power Management ^^^^^^^^^^^^^^^^ diff --git a/docs/zh_CN/api-reference/peripherals/adc_continuous.rst b/docs/zh_CN/api-reference/peripherals/adc_continuous.rst index e1f33caf556..5ebd83dabad 100644 --- a/docs/zh_CN/api-reference/peripherals/adc_continuous.rst +++ b/docs/zh_CN/api-reference/peripherals/adc_continuous.rst @@ -290,39 +290,19 @@ ADC 连续转换模式驱动使用内部缓冲池保存转换结果，缓冲池 硬件限制 ^^^^^^^^^^^^^^^^^^^^ -- 一个 ADC 单元一次只能运行一种操作模式，即连续模式或单次模式。:cpp:func:`adc_continuous_start` 提供了保护措施。 - -- 随机数生成器 (RNG) 以 ADC 为输入源。使用 ADC 连续转换模式驱动从 RNG 生成随机数时，随机性会减弱。 - -.. only:: esp32 or esp32s2 - - - Wi-Fi 也使用 ADC2，:cpp:func:`adc_continuous_start` 提供了 Wi-Fi 驱动和 ADC 连续转换模式驱动之间的保护。 - -.. only:: esp32 - - - ADC 连续转换模式驱动使用 I2S0 外设作为硬件 DMA FIFO。因此，如果 I2S0 已在使用中，:cpp:func:`adc_continuous_new_handle` 将返回 :c:macro:`ESP_ERR_NOT_FOUND`。 - - - ESP32 DevKitC：由于存在外部自动烧录电路，GPIO 0 不能用于 ADC 连续转换模式。 - - - ESP-WROVER-KIT：由于部分 GPIO 管脚可能已经用于其他目的，GPIO 0、2、4 和 15 不能用于 ADC 连续转换模式。 - -.. only:: esp32s2 - - - ADC 连续转换模式驱动使用 SPI3 外设作为硬件 DMA FIFO。因此，如果 SPI3 已在使用中，:cpp:func:`adc_continuous_new_handle` 将返回 :c:macro:`ESP_ERR_NOT_FOUND`。 - -.. only:: esp32c3 - - - 由于硬件限制，现已不再支持使用 ADC2 DMA 功能获取 ADC 转换结果。使用 ADC2 连续转换的结果可能不稳定，具体可参考 `ESP32-C3 系列芯片勘误表 `__。出于兼容性考虑，可以启用 :ref:`CONFIG_ADC_CONTINUOUS_FORCE_USE_ADC2_ON_C3_S3`，强制使用 ADC2。 - -.. only:: esp32s3 - - - 由于硬件限制，现已不再支持使用 ADC2 DMA 功能获取 ADC 转换结果。使用 ADC2 连续转换的结果可能不稳定，具体可参考 `ESP32-S3 系列芯片勘误表 `__。出于兼容性考虑，可以启用 :ref:`CONFIG_ADC_CONTINUOUS_FORCE_USE_ADC2_ON_C3_S3`，强制使用 ADC2。 - - .. _adc-continuous-power-management: - -.. only:: not esp32s3 - - .. _adc-continuous-power-management: +.. list:: + + - 一个 ADC 单元一次只能运行一种操作模式，即连续模式或单次模式。:cpp:func:`adc_continuous_start` 提供了保护措施。 + - 随机数生成器 (RNG) 以 ADC 为输入源。使用 ADC 连续转换模式驱动从 RNG 生成随机数时，随机性会减弱。 + :esp32 or esp32s2: - Wi-Fi 也使用 ADC2，:cpp:func:`adc_continuous_start` 提供了 Wi-Fi 驱动和 ADC 连续转换模式驱动之间的保护。 + :esp32: - ADC 连续转换模式驱动使用 I2S0 外设作为硬件 DMA FIFO。因此，如果 I2S0 已在使用中，:cpp:func:`adc_continuous_new_handle` 将返回 :c:macro:`ESP_ERR_NOT_FOUND`。 + :esp32: - ESP32 DevKitC：由于存在外部自动烧录电路，GPIO 0 不能用于 ADC 连续转换模式。 + :esp32: - ESP-WROVER-KIT：由于部分 GPIO 管脚可能已经用于其他目的，GPIO 0、2、4 和 15 不能用于 ADC 连续转换模式。 + :esp32s2: - ADC 连续转换模式驱动使用 SPI3 外设作为硬件 DMA FIFO。因此，如果 SPI3 已在使用中，:cpp:func:`adc_continuous_new_handle` 将返回 :c:macro:`ESP_ERR_NOT_FOUND`。 + :esp32c3: - 由于硬件限制，现已不再支持使用 ADC2 DMA 功能获取 ADC 转换结果。使用 ADC2 连续转换的结果可能不稳定，具体可参考 `ESP32-C3 系列芯片勘误表 `__。出于兼容性考虑，可以启用 :ref:`CONFIG_ADC_CONTINUOUS_FORCE_USE_ADC2_ON_C3_S3`，强制使用 ADC2。 + :esp32s3: - 由于硬件限制，现已不再支持使用 ADC2 DMA 功能获取 ADC 转换结果。使用 ADC2 连续转换的结果可能不稳定，具体可参考 `ESP32-S3 系列芯片勘误表 `__。出于兼容性考虑，可以启用 :ref:`CONFIG_ADC_CONTINUOUS_FORCE_USE_ADC2_ON_C3_S3`，强制使用 ADC2。 + +.. _adc-continuous-power-management: 电源管理 ^^^^^^^^^^^^^^^^ diff --git a/docs/zh_CN/api-reference/peripherals/adc_oneshot.rst b/docs/zh_CN/api-reference/peripherals/adc_oneshot.rst index 0f7a2bfbb03..8365bb49e99 100644 --- a/docs/zh_CN/api-reference/peripherals/adc_oneshot.rst +++ b/docs/zh_CN/api-reference/peripherals/adc_oneshot.rst @@ -3,20 +3,17 @@ :link_to_translation:`en:[English]` -{IDF_TARGET_ADC_NUM:default="两", esp32c2="一", esp32c6="一", esp32h2="一", esp32c5="一"} - 简介 ---- 模数转换器集成于芯片，支持测量特定模拟 IO 管脚的模拟信号。 -{IDF_TARGET_NAME} 有 {IDF_TARGET_ADC_NUM} 个 ADC 单元，可以在以下场景使用： - -- 生成 ADC 单次转换结果 +{IDF_TARGET_NAME} 有 {SOC_ADC_PERIPH_NUM} 个 ADC 单元，可以在以下场景使用： -.. only:: SOC_ADC_DMA_SUPPORTED +.. list:: - - 生成连续 ADC 转换结果 + - 生成 ADC 单次转换结果 + :SOC_ADC_DMA_SUPPORTED: - 生成连续 ADC 转换结果 本指南介绍了 ADC 单次转换模式。 @@ -164,31 +161,16 @@ ADC 单次转换模式驱动基于 {IDF_TARGET_NAME} SAR ADC 模块实现，不 硬件限制 ^^^^^^^^^^^^^^^^^^^^ -- 随机数生成器 (RNG) 以 ADC 为输入源。使用 ADC 单次转换模式驱动从 RNG 生成随机数时，随机性会减弱。 - -.. only:: SOC_ADC_DMA_SUPPORTED - - - 一个 ADC 单元每次只能在一种操作模式下运行，可以是连续模式或单次模式。:cpp:func:`adc_oneshot_start` 提供了保护措施。 - -.. only:: esp32 or esp32s2 or esp32s3 - - - Wi-Fi 也使用 ADC2，:cpp:func:`adc_oneshot_read` 提供了 Wi-Fi 驱动与 ADC 单次转换模式驱动间的保护。 - -.. only:: esp32c3 - - - 由于硬件限制，现已不再支持使用 ADC2 DMA 功能获取 ADC 转换结果。使用 ADC2 单次转换的结果可能不稳定，具体可参考 `ESP32-C3 系列芯片勘误表 `__。出于兼容性考虑，可以启用 :ref:`CONFIG_ADC_ONESHOT_FORCE_USE_ADC2_ON_C3`，强制使用 ADC2。 - -.. only:: esp32 - - - ESP32-DevKitC：GPIO0 已用于自动烧录功能，不能用于 ADC 单次转换模式。 - - - ESP-WROVER-KIT：GPIO0、GPIO2、GPIO4 和 GPIO15 已有其他用途，不能用于 ADC 单次转换模式。 - - .. _adc-oneshot-power-management: +.. list:: -.. only:: not esp32 + - 随机数生成器 (RNG) 以 ADC 为输入源。使用 ADC 单次转换模式驱动从 RNG 生成随机数时，随机性会减弱。 + :SOC_ADC_DMA_SUPPORTED: - 一个 ADC 单元每次只能在一种操作模式下运行，可以是连续模式或单次模式。:cpp:func:`adc_oneshot_start` 提供了保护措施。 + :esp32 or esp32s2 or esp32s3: - Wi-Fi 也使用 ADC2，:cpp:func:`adc_oneshot_read` 提供了 Wi-Fi 驱动与 ADC 单次转换模式驱动间的保护。 + :esp32c3: - 由于硬件限制，现已不再支持使用 ADC2 DMA 功能获取 ADC 转换结果。使用 ADC2 单次转换的结果可能不稳定，具体可参考 `ESP32-C3 系列芯片勘误表 `__。出于兼容性考虑，可以启用 :ref:`CONFIG_ADC_ONESHOT_FORCE_USE_ADC2_ON_C3`，强制使用 ADC2。 + :esp32: - ESP32-DevKitC：GPIO0 已用于自动烧录功能，不能用于 ADC 单次转换模式。 + :esp32: - ESP-WROVER-KIT：GPIO0、GPIO2、GPIO4 和 GPIO15 已有其他用途，不能用于 ADC 单次转换模式。 - .. _adc-oneshot-power-management: +.. _adc-oneshot-power-management: 电源管理 ^^^^^^^^ From ff83d87bcebdf2fbe23491f18f646bd20c2aedd5 Mon Sep 17 00:00:00 2001 From: xiongweichao Date: Wed, 28 Aug 2024 10:35:22 +0800 Subject: [PATCH 007/472] feat(ble): Support using 32k oscillator as Bluetooth sleep clock --- components/bt/controller/esp32/Kconfig.in | 6 +++--- components/bt/controller/esp32c3/Kconfig.in | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/components/bt/controller/esp32/Kconfig.in b/components/bt/controller/esp32/Kconfig.in index 191738d0d22..a1bc0270bd3 100644 --- a/components/bt/controller/esp32/Kconfig.in +++ b/components/bt/controller/esp32/Kconfig.in @@ -300,10 +300,10 @@ menu "MODEM SLEEP Options" the bluetooth low power clock source. config BTDM_CTRL_LPCLK_SEL_EXT_32K_XTAL - bool "External 32kHz crystal" - depends on RTC_CLK_SRC_EXT_CRYS + bool "External 32kHz crystal/oscillator" + depends on RTC_CLK_SRC_EXT_CRYS || RTC_CLK_SRC_EXT_OSC help - External 32kHz crystal has a nominal frequency of 32.768kHz and provides good frequency + External 32kHz crystal/oscillator has a nominal frequency of 32.768kHz and provides good frequency stability. If used as Bluetooth low power clock, External 32kHz can support Bluetooth modem sleep to be used with both DFS and light sleep. endchoice diff --git a/components/bt/controller/esp32c3/Kconfig.in b/components/bt/controller/esp32c3/Kconfig.in index 5178ef86021..77173951533 100644 --- a/components/bt/controller/esp32c3/Kconfig.in +++ b/components/bt/controller/esp32c3/Kconfig.in @@ -402,10 +402,10 @@ menu "MODEM SLEEP Options" bluetooth can work under light sleep enabled. Main crystal has a relatively better performance than other bluetooth low power clock sources. config BT_CTRL_LPCLK_SEL_EXT_32K_XTAL - bool "External 32kHz crystal" - depends on RTC_CLK_SRC_EXT_CRYS + bool "External 32kHz crystal/oscillator" + depends on RTC_CLK_SRC_EXT_CRYS || RTC_CLK_SRC_EXT_OSC help - External 32kHz crystal has a nominal frequency of 32.768kHz and provides good frequency + External 32kHz crystal/oscillator has a nominal frequency of 32.768kHz and provides good frequency stability. If used as Bluetooth low power clock, External 32kHz can support Bluetooth modem sleep to be used with both DFS and light sleep. From 31dc7b6f07a2063c9b74bebcc0eea82eb135274b Mon Sep 17 00:00:00 2001 From: Peter Dragun Date: Tue, 3 Sep 2024 14:58:51 +0200 Subject: [PATCH 008/472] docs: Move monitor configuration documentation to its own repository --- docs/en/api-guides/tools/idf-monitor.rst | 166 +------------------ docs/zh_CN/api-guides/tools/idf-monitor.rst | 168 +------------------- 2 files changed, 9 insertions(+), 325 deletions(-) diff --git a/docs/en/api-guides/tools/idf-monitor.rst b/docs/en/api-guides/tools/idf-monitor.rst index 5c4408209de..9505a76210d 100644 --- a/docs/en/api-guides/tools/idf-monitor.rst +++ b/docs/en/api-guides/tools/idf-monitor.rst @@ -252,63 +252,7 @@ Custom Reset Sequence For more advanced users or specific use cases, IDF Monitor supports the configuration of a custom reset sequence using :ref:`configuration-file`. This is particularly useful in extreme edge cases where the default sequence may not suffice. -The sequence is defined with a string in the following format: - -- Consists of individual commands divided by ``|`` (e.g. ``R0|D1|W0.5``). -- Commands (e.g. ``R0``) are defined by a code (``R``) and an argument (``0``). - -.. list-table:: - :header-rows: 1 - :widths: 15 50 35 - :align: center - - * - Code - - Action - - Argument - * - D - - Set DTR control line - - ``1``/``0`` - * - R - - Set RTS control line - - ``1``/``0`` - * - U - - Set DTR and RTS control lines at the same time (Unix-like systems only) - - ``0,0``/``0,1``/``1,0``/``1,1`` - * - W - - Wait for ``N`` seconds (where ``N`` is a float) - - N - -Example: - -.. code-block:: ini - - [esp-idf-monitor] - custom_reset_sequence = U0,1|W0.1|D1|R0|W0.5|D0 - -Refer to `custom reset sequence`_ from Esptool documentation for further details. Please note that ``custom_reset_sequence`` is the only used value from the Esptool configuration, and others will be ignored in IDF Monitor. - -Share Configuration Across Tools --------------------------------- - -The configuration for the custom reset sequence can be specified in a shared configuration file between IDF Monitor and Esptool. In this case, your configuration file name should be either ``setup.cfg`` or ``tox.ini`` so it would be recognized by both tools. - -Example of a shared configuration file: - -.. code-block:: ini - - [esp-idf-monitor] - menu_key = T - skip_menu_key = True - - [esptool] - custom_reset_sequence = U0,1|W0.1|D1|R0|W0.5|D0 - -.. note:: - - When using the ``custom_reset_sequence`` parameter in both the ``[esp-idf-monitor]`` section and the ``[esptool]`` section, the configuration from the ``[esp-idf-monitor]`` section will take precedence in IDF Monitor. Any conflicting configuration in the ``[esptool]`` section will be ignored. - - This precedence rule also applies when the configuration is spread across multiple files. The global esp-idf-monitor configuration will take precedence over the local esptool configuration. - +If you would like to use a custom reset sequence, take a look at the `IDF Monitor documentation`_ for more details. Launching GDB with GDBStub ~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -397,107 +341,9 @@ The options ``--print_filter="light_driver:D esp_image:N boot:N cpu_start:N vfs: Configuration File ================== -``esp-idf-monitor`` is using `C0 control codes`_ to interact with the console. Characters from the config file are converted to their C0 control codes. Available characters include the English alphabet (A-Z) and special symbols: ``[``, ``]``, ``\``, ``^``, ``_``. - -.. warning:: +``esp-idf-monitor`` offers option to change its default behavior with configuration file. This file can be used for example to set custom key bindings, or set a custom reset sequence for resetting the chip into bootloader mode. - Please note that some characters may not work on all platforms or can be already reserved as a shortcut for something else. Use this feature with caution! - - -File Location -~~~~~~~~~~~~~ - -The default name for a configuration file is ``esp-idf-monitor.cfg``. First, the same directory ``esp-idf-monitor`` is being run if is inspected. - -If a configuration file is not found here, the current user's OS configuration directory is inspected next: - - - Linux: ``/home//.config/esp-idf-monitor/`` - - MacOS ``/Users//.config/esp-idf-monitor/`` - - Windows: ``c:\Users\\AppData\Local\esp-idf-monitor\`` - -If a configuration file is still not found, the last inspected location is the home directory: - - - Linux: ``/home//`` - - MacOS ``/Users//`` - - Windows: ``c:\Users\\`` - -On Windows, the home directory can be set with the ``HOME`` or ``USERPROFILE`` environment variables. Therefore, the Windows configuration directory location also depends on these. - -A different location for the configuration file can be specified with the ``ESP_IDF_MONITOR_CFGFILE`` environment variable, e.g., ``ESP_IDF_MONITOR_CFGFILE = ~/custom_config.cfg``. This overrides the search priorities described above. - -``esp-idf-monitor`` will read settings from other usual configuration files if no other configuration file is used. It automatically reads from ``setup.cfg`` or ``tox.ini`` if they exist. - -Configuration Options -~~~~~~~~~~~~~~~~~~~~~ - -Below is a table listing the available configuration options: - -.. list-table:: - :header-rows: 1 - :widths: 30 50 20 - :align: center - - * - Option Name - - Description - - Default Value - * - menu_key - - Key to access the main menu. - - ``T`` - * - exit_key - - Key to exit the monitor. - - ``]`` - * - chip_reset_key - - Key to initiate a chip reset. - - ``R`` - * - recompile_upload_key - - Key to recompile and upload. - - ``F`` - * - recompile_upload_app_key - - Key to recompile and upload just the application. - - ``A`` - * - toggle_output_key - - Key to toggle the output display. - - ``Y`` - * - toggle_log_key - - Key to toggle the logging feature. - - ``L`` - * - toggle_timestamp_key - - Key to toggle timestamp display. - - ``I`` - * - chip_reset_bootloader_key - - Key to reset the chip to bootloader mode. - - ``P`` - * - exit_menu_key - - Key to exit the monitor from the menu. - - ``X`` - * - skip_menu_key - - Pressing the menu key can be skipped for menu commands. - - ``False`` - * - custom_reset_sequence - - Custom reset sequence for resetting into the bootloader. - - N/A - - -Syntax -~~~~~~ - -The configuration file is in .ini file format: it must be introduced by an ``[esp-idf-monitor]`` header to be recognized as valid. This section then contains name = value entries. Lines beginning with ``#`` or ``;`` are ignored as comments. - -.. code-block:: ini - - # esp-idf-monitor.cfg file to configure internal settings of esp-idf-monitor - [esp-idf-monitor] - menu_key = T - exit_key = ] - chip_reset_key = R - recompile_upload_key = F - recompile_upload_app_key = A - toggle_output_key = Y - toggle_log_key = L - toggle_timestamp_key = I - chip_reset_bootloader_key = P - exit_menu_key = X - skip_menu_key = False +For more details on the configuration file, see the `IDF Monitor documentation`_. Known Issues with IDF Monitor @@ -505,10 +351,6 @@ Known Issues with IDF Monitor If you encounter any issues while using IDF Monitor, check our `GitHub repository `_ for a list of known issues and their current status. If you come across a problem that hasn't been documented yet, we encourage you to create a new issue report. -.. _addr2line: https://sourceware.org/binutils/docs/binutils/addr2line.html .. _esp-idf-monitor: https://github.com/espressif/esp-idf-monitor +.. _IDF Monitor documentation: https://github.com/espressif/esp-idf-monitor/blob/v1.5.0/README.md#documentation .. _gdb: https://sourceware.org/gdb/download/onlinedocs/ -.. _pySerial: https://github.com/pyserial/pyserial -.. _miniterm: https://pyserial.readthedocs.org/en/latest/tools.html#module-serial.tools.miniterm -.. _C0 control codes: https://en.wikipedia.org/wiki/C0_and_C1_control_codes#C0_controls -.. _custom reset sequence: https://docs.espressif.com/projects/esptool/en/latest/{IDF_TARGET_PATH_NAME}/esptool/configuration-file.html#custom-reset-sequence diff --git a/docs/zh_CN/api-guides/tools/idf-monitor.rst b/docs/zh_CN/api-guides/tools/idf-monitor.rst index 7e38c5a187c..8c186f6539f 100644 --- a/docs/zh_CN/api-guides/tools/idf-monitor.rst +++ b/docs/zh_CN/api-guides/tools/idf-monitor.rst @@ -252,63 +252,7 @@ IDF 监视器的默认复位序列可在大多数环境中使用。使用默认 对于高级用户或特定用例，IDF 监视器支持使用 :ref:`configuration-file` 配置自定义复位序列。这在默认序列可能不足的极端情况下特别有用。 -复位序列可通过以下格式的字符串定义： - -- 各个命令由 ``|`` 分隔（例如 ``R0|D1|W0.5``）。 -- 命令（例如 ``R0``）由代码（``R``）和参数（``0``）定义。 - -.. list-table:: - :header-rows: 1 - :widths: 15 50 35 - :align: center - - * - 代码 - - 操作 - - 参数 - * - D - - 设置 DTR 控制线 - - ``1``/``0`` - * - R - - 设置 RTS 控制线 - - ``1``/``0`` - * - U - - 同时设置 DTR 和 RTS 控制线（仅适用于类 Unix 系统） - - ``0,0``/``0,1``/``1,0``/``1,1`` - * - W - - 等待 ``N`` 秒（其中 ``N`` 为浮点数） - - N - -示例： - -.. code-block:: ini - - [esp-idf-monitor] - custom_reset_sequence = U0,1|W0.1|D1|R0|W0.5|D0 - -有关更多详细信息，请参阅 Esptool 文档中 `custom reset sequence`_ 章节。请注意，IDF 监视器只使用了 Esptool 配置中的 ``custom_reset_sequence`` 值，其他值会被 IDF 监视器忽略。 - -IDF 监视器和 Esptool 之间共享配置 ----------------------------------------------- - -自定义复位序列的配置可以在 IDF 监视器和 Esptool 之间的共享配置文件中指定。在这种情况下，为了使两个工具都能识别配置文件，其名称应为 ``setup.cfg`` 或 ``tox.ini``。 - -共享配置文件的示例： - -.. code-block:: ini - - [esp-idf-monitor] - menu_key = T - skip_menu_key = True - - [esptool] - custom_reset_sequence = U0,1|W0.1|D1|R0|W0.5|D0 - -.. note:: - - 当在 ``[esp-idf-monitor]`` 部分和 ``[esptool]`` 部分都使用 ``custom_reset_sequence`` 参数时，IDF 监视器会优先使用 ``[esp-idf-monitor]`` 部分的配置。``[esptool]`` 部分中任何与之冲突的配置都将被忽略。 - - 当配置分散在多个文件中时，此优先规则也适用。全局 esp-idf-monitor 配置将优先于本地 esptool 配置。 - +如需使用自定义复位序列，请参阅 `IDF 监视器文档`_ 获取更多详细信息。 配置 GDBStub 以启用 GDB ~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -397,118 +341,16 @@ GDBStub 支持在运行时进行调试。GDBStub 在目标上运行，并通过 配置文件 ======== -``esp-idf-monitor`` 使用 `C0 控制字符`_ 与控制台进行交互。配置文件中的字符会被转换为对应的 C0 控制代码。可用字符包括英文字母 (A-Z) 和特殊符号：``[``、``]``、``\``、``^``、和 ``_``. - -.. warning:: - - 注意，一些字符可能无法在所有平台通用，或被保留作为其他用途的快捷键。请谨慎使用此功能。 - - -文件位置 -~~~~~~~~~~ - -配置文件的默认名称为 ``esp-idf-monitor.cfg``。首先，在 ``esp-idf-monitor`` 路径中检测配置文件并运行。 - -如果此目录中没有检测到配置文件，则检查当前用户操作系统的配置目录： - - - Linux: ``/home//.config/esp-idf-monitor/`` - - MacOS ``/Users//.config/esp-idf-monitor/`` - - Windows: ``c:\Users\\AppData\Local\esp-idf-monitor\`` +``esp-idf-monitor`` 支持通过配置文件更改其默认行为。该配置文件可用于设置自定义快捷键，或设置自定义复位序列以重置芯片进入引导加载程序。 -如仍未检测到配置文件，会最后再检查主目录： - - - Linux: ``/home//`` - - MacOS ``/Users//`` - - Windows: ``c:\Users\\`` - -在 Windows 中，可以使用 ``HOME`` 或 ``USERPROFILE`` 环境变量设置主目录，因此，Windows 配置目录的位置也取决于这些变量。 - -还可以使用 ``ESP_IDF_MONITOR_CFGFILE`` 环境变量为配置文件指定一个不同的位置，例如 ``ESP_IDF_MONITOR_CFGFILE = ~/custom_config.cfg``。这一设置的检测优先级高于上述所有位置检测的优先级。 - -如果没有使用其他配置文件，``esp-idf-monitor`` 会从其他常用的配置文件中读取设置。如果存在 ``setup.cfg`` 或 ``tox.ini`` 文件，``esp-idf-monitor`` 会自动从这些文件中读取设置。 - -配置选项 -~~~~~~~~~~ - -下表列出了可用的配置选项： - -.. list-table:: - :header-rows: 1 - :widths: 30 50 20 - :align: center - - * - 选项名称 - - 描述 - - 默认值 - * - menu_key - - 访问主菜单 - - ``T`` - * - exit_key - - 退出监视器 - - ``]`` - * - chip_reset_key - - 初始化芯片重置 - - ``R`` - * - recompile_upload_key - - 重新编译并上传 - - ``F`` - * - recompile_upload_app_key - - 仅重新编译并上传应用程序 - - ``A`` - * - toggle_output_key - - 切换输出显示 - - ``Y`` - * - toggle_log_key - - 切换日志功能 - - ``L`` - * - toggle_timestamp_key - - 切换时间戳显示 - - ``I`` - * - chip_reset_bootloader_key - - 将芯片重置为引导加载模式 - - ``P`` - * - exit_menu_key - - 从菜单中退出监视器 - - ``X`` - * - skip_menu_key - - 设置使用菜单命令时无需按下主菜单键 - - ``False`` - * - custom_reset_sequence - - 复位目标到引导加载程序的自定义复位序列 - - 无默认值 - - -语法 -~~~~ - -配置文件为 .ini 文件格式，必须以 ``[esp-idf-monitor]`` 标头引入才能被识别为有效文件。以下语法以“配置名称 = 配置值”形式列出。以 ``#`` 或 ``;`` 开头的行是注释，将被忽略。 - -.. code-block:: ini - - # esp-idf-monitor.cfg file to configure internal settings of esp-idf-monitor - [esp-idf-monitor] - menu_key = T - exit_key = ] - chip_reset_key = R - recompile_upload_key = F - recompile_upload_app_key = A - toggle_output_key = Y - toggle_log_key = L - toggle_timestamp_key = I - chip_reset_bootloader_key = P - exit_menu_key = X - skip_menu_key = False +有关配置文件的更多详细信息，请参阅 `IDF 监视器文档`_。 IDF 监视器已知问题 ================================= -如果在使用 IDF 监视器过程中遇到任何问题，请查看我们的 `GitHub 仓库 `_ 以获取已知问题列表及其当前状态。如果遇到的问题没有相关记录，请创建一个新的问题报告。 +如果在使用 IDF 监视器过程中遇到任何问题，请查看 `GitHub 仓库 `_ 以获取已知问题列表及其当前状态。如果遇到的问题没有相关记录，请创建一个新的问题报告。 -.. _addr2line: https://sourceware.org/binutils/docs/binutils/addr2line.html .. _esp-idf-monitor: https://github.com/espressif/esp-idf-monitor +.. _IDF 监视器文档: https://github.com/espressif/esp-idf-monitor/blob/v1.5.0/README.md#documentation .. _gdb: https://sourceware.org/gdb/download/onlinedocs/ -.. _pySerial: https://github.com/pyserial/pyserial -.. _miniterm: https://pyserial.readthedocs.org/en/latest/tools.html#module-serial.tools.miniterm -.. _C0 控制字符: https://zh.wikipedia.org/wiki/C0%E4%B8%8EC1%E6%8E%A7%E5%88%B6%E5%AD%97%E7%AC%A6#C0_(ASCII%E5%8F%8A%E5%85%B6%E6%B4%BE%E7%94%9F) -.. _custom reset sequence: https://docs.espressif.com/projects/esptool/en/latest/{IDF_TARGET_PATH_NAME}/esptool/configuration-file.html#custom-reset-sequence From 2a02d45bdee9a5d1f089af733d3fae095110b297 Mon Sep 17 00:00:00 2001 From: Alexey Lapshin Date: Fri, 23 Aug 2024 16:57:42 +0700 Subject: [PATCH 009/472] fix(cxx): fix TLS classes destructor call Closes https://github.com/espressif/esp-idf/issues/14360 --- CMakeLists.txt | 4 ++- components/cxx/cxx_guards.cpp | 8 ++++- .../general/main/test_cxx_general.cpp | 33 ++++++++++++++++++- 3 files changed, 42 insertions(+), 3 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 20ef5b96896..b4dbce1bc23 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -251,7 +251,9 @@ if(CMAKE_C_COMPILER_ID MATCHES "GNU") endif() if(CMAKE_C_COMPILER_ID MATCHES "Clang") - list(APPEND compile_options "-fno-use-cxa-atexit") + list(APPEND compile_options "-fno-use-cxa-atexit") # TODO IDF-10934 +else() + list(APPEND cxx_compile_options "-fuse-cxa-atexit") endif() if(COMPILER_RT_LIB_NAME) diff --git a/components/cxx/cxx_guards.cpp b/components/cxx/cxx_guards.cpp index 0a76173769e..e4f9f905a66 100644 --- a/components/cxx/cxx_guards.cpp +++ b/components/cxx/cxx_guards.cpp @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -210,6 +210,12 @@ extern "C" void __cxa_guard_abort(__guard* pg) throw() } } +/* Originally, this should come with crtbegin.o from the toolchain (if GCC is configured with --enable-__cxa_atexit). + Since we do not link with crtbegin.o and have not configured GCC with --enable-__cxa_atexit, it is declared here. + Note: It should have a unique value in every shared object; in the main program its value is zero. */ +extern "C" void *__dso_handle __attribute__((__visibility__("hidden"))); +void *__dso_handle = 0; + /** * Dummy function used to force linking this file instead of the same one in libstdc++. * This works via -u __cxa_guard_dummy flag in component.mk diff --git a/components/cxx/test_apps/general/main/test_cxx_general.cpp b/components/cxx/test_apps/general/main/test_cxx_general.cpp index 0e483ab655a..858b16bc16a 100644 --- a/components/cxx/test_apps/general/main/test_cxx_general.cpp +++ b/components/cxx/test_apps/general/main/test_cxx_general.cpp @@ -197,7 +197,7 @@ struct PriorityInitTest { int PriorityInitTest::order = 0; -// init_priority objects are initialized from the lowest to the heighest priority number +// init_priority objects are initialized from the lowest to the highest priority number // Default init_priority is always the lowest (highest priority number) PriorityInitTest g_static_init_priority_test2; PriorityInitTest g_static_init_priority_test1 __attribute__((init_priority(1000))); @@ -243,6 +243,36 @@ TEST_CASE("can use std::vector", "[misc]") TEST_ASSERT_EQUAL(51, std::accumulate(std::begin(v), std::end(v), 0)); } +static volatile bool is_tls_class_destructor_called; +struct TestTLS { + TestTLS() { } + ~TestTLS() + { + is_tls_class_destructor_called = true; + } + void foo() { } +}; + +thread_local TestTLS s_testTLS; + +void test_thread_local_destructors(void * arg) +{ + s_testTLS.foo(); + xSemaphoreGive(s_slow_init_sem); + vTaskDelete(NULL); +} + +TEST_CASE("call destructors for thread_local classes CXX", "[misc]") +{ + is_tls_class_destructor_called = false; + s_slow_init_sem = xSemaphoreCreateCounting(1, 0); + xTaskCreate(test_thread_local_destructors, "test_thread_local_destructors", 2048, NULL, 10, NULL); + vTaskDelay(1); /* Triggers IDLE task to call prvCheckTasksWaitingTermination() which cleans task-specific data */ + TEST_ASSERT_TRUE(xSemaphoreTake(s_slow_init_sem, 500 / portTICK_PERIOD_MS)); + vSemaphoreDelete(s_slow_init_sem); + TEST_ASSERT_TRUE(is_tls_class_destructor_called); +} + /* These test cases pull a lot of code from libstdc++ and are disabled for now */ #if 0 @@ -291,6 +321,7 @@ TEST_CASE("stack smashing protection CXX", "[stack_smash]") extern "C" void app_main(void) { + s_testTLS.foo(); /* allocates memory that will be reused */ printf("CXX GENERAL TEST\n"); unity_run_menu(); } From 69f74c34a262485490cced31dc0875ceb7d2a81b Mon Sep 17 00:00:00 2001 From: Ivan Grokhotkov Date: Wed, 25 Sep 2024 12:50:23 +0200 Subject: [PATCH 010/472] fix(examples): remove stray EXTRA_COMPONENT_DIRS, fix check --- examples/storage/sd_card/sdspi/CMakeLists.txt | 1 - examples/storage/sd_card/sdspi/main/idf_component.yml | 3 +++ tools/ci/check_examples_extra_component_dirs.sh | 2 +- 3 files changed, 4 insertions(+), 2 deletions(-) create mode 100644 examples/storage/sd_card/sdspi/main/idf_component.yml diff --git a/examples/storage/sd_card/sdspi/CMakeLists.txt b/examples/storage/sd_card/sdspi/CMakeLists.txt index d41a683007d..e140d486250 100644 --- a/examples/storage/sd_card/sdspi/CMakeLists.txt +++ b/examples/storage/sd_card/sdspi/CMakeLists.txt @@ -2,7 +2,6 @@ # in this exact order for cmake to work correctly cmake_minimum_required(VERSION 3.16) -list(APPEND EXTRA_COMPONENT_DIRS "$ENV{IDF_PATH}/examples/storage/sd_card/sdmmc/components/sd_card") set(COMPONENTS main) include($ENV{IDF_PATH}/tools/cmake/project.cmake) diff --git a/examples/storage/sd_card/sdspi/main/idf_component.yml b/examples/storage/sd_card/sdspi/main/idf_component.yml new file mode 100644 index 00000000000..b755a62b147 --- /dev/null +++ b/examples/storage/sd_card/sdspi/main/idf_component.yml @@ -0,0 +1,3 @@ +dependencies: + sd_card: + path: ${IDF_PATH}/examples/storage/sd_card/sdmmc/components/sd_card diff --git a/tools/ci/check_examples_extra_component_dirs.sh b/tools/ci/check_examples_extra_component_dirs.sh index 207efff7f4d..ac71e5975a5 100755 --- a/tools/ci/check_examples_extra_component_dirs.sh +++ b/tools/ci/check_examples_extra_component_dirs.sh @@ -5,7 +5,7 @@ set -uo pipefail # Examples shouldn't use EXTRA_COMPONENT_DIRS, instead the dependencies should be specified in idf_component.yml files output=$(find ${IDF_PATH}/examples -name "CMakeLists.txt" -not -path "**/managed_components/**" -not -path "**/build/**") -files=$(egrep "set\(EXTRA_COMPONENT_DIRS" ${output} | cut -d ":" -f 1) +files=$(egrep "EXTRA_COMPONENT_DIRS" ${output} | cut -d ":" -f 1) found_issues=0 for file in ${files} do From f4eec4da48502ce725d6e74f5b5d9c8237aa7abf Mon Sep 17 00:00:00 2001 From: Erhan Kurubas Date: Sun, 9 Jun 2024 16:16:24 +0200 Subject: [PATCH 011/472] feat(esp_system): preload openocd stub binaries and reserve memory for debugging --- components/esp_system/CMakeLists.txt | 4 ++ components/esp_system/Kconfig | 13 ++++++ .../esp_system/ld/esp32c6/sections.ld.in | 15 +++++++ .../esp_system/ld/esp32h2/sections.ld.in | 15 +++++++ .../openocd_stub_bins/CMakeLists.txt | 43 +++++++++++++++++++ .../esp_riscv_stub_tramp.inc | 1 + .../openocd_stub_bins/openocd_stub_flasher.c | 33 ++++++++++++++ .../esp32c6/include/soc/Kconfig.soc_caps.in | 4 ++ components/soc/esp32c6/include/soc/soc_caps.h | 3 ++ .../esp32h2/include/soc/Kconfig.soc_caps.in | 4 ++ components/soc/esp32h2/include/soc/soc_caps.h | 3 ++ docs/en/api-guides/performance/ram-usage.rst | 3 +- .../api-guides/performance/ram-usage.rst | 1 + tools/ci/astyle-rules.yml | 4 ++ 14 files changed, 145 insertions(+), 1 deletion(-) create mode 100644 components/esp_system/openocd_stub_bins/CMakeLists.txt create mode 100644 components/esp_system/openocd_stub_bins/esp_riscv_stub_tramp.inc create mode 100644 components/esp_system/openocd_stub_bins/openocd_stub_flasher.c diff --git a/components/esp_system/CMakeLists.txt b/components/esp_system/CMakeLists.txt index d2f97850ece..1443e619d4b 100644 --- a/components/esp_system/CMakeLists.txt +++ b/components/esp_system/CMakeLists.txt @@ -147,3 +147,7 @@ endif() if(CONFIG_SOC_MEM_NON_CONTIGUOUS_SRAM) target_link_options(${COMPONENT_LIB} INTERFACE "-Wl,--enable-non-contiguous-regions") endif() + +if(CONFIG_ESP_DEBUG_INCLUDE_OCD_STUB_BINS) + add_subdirectory(openocd_stub_bins) +endif() diff --git a/components/esp_system/Kconfig b/components/esp_system/Kconfig index e597eac88fa..98a266a7001 100644 --- a/components/esp_system/Kconfig +++ b/components/esp_system/Kconfig @@ -542,6 +542,19 @@ menu "ESP System Settings" Debug stubs are used by OpenOCD to execute pre-compiled onboard code which does some useful debugging stuff, e.g. GCOV data dump. + config ESP_DEBUG_INCLUDE_OCD_STUB_BINS + bool "Preload OpenOCD stub binaries to speed up debugging. 8K memory will be reserved" + default y + depends on SOC_DEBUG_HAVE_OCD_STUB_BINS + help + OpenOCD uses stub code to access flash during programming or when inserting and removing + SW flash breakpoints. + To execute stub code, OpenOCD allocates memory on the target device, backs up the existing memory, + loads the stub binary, runs the binary, and then restores the original memory. + This process can be time-consuming, especially when using USB serial JTAG. + By enabling this option, 8K of memory in RAM will be preallocated with the stub code, + eliminating the need to back up and restore the memory region. + config ESP_DEBUG_OCDAWARE bool "Make exception and panic handlers JTAG/OCD aware" default y diff --git a/components/esp_system/ld/esp32c6/sections.ld.in b/components/esp_system/ld/esp32c6/sections.ld.in index 98b23613d32..da8a695be4a 100644 --- a/components/esp_system/ld/esp32c6/sections.ld.in +++ b/components/esp_system/ld/esp32c6/sections.ld.in @@ -156,6 +156,21 @@ SECTIONS .iram0.text : { _iram_start = ABSOLUTE(.); + +#if CONFIG_ESP_DEBUG_INCLUDE_OCD_STUB_BINS + /* Do not move this block! OpenOCD expects this to be at the beginning of IRAM. */ + KEEP(*(.ocd_stub.code)); + KEEP(*(.ocd_stub.tramp)); + . = ALIGN(0x800); + KEEP(*(.ocd_stub.data)); + KEEP(*(.ocd_stub.bss)); + KEEP(*(.ocd_stub.stack)); + KEEP(*(.ocd_stub.params)); + . = ALIGN(0x1000); + KEEP(*(.ocd_stub.scratchmem)); + ASSERT(ABSOLUTE(.) == _iram_start + 0x2000, "openocd stub memory must be ended at _iram_start + 0x2000"); +#endif + /* Vectors go to start of IRAM */ ASSERT(ABSOLUTE(.) % 0x100 == 0, "vector address must be 256 byte aligned"); KEEP(*(.exception_vectors_table.text)); diff --git a/components/esp_system/ld/esp32h2/sections.ld.in b/components/esp_system/ld/esp32h2/sections.ld.in index 5ffe1de81d6..5fb84f6b3b0 100644 --- a/components/esp_system/ld/esp32h2/sections.ld.in +++ b/components/esp_system/ld/esp32h2/sections.ld.in @@ -156,6 +156,21 @@ SECTIONS .iram0.text : { _iram_start = ABSOLUTE(.); + +#if CONFIG_ESP_DEBUG_INCLUDE_OCD_STUB_BINS + /* Do not move this block! OpenOCD expects this to be at the beginning of IRAM. */ + KEEP(*(.ocd_stub.code)); + KEEP(*(.ocd_stub.tramp)); + . = ALIGN(0x800); + KEEP(*(.ocd_stub.data)); + KEEP(*(.ocd_stub.bss)); + KEEP(*(.ocd_stub.stack)); + KEEP(*(.ocd_stub.params)); + . = ALIGN(0x1000); + KEEP(*(.ocd_stub.scratchmem)); + ASSERT(ABSOLUTE(.) == _iram_start + 0x2000, "openocd stub memory must be ended at _iram_start + 0x2000"); +#endif + /* Vectors go to start of IRAM */ ASSERT(ABSOLUTE(.) % 0x100 == 0, "vector address must be 256 byte aligned"); KEEP(*(.exception_vectors_table.text)); diff --git a/components/esp_system/openocd_stub_bins/CMakeLists.txt b/components/esp_system/openocd_stub_bins/CMakeLists.txt new file mode 100644 index 00000000000..175fe71c997 --- /dev/null +++ b/components/esp_system/openocd_stub_bins/CMakeLists.txt @@ -0,0 +1,43 @@ +idf_build_get_property(target IDF_TARGET) + +# Function to add custom commands for copying stub files +function(add_copy_command src dest) + add_custom_command( + OUTPUT ${dest} + COMMAND ${CMAKE_COMMAND} -E copy_if_different ${src} ${dest} + DEPENDS ${src} + COMMENT "Copying ${src} to ${dest}" + VERBATIM + ) +endfunction() + +set(openocd_path $ENV{OPENOCD_SCRIPTS}) + +if(openocd_path) + set(stub_bin_path ${openocd_path}/../espressif/stub_bins) + if(IS_DIRECTORY ${stub_bin_path} AND IS_DIRECTORY ${stub_bin_path}/${target}) + set(code_bin "${stub_bin_path}/${target}/stub_flash_idf_binary_code.inc") + set(data_bin "${stub_bin_path}/${target}/stub_flash_idf_binary_data.inc") + set(img_header "${stub_bin_path}/${target}/stub_flash_idf_image.h") + if(EXISTS ${code_bin} AND EXISTS ${data_bin} AND EXISTS ${img_header}) + set(dest_dir "${IDF_PATH}/components/esp_system/openocd_stub_bins") + set(output_code_bin "${dest_dir}/stub_flash_idf_binary_code.inc") + set(output_data_bin "${dest_dir}/stub_flash_idf_binary_data.inc") + set(output_img_header "${dest_dir}/stub_flash_idf_image.h") + add_copy_command(${code_bin} ${output_code_bin}) + add_copy_command(${data_bin} ${output_data_bin}) + add_copy_command(${img_header} ${output_img_header}) + add_custom_target(copy_stub_bins ALL + DEPENDS ${output_code_bin} ${output_data_bin} ${output_img_header} + COMMENT "Copying OpenOCD stub binaries and image header" + ) + endif() + endif() + + set(srcs "openocd_stub_flasher.c") + add_prefix(srcs "${CMAKE_CURRENT_LIST_DIR}/" "${srcs}") + target_sources(${COMPONENT_LIB} PRIVATE ${srcs}) + target_include_directories(${COMPONENT_LIB} PUBLIC .) + target_link_libraries(${COMPONENT_LIB} INTERFACE "-u esp_system_include_openocd_stub_binaries") + +endif() diff --git a/components/esp_system/openocd_stub_bins/esp_riscv_stub_tramp.inc b/components/esp_system/openocd_stub_bins/esp_riscv_stub_tramp.inc new file mode 100644 index 00000000000..22c0b530f60 --- /dev/null +++ b/components/esp_system/openocd_stub_bins/esp_riscv_stub_tramp.inc @@ -0,0 +1 @@ + 0x82, 0x98, 0x02, 0x90 diff --git a/components/esp_system/openocd_stub_bins/openocd_stub_flasher.c b/components/esp_system/openocd_stub_bins/openocd_stub_flasher.c new file mode 100644 index 00000000000..52331ec67c1 --- /dev/null +++ b/components/esp_system/openocd_stub_bins/openocd_stub_flasher.c @@ -0,0 +1,33 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include + +#include "stub_flash_idf_image.h" + +/* Copied from openocd-esp32/contrib/loaders/flash/espressif/${target}/inc/stub_flash_idf_binary_code.inc */ +static const uint8_t s_flasher_stub_code[] __attribute__((used, section(".ocd_stub.code"))) = { +#include "stub_flash_idf_binary_code.inc" +}; + +/* Copied from openocd-esp32/src/target/espressif/esp_riscv_stub_tramp.inc */ +static const uint8_t s_flasher_stub_tramp[] __attribute__((used, section(".ocd_stub.tramp"))) = { +#include "esp_riscv_stub_tramp.inc" +}; + +/* Copied from openocd-esp32/contrib/loaders/flash/espressif/${target}/inc/stub_flash_idf_binary_data.inc */ +static const uint8_t s_flasher_stub_data[] __attribute__((used, section(".ocd_stub.data"))) = { +#include "stub_flash_idf_binary_data.inc" +}; + +static uint8_t s_flasher_stub_bss[OPENOCD_STUB_BSS_SIZE] __attribute__((used, section(".ocd_stub.bss"))); +static uint8_t s_flasher_stub_stack[OPENOCD_STUB_STACK_SIZE] __attribute__((used, section(".ocd_stub.stack"))); +static uint8_t s_flasher_stub_params[OPENOCD_STUB_PARAM_SIZE] __attribute__((used, section(".ocd_stub.params"))); +static uint8_t s_flasher_stub_bp_sectors[OPENOCD_STUB_BP_SECTOR_SIZE] __attribute__((used, section(".ocd_stub.scratchmem"))); + +// Hook to force the linker to include this file +void esp_system_include_openocd_stub_binaries(void) +{ +} diff --git a/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in index 47dc43d9d5b..1f6da29da44 100644 --- a/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in @@ -1542,3 +1542,7 @@ config SOC_LP_CORE_SINGLE_INTERRUPT_VECTOR config SOC_LP_CORE_SUPPORT_ETM bool default y + +config SOC_DEBUG_HAVE_OCD_STUB_BINS + bool + default y diff --git a/components/soc/esp32c6/include/soc/soc_caps.h b/components/soc/esp32c6/include/soc/soc_caps.h index b997a19b909..3c6692015c2 100644 --- a/components/soc/esp32c6/include/soc/soc_caps.h +++ b/components/soc/esp32c6/include/soc/soc_caps.h @@ -609,3 +609,6 @@ /*------------------------------------- ULP CAPS -------------------------------------*/ #define SOC_LP_CORE_SINGLE_INTERRUPT_VECTOR (1) /*!< LP Core interrupts all map to a single entry in vector table */ #define SOC_LP_CORE_SUPPORT_ETM (1) /*!< LP Core supports ETM */ + +/*------------------------------------- DEBUG CAPS -------------------------------------*/ +#define SOC_DEBUG_HAVE_OCD_STUB_BINS (1) diff --git a/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in b/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in index f66714fbaea..3994425d3b6 100644 --- a/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in @@ -1450,3 +1450,7 @@ config SOC_BLE_MULTI_CONN_OPTIMIZATION config SOC_BLE_PERIODIC_ADV_ENH_SUPPORTED bool default y + +config SOC_DEBUG_HAVE_OCD_STUB_BINS + bool + default y diff --git a/components/soc/esp32h2/include/soc/soc_caps.h b/components/soc/esp32h2/include/soc/soc_caps.h index 8831aa1a3cd..12ed5a23b5c 100644 --- a/components/soc/esp32h2/include/soc/soc_caps.h +++ b/components/soc/esp32h2/include/soc/soc_caps.h @@ -570,3 +570,6 @@ #define SOC_BLE_POWER_CONTROL_SUPPORTED (1) /*!< Support Bluetooth Power Control */ #define SOC_BLE_MULTI_CONN_OPTIMIZATION (1) /*!< Support multiple connections optimization */ #define SOC_BLE_PERIODIC_ADV_ENH_SUPPORTED (1) /*!< Support For BLE Periodic Adv Enhancements */ + +/*------------------------------------- DEBUG CAPS -------------------------------------*/ +#define SOC_DEBUG_HAVE_OCD_STUB_BINS (1) diff --git a/docs/en/api-guides/performance/ram-usage.rst b/docs/en/api-guides/performance/ram-usage.rst index b3a0d142cf7..a144005d081 100644 --- a/docs/en/api-guides/performance/ram-usage.rst +++ b/docs/en/api-guides/performance/ram-usage.rst @@ -192,6 +192,7 @@ The following options will reduce IRAM usage of some ESP-IDF features: - Refer to the sdkconfig menu ``Auto-detect Flash chips``, and you can disable flash drivers which you do not need to save some IRAM. :SOC_GPSPI_SUPPORTED: - Enable :ref:`CONFIG_HEAP_PLACE_FUNCTION_INTO_FLASH`. Provided that :ref:`CONFIG_SPI_MASTER_ISR_IN_IRAM` is not enabled and the heap functions are not incorrectly used from ISRs, this option is safe to enable in all configurations. :esp32c2: - Enable :ref:`CONFIG_BT_RELEASE_IRAM`. Release BT text section and merge BT data, bss & text into a large free heap region when ``esp_bt_mem_release`` is called. This makes Bluetooth unavailable until the next restart, but saving ~22 KB or more of IRAM. + :SOC_DEBUG_HAVE_OCD_STUB_BINS: - Disabling :ref:`CONFIG_ESP_DEBUG_INCLUDE_OCD_STUB_BINS` frees 8 KB IRAM but overall speed of debugging might be impacted due to the added overhead of runtime stub loading especially when using flash breakpoints. .. only:: esp32 @@ -202,7 +203,7 @@ The following options will reduce IRAM usage of some ESP-IDF features: To use this option, ESP-IDF should be able to recognize that the new SRAM1 area is also a valid load address for an image segment. If the software bootloader was compiled before this option existed, then the bootloader will not be able to load the app that has code placed in this new extended IRAM area. This would typically happen if you are doing an OTA update, where only the app would be updated. - If the IRAM section were to be placed in an invalid area, then this would be detected during the boot-up process, and result in a failed boot: + If the IRAM section were to be placed in an invalid area, then this would be detected during the boot up process, and result in a failed boot: .. code-block:: text diff --git a/docs/zh_CN/api-guides/performance/ram-usage.rst b/docs/zh_CN/api-guides/performance/ram-usage.rst index 44839f698ee..b4a7a89cf8f 100644 --- a/docs/zh_CN/api-guides/performance/ram-usage.rst +++ b/docs/zh_CN/api-guides/performance/ram-usage.rst @@ -192,6 +192,7 @@ IRAM 优化 - 要禁用不需要的 flash 驱动程序，节省 IRAM 空间，请参阅 sdkconfig 菜单中的 ``Auto-detect Flash chips`` 选项。 :SOC_GPSPI_SUPPORTED: - 启用 :ref:`CONFIG_HEAP_PLACE_FUNCTION_INTO_FLASH`。只要未启用 :ref:`CONFIG_SPI_MASTER_ISR_IN_IRAM` 选项，且没有从 ISR 中错误地调用堆函数，就可以在所有配置中安全启用此选项。 :esp32c2: - 启用 :ref:`CONFIG_BT_RELEASE_IRAM`。 蓝牙所使用的 data，bss 和 text 段已经被分配在连续的RAM区间。当调用 ``esp_bt_mem_release`` 时，这些段都会被添加到 Heap 中。 这将节省约 22 KB 的 RAM。但要再次使用蓝牙功能，需要重启程序。 + :SOC_DEBUG_HAVE_OCD_STUB_BINS: - 禁用 :ref:`CONFIG_ESP_DEBUG_INCLUDE_OCD_STUB_BINS` 选项可以释放 8 KB 的 IRAM, 但由于运行时加载存根的额外开销，特别是在使用 flash 断点时，可能会影响调试的整体速度。 .. only:: esp32 diff --git a/tools/ci/astyle-rules.yml b/tools/ci/astyle-rules.yml index e74f913eb54..12da05ef74e 100644 --- a/tools/ci/astyle-rules.yml +++ b/tools/ci/astyle-rules.yml @@ -161,6 +161,10 @@ components_not_formatted_permanent: - "/examples/peripherals/dac/dac_continuous/dac_audio/main/audio_example_file.h" # Coredump (generated) - /components/espcoredump/include_core_dump/elf.h + # OpenOCD stub binaries (generated) + - /components/esp_system/openocd_stub_bins/*.inc + - /components/esp_system/openocd_stub_bins/esp32c6/*.inc + - /components/esp_system/openocd_stub_bins/esp32h2/*.inc docs: # Docs directory contains some .inc files, which are not C include files From d78439a5722dc22342a98b798a1d9ae93f687b35 Mon Sep 17 00:00:00 2001 From: Mahavir Jain Date: Thu, 26 Sep 2024 20:48:44 +0530 Subject: [PATCH 012/472] docs: enable qemu doc guide for ESP32-S3 --- docs/conf_common.py | 9 ++++++++- docs/en/api-guides/tools/index.rst | 2 +- docs/zh_CN/api-guides/tools/index.rst | 2 +- 3 files changed, 10 insertions(+), 3 deletions(-) diff --git a/docs/conf_common.py b/docs/conf_common.py index 2a9a6fee84b..c7c26263d85 100644 --- a/docs/conf_common.py +++ b/docs/conf_common.py @@ -218,7 +218,7 @@ 'api-reference/peripherals/touch_pad.rst', 'api-reference/peripherals/sd_pullup_requirements.rst', 'api-guides/RF_calibration.rst', - 'api-guides/phy.rst'] + USB_OTG_DFU_DOCS + USB_OTG_CONSOLE_DOCS + 'api-guides/phy.rst'] + USB_OTG_DFU_DOCS + USB_OTG_CONSOLE_DOCS + QEMU_DOCS # No JTAG docs for this one as it gets gated on SOC_USB_SERIAL_JTAG_SUPPORTED down below. ESP32C3_DOCS = ['hw-reference/esp32c3/**', @@ -379,6 +379,9 @@ idf_build_system = {'doxygen_component_info': True, 'component_info_ignore_file': Path(os.environ['IDF_PATH']) / 'docs' / 'component_info_ignore_file.txt'} +# Please update following list to enable Qemu doc guide (and cross references) for a new target +QEMU_TARGETS = ['esp32', 'esp32c3', 'esp32s3'] + # Callback function for user setup that needs be done after `config-init`-event # config.idf_target is not available at the initial config stage @@ -386,6 +389,10 @@ def conf_setup(app, config): config.add_warnings_content = 'This document is not updated for {} yet, so some of the content may not be correct.'.format(config.idf_target.upper()) add_warnings_file = '{}/../docs_not_updated/{}.txt'.format(app.confdir, config.idf_target) + + if config.idf_target in QEMU_TARGETS: + app.tags.add('TARGET_SUPPORT_QEMU') + try: with open(add_warnings_file) as warning_file: config.add_warnings_pages = warning_file.read().splitlines() diff --git a/docs/en/api-guides/tools/index.rst b/docs/en/api-guides/tools/index.rst index 1b25030209f..f5d1801ab77 100644 --- a/docs/en/api-guides/tools/index.rst +++ b/docs/en/api-guides/tools/index.rst @@ -12,4 +12,4 @@ Tools idf-clang-tidy idf-tools idf-size - :esp32 or esp32c3: qemu + :TARGET_SUPPORT_QEMU: qemu diff --git a/docs/zh_CN/api-guides/tools/index.rst b/docs/zh_CN/api-guides/tools/index.rst index 44916de2606..e6b4d2158fc 100644 --- a/docs/zh_CN/api-guides/tools/index.rst +++ b/docs/zh_CN/api-guides/tools/index.rst @@ -12,4 +12,4 @@ idf-clang-tidy idf-tools idf-size - :esp32 or esp32c3: qemu + :TARGET_SUPPORT_QEMU: qemu From d6c4cbb53f4713f781f45bc1c2a5d3da8e5f01aa Mon Sep 17 00:00:00 2001 From: Mahavir Jain Date: Thu, 26 Sep 2024 20:49:27 +0530 Subject: [PATCH 013/472] docs: fix typo related to secure boot --- docs/en/api-guides/bootloader.rst | 2 +- docs/zh_CN/api-guides/bootloader.rst | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/docs/en/api-guides/bootloader.rst b/docs/en/api-guides/bootloader.rst index 58b7d9ee702..f835b597dc9 100644 --- a/docs/en/api-guides/bootloader.rst +++ b/docs/en/api-guides/bootloader.rst @@ -6,7 +6,7 @@ Bootloader The ESP-IDF Software Bootloader performs the following functions: 1. Minimal initial configuration of internal modules; -2. Initialize :doc:`/security/flash-encryption` and/or :doc:`Secure ` features, if configured; +2. Initialize :doc:`/security/flash-encryption` and/or :doc:`Secure Boot ` features, if configured; 3. Select the application partition to boot, based on the partition table and ota_data (if any); 4. Load this image to RAM (IRAM & DRAM) and transfer management to the image that was just loaded. diff --git a/docs/zh_CN/api-guides/bootloader.rst b/docs/zh_CN/api-guides/bootloader.rst index 29277188a71..a4577c67d91 100644 --- a/docs/zh_CN/api-guides/bootloader.rst +++ b/docs/zh_CN/api-guides/bootloader.rst @@ -6,7 +6,7 @@ ESP-IDF 软件引导加载程序 (Bootloader) 主要执行以下任务： 1. 内部模块的最小化初始配置； -2. 如果配置了 :doc:`/security/flash-encryption` 和/或 :doc:`Secure `，则对其进行初始化。 +2. 如果配置了 :doc:`/security/flash-encryption` 和/或 :doc:`Secure Boot `，则对其进行初始化。 3. 根据分区表和 ota_data（如果存在）选择需要引导的应用程序 (app) 分区； 4. 将此应用程序镜像加载到 RAM（IRAM 和 DRAM）中，最后把控制权转交给此应用程序。 From 1e94096e16eec54aa83e2946adbc9d50614f483d Mon Sep 17 00:00:00 2001 From: Mahavir Jain Date: Thu, 26 Sep 2024 20:50:04 +0530 Subject: [PATCH 014/472] docs: update qemu guide for efuse commands - add mention of qemu guide in security related chapters - also added a note about secure boot v2 config in qemu workflow --- docs/en/api-guides/tools/qemu.rst | 30 +++++++++++++++++-- ...security-features-enablement-workflows.rst | 5 ++++ docs/en/security/security.rst | 6 ++++ 3 files changed, 39 insertions(+), 2 deletions(-) diff --git a/docs/en/api-guides/tools/qemu.rst b/docs/en/api-guides/tools/qemu.rst index 697f45ca7cd..d5b2649919e 100644 --- a/docs/en/api-guides/tools/qemu.rst +++ b/docs/en/api-guides/tools/qemu.rst @@ -1,6 +1,8 @@ QEMU Emulator ============= +{IDF_TARGET_CRYPT_CNT:default="SPI_BOOT_CRYPT_CNT",esp32="FLASH_CRYPT_CNT"} + :link_to_translation:`zh_CN:[中文]` Espressif maintains a `fork `_ of the QEMU emulator with support for {IDF_TARGET_NAME}. This fork implements emulation of the CPU, memory, and several peripherals of {IDF_TARGET_NAME}. For more information about QEMU for {IDF_TARGET_NAME}, see the `QEMU README documentation `_. @@ -119,13 +121,37 @@ QEMU supports emulation of eFuses. This can be a convenient way to test security You can use :doc:`idf.py` eFuse-related commands to program eFuses. When you run any of these commands together with ``qemu`` command, the eFuses are programmed in QEMU, and the ``qemu_efuse.bin`` file is updated. For example, +.. only:: not SOC_FLASH_ENCRYPTION_XTS_AES + + .. code-block:: console + + idf.py qemu efuse-burn {IDF_TARGET_CRYPT_CNT} 1 + idf.py qemu efuse-burn-key flash_encryption my_flash_encryption_key.bin + +.. only:: SOC_FLASH_ENCRYPTION_XTS_AES + + .. code-block:: console + + idf.py qemu efuse-burn {IDF_TARGET_CRYPT_CNT} 1 + idf.py qemu efuse-burn-key BLOCK my_flash_encryption_key.bin KEYPURPOSE + + For details regarding the ``BLOCK`` and ``KEYPURPOSE``, please refer to the :doc:`../../security/flash-encryption` guide. + +To dump the eFuse summary, please use the following command: + .. code-block:: console - idf.py qemu efuse-burn FLASH_CRYPT_CNT 1 + idf.py qemu efuse-summary By default, the values of eFuses are read from and written to the ``qemu_efuse.bin`` file in the build directory. You can specify a different file using the ``--efuse-file`` option. For example, .. code-block:: console - idf.py qemu --efuse-file my_efuse.bin efuse-burn FLASH_CRYPT_CNT 1 + idf.py qemu --efuse-file my_efuse.bin efuse-burn {IDF_TARGET_CRYPT_CNT} 1 idf.py qemu --efuse-file my_efuse.bin monitor + +Emulating Secure Boot +~~~~~~~~~~~~~~~~~~~~~ + +QEMU supports emulation of secure boot v2 scheme. Please keep :ref:`CONFIG_SECURE_BOOT_FLASH_BOOTLOADER_DEFAULT` enabled to include signed bootloader image into the qemu image artifact. + diff --git a/docs/en/security/security-features-enablement-workflows.rst b/docs/en/security/security-features-enablement-workflows.rst index 35e36344b83..ecaeea7044b 100644 --- a/docs/en/security/security-features-enablement-workflows.rst +++ b/docs/en/security/security-features-enablement-workflows.rst @@ -18,6 +18,11 @@ When enabling security features on ESP32 SoCs, it is recommended that power supp This guide describes a set of workflows to enable security features on the device with the assistance of an external host machine. These workflows are broken down into various stages, with each stage generating signing/encryption keys on the host machine. This allows for greater chances of recovery in case of power or other failures. Furthermore, these workflows expedites the overall provisioning process via the use of the host machine (e.g., encrypting firmware on the host is quicker than on the device). +.. only:: TARGET_SUPPORT_QEMU + + .. important:: + + It is possible to try out the security features for {IDF_TARGET_NAME} target SoC under :doc:`../api-guides/tools/qemu` virtually. Once the security workflow is established, you can then proceed to the real hardware. Goals ----- diff --git a/docs/en/security/security.rst b/docs/en/security/security.rst index 07e3ef2b262..d834e7c9d4b 100644 --- a/docs/en/security/security.rst +++ b/docs/en/security/security.rst @@ -13,6 +13,12 @@ This guide provides an overview of the overall security features available in va In this guide, most used commands are in the form of ``idf.py secure-``, which is a wrapper around corresponding ``espsecure.py ``. The ``idf.py`` based commands provides more user-friendly experience, although may lack some of the advanced functionality of their ``espsecure.py`` based counterparts. +.. only:: TARGET_SUPPORT_QEMU + + .. important:: + + It is possible to try out the security features for {IDF_TARGET_NAME} target SoC under :doc:`../api-guides/tools/qemu` virtually. Once the security workflow is established, you can then proceed to the real hardware. + Goals ----- From a3810dcd5a1c8ce4161ad3a7f6cb066a7c0145eb Mon Sep 17 00:00:00 2001 From: Mahavir Jain Date: Thu, 26 Sep 2024 20:51:52 +0530 Subject: [PATCH 015/472] ci: add codeowners entry for docs_not_updated directory --- .gitlab/CODEOWNERS | 1 + 1 file changed, 1 insertion(+) diff --git a/.gitlab/CODEOWNERS b/.gitlab/CODEOWNERS index b1ef4019e94..9c191dabef2 100644 --- a/.gitlab/CODEOWNERS +++ b/.gitlab/CODEOWNERS @@ -159,6 +159,7 @@ /components/xtensa/ @esp-idf-codeowners/system /docs/ @esp-idf-codeowners/docs +/docs/docs_not_updated/ @esp-idf-codeowners/all-maintainers /docs/**/api-guides/tools/ @esp-idf-codeowners/tools /docs/en/api-guides/core_dump.rst @esp-idf-codeowners/debugging /docs/en/api-guides/jtag-debugging/ @esp-idf-codeowners/debugging From 8a80675b7c05d613b3e9a7126a0049458b589db2 Mon Sep 17 00:00:00 2001 From: zhanghaipeng Date: Sat, 28 Sep 2024 12:14:31 +0800 Subject: [PATCH 016/472] fix(bt): Update bt lib for ESP32-C3 and ESP32-S3(01cc408) - Fixed extended connectable advertising data length check --- components/bt/controller/lib_esp32c3_family | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/components/bt/controller/lib_esp32c3_family b/components/bt/controller/lib_esp32c3_family index 061e70c3195..73ae8322b2d 160000 --- a/components/bt/controller/lib_esp32c3_family +++ b/components/bt/controller/lib_esp32c3_family @@ -1 +1 @@ -Subproject commit 061e70c319576bf28b5695f5478dbe01ad18b18d +Subproject commit 73ae8322b2d7c990c195bfe3dca118ff43196f70 From b3778fdb24bfb4bc7a833b85bd741e6442724b83 Mon Sep 17 00:00:00 2001 From: yinqingzhao Date: Wed, 25 Sep 2024 14:07:15 +0800 Subject: [PATCH 017/472] feat(phy): esp32c6 update phy init data --- components/esp_phy/esp32c6/phy_init_data.c | 112 ++++++++++----------- 1 file changed, 56 insertions(+), 56 deletions(-) diff --git a/components/esp_phy/esp32c6/phy_init_data.c b/components/esp_phy/esp32c6/phy_init_data.c index f60ba8f7e39..499b60d6609 100644 --- a/components/esp_phy/esp32c6/phy_init_data.c +++ b/components/esp_phy/esp32c6/phy_init_data.c @@ -13,8 +13,8 @@ const char __attribute__((section(".rodata"))) phy_init_magic_pre[] = PHY_INIT_M * @brief Structure containing default recommended PHY initialization parameters. */ const esp_phy_init_data_t phy_init_data= { { - 0x01, - 0x00, + 0xa, + 0x0, LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x54), LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x54), LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x50), @@ -29,62 +29,62 @@ const esp_phy_init_data_t phy_init_data= { { LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x3C), LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x3C), LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x3C), + LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x4c), + LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x4c), + LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x4c), + LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x48), + 0x0, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, 0x00, 0x00, 0x00, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0, - 0, 0, 0, 0, @@ -140,7 +140,7 @@ const esp_phy_init_data_t phy_init_data= { { 0, 0, 0, - 0x70 + 0x51 } }; const char __attribute__((section(".rodata"))) phy_init_magic_post[] = PHY_INIT_MAGIC; From c0f296dafc9cc55602d9c52e34ad5769c8d18122 Mon Sep 17 00:00:00 2001 From: shenmengjing Date: Fri, 2 Aug 2024 10:53:08 +0800 Subject: [PATCH 018/472] docs: Update the CN translation for several docs --- docs/en/api-guides/external-ram.rst | 8 +-- docs/en/api-guides/hlinterrupts.rst | 2 +- docs/en/api-reference/system/ota.rst | 2 +- docs/en/api-reference/system/pthread.rst | 5 +- docs/zh_CN/api-guides/cplusplus.rst | 9 --- docs/zh_CN/api-guides/external-ram.rst | 6 +- docs/zh_CN/api-guides/hlinterrupts.rst | 2 + .../low-power-mode/low-power-mode-wifi.rst | 13 ++-- .../protocols/esp_crt_bundle.rst | 2 +- docs/zh_CN/api-reference/storage/fatfs.rst | 1 + docs/zh_CN/api-reference/system/ota.rst | 4 +- docs/zh_CN/api-reference/system/pthread.rst | 70 +++++++++++++++++-- 12 files changed, 90 insertions(+), 34 deletions(-) diff --git a/docs/en/api-guides/external-ram.rst b/docs/en/api-guides/external-ram.rst index f8cebef14d4..225de5fe995 100644 --- a/docs/en/api-guides/external-ram.rst +++ b/docs/en/api-guides/external-ram.rst @@ -167,7 +167,7 @@ By applying the macro ``EXT_RAM_NOINIT_ATTR``, data could be moved from the inte The benefits of XiP from PSRAM is: - - PSRAM access speed may be faster than Flash access, so the overall application performance may be better. For example, if the PSRAM is an Octal mode (8-line-PSRAM) and is configured to 80 MHz, then it is faster than a Quad flash (4-line-flash) which is configured to 80 MHz. + - PSRAM access speed may be faster than flash access, so the overall application performance may be better. For example, if the PSRAM is an Octal mode (8-line PSRAM) and is configured to 80 MHz, then it is faster than a Quad flash (4-line flash) which is configured to 80 MHz. - The cache will not be disabled during an SPI1 flash operation, thus optimizing the code execution performance during SPI1 flash operations. For ISRs, ISR callbacks and data which might be accessed during this period, you do not need to place them in internal RAM, thus internal RAM usage can be optimized. This feature is useful for high throughput peripheral involved applications to improve the performance during SPI1 flash operations. @@ -186,11 +186,11 @@ By applying the macro ``EXT_RAM_NOINIT_ATTR``, data could be moved from the inte .. only:: SOC_MMU_PER_EXT_MEM_TARGET - Because {IDF_TARGET_NAME} flash and PSRAM are using two separate SPI buses, moving flash content to PSRAM will actually increase the load of the PSRAM MSPI bus, so the exact impact on performance will be dependent on your app usage of PSRAM. + Since the flash and PSRAM in {IDF_TARGET_NAME} use two separate SPI buses, moving flash content to PSRAM will actually increase the load on the PSRAM MSPI bus. Therefore, the exact impact on performance will be dependent on your app usage of PSRAM. - For example, as the PSRAM bus speed could be faster than flash bus speed (e.g., if the PSRAM is a HEX (16-line-PSRAM on ESP32P4) and is configured to 200 Mhz, then it is much faster than a Quad flash (4-line-flash) which is configured to 80 MHz.). + The PSRAM bus can operate at a higher speed than the flash bus. For example, if the PSRAM is a HEX (16-line PSRAM on ESP32P4) running at 200 MHz, it is significantly faster than a Quad flash (4-line flash) running at 80 MHz. - If the instructions and data that are used to be in flash are not accessed very frequently, you should get better performance with this option enabled. We suggest doing performance profiling to determine how enabling this option will impact your system. + If the instructions and data previously stored in flash are not accessed frequently, then enabling this option could improve performance. It is recommended to conduct performance profiling to evaluate how this option will affect your system. Restrictions ============ diff --git a/docs/en/api-guides/hlinterrupts.rst b/docs/en/api-guides/hlinterrupts.rst index 6655a13ae43..4b0dd29295d 100644 --- a/docs/en/api-guides/hlinterrupts.rst +++ b/docs/en/api-guides/hlinterrupts.rst @@ -114,7 +114,7 @@ Then, in the component ``CMakeLists.txt``, add this name as an unresolved symbol This will ensure the linker to always includes the file defining ``ld_include_my_isr_file``, so that the ISR is always linked. -- High-priority interrupts can be routed and handled using :cpp:func:`esp_intr_alloc` and associated functions. The handler and handler arguments to :cpp:func:`esp_intr_alloc` must be NULL, however. +- High-priority interrupts can be routed and handled using :cpp:func:`esp_intr_alloc` and associated functions. However, the handler and handler arguments to :cpp:func:`esp_intr_alloc` must be NULL. - In theory, medium priority interrupts could also be handled in this way. ESP-IDF does not support this yet. diff --git a/docs/en/api-reference/system/ota.rst b/docs/en/api-reference/system/ota.rst index e446a5ce88d..db5e7c812b4 100644 --- a/docs/en/api-reference/system/ota.rst +++ b/docs/en/api-reference/system/ota.rst @@ -344,7 +344,7 @@ See Also Application Examples -------------------- -- :example:`system/ota/native_ota_example` demonstrates how to use the `app_update` component's APIs for native Over-the-Air (OTA) updates on {IDF_TARGET_NAME}. For the applicable SoCs, please refer to :example_file:`system/ota/native_ota_example/README.md`. +- :example:`system/ota/native_ota_example` demonstrates how to use the `app_update` component's APIs for native over-the-air (OTA) updates on {IDF_TARGET_NAME}. For applicable SoCs, please refer to :example_file:`system/ota/native_ota_example/README.md`. - :example:`system/ota/otatool` demonstrates how to use the OTA tool to perform operations such as reading, writing, and erasing OTA partitions, switching boot partitions, and switching to factory partition. For more information, please refer to :example_file:`system/ota/otatool/README.md`. diff --git a/docs/en/api-reference/system/pthread.rst b/docs/en/api-reference/system/pthread.rst index f78a8fbe6e7..894e1a659ef 100644 --- a/docs/en/api-reference/system/pthread.rst +++ b/docs/en/api-reference/system/pthread.rst @@ -183,6 +183,7 @@ Message Queues ^^^^^^^^^^^^^^ The message queue implementation is based on the `FreeRTOS-Plus-POSIX `_ project. Message queues are not made available in any filesystem on ESP-IDF. Message priorities are not supported. + The following API functions of the POSIX message queue specification are implemented: * `mq_open() `_ @@ -191,7 +192,7 @@ The following API functions of the POSIX message queue specification are impleme - It has to begin with a leading slash. - It has to be no more than 255 + 2 characters long (including the leading slash, excluding the terminating null byte). However, memory for ``name`` is dynamically allocated internally, so the shorter it is, the fewer memory it will consume. - The ``mode`` argument is not implemented and is ignored. - - Supported ``oflags``: ``O_RDWR``, ``O_CREAT``, ``O_EXCL``, and ``O_NONBLOCK`` + - Supported ``oflags``: ``O_RDWR``, ``O_CREAT``, ``O_EXCL``, and ``O_NONBLOCK``. * `mq_close() `_ * `mq_unlink() `_ @@ -218,7 +219,7 @@ The following API functions of the POSIX message queue specification are impleme Building ........ -To use the POSIX message queue API, please add ``rt`` as a requirement in your component's ``CMakeLists.txt`` +To use the POSIX message queue API, please add ``rt`` as a requirement in your component's ``CMakeLists.txt``. .. note:: diff --git a/docs/zh_CN/api-guides/cplusplus.rst b/docs/zh_CN/api-guides/cplusplus.rst index 5968ef27228..ba0c833e907 100644 --- a/docs/zh_CN/api-guides/cplusplus.rst +++ b/docs/zh_CN/api-guides/cplusplus.rst @@ -193,12 +193,3 @@ ESP-IDF 支持 ``iostream`` 功能，但应注意： ------------- 请勿在 C++ 中使用 ``setjmp``/``longjmp``。``longjmp`` 会在不调用任何析构函数的情况下盲目跳出堆栈，容易引起未定义的行为和内存泄漏。请改用 C++ 异常处理，这类程序可以确保正确调用析构函数。如果无法使用 C++ 异常处理，请使用其他替代方案（ ``setjmp``/``longjmp`` 除外），如简单的返回码。 - -应用示例 --------------------- - -- :example:`cxx/pthread` - -- :example:`cxx/exceptions` 演示了如何在 {IDF_TARGET_NAME} 中启用和使用 C++ 异常。该示例声明了一个类，当提供的参数等于 0 时，这个类会在构造函数中抛出异常。 - -- :example:`cxx/rtti` diff --git a/docs/zh_CN/api-guides/external-ram.rst b/docs/zh_CN/api-guides/external-ram.rst index 92bfa9eafcd..e23be50de1d 100644 --- a/docs/zh_CN/api-guides/external-ram.rst +++ b/docs/zh_CN/api-guides/external-ram.rst @@ -167,7 +167,7 @@ ESP-IDF 启动过程中，片外 RAM 被映射到数据虚拟地址空间，该 在 PSRAM 中直接执行代码的好处包括： - - PSRAM 访问速度可能快于 flash，因此性能更好。例如，如果使用的 PSRAM 是八线的，且被配置为 80 MHz，而 flash 是4线的，且被配置为 80 Mhz，那么 PSRAM 的访问速度是快于 flash 的。 + - PSRAM 的访问速度可能快于 flash，因此性能更好。例如，如果使用的 PSRAM 是八线的，且被配置为 80 MHz，而 flash 是四线的，且被配置为 80 Mhz，那么 PSRAM 的访问速度将快于 flash。 - 在进行 SPI1 flash 操作期间，cache 仍然保持启用状态，这样可以优化代码执行性能。由于无需把中断服务程序 (ISR)、ISR 回调和在此期间可能被访问的数据放置在片上 RAM 中，片上 RAM 可用于其他用途，从而提高了使用效率。这个特性适用于需要处理大量数据的高吞吐量外设应用，能显著提高 SPI1 flash 操作期间的性能。 @@ -188,7 +188,9 @@ ESP-IDF 启动过程中，片外 RAM 被映射到数据虚拟地址空间，该 由于 {IDF_TARGET_NAME} flash 和 PSRAM 使用两个独立的 SPI 总线，将 flash 内容移动到 PSRAM 实际上增加了 PSRAM MSPI 总线的负载， - 例如，PSRAM 的访问速度可能快于 flash (比如在 ESP32-P4 上，选择的 PSRAM 是十六线的并将其配置为 200 MHz， 此时 PSRAM 的访问速度是远快于一颗被配置为 80 MHz 的四线 flash 芯片)，如果这些之前在 flash 中被就地执行的指令和数据不是十分频繁地被访问，则使能这个选项会增加系统的性能。建议先进行性能分析以确定启用此选项是否会显著影响应用程序性能。 + PSRAM 的访问速度可能快于 flash。比如在 ESP32-P4 上，选择十六线 PSRAM 并将其配置为 200 MHz，此时 PSRAM 的访问速度远快于被配置为 80 MHz 的四线 flash 芯片。 + + 如果这些之前在 flash 中被就地执行的指令和数据不会被频繁访问，则使能该选项可能会提高系统的性能。建议先进行性能分析，评估启用此选项是否会显著影响应用程序的性能。 片外 RAM 使用限制 =================== diff --git a/docs/zh_CN/api-guides/hlinterrupts.rst b/docs/zh_CN/api-guides/hlinterrupts.rst index 7f78e1a3d9c..07fec7119e7 100644 --- a/docs/zh_CN/api-guides/hlinterrupts.rst +++ b/docs/zh_CN/api-guides/hlinterrupts.rst @@ -119,3 +119,5 @@ Xtensa 架构支持 32 个中断处理程序，这些中断分为从 1 到 7 的 - 中等优先级的中断理论上也可以通过上述方式处理，但 ESP-IDF 尚不支持此功能。 - 要检查 Xtensa 指令集架构 (ISA)，请参阅 `Xtensa ISA 摘要 `_。 + +:example:`system/nmi_isr` 提供了一个示例，可以在基于 Xtensa 架构的目标平台上实现自定义 NMI 处理程序。 diff --git a/docs/zh_CN/api-guides/low-power-mode/low-power-mode-wifi.rst b/docs/zh_CN/api-guides/low-power-mode/low-power-mode-wifi.rst index ac6af18ba32..06825059f3b 100644 --- a/docs/zh_CN/api-guides/low-power-mode/low-power-mode-wifi.rst +++ b/docs/zh_CN/api-guides/low-power-mode/low-power-mode-wifi.rst @@ -14,14 +14,13 @@ Wi-Fi 场景下低功耗模式介绍 在介绍具体内容前先给出 Wi-Fi 场景下低功耗模式总结表，以方便用户根据需求快速选择想要了解的内容，选择合适的低功耗模式。 - .. include:: ../sleep-current/{IDF_TARGET_PATH_NAME}_summary.inc .. note:: 上表中所有电流均为平均电流，表中术语在下文均有介绍，用户可根据需求进行查看。 -.. _Wi-Fi 省电的基本原理: +.. _Basic Principles of Wi-Fi Power Saving: Wi-Fi 省电的基本原理 --------------------- @@ -90,9 +89,9 @@ Wi-Fi 省电的基本原理 可以看出影响功耗表现的主要有三点：interval、period 和 base current。 - - **interval** 是 station Wi-Fi 相关模块工作的间隔，既可以由低功耗模式自定义，也可根据 Wi-Fi 协议省电机制（详细内容请见 :ref:`Wi-Fi 省电的基本原理`），由 DTIM 周期决定。可以看出在同等情下，interval 越大，功耗表现会更好，但是响应会更慢，影响通信的及时性。 + - **interval** 是 station Wi-Fi 相关模块工作的间隔，既可以由低功耗模式自定义，也可根据 Wi-Fi 协议省电机制（详细内容请见 :ref:`Basic Principles of Wi-Fi Power Saving`），由 DTIM 周期决定。可以看出在同等情下，interval 越大，功耗表现会更好，但是响应会更慢，影响通信的及时性。 - - **period** 可以看作每次 station Wi-Fi 工作的时间，这段时间的长度也会影响功耗的表现。period 不是一个固定的时长（详细内容请见 :ref:`Wi-Fi 省电的基本原理`），在保证 Wi-Fi 通信正常的情况下，period 持续时间越短，功耗表现越好。但是减少 period 时间，必然会影响通信的可靠性。 + - **period** 可以看作每次 station Wi-Fi 工作的时间，这段时间的长度也会影响功耗的表现。period 不是一个固定的时长（详细内容请见 :ref:`Basic Principles of Wi-Fi Power Saving`），在保证 Wi-Fi 通信正常的情况下，period 持续时间越短，功耗表现越好。但是减少 period 时间，必然会影响通信的可靠性。 - **base current** 是 Wi-Fi 相关模块不工作时芯片的电流，影响其大小的因素很多，不同的功耗模式下休眠策略不同。所以，在满足功能的情况下，优化配置降低该电流大小可以提高功耗表现，但同时关闭其余模块会影响相关功能和芯片的唤醒时间。 @@ -106,7 +105,7 @@ Modem-sleep 模式主要工作原理基于 DTIM 机制，周期性的醒来处 Modem-sleep 模式会在 Wi-Fi 任务结束后自动进入休眠无需调用 API，休眠时仅会关闭 Wi-Fi 相关模块 (PHY)，其余模块均处在正常上电状态。 -Modem-sleep 模式默认会根据 DTIM 周期或 listen interval（于 :ref:`Modem-sleep 模式配置` 中介绍）醒来，相当于系统自动设置了一个 Wi-Fi 唤醒源，因此用户无需再配置唤醒源，同时系统主动发包时也可以唤醒。 +Modem-sleep 模式默认会根据 DTIM 周期或 listen interval（于 :ref:`Modem-sleep Mode Configuration` 中介绍）醒来，相当于系统自动设置了一个 Wi-Fi 唤醒源，因此用户无需再配置唤醒源，同时系统主动发包时也可以唤醒。 Modem-sleep 模式是一个开关型的模式，调用 API 开启后一直自动运行，其工作流程十分简单，具体如下图。 @@ -121,7 +120,7 @@ Modem-sleep 模式是一个开关型的模式，调用 API 开启后一直自动 Modem-sleep 模式工作流程图 -根据上文的基本电流图，结合 Modem-sleep 模式的工作原理，以 Min Modem 模式（于 :ref:`Modem-sleep 模式配置` 中介绍）为例可得理想情况下电流变化图。 +根据上文的基本电流图，结合 Modem-sleep 模式的工作原理，以 Min Modem 模式（于 :ref:`Modem-sleep Mode Configuration` 中介绍）为例可得理想情况下电流变化图。 .. code-block:: text @@ -294,7 +293,7 @@ Deep-sleep 模式在 Wi-Fi 场景下与纯系统下基本相同，详情可以 - 丢失 beacon 时睡眠优化 (:ref:`CONFIG_ESP_WIFI_SLP_BEACON_LOST_OPT`) -.. _Modem-sleep 模式配置: +.. _Modem-sleep Mode Configuration: Modem-sleep 模式配置 +++++++++++++++++++++++ diff --git a/docs/zh_CN/api-reference/protocols/esp_crt_bundle.rst b/docs/zh_CN/api-reference/protocols/esp_crt_bundle.rst index a08e012377e..2fdb0d4c4ad 100644 --- a/docs/zh_CN/api-reference/protocols/esp_crt_bundle.rst +++ b/docs/zh_CN/api-reference/protocols/esp_crt_bundle.rst @@ -16,7 +16,7 @@ ESP x509 证书包 API 提供了一种简便的方法，帮助你安装自定义 生成证书包时，你需选择： -* 来自 Mozilla 的完整根证书包，包含超过 130 份证书。目前提供的证书包更新于 2024 年 3 月 11 日，星期一，15:25:27 (GMT)。 +* 来自 Mozilla 的完整根证书包，包含超过 130 份证书。目前提供的证书包更新于 2024 年 9 月 24 日，星期二，03:12:04 (GMT)。 * 一组预先筛选的常用根证书。其中仅包含约 41 份证书，但根据 SSL 证书颁发机构统计数据，其绝对使用率约达到 90%，市场覆盖率约达 99%。 此外，还可指定证书文件的路径或包含证书的目录，将其他证书添加到生成的证书包中。 diff --git a/docs/zh_CN/api-reference/storage/fatfs.rst b/docs/zh_CN/api-reference/storage/fatfs.rst index 65f281bd790..54dfdf27c7b 100644 --- a/docs/zh_CN/api-reference/storage/fatfs.rst +++ b/docs/zh_CN/api-reference/storage/fatfs.rst @@ -141,6 +141,7 @@ FatFs 分区生成器 相关示例请查看 :example:`storage/fatfsgen`。 + .. _fatfs-partition-analyzer: FatFs 分区分析器 diff --git a/docs/zh_CN/api-reference/system/ota.rst b/docs/zh_CN/api-reference/system/ota.rst index 53d0d1b6723..272f193ec44 100644 --- a/docs/zh_CN/api-reference/system/ota.rst +++ b/docs/zh_CN/api-reference/system/ota.rst @@ -344,7 +344,9 @@ Python API 应用示例 ------------ -- :example:`system/ota/otatool` 演示了如何使用 OTA 工具执行读取、写入和擦除 OTA 分区、切换启动分区以及切换到出厂分区等操作。有关更多信息，请参考 :example_file:`system/ota/otatool/README.md`。 +- :example:`system/ota/native_ota_example` 演示了如何在 {IDF_TARGET_NAME} 上使用 `app_update` 组件的 API 进行原生空中升级 (OTA)。适用的 SoC 请参阅 :example_file:`system/ota/native_ota_example/README.md`。 + +- :example:`system/ota/otatool` 演示了如何使用 OTA 工具执行读取、写入和擦除 OTA 分区、切换启动分区以及切换到工厂分区等操作。详情请参阅 :example_file:`system/ota/otatool/README.md`。 API 参考 -------- diff --git a/docs/zh_CN/api-reference/system/pthread.rst b/docs/zh_CN/api-reference/system/pthread.rst index 218c647ec21..48af7bf9b89 100644 --- a/docs/zh_CN/api-reference/system/pthread.rst +++ b/docs/zh_CN/api-reference/system/pthread.rst @@ -1,5 +1,5 @@ -POSIX Thread -============ +POSIX 支持（包括 POSIX 线程支持） +================================= :link_to_translation:`en:[English]` @@ -12,7 +12,11 @@ ESP-IDF 基于 FreeRTOS，但提供了一系列与 POSIX 兼容的 API，以便 添加标准 ``pthread.h`` 头文件后可以在 ESP-IDF 中使用 pthread，该头文件已包含在工具链 libc 中。还有另一个专用于 ESP-IDF 的头文件 ``esp_pthread.h``，其中提供了一些额外的非 POSIX API，以便通过 pthread 使用一些 ESP-IDF 功能。 -C++ 标准库中的 ``std::thread``、``std::mutex``、``std::condition_variable`` 等功能也是通过 pthread（利用 GCC libstdc++）实现的。因此，本文档提到的限制条件也同样适用于 C++ 标准库中等效功能。 +除了 POSIX 线程，ESP-IDF 还支持 :ref:`POSIX 消息队列 `。 + +C++ 标准库中的 ``std::thread``、``std::mutex``、``std::condition_variable`` 等功能也是通过 pthread 和其他 POSIX API（利用 GCC libstdc++）实现的。因此，本文档提到的限制条件也同样适用于 C++ 标准库中的等效功能。 + +如果希望 ESP-IDF 支持某个尚未实现的 API，请 `在 GitHub 上发起功能请求 `_ 并提供详细信息。 RTOS 集成 ---------------- @@ -23,6 +27,10 @@ RTOS 集成 如果调用 C 标准库或 C++ sleep 函数，例如在 ``unistd.h`` 中定义的 ``usleep``，那么只有当睡眠时间超过 :ref:`一个 FreeRTOS 滴答周期 ` 时，任务才会阻塞并让出内核。如果时间较短，线程将处于忙等待状态，不会让步给另一个 RTOS 任务。 +.. note:: + + POSIX 的 ``errno`` 由 ESP-IDF 中的 newlib 提供。因此，配置项 ``configUSE_POSIX_ERRNO`` 并未被使用，应该保持禁用状态。 + 默认情况下，所有 pthread 具有相同的 RTOS 优先级，但可以通过调用 :ref:`ESP-IDF 提供的扩展 API ` 对此优先级进行更改。 标准功能 @@ -169,15 +177,65 @@ ESP-IDF 中实现了 POSIX 读写锁规范的以下 API 函数： ESP-IDF 中还有其他的线程本地存储选项，包括性能更高的选项。参见 :doc:`/api-guides/thread-local-storage`。 +.. _posix_message_queues: + +消息队列 +^^^^^^^^ + +消息队列的实现基于 `FreeRTOS-Plus-POSIX `_ 项目，ESP-IDF 的文件系统不提供消息队列，不支持消息优先级。 + +以下 POSIX 消息队列规范中的 API 函数已被实现： + +* `mq_open() `_ + + - 除了要符合 POSIX 规范，``name`` 参数还有以下额外限制： + - 必须以斜杠开头。 + - 长度不得超过 255 + 2 个字符（包括开头的斜杠，除去终止的空字符）。但 ``name`` 的内存是在内部动态分配的，所以名称越短，消耗的内存越少。 + - ``mode`` 参数未实现且被忽略。 + - 支持的 ``oflags``：``O_RDWR``、``O_CREAT``、``O_EXCL`` 和 ``O_NONBLOCK``。 + +* `mq_close() `_ +* `mq_unlink() `_ +* `mq_receive() `_ + + - 不支持消息优先级，因此 ``msg_prio`` 未被使用。 + +* `mq_timedreceive() `_ + + - 不支持消息优先级，因此 ``msg_prio`` 未被使用。 + +* `mq_send() `_ + + - 不支持消息优先级，因此 ``msg_prio`` 无效。 + +* `mq_timedsend() `_ + + - 不支持消息优先级，因此 ``msg_prio`` 无效。 + +* `mq_getattr() `_ + +尚未实现 `mq_notify() `_ 和 `mq_setattr() `_。 + +构建 +.... + +要使用 POSIX 消息队列 API，请在组件的 ``CMakeLists.txt`` 文件中添加 ``rt`` 作为依赖项。 + +.. note:: + + 请注意，如果曾在其他 FreeRTOS 项目中使用过 `FreeRTOS-Plus-POSIX `_，则 IDF 中的包含路径是 POSIX 风格的。因此，应用程序应直接包含 ``mqueue.h``，而不是使用子目录来包含 ``FreeRTOS_POSIX/mqueue.h``。 + 未实现 API --------------- ``pthread.h`` 头文件是一个标准头文件，包含了在 ESP-IDF 中未实现的额外 API 和功能，包括： -* 如果调用 ``pthread_cancel()``，返回 ``ENOSYS``。 -* ``pthread_condattr_init()`` 如果被调用，返回 ``ENOSYS``。 +* 若调用 ``pthread_cancel()``，则返回 ``ENOSYS``。 +* 若调用 ``pthread_condattr_init()``，则返回 ``ENOSYS``。 +* 若调用 `mq_notify() `_，则返回 ``ENOSYS``。 +* 若调用 `mq_setattr() `_，则返回 ``ENOSYS``。 -其他未列出的 pthread 函数未在 ESP-IDF 中实现，如果从 ESP-IDF 应用程序中直接引用，将产生编译器错误或链接器错误。如果希望 ESP-IDF 支持某个尚未实现的 API，请 `在 GitHub 上发起功能请求 `_ 并提供详细信息。 +其他未列出的 pthread 函数未在 ESP-IDF 中实现，如果从 ESP-IDF 应用程序中直接引用，将产生编译器错误或链接器错误。 .. _esp-pthread: From 757fa4d72c3ea7827fcedd1ed2a1724371a037f9 Mon Sep 17 00:00:00 2001 From: renpeiying Date: Fri, 27 Sep 2024 17:16:23 +0800 Subject: [PATCH 019/472] docs: Update Chinese translation for docs --- docs/en/api-guides/tools/qemu.rst | 2 +- docs/zh_CN/api-guides/tools/qemu.rst | 30 +++++++++++++++++-- ...security-features-enablement-workflows.rst | 5 ++++ docs/zh_CN/security/security.rst | 6 ++++ 4 files changed, 40 insertions(+), 3 deletions(-) diff --git a/docs/en/api-guides/tools/qemu.rst b/docs/en/api-guides/tools/qemu.rst index d5b2649919e..3160bab91b4 100644 --- a/docs/en/api-guides/tools/qemu.rst +++ b/docs/en/api-guides/tools/qemu.rst @@ -153,5 +153,5 @@ By default, the values of eFuses are read from and written to the ``qemu_efuse.b Emulating Secure Boot ~~~~~~~~~~~~~~~~~~~~~ -QEMU supports emulation of secure boot v2 scheme. Please keep :ref:`CONFIG_SECURE_BOOT_FLASH_BOOTLOADER_DEFAULT` enabled to include signed bootloader image into the qemu image artifact. +QEMU supports emulation of secure boot v2 scheme. Please keep :ref:`CONFIG_SECURE_BOOT_FLASH_BOOTLOADER_DEFAULT` enabled to include signed bootloader image into the QEMU image artifact. diff --git a/docs/zh_CN/api-guides/tools/qemu.rst b/docs/zh_CN/api-guides/tools/qemu.rst index 14f962dbcfe..87ba8729a27 100644 --- a/docs/zh_CN/api-guides/tools/qemu.rst +++ b/docs/zh_CN/api-guides/tools/qemu.rst @@ -1,6 +1,8 @@ QEMU 模拟器 =========== +{IDF_TARGET_CRYPT_CNT:default="SPI_BOOT_CRYPT_CNT",esp32="FLASH_CRYPT_CNT"} + :link_to_translation:`en:[English]` 乐鑫维护了一个 QEMU 模拟器的 `分支 `_，支持 {IDF_TARGET_NAME}。这个分支实现了对 {IDF_TARGET_NAME} 的 CPU、内存和多个外设的模拟。更多有关 {IDF_TARGET_NAME} 的 QEMU 的信息，请参阅 `QEMU README 文档 `_。 @@ -119,13 +121,37 @@ QEMU 支持 eFuse 的仿真，可用来测试安全启动和 flash 加密等与 使用 :doc:`idf.py` eFuse 相关命令来编程 eFuse。当这些命令与 ``qemu`` 命令一起运行时，eFuse 会在 QEMU 中编程，并且 ``qemu_efuse.bin`` 文件会更新。例如， +.. only:: not SOC_FLASH_ENCRYPTION_XTS_AES + + .. code-block:: console + + idf.py qemu efuse-burn {IDF_TARGET_CRYPT_CNT} 1 + idf.py qemu efuse-burn-key flash_encryption my_flash_encryption_key.bin + +.. only:: SOC_FLASH_ENCRYPTION_XTS_AES + + .. code-block:: console + + idf.py qemu efuse-burn {IDF_TARGET_CRYPT_CNT} 1 + idf.py qemu efuse-burn-key BLOCK my_flash_encryption_key.bin KEYPURPOSE + + 有关 ``BLOCK`` 和 ``KEYPURPOSE`` 的详细信息，请参阅 :doc:`../../security/flash-encryption` 指南。 + +如需导出 eFuse 概要，使用以下命令： + .. code-block:: console - idf.py qemu efuse-burn FLASH_CRYPT_CNT 1 + idf.py qemu efuse-summary 默认情况下，eFuse 的值从编译文件夹里的 ``qemu_efuse.bin`` 文件中读取和写入。也可以使用 ``--efuse-file`` 选项指定不同的文件。例如， .. code-block:: console - idf.py qemu --efuse-file my_efuse.bin efuse-burn FLASH_CRYPT_CNT 1 + idf.py qemu --efuse-file my_efuse.bin efuse-burn {IDF_TARGET_CRYPT_CNT} 1 idf.py qemu --efuse-file my_efuse.bin monitor + +模拟安全启动 +~~~~~~~~~~~~~ + +QEMU 支持模拟安全启动 v2 机制。请保持 :ref:`CONFIG_SECURE_BOOT_FLASH_BOOTLOADER_DEFAULT` 处于启用状态，将签名的引导加载程序镜像嵌入到 QEMU 的镜像文件中。 + diff --git a/docs/zh_CN/security/security-features-enablement-workflows.rst b/docs/zh_CN/security/security-features-enablement-workflows.rst index d7f9a8a3ddf..56a743b4d37 100644 --- a/docs/zh_CN/security/security-features-enablement-workflows.rst +++ b/docs/zh_CN/security/security-features-enablement-workflows.rst @@ -18,6 +18,11 @@ 这份指南介绍了一系列工作流程，从而在外部主机的协助下启用设备的安全功能。这些工作流程分为多个阶段，每个阶段都会在主机上生成签名/加密密钥，从而在发生电力或其他故障时，提高恢复几率。此外，在主机的协助下，这些流程将加快整体配置过程（例如，在主机上加密固件要比在设备上加密更快）。 +.. only:: TARGET_SUPPORT_QEMU + + .. important:: + + 可以在 :doc:`../api-guides/tools/qemu` 中虚拟测试 {IDF_TARGET_NAME} 目标芯片的安全功能。安全工作流程建立后，便可在真实硬件上继续操作。 目标 ---- diff --git a/docs/zh_CN/security/security.rst b/docs/zh_CN/security/security.rst index 455c79723f7..104c38b7fbc 100644 --- a/docs/zh_CN/security/security.rst +++ b/docs/zh_CN/security/security.rst @@ -13,6 +13,12 @@ 在本指南中，最常用的命令形式为 ``idf.py secure-``，这是对应 ``espsecure.py `` 的封装。基于 ``idf.py`` 的命令能提供更好的用户体验，但与基于 ``espsecure.py`` 的命令相比，可能会损失一部分高级功能。 +.. only:: TARGET_SUPPORT_QEMU + + .. important:: + + 可以在 :doc:`../api-guides/tools/qemu` 中虚拟测试 {IDF_TARGET_NAME} 目标芯片的安全功能。安全工作流程建立后，便可在真实硬件上继续操作。 + 目标 ---- From 5a1dd125135ccc33785deb540dba89b1005a2cc0 Mon Sep 17 00:00:00 2001 From: Sarvesh Bodakhe Date: Mon, 15 Jul 2024 15:06:13 +0530 Subject: [PATCH 020/472] fix(wifi): Do not try re-connection when sta disconnects with esp_wifi_disconnect() Do not follow wifi_config::wifi_sta_config::failure_retry_cnt logic when station itself issues a disconnect from AP/Router using esp_wifi_disconnect() --- components/esp_wifi/lib | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/components/esp_wifi/lib b/components/esp_wifi/lib index dde71a69c52..f3ea158d7c6 160000 --- a/components/esp_wifi/lib +++ b/components/esp_wifi/lib @@ -1 +1 @@ -Subproject commit dde71a69c525d0a69989eca620557536b2773231 +Subproject commit f3ea158d7c62b1a4479f6c0174a02bc19fa59f90 From 1a547e34f15151453f3f8c4702a627b10b5c84a1 Mon Sep 17 00:00:00 2001 From: Sudeep Mohanty Date: Fri, 27 Sep 2024 12:04:57 +0200 Subject: [PATCH 021/472] fix(freertos): Fix freertos example pytest script This commit updates the freertos/basic_freertos_smp_usage pytest script to not follow a rigid order when testing against output logs as tasks can spawn on any core in no particular order. --- .../main/lock_example.c | 4 +-- .../pytest_smp_examples.py | 27 ++++++++++--------- 2 files changed, 17 insertions(+), 14 deletions(-) diff --git a/examples/system/freertos/basic_freertos_smp_usage/main/lock_example.c b/examples/system/freertos/basic_freertos_smp_usage/main/lock_example.c index 670b13edc12..409e2095b62 100644 --- a/examples/system/freertos/basic_freertos_smp_usage/main/lock_example.c +++ b/examples/system/freertos/basic_freertos_smp_usage/main/lock_example.c @@ -78,7 +78,7 @@ static void inc_num_atomic_iter(void *arg) static void inc_num_mutex(void *arg) { - int task_index = *(int*)arg; + int task_index = (int)arg; ESP_LOGI(TAG, "mutex task %d created", task_index); while (!timed_out) { @@ -159,7 +159,7 @@ int comp_lock_entry_func(int argc, char **argv) s_global_num = 0; // create 2 tasks to increase a shared number in turn for (thread_id = 0; thread_id < SHARE_RES_THREAD_NUM; thread_id++) { - xTaskCreatePinnedToCore(inc_num_mutex, NULL, 4096, &thread_id, TASK_PRIO_3, NULL, tskNO_AFFINITY); + xTaskCreatePinnedToCore(inc_num_mutex, NULL, 4096, (void *)thread_id, TASK_PRIO_3, NULL, tskNO_AFFINITY); } // time out and stop running after 5 seconds diff --git a/examples/system/freertos/basic_freertos_smp_usage/pytest_smp_examples.py b/examples/system/freertos/basic_freertos_smp_usage/pytest_smp_examples.py index 5019db6a4b4..fa7ac3b547d 100644 --- a/examples/system/freertos/basic_freertos_smp_usage/pytest_smp_examples.py +++ b/examples/system/freertos/basic_freertos_smp_usage/pytest_smp_examples.py @@ -13,10 +13,13 @@ def test_creating_task( dut.expect(r'esp32(?:[a-zA-Z]\d)?>') # test creating_task dut.write('create_task') - dut.expect('create task example: task#0 is running on core#0') - dut.expect('create task example: task#1 is running on core#0') - dut.expect(r'create task example: task#2 is running on core#\d') - dut.expect(r'create task example: task#3 is running on core#\d') + expected_patterns = [ + 'create task example: task#0 is running on core#0', + 'create task example: task#1 is running on core#0', + r'create task example: task#2 is running on core#\d', + r'create task example: task#3 is running on core#\d', + ] + dut.expect(expected_patterns, expect_all=True) @pytest.mark.esp32c3 @@ -46,14 +49,14 @@ def test_locks( dut.expect(r'esp32(?:[a-zA-Z]\d)?>') # test locks dut.write('lock') - dut.expect(r'lock example: mutex task took \d+ us on core\d') - dut.expect(r'lock example: spinlock task took \d+ us on core\d') - dut.expect(r'lock example: atomic task took \d+ us on core\d') - dut.expect(r'task0 read value = 0 on core #\d') - dut.expect('task0 set value = 1') - dut.expect(r'task\d read value = 1 on core #\d') - dut.expect(r'task\d set value = 2') - dut.expect(r'task0 read value = 2 on core #\d') + expected_patterns = [ + r'lock example: mutex task took \d+ us on core\d', + r'lock example: spinlock task took \d+ us on core\d', + r'lock example: atomic task took \d+ us on core\d', + r'task\d read value = \d on core #\d', + r'task\d set value = \d', + ] + dut.expect(expected_patterns, expect_all=True) @pytest.mark.esp32c3 From 2c458f3af191f404923c8d59a31688530d4c41ee Mon Sep 17 00:00:00 2001 From: Peter Dragun Date: Wed, 18 Sep 2024 15:22:20 +0200 Subject: [PATCH 022/472] feat(tools): Add auto color to monitor and disable colors from chip logs ANSI color codes are handled on the host side instead of the chip side. This will result in shorter log messages transmitted over serial. --- components/bootloader/Kconfig.log.format | 2 +- components/log/Kconfig.format | 2 +- docs/en/migration-guides/release-5.x/5.4/system.rst | 1 + examples/storage/semihost_vfs/README.md | 3 +-- examples/storage/semihost_vfs/pytest_semihost_vfs.py | 8 +++++--- tools/idf_py_actions/serial_ext.py | 9 +++++++++ 6 files changed, 18 insertions(+), 7 deletions(-) diff --git a/components/bootloader/Kconfig.log.format b/components/bootloader/Kconfig.log.format index b1b877b0a99..6d87bc56012 100644 --- a/components/bootloader/Kconfig.log.format +++ b/components/bootloader/Kconfig.log.format @@ -2,7 +2,7 @@ menu "Format" config BOOTLOADER_LOG_COLORS bool "Color" - default y + default n help Use ANSI terminal colors in log output Enable ANSI terminal color codes. diff --git a/components/log/Kconfig.format b/components/log/Kconfig.format index ba0c6286ed8..e743dabff2e 100644 --- a/components/log/Kconfig.format +++ b/components/log/Kconfig.format @@ -2,7 +2,7 @@ menu "Format" config LOG_COLORS bool "Color" - default y + default n help Enable ANSI terminal color codes. In order to view these, your terminal program must support ANSI color codes. diff --git a/docs/en/migration-guides/release-5.x/5.4/system.rst b/docs/en/migration-guides/release-5.x/5.4/system.rst index e6e0ede0156..ca461e15d67 100644 --- a/docs/en/migration-guides/release-5.x/5.4/system.rst +++ b/docs/en/migration-guides/release-5.x/5.4/system.rst @@ -8,6 +8,7 @@ Log - `esp_log_buffer_hex` is deprecated, use `ESP_LOG_BUFFER_HEX` instead. - `esp_log_buffer_char` is deprecated, use `ESP_LOG_BUFFER_CHAR` instead. +- The default value for ``CONFIG_LOG_COLORS`` is now set to false. Colors are added on the host side by default in IDF Monitor. If you want to enable colors in the log output for other console monitors, set ``CONFIG_LOG_COLORS`` to true in your project configuration. To disable automatic coloring in IDF Monitor, run the following command: ``idf.py monitor --disable-auto-color``. ESP ROM --------- diff --git a/examples/storage/semihost_vfs/README.md b/examples/storage/semihost_vfs/README.md index 0cf77e01fa4..0ce5acc0eac 100644 --- a/examples/storage/semihost_vfs/README.md +++ b/examples/storage/semihost_vfs/README.md @@ -97,7 +97,7 @@ There are two outputs produced by example: ``` W (274) example: Switch to semihosted stdout W (274) example: Switched back to UART stdout - I (274) example: Wrote 2798 bytes + I (274) example: Wrote 2776 bytes ====================== HOST DATA START ========================= The following are the graphical (non-control) characters defined by ISO 8859-1 (1987). Descriptions in words aren't all that helpful, @@ -115,4 +115,3 @@ There are two outputs produced by example: ====================== HOST DATA END ========================= I (694) example: Read 6121 bytes ``` - diff --git a/examples/storage/semihost_vfs/pytest_semihost_vfs.py b/examples/storage/semihost_vfs/pytest_semihost_vfs.py index aff2e51227a..90af90e29e2 100644 --- a/examples/storage/semihost_vfs/pytest_semihost_vfs.py +++ b/examples/storage/semihost_vfs/pytest_semihost_vfs.py @@ -1,6 +1,5 @@ -# SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD +# SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD # SPDX-License-Identifier: Unlicense OR CC0-1.0 - import os import shutil import tempfile @@ -42,7 +41,10 @@ def prepare() -> t.Generator[None, None, None]: def test_semihost_vfs(dut: IdfDut) -> None: dut.expect_exact('example: Switch to semihosted stdout') dut.expect_exact('example: Switched back to UART stdout') - dut.expect_exact('example: Wrote 2798 bytes') + if dut.app.sdkconfig.get('LOG_COLORS') is True: + dut.expect_exact('example: Wrote 2798 bytes') + else: + dut.expect_exact('example: Wrote 2776 bytes') dut.expect_exact('====================== HOST DATA START =========================') with open(HOST_FILE_PATH) as f: diff --git a/tools/idf_py_actions/serial_ext.py b/tools/idf_py_actions/serial_ext.py index 9d8c1b3a3a7..502ca5ecec0 100644 --- a/tools/idf_py_actions/serial_ext.py +++ b/tools/idf_py_actions/serial_ext.py @@ -105,6 +105,7 @@ def monitor( timestamps: bool, timestamp_format: str, force_color: bool, + disable_auto_color: bool, ) -> None: """ Run esp_idf_monitor to watch build output @@ -187,6 +188,9 @@ def monitor( if force_color or os.name == 'nt': monitor_args += ['--force-color'] + if disable_auto_color: + monitor_args += ['--disable-auto-color'] + idf_py = [PYTHON] + _get_commandline_options(ctx) # commands to re-run idf.py monitor_args += ['-m', ' '.join("'%s'" % a for a in idf_py)] hints = not args.no_hints @@ -1011,6 +1015,11 @@ def efuse_write_protect(action: str, ctx: click.core.Context, args: PropertyDict 'is_flag': True, 'help': 'Always print ANSI for colors', }, + { + 'names': ['--disable-auto-color'], + 'is_flag': True, + 'help': 'Disable auto coloring logs', + }, ], 'order_dependencies': [ 'flash', From d5f37b526d4aca11a41fc37ecf0d41c749a6e985 Mon Sep 17 00:00:00 2001 From: Konstantin Kondrashov Date: Mon, 12 Aug 2024 12:49:27 +0300 Subject: [PATCH 023/472] feat(partitions): Adds new partition types and subtypes for bootloader and partition_table --- .../include/esp_flash_partitions.h | 14 ++++++++++- .../src/bootloader_utility.c | 20 +++++++++++++++ .../esp_partition/include/esp_partition.h | 6 +++++ components/esp_partition/partition_linux.c | 14 +++++++++++ components/partition_table/gen_esp32part.py | 25 +++++++++++++++---- docs/en/api-guides/partition-tables.rst | 18 +++++++++++-- .../bootloader/sdkconfig.ci.verbose_logging | 1 + 7 files changed, 90 insertions(+), 8 deletions(-) diff --git a/components/bootloader_support/include/esp_flash_partitions.h b/components/bootloader_support/include/esp_flash_partitions.h index 47fe9759610..d05ded654fe 100644 --- a/components/bootloader_support/include/esp_flash_partitions.h +++ b/components/bootloader_support/include/esp_flash_partitions.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -29,6 +29,14 @@ extern "C" { #define PART_SUBTYPE_DATA_NVS_KEYS 0x04 #define PART_SUBTYPE_DATA_EFUSE_EM 0x05 +#define PART_TYPE_BOOTLOADER 0x02 +#define PART_SUBTYPE_BOOTLOADER_PRIMARY 0x00 +#define PART_SUBTYPE_BOOTLOADER_OTA 0x01 + +#define PART_TYPE_PARTITION_TABLE 0x03 +#define PART_SUBTYPE_PARTITION_TABLE_PRIMARY 0x00 +#define PART_SUBTYPE_PARTITION_TABLE_OTA 0x01 + #define PART_TYPE_END 0xff #define PART_SUBTYPE_END 0xff @@ -41,7 +49,11 @@ extern "C" { /* Pre-partition table fixed flash offsets */ #define ESP_BOOTLOADER_DIGEST_OFFSET 0x0 #define ESP_BOOTLOADER_OFFSET CONFIG_BOOTLOADER_OFFSET_IN_FLASH /* Offset of bootloader image. Has matching value in bootloader KConfig.projbuild file. */ +#define ESP_PRIMARY_BOOTLOADER_OFFSET CONFIG_BOOTLOADER_OFFSET_IN_FLASH /* Offset of Primary bootloader image. */ #define ESP_PARTITION_TABLE_OFFSET CONFIG_PARTITION_TABLE_OFFSET /* Offset of partition table. Backwards-compatible name.*/ +#define ESP_PRIMARY_PARTITION_TABLE_OFFSET CONFIG_PARTITION_TABLE_OFFSET /* Offset of partition table. */ +#define ESP_PARTITION_TABLE_SIZE (0x1000) /* The partition table occupies 1 sector of flash (SPI_FLASH_SEC_SIZE) */ +#define ESP_BOOTLOADER_SIZE (ESP_PARTITION_TABLE_OFFSET - ESP_BOOTLOADER_OFFSET) #define ESP_PARTITION_TABLE_MAX_LEN 0xC00 /* Maximum length of partition table data */ #define ESP_PARTITION_TABLE_MAX_ENTRIES (ESP_PARTITION_TABLE_MAX_LEN / sizeof(esp_partition_info_t)) /* Maximum length of partition table data, including terminating entry */ diff --git a/components/bootloader_support/src/bootloader_utility.c b/components/bootloader_support/src/bootloader_utility.c index 30dd5049fc3..d27aaaf5397 100644 --- a/components/bootloader_support/src/bootloader_utility.c +++ b/components/bootloader_support/src/bootloader_utility.c @@ -199,6 +199,26 @@ bool bootloader_utility_load_partition_table(bootloader_state_t *bs) break; } break; /* PARTITION_USAGE_DATA */ + case PART_TYPE_BOOTLOADER: /* Bootloader partition */ + switch (partition->subtype) { + case PART_SUBTYPE_BOOTLOADER_PRIMARY: + partition_usage = "primary bootloader"; + break; + case PART_SUBTYPE_BOOTLOADER_OTA: + partition_usage = "ota bootloader"; + break; + } + break; /* PART_TYPE_BOOTLOADER */ + case PART_TYPE_PARTITION_TABLE: /* Partition table partition */ + switch (partition->subtype) { + case PART_SUBTYPE_PARTITION_TABLE_PRIMARY: + partition_usage = "primary partition_table"; + break; + case PART_SUBTYPE_PARTITION_TABLE_OTA: + partition_usage = "ota partition_table"; + break; + } + break; /* PART_TYPE_PARTITION_TABLE */ default: /* other partition type */ break; } diff --git a/components/esp_partition/include/esp_partition.h b/components/esp_partition/include/esp_partition.h index ea0c42dde13..2a108ac0ac3 100644 --- a/components/esp_partition/include/esp_partition.h +++ b/components/esp_partition/include/esp_partition.h @@ -67,6 +67,12 @@ typedef enum { * @internal Keep this enum in sync with PartitionDefinition class gen_esp32part.py @endinternal */ typedef enum { + ESP_PARTITION_SUBTYPE_BOOTLOADER_PRIMARY = 0x00, //!< Primary Bootloader + ESP_PARTITION_SUBTYPE_BOOTLOADER_OTA = 0x01, //!< Temporary OTA storage for Bootloader, where the OTA uploads a new Bootloader image + + ESP_PARTITION_SUBTYPE_PARTITION_TABLE_PRIMARY = 0x00, //!< Primary Partition table + ESP_PARTITION_SUBTYPE_PARTITION_TABLE_OTA = 0x01, //!< Temporary OTA storage for Partition table, where the OTA uploads a new Partition table image + ESP_PARTITION_SUBTYPE_APP_FACTORY = 0x00, //!< Factory application partition ESP_PARTITION_SUBTYPE_APP_OTA_MIN = 0x10, //!< Base for OTA partition subtypes ESP_PARTITION_SUBTYPE_APP_OTA_0 = ESP_PARTITION_SUBTYPE_APP_OTA_MIN + 0, //!< OTA partition 0 diff --git a/components/esp_partition/partition_linux.c b/components/esp_partition/partition_linux.c index c85ac0ced8e..daeba669312 100644 --- a/components/esp_partition/partition_linux.c +++ b/components/esp_partition/partition_linux.c @@ -67,6 +67,8 @@ const char *esp_partition_type_to_str(const uint32_t type) switch (type) { case PART_TYPE_APP: return "app"; case PART_TYPE_DATA: return "data"; + case PART_TYPE_BOOTLOADER: return "bootloader"; + case PART_TYPE_PARTITION_TABLE: return "partition_table"; default: return "unknown"; } } @@ -74,6 +76,18 @@ const char *esp_partition_type_to_str(const uint32_t type) const char *esp_partition_subtype_to_str(const uint32_t type, const uint32_t subtype) { switch (type) { + case PART_TYPE_BOOTLOADER: + switch (subtype) { + case PART_SUBTYPE_BOOTLOADER_PRIMARY: return "primary"; + case PART_SUBTYPE_BOOTLOADER_OTA: return "ota"; + default: return "unknown"; + } + case PART_TYPE_PARTITION_TABLE: + switch (subtype) { + case PART_SUBTYPE_PARTITION_TABLE_PRIMARY: return "primary"; + case PART_SUBTYPE_PARTITION_TABLE_OTA: return "ota"; + default: return "unknown"; + } case PART_TYPE_APP: switch (subtype) { case PART_SUBTYPE_FACTORY: return "factory"; diff --git a/components/partition_table/gen_esp32part.py b/components/partition_table/gen_esp32part.py index cce5b78e916..6c6592b326c 100755 --- a/components/partition_table/gen_esp32part.py +++ b/components/partition_table/gen_esp32part.py @@ -7,11 +7,8 @@ # See https://docs.espressif.com/projects/esp-idf/en/latest/api-guides/partition-tables.html # for explanation of partition table structure and uses. # -# SPDX-FileCopyrightText: 2016-2023 Espressif Systems (Shanghai) CO LTD +# SPDX-FileCopyrightText: 2016-2024 Espressif Systems (Shanghai) CO LTD # SPDX-License-Identifier: Apache-2.0 - -from __future__ import division, print_function, unicode_literals - import argparse import binascii import errno @@ -36,8 +33,12 @@ APP_TYPE = 0x00 DATA_TYPE = 0x01 +BOOTLOADER_TYPE = 0x02 +PARTITION_TABLE_TYPE = 0x03 TYPES = { + 'bootloader': BOOTLOADER_TYPE, + 'partition_table': PARTITION_TABLE_TYPE, 'app': APP_TYPE, 'data': DATA_TYPE, } @@ -56,6 +57,14 @@ def get_ptype_as_int(ptype): # Keep this map in sync with esp_partition_subtype_t enum in esp_partition.h SUBTYPES = { + BOOTLOADER_TYPE: { + # 'primary': 0x00, # The tool does not allow to define this partition yet. + 'ota': 0x01, + }, + PARTITION_TABLE_TYPE: { + # 'primary': 0x00, # The tool does not allow to define this partition yet. + 'ota': 0x01, + }, APP_TYPE: { 'factory': 0x00, 'test': 0x20, @@ -90,6 +99,8 @@ def get_subtype_as_int(ptype, subtype): ALIGNMENT = { APP_TYPE: 0x10000, DATA_TYPE: 0x1000, + BOOTLOADER_TYPE: 0x1000, + PARTITION_TABLE_TYPE: 0x1000, } @@ -110,7 +121,7 @@ def get_alignment_size_for_type(ptype): else: # For no secure boot enabled case, app partition must be 4K aligned (min. flash erase size) return 0x1000 - # No specific size alignement requirement as such + # No specific size alignment requirement as such return 0x1 @@ -119,6 +130,10 @@ def get_partition_type(ptype): return APP_TYPE if ptype == 'data': return DATA_TYPE + if ptype == 'bootloader': + return BOOTLOADER_TYPE + if ptype == 'partition_table': + return PARTITION_TABLE_TYPE raise InputError('Invalid partition type') diff --git a/docs/en/api-guides/partition-tables.rst b/docs/en/api-guides/partition-tables.rst index 9da55858a1a..0ea3cb87c27 100644 --- a/docs/en/api-guides/partition-tables.rst +++ b/docs/en/api-guides/partition-tables.rst @@ -75,9 +75,13 @@ Name field can be any meaningful name. It is not significant to the {IDF_TARGET_ Type Field ~~~~~~~~~~ -Partition type field can be specified as ``app`` (0x00) or ``data`` (0x01). Or it can be a number 0-254 (or as hex 0x00-0xFE). Types 0x00-0x3F are reserved for ESP-IDF core functions. +Partition type field can be specified as a name or a number 0-254 (or as hex 0x00-0xFE). Types 0x00-0x3F are reserved for ESP-IDF core functions. -If your app needs to store data in a format not already supported by ESP-IDF, then please add a custom partition type value in the range 0x40-0xFE. +- ``app`` (0x00), +- ``data`` (0x01), +- ``bootloader`` (0x02). By default, this partition is not included in any CSV partition table files because it is not required and does not impact the system's functionality. It is only useful for the bootloader OTA update. Even if this partition is not present in the CSV file, it is still possible to perform the OTA. Please note that if you specify this partition in the CSV file, its address and size must match Kconfigs, +- ``partition_table`` (0x03), +- 0x40-0xFE are reserved for **custom partition types**. If your app needs to store data in a format not already supported by ESP-IDF, then use a value from this range. See :cpp:type:`esp_partition_type_t` for the enum definitions for ``app`` and ``data`` partitions. @@ -105,6 +109,16 @@ See enum :cpp:type:`esp_partition_subtype_t` for the full list of subtypes defin - ``ota_0`` (0x10) ... ``ota_15`` (0x1F) are the OTA app slots. When :doc:`OTA <../api-reference/system/ota>` is in use, the OTA data partition configures which app slot the bootloader should boot. When using OTA, an application should have at least two OTA application slots (``ota_0`` & ``ota_1``). Refer to the :doc:`OTA documentation <../api-reference/system/ota>` for more details. - ``test`` (0x20) is a reserved subtype for factory test procedures. It will be used as the fallback boot partition if no other valid app partition is found. It is also possible to configure the bootloader to read a GPIO input during each boot, and boot this partition if the GPIO is held low, see :ref:`bootloader_boot_from_test_firmware`. +* When type is ``bootloader``, the SubType field can be specified as: + + - ``primary`` (0x00). It is the so-called 2nd stage bootloader, which is placed at the {IDF_TARGET_CONFIG_BOOTLOADER_OFFSET_IN_FLASH} address in the flash. The ``gen_esp32part.py`` does not allow to have this partition in the CSV file for now. + - ``ota`` (0x01). It is a temporary bootloader partition used by the bootloader OTA update functionality for downloading a new image. + +* When type is ``partition_table``, the SubType field can be specified as: + + - ``primary`` (0x00). It is the primary partition table, which is placed at the :ref:`CONFIG_PARTITION_TABLE_OFFSET` address in the flash. The ``gen_esp32part.py`` does not allow to have this partition in the CSV file for now. + - ``ota`` (0x01). It is a temporary partition table partition used by the partition table OTA update functionality for downloading a new image. + * When type is ``data``, the subtype field can be specified as ``ota`` (0x00), ``phy`` (0x01), ``nvs`` (0x02), nvs_keys (0x04), or a range of other component-specific subtypes (see :cpp:type:`subtype enum `). - ``ota`` (0) is the :ref:`OTA data partition ` which stores information about the currently selected OTA app slot. This partition should be 0x2000 bytes in size. Refer to the :ref:`OTA documentation ` for more details. diff --git a/tools/test_apps/build_system/bootloader/sdkconfig.ci.verbose_logging b/tools/test_apps/build_system/bootloader/sdkconfig.ci.verbose_logging index 2ce67a363ce..06028d51aba 100644 --- a/tools/test_apps/build_system/bootloader/sdkconfig.ci.verbose_logging +++ b/tools/test_apps/build_system/bootloader/sdkconfig.ci.verbose_logging @@ -2,3 +2,4 @@ # Turn verbose log on for bootloader # CONFIG_BOOTLOADER_LOG_LEVEL_VERBOSE=y +CONFIG_PARTITION_TABLE_OFFSET=0xF000 From 20d1a480ab7acb2441a8dc60af3d9c8fc9336fea Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Adam=20M=C3=BAdry?= Date: Tue, 1 Oct 2024 15:04:13 +0200 Subject: [PATCH 024/472] feat(nvs): Add raw_data variable to NVS_Partition class in nvs_parser.py --- components/nvs_flash/nvs_partition_tool/nvs_parser.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/components/nvs_flash/nvs_partition_tool/nvs_parser.py b/components/nvs_flash/nvs_partition_tool/nvs_parser.py index 29b610b33b2..a4bb3dae570 100644 --- a/components/nvs_flash/nvs_partition_tool/nvs_parser.py +++ b/components/nvs_flash/nvs_partition_tool/nvs_parser.py @@ -64,8 +64,9 @@ def __init__(self, name: str, raw_data: bytearray): f'Given partition data is not aligned to page size ({len(raw_data)} % {nvs_const.page_size} = {len(raw_data)%nvs_const.page_size})' ) - # Divide partition into pages self.name = name + self.raw_data = raw_data + # Divide partition into pages self.pages = [] for i in range(0, len(raw_data), nvs_const.page_size): self.pages.append(NVS_Page(raw_data[i: i + nvs_const.page_size], i)) From 9a043e82afc2d64dc02e59c08963483403e4fe9b Mon Sep 17 00:00:00 2001 From: Erhan Kurubas Date: Fri, 13 Sep 2024 16:38:26 +0300 Subject: [PATCH 025/472] docs(esp32c61): remove coredump.rst from not updated list --- docs/docs_not_updated/esp32c61.txt | 1 - 1 file changed, 1 deletion(-) diff --git a/docs/docs_not_updated/esp32c61.txt b/docs/docs_not_updated/esp32c61.txt index 444a1b4d36c..7dfeaed03e7 100644 --- a/docs/docs_not_updated/esp32c61.txt +++ b/docs/docs_not_updated/esp32c61.txt @@ -1,4 +1,3 @@ -api-guides/core_dump_internals.rst api-guides/performance/speed.rst api-guides/performance/size.rst api-guides/performance/ram-usage.rst From 6d9905a90cf5ff2ee65358dc3aa094dabf6afde2 Mon Sep 17 00:00:00 2001 From: Erhan Kurubas Date: Fri, 13 Sep 2024 16:36:15 +0300 Subject: [PATCH 026/472] feat(esp-coredump): enable esp32c61 tests --- tools/test_apps/system/panic/pytest_panic.py | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/tools/test_apps/system/panic/pytest_panic.py b/tools/test_apps/system/panic/pytest_panic.py index d75f71224fb..d0c093e3575 100644 --- a/tools/test_apps/system/panic/pytest_panic.py +++ b/tools/test_apps/system/panic/pytest_panic.py @@ -29,6 +29,7 @@ pytest.mark.esp32c5, pytest.mark.esp32c6, pytest.mark.esp32h2, + pytest.mark.esp32c61, ] TARGETS_RISCV_DUAL_CORE = [ @@ -54,9 +55,8 @@ pytest.param('coredump_uart_bin_crc', marks=TARGETS_ALL), pytest.param('coredump_uart_elf_crc', marks=TARGETS_ALL), pytest.param('coredump_flash_custom_stack', marks=TARGETS_RISCV), - # TODO: Move esp32c61 to TARGETS_RISCV once Core Dump is supported (IDF-9268) - pytest.param('gdbstub', marks=TARGETS_ALL + [pytest.mark.esp32c61]), - pytest.param('panic', marks=TARGETS_ALL + [pytest.mark.esp32c61]), + pytest.param('gdbstub', marks=TARGETS_ALL), + pytest.param('panic', marks=TARGETS_ALL), ] CONFIGS_DUAL_CORE = [ @@ -85,7 +85,6 @@ pytest.param('coredump_flash_bin_crc', marks=TARGETS_RISCV), pytest.param('coredump_uart_bin_crc', marks=TARGETS_RISCV), pytest.param('coredump_uart_elf_crc', marks=TARGETS_RISCV), - # TODO: Add stack guard support to the ESP32-C61: IDF-9269 pytest.param('gdbstub', marks=TARGETS_RISCV), pytest.param('panic', marks=TARGETS_RISCV), ] @@ -981,7 +980,7 @@ def test_hw_stack_guard_cpu(dut: PanicTestDut, cpu: int) -> None: assert end_addr > start_addr -@pytest.mark.temp_skip_ci(targets=['esp32c5'], reason='TODO: IDF-8662') +@pytest.mark.temp_skip_ci(targets=['esp32c5', 'esp32c61'], reason='TODO: IDF-8662 and IDF-9269') @pytest.mark.parametrize('config', CONFIGS_HW_STACK_GUARD, indirect=True) @pytest.mark.generic def test_hw_stack_guard_cpu0(dut: PanicTestDut, config: str, test_func_name: str) -> None: @@ -990,7 +989,6 @@ def test_hw_stack_guard_cpu0(dut: PanicTestDut, config: str, test_func_name: str common_test(dut, config) -@pytest.mark.temp_skip_ci(targets=['esp32c5'], reason='TODO: IDF-8662') @pytest.mark.parametrize('config', CONFIGS_HW_STACK_GUARD_DUAL_CORE, indirect=True) @pytest.mark.generic def test_hw_stack_guard_cpu1(dut: PanicTestDut, config: str, test_func_name: str) -> None: @@ -1037,7 +1035,7 @@ def test_capture_dram(dut: PanicTestDut, config: str, test_func_name: str) -> No assert int(dut.gdb_data_eval_expr('g_cd_iram')) == 0x4243 assert int(dut.gdb_data_eval_expr('g_cd_dram')) == 0x4344 - if dut.target != 'esp32c2': + if dut.target not in ['esp32c61', 'esp32c2']: assert int(dut.gdb_data_eval_expr('g_rtc_data_var')) == 0x55AA assert int(dut.gdb_data_eval_expr('g_rtc_fast_var')) == 0xAABBCCDD From 1b82ca33eefe0384fd663dd4d0f03a7dd74090d2 Mon Sep 17 00:00:00 2001 From: Erhan Kurubas Date: Fri, 4 Oct 2024 22:22:31 +0200 Subject: [PATCH 027/472] ci(apptrace): enable build tests for all targets except esp32p4 --- examples/system/.build-test-rules.yml | 6 +++++- examples/system/app_trace_basic/README.md | 4 ++-- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/examples/system/.build-test-rules.yml b/examples/system/.build-test-rules.yml index ddb33070ef0..3152b243fde 100644 --- a/examples/system/.build-test-rules.yml +++ b/examples/system/.build-test-rules.yml @@ -2,9 +2,13 @@ examples/system/app_trace_basic: disable: + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: not ready yet. IDF-8107 + disable_test: - if: IDF_TARGET in ["esp32c6", "esp32h2", "esp32p4", "esp32c5", "esp32c61"] temporary: true - reason: targets not supported yet, TODO[C61] IDF-9264 IDF-10992 + reason: usb-serial-jtag tests are not stable yet. TODO[C61] IDF-10992 examples/system/base_mac_address: depends_components: diff --git a/examples/system/app_trace_basic/README.md b/examples/system/app_trace_basic/README.md index 2da31cd059a..72abab1b8da 100644 --- a/examples/system/app_trace_basic/README.md +++ b/examples/system/app_trace_basic/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | # Application Level Tracing Example (Basic) From 26c514ffe78fa0852626ea0f024f989031ecc7bc Mon Sep 17 00:00:00 2001 From: Abhinav Kudnar Date: Tue, 1 Oct 2024 20:01:17 +0800 Subject: [PATCH 028/472] fix(nimble): Fix the sequence of ll and host transport init --- components/bt/host/nimble/nimble | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/components/bt/host/nimble/nimble b/components/bt/host/nimble/nimble index 03462b6686c..87dd8bdc037 160000 --- a/components/bt/host/nimble/nimble +++ b/components/bt/host/nimble/nimble @@ -1 +1 @@ -Subproject commit 03462b6686cf49bb0bb026461300fec593c6f4c5 +Subproject commit 87dd8bdc0374572bfde0067b068fafb7bf2374e1 From 3d07895c8f3027257432f75604b3a52201ca00bc Mon Sep 17 00:00:00 2001 From: Roman Leonov Date: Tue, 18 Jun 2024 12:06:16 +0200 Subject: [PATCH 029/472] refactor(usb_host_examples): Enabled Hub support by default --- .../usb/test_apps/hcd/sdkconfig.defaults | 1 + .../usb/test_apps/usb_host/sdkconfig.defaults | 1 + .../host/cdc/cdc_acm_vcp/sdkconfig.defaults | 1 + .../usb/host/hid/sdkconfig.defaults | 4 + .../usb/host/msc/main/msc_example_main.c | 92 ++++--- .../usb/host/msc/sdkconfig.defaults | 4 + .../usb/host/usb_host_lib/main/class_driver.c | 254 ++++++++++++------ .../usb_host_lib/main/usb_host_lib_main.c | 49 ++-- .../usb/host/usb_host_lib/sdkconfig.defaults | 4 + 9 files changed, 258 insertions(+), 152 deletions(-) create mode 100644 examples/peripherals/usb/host/hid/sdkconfig.defaults create mode 100644 examples/peripherals/usb/host/msc/sdkconfig.defaults create mode 100644 examples/peripherals/usb/host/usb_host_lib/sdkconfig.defaults diff --git a/components/usb/test_apps/hcd/sdkconfig.defaults b/components/usb/test_apps/hcd/sdkconfig.defaults index 0632edf7579..d433503fbfd 100644 --- a/components/usb/test_apps/hcd/sdkconfig.defaults +++ b/components/usb/test_apps/hcd/sdkconfig.defaults @@ -6,3 +6,4 @@ CONFIG_HEAP_POISONING_COMPREHENSIVE=y # CONFIG_UNITY_ENABLE_FLOAT is not set # CONFIG_UNITY_ENABLE_DOUBLE is not set CONFIG_UNITY_ENABLE_BACKTRACE_ON_FAIL=y +CONFIG_USB_HOST_HUBS_SUPPORTED=y diff --git a/components/usb/test_apps/usb_host/sdkconfig.defaults b/components/usb/test_apps/usb_host/sdkconfig.defaults index 0632edf7579..d433503fbfd 100644 --- a/components/usb/test_apps/usb_host/sdkconfig.defaults +++ b/components/usb/test_apps/usb_host/sdkconfig.defaults @@ -6,3 +6,4 @@ CONFIG_HEAP_POISONING_COMPREHENSIVE=y # CONFIG_UNITY_ENABLE_FLOAT is not set # CONFIG_UNITY_ENABLE_DOUBLE is not set CONFIG_UNITY_ENABLE_BACKTRACE_ON_FAIL=y +CONFIG_USB_HOST_HUBS_SUPPORTED=y diff --git a/examples/peripherals/usb/host/cdc/cdc_acm_vcp/sdkconfig.defaults b/examples/peripherals/usb/host/cdc/cdc_acm_vcp/sdkconfig.defaults index 990777805d6..a3e635c9d8d 100644 --- a/examples/peripherals/usb/host/cdc/cdc_acm_vcp/sdkconfig.defaults +++ b/examples/peripherals/usb/host/cdc/cdc_acm_vcp/sdkconfig.defaults @@ -2,3 +2,4 @@ # Espressif IoT Development Framework (ESP-IDF) Project Minimal Configuration # CONFIG_COMPILER_CXX_EXCEPTIONS=y +CONFIG_USB_HOST_HUBS_SUPPORTED=y diff --git a/examples/peripherals/usb/host/hid/sdkconfig.defaults b/examples/peripherals/usb/host/hid/sdkconfig.defaults new file mode 100644 index 00000000000..bf1b553b238 --- /dev/null +++ b/examples/peripherals/usb/host/hid/sdkconfig.defaults @@ -0,0 +1,4 @@ +# This file was generated using idf.py save-defconfig. It can be edited manually. +# Espressif IoT Development Framework (ESP-IDF) Project Minimal Configuration +# +CONFIG_USB_HOST_HUBS_SUPPORTED=y diff --git a/examples/peripherals/usb/host/msc/main/msc_example_main.c b/examples/peripherals/usb/host/msc/main/msc_example_main.c index eb934a56810..630c95e6b15 100644 --- a/examples/peripherals/usb/host/msc/main/msc_example_main.c +++ b/examples/peripherals/usb/host/msc/main/msc_example_main.c @@ -29,6 +29,11 @@ static const char *TAG = "example"; #define APP_QUIT_PIN GPIO_NUM_0 // BOOT button on most boards #define BUFFER_SIZE 4096 // The read/write performance can be improved with larger buffer for the cost of RAM, 4kB is enough for most usecases +// IMPORTANT NOTE +// MSC Class Driver is not fully support connecting devices through external Hub. +// TODO: Remove this line after MSC Class Driver will support it +static bool dev_present = false; + /** * @brief Application Queue and its messages ID */ @@ -78,7 +83,7 @@ static void gpio_cb(void *arg) static void msc_event_cb(const msc_host_event_t *event, void *arg) { if (event->event == MSC_DEVICE_CONNECTED) { - ESP_LOGI(TAG, "MSC device connected"); + ESP_LOGI(TAG, "MSC device connected (usb_addr=%d)", event->device.address); app_message_t message = { .id = APP_DEVICE_CONNECTED, .data.new_dev_address = event->device.address, @@ -274,47 +279,56 @@ void app_main(void) xQueueReceive(app_queue, &msg, portMAX_DELAY); if (msg.id == APP_DEVICE_CONNECTED) { - // 1. MSC flash drive connected. Open it and map it to Virtual File System - ESP_ERROR_CHECK(msc_host_install_device(msg.data.new_dev_address, &msc_device)); - const esp_vfs_fat_mount_config_t mount_config = { - .format_if_mount_failed = false, - .max_files = 3, - .allocation_unit_size = 8192, - }; - ESP_ERROR_CHECK(msc_host_vfs_register(msc_device, MNT_PATH, &mount_config, &vfs_handle)); - - // 2. Print information about the connected disk - msc_host_device_info_t info; - ESP_ERROR_CHECK(msc_host_get_device_info(msc_device, &info)); - msc_host_print_descriptors(msc_device); - print_device_info(&info); - - // 3. List all the files in root directory - ESP_LOGI(TAG, "ls command output:"); - struct dirent *d; - DIR *dh = opendir(MNT_PATH); - assert(dh); - while ((d = readdir(dh)) != NULL) { - printf("%s\n", d->d_name); + if (dev_present) { + ESP_LOGW(TAG, "MSC Example handles only one device at a time"); + } else { + // 0. Change flag + dev_present = true; + // 1. MSC flash drive connected. Open it and map it to Virtual File System + ESP_ERROR_CHECK(msc_host_install_device(msg.data.new_dev_address, &msc_device)); + const esp_vfs_fat_mount_config_t mount_config = { + .format_if_mount_failed = false, + .max_files = 3, + .allocation_unit_size = 8192, + }; + ESP_ERROR_CHECK(msc_host_vfs_register(msc_device, MNT_PATH, &mount_config, &vfs_handle)); + + // 2. Print information about the connected disk + msc_host_device_info_t info; + ESP_ERROR_CHECK(msc_host_get_device_info(msc_device, &info)); + msc_host_print_descriptors(msc_device); + print_device_info(&info); + + // 3. List all the files in root directory + ESP_LOGI(TAG, "ls command output:"); + struct dirent *d; + DIR *dh = opendir(MNT_PATH); + assert(dh); + while ((d = readdir(dh)) != NULL) { + printf("%s\n", d->d_name); + } + closedir(dh); + + // 4. The disk is mounted to Virtual File System, perform some basic demo file operation + file_operations(); + + // 5. Perform speed test + speed_test(); + + ESP_LOGI(TAG, "Example finished, you can disconnect the USB flash drive"); } - closedir(dh); - - // 4. The disk is mounted to Virtual File System, perform some basic demo file operation - file_operations(); - - // 5. Perform speed test - speed_test(); - - ESP_LOGI(TAG, "Example finished, you can disconnect the USB flash drive"); } if ((msg.id == APP_DEVICE_DISCONNECTED) || (msg.id == APP_QUIT)) { - if (vfs_handle) { - ESP_ERROR_CHECK(msc_host_vfs_unregister(vfs_handle)); - vfs_handle = NULL; - } - if (msc_device) { - ESP_ERROR_CHECK(msc_host_uninstall_device(msc_device)); - msc_device = NULL; + if (dev_present) { + dev_present = false; + if (vfs_handle) { + ESP_ERROR_CHECK(msc_host_vfs_unregister(vfs_handle)); + vfs_handle = NULL; + } + if (msc_device) { + ESP_ERROR_CHECK(msc_host_uninstall_device(msc_device)); + msc_device = NULL; + } } if (msg.id == APP_QUIT) { // This will cause the usb_task to exit diff --git a/examples/peripherals/usb/host/msc/sdkconfig.defaults b/examples/peripherals/usb/host/msc/sdkconfig.defaults new file mode 100644 index 00000000000..bf1b553b238 --- /dev/null +++ b/examples/peripherals/usb/host/msc/sdkconfig.defaults @@ -0,0 +1,4 @@ +# This file was generated using idf.py save-defconfig. It can be edited manually. +# Espressif IoT Development Framework (ESP-IDF) Project Minimal Configuration +# +CONFIG_USB_HOST_HUBS_SUPPORTED=y diff --git a/examples/peripherals/usb/host/usb_host_lib/main/class_driver.c b/examples/peripherals/usb/host/usb_host_lib/main/class_driver.c index 594488df519..3b7077986f2 100644 --- a/examples/peripherals/usb/host/usb_host_lib/main/class_driver.c +++ b/examples/peripherals/usb/host/usb_host_lib/main/class_driver.c @@ -13,21 +13,40 @@ #define CLIENT_NUM_EVENT_MSG 5 typedef enum { - ACTION_OPEN_DEV = 0x01, - ACTION_GET_DEV_INFO = 0x02, - ACTION_GET_DEV_DESC = 0x04, - ACTION_GET_CONFIG_DESC = 0x08, - ACTION_GET_STR_DESC = 0x10, - ACTION_CLOSE_DEV = 0x20, - ACTION_EXIT = 0x40, - ACTION_RECONNECT = 0x80, + ACTION_OPEN_DEV = (1 << 0), + ACTION_GET_DEV_INFO = (1 << 1), + ACTION_GET_DEV_DESC = (1 << 2), + ACTION_GET_CONFIG_DESC = (1 << 3), + ACTION_GET_STR_DESC = (1 << 4), + ACTION_CLOSE_DEV = (1 << 5), } action_t; +#define DEV_MAX_COUNT 128 + typedef struct { usb_host_client_handle_t client_hdl; uint8_t dev_addr; usb_device_handle_t dev_hdl; - uint32_t actions; + action_t actions; +} usb_device_t; + +typedef struct { + struct { + union { + struct { + uint8_t unhandled_devices: 1; /**< Device has unhandled devices */ + uint8_t shutdown: 1; /**< */ + uint8_t reserved6: 6; /**< Reserved */ + }; + uint8_t val; /**< Class drivers' flags value */ + } flags; /**< Class drivers' flags */ + usb_device_t device[DEV_MAX_COUNT]; /**< Class drivers' static array of devices */ + } mux_protected; /**< Mutex protected members. Must be protected by the Class mux_lock when accessed */ + + struct { + usb_host_client_handle_t client_hdl; + SemaphoreHandle_t mux_lock; /**< Mutex for protected members */ + } constant; /**< Constant members. Do not change after installation thus do not require a critical section or mutex */ } class_driver_t; static const char *TAG = "CLASS"; @@ -38,79 +57,94 @@ static void client_event_cb(const usb_host_client_event_msg_t *event_msg, void * class_driver_t *driver_obj = (class_driver_t *)arg; switch (event_msg->event) { case USB_HOST_CLIENT_EVENT_NEW_DEV: - if (driver_obj->dev_addr == 0) { - driver_obj->dev_addr = event_msg->new_dev.address; - //Open the device next - driver_obj->actions |= ACTION_OPEN_DEV; - } + // Save the device address + xSemaphoreTake(driver_obj->constant.mux_lock, portMAX_DELAY); + driver_obj->mux_protected.device[event_msg->new_dev.address].dev_addr = event_msg->new_dev.address; + driver_obj->mux_protected.device[event_msg->new_dev.address].dev_hdl = NULL; + // Open the device next + driver_obj->mux_protected.device[event_msg->new_dev.address].actions |= ACTION_OPEN_DEV; + // Set flag + driver_obj->mux_protected.flags.unhandled_devices = 1; + xSemaphoreGive(driver_obj->constant.mux_lock); break; case USB_HOST_CLIENT_EVENT_DEV_GONE: - if (driver_obj->dev_hdl != NULL) { - //Cancel any other actions and close the device next - driver_obj->actions = ACTION_CLOSE_DEV; + // Cancel any other actions and close the device next + xSemaphoreTake(driver_obj->constant.mux_lock, portMAX_DELAY); + for (uint8_t i = 0; i < DEV_MAX_COUNT; i++) { + if (driver_obj->mux_protected.device[i].dev_hdl == event_msg->dev_gone.dev_hdl) { + driver_obj->mux_protected.device[i].actions = ACTION_CLOSE_DEV; + // Set flag + driver_obj->mux_protected.flags.unhandled_devices = 1; + } } + xSemaphoreGive(driver_obj->constant.mux_lock); break; default: - //Should never occur + // Should never occur abort(); } } -static void action_open_dev(class_driver_t *driver_obj) +static void action_open_dev(usb_device_t *device_obj) { - assert(driver_obj->dev_addr != 0); - ESP_LOGI(TAG, "Opening device at address %d", driver_obj->dev_addr); - ESP_ERROR_CHECK(usb_host_device_open(driver_obj->client_hdl, driver_obj->dev_addr, &driver_obj->dev_hdl)); - //Get the device's information next - driver_obj->actions &= ~ACTION_OPEN_DEV; - driver_obj->actions |= ACTION_GET_DEV_INFO; + assert(device_obj->dev_addr != 0); + ESP_LOGI(TAG, "Opening device at address %d", device_obj->dev_addr); + ESP_ERROR_CHECK(usb_host_device_open(device_obj->client_hdl, device_obj->dev_addr, &device_obj->dev_hdl)); + // Get the device's information next + device_obj->actions |= ACTION_GET_DEV_INFO; } -static void action_get_info(class_driver_t *driver_obj) +static void action_get_info(usb_device_t *device_obj) { - assert(driver_obj->dev_hdl != NULL); + assert(device_obj->dev_hdl != NULL); ESP_LOGI(TAG, "Getting device information"); usb_device_info_t dev_info; - ESP_ERROR_CHECK(usb_host_device_info(driver_obj->dev_hdl, &dev_info)); + ESP_ERROR_CHECK(usb_host_device_info(device_obj->dev_hdl, &dev_info)); ESP_LOGI(TAG, "\t%s speed", (char *[]) { "Low", "Full", "High" }[dev_info.speed]); - ESP_LOGI(TAG, "\tbConfigurationValue %d", dev_info.bConfigurationValue); + ESP_LOGI(TAG, "\tParent info:"); + if (dev_info.parent.dev_hdl) { + usb_device_info_t parent_dev_info; + ESP_ERROR_CHECK(usb_host_device_info(dev_info.parent.dev_hdl, &parent_dev_info)); + ESP_LOGI(TAG, "\t\tBus addr: %d", parent_dev_info.dev_addr); + ESP_LOGI(TAG, "\t\tPort: %d", dev_info.parent.port_num); - //Get the device descriptor next - driver_obj->actions &= ~ACTION_GET_DEV_INFO; - driver_obj->actions |= ACTION_GET_DEV_DESC; + } else { + ESP_LOGI(TAG, "\t\tPort: ROOT"); + } + ESP_LOGI(TAG, "\tbConfigurationValue %d", dev_info.bConfigurationValue); + // Get the device descriptor next + device_obj->actions |= ACTION_GET_DEV_DESC; } -static void action_get_dev_desc(class_driver_t *driver_obj) +static void action_get_dev_desc(usb_device_t *device_obj) { - assert(driver_obj->dev_hdl != NULL); + assert(device_obj->dev_hdl != NULL); ESP_LOGI(TAG, "Getting device descriptor"); const usb_device_desc_t *dev_desc; - ESP_ERROR_CHECK(usb_host_get_device_descriptor(driver_obj->dev_hdl, &dev_desc)); + ESP_ERROR_CHECK(usb_host_get_device_descriptor(device_obj->dev_hdl, &dev_desc)); usb_print_device_descriptor(dev_desc); - //Get the device's config descriptor next - driver_obj->actions &= ~ACTION_GET_DEV_DESC; - driver_obj->actions |= ACTION_GET_CONFIG_DESC; + // Get the device's config descriptor next + device_obj->actions |= ACTION_GET_CONFIG_DESC; } -static void action_get_config_desc(class_driver_t *driver_obj) +static void action_get_config_desc(usb_device_t *device_obj) { - assert(driver_obj->dev_hdl != NULL); + assert(device_obj->dev_hdl != NULL); ESP_LOGI(TAG, "Getting config descriptor"); const usb_config_desc_t *config_desc; - ESP_ERROR_CHECK(usb_host_get_active_config_descriptor(driver_obj->dev_hdl, &config_desc)); + ESP_ERROR_CHECK(usb_host_get_active_config_descriptor(device_obj->dev_hdl, &config_desc)); usb_print_config_descriptor(config_desc, NULL); - //Get the device's string descriptors next - driver_obj->actions &= ~ACTION_GET_CONFIG_DESC; - driver_obj->actions |= ACTION_GET_STR_DESC; + // Get the device's string descriptors next + device_obj->actions |= ACTION_GET_STR_DESC; } -static void action_get_str_desc(class_driver_t *driver_obj) +static void action_get_str_desc(usb_device_t *device_obj) { - assert(driver_obj->dev_hdl != NULL); + assert(device_obj->dev_hdl != NULL); usb_device_info_t dev_info; - ESP_ERROR_CHECK(usb_host_device_info(driver_obj->dev_hdl, &dev_info)); + ESP_ERROR_CHECK(usb_host_device_info(device_obj->dev_hdl, &dev_info)); if (dev_info.str_desc_manufacturer) { ESP_LOGI(TAG, "Getting Manufacturer string descriptor"); usb_print_string_descriptor(dev_info.str_desc_manufacturer); @@ -123,25 +157,59 @@ static void action_get_str_desc(class_driver_t *driver_obj) ESP_LOGI(TAG, "Getting Serial Number string descriptor"); usb_print_string_descriptor(dev_info.str_desc_serial_num); } - //Nothing to do until the device disconnects - driver_obj->actions &= ~ACTION_GET_STR_DESC; } -static void action_close_dev(class_driver_t *driver_obj) +static void action_close_dev(usb_device_t *device_obj) { - ESP_ERROR_CHECK(usb_host_device_close(driver_obj->client_hdl, driver_obj->dev_hdl)); - driver_obj->dev_hdl = NULL; - driver_obj->dev_addr = 0; - //We need to connect a new device - driver_obj->actions &= ~ACTION_CLOSE_DEV; - driver_obj->actions |= ACTION_RECONNECT; + ESP_ERROR_CHECK(usb_host_device_close(device_obj->client_hdl, device_obj->dev_hdl)); + device_obj->dev_hdl = NULL; + device_obj->dev_addr = 0; +} + +static void class_driver_device_handle(usb_device_t *device_obj) +{ + uint8_t actions = device_obj->actions; + device_obj->actions = 0; + + while (actions) { + if (actions & ACTION_OPEN_DEV) { + action_open_dev(device_obj); + } + if (actions & ACTION_GET_DEV_INFO) { + action_get_info(device_obj); + } + if (actions & ACTION_GET_DEV_DESC) { + action_get_dev_desc(device_obj); + } + if (actions & ACTION_GET_CONFIG_DESC) { + action_get_config_desc(device_obj); + } + if (actions & ACTION_GET_STR_DESC) { + action_get_str_desc(device_obj); + } + if (actions & ACTION_CLOSE_DEV) { + action_close_dev(device_obj); + } + + actions = device_obj->actions; + device_obj->actions = 0; + } } void class_driver_task(void *arg) { class_driver_t driver_obj = {0}; + usb_host_client_handle_t class_driver_client_hdl = NULL; ESP_LOGI(TAG, "Registering Client"); + + SemaphoreHandle_t mux_lock = xSemaphoreCreateMutex(); + if (mux_lock == NULL) { + ESP_LOGE(TAG, "Unable to create class driver mutex"); + vTaskDelete(NULL); + return; + } + usb_host_client_config_t client_config = { .is_synchronous = false, //Synchronous clients currently not supported. Set this to false .max_num_event_msg = CLIENT_NUM_EVENT_MSG, @@ -150,52 +218,62 @@ void class_driver_task(void *arg) .callback_arg = (void *) &driver_obj, }, }; - ESP_ERROR_CHECK(usb_host_client_register(&client_config, &driver_obj.client_hdl)); + ESP_ERROR_CHECK(usb_host_client_register(&client_config, &class_driver_client_hdl)); + + driver_obj.constant.mux_lock = mux_lock; + driver_obj.constant.client_hdl = class_driver_client_hdl; + + for (uint8_t i = 0; i < DEV_MAX_COUNT; i++) { + driver_obj.mux_protected.device[i].client_hdl = class_driver_client_hdl; + } + s_driver_obj = &driver_obj; while (1) { - if (driver_obj.actions == 0) { - usb_host_client_handle_events(driver_obj.client_hdl, portMAX_DELAY); - } else { - if (driver_obj.actions & ACTION_OPEN_DEV) { - action_open_dev(&driver_obj); + // Driver has unhandled devices, handle all devices first + if (driver_obj.mux_protected.flags.unhandled_devices) { + xSemaphoreTake(driver_obj.constant.mux_lock, portMAX_DELAY); + for (uint8_t i = 0; i < DEV_MAX_COUNT; i++) { + if (driver_obj.mux_protected.device[i].actions) { + class_driver_device_handle(&driver_obj.mux_protected.device[i]); + } } - if (driver_obj.actions & ACTION_GET_DEV_INFO) { - action_get_info(&driver_obj); - } - if (driver_obj.actions & ACTION_GET_DEV_DESC) { - action_get_dev_desc(&driver_obj); - } - if (driver_obj.actions & ACTION_GET_CONFIG_DESC) { - action_get_config_desc(&driver_obj); - } - if (driver_obj.actions & ACTION_GET_STR_DESC) { - action_get_str_desc(&driver_obj); - } - if (driver_obj.actions & ACTION_CLOSE_DEV) { - action_close_dev(&driver_obj); - } - if (driver_obj.actions & ACTION_EXIT) { + driver_obj.mux_protected.flags.unhandled_devices = 0; + xSemaphoreGive(driver_obj.constant.mux_lock); + } else { + // Driver is active, handle client events + if (driver_obj.mux_protected.flags.shutdown == 0) { + usb_host_client_handle_events(class_driver_client_hdl, portMAX_DELAY); + } else { + // Shutdown the driver break; } - if (driver_obj.actions & ACTION_RECONNECT) { - driver_obj.actions = 0; - } } } - ESP_LOGI(TAG, "Deregistering Client"); - ESP_ERROR_CHECK(usb_host_client_deregister(driver_obj.client_hdl)); - vTaskSuspend(NULL); + ESP_LOGI(TAG, "Deregistering Class Client"); + ESP_ERROR_CHECK(usb_host_client_deregister(class_driver_client_hdl)); + if (mux_lock != NULL) { + vSemaphoreDelete(mux_lock); + } + vTaskDelete(NULL); } void class_driver_client_deregister(void) { - if (s_driver_obj->dev_hdl != NULL) { - s_driver_obj->actions = ACTION_CLOSE_DEV; + // Mark all opened devices + xSemaphoreTake(s_driver_obj->constant.mux_lock, portMAX_DELAY); + for (uint8_t i = 0; i < DEV_MAX_COUNT; i++) { + if (s_driver_obj->mux_protected.device[i].dev_hdl != NULL) { + // Mark device to close + s_driver_obj->mux_protected.device[i].actions |= ACTION_CLOSE_DEV; + // Set flag + s_driver_obj->mux_protected.flags.unhandled_devices = 1; + } } - s_driver_obj->actions |= ACTION_EXIT; + s_driver_obj->mux_protected.flags.shutdown = 1; + xSemaphoreGive(s_driver_obj->constant.mux_lock); // Unblock, exit the loop and proceed to deregister client - ESP_ERROR_CHECK(usb_host_client_unblock(s_driver_obj->client_hdl)); + ESP_ERROR_CHECK(usb_host_client_unblock(s_driver_obj->constant.client_hdl)); } diff --git a/examples/peripherals/usb/host/usb_host_lib/main/usb_host_lib_main.c b/examples/peripherals/usb/host/usb_host_lib/main/usb_host_lib_main.c index e6c2a8df92d..f1a2dc348a5 100644 --- a/examples/peripherals/usb/host/usb_host_lib/main/usb_host_lib_main.c +++ b/examples/peripherals/usb/host/usb_host_lib/main/usb_host_lib_main.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Unlicense OR CC0-1.0 */ @@ -120,26 +120,26 @@ static void usb_host_lib_task(void *arg) xTaskNotifyGive(arg); bool has_clients = true; - bool has_devices = true; - while (has_clients || has_devices) { + bool has_devices = false; + while (has_clients) { uint32_t event_flags; ESP_ERROR_CHECK(usb_host_lib_handle_events(portMAX_DELAY, &event_flags)); if (event_flags & USB_HOST_LIB_EVENT_FLAGS_NO_CLIENTS) { - ESP_LOGI(TAG, "No more clients"); - has_clients = false; + ESP_LOGI(TAG, "Get FLAGS_NO_CLIENTS"); if (ESP_OK == usb_host_device_free_all()) { - ESP_LOGI(TAG, "All devices marked as free"); + ESP_LOGI(TAG, "All devices marked as free, no need to wait FLAGS_ALL_FREE event"); + has_clients = false; } else { - ESP_LOGI(TAG, "Wait for the ALL FREE EVENT"); + ESP_LOGI(TAG, "Wait for the FLAGS_ALL_FREE"); + has_devices = true; } } - if (event_flags & USB_HOST_LIB_EVENT_FLAGS_ALL_FREE) { - ESP_LOGI(TAG, "No more devices"); - has_devices = false; + if (has_devices && event_flags & USB_HOST_LIB_EVENT_FLAGS_ALL_FREE) { + ESP_LOGI(TAG, "Get FLAGS_ALL_FREE"); + has_clients = false; } - } - ESP_LOGI(TAG, "No more clients and devices"); + ESP_LOGI(TAG, "No more clients and devices, uninstall USB Host library"); //Uninstall the USB Host Library ESP_ERROR_CHECK(usb_host_uninstall()); @@ -167,7 +167,7 @@ void app_main(void) TaskHandle_t host_lib_task_hdl, class_driver_task_hdl; - //Create usb host lib task + // Create usb host lib task BaseType_t task_created; task_created = xTaskCreatePinnedToCore(usb_host_lib_task, "usb_host", @@ -178,19 +178,20 @@ void app_main(void) 0); assert(task_created == pdTRUE); - //Wait unit the USB host library is installed + // Wait unit the USB host library is installed ulTaskNotifyTake(false, 1000); - //Create class driver task + // Create class driver task task_created = xTaskCreatePinnedToCore(class_driver_task, "class", - 4096, + 5 * 1024, NULL, CLASS_TASK_PRIORITY, &class_driver_task_hdl, 0); assert(task_created == pdTRUE); - vTaskDelay(10); //Add a short delay to let the tasks run + // Add a short delay to let the tasks run + vTaskDelay(10); while (1) { if (xQueueReceive(app_event_queue, &evt_queue, portMAX_DELAY)) { @@ -198,22 +199,20 @@ void app_main(void) // User pressed button usb_host_lib_info_t lib_info; ESP_ERROR_CHECK(usb_host_lib_info(&lib_info)); - if (lib_info.num_devices == 0) { - // End while cycle - break; - } else { - ESP_LOGW(TAG, "To shutdown example, remove all USB devices and press button again."); - // Keep polling + if (lib_info.num_devices != 0) { + ESP_LOGW(TAG, "Shutdown with attached devices."); } + // End while cycle + break; } } } - //Deregister client + // Deregister client class_driver_client_deregister(); vTaskDelay(10); - //Delete the tasks + // Delete the tasks vTaskDelete(class_driver_task_hdl); vTaskDelete(host_lib_task_hdl); diff --git a/examples/peripherals/usb/host/usb_host_lib/sdkconfig.defaults b/examples/peripherals/usb/host/usb_host_lib/sdkconfig.defaults new file mode 100644 index 00000000000..bf1b553b238 --- /dev/null +++ b/examples/peripherals/usb/host/usb_host_lib/sdkconfig.defaults @@ -0,0 +1,4 @@ +# This file was generated using idf.py save-defconfig. It can be edited manually. +# Espressif IoT Development Framework (ESP-IDF) Project Minimal Configuration +# +CONFIG_USB_HOST_HUBS_SUPPORTED=y From 484a2d6d6cfe27a2fa8a0ffcd4a23be4010f0c54 Mon Sep 17 00:00:00 2001 From: Showier Drastic <168159404+showier-drastic@users.noreply.github.com> Date: Thu, 4 Jul 2024 10:50:34 +0800 Subject: [PATCH 030/472] feat(lwip/apps): only hand out DNS in DHCP if explicitly specified --- components/lwip/apps/dhcpserver/dhcpserver.c | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/components/lwip/apps/dhcpserver/dhcpserver.c b/components/lwip/apps/dhcpserver/dhcpserver.c index e6abfd743cf..60e6e15cd4f 100644 --- a/components/lwip/apps/dhcpserver/dhcpserver.c +++ b/components/lwip/apps/dhcpserver/dhcpserver.c @@ -454,18 +454,13 @@ static u8_t *add_offer_options(dhcps_t *dhcps, u8_t *optptr) } } - *optptr++ = DHCP_OPTION_DNS_SERVER; - *optptr++ = 4; if (dhcps_dns_enabled(dhcps->dhcps_dns)) { + *optptr++ = DHCP_OPTION_DNS_SERVER; + *optptr++ = 4; *optptr++ = ip4_addr1(&dhcps->dns_server); *optptr++ = ip4_addr2(&dhcps->dns_server); *optptr++ = ip4_addr3(&dhcps->dns_server); *optptr++ = ip4_addr4(&dhcps->dns_server); - }else { - *optptr++ = ip4_addr1(&ipadd); - *optptr++ = ip4_addr2(&ipadd); - *optptr++ = ip4_addr3(&ipadd); - *optptr++ = ip4_addr4(&ipadd); } ip4_addr_t broadcast_addr = { .addr = (ipadd.addr & dhcps->dhcps_mask.addr) | ~dhcps->dhcps_mask.addr }; From 649816d9a104796ea451b2d2b1c6bc4900ffb80d Mon Sep 17 00:00:00 2001 From: David Cermak Date: Tue, 1 Oct 2024 17:27:43 +0200 Subject: [PATCH 031/472] fix(lwip/dhcps): Fallback DNS option to DHCP server's IP by default Adds backward compatibity option CONFIG_LWIP_DHCPS_ADD_DNS, which prevents breaking changes. This option should be removed in IDF v6.0 Merges https://github.com/espressif/esp-idf/pull/14132 --- components/lwip/Kconfig | 14 ++++++++++++++ components/lwip/apps/dhcpserver/dhcpserver.c | 9 +++++++++ 2 files changed, 23 insertions(+) diff --git a/components/lwip/Kconfig b/components/lwip/Kconfig index 231536c39d8..c51fab4514b 100644 --- a/components/lwip/Kconfig +++ b/components/lwip/Kconfig @@ -433,6 +433,20 @@ menu "LWIP" Enabling this option allows DHCP server to support temporary static ARP entries for DHCP Client. This will help the DHCP server to send the DHCP OFFER and DHCP ACK using IP unicast. + config LWIP_DHCPS_ADD_DNS + bool "Always add DNS option in DHCP responses" + default y + depends on LWIP_DHCPS + help + This allows the DNS option to be optional in the DHCP offers, + depending on the server's runtime configuration. + When enabled, the DHCP server will always add the DNS option to DHCP responses. + If a DNS server is not explicitly configured, the server's IP address will be used + as the fallback for the DNS option. + When disabled, the DHCP server will only include the DNS option in responses + if a DNS server has been explicitly configured. + This option will be removed in IDF v6.x + endmenu # DHCPS menuconfig LWIP_AUTOIP diff --git a/components/lwip/apps/dhcpserver/dhcpserver.c b/components/lwip/apps/dhcpserver/dhcpserver.c index 60e6e15cd4f..8859e52c63b 100644 --- a/components/lwip/apps/dhcpserver/dhcpserver.c +++ b/components/lwip/apps/dhcpserver/dhcpserver.c @@ -461,6 +461,15 @@ static u8_t *add_offer_options(dhcps_t *dhcps, u8_t *optptr) *optptr++ = ip4_addr2(&dhcps->dns_server); *optptr++ = ip4_addr3(&dhcps->dns_server); *optptr++ = ip4_addr4(&dhcps->dns_server); +#ifdef CONFIG_LWIP_DHCPS_ADD_DNS + }else { + *optptr++ = DHCP_OPTION_DNS_SERVER; + *optptr++ = 4; + *optptr++ = ip4_addr1(&ipadd); + *optptr++ = ip4_addr2(&ipadd); + *optptr++ = ip4_addr3(&ipadd); + *optptr++ = ip4_addr4(&ipadd); +#endif /* CONFIG_LWIP_DHCPS_ADD_DNS */ } ip4_addr_t broadcast_addr = { .addr = (ipadd.addr & dhcps->dhcps_mask.addr) | ~dhcps->dhcps_mask.addr }; From 463149cad27bcb0f37b8ac6a9650840778914d2c Mon Sep 17 00:00:00 2001 From: Sarvesh Bodakhe Date: Wed, 22 May 2024 15:42:33 +0530 Subject: [PATCH 032/472] fix(wifi): Fix bug in wrong profile checking of AP's RSNXE IE --- components/esp_wifi/lib | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/components/esp_wifi/lib b/components/esp_wifi/lib index f3ea158d7c6..e5111a1452e 160000 --- a/components/esp_wifi/lib +++ b/components/esp_wifi/lib @@ -1 +1 @@ -Subproject commit f3ea158d7c62b1a4479f6c0174a02bc19fa59f90 +Subproject commit e5111a1452e6d5ae3474a7cbe1c151998537e10b From 9ebfd93c5d460ded5a157a0d4b2f23887b4e8dec Mon Sep 17 00:00:00 2001 From: Sarvesh Bodakhe Date: Mon, 30 Sep 2024 12:05:57 +0530 Subject: [PATCH 033/472] fix(wpa_supplicant): Fix debug print in wps_start_msg_timer() --- components/wpa_supplicant/esp_supplicant/src/esp_wps.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/components/wpa_supplicant/esp_supplicant/src/esp_wps.c b/components/wpa_supplicant/esp_supplicant/src/esp_wps.c index ae84728bf8a..c67413b1271 100644 --- a/components/wpa_supplicant/esp_supplicant/src/esp_wps.c +++ b/components/wpa_supplicant/esp_supplicant/src/esp_wps.c @@ -930,7 +930,7 @@ int wps_start_msg_timer(void) ret = 0; } else if (sm->wps->state == RECV_M2) { msg_timeout = 5; - wpa_printf(MSG_DEBUG, "start msg timer RECV_M2 %" PRId32 " ms", msg_timeout); + wpa_printf(MSG_DEBUG, "start msg timer RECV_M2 %" PRId32 " s", msg_timeout); eloop_cancel_timeout(wifi_station_wps_msg_timeout, NULL, NULL); eloop_register_timeout(msg_timeout, 0, wifi_station_wps_msg_timeout, NULL, NULL); ret = 0; From 9d32a3165747c6a74e92348a3a271589c4defc99 Mon Sep 17 00:00:00 2001 From: Alexey Lapshin Date: Fri, 4 Oct 2024 13:54:03 +0700 Subject: [PATCH 034/472] feat(tools): add binary size exceeded hint --- tools/idf_py_actions/hints.yml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/tools/idf_py_actions/hints.yml b/tools/idf_py_actions/hints.yml index f17f3fa2874..68181be0415 100644 --- a/tools/idf_py_actions/hints.yml +++ b/tools/idf_py_actions/hints.yml @@ -443,3 +443,7 @@ - re: "discarded output section: .*\\.got" hint: "Some objects being linked were compiled with the \"-fpic\"/\"-fpie\" options. These options may be suitable for \"linux\" builds, but must not be applied for esp32XX targets." + +- + re: "(error: Total discarded sections size is \\d+ bytes)|(region [`'.\\w]+ overflowed by \\d+ bytes)" + hint: "The binary size has exceeded the limit. To resolve the issue consider reducing the binary size.\nYou can explore size optimization techniques in the documentation by running 'idf.py docs -sp api-guides/performance/size.html#reducing-overall-size'.\nNote that the linker performed the dead code elimination." From 28ffd5fc04b58119d754941b7095d10a0378cddc Mon Sep 17 00:00:00 2001 From: Shen Weilong Date: Tue, 8 Oct 2024 11:01:42 +0800 Subject: [PATCH 035/472] update(ble): Modified the ble multi_conn example's readme --- .../nimble/ble_multi_conn/ble_multi_conn_cent/README.md | 2 ++ .../nimble/ble_multi_conn/ble_multi_conn_prph/README.md | 2 ++ 2 files changed, 4 insertions(+) diff --git a/examples/bluetooth/nimble/ble_multi_conn/ble_multi_conn_cent/README.md b/examples/bluetooth/nimble/ble_multi_conn/ble_multi_conn_cent/README.md index 6c32318b9fe..8f3339a66ec 100644 --- a/examples/bluetooth/nimble/ble_multi_conn/ble_multi_conn_cent/README.md +++ b/examples/bluetooth/nimble/ble_multi_conn/ble_multi_conn_cent/README.md @@ -5,6 +5,8 @@ (See the README.md file in the upper level 'examples' directory for more information about examples.) +**This example relies on the BLE controller. Currently, the ESP32/ESP32-C3/ESP32-S3/ESP32-C2 does not support the relevant vendor HCI, so please use the chip modules listed under Supported Targets.** + Please check the [tutorial](tutorial/Ble_Multiple_Connections_Central_Example_Walkthrough.md) for more information about this example. ## How to Use Example diff --git a/examples/bluetooth/nimble/ble_multi_conn/ble_multi_conn_prph/README.md b/examples/bluetooth/nimble/ble_multi_conn/ble_multi_conn_prph/README.md index 8035d1b6419..95d7358bbdd 100644 --- a/examples/bluetooth/nimble/ble_multi_conn/ble_multi_conn_prph/README.md +++ b/examples/bluetooth/nimble/ble_multi_conn/ble_multi_conn_prph/README.md @@ -5,6 +5,8 @@ (See the README.md file in the upper level 'examples' directory for more information about examples.) +**This example relies on the BLE controller. Currently, the ESP32/ESP32-C3/ESP32-S3/ESP32-C2 does not support the relevant vendor HCI, so please use the chip modules listed under Supported Targets.** + Please check the [tutorial](tutorial/Ble_Multiple_Connections_Peripheral_Example_Walkthrough.md) for more information about this example. ## How to Use Example From 808a82de812a8fb800752c6fcab26870619d8d74 Mon Sep 17 00:00:00 2001 From: Zhang Shuxian Date: Fri, 27 Sep 2024 19:19:40 +0800 Subject: [PATCH 036/472] docs: Update CN translation for secure-boot-v2.rst --- docs/en/security/secure-boot-v2.rst | 3 +- docs/zh_CN/security/secure-boot-v2.rst | 76 +++++++++++++++----------- 2 files changed, 46 insertions(+), 33 deletions(-) diff --git a/docs/en/security/secure-boot-v2.rst b/docs/en/security/secure-boot-v2.rst index 7cc0a8d2277..7fbe4011da5 100644 --- a/docs/en/security/secure-boot-v2.rst +++ b/docs/en/security/secure-boot-v2.rst @@ -637,8 +637,7 @@ Secure Boot Best Practices .. note:: - It may be necessary to revoke a key that isn't currently being used. - For example, if the active application is signed with key #0, but key #1 becomes compromised, you should revoke key #1 by using the above approach. The new OTA update should continue to be signed with key #0, and the API `esp_ota_revoke_secure_boot_public_key(SECURE_BOOT_PUBLIC_KEY_INDEX_[N])` can be used to revoke the key #N (N would be 1 in this case). After revoking, all remaining unrevoked keys can still be used to sign future applications. + It may be necessary to revoke a key that isn't currently being used. For example, if the active application is signed with key #0, but key #1 becomes compromised, you should revoke key #1 by using the above approach. The new OTA update should continue to be signed with key #0, and the API `esp_ota_revoke_secure_boot_public_key (SECURE_BOOT_PUBLIC_KEY_INDEX_[N])` can be used to revoke the key #N (N would be 1 in this case). After revoking, all remaining unrevoked keys can still be used to sign future applications. .. _secure-boot-v2-aggressive-key-revocation: diff --git a/docs/zh_CN/security/secure-boot-v2.rst b/docs/zh_CN/security/secure-boot-v2.rst index 640a32889eb..e9d2d400f06 100644 --- a/docs/zh_CN/security/secure-boot-v2.rst +++ b/docs/zh_CN/security/secure-boot-v2.rst @@ -29,7 +29,7 @@ .. only:: esp32 - 芯片版本低于 v3.0 的 ESP32 安全启动请参阅 :doc:`secure-boot-v1`。如果你的芯片版本支持安全启动 v2，推荐使用此模式，相比安全启动 v1 更安全且灵活。 + 芯片版本低于 v3.0 的 ESP32 安全启动请参阅 :doc:`secure-boot-v1`。如果当前芯片版本支持安全启动 v2，推荐使用此模式，相比安全启动 v1 更安全且灵活。 安全启动 v2 使用基于 {IDF_TARGET_SBV2_SCHEME} 的应用程序和引导加载程序 (bootloader) :ref:`second-stage-bootloader` 验证。若需要使用 {IDF_TARGET_SBV2_SCHEME} 方案对应用程序签名，且无需对 bootloader 签名，同样可以参考本文档。 @@ -83,10 +83,10 @@ - 芯片在量产时最多能生成并存储三个公钥。 - - {IDF_TARGET_NAME} 支持永久注销个别公钥，对此可以选择保守或激进的配置。 + - {IDF_TARGET_NAME} 支持永久撤销个别公钥，对此可以选择保守或激进的配置。 - - 保守配置：在此情况下，只有在 bootloader 和应用程序成功迁移到新密钥后才会注销旧密钥。 - - 激进配置：在此情况下，只要使用此密钥验证失败，就会立即注销该密钥。 + - 保守配置：在此情况下，只有在 bootloader 和应用程序成功迁移到新密钥后才会撤销旧密钥。 + - 激进配置：在此情况下，只要使用此密钥验证失败，就会立即撤销该密钥。 - 应用程序和软件 bootloader 采用相同的镜像格式和签名验证方法。 @@ -361,11 +361,11 @@ bootloader 大小 - BLOCK_KEYX - 该块包含其在 KEY_PURPOSE_X 中烧录的功能的对应数据，并存储公钥的 SHA-256 哈希摘要。公钥模数、指数、预先计算的 R 和 M' 值的 SHA-256 哈希摘要都将写入 eFuse 密钥块。这个摘要大小为 776 字节，偏移量从 36 到 812，如 :ref:`signature-block-format` 所示。注意，必须设置写保护位，但切勿设置读保护位。 - - KEY_REVOKEX - 与 3 个密钥块中的每一个相对应的注销标记。例如，设置 KEY_REVOKE2 将注销密钥功能为 SECURE_BOOT_DIGEST2 的密钥块。 + - KEY_REVOKEX - 与 3 个密钥块中的每一个相对应的撤销标记。例如，设置 KEY_REVOKE2 将撤销密钥功能为 SECURE_BOOT_DIGEST2 的密钥块。 - - SECURE_BOOT_AGGRESSIVE_REVOKE - 启用激进的密钥注销。只要与此密钥的验证失败，密钥就会立即注销。 + - SECURE_BOOT_AGGRESSIVE_REVOKE - 启用激进的密钥撤销。只要与此密钥的验证失败，密钥就会立即撤销。 - 为确保后续不会有攻击者添加受信任的密钥，应使用 KEY_REVOKEX 注销所有未使用的密钥摘要槽。若未启用 :ref:`CONFIG_SECURE_BOOT_ALLOW_UNUSED_DIGEST_SLOTS`，应用程序启动时，将在 :cpp:func:`esp_secure_boot_init_checks` 中检查和修复注销操作。 + 为确保后续不会有攻击者添加受信任的密钥，应使用 KEY_REVOKEX 撤销所有未使用的密钥摘要槽。若未启用 :ref:`CONFIG_SECURE_BOOT_ALLOW_UNUSED_DIGEST_SLOTS`，应用程序启动时，将在 :cpp:func:`esp_secure_boot_init_checks` 中检查和修复撤销操作。 密钥必须为可读密钥，以便软件访问。如果密钥设置了读保护，软件只能读取到全为零的数据，导致签名验证失败，启动中止。 @@ -407,15 +407,15 @@ bootloader 大小 7. 运行 ``idf.py bootloader`` 构建启用了安全启动的 bootloader ，构建输出中会包含一个烧录命令的提示，使用 ``esptool.py write_flash`` 烧录。 -8. 当你准备好烧录 bootloader 时，请运行指定命令并等待烧录完成。注意，此处的指定命令需要手动输入，构建系统不会执行此过程。 +8. 烧录 bootloader 前，请运行指定命令并等待烧录完成。注意，此处的指定命令需要手动输入，构建系统不会执行此过程。 9. 运行 ``idf.py flash`` 构建并烧录分区表以及刚刚构建的应用程序镜像，该镜像使用步骤 6 中生成的签名密钥进行签名。 .. note:: - 如果启用了安全启动，``idf.py flash`` 不会烧录 bootloader 。 + 如果启用了安全启动，``idf.py flash`` 不会烧录 bootloader。 -10. 重置 {IDF_TARGET_NAME}，它将启动你烧录的软件 bootloader 。该软件 bootloader 会在芯片上启用安全启动，然后验证应用程序镜像签名，并启动应用程序。请查看 {IDF_TARGET_NAME} 的串行控制器输出，确保已启用安全启动，且没有因构建配置发生错误。 +10. 重置 {IDF_TARGET_NAME} 将启动烧录的软件 bootloader。该软件 bootloader 会在芯片上启用安全启动，然后验证应用程序镜像签名，并启动应用程序。请查看 {IDF_TARGET_NAME} 的串行控制器输出，确保已启用安全启动，且没有因构建配置发生错误。 .. note:: @@ -435,16 +435,16 @@ bootloader 大小 - 注意，启用安全启动或 flash 加密会禁用 ROM 中的 USB-OTG USB 栈，阻止通过该端口进行串行仿真或设备固件更新 (DFU)。 +- 一旦启用安全启动，就无法再对 eFuse 密钥进行读保护，这可以避免攻击者对存储公共密钥摘要的 eFuse 块进行读保护，进而导致系统无法验证和处理签名，系统服务无法正常运行。有关读保护密钥的更多信息，请参阅下方详细说明。 + 烧录读保护密钥 ~~~~~~~~~~~~~~~ -一旦启用安全启动，就无法再对 eFuses 进行读保护，这可以避免攻击者对存储公共密钥摘要的 eFuse 块进行读保护，进而导致系统无法验证和处理签名，系统服务无法正常运行。 - -如果第二阶段 bootloader 启用了 :doc:`/security/flash-encryption`，它会确保在第一次启动时生成的 flash 加密密钥被读保护。 - -如需在设备启用安全启动后对密钥进行读保护，如： +**读保护密钥**： +以下密钥受到读保护后，相应的硬件将直接访问这些密钥（软件无法读取）： .. list:: + :SOC_FLASH_ENC_SUPPORTED:* flash 加密密钥 :SOC_HMAC_SUPPORTED:* HMAC 密钥 @@ -453,19 +453,28 @@ bootloader 大小 :SOC_KEY_MANAGER_SUPPORTED:* 密钥管理器密钥 -请在启用安全启动的同时启用配置项 :ref:`CONFIG_SECURE_BOOT_V2_ALLOW_EFUSE_RD_DIS`，以防止禁用 eFuses 读保护功能。 +**不受读保护的密钥**： +因软件访问需要（软件可读取），以下密钥不受读保护： + +.. list:: + + :SOC_SECURE_BOOT_SUPPORTED:* 安全启动公共密钥摘要 + * 用户数据 + +启用安全启动后，默认禁用 eFuses 读保护功能。如后续需在应用程序中对某个 eFuse（例如上述读保护密钥列表中的密钥）进行读保护，请在启用安全启动的同时启用配置项 :ref:`CONFIG_SECURE_BOOT_V2_ALLOW_EFUSE_RD_DIS`。 -建议在启用安全启动之前，完成全部密钥的烧录。 +建议在启用安全启动之前，完成全部密钥的烧录。如需启用配置项 :ref:`CONFIG_SECURE_BOOT_V2_ALLOW_EFUSE_RD_DIS`，请在所有读保护 eFuse 密钥烧录后，使用 :cpp:func:`esp_efuse_write_field_bit` 烧录 eFuse {IDF_TARGET_EFUSE_WR_DIS_RD_DIS}。 -如需启用配置项 :ref:`CONFIG_SECURE_BOOT_V2_ALLOW_EFUSE_RD_DIS`，请在所有读保护 eFuses 密钥烧录后，使用 ``esp_efuse.h`` 的 ``esp_efuse_write_field_bit()`` API 烧录 eFuses {IDF_TARGET_EFUSE_WR_DIS_RD_DIS}。 +.. note:: + 如果在启用安全启动时，第二阶段引导加载程序启用了 :doc:`/security/flash-encryption`，则首次启动时生成的 flash 加密密钥已经受到读保护。 .. _secure-boot-v2-generate-key: 生成安全启动签名密钥 ---------------------------------- -构建系统会提示你，使用 ``idf.py secure-generate-signing-key`` 命令生成新签名密钥。 +根据构建系统提示，使用 ``idf.py secure-generate-signing-key`` 命令生成新签名密钥。 .. only:: esp32 or SOC_SECURE_BOOT_V2_RSA @@ -522,7 +531,7 @@ bootloader 大小 idf.py secure-sign-data BINARY_FILE --keyfile PRIVATE_SIGNING_KEY -上述命令将镜像签名附加到现有的二进制文件中，你可以使用 `--output` 参数将签名后的二进制文件写入单独的文件： +上述命令将镜像签名附加到现有的二进制文件中，可以使用 `--output` 参数将签名后的二进制文件写入单独的文件： .. code-block:: @@ -532,7 +541,7 @@ bootloader 大小 使用预计算的签名进行签名 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -如果你拥有为镜像生成的有效预计算签名及相应公钥，你可以使用这些签名生成一个签名扇区，并将其附加到镜像中。注意，预计算的签名应计算在镜像中的所有字节，包括安全填充字节。 +如果存在为镜像生成的有效预计算签名及相应公钥，可以使用这些签名生成一个签名扇区，并将其附加到镜像中。注意，预计算的签名应计算在镜像中的所有字节，包括安全填充字节。 在此情况下，应禁用选项 :ref:`CONFIG_SECURE_BOOT_BUILD_SIGNED_BINARIES` 来构建固件镜像。该镜像将进行安全填充，并使用以下命令，生成带签名的二进制文件： @@ -546,7 +555,7 @@ bootloader 大小 使用外部硬件安全模块 (HSM) 进行签名 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -为了提高安全性，你可能会使用外部硬件安全模块 (HSM) 存储私钥，该私钥无法直接访问，但具备一个接口，可以生成二进制文件及其相应公钥的签名。 +为了提高安全性，可能需要使用外部硬件安全模块 (HSM) 存储私钥，该私钥无法直接访问，但具备一个接口，可以生成二进制文件及其相应公钥的签名。 在此情况下，请禁用选项 :ref:`CONFIG_SECURE_BOOT_BUILD_SIGNED_BINARIES` 并构建固件。随后，可以将已进行安全填充的镜像提供给外部硬件安全模块来生成签名。请参阅 `使用外部 HSM 签名 `_ 生成已签名镜像。 @@ -583,15 +592,15 @@ bootloader 大小 * 烧录 eFuse 可以由软件 bootloader 在首次从 menuconfig 启用 ``Secure Boot v2`` 后进行，也可以使用 ``espefuse.py``，后者与 ROM 中的串行 bootloader 通信。 * KEY_DIGEST 应从密钥摘要 #0 开始，按顺序编号。如果使用了密钥摘要 #1，则必须使用密钥摘要 #0。如果使用了密钥摘要 #2，则必须使用密钥摘要 #0 和 #1。 * 软件 bootloader 不支持 OTA 升级，它将至少由一个私钥签名，也可能使用全部三个私钥，并在工厂内烧录。 - * 应用程序应仅由单个私钥签名，其他私钥应妥善保管。但如果需要注销某些私钥，也可以使用多个签名私钥，请参阅下文的 :ref:`secure-boot-v2-key-revocation`。 + * 应用程序应仅由单个私钥签名，其他私钥应妥善保管。但如果需要撤销某些私钥，也可以使用多个签名私钥，请参阅下文的 :ref:`secure-boot-v2-key-revocation`。 多个密钥管理 ------------- * 在烧录 bootloader 之前，应使用设备整个生命周期所需的所有私钥对 bootloader 签名。 - * 构建系统每次只能使用一个私钥签名，如果需要，你必须手动运行命令以附加更多签名。 - * 你可以使用 ``idf.py secure-sign-data`` 的附加功能，此命令也将在启用安全启动 v2 的 bootloader 编译的末尾显示。 + * 构建系统每次只能使用一个私钥签名，如果需要，必须手动运行命令以附加更多签名。 + * 可以使用 ``idf.py secure-sign-data`` 的附加功能，此命令也将在启用安全启动 v2 的 bootloader 编译的末尾显示。 .. code-block:: @@ -606,10 +615,11 @@ bootloader 大小 .. _secure-boot-v2-key-revocation: - 注销密钥管理 + 撤销密钥管理 -------------- * 密钥按线性顺序处理，即密钥 #0、密钥 #1、密钥 #2。 + * 撤销一个密钥后，其余未被撤销的密钥仍可用于应用程序签名。例如，如密钥 #1 被撤销，仍然可以使用密钥 #0 和密钥 #2 给应用程序签名。 * 应用程序每次应只使用一个密钥签名，尽量避免暴露未使用的私钥。 * bootloader 可以使用来自工厂的多个函数签名。 @@ -629,24 +639,28 @@ bootloader 大小 3. 验证新应用程序的签名块。对比公钥与 eFuse 中烧录的摘要，并使用已验证的公钥验证应用程序。 4. 将活动分区设置为新的 OTA 应用程序分区。 5. 设备重置并加载使用密钥 #N-1 验证的 bootloader ，随后启动使用密钥 #N 验证的新应用程序。 - 6. 新应用程序使用密钥 #N 验证 bootloader ，这是最后的检查，然后运行代码注销密钥 #N-1，即设置 KEY_REVOKE eFuse 位。 - 7. 可以使用 API `esp_ota_revoke_secure_boot_public_key()` 注销密钥 #N-1。 + 6. 新应用程序使用密钥 #N 验证 bootloader ，这是最后的检查，然后运行代码撤销密钥 #N-1，即设置 KEY_REVOKE eFuse 位。 + 7. 可以使用 API :cpp:func:`esp_ota_revoke_secure_boot_public_key` 撤销密钥 #N-1。 * 类似的方法也可以用于物理重新烧录，以使用新的密钥，还可以同时更改 bootloader 的内容。 + .. note:: + + 当前未使用的密钥可以被撤销。例如，如果活动应用程序由密钥 #0 签名，但密钥 #1 已被泄露，请通过上述方法撤销密钥 #1。新的 OTA 更新应继续使用密钥 #0 签名，并且可以使用 API `esp_ota_revoke_secure_boot_public_key (SECURE_BOOT_PUBLIC_KEY_INDEX_[N])` 来撤销密钥 #N（在此例中，N 为 1）。撤销该密钥后，其余密钥以后仍可用于给应用程序签名。 + .. _secure-boot-v2-aggressive-key-revocation: 激进方法 ~~~~~~~~~~~~~~ - ROM 代码具备一项额外功能，即在签名验证失败时可以注销公钥摘要。 + ROM 代码具备一项额外功能，即在签名验证失败时可以撤销公钥摘要。 请烧录 ``SECURE_BOOT_AGGRESSIVE_REVOKE`` eFuse 或启用 :ref:`CONFIG_SECURE_BOOT_ENABLE_AGGRESSIVE_KEY_REVOKE` 以启用此功能。 - 注销密钥仅适用于成功启用了安全启动的情况。此外，在签名块无效或镜像摘要无效的情况下不会注销密钥，仅在签名验证失败时，即在 :ref:`verify_image` 的第 3 步中验证失败时，才会执行注销操作。 + 撤销密钥仅适用于成功启用了安全启动的情况。此外，在签名块无效或镜像摘要无效的情况下不会撤销密钥，仅在签名验证失败时，即在 :ref:`verify_image` 的第 3 步中验证失败时，才会执行撤销操作。 - 一旦注销了密钥，它将无法再用于验证镜像签名。该功能提供了强大的物理攻击防护，但如果由于签名验证失败而注销了所有密钥，可能会导致设备再也无法使用。 + 一旦撤销了密钥，它将无法再用于验证镜像签名。该功能提供了强大的物理攻击防护，但如果由于签名验证失败而撤销了所有密钥，可能会导致设备再也无法使用。 .. _secure-boot-v2-technical-details: From 5126742003f8eb5c10648679393c500d3a66009a Mon Sep 17 00:00:00 2001 From: zhanghaipeng Date: Sat, 21 Sep 2024 16:21:30 +0800 Subject: [PATCH 037/472] fix(ble/bluedroid): Fixed error when writing Client Supported Features characteristic --- .../bt/host/bluedroid/stack/gatt/gatt_db.c | 44 +++++++++++-------- 1 file changed, 25 insertions(+), 19 deletions(-) diff --git a/components/bt/host/bluedroid/stack/gatt/gatt_db.c b/components/bt/host/bluedroid/stack/gatt/gatt_db.c index efae6413ad2..8844ef5dc8e 100644 --- a/components/bt/host/bluedroid/stack/gatt/gatt_db.c +++ b/components/bt/host/bluedroid/stack/gatt/gatt_db.c @@ -60,7 +60,7 @@ static BOOLEAN gatts_add_char_desc_value_check (tGATT_ATTR_VAL *attr_val, tGATTS ** Parameter p_db: database pointer. ** len: size of the memory space. ** -** Returns Status of te operation. +** Returns Status of the operation. ** *******************************************************************************/ BOOLEAN gatts_init_service_db (tGATT_SVC_DB *p_db, tBT_UUID *p_service, BOOLEAN is_pri, @@ -94,7 +94,7 @@ BOOLEAN gatts_init_service_db (tGATT_SVC_DB *p_db, tBT_UUID *p_service, BOOLEAN ** Parameter p_db: database pointer. ** len: size of the memory space. ** -** Returns Status of te operation. +** Returns Status of the operation. ** *******************************************************************************/ tBT_UUID *gatts_get_service_uuid (tGATT_SVC_DB *p_db) @@ -497,14 +497,14 @@ UINT16 gatts_add_included_service (tGATT_SVC_DB *p_db, UINT16 s_handle, UINT16 e ** Function gatts_add_characteristic ** ** Description This function add a characteristics and its descriptor into -** a servce identified by the service database pointer. +** a service identified by the service database pointer. ** ** Parameter p_db: database pointer. ** perm: permission (authentication and key size requirements) ** property: property of the characteristic. ** p_char: characteristic value information. ** -** Returns Status of te operation. +** Returns Status of the operation. ** *******************************************************************************/ UINT16 gatts_add_characteristic (tGATT_SVC_DB *p_db, tGATT_PERM perm, @@ -1173,40 +1173,40 @@ tGATT_STATUS gatts_write_attr_perm_check (tGATT_SVC_DB *p_db, UINT8 op_code, if ((op_code == GATT_SIGN_CMD_WRITE) && !(perm & GATT_WRITE_SIGNED_PERM)) { status = GATT_WRITE_NOT_PERMIT; - GATT_TRACE_DEBUG( "gatts_write_attr_perm_check - sign cmd write not allowed,handle:0x%04x",handle); + GATT_TRACE_DEBUG( "gatts_write_attr_perm_check - sign cmd write not allowed,handle %04x,perm %04x", handle, perm); } if ((op_code == GATT_SIGN_CMD_WRITE) && (sec_flag & GATT_SEC_FLAG_ENCRYPTED)) { status = GATT_INVALID_PDU; - GATT_TRACE_ERROR( "gatts_write_attr_perm_check - Error!! sign cmd write sent on a encypted link,handle:0x%04x",handle); + GATT_TRACE_ERROR( "gatts_write_attr_perm_check - Error!! sign cmd write sent on a encrypted link,handle %04x,perm %04x", handle, perm); } else if (!(perm & GATT_WRITE_ALLOWED)) { status = GATT_WRITE_NOT_PERMIT; - GATT_TRACE_ERROR( "gatts_write_attr_perm_check - GATT_WRITE_NOT_PERMIT,handle:0x%04x",handle); + GATT_TRACE_ERROR("gatts_write_attr_perm_check - GATT_WRITE_NOT_PERMIT,handle %04x, perm %04x", handle, perm); } /* require authentication, but not been authenticated */ else if ((perm & GATT_WRITE_AUTH_REQUIRED ) && !(sec_flag & GATT_SEC_FLAG_LKEY_UNAUTHED)) { status = GATT_INSUF_AUTHENTICATION; - GATT_TRACE_ERROR( "gatts_write_attr_perm_check - GATT_INSUF_AUTHENTICATION,handle:0x%04x",handle); + GATT_TRACE_ERROR( "gatts_write_attr_perm_check - GATT_INSUF_AUTHENTICATION,handle %04x, perm %04x", handle, perm); } else if ((perm & GATT_WRITE_MITM_REQUIRED ) && !(sec_flag & GATT_SEC_FLAG_LKEY_AUTHED)) { status = GATT_INSUF_AUTHENTICATION; - GATT_TRACE_ERROR( "gatts_write_attr_perm_check - GATT_INSUF_AUTHENTICATION: MITM required,handle:0x%04x",handle); + GATT_TRACE_ERROR( "gatts_write_attr_perm_check - GATT_INSUF_AUTHENTICATION: MITM required,handle %04x,perm %04x", handle, perm); } else if ((perm & GATT_WRITE_ENCRYPTED_PERM ) && !(sec_flag & GATT_SEC_FLAG_ENCRYPTED)) { status = GATT_INSUF_ENCRYPTION; - GATT_TRACE_ERROR( "gatts_write_attr_perm_check - GATT_INSUF_ENCRYPTION,handle:0x%04x",handle); + GATT_TRACE_ERROR( "gatts_write_attr_perm_check - GATT_INSUF_ENCRYPTION,handle:0x%04x, perm:0x%04x", handle, perm); } else if ((perm & GATT_WRITE_ENCRYPTED_PERM ) && (sec_flag & GATT_SEC_FLAG_ENCRYPTED) && (key_size < min_key_size)) { status = GATT_INSUF_KEY_SIZE; - GATT_TRACE_ERROR( "gatts_write_attr_perm_check - GATT_INSUF_KEY_SIZE,handle:0x%04x",handle); + GATT_TRACE_ERROR( "gatts_write_attr_perm_check - GATT_INSUF_KEY_SIZE,handle %04x,perm %04x", handle, perm); } /* LE Authorization check*/ else if ((perm & GATT_WRITE_AUTHORIZATION) && (!(sec_flag & GATT_SEC_FLAG_LKEY_AUTHED) || !(sec_flag & GATT_SEC_FLAG_AUTHORIZATION))){ status = GATT_INSUF_AUTHORIZATION; - GATT_TRACE_ERROR( "gatts_write_attr_perm_check - GATT_INSUF_AUTHORIZATION,handle:0x%04x",handle); + GATT_TRACE_ERROR( "gatts_write_attr_perm_check - GATT_INSUF_AUTHORIZATION,handle %04x,perm %04x", handle, perm); } /* LE security mode 2 attribute */ else if (perm & GATT_WRITE_SIGNED_PERM && op_code != GATT_SIGN_CMD_WRITE && !(sec_flag & GATT_SEC_FLAG_ENCRYPTED) && (perm & GATT_WRITE_ALLOWED) == 0) { status = GATT_INSUF_AUTHENTICATION; - GATT_TRACE_ERROR( "gatts_write_attr_perm_check - GATT_INSUF_AUTHENTICATION: LE security mode 2 required,handle:0x%04x",handle); - } else { /* writable: must be char value declaration or char descritpors */ + GATT_TRACE_ERROR( "gatts_write_attr_perm_check - GATT_INSUF_AUTHENTICATION: LE security mode 2 required,handle %04x,perm %04x", handle, perm); + } else { /* writable: must be char value declaration or char descriptors */ if (p_attr->uuid_type == GATT_ATTR_UUID_TYPE_16) { switch (p_attr->uuid) { case GATT_UUID_CHAR_PRESENT_FORMAT:/* should be readable only */ @@ -1215,13 +1215,19 @@ tGATT_STATUS gatts_write_attr_perm_check (tGATT_SVC_DB *p_db, UINT8 op_code, case GATT_UUID_CHAR_VALID_RANGE: status = GATT_WRITE_NOT_PERMIT; break; - + case GATT_UUID_GAP_ICON:/* The Appearance characteristic value shall be 2 octets in length */ case GATT_UUID_CHAR_CLIENT_CONFIG: /* coverity[MISSING_BREAK] */ /* intnended fall through, ignored */ /* fall through */ case GATT_UUID_CHAR_SRVR_CONFIG: max_size = 2; + status = GATT_SUCCESS; + break; + case GATT_UUID_CLIENT_SUP_FEAT: + max_size = 1; + status = GATT_SUCCESS; + break; case GATT_UUID_CHAR_DESCRIPTION: default: /* any other must be character value declaration */ status = GATT_SUCCESS; @@ -1242,17 +1248,17 @@ tGATT_STATUS gatts_write_attr_perm_check (tGATT_SVC_DB *p_db, UINT8 op_code, else if ( (p_attr->uuid_type == GATT_ATTR_UUID_TYPE_16) && (p_attr->uuid == GATT_UUID_CHAR_CLIENT_CONFIG || p_attr->uuid == GATT_UUID_CHAR_SRVR_CONFIG || - p_attr->uuid == GATT_UUID_CLIENT_SUP_FEAT || + p_attr->uuid == GATT_UUID_CLIENT_SUP_FEAT || p_attr->uuid == GATT_UUID_GAP_ICON ) ) // btla-specific -- { if (op_code == GATT_REQ_PREPARE_WRITE) { /* does not allow write blob */ status = GATT_REQ_NOT_SUPPORTED; - GATT_TRACE_ERROR( "gatts_write_attr_perm_check - GATT_REQ_NOT_SUPPORTED,handle:0x%04x",handle); + GATT_TRACE_ERROR("gatts_write_attr_perm_check - GATT_REQ_NOT_SUPPORTED,handle %04x,opcode %4x", handle, op_code); } else if (len != max_size) { /* data does not match the required format */ status = GATT_INVALID_ATTR_LEN; - GATT_TRACE_ERROR( "gatts_write_attr_perm_check - GATT_INVALID_ATTR_LEN,handle:0x%04x",handle); + GATT_TRACE_ERROR("gatts_write_attr_perm_check - GATT_INVALID_ATTR_LEN,handle %04x,op_code %04x,len %d,max_size %d", handle, op_code, len, max_size); } else { status = GATT_SUCCESS; } @@ -1554,7 +1560,7 @@ static BOOLEAN gatts_db_add_service_declaration(tGATT_SVC_DB *p_db, tBT_UUID *p_ uuid.uu.uuid16 = GATT_UUID_SEC_SERVICE; } - /* add service declration record */ + /* add service declaration record */ if ((p_attr = (tGATT_ATTR16 *)(allocate_attr_in_db(p_db, &uuid, GATT_PERM_READ))) != NULL) { if (copy_extra_byte_in_db (p_db, (void **)&p_attr->p_value, sizeof(tBT_UUID))) { if (p_service->len == LEN_UUID_16) { From e1423c53d5e994fc7967373423122fd80b807aa0 Mon Sep 17 00:00:00 2001 From: "chaijie@espressif.com" Date: Fri, 23 Aug 2024 14:31:49 +0800 Subject: [PATCH 038/472] feat(pwr_glitch): Add power glitch support on esp32c5/esp32c61 --- .../private_include/bootloader_soc.h | 8 +++ .../src/esp32c5/bootloader_esp32c5.c | 5 +- .../src/esp32c5/bootloader_soc.c | 29 ++++++--- .../src/esp32c61/bootloader_esp32c61.c | 6 +- .../src/esp32c61/bootloader_soc.c | 30 ++++++--- .../hal/esp32c5/include/hal/brownout_ll.h | 2 - .../hal/esp32c61/include/hal/brownout_ll.h | 2 - .../esp32c5/include/soc/lp_analog_peri_reg.h | 5 ++ .../soc/esp32c5/include/soc/regi2c_saradc.h | 16 +++++ .../esp32c61/include/soc/lp_analog_peri_reg.h | 5 ++ .../soc/esp32c61/include/soc/regi2c_saradc.h | 61 ++++++++++++------- 11 files changed, 119 insertions(+), 50 deletions(-) diff --git a/components/bootloader_support/private_include/bootloader_soc.h b/components/bootloader_support/private_include/bootloader_soc.h index d854112f638..acce77cfb6c 100644 --- a/components/bootloader_support/private_include/bootloader_soc.h +++ b/components/bootloader_support/private_include/bootloader_soc.h @@ -24,6 +24,14 @@ void bootloader_ana_super_wdt_reset_config(bool enable); */ void bootloader_ana_clock_glitch_reset_config(bool enable); +/** + * @brief Configure analog power glitch reset & glitch reset dref + * + * @param enable Boolean to enable or disable power glitch reset + * @param dref voltage threshold + */ +void bootloader_power_glitch_reset_config(bool enable, uint8_t dref); + #ifdef __cplusplus } #endif diff --git a/components/bootloader_support/src/esp32c5/bootloader_esp32c5.c b/components/bootloader_support/src/esp32c5/bootloader_esp32c5.c index 0f53f259ad5..02b83fc1e8c 100644 --- a/components/bootloader_support/src/esp32c5/bootloader_esp32c5.c +++ b/components/bootloader_support/src/esp32c5/bootloader_esp32c5.c @@ -92,11 +92,10 @@ static inline void bootloader_hardware_init(void) static inline void bootloader_ana_reset_config(void) { - // TODO: [ESP32C5] IDF-8650 - //Enable super WDT reset. - // bootloader_ana_super_wdt_reset_config(true); //Enable BOD reset (mode1) brownout_ll_ana_reset_enable(true); + uint8_t power_glitch_dref = 0; + bootloader_power_glitch_reset_config(true, power_glitch_dref); } esp_err_t bootloader_init(void) diff --git a/components/bootloader_support/src/esp32c5/bootloader_soc.c b/components/bootloader_support/src/esp32c5/bootloader_soc.c index 95238f511e9..1e4335491b9 100644 --- a/components/bootloader_support/src/esp32c5/bootloader_soc.c +++ b/components/bootloader_support/src/esp32c5/bootloader_soc.c @@ -7,18 +7,29 @@ #include #include "soc/soc.h" #include "soc/lp_analog_peri_reg.h" -// TODO: [ESP32C5] IDF-8667 remove esp_log.h -#include "esp_log.h" - -void bootloader_ana_super_wdt_reset_config(bool enable) -{ - // TODO: [ESP32C5] IDF-8667 - ESP_EARLY_LOGW("bootloader", "bootloader_ana_super_wdt_reset_config() has not been implemented on C5 yet"); -} +#include "soc/pmu_reg.h" +#include "hal/regi2c_ctrl.h" +#include "soc/regi2c_saradc.h" //Not supported but common bootloader calls the function. Do nothing void bootloader_ana_clock_glitch_reset_config(bool enable) { - // TODO: [ESP32C5] IDF-8667, PM-207 (void)enable; } + +void bootloader_power_glitch_reset_config(bool enable, uint8_t dref) +{ + assert(dref < 8); + REG_SET_FIELD(LP_ANA_FIB_ENABLE_REG, LP_ANA_ANA_FIB_PWR_GLITCH_ENA, 0); + if (enable) { + SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_PERIF_I2C_RSTB); + SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_PERIF_I2C); + REGI2C_WRITE_MASK(I2C_SAR_ADC, POWER_GLITCH_DREF_VDET_PERIF, dref); + REGI2C_WRITE_MASK(I2C_SAR_ADC, POWER_GLITCH_DREF_VDET_VDDPST, dref); + REGI2C_WRITE_MASK(I2C_SAR_ADC, POWER_GLITCH_DREF_VDET_XTAL, dref); + REGI2C_WRITE_MASK(I2C_SAR_ADC, POWER_GLITCH_DREF_VDET_PLL, dref); + REG_SET_FIELD(LP_ANA_CK_GLITCH_CNTL_REG, LP_ANA_PWR_GLITCH_RESET_ENA, 0xf); + } else { + REG_SET_FIELD(LP_ANA_CK_GLITCH_CNTL_REG, LP_ANA_PWR_GLITCH_RESET_ENA, 0); + } +} diff --git a/components/bootloader_support/src/esp32c61/bootloader_esp32c61.c b/components/bootloader_support/src/esp32c61/bootloader_esp32c61.c index 8d62e4746e8..d9b65d3e33b 100644 --- a/components/bootloader_support/src/esp32c61/bootloader_esp32c61.c +++ b/components/bootloader_support/src/esp32c61/bootloader_esp32c61.c @@ -93,17 +93,17 @@ static inline void bootloader_hardware_init(void) static inline void bootloader_ana_reset_config(void) { - //Enable super WDT reset. - bootloader_ana_super_wdt_reset_config(true); //Enable BOD reset (mode1) brownout_ll_ana_reset_enable(true); + uint8_t power_glitch_dref = 0; + bootloader_power_glitch_reset_config(true, power_glitch_dref); } esp_err_t bootloader_init(void) { esp_err_t ret = ESP_OK; bootloader_hardware_init(); - // bootloader_ana_reset_config(); //TODO: [ESP32C61] IDF-9260 + bootloader_ana_reset_config(); bootloader_super_wdt_auto_feed(); // In RAM_APP, memory will be initialized in `call_start_cpu0` diff --git a/components/bootloader_support/src/esp32c61/bootloader_soc.c b/components/bootloader_support/src/esp32c61/bootloader_soc.c index e2876607d66..055fe372bdd 100644 --- a/components/bootloader_support/src/esp32c61/bootloader_soc.c +++ b/components/bootloader_support/src/esp32c61/bootloader_soc.c @@ -7,19 +7,29 @@ #include #include "soc/soc.h" #include "soc/lp_analog_peri_reg.h" - -//TODO: [ESP32C61] IDF-9260, commented in verify code, check - -void bootloader_ana_super_wdt_reset_config(bool enable) -{ - //C61 doesn't support bypass super WDT reset - assert(enable); - // lp_analog_peri_reg.h updated, now following registers - // REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_FIB_ENABLE_REG, LP_ANALOG_PERI_LP_ANA_FIB_SUPER_WDT_RST); -} +#include "soc/pmu_reg.h" +#include "hal/regi2c_ctrl.h" +#include "soc/regi2c_saradc.h" //Not supported but common bootloader calls the function. Do nothing void bootloader_ana_clock_glitch_reset_config(bool enable) { (void)enable; } + +void bootloader_power_glitch_reset_config(bool enable, uint8_t dref) +{ + assert(dref < 8); + REG_SET_FIELD(LP_ANA_FIB_ENABLE_REG, LP_ANA_ANA_FIB_PWR_GLITCH_ENA, 0); + if (enable) { + SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_PERIF_I2C_RSTB); + SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_PERIF_I2C); + REGI2C_WRITE_MASK(I2C_SAR_ADC, POWER_GLITCH_DREF_VDET_PERIF, dref); + REGI2C_WRITE_MASK(I2C_SAR_ADC, POWER_GLITCH_DREF_VDET_VDDPST, dref); + REGI2C_WRITE_MASK(I2C_SAR_ADC, POWER_GLITCH_DREF_VDET_PLLBB, dref); + REGI2C_WRITE_MASK(I2C_SAR_ADC, POWER_GLITCH_DREF_VDET_PLL, dref); + REG_SET_FIELD(LP_ANA_POWER_GLITCH_CNTL_REG, LP_ANA_POWER_GLITCH_RESET_ENA, 0xf); + } else { + REG_SET_FIELD(LP_ANA_POWER_GLITCH_CNTL_REG, LP_ANA_POWER_GLITCH_RESET_ENA, 0); + } +} diff --git a/components/hal/esp32c5/include/hal/brownout_ll.h b/components/hal/esp32c5/include/hal/brownout_ll.h index 09dcb3cb5e9..e103d2639c9 100644 --- a/components/hal/esp32c5/include/hal/brownout_ll.h +++ b/components/hal/esp32c5/include/hal/brownout_ll.h @@ -113,8 +113,6 @@ static inline void brownout_ll_ana_reset_enable(bool enable) LP_ANA_PERI.fib_enable.val &= ~BROWNOUT_DETECTOR_LL_FIB_ENABLE; // then we can enable or disable if we want the BOD mode1 to reset the system LP_ANA_PERI.bod_mode1_cntl.bod_mode1_reset_ena = enable; - // Disable the power glitch detect. - LP_ANA_PERI.fib_enable.val &= ~(BIT2|BIT3|BIT4|BIT5); } /** diff --git a/components/hal/esp32c61/include/hal/brownout_ll.h b/components/hal/esp32c61/include/hal/brownout_ll.h index 7a4bb9e1841..ac3b966d56a 100644 --- a/components/hal/esp32c61/include/hal/brownout_ll.h +++ b/components/hal/esp32c61/include/hal/brownout_ll.h @@ -113,8 +113,6 @@ static inline void brownout_ll_ana_reset_enable(bool enable) LP_ANA.fib_enable.val &= ~BROWNOUT_DETECTOR_LL_FIB_ENABLE; // then we can enable or disable if we want the BOD mode1 to reset the system LP_ANA.bod_mode1_cntl.bod_mode1_reset_ena = enable; - // Disable the power glitch detect. - LP_ANA.fib_enable.val &= ~(BIT2|BIT3|BIT4|BIT5); } /** diff --git a/components/soc/esp32c5/include/soc/lp_analog_peri_reg.h b/components/soc/esp32c5/include/soc/lp_analog_peri_reg.h index edc9199d436..13fd8e80e16 100644 --- a/components/soc/esp32c5/include/soc/lp_analog_peri_reg.h +++ b/components/soc/esp32c5/include/soc/lp_analog_peri_reg.h @@ -129,6 +129,11 @@ extern "C" { #define LP_ANA_ANA_FIB_ENA_V 0xFFFFFFFFU #define LP_ANA_ANA_FIB_ENA_S 0 +#define LP_ANA_ANA_FIB_PWR_GLITCH_ENA 0x0000000FU +#define LP_ANA_ANA_FIB_PWR_GLITCH_ENA_M (LP_ANA_ANA_FIB_PWR_GLITCH_ENA_V << LP_ANA_ANA_FIB_PWR_GLITCH_ENA_S) +#define LP_ANA_ANA_FIB_PWR_GLITCH_ENA_V 0x0000000FU +#define LP_ANA_ANA_FIB_PWR_GLITCH_ENA_S 2 + /** LP_ANA_INT_RAW_REG register * interrpt raw register */ diff --git a/components/soc/esp32c5/include/soc/regi2c_saradc.h b/components/soc/esp32c5/include/soc/regi2c_saradc.h index 120d51fc20d..7fa3ff46026 100644 --- a/components/soc/esp32c5/include/soc/regi2c_saradc.h +++ b/components/soc/esp32c5/include/soc/regi2c_saradc.h @@ -81,3 +81,19 @@ #define ADC_SARADC2_EN_TOUT_ADDR 0x8 #define ADC_SARADC2_EN_TOUT_ADDR_MSB 0x2 #define ADC_SARADC2_EN_TOUT_ADDR_LSB 0x2 + +#define POWER_GLITCH_DREF_VDET_PERIF 11 +#define POWER_GLITCH_DREF_VDET_PERIF_MSB 2 +#define POWER_GLITCH_DREF_VDET_PERIF_LSB 0 + +#define POWER_GLITCH_DREF_VDET_VDDPST 11 +#define POWER_GLITCH_DREF_VDET_VDDPST_MSB 6 +#define POWER_GLITCH_DREF_VDET_VDDPST_LSB 4 + +#define POWER_GLITCH_DREF_VDET_XTAL 12 +#define POWER_GLITCH_DREF_VDET_XTAL_MSB 2 +#define POWER_GLITCH_DREF_VDET_XTAL_LSB 0 + +#define POWER_GLITCH_DREF_VDET_PLL 12 +#define POWER_GLITCH_DREF_VDET_PLL_MSB 6 +#define POWER_GLITCH_DREF_VDET_PLL_LSB 4 diff --git a/components/soc/esp32c61/include/soc/lp_analog_peri_reg.h b/components/soc/esp32c61/include/soc/lp_analog_peri_reg.h index cea0165480b..d7398ecbda4 100644 --- a/components/soc/esp32c61/include/soc/lp_analog_peri_reg.h +++ b/components/soc/esp32c61/include/soc/lp_analog_peri_reg.h @@ -108,6 +108,11 @@ extern "C" { #define LP_ANA_ANA_FIB_ENA_V 0xFFFFFFFFU #define LP_ANA_ANA_FIB_ENA_S 0 +#define LP_ANA_ANA_FIB_PWR_GLITCH_ENA 0x0000000FU +#define LP_ANA_ANA_FIB_PWR_GLITCH_ENA_M (LP_ANA_ANA_FIB_PWR_GLITCH_ENA_V << LP_ANA_ANA_FIB_PWR_GLITCH_ENA_S) +#define LP_ANA_ANA_FIB_PWR_GLITCH_ENA_V 0x0000000FU +#define LP_ANA_ANA_FIB_PWR_GLITCH_ENA_S 2 + /** LP_ANA_INT_RAW_REG register * need_des */ diff --git a/components/soc/esp32c61/include/soc/regi2c_saradc.h b/components/soc/esp32c61/include/soc/regi2c_saradc.h index c7137f3bb00..0a80bbbc539 100644 --- a/components/soc/esp32c61/include/soc/regi2c_saradc.h +++ b/components/soc/esp32c61/include/soc/regi2c_saradc.h @@ -18,41 +18,39 @@ #define I2C_SAR_ADC 0X69 #define I2C_SAR_ADC_HOSTID 0 -#define ADC_SAR1_ENCAL_GND_ADDR 0x7 -#define ADC_SAR1_ENCAL_GND_ADDR_MSB 5 -#define ADC_SAR1_ENCAL_GND_ADDR_LSB 5 -#define ADC_SAR2_ENCAL_GND_ADDR 0x7 -#define ADC_SAR2_ENCAL_GND_ADDR_MSB 7 -#define ADC_SAR2_ENCAL_GND_ADDR_LSB 7 + +#define ADC_SAR1_INITIAL_CODE_LOW_ADDR 0x0 +#define ADC_SAR1_INITIAL_CODE_LOW_ADDR_MSB 0x7 +#define ADC_SAR1_INITIAL_CODE_LOW_ADDR_LSB 0x0 #define ADC_SAR1_INITIAL_CODE_HIGH_ADDR 0x1 #define ADC_SAR1_INITIAL_CODE_HIGH_ADDR_MSB 0x3 #define ADC_SAR1_INITIAL_CODE_HIGH_ADDR_LSB 0x0 -#define ADC_SAR1_INITIAL_CODE_LOW_ADDR 0x0 -#define ADC_SAR1_INITIAL_CODE_LOW_ADDR_MSB 0x7 -#define ADC_SAR1_INITIAL_CODE_LOW_ADDR_LSB 0x0 +#define ADC_SAR1_SAMPLE_CYCLE_ADDR 0x2 +#define ADC_SAR1_SAMPLE_CYCLE_ADDR_MSB 0x2 +#define ADC_SAR1_SAMPLE_CYCLE_ADDR_LSB 0x0 -#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR 0x4 -#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR_MSB 0x3 -#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR_LSB 0x0 +#define ADC_SAR1_DREF_ADDR 0x2 +#define ADC_SAR1_DREF_ADDR_MSB 0x6 +#define ADC_SAR1_DREF_ADDR_LSB 0x4 #define ADC_SAR2_INITIAL_CODE_LOW_ADDR 0x3 #define ADC_SAR2_INITIAL_CODE_LOW_ADDR_MSB 0x7 #define ADC_SAR2_INITIAL_CODE_LOW_ADDR_LSB 0x0 -#define ADC_SAR1_DREF_ADDR 0x2 -#define ADC_SAR1_DREF_ADDR_MSB 0x6 -#define ADC_SAR1_DREF_ADDR_LSB 0x4 +#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR 0x4 +#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR_MSB 0x3 +#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR_LSB 0x0 #define ADC_SAR2_DREF_ADDR 0x5 #define ADC_SAR2_DREF_ADDR_MSB 0x6 #define ADC_SAR2_DREF_ADDR_LSB 0x4 -#define ADC_SAR1_SAMPLE_CYCLE_ADDR 0x2 -#define ADC_SAR1_SAMPLE_CYCLE_ADDR_MSB 0x2 -#define ADC_SAR1_SAMPLE_CYCLE_ADDR_LSB 0x0 +#define I2C_SARADC_TSENS_DAC 0x6 +#define I2C_SARADC_TSENS_DAC_MSB 3 +#define I2C_SARADC_TSENS_DAC_LSB 0 #define ADC_SARADC_DTEST_RTC_ADDR 0x7 #define ADC_SARADC_DTEST_RTC_ADDR_MSB 1 @@ -70,10 +68,31 @@ #define ADC_SARADC1_ENCAL_REF_ADDR_MSB 4 #define ADC_SARADC1_ENCAL_REF_ADDR_LSB 4 +#define ADC_SAR1_ENCAL_GND_ADDR 0x7 +#define ADC_SAR1_ENCAL_GND_ADDR_MSB 5 +#define ADC_SAR1_ENCAL_GND_ADDR_LSB 5 + #define ADC_SARADC2_ENCAL_REF_ADDR 0x7 #define ADC_SARADC2_ENCAL_REF_ADDR_MSB 6 #define ADC_SARADC2_ENCAL_REF_ADDR_LSB 6 -#define I2C_SARADC_TSENS_DAC 0x6 -#define I2C_SARADC_TSENS_DAC_MSB 3 -#define I2C_SARADC_TSENS_DAC_LSB 0 +#define ADC_SAR2_ENCAL_GND_ADDR 0x7 +#define ADC_SAR2_ENCAL_GND_ADDR_MSB 7 +#define ADC_SAR2_ENCAL_GND_ADDR_LSB 7 + + +#define POWER_GLITCH_DREF_VDET_PERIF 11 +#define POWER_GLITCH_DREF_VDET_PERIF_MSB 2 +#define POWER_GLITCH_DREF_VDET_PERIF_LSB 0 + +#define POWER_GLITCH_DREF_VDET_VDDPST 11 +#define POWER_GLITCH_DREF_VDET_VDDPST_MSB 6 +#define POWER_GLITCH_DREF_VDET_VDDPST_LSB 4 + +#define POWER_GLITCH_DREF_VDET_PLLBB 12 +#define POWER_GLITCH_DREF_VDET_PLLBB_MSB 2 +#define POWER_GLITCH_DREF_VDET_PLLBB_LSB 0 + +#define POWER_GLITCH_DREF_VDET_PLL 12 +#define POWER_GLITCH_DREF_VDET_PLL_MSB 6 +#define POWER_GLITCH_DREF_VDET_PLL_LSB 4 From 3e443a9033aa215c136284bfbbda911ba58e0cdf Mon Sep 17 00:00:00 2001 From: Marius Vikhammer Date: Sat, 14 Sep 2024 11:26:09 +0800 Subject: [PATCH 039/472] fix(system): fixed docs for ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP, enabled on H2 --- components/esp_system/Kconfig | 15 +- components/mbedtls/test_apps/main/test_aes.c | 169 +++++++++--------- .../mbedtls/test_apps/main/test_mbedtls_sha.c | 3 +- 3 files changed, 91 insertions(+), 96 deletions(-) diff --git a/components/esp_system/Kconfig b/components/esp_system/Kconfig index e597eac88fa..8b0d24a0dcd 100644 --- a/components/esp_system/Kconfig +++ b/components/esp_system/Kconfig @@ -92,14 +92,8 @@ menu "ESP System Settings" config ESP_SYSTEM_RTC_FAST_MEM_AS_HEAP_DEPCHECK bool - default y if IDF_TARGET_ESP32 && ESP_SYSTEM_SINGLE_CORE_MODE - default y if IDF_TARGET_ESP32S2 - default y if IDF_TARGET_ESP32C3 - default y if IDF_TARGET_ESP32S3 - default y if IDF_TARGET_ESP32C6 - default n if IDF_TARGET_ESP32H2 # IDF-5667 - default y if IDF_TARGET_ESP32P4 - default y if IDF_TARGET_ESP32C5 + default n if IDF_TARGET_ESP32 && !ESP_SYSTEM_SINGLE_CORE_MODE + default y depends on SOC_RTC_FAST_MEM_SUPPORTED config ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP @@ -108,9 +102,8 @@ menu "ESP System Settings" depends on ESP_SYSTEM_RTC_FAST_MEM_AS_HEAP_DEPCHECK help This config option allows to add RTC fast memory region to system heap with capability - similar to that of DRAM region but without DMA. This memory will be consumed first per - heap initialization order by early startup services and scheduler related code. Speed - wise RTC fast memory operates on APB clock and hence does not have much performance impact. + similar to that of DRAM region but without DMA. Speed wise RTC fast memory operates on + APB clock and hence does not have much performance impact. config ESP_SYSTEM_USE_EH_FRAME bool "Generate and use eh_frame for backtracing" diff --git a/components/mbedtls/test_apps/main/test_aes.c b/components/mbedtls/test_apps/main/test_aes.c index 5ac71e82ec9..1e3e9865146 100644 --- a/components/mbedtls/test_apps/main/test_aes.c +++ b/components/mbedtls/test_apps/main/test_aes.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Unlicense OR CC0-1.0 */ @@ -67,7 +67,7 @@ static const uint8_t iv[] = { print(as_c_array(plain)) ct = encryptor.update(plain) + encryptor.finalize() - print("Chipertext: {}".format(as_c_array(ct))) + print("Ciphertext: {}".format(as_c_array(ct))) */ TEST_CASE("mbedtls CBC AES-256 test", "[aes]") { @@ -85,11 +85,11 @@ TEST_CASE("mbedtls CBC AES-256 test", "[aes]") memcpy(nonce, iv, 16); // allocate internal memory - uint8_t *chipertext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL); + uint8_t *ciphertext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL); uint8_t *plaintext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL); uint8_t *decryptedtext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL); - TEST_ASSERT_NOT_NULL(chipertext); + TEST_ASSERT_NOT_NULL(ciphertext); TEST_ASSERT_NOT_NULL(plaintext); TEST_ASSERT_NOT_NULL(decryptedtext); @@ -100,19 +100,19 @@ TEST_CASE("mbedtls CBC AES-256 test", "[aes]") memset(decryptedtext, 0x0, SZ); // Encrypt - mbedtls_aes_crypt_cbc(&ctx, MBEDTLS_AES_ENCRYPT, SZ, nonce, plaintext, chipertext); - TEST_ASSERT_EQUAL_HEX8_ARRAY(expected_cipher_end, chipertext + SZ - 32, 32); + mbedtls_aes_crypt_cbc(&ctx, MBEDTLS_AES_ENCRYPT, SZ, nonce, plaintext, ciphertext); + TEST_ASSERT_EQUAL_HEX8_ARRAY(expected_cipher_end, ciphertext + SZ - 32, 32); // Decrypt memcpy(nonce, iv, 16); mbedtls_aes_setkey_dec(&ctx, key_256, 256); - mbedtls_aes_crypt_cbc(&ctx, MBEDTLS_AES_DECRYPT, SZ, nonce, chipertext, decryptedtext); + mbedtls_aes_crypt_cbc(&ctx, MBEDTLS_AES_DECRYPT, SZ, nonce, ciphertext, decryptedtext); TEST_ASSERT_EQUAL_HEX8_ARRAY(plaintext, decryptedtext, SZ); mbedtls_aes_free(&ctx); free(plaintext); - free(chipertext); + free(ciphertext); free(decryptedtext); } @@ -134,11 +134,11 @@ TEST_CASE("mbedtls CBC AES-256 DMA buffer align test", "[aes]") memcpy(nonce, iv, 16); // allocate internal memory - uint8_t *chipertext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL); + uint8_t *ciphertext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL); uint8_t *plaintext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL); uint8_t *decryptedtext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL); - TEST_ASSERT_NOT_NULL(chipertext); + TEST_ASSERT_NOT_NULL(ciphertext); TEST_ASSERT_NOT_NULL(plaintext); TEST_ASSERT_NOT_NULL(decryptedtext); @@ -149,19 +149,19 @@ TEST_CASE("mbedtls CBC AES-256 DMA buffer align test", "[aes]") memset(decryptedtext, 0x0, SZ); // Encrypt - mbedtls_aes_crypt_cbc(&ctx, MBEDTLS_AES_ENCRYPT, SZ, nonce, plaintext, chipertext); - TEST_ASSERT_EQUAL_HEX8_ARRAY(expected_cipher_end, chipertext + SZ - 32, 32); + mbedtls_aes_crypt_cbc(&ctx, MBEDTLS_AES_ENCRYPT, SZ, nonce, plaintext, ciphertext); + TEST_ASSERT_EQUAL_HEX8_ARRAY(expected_cipher_end, ciphertext + SZ - 32, 32); // Decrypt memcpy(nonce, iv, 16); mbedtls_aes_setkey_dec(&ctx, key_256, 256); - mbedtls_aes_crypt_cbc(&ctx, MBEDTLS_AES_DECRYPT, SZ, nonce, chipertext, decryptedtext); + mbedtls_aes_crypt_cbc(&ctx, MBEDTLS_AES_DECRYPT, SZ, nonce, ciphertext, decryptedtext); TEST_ASSERT_EQUAL_HEX8_ARRAY(plaintext, decryptedtext, SZ); mbedtls_aes_free(&ctx); free(plaintext); - free(chipertext); + free(ciphertext); free(decryptedtext); } @@ -183,11 +183,11 @@ TEST_CASE("mbedtls CTR AES-256 test", "[aes]") memcpy(nonce, iv, 16); // allocate internal memory - uint8_t *chipertext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL); + uint8_t *ciphertext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL); uint8_t *plaintext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL); uint8_t *decryptedtext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL); - TEST_ASSERT_NOT_NULL(chipertext); + TEST_ASSERT_NOT_NULL(ciphertext); TEST_ASSERT_NOT_NULL(plaintext); TEST_ASSERT_NOT_NULL(decryptedtext); @@ -198,19 +198,19 @@ TEST_CASE("mbedtls CTR AES-256 test", "[aes]") memset(decryptedtext, 0x0, SZ); // Encrypt - mbedtls_aes_crypt_ctr(&ctx, SZ, &nc_off, nonce, stream_block, plaintext, chipertext); - TEST_ASSERT_EQUAL_HEX8_ARRAY(expected_cipher_end, chipertext + SZ - 32, 32); + mbedtls_aes_crypt_ctr(&ctx, SZ, &nc_off, nonce, stream_block, plaintext, ciphertext); + TEST_ASSERT_EQUAL_HEX8_ARRAY(expected_cipher_end, ciphertext + SZ - 32, 32); // Decrypt nc_off = 0; memcpy(nonce, iv, 16); - mbedtls_aes_crypt_ctr(&ctx, SZ, &nc_off, nonce, stream_block, chipertext, decryptedtext); + mbedtls_aes_crypt_ctr(&ctx, SZ, &nc_off, nonce, stream_block, ciphertext, decryptedtext); TEST_ASSERT_EQUAL_HEX8_ARRAY(plaintext, decryptedtext, SZ); mbedtls_aes_free(&ctx); free(plaintext); - free(chipertext); + free(ciphertext); free(decryptedtext); } @@ -231,11 +231,11 @@ TEST_CASE("mbedtls OFB AES-256 test", "[aes]") memcpy(nonce, iv, 16); // allocate internal memory - uint8_t *chipertext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL); + uint8_t *ciphertext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL); uint8_t *plaintext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL); uint8_t *decryptedtext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL); - TEST_ASSERT_NOT_NULL(chipertext); + TEST_ASSERT_NOT_NULL(ciphertext); TEST_ASSERT_NOT_NULL(plaintext); TEST_ASSERT_NOT_NULL(decryptedtext); @@ -246,19 +246,19 @@ TEST_CASE("mbedtls OFB AES-256 test", "[aes]") memset(decryptedtext, 0x0, SZ); // Encrypt - mbedtls_aes_crypt_ofb(&ctx, SZ, &nc_off, nonce, plaintext, chipertext); - TEST_ASSERT_EQUAL_HEX8_ARRAY(expected_cipher_end, chipertext + SZ - 32, 32); + mbedtls_aes_crypt_ofb(&ctx, SZ, &nc_off, nonce, plaintext, ciphertext); + TEST_ASSERT_EQUAL_HEX8_ARRAY(expected_cipher_end, ciphertext + SZ - 32, 32); // Decrypt nc_off = 0; memcpy(nonce, iv, 16); - mbedtls_aes_crypt_ofb(&ctx, SZ, &nc_off, nonce, chipertext, decryptedtext); + mbedtls_aes_crypt_ofb(&ctx, SZ, &nc_off, nonce, ciphertext, decryptedtext); TEST_ASSERT_EQUAL_HEX8_ARRAY(plaintext, decryptedtext, SZ); mbedtls_aes_free(&ctx); free(plaintext); - free(chipertext); + free(ciphertext); free(decryptedtext); } @@ -278,11 +278,11 @@ TEST_CASE("mbedtls CFB-8 AES-256 test", "[aes]") memcpy(nonce, iv, 16); // allocate internal memory - uint8_t *chipertext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL); + uint8_t *ciphertext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL); uint8_t *plaintext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL); uint8_t *decryptedtext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL); - TEST_ASSERT_NOT_NULL(chipertext); + TEST_ASSERT_NOT_NULL(ciphertext); TEST_ASSERT_NOT_NULL(plaintext); TEST_ASSERT_NOT_NULL(decryptedtext); @@ -293,18 +293,18 @@ TEST_CASE("mbedtls CFB-8 AES-256 test", "[aes]") memset(decryptedtext, 0x0, SZ); // Encrypt - mbedtls_aes_crypt_cfb8(&ctx, MBEDTLS_AES_ENCRYPT, SZ, nonce, plaintext, chipertext); - TEST_ASSERT_EQUAL_HEX8_ARRAY(expected_cipher_end, chipertext + SZ - 32, 32); + mbedtls_aes_crypt_cfb8(&ctx, MBEDTLS_AES_ENCRYPT, SZ, nonce, plaintext, ciphertext); + TEST_ASSERT_EQUAL_HEX8_ARRAY(expected_cipher_end, ciphertext + SZ - 32, 32); // Decrypt memcpy(nonce, iv, 16); - mbedtls_aes_crypt_cfb8(&ctx, MBEDTLS_AES_DECRYPT, SZ, nonce, chipertext, decryptedtext); + mbedtls_aes_crypt_cfb8(&ctx, MBEDTLS_AES_DECRYPT, SZ, nonce, ciphertext, decryptedtext); TEST_ASSERT_EQUAL_HEX8_ARRAY(plaintext, decryptedtext, SZ); mbedtls_aes_free(&ctx); free(plaintext); - free(chipertext); + free(ciphertext); free(decryptedtext); } @@ -325,11 +325,11 @@ TEST_CASE("mbedtls CFB-128 AES-256 test", "[aes]") memcpy(nonce, iv, 16); // allocate internal memory - uint8_t *chipertext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL); + uint8_t *ciphertext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL); uint8_t *plaintext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL); uint8_t *decryptedtext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL); - TEST_ASSERT_NOT_NULL(chipertext); + TEST_ASSERT_NOT_NULL(ciphertext); TEST_ASSERT_NOT_NULL(plaintext); TEST_ASSERT_NOT_NULL(decryptedtext); @@ -340,19 +340,19 @@ TEST_CASE("mbedtls CFB-128 AES-256 test", "[aes]") memset(decryptedtext, 0x0, SZ); // Encrypt - mbedtls_aes_crypt_cfb128(&ctx, MBEDTLS_AES_ENCRYPT, SZ, &nc_off, nonce, plaintext, chipertext); - TEST_ASSERT_EQUAL_HEX8_ARRAY(expected_cipher_end, chipertext + SZ - 32, 32); + mbedtls_aes_crypt_cfb128(&ctx, MBEDTLS_AES_ENCRYPT, SZ, &nc_off, nonce, plaintext, ciphertext); + TEST_ASSERT_EQUAL_HEX8_ARRAY(expected_cipher_end, ciphertext + SZ - 32, 32); // Decrypt nc_off = 0; memcpy(nonce, iv, 16); - mbedtls_aes_crypt_cfb128(&ctx, MBEDTLS_AES_DECRYPT, SZ, &nc_off, nonce, chipertext, decryptedtext); + mbedtls_aes_crypt_cfb128(&ctx, MBEDTLS_AES_DECRYPT, SZ, &nc_off, nonce, ciphertext, decryptedtext); TEST_ASSERT_EQUAL_HEX8_ARRAY(plaintext, decryptedtext, SZ); mbedtls_aes_free(&ctx); free(plaintext); - free(chipertext); + free(ciphertext); free(decryptedtext); } @@ -401,11 +401,11 @@ static void aes_ctr_stream_test(void) memset(key, 0x44, 16); // allocate internal memory - uint8_t *chipertext = heap_caps_malloc(SZ, MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL); + uint8_t *ciphertext = heap_caps_malloc(SZ, MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL); uint8_t *plaintext = heap_caps_malloc(SZ, MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL); uint8_t *decryptedtext = heap_caps_malloc(SZ, MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL); - TEST_ASSERT_NOT_NULL(chipertext); + TEST_ASSERT_NOT_NULL(ciphertext); TEST_ASSERT_NOT_NULL(plaintext); TEST_ASSERT_NOT_NULL(decryptedtext); @@ -419,7 +419,7 @@ static void aes_ctr_stream_test(void) for (int bytes_to_process = 1; bytes_to_process < SZ; bytes_to_process++) { ESP_LOGD("test", "bytes_to_process %d", bytes_to_process); memset(nonce, 0xEE, 16); - memset(chipertext, 0x0, SZ); + memset(ciphertext, 0x0, SZ); memset(decryptedtext, 0x0, SZ); size_t offset = 0; @@ -429,12 +429,12 @@ static void aes_ctr_stream_test(void) size_t length = (idx + bytes_to_process > SZ) ? (SZ - idx) : bytes_to_process; mbedtls_aes_crypt_ctr(&ctx, length, &offset, nonce, - stream_block, plaintext + idx, chipertext + idx ); + stream_block, plaintext + idx, ciphertext + idx ); } ESP_LOG_BUFFER_HEXDUMP("expected", expected_cipher, SZ, ESP_LOG_DEBUG); - ESP_LOG_BUFFER_HEXDUMP("actual ", chipertext, SZ, ESP_LOG_DEBUG); + ESP_LOG_BUFFER_HEXDUMP("actual ", ciphertext, SZ, ESP_LOG_DEBUG); - TEST_ASSERT_EQUAL_HEX8_ARRAY(expected_cipher, chipertext, SZ); + TEST_ASSERT_EQUAL_HEX8_ARRAY(expected_cipher, ciphertext, SZ); // Decrypt memset(nonce, 0xEE, 16); @@ -444,7 +444,7 @@ static void aes_ctr_stream_test(void) // Limit length of last call to avoid exceeding buffer size size_t length = (idx + bytes_to_process > SZ) ? (SZ - idx) : bytes_to_process; mbedtls_aes_crypt_ctr(&ctx, length, &offset, nonce, - stream_block, chipertext + idx, decryptedtext + idx ); + stream_block, ciphertext + idx, decryptedtext + idx ); } ESP_LOG_BUFFER_HEXDUMP("decrypted", decryptedtext, SZ, ESP_LOG_DEBUG); TEST_ASSERT_EQUAL_HEX8_ARRAY(plaintext, decryptedtext, SZ); @@ -452,7 +452,7 @@ static void aes_ctr_stream_test(void) mbedtls_aes_free(&ctx); free(plaintext); - free(chipertext); + free(ciphertext); free(decryptedtext); } @@ -505,11 +505,11 @@ TEST_CASE("mbedtls OFB stream test", "[aes]") memset(key, 0x44, 16); // allocate internal memory - uint8_t *chipertext = heap_caps_malloc(SZ, MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL); + uint8_t *ciphertext = heap_caps_malloc(SZ, MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL); uint8_t *plaintext = heap_caps_malloc(SZ, MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL); uint8_t *decryptedtext = heap_caps_malloc(SZ, MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL); - TEST_ASSERT_NOT_NULL(chipertext); + TEST_ASSERT_NOT_NULL(ciphertext); TEST_ASSERT_NOT_NULL(plaintext); TEST_ASSERT_NOT_NULL(decryptedtext); @@ -529,10 +529,10 @@ TEST_CASE("mbedtls OFB stream test", "[aes]") for (int idx = 0; idx < SZ; idx = idx + bytes_to_process) { // Limit length of last call to avoid exceeding buffer size size_t length = ( (idx + bytes_to_process) > SZ) ? (SZ - idx) : bytes_to_process; - mbedtls_aes_crypt_ofb(&ctx, length, &offset, iv, plaintext + idx, chipertext + idx); + mbedtls_aes_crypt_ofb(&ctx, length, &offset, iv, plaintext + idx, ciphertext + idx); } - TEST_ASSERT_EQUAL_HEX8_ARRAY(expected_cipher, chipertext, SZ); + TEST_ASSERT_EQUAL_HEX8_ARRAY(expected_cipher, ciphertext, SZ); // Decrypt memset(iv, 0xEE, 16); @@ -541,14 +541,14 @@ TEST_CASE("mbedtls OFB stream test", "[aes]") for (int idx = 0; idx < SZ; idx = idx + bytes_to_process) { // Limit length of last call to avoid exceeding buffer size size_t length = (idx + bytes_to_process > SZ) ? (SZ - idx) : bytes_to_process; - mbedtls_aes_crypt_ofb(&ctx, length, &offset, iv, chipertext + idx, decryptedtext + idx); + mbedtls_aes_crypt_ofb(&ctx, length, &offset, iv, ciphertext + idx, decryptedtext + idx); } TEST_ASSERT_EQUAL_HEX8_ARRAY(plaintext, decryptedtext, SZ); } mbedtls_aes_free(&ctx); free(plaintext); - free(chipertext); + free(ciphertext); free(decryptedtext); } @@ -595,11 +595,11 @@ TEST_CASE("mbedtls CFB8 stream test", "[aes]") memset(key, 0x44, 16); // allocate internal memory - uint8_t *chipertext = heap_caps_malloc(SZ, MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL); + uint8_t *ciphertext = heap_caps_malloc(SZ, MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL); uint8_t *plaintext = heap_caps_malloc(SZ, MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL); uint8_t *decryptedtext = heap_caps_malloc(SZ, MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL); - TEST_ASSERT_NOT_NULL(chipertext); + TEST_ASSERT_NOT_NULL(ciphertext); TEST_ASSERT_NOT_NULL(plaintext); TEST_ASSERT_NOT_NULL(decryptedtext); @@ -616,16 +616,16 @@ TEST_CASE("mbedtls CFB8 stream test", "[aes]") for (int idx = 0; idx < SZ; idx = idx + bytes_to_process) { // Limit length of last call to avoid exceeding buffer size size_t length = ( (idx + bytes_to_process) > SZ) ? (SZ - idx) : bytes_to_process; - mbedtls_aes_crypt_cfb8(&ctx, MBEDTLS_AES_ENCRYPT, length, iv, plaintext + idx, chipertext + idx); + mbedtls_aes_crypt_cfb8(&ctx, MBEDTLS_AES_ENCRYPT, length, iv, plaintext + idx, ciphertext + idx); } - TEST_ASSERT_EQUAL_HEX8_ARRAY(expected_cipher, chipertext, SZ); + TEST_ASSERT_EQUAL_HEX8_ARRAY(expected_cipher, ciphertext, SZ); memset(iv, 0xEE, 16); for (int idx = 0; idx < SZ; idx = idx + bytes_to_process) { // Limit length of last call to avoid exceeding buffer size size_t length = ( (idx + bytes_to_process) > SZ) ? (SZ - idx) : bytes_to_process; - mbedtls_aes_crypt_cfb8(&ctx, MBEDTLS_AES_DECRYPT, length, iv, chipertext + idx, decryptedtext + idx); + mbedtls_aes_crypt_cfb8(&ctx, MBEDTLS_AES_DECRYPT, length, iv, ciphertext + idx, decryptedtext + idx); } TEST_ASSERT_EQUAL_HEX8_ARRAY(plaintext, decryptedtext, SZ); @@ -633,7 +633,7 @@ TEST_CASE("mbedtls CFB8 stream test", "[aes]") mbedtls_aes_free(&ctx); free(plaintext); - free(chipertext); + free(ciphertext); free(decryptedtext); } @@ -680,11 +680,11 @@ TEST_CASE("mbedtls CFB128 stream test", "[aes]") memset(key, 0x44, 16); // allocate internal memory - uint8_t *chipertext = heap_caps_malloc(SZ, MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL); + uint8_t *ciphertext = heap_caps_malloc(SZ, MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL); uint8_t *plaintext = heap_caps_malloc(SZ, MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL); uint8_t *decryptedtext = heap_caps_malloc(SZ, MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL); - TEST_ASSERT_NOT_NULL(chipertext); + TEST_ASSERT_NOT_NULL(ciphertext); TEST_ASSERT_NOT_NULL(plaintext); TEST_ASSERT_NOT_NULL(decryptedtext); @@ -703,24 +703,24 @@ TEST_CASE("mbedtls CFB128 stream test", "[aes]") for (int idx = 0; idx < SZ; idx = idx + bytes_to_process) { // Limit length of last call to avoid exceeding buffer size size_t length = ( (idx + bytes_to_process) > SZ) ? (SZ - idx) : bytes_to_process; - mbedtls_aes_crypt_cfb128(&ctx, MBEDTLS_AES_ENCRYPT, length, &offset, iv, plaintext + idx, chipertext + idx); + mbedtls_aes_crypt_cfb128(&ctx, MBEDTLS_AES_ENCRYPT, length, &offset, iv, plaintext + idx, ciphertext + idx); } - TEST_ASSERT_EQUAL_HEX8_ARRAY(expected_cipher, chipertext, SZ); + TEST_ASSERT_EQUAL_HEX8_ARRAY(expected_cipher, ciphertext, SZ); offset = 0; memset(iv, 0xEE, 16); for (int idx = 0; idx < SZ; idx = idx + bytes_to_process) { // Limit length of last call to avoid exceeding buffer size size_t length = ( (idx + bytes_to_process) > SZ) ? (SZ - idx) : bytes_to_process; - mbedtls_aes_crypt_cfb128(&ctx, MBEDTLS_AES_DECRYPT, length, &offset, iv, chipertext + idx, decryptedtext + idx); + mbedtls_aes_crypt_cfb128(&ctx, MBEDTLS_AES_DECRYPT, length, &offset, iv, ciphertext + idx, decryptedtext + idx); } TEST_ASSERT_EQUAL_HEX8_ARRAY(plaintext, decryptedtext, SZ); mbedtls_aes_free(&ctx); free(plaintext); - free(chipertext); + free(ciphertext); free(decryptedtext); } @@ -804,11 +804,11 @@ TEST_CASE("mbedtls OFB, chained DMA descriptors", "[aes]") memcpy(nonce, iv, 16); // allocate internal memory - uint8_t *chipertext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL); + uint8_t *ciphertext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL); uint8_t *plaintext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL); uint8_t *decryptedtext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL); - TEST_ASSERT_NOT_NULL(chipertext); + TEST_ASSERT_NOT_NULL(ciphertext); TEST_ASSERT_NOT_NULL(plaintext); TEST_ASSERT_NOT_NULL(decryptedtext); @@ -819,20 +819,20 @@ TEST_CASE("mbedtls OFB, chained DMA descriptors", "[aes]") memset(decryptedtext, 0x0, SZ); // Encrypt - mbedtls_aes_crypt_ofb(&ctx, SZ, &nc_off, nonce, plaintext, chipertext); - TEST_ASSERT_EQUAL_HEX8_ARRAY(expected_cipher_end, chipertext + SZ - 32, 32); + mbedtls_aes_crypt_ofb(&ctx, SZ, &nc_off, nonce, plaintext, ciphertext); + TEST_ASSERT_EQUAL_HEX8_ARRAY(expected_cipher_end, ciphertext + SZ - 32, 32); // Decrypt nc_off = 0; memcpy(nonce, iv, 16); - mbedtls_aes_crypt_ofb(&ctx, SZ, &nc_off, nonce, chipertext, decryptedtext); + mbedtls_aes_crypt_ofb(&ctx, SZ, &nc_off, nonce, ciphertext, decryptedtext); TEST_ASSERT_EQUAL_HEX8_ARRAY(plaintext, decryptedtext, SZ); mbedtls_aes_free(&ctx); free(plaintext); - free(chipertext); + free(ciphertext); free(decryptedtext); } @@ -858,11 +858,11 @@ void aes_ctr_alignment_test(uint32_t input_buf_caps, uint32_t output_buf_caps) memset(key, 0x1E, 16); // allocate memory according the requested caps - uint8_t *chipertext = heap_caps_malloc(SZ + ALIGNMENT_SIZE_BYTES, output_buf_caps); + uint8_t *ciphertext = heap_caps_malloc(SZ + ALIGNMENT_SIZE_BYTES, output_buf_caps); uint8_t *plaintext = heap_caps_malloc(SZ + ALIGNMENT_SIZE_BYTES, input_buf_caps); uint8_t *decryptedtext = heap_caps_malloc(SZ, MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL); - TEST_ASSERT_NOT_NULL(chipertext); + TEST_ASSERT_NOT_NULL(ciphertext); TEST_ASSERT_NOT_NULL(plaintext); TEST_ASSERT_NOT_NULL(decryptedtext); @@ -877,14 +877,14 @@ void aes_ctr_alignment_test(uint32_t input_buf_caps, uint32_t output_buf_caps) // Encrypt with input buffer in external ram offset = 0; memset(nonce, 0x2F, 16); - mbedtls_aes_crypt_ctr(&ctx, SZ, &offset, nonce, stream_block, plaintext + i, chipertext + i); - TEST_ASSERT_EQUAL_HEX8_ARRAY(expected_cipher_ctr_end, chipertext + i + SZ - 32, 32); + mbedtls_aes_crypt_ctr(&ctx, SZ, &offset, nonce, stream_block, plaintext + i, ciphertext + i); + TEST_ASSERT_EQUAL_HEX8_ARRAY(expected_cipher_ctr_end, ciphertext + i + SZ - 32, 32); // Decrypt offset = 0; memset(nonce, 0x2F, 16); // Decrypt with input buffer in instruction memory, the crypto DMA can't access this - mbedtls_aes_crypt_ctr(&ctx, SZ, &offset, nonce, stream_block, chipertext + i, decryptedtext); + mbedtls_aes_crypt_ctr(&ctx, SZ, &offset, nonce, stream_block, ciphertext + i, decryptedtext); TEST_ASSERT_EQUAL_HEX8_ARRAY(plaintext, decryptedtext, SZ); @@ -892,7 +892,7 @@ void aes_ctr_alignment_test(uint32_t input_buf_caps, uint32_t output_buf_caps) mbedtls_aes_free(&ctx); free(plaintext); - free(chipertext); + free(ciphertext); free(decryptedtext); } @@ -1483,10 +1483,10 @@ void aes_ext_flash_ctr_test(uint32_t output_buf_caps) memset(nonce, 0x2F, 16); memset(key, 0x1E, 16); - uint8_t *chipertext = heap_caps_malloc(SZ, output_buf_caps); + uint8_t *ciphertext = heap_caps_malloc(SZ, output_buf_caps); uint8_t *decryptedtext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT | MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL); - TEST_ASSERT_NOT_NULL(chipertext); + TEST_ASSERT_NOT_NULL(ciphertext); TEST_ASSERT_NOT_NULL(decryptedtext); mbedtls_aes_init(&ctx); @@ -1497,19 +1497,19 @@ void aes_ext_flash_ctr_test(uint32_t output_buf_caps) // Encrypt with input buffer in external flash offset = 0; memset(nonce, 0x2F, 16); - mbedtls_aes_crypt_ctr(&ctx, SZ, &offset, nonce, stream_block, long_input, chipertext); - TEST_ASSERT_EQUAL_HEX8_ARRAY(expected_cipher_long_input_end, chipertext + SZ - 32, 32); + mbedtls_aes_crypt_ctr(&ctx, SZ, &offset, nonce, stream_block, long_input, ciphertext); + TEST_ASSERT_EQUAL_HEX8_ARRAY(expected_cipher_long_input_end, ciphertext + SZ - 32, 32); // Decrypt offset = 0; memset(nonce, 0x2F, 16); // Decrypt with input buffer in external flash, the crypto DMA can't access this - mbedtls_aes_crypt_ctr(&ctx, SZ, &offset, nonce, stream_block, chipertext, decryptedtext); + mbedtls_aes_crypt_ctr(&ctx, SZ, &offset, nonce, stream_block, ciphertext, decryptedtext); TEST_ASSERT_EQUAL_HEX8_ARRAY(long_input, decryptedtext, SZ); mbedtls_aes_free(&ctx); - free(chipertext); + free(ciphertext); free(decryptedtext); } @@ -1540,7 +1540,8 @@ static void __attribute__((unused)) aes_ctr_stream_test_task(void *pv) vTaskDelete(NULL); } -#if CONFIG_ESP_SYSTEM_RTC_FAST_MEM_AS_HEAP_DEPCHECK +#if CONFIG_ESP_SYSTEM_RTC_FAST_MEM_AS_HEAP_DEPCHECK && !CONFIG_IDF_TARGET_ESP32H2 +// Not enough rtc memory for test on H2 TEST_CASE("mbedtls AES stack in RTC RAM", "[mbedtls]") { @@ -1561,7 +1562,7 @@ TEST_CASE("mbedtls AES stack in RTC RAM", "[mbedtls]") vSemaphoreDelete(done_sem); } -#endif //CONFIG_ESP_SYSTEM_RTC_FAST_MEM_AS_HEAP_DEPCHECK +#endif //CONFIG_ESP_SYSTEM_RTC_FAST_MEM_AS_HEAP_DEPCHECK && !CONFIG_IDF_TARGET_ESP32H2 #if CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY && CONFIG_SPIRAM_USE_MALLOC diff --git a/components/mbedtls/test_apps/main/test_mbedtls_sha.c b/components/mbedtls/test_apps/main/test_mbedtls_sha.c index 003b35db8b5..0d07fc7ff1c 100644 --- a/components/mbedtls/test_apps/main/test_mbedtls_sha.c +++ b/components/mbedtls/test_apps/main/test_mbedtls_sha.c @@ -563,7 +563,8 @@ TEST_CASE("mbedtls SHA256 PSRAM DMA large buffer", "[hw_crypto]") #endif //CONFIG_SPIRAM_USE_MALLOC -#if CONFIG_ESP_SYSTEM_RTC_FAST_MEM_AS_HEAP_DEPCHECK +#if CONFIG_ESP_SYSTEM_RTC_FAST_MEM_AS_HEAP_DEPCHECK && !CONFIG_IDF_TARGET_ESP32H2 +// Not enough rtc memory for test on H2 TEST_CASE("mbedtls SHA stack in RTC RAM", "[mbedtls]") { From c672db530bc91efa6f0647fbb85813f546997140 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Adam=20M=C3=BAdry?= Date: Tue, 24 Sep 2024 11:52:14 +0200 Subject: [PATCH 040/472] docs(nvs): Document nvs_check.py functions --- .../nvs_flash/nvs_partition_tool/nvs_check.py | 76 ++++++++++++++++--- 1 file changed, 65 insertions(+), 11 deletions(-) diff --git a/components/nvs_flash/nvs_partition_tool/nvs_check.py b/components/nvs_flash/nvs_partition_tool/nvs_check.py index b6a4da3abaf..ca2cd4680a4 100644 --- a/components/nvs_flash/nvs_partition_tool/nvs_check.py +++ b/components/nvs_flash/nvs_partition_tool/nvs_check.py @@ -22,6 +22,22 @@ def check_partition_size(nvs_partition: NVS_Partition, nvs_log: NVS_Logger) -> bool: + """ Checks if the partition is large enough and has enough pages + """ + if len(nvs_partition.raw_data) / 0x1000 < 3: + nvs_log.info( + nvs_log.yellow( + 'NVS Partition size must be at least 0x3000 (4kiB * 3 pages == 12kiB)!' + ) + ) + return False + if len(nvs_partition.raw_data) % 0x1000 != 0: + nvs_log.info( + nvs_log.yellow( + 'NVS Partition size must be a multiple of 0x1000 (4kiB)!' + ) + ) + return False if len(nvs_partition.pages) < 3: nvs_log.info( nvs_log.yellow( @@ -83,16 +99,22 @@ def check_page_crc(nvs_page: NVS_Page, nvs_log: NVS_Logger) -> bool: return False -def identify_entry_duplicates(entry: NVS_Entry, seen_written_entires: Dict[str, List[NVS_Entry]]) -> Dict[str, List[NVS_Entry]]: +def identify_entry_duplicates(entry: NVS_Entry, entry_dict: Dict[str, List[NVS_Entry]]) -> Dict[str, List[NVS_Entry]]: + """Identifies and logs written entries + + Part 1 of duplicate entry check mechanism + """ if entry.state == 'Written': - if entry.key in seen_written_entires: - seen_written_entires[entry.key].append(entry) + if entry.key in entry_dict: + entry_dict[entry.key].append(entry) else: - seen_written_entires[entry.key] = [entry] - return seen_written_entires + entry_dict[entry.key] = [entry] + return entry_dict def check_page_entries(nvs_page: NVS_Page, nvs_log: NVS_Logger) -> Dict[str, List[NVS_Entry]]: + """Checks entries in the given page (entry state, children CRC32, entry type, span and gathers blobs and namespaces) + """ seen_written_entires: Dict[str, List[NVS_Entry]] = {} for entry in nvs_page.entries: @@ -203,6 +225,11 @@ def check_page_entries(nvs_page: NVS_Page, nvs_log: NVS_Logger) -> Dict[str, Lis def filter_namespaces_fake_duplicates(duplicate_entries_dict: Dict[str, List[NVS_Entry]]) -> Dict[str, List[NVS_Entry]]: + """Takes a dictionary of entries (as written) and returns a new dictionary with "fake" duplicates, + where entries which have the same key but under different namespaces are filtered out + + Use `filter_entry_duplicates()` to properly filter out all duplicates + """ new_duplicate_entries_dict: Dict[str, List[NVS_Entry]] = {} for key, duplicate_entries in duplicate_entries_dict.items(): seen_entries: List[NVS_Entry] = [] @@ -237,6 +264,11 @@ def filter_namespaces_fake_duplicates(duplicate_entries_dict: Dict[str, List[NVS def filter_blob_related_duplicates(duplicate_entries_dict: Dict[str, List[NVS_Entry]]) -> Dict[str, List[NVS_Entry]]: + """Takes a dictionary of entries (as written) and returns a new dictionary with "fake" duplicates, + where entries related to blob index and blob data under the same namespace are filtered out + + Use `filter_entry_duplicates()` to properly filter out all duplicates + """ new_duplicate_entries_dict: Dict[str, List[NVS_Entry]] = {} for key, duplicate_entries in duplicate_entries_dict.items(): seen_blob_index: List[NVS_Entry] = [] @@ -298,9 +330,19 @@ def filter_blob_related_duplicates(duplicate_entries_dict: Dict[str, List[NVS_En return new_duplicate_entries_dict -def filter_entry_duplicates(seen_written_entires: Dict[str, List[NVS_Entry]]) -> Dict[str, List[NVS_Entry]]: - duplicate_entries_list = {key: v for key, v in seen_written_entires.items() if len(v) > 1} +def filter_entry_duplicates(entries: Dict[str, List[NVS_Entry]]) -> Dict[str, List[NVS_Entry]]: + """Takes a dictionary of (seen written) entries and outputs a new dictionary with "fake" duplicates filtered out, keeping only real duplicates in + + (i.e. duplicate keys under different namespaces and blob index and blob data having the same key under the same namespace are allowed + and should be filtered out) + + Part 2 of duplicate entry check mechanism + """ + # Only keep seen written entries which have been observerd multiple times (duplicates) + duplicate_entries_list = {key: v for key, v in entries.items() if len(v) > 1} + # Filter out "fake" duplicates 1 (duplicate keys under different namespaces are allowed) duplicate_entries_list_1 = filter_namespaces_fake_duplicates(duplicate_entries_list) + # Filter out "fake" duplicates 2 (blob index and blob data are allowed to have the same key even in the same namespace) duplicate_entries_list_2 = filter_blob_related_duplicates(duplicate_entries_list_1) return duplicate_entries_list_2 @@ -341,6 +383,8 @@ def print_entry_duplicates(duplicate_entries_list: Dict[str, List[NVS_Entry]], n def assemble_blobs(nvs_log: NVS_Logger) -> None: + """Assembles blob data from blob chunks + """ for chunk in blob_chunks: # chunk: NVS_Entry parent = blobs.get( @@ -361,6 +405,8 @@ def assemble_blobs(nvs_log: NVS_Logger) -> None: def check_blob_data(nvs_log: NVS_Logger) -> None: + """Checks blob data for missing chunks or data + """ for blob_key in blobs: blob_index = blobs[blob_key][0] blob_chunks = blobs[blob_key][1:] @@ -395,6 +441,8 @@ def check_blobs(nvs_log: NVS_Logger) -> None: def check_namespaces(nvs_log: NVS_Logger) -> None: + """Checks namespaces (entries using undefined namespace indexes, unused namespaces) + """ # Undefined namespace index check for used_ns in used_namespaces: key = found_namespaces.pop(used_ns, None) @@ -415,6 +463,9 @@ def check_namespaces(nvs_log: NVS_Logger) -> None: def reset_global_variables() -> None: + """Global variables need to be cleared out before calling `integrity_check()` multiple times from a script + (e.g. when running tests) to avoid incorrect output + """ global used_namespaces, found_namespaces, blobs, blob_chunks used_namespaces = {} found_namespaces = {} @@ -423,6 +474,8 @@ def reset_global_variables() -> None: def integrity_check(nvs_partition: NVS_Partition, nvs_log: NVS_Logger) -> None: + """Function for multi-stage integrity check of a NVS partition + """ # Partition size check check_partition_size(nvs_partition, nvs_log) @@ -431,18 +484,19 @@ def integrity_check(nvs_partition: NVS_Partition, nvs_log: NVS_Logger) -> None: seen_written_entires_all: Dict[str, List[NVS_Entry]] = {} + # Loop through all pages in the partition for page in nvs_partition.pages: # page: NVS_Page - # Print page header + # Print a page header if page.header['status'] == 'Empty': - # Check if page is truly empty + # Check if a page is truly empty check_empty_page_content(page, nvs_log) else: - # Check page header CRC32 + # Check a page header CRC32 check_page_crc(page, nvs_log) - # Check all entries + # Check all entries in a page seen_written_entires = check_page_entries(page, nvs_log) # Collect all seen written entries From 4c08e00c6a20176b0dfb75e334438e61d7bb5f5f Mon Sep 17 00:00:00 2001 From: Zhang Shuxian Date: Tue, 8 Oct 2024 14:49:14 +0800 Subject: [PATCH 041/472] docs: Update CN translation for system.rst --- docs/zh_CN/migration-guides/release-5.x/5.4/system.rst | 1 + 1 file changed, 1 insertion(+) diff --git a/docs/zh_CN/migration-guides/release-5.x/5.4/system.rst b/docs/zh_CN/migration-guides/release-5.x/5.4/system.rst index dbe6984ddd7..593a62105c3 100644 --- a/docs/zh_CN/migration-guides/release-5.x/5.4/system.rst +++ b/docs/zh_CN/migration-guides/release-5.x/5.4/system.rst @@ -8,6 +8,7 @@ - `esp_log_buffer_hex` 已弃用，应使用 `ESP_LOG_BUFFER_HEX` 替代。 - `esp_log_buffer_char` 已弃用，应使用 `ESP_LOG_BUFFER_CHAR` 替代。 +- ``CONFIG_LOG_COLORS`` 的默认值设置为 false。默认情况下，IDF Monitor 在主机端添加颜色。如需在其他控制台监视器的日志输出中启用颜色，请将 ``CONFIG_LOG_COLORS`` 设置为 true。如需在 IDF Monitor 中关闭自动的日志颜色显示，请运行命令： ``idf.py monitor --disable-auto-color``。 ESP ROM --------- From aa022b14ce7628232af71e21c48c2bdf6e01002b Mon Sep 17 00:00:00 2001 From: luoxu Date: Wed, 18 Sep 2024 20:45:47 +0800 Subject: [PATCH 042/472] feat(ble_mesh): esp ble mesh v1.1 features enable/disable supported --- components/bt/CMakeLists.txt | 71 +-- components/bt/common/btc/core/btc_task.c | 12 +- components/bt/esp_ble_mesh/Kconfig.in | 430 +++++++++--------- .../bt/esp_ble_mesh/btc/btc_ble_mesh_prov.c | 8 +- components/bt/esp_ble_mesh/core/access.c | 148 +++++- components/bt/esp_ble_mesh/core/beacon.c | 9 +- .../core/bluedroid_host/adapter.c | 2 + components/bt/esp_ble_mesh/core/cfg_srv.c | 158 ++++++- components/bt/esp_ble_mesh/core/crypto.c | 2 + components/bt/esp_ble_mesh/core/friend.c | 2 + components/bt/esp_ble_mesh/core/lpn.c | 3 + components/bt/esp_ble_mesh/core/main.c | 12 +- components/bt/esp_ble_mesh/core/mesh.h | 1 + components/bt/esp_ble_mesh/core/net.c | 118 ++++- components/bt/esp_ble_mesh/core/prov_common.h | 2 + components/bt/esp_ble_mesh/core/prov_node.c | 2 + components/bt/esp_ble_mesh/core/prov_pvnr.c | 6 +- .../bt/esp_ble_mesh/core/proxy_client.c | 2 + .../bt/esp_ble_mesh/core/proxy_client.h | 2 + .../bt/esp_ble_mesh/core/proxy_server.c | 2 + components/bt/esp_ble_mesh/core/pvnr_mgmt.c | 2 + components/bt/esp_ble_mesh/core/scan.c | 9 +- .../bt/esp_ble_mesh/core/storage/settings.c | 2 + components/bt/esp_ble_mesh/core/tag.h | 53 +++ components/bt/esp_ble_mesh/core/transport.c | 27 +- .../lib/include/mesh_v1.1/utils.h | 2 +- .../models/client/client_common.c | 2 + 27 files changed, 813 insertions(+), 276 deletions(-) create mode 100644 components/bt/esp_ble_mesh/core/tag.h diff --git a/components/bt/CMakeLists.txt b/components/bt/CMakeLists.txt index 70f8aacbbe1..0e278b35c46 100644 --- a/components/bt/CMakeLists.txt +++ b/components/bt/CMakeLists.txt @@ -39,12 +39,20 @@ set(ble_mesh_include_dirs "esp_ble_mesh/api/core/include" "esp_ble_mesh/api/models/include" "esp_ble_mesh/api" +) + +set(ble_mesh_v11_include_dirs "esp_ble_mesh/lib/include" "esp_ble_mesh/v1.1/api/core/include" "esp_ble_mesh/v1.1/api/models/include" "esp_ble_mesh/v1.1/btc/include" ) +if(CONFIG_IDF_DOC_BUILD) + list(APPEND ble_mesh_include_dirs + ${ble_mesh_v11_include_dirs}) +endif() + set(bluedroid_include_dirs host/bluedroid/api/include/api) if(CONFIG_BT_CONTROLLER_ENABLED OR CONFIG_IDF_DOC_BUILD) @@ -524,34 +532,41 @@ if(CONFIG_BT_ENABLED) "esp_ble_mesh/models/server/server_common.c" "esp_ble_mesh/models/server/state_binding.c" "esp_ble_mesh/models/server/state_transition.c" - "esp_ble_mesh/models/server/time_scene_server.c" - "esp_ble_mesh/v1.1/api/core/esp_ble_mesh_agg_model_api.c" - "esp_ble_mesh/v1.1/api/core/esp_ble_mesh_brc_model_api.c" - "esp_ble_mesh/v1.1/api/core/esp_ble_mesh_cm_data_api.c" - "esp_ble_mesh/v1.1/api/core/esp_ble_mesh_df_model_api.c" - "esp_ble_mesh/v1.1/api/core/esp_ble_mesh_lcd_model_api.c" - "esp_ble_mesh/v1.1/api/core/esp_ble_mesh_odp_model_api.c" - "esp_ble_mesh/v1.1/api/core/esp_ble_mesh_prb_model_api.c" - "esp_ble_mesh/v1.1/api/core/esp_ble_mesh_rpr_model_api.c" - "esp_ble_mesh/v1.1/api/core/esp_ble_mesh_sar_model_api.c" - "esp_ble_mesh/v1.1/api/core/esp_ble_mesh_srpl_model_api.c" - "esp_ble_mesh/v1.1/api/models/esp_ble_mesh_mbt_model_api.c" - "esp_ble_mesh/v1.1/btc/btc_ble_mesh_agg_model.c" - "esp_ble_mesh/v1.1/btc/btc_ble_mesh_brc_model.c" - "esp_ble_mesh/v1.1/btc/btc_ble_mesh_df_model.c" - "esp_ble_mesh/v1.1/btc/btc_ble_mesh_lcd_model.c" - "esp_ble_mesh/v1.1/btc/btc_ble_mesh_mbt_model.c" - "esp_ble_mesh/v1.1/btc/btc_ble_mesh_odp_model.c" - "esp_ble_mesh/v1.1/btc/btc_ble_mesh_prb_model.c" - "esp_ble_mesh/v1.1/btc/btc_ble_mesh_rpr_model.c" - "esp_ble_mesh/v1.1/btc/btc_ble_mesh_sar_model.c" - "esp_ble_mesh/v1.1/btc/btc_ble_mesh_srpl_model.c" - "esp_ble_mesh/lib/ext.c") - - if(CONFIG_BLE_MESH_SAR_ENHANCEMENT) - list(APPEND srcs "esp_ble_mesh/core/transport.enh.c") + "esp_ble_mesh/models/server/time_scene_server.c") + if(CONFIG_BLE_MESH_V11_SUPPORT) + list(APPEND include_dirs ${ble_mesh_v11_include_dirs}) + + list(APPEND srcs + "esp_ble_mesh/v1.1/api/core/esp_ble_mesh_agg_model_api.c" + "esp_ble_mesh/v1.1/api/core/esp_ble_mesh_brc_model_api.c" + "esp_ble_mesh/v1.1/api/core/esp_ble_mesh_cm_data_api.c" + "esp_ble_mesh/v1.1/api/core/esp_ble_mesh_df_model_api.c" + "esp_ble_mesh/v1.1/api/core/esp_ble_mesh_lcd_model_api.c" + "esp_ble_mesh/v1.1/api/core/esp_ble_mesh_odp_model_api.c" + "esp_ble_mesh/v1.1/api/core/esp_ble_mesh_prb_model_api.c" + "esp_ble_mesh/v1.1/api/core/esp_ble_mesh_rpr_model_api.c" + "esp_ble_mesh/v1.1/api/core/esp_ble_mesh_sar_model_api.c" + "esp_ble_mesh/v1.1/api/core/esp_ble_mesh_srpl_model_api.c" + "esp_ble_mesh/v1.1/api/models/esp_ble_mesh_mbt_model_api.c" + "esp_ble_mesh/v1.1/btc/btc_ble_mesh_agg_model.c" + "esp_ble_mesh/v1.1/btc/btc_ble_mesh_brc_model.c" + "esp_ble_mesh/v1.1/btc/btc_ble_mesh_df_model.c" + "esp_ble_mesh/v1.1/btc/btc_ble_mesh_lcd_model.c" + "esp_ble_mesh/v1.1/btc/btc_ble_mesh_mbt_model.c" + "esp_ble_mesh/v1.1/btc/btc_ble_mesh_odp_model.c" + "esp_ble_mesh/v1.1/btc/btc_ble_mesh_prb_model.c" + "esp_ble_mesh/v1.1/btc/btc_ble_mesh_rpr_model.c" + "esp_ble_mesh/v1.1/btc/btc_ble_mesh_sar_model.c" + "esp_ble_mesh/v1.1/btc/btc_ble_mesh_srpl_model.c" + "esp_ble_mesh/lib/ext.c") + if(CONFIG_BLE_MESH_SAR_ENHANCEMENT) + list(APPEND srcs "esp_ble_mesh/core/transport.enh.c") + else() + list(APPEND srcs "esp_ble_mesh/core/transport.c") + endif() else() - list(APPEND srcs "esp_ble_mesh/core/transport.c") + list(APPEND srcs + "esp_ble_mesh/core/transport.c") endif() endif() @@ -879,7 +894,7 @@ if(CONFIG_BT_ENABLED) target_compile_options(${COMPONENT_LIB} PRIVATE "-Wno-format") endif() -if(CONFIG_BLE_MESH) +if(CONFIG_BLE_MESH_V11_SUPPORT) if(CONFIG_IDF_TARGET_ESP32) add_prebuilt_library(ble_mesh "esp_ble_mesh/lib/lib/esp32/libble_mesh.a") target_link_libraries(${COMPONENT_LIB} PRIVATE ble_mesh) diff --git a/components/bt/common/btc/core/btc_task.c b/components/bt/common/btc/core/btc_task.c index 875f64b18a5..7859c99cd37 100644 --- a/components/bt/common/btc/core/btc_task.c +++ b/components/bt/common/btc/core/btc_task.c @@ -69,6 +69,12 @@ #include "btc_ble_mesh_prov.h" #include "btc_ble_mesh_health_model.h" #include "btc_ble_mesh_config_model.h" +#include "btc_ble_mesh_generic_model.h" +#include "btc_ble_mesh_lighting_model.h" +#include "btc_ble_mesh_sensor_model.h" +#include "btc_ble_mesh_time_scene_model.h" +#if CONFIG_BLE_MESH_V11_SUPPORT +#include "btc_ble_mesh_mbt_model.h" #include "btc_ble_mesh_agg_model.h" #include "btc_ble_mesh_brc_model.h" #include "btc_ble_mesh_df_model.h" @@ -78,11 +84,7 @@ #include "btc_ble_mesh_rpr_model.h" #include "btc_ble_mesh_sar_model.h" #include "btc_ble_mesh_srpl_model.h" -#include "btc_ble_mesh_generic_model.h" -#include "btc_ble_mesh_lighting_model.h" -#include "btc_ble_mesh_sensor_model.h" -#include "btc_ble_mesh_time_scene_model.h" -#include "btc_ble_mesh_mbt_model.h" +#endif /* CONFIG_BLE_MESH_V11_SUPPORT */ #endif /* #if CONFIG_BLE_MESH */ #define BTC_TASK_PINNED_TO_CORE (TASK_PINNED_TO_CORE) diff --git a/components/bt/esp_ble_mesh/Kconfig.in b/components/bt/esp_ble_mesh/Kconfig.in index 17d23ba94ec..47c6fad2c03 100644 --- a/components/bt/esp_ble_mesh/Kconfig.in +++ b/components/bt/esp_ble_mesh/Kconfig.in @@ -6,6 +6,12 @@ if BLE_MESH help It is a temporary solution and needs further modifications. + config BLE_MESH_V11_SUPPORT + bool "Support ESP BLE Mesh v1.1 features (Preview)" + default y + help + Support BLE Mesh v1.1 features + config BLE_MESH_RANDOM_ADV_INTERVAL bool "Support using random adv interval for mesh packets" select BT_BLE_HIGH_DUTY_ADV_INTERVAL if BT_BLUEDROID_ENABLED @@ -32,6 +38,7 @@ if BLE_MESH config BLE_MESH_ACTIVE_SCAN bool "Support Active Scan in BLE Mesh" + depends on BLE_MESH_V11_SUPPORT help Enable this option to allow using BLE Active Scan for BLE Mesh. @@ -281,6 +288,7 @@ if BLE_MESH config BLE_MESH_PROV_EPA bool "BLE Mesh enhanced provisioning authentication" depends on BLE_MESH_PROV + depends on BLE_MESH_V11_SUPPORT default y help Enable this option to support BLE Mesh enhanced provisioning authentication @@ -290,6 +298,7 @@ if BLE_MESH config BLE_MESH_CERT_BASED_PROV bool "Support Certificate-based provisioning" depends on BLE_MESH_PROV + depends on BLE_MESH_V11_SUPPORT default n help Enable this option to support BLE Mesh Certificate-Based Provisioning. @@ -390,6 +399,7 @@ if BLE_MESH config BLE_MESH_PROXY_SOLIC_PDU_RX bool "Support receiving Proxy Solicitation PDU" depends on BLE_MESH_GATT_PROXY_SERVER + depends on BLE_MESH_V11_SUPPORT help Enable this option to support receiving Proxy Solicitation PDU. @@ -417,6 +427,7 @@ if BLE_MESH config BLE_MESH_PROXY_SOLIC_PDU_TX bool "Support sending Proxy Solicitation PDU" depends on BLE_MESH_GATT_PROXY_CLIENT + depends on BLE_MESH_V11_SUPPORT help Enable this option to support sending Proxy Solicitation PDU. @@ -703,6 +714,7 @@ if BLE_MESH to perform the IV index recovery procedure. config BLE_MESH_SAR_ENHANCEMENT + depends on BLE_MESH_V11_SUPPORT bool "Segmentation and reassembly enhancement" default n help @@ -1102,253 +1114,257 @@ if BLE_MESH help Enable support for Health Server model. - config BLE_MESH_BRC_CLI - bool "Bridge Configuration Client model" - help - Enable support for Bridge Configuration Client model. - - config BLE_MESH_BRC_SRV - bool "Bridge Configuration Server model" - default n - help - Enable support for Bridge Configuration Server model. - - if BLE_MESH_BRC_SRV + if BLE_MESH_V11_SUPPORT - config BLE_MESH_MAX_BRIDGING_TABLE_ENTRY_COUNT - int "Maximum number of Bridging Table entries" - range 16 65535 - default 16 + config BLE_MESH_BRC_CLI + bool "Bridge Configuration Client model" help - Maximum number of Bridging Table entries that the Bridge Configuration Server can support. + Enable support for Bridge Configuration Client model. - config BLE_MESH_BRIDGE_CRPL - int "Maximum capacity of bridge replay protection list" - default 5 - range 1 255 + config BLE_MESH_BRC_SRV + bool "Bridge Configuration Server model" + default n help - This option specifies the maximum capacity of the bridge replay - protection list. The bridge replay protection list is used to - prevent a bridged subnet from replay attack, which will store the - source address and sequence number of the received bridge messages. + Enable support for Bridge Configuration Server model. - endif #BLE_MESH_BRC_SRV + if BLE_MESH_BRC_SRV - config BLE_MESH_PRB_CLI - bool "Mesh Private Beacon Client model" - help - Enable support for Mesh Private Beacon Client model. + config BLE_MESH_MAX_BRIDGING_TABLE_ENTRY_COUNT + int "Maximum number of Bridging Table entries" + range 16 65535 + default 16 + help + Maximum number of Bridging Table entries that the Bridge Configuration Server can support. - config BLE_MESH_PRB_SRV - bool "Mesh Private Beacon Server model" - help - Enable support for Mesh Private Beacon Server model. + config BLE_MESH_BRIDGE_CRPL + int "Maximum capacity of bridge replay protection list" + default 5 + range 1 255 + help + This option specifies the maximum capacity of the bridge replay + protection list. The bridge replay protection list is used to + prevent a bridged subnet from replay attack, which will store the + source address and sequence number of the received bridge messages. - config BLE_MESH_ODP_CLI - bool "On-Demand Private Proxy Client model" - help - Enable support for On-Demand Private Proxy Client model. + endif #BLE_MESH_BRC_SRV - config BLE_MESH_ODP_SRV - bool "On-Demand Private Proxy Server model" - depends on BLE_MESH_PROXY_SOLIC_PDU_RX - select BLE_MESH_SRPL_SRV - help - Enable support for On-Demand Private Proxy Server model. + config BLE_MESH_PRB_CLI + bool "Mesh Private Beacon Client model" + help + Enable support for Mesh Private Beacon Client model. - config BLE_MESH_SRPL_CLI - bool "Solicitation PDU RPL Configuration Client model" - help - Enable support for Solicitation PDU RPL Configuration Client model. + config BLE_MESH_PRB_SRV + bool "Mesh Private Beacon Server model" + help + Enable support for Mesh Private Beacon Server model. - config BLE_MESH_SRPL_SRV - bool "Solicitation PDU RPL Configuration Server model" - depends on BLE_MESH_PROXY_SOLIC_PDU_RX - help - Enable support for Solicitation PDU RPL Configuration Server model. - Note: - This option depends on the functionality of receiving Solicitation - PDU. If the device doesn't support receiving Solicitation PDU, then - there is no need to enable this server model. + config BLE_MESH_ODP_CLI + bool "On-Demand Private Proxy Client model" + help + Enable support for On-Demand Private Proxy Client model. - config BLE_MESH_AGG_CLI - bool "Opcodes Aggregator Client model" - help - Enable support for Opcodes Aggregator Client model. + config BLE_MESH_ODP_SRV + bool "On-Demand Private Proxy Server model" + depends on BLE_MESH_PROXY_SOLIC_PDU_RX + select BLE_MESH_SRPL_SRV + help + Enable support for On-Demand Private Proxy Server model. - config BLE_MESH_AGG_SRV - bool "Opcodes Aggregator Server model" - help - Enable support for Opcodes Aggregator Server model. + config BLE_MESH_SRPL_CLI + bool "Solicitation PDU RPL Configuration Client model" + help + Enable support for Solicitation PDU RPL Configuration Client model. - config BLE_MESH_SAR_CLI - bool "SAR Configuration Client model" - help - Enable support for SAR Configuration Client model. + config BLE_MESH_SRPL_SRV + bool "Solicitation PDU RPL Configuration Server model" + depends on BLE_MESH_PROXY_SOLIC_PDU_RX + help + Enable support for Solicitation PDU RPL Configuration Server model. + Note: + This option depends on the functionality of receiving Solicitation + PDU. If the device doesn't support receiving Solicitation PDU, then + there is no need to enable this server model. + + config BLE_MESH_AGG_CLI + bool "Opcodes Aggregator Client model" + help + Enable support for Opcodes Aggregator Client model. - config BLE_MESH_SAR_SRV - bool "SAR Configuration Server model" - help - Enable support for SAR Configuration Server model. + config BLE_MESH_AGG_SRV + bool "Opcodes Aggregator Server model" + help + Enable support for Opcodes Aggregator Server model. - config BLE_MESH_COMP_DATA_1 - bool "Support Composition Data Page 1" - help - Composition Data Page 1 contains information about the relationships - among models. - Each model either can be a root model or can extend other models. + config BLE_MESH_SAR_CLI + bool "SAR Configuration Client model" + help + Enable support for SAR Configuration Client model. - config BLE_MESH_COMP_DATA_128 - bool "Support Composition Data Page 128" - help - Composition Data Page 128 is used to indicate the structure of - elements, features, and models of a node after the successful - execution of the Node Address Refresh procedure or the Node - Composition Refresh procedure, or after the execution of the - Node Removal procedure followed by the provisioning process. - Composition Data Page 128 shall be present if the node supports - the Remote Provisioning Server model; otherwise it is optional. + config BLE_MESH_SAR_SRV + bool "SAR Configuration Server model" + help + Enable support for SAR Configuration Server model. - config BLE_MESH_MODELS_METADATA_0 - bool "Support Models Metadata Page 0" - help - The Models Metadata state contains metadata of a node’s models. - The Models Metadata state is composed of a number of pages of - information. - Models Metadata Page 0 shall be present if the node supports - the Large Composition Data Server model. + config BLE_MESH_COMP_DATA_1 + bool "Support Composition Data Page 1" + help + Composition Data Page 1 contains information about the relationships + among models. + Each model either can be a root model or can extend other models. - config BLE_MESH_MODELS_METADATA_128 - bool "Support Models Metadata Page 128" - depends on BLE_MESH_MODELS_METADATA_0 - help - The Models Metadata state contains metadata of a node’s models. - The Models Metadata state is composed of a number of pages of - information. - Models Metadata Page 128 contains metadata for the node’s models - after the successful execution of the Node Address Refresh - procedure or the Node Composition Refresh procedure, or after - the execution of the Node Removal procedure followed by the - provisioning process. - Models Metadata Page 128 shall be present if the node supports - the Remote Provisioning Server model and the node supports the - Large Composition Data Server model. + config BLE_MESH_COMP_DATA_128 + bool "Support Composition Data Page 128" + help + Composition Data Page 128 is used to indicate the structure of + elements, features, and models of a node after the successful + execution of the Node Address Refresh procedure or the Node + Composition Refresh procedure, or after the execution of the + Node Removal procedure followed by the provisioning process. + Composition Data Page 128 shall be present if the node supports + the Remote Provisioning Server model; otherwise it is optional. + + config BLE_MESH_MODELS_METADATA_0 + bool "Support Models Metadata Page 0" + help + The Models Metadata state contains metadata of a node’s models. + The Models Metadata state is composed of a number of pages of + information. + Models Metadata Page 0 shall be present if the node supports + the Large Composition Data Server model. + + config BLE_MESH_MODELS_METADATA_128 + bool "Support Models Metadata Page 128" + depends on BLE_MESH_MODELS_METADATA_0 + help + The Models Metadata state contains metadata of a node’s models. + The Models Metadata state is composed of a number of pages of + information. + Models Metadata Page 128 contains metadata for the node’s models + after the successful execution of the Node Address Refresh + procedure or the Node Composition Refresh procedure, or after + the execution of the Node Removal procedure followed by the + provisioning process. + Models Metadata Page 128 shall be present if the node supports + the Remote Provisioning Server model and the node supports the + Large Composition Data Server model. + + config BLE_MESH_LCD_CLI + bool "Large Composition Data Client model" + help + Enable support for Large Composition Data Client model. - config BLE_MESH_LCD_CLI - bool "Large Composition Data Client model" - help - Enable support for Large Composition Data Client model. + config BLE_MESH_LCD_SRV + bool "Large Composition Data Server model" + select BLE_MESH_MODELS_METADATA_0 + help + Enable support for Large Composition Data Server model. - config BLE_MESH_LCD_SRV - bool "Large Composition Data Server model" - select BLE_MESH_MODELS_METADATA_0 - help - Enable support for Large Composition Data Server model. + config BLE_MESH_RPR_CLI + bool "Remote Provisioning Client model" + depends on BLE_MESH_PROVISIONER + select BLE_MESH_PROV + help + Enable support for Remote Provisioning Client model - config BLE_MESH_RPR_CLI - bool "Remote Provisioning Client model" - depends on BLE_MESH_PROVISIONER - select BLE_MESH_PROV - help - Enable support for Remote Provisioning Client model + if BLE_MESH_RPR_CLI - if BLE_MESH_RPR_CLI + config BLE_MESH_RPR_CLI_PROV_SAME_TIME + int "Maximum number of PB-Remote running at the same time by Provisioner" + range 1 5 + default 2 + help + This option specifies how many devices can be provisioned at the same time + using PB-REMOTE. For example, if the value is 2, it means a Provisioner can + provision two unprovisioned devices with PB-REMOTE at the same time. - config BLE_MESH_RPR_CLI_PROV_SAME_TIME - int "Maximum number of PB-Remote running at the same time by Provisioner" - range 1 5 - default 2 + endif # BLE_MESH_RPR_CLI + + config BLE_MESH_RPR_SRV + bool "Remote Provisioning Server model" + depends on BLE_MESH_NODE + select BLE_MESH_PB_ADV help - This option specifies how many devices can be provisioned at the same time - using PB-REMOTE. For example, if the value is 2, it means a Provisioner can - provision two unprovisioned devices with PB-REMOTE at the same time. + Enable support for Remote Provisioning Server model - endif # BLE_MESH_RPR_CLI + if BLE_MESH_RPR_SRV - config BLE_MESH_RPR_SRV - bool "Remote Provisioning Server model" - depends on BLE_MESH_NODE - select BLE_MESH_PB_ADV - help - Enable support for Remote Provisioning Server model + config BLE_MESH_RPR_SRV_MAX_SCANNED_ITEMS + int "Maximum number of device information can be scanned" + range 4 255 + default 10 + help + This option specifies how many device information can a Remote + Provisioning Server store each time while scanning. - if BLE_MESH_RPR_SRV + config BLE_MESH_RPR_SRV_ACTIVE_SCAN + bool "Support Active Scan for remote provisioning" + select BLE_MESH_ACTIVE_SCAN + help + Enable this option to support Active Scan for remote provisioning. - config BLE_MESH_RPR_SRV_MAX_SCANNED_ITEMS - int "Maximum number of device information can be scanned" - range 4 255 - default 10 - help - This option specifies how many device information can a Remote - Provisioning Server store each time while scanning. + config BLE_MESH_RPR_SRV_MAX_EXT_SCAN + int "Maximum number of extended scan procedures" + range 1 10 + default 1 + help + This option specifies how many extended scan procedures can be + started by the Remote Provisioning Server. - config BLE_MESH_RPR_SRV_ACTIVE_SCAN - bool "Support Active Scan for remote provisioning" - select BLE_MESH_ACTIVE_SCAN - help - Enable this option to support Active Scan for remote provisioning. + endif # BLE_MESH_RPR_SRV - config BLE_MESH_RPR_SRV_MAX_EXT_SCAN - int "Maximum number of extended scan procedures" - range 1 10 - default 1 + config BLE_MESH_DF_CLI + bool "Directed Forwarding Configuration Client model" help - This option specifies how many extended scan procedures can be - started by the Remote Provisioning Server. + Enable support for Directed Forwarding Configuration Client model. - endif # BLE_MESH_RPR_SRV + config BLE_MESH_DF_SRV + bool "Directed Forwarding Configuration Server model" + help + Enable support for Directed Forwarding Configuration Server model. - config BLE_MESH_DF_CLI - bool "Directed Forwarding Configuration Client model" - help - Enable support for Directed Forwarding Configuration Client model. + if BLE_MESH_DF_SRV - config BLE_MESH_DF_SRV - bool "Directed Forwarding Configuration Server model" - help - Enable support for Directed Forwarding Configuration Server model. + config BLE_MESH_MAX_DISC_TABLE_ENTRY_COUNT + int "Maximum number of discovery table entries in a given subnet" + range 2 255 + default 2 + help + Maximum number of Discovery Table entries supported by the node in a given subnet. - if BLE_MESH_DF_SRV + config BLE_MESH_MAX_FORWARD_TABLE_ENTRY_COUNT + int "Maximum number of forward table entries in a given subnet" + range 2 64 + default 2 + help + Maximum number of Forward Table entries supported by the node in a given subnet. - config BLE_MESH_MAX_DISC_TABLE_ENTRY_COUNT - int "Maximum number of discovery table entries in a given subnet" - range 2 255 - default 2 - help - Maximum number of Discovery Table entries supported by the node in a given subnet. + config BLE_MESH_MAX_DEPS_NODES_PER_PATH + int "Maximum number of dependent nodes per path" + range 2 64 + default 2 + help + Maximum size of dependent nodes list supported by each forward table entry. - config BLE_MESH_MAX_FORWARD_TABLE_ENTRY_COUNT - int "Maximum number of forward table entries in a given subnet" - range 2 64 - default 2 - help - Maximum number of Forward Table entries supported by the node in a given subnet. + config BLE_MESH_PATH_MONITOR_TEST + bool "Enable Path Monitoring test mode" + default n + help + The option only removes the Path Use timer; all other behavior of the + device is not changed. + If Path Monitoring test mode is going to be used, this option should + be enabled. - config BLE_MESH_MAX_DEPS_NODES_PER_PATH - int "Maximum number of dependent nodes per path" - range 2 64 - default 2 - help - Maximum size of dependent nodes list supported by each forward table entry. + if BLE_MESH_GATT_PROXY_SERVER + config BLE_MESH_SUPPORT_DIRECTED_PROXY + bool "Enable Directed Proxy functionality" + default y + help + Support Directed Proxy functionality. + endif - config BLE_MESH_PATH_MONITOR_TEST - bool "Enable Path Monitoring test mode" - default n - help - The option only removes the Path Use timer; all other behavior of the - device is not changed. - If Path Monitoring test mode is going to be used, this option should - be enabled. - - if BLE_MESH_GATT_PROXY_SERVER - config BLE_MESH_SUPPORT_DIRECTED_PROXY - bool "Enable Directed Proxy functionality" - default y - help - Support Directed Proxy functionality. - endif + endif # BLE_MESH_DF_SRV - endif # BLE_MESH_DF_SRV + endif # BLE_MESH_V11_SUPPORT endmenu #Support for BLE Mesh Foundation models @@ -1465,6 +1481,7 @@ if BLE_MESH config BLE_MESH_MBT_CLI bool "BLOB Transfer Client model" + depends on BLE_MESH_V11_SUPPORT default n help Enable support for BLOB Transfer Client model. @@ -1483,6 +1500,7 @@ if BLE_MESH config BLE_MESH_MBT_SRV bool "BLOB Transfer Server model" + depends on BLE_MESH_V11_SUPPORT default n help Enable support for BLOB Transfer Server model. diff --git a/components/bt/esp_ble_mesh/btc/btc_ble_mesh_prov.c b/components/bt/esp_ble_mesh/btc/btc_ble_mesh_prov.c index 67d5353be8f..f6cdb426f1b 100644 --- a/components/bt/esp_ble_mesh/btc/btc_ble_mesh_prov.c +++ b/components/bt/esp_ble_mesh/btc/btc_ble_mesh_prov.c @@ -10,11 +10,13 @@ #include "btc_ble_mesh_prov.h" #include "btc_ble_mesh_config_model.h" #include "btc_ble_mesh_health_model.h" -#include "btc_ble_mesh_prb_model.h" #include "btc_ble_mesh_generic_model.h" #include "btc_ble_mesh_time_scene_model.h" #include "btc_ble_mesh_sensor_model.h" #include "btc_ble_mesh_lighting_model.h" + +#if CONFIG_BLE_MESH_V11_SUPPORT +#include "btc_ble_mesh_prb_model.h" #include "btc_ble_mesh_brc_model.h" #include "btc_ble_mesh_odp_model.h" #include "btc_ble_mesh_srpl_model.h" @@ -24,6 +26,8 @@ #include "btc_ble_mesh_rpr_model.h" #include "btc_ble_mesh_df_model.h" #include "btc_ble_mesh_mbt_model.h" +#include "mesh_v1.1/utils.h" +#endif /* CONFIG_BLE_MESH_V11_SUPPORT */ #include "adv.h" #include "mesh/kernel.h" @@ -65,8 +69,6 @@ #include "mesh/state_binding.h" #include "local.h" -#include "mesh_v1.1/utils.h" - #include "esp_ble_mesh_common_api.h" #include "esp_ble_mesh_provisioning_api.h" #include "esp_ble_mesh_networking_api.h" diff --git a/components/bt/esp_ble_mesh/core/access.c b/components/bt/esp_ble_mesh/core/access.c index 9606581eb89..3791add9e34 100644 --- a/components/bt/esp_ble_mesh/core/access.c +++ b/components/bt/esp_ble_mesh/core/access.c @@ -2,7 +2,7 @@ /* * SPDX-FileCopyrightText: 2017 Intel Corporation - * SPDX-FileContributor: 2018-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileContributor: 2018-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -11,6 +11,7 @@ #include #include "mesh.h" +#include "tag.h" #include "adv.h" #include "lpn.h" #include "friend.h" @@ -22,7 +23,9 @@ #include "fast_prov.h" #include "pvnr_mgmt.h" +#if CONFIG_BLE_MESH_V11_SUPPORT #include "mesh_v1.1/utils.h" +#endif #define BLE_MESH_SDU_MAX_LEN 384 @@ -814,6 +817,135 @@ static bool ready_to_send(uint16_t dst) return false; } +#if !CONFIG_BLE_MESH_V11_SUPPORT +static bool use_friend_cred(uint16_t net_idx, uint16_t dst) +{ + /* Currently LPN only supports using NetKey in bt_mesh.sub[0] */ + if (IS_ENABLED(CONFIG_BLE_MESH_LOW_POWER) && + net_idx == 0 && + bt_mesh_lpn_match(dst)) { + return true; + } + + if (IS_ENABLED(CONFIG_BLE_MESH_FRIEND) && + bt_mesh_friend_match(net_idx, dst)) { + return true; + } + + return false; +} + +bool bt_mesh_valid_security_cred(struct bt_mesh_net_tx *tx) +{ + /* If the message is tagged with immutable-credentials, + * then the security credentials shall not be changed + * in lower layers. + * If not, later a better security credentials could be + * chosen for the message. + */ + if (!bt_mesh_tag_immutable_cred(tx->ctx->send_tag)) { + return true; + } + + if (tx->ctx->send_cred > BLE_MESH_FRIENDSHIP_CRED) { + return false; + } + + if (tx->ctx->send_cred == BLE_MESH_FRIENDSHIP_CRED && + !use_friend_cred(tx->ctx->net_idx, tx->ctx->addr)) { + return false; + } + + return true; +} + +void bt_mesh_choose_better_security_cred(struct bt_mesh_net_tx *tx) +{ + uint8_t send_cred = 0U; + uint8_t send_tag = 0U; + uint16_t net_idx = 0U; + uint16_t addr = 0U; + + send_cred = tx->ctx->send_cred; + send_tag = tx->ctx->send_tag; + net_idx = tx->ctx->net_idx; + addr = tx->ctx->addr; + + /* If the message is tagged with immutable-credentials, + * then the security credentials shall not be changed. + */ + if (bt_mesh_tag_immutable_cred(send_tag)) { + return; + } + + if (send_cred > BLE_MESH_FRIENDSHIP_CRED) { + BT_INFO("Use managed flooding security credentials"); + tx->ctx->send_cred = BLE_MESH_FLOODING_CRED; + return; + } + + if (send_cred == BLE_MESH_FRIENDSHIP_CRED) { + if (!use_friend_cred(net_idx, addr)) { + BT_INFO("Use managed flooding security credentials"); + tx->ctx->send_cred = BLE_MESH_FLOODING_CRED; + tx->ctx->send_tag = send_tag | BLE_MESH_TAG_IMMUTABLE_CRED; + } else { + /* TODO: + * For LPN, do we need to change the friendship security + * credentials to managed flooding credentials? + * If changed, this could increase the possibility that + * the corresponding Friend node receives this message. + */ + } + return; + } + + /* If the message is destinated to a LPN, the following could be + * introduced to send the message with the friendship credentials. + * + * For LPN, this optimization should not be introduced, since it + * may cause the message failed to received by the Friend node, + * using friendship credentials will make the message can not be + * relayed by other mesh nodes. + */ + if (IS_ENABLED(CONFIG_BLE_MESH_FRIEND) && + BLE_MESH_ADDR_IS_UNICAST(addr) && + bt_mesh_friend_match(net_idx, addr)) { + BT_INFO("Use friendship security credentials"); + tx->ctx->send_cred = BLE_MESH_FRIENDSHIP_CRED; + tx->ctx->send_tag = send_tag | BLE_MESH_TAG_IMMUTABLE_CRED; + return; + } + + /** + * Spec 3.7.3.1 + * The Low power node in friendship should use friendship security + * material. + * + * But in Spec 3.6.6.2 + * Depending on the value of the Publish Friendship Credentials Flag + * (see Section 4.2.3.4), the Low Power node model publishes messages + * using either the friendship security credentials or the managed + * flooding security credentials (see Section 3.9.6.3.1). + * + * So use the BLE_MESH_TAG_IMMUTABLE_CRED to indicate that the + * credentials of the message should not be changed when the + * message is sent by model publishing, even though the spec + * didn't require this flag to be set when model publishing. + */ + +#if CONFIG_BLE_MESH_LOW_POWER + if (BLE_MESH_ADDR_IS_UNICAST(addr) && + bt_mesh.lpn.frnd == addr && + !bt_mesh_tag_immutable_cred(send_tag)) { + tx->ctx->send_cred = BLE_MESH_FRIENDSHIP_CRED; + tx->ctx->send_tag = send_tag | BLE_MESH_TAG_IMMUTABLE_CRED; + return; + } +#endif +} +#endif /* !CONFIG_BLE_MESH_V11_SUPPORT */ + static int model_send(struct bt_mesh_model *model, struct bt_mesh_net_tx *tx, bool implicit_bind, struct net_buf_simple *msg, @@ -1108,11 +1240,13 @@ size_t bt_mesh_rx_devkey_size(void) #if CONFIG_BLE_MESH_NODE && !CONFIG_BLE_MESH_PROVISIONER if (bt_mesh_is_provisioned()) { size = 1; +#if CONFIG_BLE_MESH_RPR_SRV if (bt_mesh_dev_key_ca_valid()) { size += 1; } +#endif /* CONFIG_BLE_MESH_RPR_SRV */ } -#endif +#endif /* CONFIG_BLE_MESH_NODE && !CONFIG_BLE_MESH_PROVISIONER */ #if !CONFIG_BLE_MESH_NODE && CONFIG_BLE_MESH_PROVISIONER if (bt_mesh_is_provisioner_en()) { @@ -1122,9 +1256,11 @@ size_t bt_mesh_rx_devkey_size(void) #if CONFIG_BLE_MESH_NODE && CONFIG_BLE_MESH_PROVISIONER size = 1; +#if CONFIG_BLE_MESH_RPR_SRV if (bt_mesh_dev_key_ca_valid()) { size += 1; } +#endif /* CONFIG_BLE_MESH_RPR_SRV */ if (bt_mesh_is_provisioner_en()) { size += 1; } @@ -1156,7 +1292,9 @@ const uint8_t *bt_mesh_rx_devkey_get(size_t index, uint16_t src) #if CONFIG_BLE_MESH_NODE && CONFIG_BLE_MESH_PROVISIONER if (index == 0) { key = bt_mesh.dev_key; - } else if (index == 1 && bt_mesh_dev_key_ca_valid()) { + } else +#if CONFIG_BLE_MESH_RPR_SRV + if (index == 1 && bt_mesh_dev_key_ca_valid()) { /* If index == 1, there are two cases. * 1. bt_mesh_dev_key_ca_valid() is true, it should be return bt_mesh.dev_key_ca. * 2. bt_mesh_is_provisioner_en() is true, it should be return bt_mesh_provisioner_dev_key_get(src). @@ -1166,7 +1304,9 @@ const uint8_t *bt_mesh_rx_devkey_get(size_t index, uint16_t src) * Then this round of function bt_mesh_rx_devkey_get(2, src) will return bt_mesh_provisioner_dev_key_get(src). */ key = bt_mesh.dev_key_ca; - } else { + } else +#endif + { key = bt_mesh_provisioner_dev_key_get(src); } #endif diff --git a/components/bt/esp_ble_mesh/core/beacon.c b/components/bt/esp_ble_mesh/core/beacon.c index 488a3c5f6d0..45e4a2d1a95 100644 --- a/components/bt/esp_ble_mesh/core/beacon.c +++ b/components/bt/esp_ble_mesh/core/beacon.c @@ -2,7 +2,7 @@ /* * SPDX-FileCopyrightText: 2017 Intel Corporation - * SPDX-FileContributor: 2018-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileContributor: 2018-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -25,7 +25,9 @@ #include "pvnr_mgmt.h" #include "mesh/common.h" +#if CONFIG_BLE_MESH_V11_SUPPORT #include "mesh_v1.1/utils.h" +#endif #if defined(CONFIG_BLE_MESH_UNPROVISIONED_BEACON_INTERVAL) #define UNPROV_BEACON_INTERVAL K_SECONDS(CONFIG_BLE_MESH_UNPROVISIONED_BEACON_INTERVAL) @@ -472,12 +474,13 @@ void bt_mesh_beacon_recv(struct net_buf_simple *buf, int8_t rssi) bt_mesh_provisioner_unprov_beacon_recv(buf, rssi); } - if (IS_ENABLED(CONFIG_BLE_MESH_RPR_SRV) && - bt_mesh_is_provisioned()) { +#if CONFIG_BLE_MESH_RPR_SRV + if (bt_mesh_is_provisioned()) { const bt_mesh_addr_t *addr = bt_mesh_get_unprov_dev_addr(); bt_mesh_unprov_dev_fifo_enqueue(buf->data, addr->val, bt_mesh_get_adv_type()); bt_mesh_rpr_srv_unprov_beacon_recv(buf, bt_mesh_get_adv_type(), addr, rssi); } +#endif break; case BEACON_TYPE_SECURE: secure_beacon_recv(buf); diff --git a/components/bt/esp_ble_mesh/core/bluedroid_host/adapter.c b/components/bt/esp_ble_mesh/core/bluedroid_host/adapter.c index e0fc33b4844..f16456d6dd9 100644 --- a/components/bt/esp_ble_mesh/core/bluedroid_host/adapter.c +++ b/components/bt/esp_ble_mesh/core/bluedroid_host/adapter.c @@ -32,7 +32,9 @@ #include "net.h" #include "beacon.h" +#if CONFIG_BLE_MESH_V11_SUPPORT #include "mesh_v1.1/utils.h" +#endif struct bt_mesh_dev bt_mesh_dev; diff --git a/components/bt/esp_ble_mesh/core/cfg_srv.c b/components/bt/esp_ble_mesh/core/cfg_srv.c index 9d91cb217b3..a8fe1af424d 100644 --- a/components/bt/esp_ble_mesh/core/cfg_srv.c +++ b/components/bt/esp_ble_mesh/core/cfg_srv.c @@ -2,7 +2,7 @@ /* * SPDX-FileCopyrightText: 2017 Intel Corporation - * SPDX-FileContributor: 2018-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileContributor: 2018-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -30,7 +30,9 @@ #include "mesh/common.h" #include "heartbeat.h" +#if CONFIG_BLE_MESH_V11_SUPPORT #include "mesh_v1.1/utils.h" +#endif #define DEFAULT_TTL 7 @@ -38,6 +40,158 @@ static struct bt_mesh_cfg_srv *conf; static struct label labels[CONFIG_BLE_MESH_LABEL_COUNT]; +#if !CONFIG_BLE_MESH_V11_SUPPORT +const void *comp_0; + +static uint8_t bt_mesh_comp_page_check(uint8_t page, bool largest) +{ + /* If the page doesn't exist, TWO situations currently: + * 1. For Composition Data Get: + * With the Page field set to the largest page number of + * the Composition Data that the node supports and that is + * less than the Page field value of the received Config + * Composition Data Get message; + * 2. For Large Composition Data Get: + * The Page field shall be set to the largest page number + * of the Composition Data that the node supports. + */ + ARG_UNUSED(largest); + + if (page != 0) { + BT_WARN("Composition Data Page %d not exists", page); + } + + return 0; +} + +static inline uint16_t get_comp_elem_size(struct bt_mesh_elem *elem) +{ + return (4 + elem->model_count * 2 + elem->vnd_model_count * 4); +} + +static uint16_t get_comp_data_size(const struct bt_mesh_comp *comp) +{ + uint16_t size = 10; /* CID + PID + VID + CRPL + Features */ + + for (int i = 0; i < comp->elem_count; i++) { + size += get_comp_elem_size(&(comp->elem[i])); + } + + return size; +} + +static void get_comp_data(struct net_buf_simple *buf, + const struct bt_mesh_comp *comp, + bool full_element) +{ + struct bt_mesh_model *model = NULL; + struct bt_mesh_elem *elem = NULL; + uint16_t feat = 0; + + if (IS_ENABLED(CONFIG_BLE_MESH_RELAY)) { + feat |= BLE_MESH_FEAT_RELAY; + } + + if (IS_ENABLED(CONFIG_BLE_MESH_GATT_PROXY_SERVER)) { + feat |= BLE_MESH_FEAT_PROXY; + } + + if (IS_ENABLED(CONFIG_BLE_MESH_FRIEND)) { + feat |= BLE_MESH_FEAT_FRIEND; + } + + if (IS_ENABLED(CONFIG_BLE_MESH_LOW_POWER)) { + feat |= BLE_MESH_FEAT_LOW_POWER; + } + + net_buf_simple_add_le16(buf, comp->cid); + net_buf_simple_add_le16(buf, comp->pid); + net_buf_simple_add_le16(buf, comp->vid); + net_buf_simple_add_le16(buf, CONFIG_BLE_MESH_CRPL); + net_buf_simple_add_le16(buf, feat); + + for (size_t i = 0; i < comp->elem_count; i++) { + elem = &(comp->elem[i]); + + /* If "full_element" is true, which means the complete list + * of models within the element needs to fit in the data, + * otherwise the element shall not be reported. + */ + if (full_element && + net_buf_simple_tailroom(buf) < get_comp_elem_size(elem)) { + return; + } + + net_buf_simple_add_le16(buf, elem->loc); + net_buf_simple_add_u8(buf, elem->model_count); + net_buf_simple_add_u8(buf, elem->vnd_model_count); + + for (size_t j = 0; j < elem->model_count; j++) { + model = &(elem->models[j]); + net_buf_simple_add_le16(buf, model->id); + } + + for (size_t j = 0; j < elem->vnd_model_count; j++) { + model = &(elem->vnd_models[j]); + net_buf_simple_add_le16(buf, model->vnd.company); + net_buf_simple_add_le16(buf, model->vnd.id); + } + } +} + +static int fetch_comp_data(struct net_buf_simple *buf, + const struct bt_mesh_comp *comp, + uint8_t page, uint16_t offset, + bool full_element) +{ + uint16_t size = get_comp_data_size(comp); + + if (offset >= size) { + BT_WARN("Too large offset %d for comp data %d, size %d", + page, offset, size); + return 0; + } + + if (net_buf_simple_tailroom(buf) < 10 || + size - offset > net_buf_simple_tailroom(buf)) { + BT_ERR("Too small buffer for comp data %d, %d, expected %d", + page, buf->size, size - offset); + return -EINVAL; + } + + if (offset) { + struct net_buf_simple *pdu = bt_mesh_alloc_buf(size); + if (pdu == NULL) { + BT_ERR("%s, Out of memory", __func__); + return -ENOMEM; + } + + get_comp_data(pdu, comp, false); + + /* Get part of Composition Data Page 0/128 */ + net_buf_simple_add_mem(buf, pdu->data + offset, pdu->len - offset); + + bt_mesh_free_buf(pdu); + } else { + get_comp_data(buf, comp, full_element); + } + + return 0; +} + +static int bt_mesh_get_comp_data(struct net_buf_simple *buf, + uint8_t page, uint16_t offset, + bool full_element) +{ + if (page == 0) { + return fetch_comp_data(buf, comp_0, page, offset, full_element); + } + + BT_ERR("Invalid Composition Data Page %d", page); + return -EINVAL; +} +#endif /* !CONFIG_BLE_MESH_V11_SUPPORT */ + static void comp_data_get(struct bt_mesh_model *model, struct bt_mesh_msg_ctx *ctx, struct net_buf_simple *buf) @@ -2758,7 +2912,7 @@ static void node_reset(struct bt_mesh_model *model, bt_mesh_model_msg_init(&msg, OP_NODE_RESET_STATUS); - /* Send the response first since we wont have any keys left to + /* Send the response first since we won't have any keys left to * send it later. */ if (bt_mesh_model_send(model, ctx, &msg, NULL, NULL)) { diff --git a/components/bt/esp_ble_mesh/core/crypto.c b/components/bt/esp_ble_mesh/core/crypto.c index 9b762fb5ed3..2577c65efba 100644 --- a/components/bt/esp_ble_mesh/core/crypto.c +++ b/components/bt/esp_ble_mesh/core/crypto.c @@ -22,7 +22,9 @@ #include "mesh/common.h" #include "mesh/adapter.h" +#if CONFIG_BLE_MESH_V11_SUPPORT #include "mesh_v1.1/utils.h" +#endif #define NET_MIC_LEN(pdu) (((pdu)[1] & 0x80) ? 8 : 4) #define APP_MIC_LEN(aszmic) ((aszmic) ? 8 : 4) diff --git a/components/bt/esp_ble_mesh/core/friend.c b/components/bt/esp_ble_mesh/core/friend.c index b1a298d5a97..aa9607492b2 100644 --- a/components/bt/esp_ble_mesh/core/friend.c +++ b/components/bt/esp_ble_mesh/core/friend.c @@ -21,7 +21,9 @@ #include "mesh/common.h" #include "pvnr_mgmt.h" +#if CONFIG_BLE_MESH_V11_SUPPORT #include "mesh_v1.1/utils.h" +#endif #ifdef CONFIG_BLE_MESH_FRIEND diff --git a/components/bt/esp_ble_mesh/core/lpn.c b/components/bt/esp_ble_mesh/core/lpn.c index f445be5632c..80f5b4321af 100644 --- a/components/bt/esp_ble_mesh/core/lpn.c +++ b/components/bt/esp_ble_mesh/core/lpn.c @@ -10,6 +10,7 @@ #include #include "crypto.h" +#include "tag.h" #include "adv.h" #include "scan.h" #include "mesh.h" @@ -23,7 +24,9 @@ #include "mesh/cfg_srv.h" #include "heartbeat.h" +#if CONFIG_BLE_MESH_V11_SUPPORT #include "mesh_v1.1/utils.h" +#endif #ifdef CONFIG_BLE_MESH_LOW_POWER diff --git a/components/bt/esp_ble_mesh/core/main.c b/components/bt/esp_ble_mesh/core/main.c index ad94e2c88b2..94a43c19b14 100644 --- a/components/bt/esp_ble_mesh/core/main.c +++ b/components/bt/esp_ble_mesh/core/main.c @@ -2,7 +2,7 @@ /* * SPDX-FileCopyrightText: 2017 Intel Corporation - * SPDX-FileContributor: 2018-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileContributor: 2018-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -30,7 +30,9 @@ #include "prov_pvnr.h" #include "pvnr_mgmt.h" +#if CONFIG_BLE_MESH_V11_SUPPORT #include "mesh_v1.1/utils.h" +#endif static bool mesh_init = false; @@ -161,9 +163,9 @@ void bt_mesh_node_reset(void) bt_mesh_clear_seq(); bt_mesh_clear_dkca(); bt_mesh_clear_role(); - if (IS_ENABLED(CONFIG_BLE_MESH_DF_SRV)) { - bt_mesh_clear_all_directed_forwarding_table_data(); - } +#if CONFIG_BLE_MESH_DF_SRV + bt_mesh_clear_all_directed_forwarding_table_data(); +#endif } memset(bt_mesh.flags, 0, sizeof(bt_mesh.flags)); @@ -405,12 +407,14 @@ int bt_mesh_init(const struct bt_mesh_prov *prov, return -EALREADY; } +#if CONFIG_BLE_MESH_V11_SUPPORT extern int bt_mesh_v11_ext_init(void); err = bt_mesh_v11_ext_init(); if (err) { BT_ERR("Bluetooth Mesh v1.1 init failed"); return err; } +#endif bt_mesh_mutex_init(); diff --git a/components/bt/esp_ble_mesh/core/mesh.h b/components/bt/esp_ble_mesh/core/mesh.h index c9392240696..127844790fb 100644 --- a/components/bt/esp_ble_mesh/core/mesh.h +++ b/components/bt/esp_ble_mesh/core/mesh.h @@ -11,6 +11,7 @@ #define _MESH_H_ #include "net.h" +#include "tag.h" #ifdef __cplusplus extern "C" { diff --git a/components/bt/esp_ble_mesh/core/net.c b/components/bt/esp_ble_mesh/core/net.c index d5b768c7d22..15d099cc5cd 100644 --- a/components/bt/esp_ble_mesh/core/net.c +++ b/components/bt/esp_ble_mesh/core/net.c @@ -31,7 +31,9 @@ #include "proxy_server.h" #include "pvnr_mgmt.h" +#if CONFIG_BLE_MESH_V11_SUPPORT #include "mesh_v1.1/utils.h" +#endif /* Minimum valid Mesh Network PDU length. The Network headers * themselves take up 9 bytes. After that there is a minimum of 1 byte @@ -1019,6 +1021,33 @@ int bt_mesh_net_encode(struct bt_mesh_net_tx *tx, struct net_buf_simple *buf, return bt_mesh_net_obfuscate(buf->data, BLE_MESH_NET_IVI_TX, priv); } +#if !CONFIG_BLE_MESH_V11_SUPPORT +static void bt_mesh_net_adv_xmit_update(struct bt_mesh_net_tx *tx) +{ + /* When transmitting a Network PDU that is tagged as friendship, + * the Advertising Bearer Network Interface shall transmit the + * Network PDU over the advertising bearer only once. + * + * Note: Currently when transmitting a packet with the friendship + * credentials used, the message flow will not reach here. It + * will be enqueued into the friend queue in transport.c, and + * waited to be sent. + */ + if (bt_mesh_tag_friendship(tx->ctx->send_tag)) { + tx->xmit = BLE_MESH_TRANSMIT(0, BLE_MESH_TRANSMIT_INT(bt_mesh_net_transmit_get())); + return; + } + + if (bt_mesh_tag_relay(tx->ctx->send_tag)) { + tx->xmit = bt_mesh_relay_retransmit_get(); + } else { + tx->xmit = bt_mesh_net_transmit_get(); + } + + return; +} +#endif /* !CONFIG_BLE_MESH_V11_SUPPORT */ + int bt_mesh_net_send(struct bt_mesh_net_tx *tx, struct net_buf *buf, const struct bt_mesh_send_cb *cb, void *cb_data) { @@ -1418,13 +1447,94 @@ static bool relay_to_adv(enum bt_mesh_net_if net_if) case BLE_MESH_NET_IF_ADV: return (bt_mesh_relay_get() == BLE_MESH_RELAY_ENABLED); case BLE_MESH_NET_IF_PROXY: - return (bt_mesh_gatt_proxy_get() == BLE_MESH_GATT_PROXY_ENABLED || - bt_mesh_private_gatt_proxy_state_get() == BLE_MESH_PRIVATE_GATT_PROXY_ENABLED); + return (bt_mesh_gatt_proxy_get() == BLE_MESH_GATT_PROXY_ENABLED +#if CONFIG_BLE_MESH_PRB_SRV + || bt_mesh_private_gatt_proxy_state_get() == BLE_MESH_PRIVATE_GATT_PROXY_ENABLED +#endif + ); default: return false; } } +#if !CONFIG_BLE_MESH_V11_SUPPORT +static uint8_t net_retransmission_adv(struct bt_mesh_net_rx *rx, + uint8_t *cred, uint8_t *tag) +{ + if (rx->ctx.recv_cred == BLE_MESH_FLOODING_CRED) { + uint8_t bearer = BLE_MESH_NONE_BEARER; + + /* Inbound bearer: ADV; + * Inbound Security Material: managed flooding; + */ + + /* Condition: Relay is enabled. */ + if (IS_ENABLED(CONFIG_BLE_MESH_RELAY) && + bt_mesh_relay_get() == BLE_MESH_RELAY_ENABLED) { + bearer |= BLE_MESH_ADV_BEARER; + *cred = BLE_MESH_FLOODING_CRED; + /* Additional action: Tag as relay */ + *tag |= BLE_MESH_TAG_RELAY; + } + + /* Condition: Proxy is enabled. */ + if (IS_ENABLED(CONFIG_BLE_MESH_GATT_PROXY_SERVER) && + bt_mesh_gatt_proxy_get() == BLE_MESH_GATT_PROXY_ENABLED) { + bearer |= BLE_MESH_GATT_BEARER; + *cred = BLE_MESH_FLOODING_CRED; + } + + return bearer; + } + + if (rx->ctx.recv_cred == BLE_MESH_FRIENDSHIP_CRED && + IS_ENABLED(CONFIG_BLE_MESH_FRIEND) && + bt_mesh_friend_get() == BLE_MESH_FRIEND_ENABLED) { + + /* Condition: Directed friend is disabled. */ + *cred = BLE_MESH_FLOODING_CRED; + return BLE_MESH_ALL_BEARERS; + } + + return BLE_MESH_NONE_BEARER; +} + +static uint8_t net_retransmission_gatt(struct bt_mesh_net_rx *rx, + uint8_t *cred, uint8_t *tag) +{ + if (rx->ctx.recv_cred == BLE_MESH_FLOODING_CRED) { + /* Inbound bearer: GATT; + * Inbound Security Material: managed flooding; + * Condition: Proxy is enabled; + */ + if (IS_ENABLED(CONFIG_BLE_MESH_GATT_PROXY_SERVER) && + bt_mesh_gatt_proxy_get() == BLE_MESH_GATT_PROXY_ENABLED) { + /* Condition: Directed proxy is disabled. */ + *cred = BLE_MESH_FLOODING_CRED; + return BLE_MESH_ALL_BEARERS; + } + + return BLE_MESH_NONE_BEARER; + } + + return BLE_MESH_NONE_BEARER; +} + +static uint8_t bt_mesh_net_retrans_match(struct bt_mesh_net_rx *rx, + uint8_t *cred, uint8_t *tag) +{ + if (rx->net_if == BLE_MESH_NET_IF_ADV) { + return net_retransmission_adv(rx, cred, tag); + } + + if (rx->net_if == BLE_MESH_NET_IF_PROXY) { + return net_retransmission_gatt(rx, cred, tag); + } + + return BLE_MESH_NONE_BEARER; +} +#endif /* !CONFIG_BLE_MESH_V11_SUPPORT */ + static void bt_mesh_net_relay(struct net_buf_simple *sbuf, struct bt_mesh_net_rx *rx) { @@ -1621,7 +1731,9 @@ static void bt_mesh_net_relay(struct net_buf_simple *sbuf, (bearer & BLE_MESH_GATT_BEARER) && ((bt_mesh_gatt_proxy_get() == BLE_MESH_GATT_PROXY_ENABLED && cred != BLE_MESH_FRIENDSHIP_CRED) || +#if CONFIG_BLE_MESH_PRB_SRV bt_mesh_private_gatt_proxy_state_get() == BLE_MESH_PRIVATE_GATT_PROXY_ENABLED || +#endif rx->net_if == BLE_MESH_NET_IF_LOCAL || rx->ctx.recv_cred == BLE_MESH_FRIENDSHIP_CRED)) { if (bt_mesh_proxy_server_relay(&buf->b, rx->ctx.recv_dst) && @@ -1819,7 +1931,9 @@ void bt_mesh_net_recv(struct net_buf_simple *data, int8_t rssi, bt_mesh_elem_find(rx.ctx.recv_dst)); if (IS_ENABLED(CONFIG_BLE_MESH_GATT_PROXY_SERVER) && +#if CONFIG_BLE_MESH_PRB_SRV bt_mesh_private_gatt_proxy_state_get() != BLE_MESH_PRIVATE_GATT_PROXY_ENABLED && +#endif net_if == BLE_MESH_NET_IF_PROXY) { bt_mesh_proxy_server_addr_add(data, rx.ctx.addr); diff --git a/components/bt/esp_ble_mesh/core/prov_common.h b/components/bt/esp_ble_mesh/core/prov_common.h index 561712ef146..d2a8771bec8 100644 --- a/components/bt/esp_ble_mesh/core/prov_common.h +++ b/components/bt/esp_ble_mesh/core/prov_common.h @@ -17,7 +17,9 @@ #include "mesh/timer.h" #include "mesh/adapter.h" +#if CONFIG_BLE_MESH_V11_SUPPORT #include "mesh_v1.1/utils.h" +#endif #ifdef __cplusplus extern "C" { diff --git a/components/bt/esp_ble_mesh/core/prov_node.c b/components/bt/esp_ble_mesh/core/prov_node.c index 4871a1cb1eb..8053ac82018 100644 --- a/components/bt/esp_ble_mesh/core/prov_node.c +++ b/components/bt/esp_ble_mesh/core/prov_node.c @@ -22,7 +22,9 @@ #include "prov_common.h" #include "prov_node.h" +#if CONFIG_BLE_MESH_V11_SUPPORT #include "mesh_v1.1/utils.h" +#endif #if CONFIG_BLE_MESH_NODE diff --git a/components/bt/esp_ble_mesh/core/prov_pvnr.c b/components/bt/esp_ble_mesh/core/prov_pvnr.c index e2e0fe5850d..9066597e876 100644 --- a/components/bt/esp_ble_mesh/core/prov_pvnr.c +++ b/components/bt/esp_ble_mesh/core/prov_pvnr.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -22,7 +22,9 @@ #include "prov_pvnr.h" #include "pvnr_mgmt.h" +#if CONFIG_BLE_MESH_V11_SUPPORT #include "mesh_v1.1/utils.h" +#endif #if CONFIG_BLE_MESH_PROVISIONER @@ -1413,7 +1415,7 @@ static int prov_auth(struct bt_mesh_prov_link *link, return -EINVAL; } - /* Provisioner ouput number/string and wait for device's Provisioning Input Complete PDU */ + /* Provisioner output number/string and wait for device's Provisioning Input Complete PDU */ link->expect = PROV_INPUT_COMPLETE; /* NOTE: The Bluetooth SIG recommends that mesh implementations enforce a randomly diff --git a/components/bt/esp_ble_mesh/core/proxy_client.c b/components/bt/esp_ble_mesh/core/proxy_client.c index 9382cf61478..1719e4737df 100644 --- a/components/bt/esp_ble_mesh/core/proxy_client.c +++ b/components/bt/esp_ble_mesh/core/proxy_client.c @@ -21,7 +21,9 @@ #include "pvnr_mgmt.h" #include "mesh/adapter.h" +#if CONFIG_BLE_MESH_V11_SUPPORT #include "mesh_v1.1/utils.h" +#endif #if (CONFIG_BLE_MESH_PROVISIONER && CONFIG_BLE_MESH_PB_GATT) || \ CONFIG_BLE_MESH_GATT_PROXY_CLIENT diff --git a/components/bt/esp_ble_mesh/core/proxy_client.h b/components/bt/esp_ble_mesh/core/proxy_client.h index d2d85017019..ef8db32f6d2 100644 --- a/components/bt/esp_ble_mesh/core/proxy_client.h +++ b/components/bt/esp_ble_mesh/core/proxy_client.h @@ -11,7 +11,9 @@ #include "mesh/adapter.h" #include "prov_common.h" +#if CONFIG_BLE_MESH_V11_SUPPORT #include "mesh_v1.1/utils.h" +#endif #ifdef __cplusplus extern "C" { diff --git a/components/bt/esp_ble_mesh/core/proxy_server.c b/components/bt/esp_ble_mesh/core/proxy_server.c index 020793dc6e8..532b23d823c 100644 --- a/components/bt/esp_ble_mesh/core/proxy_server.c +++ b/components/bt/esp_ble_mesh/core/proxy_server.c @@ -22,7 +22,9 @@ #include "prov_common.h" #include "prov_node.h" +#if CONFIG_BLE_MESH_V11_SUPPORT #include "mesh_v1.1/utils.h" +#endif #if (CONFIG_BLE_MESH_NODE && CONFIG_BLE_MESH_PB_GATT) || \ CONFIG_BLE_MESH_GATT_PROXY_SERVER diff --git a/components/bt/esp_ble_mesh/core/pvnr_mgmt.c b/components/bt/esp_ble_mesh/core/pvnr_mgmt.c index 2531a2d2fdb..96ad2feb324 100644 --- a/components/bt/esp_ble_mesh/core/pvnr_mgmt.c +++ b/components/bt/esp_ble_mesh/core/pvnr_mgmt.c @@ -22,7 +22,9 @@ #include "prov_pvnr.h" #include "pvnr_mgmt.h" +#if CONFIG_BLE_MESH_V11_SUPPORT #include "mesh_v1.1/utils.h" +#endif #if CONFIG_BLE_MESH_PROVISIONER diff --git a/components/bt/esp_ble_mesh/core/scan.c b/components/bt/esp_ble_mesh/core/scan.c index e1b43dd2f63..72b1ccb3000 100644 --- a/components/bt/esp_ble_mesh/core/scan.c +++ b/components/bt/esp_ble_mesh/core/scan.c @@ -2,7 +2,7 @@ /* * SPDX-FileCopyrightText: 2017 Intel Corporation - * SPDX-FileContributor: 2020-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileContributor: 2020-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -27,7 +27,9 @@ #include "prov_pvnr.h" #include "mesh/adapter.h" +#if CONFIG_BLE_MESH_V11_SUPPORT #include "mesh_v1.1/utils.h" +#endif /* Scan Window and Interval are equal for continuous scanning */ #define SCAN_INTERVAL 0x20 @@ -263,12 +265,13 @@ static void handle_adv_service_data(struct net_buf_simple *buf, bt_mesh_provisioner_prov_adv_recv(buf, addr, rssi); } - if (IS_ENABLED(CONFIG_BLE_MESH_RPR_SRV) && - bt_mesh_is_provisioned()) { +#if CONFIG_BLE_MESH_RPR_SRV + if (bt_mesh_is_provisioned()) { const bt_mesh_addr_t *addr = bt_mesh_get_unprov_dev_addr(); bt_mesh_unprov_dev_fifo_enqueue(buf->data, addr->val, bt_mesh_get_adv_type()); bt_mesh_rpr_srv_unprov_beacon_recv(buf, bt_mesh_get_adv_type(), addr, rssi); } +#endif break; #endif #if CONFIG_BLE_MESH_GATT_PROXY_CLIENT diff --git a/components/bt/esp_ble_mesh/core/storage/settings.c b/components/bt/esp_ble_mesh/core/storage/settings.c index 34a40d2d303..ad223201769 100644 --- a/components/bt/esp_ble_mesh/core/storage/settings.c +++ b/components/bt/esp_ble_mesh/core/storage/settings.c @@ -22,7 +22,9 @@ #include "pvnr_mgmt.h" #include "prov_pvnr.h" +#if CONFIG_BLE_MESH_V11_SUPPORT #include "mesh_v1.1/utils.h" +#endif /* BLE Mesh NVS Key and corresponding data struct. * Note: The length of nvs key must be <= 15. diff --git a/components/bt/esp_ble_mesh/core/tag.h b/components/bt/esp_ble_mesh/core/tag.h new file mode 100644 index 00000000000..d1b9831094a --- /dev/null +++ b/components/bt/esp_ble_mesh/core/tag.h @@ -0,0 +1,53 @@ +/* + * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _BLE_MESH_v11_TAG_H_ +#define _BLE_MESH_v11_TAG_H_ + +#include +#include + +#include "mesh.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#if !CONFIG_BLE_MESH_V11_SUPPORT + +/* TAG - additional metadata */ +#define BLE_MESH_TAG_SEND_SEGMENTED BIT(0) +#define BLE_MESH_TAG_IMMUTABLE_CRED BIT(1) +#define BLE_MESH_TAG_RELAY BIT(3) +#define BLE_MESH_TAG_FRIENDSHIP BIT(4) + +static inline bool bt_mesh_tag_send_segmented(uint8_t tag) +{ + return (tag & BLE_MESH_TAG_SEND_SEGMENTED); +} + +static inline bool bt_mesh_tag_immutable_cred(uint8_t tag) +{ + return (tag & BLE_MESH_TAG_IMMUTABLE_CRED); +} + +static inline bool bt_mesh_tag_relay(uint8_t tag) +{ + return (tag & BLE_MESH_TAG_RELAY); +} + +static inline bool bt_mesh_tag_friendship(uint8_t tag) +{ + return (tag & BLE_MESH_TAG_FRIENDSHIP); +} + +#endif /* !CONFIG_BLE_MESH_V11_SUPPORT */ + +#ifdef __cplusplus +} +#endif + +#endif /* _BLE_MESH_v11_TAG_H_ */ diff --git a/components/bt/esp_ble_mesh/core/transport.c b/components/bt/esp_ble_mesh/core/transport.c index 70589706dae..4f125b99df7 100644 --- a/components/bt/esp_ble_mesh/core/transport.c +++ b/components/bt/esp_ble_mesh/core/transport.c @@ -11,6 +11,7 @@ #include #include "crypto.h" +#include "tag.h" #include "adv.h" #include "mesh.h" #include "lpn.h" @@ -26,7 +27,9 @@ #include "mesh/cfg_srv.h" #include "heartbeat.h" +#if CONFIG_BLE_MESH_V11_SUPPORT #include "mesh_v1.1/utils.h" +#endif /* The transport layer needs at least three buffers for itself to avoid * deadlocks. Ensure that there are a sufficient number of advertising @@ -1039,18 +1042,18 @@ static int ctl_recv(struct bt_mesh_net_rx *rx, uint8_t hdr, return 0; } - if (IS_ENABLED(CONFIG_BLE_MESH_DF_SRV)) { - switch (ctl_op) { - case TRANS_CTL_OP_PATH_REQ: - case TRANS_CTL_OP_PATH_REPLY: - case TRANS_CTL_OP_PATH_CFM: - case TRANS_CTL_OP_PATH_ECHO_REQ: - case TRANS_CTL_OP_PATH_ECHO_REPLY: - case TRANS_CTL_OP_DEP_NODE_UPDATE: - case TRANS_CTL_OP_PATH_REQ_SOLIC: - return bt_mesh_directed_forwarding_ctl_recv(ctl_op, rx, buf); - } +#if CONFIG_BLE_MESH_DF_SRV + switch (ctl_op) { + case TRANS_CTL_OP_PATH_REQ: + case TRANS_CTL_OP_PATH_REPLY: + case TRANS_CTL_OP_PATH_CFM: + case TRANS_CTL_OP_PATH_ECHO_REQ: + case TRANS_CTL_OP_PATH_ECHO_REPLY: + case TRANS_CTL_OP_DEP_NODE_UPDATE: + case TRANS_CTL_OP_PATH_REQ_SOLIC: + return bt_mesh_directed_forwarding_ctl_recv(ctl_op, rx, buf); } +#endif if (IS_ENABLED(CONFIG_BLE_MESH_FRIEND) && !bt_mesh_lpn_established()) { switch (ctl_op) { @@ -1759,8 +1762,6 @@ void bt_mesh_trans_init(void) { int i; - bt_mesh_sar_init(); - for (i = 0; i < ARRAY_SIZE(seg_tx); i++) { k_delayed_work_init(&seg_tx[i].rtx_timer, seg_retransmit); } diff --git a/components/bt/esp_ble_mesh/lib/include/mesh_v1.1/utils.h b/components/bt/esp_ble_mesh/lib/include/mesh_v1.1/utils.h index 71a02314c81..d8e80b196ff 100644 --- a/components/bt/esp_ble_mesh/lib/include/mesh_v1.1/utils.h +++ b/components/bt/esp_ble_mesh/lib/include/mesh_v1.1/utils.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ diff --git a/components/bt/esp_ble_mesh/models/client/client_common.c b/components/bt/esp_ble_mesh/models/client/client_common.c index db87851613d..7e5448707d9 100644 --- a/components/bt/esp_ble_mesh/models/client/client_common.c +++ b/components/bt/esp_ble_mesh/models/client/client_common.c @@ -14,7 +14,9 @@ #include "mesh/client_common.h" #include "mesh/common.h" +#if CONFIG_BLE_MESH_V11_SUPPORT #include "mesh_v1.1/utils.h" +#endif #define HCI_TIME_FOR_START_ADV K_MSEC(5) /* Three adv related hci commands may take 4 ~ 5ms */ From bd4de3c8a376995fffd3b89cea3a4c30152b1c01 Mon Sep 17 00:00:00 2001 From: Sudeep Mohanty Date: Tue, 1 Oct 2024 15:35:37 +0200 Subject: [PATCH 043/472] fix(freertos): Fixed priority inversion when setting event group bits This commit fixes a priority inversion when a lower priority task set event group bits to unblock a higher priority task but the lower priority task continued to run. --- components/freertos/FreeRTOS-Kernel/tasks.c | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/components/freertos/FreeRTOS-Kernel/tasks.c b/components/freertos/FreeRTOS-Kernel/tasks.c index 8d06ea30b0d..368a20599fd 100644 --- a/components/freertos/FreeRTOS-Kernel/tasks.c +++ b/components/freertos/FreeRTOS-Kernel/tasks.c @@ -4123,10 +4123,19 @@ void vTaskRemoveFromUnorderedEventList( ListItem_t * pxEventListItem, if( taskIS_YIELD_REQUIRED( pxUnblockedTCB, pdFALSE ) == pdTRUE ) { /* The unblocked task has a priority above that of the calling task, so - * a context switch is required. This function is called with the - * scheduler suspended so xYieldPending is set so the context switch - * occurs immediately that the scheduler is resumed (unsuspended). */ - xYieldPending[ xCurCoreID ] = pdTRUE; + * a context switch is required. */ + #if ( configNUM_CORES > 1 ) + + /* In SMP mode, this function is called from a critical section, so we + * yield the current core to schedule the unblocked task. */ + portYIELD_WITHIN_API(); + #else /* configNUM_CORES > 1 */ + + /* In single-core mode, this function is called with the scheduler suspended + * so xYieldPending is set so the context switch occurs immediately once the + * scheduler is resumed (unsuspended). */ + xYieldPending[ xCurCoreID ] = pdTRUE; + #endif /* configNUM_CORES > 1 */ } } } From fc84220d90ad2f96d3d7a0365384121e7627d579 Mon Sep 17 00:00:00 2001 From: Sudeep Mohanty Date: Wed, 2 Oct 2024 10:43:15 +0200 Subject: [PATCH 044/472] test(freertos): Added unit test for event groups to test priority inversion This commit adds a FreeRTOS unit test to verify that event groups do not cause priority inversion when unblocking a higher priority task. --- .../event_groups/test_freertos_eventgroups.c | 51 +++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/components/freertos/test_apps/freertos/kernel/event_groups/test_freertos_eventgroups.c b/components/freertos/test_apps/freertos/kernel/event_groups/test_freertos_eventgroups.c index b14f1ea1ca2..00ff6980c9e 100644 --- a/components/freertos/test_apps/freertos/kernel/event_groups/test_freertos_eventgroups.c +++ b/components/freertos/test_apps/freertos/kernel/event_groups/test_freertos_eventgroups.c @@ -132,6 +132,57 @@ TEST_CASE("FreeRTOS Event Group Sync", "[freertos]") vEventGroupDelete(eg); } +static TaskHandle_t run_order[2]; +static uint32_t run_order_index = 0; + +void task_test_eg_prio(void *arg) +{ + TaskHandle_t main_task_hdl = (TaskHandle_t)arg; + + /* Notify the main task that this task has been created */ + xTaskNotifyGive(main_task_hdl); + + /* Wait for the event group bits to be set */ + TEST_ASSERT_EQUAL(1, xEventGroupWaitBits(eg, 1, pdTRUE, pdTRUE, portMAX_DELAY)); + + /* Record the task handle in the run order array */ + run_order[run_order_index++] = xTaskGetCurrentTaskHandle(); + + /* Suspend the task */ + vTaskSuspend(NULL); +} + +TEST_CASE("FreeRTOS Event Groups do not cause priority inversion when higher priority task is unblocked", "[freertos]") +{ + run_order[0] = NULL; + run_order[1] = NULL; + run_order_index = 0; + + /* Initialize the event group */ + eg = xEventGroupCreate(); + + /* Create a task with higher priority than the task that will set the event group bits */ + TaskHandle_t higher_prio_hdl; + TEST_ASSERT_EQUAL(pdTRUE, xTaskCreatePinnedToCore(task_test_eg_prio, "task_test_eg_prio", 2048, (void *)xTaskGetCurrentTaskHandle(), CONFIG_UNITY_FREERTOS_PRIORITY + 1, &higher_prio_hdl, CONFIG_UNITY_FREERTOS_CPU)); + + /* Wait for the task to be created */ + ulTaskNotifyTake(pdTRUE, portMAX_DELAY); + + /* Set the event group bits */ + xEventGroupSetBits(eg, 1); + + /* Record the task handle in the run order array */ + run_order[run_order_index++] = xTaskGetCurrentTaskHandle(); + + /* Verify that the higher priority task was unblocked and immediately scheduled and the lower priority task was preempted */ + TEST_ASSERT_EQUAL(higher_prio_hdl, run_order[0]); + TEST_ASSERT_EQUAL(xTaskGetCurrentTaskHandle(), run_order[1]); + + /* Clean up */ + vEventGroupDelete(eg); + vTaskDelete(higher_prio_hdl); +} + /*-----------------Test case for event group trace facilities-----------------*/ #ifdef CONFIG_FREERTOS_USE_TRACE_FACILITY /* From 02e9c850d8be6be04d0e34dbfe979708c947b395 Mon Sep 17 00:00:00 2001 From: sibeibei Date: Tue, 8 Oct 2024 15:36:40 +0800 Subject: [PATCH 045/472] fix(wifi): fix wifi bugs 240919 --- components/esp_coex/Kconfig | 4 ++-- components/esp_coex/src/coexist_debug.c | 2 ++ components/esp_wifi/lib | 2 +- 3 files changed, 5 insertions(+), 3 deletions(-) diff --git a/components/esp_coex/Kconfig b/components/esp_coex/Kconfig index 5fb0eac973a..bc37b3820b2 100644 --- a/components/esp_coex/Kconfig +++ b/components/esp_coex/Kconfig @@ -217,7 +217,7 @@ menu "Wireless Coexistence" default 12 if IDF_TARGET_ESP32S3 default 3 if IDF_TARGET_ESP32C2 default 22 if IDF_TARGET_ESP32C6 - default 16 if IDF_TARGET_ESP32C5 + default 10 if IDF_TARGET_ESP32C5 default 13 if IDF_TARGET_ESP32C61 default 11 @@ -231,7 +231,7 @@ menu "Wireless Coexistence" default 13 if IDF_TARGET_ESP32S3 default 2 if IDF_TARGET_ESP32C2 default 21 if IDF_TARGET_ESP32C6 - default 0 if IDF_TARGET_ESP32C5 + default 9 if IDF_TARGET_ESP32C5 default 12 if IDF_TARGET_ESP32C61 default 12 diff --git a/components/esp_coex/src/coexist_debug.c b/components/esp_coex/src/coexist_debug.c index 7c38eea8e51..317f7c4547e 100644 --- a/components/esp_coex/src/coexist_debug.c +++ b/components/esp_coex/src/coexist_debug.c @@ -89,6 +89,7 @@ static const void* rom_funcs[] = { pm_tx_null_data_done_process, pm_start, pm_stop, + pm_disconnected_wake, #endif }; static const char* rom_funcs_name[] = { @@ -109,6 +110,7 @@ static const char* rom_funcs_name[] = { "pm_tx_null_data_done_process", "pm_start", "pm_stop", + "pm_disconnected_wake", #endif }; diff --git a/components/esp_wifi/lib b/components/esp_wifi/lib index e5111a1452e..6c96f870aee 160000 --- a/components/esp_wifi/lib +++ b/components/esp_wifi/lib @@ -1 +1 @@ -Subproject commit e5111a1452e6d5ae3474a7cbe1c151998537e10b +Subproject commit 6c96f870aeec6bf57b321d0fd52f95086e9e7e80 From 3f061bd557b3b4c77fe30e2823388f7c292a33a8 Mon Sep 17 00:00:00 2001 From: "C.S.M" Date: Mon, 23 Sep 2024 17:50:12 +0800 Subject: [PATCH 046/472] feat(i2c_master): Support i2c sleep retention on esp32c5/p4/c61 --- components/driver/i2c/i2c.c | 10 ++-- components/esp_driver_i2c/i2c_common.c | 38 ++++++++++----- components/esp_driver_i2c/i2c_master.c | 10 ++++ components/esp_driver_i2c/i2c_private.h | 13 ++++++ components/esp_driver_i2c/i2c_slave.c | 6 +++ .../include/driver/i2c_master.h | 3 ++ .../esp_driver_i2c/include/driver/i2c_slave.h | 3 ++ .../test_apps/.build-test-rules.yml | 5 -- .../i2c_test_apps/main/CMakeLists.txt | 7 +-- .../main/test_i2c_sleep_retention.c | 10 ++++ .../test_apps/i2c_test_apps/pytest_i2c.py | 18 +------- .../i2c_test_apps/sdkconfig.ci.iram_safe | 1 + .../i2c_test_apps/sdkconfig.ci.release | 1 + .../sdkconfig.ci.sleep_retention | 5 -- components/hal/esp32c6/include/hal/i2c_ll.h | 3 -- components/hal/esp32h2/include/hal/i2c_ll.h | 3 -- components/soc/esp32c5/i2c_periph.c | 29 ++++++++++++ .../esp32c5/include/soc/Kconfig.soc_caps.in | 4 ++ components/soc/esp32c5/include/soc/soc_caps.h | 2 +- components/soc/esp32c6/i2c_periph.c | 4 +- components/soc/esp32c61/i2c_periph.c | 29 ++++++++++++ .../esp32c61/include/soc/Kconfig.soc_caps.in | 4 ++ .../soc/esp32c61/include/soc/soc_caps.h | 1 + components/soc/esp32h2/i2c_periph.c | 6 +-- components/soc/esp32p4/i2c_periph.c | 46 +++++++++++++++++++ .../esp32p4/include/soc/Kconfig.soc_caps.in | 4 ++ .../include/soc/retention_periph_defs.h | 2 + components/soc/esp32p4/include/soc/soc_caps.h | 2 +- components/soc/include/soc/i2c_periph.h | 4 ++ docs/en/api-reference/peripherals/i2c.rst | 2 +- docs/zh_CN/api-reference/peripherals/i2c.rst | 1 + .../cxx_build_test/main/test_i2c_lcd.cpp | 1 + 32 files changed, 216 insertions(+), 61 deletions(-) delete mode 100644 components/esp_driver_i2c/test_apps/i2c_test_apps/sdkconfig.ci.sleep_retention diff --git a/components/driver/i2c/i2c.c b/components/driver/i2c/i2c.c index 12f2a25d7b7..1450f9af1e8 100644 --- a/components/driver/i2c/i2c.c +++ b/components/driver/i2c/i2c.c @@ -280,7 +280,7 @@ static void i2c_hw_enable(i2c_port_t i2c_num) static esp_err_t i2c_sleep_retention_init(void *arg) { i2c_port_t i2c_num = *(i2c_port_t *)arg; - esp_err_t ret = sleep_retention_entries_create(i2c_regs_retention[i2c_num].link_list, i2c_regs_retention[i2c_num].link_num, REGDMA_LINK_PRI_I2C, I2C_SLEEP_RETENTION_MODULE(i2c_num)); + esp_err_t ret = sleep_retention_entries_create(i2c_regs_retention[i2c_num].link_list, i2c_regs_retention[i2c_num].link_num, REGDMA_LINK_PRI_I2C, i2c_regs_retention[i2c_num].module_id); ESP_RETURN_ON_ERROR(ret, I2C_TAG, "failed to allocate mem for sleep retention"); return ret; } @@ -428,9 +428,9 @@ esp_err_t i2c_driver_install(i2c_port_t i2c_num, i2c_mode_t mode, size_t slv_rx_ sleep_retention_module_init_param_t init_param = { .cbs = { .create = { .handle = i2c_sleep_retention_init, .arg = &i2c_num } } }; - ret = sleep_retention_module_init(I2C_SLEEP_RETENTION_MODULE(i2c_num), &init_param); + ret = sleep_retention_module_init(i2c_regs_retention[i2c_num].module_id, &init_param); if (ret == ESP_OK) { - sleep_retention_module_allocate(I2C_SLEEP_RETENTION_MODULE(i2c_num)); + sleep_retention_module_allocate(i2c_regs_retention[i2c_num].module_id); } #endif return ESP_OK; @@ -486,9 +486,9 @@ esp_err_t i2c_driver_delete(i2c_port_t i2c_num) p_i2c->intr_handle = NULL; #if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP && SOC_I2C_SUPPORT_SLEEP_RETENTION - esp_err_t err = sleep_retention_module_free(I2C_SLEEP_RETENTION_MODULE(i2c_num)); + esp_err_t err = sleep_retention_module_free(i2c_regs_retention[i2c_num].module_id); if (err == ESP_OK) { - err = sleep_retention_module_deinit(I2C_SLEEP_RETENTION_MODULE(i2c_num)); + err = sleep_retention_module_deinit(i2c_regs_retention[i2c_num].module_id); } #endif diff --git a/components/esp_driver_i2c/i2c_common.c b/components/esp_driver_i2c/i2c_common.c index 87bad063b03..b2590a7bae8 100644 --- a/components/esp_driver_i2c/i2c_common.c +++ b/components/esp_driver_i2c/i2c_common.c @@ -33,7 +33,7 @@ #include "soc/rtc_io_channel.h" #include "driver/lp_io.h" #endif -#if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP +#if I2C_USE_RETENTION_LINK #include "esp_private/sleep_retention.h" #endif @@ -47,15 +47,31 @@ typedef struct i2c_platform_t { static i2c_platform_t s_i2c_platform = {}; // singleton platform -#if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP && SOC_I2C_SUPPORT_SLEEP_RETENTION +#if I2C_USE_RETENTION_LINK static esp_err_t s_i2c_sleep_retention_init(void *arg) { i2c_bus_t *bus = (i2c_bus_t *)arg; i2c_port_num_t port_num = bus->port_num; - esp_err_t ret = sleep_retention_entries_create(i2c_regs_retention[port_num].link_list, i2c_regs_retention[port_num].link_num, REGDMA_LINK_PRI_I2C, I2C_SLEEP_RETENTION_MODULE(port_num)); + esp_err_t ret = sleep_retention_entries_create(i2c_regs_retention[port_num].link_list, i2c_regs_retention[port_num].link_num, REGDMA_LINK_PRI_I2C, i2c_regs_retention[port_num].module_id); ESP_RETURN_ON_ERROR(ret, TAG, "failed to allocate mem for sleep retention"); return ret; } + +void i2c_create_retention_module(i2c_bus_handle_t handle) +{ + i2c_port_num_t port_num = handle->port_num; + _lock_acquire(&s_i2c_platform.mutex); + if (handle->retention_link_created == false) { + if (sleep_retention_module_allocate(i2c_regs_retention[port_num].module_id) != ESP_OK) { + // even though the sleep retention module create failed, I2C driver should still work, so just warning here + ESP_LOGW(TAG, "create retention module failed, power domain can't turn off"); + } else { + handle->retention_link_created = true; + } + } + _lock_release(&s_i2c_platform.mutex); + +} #endif static esp_err_t s_i2c_bus_handle_acquire(i2c_port_num_t port_num, i2c_bus_handle_t *i2c_new_bus, i2c_bus_mode_t mode) @@ -77,14 +93,14 @@ static esp_err_t s_i2c_bus_handle_acquire(i2c_port_num_t port_num, i2c_bus_handl bus->bus_mode = mode; bus->is_lp_i2c = (bus->port_num < SOC_HP_I2C_NUM) ? false : true; -#if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP && SOC_I2C_SUPPORT_SLEEP_RETENTION +#if I2C_USE_RETENTION_LINK if (bus->is_lp_i2c == false) { sleep_retention_module_init_param_t init_param = { .cbs = { .create = { .handle = s_i2c_sleep_retention_init, .arg = (void *)bus } } }; - ret = sleep_retention_module_init(I2C_SLEEP_RETENTION_MODULE(port_num), &init_param); - if (ret == ESP_OK) { - sleep_retention_module_allocate(I2C_SLEEP_RETENTION_MODULE(port_num)); + esp_err_t err = sleep_retention_module_init(i2c_regs_retention[port_num].module_id, &init_param); + if (err != ESP_OK) { + ESP_LOGW(TAG, "init sleep retention failed on bus %d, power domain may be turned off during sleep", port_num); } } else { ESP_LOGW(TAG, "Detected PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP is enabled while LP_I2C is used. Sleep retention is not supported on LP I2C. Please use it properly"); @@ -175,12 +191,12 @@ esp_err_t i2c_release_bus_handle(i2c_bus_handle_t i2c_bus) if (s_i2c_platform.count[port_num] == 0) { do_deinitialize = true; s_i2c_platform.buses[port_num] = NULL; -#if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP && SOC_I2C_SUPPORT_SLEEP_RETENTION +#if I2C_USE_RETENTION_LINK if (i2c_bus->is_lp_i2c == false) { - esp_err_t err = sleep_retention_module_free(I2C_SLEEP_RETENTION_MODULE(port_num)); - if (err == ESP_OK) { - err = sleep_retention_module_deinit(I2C_SLEEP_RETENTION_MODULE(port_num)); + if (i2c_bus->retention_link_created) { + sleep_retention_module_free(i2c_regs_retention[port_num].module_id); } + sleep_retention_module_deinit(i2c_regs_retention[port_num].module_id); } #endif if (i2c_bus->intr_handle) { diff --git a/components/esp_driver_i2c/i2c_master.c b/components/esp_driver_i2c/i2c_master.c index ad18d2806d3..838d0578d73 100644 --- a/components/esp_driver_i2c/i2c_master.c +++ b/components/esp_driver_i2c/i2c_master.c @@ -932,6 +932,10 @@ esp_err_t i2c_new_master_bus(const i2c_master_bus_config_t *bus_config, i2c_mast ESP_RETURN_ON_FALSE((bus_config->i2c_port < SOC_I2C_NUM || bus_config->i2c_port == -1), ESP_ERR_INVALID_ARG, TAG, "invalid i2c port number"); ESP_RETURN_ON_FALSE(GPIO_IS_VALID_GPIO(bus_config->sda_io_num) && GPIO_IS_VALID_GPIO(bus_config->scl_io_num), ESP_ERR_INVALID_ARG, TAG, "invalid SDA/SCL pin number"); +#if !SOC_I2C_SUPPORT_SLEEP_RETENTION + ESP_RETURN_ON_FALSE(bus_config->flags.allow_pd == 0, ESP_ERR_NOT_SUPPORTED, TAG, "not able to power down in light sleep"); +#endif // SOC_I2C_SUPPORT_SLEEP_RETENTION + i2c_master = heap_caps_calloc(1, sizeof(i2c_master_bus_t) + 20 * sizeof(i2c_transaction_t), I2C_MEM_ALLOC_CAPS); ESP_RETURN_ON_FALSE(i2c_master, ESP_ERR_NO_MEM, TAG, "no memory for i2c master bus"); @@ -980,6 +984,12 @@ esp_err_t i2c_new_master_bus(const i2c_master_bus_config_t *bus_config, i2c_mast ESP_RETURN_ON_FALSE(1 << (bus_config->intr_priority) & I2C_ALLOW_INTR_PRIORITY_MASK, ESP_ERR_INVALID_ARG, TAG, "invalid interrupt priority:%d", bus_config->intr_priority); } +#if I2C_USE_RETENTION_LINK + if (bus_config->flags.allow_pd != 0) { + i2c_create_retention_module(i2c_master->base); + } +#endif // I2C_USE_RETENTION_LINK + xSemaphoreTake(i2c_master->bus_lock_mux, portMAX_DELAY); SLIST_INIT(&i2c_master->device_list); xSemaphoreGive(i2c_master->bus_lock_mux); diff --git a/components/esp_driver_i2c/i2c_private.h b/components/esp_driver_i2c/i2c_private.h index a78dfdd0674..97938765519 100644 --- a/components/esp_driver_i2c/i2c_private.h +++ b/components/esp_driver_i2c/i2c_private.h @@ -54,6 +54,9 @@ extern "C" { #define I2C_INTR_ALLOC_FLAG (ESP_INTR_FLAG_SHARED | ESP_INTR_FLAG_LOWMED) #endif +// Use retention link only when the target supports sleep retention and PM is enabled +#define I2C_USE_RETENTION_LINK (SOC_I2C_SUPPORT_SLEEP_RETENTION && CONFIG_PM_ENABLE && CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP) + #define I2C_ALLOW_INTR_PRIORITY_MASK ESP_INTR_FLAG_LOWMED #define I2C_PM_LOCK_NAME_LEN_MAX 16 @@ -119,6 +122,9 @@ struct i2c_bus_t { char pm_lock_name[I2C_PM_LOCK_NAME_LEN_MAX]; // pm lock name #endif i2c_bus_mode_t bus_mode; // I2C bus mode +#if SOC_I2C_SUPPORT_SLEEP_RETENTION + bool retention_link_created; // mark if the retention link is created. +#endif }; typedef struct i2c_master_device_list { @@ -260,6 +266,13 @@ esp_err_t i2c_common_set_pins(i2c_bus_handle_t handle); */ bool i2c_bus_occupied(i2c_port_num_t port_num); +/** + * @brief Create sleep retention link + * + * @param handle I2C bus handle + */ +void i2c_create_retention_module(i2c_bus_handle_t handle); + #ifdef __cplusplus } #endif diff --git a/components/esp_driver_i2c/i2c_slave.c b/components/esp_driver_i2c/i2c_slave.c index 6b000ef66ed..2cb3da25958 100644 --- a/components/esp_driver_i2c/i2c_slave.c +++ b/components/esp_driver_i2c/i2c_slave.c @@ -235,6 +235,12 @@ esp_err_t i2c_new_slave_device(const i2c_slave_config_t *slave_config, i2c_slave ret = esp_intr_alloc_intrstatus(i2c_periph_signal[i2c_port_num].irq, isr_flags, (uint32_t)i2c_ll_get_interrupt_status_reg(hal->dev), I2C_LL_SLAVE_EVENT_INTR, s_slave_isr_handle_default, i2c_slave, &i2c_slave->base->intr_handle); ESP_GOTO_ON_ERROR(ret, err, TAG, "install i2c slave interrupt failed"); +#if I2C_USE_RETENTION_LINK + if (slave_config->flags.allow_pd != 0) { + i2c_create_retention_module(i2c_slave->base); + } +#endif // I2C_USE_RETENTION_LINK + portENTER_CRITICAL(&i2c_slave->base->spinlock); i2c_ll_clear_intr_mask(hal->dev, I2C_LL_SLAVE_EVENT_INTR); i2c_hal_slave_init(hal); diff --git a/components/esp_driver_i2c/include/driver/i2c_master.h b/components/esp_driver_i2c/include/driver/i2c_master.h index a7b1a0d4c72..92928b14417 100644 --- a/components/esp_driver_i2c/include/driver/i2c_master.h +++ b/components/esp_driver_i2c/include/driver/i2c_master.h @@ -33,6 +33,9 @@ typedef struct { size_t trans_queue_depth; /*!< Depth of internal transfer queue, increase this value can support more transfers pending in the background, only valid in asynchronous transaction. (Typically max_device_num * per_transaction)*/ struct { uint32_t enable_internal_pullup: 1; /*!< Enable internal pullups. Note: This is not strong enough to pullup buses under high-speed frequency. Recommend proper external pull-up if possible */ + uint32_t allow_pd: 1; /*!< If set, the driver will backup/restore the I2C registers before/after entering/exist sleep mode. + By this approach, the system can power off I2C's power domain. + This can save power, but at the expense of more RAM being consumed */ } flags; /*!< I2C master config flags */ } i2c_master_bus_config_t; diff --git a/components/esp_driver_i2c/include/driver/i2c_slave.h b/components/esp_driver_i2c/include/driver/i2c_slave.h index 897b9899ed0..5a443a174c9 100644 --- a/components/esp_driver_i2c/include/driver/i2c_slave.h +++ b/components/esp_driver_i2c/include/driver/i2c_slave.h @@ -40,6 +40,9 @@ typedef struct { #if SOC_I2C_SLAVE_SUPPORT_SLAVE_UNMATCH uint32_t slave_unmatch_en: 1; /*!< Can trigger unmatch interrupt when slave address does not match what master sends*/ #endif + uint32_t allow_pd: 1; /*!< If set, the driver will backup/restore the I2C registers before/after entering/exist sleep mode. + By this approach, the system can power off I2C's power domain. + This can save power, but at the expense of more RAM being consumed */ } flags; /*!< I2C slave config flags */ } i2c_slave_config_t; diff --git a/components/esp_driver_i2c/test_apps/.build-test-rules.yml b/components/esp_driver_i2c/test_apps/.build-test-rules.yml index b363f05a991..5436c0467ea 100644 --- a/components/esp_driver_i2c/test_apps/.build-test-rules.yml +++ b/components/esp_driver_i2c/test_apps/.build-test-rules.yml @@ -5,8 +5,3 @@ components/esp_driver_i2c/test_apps/i2c_test_apps: - if: SOC_I2C_SUPPORTED != 1 depends_components: - esp_driver_i2c - # Following dependency is needed because they might increase lazy installed memory - # that can cause sleep retention memory leak check failed. - - components/ieee802154/** - - components/esp_coex/** - - components/esp_phy/** diff --git a/components/esp_driver_i2c/test_apps/i2c_test_apps/main/CMakeLists.txt b/components/esp_driver_i2c/test_apps/i2c_test_apps/main/CMakeLists.txt index 2f653da9aeb..564a14d2d1f 100644 --- a/components/esp_driver_i2c/test_apps/i2c_test_apps/main/CMakeLists.txt +++ b/components/esp_driver_i2c/test_apps/i2c_test_apps/main/CMakeLists.txt @@ -25,13 +25,10 @@ if(CONFIG_SOC_LP_I2C_SUPPORTED) list(APPEND srcs "test_lp_i2c.c") endif() -# Only build this file with `CONFIG_PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP` and `CONFIG_IEEE802154_ENABLED` enabled -# Enable `CONFIG_IEEE802154_ENABLED` is for modem domain really power down. -# This reliable can be removed if the sleep retention got finished. -if(CONFIG_PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP AND CONFIG_IEEE802154_ENABLED) +if(CONFIG_SOC_I2C_SUPPORT_SLEEP_RETENTION) list(APPEND srcs "test_i2c_sleep_retention.c") endif() idf_component_register(SRCS ${srcs} - PRIV_REQUIRES unity driver test_utils ieee802154 + PRIV_REQUIRES unity driver test_utils WHOLE_ARCHIVE) diff --git a/components/esp_driver_i2c/test_apps/i2c_test_apps/main/test_i2c_sleep_retention.c b/components/esp_driver_i2c/test_apps/i2c_test_apps/main/test_i2c_sleep_retention.c index 8f1ca39d8e8..845791cfed7 100644 --- a/components/esp_driver_i2c/test_apps/i2c_test_apps/main/test_i2c_sleep_retention.c +++ b/components/esp_driver_i2c/test_apps/i2c_test_apps/main/test_i2c_sleep_retention.c @@ -43,6 +43,7 @@ static void i2c_master_write_sleep_retention_test(void) .scl_io_num = I2C_MASTER_SCL_IO, .sda_io_num = I2C_MASTER_SDA_IO, .flags.enable_internal_pullup = true, + .flags.allow_pd = true, }; i2c_master_bus_handle_t bus_handle; @@ -68,7 +69,9 @@ static void i2c_master_write_sleep_retention_test(void) TEST_ESP_OK(i2c_master_transmit(dev_handle, data_wr, DATA_LENGTH, -1)); unity_wait_for_signal("i2c slave receive once, master to sleep"); +#if ESP_SLEEP_POWER_DOWN_CPU TEST_ESP_OK(sleep_cpu_configure(true)); +#endif TEST_ESP_OK(esp_sleep_enable_timer_wakeup(3 * 1000 * 1000)); TEST_ESP_OK(esp_light_sleep_start()); @@ -84,7 +87,9 @@ static void i2c_master_write_sleep_retention_test(void) unity_send_signal("master write again"); unity_wait_for_signal("ready to delete"); +#if ESP_SLEEP_POWER_DOWN_CPU TEST_ESP_OK(sleep_cpu_configure(false)); +#endif TEST_ESP_OK(i2c_master_bus_rm_device(dev_handle)); TEST_ESP_OK(i2c_del_master_bus(bus_handle)); @@ -103,6 +108,7 @@ static void i2c_slave_read_sleep_retention_test(void) .scl_io_num = I2C_SLAVE_SCL_IO, .sda_io_num = I2C_SLAVE_SDA_IO, .slave_addr = 0x58, + .flags.allow_pd = true, }; i2c_slave_dev_handle_t slave_handle; @@ -128,7 +134,9 @@ static void i2c_slave_read_sleep_retention_test(void) unity_send_signal("i2c slave receive once, master to sleep"); // Slave sleep as well.. +#if ESP_SLEEP_POWER_DOWN_CPU TEST_ESP_OK(sleep_cpu_configure(true)); +#endif TEST_ESP_OK(esp_sleep_enable_timer_wakeup(1 * 1000 * 1000)); TEST_ESP_OK(esp_light_sleep_start()); @@ -147,7 +155,9 @@ static void i2c_slave_read_sleep_retention_test(void) vQueueDelete(s_receive_queue); unity_send_signal("ready to delete"); +#if ESP_SLEEP_POWER_DOWN_CPU TEST_ESP_OK(sleep_cpu_configure(false)); +#endif TEST_ESP_OK(i2c_del_slave_device(slave_handle)); } diff --git a/components/esp_driver_i2c/test_apps/i2c_test_apps/pytest_i2c.py b/components/esp_driver_i2c/test_apps/i2c_test_apps/pytest_i2c.py index 56a8eb0bf89..4683913b5c0 100644 --- a/components/esp_driver_i2c/test_apps/i2c_test_apps/pytest_i2c.py +++ b/components/esp_driver_i2c/test_apps/i2c_test_apps/pytest_i2c.py @@ -31,6 +31,8 @@ def test_i2c(dut: Dut) -> None: 'count, config', [ (2, 'defaults',), + (2, 'release',), + (2, 'iram_safe',), ], indirect=True ) @@ -38,19 +40,3 @@ def test_i2c_multi_device(case_tester) -> None: # type: ignore for case in case_tester.test_menu: if case.attributes.get('test_env', 'generic_multi_device') == 'generic_multi_device': case_tester.run_multi_dev_case(case=case, reset=True) - - -@pytest.mark.esp32c6 -@pytest.mark.esp32h2 -@pytest.mark.generic_multi_device -@pytest.mark.parametrize( - 'count, config', - [ - (2, 'sleep_retention',), - ], - indirect=True -) -def test_i2c_sleep_retention(case_tester) -> None: # type: ignore - for case in case_tester.test_menu: - if case.attributes.get('test_env', 'generic_multi_device') == 'generic_multi_device': - case_tester.run_multi_dev_case(case=case, reset=True, timeout=250) diff --git a/components/esp_driver_i2c/test_apps/i2c_test_apps/sdkconfig.ci.iram_safe b/components/esp_driver_i2c/test_apps/i2c_test_apps/sdkconfig.ci.iram_safe index 3d824868635..05c3f1a8d13 100644 --- a/components/esp_driver_i2c/test_apps/i2c_test_apps/sdkconfig.ci.iram_safe +++ b/components/esp_driver_i2c/test_apps/i2c_test_apps/sdkconfig.ci.iram_safe @@ -2,5 +2,6 @@ CONFIG_PM_ENABLE=y CONFIG_COMPILER_DUMP_RTL_FILES=y CONFIG_FREERTOS_USE_TICKLESS_IDLE=y CONFIG_COMPILER_OPTIMIZATION_NONE=y +CONFIG_ESP_MAIN_TASK_STACK_SIZE=8192 CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_SILENT=y CONFIG_I2C_ISR_IRAM_SAFE=y diff --git a/components/esp_driver_i2c/test_apps/i2c_test_apps/sdkconfig.ci.release b/components/esp_driver_i2c/test_apps/i2c_test_apps/sdkconfig.ci.release index 91d93f163e6..eb643d4d06b 100644 --- a/components/esp_driver_i2c/test_apps/i2c_test_apps/sdkconfig.ci.release +++ b/components/esp_driver_i2c/test_apps/i2c_test_apps/sdkconfig.ci.release @@ -1,4 +1,5 @@ CONFIG_PM_ENABLE=y +CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP=y CONFIG_FREERTOS_USE_TICKLESS_IDLE=y CONFIG_COMPILER_OPTIMIZATION_SIZE=y CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE=y diff --git a/components/esp_driver_i2c/test_apps/i2c_test_apps/sdkconfig.ci.sleep_retention b/components/esp_driver_i2c/test_apps/i2c_test_apps/sdkconfig.ci.sleep_retention deleted file mode 100644 index 219e27e6b93..00000000000 --- a/components/esp_driver_i2c/test_apps/i2c_test_apps/sdkconfig.ci.sleep_retention +++ /dev/null @@ -1,5 +0,0 @@ -CONFIG_PM_ENABLE=y -CONFIG_PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP=y -CONFIG_FREERTOS_USE_TICKLESS_IDLE=y -CONFIG_IEEE802154_ENABLED=y -CONFIG_IEEE802154_SLEEP_ENABLE=y diff --git a/components/hal/esp32c6/include/hal/i2c_ll.h b/components/hal/esp32c6/include/hal/i2c_ll.h index e8aaa77828d..c50ad9c1361 100644 --- a/components/hal/esp32c6/include/hal/i2c_ll.h +++ b/components/hal/esp32c6/include/hal/i2c_ll.h @@ -85,9 +85,6 @@ typedef enum { #define LP_I2C_SDA_IOMUX_PAD 6 #define LP_I2C_SCL_IOMUX_PAD 7 -// I2C sleep retention module -#define I2C_SLEEP_RETENTION_MODULE(i2c_num) (SLEEP_RETENTION_MODULE_I2C0) - /** * @brief Calculate I2C bus frequency * Note that the clock accuracy is affected by the external pull-up resistor, diff --git a/components/hal/esp32h2/include/hal/i2c_ll.h b/components/hal/esp32h2/include/hal/i2c_ll.h index d636cc0c719..83d8816f734 100644 --- a/components/hal/esp32h2/include/hal/i2c_ll.h +++ b/components/hal/esp32h2/include/hal/i2c_ll.h @@ -76,9 +76,6 @@ typedef enum { #define I2C_LL_RESET_SLV_SCL_PULSE_NUM_DEFAULT (9) #define I2C_LL_SCL_WAIT_US_VAL_DEFAULT (2500) // Approximate value for SCL timeout regs (in us). -// I2C sleep retention module -#define I2C_SLEEP_RETENTION_MODULE(i2c_num) ((i2c_num == 0) ? SLEEP_RETENTION_MODULE_I2C0 : SLEEP_RETENTION_MODULE_I2C1) - /** * @brief Calculate I2C bus frequency * Note that the clock accuracy is affected by the external pull-up resistor, diff --git a/components/soc/esp32c5/i2c_periph.c b/components/soc/esp32c5/i2c_periph.c index 5cc53907f94..bd702887f88 100644 --- a/components/soc/esp32c5/i2c_periph.c +++ b/components/soc/esp32c5/i2c_periph.c @@ -40,3 +40,32 @@ const i2c_signal_conn_t i2c_periph_signal[SOC_I2C_NUM] = { .irq = ETS_LP_I2C_INTR_SOURCE, }, }; + +// I2C sleep retention entries +// I2C registers require set the reg_update bit to make the configuration take effect + +/* I2C Registers Context + Include: I2C_SCL_LOW_PERIOD_REG / + I2C_CTR_REG / I2C_TO_REG / I2C_SLAVE_ADDR_REG / I2C_FIFO_CONF_REG + I2C_INT_ENA_REG / I2C_SDA_HOLD_REG / I2C_SDA_SAMPLE_REG / I2C_SCL_START_HOLD_REG + I2C_SCL_RSTART_SETUP_REG / I2C_SCL_STOP_HOLD_REG / I2C_SCL_STOP_SETUP_REG /I2C_FILTER_CFG_REG / I2C_CLK_CONF_REG / I2C_SCL_ST_TIME_OUT_REG / I2C_SCL_MAIN_ST_TIME_OUT_REG / I2C_SCL_SP_CONF_REG / I2C_SCL_STRETCH_CONF_REG +*/ +#define I2C0_RETENTION_REGS_CNT 18 +#define I2C0_RETENTION_MAP_BASE I2C_SCL_LOW_PERIOD_REG(0) +static const uint32_t i2c0_regs_map[4] = {0xc03f345b, 0x3, 0, 0}; +static const regdma_entries_config_t i2c0_regs_retention[] = { + [0] = {.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_I2C_LINK(0x00), I2C0_RETENTION_MAP_BASE, I2C0_RETENTION_MAP_BASE, I2C0_RETENTION_REGS_CNT, 0, 0, i2c0_regs_map[0], i2c0_regs_map[1], i2c0_regs_map[2], i2c0_regs_map[3]), \ + .owner = ENTRY(0) | ENTRY(2) }, \ + [1] = {.config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x01), I2C_CTR_REG(0), I2C_FSM_RST, I2C_FSM_RST_M, 1, 0), \ + .owner = ENTRY(0) | ENTRY(2) }, \ + [2] = {.config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x02), I2C_CTR_REG(0), 0x0, I2C_FSM_RST_M, 1, 0), \ + .owner = ENTRY(0) | ENTRY(2) }, \ + [3] = {.config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x03), I2C_CTR_REG(0), I2C_CONF_UPGATE, I2C_CONF_UPGATE_M, 1, 0), \ + .owner = ENTRY(0) | ENTRY(2) }, \ + [4] = {.config = REGDMA_LINK_WAIT_INIT(REGDMA_I2C_LINK(0x04), I2C_CTR_REG(0), 0x0, I2C_CONF_UPGATE_M, 1, 0), \ + .owner = ENTRY(0) | ENTRY(2) }, \ +}; + +const i2c_reg_ctx_link_t i2c_regs_retention[SOC_HP_I2C_NUM] = { + {i2c0_regs_retention, ARRAY_SIZE(i2c0_regs_retention), SLEEP_RETENTION_MODULE_I2C0}, +}; diff --git a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in index 8943b4f2795..23a96312324 100644 --- a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in @@ -615,6 +615,10 @@ config SOC_I2C_SLAVE_SUPPORT_SLAVE_UNMATCH bool default y +config SOC_I2C_SUPPORT_SLEEP_RETENTION + bool + default y + config SOC_LP_I2C_NUM int default 1 diff --git a/components/soc/esp32c5/include/soc/soc_caps.h b/components/soc/esp32c5/include/soc/soc_caps.h index 5badeefac16..c8f1619ce98 100644 --- a/components/soc/esp32c5/include/soc/soc_caps.h +++ b/components/soc/esp32c5/include/soc/soc_caps.h @@ -265,7 +265,7 @@ #define SOC_I2C_SLAVE_SUPPORT_I2CRAM_ACCESS (1) #define SOC_I2C_SLAVE_SUPPORT_SLAVE_UNMATCH (1) -// #define SOC_I2C_SUPPORT_SLEEP_RETENTION (1) // TODO: IDF-9693 +#define SOC_I2C_SUPPORT_SLEEP_RETENTION (1) /*-------------------------- LP_I2C CAPS -------------------------------------*/ // ESP32-C5 has 1 LP_I2C diff --git a/components/soc/esp32c6/i2c_periph.c b/components/soc/esp32c6/i2c_periph.c index 21771444744..c2a39d3c9c6 100644 --- a/components/soc/esp32c6/i2c_periph.c +++ b/components/soc/esp32c6/i2c_periph.c @@ -50,7 +50,7 @@ static const regdma_entries_config_t i2c0_regs_retention[] = { [1] = {.config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x01), I2C_CTR_REG(0), I2C_FSM_RST, I2C_FSM_RST_M, 1, 0), \ .owner = ENTRY(0) | ENTRY(2) }, \ [2] = {.config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x02), I2C_CTR_REG(0), 0x0, I2C_FSM_RST_M, 1, 0), \ - .owner = ENTRY(0) | ENTRY(2) }, \ + .owner = ENTRY(0) | ENTRY(2) }, \ [3] = {.config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x03), I2C_CTR_REG(0), I2C_CONF_UPGATE, I2C_CONF_UPGATE_M, 1, 0), \ .owner = ENTRY(0) | ENTRY(2) }, \ [4] = {.config = REGDMA_LINK_WAIT_INIT(REGDMA_I2C_LINK(0x04), I2C_CTR_REG(0), 0x0, I2C_CONF_UPGATE_M, 1, 0), \ @@ -58,5 +58,5 @@ static const regdma_entries_config_t i2c0_regs_retention[] = { }; const i2c_reg_ctx_link_t i2c_regs_retention[SOC_HP_I2C_NUM] = { - {i2c0_regs_retention, ARRAY_SIZE(i2c0_regs_retention)}, + {i2c0_regs_retention, ARRAY_SIZE(i2c0_regs_retention), SLEEP_RETENTION_MODULE_I2C0}, }; diff --git a/components/soc/esp32c61/i2c_periph.c b/components/soc/esp32c61/i2c_periph.c index cc11ee808f5..f86531948d2 100644 --- a/components/soc/esp32c61/i2c_periph.c +++ b/components/soc/esp32c61/i2c_periph.c @@ -21,3 +21,32 @@ const i2c_signal_conn_t i2c_periph_signal[SOC_I2C_NUM] = { .irq = ETS_I2C_EXT0_INTR_SOURCE, }, }; + +// I2C sleep retention entries +// I2C registers require set the reg_update bit to make the configuration take effect + +/* I2C Registers Context + Include: I2C_SCL_LOW_PERIOD_REG / + I2C_CTR_REG / I2C_TO_REG / I2C_SLAVE_ADDR_REG / I2C_FIFO_CONF_REG + I2C_INT_ENA_REG / I2C_SDA_HOLD_REG / I2C_SDA_SAMPLE_REG / I2C_SCL_START_HOLD_REG + I2C_SCL_RSTART_SETUP_REG / I2C_SCL_STOP_HOLD_REG / I2C_SCL_STOP_SETUP_REG /I2C_FILTER_CFG_REG / I2C_CLK_CONF_REG / I2C_SCL_ST_TIME_OUT_REG / I2C_SCL_MAIN_ST_TIME_OUT_REG / I2C_SCL_SP_CONF_REG / I2C_SCL_STRETCH_CONF_REG +*/ +#define I2C0_RETENTION_REGS_CNT 18 +#define I2C0_RETENTION_MAP_BASE I2C_SCL_LOW_PERIOD_REG +static const uint32_t i2c0_regs_map[4] = {0xc03f345b, 0x3, 0, 0}; +static const regdma_entries_config_t i2c0_regs_retention[] = { + [0] = {.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_I2C_LINK(0x00), I2C0_RETENTION_MAP_BASE, I2C0_RETENTION_MAP_BASE, I2C0_RETENTION_REGS_CNT, 0, 0, i2c0_regs_map[0], i2c0_regs_map[1], i2c0_regs_map[2], i2c0_regs_map[3]), \ + .owner = ENTRY(0) | ENTRY(2) }, \ + [1] = {.config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x01), I2C_CTR_REG, I2C_FSM_RST, I2C_FSM_RST_M, 1, 0), \ + .owner = ENTRY(0) | ENTRY(2) }, \ + [2] = {.config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x02), I2C_CTR_REG, 0x0, I2C_FSM_RST_M, 1, 0), \ + .owner = ENTRY(0) | ENTRY(2) }, \ + [3] = {.config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x03), I2C_CTR_REG, I2C_CONF_UPGATE, I2C_CONF_UPGATE_M, 1, 0), \ + .owner = ENTRY(0) | ENTRY(2) }, \ + [4] = {.config = REGDMA_LINK_WAIT_INIT(REGDMA_I2C_LINK(0x04), I2C_CTR_REG, 0x0, I2C_CONF_UPGATE_M, 1, 0), \ + .owner = ENTRY(0) | ENTRY(2) }, \ +}; + +const i2c_reg_ctx_link_t i2c_regs_retention[SOC_HP_I2C_NUM] = { + {i2c0_regs_retention, ARRAY_SIZE(i2c0_regs_retention), SLEEP_RETENTION_MODULE_I2C0}, +}; diff --git a/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in index 2572350a643..94aaaa03901 100644 --- a/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in @@ -423,6 +423,10 @@ config SOC_I2C_SLAVE_SUPPORT_SLAVE_UNMATCH bool default y +config SOC_I2C_SUPPORT_SLEEP_RETENTION + bool + default y + config SOC_LEDC_SUPPORT_PLL_DIV_CLOCK bool default y diff --git a/components/soc/esp32c61/include/soc/soc_caps.h b/components/soc/esp32c61/include/soc/soc_caps.h index bf1fab84d33..34a34bdb91d 100644 --- a/components/soc/esp32c61/include/soc/soc_caps.h +++ b/components/soc/esp32c61/include/soc/soc_caps.h @@ -228,6 +228,7 @@ #define SOC_I2C_SLAVE_CAN_GET_STRETCH_CAUSE (1) #define SOC_I2C_SLAVE_SUPPORT_I2CRAM_ACCESS (1) #define SOC_I2C_SLAVE_SUPPORT_SLAVE_UNMATCH (1) +#define SOC_I2C_SUPPORT_SLEEP_RETENTION (1) // /*-------------------------- I2S CAPS ----------------------------------------*/ // #define SOC_I2S_NUM (1U) diff --git a/components/soc/esp32h2/i2c_periph.c b/components/soc/esp32h2/i2c_periph.c index f1fd089056a..5afb3995eb3 100644 --- a/components/soc/esp32h2/i2c_periph.c +++ b/components/soc/esp32h2/i2c_periph.c @@ -47,7 +47,7 @@ static const regdma_entries_config_t i2c0_regs_retention[] = { [1] = {.config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x01), I2C_CTR_REG(0), I2C_FSM_RST, I2C_FSM_RST_M, 1, 0), \ .owner = ENTRY(0) | ENTRY(2) }, \ [2] = {.config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x02), I2C_CTR_REG(0), 0x0, I2C_FSM_RST_M, 1, 0), \ - .owner = ENTRY(0) | ENTRY(2) }, \ + .owner = ENTRY(0) | ENTRY(2) }, \ [3] = {.config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x03), I2C_CTR_REG(0), I2C_CONF_UPGATE, I2C_CONF_UPGATE_M, 1, 0), \ .owner = ENTRY(0) | ENTRY(2) }, \ [4] = {.config = REGDMA_LINK_WAIT_INIT(REGDMA_I2C_LINK(0x04), I2C_CTR_REG(0), 0x0, I2C_CONF_UPGATE_M, 1, 0), \ @@ -71,6 +71,6 @@ static const regdma_entries_config_t i2c1_regs_retention[] = { }; const i2c_reg_ctx_link_t i2c_regs_retention[SOC_HP_I2C_NUM] = { - {i2c0_regs_retention, ARRAY_SIZE(i2c0_regs_retention)}, - {i2c1_regs_retention, ARRAY_SIZE(i2c1_regs_retention)}, + {i2c0_regs_retention, ARRAY_SIZE(i2c0_regs_retention), SLEEP_RETENTION_MODULE_I2C0}, + {i2c1_regs_retention, ARRAY_SIZE(i2c1_regs_retention), SLEEP_RETENTION_MODULE_I2C1}, }; diff --git a/components/soc/esp32p4/i2c_periph.c b/components/soc/esp32p4/i2c_periph.c index 41c208dda0f..699e5890dec 100644 --- a/components/soc/esp32p4/i2c_periph.c +++ b/components/soc/esp32p4/i2c_periph.c @@ -34,3 +34,49 @@ const i2c_signal_conn_t i2c_periph_signal[SOC_I2C_NUM] = { .irq = ETS_LP_I2C_INTR_SOURCE, }, }; + +// I2C sleep retention entries +// I2C registers require set the reg_update bit to make the configuration take effect + +/* I2C Registers Context + Include: I2C_SCL_LOW_PERIOD_REG / + I2C_CTR_REG / I2C_TO_REG / I2C_SLAVE_ADDR_REG / I2C_FIFO_CONF_REG + I2C_INT_ENA_REG / I2C_SDA_HOLD_REG / I2C_SDA_SAMPLE_REG / I2C_SCL_START_HOLD_REG + I2C_SCL_RSTART_SETUP_REG / I2C_SCL_STOP_HOLD_REG / I2C_SCL_STOP_SETUP_REG /I2C_FILTER_CFG_REG / I2C_CLK_CONF_REG / I2C_SCL_ST_TIME_OUT_REG / I2C_SCL_MAIN_ST_TIME_OUT_REG / I2C_SCL_SP_CONF_REG / I2C_SCL_STRETCH_CONF_REG +*/ +#define I2C0_RETENTION_REGS_CNT 18 +#define I2C0_RETENTION_MAP_BASE I2C_SCL_LOW_PERIOD_REG(0) +static const uint32_t i2c0_regs_map[4] = {0xc03f345b, 0x3, 0, 0}; +static const regdma_entries_config_t i2c0_regs_retention[] = { + [0] = {.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_I2C_LINK(0x00), I2C0_RETENTION_MAP_BASE, I2C0_RETENTION_MAP_BASE, I2C0_RETENTION_REGS_CNT, 0, 0, i2c0_regs_map[0], i2c0_regs_map[1], i2c0_regs_map[2], i2c0_regs_map[3]), \ + .owner = ENTRY(0) }, \ + [1] = {.config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x01), I2C_CTR_REG(0), I2C_FSM_RST, I2C_FSM_RST_M, 1, 0), \ + .owner = ENTRY(0) }, \ + [2] = {.config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x02), I2C_CTR_REG(0), 0x0, I2C_FSM_RST_M, 1, 0), \ + .owner = ENTRY(0) }, \ + [3] = {.config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x03), I2C_CTR_REG(0), I2C_CONF_UPGATE, I2C_CONF_UPGATE_M, 1, 0), \ + .owner = ENTRY(0) }, \ + [4] = {.config = REGDMA_LINK_WAIT_INIT(REGDMA_I2C_LINK(0x04), I2C_CTR_REG(0), 0x0, I2C_CONF_UPGATE_M, 1, 0), \ + .owner = ENTRY(0) }, \ +}; + +#define I2C1_RETENTION_REGS_CNT 18 +#define I2C1_RETENTION_MAP_BASE I2C_SCL_LOW_PERIOD_REG(1) +static const uint32_t i2c1_regs_map[4] = {0xc03f345b, 0x3, 0, 0}; +static const regdma_entries_config_t i2c1_regs_retention[] = { + [0] = {.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_I2C_LINK(0x00), I2C1_RETENTION_MAP_BASE, I2C1_RETENTION_MAP_BASE, I2C1_RETENTION_REGS_CNT, 0, 0, i2c1_regs_map[0], i2c1_regs_map[1], i2c1_regs_map[2], i2c1_regs_map[3]), \ + .owner = ENTRY(0) }, \ + [1] = {.config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x01), I2C_CTR_REG(1), I2C_FSM_RST, I2C_FSM_RST_M, 1, 0), \ + .owner = ENTRY(0) }, \ + [2] = {.config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x02), I2C_CTR_REG(1), 0x0, I2C_FSM_RST_M, 1, 0), \ + .owner = ENTRY(0) }, \ + [3] = {.config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x03), I2C_CTR_REG(1), I2C_CONF_UPGATE, I2C_CONF_UPGATE_M, 1, 0), \ + .owner = ENTRY(0) }, \ + [4] = {.config = REGDMA_LINK_WAIT_INIT(REGDMA_I2C_LINK(0x04), I2C_CTR_REG(1), 0x0, I2C_CONF_UPGATE_M, 1, 0), \ + .owner = ENTRY(0) }, \ +}; + +const i2c_reg_ctx_link_t i2c_regs_retention[SOC_HP_I2C_NUM] = { + {i2c0_regs_retention, ARRAY_SIZE(i2c0_regs_retention), SLEEP_RETENTION_MODULE_I2C0}, + {i2c1_regs_retention, ARRAY_SIZE(i2c1_regs_retention), SLEEP_RETENTION_MODULE_I2C1}, +}; diff --git a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in index a883653c744..cefa4d0350f 100644 --- a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in @@ -775,6 +775,10 @@ config SOC_I2C_SLAVE_SUPPORT_SLAVE_UNMATCH bool default y +config SOC_I2C_SUPPORT_SLEEP_RETENTION + bool + default y + config SOC_LP_I2C_NUM int default 1 diff --git a/components/soc/esp32p4/include/soc/retention_periph_defs.h b/components/soc/esp32p4/include/soc/retention_periph_defs.h index b069f7babd2..37c04d2071b 100644 --- a/components/soc/esp32p4/include/soc/retention_periph_defs.h +++ b/components/soc/esp32p4/include/soc/retention_periph_defs.h @@ -40,6 +40,8 @@ typedef enum periph_retention_module { SLEEP_RETENTION_MODULE_AXI_DMA_CH0 = 16, SLEEP_RETENTION_MODULE_AXI_DMA_CH1 = 17, SLEEP_RETENTION_MODULE_AXI_DMA_CH2 = 18, + SLEEP_RETENTION_MODULE_I2C0 = 19, + SLEEP_RETENTION_MODULE_I2C1 = 20, SLEEP_RETENTION_MODULE_I2S0 = 19, SLEEP_RETENTION_MODULE_I2S1 = 20, diff --git a/components/soc/esp32p4/include/soc/soc_caps.h b/components/soc/esp32p4/include/soc/soc_caps.h index d7dcd4200f0..ba380964b4f 100644 --- a/components/soc/esp32p4/include/soc/soc_caps.h +++ b/components/soc/esp32p4/include/soc/soc_caps.h @@ -304,7 +304,7 @@ #define SOC_I2C_SLAVE_SUPPORT_I2CRAM_ACCESS (1) #define SOC_I2C_SLAVE_SUPPORT_SLAVE_UNMATCH (1) -// #define SOC_I2C_SUPPORT_SLEEP_RETENTION (1) // TODO: IDF-9353 +#define SOC_I2C_SUPPORT_SLEEP_RETENTION (1) /*-------------------------- LP_I2C CAPS -------------------------------------*/ // ESP32-P4 has 1 LP_I2C diff --git a/components/soc/include/soc/i2c_periph.h b/components/soc/include/soc/i2c_periph.h index 408da3afc49..c1fbb0fbc8d 100644 --- a/components/soc/include/soc/i2c_periph.h +++ b/components/soc/include/soc/i2c_periph.h @@ -11,6 +11,9 @@ #if SOC_I2C_SUPPORTED #include "soc/regdma.h" #include "soc/interrupts.h" +#if SOC_I2C_SUPPORT_SLEEP_RETENTION +#include "soc/retention_periph_defs.h" +#endif #ifdef __cplusplus extern "C" { @@ -31,6 +34,7 @@ extern const i2c_signal_conn_t i2c_periph_signal[SOC_I2C_NUM]; typedef struct { const regdma_entries_config_t *link_list; uint32_t link_num; + periph_retention_module_t module_id; } i2c_reg_ctx_link_t; extern const i2c_reg_ctx_link_t i2c_regs_retention[SOC_HP_I2C_NUM]; diff --git a/docs/en/api-reference/peripherals/i2c.rst b/docs/en/api-reference/peripherals/i2c.rst index a592b250864..dd35c6322b5 100644 --- a/docs/en/api-reference/peripherals/i2c.rst +++ b/docs/en/api-reference/peripherals/i2c.rst @@ -111,7 +111,7 @@ I2C master bus requires the configuration that specified by :cpp:type:`i2c_maste - :cpp:member:`i2c_master_bus_config_t::intr_priority` sets the priority of the interrupt. If set to ``0`` , then the driver will use a interrupt with low or medium priority (priority level may be one of 1, 2 or 3), otherwise use the priority indicated by :cpp:member:`i2c_master_bus_config_t::intr_priority`. Please use the number form (1, 2, 3) , not the bitmask form ((1<<1), (1<<2), (1<<3)). - :cpp:member:`i2c_master_bus_config_t::trans_queue_depth` sets the depth of internal transfer queue. Only valid in asynchronous transaction. - :cpp:member:`i2c_master_bus_config_t::enable_internal_pullup` enables internal pullups. Note: This is not strong enough to pullup buses under high-speed frequency. A suitable external pullup is recommended. - +- :cpp:member:`i2c_master_bus_config_t::allow_pd` configures if the driver allows the system to power down the peripheral in light sleep mode. Before entering sleep, the system will backup the I2C register context, which will be restored later when the system exit the sleep mode. Powering down the peripheral can save more power, but at the cost of more memory consumed to save the register context. It's a tradeoff between power consumption and memory consumption. This configuration option relies on specific hardware feature, if you enable it on an unsupported chip, you will see error message like ``not able to power down in light sleep``. If the configurations in :cpp:type:`i2c_master_bus_config_t` is specified, then :cpp:func:`i2c_new_master_bus` can be called to allocate and initialize an I2C master bus. This function will return an I2C bus handle if it runs correctly. Specifically, when there are no more I2C port available, this function will return :c:macro:`ESP_ERR_NOT_FOUND` error. diff --git a/docs/zh_CN/api-reference/peripherals/i2c.rst b/docs/zh_CN/api-reference/peripherals/i2c.rst index 0b545cf773e..e515082f618 100644 --- a/docs/zh_CN/api-reference/peripherals/i2c.rst +++ b/docs/zh_CN/api-reference/peripherals/i2c.rst @@ -111,6 +111,7 @@ I2C 主机总线需要 :cpp:type:`i2c_master_bus_config_t` 指定的配置： - :cpp:member:`i2c_master_bus_config_t::intr_priority` 设置中断的优先级。如果设置为 ``0``，则驱动程序将使用低或中优先级的中断（优先级可设为 1、2 或 3 中的一个），若未设置，则将使用 :cpp:member:`i2c_master_bus_config_t::intr_priority` 指示的优先级。请使用数字形式（1、2、3），不要用位掩码形式（(1<<1)、(1<<2)、(1<<3)）。 - :cpp:member:`i2c_master_bus_config_t::trans_queue_depth` 设置内部传输队列的深度，但仅在异步传输中有效。 - :cpp:member:`i2c_master_bus_config_t::enable_internal_pullup` 启用内部上拉电阻。注意：该设置无法在高速频率下拉高总线，此时建议使用合适的外部上拉电阻。 +- :cpp:member:`i2c_master_bus_config_t::allow_pd` 配置驱动程序是否允许系统在睡眠模式下关闭外设电源。在进入睡眠之前，系统将备份 I2C 寄存器上下文，当系统退出睡眠模式时，这些上下文将被恢复。关闭外设可以节省更多功耗，但代价是消耗更多内存来保存寄存器上下文。你需要在功耗和内存消耗之间做权衡。此配置选项依赖于特定的硬件功能，如果在不支持的芯片上启用它，你将看到类似 ``not able to power down in light sleep`` 的错误消息。 如果在 :cpp:type:`i2c_master_bus_config_t` 中指定了配置，则可调用 :cpp:func:`i2c_new_master_bus` 来分配和初始化 I2C 主机总线。如果函数运行正确，则将返回一个 I2C 总线句柄。若没有可用的 I2C 端口，此函数将返回 :c:macro:`ESP_ERR_NOT_FOUND` 错误。 diff --git a/tools/test_apps/system/cxx_build_test/main/test_i2c_lcd.cpp b/tools/test_apps/system/cxx_build_test/main/test_i2c_lcd.cpp index cb058d62c06..716e6d4eb0e 100644 --- a/tools/test_apps/system/cxx_build_test/main/test_i2c_lcd.cpp +++ b/tools/test_apps/system/cxx_build_test/main/test_i2c_lcd.cpp @@ -52,6 +52,7 @@ void test_i2c_lcd_apis(void) .trans_queue_depth = 4, .flags = { .enable_internal_pullup = true, + .allow_pd = false, } }; From 0a9c99f86e7cc13454468beb825b66bf9567d628 Mon Sep 17 00:00:00 2001 From: Marius Vikhammer Date: Tue, 8 Oct 2024 16:19:01 +0800 Subject: [PATCH 047/472] change(system): cleanup c5 reset reason todo --- components/soc/esp32c5/include/soc/reset_reasons.h | 1 - 1 file changed, 1 deletion(-) diff --git a/components/soc/esp32c5/include/soc/reset_reasons.h b/components/soc/esp32c5/include/soc/reset_reasons.h index f86a798e289..8822b2573a5 100644 --- a/components/soc/esp32c5/include/soc/reset_reasons.h +++ b/components/soc/esp32c5/include/soc/reset_reasons.h @@ -23,7 +23,6 @@ extern "C" { #endif -// TODO: [ESP32C5] IDF-8660 Check reset reasons for MP version /** * @brief Naming conventions: RESET_REASON_{reset level}_{reset reason} * @note refer to TRM: chapter From 08eadd8d25abb4766807b7ba3aadfbee4791cb69 Mon Sep 17 00:00:00 2001 From: Alexey Lapshin Date: Fri, 6 Sep 2024 18:27:09 +0700 Subject: [PATCH 048/472] fix(newlib): sbom: add CVE-2024-30949 to cve-exclude-list --- components/newlib/sbom.yml | 3 +++ docs/en/security/vulnerabilities.rst | 9 +++++++++ 2 files changed, 12 insertions(+) diff --git a/components/newlib/sbom.yml b/components/newlib/sbom.yml index f0fee872555..496cb10c30b 100644 --- a/components/newlib/sbom.yml +++ b/components/newlib/sbom.yml @@ -4,3 +4,6 @@ cpe: cpe:2.3:a:newlib_project:newlib:{}:*:*:*:*:*:*:* supplier: 'Organization: Espressif Systems (Shanghai) CO LTD' originator: 'Organization: Red Hat Incorporated' description: An open-source C standard library implementation with additional features and patches from Espressif. +cve-exclude-list: + - cve: CVE-2024-30949 + reason: A vulnerability was discovered in the gettimeofday system call implementation within the RISC-V libgloss component of Newlib. ESP-IDF does not link against libgloss for RISC-V, hence the issue is not directly applicable. Still, the relevant fix has been patched through https://github.com/espressif/newlib-esp32/commit/047ba47013c2656a1e7838dc86cbc75aeeaa67a7 diff --git a/docs/en/security/vulnerabilities.rst b/docs/en/security/vulnerabilities.rst index a8629f945e9..00d87aad5ff 100644 --- a/docs/en/security/vulnerabilities.rst +++ b/docs/en/security/vulnerabilities.rst @@ -10,6 +10,15 @@ This page briefly lists all of the vulnerabilities that are discovered and fixed CVE-2024 -------- +CVE-2024-30949 +~~~~~~~~~~~~~~ + +RISC-V gettimeofday system call vulnerability in Newlib's + +* Impact: ESP-IDF does not use system call implementations from Newlib +* Resolution: NA + + CVE-2024-28183 ~~~~~~~~~~~~~~ From 5888cb8b4c4ef5e5a2deb8fac36f7019f745bde8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Neboj=C5=A1a=20Cvetkovi=C4=87?= Date: Thu, 27 Jun 2024 18:26:11 +0100 Subject: [PATCH 049/472] build: Reduce verbosity of disabled component manager warning closes https://github.com/espressif/esp-idf/pull/14097 --- tools/cmake/build.cmake | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/cmake/build.cmake b/tools/cmake/build.cmake index 81f133e2301..c9414c437d4 100644 --- a/tools/cmake/build.cmake +++ b/tools/cmake/build.cmake @@ -631,7 +631,7 @@ macro(idf_build_process target) endforeach() if(NOT "${__components_with_manifests}" STREQUAL "") - message(WARNING "\"idf_component.yml\" file was found for components:\n${__components_with_manifests}" + message(NOTICE "\"idf_component.yml\" file was found for components:\n${__components_with_manifests}" "However, the component manager is not enabled.") endif() endif() From 24fa2facd3849c57cc638fab7e410f52807e33b4 Mon Sep 17 00:00:00 2001 From: Mahavir Jain Date: Mon, 30 Sep 2024 10:44:44 +0530 Subject: [PATCH 050/472] docs: update mbedtls guide for TLS 1.3 supported change --- docs/en/api-reference/protocols/mbedtls.rst | 12 ++++-------- docs/zh_CN/api-reference/protocols/mbedtls.rst | 12 ++++-------- 2 files changed, 8 insertions(+), 16 deletions(-) diff --git a/docs/en/api-reference/protocols/mbedtls.rst b/docs/en/api-reference/protocols/mbedtls.rst index 11a9fb02df3..cc636fd033c 100644 --- a/docs/en/api-reference/protocols/mbedtls.rst +++ b/docs/en/api-reference/protocols/mbedtls.rst @@ -9,7 +9,7 @@ Mbed TLS ESP-IDF uses a `fork `_ of Mbed TLS which includes a few patches (related to hardware routines of certain modules like ``bignum (MPI)`` and ``ECC``) over vanilla Mbed TLS. -Mbed TLS supports SSL 3.0 up to TLS 1.3 and DTLS 1.0 to 1.2 communication by providing the following: +Mbed TLS supports TLS 1.2, TLS 1.3 and DTLS 1.2 communication by providing the following: - TCP/IP communication functions: listen, connect, accept, read/write. - SSL/TLS communication functions: init, handshake, read/write. @@ -18,8 +18,9 @@ Mbed TLS supports SSL 3.0 up to TLS 1.3 and DTLS 1.0 to 1.2 communication by pro - Hashing - Encryption/decryption -Supported TLS versions include SSL 3.0, TLS 1.0, TLS 1.1, TLS 1.2, and TLS 1.3, but on the latest ESP-IDF, SSL 3.0, TLS 1.0, and TLS 1.1 have been removed from Mbed TLS. Supported DTLS versions include DTLS 1.0, DTLS 1.1, and DTLS 1.2, but on the latest ESP-IDF, DTLS 1.0 has been removed from Mbed TLS. +.. note:: + Mbed TLS v3.x.x series supports only TLS 1.2 and TLS 1.3 protocols. Support for SSL 3.0, TLS 1.0/1.1 and DTLS 1.0 has been removed (deprecated). TLS 1.3 is fully supported starting Mbed TLS v3.6.0 release, before this release some features were still in experimental state. Please refer to :component_file:`Mbed TLS ChangeLog ` for more details. Mbed TLS Documentation ---------------------- @@ -73,11 +74,6 @@ Following is a brief list of important config options accessible at ``Component :SOC_MPI_SUPPORTED: - :ref:`CONFIG_MBEDTLS_HARDWARE_MPI`: Support for hardware MPI (bignum) acceleration :SOC_ECC_SUPPORTED: - :ref:`CONFIG_MBEDTLS_HARDWARE_ECC`: Support for hardware ECC acceleration -.. note:: - - Mbed TLS v3.6.0 and later support only TLS 1.2 and TLS 1.3 (SSL 3.0, TLS 1.0, TLS 1.1, and DTLS 1.0 are not supported). More information about this can be found out `here `__. - - Performance and Memory Tweaks ----------------------------- @@ -122,5 +118,5 @@ Reducing Binary Size Under ``Component Config -> mbedTLS``, there are multiple Mbed TLS features which are enabled by default but can be disabled if not needed to save code size. More information can be about this can be found in :ref:`Minimizing Binary Size ` docs. -.. _`API Reference`: https://mbed-tls.readthedocs.io/projects/api/en/v3.4.1/ +.. _`API Reference`: https://mbed-tls.readthedocs.io/projects/api/en/v3.6.1/ .. _`Knowledge Base`: https://mbed-tls.readthedocs.io/en/latest/kb/ diff --git a/docs/zh_CN/api-reference/protocols/mbedtls.rst b/docs/zh_CN/api-reference/protocols/mbedtls.rst index 976d039ac40..2ed68754969 100644 --- a/docs/zh_CN/api-reference/protocols/mbedtls.rst +++ b/docs/zh_CN/api-reference/protocols/mbedtls.rst @@ -9,7 +9,7 @@ Mbed TLS ESP-IDF 使用的 Mbed TLS `复刻仓库 `_ 中包含对原生 Mbed TLS 的补丁。这些补丁与某些模块的硬件例程有关，如 ``bignum (MPI)`` 和 ``ECC``。 -Mbed TLS 提供以下功能： +Mbed TLS 通过提供以下内容支持 TLS 1.2、TLS 1.3 和 DTLS 1.2 通信： - TCP/IP 通信功能：监听、连接、接收、读/写。 - SSL/TLS 通信功能：初始化、握手、读/写。 @@ -18,8 +18,9 @@ Mbed TLS 提供以下功能： - 哈希 - 加密/解密 -TLS 版本支持 SSL 3.0, TLS 1.0、TLS 1.1、TLS 1.2 和 TLS 1.3，但是最新的 ESP-IDF 上 Mbed TLS 已经移除了 SSL 3.0、TLS 1.0 和 TLS 1.1。DTLS 版本支持 DTLS 1.0、DTLS 1.1 和 DTLS 1.2，但最新的 ESP-IDF 上 Mbed TLS 已经移除了 DTLS 1.0。 +.. note:: + Mbed TLS v3.x.x 系列仅支持 TLS 1.2 和 TLS 1.3 协议。对 SSL 3.0、TLS 1.0/1.1 和 DTLS 1.0 的支持已被删除（弃用）。从 Mbed TLS v3.6.0 版本开始完全支持 TLS 1.3，在此版本之前，某些功能仍处于试验状态。有关更多详细信息，请参阅 :component_file:`Mbed TLS ChangeLog `。 Mbed TLS 文档 ------------------ @@ -73,11 +74,6 @@ ESP-IDF 中的示例使用 :doc:`/api-reference/protocols/esp_tls`，为访问 :SOC_MPI_SUPPORTED: - :ref:`CONFIG_MBEDTLS_HARDWARE_MPI`: 支持硬件 MPI (bignum) 加速 :SOC_ECC_SUPPORTED: - :ref:`CONFIG_MBEDTLS_HARDWARE_ECC`: 支持硬件 ECC 加速 -.. note:: - - Mbed TLS v3.0.0 及其更新版本仅支持 TLS 1.2 和 TLS 1.3，不支持 SSL 3.0、TLS 1.0、TLS 1.1、和 DTLS 1.0)。TLS 1.3 尚在试验阶段，仅支持客户端。要了解更多信息，请点击 `此处 `__。 - - 性能和内存调整 ------------------ @@ -122,5 +118,5 @@ ESP-IDF 中的示例使用 :doc:`/api-reference/protocols/esp_tls`，为访问 在 ``Component Config -> mbedTLS`` 中，有多个 Mbed TLS 功能默认为启用状态。如果不需要这些功能，可将其禁用以减小固件大小。要了解更多信息，请参考 :ref:`Minimizing Binary Size ` 文档。 -.. _`API Reference`: https://mbed-tls.readthedocs.io/projects/api/en/v3.4.1/ +.. _`API Reference`: https://mbed-tls.readthedocs.io/projects/api/en/v3.6.1/ .. _`Knowledge Base`: https://mbed-tls.readthedocs.io/en/latest/kb/ From 0e5adc1b9c3526d14996cc29420774ae3879e439 Mon Sep 17 00:00:00 2001 From: Sudeep Mohanty Date: Tue, 8 Oct 2024 12:05:39 +0200 Subject: [PATCH 051/472] feat(freertos): Add FreeRTOS port layer mocks for CMock tests This commit adds mocks for the FreeRTOS linux port layer for tests which mock the FreeRTOS component and use port layer APIs. --- .../portable/linux/include/freertos/portmacro.h | 4 ++-- tools/mocks/freertos/CMakeLists.txt | 3 ++- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/components/freertos/FreeRTOS-Kernel/portable/linux/include/freertos/portmacro.h b/components/freertos/FreeRTOS-Kernel/portable/linux/include/freertos/portmacro.h index 179265b778e..583c568d888 100644 --- a/components/freertos/FreeRTOS-Kernel/portable/linux/include/freertos/portmacro.h +++ b/components/freertos/FreeRTOS-Kernel/portable/linux/include/freertos/portmacro.h @@ -94,8 +94,8 @@ extern void vPortEnableInterrupts( void ); extern BaseType_t xPortSetInterruptMask( void ); extern void vPortClearInterruptMask( BaseType_t xMask ); -extern void vPortEnterCritical( void ); -extern void vPortExitCritical( void ); +void vPortEnterCritical( void ); +void vPortExitCritical( void ); #define portSET_INTERRUPT_MASK_FROM_ISR() xPortSetInterruptMask() #define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vPortClearInterruptMask(x) #define portDISABLE_INTERRUPTS() portSET_INTERRUPT_MASK() diff --git a/tools/mocks/freertos/CMakeLists.txt b/tools/mocks/freertos/CMakeLists.txt index ce6111260ab..9286bd3d2ce 100644 --- a/tools/mocks/freertos/CMakeLists.txt +++ b/tools/mocks/freertos/CMakeLists.txt @@ -25,7 +25,8 @@ idf_component_mock(INCLUDE_DIRS ${include_dirs} ${original_freertos_dir}/esp_additions/include/freertos/idf_additions.h ${original_freertos_dir}/FreeRTOS-Kernel/include/freertos/task.h ${original_freertos_dir}/FreeRTOS-Kernel/include/freertos/event_groups.h - ${original_freertos_dir}/FreeRTOS-Kernel/include/freertos/queue.h) + ${original_freertos_dir}/FreeRTOS-Kernel/include/freertos/queue.h + ${original_freertos_dir}/FreeRTOS-Kernel/portable/linux/include/freertos/portmacro.h) idf_component_get_property(freertos_lib freertos COMPONENT_LIB) target_compile_definitions(${freertos_lib} PUBLIC "projCOVERAGE_TEST=0") From ff25e646fb7ec627d12bb376cf2a3f88a7e12e6a Mon Sep 17 00:00:00 2001 From: Abhik Roy Date: Sun, 29 Sep 2024 14:24:25 +1000 Subject: [PATCH 052/472] fix(lwip): Fixed active DNS entries before clearing cache --- components/lwip/lwip | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/components/lwip/lwip b/components/lwip/lwip index f150e2321ac..b15cd2de75d 160000 --- a/components/lwip/lwip +++ b/components/lwip/lwip @@ -1 +1 @@ -Subproject commit f150e2321ac09bb0fd35a7fcbc1b116fbf93434e +Subproject commit b15cd2de75d408f9f813367571143b9bcff20738 From 160b1b3b32edcaea5065355e5feb35fef637ea3a Mon Sep 17 00:00:00 2001 From: renpeiying Date: Tue, 8 Oct 2024 19:07:30 +0800 Subject: [PATCH 053/472] docs: Remove user guide for esp32-devkitm-1 migration --- docs/_static/ESP32_DevKitM-1_pinlayout.png | Bin 410187 -> 0 bytes docs/_static/esp32-DevKitM-1-front.png | Bin 1138905 -> 0 bytes docs/_static/esp32-DevKitM-1-isometric.png | Bin 1215003 -> 0 bytes .../esp32-DevKitM-1_v1_SystemBlock.png | Bin 166318 -> 0 bytes .../esp32-devkitm-1-v1-annotated-photo.png | Bin 509115 -> 0 bytes docs/en/get-started/index.rst | 2 +- .../esp32/user-guide-devkitm-1.rst | 335 ------------------ docs/zh_CN/get-started/index.rst | 2 +- .../esp32/user-guide-devkitm-1.rst | 335 ------------------ 9 files changed, 2 insertions(+), 672 deletions(-) delete mode 100644 docs/_static/ESP32_DevKitM-1_pinlayout.png delete mode 100644 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    Setup serial port for QEMU - If you are enabling eFuses on esp32c3 emulated using QEMU then we shall set the serial port as follows: + If you are enabling eFuses on ESP32-C3 emulated using QEMU then we shall set the serial port as follows: export ESPPORT=socket://localhost:5555 @@ -40,19 +39,23 @@ export ESPPORT=/* Serial port to which esp is connected */
    -**Please make sure to perform this step every time when you open a new terminal to use `esptool/espefuse` commands.** +**Make sure to perform this step every time when you open a new terminal to use `esptool/espefuse` commands.** ### 2. Erase flash We shall erase the flash on the device to ensure a clean state. -```idf.py -p $ESPPORT erase_flash``` +``` +idf.py -p $ESPPORT erase_flash +``` ### 3. Install esptool We shall require esptool utility which can be installed as follows: -```pip install esptool``` +``` +pip install esptool +``` ### 4. Installing qemu (optional) @@ -112,7 +115,8 @@ When the application is built (later in the workflow) the `bootloader` and `appl ``` espsecure.py sign_data --version 2 --keyfile /* Signing key placeholder */ --output bootloader-signed.bin build/bootloader/bootloader.bin - + ``` + ``` espsecure.py sign_data --version 2 --keyfile /* Signing key placeholder */ --output my-app-signed.bin build/security_features.bin ``` @@ -122,7 +126,7 @@ When the application is built (later in the workflow) the `bootloader` and `appl Details about the Flash Encryption protocol can be found at the [Flash Encryption documentation](https://docs.espressif.com/projects/esp-idf/en/stable/esp32c3/security/flash-encryption.html) The indicates the status of Flash Encryption feature for the chip. The example also demonstrates writing and reading encrypted partitions in flash. -Please follow below steps to enable Flash Encryption: +Follow below steps to enable Flash Encryption: 1. Generate Flash Encryption keys @@ -163,9 +167,11 @@ It can be done with following commands: ``` espsecure.py encrypt_flash_data --aes_xts --keyfile my_flash_encryption_key.bin --address 0x0 --output encrypted_data/bootloader-enc.bin build/bootloader/bootloader.bin - +``` +``` espsecure.py encrypt_flash_data --aes_xts --keyfile my_flash_encryption_key.bin --address 0xD000 --output encrypted_data/partition-table-enc.bin build/partition_table/partition-table.bin - +``` +``` espsecure.py encrypt_flash_data --aes_xts --keyfile my_flash_encryption_key.bin --address 0x20000 --output encrypted_data/security_features-enc.bin build/security_features_app.bin ``` @@ -200,7 +206,7 @@ We shall use the [nvs_partition_gen.py](../../../components/nvs_flash/nvs_partit Execute following command to generate the encrypted NVS partition. ``` - python3 nvs_partition_gen.py encrypt /* CSV placeholder */ nvs_encr_partition.bin /* NVS partition offset */ --inputkey keys/nvs_encr_key.bin + python3 $IDF_PATH/components/nvs_flash/nvs_partition_generator/nvs_partition_gen.py encrypt /* CSV placeholder */ nvs_encr_partition.bin /* NVS partition offset */ --inputkey keys/nvs_encr_key.bin ``` * `CSV placeholder`: CSV file which contains data of the NVS partition. See [CSV file format](https://docs.espressif.com/projects/esp-idf/en/stable/esp32c3/api-reference/storage/nvs_partition_gen.html#csv-file-format) for more details. * `NVS partition offset`: NVS partition offset. Can be found out by executing `idf.py partition-table` @@ -463,7 +469,7 @@ A hex file containing the eFuse configuration of ESP32C3 v0.3 (ECO3) has been ke This command shall start a serial connection with QEMU. Keep this running in one terminal and execute espefuse commands in an alternate terminal. - After espefuse commands are used to update the eFuses of the emulated esp the eFuse file generated in *Step 1* shall get ovwewritten. To revert to the original state, execute the command provided in *Step 1* once again. + After espefuse commands are used to update the eFuses of the emulated esp the eFuse file generated in *Step 1* shall get overwritten. To revert to the original state, execute the command provided in *Step 1* once again. 3. Execute the commands to enable security features From 6d86e581d3fbe3d932c16d99f9463f4de9a113f0 Mon Sep 17 00:00:00 2001 From: Aditya Patwardhan Date: Mon, 14 Oct 2024 11:18:49 +0530 Subject: [PATCH 140/472] feat(security): Added README for security examples --- examples/security/README.md | 39 +++++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) create mode 100644 examples/security/README.md diff --git a/examples/security/README.md b/examples/security/README.md new file mode 100644 index 00000000000..2d9f53a4c76 --- /dev/null +++ b/examples/security/README.md @@ -0,0 +1,39 @@ +# Security Examples + +## Security Features App + +This example demonstrates how to enable most of the security features on the ESP32 series SoC with the help of host-based tools such as (idf.py, esptool, espsecure). The example also supports the use of QEMU emulated ESP32-C3 for testing the security features without the need for physical hardware. +Note: Currently, this example is only supported on the ESP32-C3 SoC. +The example demonstrates the following security features: +* Secure Boot V2 +* Flash Encryption +* HMAC-based NVS Encryption +* Secure JTAG Return Material Access + +## Flash Encryption + +The Flash Encryption example for the ESP32 series SoC demonstrates how to enable and use flash encryption in Development and Release modes. +It includes: +* Checking the status of flash encryption and relevant eFuses. +* Writing to and reading from encrypted flash partitions. +* Initializing FATFS and NVS partitions, both encrypted and non-encrypted. +* Flashing the example in different modes, with guidance on handling encrypted data. + +## NVS Encryption - HMAC + +This example demonstrates how to use NVS (Non-Volatile Storage) encryption with an HMAC-based encryption key protection scheme on Espressif SoC chips. The encryption keys are derived from an HMAC key stored in eFuse, ensuring they are not stored in flash memory. This approach eliminates the need for a separate nvs_keys partition and does not require flash encryption to be enabled. +The steps include: +* Generating a secure HMAC key using the host tool. +* Burning the HMAC key into the eFuse. +* Enabling the HMAC-based NVS encryption scheme. +* Reading and writing to the encrypted NVS partition. + +## HMAC Soft JTAG + +The "JTAG Re-enable Example" demonstrates how to use the HMAC peripheral to securely re-enable a software-disabled JTAG interface after authentication on supported ESP32 Series SoCs. This is useful for implementing the Return Material Access (RMA) feature for a device. +The steps include: +* Generating a 32-byte HMAC key. +* Burning the key to an eFuse. +* Generating token data from the key. +* Using commands to re-enable JTAG access. + From 4d7436f861fd47da2b3d0220ebdfb42da030ea19 Mon Sep 17 00:00:00 2001 From: Linda Date: Fri, 20 Sep 2024 12:17:36 +0800 Subject: [PATCH 141/472] docs: update application examples for modbus.rst, mqtt.rst and lwip.rst --- docs/en/api-guides/lwip.rst | 27 ++++++++++------- docs/en/api-reference/network/esp_netif.rst | 15 +++++----- docs/en/api-reference/protocols/icmp_echo.rst | 6 ++-- docs/en/api-reference/protocols/modbus.rst | 17 ++++++----- docs/en/api-reference/protocols/mqtt.rst | 29 ++++++++++++------- docs/zh_CN/api-guides/lwip.rst | 23 ++++++++++----- .../zh_CN/api-reference/network/esp_netif.rst | 14 ++++----- .../api-reference/protocols/icmp_echo.rst | 2 +- docs/zh_CN/api-reference/protocols/modbus.rst | 11 ++++--- docs/zh_CN/api-reference/protocols/mqtt.rst | 25 +++++++++++----- 10 files changed, 102 insertions(+), 67 deletions(-) diff --git a/docs/en/api-guides/lwip.rst b/docs/en/api-guides/lwip.rst index 462ded4e9eb..1920e2b03ad 100644 --- a/docs/en/api-guides/lwip.rst +++ b/docs/en/api-guides/lwip.rst @@ -31,9 +31,9 @@ Some common lwIP app APIs are supported indirectly by ESP-IDF: DNS server configuration in lwIP is global, not interface-specific. If you are using multiple network interfaces with distinct DNS servers, exercise caution to prevent inadvertent overwrites of one interface's DNS settings when acquiring a DHCP lease from another interface. -- Simple Network Time Protocol (SNTP) is also supported via the :doc:`/api-reference/network/esp_netif`, or directly via the :component_file:`lwip/include/apps/esp_sntp.h` functions, which also provide thread-safe API to :component_file:`lwip/lwip/src/include/lwip/apps/sntp.h` functions, see also :ref:`system-time-sntp-sync`. +- Simple Network Time Protocol (SNTP) is also supported via the :doc:`/api-reference/network/esp_netif`, or directly via the :component_file:`lwip/include/apps/esp_sntp.h` functions, which also provide thread-safe API to :component_file:`lwip/lwip/src/include/lwip/apps/sntp.h` functions, see also :ref:`system-time-sntp-sync`. For implementation details, see :example:`protocols/sntp`. This example demonstrates how to use the LwIP SNTP module to obtain time from internet servers, configure the synchronization method and interval, and retrieve time using the SNTP-over-DHCP module. - ICMP Ping is supported using a variation on the lwIP ping API, see :doc:`/api-reference/protocols/icmp_echo`. -- ICMPv6 Ping, supported by lwIP's ICMPv6 Echo API, is used to test IPv6 network connectivity. For more information, see :example:`protocols/sockets/icmpv6_ping`. +- ICMPv6 Ping, supported by lwIP's ICMPv6 Echo API, is used to test IPv6 network connectivity. For more information, see :example:`protocols/sockets/icmpv6_ping`. This example demonstrates how to use the network interface to discover an IPv6 address, create a raw ICMPv6 socket, send an ICMPv6 Echo Request to a destination IPv6 address, and wait for an Echo Reply from the target. - NetBIOS lookup is available using the standard lwIP API. :example:`protocols/http_server/restful_server` has the option to demonstrate using NetBIOS to look up a host on the LAN. - mDNS uses a different implementation to the lwIP default mDNS, see :doc:`/api-reference/protocols/mdns`. But lwIP can look up mDNS hosts using standard APIs such as ``gethostbyname()`` and the convention ``hostname.local``, provided the :ref:`CONFIG_LWIP_DNS_SUPPORT_MDNS_QUERIES` setting is enabled. - The PPP implementation in lwIP can be used to create PPPoS (PPP over serial) interface in ESP-IDF. Please refer to the documentation of the :doc:`/api-reference/network/esp_netif` component to create and configure a PPP network interface, by means of the ``ESP_NETIF_DEFAULT_PPP()`` macro defined in :component_file:`esp_netif/include/esp_netif_defaults.h`. Additional runtime settings are provided via :component_file:`esp_netif/include/esp_netif_ppp.h`. PPPoS interfaces are typically used to interact with NBIoT/GSM/LTE modems. More application-level friendly API is supported by the `esp_modem `_ library, which uses this PPP lwIP module behind the scenes. @@ -53,17 +53,24 @@ A wide range of BSD Sockets reference materials are available, including: - `Single UNIX Specification - BSD Sockets page `_ - `Berkeley Sockets - Wikipedia page `_ -Examples -^^^^^^^^ +Application Examples +^^^^^^^^^^^^^^^^^^^^ A number of ESP-IDF examples show how to use the BSD Sockets APIs: -- :example:`protocols/sockets/tcp_server` -- :example:`protocols/sockets/tcp_client` -- :example:`protocols/sockets/udp_server` -- :example:`protocols/sockets/udp_client` -- :example:`protocols/sockets/udp_multicast` -- :example:`protocols/http_request`: this simplified example uses a TCP socket to send an HTTP request, but :doc:`/api-reference/protocols/esp_http_client` is a much better option for sending HTTP requests +- :example:`protocols/sockets/non_blocking` demonstrates how to configure and run a non-blocking TCP client and server, supporting both IPv4 and IPv6 protocols. + +- :example:`protocols/sockets/tcp_server` demonstrates how to create a TCP server that accepts client connection requests and receives data. + +- :example:`protocols/sockets/tcp_client` demonstrates how to create a TCP client that connects to a server using a predefined IP address and port. + +- :example:`protocols/sockets/tcp_client_multi_net` demonstrates how to use Ethernet and Wi-Fi interfaces together, connect to both simultaneously, create a TCP client for each interface, and send a basic HTTP request and response. + +- :example:`protocols/sockets/udp_server` demonstrates how to create a UDP server that receives client connection requests and data. + +- :example:`protocols/sockets/udp_client` demonstrates how to create a UDP client that connects to a server using a predefined IP address and port. + +- :example:`protocols/sockets/udp_multicast` demonstrates how to use the IPV4 and IPV6 UDP multicast features via the BSD-style sockets interface. Supported Functions ^^^^^^^^^^^^^^^^^^^ diff --git a/docs/en/api-reference/network/esp_netif.rst b/docs/en/api-reference/network/esp_netif.rst index 70faff41a15..e9ffb448bea 100644 --- a/docs/en/api-reference/network/esp_netif.rst +++ b/docs/en/api-reference/network/esp_netif.rst @@ -82,20 +82,19 @@ Common Network Interfaces As the initialization of network interfaces could be quite complex, ESP-NETIF provides some convenient methods of creating the most common ones, such as Wi-Fi and Ethernet. -Please refer to the following example to understand the initialization process of the default interface: +Please refer to the following examples to understand the initialization process of the default interface: +.. list:: -.. only:: SOC_WIFI_SUPPORTED - - - Wi-Fi Station: :example_file:`wifi/getting_started/station/main/station_example_main.c` + :SOC_WIFI_SUPPORTED: - :example:`wifi/getting_started/station` demonstrates how to use the station functionality to connect {IDF_TARGET_NAME} to an AP. -- Ethernet: :example_file:`ethernet/basic/main/ethernet_example_main.c` + :CONFIG_ESP_WIFI_SOFTAP_SUPPORT: - :example:`wifi/getting_started/softAP` demonstrates how to use the SoftAP functionality to configure {IDF_TARGET_NAME} as an AP. -- L2 TAP: :example_file:`protocols/l2tap/main/l2tap_main.c` + - :example:`ethernet/basic` demonstrates how to use the Ethernet driver, attach it to `esp_netif`, and obtain an IP address that can be pinged. -.. only:: CONFIG_ESP_WIFI_SOFTAP_SUPPORT + - :example:`protocols/l2tap` demonstrates how to use the ESP-NETIF L2 TAP interface to access the Data Link Layer for receiving and transmitting frames, implement non-IP protocols, and echo Ethernet frames with specific EthTypes. - - Wi-Fi Access Point: :example_file:`wifi/getting_started/softAP/main/softap_example_main.c` + - :example:`protocols/static_ip` demonstrates how to configure Wi-Fi as a station, including setting up a static IP, netmask, gateway and DNS server. .. only:: SOC_WIFI_SUPPORTED diff --git a/docs/en/api-reference/protocols/icmp_echo.rst b/docs/en/api-reference/protocols/icmp_echo.rst index 929211088b4..5aa1451133a 100644 --- a/docs/en/api-reference/protocols/icmp_echo.rst +++ b/docs/en/api-reference/protocols/icmp_echo.rst @@ -109,10 +109,10 @@ Get Runtime Statistics As the example code above, you can call ``esp_ping_get_profile`` to get different runtime statistics of ping session in the callback function. -Application Example -------------------- +Application Examples +-------------------- -ICMP echo example: :example:`protocols/icmp_echo` +- :example:`protocols/icmp_echo` demonstrates how to implement a simple ping command line utility to test if a remote host is reachable on the IP network, using ICMP echo request packets. API Reference ------------- diff --git a/docs/en/api-reference/protocols/modbus.rst b/docs/en/api-reference/protocols/modbus.rst index c74978e2f24..529f3c8b414 100644 --- a/docs/en/api-reference/protocols/modbus.rst +++ b/docs/en/api-reference/protocols/modbus.rst @@ -14,15 +14,18 @@ The documentation can be found through the link below: * `ESP-Modbus documentation (English) `__ -Application Example -------------------- +Application Examples +-------------------- The examples below demonstrate the ESP-Modbus library of serial and TCP ports for both slave and master implementations respectively. -- :example:`protocols/modbus/serial/mb_slave` -- :example:`protocols/modbus/serial/mb_master` -- :example:`protocols/modbus/tcp/mb_tcp_slave` -- :example:`protocols/modbus/tcp/mb_tcp_master` +- :example:`protocols/modbus/serial/mb_slave` demonstrates how to use {IDF_TARGET_NAME} as a Modbus serial slave device with the esp-modbus stack, enabling an external Modbus host to read and write device parameters using the Modbus protocol. + +- :example:`protocols/modbus/serial/mb_master` demonstrates how to use the esp-modbus stack port on {IDF_TARGET_NAME} as a Modbus serial master device, capable of reading and writing values from slave devices in a Modbus segment. + +- :example:`protocols/modbus/tcp/mb_tcp_slave` demonstrates the esp-modbus TCP slave stack port, allowing an external Modbus host to read and write device parameters via the Modbus protocol. + +- :example:`protocols/modbus/tcp/mb_tcp_master` demonstrates how to use the esp-modbus stack port on {IDF_TARGET_NAME} as a Modbus TCP master device, capable of reading and writing values from slave devices in a Modbus network. Please refer to the ``README.md`` documents of each specific example for details. @@ -30,5 +33,3 @@ Protocol References ------------------- - For the detailed protocol specifications, see `The Modbus Organization `_. - - diff --git a/docs/en/api-reference/protocols/mqtt.rst b/docs/en/api-reference/protocols/mqtt.rst index 7c5899de56c..b408c3bc2d8 100644 --- a/docs/en/api-reference/protocols/mqtt.rst +++ b/docs/en/api-reference/protocols/mqtt.rst @@ -19,16 +19,25 @@ Features Application Examples ---------------------- - - * :example:`protocols/mqtt/tcp`: MQTT over TCP, default port 1883 - * :example:`protocols/mqtt/ssl`: MQTT over TLS, default port 8883 - * :example:`protocols/mqtt/ssl_ds`: MQTT over TLS using digital signature peripheral for authentication, default port 8883 - * :example:`protocols/mqtt/ssl_mutual_auth`: MQTT over TLS using certificates for authentication, default port 8883 - * :example:`protocols/mqtt/ssl_psk`: MQTT over TLS using pre-shared keys for authentication, default port 8883 - * :example:`protocols/mqtt/ws`: MQTT over WebSocket, default port 80 - * :example:`protocols/mqtt/wss`: MQTT over WebSocket Secure, default port 443 - * :example:`protocols/mqtt5`: Uses ESP-MQTT library to connect to broker with MQTT v5.0 +-------------------- + + - :example:`protocols/mqtt/tcp` demonstrates how to implement MQTT communication over TCP (default port 1883). + + - :example:`protocols/mqtt/ssl` demonstrates how to use SSL transport to implement MQTT communication over TLS (default port 8883). + + - :example:`protocols/mqtt/ssl_ds` demonstrates how to use digital signature peripheral for authentication to implement MQTT communication over TLS (default port 8883). + + - :example:`protocols/mqtt/ssl_mutual_auth` demonstrates how to use certificates for authentication to implement MQTT communication (default port 8883). + + - :example:`protocols/mqtt/ssl_psk` demonstrates how to use pre-shared keys for authentication to implement MQTT communication over TLS (default port 8883). + + - :example:`protocols/mqtt/ws` demonstrates how to implement MQTT communication over WebSocket (default port 80). + + - :example:`protocols/mqtt/wss` demonstrates how to implement MQTT communication over WebSocket Secure (default port 443). + + - :example:`protocols/mqtt5` demonstrates how to use ESP-MQTT library to connect to broker with MQTT v5.0. + + - :example:`protocols/mqtt/custom_outbox` demonstrates how to customize the outbox in the ESP-MQTT library. MQTT Message Retransmission --------------------------- diff --git a/docs/zh_CN/api-guides/lwip.rst b/docs/zh_CN/api-guides/lwip.rst index 34e8b485fe2..4ebc5975531 100644 --- a/docs/zh_CN/api-guides/lwip.rst +++ b/docs/zh_CN/api-guides/lwip.rst @@ -31,9 +31,9 @@ ESP-IDF 间接支持以下常见的 lwIP 应用程序 API： lwIP 中的 DNS 服务器配置为全局配置，而非针对特定接口的配置。如需同时使用不同 DNS 服务器的多个网络接口，在从一个接口获取 DHCP 租约时，请注意避免意外覆盖另一个接口的 DNS 设置。 -- 简单网络时间协议 (SNTP)，由 :doc:`/api-reference/network/esp_netif` 功能间接支持，或通过 :component_file:`lwip/include/apps/esp_sntp.h` 中的函数直接支持。该函数还为 :component_file:`lwip/lwip/src/include/lwip/apps/sntp.h` 函数提供了线程安全的 API，请参阅 :ref:`system-time-sntp-sync`。 +- 简单网络时间协议 (SNTP)，由 :doc:`/api-reference/network/esp_netif` 功能间接支持，或通过 :component_file:`lwip/include/apps/esp_sntp.h` 中的函数直接支持。该函数还为 :component_file:`lwip/lwip/src/include/lwip/apps/sntp.h` 函数提供了线程安全的 API，请参阅 :ref:`system-time-sntp-sync`。有关详细信息，请见 :example:`protocols/sntp`。该示例演示了如何使用 LwIP SNTP 模块从互联网服务器获取时间、配置同步方法与时间间隔，并使用 SNTP-over-DHCP 模块检索时间。 - ICMP Ping，由 lwIP ping API 的变体支持，请参阅 :doc:`/api-reference/protocols/icmp_echo`。 -- ICMPv6 Ping，由 lwIP 的 ICMPv6 Echo API 支持，用于测试 IPv6 网络连接情况。有关详细信息，请参阅 :example:`protocols/sockets/icmpv6_ping`。 +- ICMPv6 Ping，由 lwIP 的 ICMPv6 Echo API 支持，用于测试 IPv6 网络连接情况。有关详细信息，请参阅 :example:`protocols/sockets/icmpv6_ping`。该示例演示了如何使用网络接口发现 IPv6 地址，创建原始 ICMPv6 套接字，向目标 IPv6 地址发送 ICMPv6 Echo 请求，并等待目标返回 Echo 回复。 - NetBIOS 查找，由标准的 lwIP API 支持，:example:`protocols/http_server/restful_server` 示例中提供了使用 NetBIOS 在局域网中查找主机的选项。 - mDNS 与 lwIP 的默认 mDNS 使用不同实现方式，请参阅 :doc:`/api-reference/protocols/mdns`。但启用 :ref:`CONFIG_LWIP_DNS_SUPPORT_MDNS_QUERIES` 设置项后，lwIP 可以使用 ``gethostbyname()`` 等标准 API 和 ``hostname.local`` 约定查找 mDNS 主机。 - lwIP 中的 PPP 实现可用于在 ESP-IDF 中创建 PPPoS（串行 PPP）接口。请参阅 :doc:`/api-reference/network/esp_netif` 组件文档，使用 :component_file:`esp_netif/include/esp_netif_defaults.h` 中定义的 ``ESP_NETIF_DEFAULT_PPP()`` 宏创建并配置 PPP 网络接口。:component_file:`esp_netif/include/esp_netif_ppp.h` 中提供了其他的运行时设置。PPPoS 接口通常用于与 NBIoT/GSM/LTE 调制解调器交互。`esp_modem `_ 仓库还支持更多应用层友好的 API，该仓库内部使用了上述 PPP lwIP 模块。 @@ -58,12 +58,19 @@ BSD 套接字的相关参考资料十分丰富，包括但不限于： 以下为 ESP-IDF 中使用 BSD 套接字 API 的部分示例： -- :example:`protocols/sockets/tcp_server` -- :example:`protocols/sockets/tcp_client` -- :example:`protocols/sockets/udp_server` -- :example:`protocols/sockets/udp_client` -- :example:`protocols/sockets/udp_multicast` -- :example:`protocols/http_request`：此简化示例使用 TCP 套接字发送 HTTP 请求，但更推荐使用 :doc:`/api-reference/protocols/esp_http_client` 发送 HTTP 请求 +- :example:`protocols/sockets/non_blocking` 演示了如何配置和运行一个支持 IPv4 和 IPv6 协议的非阻塞 TCP 客户端和服务器。 + +- :example:`protocols/sockets/tcp_server` 演示了如何创建一个 TCP 服务器，该服务器可以接受客户端的连接请求并接收数据。 + +- :example:`protocols/sockets/tcp_client` 演示了如何创建一个 TCP 客户端，该客户端使用预定义的 IP 地址和端口连接到服务器。 + +- :example:`protocols/sockets/tcp_client_multi_net` 演示了如何同时使用以太网和 Wi-Fi 接口连接，在每个接口上创建一个 TCP 客户端，并发送一个简单的 HTTP 请求和响应。 + +- :example:`protocols/sockets/udp_server` 演示了如何创建一个 UDP 服务器，该服务器可以接收客户端的连接请求和数据。 + +- :example:`protocols/sockets/udp_client` 演示了如何创建一个 UDP 客户端，该客户端使用预定义的 IP 地址和端口连接到服务器。 + +- :example:`protocols/sockets/udp_multicast` 演示了如何通过 BSD 风格的套接字接口使用 IPV4 和 IPV6 的 UDP 组播功能。 支持的函数 ^^^^^^^^^^^^^^^^^^^ diff --git a/docs/zh_CN/api-reference/network/esp_netif.rst b/docs/zh_CN/api-reference/network/esp_netif.rst index 00c0d6fe750..596ecdf4f1e 100644 --- a/docs/zh_CN/api-reference/network/esp_netif.rst +++ b/docs/zh_CN/api-reference/network/esp_netif.rst @@ -82,20 +82,20 @@ ESP-NETIF 组件使用了系统事件，典型的网络启动代码如下所示 初始化网络接口可能有些复杂，ESP-NETIF 提供了一些创建常见接口（例如 Wi-Fi 和以太网）的快捷方式。 -以下示例展示了默认接口的初始化过程： +请参考以下示例来了解如何初始化默认接口： -.. only:: SOC_WIFI_SUPPORTED +.. list:: - - Wi-Fi 站点：:example_file:`wifi/getting_started/station/main/station_example_main.c` + :SOC_WIFI_SUPPORTED: - :example:`wifi/getting_started/station` 演示了如何使用 station 功能将 {IDF_TARGET_NAME} 连接到 AP。 -- 以太网：:example_file:`ethernet/basic/main/ethernet_example_main.c` + :CONFIG_ESP_WIFI_SOFTAP_SUPPORT: - :example:`wifi/getting_started/softAP` 演示了如何使用 SoftAP 功能将 {IDF_TARGET_NAME} 配置为 AP。 -- L2 TAP: :example_file:`protocols/l2tap/main/l2tap_main.c` + - :example:`ethernet/basic` 演示了如何使用以太网驱动程序，将其添加到 `esp_netif`，并获取一个可 ping 的 IP 地址。 -.. only:: CONFIG_ESP_WIFI_SOFTAP_SUPPORT + - :example:`protocols/l2tap` 演示了如何使用 ESP-NETIF L2 TAP 接口访问数据链路层，以接收和传输帧，实现非 IP 协议，并使用特定的 EthTypes 回显以太网帧。 - - Wi-Fi 接入点：:example_file:`wifi/getting_started/softAP/main/softap_example_main.c` + - :example:`protocols/static_ip` 演示了如何将 Wi-Fi 配置为 station，包括设置静态 IP、子网掩码、网关和 DNS 服务器。 .. only:: SOC_WIFI_SUPPORTED diff --git a/docs/zh_CN/api-reference/protocols/icmp_echo.rst b/docs/zh_CN/api-reference/protocols/icmp_echo.rst index 87dea76943a..38bb987ac05 100644 --- a/docs/zh_CN/api-reference/protocols/icmp_echo.rst +++ b/docs/zh_CN/api-reference/protocols/icmp_echo.rst @@ -112,7 +112,7 @@ IoT 设备通常需要检查远程服务器是否可用。如果服务器离线 应用示例 ---------- -ICMP echo 示例： :example:`protocols/icmp_echo` +- :example:`protocols/icmp_echo` 演示了如何实现一个简单的 ping 命令行工具，使用 ICMP 回显请求数据包测试远程主机在 IP 网络上的可达性。 API 参考 -------------- diff --git a/docs/zh_CN/api-reference/protocols/modbus.rst b/docs/zh_CN/api-reference/protocols/modbus.rst index 3d88cbcfba8..11234ae4843 100644 --- a/docs/zh_CN/api-reference/protocols/modbus.rst +++ b/docs/zh_CN/api-reference/protocols/modbus.rst @@ -19,10 +19,13 @@ ESP-Modbus 以下示例分别介绍了 ESP-Modbus 库的串行端口、TCP 端口的从机和主机实现。 -- :example:`protocols/modbus/serial/mb_slave` -- :example:`protocols/modbus/serial/mb_master` -- :example:`protocols/modbus/tcp/mb_tcp_slave` -- :example:`protocols/modbus/tcp/mb_tcp_master` +- :example:`protocols/modbus/serial/mb_slave` 演示了如何使用 {IDF_TARGET_NAME} 作为 Modbus 串行从设备，通过 esp-modbus 栈，使外部 Modbus 主机能够使用 Modbus 协议读取和写入设备参数。 + +- :example:`protocols/modbus/serial/mb_master` 演示了如何在 {IDF_TARGET_NAME} 上使用 esp-modbus 栈端口作为 Modbus 串行主设备，读取和写入 Modbus 网络中从设备的值。 + +- :example:`protocols/modbus/tcp/mb_tcp_slave` 演示了 esp-modbus TCP 从设备栈端口，允许外部 Modbus 主机通过 Modbus 协议读取和写入设备参数。 + +- :example:`protocols/modbus/tcp/mb_tcp_master` 演示了如何在 {IDF_TARGET_NAME} 上使用 esp-modbus 栈端口作为 Modbus TCP 主设备，读取和写入 Modbus 网络中从设备的值。 详情请参阅具体示例的 ``README.md`` 。 diff --git a/docs/zh_CN/api-reference/protocols/mqtt.rst b/docs/zh_CN/api-reference/protocols/mqtt.rst index 9365dfe850a..7ad56ec21e2 100644 --- a/docs/zh_CN/api-reference/protocols/mqtt.rst +++ b/docs/zh_CN/api-reference/protocols/mqtt.rst @@ -21,14 +21,23 @@ ESP-MQTT 是 `MQTT `__ 协议客户端的实现，MQTT 是一 应用示例 ------------------- - * :example:`protocols/mqtt/tcp`：基于 TCP 的 MQTT，默认端口 1883 - * :example:`protocols/mqtt/ssl`：基于 TLS 的 MQTT，默认端口 8883 - * :example:`protocols/mqtt/ssl_ds`：基于 TLS 的 MQTT，使用数字签名外设进行身份验证，默认端口 8883 - * :example:`protocols/mqtt/ssl_mutual_auth`：基于 TLS 的 MQTT，使用证书进行身份验证，默认端口 8883 - * :example:`protocols/mqtt/ssl_psk`：基于 TLS 的 MQTT，使用预共享密钥进行身份验证，默认端口 8883 - * :example:`protocols/mqtt/ws`：基于 WebSocket 的 MQTT，默认端口 80 - * :example:`protocols/mqtt/wss`：基于 WebSocket Secure 的 MQTT，默认端口 443 - * :example:`protocols/mqtt5`: 使用 ESP-MQTT 库连接 MQTT v5.0 的服务器 + - :example:`protocols/mqtt/tcp` 演示了如何通过 TCP 实现 MQTT 通信（默认端口 1883）。 + + - :example:`protocols/mqtt/ssl` 演示了如何使用 SSL 传输来实现基于 TLS 的 MQTT 通信（默认端口 8883）。 + + - :example:`protocols/mqtt/ssl_ds` 演示了如何使用数字签名外设进行身份验证，以实现基于 TLS 的 MQTT 通信（默认端口 8883）。 + + - :example:`protocols/mqtt/ssl_mutual_auth` 演示了如何使用证书进行身份验证实现 MQTT 通信（默认端口 8883）。 + + - :example:`protocols/mqtt/ssl_psk` 演示了如何使用预共享密钥进行身份验证，以实现基于 TLS 的 MQTT 通信（默认端口 8883）。 + + - :example:`protocols/mqtt/ws` 演示了如何通过 WebSocket 实现 MQTT 通信（默认端口 80）。 + + - :example:`protocols/mqtt/wss` 演示了如何通过 WebSocket Secure 实现 MQTT 通信（默认端口 443）。 + + - :example:`protocols/mqtt5` 演示了如何使用 ESP-MQTT 库通过 MQTT v5.0 连接到代理。 + + - :example:`protocols/mqtt/custom_outbox` 演示了如何自定义 ESP-MQTT 库中的 outbox。 MQTT 消息重传 -------------------------- From e005b7c97be32e7accb4290f755306363925839e Mon Sep 17 00:00:00 2001 From: Roland Dobai Date: Tue, 1 Oct 2024 16:02:19 +0200 Subject: [PATCH 142/472] fix(tools): Update chip support status of ESP32-C5 and ESP32-C61 --- README.md | 23 ++++++++++++----------- README_CN.md | 23 ++++++++++++----------- 2 files changed, 24 insertions(+), 22 deletions(-) diff --git a/README.md b/README.md index ce807d91da8..d90e7e0eee9 100644 --- a/README.md +++ b/README.md @@ -15,17 +15,18 @@ ESP-IDF is the development framework for Espressif SoCs supported on Windows, Li The following table shows ESP-IDF support of Espressif SoCs where ![alt text][preview] and ![alt text][supported] denote preview status and support, respectively. The preview support is usually limited in time and intended for beta versions of chips. Please use an ESP-IDF release where the desired SoC is already supported. -|Chip | v5.0 | v5.1 | v5.2 | v5.3 | | -|:----------- | :---------------------:| :--------------------: | :--------------------: | :--------------------: | :--------------------------------------------------------- | -|ESP32 | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | | -|ESP32-S2 | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | | -|ESP32-C3 | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | | -|ESP32-S3 | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | [Announcement](https://www.espressif.com/en/news/ESP32_S3) | -|ESP32-C2 | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | [Announcement](https://www.espressif.com/en/news/ESP32-C2) | -|ESP32-C6 | | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | [Announcement](https://www.espressif.com/en/news/ESP32_C6) | -|ESP32-H2 | | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | [Announcement](https://www.espressif.com/en/news/ESP32_H2) | -|ESP32-P4 | | | | ![alt text][supported] | [Announcement](https://www.espressif.com/en/news/ESP32-P4) | -|ESP32-C5 | | | | ![alt text][preview] | [Announcement](https://www.espressif.com/en/news/ESP32-C5) | +|Chip | v5.0 | v5.1 | v5.2 | v5.3 | v5.4 | | +|:----------- | :---------------------:| :--------------------: | :--------------------: | :--------------------: | :--------------------: |:------------------------------------------------------------------- | +|ESP32 | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | | +|ESP32-S2 | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | | +|ESP32-C3 | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | | +|ESP32-S3 | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] |[Announcement](https://www.espressif.com/en/news/ESP32_S3) | +|ESP32-C2 | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] |[Announcement](https://www.espressif.com/en/news/ESP32-C2) | +|ESP32-C6 | | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] |[Announcement](https://www.espressif.com/en/news/ESP32_C6) | +|ESP32-H2 | | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] |[Announcement](https://www.espressif.com/en/news/ESP32_H2) | +|ESP32-P4 | | | | ![alt text][supported] | ![alt text][supported] |[Announcement](https://www.espressif.com/en/news/ESP32-P4) | +|ESP32-C5 | | | | | ![alt text][preview] |[Announcement](https://www.espressif.com/en/news/ESP32-C5) | +|ESP32-C61 | | | | | ![alt text][preview] |[Announcement](https://www.espressif.com/en/products/socs/esp32-c61) | [supported]: https://img.shields.io/badge/-supported-green "supported" [preview]: https://img.shields.io/badge/-preview-orange "preview" diff --git a/README_CN.md b/README_CN.md index e8f21600d1d..6aeb55a5ac7 100644 --- a/README_CN.md +++ b/README_CN.md @@ -15,17 +15,18 @@ ESP-IDF 是乐鑫官方推出的物联网开发框架，支持 Windows、Linux 下表总结了乐鑫芯片在 ESP-IDF 各版本中的支持状态，其中 ![alt text][supported] 代表已支持，![alt text][preview] 代表目前处于预览支持状态。预览支持状态通常有时间限制，而且仅适用于测试版芯片。请确保使用与芯片相匹配的 ESP-IDF 版本。 -|芯片 | v5.0 | v5.1 | v5.2 | v5.3 | | -|:----------- | :---------------------:| :--------------------: | :--------------------: | :--------------------: | :-------------------------------------------------------------- | -|ESP32 | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | | -|ESP32-S2 | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | | -|ESP32-C3 | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | | -|ESP32-S3 | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | [芯片发布公告](https://www.espressif.com/zh-hans/news/ESP32_S3) | -|ESP32-C2 | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | [芯片发布公告](https://www.espressif.com/zh-hans/news/ESP32-C2) | -|ESP32-C6 | | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | [芯片发布公告](https://www.espressif.com/zh-hans/news/ESP32_C6) | -|ESP32-H2 | | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | [芯片发布公告](https://www.espressif.com/zh-hans/news/ESP32_H2) | -|ESP32-P4 | | | | ![alt text][supported] | [芯片发布公告](https://www.espressif.com/zh-hans/news/ESP32-P4) | -|ESP32-C5 | | | | ![alt text][preview] | [芯片发布公告](https://www.espressif.com/zh-hans/news/ESP32-C5) | +|芯片 | v5.0 | v5.1 | v5.2 | v5.3 | v5.4 | | +|:----------- | :---------------------:| :--------------------: | :--------------------: | :--------------------: | :--------------------: | :------------------------------------------------------------------------ | +|ESP32 | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | | +|ESP32-S2 | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | | +|ESP32-C3 | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | | +|ESP32-S3 | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | [芯片发布公告](https://www.espressif.com/zh-hans/news/ESP32_S3) | +|ESP32-C2 | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | [芯片发布公告](https://www.espressif.com/zh-hans/news/ESP32-C2) | +|ESP32-C6 | | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | [芯片发布公告](https://www.espressif.com/zh-hans/news/ESP32_C6) | +|ESP32-H2 | | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | [芯片发布公告](https://www.espressif.com/zh-hans/news/ESP32_H2) | +|ESP32-P4 | | | | ![alt text][supported] | ![alt text][supported] | [芯片发布公告](https://www.espressif.com/zh-hans/news/ESP32-P4) | +|ESP32-C5 | | | | | ![alt text][preview] | [芯片发布公告](https://www.espressif.com/zh-hans/news/ESP32-C5) | +|ESP32-C61 | | | | | ![alt text][preview] | [芯片发布公告](https://www.espressif.com/zh-hans/products/socs/esp32-c61) | [supported]: https://img.shields.io/badge/-%E6%94%AF%E6%8C%81-green "supported" [preview]: https://img.shields.io/badge/-%E9%A2%84%E8%A7%88-orange "preview" From 0a354e09ef58d898c5652f38e09547d6c3d8d707 Mon Sep 17 00:00:00 2001 From: Roland Dobai Date: Fri, 11 Oct 2024 10:40:52 +0200 Subject: [PATCH 143/472] Tools: Add new ROM binary release including for ESP32-C5 --- tools/idf_py_actions/roms.json | 7 +++++++ tools/tools.json | 8 ++++---- 2 files changed, 11 insertions(+), 4 deletions(-) diff --git a/tools/idf_py_actions/roms.json b/tools/idf_py_actions/roms.json index 40a4ff930a0..01524dc9cf1 100644 --- a/tools/idf_py_actions/roms.json +++ b/tools/idf_py_actions/roms.json @@ -44,6 +44,13 @@ "build_date_str": "Feb 7 2021" } ], + "esp32c5": [ + { + "rev": 0, + "build_date_str_addr": "0x4004b3c4", + "build_date_str": "Mar 29 2024" + } + ], "esp32c6": [ { "rev": 0, diff --git a/tools/tools.json b/tools/tools.json index 54b3037af73..dc3ac44fd5c 100644 --- a/tools/tools.json +++ b/tools/tools.json @@ -863,11 +863,11 @@ "versions": [ { "any": { - "sha256": "a26609b415710f0163d785850c769752717004059c129c472e9a0cbd54e0422c", - "size": 3258247, - "url": "https://github.com/espressif/esp-rom-elfs/releases/download/20240305/esp-rom-elfs-20240305.tar.gz" + "sha256": "921f000164a421c7628fbfee55b173384aafaa51883adc65cd27bf9b0af9e9a9", + "size": 3540038, + "url": "https://github.com/espressif/esp-rom-elfs/releases/download/20241011/esp-rom-elfs-20241011.tar.gz" }, - "name": "20240305", + "name": "20241011", "status": "recommended" } ] From 3683e4c18b79c42e7951375cb41d9c88773eac1e Mon Sep 17 00:00:00 2001 From: morris Date: Mon, 14 Oct 2024 14:34:57 +0800 Subject: [PATCH 144/472] fix(hal): reenable gnu static analyzer --- components/hal/CMakeLists.txt | 5 ----- 1 file changed, 5 deletions(-) diff --git a/components/hal/CMakeLists.txt b/components/hal/CMakeLists.txt index 35ca479f78f..1eae44dfffd 100644 --- a/components/hal/CMakeLists.txt +++ b/components/hal/CMakeLists.txt @@ -330,8 +330,3 @@ if(CONFIG_HAL_DEFAULT_ASSERTION_LEVEL EQUAL 1) elseif(CONFIG_HAL_DEFAULT_ASSERTION_LEVEL EQUAL 2) target_link_libraries(${COMPONENT_LIB} INTERFACE "-u __assert_func") endif() - -if((CONFIG_IDF_TARGET_ESP32H2 OR CONFIG_IDF_TARGET_ESP32S2 OR CONFIG_IDF_TARGET_ESP32S3) AND - CONFIG_COMPILER_STATIC_ANALYZER AND CMAKE_C_COMPILER_ID STREQUAL "GNU") # TODO IDF-10234 - target_compile_options(${COMPONENT_LIB} PRIVATE "-fno-analyzer") -endif() From 0682be88c94c0b88a5ac2cbfcdf79557bdb40064 Mon Sep 17 00:00:00 2001 From: zwx Date: Mon, 14 Oct 2024 15:34:41 +0800 Subject: [PATCH 145/472] fix(esp_phy): fix C5 coex phy init issue --- components/esp_phy/lib | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/components/esp_phy/lib b/components/esp_phy/lib index 6bd4ea98abf..8fd02ff780e 160000 --- a/components/esp_phy/lib +++ b/components/esp_phy/lib @@ -1 +1 @@ -Subproject commit 6bd4ea98abf865ee8ee3598f58d7260bf06ff03e +Subproject commit 8fd02ff780e977e76e7ed78619629c8344f0fc50 From 5e6e1ba49abe768423b9cd9f8ac6ef3121e625ba Mon Sep 17 00:00:00 2001 From: "wangtao@espressif.com" Date: Mon, 14 Oct 2024 16:39:47 +0800 Subject: [PATCH 146/472] fix(wifi): fix esp32eco4 softap h2e issue --- components/esp_rom/esp32c2/ld/esp32c2.rom.eco4.ld | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/components/esp_rom/esp32c2/ld/esp32c2.rom.eco4.ld b/components/esp_rom/esp32c2/ld/esp32c2.rom.eco4.ld index 22130d601e4..c0a53597386 100644 --- a/components/esp_rom/esp32c2/ld/esp32c2.rom.eco4.ld +++ b/components/esp_rom/esp32c2/ld/esp32c2.rom.eco4.ld @@ -1201,7 +1201,7 @@ ieee80211_send_mgmt = 0x40002038; //ieee80211_auth_construct = 0x4000203c; ieee80211_deauth_construct = 0x40002040; ieee80211_disassoc_construct = 0x40002044; -ieee80211_add_xrates = 0x40002058; +//ieee80211_add_xrates = 0x40002058; //ieee80211_assoc_req_construct = 0x40002060; ieee80211_assoc_resp_construct = 0x40002064; ieee80211_timer_process = 0x4000208c; From f333131063a6369ac3446dca9cf991be67e787a8 Mon Sep 17 00:00:00 2001 From: Roman Leonov Date: Fri, 20 Sep 2024 13:33:28 +0200 Subject: [PATCH 147/472] feat(hub): Added notification when hubs support disabled --- components/usb/ext_hub.c | 2 +- components/usb/hub.c | 35 +++++++++++++++++++++++++--- components/usb/private_include/hub.h | 4 +++- components/usb/usb_host.c | 10 ++++---- 4 files changed, 41 insertions(+), 10 deletions(-) diff --git a/components/usb/ext_hub.c b/components/usb/ext_hub.c index 1c821677f45..8b02f4191f1 100644 --- a/components/usb/ext_hub.c +++ b/components/usb/ext_hub.c @@ -528,7 +528,7 @@ static esp_err_t device_alloc(device_config_t *config, ext_hub_dev_t **ext_hub_d usb_device_info_t dev_info; ESP_ERROR_CHECK(usbh_dev_get_info(config->dev_hdl, &dev_info)); if (dev_info.parent.dev_hdl) { - ESP_LOGW(EXT_HUB_TAG, "Multiple Hubs not supported, use menuconfig to enable feature"); + ESP_LOGW(EXT_HUB_TAG, "Multiple Hubs support disabled, Hub device was not initialized"); ret = ESP_ERR_NOT_SUPPORTED; goto fail; } diff --git a/components/usb/hub.c b/components/usb/hub.c index 2d328bcf39a..e39e741d694 100644 --- a/components/usb/hub.c +++ b/components/usb/hub.c @@ -778,14 +778,35 @@ esp_err_t hub_port_disable(usb_device_handle_t parent_dev_hdl, uint8_t parent_po return ret; } -#if ENABLE_USB_HUBS esp_err_t hub_notify_new_dev(uint8_t dev_addr) { HUB_DRIVER_ENTER_CRITICAL(); HUB_DRIVER_CHECK_FROM_CRIT(p_hub_driver_obj != NULL, ESP_ERR_INVALID_STATE); HUB_DRIVER_EXIT_CRITICAL(); - return ext_hub_new_dev(dev_addr); + esp_err_t ret; +#if ENABLE_USB_HUBS + ret = ext_hub_new_dev(dev_addr); +#else + // Verify the device descriptor and if the bDeviceClass is a Hub class, + // show the warning message, that Hub support feature is not enabled + usb_device_handle_t dev_hdl = NULL; + const usb_device_desc_t *device_desc = NULL; + // Open device + if (usbh_devs_open(dev_addr, &dev_hdl) == ESP_OK) { + // Get Device Descriptor + if (usbh_dev_get_desc(dev_hdl, &device_desc) == ESP_OK) { + if (device_desc->bDeviceClass == USB_CLASS_HUB) { + ESP_LOGW(HUB_DRIVER_TAG, "External Hubs support disabled, Hub device was not initialized"); + } + } + // Close device + usbh_dev_close(dev_hdl); + } + // Logic should not stop the flow, so no error to return + ret = ESP_OK; +#endif // ENABLE_USB_HUBS + return ret; } esp_err_t hub_notify_dev_gone(uint8_t dev_addr) @@ -794,9 +815,17 @@ esp_err_t hub_notify_dev_gone(uint8_t dev_addr) HUB_DRIVER_CHECK_FROM_CRIT(p_hub_driver_obj != NULL, ESP_ERR_INVALID_STATE); HUB_DRIVER_EXIT_CRITICAL(); - return ext_hub_dev_gone(dev_addr); + esp_err_t ret; +#if ENABLE_USB_HUBS + ret = ext_hub_dev_gone(dev_addr); +#else + // Nothing to do, while Hubs support is not enabled + ret = ESP_OK; +#endif // ENABLE_USB_HUBS + return ret; } +#if (ENABLE_USB_HUBS) esp_err_t hub_notify_all_free(void) { HUB_DRIVER_ENTER_CRITICAL(); diff --git a/components/usb/private_include/hub.h b/components/usb/private_include/hub.h index e3efaac9bf8..f563a56f283 100644 --- a/components/usb/private_include/hub.h +++ b/components/usb/private_include/hub.h @@ -191,13 +191,13 @@ esp_err_t hub_port_active(usb_device_handle_t parent_dev_hdl, uint8_t parent_por */ esp_err_t hub_port_disable(usb_device_handle_t parent_dev_hdl, uint8_t parent_port_num); -#if ENABLE_USB_HUBS /** * @brief Notify Hub driver that new device has been attached * * If device is has a HUB class, then it will be added as External Hub to Hub Driver. * * @note This function should only be called from the Host Library task + * @note If the Hub support feature is disabled and device has a Hub class, only the warning message will be shown. * * @param[in] dev_addr Device bus address * @@ -213,6 +213,7 @@ esp_err_t hub_notify_new_dev(uint8_t dev_addr); * If the device was an External Hub, then it will be removed from the Hub Driver. * * @note This function should only be called from the Host Library task + * @note If the Hub support feature is disabled, no additional logic requires here. * * @param[in] dev_addr Device bus address * @@ -222,6 +223,7 @@ esp_err_t hub_notify_new_dev(uint8_t dev_addr); */ esp_err_t hub_notify_dev_gone(uint8_t dev_addr); +#if ENABLE_USB_HUBS /** * @brief Notify Hub driver that all devices should be freed * diff --git a/components/usb/usb_host.c b/components/usb/usb_host.c index bc41bab9089..9e5f3feea36 100644 --- a/components/usb/usb_host.c +++ b/components/usb/usb_host.c @@ -309,21 +309,21 @@ static void usbh_event_callback(usbh_event_data_t *event_data, void *arg) break; } case USBH_EVENT_NEW_DEV: { + // Internal client + hub_notify_new_dev(event_data->new_dev_data.dev_addr); + // External clients // Prepare a NEW_DEV client event message, the send it to all clients usb_host_client_event_msg_t event_msg = { .event = USB_HOST_CLIENT_EVENT_NEW_DEV, .new_dev.address = event_data->new_dev_data.dev_addr, }; send_event_msg_to_clients(&event_msg, true, 0); -#if ENABLE_USB_HUBS - hub_notify_new_dev(event_data->new_dev_data.dev_addr); -#endif // ENABLE_USB_HUBS break; } case USBH_EVENT_DEV_GONE: { -#if ENABLE_USB_HUBS + // Internal client hub_notify_dev_gone(event_data->new_dev_data.dev_addr); -#endif // ENABLE_USB_HUBS + // External clients // Prepare event msg, send only to clients that have opened the device usb_host_client_event_msg_t event_msg = { .event = USB_HOST_CLIENT_EVENT_DEV_GONE, From 30dbe31ef67ead76f2c72813812007c2f5ba34ce Mon Sep 17 00:00:00 2001 From: renpeiying Date: Mon, 14 Oct 2024 15:24:03 +0800 Subject: [PATCH 148/472] docs: Update CN translation for fatfs.rst --- .../api-guides/file-system-considerations.rst | 2 +- docs/en/api-reference/storage/fatfs.rst | 16 +++++---- docs/zh_CN/api-reference/storage/fatfs.rst | 33 +++++++++++++++++-- 3 files changed, 40 insertions(+), 11 deletions(-) diff --git a/docs/en/api-guides/file-system-considerations.rst b/docs/en/api-guides/file-system-considerations.rst index ac90b678320..bef83ad7765 100644 --- a/docs/en/api-guides/file-system-considerations.rst +++ b/docs/en/api-guides/file-system-considerations.rst @@ -50,7 +50,7 @@ The most significant properties and features of above-mentioned file systems are - Integrated - Integrated * - Minimum partition size - - * 8 sectors with wear levelling on (4 FATFS sectors + 4 WL sectors with WL sector size=4096B) + - * 8 sectors with wear levelling on (4 FATFS sectors + 4 WL sectors with WL sector size = 4096B) * plus 4 sectors at least * real number given by WL configuration (Safe, Perf) - * 6 logical blocks diff --git a/docs/en/api-reference/storage/fatfs.rst b/docs/en/api-reference/storage/fatfs.rst index 3777c4f17ca..4c6520eb273 100644 --- a/docs/en/api-reference/storage/fatfs.rst +++ b/docs/en/api-reference/storage/fatfs.rst @@ -166,20 +166,22 @@ The FATFS component supports FAT12, FAT16, and FAT32 file system types. The file * For a partition with wear leveling enabled, 4 sectors will be reserved for wear-leveling operations, and 4 sectors will be used by the FATFS (1 reserved sector, 1 FAT sector, 1 root directory sector and 1 data sector). * Increasing the partition size will allocate additional data sectors, allowing for more storage space. * For partition sizes less than 528 KB, 1 root directory sector will be allocated; for larger partitions, 4 root directory sectors will be used. -* By default, two FAT sectors are created, increasing the partition size by one sector to accommodate the extra FAT sector. To enable a single FAT sector, configure the `use_one_fat` option in `struct esp_vfs_fat_mount_config_t` (see/vfs/esp_vfs_fat.h). Enabling this option allows the minimum partition size to be reduced to 32 KB. +* By default, two FAT sectors are created, increasing the partition size by one sector to accommodate the extra FAT sector. To enable a single FAT sector, configure the `use_one_fat` option in `struct esp_vfs_fat_mount_config_t` (see :component_file:`fatfs/vfs/esp_vfs_fat.h`). Enabling this option allows the minimum partition size to be reduced to 32 KB. * The general formula for calculating the partition size for a wear-leveled partition is:: partition_size = Wear-levelling sectors * FLASH_SEC_SIZE + FATFS partition sectors * FAT_SEC_SIZE - Where, - - Wear-leveling sectors are fixed at 4, - - FLASH_SEC_SIZE is 4096 bytes, - - FATFS partition sectors include: 1 reserved sector + FAT sectors + root directory sectors + data sectors, - - FAT_SEC_SIZE can be either 512 bytes or 4096 bytes, depending on the configuration. + Where: + + - Wear-leveling sectors are fixed at 4 + - FLASH_SEC_SIZE is 4096 bytes + - FATFS partition sectors include: 1 reserved sector + FAT sectors + root directory sectors + data sectors + - FAT_SEC_SIZE can be either 512 bytes or 4096 bytes, depending on the configuration * For read-only partitions without wear leveling enabled and a sector size of 512 bytes, the minimum partition size can be reduced to as low as 2 KB. -Please refer :doc:`File System Considerations <../../api-guides/file-system-considerations>` for further details . +Please refer :doc:`File System Considerations <../../api-guides/file-system-considerations>` for further details. + High-level API Reference ------------------------ diff --git a/docs/zh_CN/api-reference/storage/fatfs.rst b/docs/zh_CN/api-reference/storage/fatfs.rst index 65f281bd790..ef34512814e 100644 --- a/docs/zh_CN/api-reference/storage/fatfs.rst +++ b/docs/zh_CN/api-reference/storage/fatfs.rst @@ -99,7 +99,7 @@ FatFs 分区生成器 该生成器可以在主机上创建文件系统镜像，并用指定的主机文件夹内容对其进行填充。 -该脚本是建立在分区生成器的基础上 (:component_file:`fatfsgen.py`)，目前除了可以生成分区外，也可以初始化磨损均衡。 +该脚本是建立在分区生成器的基础上 (:component_file:`fatfsgen.py`)，目前除了可以生成分区外，也可以初始化损耗均衡。 目前的最新版本支持短文件名、长文件名、FAT12 和 FAT16。长文件名的上限是 255 个字符，文件名中可以包含多个 ``.`` 字符以及其他字符，如 ``+``、``,``、``;``、``=``、``[`` and ``]`` 等。 @@ -112,13 +112,13 @@ FatFs 分区生成器 fatfs_create_spiflash_image( [FLASH_IN_PROJECT]) -如果不希望在生成分区时使用磨损均衡，可以使用 ``fatfs_create_rawflash_image``:: +如果不希望在生成分区时使用损耗均衡，可以使用 ``fatfs_create_rawflash_image``:: fatfs_create_rawflash_image( [FLASH_IN_PROJECT]) ``fatfs_create_spiflash_image`` 以及 ``fatfs_create_rawflash_image`` 必须从项目的 CMakeLists.txt 中调用。 -如果决定使用 ``fatfs_create_rawflash_image`` （不支持磨损均衡），请注意它仅支持在设备中以只读模式安装。 +如果决定使用 ``fatfs_create_rawflash_image`` （不支持损耗均衡），请注意它仅支持在设备中以只读模式安装。 该函数的参数如下： @@ -156,6 +156,33 @@ FatFs 分区分析器 生成文件夹结构之前，参数 --verbose 将根据 FatFs 镜像的引导扇区在终端打印详细信息。 + +FATFS 最小分区大小及限制 +------------------------ + +FATFS 组件支持 FAT12、FAT16 和 FAT32 文件系统类型。文件系统类型取决于卷上簇的数量（簇数通过数据扇区数量除以每簇包含的扇区数计算得出）。最小分区大小由分配给 FAT 表、根目录和数据簇的扇区数量决定。 + +* 对于 4096 字节的扇区，启用损耗均衡的 FAT 分区大小最小支持 32 KB。对于 512 字节的扇区，最小分区大小取决于损耗均衡的配置：性能模式下，最小支持 20 KB，安全模式下最小支持 28 KB（需要额外的 2 个扇区）。 +* 启用了损耗均衡的分区会预留 4 个扇区用于损耗均衡操作。此外，FATFS 本身也会使用 4 个扇区，分别为 1 个保留扇区、1 个 FAT 扇区、1 个根目录扇区和 1 个数据扇区。 +* 增加分区大小将分配更多的数据扇区，提供更大的存储空间。 +* 对小于 528 KB 的分区，将分配 1 个根目录扇区；对于更大的分区，将分配 4 个根目录扇区。 +* 默认会创建两个 FAT 扇区，因此分区大小会增加一个扇区来容纳这个额外的 FAT 扇区。如要启用单个 FAT 扇区，可以在 `struct esp_vfs_fat_mount_config_t` 中（参见 :component_file:`fatfs/vfs/esp_vfs_fat.h`）设置 `use_one_fat` 选项。启用此选项后，最小分区大小可减少至 32 KB。 +* 计算损耗均衡分区大小的一般公式为:: + + partition_size = 损耗均衡扇区数 * FLASH_SEC_SIZE + FATFS 分区扇区数量 * FAT_SEC_SIZE + + 其中： + + - 损耗均衡扇区数固定为 4 个 + - FLASH_SEC_SIZE 为 4096 字节 + - FATFS 分区扇区包括：1 个保留扇区 + FAT 扇区 + 根目录扇区 + 数据扇区 + - FAT_SEC_SIZE 根据不同的配置，可以是 512 字节或 4096 字节 + +* 对于未启用损耗均衡、扇区大小为 512 字节的只读分区，最小分区大小可减少至 2 KB。 + +更多详情请参考 :doc:`文件系统注意事项 <../../api-guides/file-system-considerations>`。 + + 高级 API 参考 ------------------------ From 42677a155648082b21dc1b86d44ed7666ffdcdbb Mon Sep 17 00:00:00 2001 From: Rahul Tank Date: Mon, 14 Oct 2024 20:49:33 +0530 Subject: [PATCH 149/472] fix(nimble): Adjust Data len time in case 5.0 support is not present --- components/bt/host/nimble/nimble | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/components/bt/host/nimble/nimble b/components/bt/host/nimble/nimble index 24ff17de7c0..32b2124f542 160000 --- a/components/bt/host/nimble/nimble +++ b/components/bt/host/nimble/nimble @@ -1 +1 @@ -Subproject commit 24ff17de7c07d53f2db2940052c52bfc48f8414c +Subproject commit 32b2124f54238e70ecd4c72a753698babdd939f7 From 64e0fc7a5ad5f32fc85443d3ad5449ee279330db Mon Sep 17 00:00:00 2001 From: Marius Vikhammer Date: Thu, 10 Oct 2024 11:10:51 +0800 Subject: [PATCH 150/472] fix(system): rename __VA_NARG__ macro __VA_NARG__ is copied from a forum post and is a pretty common implementation with a high chance of causing naming collision Added ESP_ namespace to avoid this. --- components/esp_common/include/esp_macros.h | 31 ++++--------------- .../test_apps/esp_common/main/CMakeLists.txt | 2 +- .../esp_common/main/test_esp_macro.c | 21 +++++++++++++ .../include/esp_private/esp_regdma.h | 4 +-- .../release-5.x/5.4/system.rst | 5 +++ .../release-5.x/5.4/system.rst | 5 +++ tools/idf_py_actions/hints.yml | 3 ++ 7 files changed, 43 insertions(+), 28 deletions(-) create mode 100644 components/esp_common/test_apps/esp_common/main/test_esp_macro.c diff --git a/components/esp_common/include/esp_macros.h b/components/esp_common/include/esp_macros.h index 183c947a44f..0893878e7eb 100644 --- a/components/esp_common/include/esp_macros.h +++ b/components/esp_common/include/esp_macros.h @@ -50,15 +50,15 @@ extern "C" { /* Count number of arguments of __VA_ARGS__ * - reference https://groups.google.com/forum/#!topic/comp.std.c/d-6Mj5Lko_s * - __GET_NTH_ARG__() takes args >= N (64) but only expand to Nth one (64th) - * - __RSEQ_N__() is reverse sequential to N to add padding to have Nth + * - ESP_RSEQ_N() is reverse sequential to N to add padding to have Nth * position is the same as the number of arguments * - ##__VA_ARGS__ is used to deal with 0 parameter (swallows comma) */ -#ifndef __VA_NARG__ -# define __VA_NARG__(...) __NARG__(_0, ##__VA_ARGS__, __RSEQ_N__()) +#ifndef ESP_VA_NARG +# define ESP_VA_NARG(...) ESP_NARG(_0, ##__VA_ARGS__, ESP_RSEQ_N()) -# define __NARG__(...) __GET_NTH_ARG__(__VA_ARGS__) -# define __GET_NTH_ARG__( \ +# define ESP_NARG(...) ESP_GET_NTH_ARG(__VA_ARGS__) +# define ESP_GET_NTH_ARG( \ _01,_02,_03,_04,_05,_06,_07,_08,_09,_10, \ _11,_12,_13,_14,_15,_16,_17,_18,_19,_20, \ _21,_22,_23,_24,_25,_26,_27,_28,_29,_30, \ @@ -66,7 +66,7 @@ extern "C" { _41,_42,_43,_44,_45,_46,_47,_48,_49,_50, \ _51,_52,_53,_54,_55,_56,_57,_58,_59,_60, \ _61,_62,_63,N,...) N -# define __RSEQ_N__() \ +# define ESP_RSEQ_N() \ 62,61,60, \ 59,58,57,56,55,54,53,52,51,50, \ 49,48,47,46,45,44,43,42,41,40, \ @@ -80,25 +80,6 @@ extern "C" { #define ESP_UNUSED(x) ((void)(x)) #endif -/* test macros */ -#define foo_args(...) 1 -#define foo_no_args() 2 -#if defined(__cplusplus) && (__cplusplus > 201703L) -#define foo(...) CHOOSE_MACRO_VA_ARG(foo_args, foo_no_args __VA_OPT__(,) __VA_ARGS__)(__VA_ARGS__) -#else -#define foo(...) CHOOSE_MACRO_VA_ARG(foo_args, foo_no_args, ##__VA_ARGS__)(__VA_ARGS__) -#endif - -ESP_STATIC_ASSERT(foo() == 2, "CHOOSE_MACRO_VA_ARG() result does not match for 0 arguments"); -ESP_STATIC_ASSERT(foo(42) == 1, "CHOOSE_MACRO_VA_ARG() result does not match for 1 argument"); -#if defined(__cplusplus) && (__cplusplus > 201703L) -ESP_STATIC_ASSERT(foo(42, 87) == 1, "CHOOSE_MACRO_VA_ARG() result does not match for n arguments"); -#endif - -#undef foo -#undef foo_args -#undef foo_no_args - #define ESP_INFINITE_LOOP() \ do { \ ESP_COMPILER_DIAGNOSTIC_PUSH_IGNORE("-Wanalyzer-infinite-loop") \ diff --git a/components/esp_common/test_apps/esp_common/main/CMakeLists.txt b/components/esp_common/test_apps/esp_common/main/CMakeLists.txt index d1e953e6382..f45ce0708cd 100644 --- a/components/esp_common/test_apps/esp_common/main/CMakeLists.txt +++ b/components/esp_common/test_apps/esp_common/main/CMakeLists.txt @@ -1,4 +1,4 @@ -idf_component_register(SRCS "test_app_main.c" "test_attr.c" +idf_component_register(SRCS "test_app_main.c" "test_attr.c" "test_esp_macro.c" INCLUDE_DIRS "." PRIV_REQUIRES unity esp_mm esp_psram WHOLE_ARCHIVE) diff --git a/components/esp_common/test_apps/esp_common/main/test_esp_macro.c b/components/esp_common/test_apps/esp_common/main/test_esp_macro.c new file mode 100644 index 00000000000..334fa980672 --- /dev/null +++ b/components/esp_common/test_apps/esp_common/main/test_esp_macro.c @@ -0,0 +1,21 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Unlicense OR CC0-1.0 + */ +#include "esp_macros.h" + +/* test macros */ +#define foo_args(...) 1 +#define foo_no_args() 2 +#if defined(__cplusplus) && (__cplusplus > 201703L) +#define foo(...) CHOOSE_MACRO_VA_ARG(foo_args, foo_no_args __VA_OPT__(,) __VA_ARGS__)(__VA_ARGS__) +#else +#define foo(...) CHOOSE_MACRO_VA_ARG(foo_args, foo_no_args, ##__VA_ARGS__)(__VA_ARGS__) +#endif + +ESP_STATIC_ASSERT(foo() == 2, "CHOOSE_MACRO_VA_ARG() result does not match for 0 arguments"); +ESP_STATIC_ASSERT(foo(42) == 1, "CHOOSE_MACRO_VA_ARG() result does not match for 1 argument"); +#if defined(__cplusplus) && (__cplusplus > 201703L) +ESP_STATIC_ASSERT(foo(42, 87) == 1, "CHOOSE_MACRO_VA_ARG() result does not match for n arguments"); +#endif diff --git a/components/esp_hw_support/include/esp_private/esp_regdma.h b/components/esp_hw_support/include/esp_private/esp_regdma.h index 9e904997f70..1a082408fd7 100644 --- a/components/esp_hw_support/include/esp_private/esp_regdma.h +++ b/components/esp_hw_support/include/esp_private/esp_regdma.h @@ -396,9 +396,9 @@ void *regdma_find_prev_module_link_tail(void *link, void *tail, int entry, uint3 */ void *regdma_find_next_module_link_head(void *link, void *tail, int entry, uint32_t module); -#define regdma_link_init_safe(pcfg, branch, module, ...) regdma_link_init((pcfg), (branch), (module), __VA_NARG__(__VA_ARGS__), ##__VA_ARGS__) +#define regdma_link_init_safe(pcfg, branch, module, ...) regdma_link_init((pcfg), (branch), (module), ESP_VA_NARG(__VA_ARGS__), ##__VA_ARGS__) -#define regdma_link_update_next_safe(link, ...) regdma_link_update_next((link), __VA_NARG__(__VA_ARGS__), ##__VA_ARGS__) +#define regdma_link_update_next_safe(link, ...) regdma_link_update_next((link), ESP_VA_NARG(__VA_ARGS__), ##__VA_ARGS__) #endif // SOC_PAU_SUPPORTED diff --git a/docs/en/migration-guides/release-5.x/5.4/system.rst b/docs/en/migration-guides/release-5.x/5.4/system.rst index e6e0ede0156..cddbd0a6bb5 100644 --- a/docs/en/migration-guides/release-5.x/5.4/system.rst +++ b/docs/en/migration-guides/release-5.x/5.4/system.rst @@ -3,6 +3,11 @@ System :link_to_translation:`zh_CN:[中文]` +ESP-Common +---------- + +``__VA_NARG__`` and its related macros have been re-named to avoid naming collisions, use the new name with ``ESP`` pre-fix, e.g. ``ESP_VA_NARG`` instead. + Log --- diff --git a/docs/zh_CN/migration-guides/release-5.x/5.4/system.rst b/docs/zh_CN/migration-guides/release-5.x/5.4/system.rst index dbe6984ddd7..bb748fef113 100644 --- a/docs/zh_CN/migration-guides/release-5.x/5.4/system.rst +++ b/docs/zh_CN/migration-guides/release-5.x/5.4/system.rst @@ -3,6 +3,11 @@ :link_to_translation:`en:[English]` +ESP-Common +---------- + +``__VA_NARG__`` 及其相关宏已被重新命名以避免命名冲突，请使用带有 ESP 前缀的新名称，例如 ``ESP_VA_NARG``。 + 日志 ------ diff --git a/tools/idf_py_actions/hints.yml b/tools/idf_py_actions/hints.yml index 68181be0415..20ff00e2c0e 100644 --- a/tools/idf_py_actions/hints.yml +++ b/tools/idf_py_actions/hints.yml @@ -447,3 +447,6 @@ - re: "(error: Total discarded sections size is \\d+ bytes)|(region [`'.\\w]+ overflowed by \\d+ bytes)" hint: "The binary size has exceeded the limit. To resolve the issue consider reducing the binary size.\nYou can explore size optimization techniques in the documentation by running 'idf.py docs -sp api-guides/performance/size.html#reducing-overall-size'.\nNote that the linker performed the dead code elimination." + + re: "implicit declaration of function '__VA_NARG__'" + hint: "__VA_NARG_ has been renamed. Please use ESP_VA_NARG instead" From d53572ab10b677e61e69d08fefb84f6292dd3540 Mon Sep 17 00:00:00 2001 From: chenjianhua Date: Tue, 15 Oct 2024 10:46:02 +0800 Subject: [PATCH 151/472] fix(bt/bluedroid): Update address type for BLE link when the connection is completed --- components/bt/host/bluedroid/stack/l2cap/l2c_ble.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/components/bt/host/bluedroid/stack/l2cap/l2c_ble.c b/components/bt/host/bluedroid/stack/l2cap/l2c_ble.c index 01edf9caf53..36f91cfe087 100644 --- a/components/bt/host/bluedroid/stack/l2cap/l2c_ble.c +++ b/components/bt/host/bluedroid/stack/l2cap/l2c_ble.c @@ -376,6 +376,7 @@ void l2cble_scanner_conn_comp (UINT16 handle, BD_ADDR bda, tBLE_ADDR_TYPE type, p_lcb->waiting_update_conn_latency = p_lcb->current_used_conn_latency = conn_latency; p_lcb->conn_update_mask = L2C_BLE_NOT_DEFAULT_PARAM; p_lcb->updating_param_flag = false; + p_lcb->ble_addr_type = type; /* If there are any preferred connection parameters, set them now */ if ( (p_dev_rec->conn_params.min_conn_int >= BTM_BLE_CONN_INT_MIN ) && @@ -476,6 +477,7 @@ void l2cble_advertiser_conn_comp (UINT16 handle, BD_ADDR bda, tBLE_ADDR_TYPE typ p_lcb->waiting_update_conn_latency = p_lcb->current_used_conn_latency = conn_latency; p_lcb->conn_update_mask = L2C_BLE_NOT_DEFAULT_PARAM; p_lcb->updating_param_flag = false; + p_lcb->ble_addr_type = type; /* Tell BTM Acl management about the link */ p_dev_rec = btm_find_or_alloc_dev (bda); From d327186ddd5281f6ebba1c82617c0e79731eca3f Mon Sep 17 00:00:00 2001 From: Omar Chebib Date: Mon, 30 Sep 2024 11:31:37 +0800 Subject: [PATCH 152/472] fix(esp_psram): fix a bug in PSRAM heap registration This commit fixes a bug in the PSRAM heap initialization that didn't take into account the reserved himem area when registering the PSRAM virtual space as a heap. --- components/esp_psram/esp_psram.c | 1 + .../test_apps/psram/main/test_himem.c | 57 ++++++++++++++++++- 2 files changed, 57 insertions(+), 1 deletion(-) diff --git a/components/esp_psram/esp_psram.c b/components/esp_psram/esp_psram.c index 59176e7c74e..80a9cdeb5f4 100644 --- a/components/esp_psram/esp_psram.c +++ b/components/esp_psram/esp_psram.c @@ -325,6 +325,7 @@ static void s_psram_mapping(uint32_t psram_available_size, uint32_t start_page) #if CONFIG_IDF_TARGET_ESP32 s_psram_ctx.regions_to_heap[PSRAM_MEM_8BIT_ALIGNED].size -= esp_himem_reserved_area_size() - 1; + s_psram_ctx.regions_to_heap[PSRAM_MEM_8BIT_ALIGNED].vaddr_end -= esp_himem_reserved_area_size(); #endif } diff --git a/components/esp_psram/test_apps/psram/main/test_himem.c b/components/esp_psram/test_apps/psram/main/test_himem.c index cfb4372d201..7e048c3af34 100644 --- a/components/esp_psram/test_apps/psram/main/test_himem.c +++ b/components/esp_psram/test_apps/psram/main/test_himem.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -7,6 +7,7 @@ #include #include #include +#include #include "inttypes.h" #include "freertos/FreeRTOS.h" #include "freertos/task.h" @@ -106,6 +107,60 @@ TEST_CASE("high psram memory test", "[himem]") vTaskDelay(100); } +#define CACHE_BLOCKSIZE (32*1024) +#define ALLOCATIONS_SIZE (CACHE_BLOCKSIZE / 2) +#define MAX_ALLOCATIONS ((4*1024*1024) / ALLOCATIONS_SIZE) + +TEST_CASE("psram heap doesn't affect himem", "[himem]") +{ + esp_himem_handle_t mh; + esp_himem_rangehandle_t rh; + uint32_t *ptr = NULL; + /* Array containing all the areas from the heap */ + void* allocs[MAX_ALLOCATIONS] = { 0 }; + int allocs_idx = 0; + + /* Allocate a physical block from the PSRAM */ + ESP_ERROR_CHECK(esp_himem_alloc(CACHE_BLOCKSIZE, &mh)); + /* Allocate a range of virtual memory where we can map the allocated block */ + ESP_ERROR_CHECK(esp_himem_alloc_map_range(ESP_HIMEM_BLKSZ, &rh)); + /* Map that physical block in the allocated virtual memory */ + ESP_ERROR_CHECK(esp_himem_map(mh, rh, 0, 0, ESP_HIMEM_BLKSZ, 0, (void**)&ptr)); + /* Memset that part of the memory with an arbitrary pattern */ + memset(ptr, 0x42, CACHE_BLOCKSIZE); + + /* Allocate heap memory in PSRAM until there is no more memory */ + while (1) { + uint8_t* data = heap_caps_malloc(ALLOCATIONS_SIZE, MALLOC_CAP_SPIRAM); + /* If the allocation failed, there is no more memory, we can break */ + if (data == NULL) { + break; + } + assert(allocs_idx < MAX_ALLOCATIONS); + allocs[allocs_idx++] = data; + /* Set the allocated memory to another pattern */ + memset(data, 0xAB, ALLOCATIONS_SIZE); + } + + /* Make sure we allocated more than 127 blocks */ + printf("Allocated %d blocks\n", allocs_idx); + TEST_ASSERT_GREATER_THAN_INT(127, allocs_idx); + + /* Check if the himem block has been altered by the heap */ + TEST_ASSERT_EACH_EQUAL_INT8(0x42, ptr, CACHE_BLOCKSIZE); + + /* Free all the allocated memories */ + for (int i = 0; i < allocs_idx; i++) { + heap_caps_free(allocs[i]); + } + + ESP_ERROR_CHECK(esp_himem_unmap(rh, ptr, ESP_HIMEM_BLKSZ)); + ESP_ERROR_CHECK(esp_himem_free(mh)); + ESP_ERROR_CHECK(esp_himem_free_map_range(rh)); + + printf("Success!\n"); +} + #endif #endif // CONFIG_IDF_TARGET_ESP32 From 2a7ba86824cf523d0d35b9c603ce5ef883742b67 Mon Sep 17 00:00:00 2001 From: wanckl Date: Fri, 23 Aug 2024 19:32:59 +0800 Subject: [PATCH 153/472] fix(driver_spi): enable p4 multi dut test --- .../include/test_spi_utils.h | 5 ---- .../test_driver_utils/test_spi_utils.c | 3 +++ .../test_apps/.build-test-rules.yml | 4 ---- .../test_apps/master/main/test_spi_master.c | 17 ++++++++------ .../test_apps/master/pytest_spi_master.py | 4 ++-- .../test_apps/param/main/test_spi_param.c | 23 +++++++++++++------ .../test_apps/param/pytest_spi_param.py | 7 ++---- .../test_apps/slave/main/test_spi_slave.c | 2 ++ .../test_apps/slave/pytest_spi_slave.py | 4 ++-- .../slave_hd/main/test_spi_slave_hd.c | 10 ++++++-- .../test_apps/slave_hd/pytest_spi_slave_hd.py | 1 + components/soc/esp32p4/spi_periph.c | 1 - 12 files changed, 46 insertions(+), 35 deletions(-) diff --git a/components/driver/test_apps/components/test_driver_utils/include/test_spi_utils.h b/components/driver/test_apps/components/test_driver_utils/include/test_spi_utils.h index 0fdcb27e493..6bcac2a72d9 100644 --- a/components/driver/test_apps/components/test_driver_utils/include/test_spi_utils.h +++ b/components/driver/test_apps/components/test_driver_utils/include/test_spi_utils.h @@ -94,11 +94,6 @@ #define WIRE_DELAY 12.5 #endif //CONFIG_IDF_TARGET_ESP32 -#define GET_DMA_CHAN(HOST) (HOST) - -#define TEST_DMA_CHAN_MASTER GET_DMA_CHAN(TEST_SPI_HOST) -#define TEST_DMA_CHAN_SLAVE GET_DMA_CHAN(TEST_SLAVE_HOST) - #define FUNC_SPI SPI2_FUNC_NUM #define FUNC_GPIO PIN_FUNC_GPIO diff --git a/components/driver/test_apps/components/test_driver_utils/test_spi_utils.c b/components/driver/test_apps/components/test_driver_utils/test_spi_utils.c index 124021167f7..8e23021d84b 100644 --- a/components/driver/test_apps/components/test_driver_utils/test_spi_utils.c +++ b/components/driver/test_apps/components/test_driver_utils/test_spi_utils.c @@ -91,6 +91,7 @@ void spitest_slave_task(void* arg) t.length = txdata.len; t.tx_buffer = txdata.start; t.rx_buffer = recvbuf + 8; + t.flags |= SPI_SLAVE_TRANS_DMA_BUFFER_ALIGN_AUTO; //loop until trans_len != 0 to skip glitches do { TEST_ESP_OK(spi_slave_transmit(context->spi, &t, portMAX_DELAY)); @@ -231,6 +232,7 @@ void spitest_gpio_input_sel(uint32_t gpio_num, int func, uint32_t signal_idx) esp_rom_gpio_connect_in_signal(gpio_num, signal_idx, 0); } +#if (TEST_SPI_PERIPH_NUM >= 2) //Note this cs_dev_id is the ID of the connected devices' ID, e.g. if 2 devices are connected to the bus, //then the cs_dev_id of the 1st and 2nd devices are 0 and 1 respectively. void same_pin_func_sel(spi_bus_config_t bus, spi_device_interface_config_t dev, uint8_t cs_dev_id) @@ -247,3 +249,4 @@ void same_pin_func_sel(spi_bus_config_t bus, spi_device_interface_config_t dev, spitest_gpio_output_sel(bus.sclk_io_num, FUNC_GPIO, spi_periph_signal[TEST_SPI_HOST].spiclk_out); spitest_gpio_input_sel(bus.sclk_io_num, FUNC_GPIO, spi_periph_signal[TEST_SLAVE_HOST].spiclk_in); } +#endif //(TEST_SPI_PERIPH_NUM >= 2) diff --git a/components/esp_driver_spi/test_apps/.build-test-rules.yml b/components/esp_driver_spi/test_apps/.build-test-rules.yml index 81f1c69c5cf..9413dfd7e59 100644 --- a/components/esp_driver_spi/test_apps/.build-test-rules.yml +++ b/components/esp_driver_spi/test_apps/.build-test-rules.yml @@ -18,10 +18,6 @@ components/esp_driver_spi/test_apps/master: components/esp_driver_spi/test_apps/param: disable: - if: SOC_GPSPI_SUPPORTED != 1 - disable_test: - - if: IDF_TARGET == "esp32p4" - temporary: true - reason: no multi-dev runner # TODO: [ESP32P4] IDF-9517 <<: *spi_depends_default components/esp_driver_spi/test_apps/slave: diff --git a/components/esp_driver_spi/test_apps/master/main/test_spi_master.c b/components/esp_driver_spi/test_apps/master/main/test_spi_master.c index 4298dcdd222..c59347d3ebc 100644 --- a/components/esp_driver_spi/test_apps/master/main/test_spi_master.c +++ b/components/esp_driver_spi/test_apps/master/main/test_spi_master.c @@ -1251,6 +1251,7 @@ static void slave_only_tx_trans(uint8_t *slv_send_buf, uint32_t length) { ESP_LOGI(SLAVE_TAG, "FD DMA, Only TX"); spi_slave_transaction_t trans = {0}; + trans.flags |= SPI_SLAVE_TRANS_DMA_BUFFER_ALIGN_AUTO; trans.tx_buffer = slv_send_buf; trans.length = length * 8; unity_send_signal("Slave ready"); @@ -1262,6 +1263,7 @@ static void slave_only_rx_trans(uint8_t *slv_recv_buf, uint8_t *mst_send_buf, ui { ESP_LOGI(SLAVE_TAG, "FD DMA, Only RX"); spi_slave_transaction_t trans = {}; + trans.flags |= SPI_SLAVE_TRANS_DMA_BUFFER_ALIGN_AUTO; trans.tx_buffer = NULL; trans.rx_buffer = slv_recv_buf; trans.length = length * 8; @@ -1276,6 +1278,7 @@ static void slave_both_trans(uint8_t *slv_send_buf, uint8_t *slv_recv_buf, uint8 { ESP_LOGI(SLAVE_TAG, "FD DMA, Both TX and RX:"); spi_slave_transaction_t trans = {0}; + trans.flags |= SPI_SLAVE_TRANS_DMA_BUFFER_ALIGN_AUTO; trans.tx_buffer = slv_send_buf; trans.rx_buffer = slv_recv_buf; trans.length = length * 8; @@ -1492,6 +1495,8 @@ TEST_CASE("spi_speed", "[spi]") #define DUMMY_CS_PINS() {25, 26, 27} #elif CONFIG_IDF_TARGET_ESP32H2 #define DUMMY_CS_PINS() {9, 10, 11, 12, 22, 25} +#elif CONFIG_IDF_TARGET_ESP32P4 +#define DUMMY_CS_PINS() {20, 21, 22, 23, 24, 25} #else #define DUMMY_CS_PINS() {0, 1, 4, 5, 8, 9} #endif //CONFIG_IDF_TARGET_ESP32 @@ -1575,6 +1580,7 @@ void test_add_device_slave(void) slave_trans.length = sizeof(slave_sendbuf) * 8; slave_trans.tx_buffer = slave_sendbuf; slave_trans.rx_buffer = slave_recvbuf; + slave_trans.flags |= SPI_SLAVE_TRANS_DMA_BUFFER_ALIGN_AUTO; for (uint8_t i = 0; i < SOC_SPI_MAX_CS_NUM; i++) { memset(slave_recvbuf, 0, sizeof(slave_recvbuf)); @@ -1697,7 +1703,6 @@ static IRAM_ATTR void test_master_iram(void) spi_flash_enable_interrupts_caches_and_other_cpu(); ESP_LOG_BUFFER_HEX("master tx", ret_trans->tx_buffer, TEST_MASTER_IRAM_TRANS_LEN); - ESP_LOG_BUFFER_HEX("master rx", ret_trans->rx_buffer, TEST_MASTER_IRAM_TRANS_LEN); spitest_cmp_or_dump(master_exp, trans_cfg.rx_buffer, TEST_MASTER_IRAM_TRANS_LEN); // Test polling trans api once ------------------------------- @@ -1709,13 +1714,12 @@ static IRAM_ATTR void test_master_iram(void) spi_flash_enable_interrupts_caches_and_other_cpu(); ESP_LOG_BUFFER_HEX("master tx", ret_trans->tx_buffer, TEST_MASTER_IRAM_TRANS_LEN); - ESP_LOG_BUFFER_HEX("master rx", ret_trans->rx_buffer, TEST_MASTER_IRAM_TRANS_LEN); spitest_cmp_or_dump(master_exp, trans_cfg.rx_buffer, TEST_MASTER_IRAM_TRANS_LEN); free(master_send); free(master_recv); free(master_exp); - spi_bus_remove_device(dev_handle); + TEST_ESP_OK(spi_bus_remove_device(dev_handle)); spi_bus_free(TEST_SPI_HOST); } @@ -1733,20 +1737,19 @@ static void test_iram_slave_normal(void) slave_trans.length = TEST_MASTER_IRAM_TRANS_LEN * 8; slave_trans.tx_buffer = slave_sendbuf; slave_trans.rx_buffer = slave_recvbuf; + slave_trans.flags |= SPI_SLAVE_TRANS_DMA_BUFFER_ALIGN_AUTO; test_fill_random_to_buffers_dualboard(211, slave_expect, slave_sendbuf, TEST_MASTER_IRAM_TRANS_LEN); unity_wait_for_signal("Master ready"); unity_send_signal("Slave ready"); - spi_slave_transmit(TEST_SPI_HOST, &slave_trans, portMAX_DELAY); + TEST_ESP_OK(spi_slave_transmit(TEST_SPI_HOST, &slave_trans, portMAX_DELAY)); ESP_LOG_BUFFER_HEX("slave tx", slave_sendbuf, TEST_MASTER_IRAM_TRANS_LEN); - ESP_LOG_BUFFER_HEX("slave rx", slave_recvbuf, TEST_MASTER_IRAM_TRANS_LEN); spitest_cmp_or_dump(slave_expect, slave_recvbuf, TEST_MASTER_IRAM_TRANS_LEN); unity_send_signal("Slave ready"); test_fill_random_to_buffers_dualboard(119, slave_expect, slave_sendbuf, TEST_MASTER_IRAM_TRANS_LEN); - spi_slave_transmit(TEST_SPI_HOST, &slave_trans, portMAX_DELAY); + TEST_ESP_OK(spi_slave_transmit(TEST_SPI_HOST, &slave_trans, portMAX_DELAY)); ESP_LOG_BUFFER_HEX("slave tx", slave_sendbuf, TEST_MASTER_IRAM_TRANS_LEN); - ESP_LOG_BUFFER_HEX("slave rx", slave_recvbuf, TEST_MASTER_IRAM_TRANS_LEN); spitest_cmp_or_dump(slave_expect, slave_recvbuf, TEST_MASTER_IRAM_TRANS_LEN); free(slave_sendbuf); diff --git a/components/esp_driver_spi/test_apps/master/pytest_spi_master.py b/components/esp_driver_spi/test_apps/master/pytest_spi_master.py index 1ac833a84de..0afe5c97f39 100644 --- a/components/esp_driver_spi/test_apps/master/pytest_spi_master.py +++ b/components/esp_driver_spi/test_apps/master/pytest_spi_master.py @@ -27,8 +27,8 @@ def test_master_esp_flash(case_tester) -> None: # type: ignore # if `test_env` not defined, will run on `generic_multi_device` by default -# TODO: [ESP32P4] IDF-9517 [ESP32C5] IDF-10322 [ESP32C61] IDF-10949 -@pytest.mark.temp_skip_ci(targets=['esp32p4', 'esp32c5', 'esp32c61'], reason='no multi-dev runner') +# TODO: [ESP32C5] IDF-10322 [ESP32C61] IDF-10949 +@pytest.mark.temp_skip_ci(targets=['esp32c5', 'esp32c61'], reason='no multi-dev runner') @pytest.mark.supported_targets @pytest.mark.generic_multi_device @pytest.mark.parametrize( diff --git a/components/esp_driver_spi/test_apps/param/main/test_spi_param.c b/components/esp_driver_spi/test_apps/param/main/test_spi_param.c index 627f4ad492a..71506acb752 100644 --- a/components/esp_driver_spi/test_apps/param/main/test_spi_param.c +++ b/components/esp_driver_spi/test_apps/param/main/test_spi_param.c @@ -109,6 +109,10 @@ static void local_test_start(spi_device_handle_t *spi, int freq, const spitest_p devcfg.flags |= SPI_DEVICE_NO_DUMMY; } +#if CONFIG_IDF_TARGET_ESP32P4 //TODO: IDF-8313, update P4 defaulte clock source + devcfg.clock_source = SPI_CLK_SRC_SPLL; +#endif + //slave config slvcfg.mode = pset->mode; slave_pull_up(&buscfg, slvcfg.spics_io_num); @@ -192,6 +196,7 @@ static void local_test_loop(const void *arg1, void *arg2) .tx_buffer = txdata->start, .rx_buffer = recvbuf, .length = txdata->len, + .flags = SPI_SLAVE_TRANS_DMA_BUFFER_ALIGN_AUTO, }; esp_err_t err = spi_slave_queue_trans(TEST_SLAVE_HOST, &slave_trans, portMAX_DELAY); TEST_ESP_OK(err); @@ -247,8 +252,7 @@ static void local_test_loop(const void *arg1, void *arg2) /************ Timing Test ***********************************************/ //TODO: esp32s2 has better timing performance static spitest_param_set_t timing_pgroup[] = { -//signals are not fed to peripherals through iomux if the functions are not selected to iomux -#if !DISABLED_FOR_TARGETS(ESP32S2, ESP32S3) +#if (SLAVE_IOMUX_PIN_MISO != -1) //SPI3 slave has iomux pin { .pset_name = "FULL_DUP, MASTER IOMUX", .freq_limit = ESP_SPI_SLAVE_MAX_FREQ_SYNC, @@ -277,8 +281,7 @@ static spitest_param_set_t timing_pgroup[] = { .slave_iomux = false, .slave_tv_ns = TV_INT_CONNECT_GPIO, }, -//signals are not fed to peripherals through iomux if the functions are not selected to iomux -#if !DISABLED_FOR_TARGETS(ESP32S2, ESP32S3) +#if (SLAVE_IOMUX_PIN_MISO != -1) //SPI3 slave has iomux pin { .pset_name = "MISO_DUP, MASTER IOMUX", .freq_limit = ESP_SPI_SLAVE_MAX_FREQ_SYNC, @@ -307,8 +310,7 @@ static spitest_param_set_t timing_pgroup[] = { .slave_iomux = false, .slave_tv_ns = TV_INT_CONNECT_GPIO, }, -//signals are not fed to peripherals through iomux if the functions are not selected to iomux -#if !DISABLED_FOR_TARGETS(ESP32S2, ESP32S3) +#if (SLAVE_IOMUX_PIN_MISO != -1) //SPI3 slave has iomux pin { .pset_name = "MOSI_DUP, MASTER IOMUX", .freq_limit = ESP_SPI_SLAVE_MAX_FREQ_SYNC, @@ -616,7 +618,8 @@ TEST_CASE("Slave receive correct data", "[spi]") spi_slave_transaction_t slave_trans = { .length = slave_trans_len * 8, .tx_buffer = slave_sendbuf, - .rx_buffer = slave_recvbuf + .rx_buffer = slave_recvbuf, + .flags = SPI_SLAVE_TRANS_DMA_BUFFER_ALIGN_AUTO, }; esp_err_t ret = spi_slave_queue_trans(TEST_SLAVE_HOST, &slave_trans, portMAX_DELAY); TEST_ESP_OK(ret); @@ -1270,7 +1273,9 @@ static int s_spi_bus_freq[] = { IDF_PERFORMANCE_MAX_SPI_CLK_FREQ / 7, IDF_PERFORMANCE_MAX_SPI_CLK_FREQ / 4, IDF_PERFORMANCE_MAX_SPI_CLK_FREQ / 2, +#if !CONFIG_IDF_TARGET_ESP32P4 //TODO: IDF-8313, update P4 defaulte clock source IDF_PERFORMANCE_MAX_SPI_CLK_FREQ, +#endif }; //------------------------------------------- Full Duplex with DMA Freq test -------------------------------------- @@ -1483,6 +1488,7 @@ static void test_slave_fd_no_dma(void) .tx_buffer = slave_send, .rx_buffer = slave_receive, .length = test_trans_len * 8, + .flags = SPI_SLAVE_TRANS_DMA_BUFFER_ALIGN_AUTO, }; unity_send_signal("Slave ready"); TEST_ESP_OK(spi_slave_transmit(TEST_SPI_HOST, &trans_cfg, portMAX_DELAY)); @@ -1587,6 +1593,7 @@ static void test_slave_hd_dma(void) TEST_ESP_OK(spi_slave_hd_queue_trans(TEST_SPI_HOST, SPI_SLAVE_CHAN_TX, &slave_trans, portMAX_DELAY)); slave_trans.data = slave_receive; TEST_ESP_OK(spi_slave_hd_queue_trans(TEST_SPI_HOST, SPI_SLAVE_CHAN_RX, &slave_trans, portMAX_DELAY)); + TEST_ESP_OK(spi_slave_hd_get_trans_res(TEST_SPI_HOST, SPI_SLAVE_CHAN_TX, &ret_trans, portMAX_DELAY)); TEST_ESP_OK(spi_slave_hd_get_trans_res(TEST_SPI_HOST, SPI_SLAVE_CHAN_RX, &ret_trans, portMAX_DELAY)); ESP_LOG_BUFFER_HEX("slave tx", slave_send, test_trans_len); @@ -1688,6 +1695,7 @@ static void test_slave_hd_no_dma(void) TEST_ESP_OK(spi_slave_hd_queue_trans(TEST_SPI_HOST, SPI_SLAVE_CHAN_TX, &slave_trans, portMAX_DELAY)); slave_trans.data = slave_receive; TEST_ESP_OK(spi_slave_hd_queue_trans(TEST_SPI_HOST, SPI_SLAVE_CHAN_RX, &slave_trans, portMAX_DELAY)); + TEST_ESP_OK(spi_slave_hd_get_trans_res(TEST_SPI_HOST, SPI_SLAVE_CHAN_TX, &ret_trans, portMAX_DELAY)); TEST_ESP_OK(spi_slave_hd_get_trans_res(TEST_SPI_HOST, SPI_SLAVE_CHAN_RX, &ret_trans, portMAX_DELAY)); ESP_LOG_BUFFER_HEX("slave tx", slave_send, test_trans_len); @@ -1951,6 +1959,7 @@ static void test_slave_sio_no_dma(void) .length = SOC_SPI_MAXIMUM_BUFFER_SIZE * 8, .tx_buffer = slave_send, .rx_buffer = slave_receive, + .flags = SPI_SLAVE_TRANS_DMA_BUFFER_ALIGN_AUTO, }; unity_send_signal("Slave ready"); TEST_ESP_OK(spi_slave_transmit(TEST_SPI_HOST, &trans, portMAX_DELAY)); diff --git a/components/esp_driver_spi/test_apps/param/pytest_spi_param.py b/components/esp_driver_spi/test_apps/param/pytest_spi_param.py index d565235e9c8..26308aaf34d 100644 --- a/components/esp_driver_spi/test_apps/param/pytest_spi_param.py +++ b/components/esp_driver_spi/test_apps/param/pytest_spi_param.py @@ -4,9 +4,7 @@ # If `test_env` is define, should not run on generic runner -@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 support TBD') # TODO: IDF-8942 @pytest.mark.supported_targets -@pytest.mark.esp32h2 @pytest.mark.generic def test_param_single_dev(case_tester) -> None: # type: ignore for case in case_tester.test_menu: @@ -16,10 +14,9 @@ def test_param_single_dev(case_tester) -> None: # type: ignore # if `test_env` not defined, will run on `generic_multi_device` by default -# TODO: [ESP32P4] IDF-8942 [ESP32C5] IDF-10322 [ESP32C61] IDF-10949 -@pytest.mark.temp_skip_ci(targets=['esp32p4', 'esp32c5', 'esp32c61'], reason='no multi-dev runner') +# TODO: [ESP32C5] IDF-10322 [ESP32C61] IDF-10949 +@pytest.mark.temp_skip_ci(targets=['esp32c5', 'esp32c61'], reason='no multi-dev runner') @pytest.mark.supported_targets -@pytest.mark.esp32h2 @pytest.mark.generic_multi_device @pytest.mark.parametrize('count', [2,], indirect=True) def test_param_multi_dev(case_tester) -> None: # type: ignore diff --git a/components/esp_driver_spi/test_apps/slave/main/test_spi_slave.c b/components/esp_driver_spi/test_apps/slave/main/test_spi_slave.c index 8a27902e716..46537168210 100644 --- a/components/esp_driver_spi/test_apps/slave/main/test_spi_slave.c +++ b/components/esp_driver_spi/test_apps/slave/main/test_spi_slave.c @@ -562,6 +562,7 @@ static IRAM_ATTR void test_slave_isr_iram(void) } TEST_CASE_MULTIPLE_DEVICES("SPI_Slave: Test_ISR_IRAM_disable_cache", "[spi_ms]", test_slave_iram_master_normal, test_slave_isr_iram); +#if !SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE //isr option is not supported in this condition static uint32_t isr_trans_cnt, isr_trans_test_fail; static IRAM_ATTR void test_trans_in_isr_post_trans_cbk(spi_slave_transaction_t *curr_trans) { @@ -725,6 +726,7 @@ static IRAM_ATTR void spi_queue_reset_in_isr(void) spi_slave_free(TEST_SPI_HOST); } TEST_CASE_MULTIPLE_DEVICES("SPI_Slave: Test_Queue_Reset_in_ISR", "[spi_ms]", test_slave_iram_master_normal, spi_queue_reset_in_isr); +#endif // SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE #endif // CONFIG_SPI_SLAVE_ISR_IN_IRAM #if (SOC_CPU_CORES_NUM > 1) && (!CONFIG_FREERTOS_UNICORE) diff --git a/components/esp_driver_spi/test_apps/slave/pytest_spi_slave.py b/components/esp_driver_spi/test_apps/slave/pytest_spi_slave.py index b39e7f94847..f58db76aee4 100644 --- a/components/esp_driver_spi/test_apps/slave/pytest_spi_slave.py +++ b/components/esp_driver_spi/test_apps/slave/pytest_spi_slave.py @@ -15,8 +15,8 @@ def test_slave_single_dev(case_tester) -> None: # type: ignore # if `test_env` not defined, will run on `generic_multi_device` by default -# TODO: [ESP32P4] IDF-9517 [ESP32C5] IDF-10322 [ESP32C61] IDF-10949 -@pytest.mark.temp_skip_ci(targets=['esp32p4', 'esp32c5', 'esp32c61'], reason='no multi-dev runner') +# TODO: [ESP32C5] IDF-10322 [ESP32C61] IDF-10949 +@pytest.mark.temp_skip_ci(targets=['esp32c5', 'esp32c61'], reason='no multi-dev runner') @pytest.mark.supported_targets @pytest.mark.generic_multi_device @pytest.mark.parametrize('count, config', [(2, 'defaults'), (2, 'iram_safe')], indirect=True) diff --git a/components/esp_driver_spi/test_apps/slave_hd/main/test_spi_slave_hd.c b/components/esp_driver_spi/test_apps/slave_hd/main/test_spi_slave_hd.c index 397a30f4a1a..eea77e52c33 100644 --- a/components/esp_driver_spi/test_apps/slave_hd/main/test_spi_slave_hd.c +++ b/components/esp_driver_spi/test_apps/slave_hd/main/test_spi_slave_hd.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -855,19 +855,23 @@ static void hd_slave_quad(void) { .data = slave_recv_buf, .len = (trans_len + 3) & (~3), + .flags = SPI_SLAVE_HD_TRANS_DMA_BUFFER_ALIGN_AUTO, }, { .data = slave_recv_buf + BUF_SIZE / 2, .len = (trans_len + 3) & (~3), + .flags = SPI_SLAVE_HD_TRANS_DMA_BUFFER_ALIGN_AUTO, }, //send { .data = slave_send_buf, .len = (trans_len + 3) & (~3), + .flags = SPI_SLAVE_HD_TRANS_DMA_BUFFER_ALIGN_AUTO, }, { .data = slave_send_buf + BUF_SIZE / 2, .len = (trans_len + 3) & (~3), + .flags = SPI_SLAVE_HD_TRANS_DMA_BUFFER_ALIGN_AUTO, }, }; @@ -901,7 +905,7 @@ static void hd_slave_quad(void) spi_slave_hd_deinit(TEST_SLAVE_HOST); } -TEST_CASE_MULTIPLE_DEVICES("SPI quad hd test ", "[spi_ms][test_env=generic_multi_device]", hd_master_quad, hd_slave_quad); +TEST_CASE_MULTIPLE_DEVICES("SPI quad hd test", "[spi_ms][test_env=generic_multi_device]", hd_master_quad, hd_slave_quad); #endif // #if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2) @@ -941,6 +945,7 @@ void slave_run_append(void) slave_rx_trans[append_idx].data = heap_caps_aligned_calloc(4, 1, TEST_TRANS_LEN, MALLOC_CAP_DMA); TEST_ASSERT_NOT_NULL(slave_rx_trans[append_idx].data); slave_rx_trans[append_idx].len = trans_len; + slave_rx_trans[append_idx].flags |= SPI_SLAVE_HD_TRANS_DMA_BUFFER_ALIGN_AUTO; TEST_ESP_OK(spi_slave_hd_append_trans(TEST_SPI_HOST, SPI_SLAVE_CHAN_RX, &slave_rx_trans[append_idx], portMAX_DELAY)); } @@ -982,6 +987,7 @@ void slave_run_append(void) } slave_tx_trans[append_idx].data = slave_rx_trans[append_idx].data; slave_tx_trans[append_idx].len = trans_len; + slave_tx_trans[append_idx].flags |= SPI_SLAVE_HD_TRANS_DMA_BUFFER_ALIGN_AUTO; prepare_data(slave_tx_trans[append_idx].data, trans_len, -3); TEST_ESP_OK(spi_slave_hd_append_trans(TEST_SPI_HOST, SPI_SLAVE_CHAN_TX, &slave_tx_trans[append_idx], portMAX_DELAY)); } diff --git a/components/esp_driver_spi/test_apps/slave_hd/pytest_spi_slave_hd.py b/components/esp_driver_spi/test_apps/slave_hd/pytest_spi_slave_hd.py index d8470588460..6fea4581ee6 100644 --- a/components/esp_driver_spi/test_apps/slave_hd/pytest_spi_slave_hd.py +++ b/components/esp_driver_spi/test_apps/slave_hd/pytest_spi_slave_hd.py @@ -28,6 +28,7 @@ def test_slave_hd_single_dev(case_tester) -> None: # type: ignore @pytest.mark.esp32c3 @pytest.mark.esp32c6 @pytest.mark.esp32h2 +@pytest.mark.esp32p4 @pytest.mark.generic_multi_device @pytest.mark.parametrize('count', [2,], indirect=True) def test_slave_hd_multi_dev(case_tester) -> None: # type: ignore diff --git a/components/soc/esp32p4/spi_periph.c b/components/soc/esp32p4/spi_periph.c index 5a629b6604c..8d88638166e 100644 --- a/components/soc/esp32p4/spi_periph.c +++ b/components/soc/esp32p4/spi_periph.c @@ -73,7 +73,6 @@ const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = { .spiclk_in = SPI3_CK_PAD_IN_IDX, .spid_out = SPI3_D_PAD_OUT_IDX, .spiq_out = SPI3_QO_PAD_OUT_IDX, - //SPI3 doesn't have wp and hd signals .spiwp_out = SPI3_WP_PAD_OUT_IDX, .spihd_out = SPI3_HOLD_PAD_OUT_IDX, .spid_in = SPI3_D_PAD_IN_IDX, From ca66d3fb4095fe54c0b9b5216ce70b479c26dbb5 Mon Sep 17 00:00:00 2001 From: wanckl Date: Mon, 26 Aug 2024 18:51:47 +0800 Subject: [PATCH 154/472] fix(driver_spi): enable c5 spi test --- components/esp_driver_spi/test_apps/.build-test-rules.yml | 4 ---- .../components/spi_bench_mark/include/spi_performance.h | 2 +- .../esp_driver_spi/test_apps/master/pytest_spi_master.py | 5 ++--- .../esp_driver_spi/test_apps/param/pytest_spi_param.py | 4 ++-- .../esp_driver_spi/test_apps/slave/pytest_spi_slave.py | 4 ++-- .../esp_driver_spi/test_apps/slave_hd/pytest_spi_slave_hd.py | 1 + 6 files changed, 8 insertions(+), 12 deletions(-) diff --git a/components/esp_driver_spi/test_apps/.build-test-rules.yml b/components/esp_driver_spi/test_apps/.build-test-rules.yml index 9413dfd7e59..9b605ff8552 100644 --- a/components/esp_driver_spi/test_apps/.build-test-rules.yml +++ b/components/esp_driver_spi/test_apps/.build-test-rules.yml @@ -9,10 +9,6 @@ components/esp_driver_spi/test_apps/master: disable: - if: SOC_GPSPI_SUPPORTED != 1 - disable_test: - - if: IDF_TARGET in ["esp32c61"] - temporary: true - reason: no multi-dev runner # TODO: [ESP32C61] IDF-10949 <<: *spi_depends_default components/esp_driver_spi/test_apps/param: diff --git a/components/esp_driver_spi/test_apps/components/spi_bench_mark/include/spi_performance.h b/components/esp_driver_spi/test_apps/components/spi_bench_mark/include/spi_performance.h index 5dcb6f690f3..2b68f9d0406 100644 --- a/components/esp_driver_spi/test_apps/components/spi_bench_mark/include/spi_performance.h +++ b/components/esp_driver_spi/test_apps/components/spi_bench_mark/include/spi_performance.h @@ -84,7 +84,7 @@ #elif CONFIG_IDF_TARGET_ESP32C61 #define IDF_PERFORMANCE_MAX_SPI_CLK_FREQ 40*1000*1000 #define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING 32 -#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING 17 +#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING 19 #define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING_NO_DMA 29 #define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING_NO_DMA 14 diff --git a/components/esp_driver_spi/test_apps/master/pytest_spi_master.py b/components/esp_driver_spi/test_apps/master/pytest_spi_master.py index 0afe5c97f39..691929a135a 100644 --- a/components/esp_driver_spi/test_apps/master/pytest_spi_master.py +++ b/components/esp_driver_spi/test_apps/master/pytest_spi_master.py @@ -5,7 +5,6 @@ # If `test_env` is define, should not run on generic runner @pytest.mark.supported_targets -@pytest.mark.temp_skip_ci(targets=['esp32c61'], reason='test case fail') # TODO: [ESP32C61] IDF-10949 @pytest.mark.generic @pytest.mark.parametrize('config', ['defaults', 'release', 'freertos_compliance', 'freertos_flash',], indirect=True) def test_master_single_dev(case_tester) -> None: # type: ignore @@ -27,8 +26,8 @@ def test_master_esp_flash(case_tester) -> None: # type: ignore # if `test_env` not defined, will run on `generic_multi_device` by default -# TODO: [ESP32C5] IDF-10322 [ESP32C61] IDF-10949 -@pytest.mark.temp_skip_ci(targets=['esp32c5', 'esp32c61'], reason='no multi-dev runner') +# TODO: [ESP32C61] IDF-10949 +@pytest.mark.temp_skip_ci(targets=['esp32c61'], reason='no multi-dev runner') @pytest.mark.supported_targets @pytest.mark.generic_multi_device @pytest.mark.parametrize( diff --git a/components/esp_driver_spi/test_apps/param/pytest_spi_param.py b/components/esp_driver_spi/test_apps/param/pytest_spi_param.py index 26308aaf34d..d7df6964106 100644 --- a/components/esp_driver_spi/test_apps/param/pytest_spi_param.py +++ b/components/esp_driver_spi/test_apps/param/pytest_spi_param.py @@ -14,8 +14,8 @@ def test_param_single_dev(case_tester) -> None: # type: ignore # if `test_env` not defined, will run on `generic_multi_device` by default -# TODO: [ESP32C5] IDF-10322 [ESP32C61] IDF-10949 -@pytest.mark.temp_skip_ci(targets=['esp32c5', 'esp32c61'], reason='no multi-dev runner') +# TODO: [ESP32C61] IDF-10949 +@pytest.mark.temp_skip_ci(targets=['esp32c61'], reason='no multi-dev runner') @pytest.mark.supported_targets @pytest.mark.generic_multi_device @pytest.mark.parametrize('count', [2,], indirect=True) diff --git a/components/esp_driver_spi/test_apps/slave/pytest_spi_slave.py b/components/esp_driver_spi/test_apps/slave/pytest_spi_slave.py index f58db76aee4..5b9f8823dc2 100644 --- a/components/esp_driver_spi/test_apps/slave/pytest_spi_slave.py +++ b/components/esp_driver_spi/test_apps/slave/pytest_spi_slave.py @@ -15,8 +15,8 @@ def test_slave_single_dev(case_tester) -> None: # type: ignore # if `test_env` not defined, will run on `generic_multi_device` by default -# TODO: [ESP32C5] IDF-10322 [ESP32C61] IDF-10949 -@pytest.mark.temp_skip_ci(targets=['esp32c5', 'esp32c61'], reason='no multi-dev runner') +# TODO: [ESP32C61] IDF-10949 +@pytest.mark.temp_skip_ci(targets=['esp32c61'], reason='no multi-dev runner') @pytest.mark.supported_targets @pytest.mark.generic_multi_device @pytest.mark.parametrize('count, config', [(2, 'defaults'), (2, 'iram_safe')], indirect=True) diff --git a/components/esp_driver_spi/test_apps/slave_hd/pytest_spi_slave_hd.py b/components/esp_driver_spi/test_apps/slave_hd/pytest_spi_slave_hd.py index 6fea4581ee6..5d09b75f069 100644 --- a/components/esp_driver_spi/test_apps/slave_hd/pytest_spi_slave_hd.py +++ b/components/esp_driver_spi/test_apps/slave_hd/pytest_spi_slave_hd.py @@ -26,6 +26,7 @@ def test_slave_hd_single_dev(case_tester) -> None: # type: ignore @pytest.mark.esp32s3 @pytest.mark.esp32c2 @pytest.mark.esp32c3 +@pytest.mark.esp32c5 @pytest.mark.esp32c6 @pytest.mark.esp32h2 @pytest.mark.esp32p4 From 020f7a6297f52e473e724af6509b72350024e62f Mon Sep 17 00:00:00 2001 From: chenjianhua Date: Tue, 15 Oct 2024 12:11:13 +0800 Subject: [PATCH 155/472] fix(bt/controller): Fixed BLE functions overriding on ESP32-C3 ECO7 --- components/esp_rom/esp32c3/ld/esp32c3.rom.eco7.ld | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/components/esp_rom/esp32c3/ld/esp32c3.rom.eco7.ld b/components/esp_rom/esp32c3/ld/esp32c3.rom.eco7.ld index 69df558be7e..beaccc21dd6 100644 --- a/components/esp_rom/esp32c3/ld/esp32c3.rom.eco7.ld +++ b/components/esp_rom/esp32c3/ld/esp32c3.rom.eco7.ld @@ -172,7 +172,6 @@ r_bt_rtp_get_txpwr_idx_by_act = 0x40000c00; r_btdm_task_post = 0x40000c14; r_btdm_task_post_from_isr = 0x40000c18; r_btdm_task_recycle = 0x40000c1c; -r_hci_register_vendor_desc_tab = 0x40000d9c; r_ke_task_schedule = 0x40000e80; r_llc_hci_command_handler = 0x40000ef0; r_llc_loc_ch_map_proc_continue = 0x40000f5c; @@ -183,8 +182,6 @@ r_lld_con_sched = 0x40001118; r_lld_con_stop = 0x40001124; r_lld_llcp_rx_ind_handler = 0x400011b0; r_lld_per_adv_sched = 0x400011f8; -r_lld_scan_process_pkt_rx_adv_rep = 0x40001284; -r_register_esp_vendor_cmd_handler = 0x40001400; r_rf_txpwr_cs_get = 0x40001428; r_rf_txpwr_dbm_get = 0x4000142c; r_sch_arb_event_start_isr = 0x400014f8; @@ -216,6 +213,9 @@ r_lld_scan_start_hook = 0x40001c74; r_lld_init_start_hook = 0x40001cb8; r_lld_scan_evt_start_cbk_eco = 0x40001d20; r_ke_task_handler_get_overwrite = 0x40001da8; +r_hci_register_vendor_desc_tab = 0x40000d9c; +r_lld_scan_process_pkt_rx_adv_rep = 0x40001284; +r_register_esp_vendor_cmd_handler = 0x40001400; */ From 82e6c0619338214cb90b8e42dfdceb66b2aca278 Mon Sep 17 00:00:00 2001 From: Nachiket Kukade Date: Mon, 14 Oct 2024 21:29:52 +0530 Subject: [PATCH 156/472] feat(wpa_supplicant): Add sbom manifest file for wpa_supplicant --- components/wpa_supplicant/sbom.yml | 6 ++++++ 1 file changed, 6 insertions(+) create mode 100644 components/wpa_supplicant/sbom.yml diff --git a/components/wpa_supplicant/sbom.yml b/components/wpa_supplicant/sbom.yml new file mode 100644 index 00000000000..c283feb6320 --- /dev/null +++ b/components/wpa_supplicant/sbom.yml @@ -0,0 +1,6 @@ +name: 'wpa_supplicant' +version: '2.10' +cpe: cpe:2.3:a:w1.fi:wpa_supplicant:{}:*:*:*:*:*:*:* +supplier: 'Organization: Espressif Systems (Shanghai) CO LTD' +originator: 'Person: Jouni Malinen' +description: Espressif fork of wpa_supplicant - an open-source WPA/WPA2/WPA3/IEEE 802.1X Supplicant. From af318a91a1c0394fdabbbd60963e89bb3e63fc47 Mon Sep 17 00:00:00 2001 From: "C.S.M" Date: Tue, 15 Oct 2024 17:30:48 +0800 Subject: [PATCH 157/472] test(spi_flash): Add 32MB flash encrypted write-read test (beyond 16MB) --- .../main/test_flash_encryption.c | 80 +++++++++++++++++++ .../sdkconfig.ci.release_f8r8 | 1 + 2 files changed, 81 insertions(+) diff --git a/components/spi_flash/test_apps/flash_encryption/main/test_flash_encryption.c b/components/spi_flash/test_apps/flash_encryption/main/test_flash_encryption.c index 6ebfa46b523..0277dd5ebcd 100644 --- a/components/spi_flash/test_apps/flash_encryption/main/test_flash_encryption.c +++ b/components/spi_flash/test_apps/flash_encryption/main/test_flash_encryption.c @@ -273,6 +273,33 @@ TEST_CASE("test read & write encrypted data(32 bytes alianed address)", "[flash_ free(cmp_normal_buf); free(cmp_encrypt_buf); + + uint32_t size; + esp_flash_get_physical_size(NULL, &size); + + if (size > 0x1000000) { + start = 0x1030000; + TEST_ESP_OK(esp_flash_erase_region(NULL, start, SPI_FLASH_SEC_SIZE)); + start = (start + 31) & (~31); // round up to 32 byte boundary + printf("Test data partition @ 0x%" PRIx32 "\n", (uint32_t) start); + ESP_LOG_BUFFER_HEXDUMP(TAG, plainttext_data, sizeof(plainttext_data), ESP_LOG_INFO); + printf("Encrypted writing......\n"); + TEST_ESP_OK(esp_flash_write_encrypted(NULL, start, plainttext_data, sizeof(plainttext_data))); + + cmp_encrypt_buf = heap_caps_malloc(SPI_FLASH_SEC_SIZE, MALLOC_CAP_32BIT | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL); + printf("Encrypted reading......\n"); + TEST_ESP_OK(esp_flash_read_encrypted(NULL, start, cmp_encrypt_buf, SPI_FLASH_SEC_SIZE)); + ESP_LOG_BUFFER_HEXDUMP(TAG, cmp_encrypt_buf, sizeof(plainttext_data), ESP_LOG_INFO); + TEST_ASSERT_EQUAL_HEX8_ARRAY(plainttext_data, cmp_encrypt_buf, sizeof(plainttext_data)); + + cmp_normal_buf = heap_caps_malloc(SPI_FLASH_SEC_SIZE, MALLOC_CAP_32BIT | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL); + TEST_ESP_OK(esp_flash_read(NULL, cmp_normal_buf, start, SPI_FLASH_SEC_SIZE)); + printf("Normal read(esp_flash_read)......\n"); + ESP_LOG_BUFFER_HEXDUMP(TAG, cmp_normal_buf, sizeof(plainttext_data), ESP_LOG_INFO); + + free(cmp_normal_buf); + free(cmp_encrypt_buf); + } } TEST_CASE("test read & write encrypted data(16 bytes alianed but 32 bytes unaligned)", "[flash_encryption]") @@ -305,6 +332,38 @@ TEST_CASE("test read & write encrypted data(16 bytes alianed but 32 bytes unalig free(cmp_normal_buf); free(cmp_encrypt_buf); + + uint32_t size; + esp_flash_get_physical_size(NULL, &size); + if (size > 0x1000000) { + start = 0x1030000; + TEST_ESP_OK(esp_flash_erase_region(NULL, start, SPI_FLASH_SEC_SIZE)); + do { + start++; + } while ((start % 16) != 0); + + if (start % 32 == 0) { + start += 16; + } + printf("Test data partition @ 0x%" PRIx32 "\n", (uint32_t) start); + ESP_LOG_BUFFER_HEXDUMP(TAG, plainttext_data, sizeof(plainttext_data), ESP_LOG_INFO); + printf("Encrypted writing......\n"); + TEST_ESP_OK(esp_flash_write_encrypted(NULL, start, plainttext_data, sizeof(plainttext_data))); + + cmp_encrypt_buf = heap_caps_malloc(SPI_FLASH_SEC_SIZE, MALLOC_CAP_32BIT | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL); + printf("Encrypted reading......\n"); + TEST_ESP_OK(esp_flash_read_encrypted(NULL, start, cmp_encrypt_buf, SPI_FLASH_SEC_SIZE)); + ESP_LOG_BUFFER_HEXDUMP(TAG, cmp_encrypt_buf, sizeof(plainttext_data), ESP_LOG_INFO); + TEST_ASSERT_EQUAL_HEX8_ARRAY(plainttext_data, cmp_encrypt_buf, sizeof(plainttext_data)); + + cmp_normal_buf = heap_caps_malloc(SPI_FLASH_SEC_SIZE, MALLOC_CAP_32BIT | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL); + TEST_ESP_OK(esp_flash_read(NULL, cmp_normal_buf, start, SPI_FLASH_SEC_SIZE)); + printf("Normal read(esp_flash_read)......\n"); + ESP_LOG_BUFFER_HEXDUMP(TAG, cmp_normal_buf, sizeof(plainttext_data), ESP_LOG_INFO); + + free(cmp_normal_buf); + free(cmp_encrypt_buf); + } } static const uint8_t large_const_buffer[16432] = { @@ -338,6 +397,27 @@ TEST_CASE("test read & write encrypted data with large buffer(n*64+32+16)", "[fl TEST_ESP_OK(esp_flash_read_encrypted(NULL, start, buf, sizeof(large_const_buffer))); TEST_ASSERT_EQUAL_HEX8_ARRAY(buf, large_const_buffer, sizeof(large_const_buffer)); free(buf); + + uint32_t size; + esp_flash_get_physical_size(NULL, &size); + + if (size > 0x1000000) { + start = 0x1030000; + printf("Test data partition @ 0x%" PRIx32 "\n", (uint32_t) start); + TEST_ESP_OK(esp_flash_erase_region(NULL, start, 5 * 4096)); + printf("Encrypted writing......\n"); + + TEST_ESP_OK(ccomp_timer_start()); + TEST_ESP_OK(esp_flash_write_encrypted(NULL, start, large_const_buffer, sizeof(large_const_buffer))); + write_time = ccomp_timer_stop(); + IDF_LOG_PERFORMANCE(TAG, "Writing speed: %.2f us/KB", (double)(write_time/sizeof(large_const_buffer))*1024); + + buf = (uint8_t*)heap_caps_malloc(sizeof(large_const_buffer), MALLOC_CAP_8BIT); + + TEST_ESP_OK(esp_flash_read_encrypted(NULL, start, buf, sizeof(large_const_buffer))); + TEST_ASSERT_EQUAL_HEX8_ARRAY(buf, large_const_buffer, sizeof(large_const_buffer)); + free(buf); + } } static DRAM_ATTR const uint8_t large_const_buffer_dram[16432] = { diff --git a/components/spi_flash/test_apps/flash_encryption/sdkconfig.ci.release_f8r8 b/components/spi_flash/test_apps/flash_encryption/sdkconfig.ci.release_f8r8 index b31f5907ca3..6fab53cf3ad 100644 --- a/components/spi_flash/test_apps/flash_encryption/sdkconfig.ci.release_f8r8 +++ b/components/spi_flash/test_apps/flash_encryption/sdkconfig.ci.release_f8r8 @@ -18,3 +18,4 @@ CONFIG_SPIRAM_MODE_OCT=y CONFIG_SPIRAM_TYPE_AUTO=y CONFIG_ESPTOOLPY_OCT_FLASH=y CONFIG_ESPTOOLPY_FLASHMODE_OPI=y +CONFIG_ESPTOOLPY_FLASHSIZE_32MB=y From 9742007ce01f4f09d9f1c46583c8f5a082ccb3a1 Mon Sep 17 00:00:00 2001 From: morris Date: Tue, 15 Oct 2024 17:26:26 +0800 Subject: [PATCH 158/472] fix(pcnt): install the pm lock upon driver installation --- components/esp_driver_pcnt/src/pulse_cnt.c | 17 ++++++++--------- docs/en/api-reference/peripherals/pcnt.rst | 8 ++++---- docs/zh_CN/api-reference/peripherals/pcnt.rst | 8 ++++---- 3 files changed, 16 insertions(+), 17 deletions(-) diff --git a/components/esp_driver_pcnt/src/pulse_cnt.c b/components/esp_driver_pcnt/src/pulse_cnt.c index 5f50e39acff..0f1148e9fdd 100644 --- a/components/esp_driver_pcnt/src/pulse_cnt.c +++ b/components/esp_driver_pcnt/src/pulse_cnt.c @@ -246,6 +246,14 @@ esp_err_t pcnt_new_unit(const pcnt_unit_config_t *config, pcnt_unit_handle_t *re TAG, "install interrupt service failed"); } + // PCNT uses the APB as its function clock, + // and its filter module is sensitive to the clock frequency +#if CONFIG_PM_ENABLE + sprintf(unit->pm_lock_name, "pcnt_%d_%d", group_id, unit_id); // e.g. pcnt_0_0 + ESP_GOTO_ON_ERROR(esp_pm_lock_create(ESP_PM_APB_FREQ_MAX, 0, unit->pm_lock_name, &unit->pm_lock), err, TAG, "install pm lock failed"); + ESP_LOGD(TAG, "install APB_FREQ_MAX lock for unit (%d,%d)", group_id, unit_id); +#endif + // some events are enabled by default, disable them all pcnt_ll_disable_all_events(group->hal.dev, unit_id); // disable filter by default @@ -375,15 +383,6 @@ esp_err_t pcnt_unit_set_glitch_filter(pcnt_unit_handle_t unit, const pcnt_glitch if (config) { glitch_filter_thres = esp_clk_apb_freq() / 1000000 * config->max_glitch_ns / 1000; ESP_RETURN_ON_FALSE(glitch_filter_thres <= PCNT_LL_MAX_GLITCH_WIDTH, ESP_ERR_INVALID_ARG, TAG, "glitch width out of range"); - - // The filter module is working against APB clock, so lazy install PM lock -#if CONFIG_PM_ENABLE - if (!unit->pm_lock) { - sprintf(unit->pm_lock_name, "pcnt_%d_%d", group->group_id, unit->unit_id); // e.g. pcnt_0_0 - ESP_RETURN_ON_ERROR(esp_pm_lock_create(ESP_PM_APB_FREQ_MAX, 0, unit->pm_lock_name, &unit->pm_lock), TAG, "install pm lock failed"); - ESP_LOGD(TAG, "install APB_FREQ_MAX lock for unit (%d,%d)", group->group_id, unit->unit_id); - } -#endif } // filter control bit is mixed with other PCNT control bits in the same register diff --git a/docs/en/api-reference/peripherals/pcnt.rst b/docs/en/api-reference/peripherals/pcnt.rst index 15478424fe1..3f7d9a12c08 100644 --- a/docs/en/api-reference/peripherals/pcnt.rst +++ b/docs/en/api-reference/peripherals/pcnt.rst @@ -226,7 +226,7 @@ This function should be called when the unit is in the init state. Otherwise, it .. note:: - The glitch filter is clocked from APB. For the counter not to miss any pulses, the maximum glitch width should be longer than one APB_CLK cycle (usually 12.5 ns if APB equals 80 MHz). As the APB frequency would be changed after DFS (Dynamic Frequency Scaling) enabled, which means the filter does not work as expect in that case. So the driver installs a PM lock for PCNT unit during the first time you enable the glitch filter. For more information related to power management strategy used in PCNT driver, please see :ref:`pcnt-power-management`. + The glitch filter operates using the APB clock. To ensure the counter does not miss any pulses, the maximum glitch width should be longer than one APB_CLK cycle (typically 12.5 ns if APB is 80 MHz). Since the APB frequency can change with Dynamic Frequency Scaling (DFS), the filter may not function as expected in such cases. Therefore, the driver installs a power management lock for each PCNT unit. For more details on the power management strategy used in the PCNT driver, please refer to :ref:`pcnt-power-management`. .. code:: c @@ -269,7 +269,7 @@ Before doing IO control to the PCNT unit, you need to enable it first, by callin * switches the PCNT driver state from **init** to **enable**. * enables the interrupt service if it has been lazy installed in :cpp:func:`pcnt_unit_register_event_callbacks`. -* acquires a proper power management lock if it has been lazy installed in :cpp:func:`pcnt_unit_set_glitch_filter`. See also :ref:`pcnt-power-management` for more information. +* acquires a proper power management lock if it has been installed. See also :ref:`pcnt-power-management` for more information. On the contrary, calling :cpp:func:`pcnt_unit_disable` will do the opposite, that is, put the PCNT driver back to the **init** state, disable the interrupts service and release the power management lock. @@ -327,9 +327,9 @@ The internal hardware counter will be cleared to zero automatically when it reac Power Management ^^^^^^^^^^^^^^^^ -When power management is enabled (i.e., :ref:`CONFIG_PM_ENABLE` is on), the system will adjust the APB frequency before going into light sleep, thus potentially changing the behavior of PCNT glitch filter and leading to valid signal being treated as noise. +When power management is enabled (i.e., :ref:`CONFIG_PM_ENABLE` is on), the system adjusts the APB frequency before entering light sleep, which can cause the PCNT glitch filter to misinterpret valid signals as noise. -However, the driver can prevent the system from changing APB frequency by acquiring a power management lock of type :cpp:enumerator:`ESP_PM_APB_FREQ_MAX`. Whenever you enable the glitch filter by :cpp:func:`pcnt_unit_set_glitch_filter`, the driver guarantees that the power management lock is acquired after the PCNT unit is enabled by :cpp:func:`pcnt_unit_enable`. Likewise, the driver releases the lock after :cpp:func:`pcnt_unit_disable` is called. +To prevent this, the driver can acquire a power management lock of type :cpp:enumerator:`ESP_PM_APB_FREQ_MAX`, ensuring the APB frequency remains constant. This lock is acquired when the PCNT unit is enabled via :cpp:func:`pcnt_unit_enable` and released when the unit is disabled via :cpp:func:`pcnt_unit_disable`. .. _pcnt-iram-safe: diff --git a/docs/zh_CN/api-reference/peripherals/pcnt.rst b/docs/zh_CN/api-reference/peripherals/pcnt.rst index 4f4cc2b0858..acd8ed55054 100644 --- a/docs/zh_CN/api-reference/peripherals/pcnt.rst +++ b/docs/zh_CN/api-reference/peripherals/pcnt.rst @@ -226,7 +226,7 @@ PCNT 单元的滤波器可滤除信号中的短时毛刺，:cpp:type:`pcnt_glitc .. note:: - 毛刺滤波器的时钟信息来自 APB。为确保 PCNT 单元不会滤除脉冲信号，最大毛刺宽度应大于一个 APB_CLK 周期（如果 APB 的频率为 80 MHz，则最大毛刺宽度为 12.5 ns）。使能动态频率缩放 (DFS) 后，APB 的频率会发生变化，从而最大毛刺宽度也会发生变化，这会导致计数器无法正常工作。因此，第一次使能毛刺滤波器时，驱动会为 PCNT 单元安装 PM 锁。关于 PCNT 驱动的电源管理的更多信息，请参考 :ref:`pcnt-power-management`。 + 毛刺滤波器的时钟信息来自 APB。为确保 PCNT 单元不会滤除脉冲信号，最大毛刺宽度应大于一个 APB_CLK 周期（如果 APB 的频率为 80 MHz，则最大毛刺宽度为 12.5 ns）。使能动态频率缩放 (DFS) 后，APB 的频率会发生变化，从而最大毛刺宽度也会发生变化，这会导致计数器无法正常工作。因此，驱动会为每个 PCNT 单元安装电源锁。关于 PCNT 驱动的电源管理的更多信息，请参考 :ref:`pcnt-power-management`。 .. code:: c @@ -269,7 +269,7 @@ PCNT 单元的滤波器可滤除信号中的短时毛刺，:cpp:type:`pcnt_glitc * 将 PCNT 单元的驱动状态从 **初始** 切换到 **使能** 。 * 如果中断服务已经在 :cpp:func:`pcnt_unit_register_event_callbacks` 延迟安装，使能中断服务。 -* 如果电源管理锁已经在 :cpp:func:`pcnt_unit_set_glitch_filter` 延迟安装，获取该电源管理锁。请参考 :ref:`pcnt-power-management` 获取更多信息。 +* 如果电源管理锁已经安装，获取该电源管理锁。请参考 :ref:`pcnt-power-management` 获取更多信息。 调用函数 :cpp:func:`pcnt_unit_disable` 会进行相反的操作，即将 PCNT 单元的驱动状态切换回 **初始** 状态，禁用中断服务并释放电源管理锁。 @@ -327,9 +327,9 @@ PCNT 内部的硬件计数器会在计数达到高/低门限的时候自动清 电源管理 ^^^^^^^^^^ -使能电源管理（即 :ref:`CONFIG_PM_ENABLE` 开启）后，在进入 Light-sleep 模式之前，系统会调整 APB 的频率。这会改变 PCNT 毛刺滤波器的参数，从而可能导致有效信号被滤除。 +当电源管理使能（即 :ref:`CONFIG_PM_ENABLE` 开启）时，系统会在进入 Light-sleep 模式之前调整 APB 的频率，这可能导致 PCNT 毛刺滤波器将有效信号误认为噪声。 -驱动通过获取 :cpp:enumerator:`ESP_PM_APB_FREQ_MAX` 类型的电源管理锁来防止系统修改 APB 频率。每当通过 :cpp:func:`pcnt_unit_set_glitch_filter` 使能毛刺滤波器时，驱动可以保证系统在 :cpp:func:`pcnt_unit_enable` 使能 PCNT 单元后获取电源管理锁。而系统调用 :cpp:func:`pcnt_unit_disable` 之后，驱动会释放电源管理锁。 +为了防止这种情况发生，驱动程序可以获取类型为 :cpp:enumerator:`ESP_PM_APB_FREQ_MAX` 的电源管理锁，以确保 APB 频率保持不变。该锁在通过 :cpp:func:`pcnt_unit_enable` 使能 PCNT 单元时获取，并在通过 :cpp:func:`pcnt_unit_disable` 禁用单元时释放。 .. _pcnt-iram-safe: From 8d8b3fc0a25425fdfcec71a038968aad061bbc1a Mon Sep 17 00:00:00 2001 From: "nilesh.kale" Date: Mon, 14 Oct 2024 17:08:51 +0530 Subject: [PATCH 159/472] fix(esp_http_client): Fix ota failure with openssl server If the TLS server (e.g., openssl) closes connection with encrypted close-notify alert then `errno` is not explicitly set on the socket by LwIP stack. For this scenario, we must rely only on `ERR_TCP_TRANSPORT_CONNECTION_CLOSED_BY_FIN` return value as the connection close case and do the graceful connection closure. Closes https://github.com/espressif/esp-idf/issues/14724 --- components/esp_http_client/esp_http_client.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/components/esp_http_client/esp_http_client.c b/components/esp_http_client/esp_http_client.c index 1e642d63dac..c7d2c28ffaf 100644 --- a/components/esp_http_client/esp_http_client.c +++ b/components/esp_http_client/esp_http_client.c @@ -1247,15 +1247,15 @@ int esp_http_client_read(esp_http_client_handle_t client, char *buffer, int len) ESP_LOGD(TAG, "need_read=%d, byte_to_read=%d, rlen=%d, ridx=%d", need_read, byte_to_read, rlen, ridx); if (rlen <= 0) { + esp_log_level_t sev = ESP_LOG_WARN; + /* Check for cleanly closed connection */ + if (rlen == ERR_TCP_TRANSPORT_CONNECTION_CLOSED_BY_FIN && client->response->is_chunked) { + /* Explicit call to parser for invoking `message_complete` callback */ + http_parser_execute(client->parser, client->parser_settings, res_buffer->data, 0); + /* ...and lowering the message severity, as closed connection from server side is expected in chunked transport */ + sev = ESP_LOG_DEBUG; + } if (errno != 0) { - esp_log_level_t sev = ESP_LOG_WARN; - /* Check for cleanly closed connection */ - if (rlen == ERR_TCP_TRANSPORT_CONNECTION_CLOSED_BY_FIN && client->response->is_chunked) { - /* Explicit call to parser for invoking `message_complete` callback */ - http_parser_execute(client->parser, client->parser_settings, res_buffer->data, 0); - /* ...and lowering the message severity, as closed connection from server side is expected in chunked transport */ - sev = ESP_LOG_DEBUG; - } ESP_LOG_LEVEL(sev, TAG, "esp_transport_read returned:%d and errno:%d ", rlen, errno); } From d66442b74a9daddcc6c32b87dce4704f49288ca1 Mon Sep 17 00:00:00 2001 From: "nilesh.kale" Date: Tue, 15 Oct 2024 17:25:03 +0530 Subject: [PATCH 160/472] fix(esp_http_server): updated condition to verify http version Closes https://github.com/espressif/esp-idf/issues/14723 --- components/esp_http_server/src/httpd_parse.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/components/esp_http_server/src/httpd_parse.c b/components/esp_http_server/src/httpd_parse.c index 3d76380a8b4..2fbc37f3eb8 100644 --- a/components/esp_http_server/src/httpd_parse.c +++ b/components/esp_http_server/src/httpd_parse.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2018-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2018-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -86,7 +86,7 @@ static esp_err_t verify_url (http_parser *parser) ESP_LOGD(TAG, LOG_FMT("received URI = %s"), r->uri); /* Make sure version is HTTP/1.1 */ - if ((parser->http_major != 1) && (parser->http_minor != 1)) { + if (!((parser->http_major == 1) && (parser->http_minor == 1))) { ESP_LOGW(TAG, LOG_FMT("unsupported HTTP version = %d.%d"), parser->http_major, parser->http_minor); parser_data->error = HTTPD_505_VERSION_NOT_SUPPORTED; @@ -106,7 +106,7 @@ static esp_err_t verify_url (http_parser *parser) } /* http_parser callback on finding url in HTTP request - * Will be invoked ATLEAST once every packet + * Will be invoked AT LEAST once every packet */ static esp_err_t cb_url(http_parser *parser, const char *at, size_t length) @@ -191,7 +191,7 @@ static size_t continue_parsing(http_parser *parser, size_t length) } /* http_parser callback on header field in HTTP request - * May be invoked ATLEAST once every header field + * May be invoked AT LEAST once every header field */ static esp_err_t cb_header_field(http_parser *parser, const char *at, size_t length) { @@ -250,7 +250,7 @@ static esp_err_t cb_header_field(http_parser *parser, const char *at, size_t len } /* http_parser callback on header value in HTTP request. - * May be invoked ATLEAST once every header value + * May be invoked AT LEAST once every header value */ static esp_err_t cb_header_value(http_parser *parser, const char *at, size_t length) { From b4c501374f9e88adc20c4dda8d9281fc51d95b5d Mon Sep 17 00:00:00 2001 From: Marius Vikhammer Date: Mon, 1 Jul 2024 16:56:44 +0800 Subject: [PATCH 161/472] feat(lp_core): added support for LP-IO as LP-core wakeup source --- .../hal/esp32c6/include/hal/rtc_io_ll.h | 8 ++ components/ulp/lp_core/lp_core.c | 2 +- examples/system/.build-test-rules.yml | 6 ++ .../ulp/lp_core/gpio_wakeup/CMakeLists.txt | 6 ++ .../system/ulp/lp_core/gpio_wakeup/README.md | 26 ++++++ .../lp_core/gpio_wakeup/main/CMakeLists.txt | 27 ++++++ .../main/lp_core_gpio_wake_up_example_main.c | 86 +++++++++++++++++++ .../ulp/lp_core/gpio_wakeup/main/ulp/main.c | 23 +++++ .../lp_core/gpio_wakeup/sdkconfig.defaults | 9 ++ 9 files changed, 192 insertions(+), 1 deletion(-) create mode 100644 examples/system/ulp/lp_core/gpio_wakeup/CMakeLists.txt create mode 100644 examples/system/ulp/lp_core/gpio_wakeup/README.md create mode 100644 examples/system/ulp/lp_core/gpio_wakeup/main/CMakeLists.txt create mode 100644 examples/system/ulp/lp_core/gpio_wakeup/main/lp_core_gpio_wake_up_example_main.c create mode 100644 examples/system/ulp/lp_core/gpio_wakeup/main/ulp/main.c create mode 100644 examples/system/ulp/lp_core/gpio_wakeup/sdkconfig.defaults diff --git a/components/hal/esp32c6/include/hal/rtc_io_ll.h b/components/hal/esp32c6/include/hal/rtc_io_ll.h index 0cd64df36d5..6fcac4cd406 100644 --- a/components/hal/esp32c6/include/hal/rtc_io_ll.h +++ b/components/hal/esp32c6/include/hal/rtc_io_ll.h @@ -309,6 +309,14 @@ static inline void rtcio_ll_wakeup_enable(int rtcio_num, rtcio_ll_wake_type_t ty { LP_IO.pin[rtcio_num].wakeup_enable = 1; LP_IO.pin[rtcio_num].int_type = type; + + /* Work around for HW issue, + need to also enable this clk, otherwise it will + not trigger a wake-up on the ULP. This is not needed + for triggering a wakeup on HP CPU, but always setting this + has no side-effects. + */ + LP_IO.date.clk_en = 1; } /** diff --git a/components/ulp/lp_core/lp_core.c b/components/ulp/lp_core/lp_core.c index aedcf0e78e2..50e019ad26a 100644 --- a/components/ulp/lp_core/lp_core.c +++ b/components/ulp/lp_core/lp_core.c @@ -130,7 +130,7 @@ esp_err_t ulp_lp_core_run(ulp_lp_core_cfg_t* cfg) } #endif - if (cfg->wakeup_source & (ULP_LP_CORE_WAKEUP_SOURCE_LP_UART | ULP_LP_CORE_WAKEUP_SOURCE_LP_IO)) { + if (cfg->wakeup_source & (ULP_LP_CORE_WAKEUP_SOURCE_LP_UART)) { ESP_LOGE(TAG, "Wake-up source not yet supported"); return ESP_ERR_INVALID_ARG; } diff --git a/examples/system/.build-test-rules.yml b/examples/system/.build-test-rules.yml index ddb33070ef0..c4a9e2b3d58 100644 --- a/examples/system/.build-test-rules.yml +++ b/examples/system/.build-test-rules.yml @@ -299,6 +299,12 @@ examples/system/ulp/lp_core/gpio_intr_pulse_counter: depends_components: - ulp +examples/system/ulp/lp_core/gpio_wakeup: + enable: + - if: (SOC_LP_CORE_SUPPORTED == 1) and (SOC_RTCIO_PIN_COUNT > 0) + depends_components: + - ulp + examples/system/ulp/lp_core/inter_cpu_critical_section/: enable: - if: SOC_LP_CORE_SUPPORTED == 1 diff --git a/examples/system/ulp/lp_core/gpio_wakeup/CMakeLists.txt b/examples/system/ulp/lp_core/gpio_wakeup/CMakeLists.txt new file mode 100644 index 00000000000..8c1a422f3f4 --- /dev/null +++ b/examples/system/ulp/lp_core/gpio_wakeup/CMakeLists.txt @@ -0,0 +1,6 @@ +# The following lines of boilerplate have to be in your project's CMakeLists +# in this exact order for cmake to work correctly +cmake_minimum_required(VERSION 3.16) + +include($ENV{IDF_PATH}/tools/cmake/project.cmake) +project(ulp_lp_core_gpio_wakeup_example) diff --git a/examples/system/ulp/lp_core/gpio_wakeup/README.md b/examples/system/ulp/lp_core/gpio_wakeup/README.md new file mode 100644 index 00000000000..66925750726 --- /dev/null +++ b/examples/system/ulp/lp_core/gpio_wakeup/README.md @@ -0,0 +1,26 @@ +| Supported Targets | ESP32-C5 | ESP32-C6 | ESP32-P4 | +| ----------------- | -------- | -------- | -------- | +# ULP-LP-Core simple example with GPIO Interrupt: + +This example demonstrates how to program the LP-Core coprocessor to wake up from a RTC IO interrupt, instead of waking periodically from the ULP timer. + +ULP program written in C can be found across `ulp/main.c`. The build system compiles and links this program, converts it into binary format, and embeds it into the .rodata section of the ESP-IDF application. + +At runtime, the main code running on the ESP (found in lp_core_gpio_wake_up_example_main.c) loads ULP program into the `RTC_SLOW_MEM` memory region using `ulp_lp_core_load_binary` function. The main code then configures the ULP GPIO wakeup source and starts the coprocessor by using `ulp_lp_core_run` followed by putting the chip into deep sleep mode. + +When the wakeup source pin is pulled low the LP-Core coprocessor is woken up, sends a wakeup signal to the main CPU and goes back to sleep again. + +In this example the input signal is connected to GPIO2. To change the pin number, check the Chip Pin List document and adjust `WAKEUP_PIN` variable in main.c. + + +## Example output + +``` +Not a LP-Core wakeup, initializing it! +Entering deep sleep + +... + +LP-Core woke up the main CPU! +Entering deep sleep +``` diff --git a/examples/system/ulp/lp_core/gpio_wakeup/main/CMakeLists.txt b/examples/system/ulp/lp_core/gpio_wakeup/main/CMakeLists.txt new file mode 100644 index 00000000000..9970ae3effb --- /dev/null +++ b/examples/system/ulp/lp_core/gpio_wakeup/main/CMakeLists.txt @@ -0,0 +1,27 @@ +# Set usual component variables +set(COMPONENT_SRCS "lp_core_gpio_wake_up_example_main.c") +set(COMPONENT_ADD_INCLUDEDIRS "") +set(COMPONENT_REQUIRES ulp driver) + +register_component() + +# +# ULP support additions to component CMakeLists.txt. +# +# 1. The ULP app name must be unique (if multiple components use ULP). +set(ulp_app_name ulp_${COMPONENT_NAME}) +# +# 2. Specify all C and Assembly source files. +# Files should be placed into a separate directory (in this case, ulp/), +# which should not be added to COMPONENT_SRCS. +set(ulp_riscv_sources "ulp/main.c") + +# +# 3. List all the component source files which include automatically +# generated ULP export file, ${ulp_app_name}.h: +set(ulp_exp_dep_srcs "lp_core_gpio_wake_up_example_main.c") + +# +# 4. Call function to build ULP binary and embed in project using the argument +# values above. +ulp_embed_binary(${ulp_app_name} "${ulp_riscv_sources}" "${ulp_exp_dep_srcs}") diff --git a/examples/system/ulp/lp_core/gpio_wakeup/main/lp_core_gpio_wake_up_example_main.c b/examples/system/ulp/lp_core/gpio_wakeup/main/lp_core_gpio_wake_up_example_main.c new file mode 100644 index 00000000000..7de67d59c36 --- /dev/null +++ b/examples/system/ulp/lp_core/gpio_wakeup/main/lp_core_gpio_wake_up_example_main.c @@ -0,0 +1,86 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Unlicense OR CC0-1.0 + */ +/* ULP LP-Core GPIO wake-up example + + This example code is in the Public Domain (or CC0 licensed, at your option.) + + Unless required by applicable law or agreed to in writing, this + software is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR + CONDITIONS OF ANY KIND, either express or implied. +*/ + +#include +#include "esp_sleep.h" +#include "driver/rtc_io.h" +#include "ulp_lp_core.h" +#include "ulp_main.h" +#include "freertos/FreeRTOS.h" +#include "freertos/task.h" + +#define WAKEUP_PIN 2 + +extern const uint8_t ulp_main_bin_start[] asm("_binary_ulp_main_bin_start"); +extern const uint8_t ulp_main_bin_end[] asm("_binary_ulp_main_bin_end"); + +static void init_ulp_program(void); + +static void wakeup_gpio_init(void) +{ + /* Configure the button GPIO as input, enable wakeup */ + rtc_gpio_init(WAKEUP_PIN); + rtc_gpio_set_direction(WAKEUP_PIN, RTC_GPIO_MODE_INPUT_ONLY); + rtc_gpio_pulldown_dis(WAKEUP_PIN); + rtc_gpio_pullup_en(WAKEUP_PIN); + rtc_gpio_wakeup_enable(WAKEUP_PIN, GPIO_INTR_LOW_LEVEL); +} + +void app_main(void) +{ + /* If user is using USB-serial-jtag then idf monitor needs some time to + * re-connect to the USB port. We wait 1 sec here to allow for it to make the reconnection + * before we print anything. Otherwise the chip will go back to sleep again before the user + * has time to monitor any output. + */ + vTaskDelay(pdMS_TO_TICKS(1000)); + + wakeup_gpio_init(); + + esp_sleep_wakeup_cause_t cause = esp_sleep_get_wakeup_cause(); + /* not a wakeup from ULP, load the firmware */ + if (cause != ESP_SLEEP_WAKEUP_ULP) { + printf("Not a ULP wakeup, initializing it! \n"); + init_ulp_program(); + } + + /* ULP read and detected a change in WAKEUP_PIN, prints */ + if (cause == ESP_SLEEP_WAKEUP_ULP) { + printf("ULP woke up the main CPU! \n"); + } + + /* Go back to sleep, only the ULP will run */ + printf("Entering deep sleep\n\n"); + + /* Small delay to ensure the messages are printed */ + vTaskDelay(100 / portTICK_PERIOD_MS); + + ESP_ERROR_CHECK( esp_sleep_enable_ulp_wakeup()); + + esp_deep_sleep_start(); +} + +static void init_ulp_program(void) +{ + esp_err_t err = ulp_lp_core_load_binary(ulp_main_bin_start, (ulp_main_bin_end - ulp_main_bin_start)); + ESP_ERROR_CHECK(err); + + /* Start the program */ + ulp_lp_core_cfg_t cfg = { + .wakeup_source = ULP_LP_CORE_WAKEUP_SOURCE_LP_IO, + }; + + err = ulp_lp_core_run(&cfg); + ESP_ERROR_CHECK(err); +} diff --git a/examples/system/ulp/lp_core/gpio_wakeup/main/ulp/main.c b/examples/system/ulp/lp_core/gpio_wakeup/main/ulp/main.c new file mode 100644 index 00000000000..0f630ddc0cc --- /dev/null +++ b/examples/system/ulp/lp_core/gpio_wakeup/main/ulp/main.c @@ -0,0 +1,23 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Unlicense OR CC0-1.0 + */ +#include +#include +#include "ulp_lp_core.h" +#include "ulp_lp_core_utils.h" +#include "ulp_lp_core_gpio.h" + + +int main (void) +{ + ulp_lp_core_wakeup_main_processor(); + + /* Wakeup interrupt is a level interrupt, wait 1 sec to + allow user to release button to avoid waking up the ULP multiple times */ + ulp_lp_core_delay_us(1000*1000); + ulp_lp_core_gpio_clear_intr_status(); + + return 0; +} diff --git a/examples/system/ulp/lp_core/gpio_wakeup/sdkconfig.defaults b/examples/system/ulp/lp_core/gpio_wakeup/sdkconfig.defaults new file mode 100644 index 00000000000..456833bc8c3 --- /dev/null +++ b/examples/system/ulp/lp_core/gpio_wakeup/sdkconfig.defaults @@ -0,0 +1,9 @@ +# Enable ULP +CONFIG_ULP_COPROC_ENABLED=y +CONFIG_ULP_COPROC_TYPE_LP_CORE=y +CONFIG_ULP_COPROC_RESERVE_MEM=8128 +# Set log level to Warning to produce clean output +CONFIG_BOOTLOADER_LOG_LEVEL_WARN=y +CONFIG_BOOTLOADER_LOG_LEVEL=2 +CONFIG_LOG_DEFAULT_LEVEL_WARN=y +CONFIG_LOG_DEFAULT_LEVEL=2 From 3b8bd7b60838f921c944f146b70a8827ea55ab41 Mon Sep 17 00:00:00 2001 From: liuning Date: Mon, 23 Sep 2024 20:18:43 +0800 Subject: [PATCH 162/472] fix(coex): fix some coexist debug issues --- .../include/private/esp_coexist_debug.h | 11 ++++- components/esp_coex/src/coexist_debug.c | 49 ++++++++++--------- 2 files changed, 34 insertions(+), 26 deletions(-) diff --git a/components/esp_coex/include/private/esp_coexist_debug.h b/components/esp_coex/include/private/esp_coexist_debug.h index 26147262c75..80bfbbd5aa6 100644 --- a/components/esp_coex/include/private/esp_coexist_debug.h +++ b/components/esp_coex/include/private/esp_coexist_debug.h @@ -108,7 +108,7 @@ typedef enum { #endif /* wifi callback -> debug */ -void wifi_set_gpio_debug_cb(void (* cb)(int, int)); +void wifi_set_gpio_debug_cb(void (* cb)(int, coex_gpio_debug_sig_t)); int wifi_gpio_debug_max_event_get(void); /* functions to check if in ROM */ @@ -128,9 +128,10 @@ void pm_check_state(void); void pm_tx_null_data_done_process(void); void pm_start(void); void pm_stop(void); +void pm_disconnected_wake(void); /* coex callback -> debug */ -void coex_set_gpio_debug_cb(void (*cb)(int, int)); +void coex_set_gpio_debug_cb(void (*cb)(int, coex_gpio_debug_sig_t)); int coex_gpio_debug_max_event_get(void); esp_err_t coex_gpio_debug_matrix_init(void); @@ -142,4 +143,10 @@ void wifi_bind_io_to_evt(uint8_t io_idx, uint8_t evt); void coex_bind_io_to_evt(uint8_t io_idx, uint8_t evt); void diagram_bind_io_to_evt(void); +/* coex -> debug + * configure single gpio debug event */ +esp_err_t coex_gpio_debug_matrix_config(int event); +/* debug -> internal use */ +esp_err_t esp_coexist_gpio_debug_matrix_config(int event); + #endif diff --git a/components/esp_coex/src/coexist_debug.c b/components/esp_coex/src/coexist_debug.c index 317f7c4547e..8ef1eb6de16 100644 --- a/components/esp_coex/src/coexist_debug.c +++ b/components/esp_coex/src/coexist_debug.c @@ -13,37 +13,20 @@ #include "esp_attr.h" #include "esp_log.h" -#if CONFIG_IDF_TARGET_ESP32 -#include "esp32/rom/gpio.h" -#include "esp32/rom/ets_sys.h" -#elif defined(CONFIG_IDF_TARGET_ESP32S2) -#include "esp32s2/rom/gpio.h" -#include "esp32s2/rom/ets_sys.h" -#elif defined(CONFIG_IDF_TARGET_ESP32C3) -#include "esp32c3/rom/gpio.h" -#include "esp32c3/rom/ets_sys.h" -#elif defined(CONFIG_IDF_TARGET_ESP32C2) -#include "esp32c2/rom/gpio.h" -#include "esp32c2/rom/ets_sys.h" -#elif defined(CONFIG_IDF_TARGET_ESP32C6) -#include "esp32c6/rom/gpio.h" -#include "esp32c6/rom/ets_sys.h" -#elif defined(CONFIG_IDF_TARGET_ESP32C5) -#include "esp32c5/rom/gpio.h" -#include "esp32c5/rom/ets_sys.h" -#elif defined(CONFIG_IDF_TARGET_ESP32C61) -#include "esp32c61/rom/gpio.h" -#include "esp32c61/rom/ets_sys.h" -#endif +#include "rom/gpio.h" +#include "rom/ets_sys.h" #include "driver/gpio.h" #include "soc/gpio_sig_map.h" #include "esp_rom_gpio.h" #include "soc/soc.h" +#if SOC_MODEM_CLOCK_IS_INDEPENDENT +#include "esp_private/esp_modem_clock.h" +#endif #if CONFIG_ESP_COEX_GPIO_DEBUG static char* TAG = "coexist debug"; -__attribute__((weak)) void wifi_set_gpio_debug_cb(void (* cb)(int, int)) +__attribute__((weak)) void wifi_set_gpio_debug_cb(void (* cb)(int, coex_gpio_debug_sig_t)) { ESP_LOGW(TAG, "Not support: %s", __FUNCTION__); } @@ -53,7 +36,7 @@ __attribute__((weak)) int wifi_gpio_debug_max_event_get(void) return 0; } -__attribute__((weak)) void coex_set_gpio_debug_cb(void (*cb)(int, int)) +__attribute__((weak)) void coex_set_gpio_debug_cb(void (*cb)(int, coex_gpio_debug_sig_t)) { ESP_LOGW(TAG, "Not support: %s", __FUNCTION__); } @@ -207,6 +190,18 @@ esp_err_t esp_coexist_debug_matrix_init(int evt, int sig, bool rev) return ESP_OK; } +esp_err_t esp_coexist_gpio_debug_matrix_config(int event) +{ +#if SOC_MODEM_CLOCK_IS_INDEPENDENT + modem_clock_module_enable(PERIPH_COEX_MODULE); +#endif + esp_err_t ret = coex_gpio_debug_matrix_config(event); +#if SOC_MODEM_CLOCK_IS_INDEPENDENT + modem_clock_module_disable(PERIPH_COEX_MODULE); +#endif + return ret; +} + esp_err_t esp_coexist_debug_init(void) { if (check_funcs_in_rom()) { @@ -270,8 +265,14 @@ esp_err_t esp_coexist_debug_init(void) gpio_set_level(s_io_nums[i], false); } +#if SOC_MODEM_CLOCK_IS_INDEPENDENT + modem_clock_module_enable(PERIPH_COEX_MODULE); +#endif /* Init coexist hardware signal */ ESP_ERROR_CHECK(coex_gpio_debug_matrix_init()); +#if SOC_MODEM_CLOCK_IS_INDEPENDENT + modem_clock_module_disable(PERIPH_COEX_MODULE); +#endif return ESP_OK; } From 18f959623c558c799edb840b9c1a6d9dcd1a64e4 Mon Sep 17 00:00:00 2001 From: liuning Date: Fri, 11 Oct 2024 15:53:55 +0800 Subject: [PATCH 163/472] fix(coex): fix esp32c5 coexist hw timer issue --- components/esp_coex/esp32c2/esp_coex_adapter.c | 6 ++++++ components/esp_coex/esp32c5/esp_coex_adapter.c | 6 ++++++ components/esp_coex/esp32c6/esp_coex_adapter.c | 6 ++++++ components/esp_coex/esp32c61/esp_coex_adapter.c | 8 +++++++- components/esp_coex/esp32h2/esp_coex_adapter.c | 6 ++++++ components/esp_coex/include/private/esp_coexist_adapter.h | 1 + 6 files changed, 32 insertions(+), 1 deletion(-) diff --git a/components/esp_coex/esp32c2/esp_coex_adapter.c b/components/esp_coex/esp32c2/esp_coex_adapter.c index 4954fb9f850..b98c9c94742 100644 --- a/components/esp_coex/esp32c2/esp_coex_adapter.c +++ b/components/esp_coex/esp32c2/esp_coex_adapter.c @@ -152,6 +152,11 @@ static int esp_coexist_debug_matrix_init_wrapper(int evt, int sig, bool rev) #endif } +static IRAM_ATTR int esp_coex_common_xtal_freq_get_wrapper(void) +{ + return rtc_clk_xtal_freq_get(); +} + coex_adapter_funcs_t g_coex_adapter_funcs = { ._version = COEX_ADAPTER_VERSION, ._task_yield_from_isr = esp_coex_common_task_yield_from_isr_wrapper, @@ -172,5 +177,6 @@ coex_adapter_funcs_t g_coex_adapter_funcs = { ._timer_setfn = esp_coex_common_timer_setfn_wrapper, ._timer_arm_us = esp_coex_common_timer_arm_us_wrapper, ._debug_matrix_init = esp_coexist_debug_matrix_init_wrapper, + ._xtal_freq_get = esp_coex_common_xtal_freq_get_wrapper, ._magic = COEX_ADAPTER_MAGIC, }; diff --git a/components/esp_coex/esp32c5/esp_coex_adapter.c b/components/esp_coex/esp32c5/esp_coex_adapter.c index b5e761ffbd9..8588b7348d1 100644 --- a/components/esp_coex/esp32c5/esp_coex_adapter.c +++ b/components/esp_coex/esp32c5/esp_coex_adapter.c @@ -151,6 +151,11 @@ static int esp_coexist_debug_matrix_init_wrapper(int evt, int sig, bool rev) #endif } +static IRAM_ATTR int esp_coex_common_xtal_freq_get_wrapper(void) +{ + return rtc_clk_xtal_freq_get(); +} + coex_adapter_funcs_t g_coex_adapter_funcs = { ._version = COEX_ADAPTER_VERSION, ._task_yield_from_isr = esp_coex_common_task_yield_from_isr_wrapper, @@ -170,5 +175,6 @@ coex_adapter_funcs_t g_coex_adapter_funcs = { ._timer_setfn = esp_coex_common_timer_setfn_wrapper, ._timer_arm_us = esp_coex_common_timer_arm_us_wrapper, ._debug_matrix_init = esp_coexist_debug_matrix_init_wrapper, + ._xtal_freq_get = esp_coex_common_xtal_freq_get_wrapper, ._magic = COEX_ADAPTER_MAGIC, }; diff --git a/components/esp_coex/esp32c6/esp_coex_adapter.c b/components/esp_coex/esp32c6/esp_coex_adapter.c index 81b4eef2b1e..4b920ce1595 100644 --- a/components/esp_coex/esp32c6/esp_coex_adapter.c +++ b/components/esp_coex/esp32c6/esp_coex_adapter.c @@ -152,6 +152,11 @@ static int esp_coexist_debug_matrix_init_wrapper(int evt, int sig, bool rev) #endif } +static IRAM_ATTR int esp_coex_common_xtal_freq_get_wrapper(void) +{ + return rtc_clk_xtal_freq_get(); +} + coex_adapter_funcs_t g_coex_adapter_funcs = { ._version = COEX_ADAPTER_VERSION, ._task_yield_from_isr = esp_coex_common_task_yield_from_isr_wrapper, @@ -171,5 +176,6 @@ coex_adapter_funcs_t g_coex_adapter_funcs = { ._timer_setfn = esp_coex_common_timer_setfn_wrapper, ._timer_arm_us = esp_coex_common_timer_arm_us_wrapper, ._debug_matrix_init = esp_coexist_debug_matrix_init_wrapper, + ._xtal_freq_get = esp_coex_common_xtal_freq_get_wrapper, ._magic = COEX_ADAPTER_MAGIC, }; diff --git a/components/esp_coex/esp32c61/esp_coex_adapter.c b/components/esp_coex/esp32c61/esp_coex_adapter.c index 547e1dbd363..059160f7bab 100644 --- a/components/esp_coex/esp32c61/esp_coex_adapter.c +++ b/components/esp_coex/esp32c61/esp_coex_adapter.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -152,6 +152,11 @@ static int esp_coexist_debug_matrix_init_wrapper(int evt, int sig, bool rev) #endif } +static IRAM_ATTR int esp_coex_common_xtal_freq_get_wrapper(void) +{ + return rtc_clk_xtal_freq_get(); +} + coex_adapter_funcs_t g_coex_adapter_funcs = { ._version = COEX_ADAPTER_VERSION, ._task_yield_from_isr = esp_coex_common_task_yield_from_isr_wrapper, @@ -171,5 +176,6 @@ coex_adapter_funcs_t g_coex_adapter_funcs = { ._timer_setfn = esp_coex_common_timer_setfn_wrapper, ._timer_arm_us = esp_coex_common_timer_arm_us_wrapper, ._debug_matrix_init = esp_coexist_debug_matrix_init_wrapper, + ._xtal_freq_get = esp_coex_common_xtal_freq_get_wrapper, ._magic = COEX_ADAPTER_MAGIC, }; diff --git a/components/esp_coex/esp32h2/esp_coex_adapter.c b/components/esp_coex/esp32h2/esp_coex_adapter.c index f00cade6f6b..1fa2243ae9a 100644 --- a/components/esp_coex/esp32h2/esp_coex_adapter.c +++ b/components/esp_coex/esp32h2/esp_coex_adapter.c @@ -144,6 +144,11 @@ static int esp_coexist_debug_matrix_init_wrapper(int evt, int sig, bool rev) #endif } +static IRAM_ATTR int esp_coex_common_xtal_freq_get_wrapper(void) +{ + return rtc_clk_xtal_freq_get(); +} + coex_adapter_funcs_t g_coex_adapter_funcs = { ._version = COEX_ADAPTER_VERSION, ._task_yield_from_isr = esp_coex_common_task_yield_from_isr_wrapper, @@ -163,5 +168,6 @@ coex_adapter_funcs_t g_coex_adapter_funcs = { ._timer_setfn = esp_coex_common_timer_setfn_wrapper, ._timer_arm_us = esp_coex_common_timer_arm_us_wrapper, ._debug_matrix_init = esp_coexist_debug_matrix_init_wrapper, + ._xtal_freq_get = esp_coex_common_xtal_freq_get_wrapper, ._magic = COEX_ADAPTER_MAGIC, }; diff --git a/components/esp_coex/include/private/esp_coexist_adapter.h b/components/esp_coex/include/private/esp_coexist_adapter.h index aca50a6161a..15e8ef7114f 100644 --- a/components/esp_coex/include/private/esp_coexist_adapter.h +++ b/components/esp_coex/include/private/esp_coexist_adapter.h @@ -47,6 +47,7 @@ typedef struct { void (* _timer_setfn)(void *ptimer, void *pfunction, void *parg); void (* _timer_arm_us)(void *ptimer, uint32_t us, bool repeat); int (* _debug_matrix_init)(int event, int signal, bool rev); + int (* _xtal_freq_get)(void); int32_t _magic; } coex_adapter_funcs_t; From 05173abc43e844aad1169e7ea40fd582cb0b4d79 Mon Sep 17 00:00:00 2001 From: liuning Date: Fri, 11 Oct 2024 15:55:28 +0800 Subject: [PATCH 164/472] fix(coex): sync up coex head file --- components/esp_coex/test_md5/test_md5.sh | 54 +++++++++++++++++++----- 1 file changed, 44 insertions(+), 10 deletions(-) diff --git a/components/esp_coex/test_md5/test_md5.sh b/components/esp_coex/test_md5/test_md5.sh index 24f80b76e3b..429796bdfa7 100755 --- a/components/esp_coex/test_md5/test_md5.sh +++ b/components/esp_coex/test_md5/test_md5.sh @@ -32,40 +32,74 @@ case $IDF_TARGET in esac LIB_DIR=${IDF_TARGET} -ELF_FILE=test.elf +COEX_ELF_FILE=coex.elf +TEST_ELF_FILE=test.elf FAILURES=0 function check_md5() +{ + if [ "$1" != "$2" ]; then + echo " error: MD5 mismatch!" + FAILURES=$(($FAILURES+1)) + fi +} + +function check_md5_file_lib() { FILENAME=$1 SYMBOL=$2 - ${PREFIX}ld --unresolved-symbols=ignore-all --entry 0 -o ${ELF_FILE} \ + ${PREFIX}ld --unresolved-symbols=ignore-all --entry 0 -o ${COEX_ELF_FILE} \ -u ${SYMBOL} \ ${IDF_PATH}/components/esp_coex/lib/${LIB_DIR}/*.a GDB_COMMAND="printf \"%s\\n\", (const char*) ${SYMBOL}" - MD5_FROM_LIB=$(${PREFIX}gdb -n -batch ${ELF_FILE} -ex "${GDB_COMMAND}") + MD5_FROM_LIB=$(${PREFIX}gdb -n -batch ${COEX_ELF_FILE} -ex "${GDB_COMMAND}") MD5_FROM_HEADER=$(md5sum ${FILENAME} | cut -c 1-7) - echo "Checking ${FILENAME}:" echo " ${MD5_FROM_HEADER} - from header file" echo " ${MD5_FROM_LIB} - from library" - if [ "${MD5_FROM_LIB}" != "${MD5_FROM_HEADER}" ]; then - echo " error: MD5 mismatch!" - FAILURES=$(($FAILURES+1)) - fi + check_md5 ${MD5_FROM_HEADER} ${MD5_FROM_LIB} +} + +function check_md5_libs() +{ + COEX_SYMBOL=$1 + TEST_SYMBOL=$2 + TEST_PATH=$3 + + ${PREFIX}ld --unresolved-symbols=ignore-all --entry 0 -o ${COEX_ELF_FILE} \ + -u ${COEX_SYMBOL} \ + ${IDF_PATH}/components/esp_coex/lib/${LIB_DIR}/*.a + + ${PREFIX}ld --unresolved-symbols=ignore-all --entry 0 -o ${TEST_ELF_FILE} \ + -u ${TEST_SYMBOL} \ + ${TEST_PATH}/*.a + + COEX_GDB_COMMAND="printf \"%s\\n\", (const char*) ${COEX_SYMBOL}" + TEST_GDB_COMMAND="printf \"%s\\n\", (const char*) ${TEST_SYMBOL}" + COEX_MD5_FROM_LIB=$(${PREFIX}gdb -n -batch ${COEX_ELF_FILE} -ex "${COEX_GDB_COMMAND}") + TEST_MD5_FROM_LIB=$(${PREFIX}gdb -n -batch ${TEST_ELF_FILE} -ex "${TEST_GDB_COMMAND}") + + echo "Checking ${TEST_PATH}/${TEST_SYMBOL} " + echo " ${COEX_MD5_FROM_LIB} - from coexist library" + echo " ${TEST_MD5_FROM_LIB} - from test library" + check_md5 ${COEX_MD5_FROM_LIB} ${TEST_MD5_FROM_LIB} } echo "Checking libraries for target ${IDF_TARGET}..." -check_md5 ${IDF_PATH}/components/esp_coex/include/private/esp_coexist_adapter.h g_coex_adapter_funcs_md5 +check_md5_file_lib ${IDF_PATH}/components/esp_coex/include/private/esp_coexist_adapter.h g_coex_adapter_funcs_md5 case $IDF_TARGET in esp32c6|esp32h2|esp32c5) - check_md5 ${IDF_PATH}/components/esp_coex/include/esp_coex_i154.h g_coex_i154_funcs_md5 + check_md5_file_lib ${IDF_PATH}/components/esp_coex/include/esp_coex_i154.h g_coex_i154_funcs_md5 ;; esac +if [[ ! "$IDF_TARGET" =~ ^(esp32h2)$ ]]; then + check_md5_libs g_coex_basic_md5 g_wifi_coex_basic_md5 ${IDF_PATH}/components/esp_wifi/lib/${LIB_DIR} +fi + if [ $FAILURES -gt 0 ]; then exit 1 fi From 99dbcf536c0a6f5afedbe8353acb5ca53b45356e Mon Sep 17 00:00:00 2001 From: liuning Date: Fri, 11 Oct 2024 17:57:14 +0800 Subject: [PATCH 165/472] fix(coex): fix esp32c2/esp32c5/esp32c61 coexist memory leakage issue --- components/esp_coex/lib | 2 +- components/esp_rom/esp32c2/ld/esp32c2.rom.ld | 2 +- components/esp_rom/esp32c5/ld/esp32c5.rom.pp.ld | 2 +- components/esp_rom/esp32c61/ld/esp32c61.rom.pp.ld | 2 +- components/esp_wifi/lib | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/components/esp_coex/lib b/components/esp_coex/lib index e15e7a161fc..9baa4202b6b 160000 --- a/components/esp_coex/lib +++ b/components/esp_coex/lib @@ -1 +1 @@ -Subproject commit e15e7a161fc1a48e8fb4fd0b3da74623c30ba1cb +Subproject commit 9baa4202b6bddac85aa5f318c171a1b413e2caea diff --git a/components/esp_rom/esp32c2/ld/esp32c2.rom.ld b/components/esp_rom/esp32c2/ld/esp32c2.rom.ld index dd40a0253b9..2abe48222a5 100644 --- a/components/esp_rom/esp32c2/ld/esp32c2.rom.ld +++ b/components/esp_rom/esp32c2/ld/esp32c2.rom.ld @@ -1623,7 +1623,7 @@ dbg_lmac_rxtx_statis_dump = 0x40001e90; dbg_lmac_hw_statis_dump = 0x40001e94; dbg_lmac_diag_statis_dump = 0x40001e98; dbg_lmac_ps_statis_dump = 0x40001e9c; -pp_timer_do_process = 0x40001ea0; +/*pp_timer_do_process = 0x40001ea0;*/ rcUpdateAMPDUParam = 0x40001ea4; rcUpdatePhyMode = 0x40001ea8; rcGetHighestRateIdx = 0x40001eac; diff --git a/components/esp_rom/esp32c5/ld/esp32c5.rom.pp.ld b/components/esp_rom/esp32c5/ld/esp32c5.rom.pp.ld index 7515b90cca3..96c501f990e 100644 --- a/components/esp_rom/esp32c5/ld/esp32c5.rom.pp.ld +++ b/components/esp_rom/esp32c5/ld/esp32c5.rom.pp.ld @@ -222,7 +222,7 @@ pp_coex_tx_release = 0x40000f08; ppAdd2AMPDUTail = 0x40000f0c; ppDirectRecycleAmpdu = 0x40000f10; ppRegressAmpdu = 0x40000f14; -pp_timer_do_process = 0x40000f18; +/*pp_timer_do_process = 0x40000f18;*/ rcGetAmpduSched = 0x40000f1c; rcUpdateRxDone = 0x40000f20; rc_get_trc = 0x40000f24; diff --git a/components/esp_rom/esp32c61/ld/esp32c61.rom.pp.ld b/components/esp_rom/esp32c61/ld/esp32c61.rom.pp.ld index cf1349b9ab2..6931333f9d7 100644 --- a/components/esp_rom/esp32c61/ld/esp32c61.rom.pp.ld +++ b/components/esp_rom/esp32c61/ld/esp32c61.rom.pp.ld @@ -225,7 +225,7 @@ pp_coex_tx_release = 0x40000e7c; ppAdd2AMPDUTail = 0x40000e80; ppDirectRecycleAmpdu = 0x40000e84; ppRegressAmpdu = 0x40000e88; -pp_timer_do_process = 0x40000e8c; +/*pp_timer_do_process = 0x40000e8c;*/ rcGetAmpduSched = 0x40000e90; rcUpdateRxDone = 0x40000e94; rc_get_trc = 0x40000e98; diff --git a/components/esp_wifi/lib b/components/esp_wifi/lib index a93530033ae..0da5a8a5dfd 160000 --- a/components/esp_wifi/lib +++ b/components/esp_wifi/lib @@ -1 +1 @@ -Subproject commit a93530033aece29f1622c9ca9161eb4770aea909 +Subproject commit 0da5a8a5dfd8914496c5975af7d8903a44f8bced From bdf0821f976880a44100ccd140a6ce8bf8fef973 Mon Sep 17 00:00:00 2001 From: viayie Date: Wed, 16 Oct 2024 11:32:40 +0800 Subject: [PATCH 166/472] fix(cmake): Prevent overwriting of component properties in output file While 'component_properties_text' correctly accumulated properties from all processed components, each iteration of the loop was overwriting the entire file content. Move the file(WRITE ...) call outside the loop to ensure all accumulated component properties are written once, preserving information for all components. --- tools/cmake/component.cmake | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/tools/cmake/component.cmake b/tools/cmake/component.cmake index 1ad0ed05ede..1651a659028 100644 --- a/tools/cmake/component.cmake +++ b/tools/cmake/component.cmake @@ -122,6 +122,7 @@ endfunction() # keeps a list of all its properties. # function(__component_write_properties output_file) + set(component_properties_text "") idf_build_get_property(component_targets __COMPONENT_TARGETS) foreach(component_target ${component_targets}) __component_get_property(component_properties ${component_target} __COMPONENT_PROPERTIES) @@ -130,8 +131,8 @@ function(__component_write_properties output_file) set(component_properties_text "${component_properties_text}\nset(__component_${component_target}_${property} \"${val}\")") endforeach() - file(WRITE ${output_file} "${component_properties_text}") endforeach() + file(WRITE ${output_file} "${component_properties_text}") endfunction() # From 910bea1a1d08a45d5accf69f99ffcc5c421d09e5 Mon Sep 17 00:00:00 2001 From: Fu Hanxi Date: Wed, 16 Oct 2024 09:37:50 +0200 Subject: [PATCH 167/472] ci: bypass import failure while checking test scripts we mock the missing packages in pytest_collectstart in plugin.py. but here the common_test_methods are imported by other scripts, which got executed earlier. --- tools/ci/python_packages/common_test_methods.py | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/tools/ci/python_packages/common_test_methods.py b/tools/ci/python_packages/common_test_methods.py index 80392fbc27e..fe5db2a9e73 100644 --- a/tools/ci/python_packages/common_test_methods.py +++ b/tools/ci/python_packages/common_test_methods.py @@ -1,12 +1,19 @@ -# SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD +# SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD # SPDX-License-Identifier: Apache-2.0 - import logging import os import socket -from typing import Any, List +from typing import Any +from typing import List + +try: + import netifaces +except ImportError: + from unittest.mock import MagicMock + + netifaces = MagicMock() + logging.warning('netifaces is not installed. Please install it to get network interface information.') -import netifaces import yaml ENV_CONFIG_FILE_SEARCH = [ From bd26feef9b51ae4a22ee69619649b24b9bc44d43 Mon Sep 17 00:00:00 2001 From: Fu Hanxi Date: Wed, 16 Oct 2024 09:56:54 +0200 Subject: [PATCH 168/472] ci: ignore collect import error --- .gitlab/ci/build.yml | 4 ++++ .gitlab/ci/pre_check.yml | 4 +++- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/.gitlab/ci/build.yml b/.gitlab/ci/build.yml index ce6ccfd2764..6147e13503e 100644 --- a/.gitlab/ci/build.yml +++ b/.gitlab/ci/build.yml @@ -309,7 +309,11 @@ generate_build_child_pipeline: - non_test_related_apps.txt expire_in: 1 week when: always + variables: + PYTEST_IGNORE_COLLECT_IMPORT_ERROR: "1" script: + # requires basic pytest dependencies + - run_cmd bash install.sh --enable-pytest - run_cmd python tools/ci/dynamic_pipelines/scripts/generate_build_child_pipeline.py build_child_pipeline: diff --git a/.gitlab/ci/pre_check.yml b/.gitlab/ci/pre_check.yml index 31dfb072664..2acc5ef0bf5 100644 --- a/.gitlab/ci/pre_check.yml +++ b/.gitlab/ci/pre_check.yml @@ -117,8 +117,10 @@ check_test_scripts_build_test_rules: extends: - .pre_check_template - .before_script:build + variables: + PYTEST_IGNORE_COLLECT_IMPORT_ERROR: "1" script: - # required pytest related packages + # requires basic pytest dependencies - run_cmd bash install.sh --enable-pytest - python tools/ci/check_build_test_rules.py check-test-scripts examples/ tools/test_apps components From 1e614efa5f818aef3ccc7e7b308aa2489eba9bca Mon Sep 17 00:00:00 2001 From: Fu Hanxi Date: Wed, 16 Oct 2024 11:01:16 +0200 Subject: [PATCH 169/472] ci: add missing dependency --- tools/requirements/requirements.ci.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/tools/requirements/requirements.ci.txt b/tools/requirements/requirements.ci.txt index fa1ac259d40..dfec5b20fc3 100644 --- a/tools/requirements/requirements.ci.txt +++ b/tools/requirements/requirements.ci.txt @@ -15,3 +15,4 @@ pyyaml SimpleWebSocketServer pylint-gitlab minio +prettytable From b1dee4e0d98bf135631bdbb28bad547e0e35c42f Mon Sep 17 00:00:00 2001 From: morris Date: Tue, 25 Jun 2024 15:47:50 +0800 Subject: [PATCH 170/472] change(hw_support): temporarily ignore gcc static analyzer issues found in regdma and dma2d driver --- components/esp_hw_support/CMakeLists.txt | 4 - components/esp_hw_support/port/regdma_link.c | 3 + components/esp_hw_support/sleep_modes.c | 5 +- components/hal/esp32h2/include/hal/uart_ll.h | 102 ++++++++++--------- 4 files changed, 57 insertions(+), 57 deletions(-) diff --git a/components/esp_hw_support/CMakeLists.txt b/components/esp_hw_support/CMakeLists.txt index e1b6efc00db..52f0aa03a85 100644 --- a/components/esp_hw_support/CMakeLists.txt +++ b/components/esp_hw_support/CMakeLists.txt @@ -163,10 +163,6 @@ idf_build_get_property(target IDF_TARGET) add_subdirectory(port/${target}) add_subdirectory(lowpower) -if(CONFIG_COMPILER_STATIC_ANALYZER AND CMAKE_C_COMPILER_ID STREQUAL "GNU") # TODO IDF-10229 - target_compile_options(${COMPONENT_LIB} PRIVATE "-fno-analyzer") -endif() - if(CONFIG_ESP_SLEEP_GPIO_RESET_WORKAROUND OR CONFIG_PM_SLP_DISABLE_GPIO) target_link_libraries(${COMPONENT_LIB} INTERFACE "-u esp_sleep_gpio_include") endif() diff --git a/components/esp_hw_support/port/regdma_link.c b/components/esp_hw_support/port/regdma_link.c index a090ea0b25d..69db06f5e08 100644 --- a/components/esp_hw_support/port/regdma_link.c +++ b/components/esp_hw_support/port/regdma_link.c @@ -15,6 +15,7 @@ #include "esp_heap_caps.h" #include "esp_log.h" #include "esp_regdma.h" +#include "esp_compiler.h" @@ -419,6 +420,7 @@ static void * regdma_link_get_instance(void *link) return container_memaddr[it]; } +ESP_COMPILER_DIAGNOSTIC_PUSH_IGNORE("-Wanalyzer-null-dereference") // TODO IDF-11384 static regdma_link_stats_t * regdma_link_get_stats(void *link) { const static size_t stats_offset[] = { @@ -437,6 +439,7 @@ static regdma_link_stats_t * regdma_link_get_stats(void *link) return (regdma_link_stats_t *)(regdma_link_get_instance(link) + stats_offset[it]); } +ESP_COMPILER_DIAGNOSTIC_POP("-Wanalyzer-null-dereference") static void regdma_link_update_stats_wrapper(void *link, int entry, int depth) { diff --git a/components/esp_hw_support/sleep_modes.c b/components/esp_hw_support/sleep_modes.c index ed81134542d..ff8257c124e 100644 --- a/components/esp_hw_support/sleep_modes.c +++ b/components/esp_hw_support/sleep_modes.c @@ -12,6 +12,7 @@ #include "esp_attr.h" #include "esp_rom_caps.h" +#include "esp_macros.h" #include "esp_memory_utils.h" #include "esp_sleep.h" #include "esp_private/esp_sleep_internal.h" @@ -1215,9 +1216,7 @@ static esp_err_t IRAM_ATTR deep_sleep_start(bool allow_sleep_rejection) } else { // Because RTC is in a slower clock domain than the CPU, it // can take several CPU cycles for the sleep mode to start. - while (1) { - ; - } + ESP_INFINITE_LOOP(); } // Never returns here, except that the sleep is rejected. esp_ipc_isr_stall_resume(); diff --git a/components/hal/esp32h2/include/hal/uart_ll.h b/components/hal/esp32h2/include/hal/uart_ll.h index 4fa29d216f3..26e3e1facd1 100644 --- a/components/hal/esp32h2/include/hal/uart_ll.h +++ b/components/hal/esp32h2/include/hal/uart_ll.h @@ -94,14 +94,14 @@ typedef enum { */ FORCE_INLINE_ATTR bool uart_ll_is_enabled(uint32_t uart_num) { - uint32_t uart_clk_config_reg = ((uart_num == 0) ? PCR_UART0_CONF_REG : - (uart_num == 1) ? PCR_UART1_CONF_REG : 0); - uint32_t uart_rst_bit = ((uart_num == 0) ? PCR_UART0_RST_EN : - (uart_num == 1) ? PCR_UART1_RST_EN : 0); - uint32_t uart_en_bit = ((uart_num == 0) ? PCR_UART0_CLK_EN : - (uart_num == 1) ? PCR_UART1_CLK_EN : 0); - return REG_GET_BIT(uart_clk_config_reg, uart_rst_bit) == 0 && - REG_GET_BIT(uart_clk_config_reg, uart_en_bit) != 0; + switch (uart_num) { + case 0: + return PCR.uart0_conf.uart0_clk_en && !PCR.uart0_conf.uart0_rst_en; + case 1: + return PCR.uart1_conf.uart1_clk_en && !PCR.uart1_conf.uart1_rst_en; + default: + return false; + } } /** @@ -194,18 +194,18 @@ FORCE_INLINE_ATTR void uart_ll_sclk_disable(uart_dev_t *hw) FORCE_INLINE_ATTR void uart_ll_set_sclk(uart_dev_t *hw, soc_module_clk_t source_clk) { switch (source_clk) { - case UART_SCLK_PLL_F48M: - UART_LL_PCR_REG_SET(hw, sclk_conf, sclk_sel, 1); - break; - case UART_SCLK_RTC: - UART_LL_PCR_REG_SET(hw, sclk_conf, sclk_sel, 2); - break; - case UART_SCLK_XTAL: - UART_LL_PCR_REG_SET(hw, sclk_conf, sclk_sel, 3); - break; - default: - // Invalid UART clock source - abort(); + case UART_SCLK_PLL_F48M: + UART_LL_PCR_REG_SET(hw, sclk_conf, sclk_sel, 1); + break; + case UART_SCLK_RTC: + UART_LL_PCR_REG_SET(hw, sclk_conf, sclk_sel, 2); + break; + case UART_SCLK_XTAL: + UART_LL_PCR_REG_SET(hw, sclk_conf, sclk_sel, 3); + break; + default: + // Invalid UART clock source + abort(); } } @@ -220,16 +220,16 @@ FORCE_INLINE_ATTR void uart_ll_set_sclk(uart_dev_t *hw, soc_module_clk_t source_ FORCE_INLINE_ATTR void uart_ll_get_sclk(uart_dev_t *hw, soc_module_clk_t *source_clk) { switch (UART_LL_PCR_REG_GET(hw, sclk_conf, sclk_sel)) { - default: - case 1: - *source_clk = (soc_module_clk_t)UART_SCLK_PLL_F48M; - break; - case 2: - *source_clk = (soc_module_clk_t)UART_SCLK_RTC; - break; - case 3: - *source_clk = (soc_module_clk_t)UART_SCLK_XTAL; - break; + default: + case 1: + *source_clk = (soc_module_clk_t)UART_SCLK_PLL_F48M; + break; + case 2: + *source_clk = (soc_module_clk_t)UART_SCLK_RTC; + break; + case 3: + *source_clk = (soc_module_clk_t)UART_SCLK_XTAL; + break; } } @@ -248,7 +248,9 @@ FORCE_INLINE_ATTR void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint3 const uint32_t max_div = BIT(12) - 1; // UART divider integer part only has 12 bits uint32_t sclk_div = DIV_UP(sclk_freq, (uint64_t)max_div * baud); - if (sclk_div == 0) abort(); + if (sclk_div == 0) { + abort(); + } uint32_t clk_div = ((sclk_freq) << 4) / (baud * sclk_div); // The baud rate configuration register is divided into @@ -844,22 +846,22 @@ FORCE_INLINE_ATTR void uart_ll_set_mode_irda(uart_dev_t *hw) FORCE_INLINE_ATTR void uart_ll_set_mode(uart_dev_t *hw, uart_mode_t mode) { switch (mode) { - default: - case UART_MODE_UART: - uart_ll_set_mode_normal(hw); - break; - case UART_MODE_RS485_COLLISION_DETECT: - uart_ll_set_mode_collision_detect(hw); - break; - case UART_MODE_RS485_APP_CTRL: - uart_ll_set_mode_rs485_app_ctrl(hw); - break; - case UART_MODE_RS485_HALF_DUPLEX: - uart_ll_set_mode_rs485_half_duplex(hw); - break; - case UART_MODE_IRDA: - uart_ll_set_mode_irda(hw); - break; + default: + case UART_MODE_UART: + uart_ll_set_mode_normal(hw); + break; + case UART_MODE_RS485_COLLISION_DETECT: + uart_ll_set_mode_collision_detect(hw); + break; + case UART_MODE_RS485_APP_CTRL: + uart_ll_set_mode_rs485_app_ctrl(hw); + break; + case UART_MODE_RS485_HALF_DUPLEX: + uart_ll_set_mode_rs485_half_duplex(hw); + break; + case UART_MODE_IRDA: + uart_ll_set_mode_irda(hw); + break; } } @@ -957,7 +959,7 @@ FORCE_INLINE_ATTR void uart_ll_xon_force_on(uart_dev_t *hw, bool always_on) { hw->swfc_conf0_sync.force_xon = 1; uart_ll_update(hw); - if(!always_on) { + if (!always_on) { hw->swfc_conf0_sync.force_xon = 0; uart_ll_update(hw); } @@ -1003,7 +1005,7 @@ FORCE_INLINE_ATTR void uart_ll_inverse_signal(uart_dev_t *hw, uint32_t inv_mask) FORCE_INLINE_ATTR void uart_ll_set_rx_tout(uart_dev_t *hw, uint16_t tout_thrd) { uint16_t tout_val = tout_thrd; - if(tout_thrd > 0) { + if (tout_thrd > 0) { hw->tout_conf_sync.rx_tout_thrhd = tout_val; hw->tout_conf_sync.rx_tout_en = 1; } else { @@ -1022,7 +1024,7 @@ FORCE_INLINE_ATTR void uart_ll_set_rx_tout(uart_dev_t *hw, uint16_t tout_thrd) FORCE_INLINE_ATTR uint16_t uart_ll_get_rx_tout_thr(uart_dev_t *hw) { uint16_t tout_thrd = 0; - if(hw->tout_conf_sync.rx_tout_en > 0) { + if (hw->tout_conf_sync.rx_tout_en > 0) { tout_thrd = hw->tout_conf_sync.rx_tout_thrhd; } return tout_thrd; From 1792aba1dcc5ae7cf8aead79663d244787a2bbc2 Mon Sep 17 00:00:00 2001 From: Armando Date: Thu, 26 Sep 2024 16:18:30 +0800 Subject: [PATCH 171/472] feat(vad): lp vad driver and wakeup feature --- components/esp_driver_i2s/CMakeLists.txt | 4 + .../include/driver/lp_i2s_vad.h | 153 ++++++++++++++++++ .../include/esp_private/lp_i2s_private.h | 27 ++++ components/esp_driver_i2s/lp_i2s.c | 13 ++ components/esp_driver_i2s/lp_i2s_vad.c | 112 +++++++++++++ .../hal/esp32p4/include/hal/lp_core_ll.h | 2 +- .../hal/esp32p4/include/hal/lp_i2s_ll.h | 106 +++++++++++- .../esp32p4/include/soc/Kconfig.soc_caps.in | 12 ++ components/soc/esp32p4/include/soc/soc_caps.h | 5 + components/ulp/CMakeLists.txt | 4 + components/ulp/cmake/IDFULPProject.cmake | 1 + components/ulp/lp_core/include/ulp_lp_core.h | 1 + components/ulp/lp_core/lp_core.c | 5 +- .../ulp/lp_core/lp_core/lp_core_utils.c | 11 ++ .../include/ulp_lp_core_lp_vad_shared.h | 121 ++++++++++++++ .../shared/ulp_lp_core_lp_vad_shared.c | 65 ++++++++ 16 files changed, 635 insertions(+), 7 deletions(-) create mode 100644 components/esp_driver_i2s/include/driver/lp_i2s_vad.h create mode 100644 components/esp_driver_i2s/include/esp_private/lp_i2s_private.h create mode 100644 components/esp_driver_i2s/lp_i2s_vad.c create mode 100644 components/ulp/lp_core/shared/include/ulp_lp_core_lp_vad_shared.h create mode 100644 components/ulp/lp_core/shared/ulp_lp_core_lp_vad_shared.c diff --git a/components/esp_driver_i2s/CMakeLists.txt b/components/esp_driver_i2s/CMakeLists.txt index cc39943ae66..2498fa6126a 100644 --- a/components/esp_driver_i2s/CMakeLists.txt +++ b/components/esp_driver_i2s/CMakeLists.txt @@ -30,6 +30,10 @@ if(CONFIG_SOC_LP_I2S_SUPPORTED) list(APPEND srcs "lp_i2s.c" "lp_i2s_std.c" "lp_i2s_pdm.c") endif() +if(CONFIG_SOC_LP_I2S_SUPPORT_VAD) + list(APPEND srcs "lp_i2s_vad.c") +endif() + idf_component_register(SRCS ${srcs} INCLUDE_DIRS ${include} PRIV_REQUIRES esp_driver_gpio esp_pm esp_mm diff --git a/components/esp_driver_i2s/include/driver/lp_i2s_vad.h b/components/esp_driver_i2s/include/driver/lp_i2s_vad.h new file mode 100644 index 00000000000..ce52370cde6 --- /dev/null +++ b/components/esp_driver_i2s/include/driver/lp_i2s_vad.h @@ -0,0 +1,153 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include +#include "soc/soc_caps.h" +#include "esp_err.h" +#include "driver/i2s_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief State Machine + ┌──────────────────────────────────┐ + │ │ + ┌─────────────┤ speak-activity-listening-state │ ◄───────────────┐ + │ │ │ │ + │ └──────────────────────────────────┘ │ + │ ▲ │ + │ │ │ + │ │ │ + │ │ │ + │ │ │ +detected speak activity │ │ detected speak activity │ detected speak activity + >= │ │ >= │ >= +'speak_activity_thresh' │ │ 'min_speak_activity_thresh' │ 'max_speak_activity_thresh' + │ │ │ + │ │ && │ + │ │ │ + │ │ detected non-speak activity │ + │ │ < │ + │ │ 'non_speak_activity_thresh' │ + │ │ │ + │ │ │ + │ │ │ + │ │ │ + │ │ │ + │ ┌───────────┴─────────────────────┐ │ + │ │ │ │ + └───────────► │ speak-activity-detected-state ├─────────────────┘ + │ │ + └─┬───────────────────────────────┘ + │ + │ ▲ + │ │ + │ │ + │ │ detected speak activity + │ │ >= + │ │ 'min_speak_activity_thresh' + │ │ + │ │ && + │ │ + │ │ detected non-speak activity + │ │ < + └─────────────────────┘ 'non_speak_activity_thresh' +*/ + +/** + * @brief LP VAD peripheral + */ +typedef uint32_t lp_vad_t; + +/** + * @brief Type of VAD unit handle + */ +typedef struct vad_unit_ctx_t *vad_unit_handle_t; + +/** + * @brief LP VAD configurations + */ +typedef struct { + int init_frame_num; /**< Number of init frames that are used for VAD to denoise, this helps the VAD to decrease the accidental trigger ratio. + Note too big values may lead to voice activity miss */ + int min_energy_thresh; ///< Min energy threshold. + bool skip_band_energy_thresh; ///< Skip band energy threshold or not + + int speak_activity_thresh; /**< When in speak-activity-listening-state, if number of the detected speak activity is higher than this value, VAD runs into speak-activity-detected-state */ + + int non_speak_activity_thresh; /**< When in speak-activity-detected-state, if the number of the detected speak activity is higher than this value, but lower than `max_speak_activity_thresh`: + - if the number of the detected non-speak activity is higher than this value, VAD runs into speak-activity-listening-state + - if the number of the detected non-speak activity is lower than this value, VAD keeps in speak-activity-detected-state */ + + int min_speak_activity_thresh; /**< When in speak-activity-detected-state, if the number of the detected speak activity is higher than this value, but lower than `max_speak_activity_thresh`, + then the VAD state machine will depends on the value of `non_speak_activity_thresh` */ + + int max_speak_activity_thresh; /**< When in speak-activity-detected-state, if the number of the detected speak activity is higher than this value, VAD runs into speak-activity-listening-state */ +} lp_vad_config_t; + +typedef struct { + lp_i2s_chan_handle_t lp_i2s_chan; ///< LP I2S channel handle + lp_vad_config_t vad_config; ///< LP VAD config +} lp_vad_init_config_t; + +/** + * @brief New LP VAD unit + * @param[in] vad_id VAD id + * @param[in] init_config Initial configurations + * @param[out] ret_unit Unit handle + * + * @return + * - ESP_OK: On success + * - ESP_ERR_INVALID_ARG: Invalid argument + * - ESP_ERR_INVALID_STATE: Driver state is invalid, you shouldn't call this API at this moment + */ +esp_err_t lp_i2s_vad_new_unit(lp_vad_t vad_id, const lp_vad_init_config_t *init_config, vad_unit_handle_t *ret_unit); + +/** + * @brief Enable LP VAD + * + * @param[in] unit VAD handle + * @param[in] init_config Initial configurations + * + * @return + * - ESP_OK: On success + * - ESP_ERR_INVALID_ARG: Invalid argument + * - ESP_ERR_INVALID_STATE: Driver state is invalid, you shouldn't call this API at this moment + */ +esp_err_t lp_i2s_vad_enable(vad_unit_handle_t unit); + +/** + * @brief Disable LP VAD + * + * @param[in] unit VAD handle + * @param[in] init_config Initial configurations + * + * @return + * - ESP_OK: On success + * - ESP_ERR_INVALID_ARG: Invalid argument + * - ESP_ERR_INVALID_STATE: Driver state is invalid, you shouldn't call this API at this moment + */ +esp_err_t lp_i2s_vad_disable(vad_unit_handle_t unit); + +/** + * @brief Delete LP VAD unit + * @param[in] unit VAD handle + * + * @return + * - ESP_OK: On success + * - ESP_ERR_INVALID_ARG: Invalid argument + * - ESP_ERR_INVALID_STATE: Driver state is invalid, you shouldn't call this API at this moment + */ +esp_err_t lp_i2s_vad_del_unit(vad_unit_handle_t unit); + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_driver_i2s/include/esp_private/lp_i2s_private.h b/components/esp_driver_i2s/include/esp_private/lp_i2s_private.h new file mode 100644 index 00000000000..2785ca02633 --- /dev/null +++ b/components/esp_driver_i2s/include/esp_private/lp_i2s_private.h @@ -0,0 +1,27 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include "hal/lp_i2s_hal.h" +#include "driver/i2s_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Get LP I2S soc handle + * + * @param[in] chan LP I2S channel handle + * + * @return LP I2S soc handle + */ +lp_i2s_soc_handle_t lp_i2s_get_soc_handle(lp_i2s_chan_handle_t chan); + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_driver_i2s/lp_i2s.c b/components/esp_driver_i2s/lp_i2s.c index 7084fc8947e..0d5e43dd8d0 100644 --- a/components/esp_driver_i2s/lp_i2s.c +++ b/components/esp_driver_i2s/lp_i2s.c @@ -25,6 +25,7 @@ #include "driver/lp_i2s.h" #include "esp_private/periph_ctrl.h" #include "esp_private/i2s_platform.h" +#include "esp_private/lp_i2s_private.h" #include "i2s_private.h" #include "soc/i2s_periph.h" @@ -329,3 +330,15 @@ static void IRAM_ATTR s_i2s_default_isr(void *arg) portYIELD_FROM_ISR(); } } + +/*--------------------------------------------------------------- + HELPERS +---------------------------------------------------------------*/ +lp_i2s_soc_handle_t lp_i2s_get_soc_handle(lp_i2s_chan_handle_t chan) +{ + if (!chan) { + return NULL; + } + + return chan->ctlr->hal.dev; +} diff --git a/components/esp_driver_i2s/lp_i2s_vad.c b/components/esp_driver_i2s/lp_i2s_vad.c new file mode 100644 index 00000000000..f1cc63559ec --- /dev/null +++ b/components/esp_driver_i2s/lp_i2s_vad.c @@ -0,0 +1,112 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include "soc/soc_caps.h" +#include "stdatomic.h" +#if SOC_LP_VAD_SUPPORTED +#include "esp_check.h" +#include "esp_err.h" +#include "driver/lp_i2s_vad.h" +#include "esp_heap_caps.h" +#include "hal/lp_i2s_ll.h" +#include "hal/lp_i2s_hal.h" +#include "esp_private/lp_i2s_private.h" + +#define LP_VAD_MEM_ALLOC_CAPS (MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT) + +static const char *LP_VAD_TAG = "LP_VAD"; + +typedef enum { + VAD_FSM_INIT, + VAD_FSM_ENABLE, +} vad_fsm_t; + +typedef struct vad_unit_ctx_t { + lp_i2s_soc_handle_t hw; + lp_vad_t vad_id; + vad_fsm_t fsm; +} vad_unit_ctx_t; + +static atomic_bool s_vad_id_claimed[SOC_ADC_PERIPH_NUM] = {ATOMIC_VAR_INIT(false)}; + +static bool s_vad_claim(lp_vad_t vad_id) +{ + bool false_var = false; + return atomic_compare_exchange_strong(&s_vad_id_claimed[vad_id], &false_var, true); +} + +static bool s_vad_free(lp_vad_t vad_id) +{ + bool true_var = true; + return atomic_compare_exchange_strong(&s_vad_id_claimed[vad_id], &true_var, false); +} + +esp_err_t lp_i2s_vad_new_unit(lp_vad_t vad_id, const lp_vad_init_config_t *init_config, vad_unit_handle_t *ret_unit) +{ + esp_err_t ret = ESP_OK; + ESP_RETURN_ON_FALSE(init_config, ESP_ERR_INVALID_ARG, LP_VAD_TAG, "invalid arg"); + ESP_RETURN_ON_FALSE(init_config->lp_i2s_chan, ESP_ERR_INVALID_ARG, LP_VAD_TAG, "LP I2S not initialised"); + ESP_RETURN_ON_FALSE(init_config->vad_config.init_frame_num >= LP_VAD_LL_INIT_FRAME_MIN && init_config->vad_config.init_frame_num <= LP_VAD_LL_INIT_FRAME_MAX, ESP_ERR_INVALID_ARG, LP_VAD_TAG, "invalid init frame num"); + + bool success_claim = s_vad_claim(vad_id); + ESP_RETURN_ON_FALSE(success_claim, ESP_ERR_NOT_FOUND, LP_VAD_TAG, "vad%"PRId32" is already in use", vad_id); + + vad_unit_ctx_t *unit = heap_caps_calloc(1, sizeof(vad_unit_ctx_t), LP_VAD_MEM_ALLOC_CAPS); + ESP_GOTO_ON_FALSE(unit, ESP_ERR_NO_MEM, err, LP_VAD_TAG, "no mem for unit"); + + unit->hw = lp_i2s_get_soc_handle(init_config->lp_i2s_chan); + ESP_LOGD(LP_VAD_TAG, "unit->hw: %p", unit->hw); + lp_vad_ll_set_init_frame_num(unit->hw, init_config->vad_config.init_frame_num); + lp_vad_ll_set_init_min_energy(unit->hw, init_config->vad_config.min_energy_thresh); + lp_vad_ll_set_speak_activity_thresh(unit->hw, init_config->vad_config.speak_activity_thresh); + lp_vad_ll_set_non_speak_activity_thresh(unit->hw, init_config->vad_config.non_speak_activity_thresh); + lp_vad_ll_set_min_speak_activity_thresh(unit->hw, init_config->vad_config.min_speak_activity_thresh); + lp_vad_ll_set_max_speak_activity_thresh(unit->hw, init_config->vad_config.max_speak_activity_thresh); + lp_vad_ll_skip_band_energy(unit->hw, init_config->vad_config.skip_band_energy_thresh); + unit->fsm = VAD_FSM_INIT; + *ret_unit = unit; + + return ESP_OK; +err: + bool success_free = s_vad_free(vad_id); + assert(success_free); + + return ret; +} + +esp_err_t lp_i2s_vad_enable(vad_unit_handle_t unit) +{ + ESP_RETURN_ON_FALSE(unit, ESP_ERR_INVALID_ARG, LP_VAD_TAG, "invalid arg"); + ESP_RETURN_ON_FALSE(unit->fsm == VAD_FSM_INIT, ESP_ERR_INVALID_STATE, LP_VAD_TAG, "The driver is enabled already"); + + lp_vad_ll_enable(unit->hw, true); + unit->fsm = VAD_FSM_ENABLE; + return ESP_OK; +} + +esp_err_t lp_i2s_vad_disable(vad_unit_handle_t unit) +{ + ESP_RETURN_ON_FALSE(unit, ESP_ERR_INVALID_ARG, LP_VAD_TAG, "invalid arg"); + ESP_RETURN_ON_FALSE(unit->fsm == VAD_FSM_ENABLE, ESP_ERR_INVALID_STATE, LP_VAD_TAG, "The driver is not enabled yet"); + + lp_vad_ll_enable(unit->hw, false); + unit->fsm = VAD_FSM_INIT; + return ESP_OK; +} + +esp_err_t lp_i2s_vad_del_unit(vad_unit_handle_t unit) +{ + ESP_RETURN_ON_FALSE(unit, ESP_ERR_INVALID_ARG, LP_VAD_TAG, "invalid arg"); + ESP_RETURN_ON_FALSE(unit->fsm == VAD_FSM_INIT, ESP_ERR_INVALID_STATE, LP_VAD_TAG, "The driver is still in enabled state"); + + bool success_free = s_vad_free(unit->vad_id); + ESP_RETURN_ON_FALSE(success_free, ESP_ERR_NOT_FOUND, LP_VAD_TAG, "vad%"PRId32" isn't in use", unit->vad_id); + + free(unit); + return ESP_OK; +} +#endif /* SOC_LP_VAD_SUPPORTED */ diff --git a/components/hal/esp32p4/include/hal/lp_core_ll.h b/components/hal/esp32p4/include/hal/lp_core_ll.h index 27a9a0997fa..eb2c57be317 100644 --- a/components/hal/esp32p4/include/hal/lp_core_ll.h +++ b/components/hal/esp32p4/include/hal/lp_core_ll.h @@ -28,7 +28,7 @@ extern "C" { #define LP_CORE_LL_WAKEUP_SOURCE_LP_BOD BIT(14) #define LP_CORE_LL_WAKEUP_SOURCE_ETM BIT(17) #define LP_CORE_LL_WAKEUP_SOURCE_LP_TIMER_1 BIT(18) -#define LP_CORE_LL_WAKEUP_SOURCE_LP_I2S BIT(19) +#define LP_CORE_LL_WAKEUP_SOURCE_LP_VAD BIT(19) #define LP_CORE_LL_WAKEUP_SOURCE_HP_CPU BIT(22) /* Use lp timer 1 as the normal wakeup timer, timer 0 is used by deep sleep */ diff --git a/components/hal/esp32p4/include/hal/lp_i2s_ll.h b/components/hal/esp32p4/include/hal/lp_i2s_ll.h index c9f0d5611bd..23e81cd2a5f 100644 --- a/components/hal/esp32p4/include/hal/lp_i2s_ll.h +++ b/components/hal/esp32p4/include/hal/lp_i2s_ll.h @@ -32,6 +32,8 @@ extern "C" { #define LP_I2S_LL_EVENT_RX_DONE_INT (1<<0) #define LP_I2S_LL_EVENT_RX_HUNG_INT_INT (1<<1) #define LP_I2S_LL_EVENT_RX_FIFOMEM_UDF_INT (1<<2) +#define LP_I2S_LL_EVENT_VAD_DONE_INT (1<<3) +#define LP_I2S_LL_EVENT_VAD_RESET_DONE_INT (1<<4) #define LP_I2S_LL_EVENT_RX_MEM_THRESHOLD_INT (1<<5) #define LP_I2S_LL_TDM_CH_MASK (0x03UL) @@ -709,9 +711,9 @@ static inline uint32_t lp_i2s_ll_get_intr_status_reg_addr(lp_i2s_dev_t *hw) /** * @brief Enable LP I2S RX channel interrupt * - * @param hw LP I2S hardware instance - * @param mask mask - * @param enable enable or disable + * @param[in] hw LP I2S hardware instance + * @param[in] mask mask + * @param[in] enable enable or disable */ static inline void lp_i2s_ll_rx_enable_interrupt(lp_i2s_dev_t *hw, uint32_t mask, bool enable) { @@ -727,8 +729,8 @@ static inline void lp_i2s_ll_rx_enable_interrupt(lp_i2s_dev_t *hw, uint32_t mask /** * @brief Clear LP I2S RX channel interrupt * - * @param hw LP I2S hardware instance - * @param mask mask + * @param[in] hw LP I2S hardware instance + * @param[in] mask mask */ __attribute__((always_inline)) static inline void lp_i2s_ll_rx_clear_interrupt_status(lp_i2s_dev_t *hw, uint32_t mask) @@ -736,6 +738,100 @@ static inline void lp_i2s_ll_rx_clear_interrupt_status(lp_i2s_dev_t *hw, uint32_ hw->int_clr.val = mask; } +/*--------------------------------------------------------------- + VAD +---------------------------------------------------------------*/ +#define LP_VAD_LL_INIT_FRAME_MIN 100 +#define LP_VAD_LL_INIT_FRAME_MAX 200 + +/** + * @brief Set VAD init frame number + * + * @param[in] hw LP I2S hardware instance + * @param[in] frame_num Frame number + */ +static inline void lp_vad_ll_set_init_frame_num(lp_i2s_dev_t *hw, int frame_num) +{ + hw->vad_param0.param_init_frame_num = frame_num; +} + +/** + * @brief Set VAD min energy + * + * @param[in] hw LP I2S hardware instance + * @param[in] min_energy Min energy + */ +static inline void lp_vad_ll_set_init_min_energy(lp_i2s_dev_t *hw, int min_energy) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->vad_param0, param_min_energy, min_energy); +} + +/** + * @brief Set VAD speak activity thresh + * + * @param[in] hw LP I2S hardware instance + * @param[in] thresh Threshold + */ +static inline void lp_vad_ll_set_speak_activity_thresh(lp_i2s_dev_t *hw, int thresh) +{ + hw->vad_param1.param_hangover_speech = thresh; +} + +/** + * @brief Set VAD non speak activity thresh + * + * @param[in] hw LP I2S hardware instance + * @param[in] thresh Threshold + */ +static inline void lp_vad_ll_set_non_speak_activity_thresh(lp_i2s_dev_t *hw, int thresh) +{ + hw->vad_param1.param_hangover_silent = thresh; +} + +/** + * @brief Set VAD min speak activity thresh + * + * @param[in] hw LP I2S hardware instance + * @param[in] thresh Threshold + */ +static inline void lp_vad_ll_set_min_speak_activity_thresh(lp_i2s_dev_t *hw, int thresh) +{ + hw->vad_param1.param_min_speech_count = thresh; +} + +/** + * @brief Set VAD max speak activity thresh + * + * @param[in] hw LP I2S hardware instance + * @param[in] thresh Threshold + */ +static inline void lp_vad_ll_set_max_speak_activity_thresh(lp_i2s_dev_t *hw, int thresh) +{ + hw->vad_param1.param_max_speech_count = thresh; +} + +/** + * @brief Skip band energy check + * + * @param[in] hw LP I2S hardware instance + * @param[in] skip 1: skip; 0: not skip + */ +static inline void lp_vad_ll_skip_band_energy(lp_i2s_dev_t *hw, bool skip) +{ + hw->vad_param1.param_skip_band_energy = skip; +} + +/** + * @brief Enable LP I2S 24 fill + * + * @param[in] hw LP I2S hardware instance + * @param[in] en enable or disable + */ +static inline void lp_vad_ll_enable(lp_i2s_dev_t *hw, bool en) +{ + hw->vad_conf.vad_en = en; +} + #ifdef __cplusplus } #endif diff --git a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in index f8319e722ee..eac76a74a3f 100644 --- a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in @@ -263,6 +263,10 @@ config SOC_LP_ADC_SUPPORTED bool default y +config SOC_LP_VAD_SUPPORTED + bool + default y + config SOC_SPIRAM_SUPPORTED bool default y @@ -1763,6 +1767,10 @@ config SOC_UART_SUPPORT_FSM_TX_WAIT_SEND bool default y +config SOC_LP_I2S_SUPPORT_VAD + bool + default y + config SOC_COEX_HW_PTI bool default y @@ -1962,3 +1970,7 @@ config SOC_LP_CORE_SUPPORT_ETM config SOC_LP_CORE_SUPPORT_LP_ADC bool default y + +config SOC_LP_CORE_SUPPORT_LP_VAD + bool + default y diff --git a/components/soc/esp32p4/include/soc/soc_caps.h b/components/soc/esp32p4/include/soc/soc_caps.h index a8a90bda867..16d2aa76438 100644 --- a/components/soc/esp32p4/include/soc/soc_caps.h +++ b/components/soc/esp32p4/include/soc/soc_caps.h @@ -83,6 +83,7 @@ #define SOC_LP_I2S_SUPPORTED 1 #define SOC_LP_SPI_SUPPORTED 1 #define SOC_LP_ADC_SUPPORTED 1 +#define SOC_LP_VAD_SUPPORTED 1 #define SOC_SPIRAM_SUPPORTED 1 #define SOC_PSRAM_DMA_CAPABLE 1 #define SOC_SDMMC_HOST_SUPPORTED 1 @@ -662,6 +663,9 @@ // UART has an extra TX_WAIT_SEND state when the FIFO is not empty and XOFF is enabled #define SOC_UART_SUPPORT_FSM_TX_WAIT_SEND (1) +/*-------------------------- LP_VAD CAPS -------------------------------------*/ +#define SOC_LP_I2S_SUPPORT_VAD (1) + // TODO: IDF-5679 (Copy from esp32c3, need check) /*-------------------------- COEXISTENCE HARDWARE PTI CAPS -------------------------------*/ #define SOC_COEX_HW_PTI (1) @@ -745,3 +749,4 @@ /*------------------------------------- ULP CAPS -------------------------------------*/ #define SOC_LP_CORE_SUPPORT_ETM (1) /*!< LP Core supports ETM */ #define SOC_LP_CORE_SUPPORT_LP_ADC (1) /*!< LP ADC can be accessed from the LP-Core */ +#define SOC_LP_CORE_SUPPORT_LP_VAD (1) /*!< LP VAD can be accessed from the LP-Core */ diff --git a/components/ulp/CMakeLists.txt b/components/ulp/CMakeLists.txt index 058d05922b3..dbe990e652e 100644 --- a/components/ulp/CMakeLists.txt +++ b/components/ulp/CMakeLists.txt @@ -78,6 +78,10 @@ if(CONFIG_ULP_COPROC_TYPE_LP_CORE) if(CONFIG_SOC_LP_ADC_SUPPORTED) list(APPEND srcs "lp_core/shared/ulp_lp_core_lp_adc_shared.c") endif() + + if(CONFIG_SOC_LP_VAD_SUPPORTED) + list(APPEND srcs "lp_core/shared/ulp_lp_core_lp_vad_shared.c") + endif() endif() idf_component_register(SRCS ${srcs} diff --git a/components/ulp/cmake/IDFULPProject.cmake b/components/ulp/cmake/IDFULPProject.cmake index 04da71b00c2..fd90cfd87ff 100644 --- a/components/ulp/cmake/IDFULPProject.cmake +++ b/components/ulp/cmake/IDFULPProject.cmake @@ -126,6 +126,7 @@ function(ulp_apply_default_sources ulp_app_name) "${IDF_PATH}/components/ulp/lp_core/lp_core/lp_core_spi.c" "${IDF_PATH}/components/ulp/lp_core/lp_core/lp_core_ubsan.c" "${IDF_PATH}/components/ulp/lp_core/shared/ulp_lp_core_lp_adc_shared.c" + "${IDF_PATH}/components/ulp/lp_core/shared/ulp_lp_core_lp_vad_shared.c" "${IDF_PATH}/components/ulp/lp_core/shared/ulp_lp_core_critical_section_shared.c") set(target_folder ${IDF_TARGET}) diff --git a/components/ulp/lp_core/include/ulp_lp_core.h b/components/ulp/lp_core/include/ulp_lp_core.h index d737d638aca..6a0373aefa2 100644 --- a/components/ulp/lp_core/include/ulp_lp_core.h +++ b/components/ulp/lp_core/include/ulp_lp_core.h @@ -22,6 +22,7 @@ extern "C" { #define ULP_LP_CORE_WAKEUP_SOURCE_LP_IO BIT(2) // Enable wake-up by LP IO interrupt #define ULP_LP_CORE_WAKEUP_SOURCE_ETM BIT(3) // Enable wake-up by ETM event #define ULP_LP_CORE_WAKEUP_SOURCE_LP_TIMER BIT(4) // Enable wake-up by LP timer +#define ULP_LP_CORE_WAKEUP_SOURCE_LP_VAD BIT(5) // Enable wake-up by LP VAD /** * @brief ULP LP core init parameters diff --git a/components/ulp/lp_core/lp_core.c b/components/ulp/lp_core/lp_core.c index aedcf0e78e2..cfc8fc81cc0 100644 --- a/components/ulp/lp_core/lp_core.c +++ b/components/ulp/lp_core/lp_core.c @@ -35,7 +35,7 @@ extern uint32_t _rtc_ulp_memory_start; const static char* TAG = "ulp-lp-core"; -#define WAKEUP_SOURCE_MAX_NUMBER 5 +#define WAKEUP_SOURCE_MAX_NUMBER 6 #define RESET_HANDLER_ADDR (intptr_t)(&_rtc_ulp_memory_start + 0x80 / 4) // Placed after the 0x80 byte long vector table @@ -46,6 +46,9 @@ static uint32_t wakeup_src_sw_to_hw_flag_lookup[WAKEUP_SOURCE_MAX_NUMBER] = { LP_CORE_LL_WAKEUP_SOURCE_LP_IO, LP_CORE_LL_WAKEUP_SOURCE_ETM, LP_CORE_LL_WAKEUP_SOURCE_LP_TIMER, +#if SOC_LP_VAD_SUPPORTED + LP_CORE_LL_WAKEUP_SOURCE_LP_VAD, +#endif }; /* Convert the wake-up sources defined in ulp_lp_core.h to the actual HW wake-up source values */ diff --git a/components/ulp/lp_core/lp_core/lp_core_utils.c b/components/ulp/lp_core/lp_core/lp_core_utils.c index 8b358741fbb..d3e8664907b 100644 --- a/components/ulp/lp_core/lp_core/lp_core_utils.c +++ b/components/ulp/lp_core/lp_core/lp_core_utils.c @@ -14,6 +14,10 @@ #include "hal/pmu_ll.h" #include "hal/uart_ll.h" #include "hal/rtc_io_ll.h" +#if SOC_LP_I2S_SUPPORT_VAD +//For VAD +#include "hal/lp_i2s_ll.h" +#endif #if SOC_LP_TIMER_SUPPORTED #include "hal/lp_timer_ll.h" @@ -56,6 +60,13 @@ void ulp_lp_core_update_wakeup_cause(void) rtcio_ll_clear_interrupt_status(); } +#if SOC_LP_VAD_SUPPORTED + if ((lp_core_ll_get_wakeup_source() & LP_CORE_LL_WAKEUP_SOURCE_LP_VAD)) { + lp_wakeup_cause |= LP_CORE_LL_WAKEUP_SOURCE_LP_VAD; + lp_i2s_ll_rx_clear_interrupt_status(&LP_I2S, LP_I2S_LL_EVENT_VAD_DONE_INT); + } +#endif + #if SOC_ETM_SUPPORTED if ((lp_core_ll_get_wakeup_source() & LP_CORE_LL_WAKEUP_SOURCE_ETM) \ && lp_core_ll_get_etm_wakeup_flag()) { diff --git a/components/ulp/lp_core/shared/include/ulp_lp_core_lp_vad_shared.h b/components/ulp/lp_core/shared/include/ulp_lp_core_lp_vad_shared.h new file mode 100644 index 00000000000..8a37dee54db --- /dev/null +++ b/components/ulp/lp_core/shared/include/ulp_lp_core_lp_vad_shared.h @@ -0,0 +1,121 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include "esp_err.h" +#include "driver/lp_i2s_vad.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief LP VAD configurations + */ +typedef lp_vad_init_config_t lp_core_lp_vad_cfg_t; + +/** + * @brief State Machine + ┌──────────────────────────────────┐ + │ │ + ┌─────────────┤ speak-activity-listening-state │ ◄───────────────┐ + │ │ │ │ + │ └──────────────────────────────────┘ │ + │ ▲ │ + │ │ │ + │ │ │ + │ │ │ + │ │ │ +detected speak activity │ │ detected speak activity │ detected speak activity + >= │ │ >= │ >= +'speak_activity_thresh' │ │ 'min_speak_activity_thresh' │ 'max_speak_activity_thresh' + │ │ │ + │ │ && │ + │ │ │ + │ │ detected non-speak activity │ + │ │ < │ + │ │ 'non_speak_activity_thresh' │ + │ │ │ + │ │ │ + │ │ │ + │ │ │ + │ │ │ + │ ┌───────────┴─────────────────────┐ │ + │ │ │ │ + └───────────► │ speak-activity-detected-state ├─────────────────┘ + │ │ + └─┬───────────────────────────────┘ + │ + │ ▲ + │ │ + │ │ + │ │ detected speak activity + │ │ >= + │ │ 'min_speak_activity_thresh' + │ │ + │ │ && + │ │ + │ │ detected non-speak activity + │ │ < + └─────────────────────┘ 'non_speak_activity_thresh' +*/ + +/** + * @brief LP VAD init + * + * @param[in] vad_id VAD ID + * @param[in] init_config Initial configurations + * + * @return + * - ESP_OK: On success + * - ESP_ERR_INVALID_ARG: Invalid argument + * - ESP_ERR_INVALID_STATE: Driver state is invalid, you shouldn't call this API at this moment + */ +esp_err_t lp_core_lp_vad_init(lp_vad_t vad_id, const lp_core_lp_vad_cfg_t *init_config); + +/** + * @brief Enable LP VAD + * + * @param[in] vad_id VAD ID + * @param[in] init_config Initial configurations + * + * @return + * - ESP_OK: On success + * - ESP_ERR_INVALID_ARG: Invalid argument + * - ESP_ERR_INVALID_STATE: Driver state is invalid, you shouldn't call this API at this moment + */ +esp_err_t lp_core_lp_vad_enable(lp_vad_t vad_id); + +/** + * @brief Disable LP VAD + * + * @param[in] vad_id VAD ID + * @param[in] init_config Initial configurations + * + * @return + * - ESP_OK: On success + * - ESP_ERR_INVALID_ARG: Invalid argument + * - ESP_ERR_INVALID_STATE: Driver state is invalid, you shouldn't call this API at this moment + */ +esp_err_t lp_core_lp_vad_disable(lp_vad_t vad_id); + +/** + * @brief Deinit LP VAD + * + * @param[in] vad_id VAD ID + * + * @return + * - ESP_OK: On success + * - ESP_ERR_INVALID_ARG: Invalid argument + * - ESP_ERR_INVALID_STATE: Driver state is invalid, you shouldn't call this API at this moment + */ +esp_err_t lp_core_lp_vad_deinit(lp_vad_t vad_id); + +#ifdef __cplusplus +} +#endif diff --git a/components/ulp/lp_core/shared/ulp_lp_core_lp_vad_shared.c b/components/ulp/lp_core/shared/ulp_lp_core_lp_vad_shared.c new file mode 100644 index 00000000000..db78e746335 --- /dev/null +++ b/components/ulp/lp_core/shared/ulp_lp_core_lp_vad_shared.c @@ -0,0 +1,65 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/soc_caps.h" +#if SOC_LP_VAD_SUPPORTED +#include "esp_check.h" +#include "esp_err.h" +#include "ulp_lp_core_lp_vad_shared.h" +#if SOC_LP_I2S_SUPPORT_VAD +//For VAD +#include "hal/lp_i2s_ll.h" +#include "hal/lp_i2s_hal.h" +#include "esp_private/lp_i2s_private.h" +#endif //SOC_LP_I2S_SUPPORT_VAD + +//make this available for multi vad id in future +vad_unit_handle_t s_vad_handle; + +esp_err_t lp_core_lp_vad_init(lp_vad_t vad_id, const lp_core_lp_vad_cfg_t *init_config) +{ +#if IS_ULP_COCPU + // Not supported + return ESP_ERR_NOT_SUPPORTED; +#else + esp_err_t ret = lp_i2s_vad_new_unit(vad_id, init_config, &s_vad_handle); + return ret; +#endif +} + +esp_err_t lp_core_lp_vad_enable(lp_vad_t vad_id) +{ +#if IS_ULP_COCPU + // Not supported + return ESP_ERR_NOT_SUPPORTED; +#else + esp_err_t ret = lp_i2s_vad_enable(s_vad_handle); + return ret; +#endif +} + +esp_err_t lp_core_lp_vad_disable(lp_vad_t vad_id) +{ +#if IS_ULP_COCPU + // Not supported + return ESP_ERR_NOT_SUPPORTED; +#else + esp_err_t ret = lp_i2s_vad_disable(s_vad_handle); + return ret; +#endif +} + +esp_err_t lp_core_lp_vad_deinit(lp_vad_t vad_id) +{ +#if IS_ULP_COCPU + // Not supported + return ESP_ERR_NOT_SUPPORTED; +#else + esp_err_t ret = lp_i2s_vad_del_unit(s_vad_handle); + return ret; +#endif +} +#endif /* SOC_LP_VAD_SUPPORTED */ From 60c005d1dc8db9d09c2d9b04b58ee82544955880 Mon Sep 17 00:00:00 2001 From: Armando Date: Thu, 26 Sep 2024 16:20:30 +0800 Subject: [PATCH 172/472] test(vad): vad wakeup test --- .../lp_core_basic_tests/main/CMakeLists.txt | 15 +- .../main/Kconfig.projbuild | 9 + .../main/lp_core/test_main_vad.c | 18 ++ .../main/test_lp_core_vad.c | 154 ++++++++++++++++++ .../lp_core_basic_tests/main/test_vad_8k.pcm | Bin 0 -> 34272 bytes .../pytest_lp_core_basic.py | 13 ++ .../lp_core_basic_tests/sdkconfig.ci.default | 0 .../lp_core_basic_tests/sdkconfig.ci.lp_vad | 2 + 8 files changed, 210 insertions(+), 1 deletion(-) create mode 100644 components/ulp/test_apps/lp_core/lp_core_basic_tests/main/Kconfig.projbuild create mode 100644 components/ulp/test_apps/lp_core/lp_core_basic_tests/main/lp_core/test_main_vad.c create mode 100644 components/ulp/test_apps/lp_core/lp_core_basic_tests/main/test_lp_core_vad.c create mode 100644 components/ulp/test_apps/lp_core/lp_core_basic_tests/main/test_vad_8k.pcm delete mode 100644 components/ulp/test_apps/lp_core/lp_core_basic_tests/sdkconfig.ci.default create mode 100644 components/ulp/test_apps/lp_core/lp_core_basic_tests/sdkconfig.ci.lp_vad diff --git a/components/ulp/test_apps/lp_core/lp_core_basic_tests/main/CMakeLists.txt b/components/ulp/test_apps/lp_core/lp_core_basic_tests/main/CMakeLists.txt index 63d8f905d7c..239b78cf330 100644 --- a/components/ulp/test_apps/lp_core/lp_core_basic_tests/main/CMakeLists.txt +++ b/components/ulp/test_apps/lp_core/lp_core_basic_tests/main/CMakeLists.txt @@ -20,6 +20,10 @@ if(CONFIG_SOC_LP_ADC_SUPPORTED) list(APPEND app_sources "test_lp_core_adc.c") endif() +if(CONFIG_SOC_LP_VAD_SUPPORTED) + list(APPEND app_sources "test_lp_core_vad.c") +endif() + set(lp_core_sources "lp_core/test_main.c") set(lp_core_sources_counter "lp_core/test_main_counter.c") @@ -46,10 +50,15 @@ if(CONFIG_SOC_LP_ADC_SUPPORTED) set(lp_core_sources_adc "lp_core/test_main_adc.c") endif() +if(CONFIG_SOC_LP_VAD_SUPPORTED) + set(lp_core_sources_vad "lp_core/test_main_vad.c") +endif() + idf_component_register(SRCS ${app_sources} INCLUDE_DIRS "lp_core" REQUIRES ulp unity esp_timer test_utils - WHOLE_ARCHIVE) + WHOLE_ARCHIVE + EMBED_FILES "test_vad_8k.pcm") set(lp_core_exp_dep_srcs ${app_sources}) @@ -79,3 +88,7 @@ endif() if(CONFIG_SOC_LP_ADC_SUPPORTED) ulp_embed_binary(lp_core_test_app_adc "${lp_core_sources_adc}" "${lp_core_exp_dep_srcs}") endif() + +if(CONFIG_SOC_LP_VAD_SUPPORTED) + ulp_embed_binary(lp_core_test_app_vad "${lp_core_sources_vad}" "${lp_core_exp_dep_srcs}") +endif() diff --git a/components/ulp/test_apps/lp_core/lp_core_basic_tests/main/Kconfig.projbuild b/components/ulp/test_apps/lp_core/lp_core_basic_tests/main/Kconfig.projbuild new file mode 100644 index 00000000000..5783fc5daf0 --- /dev/null +++ b/components/ulp/test_apps/lp_core/lp_core_basic_tests/main/Kconfig.projbuild @@ -0,0 +1,9 @@ +menu "Test Configurations" + + config TEST_LP_CORE_VAD_ENABLE + bool "Enable LP VAD test" + default n + help + Enable this to trigger LP VAD test + +endmenu diff --git a/components/ulp/test_apps/lp_core/lp_core_basic_tests/main/lp_core/test_main_vad.c b/components/ulp/test_apps/lp_core/lp_core_basic_tests/main/lp_core/test_main_vad.c new file mode 100644 index 00000000000..5f6198fe370 --- /dev/null +++ b/components/ulp/test_apps/lp_core/lp_core_basic_tests/main/lp_core/test_main_vad.c @@ -0,0 +1,18 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +volatile bool vad_wakup; + +int main(void) +{ + vad_wakup = true; + + return 0; +} diff --git a/components/ulp/test_apps/lp_core/lp_core_basic_tests/main/test_lp_core_vad.c b/components/ulp/test_apps/lp_core/lp_core_basic_tests/main/test_lp_core_vad.c new file mode 100644 index 00000000000..16a3c059dd8 --- /dev/null +++ b/components/ulp/test_apps/lp_core/lp_core_basic_tests/main/test_lp_core_vad.c @@ -0,0 +1,154 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include +#include +#include "unity.h" +#include "freertos/FreeRTOS.h" +#include "freertos/task.h" +#include "esp_log.h" +#include "driver/lp_i2s.h" +#include "driver/lp_i2s_std.h" +#include "driver/i2s_std.h" +#include "ulp_lp_core.h" +#include "ulp_lp_core_lp_vad_shared.h" +#include "lp_core_test_app_vad.h" + +#if CONFIG_TEST_LP_CORE_VAD_ENABLE + +#define TEST_I2S_FRAME_SIZE (128) // Frame numbers in every writing / reading +#define TEST_I2S_TRANS_SIZE (4096) // Trans size + +extern const uint8_t test_vad_pcm_start[] asm("_binary_test_vad_8k_pcm_start"); +extern const uint8_t test_vad_pcm_end[] asm("_binary_test_vad_8k_pcm_end"); +extern const uint8_t lp_core_main_vad_bin_start[] asm("_binary_lp_core_test_app_vad_bin_start"); +extern const uint8_t lp_core_main_vad_bin_end[] asm("_binary_lp_core_test_app_vad_bin_end"); +static const char *TAG = "TEST_VAD"; + +static void load_and_start_lp_core_firmware(ulp_lp_core_cfg_t* cfg, const uint8_t* firmware_start, const uint8_t* firmware_end) +{ + TEST_ASSERT(ulp_lp_core_load_binary(firmware_start, + (firmware_end - firmware_start)) == ESP_OK); + + TEST_ASSERT(ulp_lp_core_run(cfg) == ESP_OK); +} + +void test_lp_vad(lp_vad_t vad_id) +{ + esp_err_t ret = ESP_FAIL; + int pcm_size = test_vad_pcm_end - test_vad_pcm_start; + printf("pcm_size: %d\n", pcm_size); + + lp_i2s_chan_handle_t rx_handle = NULL; + lp_i2s_chan_config_t config = { + .id = 0, + .role = I2S_ROLE_SLAVE, + .threshold = 512, + }; + TEST_ESP_OK(lp_i2s_new_channel(&config, NULL, &rx_handle)); + + i2s_chan_handle_t tx_handle = NULL; + i2s_chan_config_t i2s_channel_config = { + .id = I2S_NUM_0, + .role = I2S_ROLE_MASTER, + .dma_desc_num = 4, + .dma_frame_num = TEST_I2S_FRAME_SIZE, + .auto_clear = false, + }; + TEST_ESP_OK(i2s_new_channel(&i2s_channel_config, &tx_handle, NULL)); + + lp_i2s_std_config_t lp_std_cfg = { + .pin_cfg = { + .bck = 4, + .ws = 5, + .din = 6, + }, + }; + lp_std_cfg.slot_cfg = (lp_i2s_std_slot_config_t)LP_I2S_STD_PCM_SHORT_SLOT_DEFAULT_CONFIG(I2S_DATA_BIT_WIDTH_16BIT, I2S_SLOT_MODE_STEREO); + TEST_ESP_OK(lp_i2s_channel_init_std_mode(rx_handle, &lp_std_cfg)); + + i2s_std_config_t i2s_std_config = { + .gpio_cfg = { + .mclk = I2S_GPIO_UNUSED, + .bclk = GPIO_NUM_7, + .ws = GPIO_NUM_8, + .dout = GPIO_NUM_21, + .din = -1, + .invert_flags = { + .mclk_inv = false, + .bclk_inv = false, + .ws_inv = false, + }, + }, + }; + i2s_std_config.clk_cfg = (i2s_std_clk_config_t)I2S_STD_CLK_DEFAULT_CONFIG(16000); + i2s_std_config.slot_cfg = (i2s_std_slot_config_t)I2S_STD_PCM_SLOT_DEFAULT_CONFIG(I2S_DATA_BIT_WIDTH_16BIT, I2S_SLOT_MODE_STEREO); + TEST_ESP_OK(i2s_channel_init_std_mode(tx_handle, &i2s_std_config)); + + // LP VAD Init + lp_vad_init_config_t init_config = { + .lp_i2s_chan = rx_handle, + .vad_config = { + .init_frame_num = 100, + .min_energy_thresh = 100, + .speak_activity_thresh = 10, + .non_speak_activity_thresh = 30, + .min_speak_activity_thresh = 3, + .max_speak_activity_thresh = 100, + }, + }; + TEST_ESP_OK(lp_core_lp_vad_init(0, &init_config)); + + /* Load ULP firmware and start the coprocessor */ + ulp_lp_core_cfg_t cfg = { + .wakeup_source = ULP_LP_CORE_WAKEUP_SOURCE_LP_VAD, + }; + load_and_start_lp_core_firmware(&cfg, lp_core_main_vad_bin_start, lp_core_main_vad_bin_end); + + uint8_t *txbuf = (uint8_t *)heap_caps_calloc(1, TEST_I2S_TRANS_SIZE, MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL); + TEST_ASSERT(txbuf); + + uint8_t *prebuf = (uint8_t *)heap_caps_calloc(1, TEST_I2S_TRANS_SIZE, MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL); + TEST_ASSERT(prebuf); + + memcpy(prebuf, test_vad_pcm_start, TEST_I2S_TRANS_SIZE); + memcpy(txbuf, test_vad_pcm_start, TEST_I2S_TRANS_SIZE); + + for (int i = 0; i < TEST_I2S_TRANS_SIZE; i++) { + ESP_LOGD(TAG, "prebuf[%d]: %d", i, prebuf[i]); + ESP_LOGD(TAG, "txbuf[%d]: %d", i, txbuf[i]); + } + + size_t bytes_written = 0; + TEST_ESP_OK(i2s_channel_preload_data(tx_handle, prebuf, TEST_I2S_TRANS_SIZE, &bytes_written)); + TEST_ESP_OK(lp_i2s_channel_enable(rx_handle)); + TEST_ESP_OK(lp_core_lp_vad_enable(0)); + TEST_ESP_OK(i2s_channel_enable(tx_handle)); + + ret = i2s_channel_write(tx_handle, txbuf, TEST_I2S_TRANS_SIZE, &bytes_written, 0); + if (ret != ESP_OK && ret != ESP_ERR_TIMEOUT) { + TEST_ESP_OK(ret); + } + ESP_LOGD(TAG, "bytes_written: %d", bytes_written); + + while (!ulp_vad_wakup) { + ; + } + + ESP_LOGI(TAG, "wakeup"); + + TEST_ESP_OK(lp_i2s_channel_disable(rx_handle)); + TEST_ESP_OK(lp_i2s_del_channel(rx_handle)); + TEST_ESP_OK(i2s_channel_disable(tx_handle)); + TEST_ESP_OK(i2s_del_channel(tx_handle)); + free(txbuf); + free(prebuf); +} + +TEST_CASE("LP VAD wakeup test", "[lp_core][lp_vad]") +{ + test_lp_vad(0); +} +#endif //CONFIG_TEST_LP_CORE_VAD_ENABLE diff --git a/components/ulp/test_apps/lp_core/lp_core_basic_tests/main/test_vad_8k.pcm b/components/ulp/test_apps/lp_core/lp_core_basic_tests/main/test_vad_8k.pcm new file mode 100644 index 0000000000000000000000000000000000000000..5b6c32a03731f5cee7ba8bfa178b38477ac7f5f4 GIT binary patch literal 34272 zcmYhkXLwZA_x^qA%p{YZKp-RpkS+*HQ>>sAQE4J7BF!&|s7Oat6u}BoREqQ_B8Ujm zK@{fP{3jP%Q zC$I$L)$wYIo}#}Yh-eY5s-S_OLQqYwrq9x5XPyN?%Cmx31lnRwokJm2?nhX9@|5NuV`;^}V#e#A{3qhuv=`MAaI@1K_ z1%B7>&U5BDO$0u{AVFBr-RO%!YrXs+hI>%8kcE=Upd6kHXgxoK_{!B>J;wO6$f z<_PnMpuf@I7_1EziQcb`)<^5Z1c$Uk+P&(%s#ozU$pW9CilBqr!F|wq&`y;_R zK}V;f^Ms(S;32^-!6WV??rZ^*`-$?2a+iLWUe8m{vsG}|IBZnWs%W1ppDP~;4!8&0 z9s*Nv$~omsa3{EZ1Z@QuoC{8C!99Wv_6GZg;Iwnv+2U?-?^f?tM+(*mx(ntibCt&h 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zFgau9-ss8R29S@WPla4J^-0!rU^WFI~@FPGU0eN%kF#q?DlMnd?SOxx$T4yOh z4>`RHyoUVF`^mq7+#|Im-Y;?;X8`ikHzBLe5UUJ_ANLz_Db$Rp2a!i3x3v(U9=Qov1CWd5y`=8M`%k@#IuJh(|Azkp8HK=< literal 0 HcmV?d00001 diff --git a/components/ulp/test_apps/lp_core/lp_core_basic_tests/pytest_lp_core_basic.py b/components/ulp/test_apps/lp_core/lp_core_basic_tests/pytest_lp_core_basic.py index 53178dca4e8..33e7b3c9507 100644 --- a/components/ulp/test_apps/lp_core/lp_core_basic_tests/pytest_lp_core_basic.py +++ b/components/ulp/test_apps/lp_core/lp_core_basic_tests/pytest_lp_core_basic.py @@ -33,6 +33,19 @@ def test_lp_core_xtal(dut: Dut) -> None: dut.run_all_single_board_cases() +@pytest.mark.esp32p4 +@pytest.mark.lp_i2s +@pytest.mark.parametrize( + 'config', + [ + 'lp_vad', + ], + indirect=True, +) +def test_lp_vad(dut: Dut) -> None: + dut.run_all_single_board_cases(group='lp_vad') + + @pytest.mark.esp32c6 # TODO: Enable LP I2C test for esp32p4 (IDF-9407) @pytest.mark.generic_multi_device diff --git a/components/ulp/test_apps/lp_core/lp_core_basic_tests/sdkconfig.ci.default b/components/ulp/test_apps/lp_core/lp_core_basic_tests/sdkconfig.ci.default deleted file mode 100644 index e69de29bb2d..00000000000 diff --git a/components/ulp/test_apps/lp_core/lp_core_basic_tests/sdkconfig.ci.lp_vad b/components/ulp/test_apps/lp_core/lp_core_basic_tests/sdkconfig.ci.lp_vad new file mode 100644 index 00000000000..8397edb939d --- /dev/null +++ b/components/ulp/test_apps/lp_core/lp_core_basic_tests/sdkconfig.ci.lp_vad @@ -0,0 +1,2 @@ +CONFIG_TEST_LP_CORE_VAD_ENABLE=y +CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG=y From 6db48cff2574dab3d0e65d6bf76f6d2526c0daaf Mon Sep 17 00:00:00 2001 From: Armando Date: Wed, 9 Oct 2024 11:26:57 +0800 Subject: [PATCH 173/472] feat(sleep): support vad wakeup hp core --- .../include/esp_private/esp_pmu.h | 8 +++++++ .../include/esp_private/esp_sleep_internal.h | 1 + components/esp_hw_support/include/esp_sleep.h | 11 ++++++++++ .../esp_hw_support/port/esp32p4/pmu_sleep.c | 5 +++++ components/esp_hw_support/sleep_modes.c | 21 ++++++++++++++++++- .../hal/esp32p4/include/hal/clk_gate_ll.h | 13 ++++++++++++ .../esp32p4/include/soc/Kconfig.soc_caps.in | 8 +++++++ components/soc/esp32p4/include/soc/soc_caps.h | 2 ++ 8 files changed, 68 insertions(+), 1 deletion(-) diff --git a/components/esp_hw_support/include/esp_private/esp_pmu.h b/components/esp_hw_support/include/esp_private/esp_pmu.h index 5b481946074..6d347788a24 100644 --- a/components/esp_hw_support/include/esp_private/esp_pmu.h +++ b/components/esp_hw_support/include/esp_private/esp_pmu.h @@ -50,6 +50,7 @@ typedef enum { #define RTC_SLEEP_USE_ADC_TESEN_MONITOR BIT(17) #define RTC_SLEEP_NO_ULTRA_LOW BIT(18) //!< Avoid using ultra low power in deep sleep, in which RTCIO cannot be used as input, and RTCMEM can't work under high temperature #define RTC_SLEEP_XTAL_AS_RTC_FAST BIT(19) +#define RTC_SLEEP_LP_PERIPH_USE_XTAL BIT(20) #if SOC_PM_SUPPORT_EXT0_WAKEUP #define RTC_EXT0_TRIG_EN PMU_EXT0_WAKEUP_EN //!< EXT0 wakeup @@ -109,6 +110,12 @@ typedef enum { #define RTC_LP_CORE_TRIG_EN 0 #endif //SOC_LP_CORE_SUPPORTED +#if SOC_LP_VAD_SUPPORTED +#define RTC_LP_VAD_TRIG_EN PMU_LP_I2S_WAKEUP_EN //!< LP VAD wakeup +#else +#define RTC_LP_VAD_TRIG_EN 0 +#endif //SOC_LP_VAD_SUPPORTED + #define RTC_XTAL32K_DEAD_TRIG_EN 0 // TODO #define RTC_BROWNOUT_DET_TRIG_EN 0 // TODO @@ -127,6 +134,7 @@ typedef enum { RTC_TOUCH_TRIG_EN | \ RTC_XTAL32K_DEAD_TRIG_EN | \ RTC_USB_TRIG_EN | \ + RTC_LP_VAD_TRIG_EN | \ RTC_BROWNOUT_DET_TRIG_EN) diff --git a/components/esp_hw_support/include/esp_private/esp_sleep_internal.h b/components/esp_hw_support/include/esp_private/esp_sleep_internal.h index df9c2a79e29..7805b714959 100644 --- a/components/esp_hw_support/include/esp_private/esp_sleep_internal.h +++ b/components/esp_hw_support/include/esp_private/esp_sleep_internal.h @@ -38,6 +38,7 @@ typedef enum { ESP_SLEEP_ULTRA_LOW_MODE, //!< In ultra low mode, 2uA is saved, but RTC memory can't use at high temperature, and RTCIO can't be used as INPUT. ESP_SLEEP_RTC_FAST_USE_XTAL_MODE, //!< The mode in which the crystal is used as the RTC_FAST clock source, need keep XTAL on in HP_SLEEP mode when ULP is working. ESP_SLEEP_DIG_USE_XTAL_MODE, //!< The mode requested by digital peripherals to keep XTAL clock on during sleep (both HP_SLEEP and LP_SLEEP mode). (!!! Only valid for lightsleep, will override the XTAL domain config by esp_sleep_pd_config) + ESP_SLEEP_LP_USE_XTAL_MODE, //!< The mode requested by lp peripherals to keep XTAL clock on during sleep. Only valid for lightsleep. ESP_SLEEP_MODE_MAX, } esp_sleep_sub_mode_t; diff --git a/components/esp_hw_support/include/esp_sleep.h b/components/esp_hw_support/include/esp_sleep.h index de25aeb2683..76233f1d627 100644 --- a/components/esp_hw_support/include/esp_sleep.h +++ b/components/esp_hw_support/include/esp_sleep.h @@ -118,6 +118,7 @@ typedef enum { ESP_SLEEP_WAKEUP_COCPU, //!< Wakeup caused by COCPU int ESP_SLEEP_WAKEUP_COCPU_TRAP_TRIG, //!< Wakeup caused by COCPU crash ESP_SLEEP_WAKEUP_BT, //!< Wakeup caused by BT (light sleep only) + ESP_SLEEP_WAKEUP_VAD, //!< Wakeup caused by VAD } esp_sleep_source_t; /** @@ -179,6 +180,16 @@ esp_err_t esp_sleep_enable_ulp_wakeup(void); */ esp_err_t esp_sleep_enable_timer_wakeup(uint64_t time_in_us); +#if SOC_LP_VAD_SUPPORTED +/** + * @brief Enable wakeup by VAD + * + * @return + * - ESP_OK on success + */ +esp_err_t esp_sleep_enable_vad_wakeup(void); +#endif + #if SOC_TOUCH_SENSOR_SUPPORTED /** * @brief Enable wakeup by touch sensor diff --git a/components/esp_hw_support/port/esp32p4/pmu_sleep.c b/components/esp_hw_support/port/esp32p4/pmu_sleep.c index 97c112aa6b5..b6be295d109 100644 --- a/components/esp_hw_support/port/esp32p4/pmu_sleep.c +++ b/components/esp_hw_support/port/esp32p4/pmu_sleep.c @@ -29,6 +29,7 @@ #include "hal/pmu_hal.h" #include "hal/psram_ctrlr_ll.h" #include "hal/lp_sys_ll.h" +#include "hal/clk_gate_ll.h" #include "esp_private/esp_pmu.h" #include "pmu_param.h" #include "esp_rom_sys.h" @@ -202,6 +203,10 @@ const pmu_sleep_config_t* pmu_sleep_config_default( config->analog.hp_sys.analog.dbias = HP_CALI_ACTIVE_DBIAS_DEFAULT; } + if (sleep_flags & RTC_SLEEP_LP_PERIPH_USE_XTAL) { + _clk_gate_ll_xtal_to_lp_periph_en(true); + } + config->power = power_default; pmu_sleep_param_config_t param_default = PMU_SLEEP_PARAM_CONFIG_DEFAULT(sleep_flags); config->param = *pmu_sleep_param_config_default(¶m_default, &power_default, sleep_flags, adjustment, slowclk_period, fastclk_period); diff --git a/components/esp_hw_support/sleep_modes.c b/components/esp_hw_support/sleep_modes.c index ed81134542d..b790ade7385 100644 --- a/components/esp_hw_support/sleep_modes.c +++ b/components/esp_hw_support/sleep_modes.c @@ -222,7 +222,7 @@ typedef struct { } domain[ESP_PD_DOMAIN_MAX]; portMUX_TYPE lock; uint64_t sleep_duration; - uint32_t wakeup_triggers : 15; + uint32_t wakeup_triggers : 20; #if SOC_PM_SUPPORT_EXT1_WAKEUP uint32_t ext1_trigger_mode : 22; // 22 is the maximum RTCIO number in all chips uint32_t ext1_rtc_gpio_mask : 22; @@ -917,6 +917,12 @@ static esp_err_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags, esp_sleep_mode_t m sleep_flags |= RTC_SLEEP_XTAL_AS_RTC_FAST; } +#if SOC_LP_VAD_SUPPORTED + if (s_sleep_sub_mode_ref_cnt[ESP_SLEEP_LP_USE_XTAL_MODE] && !deep_sleep) { + sleep_flags |= RTC_SLEEP_LP_PERIPH_USE_XTAL; + } +#endif + #if CONFIG_ESP_SLEEP_DEBUG if (s_sleep_ctx != NULL) { s_sleep_ctx->sleep_flags = sleep_flags; @@ -1645,6 +1651,14 @@ esp_err_t esp_sleep_enable_timer_wakeup(uint64_t time_in_us) return ESP_OK; } +#if SOC_LP_VAD_SUPPORTED +esp_err_t esp_sleep_enable_vad_wakeup(void) +{ + s_config.wakeup_triggers |= RTC_LP_VAD_TRIG_EN; + return esp_sleep_sub_mode_config(ESP_SLEEP_LP_USE_XTAL_MODE, true); +} +#endif + static esp_err_t timer_wakeup_prepare(int64_t sleep_duration) { if (sleep_duration < 0) { @@ -2165,6 +2179,10 @@ esp_sleep_wakeup_cause_t esp_sleep_get_wakeup_cause(void) #if SOC_LP_CORE_SUPPORTED } else if (wakeup_cause & RTC_LP_CORE_TRIG_EN) { return ESP_SLEEP_WAKEUP_ULP; +#endif +#if SOC_LP_VAD_SUPPORTED + } else if (wakeup_cause & RTC_LP_VAD_TRIG_EN) { + return ESP_SLEEP_WAKEUP_VAD; #endif } else { return ESP_SLEEP_WAKEUP_UNDEFINED; @@ -2229,6 +2247,7 @@ int32_t* esp_sleep_sub_mode_dump_config(FILE *stream) { [ESP_SLEEP_ULTRA_LOW_MODE] = "ESP_SLEEP_ULTRA_LOW_MODE", [ESP_SLEEP_RTC_FAST_USE_XTAL_MODE] = "ESP_SLEEP_RTC_FAST_USE_XTAL_MODE", [ESP_SLEEP_DIG_USE_XTAL_MODE] = "ESP_SLEEP_DIG_USE_XTAL_MODE", + [ESP_SLEEP_LP_USE_XTAL_MODE] = "ESP_SLEEP_LP_USE_XTAL_MODE", }[mode], s_sleep_sub_mode_ref_cnt[mode] ? "ENABLED" : "DISABLED", s_sleep_sub_mode_ref_cnt[mode]); diff --git a/components/hal/esp32p4/include/hal/clk_gate_ll.h b/components/hal/esp32p4/include/hal/clk_gate_ll.h index 8c5fc05cfbf..9a49fd41e01 100644 --- a/components/hal/esp32p4/include/hal/clk_gate_ll.h +++ b/components/hal/esp32p4/include/hal/clk_gate_ll.h @@ -14,6 +14,7 @@ extern "C" { #include #include "esp_attr.h" #include "soc/hp_sys_clkrst_struct.h" +#include "soc/lp_clkrst_struct.h" /** * Enable or disable the clock gate for ref_20m. @@ -75,6 +76,18 @@ FORCE_INLINE_ATTR void _clk_gate_ll_ref_240m_clk_en(bool enable) /// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance #define clk_gate_ll_ref_240m_clk_en(...) (void)__DECLARE_RCC_ATOMIC_ENV; _clk_gate_ll_ref_240m_clk_en(__VA_ARGS__) +/** + * Enable or disable the clock gate for xtal to lp periph + * @param enable Enable / disable + */ +FORCE_INLINE_ATTR void _clk_gate_ll_xtal_to_lp_periph_en(bool enable) +{ + LP_AON_CLKRST.lp_clk_en.xtal_clk_force_on = enable; +} +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance +#define clk_gate_ll_xtal_to_lp_periph_en(...) (void)__DECLARE_RCC_ATOMIC_ENV; _clk_gate_ll_xtal_to_lp_periph_en(__VA_ARGS__) + #ifdef __cplusplus } #endif diff --git a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in index eac76a74a3f..ed47efb4463 100644 --- a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in @@ -1859,6 +1859,14 @@ config SOC_PM_PAU_REGDMA_UPDATE_CACHE_BEFORE_WAIT_COMPARE bool default y +config SOC_SLEEP_SYSTIMER_STALL_WORKAROUND + bool + default y + +config SOC_SLEEP_TGWDT_STOP_WORKAROUND + bool + default y + config SOC_PSRAM_VDD_POWER_MPLL bool default y diff --git a/components/soc/esp32p4/include/soc/soc_caps.h b/components/soc/esp32p4/include/soc/soc_caps.h index 16d2aa76438..bf411fb3b79 100644 --- a/components/soc/esp32p4/include/soc/soc_caps.h +++ b/components/soc/esp32p4/include/soc/soc_caps.h @@ -702,6 +702,8 @@ #define SOC_CPU_IN_TOP_DOMAIN (1) #define SOC_PM_PAU_REGDMA_UPDATE_CACHE_BEFORE_WAIT_COMPARE (1) +#define SOC_SLEEP_SYSTIMER_STALL_WORKAROUND 1 //TODO IDF-11381: replace with all xtal field clk gate control +#define SOC_SLEEP_TGWDT_STOP_WORKAROUND 1 //TODO IDF-11381: replace with all xtal field clk gate control /*-------------------------- PSRAM CAPS ----------------------------*/ #define SOC_PSRAM_VDD_POWER_MPLL (1) From 56af6b5fc4fe1fcef4a44bfc6f2341bcc93b55da Mon Sep 17 00:00:00 2001 From: Armando Date: Wed, 9 Oct 2024 14:50:00 +0800 Subject: [PATCH 174/472] test(sleep): vad wakeup hp core test --- .../test_apps/lp_i2s/sdkconfig.ci.defaults | 1 - .../test_apps/.build-test-rules.yml | 4 + .../test_apps/vad_wakeup/CMakeLists.txt | 8 + .../test_apps/vad_wakeup/README.md | 3 + .../test_apps/vad_wakeup/main/CMakeLists.txt | 7 + .../test_apps/vad_wakeup/main/test_app_main.c | 27 +++ .../test_apps/vad_wakeup/main/test_vad_8k.pcm | Bin 0 -> 34272 bytes .../vad_wakeup/main/test_vad_wakeup.c | 162 ++++++++++++++++++ .../test_apps/vad_wakeup/pytest_wakeup_vad.py | 11 ++ .../test_apps/vad_wakeup/sdkconfig.defaults | 8 + .../lp_core_basic_tests/sdkconfig.ci.lp_vad | 1 - 11 files changed, 230 insertions(+), 2 deletions(-) create mode 100644 components/esp_hw_support/test_apps/vad_wakeup/CMakeLists.txt create mode 100644 components/esp_hw_support/test_apps/vad_wakeup/README.md create mode 100644 components/esp_hw_support/test_apps/vad_wakeup/main/CMakeLists.txt create mode 100644 components/esp_hw_support/test_apps/vad_wakeup/main/test_app_main.c create mode 100644 components/esp_hw_support/test_apps/vad_wakeup/main/test_vad_8k.pcm create mode 100644 components/esp_hw_support/test_apps/vad_wakeup/main/test_vad_wakeup.c create mode 100644 components/esp_hw_support/test_apps/vad_wakeup/pytest_wakeup_vad.py create mode 100644 components/esp_hw_support/test_apps/vad_wakeup/sdkconfig.defaults diff --git a/components/esp_driver_i2s/test_apps/lp_i2s/sdkconfig.ci.defaults b/components/esp_driver_i2s/test_apps/lp_i2s/sdkconfig.ci.defaults index 5e9f8e25bd8..e69de29bb2d 100644 --- a/components/esp_driver_i2s/test_apps/lp_i2s/sdkconfig.ci.defaults +++ b/components/esp_driver_i2s/test_apps/lp_i2s/sdkconfig.ci.defaults @@ -1 +0,0 @@ -CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG=y diff --git a/components/esp_hw_support/test_apps/.build-test-rules.yml b/components/esp_hw_support/test_apps/.build-test-rules.yml index b61d8878c6c..a13010cf3aa 100644 --- a/components/esp_hw_support/test_apps/.build-test-rules.yml +++ b/components/esp_hw_support/test_apps/.build-test-rules.yml @@ -42,6 +42,10 @@ components/esp_hw_support/test_apps/rtc_power_modes: temporary: true reason: the other targets are not tested yet +components/esp_hw_support/test_apps/vad_wakeup: + disable: + - if: SOC_LP_VAD_SUPPORTED != 1 + components/esp_hw_support/test_apps/wakeup_tests: disable: - if: IDF_TARGET in ["esp32c5", "esp32p4", "linux", "esp32c61"] diff --git a/components/esp_hw_support/test_apps/vad_wakeup/CMakeLists.txt b/components/esp_hw_support/test_apps/vad_wakeup/CMakeLists.txt new file mode 100644 index 00000000000..50365600115 --- /dev/null +++ b/components/esp_hw_support/test_apps/vad_wakeup/CMakeLists.txt @@ -0,0 +1,8 @@ +# This is the project CMakeLists.txt file for the test subproject +cmake_minimum_required(VERSION 3.16) + +# "Trim" the build. Include the minimal set of components, main, and anything it depends on. +set(COMPONENTS main) + +include($ENV{IDF_PATH}/tools/cmake/project.cmake) +project(vad_wakeup) diff --git a/components/esp_hw_support/test_apps/vad_wakeup/README.md b/components/esp_hw_support/test_apps/vad_wakeup/README.md new file mode 100644 index 00000000000..f8ea707124d --- /dev/null +++ b/components/esp_hw_support/test_apps/vad_wakeup/README.md @@ -0,0 +1,3 @@ +| Supported Targets | ESP32-P4 | +| ----------------- | -------- | + diff --git a/components/esp_hw_support/test_apps/vad_wakeup/main/CMakeLists.txt b/components/esp_hw_support/test_apps/vad_wakeup/main/CMakeLists.txt new file mode 100644 index 00000000000..3a92a5d2bd7 --- /dev/null +++ b/components/esp_hw_support/test_apps/vad_wakeup/main/CMakeLists.txt @@ -0,0 +1,7 @@ +set(srcs "test_app_main.c" + "test_vad_wakeup.c") + +idf_component_register(SRCS ${srcs} + REQUIRES unity esp_driver_i2s esp_driver_uart ulp esp_timer + WHOLE_ARCHIVE + EMBED_FILES "test_vad_8k.pcm") diff --git a/components/esp_hw_support/test_apps/vad_wakeup/main/test_app_main.c b/components/esp_hw_support/test_apps/vad_wakeup/main/test_app_main.c new file mode 100644 index 00000000000..1d34b63e446 --- /dev/null +++ b/components/esp_hw_support/test_apps/vad_wakeup/main/test_app_main.c @@ -0,0 +1,27 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "unity.h" +#include "unity_test_runner.h" +#include "unity_test_utils.h" + +#define LEAKS (400) + + +void setUp(void) +{ + unity_utils_record_free_mem(); +} + +void tearDown(void) +{ + unity_utils_evaluate_leaks_direct(LEAKS); +} + +void app_main(void) +{ + unity_run_menu(); +} diff --git a/components/esp_hw_support/test_apps/vad_wakeup/main/test_vad_8k.pcm b/components/esp_hw_support/test_apps/vad_wakeup/main/test_vad_8k.pcm new file mode 100644 index 0000000000000000000000000000000000000000..5b6c32a03731f5cee7ba8bfa178b38477ac7f5f4 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SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Unlicense OR CC0-1.0 + */ + +#include +#include +#include +#include "freertos/FreeRTOS.h" +#include "freertos/task.h" +#include "esp_sleep.h" +#include "esp_log.h" +#include "driver/uart.h" +#include "driver/lp_i2s.h" +#include "driver/lp_i2s_std.h" +#include "driver/i2s_std.h" +#include "ulp_lp_core_lp_vad_shared.h" +#include "unity.h" +#include "esp_timer.h" + +#define TEST_I2S_FRAME_SIZE (128) // Frame numbers in every writing / reading +#define TEST_I2S_TRANS_SIZE (4096) // Trans size +#define TEST_LP_I2S_PIN_BCK 4 +#define TEST_LP_I2S_PIN_WS 5 +#define TEST_LP_I2S_PIN_DIN 6 + + +extern const uint8_t test_vad_pcm_start[] asm("_binary_test_vad_8k_pcm_start"); +extern const uint8_t test_vad_pcm_end[] asm("_binary_test_vad_8k_pcm_end"); +static const char *TAG = "TEST_VAD"; + +static void s_hp_i2s_config(void) +{ + esp_err_t ret = ESP_FAIL; + int pcm_size = test_vad_pcm_end - test_vad_pcm_start; + printf("pcm_size: %d\n", pcm_size); + + i2s_chan_handle_t tx_handle = NULL; + i2s_chan_config_t i2s_channel_config = { + .id = I2S_NUM_0, + .role = I2S_ROLE_MASTER, + .dma_desc_num = 16, + .dma_frame_num = TEST_I2S_FRAME_SIZE, + .auto_clear = false, + }; + TEST_ESP_OK(i2s_new_channel(&i2s_channel_config, &tx_handle, NULL)); + + + i2s_std_config_t i2s_std_config = { + .gpio_cfg = { + .mclk = I2S_GPIO_UNUSED, + .bclk = GPIO_NUM_7, + .ws = GPIO_NUM_8, + .dout = GPIO_NUM_21, + .din = -1, + .invert_flags = { + .mclk_inv = false, + .bclk_inv = false, + .ws_inv = false, + }, + }, + }; + i2s_std_config.clk_cfg = (i2s_std_clk_config_t)I2S_STD_CLK_DEFAULT_CONFIG(16000); + i2s_std_config.slot_cfg = (i2s_std_slot_config_t)I2S_STD_PCM_SLOT_DEFAULT_CONFIG(I2S_DATA_BIT_WIDTH_16BIT, I2S_SLOT_MODE_STEREO); + TEST_ESP_OK(i2s_channel_init_std_mode(tx_handle, &i2s_std_config)); + + + uint8_t *txbuf = (uint8_t *)heap_caps_calloc(1, TEST_I2S_TRANS_SIZE, MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL); + TEST_ASSERT(txbuf); + + uint8_t *prebuf = (uint8_t *)heap_caps_calloc(1, TEST_I2S_TRANS_SIZE, MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL); + TEST_ASSERT(prebuf); + + memcpy(prebuf, test_vad_pcm_start, TEST_I2S_TRANS_SIZE); + memcpy(txbuf, test_vad_pcm_start, TEST_I2S_TRANS_SIZE); + + for (int i = 0; i < TEST_I2S_TRANS_SIZE; i++) { + ESP_LOGD(TAG, "prebuf[%d]: %d", i, prebuf[i]); + ESP_LOGD(TAG, "txbuf[%d]: %d", i, txbuf[i]); + } + + size_t bytes_written = 0; + TEST_ESP_OK(i2s_channel_preload_data(tx_handle, prebuf, TEST_I2S_TRANS_SIZE, &bytes_written)); + + TEST_ESP_OK(i2s_channel_enable(tx_handle)); + + while (1) { + ret = i2s_channel_write(tx_handle, txbuf, TEST_I2S_TRANS_SIZE, &bytes_written, 0); + if (ret != ESP_OK && ret != ESP_ERR_TIMEOUT) { + TEST_ESP_OK(ret); + } + ESP_LOGD(TAG, "bytes_written: %d", bytes_written); + vTaskDelay(1); + } +} + +static void s_lp_vad_config(void) +{ + ESP_ERROR_CHECK(esp_sleep_enable_vad_wakeup()); + ESP_ERROR_CHECK(esp_sleep_pd_config(ESP_PD_DOMAIN_RTC_PERIPH, ESP_PD_OPTION_ON)); + ESP_ERROR_CHECK(esp_sleep_pd_config(ESP_PD_DOMAIN_XTAL, ESP_PD_OPTION_ON)); + + lp_i2s_chan_handle_t rx_handle = NULL; + lp_i2s_chan_config_t config = { + .id = 0, + .role = I2S_ROLE_SLAVE, + .threshold = 512, + }; + TEST_ESP_OK(lp_i2s_new_channel(&config, NULL, &rx_handle)); + + lp_i2s_std_config_t lp_std_cfg = { + .pin_cfg = { + .bck = TEST_LP_I2S_PIN_BCK, + .ws = TEST_LP_I2S_PIN_WS, + .din = TEST_LP_I2S_PIN_DIN, + }, + }; + lp_std_cfg.slot_cfg = (lp_i2s_std_slot_config_t)LP_I2S_STD_PCM_SHORT_SLOT_DEFAULT_CONFIG(I2S_DATA_BIT_WIDTH_16BIT, I2S_SLOT_MODE_STEREO); + TEST_ESP_OK(lp_i2s_channel_init_std_mode(rx_handle, &lp_std_cfg)); + + // LP VAD Init + lp_vad_init_config_t init_config = { + .lp_i2s_chan = rx_handle, + .vad_config = { + .init_frame_num = 100, + .min_energy_thresh = 100, + .speak_activity_thresh = 10, + .non_speak_activity_thresh = 30, + .min_speak_activity_thresh = 3, + .max_speak_activity_thresh = 100, + }, + }; + TEST_ESP_OK(lp_core_lp_vad_init(0, &init_config)); + TEST_ESP_OK(lp_i2s_channel_enable(rx_handle)); + TEST_ESP_OK(lp_core_lp_vad_enable(0)); + + printf("Entering light sleep\n"); + /* To make sure the complete line is printed before entering sleep mode, + * need to wait until UART TX FIFO is empty: + */ + uart_wait_tx_idle_polling(CONFIG_ESP_CONSOLE_UART_NUM); + + /* Enter sleep mode */ + esp_light_sleep_start(); + + /* Determine wake up reason */ + const char* wakeup_reason; + switch (esp_sleep_get_wakeup_cause()) { + case ESP_SLEEP_WAKEUP_VAD: + wakeup_reason = "vad"; + break; + default: + wakeup_reason = "other"; + TEST_ASSERT(false); + break; + } + + ESP_LOGI(TAG, "wakeup, reason: %s", wakeup_reason); +} + +TEST_CASE_MULTIPLE_DEVICES("test LP VAD wakeup", "[vad][ignore][manual]", s_hp_i2s_config, s_lp_vad_config); diff --git a/components/esp_hw_support/test_apps/vad_wakeup/pytest_wakeup_vad.py b/components/esp_hw_support/test_apps/vad_wakeup/pytest_wakeup_vad.py new file mode 100644 index 00000000000..b4d9f85affd --- /dev/null +++ b/components/esp_hw_support/test_apps/vad_wakeup/pytest_wakeup_vad.py @@ -0,0 +1,11 @@ +# SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD +# SPDX-License-Identifier: Unlicense OR CC0-1.0 +import pytest +from pytest_embedded import Dut + + +@pytest.mark.esp32p4 +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='lack of runners for now') +@pytest.mark.lp_i2s +def test_efuse(dut: Dut) -> None: + dut.run_all_single_board_cases() diff --git a/components/esp_hw_support/test_apps/vad_wakeup/sdkconfig.defaults b/components/esp_hw_support/test_apps/vad_wakeup/sdkconfig.defaults new file mode 100644 index 00000000000..cac3f9a01f9 --- /dev/null +++ b/components/esp_hw_support/test_apps/vad_wakeup/sdkconfig.defaults @@ -0,0 +1,8 @@ +CONFIG_ESP_TASK_WDT_INIT=n + +CONFIG_ULP_COPROC_ENABLED=y +CONFIG_ULP_COPROC_TYPE_LP_CORE=y +CONFIG_ULP_COPROC_RESERVE_MEM=12000 +CONFIG_ULP_PANIC_OUTPUT_ENABLE=y + +CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG=y diff --git a/components/ulp/test_apps/lp_core/lp_core_basic_tests/sdkconfig.ci.lp_vad b/components/ulp/test_apps/lp_core/lp_core_basic_tests/sdkconfig.ci.lp_vad index 8397edb939d..766d6c83cde 100644 --- a/components/ulp/test_apps/lp_core/lp_core_basic_tests/sdkconfig.ci.lp_vad +++ b/components/ulp/test_apps/lp_core/lp_core_basic_tests/sdkconfig.ci.lp_vad @@ -1,2 +1 @@ CONFIG_TEST_LP_CORE_VAD_ENABLE=y -CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG=y From 4cbc790628777f1c1d131a4203ec87c4195f5d5e Mon Sep 17 00:00:00 2001 From: "C.S.M" Date: Fri, 27 Sep 2024 19:11:30 +0800 Subject: [PATCH 175/472] feat(temperature_sensor): Add sleep retention support for temperature sensor --- .../include/driver/temperature_sensor.h | 8 ++- .../esp_driver_tsens/src/temperature_sensor.c | 52 +++++++++++++++ .../src/temperature_sensor_private.h | 5 +- .../temperature_sensor/main/CMakeLists.txt | 2 +- .../main/test_temperature_sensor.c | 63 ++++++++++++++++++- .../temperature_sensor/sdkconfig.ci.release | 1 + .../temperature_sensor/sdkconfig.defaults | 2 + .../include/esp_private/regi2c_ctrl.h | 9 ++- components/esp_hw_support/regi2c_ctrl.c | 21 ++++++- components/esp_hw_support/sleep_modes.c | 6 ++ .../esp32c5/include/soc/Kconfig.soc_caps.in | 8 +++ .../include/soc/retention_periph_defs.h | 3 + components/soc/esp32c5/include/soc/soc_caps.h | 2 + .../soc/esp32c5/temperature_sensor_periph.c | 24 +++++++ .../esp32c6/include/soc/Kconfig.soc_caps.in | 8 +++ .../include/soc/retention_periph_defs.h | 3 + components/soc/esp32c6/include/soc/soc_caps.h | 2 + .../soc/esp32c6/temperature_sensor_periph.c | 26 +++++++- .../esp32h2/include/soc/Kconfig.soc_caps.in | 8 +++ .../include/soc/retention_periph_defs.h | 3 + components/soc/esp32h2/include/soc/soc_caps.h | 2 + .../soc/esp32h2/temperature_sensor_periph.c | 27 +++++++- .../esp32p4/include/soc/Kconfig.soc_caps.in | 4 ++ components/soc/esp32p4/include/soc/soc_caps.h | 2 + components/soc/include/soc/regdma.h | 2 + .../include/soc/temperature_sensor_periph.h | 17 ++++- .../api-reference/peripherals/temp_sensor.rst | 1 + .../api-reference/system/power_management.rst | 1 + .../api-reference/peripherals/temp_sensor.rst | 1 + .../api-reference/system/power_management.rst | 1 + 30 files changed, 305 insertions(+), 9 deletions(-) diff --git a/components/esp_driver_tsens/include/driver/temperature_sensor.h b/components/esp_driver_tsens/include/driver/temperature_sensor.h index 3c2c18dc1c5..fc968dfb0fa 100644 --- a/components/esp_driver_tsens/include/driver/temperature_sensor.h +++ b/components/esp_driver_tsens/include/driver/temperature_sensor.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -30,6 +30,12 @@ typedef struct { int range_min; /**< the minimum value of the temperature you want to test */ int range_max; /**< the maximum value of the temperature you want to test */ temperature_sensor_clk_src_t clk_src; /**< the clock source of the temperature sensor. */ + struct { + uint32_t allow_pd; /**< If set, the driver will backup/restore the temperature sensor registers before/after entering/exist sleep mode. + By this approach, the system can power off temperature sensor's power domain. + This can save power, but at the expense of more RAM being consumed */ + } flags; /**< Temperature sensor config flags */ + } temperature_sensor_config_t; /** diff --git a/components/esp_driver_tsens/src/temperature_sensor.c b/components/esp_driver_tsens/src/temperature_sensor.c index 2bf39ca9bf2..39e44afb9b5 100644 --- a/components/esp_driver_tsens/src/temperature_sensor.c +++ b/components/esp_driver_tsens/src/temperature_sensor.c @@ -29,6 +29,9 @@ #include "soc/temperature_sensor_periph.h" #include "esp_memory_utils.h" #include "esp_private/sar_periph_ctrl.h" +#if TEMPERATURE_SENSOR_USE_RETENTION_LINK +#include "esp_private/sleep_retention.h" +#endif static const char *TAG = "temperature_sensor"; @@ -93,6 +96,26 @@ static void IRAM_ATTR temperature_sensor_isr(void *arg) } #endif // SOC_TEMPERATURE_SENSOR_INTR_SUPPORT +#if TEMPERATURE_SENSOR_USE_RETENTION_LINK +static esp_err_t s_temperature_sensor_sleep_retention_init(void *arg) +{ + esp_err_t ret = sleep_retention_entries_create(temperature_sensor_regs_retention.link_list, temperature_sensor_regs_retention.link_num, REGDMA_LINK_PRI_TEMPERATURE_SENSOR, temperature_sensor_regs_retention.module_id); + ESP_RETURN_ON_ERROR(ret, TAG, "failed to allocate mem for sleep retention"); + return ret; +} + +void temperature_sensor_create_retention_module(temperature_sensor_handle_t tsens) +{ + sleep_retention_module_t module_id = temperature_sensor_regs_retention.module_id; + if ((sleep_retention_get_inited_modules() & BIT(module_id)) && !(sleep_retention_get_created_modules() & BIT(module_id))) { + if (sleep_retention_module_allocate(module_id) != ESP_OK) { + // even though the sleep retention module_id create failed, temperature sensor driver should still work, so just warning here + ESP_LOGW(TAG, "create retention link failed, power domain won't be turned off during sleep"); + } + } +} +#endif // TEMPERATURE_SENSOR_USE_RETENTION_LINK + esp_err_t temperature_sensor_install(const temperature_sensor_config_t *tsens_config, temperature_sensor_handle_t *ret_tsens) { #if CONFIG_TEMP_SENSOR_ENABLE_DEBUG_LOG @@ -110,6 +133,24 @@ esp_err_t temperature_sensor_install(const temperature_sensor_config_t *tsens_co tsens->clk_src = tsens_config->clk_src; } +#if !SOC_TEMPERATURE_SENSOR_SUPPORT_SLEEP_RETENTION + ESP_RETURN_ON_FALSE(tsens_config->flags.allow_pd == 0, ESP_ERR_NOT_SUPPORTED, TAG, "not able to power down in light sleep"); +#endif // SOC_TEMPERATURE_SENSOR_SUPPORT_SLEEP_RETENTION + +#if TEMPERATURE_SENSOR_USE_RETENTION_LINK + sleep_retention_module_init_param_t init_param = { + .cbs = { .create = { .handle = s_temperature_sensor_sleep_retention_init, .arg = (void *)tsens } } + }; + ret = sleep_retention_module_init(temperature_sensor_regs_retention.module_id, &init_param); + if (ret != ESP_OK) { + ESP_LOGW(TAG, "init sleep retention failed, power domain may be turned off during sleep"); + } + + if (tsens_config->flags.allow_pd != 0) { + temperature_sensor_create_retention_module(tsens); + } +#endif // TEMPERATURE_SENSOR_USE_RETENTION_LINK + temperature_sensor_power_acquire(); temperature_sensor_ll_clk_sel(tsens->clk_src); @@ -147,6 +188,17 @@ esp_err_t temperature_sensor_uninstall(temperature_sensor_handle_t tsens) ESP_RETURN_ON_ERROR(esp_intr_free(tsens->temp_sensor_isr_handle), TAG, "uninstall interrupt service failed"); } #endif // SOC_TEMPERATURE_SENSOR_INTR_SUPPORT + +#if TEMPERATURE_SENSOR_USE_RETENTION_LINK + sleep_retention_module_t module_id = temperature_sensor_regs_retention.module_id; + if (sleep_retention_get_created_modules() & BIT(module_id)) { + sleep_retention_module_free(temperature_sensor_regs_retention.module_id); + } + if (sleep_retention_get_inited_modules() & BIT(module_id)) { + sleep_retention_module_deinit(temperature_sensor_regs_retention.module_id); + } +#endif // TEMPERATURE_SENSOR_USE_RETENTION_LINK + temperature_sensor_power_release(); free(tsens); diff --git a/components/esp_driver_tsens/src/temperature_sensor_private.h b/components/esp_driver_tsens/src/temperature_sensor_private.h index b511505ffba..28b84be5f8e 100644 --- a/components/esp_driver_tsens/src/temperature_sensor_private.h +++ b/components/esp_driver_tsens/src/temperature_sensor_private.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -30,6 +30,9 @@ typedef enum { #define TEMPERATURE_SENSOR_MEM_ALLOC_CAPS (MALLOC_CAP_DEFAULT) #endif +// Use retention link only when the target supports sleep retention and PM is enabled +#define TEMPERATURE_SENSOR_USE_RETENTION_LINK (SOC_TEMPERATURE_SENSOR_SUPPORT_SLEEP_RETENTION && CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP && SOC_TEMPERATURE_SENSOR_UNDER_PD_TOP_DOMAIN) + typedef struct temperature_sensor_obj_t temperature_sensor_obj_t; struct temperature_sensor_obj_t { diff --git a/components/esp_driver_tsens/test_apps/temperature_sensor/main/CMakeLists.txt b/components/esp_driver_tsens/test_apps/temperature_sensor/main/CMakeLists.txt index 5d45e0615ad..57b6fd425c6 100644 --- a/components/esp_driver_tsens/test_apps/temperature_sensor/main/CMakeLists.txt +++ b/components/esp_driver_tsens/test_apps/temperature_sensor/main/CMakeLists.txt @@ -9,5 +9,5 @@ endif() # In order for the cases defined by `TEST_CASE` to be linked into the final elf, # the component can be registered as WHOLE_ARCHIVE idf_component_register(SRCS ${srcs} - PRIV_REQUIRES unity esp_wifi test_utils nvs_flash esp_driver_tsens esp_driver_gpio + PRIV_REQUIRES unity esp_wifi test_utils nvs_flash esp_driver_tsens esp_driver_gpio esp_pm WHOLE_ARCHIVE) diff --git a/components/esp_driver_tsens/test_apps/temperature_sensor/main/test_temperature_sensor.c b/components/esp_driver_tsens/test_apps/temperature_sensor/main/test_temperature_sensor.c index 6bc7fe4e86e..15b38613c8b 100644 --- a/components/esp_driver_tsens/test_apps/temperature_sensor/main/test_temperature_sensor.c +++ b/components/esp_driver_tsens/test_apps/temperature_sensor/main/test_temperature_sensor.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -13,6 +13,11 @@ #include "freertos/task.h" #include "soc/soc_caps.h" #include "unity_test_utils_cache.h" +#include "esp_sleep.h" +#include "esp_private/sleep_cpu.h" +#include "esp_pm.h" +#include "esp_private/esp_sleep_internal.h" +#include "esp_private/esp_pmu.h" TEST_CASE("Temperature_sensor_driver_workflow_test", "[temperature_sensor]") { @@ -146,3 +151,59 @@ TEST_CASE("Temperature sensor callback test", "[temperature_sensor]") } #endif // SOC_TEMPERATURE_SENSOR_INTR_SUPPORT + +#if SOC_LIGHT_SLEEP_SUPPORTED && CONFIG_PM_ENABLE +static void test_temperature_sensor_sleep_retention(bool allow_pd) +{ + printf("Initializing Temperature sensor\n"); + float tsens_result0; + float tsens_result1; + temperature_sensor_config_t temp_sensor = { + .range_min = 10, + .range_max = 50, + .clk_src = TEMPERATURE_SENSOR_CLK_SRC_DEFAULT, + .flags.allow_pd = allow_pd, + }; + temperature_sensor_handle_t temp_handle = NULL; + TEST_ESP_OK(temperature_sensor_install(&temp_sensor, &temp_handle)); + TEST_ESP_OK(temperature_sensor_enable(temp_handle)); + printf("Temperature sensor started\n"); + TEST_ESP_OK(temperature_sensor_get_celsius(temp_handle, &tsens_result0)); + printf("Temperature out celsius %f°C\n", tsens_result0); + + esp_sleep_context_t sleep_ctx; + esp_sleep_set_sleep_context(&sleep_ctx); + +#if ESP_SLEEP_POWER_DOWN_CPU + TEST_ESP_OK(sleep_cpu_configure(true)); +#endif + TEST_ESP_OK(esp_sleep_enable_timer_wakeup(2 * 1000 * 1000)); + TEST_ESP_OK(esp_light_sleep_start()); +#if ESP_SLEEP_POWER_DOWN_CPU + TEST_ESP_OK(sleep_cpu_configure(false)); +#endif + printf("check if the sleep happened as expected\r\n"); + TEST_ASSERT_EQUAL(0, sleep_ctx.sleep_request_result); +#if SOC_TEMPERATURE_SENSOR_UNDER_PD_TOP_DOMAIN + // check if the power domain also is powered down + TEST_ASSERT_EQUAL(allow_pd ? PMU_SLEEP_PD_TOP : 0, (sleep_ctx.sleep_flags) & PMU_SLEEP_PD_TOP); +#elif CONFIG_IDF_TARGET_ESP32P4 + TEST_ASSERT_EQUAL(PMU_SLEEP_PD_TOP, (sleep_ctx.sleep_flags) & PMU_SLEEP_PD_TOP); +#endif + + TEST_ESP_OK(temperature_sensor_get_celsius(temp_handle, &tsens_result1)); + printf("Temperature out celsius %f°C\n", tsens_result1); + TEST_ASSERT_FLOAT_WITHIN(6.0, tsens_result0, tsens_result1); + + TEST_ESP_OK(temperature_sensor_disable(temp_handle)); + TEST_ESP_OK(temperature_sensor_uninstall(temp_handle)); +} + +TEST_CASE("temperature sensor sleep retention test", "[temperature_sensor]") +{ + test_temperature_sensor_sleep_retention(false); +#if SOC_TEMPERATURE_SENSOR_SUPPORT_SLEEP_RETENTION + test_temperature_sensor_sleep_retention(true); +#endif +} +#endif diff --git a/components/esp_driver_tsens/test_apps/temperature_sensor/sdkconfig.ci.release b/components/esp_driver_tsens/test_apps/temperature_sensor/sdkconfig.ci.release index 91d93f163e6..eb643d4d06b 100644 --- a/components/esp_driver_tsens/test_apps/temperature_sensor/sdkconfig.ci.release +++ b/components/esp_driver_tsens/test_apps/temperature_sensor/sdkconfig.ci.release @@ -1,4 +1,5 @@ CONFIG_PM_ENABLE=y +CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP=y CONFIG_FREERTOS_USE_TICKLESS_IDLE=y CONFIG_COMPILER_OPTIMIZATION_SIZE=y CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE=y diff --git a/components/esp_driver_tsens/test_apps/temperature_sensor/sdkconfig.defaults b/components/esp_driver_tsens/test_apps/temperature_sensor/sdkconfig.defaults index e4bfc208a55..a89cab2af3b 100644 --- a/components/esp_driver_tsens/test_apps/temperature_sensor/sdkconfig.defaults +++ b/components/esp_driver_tsens/test_apps/temperature_sensor/sdkconfig.defaults @@ -1 +1,3 @@ CONFIG_ESP_TASK_WDT_EN=n +# primitives for checking sleep internal state +CONFIG_ESP_SLEEP_DEBUG=y diff --git a/components/esp_hw_support/include/esp_private/regi2c_ctrl.h b/components/esp_hw_support/include/esp_private/regi2c_ctrl.h index def755d8156..e77322677f8 100644 --- a/components/esp_hw_support/include/esp_private/regi2c_ctrl.h +++ b/components/esp_hw_support/include/esp_private/regi2c_ctrl.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -70,6 +70,13 @@ void regi2c_analog_cali_reg_read(void); void regi2c_analog_cali_reg_write(void); #endif //#if ADC_CALI_PD_WORKAROUND +#if SOC_TEMPERATURE_SENSOR_SUPPORT_SLEEP_RETENTION +// regi2c would be powered down in light sleep, but measure range is recorded +// in regi2c, so this function is used for record. +void regi2c_tsens_reg_read(void); +void regi2c_tsens_reg_write(void); +#endif + /* Enable/Disable regi2c_saradc with calling these two functions. With reference count protection inside. Internal use only. diff --git a/components/esp_hw_support/regi2c_ctrl.c b/components/esp_hw_support/regi2c_ctrl.c index 1d63f666864..14c8e403451 100644 --- a/components/esp_hw_support/regi2c_ctrl.c +++ b/components/esp_hw_support/regi2c_ctrl.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -12,6 +12,7 @@ #include "hal/regi2c_ctrl.h" #include "hal/regi2c_ctrl_ll.h" #include "esp_hw_log.h" +#include "soc/soc_caps.h" static portMUX_TYPE mux = portMUX_INITIALIZER_UNLOCKED; @@ -109,3 +110,21 @@ void regi2c_saradc_disable(void) regi2c_exit_critical(); } + +#if SOC_TEMPERATURE_SENSOR_SUPPORT_SLEEP_RETENTION + +#include "soc/regi2c_saradc.h" + +static DRAM_ATTR uint8_t dac_offset_regi2c; + +void IRAM_ATTR regi2c_tsens_reg_read(void) +{ + dac_offset_regi2c = REGI2C_READ_MASK(I2C_SAR_ADC, I2C_SARADC_TSENS_DAC); +} + +void IRAM_ATTR regi2c_tsens_reg_write(void) +{ + REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_TSENS_DAC, dac_offset_regi2c); +} + +#endif diff --git a/components/esp_hw_support/sleep_modes.c b/components/esp_hw_support/sleep_modes.c index ed81134542d..3a4ee01c9c0 100644 --- a/components/esp_hw_support/sleep_modes.c +++ b/components/esp_hw_support/sleep_modes.c @@ -679,6 +679,9 @@ FORCE_INLINE_ATTR void misc_modules_sleep_prepare(uint32_t pd_flags, bool deep_s #endif #if REGI2C_ANA_CALI_PD_WORKAROUND regi2c_analog_cali_reg_read(); +#endif +#if SOC_TEMPERATURE_SENSOR_SUPPORT_SLEEP_RETENTION + regi2c_tsens_reg_read(); #endif } @@ -724,6 +727,9 @@ FORCE_INLINE_ATTR void misc_modules_wake_prepare(uint32_t pd_flags) #if REGI2C_ANA_CALI_PD_WORKAROUND regi2c_analog_cali_reg_write(); #endif +#if SOC_TEMPERATURE_SENSOR_SUPPORT_SLEEP_RETENTION + regi2c_tsens_reg_write(); +#endif } static IRAM_ATTR void sleep_low_power_clock_calibration(bool is_dslp) diff --git a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in index 3ca17508c5d..d8776c93c85 100644 --- a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in @@ -1407,6 +1407,14 @@ config SOC_TEMPERATURE_SENSOR_INTR_SUPPORT bool default y +config SOC_TEMPERATURE_SENSOR_SUPPORT_SLEEP_RETENTION + bool + default y + +config SOC_TEMPERATURE_SENSOR_UNDER_PD_TOP_DOMAIN + bool + default y + config SOC_WIFI_HW_TSF bool default y diff --git a/components/soc/esp32c5/include/soc/retention_periph_defs.h b/components/soc/esp32c5/include/soc/retention_periph_defs.h index b21f1d3edea..8f3db9db68b 100644 --- a/components/soc/esp32c5/include/soc/retention_periph_defs.h +++ b/components/soc/esp32c5/include/soc/retention_periph_defs.h @@ -38,6 +38,7 @@ typedef enum periph_retention_module { SLEEP_RETENTION_MODULE_UART1 = 15, SLEEP_RETENTION_MODULE_I2S0 = 16, SLEEP_RETENTION_MODULE_ETM0 = 17, + SLEEP_RETENTION_MODULE_TEMP_SENSOR = 18, /* modem module, which includes WiFi, BLE and 802.15.4 */ SLEEP_RETENTION_MODULE_WIFI_MAC = 26, @@ -78,6 +79,7 @@ typedef enum periph_retention_module_bitmap { SLEEP_RETENTION_MODULE_BM_UART1 = BIT(SLEEP_RETENTION_MODULE_UART1), SLEEP_RETENTION_MODULE_BM_I2S0 = BIT(SLEEP_RETENTION_MODULE_I2S0), SLEEP_RETENTION_MODULE_BM_ETM0 = BIT(SLEEP_RETENTION_MODULE_ETM0), + SLEEP_RETENTION_MODULE_BM_TEMP_SENSOR = BIT(SLEEP_RETENTION_MODULE_TEMP_SENSOR), SLEEP_RETENTION_MODULE_BM_GDMA_CH0 = BIT(SLEEP_RETENTION_MODULE_GDMA_CH0), SLEEP_RETENTION_MODULE_BM_GDMA_CH1 = BIT(SLEEP_RETENTION_MODULE_GDMA_CH1), @@ -100,6 +102,7 @@ typedef enum periph_retention_module_bitmap { | SLEEP_RETENTION_MODULE_BM_UART1 \ | SLEEP_RETENTION_MODULE_BM_I2S0 \ | SLEEP_RETENTION_MODULE_BM_ETM0 \ + | SLEEP_RETENTION_MODULE_BM_TEMP_SENSOR \ ) #ifdef __cplusplus } diff --git a/components/soc/esp32c5/include/soc/soc_caps.h b/components/soc/esp32c5/include/soc/soc_caps.h index b98bce60b93..ba33e35b99d 100644 --- a/components/soc/esp32c5/include/soc/soc_caps.h +++ b/components/soc/esp32c5/include/soc/soc_caps.h @@ -591,6 +591,8 @@ #define SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC (1) #define SOC_TEMPERATURE_SENSOR_SUPPORT_XTAL (1) #define SOC_TEMPERATURE_SENSOR_INTR_SUPPORT (1) +#define SOC_TEMPERATURE_SENSOR_SUPPORT_SLEEP_RETENTION (1) +#define SOC_TEMPERATURE_SENSOR_UNDER_PD_TOP_DOMAIN (1) /*------------------------------------ WI-FI CAPS ------------------------------------*/ #define SOC_WIFI_HW_TSF (1) /*!< Support hardware TSF */ diff --git a/components/soc/esp32c5/temperature_sensor_periph.c b/components/soc/esp32c5/temperature_sensor_periph.c index b0b6cfef7eb..45410347bda 100644 --- a/components/soc/esp32c5/temperature_sensor_periph.c +++ b/components/soc/esp32c5/temperature_sensor_periph.c @@ -4,7 +4,10 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include +#include "soc/regdma.h" #include "soc/temperature_sensor_periph.h" +#include "soc/apb_saradc_reg.h" const temperature_sensor_attribute_t temperature_sensor_attributes[TEMPERATURE_SENSOR_ATTR_RANGE_NUM] = { /*Offset reg_val min max error */ @@ -14,3 +17,24 @@ const temperature_sensor_attribute_t temperature_sensor_attributes[TEMPERATURE_S { 1, 11, -30, 50, 2}, { 2, 10, -40, 20, 3}, }; + +// Temperature sensor sleep retention entries +// Temperature sensor registers require set the reg_update bit to make the configuration take effect + +/* Temperature sensor Registers Context + Include: APB_SARADC_INT_ENA_REG / + APB_SARADC_APB_TSENS_CTRL_REG / APB_SARADC_TSENS_CTRL2_REG / APB_TSENS_WAKE_REG / APB_TSENS_SAMPLE_REG +*/ +#define TEMPERATURE_SENSOR_RETENTION_REGS_CNT 5 +#define TEMPERATURE_SENSOR_RETENTION_MAP_BASE APB_SARADC_INT_ENA_REG +static const uint32_t temperature_sensor_regs_map[4] = {0x6c1, 0, 0, 0}; +static const regdma_entries_config_t temperature_sensor_regs_entries[] = { + [0] = {.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_TSENS_LINK(0x00), TEMPERATURE_SENSOR_RETENTION_MAP_BASE, TEMPERATURE_SENSOR_RETENTION_MAP_BASE, TEMPERATURE_SENSOR_RETENTION_REGS_CNT, 0, 0, temperature_sensor_regs_map[0], temperature_sensor_regs_map[1], temperature_sensor_regs_map[2], temperature_sensor_regs_map[3]), \ + .owner = ENTRY(0) | ENTRY(2) }, \ +}; + +const temperature_sensor_reg_ctx_link_t temperature_sensor_regs_retention = { + .link_list = temperature_sensor_regs_entries, + .link_num = ARRAY_SIZE(temperature_sensor_regs_entries), + .module_id = SLEEP_RETENTION_MODULE_TEMP_SENSOR, +}; diff --git a/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in index 396d8ff0e07..297b260f12b 100644 --- a/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in @@ -1459,6 +1459,14 @@ config SOC_TEMPERATURE_SENSOR_SUPPORT_ETM bool default y +config SOC_TEMPERATURE_SENSOR_SUPPORT_SLEEP_RETENTION + bool + default y + +config SOC_TEMPERATURE_SENSOR_UNDER_PD_TOP_DOMAIN + bool + default y + config SOC_RNG_CLOCK_IS_INDEPENDENT bool default y diff --git a/components/soc/esp32c6/include/soc/retention_periph_defs.h b/components/soc/esp32c6/include/soc/retention_periph_defs.h index 5bba74ce353..c7c3a452a13 100644 --- a/components/soc/esp32c6/include/soc/retention_periph_defs.h +++ b/components/soc/esp32c6/include/soc/retention_periph_defs.h @@ -38,6 +38,7 @@ typedef enum periph_retention_module { SLEEP_RETENTION_MODULE_UART1 = 15, SLEEP_RETENTION_MODULE_I2S0 = 16, SLEEP_RETENTION_MODULE_ETM0 = 17, + SLEEP_RETENTION_MODULE_TEMP_SENSOR = 18, /* Modem module, which includes WiFi, BLE and 802.15.4 */ SLEEP_RETENTION_MODULE_WIFI_MAC = 26, @@ -72,6 +73,7 @@ typedef enum periph_retention_module_bitmap { SLEEP_RETENTION_MODULE_BM_UART1 = BIT(SLEEP_RETENTION_MODULE_UART1), SLEEP_RETENTION_MODULE_BM_I2S0 = BIT(SLEEP_RETENTION_MODULE_I2S0), SLEEP_RETENTION_MODULE_BM_ETM0 = BIT(SLEEP_RETENTION_MODULE_ETM0), + SLEEP_RETENTION_MODULE_BM_TEMP_SENSOR = BIT(SLEEP_RETENTION_MODULE_TEMP_SENSOR), /* modem module, which includes WiFi, BLE and 802.15.4 */ SLEEP_RETENTION_MODULE_BM_WIFI_MAC = BIT(SLEEP_RETENTION_MODULE_WIFI_MAC), SLEEP_RETENTION_MODULE_BM_WIFI_BB = BIT(SLEEP_RETENTION_MODULE_WIFI_BB), @@ -96,6 +98,7 @@ typedef enum periph_retention_module_bitmap { | SLEEP_RETENTION_MODULE_BM_UART1 \ | SLEEP_RETENTION_MODULE_BM_I2S0 \ | SLEEP_RETENTION_MODULE_BM_ETM0 \ + | SLEEP_RETENTION_MODULE_BM_TEMP_SENSOR \ ) #ifdef __cplusplus diff --git a/components/soc/esp32c6/include/soc/soc_caps.h b/components/soc/esp32c6/include/soc/soc_caps.h index 70835692ee8..bdae84ebd29 100644 --- a/components/soc/esp32c6/include/soc/soc_caps.h +++ b/components/soc/esp32c6/include/soc/soc_caps.h @@ -574,6 +574,8 @@ #define SOC_TEMPERATURE_SENSOR_SUPPORT_XTAL (1) #define SOC_TEMPERATURE_SENSOR_INTR_SUPPORT (1) #define SOC_TEMPERATURE_SENSOR_SUPPORT_ETM (1) +#define SOC_TEMPERATURE_SENSOR_SUPPORT_SLEEP_RETENTION (1) +#define SOC_TEMPERATURE_SENSOR_UNDER_PD_TOP_DOMAIN (1) /*--------------------------------- RNG CAPS --------------------------------------------*/ #define SOC_RNG_CLOCK_IS_INDEPENDENT (1) diff --git a/components/soc/esp32c6/temperature_sensor_periph.c b/components/soc/esp32c6/temperature_sensor_periph.c index f5ad36f5a9f..b1a189fe9b4 100644 --- a/components/soc/esp32c6/temperature_sensor_periph.c +++ b/components/soc/esp32c6/temperature_sensor_periph.c @@ -1,10 +1,13 @@ /* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ +#include +#include "soc/regdma.h" #include "soc/temperature_sensor_periph.h" +#include "soc/apb_saradc_reg.h" const temperature_sensor_attribute_t temperature_sensor_attributes[TEMPERATURE_SENSOR_ATTR_RANGE_NUM] = { /*Offset reg_val min max error */ @@ -14,3 +17,24 @@ const temperature_sensor_attribute_t temperature_sensor_attributes[TEMPERATURE_S { 1, 11, -30, 50, 2}, { 2, 10, -40, 20, 3}, }; + +// Temperature sensor sleep retention entries +// Temperature sensor registers require set the reg_update bit to make the configuration take effect + +/* Temperature sensor Registers Context + Include: APB_SARADC_INT_ENA_REG / + APB_SARADC_APB_TSENS_CTRL_REG / APB_SARADC_TSENS_CTRL2_REG / APB_TSENS_WAKE_REG / APB_TSENS_SAMPLE_REG +*/ +#define TEMPERATURE_SENSOR_RETENTION_REGS_CNT 5 +#define TEMPERATURE_SENSOR_RETENTION_MAP_BASE APB_SARADC_INT_ENA_REG +static const uint32_t temperature_sensor_regs_map[4] = {0x6c1, 0, 0, 0}; +static const regdma_entries_config_t temperature_sensor_regs_entries[] = { + [0] = {.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_TSENS_LINK(0x00), TEMPERATURE_SENSOR_RETENTION_MAP_BASE, TEMPERATURE_SENSOR_RETENTION_MAP_BASE, TEMPERATURE_SENSOR_RETENTION_REGS_CNT, 0, 0, temperature_sensor_regs_map[0], temperature_sensor_regs_map[1], temperature_sensor_regs_map[2], temperature_sensor_regs_map[3]), \ + .owner = ENTRY(0) | ENTRY(2) }, \ +}; + +const temperature_sensor_reg_ctx_link_t temperature_sensor_regs_retention = { + .link_list = temperature_sensor_regs_entries, + .link_num = ARRAY_SIZE(temperature_sensor_regs_entries), + .module_id = SLEEP_RETENTION_MODULE_TEMP_SENSOR, +}; diff --git a/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in b/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in index 1330fbf2332..a2254cbb3cf 100644 --- a/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in @@ -1423,6 +1423,14 @@ config SOC_TEMPERATURE_SENSOR_SUPPORT_ETM bool default y +config SOC_TEMPERATURE_SENSOR_SUPPORT_SLEEP_RETENTION + bool + default y + +config SOC_TEMPERATURE_SENSOR_UNDER_PD_TOP_DOMAIN + bool + default y + config SOC_RNG_CLOCK_IS_INDEPENDENT bool default y diff --git a/components/soc/esp32h2/include/soc/retention_periph_defs.h b/components/soc/esp32h2/include/soc/retention_periph_defs.h index 372e43e981c..e3b7c020762 100644 --- a/components/soc/esp32h2/include/soc/retention_periph_defs.h +++ b/components/soc/esp32h2/include/soc/retention_periph_defs.h @@ -39,6 +39,7 @@ typedef enum periph_retention_module { SLEEP_RETENTION_MODULE_UART1 = 16, SLEEP_RETENTION_MODULE_I2S0 = 17, SLEEP_RETENTION_MODULE_ETM0 = 18, + SLEEP_RETENTION_MODULE_TEMP_SENSOR = 19, /* Modem module, which includes BLE and 802.15.4 */ SLEEP_RETENTION_MODULE_BLE_MAC = 28, @@ -72,6 +73,7 @@ typedef enum periph_retention_module_bitmap { SLEEP_RETENTION_MODULE_BM_UART1 = BIT(SLEEP_RETENTION_MODULE_UART1), SLEEP_RETENTION_MODULE_BM_I2S0 = BIT(SLEEP_RETENTION_MODULE_I2S0), SLEEP_RETENTION_MODULE_BM_ETM0 = BIT(SLEEP_RETENTION_MODULE_ETM0), + SLEEP_RETENTION_MODULE_BM_TEMP_SENSOR = BIT(SLEEP_RETENTION_MODULE_TEMP_SENSOR), /* modem module, which includes BLE and 802.15.4 */ SLEEP_RETENTION_MODULE_BM_BLE_MAC = BIT(SLEEP_RETENTION_MODULE_BLE_MAC), SLEEP_RETENTION_MODULE_BM_BT_BB = BIT(SLEEP_RETENTION_MODULE_BT_BB), @@ -95,6 +97,7 @@ typedef enum periph_retention_module_bitmap { | SLEEP_RETENTION_MODULE_BM_UART1 \ | SLEEP_RETENTION_MODULE_BM_I2S0 \ | SLEEP_RETENTION_MODULE_BM_ETM0 \ + | SLEEP_RETENTION_MODULE_BM_TEMP_SENSOR \ ) #ifdef __cplusplus diff --git a/components/soc/esp32h2/include/soc/soc_caps.h b/components/soc/esp32h2/include/soc/soc_caps.h index 26110b48eba..1fc679eea08 100644 --- a/components/soc/esp32h2/include/soc/soc_caps.h +++ b/components/soc/esp32h2/include/soc/soc_caps.h @@ -559,6 +559,8 @@ #define SOC_TEMPERATURE_SENSOR_SUPPORT_XTAL (1) #define SOC_TEMPERATURE_SENSOR_INTR_SUPPORT (1) #define SOC_TEMPERATURE_SENSOR_SUPPORT_ETM (1) +#define SOC_TEMPERATURE_SENSOR_SUPPORT_SLEEP_RETENTION (1) +#define SOC_TEMPERATURE_SENSOR_UNDER_PD_TOP_DOMAIN (1) /*--------------------------------- RNG CAPS --------------------------------------------*/ #define SOC_RNG_CLOCK_IS_INDEPENDENT (1) diff --git a/components/soc/esp32h2/temperature_sensor_periph.c b/components/soc/esp32h2/temperature_sensor_periph.c index e75c60b3178..348567d3f2f 100644 --- a/components/soc/esp32h2/temperature_sensor_periph.c +++ b/components/soc/esp32h2/temperature_sensor_periph.c @@ -1,10 +1,14 @@ /* - * SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2019-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ +#include +#include "soc/regdma.h" #include "soc/temperature_sensor_periph.h" +#include "soc/apb_saradc_reg.h" + const temperature_sensor_attribute_t temperature_sensor_attributes[TEMPERATURE_SENSOR_ATTR_RANGE_NUM] = { /*Offset reg_val min max error */ @@ -14,3 +18,24 @@ const temperature_sensor_attribute_t temperature_sensor_attributes[TEMPERATURE_S { 1, 11, -30, 50, 2}, { 2, 10, -40, 20, 3}, }; + +// Temperature sensor sleep retention entries +// Temperature sensor registers require set the reg_update bit to make the configuration take effect + +/* Temperature sensor Registers Context + Include: APB_SARADC_INT_ENA_REG / + APB_SARADC_APB_TSENS_CTRL_REG / APB_SARADC_TSENS_CTRL2_REG / APB_TSENS_WAKE_REG / APB_TSENS_SAMPLE_REG +*/ +#define TEMPERATURE_SENSOR_RETENTION_REGS_CNT 5 +#define TEMPERATURE_SENSOR_RETENTION_MAP_BASE APB_SARADC_INT_ENA_REG +static const uint32_t temperature_sensor_regs_map[4] = {0x6c1, 0, 0, 0}; +static const regdma_entries_config_t temperature_sensor_regs_entries[] = { + [0] = {.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_TSENS_LINK(0x00), TEMPERATURE_SENSOR_RETENTION_MAP_BASE, TEMPERATURE_SENSOR_RETENTION_MAP_BASE, TEMPERATURE_SENSOR_RETENTION_REGS_CNT, 0, 0, temperature_sensor_regs_map[0], temperature_sensor_regs_map[1], temperature_sensor_regs_map[2], temperature_sensor_regs_map[3]), \ + .owner = ENTRY(0) | ENTRY(2) }, \ +}; + +const temperature_sensor_reg_ctx_link_t temperature_sensor_regs_retention = { + .link_list = temperature_sensor_regs_entries, + .link_num = ARRAY_SIZE(temperature_sensor_regs_entries), + .module_id = SLEEP_RETENTION_MODULE_TEMP_SENSOR, +}; diff --git a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in index f8319e722ee..fcc964add8b 100644 --- a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in @@ -1907,6 +1907,10 @@ config SOC_TEMPERATURE_SENSOR_SUPPORT_ETM bool default y +config SOC_TEMPERATURE_SENSOR_SUPPORT_SLEEP_RETENTION + bool + default y + config SOC_MEM_TCM_SUPPORTED bool default y diff --git a/components/soc/esp32p4/include/soc/soc_caps.h b/components/soc/esp32p4/include/soc/soc_caps.h index a8a90bda867..70755ca405f 100644 --- a/components/soc/esp32p4/include/soc/soc_caps.h +++ b/components/soc/esp32p4/include/soc/soc_caps.h @@ -722,6 +722,8 @@ #define SOC_TEMPERATURE_SENSOR_INTR_SUPPORT (1) #define SOC_TSENS_IS_INDEPENDENT_FROM_ADC (1) /*!< Temperature sensor is a separate module, not share regs with ADC */ #define SOC_TEMPERATURE_SENSOR_SUPPORT_ETM (1) +// temperature sensor on esp32p4 in under low power domain. +#define SOC_TEMPERATURE_SENSOR_SUPPORT_SLEEP_RETENTION (1) /*-------------------------- Memory CAPS --------------------------*/ #define SOC_MEM_TCM_SUPPORTED (1) diff --git a/components/soc/include/soc/regdma.h b/components/soc/include/soc/regdma.h index 15186cbb95a..6dbc3cbc78b 100644 --- a/components/soc/include/soc/regdma.h +++ b/components/soc/include/soc/regdma.h @@ -55,6 +55,7 @@ extern "C" { #define REGDMA_TG1_TIMER_LINK(_pri) ((0x1D << 8) | _pri) #define REGDMA_I2S_LINK(_pri) ((0x1E << 8) | _pri) #define REGDMA_ETM_LINK(_pri) ((0x1F << 8) | _pri) +#define REGDMA_TSENS_LINK(_pri) ((0x20 << 8) | _pri) #define REGDMA_MODEM_FE_LINK(_pri) ((0xFF << 8) | _pri) #define REGDMA_LINK_PRI_SYS_CLK REGDMA_LINK_PRI_0 @@ -74,6 +75,7 @@ extern "C" { #define REGDMA_LINK_PRI_I2C REGDMA_LINK_PRI_GENERAL_PERIPH #define REGDMA_LINK_PRI_I2S REGDMA_LINK_PRI_GENERAL_PERIPH #define REGDMA_LINK_PRI_UART REGDMA_LINK_PRI_GENERAL_PERIPH +#define REGDMA_LINK_PRI_TEMPERATURE_SENSOR REGDMA_LINK_PRI_GENERAL_PERIPH typedef enum { REGDMA_LINK_PRI_0 = 0, diff --git a/components/soc/include/soc/temperature_sensor_periph.h b/components/soc/include/soc/temperature_sensor_periph.h index 73742819350..d5273925541 100644 --- a/components/soc/include/soc/temperature_sensor_periph.h +++ b/components/soc/include/soc/temperature_sensor_periph.h @@ -1,11 +1,16 @@ /* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ #pragma once +#include "soc/regdma.h" +#if SOC_TEMPERATURE_SENSOR_SUPPORT_SLEEP_RETENTION +#include "soc/retention_periph_defs.h" +#endif + #ifdef __cplusplus extern "C" { #endif @@ -22,6 +27,16 @@ typedef struct { extern const temperature_sensor_attribute_t temperature_sensor_attributes[TEMPERATURE_SENSOR_ATTR_RANGE_NUM]; +#if SOC_TEMPERATURE_SENSOR_SUPPORT_SLEEP_RETENTION +typedef struct { + const regdma_entries_config_t *link_list; + uint32_t link_num; + periph_retention_module_t module_id; +} temperature_sensor_reg_ctx_link_t; + +extern const temperature_sensor_reg_ctx_link_t temperature_sensor_regs_retention; +#endif // SOC_TEMPERATURE_SENSOR_SUPPORT_SLEEP_RETENTION + #ifdef __cplusplus } #endif diff --git a/docs/en/api-reference/peripherals/temp_sensor.rst b/docs/en/api-reference/peripherals/temp_sensor.rst index 22b7e1a6ce3..ca7231e6e1e 100644 --- a/docs/en/api-reference/peripherals/temp_sensor.rst +++ b/docs/en/api-reference/peripherals/temp_sensor.rst @@ -59,6 +59,7 @@ In order to install a built-in temperature sensor instance, the first thing is t - :cpp:member:`range_min`: The minimum value of the testing range you have evaluated. - :cpp:member:`range_max`: The maximum value of the testing range you have evaluated. +- :cpp:member:`allow_pd` configures if the driver allows the system to power down the peripheral in light sleep mode. Before entering sleep, the system will backup the temperature sensor register context, which will be restored later when the system exit the sleep mode. Powering down the peripheral can save more power, but at the cost of more memory consumed to save the register context. It's a tradeoff between power consumption and memory consumption. This configuration option relies on specific hardware feature, if you enable it on an unsupported chip, you will see error message like ``not able to power down in light sleep``. After the ranges are set, the structure could be passed to :cpp:func:`temperature_sensor_install`, which will instantiate the temperature sensor instance and return a handle. diff --git a/docs/en/api-reference/system/power_management.rst b/docs/en/api-reference/system/power_management.rst index f583b86718c..7f72750dcf5 100644 --- a/docs/en/api-reference/system/power_management.rst +++ b/docs/en/api-reference/system/power_management.rst @@ -156,6 +156,7 @@ The following peripheral drivers are not aware of DFS yet. Applications need to :SOC_I2C_SUPPORT_SLEEP_RETENTION: - I2C :SOC_I2S_SUPPORT_SLEEP_RETENTION: - I2S :SOC_UART_SUPPORT_SLEEP_RETENTION: - All UARTs + :SOC_TEMPERATURE_SENSOR_SUPPORT_SLEEP_RETENTION: - Temperature Sensor The following peripherals are not yet supported: diff --git a/docs/zh_CN/api-reference/peripherals/temp_sensor.rst b/docs/zh_CN/api-reference/peripherals/temp_sensor.rst index bffe7b66943..a53aace2fbd 100644 --- a/docs/zh_CN/api-reference/peripherals/temp_sensor.rst +++ b/docs/zh_CN/api-reference/peripherals/temp_sensor.rst @@ -59,6 +59,7 @@ - :cpp:member:`range_min`：所测量温度范围的最小值。 - :cpp:member:`range_max`：所测量温度范围的最大值。 +- :cpp:member:`allow_pd` 配置驱动程序是否允许系统在睡眠模式下关闭外设电源。在进入睡眠之前，系统将备份温度传感器寄存器上下文，当系统退出睡眠模式时，这些上下文将被恢复。关闭外设可以节省更多功耗，但代价是消耗更多内存来保存寄存器上下文。你需要在功耗和内存消耗之间做权衡。此配置选项依赖于特定的硬件功能，如果在不支持的芯片上启用它，你将看到类似 ``not able to power down in light sleep`` 的错误消息。 设置好温度范围后，将配置结构体传递给 :cpp:func:`temperature_sensor_install`，该函数将创建温度传感器模块并返回句柄。 diff --git a/docs/zh_CN/api-reference/system/power_management.rst b/docs/zh_CN/api-reference/system/power_management.rst index 3ea51dc30bb..0d64025cd98 100644 --- a/docs/zh_CN/api-reference/system/power_management.rst +++ b/docs/zh_CN/api-reference/system/power_management.rst @@ -156,6 +156,7 @@ ESP-IDF 中集成的电源管理算法可以根据应用程序组件的需求， :SOC_I2S_SUPPORT_SLEEP_RETENTION: - I2S :SOC_ETM_SUPPORT_SLEEP_RETENTION: - ETM :SOC_UART_SUPPORT_SLEEP_RETENTION: - All UARTs + :SOC_TEMPERATURE_SENSOR_SUPPORT_SLEEP_RETENTION: - Temperature Sensor 以下外设尚未支持： From 3957e59f1a9ad67f637c65d68e062e9940e49df3 Mon Sep 17 00:00:00 2001 From: "harshal.patil" Date: Thu, 10 Oct 2024 12:34:32 +0530 Subject: [PATCH 176/472] feat(mbedtls/esp_crt_bundle): Move dummy cert to .rodata to save 408B from dram Co-authored-by: Hanno --- components/mbedtls/CMakeLists.txt | 8 +++++++- .../mbedtls/esp_crt_bundle/esp_crt_bundle.c | 7 ++++++- .../esp_crt_bundle/include/esp_crt_bundle.h | 15 ++++++++++++--- .../port/dynamic/esp_mbedtls_dynamic_impl.c | 18 +++++++++++++++++- .../port/dynamic/esp_mbedtls_dynamic_impl.h | 1 + 5 files changed, 43 insertions(+), 6 deletions(-) diff --git a/components/mbedtls/CMakeLists.txt b/components/mbedtls/CMakeLists.txt index 94033218cef..d3f4fe40a7d 100644 --- a/components/mbedtls/CMakeLists.txt +++ b/components/mbedtls/CMakeLists.txt @@ -96,7 +96,13 @@ idf_build_get_property(python PYTHON) set(Python3_EXECUTABLE ${python}) # Needed to for include_next includes to work from within mbedtls -include_directories("${COMPONENT_DIR}/port/include") +set(include_dirs "${COMPONENT_DIR}/port/include") + +if(CONFIG_MBEDTLS_CERTIFICATE_BUNDLE) + list(APPEND include_dirs "${COMPONENT_DIR}/esp_crt_bundle/include") +endif() + +include_directories(${include_dirs}) # Needed to for mbedtls_rom includes to work from within mbedtls if(CONFIG_MBEDTLS_USE_CRYPTO_ROM_IMPL) diff --git a/components/mbedtls/esp_crt_bundle/esp_crt_bundle.c b/components/mbedtls/esp_crt_bundle/esp_crt_bundle.c index dc75d0cff42..65f817f7bdd 100644 --- a/components/mbedtls/esp_crt_bundle/esp_crt_bundle.c +++ b/components/mbedtls/esp_crt_bundle/esp_crt_bundle.c @@ -54,7 +54,7 @@ static const char *TAG = "esp-x509-crt-bundle"; /* a dummy certificate so that * cacert_ptr passes non-NULL check during handshake */ -static mbedtls_x509_crt s_dummy_crt; +static const mbedtls_x509_crt s_dummy_crt; extern const uint8_t x509_crt_imported_bundle_bin_start[] asm("_binary_x509_crt_bundle_start"); extern const uint8_t x509_crt_imported_bundle_bin_end[] asm("_binary_x509_crt_bundle_end"); @@ -368,3 +368,8 @@ esp_err_t esp_crt_bundle_set(const uint8_t *x509_bundle, size_t bundle_size) { return esp_crt_bundle_init(x509_bundle, bundle_size); } + +bool esp_crt_bundle_in_use(const mbedtls_x509_crt* ca_chain) +{ + return ((ca_chain == &s_dummy_crt) ? true : false); +} diff --git a/components/mbedtls/esp_crt_bundle/include/esp_crt_bundle.h b/components/mbedtls/esp_crt_bundle/include/esp_crt_bundle.h index 49069185b3a..61c09f0bd03 100644 --- a/components/mbedtls/esp_crt_bundle/include/esp_crt_bundle.h +++ b/components/mbedtls/esp_crt_bundle/include/esp_crt_bundle.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -27,7 +27,7 @@ extern "C" { * * @return * - ESP_OK if adding certificates was successful. - * - Other if an error occured or an action must be taken by the calling process. + * - Other if an error occurred or an action must be taken by the calling process. */ esp_err_t esp_crt_bundle_attach(void *conf); @@ -55,10 +55,19 @@ void esp_crt_bundle_detach(mbedtls_ssl_config *conf); * * @return * - ESP_OK if adding certificates was successful. - * - Other if an error occured or an action must be taken by the calling process. + * - Other if an error occurred or an action must be taken by the calling process. */ esp_err_t esp_crt_bundle_set(const uint8_t *x509_bundle, size_t bundle_size); +/** + * @brief Check if the given CA certificate chain is the default "dummy" + * certificate chain attached by the esp_crt_bundle + * + * @param ca_chain A pointer to the CA chain. + * @return true if the ca_chain is the dummy CA chain attached by esp_crt_bundle + * @return false otherwise + */ +bool esp_crt_bundle_in_use(const mbedtls_x509_crt* ca_chain); #ifdef __cplusplus } diff --git a/components/mbedtls/port/dynamic/esp_mbedtls_dynamic_impl.c b/components/mbedtls/port/dynamic/esp_mbedtls_dynamic_impl.c index a5ea9fb337a..d76f6b5049c 100644 --- a/components/mbedtls/port/dynamic/esp_mbedtls_dynamic_impl.c +++ b/components/mbedtls/port/dynamic/esp_mbedtls_dynamic_impl.c @@ -1,11 +1,16 @@ /* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ #include #include "esp_mbedtls_dynamic_impl.h" +#include "sdkconfig.h" + +#if CONFIG_MBEDTLS_CERTIFICATE_BUNDLE +#include "esp_crt_bundle.h" +#endif #define COUNTER_SIZE (8) #define CACHE_IV_SIZE (16) @@ -532,7 +537,18 @@ void esp_mbedtls_free_cacert(mbedtls_ssl_context *ssl) if (ssl->MBEDTLS_PRIVATE(conf)->MBEDTLS_PRIVATE(ca_chain)) { mbedtls_ssl_config *conf = (mbedtls_ssl_config * )mbedtls_ssl_context_get_config(ssl); +#if CONFIG_MBEDTLS_CERTIFICATE_BUNDLE + /* In case of mbedtls certificate bundle, we attach a "static const" + * dummy cert, thus we need to avoid the write operations (memset()) + * performed by `mbedtls_x509_crt_free()` + */ + if (!esp_crt_bundle_in_use(conf->MBEDTLS_PRIVATE(ca_chain))) { + mbedtls_x509_crt_free(conf->MBEDTLS_PRIVATE(ca_chain)); + } +#else mbedtls_x509_crt_free(conf->MBEDTLS_PRIVATE(ca_chain)); +#endif + conf->MBEDTLS_PRIVATE(ca_chain) = NULL; } } diff --git a/components/mbedtls/port/dynamic/esp_mbedtls_dynamic_impl.h b/components/mbedtls/port/dynamic/esp_mbedtls_dynamic_impl.h index 72641b3a549..ad7a716be58 100644 --- a/components/mbedtls/port/dynamic/esp_mbedtls_dynamic_impl.h +++ b/components/mbedtls/port/dynamic/esp_mbedtls_dynamic_impl.h @@ -24,6 +24,7 @@ #include "mbedtls/ssl.h" #include "mbedtls/platform.h" #include "esp_log.h" +#include "sdkconfig.h" #define TRACE_CHECK(_fn, _state) \ ({ \ From 1fe57a5d8e1e2ad37acc26ac6f2b8590188e949a Mon Sep 17 00:00:00 2001 From: Sudeep Mohanty Date: Wed, 16 Oct 2024 09:59:45 +0200 Subject: [PATCH 177/472] fix(freertos): Fixed SMP race condition in xStreamBufferSend() This commit fixes a race condition in dual-core SMP mode where in the xStreamBufferSend() makes the xTaskWaitingToSend NULL but it may have already been evaluated to not be NULL by xStreamBufferReceive() running on another core and eventually leading to a crash in tasks.c. --- components/freertos/FreeRTOS-Kernel/idf_changes.md | 2 ++ components/freertos/FreeRTOS-Kernel/stream_buffer.c | 13 ++++++++++++- 2 files changed, 14 insertions(+), 1 deletion(-) diff --git a/components/freertos/FreeRTOS-Kernel/idf_changes.md b/components/freertos/FreeRTOS-Kernel/idf_changes.md index 83bee684332..7bf620e6e41 100644 --- a/components/freertos/FreeRTOS-Kernel/idf_changes.md +++ b/components/freertos/FreeRTOS-Kernel/idf_changes.md @@ -125,6 +125,8 @@ The following functions were modified to accommodate SMP behavior: - Added extra check to see if current blocking task has already been deleted by the other core. - `xStreamBufferReceive()` - Added a critical section for setting `xTaskWaitingToReceive` to `NULL` so that the write is SMP safe. +- `xStreamBufferSend()` + - Added a critical section for setting `xTaskWaitingToSend` to `NULL` so that the write is SMP safe. ### Critical Section Changes diff --git a/components/freertos/FreeRTOS-Kernel/stream_buffer.c b/components/freertos/FreeRTOS-Kernel/stream_buffer.c index 988eb3f5f7f..04d67a20056 100644 --- a/components/freertos/FreeRTOS-Kernel/stream_buffer.c +++ b/components/freertos/FreeRTOS-Kernel/stream_buffer.c @@ -774,7 +774,18 @@ size_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, traceBLOCKING_ON_STREAM_BUFFER_SEND( xStreamBuffer ); ( void ) xTaskNotifyWait( ( uint32_t ) 0, ( uint32_t ) 0, NULL, xTicksToWait ); - pxStreamBuffer->xTaskWaitingToSend = NULL; + /* In SMP mode, the task may have been woken and scheduled on + * another core. Hence, we must clear the xTaskWaitingToSend + * handle in a critical section. */ + #if ( configNUMBER_OF_CORES > 1 ) + taskENTER_CRITICAL( &( pxStreamBuffer->xStreamBufferLock ) ); + #endif /* configNUMBER_OF_CORES > 1 */ + { + pxStreamBuffer->xTaskWaitingToSend = NULL; + } + #if ( configNUMBER_OF_CORES > 1 ) + taskEXIT_CRITICAL( &( pxStreamBuffer->xStreamBufferLock ) ); + #endif /* configNUMBER_OF_CORES > 1 */ } while( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ); } else From 15c895fc6a41a9df43b1798c92960994c407eb58 Mon Sep 17 00:00:00 2001 From: zhanghaipeng Date: Wed, 16 Oct 2024 20:11:30 +0800 Subject: [PATCH 178/472] feat(ble/bluedroid): Support enable BLE hci log by API --- components/bt/common/hci_log/bt_hci_log.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/components/bt/common/hci_log/bt_hci_log.c b/components/bt/common/hci_log/bt_hci_log.c index e35bf1a7a68..ac85179a707 100644 --- a/components/bt/common/hci_log/bt_hci_log.c +++ b/components/bt/common/hci_log/bt_hci_log.c @@ -305,19 +305,27 @@ void bt_hci_log_data_show(bt_hci_log_t *p_hci_log_ctl) osi_mutex_unlock(&mutex_lock); } +static bool enable_hci_log_flag = true; +void bt_hci_log_record_hci_enable(bool enable) +{ + enable_hci_log_flag = enable; +} esp_err_t IRAM_ATTR bt_hci_log_record_hci_data(uint8_t data_type, uint8_t *data, uint8_t data_len) { + if (!enable_hci_log_flag) return ESP_OK; return bt_hci_log_record_data(&g_bt_hci_log_data_ctl, NULL, data_type, data, data_len); } esp_err_t IRAM_ATTR bt_hci_log_record_custom_data(char *string, uint8_t *data, uint8_t data_len) { + if (!enable_hci_log_flag) return ESP_OK; return bt_hci_log_record_data(&g_bt_hci_log_data_ctl, string, HCI_LOG_DATA_TYPE_SELF_DEFINE, data, data_len); } esp_err_t IRAM_ATTR bt_hci_log_record_hci_adv(uint8_t data_type, uint8_t *data, uint8_t data_len) { + if (!enable_hci_log_flag) return ESP_OK; return bt_hci_log_record_data(&g_bt_hci_log_adv_ctl, NULL, data_type, data, data_len); } From daf788242172ff0e00123ce866ec230f521b266f Mon Sep 17 00:00:00 2001 From: xuxiao Date: Wed, 16 Oct 2024 12:08:55 +0800 Subject: [PATCH 179/472] fix(wifi): fix can not tx in low rssi during iperf test --- components/esp_wifi/lib | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/components/esp_wifi/lib b/components/esp_wifi/lib index 0da5a8a5dfd..5dca4edbc4c 160000 --- a/components/esp_wifi/lib +++ b/components/esp_wifi/lib @@ -1 +1 @@ -Subproject commit 0da5a8a5dfd8914496c5975af7d8903a44f8bced +Subproject commit 5dca4edbc4c5e20406878926fb24e9bbfcb67e88 From 3f838d7843835215334faddd0c22add48a4657fa Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Adam=20M=C3=BAdry?= Date: Tue, 15 Oct 2024 22:28:26 +0200 Subject: [PATCH 180/472] fix(sdmmc): Improve SD card state checking after write/read command --- components/sdmmc/include/sd_protocol_defs.h | 3 ++- components/sdmmc/sdmmc_cmd.c | 9 +++++++-- components/sdmmc/sdmmc_mmc.c | 4 ++-- 3 files changed, 11 insertions(+), 5 deletions(-) diff --git a/components/sdmmc/include/sd_protocol_defs.h b/components/sdmmc/include/sd_protocol_defs.h index a1b6a8ec022..f3252be38fc 100644 --- a/components/sdmmc/include/sd_protocol_defs.h +++ b/components/sdmmc/include/sd_protocol_defs.h @@ -108,6 +108,7 @@ extern "C" { #define MMC_R1_CURRENT_STATE_POS (9) #define MMC_R1_CURRENT_STATE_MASK (0x1E00)/* card current state */ #define MMC_R1_CURRENT_STATE_TRAN (4) +#define MMC_R1_CURRENT_STATE_STATUS(status) ((status & MMC_R1_CURRENT_STATE_MASK) >> MMC_R1_CURRENT_STATE_POS) /* SPI mode R1 response type bits */ #define SD_SPI_R1_IDLE_STATE (1<<0) @@ -424,7 +425,7 @@ extern "C" { * * 67 45 23 01 ef cd ab 89 * - * MMC_RSP_BITS will extact bits as follows: + * MMC_RSP_BITS will extract bits as follows: * * start=0 len=4 -> result=0x00000007 * start=0 len=12 -> result=0x00000567 diff --git a/components/sdmmc/sdmmc_cmd.c b/components/sdmmc/sdmmc_cmd.c index fb18a9d6962..24acb6cb4a0 100644 --- a/components/sdmmc/sdmmc_cmd.c +++ b/components/sdmmc/sdmmc_cmd.c @@ -444,6 +444,11 @@ esp_err_t sdmmc_write_sectors(sdmmc_card_t* card, const void* src, return err; } +static bool mmc_ready_for_data(uint32_t status) +{ + return (status & MMC_R1_READY_FOR_DATA) && (MMC_R1_CURRENT_STATE_STATUS(status) == MMC_R1_CURRENT_STATE_TRAN); +} + esp_err_t sdmmc_write_sectors_dma(sdmmc_card_t* card, const void* src, size_t start_block, size_t block_count, size_t buffer_len) { @@ -480,7 +485,7 @@ esp_err_t sdmmc_write_sectors_dma(sdmmc_card_t* card, const void* src, int64_t t0 = esp_timer_get_time(); int64_t t1 = 0; /* SD mode: wait for the card to become idle based on R1 status */ - while (!host_is_spi(card) && !(status & MMC_R1_READY_FOR_DATA)) { + while (!host_is_spi(card) && !mmc_ready_for_data(status)) { t1 = esp_timer_get_time(); if (t1 - t0 > SDMMC_READY_FOR_DATA_TIMEOUT_US) { ESP_LOGE(TAG, "write sectors dma - timeout"); @@ -602,7 +607,7 @@ esp_err_t sdmmc_read_sectors_dma(sdmmc_card_t* card, void* dst, int64_t t0 = esp_timer_get_time(); int64_t t1 = 0; /* SD mode: wait for the card to become idle based on R1 status */ - while (!host_is_spi(card) && !(status & MMC_R1_READY_FOR_DATA)) { + while (!host_is_spi(card) && !mmc_ready_for_data(status)) { t1 = esp_timer_get_time(); if (t1 - t0 > SDMMC_READY_FOR_DATA_TIMEOUT_US) { ESP_LOGE(TAG, "read sectors dma - timeout"); diff --git a/components/sdmmc/sdmmc_mmc.c b/components/sdmmc/sdmmc_mmc.c index e3f44bc865b..23f18272f41 100644 --- a/components/sdmmc/sdmmc_mmc.c +++ b/components/sdmmc/sdmmc_mmc.c @@ -272,8 +272,8 @@ esp_err_t sdmmc_init_mmc_check_ext_csd(sdmmc_card_t* card) ESP_LOGE(TAG, "%s: send_status returned 0x%x", __func__, err); goto out; } - status = ((status & MMC_R1_CURRENT_STATE_MASK) >> MMC_R1_CURRENT_STATE_POS); - if (status != MMC_R1_CURRENT_STATE_TRAN) { + + if (MMC_R1_CURRENT_STATE_STATUS(status) != MMC_R1_CURRENT_STATE_TRAN) { ESP_LOGE(TAG, "%s: card not in transfer state", __func__); err = ESP_ERR_INVALID_STATE; goto out; From 9c7609a0e789e6607d00656620ab5e7c6e7bd608 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Adam=20M=C3=BAdry?= Date: Tue, 15 Oct 2024 23:22:27 +0200 Subject: [PATCH 181/472] fix(sdmmc): Send status (CMD13) even if write/read command fails --- components/sdmmc/include/sd_protocol_defs.h | 2 +- components/sdmmc/sdmmc_cmd.c | 30 ++++++++++++++++----- 2 files changed, 24 insertions(+), 8 deletions(-) diff --git a/components/sdmmc/include/sd_protocol_defs.h b/components/sdmmc/include/sd_protocol_defs.h index f3252be38fc..8eb52ca6b0a 100644 --- a/components/sdmmc/include/sd_protocol_defs.h +++ b/components/sdmmc/include/sd_protocol_defs.h @@ -108,7 +108,7 @@ extern "C" { #define MMC_R1_CURRENT_STATE_POS (9) #define MMC_R1_CURRENT_STATE_MASK (0x1E00)/* card current state */ #define MMC_R1_CURRENT_STATE_TRAN (4) -#define MMC_R1_CURRENT_STATE_STATUS(status) ((status & MMC_R1_CURRENT_STATE_MASK) >> MMC_R1_CURRENT_STATE_POS) +#define MMC_R1_CURRENT_STATE_STATUS(status) (((status) & MMC_R1_CURRENT_STATE_MASK) >> MMC_R1_CURRENT_STATE_POS) /* SPI mode R1 response type bits */ #define SD_SPI_R1_IDLE_STATE (1<<0) diff --git a/components/sdmmc/sdmmc_cmd.c b/components/sdmmc/sdmmc_cmd.c index 24acb6cb4a0..9d54ba3e1c2 100644 --- a/components/sdmmc/sdmmc_cmd.c +++ b/components/sdmmc/sdmmc_cmd.c @@ -444,7 +444,7 @@ esp_err_t sdmmc_write_sectors(sdmmc_card_t* card, const void* src, return err; } -static bool mmc_ready_for_data(uint32_t status) +static bool sdmmc_ready_for_data(uint32_t status) { return (status & MMC_R1_READY_FOR_DATA) && (MMC_R1_CURRENT_STATE_STATUS(status) == MMC_R1_CURRENT_STATE_TRAN); } @@ -474,18 +474,26 @@ esp_err_t sdmmc_write_sectors_dma(sdmmc_card_t* card, const void* src, } else { cmd.arg = start_block * block_size; } + + uint32_t status = 0; esp_err_t err = sdmmc_send_cmd(card, &cmd); + esp_err_t err_cmd13 = sdmmc_send_cmd_send_status(card, &status); + if (err != ESP_OK) { - ESP_LOGE(TAG, "%s: sdmmc_send_cmd returned 0x%x", __func__, err); + if (err_cmd13 == ESP_OK) { + ESP_LOGE(TAG, "%s: sdmmc_send_cmd returned 0x%x, status 0x%" PRIx32, __func__, err, status); + } else { + ESP_LOGE(TAG, "%s: sdmmc_send_cmd returned 0x%x, failed to get status (0x%x)", __func__, err, err_cmd13); + } return err; } - uint32_t status = 0; + size_t count = 0; int64_t yield_delay_us = 100 * 1000; // initially 100ms int64_t t0 = esp_timer_get_time(); int64_t t1 = 0; /* SD mode: wait for the card to become idle based on R1 status */ - while (!host_is_spi(card) && !mmc_ready_for_data(status)) { + while (!host_is_spi(card) && !sdmmc_ready_for_data(status)) { t1 = esp_timer_get_time(); if (t1 - t0 > SDMMC_READY_FOR_DATA_TIMEOUT_US) { ESP_LOGE(TAG, "write sectors dma - timeout"); @@ -596,18 +604,26 @@ esp_err_t sdmmc_read_sectors_dma(sdmmc_card_t* card, void* dst, } else { cmd.arg = start_block * block_size; } + + uint32_t status = 0; esp_err_t err = sdmmc_send_cmd(card, &cmd); + esp_err_t err_cmd13 = sdmmc_send_cmd_send_status(card, &status); + if (err != ESP_OK) { - ESP_LOGE(TAG, "%s: sdmmc_send_cmd returned 0x%x", __func__, err); + if (err_cmd13 == ESP_OK) { + ESP_LOGE(TAG, "%s: sdmmc_send_cmd returned 0x%x, status 0x%" PRIx32, __func__, err, status); + } else { + ESP_LOGE(TAG, "%s: sdmmc_send_cmd returned 0x%x, failed to get status (0x%x)", __func__, err, err_cmd13); + } return err; } - uint32_t status = 0; + size_t count = 0; int64_t yield_delay_us = 100 * 1000; // initially 100ms int64_t t0 = esp_timer_get_time(); int64_t t1 = 0; /* SD mode: wait for the card to become idle based on R1 status */ - while (!host_is_spi(card) && !mmc_ready_for_data(status)) { + while (!host_is_spi(card) && !sdmmc_ready_for_data(status)) { t1 = esp_timer_get_time(); if (t1 - t0 > SDMMC_READY_FOR_DATA_TIMEOUT_US) { ESP_LOGE(TAG, "read sectors dma - timeout"); From 7bfee98996ec165864886d8b17061bd58dd9513a Mon Sep 17 00:00:00 2001 From: Cacti4dev <107650601+Cacti4dev@users.noreply.github.com> Date: Wed, 16 Oct 2024 13:54:43 -0700 Subject: [PATCH 182/472] Update hid_host_example.c Distinguish was spelled incorrectly --- examples/peripherals/usb/host/hid/main/hid_host_example.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/examples/peripherals/usb/host/hid/main/hid_host_example.c b/examples/peripherals/usb/host/hid/main/hid_host_example.c index ca8783f0b25..fde9f95dbd4 100644 --- a/examples/peripherals/usb/host/hid/main/hid_host_example.c +++ b/examples/peripherals/usb/host/hid/main/hid_host_example.c @@ -32,7 +32,7 @@ QueueHandle_t app_event_queue = NULL; /** * @brief APP event group * - * Application logic can be different. There is a one among other ways to distingiush the + * Application logic can be different. There is a one among other ways to distinguish the * event by application event group. * In this example we have two event groups: * APP_EVENT - General event, which is APP_QUIT_PIN press event (Generally, it is IO0). From 67a87a5fcd0f59cd46e7e394f310e020cfe12d15 Mon Sep 17 00:00:00 2001 From: Song Ruo Jing Date: Wed, 16 Oct 2024 19:27:59 +0800 Subject: [PATCH 183/472] fix(pmu): enable all func clock icg during retention This should only increase a tiny amount of the power consumption in the retention process, but save debug time since some module register read/write relies not only APB but also func clock. --- .../esp_hw_support/port/esp32c5/pmu_param.c | 37 ++---------------- .../port/esp32c5/private_include/pmu_param.h | 2 +- .../esp_hw_support/port/esp32c6/pmu_param.c | 38 ++----------------- .../port/esp32c6/private_include/pmu_param.h | 2 +- .../esp_hw_support/port/esp32c61/pmu_param.c | 37 ++---------------- .../port/esp32c61/private_include/pmu_param.h | 2 +- .../esp_hw_support/port/esp32h2/pmu_param.c | 37 ++---------------- .../port/esp32h2/private_include/pmu_param.h | 6 +-- .../esp_hw_support/port/esp32p4/pmu_param.c | 26 +------------ .../port/esp32p4/private_include/pmu_param.h | 2 +- 10 files changed, 21 insertions(+), 168 deletions(-) diff --git a/components/esp_hw_support/port/esp32c5/pmu_param.c b/components/esp_hw_support/port/esp32c5/pmu_param.c index e676f8c478d..6f44a1b4e17 100644 --- a/components/esp_hw_support/port/esp32c5/pmu_param.c +++ b/components/esp_hw_support/port/esp32c5/pmu_param.c @@ -291,18 +291,7 @@ const pmu_hp_system_analog_param_t * pmu_hp_system_analog_param_default(pmu_hp_m .hp_sleep2active_backup_en = 0, \ .hp_modem2active_backup_en = 0, \ }, \ - .backup_clk = ( \ - BIT(PMU_ICG_FUNC_ENA_REGDMA) | \ - BIT(PMU_ICG_FUNC_ENA_GDMA) | \ - BIT(PMU_ICG_FUNC_ENA_TG0) | \ - BIT(PMU_ICG_FUNC_ENA_TG1) | \ - BIT(PMU_ICG_FUNC_ENA_HPBUS) | \ - BIT(PMU_ICG_FUNC_ENA_MSPI) | \ - BIT(PMU_ICG_FUNC_ENA_IOMUX) | \ - BIT(PMU_ICG_FUNC_ENA_SPI2) | \ - BIT(PMU_ICG_FUNC_ENA_UART0) | \ - BIT(PMU_ICG_FUNC_ENA_SYSTIMER) \ - ) \ + .backup_clk = 0xffffffff, \ } #define PMU_HP_MODEM_RETENTION_CONFIG_DEFAULT() { \ @@ -314,17 +303,7 @@ const pmu_hp_system_analog_param_t * pmu_hp_system_analog_param_default(pmu_hp_m .hp_sleep2modem_backup_mode = PMU_HP_RETENTION_REGDMA_CONFIG(0, 1), \ .hp_sleep2modem_backup_en = 0, \ }, \ - .backup_clk = ( \ - BIT(PMU_ICG_FUNC_ENA_REGDMA) | \ - BIT(PMU_ICG_FUNC_ENA_TG0) | \ - BIT(PMU_ICG_FUNC_ENA_TG1) | \ - BIT(PMU_ICG_FUNC_ENA_HPBUS) | \ - BIT(PMU_ICG_FUNC_ENA_MSPI) | \ - BIT(PMU_ICG_FUNC_ENA_IOMUX) | \ - BIT(PMU_ICG_FUNC_ENA_SPI2) | \ - BIT(PMU_ICG_FUNC_ENA_UART0) | \ - BIT(PMU_ICG_FUNC_ENA_SYSTIMER) \ - ) \ + .backup_clk = 0xffffffff, \ } #define PMU_HP_SLEEP_RETENTION_CONFIG_DEFAULT() { \ @@ -341,17 +320,7 @@ const pmu_hp_system_analog_param_t * pmu_hp_system_analog_param_default(pmu_hp_m .hp_modem2sleep_backup_en = 0, \ .hp_active2sleep_backup_en = 0, \ }, \ - .backup_clk = ( \ - BIT(PMU_ICG_FUNC_ENA_REGDMA) | \ - BIT(PMU_ICG_FUNC_ENA_TG0) | \ - BIT(PMU_ICG_FUNC_ENA_TG1) | \ - BIT(PMU_ICG_FUNC_ENA_HPBUS) | \ - BIT(PMU_ICG_FUNC_ENA_MSPI) | \ - BIT(PMU_ICG_FUNC_ENA_IOMUX) | \ - BIT(PMU_ICG_FUNC_ENA_SPI2) | \ - BIT(PMU_ICG_FUNC_ENA_UART0) | \ - BIT(PMU_ICG_FUNC_ENA_SYSTIMER) \ - ) \ + .backup_clk = 0xffffffff, \ } const pmu_hp_system_retention_param_t * pmu_hp_system_retention_param_default(pmu_hp_mode_t mode) diff --git a/components/esp_hw_support/port/esp32c5/private_include/pmu_param.h b/components/esp_hw_support/port/esp32c5/private_include/pmu_param.h index 8e9909749b8..bbcc0c8e70f 100644 --- a/components/esp_hw_support/port/esp32c5/private_include/pmu_param.h +++ b/components/esp_hw_support/port/esp32c5/private_include/pmu_param.h @@ -87,7 +87,7 @@ const pmu_hp_system_analog_param_t* pmu_hp_system_analog_param_default(pmu_hp_mo typedef struct { pmu_hp_backup_reg_t retention; - uint32_t backup_clk; + uint32_t backup_clk; // icg_func } pmu_hp_system_retention_param_t; const pmu_hp_system_retention_param_t* pmu_hp_system_retention_param_default(pmu_hp_mode_t mode); diff --git a/components/esp_hw_support/port/esp32c6/pmu_param.c b/components/esp_hw_support/port/esp32c6/pmu_param.c index 044c300688e..23acfc34472 100644 --- a/components/esp_hw_support/port/esp32c6/pmu_param.c +++ b/components/esp_hw_support/port/esp32c6/pmu_param.c @@ -291,18 +291,7 @@ const pmu_hp_system_analog_param_t * pmu_hp_system_analog_param_default(pmu_hp_m .hp_sleep2active_backup_en = 0, \ .hp_modem2active_backup_en = 0, \ }, \ - .backup_clk = ( \ - BIT(PMU_ICG_FUNC_ENA_GDMA) | \ - BIT(PMU_ICG_FUNC_ENA_REGDMA) | \ - BIT(PMU_ICG_FUNC_ENA_TG0) | \ - BIT(PMU_ICG_FUNC_ENA_TG1) | \ - BIT(PMU_ICG_FUNC_ENA_HPBUS) | \ - BIT(PMU_ICG_FUNC_ENA_MSPI) | \ - BIT(PMU_ICG_FUNC_ENA_IOMUX) | \ - BIT(PMU_ICG_FUNC_ENA_SPI2) | \ - BIT(PMU_ICG_FUNC_ENA_UART0) | \ - BIT(PMU_ICG_FUNC_ENA_SYSTIMER) \ - ) \ + .backup_clk = 0xffffffff, \ } #define PMU_HP_MODEM_RETENTION_CONFIG_DEFAULT() { \ @@ -314,17 +303,7 @@ const pmu_hp_system_analog_param_t * pmu_hp_system_analog_param_default(pmu_hp_m .hp_sleep2modem_backup_mode = PMU_HP_RETENTION_REGDMA_CONFIG(0, 1), \ .hp_sleep2modem_backup_en = 0, \ }, \ - .backup_clk = ( \ - BIT(PMU_ICG_FUNC_ENA_REGDMA) | \ - BIT(PMU_ICG_FUNC_ENA_TG0) | \ - BIT(PMU_ICG_FUNC_ENA_TG1) | \ - BIT(PMU_ICG_FUNC_ENA_HPBUS) | \ - BIT(PMU_ICG_FUNC_ENA_MSPI) | \ - BIT(PMU_ICG_FUNC_ENA_IOMUX) | \ - BIT(PMU_ICG_FUNC_ENA_SPI2) | \ - BIT(PMU_ICG_FUNC_ENA_UART0) | \ - BIT(PMU_ICG_FUNC_ENA_SYSTIMER) \ - ) \ + .backup_clk = 0xffffffff, \ } #define PMU_HP_SLEEP_RETENTION_CONFIG_DEFAULT() { \ @@ -341,18 +320,7 @@ const pmu_hp_system_analog_param_t * pmu_hp_system_analog_param_default(pmu_hp_m .hp_modem2sleep_backup_en = 0, \ .hp_active2sleep_backup_en = 0, \ }, \ - .backup_clk = ( \ - BIT(PMU_ICG_FUNC_ENA_GDMA) | \ - BIT(PMU_ICG_FUNC_ENA_REGDMA) | \ - BIT(PMU_ICG_FUNC_ENA_TG0) | \ - BIT(PMU_ICG_FUNC_ENA_TG1) | \ - BIT(PMU_ICG_FUNC_ENA_HPBUS) | \ - BIT(PMU_ICG_FUNC_ENA_MSPI) | \ - BIT(PMU_ICG_FUNC_ENA_IOMUX) | \ - BIT(PMU_ICG_FUNC_ENA_SPI2) | \ - BIT(PMU_ICG_FUNC_ENA_UART0) | \ - BIT(PMU_ICG_FUNC_ENA_SYSTIMER) \ - ) \ + .backup_clk = 0xffffffff, \ } const pmu_hp_system_retention_param_t * pmu_hp_system_retention_param_default(pmu_hp_mode_t mode) diff --git a/components/esp_hw_support/port/esp32c6/private_include/pmu_param.h b/components/esp_hw_support/port/esp32c6/private_include/pmu_param.h index fdef78b3300..155c3e810f4 100644 --- a/components/esp_hw_support/port/esp32c6/private_include/pmu_param.h +++ b/components/esp_hw_support/port/esp32c6/private_include/pmu_param.h @@ -92,7 +92,7 @@ const pmu_hp_system_analog_param_t* pmu_hp_system_analog_param_default(pmu_hp_mo typedef struct { pmu_hp_backup_reg_t retention; - uint32_t backup_clk; + uint32_t backup_clk; // icg_func } pmu_hp_system_retention_param_t; const pmu_hp_system_retention_param_t* pmu_hp_system_retention_param_default(pmu_hp_mode_t mode); diff --git a/components/esp_hw_support/port/esp32c61/pmu_param.c b/components/esp_hw_support/port/esp32c61/pmu_param.c index 37105bef538..4883b906772 100644 --- a/components/esp_hw_support/port/esp32c61/pmu_param.c +++ b/components/esp_hw_support/port/esp32c61/pmu_param.c @@ -290,18 +290,7 @@ const pmu_hp_system_analog_param_t * pmu_hp_system_analog_param_default(pmu_hp_m .hp_sleep2active_backup_en = 0, \ .hp_modem2active_backup_en = 0, \ }, \ - .backup_clk = ( \ - BIT(PMU_ICG_FUNC_ENA_REGDMA) | \ - BIT(PMU_ICG_FUNC_ENA_GDMA) | \ - BIT(PMU_ICG_FUNC_ENA_TG0) | \ - BIT(PMU_ICG_FUNC_ENA_TG1) | \ - BIT(PMU_ICG_FUNC_ENA_HPBUS) | \ - BIT(PMU_ICG_FUNC_ENA_MSPI) | \ - BIT(PMU_ICG_FUNC_ENA_IOMUX) | \ - BIT(PMU_ICG_FUNC_ENA_SPI2) | \ - BIT(PMU_ICG_FUNC_ENA_UART0) | \ - BIT(PMU_ICG_FUNC_ENA_SYSTIMER) \ - ) \ + .backup_clk = 0xffffffff, \ } #define PMU_HP_MODEM_RETENTION_CONFIG_DEFAULT() { \ @@ -313,17 +302,7 @@ const pmu_hp_system_analog_param_t * pmu_hp_system_analog_param_default(pmu_hp_m .hp_sleep2modem_backup_mode = PMU_HP_RETENTION_REGDMA_CONFIG(0, 1), \ .hp_sleep2modem_backup_en = 0, \ }, \ - .backup_clk = ( \ - BIT(PMU_ICG_FUNC_ENA_REGDMA) | \ - BIT(PMU_ICG_FUNC_ENA_TG0) | \ - BIT(PMU_ICG_FUNC_ENA_TG1) | \ - BIT(PMU_ICG_FUNC_ENA_HPBUS) | \ - BIT(PMU_ICG_FUNC_ENA_MSPI) | \ - BIT(PMU_ICG_FUNC_ENA_IOMUX) | \ - BIT(PMU_ICG_FUNC_ENA_SPI2) | \ - BIT(PMU_ICG_FUNC_ENA_UART0) | \ - BIT(PMU_ICG_FUNC_ENA_SYSTIMER) \ - ) \ + .backup_clk = 0xffffffff, \ } #define PMU_HP_SLEEP_RETENTION_CONFIG_DEFAULT() { \ @@ -340,17 +319,7 @@ const pmu_hp_system_analog_param_t * pmu_hp_system_analog_param_default(pmu_hp_m .hp_modem2sleep_backup_en = 0, \ .hp_active2sleep_backup_en = 0, \ }, \ - .backup_clk = ( \ - BIT(PMU_ICG_FUNC_ENA_REGDMA) | \ - BIT(PMU_ICG_FUNC_ENA_TG0) | \ - BIT(PMU_ICG_FUNC_ENA_TG1) | \ - BIT(PMU_ICG_FUNC_ENA_HPBUS) | \ - BIT(PMU_ICG_FUNC_ENA_MSPI) | \ - BIT(PMU_ICG_FUNC_ENA_IOMUX) | \ - BIT(PMU_ICG_FUNC_ENA_SPI2) | \ - BIT(PMU_ICG_FUNC_ENA_UART0) | \ - BIT(PMU_ICG_FUNC_ENA_SYSTIMER) \ - ) \ + .backup_clk = 0xffffffff, \ } const pmu_hp_system_retention_param_t * pmu_hp_system_retention_param_default(pmu_hp_mode_t mode) diff --git a/components/esp_hw_support/port/esp32c61/private_include/pmu_param.h b/components/esp_hw_support/port/esp32c61/private_include/pmu_param.h index 80aaac61ee9..4a7516a4f93 100644 --- a/components/esp_hw_support/port/esp32c61/private_include/pmu_param.h +++ b/components/esp_hw_support/port/esp32c61/private_include/pmu_param.h @@ -90,7 +90,7 @@ const pmu_hp_system_analog_param_t* pmu_hp_system_analog_param_default(pmu_hp_mo typedef struct { pmu_hp_backup_reg_t retention; - uint32_t backup_clk; + uint32_t backup_clk; // icg_func } pmu_hp_system_retention_param_t; const pmu_hp_system_retention_param_t* pmu_hp_system_retention_param_default(pmu_hp_mode_t mode); diff --git a/components/esp_hw_support/port/esp32h2/pmu_param.c b/components/esp_hw_support/port/esp32h2/pmu_param.c index 036792a6faa..56f679a9145 100644 --- a/components/esp_hw_support/port/esp32h2/pmu_param.c +++ b/components/esp_hw_support/port/esp32h2/pmu_param.c @@ -290,18 +290,7 @@ const pmu_hp_system_analog_param_t * pmu_hp_system_analog_param_default(pmu_hp_m .hp_sleep2active_backup_en = 0, \ .hp_modem2active_backup_en = 0, \ }, \ - .backup_clk = ( \ - BIT(PMU_ICG_FUNC_ENA_GDMA) \ - | BIT(PMU_ICG_FUNC_ENA_REGDMA) \ - | BIT(PMU_ICG_FUNC_ENA_TG0) \ - | BIT(PMU_ICG_FUNC_ENA_HPBUS) \ - | BIT(PMU_ICG_FUNC_ENA_MSPI) \ - | BIT(PMU_ICG_FUNC_ENA_IOMUX) \ - | BIT(PMU_ICG_FUNC_ENA_SPI2) \ - | BIT(PMU_ICG_FUNC_ENA_SEC) \ - | BIT(PMU_ICG_FUNC_ENA_PWM) \ - | BIT(PMU_ICG_FUNC_ENA_SYSTIMER) \ - | BIT(PMU_ICG_FUNC_ENA_UART0)), \ + .backup_clk = 0xffffffff, \ } #define PMU_HP_MODEM_RETENTION_CONFIG_DEFAULT() { \ @@ -313,16 +302,7 @@ const pmu_hp_system_analog_param_t * pmu_hp_system_analog_param_default(pmu_hp_m .hp_sleep2modem_backup_mode = PMU_HP_RETENTION_REGDMA_CONFIG(0, 1), \ .hp_sleep2modem_backup_en = 0, \ }, \ - .backup_clk = (BIT(PMU_ICG_FUNC_ENA_REGDMA) \ - | BIT(PMU_ICG_FUNC_ENA_TG0) \ - | BIT(PMU_ICG_FUNC_ENA_HPBUS) \ - | BIT(PMU_ICG_FUNC_ENA_MSPI) \ - | BIT(PMU_ICG_FUNC_ENA_IOMUX) \ - | BIT(PMU_ICG_FUNC_ENA_SPI2) \ - | BIT(PMU_ICG_FUNC_ENA_SEC) \ - | BIT(PMU_ICG_FUNC_ENA_PWM) \ - | BIT(PMU_ICG_FUNC_ENA_SYSTIMER) \ - | BIT(PMU_ICG_FUNC_ENA_UART0)), \ + .backup_clk = 0xffffffff, \ } #define PMU_HP_SLEEP_RETENTION_CONFIG_DEFAULT() { \ @@ -339,18 +319,7 @@ const pmu_hp_system_analog_param_t * pmu_hp_system_analog_param_default(pmu_hp_m .hp_modem2sleep_backup_en = 0, \ .hp_active2sleep_backup_en = 0, \ }, \ - .backup_clk = ( \ - BIT(PMU_ICG_FUNC_ENA_GDMA) \ - | BIT(PMU_ICG_FUNC_ENA_REGDMA) \ - | BIT(PMU_ICG_FUNC_ENA_TG0) \ - | BIT(PMU_ICG_FUNC_ENA_HPBUS) \ - | BIT(PMU_ICG_FUNC_ENA_MSPI) \ - | BIT(PMU_ICG_FUNC_ENA_IOMUX) \ - | BIT(PMU_ICG_FUNC_ENA_SPI2) \ - | BIT(PMU_ICG_FUNC_ENA_SEC) \ - | BIT(PMU_ICG_FUNC_ENA_PWM) \ - | BIT(PMU_ICG_FUNC_ENA_SYSTIMER) \ - | BIT(PMU_ICG_FUNC_ENA_UART0)), \ + .backup_clk = 0xffffffff, \ } const pmu_hp_system_retention_param_t * pmu_hp_system_retention_param_default(pmu_hp_mode_t mode) diff --git a/components/esp_hw_support/port/esp32h2/private_include/pmu_param.h b/components/esp_hw_support/port/esp32h2/private_include/pmu_param.h index 58fbf97ff48..bb78a1e7759 100644 --- a/components/esp_hw_support/port/esp32h2/private_include/pmu_param.h +++ b/components/esp_hw_support/port/esp32h2/private_include/pmu_param.h @@ -85,7 +85,7 @@ const pmu_hp_system_analog_param_t * pmu_hp_system_analog_param_default(pmu_hp_m typedef struct { pmu_hp_backup_reg_t retention; - uint32_t backup_clk; + uint32_t backup_clk; // icg_func } pmu_hp_system_retention_param_t; const pmu_hp_system_retention_param_t * pmu_hp_system_retention_param_default(pmu_hp_mode_t mode); @@ -407,7 +407,7 @@ typedef struct { typedef struct pmu_sleep_machine_constant { struct { - uint16_t min_slp_time_us; /* Mininum sleep protection time (unit: microsecond) */ + uint16_t min_slp_time_us; /* Minimum sleep protection time (unit: microsecond) */ uint8_t reserved0; uint16_t reserved1; uint16_t analog_wait_time_us; /* LP LDO power up wait time (unit: microsecond) */ @@ -418,7 +418,7 @@ typedef struct pmu_sleep_machine_constant { uint16_t power_up_wait_time_us; /* (unit: microsecond) */ } lp; struct { - uint16_t min_slp_time_us; /* Mininum sleep protection time (unit: microsecond) */ + uint16_t min_slp_time_us; /* Minimum sleep protection time (unit: microsecond) */ uint16_t analog_wait_time_us; /* HP LDO power up wait time (unit: microsecond) */ uint16_t power_supply_wait_time_us; /* (unit: microsecond) */ uint16_t power_up_wait_time_us; /* (unit: microsecond) */ diff --git a/components/esp_hw_support/port/esp32p4/pmu_param.c b/components/esp_hw_support/port/esp32p4/pmu_param.c index 0905a1268a4..c1c8896f37a 100644 --- a/components/esp_hw_support/port/esp32p4/pmu_param.c +++ b/components/esp_hw_support/port/esp32p4/pmu_param.c @@ -208,18 +208,7 @@ const pmu_hp_system_analog_param_t * pmu_hp_system_analog_param_default(pmu_hp_m .hp_sleep2active_backup_en = 0, \ .hp_modem2active_backup_en = 0, \ }, \ - .backup_clk = ( \ - BIT(PMU_ICG_FUNC_ENA_L2MEM_MEM) | \ - BIT(PMU_ICG_FUNC_ENA_L2MEM_SYS) | \ - BIT(PMU_ICG_FUNC_ENA_REGDMA) | \ - BIT(PMU_ICG_FUNC_ENA_HP_CLKRST) | \ - BIT(PMU_ICG_FUNC_ENA_SYSREG_APB) | \ - BIT(PMU_ICG_FUNC_ENA_ICM_CPU) | \ - BIT(PMU_ICG_FUNC_ENA_ICM_APB) | \ - BIT(PMU_ICG_FUNC_ENA_ICM_SYS) | \ - BIT(PMU_ICG_FUNC_ENA_ICM_MEM) | \ - BIT(PMU_ICG_FUNC_ENA_INTRMTX_APB) \ - ) \ + .backup_clk = 0xffffffff, \ } #define PMU_HP_SLEEP_RETENTION_CONFIG_DEFAULT() { \ @@ -236,18 +225,7 @@ const pmu_hp_system_analog_param_t * pmu_hp_system_analog_param_default(pmu_hp_m .hp_modem2sleep_backup_en = 0, \ .hp_active2sleep_backup_en = 0, \ }, \ - .backup_clk = ( \ - BIT(PMU_ICG_FUNC_ENA_L2MEM_MEM) | \ - BIT(PMU_ICG_FUNC_ENA_L2MEM_SYS) | \ - BIT(PMU_ICG_FUNC_ENA_REGDMA) | \ - BIT(PMU_ICG_FUNC_ENA_HP_CLKRST) | \ - BIT(PMU_ICG_FUNC_ENA_SYSREG_APB) | \ - BIT(PMU_ICG_FUNC_ENA_ICM_CPU) | \ - BIT(PMU_ICG_FUNC_ENA_ICM_APB) | \ - BIT(PMU_ICG_FUNC_ENA_ICM_SYS) | \ - BIT(PMU_ICG_FUNC_ENA_ICM_MEM) | \ - BIT(PMU_ICG_FUNC_ENA_INTRMTX_APB) \ - ) \ + .backup_clk = 0xffffffff, \ } const pmu_hp_system_retention_param_t * pmu_hp_system_retention_param_default(pmu_hp_mode_t mode) diff --git a/components/esp_hw_support/port/esp32p4/private_include/pmu_param.h b/components/esp_hw_support/port/esp32p4/private_include/pmu_param.h index 9c8be63ac55..37e67fc4831 100644 --- a/components/esp_hw_support/port/esp32p4/private_include/pmu_param.h +++ b/components/esp_hw_support/port/esp32p4/private_include/pmu_param.h @@ -86,7 +86,7 @@ const pmu_hp_system_analog_param_t* pmu_hp_system_analog_param_default(pmu_hp_mo typedef struct { pmu_hp_backup_reg_t retention; - uint32_t backup_clk; + uint32_t backup_clk; // icg_func } pmu_hp_system_retention_param_t; const pmu_hp_system_retention_param_t* pmu_hp_system_retention_param_default(pmu_hp_mode_t mode); From 7c0b1dc98c84437e7e3c6f52ed08183eee418415 Mon Sep 17 00:00:00 2001 From: Song Ruo Jing Date: Thu, 17 Oct 2024 12:23:49 +0800 Subject: [PATCH 184/472] fix(clk): rtc_clk_cpu_freq_set_xtal will always disable CPU's PLL Align C6/H2/C5/C61 rtc_clk_cpu_freq_set_xtal behavior to other chips For PMU supported chips, powering down CPU PLL in sleep will be done by PMU, not sleep code --- .../esp_hw_support/include/esp_private/rtc_clk.h | 15 +++++---------- .../esp_hw_support/port/esp32c5/include/soc/rtc.h | 5 +++-- components/esp_hw_support/port/esp32c5/rtc_clk.c | 6 ++---- .../esp_hw_support/port/esp32c6/include/soc/rtc.h | 5 +++-- components/esp_hw_support/port/esp32c6/rtc_clk.c | 6 ++---- .../port/esp32c61/include/soc/rtc.h | 5 +++-- components/esp_hw_support/port/esp32c61/rtc_clk.c | 6 ++---- .../esp_hw_support/port/esp32h2/include/soc/rtc.h | 5 +++-- components/esp_hw_support/port/esp32h2/rtc_clk.c | 6 ++---- .../esp_hw_support/port/esp32p4/include/soc/rtc.h | 4 ++-- components/esp_hw_support/port/esp32p4/rtc_clk.c | 1 + components/esp_hw_support/sleep_modes.c | 9 +++++++++ 12 files changed, 37 insertions(+), 36 deletions(-) diff --git a/components/esp_hw_support/include/esp_private/rtc_clk.h b/components/esp_hw_support/include/esp_private/rtc_clk.h index 52610fa0d1c..4480780217f 100644 --- a/components/esp_hw_support/include/esp_private/rtc_clk.h +++ b/components/esp_hw_support/include/esp_private/rtc_clk.h @@ -18,11 +18,12 @@ extern "C" { * @brief Switch CPU clock source to XTAL, and let cpu frequency equal to main XTAL frequency. * * This function does not disable CPU's source PLL. If the PLL requires to be disabled to save power, please call - * `rtc_clk_cpu_freq_set_xtal` instead. It does one extra check (if necessary) to see whether can disable the - * corresponding PLL after switching the CPU clock source to XTAL. + * `rtc_clk_cpu_freq_set_xtal` instead. It will always disable the corresponding PLL after switching the CPU clock + * source to XTAL (except for S2). * - * Currently, this function should only be called in `esp_restart_noos` and `esp_restart_noos_dig` to switch the CPU - * clock source back to XTAL (by default) before reset. + * Currently, this function is only called in `esp_restart_noos` and `esp_restart_noos_dig` to switch the CPU + * clock source back to XTAL (by default) before reset, and in `esp_sleep_start` to switch CPU clock source to XTAL + * before entering sleep for PMU supported chips. */ void rtc_clk_cpu_set_to_default_config(void); @@ -32,12 +33,6 @@ void rtc_clk_cpu_set_to_default_config(void); * Currently, this function is only used for tracking whether USB Serial/JTAG is using the 48MHz PHY clock * * Note: Calling this function only helps to not disable the BBPLL clock in `rtc_clk_cpu_freq_set_config`. - * For light and deep sleep, whether to disable the BBPLL in the internal call to `rtc_clk_cpu_freq_set_xtal` - * varies for targets. - * On ESP32C3/S3, USB CDC device can not function properly during sleep due to the lack of APB clock. Therefore. - * `rtc_clk_cpu_freq_set_xtal` will always disable BBPLL, no matter whether BBPLL has any consumer. - * On ESP32C6/H2, USB CDC device can maintain the minimum connection with the host during sleep, so - * `rtc_clk_cpu_freq_set_xtal` will check for BBPLL consumers, and keep BBPLL if USB Serial/JTAG is in use. */ void rtc_clk_bbpll_add_consumer(void); diff --git a/components/esp_hw_support/port/esp32c5/include/soc/rtc.h b/components/esp_hw_support/port/esp32c5/include/soc/rtc.h index 92a2c4f5c25..a11d201f20c 100644 --- a/components/esp_hw_support/port/esp32c5/include/soc/rtc.h +++ b/components/esp_hw_support/port/esp32c5/include/soc/rtc.h @@ -307,8 +307,9 @@ void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t *out_config); * rtc_clk_cpu_freq_set_config when a switch to XTAL is needed. * Assumes that XTAL frequency has been determined — don't call in startup code. * - * @note On ESP32C5, this function will check whether BBPLL can be disabled. If there is no consumer, then BBPLL will be - * turned off. The behaviour is the same as using rtc_clk_cpu_freq_set_config to switch cpu clock source to XTAL. + * @note This function always disables BBPLL after switching the CPU clock source to XTAL for power saving purpose. + * If this is unwanted, please use rtc_clk_cpu_freq_set_config. It helps to check whether USB Serial JTAG is in use, + * if so, then BBPLL will not be turned off. */ void rtc_clk_cpu_freq_set_xtal(void); diff --git a/components/esp_hw_support/port/esp32c5/rtc_clk.c b/components/esp_hw_support/port/esp32c5/rtc_clk.c index e3d1052c4b0..23a3941c9d2 100644 --- a/components/esp_hw_support/port/esp32c5/rtc_clk.c +++ b/components/esp_hw_support/port/esp32c5/rtc_clk.c @@ -383,10 +383,7 @@ void rtc_clk_cpu_freq_set_config_fast(const rtc_cpu_freq_config_t *config) void rtc_clk_cpu_freq_set_xtal(void) { rtc_clk_cpu_set_to_default_config(); - // We don't turn off the bbpll if some consumers depend on bbpll - if (!s_bbpll_digi_consumers_ref_count) { - rtc_clk_bbpll_disable(); - } + rtc_clk_bbpll_disable(); } void rtc_clk_cpu_set_to_default_config(void) @@ -394,6 +391,7 @@ void rtc_clk_cpu_set_to_default_config(void) int freq_mhz = (int)rtc_clk_xtal_freq_get(); rtc_clk_cpu_freq_to_xtal(freq_mhz, 1); + s_cur_pll_freq = 0; // no disable PLL, but set freq to 0 to trigger a PLL calibration after wake-up from sleep } void rtc_clk_cpu_freq_to_pll_and_pll_lock_release(int cpu_freq_mhz) diff --git a/components/esp_hw_support/port/esp32c6/include/soc/rtc.h b/components/esp_hw_support/port/esp32c6/include/soc/rtc.h index 8d508d5df39..3880b325e5b 100644 --- a/components/esp_hw_support/port/esp32c6/include/soc/rtc.h +++ b/components/esp_hw_support/port/esp32c6/include/soc/rtc.h @@ -338,8 +338,9 @@ void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t *out_config); * rtc_clk_cpu_freq_set_config when a switch to XTAL is needed. * Assumes that XTAL frequency has been determined — don't call in startup code. * - * @note On ESP32C6, this function will check whether BBPLL can be disabled. If there is no consumer, then BBPLL will be - * turned off. The behaviour is the same as using rtc_clk_cpu_freq_set_config to switch cpu clock source to XTAL. + * @note This function always disables BBPLL after switching the CPU clock source to XTAL for power saving purpose. + * If this is unwanted, please use rtc_clk_cpu_freq_set_config. It helps to check whether USB Serial JTAG is in use, + * if so, then BBPLL will not be turned off. */ void rtc_clk_cpu_freq_set_xtal(void); diff --git a/components/esp_hw_support/port/esp32c6/rtc_clk.c b/components/esp_hw_support/port/esp32c6/rtc_clk.c index 521e2fd03f5..c36c48d8593 100644 --- a/components/esp_hw_support/port/esp32c6/rtc_clk.c +++ b/components/esp_hw_support/port/esp32c6/rtc_clk.c @@ -333,10 +333,7 @@ void rtc_clk_cpu_freq_set_config_fast(const rtc_cpu_freq_config_t *config) void rtc_clk_cpu_freq_set_xtal(void) { rtc_clk_cpu_set_to_default_config(); - // We don't turn off the bbpll if some consumers depend on bbpll - if (!s_bbpll_digi_consumers_ref_count) { - rtc_clk_bbpll_disable(); - } + rtc_clk_bbpll_disable(); } void rtc_clk_cpu_set_to_default_config(void) @@ -344,6 +341,7 @@ void rtc_clk_cpu_set_to_default_config(void) int freq_mhz = (int)rtc_clk_xtal_freq_get(); rtc_clk_cpu_freq_to_xtal(freq_mhz, 1); + s_cur_pll_freq = 0; // no disable PLL, but set freq to 0 to trigger a PLL calibration after wake-up from sleep } void rtc_clk_cpu_freq_to_pll_and_pll_lock_release(int cpu_freq_mhz) diff --git a/components/esp_hw_support/port/esp32c61/include/soc/rtc.h b/components/esp_hw_support/port/esp32c61/include/soc/rtc.h index 12c15bc101d..b0413273398 100644 --- a/components/esp_hw_support/port/esp32c61/include/soc/rtc.h +++ b/components/esp_hw_support/port/esp32c61/include/soc/rtc.h @@ -307,8 +307,9 @@ void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t *out_config); * rtc_clk_cpu_freq_set_config when a switch to XTAL is needed. * Assumes that XTAL frequency has been determined — don't call in startup code. * - * @note On ESP32C61, this function will check whether BBPLL can be disabled. If there is no consumer, then BBPLL will be - * turned off. The behaviour is the same as using rtc_clk_cpu_freq_set_config to switch cpu clock source to XTAL. + * @note This function always disables BBPLL after switching the CPU clock source to XTAL for power saving purpose. + * If this is unwanted, please use rtc_clk_cpu_freq_set_config. It helps to check whether USB Serial JTAG is in use, + * if so, then BBPLL will not be turned off. */ void rtc_clk_cpu_freq_set_xtal(void); diff --git a/components/esp_hw_support/port/esp32c61/rtc_clk.c b/components/esp_hw_support/port/esp32c61/rtc_clk.c index e46cdbe1c48..5c32d173585 100644 --- a/components/esp_hw_support/port/esp32c61/rtc_clk.c +++ b/components/esp_hw_support/port/esp32c61/rtc_clk.c @@ -327,10 +327,7 @@ void rtc_clk_cpu_freq_set_config_fast(const rtc_cpu_freq_config_t *config) void rtc_clk_cpu_freq_set_xtal(void) { rtc_clk_cpu_set_to_default_config(); - // We don't turn off the bbpll if some consumers depend on bbpll - if (!s_bbpll_digi_consumers_ref_count) { - rtc_clk_bbpll_disable(); - } + rtc_clk_bbpll_disable(); } void rtc_clk_cpu_set_to_default_config(void) @@ -338,6 +335,7 @@ void rtc_clk_cpu_set_to_default_config(void) int freq_mhz = (int)rtc_clk_xtal_freq_get(); rtc_clk_cpu_freq_to_xtal(freq_mhz, 1); + s_cur_pll_freq = 0; // no disable PLL, but set freq to 0 to trigger a PLL calibration after wake-up from sleep } void rtc_clk_cpu_freq_to_pll_and_pll_lock_release(int cpu_freq_mhz) diff --git a/components/esp_hw_support/port/esp32h2/include/soc/rtc.h b/components/esp_hw_support/port/esp32h2/include/soc/rtc.h index dfd1f96f019..fa820b48d82 100644 --- a/components/esp_hw_support/port/esp32h2/include/soc/rtc.h +++ b/components/esp_hw_support/port/esp32h2/include/soc/rtc.h @@ -354,8 +354,9 @@ void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t *out_config); * rtc_clk_cpu_freq_set_config when a switch to XTAL is needed. * Assumes that XTAL frequency has been determined — don't call in startup code. * - * @note On ESP32H2, this function will check whether BBPLL can be disabled. If there is no consumer, then BBPLL will be - * turned off. The behaviour is the same as using rtc_clk_cpu_freq_set_config to switch cpu clock source to XTAL. + * @note This function always disables BBPLL after switching the CPU clock source to XTAL for power saving purpose. + * If this is unwanted, please use rtc_clk_cpu_freq_set_config. It helps to check whether USB Serial JTAG is in use, + * if so, then BBPLL will not be turned off. */ void rtc_clk_cpu_freq_set_xtal(void); diff --git a/components/esp_hw_support/port/esp32h2/rtc_clk.c b/components/esp_hw_support/port/esp32h2/rtc_clk.c index 0c6664fdce8..7a8a82ef594 100644 --- a/components/esp_hw_support/port/esp32h2/rtc_clk.c +++ b/components/esp_hw_support/port/esp32h2/rtc_clk.c @@ -393,10 +393,7 @@ void rtc_clk_cpu_freq_set_config_fast(const rtc_cpu_freq_config_t *config) void rtc_clk_cpu_freq_set_xtal(void) { rtc_clk_cpu_set_to_default_config(); - // We don't turn off the bbpll if some consumers only depends on bbpll - if (!s_bbpll_digi_consumers_ref_count) { - rtc_clk_bbpll_disable(); - } + rtc_clk_bbpll_disable(); } void rtc_clk_cpu_set_to_default_config(void) @@ -404,6 +401,7 @@ void rtc_clk_cpu_set_to_default_config(void) int freq_mhz = (int)rtc_clk_xtal_freq_get(); rtc_clk_cpu_freq_to_xtal(freq_mhz, 1); + s_cur_pll_freq = 0; // no disable PLL, but set freq to 0 to trigger a PLL calibration after wake-up from sleep } soc_xtal_freq_t rtc_clk_xtal_freq_get(void) diff --git a/components/esp_hw_support/port/esp32p4/include/soc/rtc.h b/components/esp_hw_support/port/esp32p4/include/soc/rtc.h index 183f8a79fe6..43acaa253fa 100644 --- a/components/esp_hw_support/port/esp32p4/include/soc/rtc.h +++ b/components/esp_hw_support/port/esp32p4/include/soc/rtc.h @@ -350,8 +350,8 @@ void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t *out_config); * rtc_clk_cpu_freq_set_config when a switch to XTAL is needed. * Assumes that XTAL frequency has been determined — don't call in startup code. * - * @note On ESP32C6, this function will check whether BBPLL can be disabled. If there is no consumer, then BBPLL will be - * turned off. The behaviour is the same as using rtc_clk_cpu_freq_set_config to switch cpu clock source to XTAL. + * @note On ESP32P4, this function always disables CPLL after switching the CPU clock source to XTAL, + * since there is no peripheral relies on CPLL clock (except Flash/PSRAM if their clock source selects CPLL). */ void rtc_clk_cpu_freq_set_xtal(void); diff --git a/components/esp_hw_support/port/esp32p4/rtc_clk.c b/components/esp_hw_support/port/esp32p4/rtc_clk.c index aa3bfd96750..f9e19ce08c4 100644 --- a/components/esp_hw_support/port/esp32p4/rtc_clk.c +++ b/components/esp_hw_support/port/esp32p4/rtc_clk.c @@ -426,6 +426,7 @@ void rtc_clk_cpu_set_to_default_config(void) int freq_mhz = (int)rtc_clk_xtal_freq_get(); rtc_clk_cpu_freq_to_xtal(freq_mhz, 1, true); + s_cur_cpll_freq = 0; // no disable PLL, but set freq to 0 to trigger a PLL calibration after wake-up from sleep } soc_xtal_freq_t rtc_clk_xtal_freq_get(void) diff --git a/components/esp_hw_support/sleep_modes.c b/components/esp_hw_support/sleep_modes.c index 0f36b970c48..9c60ea1f044 100644 --- a/components/esp_hw_support/sleep_modes.c +++ b/components/esp_hw_support/sleep_modes.c @@ -810,7 +810,16 @@ static esp_err_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags, esp_sleep_mode_t m // Save current frequency and switch to XTAL rtc_cpu_freq_config_t cpu_freq_config; rtc_clk_cpu_freq_get_config(&cpu_freq_config); +#if SOC_PMU_SUPPORTED + // For PMU supported chips, CPU's PLL power can be turned off by PMU, so no need to disable the PLL at here. + // Leaving PLL on at this stage also helps USJ keep connection and retention operation (if they rely on this PLL). + rtc_clk_cpu_set_to_default_config(); +#else + // For earlier chips, there is no PMU module that can turn off the CPU's PLL, so it has to be disabled at here to save the power consumption. + // Though ESP32C3/S3 has USB CDC device, it can not function properly during sleep due to the lack of APB clock (before C6, USJ relies on APB clock to work). + // Therefore, we will always disable CPU's PLL (i.e. BBPLL). rtc_clk_cpu_freq_set_xtal(); +#endif #if SOC_PM_SUPPORT_EXT0_WAKEUP // Configure pins for external wakeup From 61a13d7e3b7d6aae480ef8f440e92a8ccf0b1534 Mon Sep 17 00:00:00 2001 From: Sarvesh Bodakhe Date: Thu, 17 Oct 2024 09:44:22 +0530 Subject: [PATCH 185/472] fix(wifi): Add support to recongize different WPA3 Authentication modes from specs Add support to recognize APs supporting 'WPA3-Enterprise-Only Mode' and 'WPA3-Enterprise-Transition Mode' using authmodes WIFI_AUTH_WPA3_ENTERPRISE and WIFI_AUTH_WPA2_WPA3_ENTERPRISE, respectively. --- components/esp_wifi/include/esp_wifi_types_generic.h | 5 ++++- components/esp_wifi/lib | 2 +- examples/wifi/scan/main/scan.c | 6 ++++++ 3 files changed, 11 insertions(+), 2 deletions(-) diff --git a/components/esp_wifi/include/esp_wifi_types_generic.h b/components/esp_wifi/include/esp_wifi_types_generic.h index 3e49682df5a..74e2a4fb7c3 100644 --- a/components/esp_wifi/include/esp_wifi_types_generic.h +++ b/components/esp_wifi/include/esp_wifi_types_generic.h @@ -62,7 +62,8 @@ typedef struct { } wifi_country_t; /* Strength of authmodes */ -/* OPEN < WEP < WPA_PSK < OWE < WPA2_PSK = WPA_WPA2_PSK < WAPI_PSK < WPA3_PSK = WPA2_WPA3_PSK = DPP */ +/* Personal Networks : OPEN < WEP < WPA_PSK < OWE < WPA2_PSK = WPA_WPA2_PSK < WAPI_PSK < WPA3_PSK = WPA2_WPA3_PSK = DPP + * Enterprise Networks : WIFI_AUTH_WPA2_ENTERPRISE < WIFI_AUTH_WPA3_ENTERPRISE = WIFI_AUTH_WPA2_WPA3_ENTERPRISE < WIFI_AUTH_WPA3_ENT_192 */ typedef enum { WIFI_AUTH_OPEN = 0, /**< authenticate mode : open */ WIFI_AUTH_WEP, /**< authenticate mode : WEP */ @@ -79,6 +80,8 @@ typedef enum { WIFI_AUTH_WPA3_EXT_PSK, /**< this authentication mode will yield same result as WIFI_AUTH_WPA3_PSK and not recommended to be used. It will be deprecated in future, please use WIFI_AUTH_WPA3_PSK instead. */ WIFI_AUTH_WPA3_EXT_PSK_MIXED_MODE, /**< this authentication mode will yield same result as WIFI_AUTH_WPA3_PSK and not recommended to be used. It will be deprecated in future, please use WIFI_AUTH_WPA3_PSK instead.*/ WIFI_AUTH_DPP, /**< authenticate mode : DPP */ + WIFI_AUTH_WPA3_ENTERPRISE, /**< authenticate mode : WPA3-Enterprise Only Mode */ + WIFI_AUTH_WPA2_WPA3_ENTERPRISE, /**< authenticate mode : WPA3-Enterprise Transition Mode */ WIFI_AUTH_MAX } wifi_auth_mode_t; diff --git a/components/esp_wifi/lib b/components/esp_wifi/lib index 5dca4edbc4c..41b2e6890de 160000 --- a/components/esp_wifi/lib +++ b/components/esp_wifi/lib @@ -1 +1 @@ -Subproject commit 5dca4edbc4c5e20406878926fb24e9bbfcb67e88 +Subproject commit 41b2e6890dec98eef2756b6fccd2d4f1417ec9d6 diff --git a/examples/wifi/scan/main/scan.c b/examples/wifi/scan/main/scan.c index 1f4be36b224..2dd34ff907a 100644 --- a/examples/wifi/scan/main/scan.c +++ b/examples/wifi/scan/main/scan.c @@ -59,6 +59,12 @@ static void print_auth_mode(int authmode) case WIFI_AUTH_WPA2_WPA3_PSK: ESP_LOGI(TAG, "Authmode \tWIFI_AUTH_WPA2_WPA3_PSK"); break; + case WIFI_AUTH_WPA3_ENTERPRISE: + ESP_LOGI(TAG, "Authmode \tWIFI_AUTH_WPA3_ENTERPRISE"); + break; + case WIFI_AUTH_WPA2_WPA3_ENTERPRISE: + ESP_LOGI(TAG, "Authmode \tWIFI_AUTH_WPA2_WPA3_ENTERPRISE"); + break; case WIFI_AUTH_WPA3_ENT_192: ESP_LOGI(TAG, "Authmode \tWIFI_AUTH_WPA3_ENT_192"); break; From 5841495e7f474c12be486c7364edf16a46b3e3b1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Tom=C3=A1=C5=A1=20Rohl=C3=ADnek?= Date: Thu, 17 Oct 2024 09:21:33 +0200 Subject: [PATCH 186/472] fix(storage/fatfs): fix CMake project names in fatfs examples --- examples/storage/fatfs/ext_flash/CMakeLists.txt | 2 +- examples/storage/fatfs/fatfsgen/CMakeLists.txt | 2 +- examples/storage/fatfs/fs_operations/CMakeLists.txt | 2 +- examples/storage/fatfs/getting_started/CMakeLists.txt | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/examples/storage/fatfs/ext_flash/CMakeLists.txt b/examples/storage/fatfs/ext_flash/CMakeLists.txt index 93841c0e29c..66233663cd7 100644 --- a/examples/storage/fatfs/ext_flash/CMakeLists.txt +++ b/examples/storage/fatfs/ext_flash/CMakeLists.txt @@ -4,4 +4,4 @@ cmake_minimum_required(VERSION 3.16) # external SPI flash driver not currently supported for ESP32-S2 include($ENV{IDF_PATH}/tools/cmake/project.cmake) -project(ext_flash_fatfs) +project(fatfs_ext_flash) diff --git a/examples/storage/fatfs/fatfsgen/CMakeLists.txt b/examples/storage/fatfs/fatfsgen/CMakeLists.txt index 1c0c2b8a1a2..0399bf40c59 100644 --- a/examples/storage/fatfs/fatfsgen/CMakeLists.txt +++ b/examples/storage/fatfs/fatfsgen/CMakeLists.txt @@ -3,4 +3,4 @@ cmake_minimum_required(VERSION 3.16) include($ENV{IDF_PATH}/tools/cmake/project.cmake) -project(fatfsgen) +project(fatfs_fatfsgen) diff --git a/examples/storage/fatfs/fs_operations/CMakeLists.txt b/examples/storage/fatfs/fs_operations/CMakeLists.txt index 1c0c2b8a1a2..2f478de10dd 100644 --- a/examples/storage/fatfs/fs_operations/CMakeLists.txt +++ b/examples/storage/fatfs/fs_operations/CMakeLists.txt @@ -3,4 +3,4 @@ cmake_minimum_required(VERSION 3.16) include($ENV{IDF_PATH}/tools/cmake/project.cmake) -project(fatfsgen) +project(fatfs_fs_operations) diff --git a/examples/storage/fatfs/getting_started/CMakeLists.txt b/examples/storage/fatfs/getting_started/CMakeLists.txt index 1c0c2b8a1a2..b5959836791 100644 --- a/examples/storage/fatfs/getting_started/CMakeLists.txt +++ b/examples/storage/fatfs/getting_started/CMakeLists.txt @@ -3,4 +3,4 @@ cmake_minimum_required(VERSION 3.16) include($ENV{IDF_PATH}/tools/cmake/project.cmake) -project(fatfsgen) +project(fatfs_getting_started) From 4ae7b4aecf473b96113284b096e5f1b95f2f4b2e Mon Sep 17 00:00:00 2001 From: chenjianhua Date: Mon, 30 Sep 2024 11:04:33 +0800 Subject: [PATCH 187/472] feat(bt/bluedroid): Added API to set supported channel selection algorithm --- .../bt/host/bluedroid/api/esp_gap_ble_api.c | 17 +++++++++++++ .../api/include/api/esp_gap_ble_api.h | 24 +++++++++++++++++++ .../bt/host/bluedroid/bta/dm/bta_dm_act.c | 6 +++++ .../bt/host/bluedroid/bta/dm/bta_dm_api.c | 13 ++++++++++ .../bt/host/bluedroid/bta/dm/bta_dm_main.c | 1 + .../bluedroid/bta/dm/include/bta_dm_int.h | 9 +++++++ .../host/bluedroid/bta/include/bta/bta_api.h | 4 ++++ .../btc/profile/std/gap/btc_gap_ble.c | 22 +++++++++++++++++ .../btc/profile/std/include/btc_gap_ble.h | 5 ++++ .../bt/host/bluedroid/stack/btm/btm_ble_gap.c | 11 +++++++++ .../bt/host/bluedroid/stack/btm/btm_devctl.c | 8 +++++++ .../bluedroid/stack/btm/include/btm_ble_int.h | 1 + .../bt/host/bluedroid/stack/hcic/hciblecmds.c | 24 ++++++++++++++++++- .../stack/include/stack/btm_ble_api.h | 15 ++++++++++++ .../bluedroid/stack/include/stack/hcidefs.h | 3 +++ .../bluedroid/stack/include/stack/hcimsgs.h | 8 +++++-- 16 files changed, 168 insertions(+), 3 deletions(-) diff --git a/components/bt/host/bluedroid/api/esp_gap_ble_api.c b/components/bt/host/bluedroid/api/esp_gap_ble_api.c index d37f3724be8..a4122529799 100644 --- a/components/bt/host/bluedroid/api/esp_gap_ble_api.c +++ b/components/bt/host/bluedroid/api/esp_gap_ble_api.c @@ -1049,6 +1049,23 @@ esp_err_t esp_ble_gap_set_privacy_mode(esp_ble_addr_type_t addr_type, esp_bd_add == BT_STATUS_SUCCESS ? ESP_OK : ESP_FAIL); } +esp_err_t esp_ble_gap_set_csa_support(uint8_t csa_select) +{ + btc_msg_t msg; + btc_ble_gap_args_t arg; + + ESP_BLUEDROID_STATUS_CHECK(ESP_BLUEDROID_STATUS_ENABLED); + + msg.sig = BTC_SIG_API_CALL; + msg.pid = BTC_PID_GAP_BLE; + msg.act = BTC_GAP_BLE_SET_CSA_SUPPORT; + + arg.set_csa_support.csa_select = csa_select; + + return (btc_transfer_context(&msg, &arg, sizeof(btc_ble_gap_args_t), NULL, NULL) + == BT_STATUS_SUCCESS ? ESP_OK : ESP_FAIL); +} + #if (BLE_50_FEATURE_SUPPORT == TRUE) esp_err_t esp_ble_gap_read_phy(esp_bd_addr_t bd_addr) diff --git a/components/bt/host/bluedroid/api/include/api/esp_gap_ble_api.h b/components/bt/host/bluedroid/api/include/api/esp_gap_ble_api.h index 589945b3175..83fea16a99c 100644 --- a/components/bt/host/bluedroid/api/include/api/esp_gap_ble_api.h +++ b/components/bt/host/bluedroid/api/include/api/esp_gap_ble_api.h @@ -229,6 +229,7 @@ typedef enum { ESP_GAP_BLE_ADD_DEV_TO_RESOLVING_LIST_COMPLETE_EVT, /*!< when add a device to the resolving list completes, the event comes*/ ESP_GAP_BLE_VENDOR_CMD_COMPLETE_EVT, /*!< When vendor hci command complete, the event comes */ ESP_GAP_BLE_SET_PRIVACY_MODE_COMPLETE_EVT, /*!< When set privacy mode complete, the event comes */ + ESP_GAP_BLE_SET_CSA_SUPPORT_COMPLETE_EVT, /*!< When set CSA support complete, the event comes */ ESP_GAP_BLE_EVT_MAX, /*!< when maximum advertising event complete, the event comes */ } esp_gap_ble_cb_event_t; @@ -1572,6 +1573,12 @@ typedef union { struct ble_set_privacy_mode_cmpl_evt_param { esp_bt_status_t status; /*!< Indicate privacy mode set operation success status */ } set_privacy_mode_cmpl; /*!< Event parameter of ESP_GAP_BLE_SET_PRIVACY_MODE_COMPLETE_EVT */ + /** + * @brief ESP_GAP_BLE_SET_CSA_SUPPORT_COMPLETE_EVT + */ + struct ble_set_csa_support_cmpl_evt_param { + esp_bt_status_t status; /*!< Indicate CSA support set operation success status */ + } set_csa_support_cmpl; /*!< Event parameter of ESP_GAP_BLE_SET_CSA_SUPPORT_COMPLETE_EVT */ } esp_ble_gap_cb_param_t; /** @@ -2744,6 +2751,23 @@ esp_err_t esp_ble_gap_vendor_command_send(esp_ble_vendor_cmd_params_t *vendor_cm */ esp_err_t esp_ble_gap_set_privacy_mode(esp_ble_addr_type_t addr_type, esp_bd_addr_t addr, esp_ble_privacy_mode_t mode); +/** + * @brief This function is used to set which channel selection algorithm(CSA) is supported. + * + * @note - This function should only be used when there are BLE compatibility issues about channel hopping after connected. + * For example, if the peer device only supports CSA#1, this function can be called to make the Controller use CSA#1. + * - This function is not supported on ESP32. + * + * @param[in] csa_select: 0: Channel Selection Algorighm will be selected by Controller + * 1: Select the LE Channel Selection Algorighm #1 + * 2: Select the LE Channel Selection Algorighm #2 + * + * @return + * - ESP_OK : success + * - other : failed + */ +esp_err_t esp_ble_gap_set_csa_support(uint8_t csa_select); + #ifdef __cplusplus } #endif diff --git a/components/bt/host/bluedroid/bta/dm/bta_dm_act.c b/components/bt/host/bluedroid/bta/dm/bta_dm_act.c index 0ff6dc6c2ca..58d545d3b94 100644 --- a/components/bt/host/bluedroid/bta/dm/bta_dm_act.c +++ b/components/bt/host/bluedroid/bta/dm/bta_dm_act.c @@ -5859,6 +5859,12 @@ void bta_dm_ble_gap_set_privacy_mode(tBTA_DM_MSG *p_data) p_data->ble_set_privacy_mode.privacy_mode, p_data->ble_set_privacy_mode.p_cback); } +void bta_dm_ble_gap_set_csa_support(tBTA_DM_MSG *p_data) +{ + APPL_TRACE_API("%s, csa_select = %d", __func__, p_data->ble_set_csa_support.csa_select); + BTM_BleSetCsaSupport(p_data->ble_set_csa_support.csa_select, p_data->ble_set_csa_support.p_cback); +} + #if (BLE_50_FEATURE_SUPPORT == TRUE) void bta_dm_ble_gap_dtm_enhance_tx_start(tBTA_DM_MSG *p_data) { diff --git a/components/bt/host/bluedroid/bta/dm/bta_dm_api.c b/components/bt/host/bluedroid/bta/dm/bta_dm_api.c index 7ec61ee9994..71555246373 100644 --- a/components/bt/host/bluedroid/bta/dm/bta_dm_api.c +++ b/components/bt/host/bluedroid/bta/dm/bta_dm_api.c @@ -3025,6 +3025,19 @@ void BTA_DmClearRandAddress(void) } } +void BTA_DmBleGapSetCsaSupport(uint8_t csa_select, tBTA_SET_CSA_SUPPORT_CMPL_CBACK *p_callback) +{ + tBTA_DM_API_BLE_SET_CSA_SUPPORT *p_msg; + + if ((p_msg = (tBTA_DM_API_BLE_SET_CSA_SUPPORT *)osi_malloc(sizeof(tBTA_DM_API_BLE_SET_CSA_SUPPORT))) + != NULL) { + p_msg->hdr.event = BTA_DM_API_BLE_SET_CSA_SUPPORT_EVT; + p_msg->csa_select = csa_select; + p_msg->p_cback = p_callback; + bta_sys_sendmsg(p_msg); + } +} + /******************************************************************************* ** ** Function BTA_VendorInit diff --git a/components/bt/host/bluedroid/bta/dm/bta_dm_main.c b/components/bt/host/bluedroid/bta/dm/bta_dm_main.c index 99736d8ecec..2d747f5b078 100644 --- a/components/bt/host/bluedroid/bta/dm/bta_dm_main.c +++ b/components/bt/host/bluedroid/bta/dm/bta_dm_main.c @@ -235,6 +235,7 @@ const tBTA_DM_ACTION bta_dm_action[BTA_DM_MAX_EVT] = { bta_dm_ble_gap_set_rpa_timeout, /* BTA_DM_API_SET_RPA_TIMEOUT_EVT */ bta_dm_ble_gap_add_dev_to_resolving_list, /* BTA_DM_API_ADD_DEV_TO_RESOLVING_LIST_EVT */ bta_dm_ble_gap_set_privacy_mode, /* BTA_DM_API_SET_PRIVACY_MODE_EVT */ + bta_dm_ble_gap_set_csa_support, /* BTA_DM_API_BLE_SET_CSA_SUPPORT_EVT */ #endif }; diff --git a/components/bt/host/bluedroid/bta/dm/include/bta_dm_int.h b/components/bt/host/bluedroid/bta/dm/include/bta_dm_int.h index 862393fe8ab..29af35c6dc5 100644 --- a/components/bt/host/bluedroid/bta/dm/include/bta_dm_int.h +++ b/components/bt/host/bluedroid/bta/dm/include/bta_dm_int.h @@ -226,6 +226,7 @@ enum { BTA_DM_API_SET_RPA_TIMEOUT_EVT, BTA_DM_API_ADD_DEV_TO_RESOLVING_LIST_EVT, BTA_DM_API_SET_PRIVACY_MODE_EVT, + BTA_DM_API_BLE_SET_CSA_SUPPORT_EVT, #endif BTA_DM_MAX_EVT }; @@ -959,6 +960,12 @@ typedef struct { tBTA_SET_PRIVACY_MODE_CMPL_CBACK *p_cback; } tBTA_DM_API_SET_PRIVACY_MODE; +typedef struct { + BT_HDR hdr; + UINT8 csa_select; + tBTA_SET_CSA_SUPPORT_CMPL_CBACK *p_cback; +} tBTA_DM_API_BLE_SET_CSA_SUPPORT; + #endif /* BLE_INCLUDED */ /* data type for BTA_DM_API_REMOVE_ACL_EVT */ @@ -1365,6 +1372,7 @@ typedef union { tBTA_DM_API_BLE_DTM_STOP dtm_stop; tBTA_DM_API_CLEAR_ADV ble_clear_adv; tBTA_DM_API_SET_PRIVACY_MODE ble_set_privacy_mode; + tBTA_DM_API_BLE_SET_CSA_SUPPORT ble_set_csa_support; #endif tBTA_DM_API_REMOVE_ACL remove_acl; @@ -1817,6 +1825,7 @@ extern void bta_dm_ble_gap_clear_adv(tBTA_DM_MSG *p_data); extern void bta_dm_ble_gap_set_rpa_timeout(tBTA_DM_MSG *p_data); extern void bta_dm_ble_gap_add_dev_to_resolving_list(tBTA_DM_MSG *p_data); extern void bta_dm_ble_gap_set_privacy_mode(tBTA_DM_MSG *p_data); +extern void bta_dm_ble_gap_set_csa_support(tBTA_DM_MSG *p_data); #if (BLE_50_FEATURE_SUPPORT == TRUE) extern void bta_dm_ble_gap_dtm_enhance_tx_start(tBTA_DM_MSG *p_data); extern void bta_dm_ble_gap_dtm_enhance_rx_start(tBTA_DM_MSG *p_data); diff --git a/components/bt/host/bluedroid/bta/include/bta/bta_api.h b/components/bt/host/bluedroid/bta/include/bta/bta_api.h index 2ba9707de5f..c0cabab2c71 100644 --- a/components/bt/host/bluedroid/bta/include/bta/bta_api.h +++ b/components/bt/host/bluedroid/bta/include/bta/bta_api.h @@ -439,6 +439,8 @@ typedef tBTM_ADD_DEV_TO_RESOLVING_LIST_CMPL_CBACK tBTA_ADD_DEV_TO_RESOLVING_LIST typedef tBTM_SET_PRIVACY_MODE_CMPL_CBACK tBTA_SET_PRIVACY_MODE_CMPL_CBACK; +typedef tBTM_SET_CSA_SUPPORT_CMPL_CBACK tBTA_SET_CSA_SUPPORT_CMPL_CBACK; + typedef tBTM_CMPL_CB tBTA_CMPL_CB; typedef tBTM_VSC_CMPL tBTA_VSC_CMPL; @@ -2921,6 +2923,8 @@ extern void BTA_DmBleDtmStop(tBTA_DTM_CMD_CMPL_CBACK *p_dtm_cmpl_cback); extern void BTA_DmBleSetPrivacyMode(uint8_t addr_type, BD_ADDR addr, uint8_t privacy_mode, tBTA_SET_PRIVACY_MODE_CMPL_CBACK *p_cback); +extern void BTA_DmBleGapSetCsaSupport(uint8_t csa_select, tBTM_SET_CSA_SUPPORT_CMPL_CBACK *p_callback); + /******************************************************************************* ** ** Function BTA_DmBleSetStorageParams diff --git a/components/bt/host/bluedroid/btc/profile/std/gap/btc_gap_ble.c b/components/bt/host/bluedroid/btc/profile/std/gap/btc_gap_ble.c index 464f032417c..b4867033466 100644 --- a/components/bt/host/bluedroid/btc/profile/std/gap/btc_gap_ble.c +++ b/components/bt/host/bluedroid/btc/profile/std/gap/btc_gap_ble.c @@ -1363,6 +1363,25 @@ static void btc_ble_set_privacy_mode_callback(UINT8 status) } } +static void btc_ble_set_csa_support_callback(UINT8 status) +{ + esp_ble_gap_cb_param_t param; + bt_status_t ret; + btc_msg_t msg = {0}; + + msg.sig = BTC_SIG_API_CB; + msg.pid = BTC_PID_GAP_BLE; + msg.act = ESP_GAP_BLE_SET_CSA_SUPPORT_COMPLETE_EVT; + + param.set_csa_support_cmpl.status = btc_btm_status_to_esp_status(status); + + ret = btc_transfer_context(&msg, ¶m, sizeof(esp_ble_gap_cb_param_t), NULL, NULL); + + if (ret != BT_STATUS_SUCCESS) { + BTC_TRACE_ERROR("%s btc_transfer_context failed\n", __func__); + } +} + void btc_get_whitelist_size(uint16_t *length) { BTM_BleGetWhiteListSize(length); @@ -2402,6 +2421,9 @@ void btc_gap_ble_call_handler(btc_msg_t *msg) btc_ble_set_privacy_mode(arg->set_privacy_mode.addr_type, arg->set_privacy_mode.addr, arg->set_privacy_mode.privacy_mode, btc_ble_set_privacy_mode_callback); break; + case BTC_GAP_BLE_SET_CSA_SUPPORT: + BTA_DmBleGapSetCsaSupport(arg->set_csa_support.csa_select, btc_ble_set_csa_support_callback); + break; default: break; } diff --git a/components/bt/host/bluedroid/btc/profile/std/include/btc_gap_ble.h b/components/bt/host/bluedroid/btc/profile/std/include/btc_gap_ble.h index e540116de19..e1324b5faf4 100644 --- a/components/bt/host/bluedroid/btc/profile/std/include/btc_gap_ble.h +++ b/components/bt/host/bluedroid/btc/profile/std/include/btc_gap_ble.h @@ -106,6 +106,7 @@ typedef enum { BTC_GAP_BLE_ACT_ADD_DEVICE_TO_RESOLVING_LIST, BTC_GAP_BLE_ACT_VENDOR_HCI_CMD_EVT, BTC_GAP_BLE_SET_PRIVACY_MODE, + BTC_GAP_BLE_SET_CSA_SUPPORT, } btc_gap_ble_act_t; /* btc_ble_gap_args_t */ @@ -274,6 +275,10 @@ typedef union { esp_bd_addr_t addr; uint8_t privacy_mode; } set_privacy_mode; + // BTC_GAP_BLE_SET_CSA_SUPPORT + struct set_csa_support_args { + uint8_t csa_select; + } set_csa_support; } btc_ble_gap_args_t; #if (BLE_50_FEATURE_SUPPORT == TRUE) diff --git a/components/bt/host/bluedroid/stack/btm/btm_ble_gap.c b/components/bt/host/bluedroid/stack/btm/btm_ble_gap.c index a85f6a16112..bef993d1852 100644 --- a/components/bt/host/bluedroid/stack/btm/btm_ble_gap.c +++ b/components/bt/host/bluedroid/stack/btm/btm_ble_gap.c @@ -4761,6 +4761,17 @@ BOOLEAN BTM_BleSetPrivacyMode(UINT8 addr_type, BD_ADDR bd_addr, UINT8 privacy_mo return TRUE; } +BOOLEAN BTM_BleSetCsaSupport(UINT8 csa_select, tBTM_SET_CSA_SUPPORT_CMPL_CBACK *p_callback) +{ + if (btsnd_hcic_ble_set_csa_support(csa_select) != TRUE) { + BTM_TRACE_ERROR("LE SetCsaSupport csa_select=%d: error", csa_select); + return FALSE; + } + + btm_cb.ble_ctr_cb.set_csa_support_cmpl_cb = p_callback; + return TRUE; +} + bool btm_ble_adv_pkt_ready(void) { tBTM_BLE_CB *p_cb = &btm_cb.ble_ctr_cb; diff --git a/components/bt/host/bluedroid/stack/btm/btm_devctl.c b/components/bt/host/bluedroid/stack/btm/btm_devctl.c index bab88739a08..d3c4ac61da2 100644 --- a/components/bt/host/bluedroid/stack/btm/btm_devctl.c +++ b/components/bt/host/bluedroid/stack/btm/btm_devctl.c @@ -773,6 +773,14 @@ void btm_vsc_complete (UINT8 *p, UINT16 opcode, UINT16 evt_len, } break; } + case HCI_VENDOR_BLE_SET_CSA_SUPPORT: { + uint8_t status; + STREAM_TO_UINT8(status, p); + if (ble_cb && ble_cb->set_csa_support_cmpl_cb) { + ble_cb->set_csa_support_cmpl_cb(status); + } + break; + } default: break; } diff --git a/components/bt/host/bluedroid/stack/btm/include/btm_ble_int.h b/components/bt/host/bluedroid/stack/btm/include/btm_ble_int.h index 0f8888fb1bd..d81a03c0a92 100644 --- a/components/bt/host/bluedroid/stack/btm/include/btm_ble_int.h +++ b/components/bt/host/bluedroid/stack/btm/include/btm_ble_int.h @@ -377,6 +377,7 @@ typedef struct { tBTM_BLE_STATE_MASK cur_states; /* bit mask of tBTM_BLE_STATE */ UINT8 link_count[2]; /* total link count master and slave*/ tBTM_UPDATE_DUPLICATE_EXCEPTIONAL_LIST_CMPL_CBACK *update_exceptional_list_cmp_cb; + tBTM_SET_CSA_SUPPORT_CMPL_CBACK *set_csa_support_cmpl_cb; } tBTM_BLE_CB; #ifdef __cplusplus diff --git a/components/bt/host/bluedroid/stack/hcic/hciblecmds.c b/components/bt/host/bluedroid/stack/hcic/hciblecmds.c index 52a2b2dc09e..c51746b1aae 100644 --- a/components/bt/host/bluedroid/stack/hcic/hciblecmds.c +++ b/components/bt/host/bluedroid/stack/hcic/hciblecmds.c @@ -1910,7 +1910,7 @@ UINT8 btsnd_hcic_ble_set_default_periodic_adv_sync_trans_params(UINT8 mode, UINT } #endif // #if (BLE_FEAT_PERIODIC_ADV_SYNC_TRANSFER == TRUE) -UINT8 btsnd_hcic_ble_set_privacy_mode(UINT8 addr_type, BD_ADDR addr, UINT8 privacy_mode) +BOOLEAN btsnd_hcic_ble_set_privacy_mode(UINT8 addr_type, BD_ADDR addr, UINT8 privacy_mode) { BT_HDR *p; UINT8 *pp; @@ -1933,4 +1933,26 @@ UINT8 btsnd_hcic_ble_set_privacy_mode(UINT8 addr_type, BD_ADDR addr, UINT8 priva btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); return (TRUE); } + +BOOLEAN btsnd_hcic_ble_set_csa_support (UINT8 csa_select) +{ + BT_HDR *p; + UINT8 *pp; + + if ((p = HCI_GET_CMD_BUF (HCIC_PARAM_SIZE_BLE_SET_CSA_SUPPORT)) == NULL) { + return (FALSE); + } + + pp = (UINT8 *)(p + 1); + + p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_BLE_SET_CSA_SUPPORT; + p->offset = 0; + + UINT16_TO_STREAM (pp, HCI_VENDOR_BLE_SET_CSA_SUPPORT); + UINT8_TO_STREAM (pp, HCIC_PARAM_SIZE_BLE_SET_CSA_SUPPORT); + UINT8_TO_STREAM (pp, csa_select); + + btu_hcif_send_cmd (LOCAL_BR_EDR_CONTROLLER_ID, p); + return TRUE; +} #endif diff --git a/components/bt/host/bluedroid/stack/include/stack/btm_ble_api.h b/components/bt/host/bluedroid/stack/include/stack/btm_ble_api.h index 21d783dd2b1..3dc7dc8b331 100644 --- a/components/bt/host/bluedroid/stack/include/stack/btm_ble_api.h +++ b/components/bt/host/bluedroid/stack/include/stack/btm_ble_api.h @@ -1007,6 +1007,7 @@ typedef void (tBTM_START_STOP_ADV_CMPL_CBACK) (UINT8 status); typedef void (tBTM_UPDATE_DUPLICATE_EXCEPTIONAL_LIST_CMPL_CBACK) (tBTM_STATUS status, uint8_t subcode, uint32_t length, uint8_t *device_info); typedef void (tBTM_CLEAR_ADV_CMPL_CBACK) (UINT8 status); typedef void (tBTM_SET_PRIVACY_MODE_CMPL_CBACK) (tBTM_STATUS status); +typedef void (tBTM_SET_CSA_SUPPORT_CMPL_CBACK) (tBTM_STATUS status); #if (BLE_50_FEATURE_SUPPORT == TRUE) #define BTM_BLE_5_GAP_READ_PHY_COMPLETE_EVT 1 @@ -2724,6 +2725,20 @@ BOOLEAN BTM_BleSetPrivacyMode(UINT8 addr_type, UINT8 privacy_mode, tBTM_SET_PRIVACY_MODE_CMPL_CBACK *p_callback); +/******************************************************************************* +** +** Function BTM_BleSetCsaSupport +** +** Description This function is called to set the ChSel field of Advertising or Initiating PDUs +** +** Parameters csa_select - Select LE Channel Selection Algorithm. +** p_callback - Callback function to be called when the operation is completed. +** +** Returns TRUE if the operation was successful, otherwise FALSE. +** +*******************************************************************************/ +BOOLEAN BTM_BleSetCsaSupport (UINT8 csa_select, tBTM_SET_CSA_SUPPORT_CMPL_CBACK *p_callback); + /* #ifdef __cplusplus } diff --git a/components/bt/host/bluedroid/stack/include/stack/hcidefs.h b/components/bt/host/bluedroid/stack/include/stack/hcidefs.h index b77e8854767..0943c624f92 100644 --- a/components/bt/host/bluedroid/stack/include/stack/hcidefs.h +++ b/components/bt/host/bluedroid/stack/include/stack/hcidefs.h @@ -422,6 +422,7 @@ #define HCI_SUBCODE_BLE_ADV_REPORT_FLOW_CONTROL 0x0A #define HCI_SUBCODE_BLE_RD_STATIC_ADDR 0x0B #define HCI_SUBCODE_BLE_CLEAR_ADV 0x0C +#define HCI_SUBCODE_BLE_SET_CSA_SUPPORT 0x12 #define HCI_SUBCODE_BLE_MAX 0x7F //ESP BT subcode define @@ -468,6 +469,8 @@ #define HCI_VENDOR_BLE_ADV_REPORT_FLOW_CONTROL HCI_ESP_VENDOR_OPCODE_BUILD(HCI_VENDOR_OGF, HCI_ESP_GROUP_BLE, HCI_SUBCODE_BLE_ADV_REPORT_FLOW_CONTROL) /* BLE clear legacy advertising */ #define HCI_VENDOR_BLE_CLEAR_ADV HCI_ESP_VENDOR_OPCODE_BUILD(HCI_VENDOR_OGF, HCI_ESP_GROUP_BLE, HCI_SUBCODE_BLE_CLEAR_ADV) +/* BLE set CSA support */ +#define HCI_VENDOR_BLE_SET_CSA_SUPPORT HCI_ESP_VENDOR_OPCODE_BUILD(HCI_VENDOR_OGF, HCI_ESP_GROUP_BLE, HCI_SUBCODE_BLE_SET_CSA_SUPPORT) //ESP BT HCI CMD #define HCI_VENDOR_BT_SET_MIN_ENC_KEY_SIZE HCI_ESP_VENDOR_OPCODE_BUILD(HCI_VENDOR_OGF, HCI_ESP_GROUP_BT, HCI_SUBCODE_BT_SET_MIN_ENC_KEY_SIZE) diff --git a/components/bt/host/bluedroid/stack/include/stack/hcimsgs.h b/components/bt/host/bluedroid/stack/include/stack/hcimsgs.h index 951e5b703a7..252efa72191 100644 --- a/components/bt/host/bluedroid/stack/include/stack/hcimsgs.h +++ b/components/bt/host/bluedroid/stack/include/stack/hcimsgs.h @@ -759,6 +759,7 @@ void btsnd_hcic_vendor_spec_cmd (BT_HDR *buffer, UINT16 opcode, #define HCIC_PARAM_SIZE_BLE_UPDATE_ADV_FLOW_CONTROL 2 #define HCIC_PARAM_SIZE_BLE_CLEAR_ADV 0 #define HCIC_PARAM_SIZE_SET_PRIVACY_MODE 8 +#define HCIC_PARAM_SIZE_BLE_SET_CSA_SUPPORT 1 #if (BLE_50_FEATURE_SUPPORT == TRUE) #define HCIC_PARAM_SIZE_BLE_READ_PHY 2 #define HCIC_PARAM_SIZE_BLE_SET_DEF_PHY 3 @@ -914,7 +915,12 @@ BOOLEAN btsnd_hcic_ble_set_rand_priv_addr_timeout (UINT16 rpa_timout); BOOLEAN btsnd_hcic_ble_clear_adv(void); +BOOLEAN btsnd_hcic_ble_set_privacy_mode(UINT8 addr_type, BD_ADDR addr, UINT8 privacy_mode); + +BOOLEAN btsnd_hcic_ble_set_csa_support (UINT8 csa_select); + #endif /* BLE_INCLUDED */ + #if (BLE_50_FEATURE_SUPPORT == TRUE) typedef struct { UINT8 scan_type; @@ -1042,8 +1048,6 @@ UINT8 btsnd_hcic_ble_write_rf_path_compensation(UINT16 rf_tx_path, UINT16 rf_rx_ #endif // #if (BLE_50_FEATURE_SUPPORT == TRUE) -UINT8 btsnd_hcic_ble_set_privacy_mode(UINT8 addr_type, BD_ADDR addr, UINT8 privacy_mode); - #define HCIC_PARAM_SIZE_WRITE_AUTHENT_PAYLOAD_TOUT 4 #define HCI__WRITE_AUTHENT_PAYLOAD_TOUT_HANDLE_OFF 0 From 8e511ffb4e097a0781ab2e9fd79b5bab2bab9ee8 Mon Sep 17 00:00:00 2001 From: Marius Vikhammer Date: Thu, 17 Oct 2024 17:04:55 +0800 Subject: [PATCH 188/472] fix(hints): added missing seperator between hints --- tools/idf_py_actions/hints.yml | 1 + 1 file changed, 1 insertion(+) diff --git a/tools/idf_py_actions/hints.yml b/tools/idf_py_actions/hints.yml index 20ff00e2c0e..67c57f3a7c6 100644 --- a/tools/idf_py_actions/hints.yml +++ b/tools/idf_py_actions/hints.yml @@ -448,5 +448,6 @@ re: "(error: Total discarded sections size is \\d+ bytes)|(region [`'.\\w]+ overflowed by \\d+ bytes)" hint: "The binary size has exceeded the limit. To resolve the issue consider reducing the binary size.\nYou can explore size optimization techniques in the documentation by running 'idf.py docs -sp api-guides/performance/size.html#reducing-overall-size'.\nNote that the linker performed the dead code elimination." +- re: "implicit declaration of function '__VA_NARG__'" hint: "__VA_NARG_ has been renamed. Please use ESP_VA_NARG instead" From 3df0e6022d600f5ac98782b035c60763c6e31423 Mon Sep 17 00:00:00 2001 From: Zhang Shuxian Date: Wed, 16 Oct 2024 15:45:15 +0800 Subject: [PATCH 189/472] docs: Delete user guide esp32-s2-saola-1, esp32-s3-devkitc-1 and esp32-s3-devkitm-1 --- .../ESP32-S3-DevKitC-1_v1-SystemBlock.png | Bin 66125 -> 0 bytes .../ESP32-S3-DevKitC-1_v1-annotated-photo.png | Bin 334074 -> 0 bytes ...SP32-S3-DevKitC-1_v1.1-annotated-photo.png | Bin 347002 -> 0 bytes .../ESP32-S3-DevKitC-1_v2-SystemBlock.png | Bin 69521 -> 0 bytes .../ESP32-S3-DevKitC-1_v2-annotated-photo.png | Bin 375317 -> 0 bytes .../ESP32-S3-DevKitM-1_v1-annotated-photo.png | Bin 334464 -> 0 bytes .../ESP32-S3-DevKitM-1_v1_SystemBlock.png | Bin 65655 -> 0 bytes docs/_static/ESP32-S3_DevKitC-1_pinlayout.jpg | Bin 340284 -> 0 bytes .../ESP32-S3_DevKitC-1_pinlayout_v1.1.jpg | Bin 461010 -> 0 bytes docs/_static/ESP32-S3_DevKitM-1_pinlayout.jpg | Bin 300954 -> 0 bytes .../esp32-s2-saola-1-v1.2-annotated-photo.png | Bin 305003 -> 0 bytes .../esp32-s2-saola-1-v1.2-block-diags.png | Bin 75801 -> 0 bytes .../esp32-s2-saola-1-v1.2-isometric.png | Bin 161893 -> 0 bytes docs/_static/esp32-s2_saola1-pinout.jpg | Bin 455028 -> 0 bytes .../esp32-s3-devkitc-1-v1-isometric.png | Bin 479204 -> 0 bytes .../esp32-s3-devkitc-1-v1.1-isometric.png | Bin 479294 -> 0 bytes .../esp32-s3-devkitm-1-v1-isometric.png | Bin 481786 -> 0 bytes docs/en/get-started/index.rst | 6 +- .../esp32s2/user-guide-saola-1-v1.2.rst | 262 -------------- .../esp32s3/user-guide-devkitc-1-v1.0.rst | 320 ----------------- .../esp32s3/user-guide-devkitc-1.rst | 329 ------------------ .../esp32s3/user-guide-devkitm-1.rst | 258 -------------- docs/zh_CN/get-started/index.rst | 6 +- .../esp32s2/user-guide-saola-1-v1.2.rst | 262 -------------- .../esp32s3/user-guide-devkitc-1-v1.0.rst | 320 ----------------- .../esp32s3/user-guide-devkitc-1.rst | 329 ------------------ .../esp32s3/user-guide-devkitm-1.rst | 258 -------------- 27 files changed, 6 insertions(+), 2344 deletions(-) delete mode 100644 docs/_static/ESP32-S3-DevKitC-1_v1-SystemBlock.png delete mode 100644 docs/_static/ESP32-S3-DevKitC-1_v1-annotated-photo.png delete mode 100644 docs/_static/ESP32-S3-DevKitC-1_v1.1-annotated-photo.png delete mode 100644 docs/_static/ESP32-S3-DevKitC-1_v2-SystemBlock.png delete mode 100644 docs/_static/ESP32-S3-DevKitC-1_v2-annotated-photo.png delete mode 100644 docs/_static/ESP32-S3-DevKitM-1_v1-annotated-photo.png delete mode 100644 docs/_static/ESP32-S3-DevKitM-1_v1_SystemBlock.png delete mode 100644 docs/_static/ESP32-S3_DevKitC-1_pinlayout.jpg delete mode 100644 docs/_static/ESP32-S3_DevKitC-1_pinlayout_v1.1.jpg delete mode 100644 docs/_static/ESP32-S3_DevKitM-1_pinlayout.jpg delete mode 100644 docs/_static/esp32-s2-saola-1-v1.2-annotated-photo.png delete mode 100644 docs/_static/esp32-s2-saola-1-v1.2-block-diags.png delete mode 100644 docs/_static/esp32-s2-saola-1-v1.2-isometric.png delete mode 100644 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ztjX`z+d##kut*8Bski46OgJgkRxL?yMm5Rp-n@Q~ifNaf`YzEJ8cP?=R!gD9cJ zEGI&DLal2$im@|bswywU^^hKDgf*+^!@k>MM?6C~LN$oY7TU_ad(^syZfitbV)}r4 z$GstKT}-ZsFOffX|C6d=cLNi#k??t+)w5HYCab~i-Xd%u=*gjfaUoET7iIUv3w^h9 zeeAR&xwF&k*pS&14WM)nB2&|ta~lnR#aYRSs$khc0WyaZ7cD%zBD-u+--YZU2NXyD zq{l$#!RpiXZkkMtAYWz3yH8_b;Z_?*aIhllK1mu#c*90{$EivrBJO-DEbnkB;do#^ zQ~32cfZBKxt#6aAf=nkdc_U^-5iIPy1xAj}9YnmvdEEED+4mbGyPE2el#s_nCZs5) zQu#g;-fX5U>Kl^@d;>vaV;z+G+6`|yI}G=u9kFZcw3BM(UB9#)IVZL2K7UXx*$W>?orb4Vj9{kfLcq24%zDr!scINAeT-@i6ybp{FTP; z9_wXonX@i3ypy)8{g_=frHYw!uEF&(*WU1AhyA{r&7eZ&o=>u6a;DbFz{790Kb!fp zpZKVBIwojl`sxNKj=?`&ypoGnFn*)LcqCb9ufll6i9UU`=K(;;1nz!UKmGFgf}N_- zL{|dYJzU3Si1vqr7YR=?N-TtxOHUtm-YexXh#VS5!zos`}0}A-ZPs_-paF# z|I3~X&@28vs+E9GPz|L2J}Olv{5z^X#gNYbzo=3=5S*zRo1fk5{s-_m=InN~+9~kL F{{VK*hEV_j diff --git a/docs/en/get-started/index.rst b/docs/en/get-started/index.rst index 31051267b3c..8b12a0f93cb 100644 --- a/docs/en/get-started/index.rst +++ b/docs/en/get-started/index.rst @@ -108,12 +108,12 @@ If you have one of {IDF_TARGET_NAME} official development boards listed below, y :maxdepth: 1 ESP32-DevKitC + ESP32-DevKitM-1 ESP-WROVER-KIT ESP32-PICO-KIT ESP32-Ethernet-Kit ESP32-PICO-KIT-1 ESP32-PICO-DevKitM-2 - ESP32-DevKitM-1 <../hw-reference/esp32/user-guide-devkitm-1> .. only:: esp32s2 diff --git a/docs/en/hw-reference/esp32/user-guide-devkitm-1.rst b/docs/en/hw-reference/esp32/user-guide-devkitm-1.rst deleted file mode 100644 index e0500316264..00000000000 --- a/docs/en/hw-reference/esp32/user-guide-devkitm-1.rst +++ /dev/null @@ -1,335 +0,0 @@ -=============== -ESP32-DevKitM-1 -=============== - -:link_to_translation:`zh_CN:[中文]` - -This user guide will help you get started with ESP32-DevKitM-1 and will also provide more in-depth information. - -ESP32-DevKitM-1 is an ESP32-MINI-1/1U-based development board produced by Espressif. Most of the I/O pins are broken out to the pin headers on both sides for easy interfacing. Users can either connect peripherals with jumper wires or mount ESP32-DevKitM-1 on a breadboard. - - -+---------------------------+-------------------------------+ -| |ESP32-DevKitM-1 - front| | |ESP32-DevKitM-1 - isometric| | -+---------------------------+-------------------------------+ -| ESP32-DevKitM-1 - front | ESP32-DevKitM-1 - isometric | -+---------------------------+-------------------------------+ - -.. |ESP32-DevKitM-1 - front| image:: ../../../_static/esp32-DevKitM-1-front.png - -.. |ESP32-DevKitM-1 - isometric| image:: ../../../_static/esp32-DevKitM-1-isometric.png - - -The document consists of the following major sections: - -- `Getting started`_: Provides an overview of the ESP32-DevKitM-1 and hardware/software setup instructions to get started. -- `Hardware reference`_: Provides more detailed information about the ESP32-DevKitM-1's hardware. -- `Related Documents`_: Gives links to related documentation. - - -Getting Started -=============== - -This section describes how to get started with ESP32-DevKitM-1. It begins with a few introductory sections about the ESP32-DevKitM-1, then Section `Start Application Development`_ provides instructions on how to do the initial hardware setup and then how to flash firmware onto the ESP32-DevKitM-1. - - -Overview --------- - -This is a small and convenient development board that features: - -- `ESP32-MINI-1, or ESP32-MINI-1U module `_ -- USB-to-serial programming interface that also provides power supply for the board -- pin headers -- pushbuttons for reset and activation of Firmware Download mode -- a few other components - - -Contents and Packaging ----------------------- - -Retail Orders -^^^^^^^^^^^^^ - -If you order a few samples, each ESP32-DevKitM-1 comes in an individual package in either antistatic bag or any packaging depending on your retailer. - -For retail orders, please go to https://www.espressif.com/en/contact-us/get-samples. - - -Wholesale Orders -^^^^^^^^^^^^^^^^ - -If you order in bulk, the boards come in large cardboard boxes. - -For wholesale orders, please go to https://www.espressif.com/en/contact-us/sales-questions. - - -Description of Components -------------------------- - -The following figure and the table below describe the key components, interfaces and controls of the ESP32-DevKitM-1 board. We take the board with a ESP32-MINI-1 module as an example in the following sections. - - -.. figure:: ../../../_static/esp32-devkitm-1-v1-annotated-photo.png - :align: center - :alt: ESP32-DevKitM-1 - front - :figclass: align-center - - ESP32-DevKitM-1 - front - - -.. list-table:: - :widths: 25 75 - :header-rows: 1 - - * - Key Component - - Description - * - On-board module - - ESP32-MINI-1 module or ESP32-MINI-1U module. ESP32-MINI-1 comes with an on-board PCB antenna. ESP32-MINI-1U comes with an external antenna connector. The two modules both have a 4 MB flash in chip package. For details, please see `ESP32-MINI-1 & ESP32-MINI-1U Datasheet `_. - * - 5 V to 3.3 V LDO - - Power regulator converts 5 V to 3.3 V. - * - Boot Button - - Download button. Holding down **Boot** and then pressing **Reset** initiates Firmware Download mode for downloading firmware through the serial port. - * - Reset Button - - Reset Button - * - Micro-USB Port - - USB interface. Power supply for the board as well as the communication interface between a computer and the ESP32 chip. - * - USB-to-UART Bridge - - Single USB-UART bridge chip provides transfer rates up to 3 Mbps. - * - 3.3 V Power On LED - - Turns on when the USB is connected to the board. For details, please see the schematics in `Related Documents`_. - * - I/O Connector - - All available GPIO pins (except for the SPI bus for flash) are broken out to the pin headers on the board. Users can program ESP32 chip to enable multiple functions. - - -Start Application Development ------------------------------ - -Before powering up your ESP32-DevKitM-1, please make sure that it is in good condition with no obvious signs of damage. - - -Required Hardware -^^^^^^^^^^^^^^^^^ - -- ESP32-DevKitM-1 -- USB 2.0 cable (Standard-A to Micro-B) -- Computer running Windows, Linux, or macOS - - -Software Setup -^^^^^^^^^^^^^^ - -Please proceed to :doc:`../../get-started/index`, where Section :ref:`get-started-step-by-step` will quickly help you set up the development environment and then flash an application example onto your ESP32-DevKitM-1. - -.. attention:: - - ESP32-DevKitM-1 boards manufactured before December 2, 2021 have a single core module installed. To verify what module you have, please check module marking information in `PCN-2021-021 `_ . If your board has a single core module installed, please enable single core mode (:ref:`CONFIG_FREERTOS_UNICORE`) in :ref:`menuconfig ` before flashing your applications. - - -Hardware Reference -================== - -Block Diagram -------------- - -A block diagram below shows the components of ESP32-DevKitM-1 and their interconnections. - -.. figure:: ../../../_static/esp32-DevKitM-1_v1_SystemBlock.png - :align: center - :alt: ESP32-DevKitM-1 - :figclass: align-center - - ESP32-DevKitM-1 - - -Power Source Select -------------------- - -There are three mutually exclusive ways to provide power to the board: - -* Micro USB port, default power supply -* 5V and GND header pins -* 3V3 and GND header pins - -.. warning:: - - - The power supply must be provided using **one and only one of the options above**, otherwise the board and/or the power supply source can be damaged. - - Power supply by micro USB port is recommended. - - -Pin Descriptions ----------------- - -The table below provides the Name and Function of pins on both sides of the board. For peripheral pin configurations, please refer to `ESP32 Datasheet`_. - -.. list-table:: - :header-rows: 1 - :widths: 10 12 12 66 - - - * - No. - - Name - - Type [1]_ - - Function - * - 1 - - GND - - P - - Ground - * - 2 - - 3V3 - - P - - 3.3 V power supply - * - 3 - - I36 - - I - - GPIO36, ADC1_CH0, RTC_GPIO0 - * - 4 - - I37 - - I - - GPIO37, ADC1_CH1, RTC_GPIO1 - * - 5 - - I38 - - I - - GPIO38, ADC1_CH2, RTC_GPIO2 - * - 6 - - I39 - - I - - GPIO39, ADC1_CH3, RTC_GPIO3 - * - 7 - - RST - - I - - Reset; High: enable; Low: powers off - * - 8 - - I34 - - I - - GPIO34, ADC1_CH6, RTC_GPIO4 - * - 9 - - I35 - - I - - GPIO35, ADC1_CH7, RTC_GPIO5 - * - 10 - - IO32 - - I/O - - GPIO32, XTAL_32K_P (32.768 kHz crystal oscillator input), ADC1_CH4, TOUCH9, RTC_GPIO9 - * - 11 - - IO33 - - I/O - - GPIO33, XTAL_32K_N (32.768 kHz crystal oscillator output), ADC1_CH5, TOUCH8, RTC_GPIO8 - * - 12 - - IO25 - - I/O - - GPIO25, DAC_1, ADC2_CH8, RTC_GPIO6, EMAC_RXD0 - * - 13 - - IO26 - - I/O - - GPIO26, DAC_2, ADC2_CH9, RTC_GPIO7, EMAC_RXD1 - * - 14 - - IO27 - - I/O - - GPIO27, ADC2_CH7, TOUCH7, RTC_GPIO17, EMAC_RX_DV - * - 15 - - IO14 - - I/O - - GPIO14, ADC2_CH6, TOUCH6, RTC_GPIO16, MTMS, HSPICLK, HS2_CLK, SD_CLK, EMAC_TXD2 - * - 16 - - 5V - - P - - 5 V power supply - * - 17 - - IO12 - - I/O - - GPIO12, ADC2_CH5, TOUCH5, RTC_GPIO15, MTDI [2]_, HSPIQ, HS2_DATA2, SD_DATA2, EMAC_TXD3 - * - 18 - - IO13 - - I/O - - GPIO13, ADC2_CH4, TOUCH4, RTC_GPIO14, MTCK, HSPID, HS2_DATA3, SD_DATA3, EMAC_RX_ER - * - 19 - - IO15 - - I/O - - GPIO15, ADC2_CH3, TOUCH3, RTC_GPIO13, MTDO [2]_, HSPICS0, HS2_CMD, SD_CMD, EMAC_RXD3 - * - 20 - - IO2 - - I/O - - GPIO2 [2]_, ADC2_CH2, TOUCH2, RTC_GPIO12, HSPIWP, HS2_DATA0, SD_DATA0 - * - 21 - - IO0 - - I/O - - GPIO0 [2]_, ADC2_CH1, TOUCH1, RTC_GPIO11, CLK_OUT1, EMAC_TX_CLK - * - 22 - - IO4 - - I/O - - GPIO4, ADC2_CH0, TOUCH0, RTC_GPIO10, HSPIHD, HS2_DATA1, SD_DATA1, EMAC_TX_ER - * - 23 - - IO9 - - I/O - - GPIO9, HS1_DATA2, U1RXD, SD_DATA2 - * - 24 - - IO10 - - I/O - - GPIO10, HS1_DATA3, U1TXD, SD_DATA3 - * - 25 - - IO5 - - I/O - - GPIO5 [2]_, HS1_DATA6, VSPICS0, EMAC_RX_CLK - * - 26 - - IO18 - - I/O - - GPIO18, HS1_DATA7, VSPICLK - * - 27 - - IO23 - - I/O - - GPIO23, HS1_STROBE, VSPID - * - 28 - - IO19 - - I/O - - GPIO19, VSPIQ, U0CTS, EMAC_TXD0 - * - 29 - - IO22 - - I/O - - GPIO22, VSPIWP, U0RTS, EMAC_TXD1 - * - 30 - - IO21 - - I/O - - GPIO21, VSPIHD, EMAC_TX_EN - * - 31 - - TXD0 - - I/O - - GPIO1, U0TXD, CLK_OUT3, EMAC_RXD2 - * - 32 - - RXD0 - - I/O - - GPIO3, U0RXD, CLK_OUT2 - -.. [1] P: Power supply; I: Input; O: Output. -.. [2] MTDI, GPIO0, GPIO2, MTDO, and GPIO5 are strapping pins. These pins are used to control several chip functions depending on binary voltage values applied to the pins during chip power-up or system reset. For description and application of the strapping pins, please refer to `ESP32 Datasheet`_ > Section *Strapping Pins*. - - -Pin Layout -^^^^^^^^^^ - -.. figure:: ../../../_static/ESP32_DevKitM-1_pinlayout.png - :align: center - :scale: 43% - :alt: ESP32-DevKitM-1 (click to enlarge) - :figclass: align-center - - ESP32-DevKitM-1 (click to enlarge) - - -Hardware Revision Details -========================= - -No previous versions available. - - -Related Documents -================= - -* `ESP32-MINI-1 & ESP32-MINI-1U Datasheet `_ (PDF) -* `ESP32-DevKitM-1 Schematics `_ (PDF) -* `ESP32-DevKitM-1 PCB layout `_ (PDF) -* `ESP32-DevKitM-1 layout `_ (DXF) - You can view it with `Autodesk Viewer `_ online -* `ESP32 Datasheet `_ (PDF) -* `ESP Product Selector `_ - -For other design documentation for the board, please contact us at sales@espressif.com. diff --git a/docs/zh_CN/get-started/index.rst b/docs/zh_CN/get-started/index.rst index 76fd2d31309..6e511ff5ad1 100644 --- a/docs/zh_CN/get-started/index.rst +++ b/docs/zh_CN/get-started/index.rst @@ -108,12 +108,12 @@ :maxdepth: 1 ESP32-DevKitC + ESP32-DevKitM-1 ESP-WROVER-KIT ESP32-PICO-KIT ESP32-Ethernet-Kit ESP32-PICO-KIT-1 ESP32-PICO-DevKitM-2 - ESP32-DevKitM-1 <../hw-reference/esp32/user-guide-devkitm-1> .. only:: esp32s2 diff --git a/docs/zh_CN/hw-reference/esp32/user-guide-devkitm-1.rst b/docs/zh_CN/hw-reference/esp32/user-guide-devkitm-1.rst deleted file mode 100644 index f23f4d7c6a5..00000000000 --- a/docs/zh_CN/hw-reference/esp32/user-guide-devkitm-1.rst +++ /dev/null @@ -1,335 +0,0 @@ -=================== -ESP32-DevKitM-1 -=================== - -:link_to_translation:`en: [English]` - -本指南将介绍如何使用 ESP32-DevKitM-1，并提供更多关于此开发板的信息。 - -ESP32-DevKitM-1 是乐鑫推出的一款基于 ESP32-MINI-1/1U 模组的入门级开发板。板上模组大部分管脚均已引出至两侧排针，用户可根据实际需求，通过跳线轻松连接多种外围设备，同时也可将开发板插在面包板上使用。 - - -+------------------------+-------------------------+ -| |ESP32-DevKitM-1-正面| | |ESP32-DevKitM-1-侧面| | -+------------------------+-------------------------+ -| ESP32-DevKitM-1-正面 | ESP32-DevKitM-1-侧面 | -+------------------------+-------------------------+ - -.. |ESP32-DevKitM-1-正面| image:: ../../../_static/esp32-DevKitM-1-front.png - -.. |ESP32-DevKitM-1-侧面| image:: ../../../_static/esp32-DevKitM-1-isometric.png - - -本指南包括： - -- `快速入门`_：提供 ESP32-DevKitM-1 的简要概述及必要的硬件和软件信息。 -- `硬件参考`_：提供 ESP32-DevKitM-1 的详细硬件信息。 -- `相关文档`_：提供相关文档的链接。 - - -快速入门 -=========== - -本节介绍如何开始使用 ESP32-DevKitM-1，主要包括三大部分：首先，介绍一些关于 ESP32-DevKitM-1 的基本信息，然后在 `应用程序开发`_ 章节介绍如何进行硬件初始化，最后介绍如何为 ESP32-DevKitM-1 烧录固件。 - - -概述 -------- - -ESP32-DevKitM-1 开发板是一款小巧实用的开发板，具备以下特色功能： - -- 集成了 `ESP32-MINI-1 或 ESP32-MINI-1U `_ 模组 -- USB 转串口编程接口同时可为开发板供电 -- 设有排针 -- 设有重置按钮和固件下载模式激活按钮 -- 以及其他组件 - - -内含组件和包装 ---------------- - -零售订单 -^^^^^^^^^^^ - -如购买样品，每个 ESP32-DevKitM-1 开发板将以防静电袋或零售商选择的其他方式包装。 - -零售订单请前往 https://www.espressif.com/zh-hans/company/contact/buy-a-sample。 - - -批量订单 -^^^^^^^^^^^ - -如批量购买，ESP32-DevKitM-1 开发板将以大纸板箱包装。 - -批量订单请前往 https://www.espressif.com/zh-hans/contact-us/sales-questions。 - - -组件介绍 ------------ - -ESP32-DevKitM-1 开发板的主要组件、接口及控制方式见下图。下文以板载 ESP32-MINI-1 的开发板为例进行说明。 - - -.. figure:: ../../../_static/esp32-devkitm-1-v1-annotated-photo.png - :align: center - :alt: ESP32-DevKitM-1 - 正面 - :figclass: align-center - - ESP32-DevKitM-1 - 正面 - - -.. list-table:: - :widths: 25 75 - :header-rows: 1 - - * - 主要组件 - - 基本介绍 - * - 板载模组 - - ESP32-MINI-1 模组或 ESP32-MINI-1U 模组。ESP32-MINI-1 带有板载 PCB 天线；ESP32-MINI-1U 带有外部天线连接器。两款模组内置的芯片均叠封 4 MB flash。更多详情，请见 `《ESP32-MINI-1 & ESP32-MINI-1U 技术规格书》 `_ - * - 5 V 转 3.3 V LDO - - 电源转换器，输入 5 V，输出 3.3 V - * - Boot 键 - - 下载按键。按下 **Boot** 键的同时按一下 **Reset** 键进入“固件下载”模式，通过串口下载固件 - * - Reset 键 - - 复位按键 - * - Micro-USB 接口 - - USB 接口，可用作开发板的供电电源或 PC 和 ESP32 芯片的通信接口 - * - USB 至 UART 桥接器 - - 单芯片 USB 至 UART 桥接器，可提供高达 3 Mbps 的传输速率 - * - 3.3 V 电源指示灯 - - 开发板连接 USB 电源后，该指示灯亮起。更多信息，请见 `相关文档`_ 中的原理图 - * - I/O 连接器 - - 所有可用 GPIO 管脚（除 Flash 的 SPI 总线）均已引出至开发板的排针。用户可对 ESP32 芯片编程，开发多种功能 - - -应用程序开发 ---------------- - -ESP32-DevKitM-1 上电前，请首先确认开发板完好无损。 - - -硬件准备 -^^^^^^^^^^^^ - -- ESP32-DevKitM-1 开发板 -- USB A / micro USB B 数据线 -- PC（Windows、Linux 或 macS） - - -软件设置 -^^^^^^^^^^^ - -现在，请前往 :doc:`../../get-started/index` 中的 :ref:`get-started-step-by-step` 章节，查看如何设置开发环境，并尝试将示例项目烧录至你的开发板。 - -.. attention:: - - 对于 2021 年 12 月 2 日之前生产的 ESP32-DevKitM-1，其搭载的模组为单核 MCU 模组。请查看 `PCN-2021-021 `_ 以确定开发板上搭载的模组是否为单核模组。对于搭载单核模组的开发板，烧录应用程序前，需要在 :ref:`menuconfig ` 中启用单核模式 (:ref:`CONFIG_FREERTOS_UNICORE`)。 - - -硬件参考 -=========== - -功能框图 ----------- - -ESP32-DevKitM-1 的主要组件和连接方式如下图所示。 - -.. figure:: ../../../_static/esp32-DevKitM-1_v1_SystemBlock.png - :align: center - :alt: ESP32-DevKitM-1 - :figclass: align-center - - ESP32-DevKitM-1 - - -电源选项 ----------- - -开发板可从以下三种供电方式中任选其一： - -* Micro USB 供电（默认） -* 5V / GND 管脚供电 -* 3V3 / GND 管脚供电 - -.. warning:: - - - 上述供电模式 **不可同时连接**，否则可能会损坏开发板和/或电源。 - - 建议选择第一种供电方式：Micro USB 端口供电。 - - -管脚描述 ----------- - -开发板两侧 I/O 管脚，其具体名称和功能见下表。外设管脚分配请参考 `《ESP32 技术规格书》`_。 - -.. list-table:: - :header-rows: 1 - :widths: 10 12 12 66 - - - * - 编号 - - 名称 - - 类型 [1]_ - - 功能 - * - 1 - - GND - - P - - 接地 - * - 2 - - 3V3 - - P - - 3.3 V 电源 - * - 3 - - I36 - - I - - GPIO36, ADC1_CH0, RTC_GPIO0 - * - 4 - - I37 - - I - - GPIO37, ADC1_CH1, RTC_GPIO1 - * - 5 - - I38 - - I - - GPIO38, ADC1_CH2, RTC_GPIO2 - * - 6 - - I39 - - I - - GPIO39, ADC1_CH3, RTC_GPIO3 - * - 7 - - RST - - I - - 复位；高电平：使能；低电平：关闭 - * - 8 - - I34 - - I - - GPIO34, ADC1_CH6, RTC_GPIO4 - * - 9 - - I35 - - I - - GPIO35, ADC1_CH7, RTC_GPIO5 - * - 10 - - IO32 - - I/O - - GPIO32, XTAL_32K_P (32.768 kHz crystal oscillator input), ADC1_CH4, TOUCH9, RTC_GPIO9 - * - 11 - - IO33 - - I/O - - GPIO33, XTAL_32K_N (32.768 kHz crystal oscillator output), ADC1_CH5, TOUCH8, RTC_GPIO8 - * - 12 - - IO25 - - I/O - - GPIO25, DAC_1, ADC2_CH8, RTC_GPIO6, EMAC_RXD0 - * - 13 - - IO26 - - I/O - - GPIO26, DAC_2, ADC2_CH9, RTC_GPIO7, EMAC_RXD1 - * - 14 - - IO27 - - I/O - - GPIO27, ADC2_CH7, TOUCH7, RTC_GPIO17, EMAC_RX_DV - * - 15 - - IO14 - - I/O - - GPIO14, ADC2_CH6, TOUCH6, RTC_GPIO16, MTMS, HSPICLK, HS2_CLK, SD_CLK, EMAC_TXD2 - * - 16 - - 5V - - P - - 5 V 电源 - * - 17 - - IO12 - - I/O - - GPIO12, ADC2_CH5, TOUCH5, RTC_GPIO15, MTDI [2]_, HSPIQ, HS2_DATA2, SD_DATA2, EMAC_TXD3 - * - 18 - - IO13 - - I/O - - GPIO13, ADC2_CH4, TOUCH4, RTC_GPIO14, MTCK, HSPID, HS2_DATA3, SD_DATA3, EMAC_RX_ER - * - 19 - - IO15 - - I/O - - GPIO15, ADC2_CH3, TOUCH3, RTC_GPIO13, MTDO [2]_, HSPICS0, HS2_CMD, SD_CMD, EMAC_RXD3 - * - 20 - - IO2 - - I/O - - GPIO2 [2]_, ADC2_CH2, TOUCH2, RTC_GPIO12, HSPIWP, HS2_DATA0, SD_DATA0 - * - 21 - - IO0 - - I/O - - GPIO0 [2]_, ADC2_CH1, TOUCH1, RTC_GPIO11, CLK_OUT1, EMAC_TX_CLK - * - 22 - - IO4 - - I/O - - GPIO4, ADC2_CH0, TOUCH0, RTC_GPIO10, HSPIHD, HS2_DATA1, SD_DATA1, EMAC_TX_ER - * - 23 - - IO9 - - I/O - - GPIO9, HS1_DATA2, U1RXD, SD_DATA2 - * - 24 - - IO10 - - I/O - - GPIO10, HS1_DATA3, U1TXD, SD_DATA3 - * - 25 - - IO5 - - I/O - - GPIO5 [2]_, HS1_DATA6, VSPICS0, EMAC_RX_CLK - * - 26 - - IO18 - - I/O - - GPIO18, HS1_DATA7, VSPICLK - * - 27 - - IO23 - - I/O - - GPIO23, HS1_STROBE, VSPID - * - 28 - - IO19 - - I/O - - GPIO19, VSPIQ, U0CTS, EMAC_TXD0 - * - 29 - - IO22 - - I/O - - GPIO22, VSPIWP, U0RTS, EMAC_TXD1 - * - 30 - - IO21 - - I/O - - GPIO21, VSPIHD, EMAC_TX_EN - * - 31 - - TXD0 - - I/O - - GPIO1, U0TXD, CLK_OUT3, EMAC_RXD2 - * - 32 - - RXD0 - - I/O - - GPIO3, U0RXD, CLK_OUT2 - -.. [1] P：电源；I：输入；O：输出。 -.. [2] MTDI、GPIO0、GPIO2、MTDO 和 GPIO5 为 Strapping 管脚。在芯片上电和系统复位过程中，Strapping 管脚根据管脚的二进制电压值控制芯片功能。Strapping 管脚的具体描述和应用，请参考 `《ESP32 技术规格书》`_ > 章节 Strapping 管脚。 - - -管脚布局 -^^^^^^^^ - -.. figure:: ../../../_static/ESP32_DevKitM-1_pinlayout.png - :align: center - :scale: 43% - :alt: ESP32-DevKitM-1 （点击放大） - :figclass: align-center - - ESP32-DevKitM-1 （点击放大） - - -硬件修订历史 -=============== - -尚无版本升级历史。 - - -相关文档 -============ - -* `《ESP32-MINI-1 & ESP32-MINI-1U 技术规格书》 `_ (PDF) -* `ESP32-DevKitM-1 原理图 `_ (PDF) -* `ESP32-DevKitM-1 PCB 布局图 `_ (PDF) -* `ESP32-DevKitM-1 布局图 `_ (DXF) - 可使用 `Autodesk Viewer `_ 查看 -* `乐鑫产品选型工具 `_ -* `《ESP32 技术规格书》 `_ (PDF) - -有关本开发板的更多设计文档，请联系我们的商务部门 sales@espressif.com。 From 024306f4bff86fe88ca7a52aad3349a89c89d190 Mon Sep 17 00:00:00 2001 From: luoxu Date: Tue, 8 Oct 2024 19:15:53 +0800 Subject: [PATCH 054/472] feat(ble_mesh): esp32c5 lib update --- components/bt/esp_ble_mesh/lib/lib | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/components/bt/esp_ble_mesh/lib/lib b/components/bt/esp_ble_mesh/lib/lib index cba99c5a2e7..71d0e43985d 160000 --- a/components/bt/esp_ble_mesh/lib/lib +++ b/components/bt/esp_ble_mesh/lib/lib @@ -1 +1 @@ -Subproject commit cba99c5a2e7f5d4bccb04e8f3f968dc888bb5667 +Subproject commit 71d0e43985db16125de2071a8ec084b06f072544 From 459f2517a8a9291d7d7f1309a09371b743e4e809 Mon Sep 17 00:00:00 2001 From: "sonika.rathi" Date: Tue, 17 Sep 2024 12:43:47 +0200 Subject: [PATCH 055/472] feat(fatfs): enable partition handling for sectors less than 128 --- components/fatfs/fatfsgen.py | 28 ++++--- .../fatfs/host_test/main/test_fatfs.cpp | 11 ++- .../fatfs/host_test/partition_table.csv | 4 +- components/fatfs/src/ff.c | 15 +++- .../test_apps/flash_wl/main/CMakeLists.txt | 2 +- .../main/test_fatfs_small_partition.c | 76 +++++++++++++++++++ .../fatfs/test_apps/flash_wl/partitions.csv | 1 + components/fatfs/vfs/vfs_fat_spiflash.c | 31 ++++++-- .../api-guides/file-system-considerations.rst | 2 +- docs/en/api-reference/storage/fatfs.rst | 24 ++++++ 10 files changed, 167 insertions(+), 27 deletions(-) create mode 100644 components/fatfs/test_apps/flash_wl/main/test_fatfs_small_partition.c diff --git a/components/fatfs/fatfsgen.py b/components/fatfs/fatfsgen.py index 4ab13020015..30d274f5260 100755 --- a/components/fatfs/fatfsgen.py +++ b/components/fatfs/fatfsgen.py @@ -1,10 +1,11 @@ #!/usr/bin/env python # SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD # SPDX-License-Identifier: Apache-2.0 - import os from datetime import datetime -from typing import Any, List, Optional +from typing import Any +from typing import List +from typing import Optional from fatfs_utils.boot_sector import BootSector from fatfs_utils.exceptions import NoFreeClusterException @@ -12,10 +13,16 @@ from fatfs_utils.fatfs_state import FATFSState from fatfs_utils.fs_object import Directory from fatfs_utils.long_filename_utils import get_required_lfn_entries_count -from fatfs_utils.utils import (BYTES_PER_DIRECTORY_ENTRY, FATFS_INCEPTION, FATFS_MIN_ALLOC_UNIT, - RESERVED_CLUSTERS_COUNT, FATDefaults, get_args_for_partition_generator, - get_fat_sectors_count, get_non_data_sectors_cnt, read_filesystem, - required_clusters_count) +from fatfs_utils.utils import BYTES_PER_DIRECTORY_ENTRY +from fatfs_utils.utils import FATDefaults +from fatfs_utils.utils import FATFS_INCEPTION +from fatfs_utils.utils import FATFS_MIN_ALLOC_UNIT +from fatfs_utils.utils import get_args_for_partition_generator +from fatfs_utils.utils import get_fat_sectors_count +from fatfs_utils.utils import get_non_data_sectors_cnt +from fatfs_utils.utils import read_filesystem +from fatfs_utils.utils import required_clusters_count +from fatfs_utils.utils import RESERVED_CLUSTERS_COUNT def duplicate_fat_decorator(func): # type: ignore @@ -48,14 +55,15 @@ def __init__(self, volume_label: str = FATDefaults.VOLUME_LABEL, file_sys_type: str = FATDefaults.FILE_SYS_TYPE, root_entry_count: int = FATDefaults.ROOT_ENTRIES_COUNT, - explicit_fat_type: int = None, + explicit_fat_type: Optional[int] = None, media_type: int = FATDefaults.MEDIA_TYPE) -> None: # root directory bytes should be aligned by sector size - assert (root_entry_count * BYTES_PER_DIRECTORY_ENTRY) % sector_size == 0 + assert (int(root_entry_count) * BYTES_PER_DIRECTORY_ENTRY) % sector_size == 0 # number of bytes in the root dir must be even multiple of BPB_BytsPerSec - assert ((root_entry_count * BYTES_PER_DIRECTORY_ENTRY) // sector_size) % 2 == 0 + if (int(root_entry_count) > 128): + assert ((int(root_entry_count) * BYTES_PER_DIRECTORY_ENTRY) // sector_size) % 2 == 0 - root_dir_sectors_cnt: int = (root_entry_count * BYTES_PER_DIRECTORY_ENTRY) // sector_size + root_dir_sectors_cnt: int = (int(root_entry_count) * BYTES_PER_DIRECTORY_ENTRY) // sector_size self.state: FATFSState = FATFSState(sector_size=sector_size, explicit_fat_type=explicit_fat_type, diff --git a/components/fatfs/host_test/main/test_fatfs.cpp b/components/fatfs/host_test/main/test_fatfs.cpp index a948822eef8..88aa16e1c49 100644 --- a/components/fatfs/host_test/main/test_fatfs.cpp +++ b/components/fatfs/host_test/main/test_fatfs.cpp @@ -44,7 +44,10 @@ TEST_CASE("Create volume, open file, write and read back data", "[fatfs]") fr_result = f_fdisk(pdrv, part_list, work_area); REQUIRE(fr_result == FR_OK); - const MKFS_PARM opt = {(BYTE)FM_ANY, 0, 0, 0, 0}; + + // For host tests, include FM_SFD flag when formatting partitions smaller than 128KB. + // if n_root field of MKFS_PARM is set to 128 => 1 root directory sec and if set to 0(default 512) => 4 root directory sectors. + const MKFS_PARM opt = {(BYTE)(FM_ANY | FM_SFD), 0, 0, 128, 0}; fr_result = f_mkfs("", &opt, work_area, sizeof(work_area)); // Use default volume // Mount the volume @@ -56,7 +59,7 @@ TEST_CASE("Create volume, open file, write and read back data", "[fatfs]") REQUIRE(fr_result == FR_OK); // Generate data - uint32_t data_size = 100000; + uint32_t data_size = 1000; char *data = (char*) malloc(data_size); char *read = (char*) malloc(data_size); @@ -130,7 +133,7 @@ static void prepare_fatfs(const char* partition_label, const esp_partition_t** p fr_result = f_fdisk(_pdrv, part_list, work_area); REQUIRE(fr_result == FR_OK); - const MKFS_PARM opt = {(BYTE)FM_ANY, 0, 0, 0, 0}; + const MKFS_PARM opt = {(BYTE)(FM_ANY | FM_SFD), 0, 0, 128, 0}; fr_result = f_mkfs(drv, &opt, work_area, sizeof(work_area)); // Use default volume REQUIRE(fr_result == FR_OK); } @@ -222,7 +225,7 @@ TEST_CASE("Test mounting 2 volumes, writing data and formatting the 2nd one, rea const size_t workbuf_size = 4096; void *workbuf = ff_memalloc(workbuf_size); REQUIRE(workbuf != NULL); - const MKFS_PARM opt = {(BYTE)(FM_ANY | FM_SFD), 0, 0, 0, CONFIG_WL_SECTOR_SIZE}; + const MKFS_PARM opt = {(BYTE)(FM_ANY | FM_SFD), 0, 0, 128, CONFIG_WL_SECTOR_SIZE}; fr_result = f_mkfs(drv1, &opt, workbuf, workbuf_size); free(workbuf); workbuf = NULL; diff --git a/components/fatfs/host_test/partition_table.csv b/components/fatfs/host_test/partition_table.csv index 30d2d909258..777a3e67e9f 100644 --- a/components/fatfs/host_test/partition_table.csv +++ b/components/fatfs/host_test/partition_table.csv @@ -3,5 +3,5 @@ nvs, data, nvs, 0x9000, 0x6000, phy_init, data, phy, 0xf000, 0x1000, factory, app, factory, 0x10000, 1M, -storage, data, fat, , 1M, -storage2, data, fat, , 1M, +storage, data, fat, , 32k, +storage2, data, fat, , 32k, diff --git a/components/fatfs/src/ff.c b/components/fatfs/src/ff.c index 49b8d89620f..3c3f1ace61d 100644 --- a/components/fatfs/src/ff.c +++ b/components/fatfs/src/ff.c @@ -34,7 +34,6 @@ #error Wrong include file (ff.h). #endif - /* Limits and boundaries */ #define MAX_DIR 0x200000 /* Max size of FAT directory */ #define MAX_DIR_EX 0x10000000 /* Max size of exFAT directory */ @@ -43,6 +42,10 @@ #define MAX_FAT32 0x0FFFFFF5 /* Max FAT32 clusters (not specified, practical limit) */ #define MAX_EXFAT 0x7FFFFFFD /* Max exFAT clusters (differs from specs, implementation limit) */ +#define MIN_FAT12_SEC_VOL 4 /* Min size of the FAT sector volume + 1 FAT, 1 root dir, 1 reserved, 1 data sector */ +#define MIN_FAT12_DATA_SEC 1 /* Min FAT data sectors */ + /* Character code support macros */ #define IsUpper(c) ((c) >= 'A' && (c) <= 'Z') @@ -3318,7 +3321,7 @@ static UINT check_fs ( /* 0:FAT/FAT32 VBR, 1:exFAT VBR, 2:Not FAT and valid BS, && ld_word(fs->win + BPB_RsvdSecCnt) != 0 /* Properness of reserved sectors (MNBZ) */ && (UINT)fs->win[BPB_NumFATs] - 1 <= 1 /* Properness of FATs (1 or 2) */ && ld_word(fs->win + BPB_RootEntCnt) != 0 /* Properness of root dir entries (MNBZ) */ - && (ld_word(fs->win + BPB_TotSec16) >= 128 || ld_dword(fs->win + BPB_TotSec32) >= 0x10000) /* Properness of volume sectors (>=128) */ + && (ld_word(fs->win + BPB_TotSec16) >= MIN_FAT12_SEC_VOL || ld_dword(fs->win + BPB_TotSec32) >= 0x10000) /* Properness of volume sectors (>=MIN_FAT12_SEC_VOL) */ && ld_word(fs->win + BPB_FATSz16) != 0) { /* Properness of FAT size (MNBZ) */ return 0; /* It can be presumed an FAT VBR */ } @@ -6034,7 +6037,11 @@ FRESULT f_mkfs ( } } } - if (sz_vol < 128) LEAVE_MKFS(FR_MKFS_ABORTED); /* Check if volume size is >=128s */ + if (n_fat == 1) { + if (sz_vol < MIN_FAT12_SEC_VOL) LEAVE_MKFS(FR_MKFS_ABORTED); /* Check if volume size is >= MIN_FAT12_SEC_VOLs */ + } else { + if (sz_vol < (MIN_FAT12_SEC_VOL + 1)) LEAVE_MKFS(FR_MKFS_ABORTED); /* Check if volume size is >= (MIN_FAT12_SEC_VOL+1)s */ + } /* Now start to create an FAT volume at b_vol and sz_vol */ @@ -6265,7 +6272,7 @@ FRESULT f_mkfs ( } /* Determine number of clusters and final check of validity of the FAT sub-type */ - if (sz_vol < b_data + pau * 16 - b_vol) LEAVE_MKFS(FR_MKFS_ABORTED); /* Too small volume? */ + if (sz_vol < b_data + pau * MIN_FAT12_DATA_SEC - b_vol) LEAVE_MKFS(FR_MKFS_ABORTED); /* Too small volume? */ n_clst = ((DWORD)sz_vol - sz_rsv - sz_fat * n_fat - sz_dir) / pau; if (fsty == FS_FAT32) { if (n_clst <= MAX_FAT16) { /* Too few clusters for FAT32? */ diff --git a/components/fatfs/test_apps/flash_wl/main/CMakeLists.txt b/components/fatfs/test_apps/flash_wl/main/CMakeLists.txt index 20b600fca29..f6501bda48f 100644 --- a/components/fatfs/test_apps/flash_wl/main/CMakeLists.txt +++ b/components/fatfs/test_apps/flash_wl/main/CMakeLists.txt @@ -1,4 +1,4 @@ -idf_component_register(SRCS "test_fatfs_flash_wl.c" +idf_component_register(SRCS "test_fatfs_flash_wl.c" "test_fatfs_small_partition.c" INCLUDE_DIRS "." PRIV_REQUIRES unity spi_flash fatfs vfs test_fatfs_common WHOLE_ARCHIVE) diff --git a/components/fatfs/test_apps/flash_wl/main/test_fatfs_small_partition.c b/components/fatfs/test_apps/flash_wl/main/test_fatfs_small_partition.c new file mode 100644 index 00000000000..fd65a4db811 --- /dev/null +++ b/components/fatfs/test_apps/flash_wl/main/test_fatfs_small_partition.c @@ -0,0 +1,76 @@ +/* + * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include +#include "unity.h" +#include "esp_vfs_fat.h" + +static wl_handle_t s_test_wl_handle; +static void test_setup(void) +{ + // With this configuration, for 32k partition size, + // 4 sectors will be used for WL and 4 sectors for FATFS + // (1 FAT, 1 root directory, 1 reserved and 1 data sector) + esp_vfs_fat_mount_config_t mount_config = { + .format_if_mount_failed = true, + .max_files = 5, + .use_one_fat = true, + }; + + TEST_ESP_OK(esp_vfs_fat_spiflash_format_cfg_rw_wl("/spiflash", "storage1", &mount_config)); + TEST_ESP_OK(esp_vfs_fat_spiflash_mount_rw_wl("/spiflash", "storage1", &mount_config, &s_test_wl_handle)); +} + +static void test_teardown(void) +{ + TEST_ESP_OK(esp_vfs_fat_spiflash_unmount_rw_wl("/spiflash", s_test_wl_handle)); +} + +static void test_write_data_sec(int num_data_sec) +{ + int fd = open("/spiflash/test.txt", O_CREAT | O_WRONLY); + TEST_ASSERT_NOT_EQUAL(-1, fd); + + // Generate data + uint32_t data_size = 4096*num_data_sec; + + char *data = (char*) malloc(data_size); + char *read_data = (char*) malloc(data_size); + + for(uint32_t i = 0; i < (data_size); i += sizeof(i)) + { + *((uint32_t*)(data + i)) = i; + } + ssize_t wr = write(fd, data, data_size); + if (num_data_sec == 1) { + TEST_ASSERT_EQUAL(data_size, wr); + } else { + TEST_ASSERT_NOT_EQUAL(data_size, wr); + } + TEST_ASSERT_EQUAL(0, close(fd)); + + fd = open("/spiflash/test.txt", O_RDONLY); + int r = read(fd, read_data, data_size); + if (num_data_sec == 1) { + TEST_ASSERT_EQUAL(data_size, r); + } else { + TEST_ASSERT_NOT_EQUAL(data_size, r); + } + TEST_ASSERT_EQUAL(0, strcmp(data, read_data)); + TEST_ASSERT_EQUAL(0, close(fd)); +} + +TEST_CASE("(WL) can format small partition and read-write data", "[fatfs][wear_levelling][timeout=120]") +{ + test_setup(); + test_write_data_sec(1); //for 1 data sectors, write and read func should work + test_write_data_sec(2); //for 2 data sectors, write and read func should fail + test_teardown(); +} diff --git a/components/fatfs/test_apps/flash_wl/partitions.csv b/components/fatfs/test_apps/flash_wl/partitions.csv index d1dcbae61db..d68a9de0115 100644 --- a/components/fatfs/test_apps/flash_wl/partitions.csv +++ b/components/fatfs/test_apps/flash_wl/partitions.csv @@ -2,3 +2,4 @@ factory, app, factory, 0x10000, 768k, storage, data, fat, , 528k, storage2, data, fat, , 528k, +storage1, data, fat, , 32k, diff --git a/components/fatfs/vfs/vfs_fat_spiflash.c b/components/fatfs/vfs/vfs_fat_spiflash.c index dffd7ec1bb8..7144f165f6a 100644 --- a/components/fatfs/vfs/vfs_fat_spiflash.c +++ b/components/fatfs/vfs/vfs_fat_spiflash.c @@ -15,6 +15,10 @@ #include "wear_levelling.h" #include "diskio_wl.h" +// If the available sectors based on partition size are less than 128, +// the root directory sector should be set to 1. +#define MIN_REQ_SEC 128 + static const char* TAG = "vfs_fat_spiflash"; static vfs_fat_spiflash_ctx_t *s_ctx[FF_VOLUMES] = {}; @@ -74,7 +78,7 @@ vfs_fat_spiflash_ctx_t* get_vfs_fat_spiflash_ctx(wl_handle_t wlhandle) return NULL; } -static esp_err_t s_f_mount_rw(FATFS *fs, const char *drv, const esp_vfs_fat_mount_config_t *mount_config, vfs_fat_x_ctx_flags_t *out_flags) +static esp_err_t s_f_mount_rw(FATFS *fs, const char *drv, const esp_vfs_fat_mount_config_t *mount_config, vfs_fat_x_ctx_flags_t *out_flags, size_t sec_num) { FRESULT fresult = f_mount(fs, drv, 1); if (fresult != FR_OK) { @@ -93,7 +97,13 @@ static esp_err_t s_f_mount_rw(FATFS *fs, const char *drv, const esp_vfs_fat_moun size_t alloc_unit_size = esp_vfs_fat_get_allocation_unit_size(CONFIG_WL_SECTOR_SIZE, mount_config->allocation_unit_size); ESP_LOGI(TAG, "Formatting FATFS partition, allocation unit size=%d", alloc_unit_size); - const MKFS_PARM opt = {(BYTE)(FM_ANY | FM_SFD), (mount_config->use_one_fat ? 1 : 2), 0, 0, alloc_unit_size}; + UINT root_dir_entries; + if (CONFIG_WL_SECTOR_SIZE == 512) { + root_dir_entries = 16; + } else { + root_dir_entries = 128; + } + const MKFS_PARM opt = {(BYTE)(FM_ANY | FM_SFD), (mount_config->use_one_fat ? 1 : 2), 0, (sec_num <= MIN_REQ_SEC ? root_dir_entries : 0), alloc_unit_size}; fresult = f_mkfs(drv, &opt, workbuf, workbuf_size); free(workbuf); workbuf = NULL; @@ -157,8 +167,9 @@ esp_err_t esp_vfs_fat_spiflash_mount_rw_wl(const char* base_path, vfs_fat_x_ctx_flags_t flags = 0; + size_t sec_num = wl_size(*wl_handle) / wl_sector_size(*wl_handle); // Try to mount partition - ret = s_f_mount_rw(fs, drv, mount_config, &flags); + ret = s_f_mount_rw(fs, drv, mount_config, &flags, sec_num); if (ret != ESP_OK) { goto fail; } @@ -224,6 +235,7 @@ esp_err_t esp_vfs_fat_spiflash_format_cfg_rw_wl(const char* base_path, const cha wl_handle_t temp_handle = WL_INVALID_HANDLE; uint32_t id = FF_VOLUMES; + size_t sec_num = 0; bool found = s_get_context_id_by_label(partition_label, &id); if (!found) { @@ -239,6 +251,7 @@ esp_err_t esp_vfs_fat_spiflash_format_cfg_rw_wl(const char* base_path, const cha } ESP_RETURN_ON_ERROR(esp_vfs_fat_spiflash_mount_rw_wl(base_path, partition_label, mount_cfg, &temp_handle), TAG, "Failed to mount"); found = s_get_context_id_by_label(partition_label, &id); + sec_num = wl_size(temp_handle) / wl_sector_size(temp_handle); assert(found); if (s_ctx[id]->flags & FORMATTED_DURING_LAST_MOUNT) { ESP_LOGD(TAG, "partition was formatted during mounting, skipping another format"); @@ -250,6 +263,8 @@ esp_err_t esp_vfs_fat_spiflash_format_cfg_rw_wl(const char* base_path, const cha if (cfg) { s_ctx[id]->mount_config = *cfg; } + temp_handle = s_ctx[id]->wlhandle; + sec_num = wl_size(temp_handle) / wl_sector_size(temp_handle); } //unmount @@ -266,7 +281,13 @@ esp_err_t esp_vfs_fat_spiflash_format_cfg_rw_wl(const char* base_path, const cha } size_t alloc_unit_size = esp_vfs_fat_get_allocation_unit_size(CONFIG_WL_SECTOR_SIZE, s_ctx[id]->mount_config.allocation_unit_size); ESP_LOGI(TAG, "Formatting FATFS partition, allocation unit size=%d", alloc_unit_size); - const MKFS_PARM opt = {(BYTE)(FM_ANY | FM_SFD), (s_ctx[id]->mount_config.use_one_fat ? 1 : 2), 0, 0, alloc_unit_size}; + UINT root_dir_entries; + if (CONFIG_WL_SECTOR_SIZE == 512) { + root_dir_entries = 16; + } else { + root_dir_entries = 128; + } + const MKFS_PARM opt = {(BYTE)(FM_ANY | FM_SFD), (s_ctx[id]->mount_config.use_one_fat ? 1 : 2), 0, (sec_num <= MIN_REQ_SEC ? root_dir_entries : 0), alloc_unit_size}; fresult = f_mkfs(drv, &opt, workbuf, workbuf_size); free(workbuf); workbuf = NULL; @@ -274,7 +295,7 @@ esp_err_t esp_vfs_fat_spiflash_format_cfg_rw_wl(const char* base_path, const cha mount_back: if (partition_was_mounted) { - esp_err_t err = s_f_mount_rw(s_ctx[id]->fs, drv, &s_ctx[id]->mount_config, NULL); + esp_err_t err = s_f_mount_rw(s_ctx[id]->fs, drv, &s_ctx[id]->mount_config, NULL, sec_num); if (err != ESP_OK) { ESP_LOGE(TAG, "failed to mount back, go to recycle"); goto recycle; diff --git a/docs/en/api-guides/file-system-considerations.rst b/docs/en/api-guides/file-system-considerations.rst index a57ab01c878..ac90b678320 100644 --- a/docs/en/api-guides/file-system-considerations.rst +++ b/docs/en/api-guides/file-system-considerations.rst @@ -50,7 +50,7 @@ The most significant properties and features of above-mentioned file systems are - Integrated - Integrated * - Minimum partition size - - * 128 sectors With wear levelling on (WL sector=4096B): + - * 8 sectors with wear levelling on (4 FATFS sectors + 4 WL sectors with WL sector size=4096B) * plus 4 sectors at least * real number given by WL configuration (Safe, Perf) - * 6 logical blocks diff --git a/docs/en/api-reference/storage/fatfs.rst b/docs/en/api-reference/storage/fatfs.rst index f45007607ce..3777c4f17ca 100644 --- a/docs/en/api-reference/storage/fatfs.rst +++ b/docs/en/api-reference/storage/fatfs.rst @@ -157,6 +157,30 @@ Usage:: Parameter --verbose prints detailed information from boot sector of the FatFs image to the terminal before folder structure is generated. +FATFS Minimum Partition Size and Limits +--------------------------------------- + +The FATFS component supports FAT12, FAT16, and FAT32 file system types. The file system type is determined by the number of clusters (calculated as data sectors divided by sectors per cluster) on the volume. The minimum partition size is defined by the number of sectors allocated to FAT tables, root directories and data clusters. + +* The minimum supported size for a FAT partition with wear leveling enabled is 32 KB for a sector size of 4096 bytes. For a sector size of 512 bytes, the minimum partition size varies based on the WL configuration: 20 KB for Performance mode and 28 KB for Safety mode (requiring 2 extra sectors). +* For a partition with wear leveling enabled, 4 sectors will be reserved for wear-leveling operations, and 4 sectors will be used by the FATFS (1 reserved sector, 1 FAT sector, 1 root directory sector and 1 data sector). +* Increasing the partition size will allocate additional data sectors, allowing for more storage space. +* For partition sizes less than 528 KB, 1 root directory sector will be allocated; for larger partitions, 4 root directory sectors will be used. +* By default, two FAT sectors are created, increasing the partition size by one sector to accommodate the extra FAT sector. To enable a single FAT sector, configure the `use_one_fat` option in `struct esp_vfs_fat_mount_config_t` (see/vfs/esp_vfs_fat.h). Enabling this option allows the minimum partition size to be reduced to 32 KB. +* The general formula for calculating the partition size for a wear-leveled partition is:: + + partition_size = Wear-levelling sectors * FLASH_SEC_SIZE + FATFS partition sectors * FAT_SEC_SIZE + + Where, + - Wear-leveling sectors are fixed at 4, + - FLASH_SEC_SIZE is 4096 bytes, + - FATFS partition sectors include: 1 reserved sector + FAT sectors + root directory sectors + data sectors, + - FAT_SEC_SIZE can be either 512 bytes or 4096 bytes, depending on the configuration. + +* For read-only partitions without wear leveling enabled and a sector size of 512 bytes, the minimum partition size can be reduced to as low as 2 KB. + +Please refer :doc:`File System Considerations <../../api-guides/file-system-considerations>` for further details . + High-level API Reference ------------------------ From c0fe2acd1d8d08da341280db36b215399580e746 Mon Sep 17 00:00:00 2001 From: Yuan Hong Hui Date: Thu, 19 Sep 2024 14:07:03 +0800 Subject: [PATCH 056/472] feat(ble): added pytest for ble example --- examples/bluetooth/.build-test-rules.yml | 49 +++- .../sdkconfig.ci.esp32c2_xtal26m_receiver | 3 + .../sdkconfig.ci.esp32c2_xtal26m_sender | 3 + .../ble/ble_ibeacon/sdkconfig.ci.receiver | 1 + .../ble/ble_ibeacon/sdkconfig.ci.sender | 1 + .../pytest_ble_throughput_test.py | 162 +++++++++++ .../sdkconfig.ci.esp32c2_xtal26m_notify | 7 + .../sdkconfig.ci.esp32c2_xtal26m_write | 6 + .../throughput_client/sdkconfig.ci.notify | 4 + .../throughput_client/sdkconfig.ci.write | 4 + .../sdkconfig.ci.esp32c2_xtal26m_notify | 7 + .../sdkconfig.ci.esp32c2_xtal26m_write | 6 + .../throughput_server/sdkconfig.ci.notify | 4 + .../throughput_server/sdkconfig.ci.write | 4 + .../gatt_client/sdkconfig.ci.esp32c2_xtal26m | 5 + .../ble/gatt_client/sdkconfig.ci.name | 2 + .../gatt_client/sdkconfig.defaults.esp32c2 | 4 + .../sdkconfig.ci.esp32c2_xtal26m | 4 + .../gatt_security_client/sdkconfig.ci.name | 3 + .../sdkconfig.ci.esp32c2_xtal26m | 4 + .../gatt_security_server/sdkconfig.ci.name | 3 + .../gatt_server/sdkconfig.ci.esp32c2_xtal26m | 4 + .../ble/gatt_server/sdkconfig.ci.name | 3 + .../gatt_server/sdkconfig.defaults.esp32c2 | 3 + .../bluedroid/ble/pytest_ble_test.py | 265 ++++++++++++++++++ .../sdkconfig.ci.esp32c2_xtal26m | 4 + .../ble50_security_client/sdkconfig.ci.name | 2 + .../sdkconfig.ci.esp32c2_xtal26m | 4 + .../ble50_security_server/sdkconfig.ci.name | 2 + .../periodic_adv/sdkconfig.ci.esp32c2_xtal26m | 4 + .../ble_50/periodic_adv/sdkconfig.ci.name | 2 + .../sdkconfig.ci.esp32c2_xtal26m | 4 + .../ble_50/periodic_sync/sdkconfig.ci.name | 2 + .../bluedroid/ble_50/pytest_ble50_test.py | 143 ++++++++++ 34 files changed, 727 insertions(+), 1 deletion(-) create mode 100644 examples/bluetooth/bluedroid/ble/ble_ibeacon/sdkconfig.ci.esp32c2_xtal26m_receiver create mode 100644 examples/bluetooth/bluedroid/ble/ble_ibeacon/sdkconfig.ci.esp32c2_xtal26m_sender create mode 100644 examples/bluetooth/bluedroid/ble/ble_ibeacon/sdkconfig.ci.receiver create mode 100644 examples/bluetooth/bluedroid/ble/ble_ibeacon/sdkconfig.ci.sender create mode 100644 examples/bluetooth/bluedroid/ble/ble_throughput/pytest_ble_throughput_test.py create mode 100644 examples/bluetooth/bluedroid/ble/ble_throughput/throughput_client/sdkconfig.ci.esp32c2_xtal26m_notify create mode 100644 examples/bluetooth/bluedroid/ble/ble_throughput/throughput_client/sdkconfig.ci.esp32c2_xtal26m_write create mode 100644 examples/bluetooth/bluedroid/ble/ble_throughput/throughput_client/sdkconfig.ci.notify create mode 100644 examples/bluetooth/bluedroid/ble/ble_throughput/throughput_client/sdkconfig.ci.write create mode 100644 examples/bluetooth/bluedroid/ble/ble_throughput/throughput_server/sdkconfig.ci.esp32c2_xtal26m_notify create mode 100644 examples/bluetooth/bluedroid/ble/ble_throughput/throughput_server/sdkconfig.ci.esp32c2_xtal26m_write create mode 100644 examples/bluetooth/bluedroid/ble/ble_throughput/throughput_server/sdkconfig.ci.notify create mode 100644 examples/bluetooth/bluedroid/ble/ble_throughput/throughput_server/sdkconfig.ci.write create mode 100644 examples/bluetooth/bluedroid/ble/gatt_client/sdkconfig.ci.esp32c2_xtal26m create mode 100644 examples/bluetooth/bluedroid/ble/gatt_client/sdkconfig.ci.name create mode 100644 examples/bluetooth/bluedroid/ble/gatt_security_client/sdkconfig.ci.esp32c2_xtal26m create mode 100644 examples/bluetooth/bluedroid/ble/gatt_security_client/sdkconfig.ci.name create mode 100644 examples/bluetooth/bluedroid/ble/gatt_security_server/sdkconfig.ci.esp32c2_xtal26m create mode 100644 examples/bluetooth/bluedroid/ble/gatt_security_server/sdkconfig.ci.name create mode 100644 examples/bluetooth/bluedroid/ble/gatt_server/sdkconfig.ci.esp32c2_xtal26m create mode 100644 examples/bluetooth/bluedroid/ble/gatt_server/sdkconfig.ci.name create mode 100644 examples/bluetooth/bluedroid/ble/pytest_ble_test.py create mode 100644 examples/bluetooth/bluedroid/ble_50/ble50_security_client/sdkconfig.ci.esp32c2_xtal26m create mode 100644 examples/bluetooth/bluedroid/ble_50/ble50_security_client/sdkconfig.ci.name create mode 100644 examples/bluetooth/bluedroid/ble_50/ble50_security_server/sdkconfig.ci.esp32c2_xtal26m create mode 100644 examples/bluetooth/bluedroid/ble_50/ble50_security_server/sdkconfig.ci.name create mode 100644 examples/bluetooth/bluedroid/ble_50/periodic_adv/sdkconfig.ci.esp32c2_xtal26m create mode 100644 examples/bluetooth/bluedroid/ble_50/periodic_adv/sdkconfig.ci.name create mode 100644 examples/bluetooth/bluedroid/ble_50/periodic_sync/sdkconfig.ci.esp32c2_xtal26m create mode 100644 examples/bluetooth/bluedroid/ble_50/periodic_sync/sdkconfig.ci.name create mode 100644 examples/bluetooth/bluedroid/ble_50/pytest_ble50_test.py diff --git a/examples/bluetooth/.build-test-rules.yml b/examples/bluetooth/.build-test-rules.yml index 2033d2a278a..20f2345ef9b 100644 --- a/examples/bluetooth/.build-test-rules.yml +++ b/examples/bluetooth/.build-test-rules.yml @@ -19,7 +19,20 @@ examples/bluetooth/bluedroid/ble: <<: *bt_default_depends disable: - if: SOC_BT_SUPPORTED != 1 - + depends_components: + - bt + - esp_phy + - nvs_flash + - esp_coex + - esp_log + - esp_console + - mbedtls + - vfs + - esp_driver_gpio + - esp_driver_i2s + - esp_driver_uart + depends_filepatterns: + - examples/bluetooth/bluedroid/ble/pytest_ble_test.py examples/bluetooth/bluedroid/ble/ble_hid_device_demo: disable: @@ -27,9 +40,43 @@ examples/bluetooth/bluedroid/ble/ble_hid_device_demo: depends_components: - esp_driver_gpio +examples/bluetooth/bluedroid/ble/ble_throughput: + <<: *bt_default_depends + disable: + - if: SOC_BT_SUPPORTED != 1 + depends_components: + - bt + - esp_phy + - nvs_flash + - esp_coex + - esp_log + - esp_console + - mbedtls + - vfs + - esp_driver_gpio + - esp_driver_i2s + - esp_driver_uart + depends_filepatterns: + - examples/bluetooth/bluedroid/ble_50/pytest_ble_throughput_test.py + examples/bluetooth/bluedroid/ble_50: + <<: *bt_default_depends disable: - if: SOC_BLE_50_SUPPORTED != 1 + depends_components: + - bt + - esp_phy + - nvs_flash + - esp_coex + - esp_log + - esp_console + - mbedtls + - vfs + - esp_driver_gpio + - esp_driver_i2s + - esp_driver_uart + depends_filepatterns: + - examples/bluetooth/bluedroid/ble_50/pytest_ble50_test.py examples/bluetooth/bluedroid/classic_bt: disable: diff --git a/examples/bluetooth/bluedroid/ble/ble_ibeacon/sdkconfig.ci.esp32c2_xtal26m_receiver b/examples/bluetooth/bluedroid/ble/ble_ibeacon/sdkconfig.ci.esp32c2_xtal26m_receiver new file mode 100644 index 00000000000..9c392443402 --- /dev/null +++ b/examples/bluetooth/bluedroid/ble/ble_ibeacon/sdkconfig.ci.esp32c2_xtal26m_receiver @@ -0,0 +1,3 @@ +CONFIG_IDF_TARGET="esp32c2" +CONFIG_XTAL_FREQ_26=y +CONFIG_IBEACON_RECEIVER=y diff --git a/examples/bluetooth/bluedroid/ble/ble_ibeacon/sdkconfig.ci.esp32c2_xtal26m_sender b/examples/bluetooth/bluedroid/ble/ble_ibeacon/sdkconfig.ci.esp32c2_xtal26m_sender new file mode 100644 index 00000000000..420137b8bac --- /dev/null +++ b/examples/bluetooth/bluedroid/ble/ble_ibeacon/sdkconfig.ci.esp32c2_xtal26m_sender @@ -0,0 +1,3 @@ +CONFIG_IDF_TARGET="esp32c2" +CONFIG_XTAL_FREQ_26=y +CONFIG_IBEACON_SENDER=y diff --git a/examples/bluetooth/bluedroid/ble/ble_ibeacon/sdkconfig.ci.receiver b/examples/bluetooth/bluedroid/ble/ble_ibeacon/sdkconfig.ci.receiver new file mode 100644 index 00000000000..b78485c510f --- /dev/null +++ b/examples/bluetooth/bluedroid/ble/ble_ibeacon/sdkconfig.ci.receiver @@ -0,0 +1 @@ +CONFIG_IBEACON_RECEIVER=y diff --git a/examples/bluetooth/bluedroid/ble/ble_ibeacon/sdkconfig.ci.sender b/examples/bluetooth/bluedroid/ble/ble_ibeacon/sdkconfig.ci.sender new file mode 100644 index 00000000000..d463a13eaf4 --- /dev/null +++ b/examples/bluetooth/bluedroid/ble/ble_ibeacon/sdkconfig.ci.sender @@ -0,0 +1 @@ +CONFIG_IBEACON_SENDER=y diff --git a/examples/bluetooth/bluedroid/ble/ble_throughput/pytest_ble_throughput_test.py b/examples/bluetooth/bluedroid/ble/ble_throughput/pytest_ble_throughput_test.py new file mode 100644 index 00000000000..f7194312ec8 --- /dev/null +++ b/examples/bluetooth/bluedroid/ble/ble_throughput/pytest_ble_throughput_test.py @@ -0,0 +1,162 @@ +# SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD +# SPDX-License-Identifier: CC0-1.0 +import os.path +import time +from typing import Tuple + +import pytest +from pytest_embedded_idf.dut import IdfDut + + +# Case 1: gatt write throughput test +@pytest.mark.esp32 +@pytest.mark.esp32c3 +@pytest.mark.esp32c6 +@pytest.mark.esp32c61 +@pytest.mark.esp32c5 +@pytest.mark.esp32h2 +@pytest.mark.esp32s3 +@pytest.mark.wifi_two_dut +@pytest.mark.parametrize( + 'count, app_path, config, erase_all', [ + (2, + f'{os.path.join(os.path.dirname(__file__), "throughput_server")}|{os.path.join(os.path.dirname(__file__), "throughput_client")}', + 'write', 'y'), + ], + indirect=True, +) +def test_gatt_write_throughput(app_path: str, dut: Tuple[IdfDut, IdfDut]) -> None: + server = dut[0] + client = dut[1] + client_addr = client.expect(r'Bluetooth MAC: (([0-9a-fA-F]{2}:){5}[0-9a-fA-F]{2})', timeout=30).group(1).decode('utf8') + server_addr = server.expect(r'Bluetooth MAC: (([0-9a-fA-F]{2}:){5}[0-9a-fA-F]{2})', timeout=30).group(1).decode('utf8') + + client.expect_exact('GATT client register, status 0', timeout=30) + server.expect_exact('GATT server register, status 0', timeout=30) + server.expect_exact('Advertising start successfully', timeout=30) + client.expect_exact('Scanning start successfully', timeout=30) + client.expect_exact('Device found ', timeout=30) + server.expect_exact('Service start, status 0', timeout=30) + server.expect_exact(f'Connected, conn_id 0, remote {client_addr}', timeout=30) + client.expect_exact(f'Connected, conn_id 0, remote {server_addr}', timeout=30) + client.expect_exact('MTU exchange, status 0, MTU 517', timeout=30) + server.expect_exact('MTU exchange, MTU 517', timeout=30) + client.expect_exact('Service search complete', timeout=30) + start_time = time.time() + while time.time() - start_time < 30: + throughput = int(server.expect(r'GATTC write Bit rate = (\d+) Byte/s', timeout=30).group(1).decode('utf8')) + assert throughput > 50000 or throughput < 95000 + + +# Case 2: gatt write throughput test for ESP32C2 26mhz xtal +@pytest.mark.esp32c2 +@pytest.mark.wifi_two_dut +@pytest.mark.xtal_26mhz +@pytest.mark.parametrize( + 'count, target, baud, app_path, config, erase_all', [ + (2, 'esp32c2|esp32c2', '74880', + f'{os.path.join(os.path.dirname(__file__), "throughput_server")}|{os.path.join(os.path.dirname(__file__), "throughput_client")}', + 'esp32c2_xtal26m_write', 'y'), + ], + indirect=True, +) +def test_c2_26mhz_xtal_write_throughput(app_path: str, dut: Tuple[IdfDut, IdfDut]) -> None: + server = dut[0] + client = dut[1] + client_addr = client.expect(r'Bluetooth MAC: (([0-9a-fA-F]{2}:){5}[0-9a-fA-F]{2})', timeout=30).group(1).decode('utf8') + server_addr = server.expect(r'Bluetooth MAC: (([0-9a-fA-F]{2}:){5}[0-9a-fA-F]{2})', timeout=30).group(1).decode('utf8') + + client.expect_exact('GATT client register, status 0', timeout=30) + server.expect_exact('GATT server register, status 0', timeout=30) + server.expect_exact('Advertising start successfully', timeout=30) + client.expect_exact('Scanning start successfully', timeout=30) + client.expect_exact('Device found ', timeout=30) + server.expect_exact('Service start, status 0', timeout=30) + server.expect_exact(f'Connected, conn_id 0, remote {client_addr}', timeout=30) + client.expect_exact(f'Connected, conn_id 0, remote {server_addr}', timeout=30) + client.expect_exact('MTU exchange, status 0, MTU 517', timeout=30) + server.expect_exact('MTU exchange, MTU 517', timeout=30) + client.expect_exact('Service search complete', timeout=30) + start_time = time.time() + while time.time() - start_time < 30: + throughput = int(server.expect(r'GATTC write Bit rate = (\d+) Byte/s', timeout=30).group(1).decode('utf8')) + assert throughput > 50000 or throughput < 95000 + + +# Case 3: gatt notify throughput test +@pytest.mark.esp32 +@pytest.mark.esp32c3 +@pytest.mark.esp32c6 +@pytest.mark.esp32c61 +@pytest.mark.esp32c5 +@pytest.mark.esp32h2 +@pytest.mark.esp32s3 +@pytest.mark.wifi_two_dut +@pytest.mark.parametrize( + 'count, app_path, config, erase_all', [ + (2, + f'{os.path.join(os.path.dirname(__file__), "throughput_server")}|{os.path.join(os.path.dirname(__file__), "throughput_client")}', + 'notify', 'y'), + ], + indirect=True, +) +def test_gatt_notify_throughput(app_path: str, dut: Tuple[IdfDut, IdfDut]) -> None: + server = dut[0] + client = dut[1] + client_addr = client.expect(r'Bluetooth MAC: (([0-9a-fA-F]{2}:){5}[0-9a-fA-F]{2})', timeout=30).group(1).decode('utf8') + server_addr = server.expect(r'Bluetooth MAC: (([0-9a-fA-F]{2}:){5}[0-9a-fA-F]{2})', timeout=30).group(1).decode('utf8') + + client.expect_exact('GATT client register, status 0', timeout=30) + server.expect_exact('GATT server register, status 0', timeout=30) + server.expect_exact('Advertising start successfully', timeout=30) + client.expect_exact('Scanning start successfully', timeout=30) + client.expect_exact('Device found ', timeout=30) + server.expect_exact('Service start, status 0', timeout=30) + server.expect_exact(f'Connected, conn_id 0, remote {client_addr}', timeout=30) + client.expect_exact(f'Connected, conn_id 0, remote {server_addr}', timeout=30) + client.expect_exact('MTU exchange, status 0, MTU 517', timeout=30) + server.expect_exact('MTU exchange, MTU 517', timeout=30) + client.expect_exact('Service search complete', timeout=30) + client.expect_exact('Notification register successfully', timeout=30) + server.expect_exact('Notification enable', timeout=30) + start_time = time.time() + while time.time() - start_time < 30: + throughput = int(client.expect(r'Notify Bit rate = (\d+) Byte/s', timeout=30).group(1).decode('utf8')) + assert throughput > 50000 or throughput < 95000 + + +# Case 4: gatt notify throughput test for ESP32C2 26mhz xtal +@pytest.mark.esp32c2 +@pytest.mark.wifi_two_dut +@pytest.mark.xtal_26mhz +@pytest.mark.parametrize( + 'count, target, baud, app_path, config, erase_all', [ + (2, 'esp32c2|esp32c2', '74880', + f'{os.path.join(os.path.dirname(__file__), "throughput_server")}|{os.path.join(os.path.dirname(__file__), "throughput_client")}', + 'esp32c2_xtal26m_notify', 'y'), + ], + indirect=True, +) +def test_c2_26mhz_xtal_notify_throughput(app_path: str, dut: Tuple[IdfDut, IdfDut]) -> None: + server = dut[0] + client = dut[1] + client_addr = client.expect(r'Bluetooth MAC: (([0-9a-fA-F]{2}:){5}[0-9a-fA-F]{2})', timeout=30).group(1).decode('utf8') + server_addr = server.expect(r'Bluetooth MAC: (([0-9a-fA-F]{2}:){5}[0-9a-fA-F]{2})', timeout=30).group(1).decode('utf8') + + client.expect_exact('GATT client register, status 0', timeout=30) + server.expect_exact('GATT server register, status 0', timeout=30) + server.expect_exact('Advertising start successfully', timeout=30) + client.expect_exact('Scanning start successfully', timeout=30) + client.expect_exact('Device found ', timeout=30) + server.expect_exact('Service start, status 0', timeout=30) + server.expect_exact(f'Connected, conn_id 0, remote {client_addr}', timeout=30) + client.expect_exact(f'Connected, conn_id 0, remote {server_addr}', timeout=30) + client.expect_exact('MTU exchange, status 0, MTU 517', timeout=30) + server.expect_exact('MTU exchange, MTU 517', timeout=30) + client.expect_exact('Service search complete', timeout=30) + client.expect_exact('Notification register successfully', timeout=30) + server.expect_exact('Notification enable', timeout=30) + start_time = time.time() + while time.time() - start_time < 30: + throughput = int(client.expect(r'Notify Bit rate = (\d+) Byte/s', timeout=30).group(1).decode('utf8')) + assert throughput > 50000 or throughput < 95000 diff --git a/examples/bluetooth/bluedroid/ble/ble_throughput/throughput_client/sdkconfig.ci.esp32c2_xtal26m_notify b/examples/bluetooth/bluedroid/ble/ble_throughput/throughput_client/sdkconfig.ci.esp32c2_xtal26m_notify new file mode 100644 index 00000000000..0448a5d2a50 --- /dev/null +++ b/examples/bluetooth/bluedroid/ble/ble_throughput/throughput_client/sdkconfig.ci.esp32c2_xtal26m_notify @@ -0,0 +1,7 @@ + +CONFIG_EXAMPLE_CI_ID=1 +CONFIG_IDF_TARGET="esp32c2" +CONFIG_XTAL_FREQ_26=y +CONFIG_EXAMPLE_CI_PIPELINE_ID=${CI_PIPELINE_ID} +CONFIG_EXAMPLE_GATTS_NOTIFY_THROUGHPUT=y +CONFIG_EXAMPLE_GATTC_WRITE_THROUGHPUT=n diff --git a/examples/bluetooth/bluedroid/ble/ble_throughput/throughput_client/sdkconfig.ci.esp32c2_xtal26m_write b/examples/bluetooth/bluedroid/ble/ble_throughput/throughput_client/sdkconfig.ci.esp32c2_xtal26m_write new file mode 100644 index 00000000000..5874287ec33 --- /dev/null +++ b/examples/bluetooth/bluedroid/ble/ble_throughput/throughput_client/sdkconfig.ci.esp32c2_xtal26m_write @@ -0,0 +1,6 @@ +CONFIG_EXAMPLE_CI_ID=1 +CONFIG_IDF_TARGET="esp32c2" +CONFIG_XTAL_FREQ_26=y +CONFIG_EXAMPLE_CI_PIPELINE_ID=${CI_PIPELINE_ID} +CONFIG_EXAMPLE_GATTC_WRITE_THROUGHPUT=y +CONFIG_EXAMPLE_GATTS_NOTIFY_THROUGHPUT=n diff --git a/examples/bluetooth/bluedroid/ble/ble_throughput/throughput_client/sdkconfig.ci.notify b/examples/bluetooth/bluedroid/ble/ble_throughput/throughput_client/sdkconfig.ci.notify new file mode 100644 index 00000000000..db7b616deba --- /dev/null +++ b/examples/bluetooth/bluedroid/ble/ble_throughput/throughput_client/sdkconfig.ci.notify @@ -0,0 +1,4 @@ +CONFIG_EXAMPLE_CI_ID=1 +CONFIG_EXAMPLE_CI_PIPELINE_ID=${CI_PIPELINE_ID} +CONFIG_EXAMPLE_GATTS_NOTIFY_THROUGHPUT=y +CONFIG_EXAMPLE_GATTC_WRITE_THROUGHPUT=n diff --git a/examples/bluetooth/bluedroid/ble/ble_throughput/throughput_client/sdkconfig.ci.write b/examples/bluetooth/bluedroid/ble/ble_throughput/throughput_client/sdkconfig.ci.write new file mode 100644 index 00000000000..a47edbf1826 --- /dev/null +++ b/examples/bluetooth/bluedroid/ble/ble_throughput/throughput_client/sdkconfig.ci.write @@ -0,0 +1,4 @@ +CONFIG_EXAMPLE_CI_ID=1 +CONFIG_EXAMPLE_CI_PIPELINE_ID=${CI_PIPELINE_ID} +CONFIG_EXAMPLE_GATTC_WRITE_THROUGHPUT=y +CONFIG_EXAMPLE_GATTS_NOTIFY_THROUGHPUT=n diff --git a/examples/bluetooth/bluedroid/ble/ble_throughput/throughput_server/sdkconfig.ci.esp32c2_xtal26m_notify b/examples/bluetooth/bluedroid/ble/ble_throughput/throughput_server/sdkconfig.ci.esp32c2_xtal26m_notify new file mode 100644 index 00000000000..0448a5d2a50 --- /dev/null +++ b/examples/bluetooth/bluedroid/ble/ble_throughput/throughput_server/sdkconfig.ci.esp32c2_xtal26m_notify @@ -0,0 +1,7 @@ + +CONFIG_EXAMPLE_CI_ID=1 +CONFIG_IDF_TARGET="esp32c2" +CONFIG_XTAL_FREQ_26=y +CONFIG_EXAMPLE_CI_PIPELINE_ID=${CI_PIPELINE_ID} +CONFIG_EXAMPLE_GATTS_NOTIFY_THROUGHPUT=y +CONFIG_EXAMPLE_GATTC_WRITE_THROUGHPUT=n diff --git a/examples/bluetooth/bluedroid/ble/ble_throughput/throughput_server/sdkconfig.ci.esp32c2_xtal26m_write b/examples/bluetooth/bluedroid/ble/ble_throughput/throughput_server/sdkconfig.ci.esp32c2_xtal26m_write new file mode 100644 index 00000000000..5874287ec33 --- /dev/null +++ b/examples/bluetooth/bluedroid/ble/ble_throughput/throughput_server/sdkconfig.ci.esp32c2_xtal26m_write @@ -0,0 +1,6 @@ +CONFIG_EXAMPLE_CI_ID=1 +CONFIG_IDF_TARGET="esp32c2" +CONFIG_XTAL_FREQ_26=y +CONFIG_EXAMPLE_CI_PIPELINE_ID=${CI_PIPELINE_ID} +CONFIG_EXAMPLE_GATTC_WRITE_THROUGHPUT=y +CONFIG_EXAMPLE_GATTS_NOTIFY_THROUGHPUT=n diff --git a/examples/bluetooth/bluedroid/ble/ble_throughput/throughput_server/sdkconfig.ci.notify b/examples/bluetooth/bluedroid/ble/ble_throughput/throughput_server/sdkconfig.ci.notify new file mode 100644 index 00000000000..db7b616deba --- /dev/null +++ b/examples/bluetooth/bluedroid/ble/ble_throughput/throughput_server/sdkconfig.ci.notify @@ -0,0 +1,4 @@ +CONFIG_EXAMPLE_CI_ID=1 +CONFIG_EXAMPLE_CI_PIPELINE_ID=${CI_PIPELINE_ID} +CONFIG_EXAMPLE_GATTS_NOTIFY_THROUGHPUT=y +CONFIG_EXAMPLE_GATTC_WRITE_THROUGHPUT=n diff --git a/examples/bluetooth/bluedroid/ble/ble_throughput/throughput_server/sdkconfig.ci.write b/examples/bluetooth/bluedroid/ble/ble_throughput/throughput_server/sdkconfig.ci.write new file mode 100644 index 00000000000..a47edbf1826 --- /dev/null +++ b/examples/bluetooth/bluedroid/ble/ble_throughput/throughput_server/sdkconfig.ci.write @@ -0,0 +1,4 @@ +CONFIG_EXAMPLE_CI_ID=1 +CONFIG_EXAMPLE_CI_PIPELINE_ID=${CI_PIPELINE_ID} +CONFIG_EXAMPLE_GATTC_WRITE_THROUGHPUT=y +CONFIG_EXAMPLE_GATTS_NOTIFY_THROUGHPUT=n diff --git a/examples/bluetooth/bluedroid/ble/gatt_client/sdkconfig.ci.esp32c2_xtal26m b/examples/bluetooth/bluedroid/ble/gatt_client/sdkconfig.ci.esp32c2_xtal26m new file mode 100644 index 00000000000..e77ed1d26cd --- /dev/null +++ b/examples/bluetooth/bluedroid/ble/gatt_client/sdkconfig.ci.esp32c2_xtal26m @@ -0,0 +1,5 @@ + +CONFIG_EXAMPLE_CI_ID=1 +CONFIG_IDF_TARGET="esp32c2" +CONFIG_XTAL_FREQ_26=y +CONFIG_EXAMPLE_CI_PIPELINE_ID=${CI_PIPELINE_ID} diff --git a/examples/bluetooth/bluedroid/ble/gatt_client/sdkconfig.ci.name b/examples/bluetooth/bluedroid/ble/gatt_client/sdkconfig.ci.name new file mode 100644 index 00000000000..6d9fd6470c4 --- /dev/null +++ b/examples/bluetooth/bluedroid/ble/gatt_client/sdkconfig.ci.name @@ -0,0 +1,2 @@ +CONFIG_EXAMPLE_CI_ID=1 +CONFIG_EXAMPLE_CI_PIPELINE_ID=${CI_PIPELINE_ID} diff --git a/examples/bluetooth/bluedroid/ble/gatt_client/sdkconfig.defaults.esp32c2 b/examples/bluetooth/bluedroid/ble/gatt_client/sdkconfig.defaults.esp32c2 index 298663d0a39..9759e23400c 100644 --- a/examples/bluetooth/bluedroid/ble/gatt_client/sdkconfig.defaults.esp32c2 +++ b/examples/bluetooth/bluedroid/ble/gatt_client/sdkconfig.defaults.esp32c2 @@ -7,3 +7,7 @@ CONFIG_BT_ENABLED=y CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y # CONFIG_BT_LE_50_FEATURE_SUPPORT is not set CONFIG_BT_LE_HCI_EVT_BUF_SIZE=257 + +# XTAL Freq Config +CONFIG_XTAL_FREQ_26=y +CONFIG_XTAL_FREQ=26 diff --git a/examples/bluetooth/bluedroid/ble/gatt_security_client/sdkconfig.ci.esp32c2_xtal26m b/examples/bluetooth/bluedroid/ble/gatt_security_client/sdkconfig.ci.esp32c2_xtal26m new file mode 100644 index 00000000000..6ab0a7ab9d4 --- /dev/null +++ b/examples/bluetooth/bluedroid/ble/gatt_security_client/sdkconfig.ci.esp32c2_xtal26m @@ -0,0 +1,4 @@ +CONFIG_EXAMPLE_CI_ID=1 +CONFIG_IDF_TARGET="esp32c2" +CONFIG_XTAL_FREQ_26=y +CONFIG_EXAMPLE_CI_PIPELINE_ID=${CI_PIPELINE_ID} diff --git a/examples/bluetooth/bluedroid/ble/gatt_security_client/sdkconfig.ci.name b/examples/bluetooth/bluedroid/ble/gatt_security_client/sdkconfig.ci.name new file mode 100644 index 00000000000..d8e23a54e91 --- /dev/null +++ b/examples/bluetooth/bluedroid/ble/gatt_security_client/sdkconfig.ci.name @@ -0,0 +1,3 @@ + +CONFIG_EXAMPLE_CI_ID=1 +CONFIG_EXAMPLE_CI_PIPELINE_ID=${CI_PIPELINE_ID} diff --git a/examples/bluetooth/bluedroid/ble/gatt_security_server/sdkconfig.ci.esp32c2_xtal26m b/examples/bluetooth/bluedroid/ble/gatt_security_server/sdkconfig.ci.esp32c2_xtal26m new file mode 100644 index 00000000000..6ab0a7ab9d4 --- /dev/null +++ b/examples/bluetooth/bluedroid/ble/gatt_security_server/sdkconfig.ci.esp32c2_xtal26m @@ -0,0 +1,4 @@ +CONFIG_EXAMPLE_CI_ID=1 +CONFIG_IDF_TARGET="esp32c2" +CONFIG_XTAL_FREQ_26=y +CONFIG_EXAMPLE_CI_PIPELINE_ID=${CI_PIPELINE_ID} diff --git a/examples/bluetooth/bluedroid/ble/gatt_security_server/sdkconfig.ci.name b/examples/bluetooth/bluedroid/ble/gatt_security_server/sdkconfig.ci.name new file mode 100644 index 00000000000..d8e23a54e91 --- /dev/null +++ b/examples/bluetooth/bluedroid/ble/gatt_security_server/sdkconfig.ci.name @@ -0,0 +1,3 @@ + +CONFIG_EXAMPLE_CI_ID=1 +CONFIG_EXAMPLE_CI_PIPELINE_ID=${CI_PIPELINE_ID} diff --git a/examples/bluetooth/bluedroid/ble/gatt_server/sdkconfig.ci.esp32c2_xtal26m b/examples/bluetooth/bluedroid/ble/gatt_server/sdkconfig.ci.esp32c2_xtal26m new file mode 100644 index 00000000000..6ab0a7ab9d4 --- /dev/null +++ b/examples/bluetooth/bluedroid/ble/gatt_server/sdkconfig.ci.esp32c2_xtal26m @@ -0,0 +1,4 @@ +CONFIG_EXAMPLE_CI_ID=1 +CONFIG_IDF_TARGET="esp32c2" +CONFIG_XTAL_FREQ_26=y +CONFIG_EXAMPLE_CI_PIPELINE_ID=${CI_PIPELINE_ID} diff --git a/examples/bluetooth/bluedroid/ble/gatt_server/sdkconfig.ci.name b/examples/bluetooth/bluedroid/ble/gatt_server/sdkconfig.ci.name new file mode 100644 index 00000000000..d8e23a54e91 --- /dev/null +++ b/examples/bluetooth/bluedroid/ble/gatt_server/sdkconfig.ci.name @@ -0,0 +1,3 @@ + +CONFIG_EXAMPLE_CI_ID=1 +CONFIG_EXAMPLE_CI_PIPELINE_ID=${CI_PIPELINE_ID} diff --git a/examples/bluetooth/bluedroid/ble/gatt_server/sdkconfig.defaults.esp32c2 b/examples/bluetooth/bluedroid/ble/gatt_server/sdkconfig.defaults.esp32c2 index 7e477f7373d..f13b703dc9f 100644 --- a/examples/bluetooth/bluedroid/ble/gatt_server/sdkconfig.defaults.esp32c2 +++ b/examples/bluetooth/bluedroid/ble/gatt_server/sdkconfig.defaults.esp32c2 @@ -6,3 +6,6 @@ CONFIG_BT_ENABLED=y CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y # CONFIG_BT_LE_50_FEATURE_SUPPORT is not set CONFIG_BT_LE_HCI_EVT_BUF_SIZE=257 +# XTAL Freq Config +CONFIG_XTAL_FREQ_26=y +CONFIG_XTAL_FREQ=26 diff --git a/examples/bluetooth/bluedroid/ble/pytest_ble_test.py b/examples/bluetooth/bluedroid/ble/pytest_ble_test.py new file mode 100644 index 00000000000..9de955b3001 --- /dev/null +++ b/examples/bluetooth/bluedroid/ble/pytest_ble_test.py @@ -0,0 +1,265 @@ +# SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD +# SPDX-License-Identifier: CC0-1.0 +import os.path +from typing import Tuple + +import pexpect +import pytest +from pytest_embedded_idf.dut import IdfDut + + +# Case 1: gatt client and gatt server test +@pytest.mark.esp32 +@pytest.mark.esp32c3 +@pytest.mark.esp32c6 +@pytest.mark.esp32c5 +@pytest.mark.esp32h2 +@pytest.mark.esp32s3 +@pytest.mark.esp32c61 +@pytest.mark.wifi_two_dut +@pytest.mark.parametrize( + 'count, app_path, config, erase_all', [ + (2, + f'{os.path.join(os.path.dirname(__file__), "gatt_server")}|{os.path.join(os.path.dirname(__file__), "gatt_client")}', + 'name', 'y'), + ], + indirect=True, +) +def test_gatt_func(app_path: str, dut: Tuple[IdfDut, IdfDut]) -> None: + gatt_client = dut[1] + gatt_server = dut[0] + gatt_client_addr = gatt_client.expect(r'Bluetooth MAC: (([0-9a-fA-F]{2}:){5}[0-9a-fA-F]{2})', timeout=30).group(1).decode('utf8') + gatt_server_addr = gatt_server.expect(r'Bluetooth MAC: (([0-9a-fA-F]{2}:){5}[0-9a-fA-F]{2})', timeout=30).group(1).decode('utf8') + gatt_client.expect_exact('GATT client register, status 0', timeout=30) + gatt_server.expect_exact('GATT server register, status 0', timeout=30) + gatt_server.expect_exact('Advertising start successfully', timeout=30) + gatt_client.expect_exact('Scanning start successfully', timeout=30) + gatt_client.expect_exact(f'Connected, conn_id 0, remote {gatt_server_addr}', timeout=30) + gatt_server.expect_exact(f'Connected, conn_id 0, remote {gatt_client_addr}', timeout=30) + gatt_client.expect_exact('Connection params update, status 0', timeout=30) + gatt_server.expect_exact('Connection params update, status 0', timeout=30) + gatt_client.expect_exact('Service discover complete', timeout=30) + gatt_client.expect_exact('Service search complete', timeout=30) + gatt_client.expect_exact('MTU exchange, status 0, MTU 500', timeout=30) + gatt_server.expect_exact('MTU exchange, MTU 500', timeout=30) + gatt_server.expect_exact('Notification enable', timeout=30) + gatt_client.expect_exact('Notification received', timeout=30) + gatt_client_output = gatt_client.expect(pexpect.TIMEOUT, timeout=10) + gatt_server_output = gatt_server.expect(pexpect.TIMEOUT, timeout=10) + assert 'rst:' not in str(gatt_client_output) and 'boot:' not in str(gatt_client_output) + assert 'rst:' not in str(gatt_server_output) and 'boot:' not in str(gatt_server_output) + assert 'Disconnected' not in str(gatt_client_output) + assert 'Disconnected' not in str(gatt_server_output) + + +# Case 2: gatt client and gatt server test for ESP32C2 26mhz xtal +@pytest.mark.esp32c2 +@pytest.mark.wifi_two_dut +@pytest.mark.xtal_26mhz +@pytest.mark.parametrize( + 'count, target, baud, app_path, config, erase_all', [ + (2, 'esp32c2|esp32c2', '74880', + f'{os.path.join(os.path.dirname(__file__), "gatt_server")}|{os.path.join(os.path.dirname(__file__), "gatt_client")}', + 'esp32c2_xtal26m', 'y'), + ], + indirect=True, +) +def test_c2_26mhz_xtal_gatt_func(app_path: str, dut: Tuple[IdfDut, IdfDut]) -> None: + gatt_client = dut[1] + gatt_server = dut[0] + gatt_client_addr = gatt_client.expect(r'Bluetooth MAC: (([0-9a-fA-F]{2}:){5}[0-9a-fA-F]{2})').group(1).decode('utf8') + gatt_server_addr = gatt_server.expect(r'Bluetooth MAC: (([0-9a-fA-F]{2}:){5}[0-9a-fA-F]{2})').group(1).decode('utf8') + gatt_client.expect_exact('GATT client register, status 0', timeout=30) + gatt_server.expect_exact('GATT server register, status 0', timeout=30) + gatt_server.expect_exact('Advertising start successfully', timeout=30) + gatt_client.expect_exact('Scanning start success', timeout=30) + gatt_client.expect_exact(f'Connected, conn_id 0, remote {gatt_server_addr}', timeout=30) + gatt_server.expect_exact(f'Connected, conn_id 0, remote {gatt_client_addr}', timeout=30) + gatt_client.expect_exact('Connection params update, status 0', timeout=30) + gatt_server.expect_exact('Connection params update, status 0', timeout=30) + gatt_client.expect_exact('Service discover complete', timeout=30) + gatt_client.expect_exact('Service search complete', timeout=30) + gatt_client.expect_exact('MTU exchange, status 0, MTU 500', timeout=30) + gatt_server.expect_exact('MTU exchange, MTU 500', timeout=30) + gatt_server.expect_exact('Notification enable', timeout=30) + gatt_client.expect_exact('Notification received', timeout=30) + gatt_client_output = gatt_client.expect(pexpect.TIMEOUT, timeout=10) + gatt_server_output = gatt_server.expect(pexpect.TIMEOUT, timeout=10) + assert 'rst:' not in str(gatt_client_output) and 'boot:' not in str(gatt_client_output) + assert 'rst:' not in str(gatt_server_output) and 'boot:' not in str(gatt_server_output) + assert 'Disconnected' not in str(gatt_client_output) + assert 'Disconnected' not in str(gatt_server_output) + + +# Case 3: gatt security server and gatt security client test +@pytest.mark.esp32 +@pytest.mark.esp32c3 +@pytest.mark.esp32c6 +@pytest.mark.esp32c5 +@pytest.mark.esp32h2 +@pytest.mark.esp32s3 +@pytest.mark.esp32c61 +@pytest.mark.wifi_two_dut +@pytest.mark.parametrize( + 'count, app_path, config, erase_all', [ + (2, + f'{os.path.join(os.path.dirname(__file__), "gatt_security_server")}|{os.path.join(os.path.dirname(__file__), "gatt_security_client")}', + 'name', 'y'), + ], + indirect=True, +) +def test_gatt_security_func(app_path: str, dut: Tuple[IdfDut, IdfDut], target: Tuple) -> None: + gatt_security_client = dut[1] + gatt_security_server = dut[0] + gatt_security_client_addr = gatt_security_client.expect(r'Bluetooth MAC: (([0-9a-fA-F]{2}:){5}[0-9a-fA-F]{2})', timeout=30).group(1).decode('utf8') + + gatt_security_client.expect_exact('GATT client register, status 0', timeout=30) + gatt_security_server.expect_exact('GATT server register, status 0', timeout=30) + gatt_security_client.expect_exact('Local privacy config successfully', timeout=30) + gatt_security_server.expect_exact('Local privacy config successfully', timeout=30) + gatt_security_server.expect_exact('Advertising start successfully', timeout=30) + gatt_security_client.expect_exact('Scanning start successfully', timeout=30) + gatt_security_client.expect_exact('Device found BE', timeout=30) + # can not get rpa_address, so not check server address + gatt_security_client.expect_exact(f'Connected, conn_id 0, remote ', timeout=30) + if target == ('esp32', 'esp32'): + gatt_security_server.expect_exact(f'Connected, conn_id 0, remote', timeout=30) + else: + gatt_security_server.expect_exact(f'Connected, conn_id 0, remote {gatt_security_client_addr}', timeout=30) + gatt_security_client.expect_exact('Key exchanged, key_type ESP_LE_KEY_PID', timeout=30) + gatt_security_client.expect_exact('Key exchanged, key_type ESP_LE_KEY_LENC', timeout=30) + gatt_security_client.expect_exact('Key exchanged, key_type ESP_LE_KEY_PENC', timeout=30) + gatt_security_client.expect_exact('Key exchanged, key_type ESP_LE_KEY_LID', timeout=30) + + gatt_security_server.expect_exact('Key exchanged, key_type ESP_LE_KEY_LENC', timeout=30) + gatt_security_server.expect_exact('Key exchanged, key_type ESP_LE_KEY_PENC', timeout=30) + gatt_security_server.expect_exact('Key exchanged, key_type ESP_LE_KEY_LID', timeout=30) + gatt_security_server.expect_exact('Key exchanged, key_type ESP_LE_KEY_PID', timeout=30) + if target == ('esp32', 'esp32'): + gatt_security_server.expect_exact(f'Authentication complete, addr_type 1, addr ', timeout=30) + else: + gatt_security_server.expect_exact(f'Authentication complete, addr_type 0, addr {gatt_security_client_addr}', timeout=30) + gatt_security_client.expect_exact(f'Authentication complete, addr_type 1, addr ', timeout=30) + gatt_security_server.expect_exact('Pairing successfully', timeout=30) + gatt_security_server.expect_exact('Bonded devices number 1', timeout=30) + gatt_security_client.expect_exact('Pairing successfully', timeout=30) + gatt_security_client.expect_exact('Service search complete', timeout=30) + gatt_security_client_output = gatt_security_client.expect(pexpect.TIMEOUT, timeout=10) + gatt_security_server_output = gatt_security_server.expect(pexpect.TIMEOUT, timeout=10) + assert 'rst:' not in str(gatt_security_client_output) and 'boot:' not in str(gatt_security_client_output) + assert 'rst:' not in str(gatt_security_server_output) and 'boot:' not in str(gatt_security_server_output) + assert 'Disconnected' not in str(gatt_security_client_output) + assert 'Disconnected' not in str(gatt_security_server_output) + + +# Case 4: gatt security server and gatt security client test for ESP32C2 26mhz xtal +@pytest.mark.esp32c2 +@pytest.mark.wifi_two_dut +@pytest.mark.xtal_26mhz +@pytest.mark.parametrize( + 'count, target, baud, app_path, config, erase_all', [ + (2, 'esp32c2|esp32c2', '74880', + f'{os.path.join(os.path.dirname(__file__), "gatt_security_server")}|{os.path.join(os.path.dirname(__file__), "gatt_security_client")}', + 'esp32c2_xtal26m', 'y'), + ], + indirect=True, +) +def test_c2_26mhz_xtal_gatt_security_func(app_path: str, dut: Tuple[IdfDut, IdfDut]) -> None: + gatt_security_client = dut[1] + gatt_security_server = dut[0] + gatt_security_client_addr = gatt_security_client.expect(r'Bluetooth MAC: (([0-9a-fA-F]{2}:){5}[0-9a-fA-F]{2})', timeout=30).group(1).decode('utf8') + + gatt_security_client.expect_exact('GATT client register, status 0', timeout=30) + gatt_security_server.expect_exact('GATT server register, status 0', timeout=30) + gatt_security_client.expect_exact('Local privacy config successfully', timeout=30) + gatt_security_server.expect_exact('Local privacy config successfully', timeout=30) + gatt_security_server.expect_exact('Advertising start successfully', timeout=30) + gatt_security_client.expect_exact('Scanning start successfully', timeout=30) + gatt_security_client.expect_exact('Device found BE', timeout=30) + # can not get rpa_address, so not check server address + gatt_security_client.expect_exact(f'Connected, conn_id 0, remote ', timeout=30) + gatt_security_server.expect_exact(f'Connected, conn_id 0, remote {gatt_security_client_addr}', timeout=30) + gatt_security_client.expect_exact('Key exchanged, key_type ESP_LE_KEY_PID', timeout=30) + gatt_security_client.expect_exact('Key exchanged, key_type ESP_LE_KEY_LENC', timeout=30) + gatt_security_client.expect_exact('Key exchanged, key_type ESP_LE_KEY_PENC', timeout=30) + gatt_security_client.expect_exact('Key exchanged, key_type ESP_LE_KEY_LID', timeout=30) + + gatt_security_server.expect_exact('Key exchanged, key_type ESP_LE_KEY_LENC', timeout=30) + gatt_security_server.expect_exact('Key exchanged, key_type ESP_LE_KEY_PENC', timeout=30) + gatt_security_server.expect_exact('Key exchanged, key_type ESP_LE_KEY_LID', timeout=30) + gatt_security_server.expect_exact('Key exchanged, key_type ESP_LE_KEY_PID', timeout=30) + gatt_security_server.expect_exact(f'Authentication complete, addr_type 0, addr {gatt_security_client_addr}', timeout=30) + gatt_security_client.expect_exact(f'Authentication complete, addr_type 1, addr ', timeout=30) + gatt_security_server.expect_exact('Pairing successfully', timeout=30) + gatt_security_server.expect_exact('Bonded devices number 1', timeout=30) + gatt_security_client.expect_exact('Pairing successfully', timeout=30) + gatt_security_client.expect_exact('Service search complete', timeout=30) + gatt_security_client_output = gatt_security_client.expect(pexpect.TIMEOUT, timeout=10) + gatt_security_server_output = gatt_security_server.expect(pexpect.TIMEOUT, timeout=10) + assert 'rst:' not in str(gatt_security_client_output) and 'boot:' not in str(gatt_security_client_output) + assert 'rst:' not in str(gatt_security_server_output) and 'boot:' not in str(gatt_security_server_output) + assert 'Disconnected' not in str(gatt_security_client_output) + assert 'Disconnected' not in str(gatt_security_server_output) + + +# Case 5: ble ibeacon test +@pytest.mark.esp32 +@pytest.mark.esp32c3 +@pytest.mark.esp32c6 +@pytest.mark.esp32c5 +@pytest.mark.esp32h2 +@pytest.mark.esp32s3 +@pytest.mark.esp32c61 +@pytest.mark.wifi_two_dut +@pytest.mark.parametrize( + 'count, app_path, config, erase_all', [ + (2, + f'{os.path.join(os.path.dirname(__file__), "ble_ibeacon")}|{os.path.join(os.path.dirname(__file__), "ble_ibeacon")}', + 'sender|receiver', 'y'), + ], + indirect=True, +) +def test_ble_ibeacon_func(app_path: str, dut: Tuple[IdfDut, IdfDut]) -> None: + ibeacon_sender = dut[0] + ibeacon_receiver = dut[1] + + ibeacon_sender_addr = ibeacon_sender.expect(r'Bluetooth MAC: (([0-9a-fA-F]{2}:){5}[0-9a-fA-F]{2})', timeout=30).group(1).decode('utf8') + + ibeacon_sender.expect_exact('Advertising start successfully', timeout=30) + ibeacon_receiver.expect_exact('Scanning start successfully', timeout=30) + ibeacon_receiver.expect_exact('iBeacon Found', timeout=30) + ibeacon_receiver.expect_exact(f'IBEACON_DEMO: Device address: {ibeacon_sender_addr}', timeout=30) + ibeacon_receiver.expect_exact('IBEACON_DEMO: Proximity UUID:', timeout=30) + ibeacon_receiver.expect_exact('Major: 0x27b7 (10167)', timeout=30) + ibeacon_receiver.expect_exact('Minor: 0xf206 (61958)', timeout=30) + ibeacon_receiver.expect_exact('Measured power (RSSI at a 1m distance):', timeout=30) + ibeacon_receiver.expect_exact('RSSI of packet: ', timeout=30) + + +# Case 5: ble ibeacon test for ESP32C2 26mhz xtal +@pytest.mark.esp32c2 +@pytest.mark.wifi_two_dut +@pytest.mark.xtal_26mhz +@pytest.mark.parametrize( + 'count, target, baud, app_path, config, erase_all', [ + (2, 'esp32c2|esp32c2', '74880', + f'{os.path.join(os.path.dirname(__file__), "ble_ibeacon")}|{os.path.join(os.path.dirname(__file__), "ble_ibeacon")}', + 'esp32c2_xtal26m_sender|esp32c2_xtal26m_receiver', 'y'), + ], + indirect=True, +) +def test_c2_26mhz_ble_ibeacon_func(app_path: str, dut: Tuple[IdfDut, IdfDut]) -> None: + ibeacon_sender = dut[0] + ibeacon_receiver = dut[1] + + ibeacon_sender_addr = ibeacon_sender.expect(r'Bluetooth MAC: (([0-9a-fA-F]{2}:){5}[0-9a-fA-F]{2})', timeout=30).group(1).decode('utf8') + + ibeacon_sender.expect_exact('Advertising start successfully', timeout=30) + ibeacon_receiver.expect_exact('Scanning start successfully', timeout=30) + ibeacon_receiver.expect_exact('iBeacon Found', timeout=30) + ibeacon_receiver.expect_exact(f'IBEACON_DEMO: Device address: {ibeacon_sender_addr}', timeout=30) + ibeacon_receiver.expect_exact('IBEACON_DEMO: Proximity UUID:', timeout=30) + ibeacon_receiver.expect_exact('Major: 0x27b7 (10167)', timeout=30) + ibeacon_receiver.expect_exact('Minor: 0xf206 (61958)', timeout=30) + ibeacon_receiver.expect_exact('Measured power (RSSI at a 1m distance):', timeout=30) + ibeacon_receiver.expect_exact('RSSI of packet: ', timeout=30) diff --git a/examples/bluetooth/bluedroid/ble_50/ble50_security_client/sdkconfig.ci.esp32c2_xtal26m b/examples/bluetooth/bluedroid/ble_50/ble50_security_client/sdkconfig.ci.esp32c2_xtal26m new file mode 100644 index 00000000000..6ab0a7ab9d4 --- /dev/null +++ b/examples/bluetooth/bluedroid/ble_50/ble50_security_client/sdkconfig.ci.esp32c2_xtal26m @@ -0,0 +1,4 @@ +CONFIG_EXAMPLE_CI_ID=1 +CONFIG_IDF_TARGET="esp32c2" +CONFIG_XTAL_FREQ_26=y +CONFIG_EXAMPLE_CI_PIPELINE_ID=${CI_PIPELINE_ID} diff --git a/examples/bluetooth/bluedroid/ble_50/ble50_security_client/sdkconfig.ci.name b/examples/bluetooth/bluedroid/ble_50/ble50_security_client/sdkconfig.ci.name new file mode 100644 index 00000000000..6d9fd6470c4 --- /dev/null +++ b/examples/bluetooth/bluedroid/ble_50/ble50_security_client/sdkconfig.ci.name @@ -0,0 +1,2 @@ +CONFIG_EXAMPLE_CI_ID=1 +CONFIG_EXAMPLE_CI_PIPELINE_ID=${CI_PIPELINE_ID} diff --git a/examples/bluetooth/bluedroid/ble_50/ble50_security_server/sdkconfig.ci.esp32c2_xtal26m b/examples/bluetooth/bluedroid/ble_50/ble50_security_server/sdkconfig.ci.esp32c2_xtal26m new file mode 100644 index 00000000000..6ab0a7ab9d4 --- /dev/null +++ b/examples/bluetooth/bluedroid/ble_50/ble50_security_server/sdkconfig.ci.esp32c2_xtal26m @@ -0,0 +1,4 @@ +CONFIG_EXAMPLE_CI_ID=1 +CONFIG_IDF_TARGET="esp32c2" +CONFIG_XTAL_FREQ_26=y +CONFIG_EXAMPLE_CI_PIPELINE_ID=${CI_PIPELINE_ID} diff --git a/examples/bluetooth/bluedroid/ble_50/ble50_security_server/sdkconfig.ci.name b/examples/bluetooth/bluedroid/ble_50/ble50_security_server/sdkconfig.ci.name new file mode 100644 index 00000000000..6d9fd6470c4 --- /dev/null +++ b/examples/bluetooth/bluedroid/ble_50/ble50_security_server/sdkconfig.ci.name @@ -0,0 +1,2 @@ +CONFIG_EXAMPLE_CI_ID=1 +CONFIG_EXAMPLE_CI_PIPELINE_ID=${CI_PIPELINE_ID} diff --git a/examples/bluetooth/bluedroid/ble_50/periodic_adv/sdkconfig.ci.esp32c2_xtal26m b/examples/bluetooth/bluedroid/ble_50/periodic_adv/sdkconfig.ci.esp32c2_xtal26m new file mode 100644 index 00000000000..6ab0a7ab9d4 --- /dev/null +++ b/examples/bluetooth/bluedroid/ble_50/periodic_adv/sdkconfig.ci.esp32c2_xtal26m @@ -0,0 +1,4 @@ +CONFIG_EXAMPLE_CI_ID=1 +CONFIG_IDF_TARGET="esp32c2" +CONFIG_XTAL_FREQ_26=y +CONFIG_EXAMPLE_CI_PIPELINE_ID=${CI_PIPELINE_ID} diff --git a/examples/bluetooth/bluedroid/ble_50/periodic_adv/sdkconfig.ci.name b/examples/bluetooth/bluedroid/ble_50/periodic_adv/sdkconfig.ci.name new file mode 100644 index 00000000000..6d9fd6470c4 --- /dev/null +++ b/examples/bluetooth/bluedroid/ble_50/periodic_adv/sdkconfig.ci.name @@ -0,0 +1,2 @@ +CONFIG_EXAMPLE_CI_ID=1 +CONFIG_EXAMPLE_CI_PIPELINE_ID=${CI_PIPELINE_ID} diff --git a/examples/bluetooth/bluedroid/ble_50/periodic_sync/sdkconfig.ci.esp32c2_xtal26m b/examples/bluetooth/bluedroid/ble_50/periodic_sync/sdkconfig.ci.esp32c2_xtal26m new file mode 100644 index 00000000000..6ab0a7ab9d4 --- /dev/null +++ b/examples/bluetooth/bluedroid/ble_50/periodic_sync/sdkconfig.ci.esp32c2_xtal26m @@ -0,0 +1,4 @@ +CONFIG_EXAMPLE_CI_ID=1 +CONFIG_IDF_TARGET="esp32c2" +CONFIG_XTAL_FREQ_26=y +CONFIG_EXAMPLE_CI_PIPELINE_ID=${CI_PIPELINE_ID} diff --git a/examples/bluetooth/bluedroid/ble_50/periodic_sync/sdkconfig.ci.name b/examples/bluetooth/bluedroid/ble_50/periodic_sync/sdkconfig.ci.name new file mode 100644 index 00000000000..6d9fd6470c4 --- /dev/null +++ b/examples/bluetooth/bluedroid/ble_50/periodic_sync/sdkconfig.ci.name @@ -0,0 +1,2 @@ +CONFIG_EXAMPLE_CI_ID=1 +CONFIG_EXAMPLE_CI_PIPELINE_ID=${CI_PIPELINE_ID} diff --git a/examples/bluetooth/bluedroid/ble_50/pytest_ble50_test.py b/examples/bluetooth/bluedroid/ble_50/pytest_ble50_test.py new file mode 100644 index 00000000000..b5b02e87f80 --- /dev/null +++ b/examples/bluetooth/bluedroid/ble_50/pytest_ble50_test.py @@ -0,0 +1,143 @@ +# SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD +# SPDX-License-Identifier: CC0-1.0 +import os.path +from typing import Tuple + +import pytest +from pytest_embedded_idf.dut import IdfDut + + +# Case 1: ble50 security client and ble50 security server test +@pytest.mark.esp32c3 +@pytest.mark.esp32c6 +@pytest.mark.esp32c5 +@pytest.mark.esp32h2 +@pytest.mark.esp32s3 +@pytest.mark.esp32c61 +@pytest.mark.wifi_two_dut +@pytest.mark.parametrize( + 'count, app_path, config, erase_all', [ + (2, + f'{os.path.join(os.path.dirname(__file__), "ble50_security_server")}|{os.path.join(os.path.dirname(__file__), "ble50_security_client")}', + 'name', 'y'), + ], + indirect=True, +) +def test_ble50_security_func(app_path: str, dut: Tuple[IdfDut, IdfDut]) -> None: + server = dut[0] + client = dut[1] + client_addr = client.expect(r'Bluetooth MAC: (([0-9a-fA-F]{2}:){5}[0-9a-fA-F]{2})', timeout=30).group(1).decode('utf8') + server_addr = server.expect(r'Bluetooth MAC: (([0-9a-fA-F]{2}:){5}[0-9a-fA-F]{2})', timeout=30).group(1).decode('utf8') + + server.expect_exact('Extended advertising params set, status 0', timeout=30) + server.expect_exact('Extended advertising data set, status 0', timeout=30) + server.expect_exact('Extended advertising start, status 0', timeout=30) + client.expect_exact('Extended scanning start successfully', timeout=30) + client.expect_exact(f'Connected, conn_id 0, remote {server_addr}', timeout=30) + server.expect_exact(f'Connected, conn_id 0, remote {client_addr}', timeout=30) + server.expect_exact('Pairing successfully', timeout=30) + client.expect_exact('Pairing successfully', timeout=30) + server.expect_exact('Bonded devices number 1', timeout=30) + server.expect_exact('Characteristic write', timeout=30) + client.expect_exact('Service discover complete', timeout=30) + client.expect_exact('Service search complete', timeout=30) + client.expect_exact('MTU exchange, status 0', timeout=30) + client.expect_exact('Descriptor write successfully', timeout=30) + + +# Case 2: ble50 security client and ble50 security server test for ESP32C2 26mhz xtal +@pytest.mark.esp32c2 +@pytest.mark.wifi_two_dut +@pytest.mark.xtal_26mhz +@pytest.mark.parametrize( + 'count, target, baud, app_path, config, erase_all', [ + (2, 'esp32c2|esp32c2', '74880', + f'{os.path.join(os.path.dirname(__file__), "ble50_security_server")}|{os.path.join(os.path.dirname(__file__), "ble50_security_client")}', + 'esp32c2_xtal26m', 'y'), + ], + indirect=True, +) +def test_c2_26mhz_xtal_ble50_security_func(app_path: str, dut: Tuple[IdfDut, IdfDut]) -> None: + server = dut[0] + client = dut[1] + client_addr = client.expect(r'Bluetooth MAC: (([0-9a-fA-F]{2}:){5}[0-9a-fA-F]{2})', timeout=30).group(1).decode('utf8') + server_addr = server.expect(r'Bluetooth MAC: (([0-9a-fA-F]{2}:){5}[0-9a-fA-F]{2})', timeout=30).group(1).decode('utf8') + + server.expect_exact('Extended advertising params set, status 0', timeout=30) + server.expect_exact('Extended advertising data set, status 0', timeout=30) + server.expect_exact('Extended advertising start, status 0', timeout=30) + client.expect_exact('Extended scanning start successfully', timeout=30) + client.expect_exact(f'Connected, conn_id 0, remote {server_addr}', timeout=30) + server.expect_exact(f'Connected, conn_id 0, remote {client_addr}', timeout=30) + server.expect_exact('Pairing successfully', timeout=30) + client.expect_exact('Pairing successfully', timeout=30) + server.expect_exact('Bonded devices number 1', timeout=30) + server.expect_exact('Characteristic write', timeout=30) + client.expect_exact('Service discover complete', timeout=30) + client.expect_exact('Service search complete', timeout=30) + client.expect_exact('MTU exchange, status 0', timeout=30) + client.expect_exact('Descriptor write successfully', timeout=30) + + +# Case 3: period_adv and period_sync test +@pytest.mark.esp32c3 +@pytest.mark.esp32c6 +@pytest.mark.esp32c5 +@pytest.mark.esp32h2 +@pytest.mark.esp32s3 +@pytest.mark.esp32c61 +@pytest.mark.wifi_two_dut +@pytest.mark.parametrize( + 'count, app_path, config, erase_all', [ + (2, + f'{os.path.join(os.path.dirname(__file__), "periodic_adv")}|{os.path.join(os.path.dirname(__file__), "periodic_sync")}', + 'name', 'y'), + ], + indirect=True, +) +def test_period_adv_sync_func(app_path: str, dut: Tuple[IdfDut, IdfDut]) -> None: + adv_dut = dut[0] + sync_dut = dut[1] + + adv_dut.expect_exact('Extended advertising params set, status 0', timeout=30) + adv_dut.expect_exact('Extended advertising random address set, status 0', timeout=30) + adv_dut.expect_exact('Extended advertising data set, status 0', timeout=30) + adv_dut.expect_exact('Extended advertising start, status 0', timeout=30) + adv_dut.expect_exact('Periodic advertising params set, status 0', timeout=30) + adv_dut.expect_exact('Periodic advertising data set, status 0', timeout=30) + adv_dut.expect_exact('Periodic advertising start, status 0', timeout=30) + sync_dut.expect_exact('Extended scanning params set, status 0', timeout=30) + sync_dut.expect_exact('Extended scanning start, status 0', timeout=30) + sync_dut.expect_exact(f'Create sync with the peer device BE', timeout=30) + sync_dut.expect_exact('Periodic advertising sync establish, status 0', timeout=30) + sync_dut.expect_exact('Periodic adv report, sync handle ', timeout=30) + + +# Case 4: period_adv and period_sync test for ESP32C2 26mhz xtal +@pytest.mark.esp32c2 +@pytest.mark.wifi_two_dut +@pytest.mark.xtal_26mhz +@pytest.mark.parametrize( + 'count, target, baud, app_path, config, erase_all', [ + (2, 'esp32c2|esp32c2', '74880', + f'{os.path.join(os.path.dirname(__file__), "periodic_adv")}|{os.path.join(os.path.dirname(__file__), "periodic_sync")}', + 'esp32c2_xtal26m', 'y'), + ], + indirect=True, +) +def test_c2_26mhz_xtal_period_adv_sync_func(app_path: str, dut: Tuple[IdfDut, IdfDut]) -> None: + adv_dut = dut[0] + sync_dut = dut[1] + + adv_dut.expect_exact('Extended advertising params set, status 0', timeout=30) + adv_dut.expect_exact('Extended advertising random address set, status 0', timeout=30) + adv_dut.expect_exact('Extended advertising data set, status 0', timeout=30) + adv_dut.expect_exact('Extended advertising start, status 0', timeout=30) + adv_dut.expect_exact('Periodic advertising params set, status 0', timeout=30) + adv_dut.expect_exact('Periodic advertising data set, status 0', timeout=30) + adv_dut.expect_exact('Periodic advertising start, status 0', timeout=30) + sync_dut.expect_exact('Extended scanning params set, status 0', timeout=30) + sync_dut.expect_exact('Extended scanning start, status 0', timeout=30) + sync_dut.expect_exact(f'Create sync with the peer device BE', timeout=30) + sync_dut.expect_exact('Periodic advertising sync establish, status 0', timeout=30) + sync_dut.expect_exact('Periodic adv report, sync handle ', timeout=30) From d19666d8e5c32232b828c1befb61d99cd798384e Mon Sep 17 00:00:00 2001 From: Peter Marcisovsky Date: Mon, 7 Oct 2024 13:51:09 +0200 Subject: [PATCH 057/472] refactor(usb_host): Update the USB component to new critical section API --- components/usb/ext_hub.c | 13 ++++++------- components/usb/hcd_dwc.c | 11 ++++++----- components/usb/hub.c | 17 ++++++++--------- components/usb/usb_host.c | 16 ++++++++-------- components/usb/usb_phy.c | 31 +++++++++++++++++-------------- components/usb/usbh.c | 18 ++++++++---------- 6 files changed, 53 insertions(+), 53 deletions(-) diff --git a/components/usb/ext_hub.c b/components/usb/ext_hub.c index 149993070c0..1c821677f45 100644 --- a/components/usb/ext_hub.c +++ b/components/usb/ext_hub.c @@ -9,8 +9,7 @@ #include "esp_err.h" #include "esp_log.h" #include "esp_heap_caps.h" -#include "freertos/FreeRTOS.h" -#include "freertos/task.h" +#include "esp_private/critical_section.h" #include "usb_private.h" #include "ext_hub.h" #include "ext_port.h" @@ -152,7 +151,6 @@ typedef struct { } ext_hub_driver_t; static ext_hub_driver_t *p_ext_hub_driver = NULL; -static portMUX_TYPE ext_hub_driver_lock = portMUX_INITIALIZER_UNLOCKED; const char *EXT_HUB_TAG = "EXT_HUB"; @@ -160,10 +158,11 @@ const char *EXT_HUB_TAG = "EXT_HUB"; // ------------------------------- Helpers ------------------------------------- // ----------------------------------------------------------------------------- -#define EXT_HUB_ENTER_CRITICAL() portENTER_CRITICAL(&ext_hub_driver_lock) -#define EXT_HUB_EXIT_CRITICAL() portEXIT_CRITICAL(&ext_hub_driver_lock) -#define EXT_HUB_ENTER_CRITICAL_SAFE() portENTER_CRITICAL_SAFE(&ext_hub_driver_lock) -#define EXT_HUB_EXIT_CRITICAL_SAFE() portEXIT_CRITICAL_SAFE(&ext_hub_driver_lock) +DEFINE_CRIT_SECTION_LOCK_STATIC(ext_hub_driver_lock); +#define EXT_HUB_ENTER_CRITICAL() esp_os_enter_critical(&ext_hub_driver_lock) +#define EXT_HUB_EXIT_CRITICAL() esp_os_exit_critical(&ext_hub_driver_lock) +#define EXT_HUB_ENTER_CRITICAL_SAFE() esp_os_enter_critical_safe(&ext_hub_driver_lock) +#define EXT_HUB_EXIT_CRITICAL_SAFE() esp_os_exit_critical_safe(&ext_hub_driver_lock) #define EXT_HUB_CHECK(cond, ret_val) ({ \ if (!(cond)) { \ diff --git a/components/usb/hcd_dwc.c b/components/usb/hcd_dwc.c index a5ea7d736ff..76f031ae210 100644 --- a/components/usb/hcd_dwc.c +++ b/components/usb/hcd_dwc.c @@ -10,6 +10,7 @@ #include "freertos/FreeRTOS.h" #include "freertos/task.h" #include "freertos/semphr.h" +#include "esp_private/critical_section.h" #include "esp_heap_caps.h" #include "esp_intr_alloc.h" #include "soc/interrupts.h" // For interrupt index @@ -84,10 +85,11 @@ const char *HCD_DWC_TAG = "HCD DWC"; -#define HCD_ENTER_CRITICAL_ISR() portENTER_CRITICAL_ISR(&hcd_lock) -#define HCD_EXIT_CRITICAL_ISR() portEXIT_CRITICAL_ISR(&hcd_lock) -#define HCD_ENTER_CRITICAL() portENTER_CRITICAL(&hcd_lock) -#define HCD_EXIT_CRITICAL() portEXIT_CRITICAL(&hcd_lock) +DEFINE_CRIT_SECTION_LOCK_STATIC(hcd_lock); +#define HCD_ENTER_CRITICAL_ISR() esp_os_enter_critical_isr(&hcd_lock) +#define HCD_EXIT_CRITICAL_ISR() esp_os_exit_critical_isr(&hcd_lock) +#define HCD_ENTER_CRITICAL() esp_os_enter_critical(&hcd_lock) +#define HCD_EXIT_CRITICAL() esp_os_exit_critical(&hcd_lock) #define HCD_CHECK(cond, ret_val) ({ \ if (!(cond)) { \ @@ -270,7 +272,6 @@ typedef struct { intr_handle_t isr_hdl; } hcd_obj_t; -static portMUX_TYPE hcd_lock = portMUX_INITIALIZER_UNLOCKED; static hcd_obj_t *s_hcd_obj = NULL; // Note: "s_" is for the static pointer // ------------------------------------------------- Forward Declare --------------------------------------------------- diff --git a/components/usb/hub.c b/components/usb/hub.c index 079a18f351a..2d328bcf39a 100644 --- a/components/usb/hub.c +++ b/components/usb/hub.c @@ -9,10 +9,9 @@ #include #include #include -#include "freertos/FreeRTOS.h" -#include "freertos/portmacro.h" #include "esp_err.h" #include "esp_heap_caps.h" +#include "esp_private/critical_section.h" #include "esp_log.h" #include "usb_private.h" #include "hcd.h" @@ -107,16 +106,16 @@ typedef struct { } hub_driver_t; static hub_driver_t *p_hub_driver_obj = NULL; -static portMUX_TYPE hub_driver_lock = portMUX_INITIALIZER_UNLOCKED; const char *HUB_DRIVER_TAG = "HUB"; -#define HUB_DRIVER_ENTER_CRITICAL_ISR() portENTER_CRITICAL_ISR(&hub_driver_lock) -#define HUB_DRIVER_EXIT_CRITICAL_ISR() portEXIT_CRITICAL_ISR(&hub_driver_lock) -#define HUB_DRIVER_ENTER_CRITICAL() portENTER_CRITICAL(&hub_driver_lock) -#define HUB_DRIVER_EXIT_CRITICAL() portEXIT_CRITICAL(&hub_driver_lock) -#define HUB_DRIVER_ENTER_CRITICAL_SAFE() portENTER_CRITICAL_SAFE(&hub_driver_lock) -#define HUB_DRIVER_EXIT_CRITICAL_SAFE() portEXIT_CRITICAL_SAFE(&hub_driver_lock) +DEFINE_CRIT_SECTION_LOCK_STATIC(hub_driver_lock); +#define HUB_DRIVER_ENTER_CRITICAL_ISR() esp_os_enter_critical_isr(&hub_driver_lock) +#define HUB_DRIVER_EXIT_CRITICAL_ISR() esp_os_exit_critical_isr(&hub_driver_lock) +#define HUB_DRIVER_ENTER_CRITICAL() esp_os_enter_critical(&hub_driver_lock) +#define HUB_DRIVER_EXIT_CRITICAL() esp_os_exit_critical(&hub_driver_lock) +#define HUB_DRIVER_ENTER_CRITICAL_SAFE() esp_os_enter_critical_safe(&hub_driver_lock) +#define HUB_DRIVER_EXIT_CRITICAL_SAFE() esp_os_exit_critical_safe(&hub_driver_lock) #define HUB_DRIVER_CHECK(cond, ret_val) ({ \ if (!(cond)) { \ diff --git a/components/usb/usb_host.c b/components/usb/usb_host.c index 644a5e777e5..bc41bab9089 100644 --- a/components/usb/usb_host.c +++ b/components/usb/usb_host.c @@ -16,6 +16,7 @@ Warning: The USB Host Library API is still a beta version and may be subject to #include "freertos/task.h" #include "freertos/queue.h" #include "freertos/semphr.h" +#include "esp_private/critical_section.h" #include "esp_err.h" #include "esp_log.h" #include "esp_heap_caps.h" @@ -26,14 +27,13 @@ Warning: The USB Host Library API is still a beta version and may be subject to #include "esp_private/usb_phy.h" #include "usb/usb_host.h" -static portMUX_TYPE host_lock = portMUX_INITIALIZER_UNLOCKED; - -#define HOST_ENTER_CRITICAL_ISR() portENTER_CRITICAL_ISR(&host_lock) -#define HOST_EXIT_CRITICAL_ISR() portEXIT_CRITICAL_ISR(&host_lock) -#define HOST_ENTER_CRITICAL() portENTER_CRITICAL(&host_lock) -#define HOST_EXIT_CRITICAL() portEXIT_CRITICAL(&host_lock) -#define HOST_ENTER_CRITICAL_SAFE() portENTER_CRITICAL_SAFE(&host_lock) -#define HOST_EXIT_CRITICAL_SAFE() portEXIT_CRITICAL_SAFE(&host_lock) +DEFINE_CRIT_SECTION_LOCK_STATIC(host_lock); +#define HOST_ENTER_CRITICAL_ISR() esp_os_enter_critical_isr(&host_lock) +#define HOST_EXIT_CRITICAL_ISR() esp_os_exit_critical_isr(&host_lock) +#define HOST_ENTER_CRITICAL() esp_os_enter_critical(&host_lock) +#define HOST_EXIT_CRITICAL() esp_os_exit_critical(&host_lock) +#define HOST_ENTER_CRITICAL_SAFE() esp_os_enter_critical_safe(&host_lock) +#define HOST_EXIT_CRITICAL_SAFE() esp_os_exit_critical_safe(&host_lock) #define HOST_CHECK(cond, ret_val) ({ \ if (!(cond)) { \ diff --git a/components/usb/usb_phy.c b/components/usb/usb_phy.c index 7ae5e5f3826..220e6317321 100644 --- a/components/usb/usb_phy.c +++ b/components/usb/usb_phy.c @@ -6,11 +6,11 @@ #include #include -#include "freertos/FreeRTOS.h" #include "esp_log.h" #include "esp_check.h" #include "esp_private/periph_ctrl.h" #include "esp_private/usb_phy.h" +#include "esp_private/critical_section.h" #include "soc/usb_dwc_periph.h" #include "hal/usb_wrap_hal.h" #include "hal/usb_serial_jtag_hal.h" @@ -61,7 +61,10 @@ typedef struct { } usb_iopin_dsc_t; static phy_ctrl_obj_t *p_phy_ctrl_obj = NULL; -static portMUX_TYPE phy_spinlock = portMUX_INITIALIZER_UNLOCKED; + +DEFINE_CRIT_SECTION_LOCK_STATIC(phy_spinlock); +#define PHY_ENTER_CRITICAL() esp_os_enter_critical(&phy_spinlock) +#define PHY_EXIT_CRITICAL() esp_os_exit_critical(&phy_spinlock) static esp_err_t phy_iopins_configure(const usb_iopin_dsc_t *usb_periph_iopins, int iopins_num) { @@ -235,29 +238,29 @@ esp_err_t usb_phy_action(usb_phy_handle_t handle, usb_phy_action_t action) static esp_err_t usb_phy_install(void) { - portENTER_CRITICAL(&phy_spinlock); + PHY_ENTER_CRITICAL(); if (p_phy_ctrl_obj) { // p_phy_ctrl_obj already installed, return immediately - portEXIT_CRITICAL(&phy_spinlock); + PHY_EXIT_CRITICAL(); return ESP_OK; } - portEXIT_CRITICAL(&phy_spinlock); + PHY_EXIT_CRITICAL(); esp_err_t ret = ESP_OK; phy_ctrl_obj_t *phy_ctrl_obj = (phy_ctrl_obj_t *) calloc(1, sizeof(phy_ctrl_obj_t)); ESP_GOTO_ON_FALSE(phy_ctrl_obj, ESP_ERR_NO_MEM, cleanup, USBPHY_TAG, "no mem for USB_PHY driver"); - portENTER_CRITICAL(&phy_spinlock); + PHY_ENTER_CRITICAL(); if (!p_phy_ctrl_obj) { p_phy_ctrl_obj = phy_ctrl_obj; p_phy_ctrl_obj->ref_count = 0; } else { // p_phy_ctrl_obj already installed, need to free resource - portEXIT_CRITICAL(&phy_spinlock); + PHY_EXIT_CRITICAL(); goto cleanup; } // Enable USB peripheral and reset the register - portEXIT_CRITICAL(&phy_spinlock); + PHY_EXIT_CRITICAL(); USB_WRAP_RCC_ATOMIC() { usb_wrap_ll_enable_bus_clock(true); usb_wrap_ll_reset_register(); @@ -281,7 +284,7 @@ esp_err_t usb_new_phy(const usb_phy_config_t *config, usb_phy_handle_t *handle_r phy_context_t *phy_context = (phy_context_t *) calloc(1, sizeof(phy_context_t)); ESP_GOTO_ON_FALSE(phy_context, ESP_ERR_NO_MEM, cleanup, USBPHY_TAG, "no mem for phy context"); - portENTER_CRITICAL(&phy_spinlock); + PHY_ENTER_CRITICAL(); usb_phy_get_phy_status(config->target, &phy_context->status); if (phy_context->status == USB_PHY_STATUS_FREE) { new_phy = true; @@ -292,7 +295,7 @@ esp_err_t usb_new_phy(const usb_phy_config_t *config, usb_phy_handle_t *handle_r p_phy_ctrl_obj->internal_phy = phy_context; } } - portEXIT_CRITICAL(&phy_spinlock); + PHY_EXIT_CRITICAL(); ESP_GOTO_ON_FALSE(new_phy, ESP_ERR_INVALID_STATE, cleanup, USBPHY_TAG, "selected PHY is in use"); phy_context->target = config->target; @@ -354,7 +357,7 @@ esp_err_t usb_new_phy(const usb_phy_config_t *config, usb_phy_handle_t *handle_r static void phy_uninstall(void) { phy_ctrl_obj_t *p_phy_ctrl_obj_free = NULL; - portENTER_CRITICAL(&phy_spinlock); + PHY_ENTER_CRITICAL(); if (p_phy_ctrl_obj->ref_count == 0) { p_phy_ctrl_obj_free = p_phy_ctrl_obj; p_phy_ctrl_obj = NULL; @@ -363,7 +366,7 @@ static void phy_uninstall(void) usb_wrap_ll_enable_bus_clock(false); } } - portEXIT_CRITICAL(&phy_spinlock); + PHY_EXIT_CRITICAL(); free(p_phy_ctrl_obj_free); } @@ -371,7 +374,7 @@ esp_err_t usb_del_phy(usb_phy_handle_t handle) { ESP_RETURN_ON_FALSE(handle, ESP_ERR_INVALID_ARG, USBPHY_TAG, "handle argument is invalid"); - portENTER_CRITICAL(&phy_spinlock); + PHY_ENTER_CRITICAL(); p_phy_ctrl_obj->ref_count--; if (handle->target == USB_PHY_TARGET_EXT) { p_phy_ctrl_obj->external_phy = NULL; @@ -380,7 +383,7 @@ esp_err_t usb_del_phy(usb_phy_handle_t handle) usb_wrap_hal_phy_disable_pull_override(&handle->wrap_hal); p_phy_ctrl_obj->internal_phy = NULL; } - portEXIT_CRITICAL(&phy_spinlock); + PHY_EXIT_CRITICAL(); free(handle->iopins); free(handle); phy_uninstall(); diff --git a/components/usb/usbh.c b/components/usb/usbh.c index c515fc01ca5..54355ace682 100644 --- a/components/usb/usbh.c +++ b/components/usb/usbh.c @@ -10,9 +10,8 @@ #include #include #include "freertos/FreeRTOS.h" -#include "freertos/portmacro.h" -#include "freertos/task.h" #include "freertos/semphr.h" +#include "esp_private/critical_section.h" #include "esp_err.h" #include "esp_log.h" #include "esp_heap_caps.h" @@ -117,16 +116,15 @@ typedef struct { static usbh_t *p_usbh_obj = NULL; -static portMUX_TYPE usbh_lock = portMUX_INITIALIZER_UNLOCKED; - const char *USBH_TAG = "USBH"; -#define USBH_ENTER_CRITICAL_ISR() portENTER_CRITICAL_ISR(&usbh_lock) -#define USBH_EXIT_CRITICAL_ISR() portEXIT_CRITICAL_ISR(&usbh_lock) -#define USBH_ENTER_CRITICAL() portENTER_CRITICAL(&usbh_lock) -#define USBH_EXIT_CRITICAL() portEXIT_CRITICAL(&usbh_lock) -#define USBH_ENTER_CRITICAL_SAFE() portENTER_CRITICAL_SAFE(&usbh_lock) -#define USBH_EXIT_CRITICAL_SAFE() portEXIT_CRITICAL_SAFE(&usbh_lock) +DEFINE_CRIT_SECTION_LOCK_STATIC(usbh_lock); +#define USBH_ENTER_CRITICAL_ISR() esp_os_enter_critical_isr(&usbh_lock) +#define USBH_EXIT_CRITICAL_ISR() esp_os_exit_critical_isr(&usbh_lock) +#define USBH_ENTER_CRITICAL() esp_os_enter_critical(&usbh_lock) +#define USBH_EXIT_CRITICAL() esp_os_exit_critical(&usbh_lock) +#define USBH_ENTER_CRITICAL_SAFE() esp_os_enter_critical_safe(&usbh_lock) +#define USBH_EXIT_CRITICAL_SAFE() esp_os_exit_critical_safe(&usbh_lock) #define USBH_CHECK(cond, ret_val) ({ \ if (!(cond)) { \ From 213c318e624a2886f5b839ce0d43872a309236d5 Mon Sep 17 00:00:00 2001 From: Erhan Kurubas Date: Tue, 8 Oct 2024 13:08:41 +0200 Subject: [PATCH 058/472] fix(apptrace): replace esp32p4 ctrl block into noncache-able TCM memory --- components/app_trace/port/riscv/port.c | 14 ++++++++++---- examples/system/.build-test-rules.yml | 4 ---- examples/system/app_trace_basic/README.md | 4 ++-- 3 files changed, 12 insertions(+), 10 deletions(-) diff --git a/components/app_trace/port/riscv/port.c b/components/app_trace/port/riscv/port.c index 3e5ceca966c..14fe223623c 100644 --- a/components/app_trace/port/riscv/port.c +++ b/components/app_trace/port/riscv/port.c @@ -57,7 +57,13 @@ static bool esp_apptrace_riscv_host_data_pending(void); const static char *TAG = "esp_apptrace"; -static esp_apptrace_riscv_ctrl_block_t s_tracing_ctrl[CONFIG_FREERTOS_NUMBER_OF_CORES]; +#if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE +#define APPTRACE_DRAM_ATTR TCM_DRAM_ATTR +#else +#define APPTRACE_DRAM_ATTR +#endif + +static APPTRACE_DRAM_ATTR esp_apptrace_riscv_ctrl_block_t s_tracing_ctrl[CONFIG_FREERTOS_NUMBER_OF_CORES]; esp_apptrace_hw_t *esp_apptrace_jtag_hw_get(void **data) { @@ -92,7 +98,7 @@ esp_apptrace_hw_t *esp_apptrace_jtag_hw_get(void **data) } /* Advertises apptrace control block address to host. - This function can be overriden with custom implementation, + This function can be overridden with custom implementation, e.g. OpenOCD flasher stub use own implementation of it. */ __attribute__((weak)) int esp_apptrace_advertise_ctrl_block(void *ctrl_block_addr) { @@ -103,7 +109,7 @@ __attribute__((weak)) int esp_apptrace_advertise_ctrl_block(void *ctrl_block_add } /* Returns up buffers config. - This function can be overriden with custom implementation, + This function can be overridden with custom implementation, e.g. OpenOCD flasher stub use own implementation of it. */ __attribute__((weak)) void esp_apptrace_get_up_buffers(esp_apptrace_mem_block_t mem_blocks_cfg[2]) { @@ -165,7 +171,7 @@ static esp_err_t esp_apptrace_riscv_init(esp_apptrace_riscv_data_t *hw_data) } // notify host about control block address int res = esp_apptrace_advertise_ctrl_block(&s_tracing_ctrl[core_id]); - assert(res == 0 && "Falied to send config to host!"); + assert(res == 0 && "Failed to send config to host!"); return ESP_OK; } diff --git a/examples/system/.build-test-rules.yml b/examples/system/.build-test-rules.yml index 3152b243fde..d0cf7db720b 100644 --- a/examples/system/.build-test-rules.yml +++ b/examples/system/.build-test-rules.yml @@ -1,10 +1,6 @@ # Documentation: .gitlab/ci/README.md#manifest-file-to-control-the-buildtest-apps examples/system/app_trace_basic: - disable: - - if: IDF_TARGET == "esp32p4" - temporary: true - reason: not ready yet. IDF-8107 disable_test: - if: IDF_TARGET in ["esp32c6", "esp32h2", "esp32p4", "esp32c5", "esp32c61"] temporary: true diff --git a/examples/system/app_trace_basic/README.md b/examples/system/app_trace_basic/README.md index 72abab1b8da..151e992d1a4 100644 --- a/examples/system/app_trace_basic/README.md +++ b/examples/system/app_trace_basic/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- | # Application Level Tracing Example (Basic) From 1723b413d64ec63bec2ee84cc36200f76ff844ab Mon Sep 17 00:00:00 2001 From: WanqQixiang Date: Wed, 9 Oct 2024 10:11:21 +0800 Subject: [PATCH 059/472] fix(openthread): Add check for ip address in DNS external resolve hook --- components/openthread/src/esp_openthread_dns64.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/components/openthread/src/esp_openthread_dns64.c b/components/openthread/src/esp_openthread_dns64.c index 79faa1ad922..86d8b5fb0e5 100644 --- a/components/openthread/src/esp_openthread_dns64.c +++ b/components/openthread/src/esp_openthread_dns64.c @@ -75,7 +75,7 @@ static void dns_found_handler(const char *name, const ip_addr_t *ipaddr, void *c { dns_resolve_entry_t *resolve_entry = (dns_resolve_entry_t *)callback_arg; if (resolve_entry && resolve_entry->found) { - if (lwip_strnicmp(name, resolve_entry->name, sizeof(resolve_entry->name)) == 0) { + if (ipaddr && lwip_strnicmp(name, resolve_entry->name, sizeof(resolve_entry->name)) == 0) { ip_addr_t ipaddr_copy = *ipaddr; ip6_addr_t nat64_prefix; if (ipaddr_copy.type == IPADDR_TYPE_V4 && esp_openthread_get_nat64_prefix(&nat64_prefix) == ESP_OK) { From 858d0647e8344900daaef75d135c57476ee7579a Mon Sep 17 00:00:00 2001 From: zhoupeng Date: Tue, 8 Oct 2024 17:06:00 +0800 Subject: [PATCH 060/472] fix(pwr_glitch): Add Comment and only add power glitch reset support on esp32c5 ECO0 --- .../bootloader_support/src/esp32c5/bootloader_esp32c5.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/components/bootloader_support/src/esp32c5/bootloader_esp32c5.c b/components/bootloader_support/src/esp32c5/bootloader_esp32c5.c index 02b83fc1e8c..d7258e52c2c 100644 --- a/components/bootloader_support/src/esp32c5/bootloader_esp32c5.c +++ b/components/bootloader_support/src/esp32c5/bootloader_esp32c5.c @@ -94,8 +94,11 @@ static inline void bootloader_ana_reset_config(void) { //Enable BOD reset (mode1) brownout_ll_ana_reset_enable(true); - uint8_t power_glitch_dref = 0; - bootloader_power_glitch_reset_config(true, power_glitch_dref); + if (efuse_hal_chip_revision() == 0) { + // decrease power glitch reset voltage to avoid start the glitch reset + uint8_t power_glitch_dref = 0; + bootloader_power_glitch_reset_config(true, power_glitch_dref); + } } esp_err_t bootloader_init(void) From fa0c7636a515aba96212cb5e6ae60af9de5fa28d Mon Sep 17 00:00:00 2001 From: wanckl Date: Fri, 27 Sep 2024 11:41:59 +0800 Subject: [PATCH 061/472] test(driver_i2s): p4 and c5 enable multi dut test --- .../test_apps/.build-test-rules.yml | 4 ---- .../i2s_multi_dev/main/test_i2s_multi_dev.c | 8 ++++++- .../i2s_multi_dev/pytest_i2s_multi_dev.py | 3 ++- .../test_apps/test_inc/test_i2s.h | 22 +++---------------- 4 files changed, 12 insertions(+), 25 deletions(-) diff --git a/components/esp_driver_i2s/test_apps/.build-test-rules.yml b/components/esp_driver_i2s/test_apps/.build-test-rules.yml index 8ecfb0daeb2..12a74125b1f 100644 --- a/components/esp_driver_i2s/test_apps/.build-test-rules.yml +++ b/components/esp_driver_i2s/test_apps/.build-test-rules.yml @@ -11,10 +11,6 @@ components/esp_driver_i2s/test_apps/i2s_multi_dev: disable: - if: SOC_I2S_SUPPORTED != 1 - if: SOC_I2S_HW_VERSION_2 != 1 - disable_test: - - if: IDF_TARGET in ["esp32p4", "esp32c5"] # TODO: [ESP32C5] IDF- 10321 - temporary: true - reason: lack of runners depends_components: - esp_driver_i2s diff --git a/components/esp_driver_i2s/test_apps/i2s_multi_dev/main/test_i2s_multi_dev.c b/components/esp_driver_i2s/test_apps/i2s_multi_dev/main/test_i2s_multi_dev.c index 3f2737b0b35..5a6d0251173 100644 --- a/components/esp_driver_i2s/test_apps/i2s_multi_dev/main/test_i2s_multi_dev.c +++ b/components/esp_driver_i2s/test_apps/i2s_multi_dev/main/test_i2s_multi_dev.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Unlicense OR CC0-1.0 */ @@ -161,6 +161,9 @@ static void test_i2s_tdm_slave(uint32_t sample_rate, i2s_data_bit_width_t bit_wi if (sample_rate >= 96000) { i2s_tdm_config.clk_cfg.bclk_div = 12; } +#if SOC_I2S_SUPPORTS_APLL + i2s_tdm_config.clk_cfg.clk_src = I2S_CLK_SRC_APLL; +#endif TEST_ESP_OK(i2s_channel_init_tdm_mode(i2s_tdm_tx_handle, &i2s_tdm_config)); TEST_ESP_OK(i2s_channel_init_tdm_mode(i2s_tdm_rx_handle, &i2s_tdm_config)); @@ -254,6 +257,8 @@ static void test_i2s_tdm_slave_48k_16bits_8slots(void) TEST_CASE_MULTIPLE_DEVICES("I2S_TDM_full_duplex_test_in_48k_16bits_8slots", "[I2S_TDM]", test_i2s_tdm_master_48k_16bits_8slots, test_i2s_tdm_slave_48k_16bits_8slots); +// The max clock source APLL on P4 is 125M which can't satisfy the following config in slave mode +#if !CONFIG_IDF_TARGET_ESP32P4 static void test_i2s_tdm_master_96k_16bits_4slots(void) { test_i2s_tdm_master(96000, I2S_DATA_BIT_WIDTH_16BIT, I2S_TDM_SLOT0 | I2S_TDM_SLOT1 | I2S_TDM_SLOT2 | I2S_TDM_SLOT3); @@ -266,6 +271,7 @@ static void test_i2s_tdm_slave_96k_16bits_4slots(void) TEST_CASE_MULTIPLE_DEVICES("I2S_TDM_full_duplex_test_in_96k_16bits_4slots", "[I2S_TDM]", test_i2s_tdm_master_96k_16bits_4slots, test_i2s_tdm_slave_96k_16bits_4slots); +#endif // !CONFIG_IDF_TARGET_ESP32P4 #endif // !CONFIG_IDF_TARGET_ESP32H2 static void test_i2s_external_clk_src(bool is_master, bool is_external) diff --git a/components/esp_driver_i2s/test_apps/i2s_multi_dev/pytest_i2s_multi_dev.py b/components/esp_driver_i2s/test_apps/i2s_multi_dev/pytest_i2s_multi_dev.py index 3d53063d50e..000bb65e399 100644 --- a/components/esp_driver_i2s/test_apps/i2s_multi_dev/pytest_i2s_multi_dev.py +++ b/components/esp_driver_i2s/test_apps/i2s_multi_dev/pytest_i2s_multi_dev.py @@ -5,9 +5,10 @@ @pytest.mark.esp32s3 @pytest.mark.esp32c3 -# @pytest.mark.esp32c5 # TODO: [ESP32C5] IDF- 10321 +@pytest.mark.esp32c5 @pytest.mark.esp32c6 @pytest.mark.esp32h2 +@pytest.mark.esp32p4 @pytest.mark.generic_multi_device @pytest.mark.parametrize('count', [ 2, diff --git a/components/esp_driver_i2s/test_apps/test_inc/test_i2s.h b/components/esp_driver_i2s/test_apps/test_inc/test_i2s.h index cbf25114cea..0be715c450b 100644 --- a/components/esp_driver_i2s/test_apps/test_inc/test_i2s.h +++ b/components/esp_driver_i2s/test_apps/test_inc/test_i2s.h @@ -22,23 +22,7 @@ extern "C" { #define SLAVE_WS_IO 22 #define DATA_IN_IO 19 #define DATA_OUT_IO 18 -#elif CONFIG_IDF_TARGET_ESP32S2 -#define MASTER_MCK_IO 0 -#define MASTER_BCK_IO 4 -#define MASTER_WS_IO 5 -#define SLAVE_BCK_IO 14 -#define SLAVE_WS_IO 15 -#define DATA_IN_IO 19 -#define DATA_OUT_IO 18 -#elif CONFIG_IDF_TARGET_ESP32C3 -#define MASTER_MCK_IO 0 -#define MASTER_BCK_IO 4 -#define MASTER_WS_IO 5 -#define SLAVE_BCK_IO 14 -#define SLAVE_WS_IO 15 -#define DATA_IN_IO 19 -#define DATA_OUT_IO 18 -#elif CONFIG_IDF_TARGET_ESP32S3 +#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3 #define MASTER_MCK_IO 0 #define MASTER_BCK_IO 4 #define MASTER_WS_IO 5 @@ -50,8 +34,8 @@ extern "C" { #define MASTER_MCK_IO 51 #define MASTER_BCK_IO 45 #define MASTER_WS_IO 46 -#define SLAVE_BCK_IO 22 -#define SLAVE_WS_IO 23 +#define SLAVE_BCK_IO 49 +#define SLAVE_WS_IO 50 #define DATA_IN_IO 47 #define DATA_OUT_IO 48 #elif CONFIG_IDF_TARGET_ESP32C5 From 71dfc8ea17eab5758d77f71ca4ecf0611cbc1721 Mon Sep 17 00:00:00 2001 From: "wangtao@espressif.com" Date: Wed, 9 Oct 2024 11:36:56 +0800 Subject: [PATCH 062/472] fix(wifi): fix send deauth mac list lock free issue --- components/esp_wifi/lib | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/components/esp_wifi/lib b/components/esp_wifi/lib index 6c96f870aee..49187f511a1 160000 --- a/components/esp_wifi/lib +++ b/components/esp_wifi/lib @@ -1 +1 @@ -Subproject commit 6c96f870aeec6bf57b321d0fd52f95086e9e7e80 +Subproject commit 49187f511a1843ea2c3a7abc69c1186d9ea0ae7d From 514155de3b0c44bf9c3b00c31f64b3b40bc36c83 Mon Sep 17 00:00:00 2001 From: zhanghaipeng Date: Sat, 28 Sep 2024 15:33:27 +0800 Subject: [PATCH 063/472] fix(ble/bluedroid): Fixed BLE handle check for GATT API --- .../bt/host/bluedroid/api/esp_gattc_api.c | 54 +++++++++++++++---- 1 file changed, 45 insertions(+), 9 deletions(-) diff --git a/components/bt/host/bluedroid/api/esp_gattc_api.c b/components/bt/host/bluedroid/api/esp_gattc_api.c index 5f078b28098..904fb32a0cc 100644 --- a/components/bt/host/bluedroid/api/esp_gattc_api.c +++ b/components/bt/host/bluedroid/api/esp_gattc_api.c @@ -363,10 +363,14 @@ esp_err_t esp_ble_gattc_read_char (esp_gatt_if_t gattc_if, } if (L2CA_CheckIsCongest(L2CAP_ATT_CID, p_tcb->peer_bda)) { - LOG_DEBUG("%s, the l2cap chanel is congest.", __func__); + LOG_DEBUG("%s, the l2cap channel is congest.", __func__); return ESP_FAIL; } + if (handle == 0) { + return ESP_GATT_INVALID_HANDLE; + } + msg.sig = BTC_SIG_API_CALL; msg.pid = BTC_PID_GATTC; msg.act = BTC_GATTC_ACT_READ_CHAR; @@ -400,10 +404,14 @@ esp_err_t esp_ble_gattc_read_by_type (esp_gatt_if_t gattc_if, } if (L2CA_CheckIsCongest(L2CAP_ATT_CID, p_tcb->peer_bda)) { - LOG_DEBUG("%s, the l2cap chanel is congest.", __func__); + LOG_DEBUG("%s, the l2cap channel is congest.", __func__); return ESP_FAIL; } + if (start_handle == 0 || end_handle == 0) { + return ESP_GATT_INVALID_HANDLE; + } + msg.sig = BTC_SIG_API_CALL; msg.pid = BTC_PID_GATTC; msg.act = BTC_GATTC_ACT_READ_BY_TYPE; @@ -432,7 +440,7 @@ esp_err_t esp_ble_gattc_read_multiple(esp_gatt_if_t gattc_if, } if (L2CA_CheckIsCongest(L2CAP_ATT_CID, p_tcb->peer_bda)) { - LOG_DEBUG("%s, the l2cap chanel is congest.", __func__); + LOG_DEBUG("%s, the l2cap channel is congest.", __func__); return ESP_FAIL; } @@ -468,7 +476,7 @@ esp_err_t esp_ble_gattc_read_multiple_variable(esp_gatt_if_t gattc_if, } if (L2CA_CheckIsCongest(L2CAP_ATT_CID, p_tcb->peer_bda)) { - LOG_DEBUG("%s, the l2cap chanel is congest.", __func__); + LOG_DEBUG("%s, the l2cap channel is congest.", __func__); return ESP_FAIL; } @@ -504,10 +512,14 @@ esp_err_t esp_ble_gattc_read_char_descr (esp_gatt_if_t gattc_if, } if (L2CA_CheckIsCongest(L2CAP_ATT_CID, p_tcb->peer_bda)) { - LOG_DEBUG("%s, the l2cap chanel is congest.", __func__); + LOG_DEBUG("%s, the l2cap channel is congest.", __func__); return ESP_FAIL; } + if (handle == 0) { + return ESP_GATT_INVALID_HANDLE; + } + msg.sig = BTC_SIG_API_CALL; msg.pid = BTC_PID_GATTC; msg.act = BTC_GATTC_ACT_READ_CHAR_DESCR; @@ -537,10 +549,14 @@ esp_err_t esp_ble_gattc_write_char(esp_gatt_if_t gattc_if, } if (L2CA_CheckIsCongest(L2CAP_ATT_CID, p_tcb->peer_bda)) { - LOG_DEBUG("%s, the l2cap chanel is congest.", __func__); + LOG_DEBUG("%s, the l2cap channel is congest.", __func__); return ESP_FAIL; } + if (handle == 0) { + return ESP_GATT_INVALID_HANDLE; + } + msg.sig = BTC_SIG_API_CALL; msg.pid = BTC_PID_GATTC; msg.act = BTC_GATTC_ACT_WRITE_CHAR; @@ -576,10 +592,14 @@ esp_err_t esp_ble_gattc_write_char_descr (esp_gatt_if_t gattc_if, } if (L2CA_CheckIsCongest(L2CAP_ATT_CID, p_tcb->peer_bda)) { - LOG_DEBUG("%s, the l2cap chanel is congest.", __func__); + LOG_DEBUG("%s, the l2cap channel is congest.", __func__); return ESP_FAIL; } + if (handle == 0) { + return ESP_GATT_INVALID_HANDLE; + } + msg.sig = BTC_SIG_API_CALL; msg.pid = BTC_PID_GATTC; msg.act = BTC_GATTC_ACT_WRITE_CHAR_DESCR; @@ -615,10 +635,14 @@ esp_err_t esp_ble_gattc_prepare_write(esp_gatt_if_t gattc_if, } if (L2CA_CheckIsCongest(L2CAP_ATT_CID, p_tcb->peer_bda)) { - LOG_DEBUG("%s, the l2cap chanel is congest.", __func__); + LOG_DEBUG("%s, the l2cap channel is congest.", __func__); return ESP_FAIL; } + if (handle == 0) { + return ESP_GATT_INVALID_HANDLE; + } + msg.sig = BTC_SIG_API_CALL; msg.pid = BTC_PID_GATTC; msg.act = BTC_GATTC_ACT_PREPARE_WRITE; @@ -652,10 +676,14 @@ esp_err_t esp_ble_gattc_prepare_write_char_descr(esp_gatt_if_t gattc_if, } if (L2CA_CheckIsCongest(L2CAP_ATT_CID, p_tcb->peer_bda)) { - LOG_DEBUG("%s, the l2cap chanel is congest.", __func__); + LOG_DEBUG("%s, the l2cap channel is congest.", __func__); return ESP_FAIL; } + if (handle == 0) { + return ESP_GATT_INVALID_HANDLE; + } + msg.sig = BTC_SIG_API_CALL; msg.pid = BTC_PID_GATTC; msg.act = BTC_GATTC_ACT_PREPARE_WRITE_CHAR_DESCR; @@ -694,6 +722,10 @@ esp_err_t esp_ble_gattc_register_for_notify (esp_gatt_if_t gattc_if, ESP_BLUEDROID_STATUS_CHECK(ESP_BLUEDROID_STATUS_ENABLED); + if (handle == 0) { + return ESP_GATT_INVALID_HANDLE; + } + msg.sig = BTC_SIG_API_CALL; msg.pid = BTC_PID_GATTC; msg.act = BTC_GATTC_ACT_REG_FOR_NOTIFY; @@ -712,6 +744,10 @@ esp_err_t esp_ble_gattc_unregister_for_notify (esp_gatt_if_t gattc_if, ESP_BLUEDROID_STATUS_CHECK(ESP_BLUEDROID_STATUS_ENABLED); + if (handle == 0) { + return ESP_GATT_INVALID_HANDLE; + } + msg.sig = BTC_SIG_API_CALL; msg.pid = BTC_PID_GATTC; msg.act = BTC_GATTC_ACT_UNREG_FOR_NOTIFY; From 9e3a846356b9bed3b3189bbb212e943f3a89a156 Mon Sep 17 00:00:00 2001 From: "harshal.patil" Date: Thu, 3 Oct 2024 11:23:24 +0530 Subject: [PATCH 064/472] ci(esp_security): Enable crypto drivers test app build only for supported targets --- .../test_apps/.build-test-rules.yml | 6 ++---- .../test_apps/crypto_drivers/README.md | 4 ++-- .../crypto_drivers/main/CMakeLists.txt | 17 +++++++++++++---- .../test_apps/crypto_drivers/main/test_ds.c | 3 --- .../test_apps/crypto_drivers/main/test_hmac.c | 4 ---- .../crypto_drivers/main/test_key_mgr.c | 2 -- .../crypto_drivers/pytest_crypto_drivers.py | 17 ++++++++--------- 7 files changed, 25 insertions(+), 28 deletions(-) diff --git a/components/esp_security/test_apps/.build-test-rules.yml b/components/esp_security/test_apps/.build-test-rules.yml index abfc86a2c5d..baac155ce35 100644 --- a/components/esp_security/test_apps/.build-test-rules.yml +++ b/components/esp_security/test_apps/.build-test-rules.yml @@ -1,7 +1,5 @@ # Documentation: .gitlab/ci/README.md#manifest-file-to-control-the-buildtest-apps components/esp_security/test_apps/crypto_drivers: - disable: - - if: IDF_TARGET in ["esp32c61"] - temporary: true - reason: Support for ESP32C61 is yet to be added. + enable: + - if: ((SOC_HMAC_SUPPORTED == 1) or (SOC_DIG_SIGN_SUPPORTED == 1)) or (SOC_KEY_MANAGER_SUPPORTED == 1) diff --git a/components/esp_security/test_apps/crypto_drivers/README.md b/components/esp_security/test_apps/crypto_drivers/README.md index 351f5fdebc7..1dfe1331b41 100644 --- a/components/esp_security/test_apps/crypto_drivers/README.md +++ b/components/esp_security/test_apps/crypto_drivers/README.md @@ -1,3 +1,3 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | +| ----------------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | diff --git a/components/esp_security/test_apps/crypto_drivers/main/CMakeLists.txt b/components/esp_security/test_apps/crypto_drivers/main/CMakeLists.txt index 67485675547..b6ae16ae0a9 100644 --- a/components/esp_security/test_apps/crypto_drivers/main/CMakeLists.txt +++ b/components/esp_security/test_apps/crypto_drivers/main/CMakeLists.txt @@ -1,7 +1,16 @@ -set(srcs "test_app_main.c" - "test_ds.c" - "test_hmac.c" - "test_key_mgr.c") +set(srcs "test_app_main.c") + +if(CONFIG_SOC_HMAC_SUPPORTED) + list(APPEND srcs "test_hmac.c") +endif() + +if(CONFIG_SOC_DIG_SIGN_SUPPORTED) + list(APPEND srcs "test_ds.c") +endif() + +if(CONFIG_SOC_KEY_MANAGER_SUPPORTED) + list(APPEND srcs "test_key_mgr.c") +endif() idf_component_register(SRCS ${srcs} REQUIRES unity efuse test_utils spi_flash esp_security diff --git a/components/esp_security/test_apps/crypto_drivers/main/test_ds.c b/components/esp_security/test_apps/crypto_drivers/main/test_ds.c index d631c7dd358..576e23fd627 100644 --- a/components/esp_security/test_apps/crypto_drivers/main/test_ds.c +++ b/components/esp_security/test_apps/crypto_drivers/main/test_ds.c @@ -8,8 +8,6 @@ #include "unity.h" #include "soc/soc_caps.h" - -#if SOC_DIG_SIGN_SUPPORTED #include "rom/efuse.h" #if CONFIG_IDF_TARGET_ESP32S2 #include "esp32s2/rom/digital_signature.h" @@ -438,4 +436,3 @@ TEST_CASE("Digital Signature Invalid Data (FPGA only)", "[hw_crypto] [ds]") } #endif // CONFIG_IDF_ENV_FPGA -#endif // SOC_DIG_SIGN_SUPPORTED diff --git a/components/esp_security/test_apps/crypto_drivers/main/test_hmac.c b/components/esp_security/test_apps/crypto_drivers/main/test_hmac.c index 9c20debc529..61fd9fb1c03 100644 --- a/components/esp_security/test_apps/crypto_drivers/main/test_hmac.c +++ b/components/esp_security/test_apps/crypto_drivers/main/test_hmac.c @@ -8,8 +8,6 @@ #include "esp_efuse.h" #include "esp_efuse_table.h" #include "esp_log.h" - -#if SOC_HMAC_SUPPORTED #include "esp_hmac.h" #if CONFIG_IDF_ENV_FPGA @@ -1315,5 +1313,3 @@ TEST_CASE("HMAC key out of range", "[hw_crypto]") TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, esp_hmac_calculate(HMAC_KEY0 - 1, message, 47, hmac)); TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, esp_hmac_calculate(HMAC_KEY5 + 1, message, 47, hmac)); } - -#endif // SOC_HMAC_SUPPORTED diff --git a/components/esp_security/test_apps/crypto_drivers/main/test_key_mgr.c b/components/esp_security/test_apps/crypto_drivers/main/test_key_mgr.c index 4484a9fde5e..1fdb5b28f19 100644 --- a/components/esp_security/test_apps/crypto_drivers/main/test_key_mgr.c +++ b/components/esp_security/test_apps/crypto_drivers/main/test_key_mgr.c @@ -7,7 +7,6 @@ #include "unity.h" #include "soc/soc_caps.h" -#if SOC_KEY_MANAGER_SUPPORTED #include "esp_partition.h" #include "esp_flash.h" #include "esp_log.h" @@ -143,4 +142,3 @@ TEST_CASE("Key Manager random mode: ECDSA key deployment", "[hw_crypto] [key_mgr esp_ret = esp_key_mgr_deploy_key_in_random_mode(&key_config, &key_info); TEST_ASSERT_EQUAL(ESP_OK, esp_ret); } -#endif diff --git a/components/esp_security/test_apps/crypto_drivers/pytest_crypto_drivers.py b/components/esp_security/test_apps/crypto_drivers/pytest_crypto_drivers.py index e0709970c50..44435595f06 100644 --- a/components/esp_security/test_apps/crypto_drivers/pytest_crypto_drivers.py +++ b/components/esp_security/test_apps/crypto_drivers/pytest_crypto_drivers.py @@ -1,17 +1,16 @@ -# SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD +# SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD # SPDX-License-Identifier: CC0-1.0 import pytest from pytest_embedded import Dut +@pytest.mark.esp32s2 +@pytest.mark.esp32s3 +@pytest.mark.esp32c3 +@pytest.mark.esp32c6 +@pytest.mark.esp32h2 +@pytest.mark.esp32p4 +@pytest.mark.esp32c5 @pytest.mark.generic -@pytest.mark.temp_skip_ci(targets=['esp32c61'], reason='Support for ESP32C61 is yet to be added.') # TODO: [ESP32C61] IDF-10987 -@pytest.mark.parametrize( - 'config', - [ - pytest.param('default', marks=[pytest.mark.supported_targets]), - ], - indirect=True, -) def test_crypto_drivers(dut: Dut) -> None: dut.run_all_single_board_cases(timeout=180) From e12c261b1b2713aaa374f3fcb67a7f2ebf66d5eb Mon Sep 17 00:00:00 2001 From: "harshal.patil" Date: Thu, 3 Oct 2024 15:17:22 +0530 Subject: [PATCH 065/472] ci(esp_security): Add config to enable FPGA-related tests --- .../test_apps/crypto_drivers/main/Kconfig.projbuild | 9 +++++++++ .../esp_security/test_apps/crypto_drivers/main/test_ds.c | 4 ++-- .../test_apps/crypto_drivers/main/test_hmac.c | 4 ++-- components/hal/test_apps/crypto/README.md | 3 ++- components/hal/test_apps/crypto/main/Kconfig.projbuild | 8 ++++++++ components/hal/test_apps/crypto/main/app_main.c | 4 ++-- .../test_apps/crypto/main/key_manager/test_key_manager.c | 6 +++--- 7 files changed, 28 insertions(+), 10 deletions(-) create mode 100644 components/esp_security/test_apps/crypto_drivers/main/Kconfig.projbuild diff --git a/components/esp_security/test_apps/crypto_drivers/main/Kconfig.projbuild b/components/esp_security/test_apps/crypto_drivers/main/Kconfig.projbuild new file mode 100644 index 00000000000..7cdf8c00fa6 --- /dev/null +++ b/components/esp_security/test_apps/crypto_drivers/main/Kconfig.projbuild @@ -0,0 +1,9 @@ +menu "ESP Security Tests" + config ESP_SECURITY_ENABLE_FPGA_TESTS + bool "Allow enabling the esp_security tests that require burning efuses" + default y if IDF_ENV_FPGA + default n + help + This includes the esp_security tests that actually require burning some efuses. + It is better to run these tests on an FPGA to avoid mistakenly burning eFuses. +endmenu diff --git a/components/esp_security/test_apps/crypto_drivers/main/test_ds.c b/components/esp_security/test_apps/crypto_drivers/main/test_ds.c index 576e23fd627..13d53308be6 100644 --- a/components/esp_security/test_apps/crypto_drivers/main/test_ds.c +++ b/components/esp_security/test_apps/crypto_drivers/main/test_ds.c @@ -255,7 +255,7 @@ TEST_CASE("Digital Signature Blocking HMAC key out of range", "[hw_crypto] [ds]" TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, esp_ds_sign(message, &ds_data, HMAC_KEY0 - 1, signature_data)); } -#if CONFIG_IDF_ENV_FPGA +#if CONFIG_ESP_SECURITY_ENABLE_FPGA_TESTS static void burn_hmac_keys(void) { @@ -435,4 +435,4 @@ TEST_CASE("Digital Signature Invalid Data (FPGA only)", "[hw_crypto] [ds]") } } -#endif // CONFIG_IDF_ENV_FPGA +#endif // CONFIG_ESP_SECURITY_ENABLE_FPGA_TESTS diff --git a/components/esp_security/test_apps/crypto_drivers/main/test_hmac.c b/components/esp_security/test_apps/crypto_drivers/main/test_hmac.c index 61fd9fb1c03..8f8ccf39ef4 100644 --- a/components/esp_security/test_apps/crypto_drivers/main/test_hmac.c +++ b/components/esp_security/test_apps/crypto_drivers/main/test_hmac.c @@ -10,7 +10,7 @@ #include "esp_log.h" #include "esp_hmac.h" -#if CONFIG_IDF_ENV_FPGA +#if CONFIG_ESP_SECURITY_ENABLE_FPGA_TESTS /* Allow testing varying message lengths (truncating the same message) for various results */ @@ -1297,7 +1297,7 @@ TEST_CASE("HMAC 'upstream' wait lock", "[hw_crypto]") } } -#endif // CONFIG_IDF_ENV_FPGA +#endif // CONFIG_ESP_SECURITY_ENABLE_FPGA_TESTS /** * This test is just a parameter test and does not write any keys to efuse. diff --git a/components/hal/test_apps/crypto/README.md b/components/hal/test_apps/crypto/README.md index 4e2c6f4f57a..3b25adda8ab 100644 --- a/components/hal/test_apps/crypto/README.md +++ b/components/hal/test_apps/crypto/README.md @@ -67,7 +67,8 @@ This contains tests for the following features of the crypto peripherals: - SHA-512/256 - SHA-512/t -> **_NOTE:_** The verification tests for the HMAC and Digital Signature peripherals would get exercised in only in an FPGA environment. +> **_NOTE:_** The verification tests for the HMAC and Digital Signature peripherals would get exercised only by enabling the example config in an FPGA environment. + # Burning the HMAC key The HMAC tests need an HMAC key to be burned in the `BLOCK_KEY3` and `BLOCK_KEY4` of the efuses. As this verification application is independent of the efuse component, the user needs to manually burn the keys and their key purposes using `espefuse.py`. diff --git a/components/hal/test_apps/crypto/main/Kconfig.projbuild b/components/hal/test_apps/crypto/main/Kconfig.projbuild index 051c5bae14b..ee68e84f19b 100644 --- a/components/hal/test_apps/crypto/main/Kconfig.projbuild +++ b/components/hal/test_apps/crypto/main/Kconfig.projbuild @@ -1,6 +1,14 @@ menu "Test App Configuration" + config CRYPTO_TEST_APP_ENABLE_FPGA_TESTS + bool "Allow enabling the crypto tests that require burning efuses" + default y if IDF_ENV_FPGA + default n + help + This includes the crypto tests that actually require burning some efuses. + It is better to run these tests on an FPGA to avoid mistakenly burning eFuses. + config CRYPTO_TEST_APP_ENABLE_DS_TESTS bool "Enable DS Peripheral test cases" default y diff --git a/components/hal/test_apps/crypto/main/app_main.c b/components/hal/test_apps/crypto/main/app_main.c index 460445a343a..87dcee3d8ef 100644 --- a/components/hal/test_apps/crypto/main/app_main.c +++ b/components/hal/test_apps/crypto/main/app_main.c @@ -34,7 +34,7 @@ static void run_all_tests(void) RUN_TEST_GROUP(key_manager); #endif -#if CONFIG_IDF_ENV_FPGA +#if CONFIG_CRYPTO_TEST_APP_ENABLE_FPGA_TESTS #if CONFIG_SOC_HMAC_SUPPORTED && CONFIG_CRYPTO_TEST_APP_ENABLE_HMAC_TESTS RUN_TEST_GROUP(hmac); @@ -48,7 +48,7 @@ static void run_all_tests(void) RUN_TEST_GROUP(ecdsa) #endif -#endif /* CONFIG_IDF_ENV_FPGA */ +#endif /* CONFIG_CRYPTO_TEST_APP_ENABLE_FPGA_TESTS */ } static void test_task(void *pvParameters) diff --git a/components/hal/test_apps/crypto/main/key_manager/test_key_manager.c b/components/hal/test_apps/crypto/main/key_manager/test_key_manager.c index ca424eb1321..2def4096e8f 100644 --- a/components/hal/test_apps/crypto/main/key_manager/test_key_manager.c +++ b/components/hal/test_apps/crypto/main/key_manager/test_key_manager.c @@ -263,7 +263,7 @@ static void key_mgr_test_ecdsa_random_mode(void) TEST_ASSERT_EQUAL(ESP_OK, esp_key_mgr_deactivate_key(key_recovery_info.key_type)); } -#if CONFIG_IDF_ENV_FPGA +#if CONFIG_CRYPTO_TEST_APP_ENABLE_FPGA_TESTS static void test_xts_aes_key_random_mode(void) { @@ -351,7 +351,7 @@ TEST(key_manager, ecdsa_key_random_deployment) key_mgr_test_ecdsa_random_mode(); } -#if CONFIG_IDF_ENV_FPGA +#if CONFIG_CRYPTO_TEST_APP_ENABLE_FPGA_TESTS TEST(key_manager, xts_key_random_deployment) { key_mgr_test_xts_aes_128_random_mode(); @@ -367,7 +367,7 @@ TEST_GROUP_RUNNER(key_manager) RUN_TEST_CASE(key_manager, xts_key_ecdh0_deployment); RUN_TEST_CASE(key_manager, ecdsa_key_ecdh0_deployment); RUN_TEST_CASE(key_manager, ecdsa_key_random_deployment); -#if CONFIG_IDF_ENV_FPGA +#if CONFIG_CRYPTO_TEST_APP_ENABLE_FPGA_TESTS RUN_TEST_CASE(key_manager, xts_key_random_deployment); #endif From aebf7009193b0c60c43681841f5dbd40c4428f87 Mon Sep 17 00:00:00 2001 From: morris Date: Fri, 27 Sep 2024 16:34:13 +0800 Subject: [PATCH 066/472] refactor(freertos): rename SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY and move to freertos --- .../esp_common/sdkconfig.ci.xip_psram_esp32p4 | 2 +- .../esp_common/sdkconfig.ci.xip_psram_esp32s2 | 2 +- .../esp_common/sdkconfig.ci.xip_psram_esp32s3 | 2 +- components/esp_hw_support/esp_memory_utils.c | 2 +- .../esp_hw_support/include/esp_memory_utils.h | 4 +- .../esp_pm/sdkconfig.ci.pm_xip_psram_esp32s2 | 2 +- .../esp_pm/sdkconfig.ci.pm_xip_psram_esp32s3 | 2 +- components/esp_psram/esp32/Kconfig.spiram | 13 -- components/esp_psram/esp32c5/Kconfig.spiram | 10 -- components/esp_psram/esp32c61/Kconfig.spiram | 10 -- components/esp_psram/esp32p4/Kconfig.spiram | 11 -- components/esp_psram/esp32s2/Kconfig.spiram | 10 -- components/esp_psram/esp32s3/Kconfig.spiram | 10 -- .../esp_psram/test_apps/.build-test-rules.yml | 8 - .../psram_no_malloc_task_stack/CMakeLists.txt | 7 - .../psram_no_malloc_task_stack/README.md | 2 - .../main/CMakeLists.txt | 3 - .../main/test_psram_no_malloc_task_stack.c | 82 --------- .../pytest_psram_no_malloc_task_stack.py | 11 -- .../sdkconfig.defaults | 4 - .../port/soc/esp32/system_internal.c | 4 +- .../port/soc/esp32s2/system_internal.c | 4 +- .../port/soc/esp32s3/system_internal.c | 4 +- .../main/test_reset_reason.c | 4 +- .../esp_system_unity_tests/sdkconfig.ci.psram | 2 +- .../sdkconfig.ci.psram_with_pd_top | 2 +- components/espcoredump/Kconfig | 2 +- .../src/port/riscv/core_dump_port.c | 6 +- .../src/port/xtensa/core_dump_port.c | 2 +- components/freertos/Kconfig | 27 +++ components/freertos/heap_idf.c | 2 +- components/freertos/sdkconfig.rename | 1 + .../freertos/misc/test_idf_additions.c | 4 +- .../test_apps/freertos/pytest_freertos.py | 2 +- .../test_apps/freertos/sdkconfig.ci.psram | 2 +- components/mbedtls/test_apps/main/test_aes.c | 168 +++++++++--------- .../mbedtls/test_apps/main/test_mbedtls_sha.c | 4 +- .../test_apps/sdkconfig.ci.psram_all_ext | 2 +- .../sdkconfig.ci.psram_all_ext_esp32p4_200m | 2 +- docs/en/api-guides/external-ram.rst | 2 +- .../inc/external-ram-esp32-notes.rst | 2 +- docs/zh_CN/api-guides/external-ram.rst | 2 +- .../inc/external-ram-esp32-notes.rst | 2 +- .../system/panic/main/include/test_panic.h | 2 +- .../system/panic/main/test_app_main.c | 2 +- .../test_apps/system/panic/main/test_panic.c | 4 +- ...g.ci.coredump_flash_extram_stack_bss_esp32 | 2 +- ...ci.coredump_flash_extram_stack_bss_esp32s2 | 2 +- ...ci.coredump_flash_extram_stack_bss_esp32s3 | 2 +- ....ci.coredump_flash_extram_stack_heap_esp32 | 2 +- ...i.coredump_flash_extram_stack_heap_esp32s2 | 2 +- ...i.coredump_flash_extram_stack_heap_esp32s3 | 2 +- 52 files changed, 158 insertions(+), 311 deletions(-) delete mode 100644 components/esp_psram/test_apps/psram_no_malloc_task_stack/CMakeLists.txt delete mode 100644 components/esp_psram/test_apps/psram_no_malloc_task_stack/README.md delete mode 100644 components/esp_psram/test_apps/psram_no_malloc_task_stack/main/CMakeLists.txt delete mode 100644 components/esp_psram/test_apps/psram_no_malloc_task_stack/main/test_psram_no_malloc_task_stack.c delete mode 100644 components/esp_psram/test_apps/psram_no_malloc_task_stack/pytest_psram_no_malloc_task_stack.py delete mode 100644 components/esp_psram/test_apps/psram_no_malloc_task_stack/sdkconfig.defaults diff --git a/components/esp_common/test_apps/esp_common/sdkconfig.ci.xip_psram_esp32p4 b/components/esp_common/test_apps/esp_common/sdkconfig.ci.xip_psram_esp32p4 index 0d33cfbf8f4..5470efa1208 100644 --- a/components/esp_common/test_apps/esp_common/sdkconfig.ci.xip_psram_esp32p4 +++ b/components/esp_common/test_apps/esp_common/sdkconfig.ci.xip_psram_esp32p4 @@ -5,4 +5,4 @@ CONFIG_SPIRAM=y CONFIG_SPIRAM_XIP_FROM_PSRAM=y CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY=y CONFIG_SPIRAM_ALLOW_NOINIT_SEG_EXTERNAL_MEMORY=y -CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY=y +CONFIG_FREERTOS_TASK_CREATE_ALLOW_EXT_MEM=y diff --git a/components/esp_common/test_apps/esp_common/sdkconfig.ci.xip_psram_esp32s2 b/components/esp_common/test_apps/esp_common/sdkconfig.ci.xip_psram_esp32s2 index fd9b7e865c3..3c7418b55d9 100644 --- a/components/esp_common/test_apps/esp_common/sdkconfig.ci.xip_psram_esp32s2 +++ b/components/esp_common/test_apps/esp_common/sdkconfig.ci.xip_psram_esp32s2 @@ -5,4 +5,4 @@ CONFIG_SPIRAM=y CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY=y CONFIG_SPIRAM_ALLOW_NOINIT_SEG_EXTERNAL_MEMORY=y CONFIG_SPIRAM_RODATA=y -CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY=y +CONFIG_FREERTOS_TASK_CREATE_ALLOW_EXT_MEM=y diff --git a/components/esp_common/test_apps/esp_common/sdkconfig.ci.xip_psram_esp32s3 b/components/esp_common/test_apps/esp_common/sdkconfig.ci.xip_psram_esp32s3 index 3b1db1f233f..53125cb9b8b 100644 --- a/components/esp_common/test_apps/esp_common/sdkconfig.ci.xip_psram_esp32s3 +++ b/components/esp_common/test_apps/esp_common/sdkconfig.ci.xip_psram_esp32s3 @@ -5,4 +5,4 @@ CONFIG_SPIRAM=y CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY=y CONFIG_SPIRAM_ALLOW_NOINIT_SEG_EXTERNAL_MEMORY=y CONFIG_SPIRAM_RODATA=y -CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY=y +CONFIG_FREERTOS_TASK_CREATE_ALLOW_EXT_MEM=y diff --git a/components/esp_hw_support/esp_memory_utils.c b/components/esp_hw_support/esp_memory_utils.c index 766ca5a2c18..62627cbcb97 100644 --- a/components/esp_hw_support/esp_memory_utils.c +++ b/components/esp_hw_support/esp_memory_utils.c @@ -67,7 +67,7 @@ bool esp_ptr_external_ram(const void *p) #endif //CONFIG_SPIRAM } -#if CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY +#if CONFIG_FREERTOS_TASK_CREATE_ALLOW_EXT_MEM bool esp_stack_ptr_in_extram(uint32_t sp) { //Check if stack ptr is on PSRAM, and 16 byte aligned. diff --git a/components/esp_hw_support/include/esp_memory_utils.h b/components/esp_hw_support/include/esp_memory_utils.h index 427dc4912ea..d17d6f26965 100644 --- a/components/esp_hw_support/include/esp_memory_utils.h +++ b/components/esp_hw_support/include/esp_memory_utils.h @@ -352,7 +352,7 @@ inline static bool esp_stack_ptr_in_dram(uint32_t sp) return !(sp < SOC_DRAM_LOW + 0x10 || sp > SOC_DRAM_HIGH - 0x10 || ((sp & 0xF) != 0)); } -#if CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY +#if CONFIG_FREERTOS_TASK_CREATE_ALLOW_EXT_MEM /** * @brief Check if the stack pointer is in external ram * @@ -374,7 +374,7 @@ __attribute__((always_inline)) inline static bool esp_stack_ptr_is_sane(uint32_t sp) { return esp_stack_ptr_in_dram(sp) -#if CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY +#if CONFIG_FREERTOS_TASK_CREATE_ALLOW_EXT_MEM || esp_stack_ptr_in_extram(sp) #endif #if CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP diff --git a/components/esp_pm/test_apps/esp_pm/sdkconfig.ci.pm_xip_psram_esp32s2 b/components/esp_pm/test_apps/esp_pm/sdkconfig.ci.pm_xip_psram_esp32s2 index 51f7a5a0451..8345d72b95f 100644 --- a/components/esp_pm/test_apps/esp_pm/sdkconfig.ci.pm_xip_psram_esp32s2 +++ b/components/esp_pm/test_apps/esp_pm/sdkconfig.ci.pm_xip_psram_esp32s2 @@ -1,6 +1,6 @@ CONFIG_IDF_TARGET="esp32s2" CONFIG_SPIRAM=y -CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY=y +CONFIG_FREERTOS_TASK_CREATE_ALLOW_EXT_MEM=y CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY=y CONFIG_SPIRAM_FETCH_INSTRUCTIONS=y CONFIG_SPIRAM_RODATA=y diff --git a/components/esp_pm/test_apps/esp_pm/sdkconfig.ci.pm_xip_psram_esp32s3 b/components/esp_pm/test_apps/esp_pm/sdkconfig.ci.pm_xip_psram_esp32s3 index 31f93b58766..7669b3050c8 100644 --- a/components/esp_pm/test_apps/esp_pm/sdkconfig.ci.pm_xip_psram_esp32s3 +++ b/components/esp_pm/test_apps/esp_pm/sdkconfig.ci.pm_xip_psram_esp32s3 @@ -1,6 +1,6 @@ CONFIG_IDF_TARGET="esp32s3" CONFIG_SPIRAM=y -CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY=y +CONFIG_FREERTOS_TASK_CREATE_ALLOW_EXT_MEM=y CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY=y CONFIG_SPIRAM_FETCH_INSTRUCTIONS=y CONFIG_SPIRAM_RODATA=y diff --git a/components/esp_psram/esp32/Kconfig.spiram b/components/esp_psram/esp32/Kconfig.spiram index f7eb1725a45..04c32ff5faf 100644 --- a/components/esp_psram/esp32/Kconfig.spiram +++ b/components/esp_psram/esp32/Kconfig.spiram @@ -259,19 +259,6 @@ menu "SPI RAM config" any himem calls, the reservation is not done and the original amount of memory will be available to malloc/esp_heap_alloc_caps. - config SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY - bool "Allow external memory as an argument to xTaskCreateStatic" - default n - depends on SPIRAM_USE_CAPS_ALLOC || SPIRAM_USE_MALLOC - help - Because some bits of the ESP32 code environment cannot be recompiled with the cache workaround, - normally tasks cannot be safely run with their stack residing in external memory; for this reason - xTaskCreate (and related task creaton functions) always allocate stack in internal memory and - xTaskCreateStatic will check if the memory passed to it is in internal memory. If you have a task that - needs a large amount of stack and does not call on ROM code in any way (no direct calls, but also no - Bluetooth/WiFi), you can try enable this to cause xTaskCreateStatic to allow tasks stack in external - memory. - choice SPIRAM_OCCUPY_SPI_HOST prompt "SPI host to use for 32MBit PSRAM" default SPIRAM_OCCUPY_VSPI_HOST diff --git a/components/esp_psram/esp32c5/Kconfig.spiram b/components/esp_psram/esp32c5/Kconfig.spiram index 75e0ec8da9d..ca941e8f1d5 100644 --- a/components/esp_psram/esp32c5/Kconfig.spiram +++ b/components/esp_psram/esp32c5/Kconfig.spiram @@ -17,16 +17,6 @@ menu "SPI RAM config" endchoice - config SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY - bool "Allow external memory as an argument to xTaskCreateStatic" - default y - help - Accessing memory in SPIRAM has certain restrictions, so task stacks allocated by xTaskCreate - are by default allocated from internal RAM. - - This option allows for passing memory allocated from SPIRAM to be passed to xTaskCreateStatic. - This should only be used for tasks where the stack is never accessed while the cache is disabled. - choice SPIRAM_SPEED prompt "Set RAM clock speed" default SPIRAM_SPEED_40M diff --git a/components/esp_psram/esp32c61/Kconfig.spiram b/components/esp_psram/esp32c61/Kconfig.spiram index 0ef577983fd..fefbd96463c 100644 --- a/components/esp_psram/esp32c61/Kconfig.spiram +++ b/components/esp_psram/esp32c61/Kconfig.spiram @@ -17,16 +17,6 @@ menu "SPI RAM config" endchoice - config SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY - bool "Allow external memory as an argument to xTaskCreateStatic" - default y - help - Accessing memory in SPIRAM has certain restrictions, so task stacks allocated by xTaskCreate - are by default allocated from internal RAM. - - This option allows for passing memory allocated from SPIRAM to be passed to xTaskCreateStatic. - This should only be used for tasks where the stack is never accessed while the cache is disabled. - choice SPIRAM_SPEED prompt "Set RAM clock speed" default SPIRAM_SPEED_40M diff --git a/components/esp_psram/esp32p4/Kconfig.spiram b/components/esp_psram/esp32p4/Kconfig.spiram index f17fb795eec..821188d2f3f 100644 --- a/components/esp_psram/esp32p4/Kconfig.spiram +++ b/components/esp_psram/esp32p4/Kconfig.spiram @@ -91,17 +91,6 @@ menu "PSRAM config" If enabled, 1/8 of the PSRAM total size will be reserved for error-correcting code. - config SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY - bool "Allow external memory as an argument to xTaskCreateStatic" - default y - help - Accessing memory in PSRAM has certain restrictions, so task stacks allocated by xTaskCreate - are by default allocated from internal RAM. - - This option allows for passing memory allocated from PSRAM to be passed to xTaskCreateStatic. - This should only be used for tasks where the stack is never accessed while the L2Cache is - disabled, e.g. during SPI Flash operations - source "$IDF_PATH/components/esp_psram/Kconfig.spiram.common" # insert non-chip-specific items here endmenu diff --git a/components/esp_psram/esp32s2/Kconfig.spiram b/components/esp_psram/esp32s2/Kconfig.spiram index 1af865756aa..6135222a5af 100644 --- a/components/esp_psram/esp32s2/Kconfig.spiram +++ b/components/esp_psram/esp32s2/Kconfig.spiram @@ -29,16 +29,6 @@ menu "SPI RAM config" bool "ESP-PSRAM64 or LY68L6400" endchoice - config SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY - bool "Allow external memory as an argument to xTaskCreateStatic" - default y - help - Accessing memory in SPIRAM has certain restrictions, so task stacks allocated by xTaskCreate - are by default allocated from internal RAM. - - This option allows for passing memory allocated from SPIRAM to be passed to xTaskCreateStatic. - This should only be used for tasks where the stack is never accessed while the cache is disabled. - config SPIRAM_CLK_IO int default 30 diff --git a/components/esp_psram/esp32s3/Kconfig.spiram b/components/esp_psram/esp32s3/Kconfig.spiram index 46634376297..1bf74912d0c 100644 --- a/components/esp_psram/esp32s3/Kconfig.spiram +++ b/components/esp_psram/esp32s3/Kconfig.spiram @@ -38,16 +38,6 @@ menu "SPI RAM config" bool "ESP-PSRAM64 , LY68L6400 or APS6408" endchoice - config SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY - bool "Allow external memory as an argument to xTaskCreateStatic" - default y - help - Accessing memory in SPIRAM has certain restrictions, so task stacks allocated by xTaskCreate - are by default allocated from internal RAM. - - This option allows for passing memory allocated from SPIRAM to be passed to xTaskCreateStatic. - This should only be used for tasks where the stack is never accessed while the cache is disabled. - config SPIRAM_CLK_IO int default 30 diff --git a/components/esp_psram/test_apps/.build-test-rules.yml b/components/esp_psram/test_apps/.build-test-rules.yml index 88e27087346..c9b865f3012 100644 --- a/components/esp_psram/test_apps/.build-test-rules.yml +++ b/components/esp_psram/test_apps/.build-test-rules.yml @@ -9,11 +9,3 @@ components/esp_psram/test_apps/psram: - esp_driver_gpio - esp_driver_spi - spi_flash - - -components/esp_psram/test_apps/psram_no_malloc_task_stack: - enable: - - if: IDF_TARGET in ["esp32", "esp32p4"] - depends_components: - - esp_psram - - freertos diff --git a/components/esp_psram/test_apps/psram_no_malloc_task_stack/CMakeLists.txt b/components/esp_psram/test_apps/psram_no_malloc_task_stack/CMakeLists.txt deleted file mode 100644 index 9debb1681bd..00000000000 --- a/components/esp_psram/test_apps/psram_no_malloc_task_stack/CMakeLists.txt +++ /dev/null @@ -1,7 +0,0 @@ -# The following five lines of boilerplate have to be in your project's -# CMakeLists in this exact order for cmake to work correctly -cmake_minimum_required(VERSION 3.16) - -include($ENV{IDF_PATH}/tools/cmake/project.cmake) -set(COMPONENTS main) -project(psram_no_malloc_task_stack) diff --git a/components/esp_psram/test_apps/psram_no_malloc_task_stack/README.md b/components/esp_psram/test_apps/psram_no_malloc_task_stack/README.md deleted file mode 100644 index 4873c15b15b..00000000000 --- a/components/esp_psram/test_apps/psram_no_malloc_task_stack/README.md +++ /dev/null @@ -1,2 +0,0 @@ -| Supported Targets | ESP32 | ESP32-P4 | -| ----------------- | ----- | -------- | diff --git a/components/esp_psram/test_apps/psram_no_malloc_task_stack/main/CMakeLists.txt b/components/esp_psram/test_apps/psram_no_malloc_task_stack/main/CMakeLists.txt deleted file mode 100644 index 90939ebf279..00000000000 --- a/components/esp_psram/test_apps/psram_no_malloc_task_stack/main/CMakeLists.txt +++ /dev/null @@ -1,3 +0,0 @@ -idf_component_register(SRCS "test_psram_no_malloc_task_stack.c" - INCLUDE_DIRS "." - PRIV_REQUIRES unity esp_psram freertos heap) diff --git a/components/esp_psram/test_apps/psram_no_malloc_task_stack/main/test_psram_no_malloc_task_stack.c b/components/esp_psram/test_apps/psram_no_malloc_task_stack/main/test_psram_no_malloc_task_stack.c deleted file mode 100644 index d0c48c608d2..00000000000 --- a/components/esp_psram/test_apps/psram_no_malloc_task_stack/main/test_psram_no_malloc_task_stack.c +++ /dev/null @@ -1,82 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Unlicense OR CC0-1.0 - */ -#include -#include "esp_log.h" -#include "unity.h" -#include "unity_test_runner.h" -#include "unity_test_utils_memory.h" -#include "unity_test_utils.h" -#include "esp_heap_caps.h" -#include "esp_memory_utils.h" -#include "freertos/FreeRTOS.h" -#include "freertos/task.h" - -static const char* TAG = "psram_no_malloc_task_stack_test"; - -#define STACK_SIZE 4096 -#define WAIT_TICKS 2 -#define TEST_TASK_PRIORITY 6 // relatively high priority to let task finish quickly - -void setUp(void) -{ - unity_utils_set_leak_level(0); - unity_utils_record_free_mem(); -} - -void tearDown(void) -{ - unity_utils_evaluate_leaks(); -} - -static uint8_t *stack_memory; -static StaticTask_t *tcb_memory; -static bool is_external; -static SemaphoreHandle_t task_waiter; - -static void test_task(void *arg) -{ - int dummy = 47; - is_external = esp_ptr_external_ram(&dummy); - xSemaphoreGive(task_waiter); - vTaskDelay(portMAX_DELAY); -} - -TEST_CASE("FreeRTOS task with stack on SPIRAM works", "[psram]") -{ - stack_memory = heap_caps_malloc(STACK_SIZE, MALLOC_CAP_8BIT | MALLOC_CAP_SPIRAM); - TEST_ASSERT_NOT_NULL(stack_memory); - tcb_memory = heap_caps_malloc(sizeof(StaticTask_t), MALLOC_CAP_8BIT); - TEST_ASSERT_NOT_NULL(tcb_memory); - task_waiter = xSemaphoreCreateBinary(); - TEST_ASSERT_NOT_NULL(task_waiter); - - TaskHandle_t task = xTaskCreateStatic(test_task, - "heap caps static", - STACK_SIZE, - NULL, - TEST_TASK_PRIORITY, - stack_memory, - tcb_memory); - TEST_ASSERT_NOT_NULL(task); - - TEST_ASSERT_EQUAL(pdTRUE, xSemaphoreTake(task_waiter, WAIT_TICKS)); - - TEST_ASSERT_EQUAL(true, is_external); - - // use unity_utils_task_delete() to avoid deleting stack of a still running task - unity_utils_task_delete(task); - - vSemaphoreDelete(task_waiter); - heap_caps_free(tcb_memory); - heap_caps_free(stack_memory); -} - -void app_main(void) -{ - ESP_LOGI(TAG, "Running PSRAM task stack test app with SPIRAM_USE_CAPS_ALLOC"); - - unity_run_menu(); -} diff --git a/components/esp_psram/test_apps/psram_no_malloc_task_stack/pytest_psram_no_malloc_task_stack.py b/components/esp_psram/test_apps/psram_no_malloc_task_stack/pytest_psram_no_malloc_task_stack.py deleted file mode 100644 index 298f6f93c87..00000000000 --- a/components/esp_psram/test_apps/psram_no_malloc_task_stack/pytest_psram_no_malloc_task_stack.py +++ /dev/null @@ -1,11 +0,0 @@ -# SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD -# SPDX-License-Identifier: CC0-1.0 -import pytest -from pytest_embedded import Dut - - -@pytest.mark.esp32 -@pytest.mark.esp32p4 -@pytest.mark.generic -def test_psram_no_malloc_task_stack(dut: Dut) -> None: - dut.run_all_single_board_cases() diff --git a/components/esp_psram/test_apps/psram_no_malloc_task_stack/sdkconfig.defaults b/components/esp_psram/test_apps/psram_no_malloc_task_stack/sdkconfig.defaults deleted file mode 100644 index 5e67e04b0c4..00000000000 --- a/components/esp_psram/test_apps/psram_no_malloc_task_stack/sdkconfig.defaults +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_ESP_TASK_WDT_EN=n -CONFIG_SPIRAM=y -CONFIG_SPIRAM_USE_CAPS_ALLOC=y -CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY=y diff --git a/components/esp_system/port/soc/esp32/system_internal.c b/components/esp_system/port/soc/esp32/system_internal.c index 75cae925114..da76aa90d1a 100644 --- a/components/esp_system/port/soc/esp32/system_internal.c +++ b/components/esp_system/port/soc/esp32/system_internal.c @@ -97,9 +97,9 @@ void IRAM_ATTR esp_restart_noos(void) wdt_hal_disable(&wdt1_context); wdt_hal_write_protect_enable(&wdt1_context); -#ifdef CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY +#ifdef CONFIG_FREERTOS_TASK_CREATE_ALLOW_EXT_MEM if (esp_ptr_external_ram(esp_cpu_get_sp())) { - // If stack_addr is from External Memory (CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY is used) + // If stack_addr is from External Memory (CONFIG_FREERTOS_TASK_CREATE_ALLOW_EXT_MEM is used) // then need to switch SP to Internal Memory otherwise // we will get the "Cache disabled but cached memory region accessed" error after Cache_Read_Disable. uint32_t new_sp = SOC_DRAM_LOW + (SOC_DRAM_HIGH - SOC_DRAM_LOW) / 2; diff --git a/components/esp_system/port/soc/esp32s2/system_internal.c b/components/esp_system/port/soc/esp32s2/system_internal.c index 3de3bafdf18..8eb6c0325c2 100644 --- a/components/esp_system/port/soc/esp32s2/system_internal.c +++ b/components/esp_system/port/soc/esp32s2/system_internal.c @@ -85,9 +85,9 @@ void IRAM_ATTR esp_restart_noos(void) wdt_hal_disable(&wdt1_context); wdt_hal_write_protect_enable(&wdt1_context); -#ifdef CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY +#ifdef CONFIG_FREERTOS_TASK_CREATE_ALLOW_EXT_MEM if (esp_ptr_external_ram(esp_cpu_get_sp())) { - // If stack_addr is from External Memory (CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY is used) + // If stack_addr is from External Memory (CONFIG_FREERTOS_TASK_CREATE_ALLOW_EXT_MEM is used) // then need to switch SP to Internal Memory otherwise // we will get the "Cache disabled but cached memory region accessed" error after Cache_Read_Disable. uint32_t new_sp = ALIGN_DOWN(_bss_end, 16); diff --git a/components/esp_system/port/soc/esp32s3/system_internal.c b/components/esp_system/port/soc/esp32s3/system_internal.c index ebdaccbcb25..f0edae876cb 100644 --- a/components/esp_system/port/soc/esp32s3/system_internal.c +++ b/components/esp_system/port/soc/esp32s3/system_internal.c @@ -92,9 +92,9 @@ void IRAM_ATTR esp_restart_noos(void) wdt_hal_disable(&wdt1_context); wdt_hal_write_protect_enable(&wdt1_context); -#ifdef CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY +#ifdef CONFIG_FREERTOS_TASK_CREATE_ALLOW_EXT_MEM if (esp_ptr_external_ram(esp_cpu_get_sp())) { - // If stack_addr is from External Memory (CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY is used) + // If stack_addr is from External Memory (CONFIG_FREERTOS_TASK_CREATE_ALLOW_EXT_MEM is used) // then need to switch SP to Internal Memory otherwise // we will get the "Cache disabled but cached memory region accessed" error after Cache_Read_Disable. uint32_t new_sp = ALIGN_DOWN(_bss_end, 16); diff --git a/components/esp_system/test_apps/esp_system_unity_tests/main/test_reset_reason.c b/components/esp_system/test_apps/esp_system_unity_tests/main/test_reset_reason.c index 3008f15b62c..491c3299b45 100644 --- a/components/esp_system/test_apps/esp_system_unity_tests/main/test_reset_reason.c +++ b/components/esp_system/test_apps/esp_system_unity_tests/main/test_reset_reason.c @@ -318,7 +318,7 @@ TEST_CASE_MULTIPLE_STAGES("reset reason ESP_RST_BROWNOUT after brownout event", do_brownout, check_reset_reason_brownout); -#ifdef CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY +#ifdef CONFIG_FREERTOS_TASK_CREATE_ALLOW_EXT_MEM #ifndef CONFIG_FREERTOS_UNICORE #if CONFIG_IDF_TARGET_ARCH_XTENSA #include "xt_instr_macros.h" @@ -402,6 +402,6 @@ TEST_CASE_MULTIPLE_STAGES("reset reason ESP_RST_PANIC after an exception in a ta #endif //CONFIG_IDF_TARGET_ARCH_XTENSA #endif // CONFIG_FREERTOS_UNICORE -#endif // CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY +#endif // CONFIG_FREERTOS_TASK_CREATE_ALLOW_EXT_MEM /* Not tested here: ESP_RST_SDIO */ diff --git a/components/esp_system/test_apps/esp_system_unity_tests/sdkconfig.ci.psram b/components/esp_system/test_apps/esp_system_unity_tests/sdkconfig.ci.psram index 482bcd8baa5..f29df53fffe 100644 --- a/components/esp_system/test_apps/esp_system_unity_tests/sdkconfig.ci.psram +++ b/components/esp_system/test_apps/esp_system_unity_tests/sdkconfig.ci.psram @@ -1,2 +1,2 @@ CONFIG_SPIRAM=y -CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY=y +CONFIG_FREERTOS_TASK_CREATE_ALLOW_EXT_MEM=y diff --git a/components/esp_system/test_apps/esp_system_unity_tests/sdkconfig.ci.psram_with_pd_top b/components/esp_system/test_apps/esp_system_unity_tests/sdkconfig.ci.psram_with_pd_top index 440009beb18..d1b0d302443 100644 --- a/components/esp_system/test_apps/esp_system_unity_tests/sdkconfig.ci.psram_with_pd_top +++ b/components/esp_system/test_apps/esp_system_unity_tests/sdkconfig.ci.psram_with_pd_top @@ -1,4 +1,4 @@ CONFIG_SPIRAM=y -CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY=y +CONFIG_FREERTOS_TASK_CREATE_ALLOW_EXT_MEM=y CONFIG_PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP=y CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP=y diff --git a/components/espcoredump/Kconfig b/components/espcoredump/Kconfig index c19b0eabbae..90b806d96aa 100644 --- a/components/espcoredump/Kconfig +++ b/components/espcoredump/Kconfig @@ -108,7 +108,7 @@ menu "Core dump" config ESP_COREDUMP_USE_STACK_SIZE bool - default y if ESP_COREDUMP_ENABLE_TO_FLASH && SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY + default y if ESP_COREDUMP_ENABLE_TO_FLASH && FREERTOS_TASK_CREATE_ALLOW_EXT_MEM default n help Force the use of a custom DRAM stack for coredump when Task stacks can be in PSRAM. diff --git a/components/espcoredump/src/port/riscv/core_dump_port.c b/components/espcoredump/src/port/riscv/core_dump_port.c index 60a2ac39546..7d872ce62e5 100644 --- a/components/espcoredump/src/port/riscv/core_dump_port.c +++ b/components/espcoredump/src/port/riscv/core_dump_port.c @@ -37,7 +37,7 @@ const static char TAG[] __attribute__((unused)) = "esp_core_dump_port"; /** * Union representing the registers of the CPU as they will be written * in the core dump. - * Registers can be adressed with their names thanks to the structure, or as + * Registers can be addressed with their names thanks to the structure, or as * an array of 32 words. */ #define RISCV_GP_REGS_COUNT 32 @@ -222,7 +222,7 @@ uint32_t esp_core_dump_get_isr_stack_end(void) static inline bool esp_core_dump_task_stack_end_is_sane(uint32_t sp) { return esp_ptr_in_dram((void *)sp) -#if CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY +#if CONFIG_FREERTOS_TASK_CREATE_ALLOW_EXT_MEM || esp_stack_ptr_in_extram(sp) #endif #if CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP @@ -315,7 +315,7 @@ bool esp_core_dump_mem_seg_is_sane(uint32_t addr, uint32_t sz) } /** - * Get the task's registers dump when the panic occured. + * Get the task's registers dump when the panic occurred. * Returns the size, in bytes, of the data pointed by reg_dumps. * The data pointed by reg_dump are allocated statically, thus, they must be * used (or copied) before calling this function again. diff --git a/components/espcoredump/src/port/xtensa/core_dump_port.c b/components/espcoredump/src/port/xtensa/core_dump_port.c index cee4c1ebc1e..8efae60d576 100644 --- a/components/espcoredump/src/port/xtensa/core_dump_port.c +++ b/components/espcoredump/src/port/xtensa/core_dump_port.c @@ -299,7 +299,7 @@ uint32_t esp_core_dump_get_isr_stack_end(void) static inline bool esp_core_dump_task_stack_end_is_sane(uint32_t sp) { return esp_ptr_in_dram((void *)sp) -#if CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY +#if CONFIG_FREERTOS_TASK_CREATE_ALLOW_EXT_MEM || esp_stack_ptr_in_extram(sp) #endif #if CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP diff --git a/components/freertos/Kconfig b/components/freertos/Kconfig index ba0bb786f48..dec261a93c8 100644 --- a/components/freertos/Kconfig +++ b/components/freertos/Kconfig @@ -573,6 +573,33 @@ menu "FreeRTOS" endmenu # Port + menu "Extra" + + config FREERTOS_TASK_CREATE_ALLOW_EXT_MEM + depends on SPIRAM + depends on FREERTOS_SUPPORT_STATIC_ALLOCATION + bool "Allow external memory as an argument to xTaskCreateStatic (READ HELP)" + default n if IDF_TARGET_ESP32 + default y + help + Accessing memory in PSRAM has certain restrictions, so task stacks allocated by xTaskCreate + are by default allocated from internal RAM. + + This option allows for passing memory allocated from SPIRAM to be passed to xTaskCreateStatic. + This should only be used for tasks where the stack is never accessed while the cache is disabled. + + Extra notes for ESP32: + + Because some bits of the ESP32 code environment cannot be recompiled with the cache workaround, + normally tasks cannot be safely run with their stack residing in external memory; for this reason + xTaskCreate (and related task creation functions) always allocate stack in internal memory and + xTaskCreateStatic will check if the memory passed to it is in internal memory. + If you have a task that needs a large amount of stack and does not call on ROM code in any way + (no direct calls, but also no Bluetooth/WiFi), you can try enable this to + cause xTaskCreateStatic to allow tasks stack in external memory. + + endmenu # Extra + # Hidden or compatibility options config FREERTOS_PORT diff --git a/components/freertos/heap_idf.c b/components/freertos/heap_idf.c index 57ff845f742..60974047097 100644 --- a/components/freertos/heap_idf.c +++ b/components/freertos/heap_idf.c @@ -99,7 +99,7 @@ bool xPortcheckValidStackMem(const void * ptr) #if CONFIG_IDF_TARGET_LINUX return true; #else /* CONFIG_IDF_TARGET_LINUX */ -#ifdef CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY +#ifdef CONFIG_FREERTOS_TASK_CREATE_ALLOW_EXT_MEM return esp_ptr_byte_accessible(ptr); #else return esp_ptr_internal(ptr) && esp_ptr_byte_accessible(ptr); diff --git a/components/freertos/sdkconfig.rename b/components/freertos/sdkconfig.rename index 5720544d0e7..da4c466482a 100644 --- a/components/freertos/sdkconfig.rename +++ b/components/freertos/sdkconfig.rename @@ -5,3 +5,4 @@ CONFIG_ENABLE_STATIC_TASK_CLEAN_UP_HOOK CONFIG_FREERTOS_ENABLE_STATIC_TASK_C CONFIG_TIMER_TASK_PRIORITY CONFIG_FREERTOS_TIMER_TASK_PRIORITY CONFIG_TIMER_TASK_STACK_DEPTH CONFIG_FREERTOS_TIMER_TASK_STACK_DEPTH CONFIG_TIMER_QUEUE_LENGTH CONFIG_FREERTOS_TIMER_QUEUE_LENGTH +CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY CONFIG_FREERTOS_TASK_CREATE_ALLOW_EXT_MEM diff --git a/components/freertos/test_apps/freertos/misc/test_idf_additions.c b/components/freertos/test_apps/freertos/misc/test_idf_additions.c index 2f4d4a1fb76..5c5c3d69add 100644 --- a/components/freertos/test_apps/freertos/misc/test_idf_additions.c +++ b/components/freertos/test_apps/freertos/misc/test_idf_additions.c @@ -89,7 +89,7 @@ TEST_CASE("IDF additions: Task creation with memory caps and self deletion", "[f xTaskNotifyGive(task_handle); } -#if CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY +#if CONFIG_FREERTOS_TASK_CREATE_ALLOW_EXT_MEM TEST_CASE("IDF additions: Task creation with SPIRAM memory caps and self deletion stress test", "[freertos]") { @@ -115,7 +115,7 @@ TEST_CASE("IDF additions: Task creation with SPIRAM memory caps and self deletio } } -#endif /* CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY */ +#endif /* CONFIG_FREERTOS_TASK_CREATE_ALLOW_EXT_MEM */ #if ( CONFIG_FREERTOS_NUMBER_OF_CORES > 1 ) diff --git a/components/freertos/test_apps/freertos/pytest_freertos.py b/components/freertos/test_apps/freertos/pytest_freertos.py index ff27e9bc354..e2cdb05bd2c 100644 --- a/components/freertos/test_apps/freertos/pytest_freertos.py +++ b/components/freertos/test_apps/freertos/pytest_freertos.py @@ -7,7 +7,7 @@ CONFIGS = [ pytest.param('default', marks=[pytest.mark.supported_targets,]), pytest.param('freertos_options', marks=[pytest.mark.supported_targets]), - pytest.param('psram', marks=[pytest.mark.esp32]), + pytest.param('psram', marks=[pytest.mark.esp32, pytest.mark.esp32s3, pytest.mark.esp32p4, pytest.mark.esp32c5]), pytest.param('single_core', marks=[pytest.mark.esp32, pytest.mark.esp32p4]), # TODO: [ESP32C5] IDF-10335 # TODO: [ESP32C61] IDF-11146 diff --git a/components/freertos/test_apps/freertos/sdkconfig.ci.psram b/components/freertos/test_apps/freertos/sdkconfig.ci.psram index 1e330983154..776e127a2aa 100644 --- a/components/freertos/test_apps/freertos/sdkconfig.ci.psram +++ b/components/freertos/test_apps/freertos/sdkconfig.ci.psram @@ -5,7 +5,7 @@ CONFIG_IDF_TARGET="esp32" # Enable SPIRAM CONFIG_SPIRAM=y CONFIG_SPIRAM_OCCUPY_NO_HOST=y -CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY=y +CONFIG_FREERTOS_TASK_CREATE_ALLOW_EXT_MEM=y # Disable encrypted flash reads/writes to save IRAM in this build configuration CONFIG_SPI_FLASH_ENABLE_ENCRYPTED_READ_WRITE=n diff --git a/components/mbedtls/test_apps/main/test_aes.c b/components/mbedtls/test_apps/main/test_aes.c index 5ac71e82ec9..e95313c2665 100644 --- a/components/mbedtls/test_apps/main/test_aes.c +++ b/components/mbedtls/test_apps/main/test_aes.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Unlicense OR CC0-1.0 */ @@ -67,7 +67,7 @@ static const uint8_t iv[] = { print(as_c_array(plain)) ct = encryptor.update(plain) + encryptor.finalize() - print("Chipertext: {}".format(as_c_array(ct))) + print("Ciphertext: {}".format(as_c_array(ct))) */ TEST_CASE("mbedtls CBC AES-256 test", "[aes]") { @@ -85,11 +85,11 @@ TEST_CASE("mbedtls CBC AES-256 test", "[aes]") memcpy(nonce, iv, 16); // allocate internal memory - uint8_t *chipertext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL); + uint8_t *ciphertext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL); uint8_t *plaintext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL); uint8_t *decryptedtext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL); - TEST_ASSERT_NOT_NULL(chipertext); + TEST_ASSERT_NOT_NULL(ciphertext); TEST_ASSERT_NOT_NULL(plaintext); TEST_ASSERT_NOT_NULL(decryptedtext); @@ -100,19 +100,19 @@ TEST_CASE("mbedtls CBC AES-256 test", "[aes]") memset(decryptedtext, 0x0, SZ); // Encrypt - mbedtls_aes_crypt_cbc(&ctx, MBEDTLS_AES_ENCRYPT, SZ, nonce, plaintext, chipertext); - TEST_ASSERT_EQUAL_HEX8_ARRAY(expected_cipher_end, chipertext + SZ - 32, 32); + mbedtls_aes_crypt_cbc(&ctx, MBEDTLS_AES_ENCRYPT, SZ, nonce, plaintext, ciphertext); + TEST_ASSERT_EQUAL_HEX8_ARRAY(expected_cipher_end, ciphertext + SZ - 32, 32); // Decrypt memcpy(nonce, iv, 16); mbedtls_aes_setkey_dec(&ctx, key_256, 256); - mbedtls_aes_crypt_cbc(&ctx, MBEDTLS_AES_DECRYPT, SZ, nonce, chipertext, decryptedtext); + mbedtls_aes_crypt_cbc(&ctx, MBEDTLS_AES_DECRYPT, SZ, nonce, ciphertext, decryptedtext); TEST_ASSERT_EQUAL_HEX8_ARRAY(plaintext, decryptedtext, SZ); mbedtls_aes_free(&ctx); free(plaintext); - free(chipertext); + free(ciphertext); free(decryptedtext); } @@ -134,11 +134,11 @@ TEST_CASE("mbedtls CBC AES-256 DMA buffer align test", "[aes]") memcpy(nonce, iv, 16); // allocate internal memory - uint8_t *chipertext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL); + uint8_t *ciphertext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL); uint8_t *plaintext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL); uint8_t *decryptedtext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL); - TEST_ASSERT_NOT_NULL(chipertext); + TEST_ASSERT_NOT_NULL(ciphertext); TEST_ASSERT_NOT_NULL(plaintext); TEST_ASSERT_NOT_NULL(decryptedtext); @@ -149,19 +149,19 @@ TEST_CASE("mbedtls CBC AES-256 DMA buffer align test", "[aes]") memset(decryptedtext, 0x0, SZ); // Encrypt - mbedtls_aes_crypt_cbc(&ctx, MBEDTLS_AES_ENCRYPT, SZ, nonce, plaintext, chipertext); - TEST_ASSERT_EQUAL_HEX8_ARRAY(expected_cipher_end, chipertext + SZ - 32, 32); + mbedtls_aes_crypt_cbc(&ctx, MBEDTLS_AES_ENCRYPT, SZ, nonce, plaintext, ciphertext); + TEST_ASSERT_EQUAL_HEX8_ARRAY(expected_cipher_end, ciphertext + SZ - 32, 32); // Decrypt memcpy(nonce, iv, 16); mbedtls_aes_setkey_dec(&ctx, key_256, 256); - mbedtls_aes_crypt_cbc(&ctx, MBEDTLS_AES_DECRYPT, SZ, nonce, chipertext, decryptedtext); + mbedtls_aes_crypt_cbc(&ctx, MBEDTLS_AES_DECRYPT, SZ, nonce, ciphertext, decryptedtext); TEST_ASSERT_EQUAL_HEX8_ARRAY(plaintext, decryptedtext, SZ); mbedtls_aes_free(&ctx); free(plaintext); - free(chipertext); + free(ciphertext); free(decryptedtext); } @@ -183,11 +183,11 @@ TEST_CASE("mbedtls CTR AES-256 test", "[aes]") memcpy(nonce, iv, 16); // allocate internal memory - uint8_t *chipertext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL); + uint8_t *ciphertext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL); uint8_t *plaintext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL); uint8_t *decryptedtext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL); - TEST_ASSERT_NOT_NULL(chipertext); + TEST_ASSERT_NOT_NULL(ciphertext); TEST_ASSERT_NOT_NULL(plaintext); TEST_ASSERT_NOT_NULL(decryptedtext); @@ -198,19 +198,19 @@ TEST_CASE("mbedtls CTR AES-256 test", "[aes]") memset(decryptedtext, 0x0, SZ); // Encrypt - mbedtls_aes_crypt_ctr(&ctx, SZ, &nc_off, nonce, stream_block, plaintext, chipertext); - TEST_ASSERT_EQUAL_HEX8_ARRAY(expected_cipher_end, chipertext + SZ - 32, 32); + mbedtls_aes_crypt_ctr(&ctx, SZ, &nc_off, nonce, stream_block, plaintext, ciphertext); + TEST_ASSERT_EQUAL_HEX8_ARRAY(expected_cipher_end, ciphertext + SZ - 32, 32); // Decrypt nc_off = 0; memcpy(nonce, iv, 16); - mbedtls_aes_crypt_ctr(&ctx, SZ, &nc_off, nonce, stream_block, chipertext, decryptedtext); + mbedtls_aes_crypt_ctr(&ctx, SZ, &nc_off, nonce, stream_block, ciphertext, decryptedtext); TEST_ASSERT_EQUAL_HEX8_ARRAY(plaintext, decryptedtext, SZ); mbedtls_aes_free(&ctx); free(plaintext); - free(chipertext); + free(ciphertext); free(decryptedtext); } @@ -231,11 +231,11 @@ TEST_CASE("mbedtls OFB AES-256 test", "[aes]") memcpy(nonce, iv, 16); // allocate internal memory - uint8_t *chipertext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL); + uint8_t *ciphertext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL); uint8_t *plaintext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL); uint8_t *decryptedtext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL); - TEST_ASSERT_NOT_NULL(chipertext); + TEST_ASSERT_NOT_NULL(ciphertext); TEST_ASSERT_NOT_NULL(plaintext); TEST_ASSERT_NOT_NULL(decryptedtext); @@ -246,19 +246,19 @@ TEST_CASE("mbedtls OFB AES-256 test", "[aes]") memset(decryptedtext, 0x0, SZ); // Encrypt - mbedtls_aes_crypt_ofb(&ctx, SZ, &nc_off, nonce, plaintext, chipertext); - TEST_ASSERT_EQUAL_HEX8_ARRAY(expected_cipher_end, chipertext + SZ - 32, 32); + mbedtls_aes_crypt_ofb(&ctx, SZ, &nc_off, nonce, plaintext, ciphertext); + TEST_ASSERT_EQUAL_HEX8_ARRAY(expected_cipher_end, ciphertext + SZ - 32, 32); // Decrypt nc_off = 0; memcpy(nonce, iv, 16); - mbedtls_aes_crypt_ofb(&ctx, SZ, &nc_off, nonce, chipertext, decryptedtext); + mbedtls_aes_crypt_ofb(&ctx, SZ, &nc_off, nonce, ciphertext, decryptedtext); TEST_ASSERT_EQUAL_HEX8_ARRAY(plaintext, decryptedtext, SZ); mbedtls_aes_free(&ctx); free(plaintext); - free(chipertext); + free(ciphertext); free(decryptedtext); } @@ -278,11 +278,11 @@ TEST_CASE("mbedtls CFB-8 AES-256 test", "[aes]") memcpy(nonce, iv, 16); // allocate internal memory - uint8_t *chipertext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL); + uint8_t *ciphertext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL); uint8_t *plaintext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL); uint8_t *decryptedtext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL); - TEST_ASSERT_NOT_NULL(chipertext); + TEST_ASSERT_NOT_NULL(ciphertext); TEST_ASSERT_NOT_NULL(plaintext); TEST_ASSERT_NOT_NULL(decryptedtext); @@ -293,18 +293,18 @@ TEST_CASE("mbedtls CFB-8 AES-256 test", "[aes]") memset(decryptedtext, 0x0, SZ); // Encrypt - mbedtls_aes_crypt_cfb8(&ctx, MBEDTLS_AES_ENCRYPT, SZ, nonce, plaintext, chipertext); - TEST_ASSERT_EQUAL_HEX8_ARRAY(expected_cipher_end, chipertext + SZ - 32, 32); + mbedtls_aes_crypt_cfb8(&ctx, MBEDTLS_AES_ENCRYPT, SZ, nonce, plaintext, ciphertext); + TEST_ASSERT_EQUAL_HEX8_ARRAY(expected_cipher_end, ciphertext + SZ - 32, 32); // Decrypt memcpy(nonce, iv, 16); - mbedtls_aes_crypt_cfb8(&ctx, MBEDTLS_AES_DECRYPT, SZ, nonce, chipertext, decryptedtext); + mbedtls_aes_crypt_cfb8(&ctx, MBEDTLS_AES_DECRYPT, SZ, nonce, ciphertext, decryptedtext); TEST_ASSERT_EQUAL_HEX8_ARRAY(plaintext, decryptedtext, SZ); mbedtls_aes_free(&ctx); free(plaintext); - free(chipertext); + free(ciphertext); free(decryptedtext); } @@ -325,11 +325,11 @@ TEST_CASE("mbedtls CFB-128 AES-256 test", "[aes]") memcpy(nonce, iv, 16); // allocate internal memory - uint8_t *chipertext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL); + uint8_t *ciphertext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL); uint8_t *plaintext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL); uint8_t *decryptedtext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL); - TEST_ASSERT_NOT_NULL(chipertext); + TEST_ASSERT_NOT_NULL(ciphertext); TEST_ASSERT_NOT_NULL(plaintext); TEST_ASSERT_NOT_NULL(decryptedtext); @@ -340,19 +340,19 @@ TEST_CASE("mbedtls CFB-128 AES-256 test", "[aes]") memset(decryptedtext, 0x0, SZ); // Encrypt - mbedtls_aes_crypt_cfb128(&ctx, MBEDTLS_AES_ENCRYPT, SZ, &nc_off, nonce, plaintext, chipertext); - TEST_ASSERT_EQUAL_HEX8_ARRAY(expected_cipher_end, chipertext + SZ - 32, 32); + mbedtls_aes_crypt_cfb128(&ctx, MBEDTLS_AES_ENCRYPT, SZ, &nc_off, nonce, plaintext, ciphertext); + TEST_ASSERT_EQUAL_HEX8_ARRAY(expected_cipher_end, ciphertext + SZ - 32, 32); // Decrypt nc_off = 0; memcpy(nonce, iv, 16); - mbedtls_aes_crypt_cfb128(&ctx, MBEDTLS_AES_DECRYPT, SZ, &nc_off, nonce, chipertext, decryptedtext); + mbedtls_aes_crypt_cfb128(&ctx, MBEDTLS_AES_DECRYPT, SZ, &nc_off, nonce, ciphertext, decryptedtext); TEST_ASSERT_EQUAL_HEX8_ARRAY(plaintext, decryptedtext, SZ); mbedtls_aes_free(&ctx); free(plaintext); - free(chipertext); + free(ciphertext); free(decryptedtext); } @@ -401,11 +401,11 @@ static void aes_ctr_stream_test(void) memset(key, 0x44, 16); // allocate internal memory - uint8_t *chipertext = heap_caps_malloc(SZ, MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL); + uint8_t *ciphertext = heap_caps_malloc(SZ, MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL); uint8_t *plaintext = heap_caps_malloc(SZ, MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL); uint8_t *decryptedtext = heap_caps_malloc(SZ, MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL); - TEST_ASSERT_NOT_NULL(chipertext); + TEST_ASSERT_NOT_NULL(ciphertext); TEST_ASSERT_NOT_NULL(plaintext); TEST_ASSERT_NOT_NULL(decryptedtext); @@ -419,7 +419,7 @@ static void aes_ctr_stream_test(void) for (int bytes_to_process = 1; bytes_to_process < SZ; bytes_to_process++) { ESP_LOGD("test", "bytes_to_process %d", bytes_to_process); memset(nonce, 0xEE, 16); - memset(chipertext, 0x0, SZ); + memset(ciphertext, 0x0, SZ); memset(decryptedtext, 0x0, SZ); size_t offset = 0; @@ -429,12 +429,12 @@ static void aes_ctr_stream_test(void) size_t length = (idx + bytes_to_process > SZ) ? (SZ - idx) : bytes_to_process; mbedtls_aes_crypt_ctr(&ctx, length, &offset, nonce, - stream_block, plaintext + idx, chipertext + idx ); + stream_block, plaintext + idx, ciphertext + idx ); } ESP_LOG_BUFFER_HEXDUMP("expected", expected_cipher, SZ, ESP_LOG_DEBUG); - ESP_LOG_BUFFER_HEXDUMP("actual ", chipertext, SZ, ESP_LOG_DEBUG); + ESP_LOG_BUFFER_HEXDUMP("actual ", ciphertext, SZ, ESP_LOG_DEBUG); - TEST_ASSERT_EQUAL_HEX8_ARRAY(expected_cipher, chipertext, SZ); + TEST_ASSERT_EQUAL_HEX8_ARRAY(expected_cipher, ciphertext, SZ); // Decrypt memset(nonce, 0xEE, 16); @@ -444,7 +444,7 @@ static void aes_ctr_stream_test(void) // Limit length of last call to avoid exceeding buffer size size_t length = (idx + bytes_to_process > SZ) ? (SZ - idx) : bytes_to_process; mbedtls_aes_crypt_ctr(&ctx, length, &offset, nonce, - stream_block, chipertext + idx, decryptedtext + idx ); + stream_block, ciphertext + idx, decryptedtext + idx ); } ESP_LOG_BUFFER_HEXDUMP("decrypted", decryptedtext, SZ, ESP_LOG_DEBUG); TEST_ASSERT_EQUAL_HEX8_ARRAY(plaintext, decryptedtext, SZ); @@ -452,7 +452,7 @@ static void aes_ctr_stream_test(void) mbedtls_aes_free(&ctx); free(plaintext); - free(chipertext); + free(ciphertext); free(decryptedtext); } @@ -505,11 +505,11 @@ TEST_CASE("mbedtls OFB stream test", "[aes]") memset(key, 0x44, 16); // allocate internal memory - uint8_t *chipertext = heap_caps_malloc(SZ, MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL); + uint8_t *ciphertext = heap_caps_malloc(SZ, MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL); uint8_t *plaintext = heap_caps_malloc(SZ, MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL); uint8_t *decryptedtext = heap_caps_malloc(SZ, MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL); - TEST_ASSERT_NOT_NULL(chipertext); + TEST_ASSERT_NOT_NULL(ciphertext); TEST_ASSERT_NOT_NULL(plaintext); TEST_ASSERT_NOT_NULL(decryptedtext); @@ -529,10 +529,10 @@ TEST_CASE("mbedtls OFB stream test", "[aes]") for (int idx = 0; idx < SZ; idx = idx + bytes_to_process) { // Limit length of last call to avoid exceeding buffer size size_t length = ( (idx + bytes_to_process) > SZ) ? (SZ - idx) : bytes_to_process; - mbedtls_aes_crypt_ofb(&ctx, length, &offset, iv, plaintext + idx, chipertext + idx); + mbedtls_aes_crypt_ofb(&ctx, length, &offset, iv, plaintext + idx, ciphertext + idx); } - TEST_ASSERT_EQUAL_HEX8_ARRAY(expected_cipher, chipertext, SZ); + TEST_ASSERT_EQUAL_HEX8_ARRAY(expected_cipher, ciphertext, SZ); // Decrypt memset(iv, 0xEE, 16); @@ -541,14 +541,14 @@ TEST_CASE("mbedtls OFB stream test", "[aes]") for (int idx = 0; idx < SZ; idx = idx + bytes_to_process) { // Limit length of last call to avoid exceeding buffer size size_t length = (idx + bytes_to_process > SZ) ? (SZ - idx) : bytes_to_process; - mbedtls_aes_crypt_ofb(&ctx, length, &offset, iv, chipertext + idx, decryptedtext + idx); + mbedtls_aes_crypt_ofb(&ctx, length, &offset, iv, ciphertext + idx, decryptedtext + idx); } TEST_ASSERT_EQUAL_HEX8_ARRAY(plaintext, decryptedtext, SZ); } mbedtls_aes_free(&ctx); free(plaintext); - free(chipertext); + free(ciphertext); free(decryptedtext); } @@ -595,11 +595,11 @@ TEST_CASE("mbedtls CFB8 stream test", "[aes]") memset(key, 0x44, 16); // allocate internal memory - uint8_t *chipertext = heap_caps_malloc(SZ, MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL); + uint8_t *ciphertext = heap_caps_malloc(SZ, MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL); uint8_t *plaintext = heap_caps_malloc(SZ, MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL); uint8_t *decryptedtext = heap_caps_malloc(SZ, MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL); - TEST_ASSERT_NOT_NULL(chipertext); + TEST_ASSERT_NOT_NULL(ciphertext); TEST_ASSERT_NOT_NULL(plaintext); TEST_ASSERT_NOT_NULL(decryptedtext); @@ -616,16 +616,16 @@ TEST_CASE("mbedtls CFB8 stream test", "[aes]") for (int idx = 0; idx < SZ; idx = idx + bytes_to_process) { // Limit length of last call to avoid exceeding buffer size size_t length = ( (idx + bytes_to_process) > SZ) ? (SZ - idx) : bytes_to_process; - mbedtls_aes_crypt_cfb8(&ctx, MBEDTLS_AES_ENCRYPT, length, iv, plaintext + idx, chipertext + idx); + mbedtls_aes_crypt_cfb8(&ctx, MBEDTLS_AES_ENCRYPT, length, iv, plaintext + idx, ciphertext + idx); } - TEST_ASSERT_EQUAL_HEX8_ARRAY(expected_cipher, chipertext, SZ); + TEST_ASSERT_EQUAL_HEX8_ARRAY(expected_cipher, ciphertext, SZ); memset(iv, 0xEE, 16); for (int idx = 0; idx < SZ; idx = idx + bytes_to_process) { // Limit length of last call to avoid exceeding buffer size size_t length = ( (idx + bytes_to_process) > SZ) ? (SZ - idx) : bytes_to_process; - mbedtls_aes_crypt_cfb8(&ctx, MBEDTLS_AES_DECRYPT, length, iv, chipertext + idx, decryptedtext + idx); + mbedtls_aes_crypt_cfb8(&ctx, MBEDTLS_AES_DECRYPT, length, iv, ciphertext + idx, decryptedtext + idx); } TEST_ASSERT_EQUAL_HEX8_ARRAY(plaintext, decryptedtext, SZ); @@ -633,7 +633,7 @@ TEST_CASE("mbedtls CFB8 stream test", "[aes]") mbedtls_aes_free(&ctx); free(plaintext); - free(chipertext); + free(ciphertext); free(decryptedtext); } @@ -680,11 +680,11 @@ TEST_CASE("mbedtls CFB128 stream test", "[aes]") memset(key, 0x44, 16); // allocate internal memory - uint8_t *chipertext = heap_caps_malloc(SZ, MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL); + uint8_t *ciphertext = heap_caps_malloc(SZ, MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL); uint8_t *plaintext = heap_caps_malloc(SZ, MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL); uint8_t *decryptedtext = heap_caps_malloc(SZ, MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL); - TEST_ASSERT_NOT_NULL(chipertext); + TEST_ASSERT_NOT_NULL(ciphertext); TEST_ASSERT_NOT_NULL(plaintext); TEST_ASSERT_NOT_NULL(decryptedtext); @@ -703,24 +703,24 @@ TEST_CASE("mbedtls CFB128 stream test", "[aes]") for (int idx = 0; idx < SZ; idx = idx + bytes_to_process) { // Limit length of last call to avoid exceeding buffer size size_t length = ( (idx + bytes_to_process) > SZ) ? (SZ - idx) : bytes_to_process; - mbedtls_aes_crypt_cfb128(&ctx, MBEDTLS_AES_ENCRYPT, length, &offset, iv, plaintext + idx, chipertext + idx); + mbedtls_aes_crypt_cfb128(&ctx, MBEDTLS_AES_ENCRYPT, length, &offset, iv, plaintext + idx, ciphertext + idx); } - TEST_ASSERT_EQUAL_HEX8_ARRAY(expected_cipher, chipertext, SZ); + TEST_ASSERT_EQUAL_HEX8_ARRAY(expected_cipher, ciphertext, SZ); offset = 0; memset(iv, 0xEE, 16); for (int idx = 0; idx < SZ; idx = idx + bytes_to_process) { // Limit length of last call to avoid exceeding buffer size size_t length = ( (idx + bytes_to_process) > SZ) ? (SZ - idx) : bytes_to_process; - mbedtls_aes_crypt_cfb128(&ctx, MBEDTLS_AES_DECRYPT, length, &offset, iv, chipertext + idx, decryptedtext + idx); + mbedtls_aes_crypt_cfb128(&ctx, MBEDTLS_AES_DECRYPT, length, &offset, iv, ciphertext + idx, decryptedtext + idx); } TEST_ASSERT_EQUAL_HEX8_ARRAY(plaintext, decryptedtext, SZ); mbedtls_aes_free(&ctx); free(plaintext); - free(chipertext); + free(ciphertext); free(decryptedtext); } @@ -804,11 +804,11 @@ TEST_CASE("mbedtls OFB, chained DMA descriptors", "[aes]") memcpy(nonce, iv, 16); // allocate internal memory - uint8_t *chipertext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL); + uint8_t *ciphertext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL); uint8_t *plaintext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL); uint8_t *decryptedtext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL); - TEST_ASSERT_NOT_NULL(chipertext); + TEST_ASSERT_NOT_NULL(ciphertext); TEST_ASSERT_NOT_NULL(plaintext); TEST_ASSERT_NOT_NULL(decryptedtext); @@ -819,20 +819,20 @@ TEST_CASE("mbedtls OFB, chained DMA descriptors", "[aes]") memset(decryptedtext, 0x0, SZ); // Encrypt - mbedtls_aes_crypt_ofb(&ctx, SZ, &nc_off, nonce, plaintext, chipertext); - TEST_ASSERT_EQUAL_HEX8_ARRAY(expected_cipher_end, chipertext + SZ - 32, 32); + mbedtls_aes_crypt_ofb(&ctx, SZ, &nc_off, nonce, plaintext, ciphertext); + TEST_ASSERT_EQUAL_HEX8_ARRAY(expected_cipher_end, ciphertext + SZ - 32, 32); // Decrypt nc_off = 0; memcpy(nonce, iv, 16); - mbedtls_aes_crypt_ofb(&ctx, SZ, &nc_off, nonce, chipertext, decryptedtext); + mbedtls_aes_crypt_ofb(&ctx, SZ, &nc_off, nonce, ciphertext, decryptedtext); TEST_ASSERT_EQUAL_HEX8_ARRAY(plaintext, decryptedtext, SZ); mbedtls_aes_free(&ctx); free(plaintext); - free(chipertext); + free(ciphertext); free(decryptedtext); } @@ -858,11 +858,11 @@ void aes_ctr_alignment_test(uint32_t input_buf_caps, uint32_t output_buf_caps) memset(key, 0x1E, 16); // allocate memory according the requested caps - uint8_t *chipertext = heap_caps_malloc(SZ + ALIGNMENT_SIZE_BYTES, output_buf_caps); + uint8_t *ciphertext = heap_caps_malloc(SZ + ALIGNMENT_SIZE_BYTES, output_buf_caps); uint8_t *plaintext = heap_caps_malloc(SZ + ALIGNMENT_SIZE_BYTES, input_buf_caps); uint8_t *decryptedtext = heap_caps_malloc(SZ, MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL); - TEST_ASSERT_NOT_NULL(chipertext); + TEST_ASSERT_NOT_NULL(ciphertext); TEST_ASSERT_NOT_NULL(plaintext); TEST_ASSERT_NOT_NULL(decryptedtext); @@ -877,14 +877,14 @@ void aes_ctr_alignment_test(uint32_t input_buf_caps, uint32_t output_buf_caps) // Encrypt with input buffer in external ram offset = 0; memset(nonce, 0x2F, 16); - mbedtls_aes_crypt_ctr(&ctx, SZ, &offset, nonce, stream_block, plaintext + i, chipertext + i); - TEST_ASSERT_EQUAL_HEX8_ARRAY(expected_cipher_ctr_end, chipertext + i + SZ - 32, 32); + mbedtls_aes_crypt_ctr(&ctx, SZ, &offset, nonce, stream_block, plaintext + i, ciphertext + i); + TEST_ASSERT_EQUAL_HEX8_ARRAY(expected_cipher_ctr_end, ciphertext + i + SZ - 32, 32); // Decrypt offset = 0; memset(nonce, 0x2F, 16); // Decrypt with input buffer in instruction memory, the crypto DMA can't access this - mbedtls_aes_crypt_ctr(&ctx, SZ, &offset, nonce, stream_block, chipertext + i, decryptedtext); + mbedtls_aes_crypt_ctr(&ctx, SZ, &offset, nonce, stream_block, ciphertext + i, decryptedtext); TEST_ASSERT_EQUAL_HEX8_ARRAY(plaintext, decryptedtext, SZ); @@ -892,7 +892,7 @@ void aes_ctr_alignment_test(uint32_t input_buf_caps, uint32_t output_buf_caps) mbedtls_aes_free(&ctx); free(plaintext); - free(chipertext); + free(ciphertext); free(decryptedtext); } @@ -1483,10 +1483,10 @@ void aes_ext_flash_ctr_test(uint32_t output_buf_caps) memset(nonce, 0x2F, 16); memset(key, 0x1E, 16); - uint8_t *chipertext = heap_caps_malloc(SZ, output_buf_caps); + uint8_t *ciphertext = heap_caps_malloc(SZ, output_buf_caps); uint8_t *decryptedtext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT | MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL); - TEST_ASSERT_NOT_NULL(chipertext); + TEST_ASSERT_NOT_NULL(ciphertext); TEST_ASSERT_NOT_NULL(decryptedtext); mbedtls_aes_init(&ctx); @@ -1497,19 +1497,19 @@ void aes_ext_flash_ctr_test(uint32_t output_buf_caps) // Encrypt with input buffer in external flash offset = 0; memset(nonce, 0x2F, 16); - mbedtls_aes_crypt_ctr(&ctx, SZ, &offset, nonce, stream_block, long_input, chipertext); - TEST_ASSERT_EQUAL_HEX8_ARRAY(expected_cipher_long_input_end, chipertext + SZ - 32, 32); + mbedtls_aes_crypt_ctr(&ctx, SZ, &offset, nonce, stream_block, long_input, ciphertext); + TEST_ASSERT_EQUAL_HEX8_ARRAY(expected_cipher_long_input_end, ciphertext + SZ - 32, 32); // Decrypt offset = 0; memset(nonce, 0x2F, 16); // Decrypt with input buffer in external flash, the crypto DMA can't access this - mbedtls_aes_crypt_ctr(&ctx, SZ, &offset, nonce, stream_block, chipertext, decryptedtext); + mbedtls_aes_crypt_ctr(&ctx, SZ, &offset, nonce, stream_block, ciphertext, decryptedtext); TEST_ASSERT_EQUAL_HEX8_ARRAY(long_input, decryptedtext, SZ); mbedtls_aes_free(&ctx); - free(chipertext); + free(ciphertext); free(decryptedtext); } @@ -1563,7 +1563,7 @@ TEST_CASE("mbedtls AES stack in RTC RAM", "[mbedtls]") #endif //CONFIG_ESP_SYSTEM_RTC_FAST_MEM_AS_HEAP_DEPCHECK -#if CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY && CONFIG_SPIRAM_USE_MALLOC +#if CONFIG_FREERTOS_TASK_CREATE_ALLOW_EXT_MEM && CONFIG_SPIRAM_USE_MALLOC TEST_CASE("mbedtls AES stack in PSRAM", "[mbedtls]") { @@ -1585,4 +1585,4 @@ TEST_CASE("mbedtls AES stack in PSRAM", "[mbedtls]") vSemaphoreDelete(done_sem); } -#endif //CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY && CONFIG_SPIRAM_USE_MALLOC +#endif //CONFIG_FREERTOS_TASK_CREATE_ALLOW_EXT_MEM && CONFIG_SPIRAM_USE_MALLOC diff --git a/components/mbedtls/test_apps/main/test_mbedtls_sha.c b/components/mbedtls/test_apps/main/test_mbedtls_sha.c index 003b35db8b5..55e0a65e098 100644 --- a/components/mbedtls/test_apps/main/test_mbedtls_sha.c +++ b/components/mbedtls/test_apps/main/test_mbedtls_sha.c @@ -587,7 +587,7 @@ TEST_CASE("mbedtls SHA stack in RTC RAM", "[mbedtls]") #endif //CONFIG_ESP_SYSTEM_RTC_FAST_MEM_AS_HEAP_DEPCHECK -#if CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY && CONFIG_SPIRAM_USE_MALLOC +#if CONFIG_FREERTOS_TASK_CREATE_ALLOW_EXT_MEM && CONFIG_SPIRAM_USE_MALLOC TEST_CASE("mbedtls SHA stack in PSRAM", "[mbedtls]") { @@ -609,4 +609,4 @@ TEST_CASE("mbedtls SHA stack in PSRAM", "[mbedtls]") vSemaphoreDelete(done_sem); } -#endif //CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY && CONFIG_SPIRAM_USE_MALLOC +#endif //CONFIG_FREERTOS_TASK_CREATE_ALLOW_EXT_MEM && CONFIG_SPIRAM_USE_MALLOC diff --git a/components/mbedtls/test_apps/sdkconfig.ci.psram_all_ext b/components/mbedtls/test_apps/sdkconfig.ci.psram_all_ext index ad3452cf7b8..cd0e64116c8 100644 --- a/components/mbedtls/test_apps/sdkconfig.ci.psram_all_ext +++ b/components/mbedtls/test_apps/sdkconfig.ci.psram_all_ext @@ -1,4 +1,4 @@ CONFIG_SPIRAM=y CONFIG_ESP_INT_WDT_TIMEOUT_MS=800 -CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY=y +CONFIG_FREERTOS_TASK_CREATE_ALLOW_EXT_MEM=y CONFIG_SPIRAM_MALLOC_ALWAYSINTERNAL=0 diff --git a/components/mbedtls/test_apps/sdkconfig.ci.psram_all_ext_esp32p4_200m b/components/mbedtls/test_apps/sdkconfig.ci.psram_all_ext_esp32p4_200m index 1c29e19bb93..6ed71c76e36 100644 --- a/components/mbedtls/test_apps/sdkconfig.ci.psram_all_ext_esp32p4_200m +++ b/components/mbedtls/test_apps/sdkconfig.ci.psram_all_ext_esp32p4_200m @@ -1,7 +1,7 @@ CONFIG_IDF_TARGET="esp32p4" CONFIG_SPIRAM=y CONFIG_ESP_INT_WDT_TIMEOUT_MS=800 -CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY=y +CONFIG_FREERTOS_TASK_CREATE_ALLOW_EXT_MEM=y CONFIG_SPIRAM_MALLOC_ALWAYSINTERNAL=0 CONFIG_IDF_EXPERIMENTAL_FEATURES=y diff --git a/docs/en/api-guides/external-ram.rst b/docs/en/api-guides/external-ram.rst index f8cebef14d4..2869531dbe2 100644 --- a/docs/en/api-guides/external-ram.rst +++ b/docs/en/api-guides/external-ram.rst @@ -213,7 +213,7 @@ External RAM use has the following restrictions: - In general, external RAM will not be used as task stack memory. :cpp:func:`xTaskCreate` and similar functions will always allocate internal memory for stack and task TCBs. -The option :ref:`CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY` can be used to allow placing task stacks into external memory. In these cases :cpp:func:`xTaskCreateStatic` must be used to specify a task stack buffer allocated from external memory, otherwise task stacks will still be allocated from internal memory. +The option :ref:`CONFIG_FREERTOS_TASK_CREATE_ALLOW_EXT_MEM` can be used to allow placing task stacks into external memory. In these cases :cpp:func:`xTaskCreateStatic` must be used to specify a task stack buffer allocated from external memory, otherwise task stacks will still be allocated from internal memory. Failure to Initialize diff --git a/docs/en/api-guides/inc/external-ram-esp32-notes.rst b/docs/en/api-guides/inc/external-ram-esp32-notes.rst index ac8f8d4764c..b914ebd8165 100644 --- a/docs/en/api-guides/inc/external-ram-esp32-notes.rst +++ b/docs/en/api-guides/inc/external-ram-esp32-notes.rst @@ -1,4 +1,4 @@ -* Regarding stacks in PSRAM: For tasks that do not call ROM code in any way (directly or indirectly), the :ref:`CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY` option will eliminate the check in :cpp:func:`xTaskCreateStatic`, allowing a task's stack to be in external RAM. However, using this is **not advised**. +* Regarding stacks in PSRAM: For tasks that do not call ROM code in any way (directly or indirectly), the :ref:`CONFIG_FREERTOS_TASK_CREATE_ALLOW_EXT_MEM` option will eliminate the check in :cpp:func:`xTaskCreateStatic`, allowing a task's stack to be in external RAM. However, using this is **not advised**. * When used at 80 MHz clock speed, external RAM must also occupy either the HSPI or VSPI bus. Select which SPI host will be used by :ref:`CONFIG_SPIRAM_OCCUPY_SPI_HOST`. diff --git a/docs/zh_CN/api-guides/external-ram.rst b/docs/zh_CN/api-guides/external-ram.rst index 92bfa9eafcd..7793385b285 100644 --- a/docs/zh_CN/api-guides/external-ram.rst +++ b/docs/zh_CN/api-guides/external-ram.rst @@ -211,7 +211,7 @@ ESP-IDF 启动过程中，片外 RAM 被映射到数据虚拟地址空间，该 - 一般来说，片外 RAM 不会用作任务堆栈存储器。:cpp:func:`xTaskCreate` 及类似函数始终会为堆栈和任务 TCB 分配片上储存器。 -可以使用 :ref:`CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY` 选项将任务堆栈放入片外存储器。这时，必须使用 :cpp:func:`xTaskCreateStatic` 指定从片外存储器分配的任务堆栈缓冲区，否则任务堆栈将仍从片上存储器分配。 +可以使用 :ref:`CONFIG_FREERTOS_TASK_CREATE_ALLOW_EXT_MEM` 选项将任务堆栈放入片外存储器。这时，必须使用 :cpp:func:`xTaskCreateStatic` 指定从片外存储器分配的任务堆栈缓冲区，否则任务堆栈将仍从片上存储器分配。 初始化失败 diff --git a/docs/zh_CN/api-guides/inc/external-ram-esp32-notes.rst b/docs/zh_CN/api-guides/inc/external-ram-esp32-notes.rst index 6d93693c8de..6c7186a3281 100644 --- a/docs/zh_CN/api-guides/inc/external-ram-esp32-notes.rst +++ b/docs/zh_CN/api-guides/inc/external-ram-esp32-notes.rst @@ -1,4 +1,4 @@ -* PSRAM 中的栈：对于不以任何直接或间接方式调用 ROM 中代码的任务，选项 :ref:`CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY` 会取消 :cpp:func:`xTaskCreateStatic` 中的检查，允许任务栈存放在外部 RAM 中。但 **不建议** 使用此选项。 +* PSRAM 中的栈：对于不以任何直接或间接方式调用 ROM 中代码的任务，选项 :ref:`CONFIG_FREERTOS_TASK_CREATE_ALLOW_EXT_MEM` 会取消 :cpp:func:`xTaskCreateStatic` 中的检查，允许任务栈存放在外部 RAM 中。但 **不建议** 使用此选项。 * 在以 80 MHz 时钟速度运行时，外部 RAM 还必须占用 HSPI 或 VSPI 总线。设置 :ref:`CONFIG_SPIRAM_OCCUPY_SPI_HOST` 选项可以选择使用的 SPI 主机。 diff --git a/tools/test_apps/system/panic/main/include/test_panic.h b/tools/test_apps/system/panic/main/include/test_panic.h index 71733add77e..32d05126554 100644 --- a/tools/test_apps/system/panic/main/include/test_panic.h +++ b/tools/test_apps/system/panic/main/include/test_panic.h @@ -31,7 +31,7 @@ void test_hw_stack_guard_cpu1(void); #endif // CONFIG_FREERTOS_UNICORE #endif // CONFIG_ESP_SYSTEM_HW_STACK_GUARD -#if CONFIG_ESP_COREDUMP_ENABLE_TO_FLASH && CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY +#if CONFIG_ESP_COREDUMP_ENABLE_TO_FLASH && CONFIG_FREERTOS_TASK_CREATE_ALLOW_EXT_MEM void test_panic_extram_stack_heap(void); #if CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY void test_panic_extram_stack_bss(void); diff --git a/tools/test_apps/system/panic/main/test_app_main.c b/tools/test_apps/system/panic/main/test_app_main.c index b55f7de7652..a824e25e5bd 100644 --- a/tools/test_apps/system/panic/main/test_app_main.c +++ b/tools/test_apps/system/panic/main/test_app_main.c @@ -95,7 +95,7 @@ void app_main(void) HANDLE_TEST(test_name, test_hw_stack_guard_cpu1); #endif // CONFIG_FREERTOS_UNICORE #endif // CONFIG_ESP_SYSTEM_HW_STACK_GUARD -#if CONFIG_ESP_COREDUMP_ENABLE_TO_FLASH && CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY +#if CONFIG_ESP_COREDUMP_ENABLE_TO_FLASH && CONFIG_FREERTOS_TASK_CREATE_ALLOW_EXT_MEM HANDLE_TEST(test_name, test_panic_extram_stack_heap); #if CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY HANDLE_TEST(test_name, test_panic_extram_stack_bss); diff --git a/tools/test_apps/system/panic/main/test_panic.c b/tools/test_apps/system/panic/main/test_panic.c index 6f58469d826..eafc9daddfe 100644 --- a/tools/test_apps/system/panic/main/test_panic.c +++ b/tools/test_apps/system/panic/main/test_panic.c @@ -96,7 +96,7 @@ void test_hw_stack_guard_cpu1(void) #endif // CONFIG_FREERTOS_UNICORE #endif // CONFIG_ESP_SYSTEM_HW_STACK_GUARD -#if CONFIG_ESP_COREDUMP_ENABLE_TO_FLASH && CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY +#if CONFIG_ESP_COREDUMP_ENABLE_TO_FLASH && CONFIG_FREERTOS_TASK_CREATE_ALLOW_EXT_MEM static void stack_in_extram(void* arg) { (void) arg; @@ -130,7 +130,7 @@ void test_panic_extram_stack_bss(void) vTaskDelay(1000); } #endif -#endif // ESP_COREDUMP_ENABLE_TO_FLASH && SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY +#endif // ESP_COREDUMP_ENABLE_TO_FLASH && FREERTOS_TASK_CREATE_ALLOW_EXT_MEM #if !CONFIG_FREERTOS_UNICORE diff --git a/tools/test_apps/system/panic/sdkconfig.ci.coredump_flash_extram_stack_bss_esp32 b/tools/test_apps/system/panic/sdkconfig.ci.coredump_flash_extram_stack_bss_esp32 index 26769c3c598..065b49d68b2 100644 --- a/tools/test_apps/system/panic/sdkconfig.ci.coredump_flash_extram_stack_bss_esp32 +++ b/tools/test_apps/system/panic/sdkconfig.ci.coredump_flash_extram_stack_bss_esp32 @@ -5,7 +5,7 @@ CONFIG_ESP_COREDUMP_CHECKSUM_SHA256=y # We need to have the coredump info log CONFIG_LOG_DEFAULT_LEVEL_INFO=y CONFIG_SPIRAM=y -CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY=y +CONFIG_FREERTOS_TASK_CREATE_ALLOW_EXT_MEM=y CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY=y CONFIG_ESP_COREDUMP_USE_STACK_SIZE=y CONFIG_ESP_COREDUMP_CAPTURE_DRAM=y diff --git a/tools/test_apps/system/panic/sdkconfig.ci.coredump_flash_extram_stack_bss_esp32s2 b/tools/test_apps/system/panic/sdkconfig.ci.coredump_flash_extram_stack_bss_esp32s2 index ad1a91fa811..7c372f58f2c 100644 --- a/tools/test_apps/system/panic/sdkconfig.ci.coredump_flash_extram_stack_bss_esp32s2 +++ b/tools/test_apps/system/panic/sdkconfig.ci.coredump_flash_extram_stack_bss_esp32s2 @@ -5,7 +5,7 @@ CONFIG_ESP_COREDUMP_CHECKSUM_SHA256=y # We need to have the coredump info log CONFIG_LOG_DEFAULT_LEVEL_INFO=y CONFIG_SPIRAM=y -CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY=y +CONFIG_FREERTOS_TASK_CREATE_ALLOW_EXT_MEM=y CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY=y CONFIG_ESP_COREDUMP_USE_STACK_SIZE=y CONFIG_ESP_COREDUMP_CAPTURE_DRAM=y diff --git a/tools/test_apps/system/panic/sdkconfig.ci.coredump_flash_extram_stack_bss_esp32s3 b/tools/test_apps/system/panic/sdkconfig.ci.coredump_flash_extram_stack_bss_esp32s3 index 46903a02235..a1533240cb6 100644 --- a/tools/test_apps/system/panic/sdkconfig.ci.coredump_flash_extram_stack_bss_esp32s3 +++ b/tools/test_apps/system/panic/sdkconfig.ci.coredump_flash_extram_stack_bss_esp32s3 @@ -5,7 +5,7 @@ CONFIG_ESP_COREDUMP_CHECKSUM_SHA256=y # We need to have the coredump info log CONFIG_LOG_DEFAULT_LEVEL_INFO=y CONFIG_SPIRAM=y -CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY=y +CONFIG_FREERTOS_TASK_CREATE_ALLOW_EXT_MEM=y CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY=y CONFIG_ESP_COREDUMP_USE_STACK_SIZE=y CONFIG_ESP_COREDUMP_CAPTURE_DRAM=y diff --git a/tools/test_apps/system/panic/sdkconfig.ci.coredump_flash_extram_stack_heap_esp32 b/tools/test_apps/system/panic/sdkconfig.ci.coredump_flash_extram_stack_heap_esp32 index 18391318a37..a98716641a9 100644 --- a/tools/test_apps/system/panic/sdkconfig.ci.coredump_flash_extram_stack_heap_esp32 +++ b/tools/test_apps/system/panic/sdkconfig.ci.coredump_flash_extram_stack_heap_esp32 @@ -5,5 +5,5 @@ CONFIG_ESP_COREDUMP_CHECKSUM_SHA256=y # We need to have the coredump info log CONFIG_LOG_DEFAULT_LEVEL_INFO=y CONFIG_SPIRAM=y -CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY=y +CONFIG_FREERTOS_TASK_CREATE_ALLOW_EXT_MEM=y CONFIG_ESP_COREDUMP_USE_STACK_SIZE=y diff --git a/tools/test_apps/system/panic/sdkconfig.ci.coredump_flash_extram_stack_heap_esp32s2 b/tools/test_apps/system/panic/sdkconfig.ci.coredump_flash_extram_stack_heap_esp32s2 index 981803c0be2..dddebf12c09 100644 --- a/tools/test_apps/system/panic/sdkconfig.ci.coredump_flash_extram_stack_heap_esp32s2 +++ b/tools/test_apps/system/panic/sdkconfig.ci.coredump_flash_extram_stack_heap_esp32s2 @@ -5,5 +5,5 @@ CONFIG_ESP_COREDUMP_CHECKSUM_SHA256=y # We need to have the coredump info log CONFIG_LOG_DEFAULT_LEVEL_INFO=y CONFIG_SPIRAM=y -CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY=y +CONFIG_FREERTOS_TASK_CREATE_ALLOW_EXT_MEM=y CONFIG_ESP_COREDUMP_USE_STACK_SIZE=y diff --git a/tools/test_apps/system/panic/sdkconfig.ci.coredump_flash_extram_stack_heap_esp32s3 b/tools/test_apps/system/panic/sdkconfig.ci.coredump_flash_extram_stack_heap_esp32s3 index ff952817bde..55202118942 100644 --- a/tools/test_apps/system/panic/sdkconfig.ci.coredump_flash_extram_stack_heap_esp32s3 +++ b/tools/test_apps/system/panic/sdkconfig.ci.coredump_flash_extram_stack_heap_esp32s3 @@ -5,5 +5,5 @@ CONFIG_ESP_COREDUMP_CHECKSUM_SHA256=y # We need to have the coredump info log CONFIG_LOG_DEFAULT_LEVEL_INFO=y CONFIG_SPIRAM=y -CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY=y +CONFIG_FREERTOS_TASK_CREATE_ALLOW_EXT_MEM=y CONFIG_ESP_COREDUMP_USE_STACK_SIZE=y From a7ebec84feae7662f40eb3a9f94cc97f6a3911e1 Mon Sep 17 00:00:00 2001 From: laokaiyao Date: Fri, 6 Sep 2024 17:27:24 +0800 Subject: [PATCH 067/472] refactor(soc): sort esp32h2 soc headers --- .../esp32c5/include/soc/usb_serial_jtag_reg.h | 2 +- .../include/soc/usb_serial_jtag_struct.h | 2 +- .../soc/esp32h2/include/soc/dport_access.h | 3 +- .../soc/esp32h2/include/soc/interrupt_reg.h | 4 +- components/soc/esp32h2/include/soc/soc.h | 2 +- .../soc/esp32h2/include/soc/system_reg.h | 2 +- components/soc/esp32h2/register/soc/.gitkeep | 0 .../{include => register}/soc/aes_reg.h | 0 .../{include => register}/soc/aes_struct.h | 0 .../soc/apb_saradc_reg.h | 0 .../soc/apb_saradc_struct.h | 0 .../soc/assist_debug_reg.h | 12 ++-- .../soc/assist_debug_struct.h | 18 +++--- .../{include => register}/soc/cache_reg.h | 8 +-- .../{include => register}/soc/cache_struct.h | 8 +-- .../{include => register}/soc/clint_reg.h | 0 .../{include => register}/soc/ds_reg.h | 0 .../{include => register}/soc/ds_struct.h | 0 .../{include => register}/soc/ecc_mult_reg.h | 4 +- .../soc/ecc_mult_struct.h | 4 +- .../{include => register}/soc/ecdsa_reg.h | 6 +- .../{include => register}/soc/ecdsa_struct.h | 6 +- .../{include => register}/soc/efuse_reg.h | 8 +-- .../{include => register}/soc/efuse_struct.h | 6 +- .../{include => register}/soc/extmem_reg.h | 38 +++++------ .../{include => register}/soc/extmem_struct.h | 8 +-- .../{include => register}/soc/gdma_reg.h | 0 .../{include => register}/soc/gdma_struct.h | 0 .../{include => register}/soc/gpio_ext_reg.h | 0 .../soc/gpio_ext_struct.h | 0 .../{include => register}/soc/gpio_reg.h | 0 .../{include => register}/soc/gpio_struct.h | 0 .../{include => register}/soc/hmac_reg.h | 0 .../{include => register}/soc/hmac_struct.h | 0 .../{include => register}/soc/hp_apm_reg.h | 0 .../{include => register}/soc/hp_apm_struct.h | 0 .../{include => register}/soc/hp_system_reg.h | 2 +- .../soc/hp_system_struct.h | 2 +- .../soc/i2c_ana_mst_reg.h | 0 .../{include => register}/soc/i2c_reg.h | 0 .../{include => register}/soc/i2c_struct.h | 0 .../{include => register}/soc/i2s_reg.h | 2 +- .../{include => register}/soc/i2s_struct.h | 2 +- .../soc/ieee802154_reg.h | 0 .../soc/ieee802154_struct.h | 0 .../soc/interrupt_matrix_reg.h | 0 .../soc/interrupt_matrix_struct.h | 0 .../{include => register}/soc/intpri_reg.h | 0 .../{include => register}/soc/intpri_struct.h | 0 .../{include => register}/soc/io_mux_reg.h | 4 +- .../{include => register}/soc/ledc_reg.h | 0 .../{include => register}/soc/ledc_struct.h | 0 .../soc/lp_analog_peri_reg.h | 0 .../soc/lp_analog_peri_struct.h | 0 .../{include => register}/soc/lp_aon_reg.h | 0 .../{include => register}/soc/lp_aon_struct.h | 0 .../{include => register}/soc/lp_apm0_reg.h | 0 .../soc/lp_apm0_struct.h | 0 .../{include => register}/soc/lp_apm_reg.h | 0 .../{include => register}/soc/lp_apm_struct.h | 0 .../{include => register}/soc/lp_clkrst_reg.h | 0 .../soc/lp_clkrst_struct.h | 0 .../{include => register}/soc/lp_timer_reg.h | 0 .../soc/lp_timer_struct.h | 0 .../{include => register}/soc/lp_wdt_reg.h | 0 .../{include => register}/soc/lp_wdt_struct.h | 0 .../{include => register}/soc/lpperi_reg.h | 0 .../{include => register}/soc/lpperi_struct.h | 0 .../{include => register}/soc/mcpwm_reg.h | 12 ++-- .../{include => register}/soc/mcpwm_struct.h | 4 +- .../soc/mem_monitor_reg.h | 8 +-- .../soc/mem_monitor_struct.h | 8 +-- .../{include => register}/soc/parl_io_reg.h | 8 +-- .../soc/parl_io_struct.h | 8 +-- .../{include => register}/soc/pau_reg.h | 0 .../{include => register}/soc/pau_struct.h | 0 .../{include => register}/soc/pcnt_reg.h | 0 .../{include => register}/soc/pcnt_struct.h | 0 .../{include => register}/soc/pcr_reg.h | 38 +++++------ .../{include => register}/soc/pcr_struct.h | 38 +++++------ .../{include => register}/soc/plic_reg.h | 0 .../{include => register}/soc/pmu_reg.h | 0 .../{include => register}/soc/pmu_struct.h | 0 .../{include => register}/soc/reg_base.h | 0 .../{include => register}/soc/rmt_reg.h | 0 .../{include => register}/soc/rmt_struct.h | 0 .../{include => register}/soc/rsa_reg.h | 0 .../{include => register}/soc/rsa_struct.h | 0 .../{include => register}/soc/sha_reg.h | 2 +- .../{include => register}/soc/sha_struct.h | 0 .../{include => register}/soc/soc_etm_reg.h | 0 .../soc/soc_etm_struct.h | 0 .../{include => register}/soc/spi_mem_reg.h | 64 +++++++++---------- .../soc/spi_mem_struct.h | 10 +-- .../{include => register}/soc/spi_reg.h | 4 +- .../{include => register}/soc/spi_struct.h | 4 +- .../{include => register}/soc/systimer_reg.h | 0 .../soc/systimer_struct.h | 0 .../{include => register}/soc/tee_reg.h | 0 .../{include => register}/soc/tee_struct.h | 0 .../soc/timer_group_reg.h | 0 .../soc/timer_group_struct.h | 0 .../{include => register}/soc/trace_reg.h | 2 +- .../{include => register}/soc/trace_struct.h | 2 +- .../{include => register}/soc/twai_reg.h | 0 .../{include => register}/soc/twai_struct.h | 0 .../{include => register}/soc/uart_reg.h | 10 +-- .../{include => register}/soc/uart_struct.h | 10 +-- .../{include => register}/soc/uhci_reg.h | 0 .../{include => register}/soc/uhci_struct.h | 0 .../soc/usb_serial_jtag_reg.h | 2 +- .../soc/usb_serial_jtag_struct.h | 0 .../{include => register}/soc/xts_aes_reg.h | 6 +- .../soc/esp32p4/include/soc/usb_wrap_struct.h | 2 +- 114 files changed, 197 insertions(+), 198 deletions(-) delete mode 100644 components/soc/esp32h2/register/soc/.gitkeep rename components/soc/esp32h2/{include => register}/soc/aes_reg.h (100%) rename components/soc/esp32h2/{include => register}/soc/aes_struct.h (100%) rename components/soc/esp32h2/{include => register}/soc/apb_saradc_reg.h (100%) rename components/soc/esp32h2/{include => register}/soc/apb_saradc_struct.h (100%) rename components/soc/esp32h2/{include => register}/soc/assist_debug_reg.h (99%) rename components/soc/esp32h2/{include => register}/soc/assist_debug_struct.h (98%) rename components/soc/esp32h2/{include => register}/soc/cache_reg.h (99%) rename components/soc/esp32h2/{include => register}/soc/cache_struct.h (99%) rename components/soc/esp32h2/{include => register}/soc/clint_reg.h (100%) rename components/soc/esp32h2/{include => register}/soc/ds_reg.h (100%) rename components/soc/esp32h2/{include => register}/soc/ds_struct.h (100%) rename components/soc/esp32h2/{include => register}/soc/ecc_mult_reg.h (97%) rename components/soc/esp32h2/{include => register}/soc/ecc_mult_struct.h (96%) rename components/soc/esp32h2/{include => register}/soc/ecdsa_reg.h (97%) rename components/soc/esp32h2/{include => register}/soc/ecdsa_struct.h (97%) rename components/soc/esp32h2/{include => register}/soc/efuse_reg.h (99%) rename components/soc/esp32h2/{include => register}/soc/efuse_struct.h (99%) rename components/soc/esp32h2/{include => register}/soc/extmem_reg.h (98%) rename components/soc/esp32h2/{include => register}/soc/extmem_struct.h (99%) rename components/soc/esp32h2/{include => register}/soc/gdma_reg.h (100%) rename components/soc/esp32h2/{include => register}/soc/gdma_struct.h (100%) rename components/soc/esp32h2/{include => register}/soc/gpio_ext_reg.h (100%) rename components/soc/esp32h2/{include => register}/soc/gpio_ext_struct.h (100%) rename components/soc/esp32h2/{include => register}/soc/gpio_reg.h (100%) rename components/soc/esp32h2/{include => register}/soc/gpio_struct.h (100%) rename components/soc/esp32h2/{include => register}/soc/hmac_reg.h (100%) rename components/soc/esp32h2/{include => register}/soc/hmac_struct.h (100%) rename components/soc/esp32h2/{include => register}/soc/hp_apm_reg.h (100%) rename components/soc/esp32h2/{include => register}/soc/hp_apm_struct.h (100%) rename components/soc/esp32h2/{include => register}/soc/hp_system_reg.h (99%) rename components/soc/esp32h2/{include => register}/soc/hp_system_struct.h (99%) rename components/soc/esp32h2/{include => register}/soc/i2c_ana_mst_reg.h (100%) rename components/soc/esp32h2/{include => register}/soc/i2c_reg.h (100%) rename components/soc/esp32h2/{include => register}/soc/i2c_struct.h (100%) rename components/soc/esp32h2/{include => register}/soc/i2s_reg.h (99%) rename components/soc/esp32h2/{include => register}/soc/i2s_struct.h (99%) rename components/soc/esp32h2/{include => register}/soc/ieee802154_reg.h (100%) rename components/soc/esp32h2/{include => register}/soc/ieee802154_struct.h (100%) rename components/soc/esp32h2/{include => register}/soc/interrupt_matrix_reg.h (100%) rename components/soc/esp32h2/{include => register}/soc/interrupt_matrix_struct.h (100%) rename components/soc/esp32h2/{include => register}/soc/intpri_reg.h (100%) rename components/soc/esp32h2/{include => register}/soc/intpri_struct.h (100%) rename components/soc/esp32h2/{include => register}/soc/io_mux_reg.h (99%) rename components/soc/esp32h2/{include => register}/soc/ledc_reg.h (100%) rename components/soc/esp32h2/{include => register}/soc/ledc_struct.h (100%) rename components/soc/esp32h2/{include => register}/soc/lp_analog_peri_reg.h (100%) rename components/soc/esp32h2/{include => register}/soc/lp_analog_peri_struct.h (100%) rename components/soc/esp32h2/{include => register}/soc/lp_aon_reg.h (100%) rename components/soc/esp32h2/{include => register}/soc/lp_aon_struct.h (100%) rename components/soc/esp32h2/{include => register}/soc/lp_apm0_reg.h (100%) rename components/soc/esp32h2/{include => register}/soc/lp_apm0_struct.h (100%) rename components/soc/esp32h2/{include => register}/soc/lp_apm_reg.h (100%) rename components/soc/esp32h2/{include => register}/soc/lp_apm_struct.h (100%) rename components/soc/esp32h2/{include => register}/soc/lp_clkrst_reg.h (100%) rename components/soc/esp32h2/{include => register}/soc/lp_clkrst_struct.h (100%) rename components/soc/esp32h2/{include => register}/soc/lp_timer_reg.h (100%) rename components/soc/esp32h2/{include => register}/soc/lp_timer_struct.h (100%) rename components/soc/esp32h2/{include => register}/soc/lp_wdt_reg.h (100%) rename components/soc/esp32h2/{include => register}/soc/lp_wdt_struct.h (100%) rename components/soc/esp32h2/{include => register}/soc/lpperi_reg.h (100%) rename components/soc/esp32h2/{include => register}/soc/lpperi_struct.h (100%) rename components/soc/esp32h2/{include => register}/soc/mcpwm_reg.h (99%) rename components/soc/esp32h2/{include => register}/soc/mcpwm_struct.h (99%) rename components/soc/esp32h2/{include => register}/soc/mem_monitor_reg.h (98%) rename components/soc/esp32h2/{include => register}/soc/mem_monitor_struct.h (98%) rename components/soc/esp32h2/{include => register}/soc/parl_io_reg.h (98%) rename components/soc/esp32h2/{include => register}/soc/parl_io_struct.h (98%) rename components/soc/esp32h2/{include => register}/soc/pau_reg.h (100%) rename components/soc/esp32h2/{include => register}/soc/pau_struct.h (100%) rename components/soc/esp32h2/{include => register}/soc/pcnt_reg.h (100%) rename components/soc/esp32h2/{include => register}/soc/pcnt_struct.h (100%) rename components/soc/esp32h2/{include => register}/soc/pcr_reg.h (99%) rename components/soc/esp32h2/{include => register}/soc/pcr_struct.h (98%) rename components/soc/esp32h2/{include => register}/soc/plic_reg.h (100%) rename components/soc/esp32h2/{include => register}/soc/pmu_reg.h (100%) rename components/soc/esp32h2/{include => register}/soc/pmu_struct.h (100%) rename components/soc/esp32h2/{include => register}/soc/reg_base.h (100%) rename components/soc/esp32h2/{include => register}/soc/rmt_reg.h (100%) rename components/soc/esp32h2/{include => register}/soc/rmt_struct.h (100%) rename components/soc/esp32h2/{include => register}/soc/rsa_reg.h (100%) rename components/soc/esp32h2/{include => register}/soc/rsa_struct.h (100%) rename components/soc/esp32h2/{include => register}/soc/sha_reg.h (98%) rename components/soc/esp32h2/{include => register}/soc/sha_struct.h (100%) rename components/soc/esp32h2/{include => register}/soc/soc_etm_reg.h (100%) rename components/soc/esp32h2/{include => register}/soc/soc_etm_struct.h (100%) rename components/soc/esp32h2/{include => register}/soc/spi_mem_reg.h (99%) rename components/soc/esp32h2/{include => register}/soc/spi_mem_struct.h (99%) rename components/soc/esp32h2/{include => register}/soc/spi_reg.h (99%) rename components/soc/esp32h2/{include => register}/soc/spi_struct.h (99%) rename components/soc/esp32h2/{include => register}/soc/systimer_reg.h (100%) rename components/soc/esp32h2/{include => register}/soc/systimer_struct.h (100%) rename components/soc/esp32h2/{include => register}/soc/tee_reg.h (100%) rename components/soc/esp32h2/{include => register}/soc/tee_struct.h (100%) rename components/soc/esp32h2/{include => register}/soc/timer_group_reg.h (100%) rename components/soc/esp32h2/{include => register}/soc/timer_group_struct.h (100%) rename components/soc/esp32h2/{include => register}/soc/trace_reg.h (99%) rename components/soc/esp32h2/{include => register}/soc/trace_struct.h (99%) rename components/soc/esp32h2/{include => register}/soc/twai_reg.h (100%) rename components/soc/esp32h2/{include => register}/soc/twai_struct.h (100%) rename components/soc/esp32h2/{include => register}/soc/uart_reg.h (99%) rename components/soc/esp32h2/{include => register}/soc/uart_struct.h (99%) rename components/soc/esp32h2/{include => register}/soc/uhci_reg.h (100%) rename components/soc/esp32h2/{include => register}/soc/uhci_struct.h (100%) rename components/soc/esp32h2/{include => register}/soc/usb_serial_jtag_reg.h (99%) rename components/soc/esp32h2/{include => register}/soc/usb_serial_jtag_struct.h (100%) rename components/soc/esp32h2/{include => register}/soc/xts_aes_reg.h (98%) diff --git a/components/soc/esp32c5/include/soc/usb_serial_jtag_reg.h b/components/soc/esp32c5/include/soc/usb_serial_jtag_reg.h index 5a8b1d4a06f..255d08ed4bb 100644 --- a/components/soc/esp32c5/include/soc/usb_serial_jtag_reg.h +++ b/components/soc/esp32c5/include/soc/usb_serial_jtag_reg.h @@ -653,7 +653,7 @@ extern "C" { #define USB_SERIAL_JTAG_TEST_ENABLE_V 0x00000001U #define USB_SERIAL_JTAG_TEST_ENABLE_S 0 /** USB_SERIAL_JTAG_TEST_USB_OE : R/W; bitpos: [1]; default: 0; - * USB pad one in test + * USB pad oen in test */ #define USB_SERIAL_JTAG_TEST_USB_OE (BIT(1)) #define USB_SERIAL_JTAG_TEST_USB_OE_M (USB_SERIAL_JTAG_TEST_USB_OE_V << USB_SERIAL_JTAG_TEST_USB_OE_S) diff --git a/components/soc/esp32c5/include/soc/usb_serial_jtag_struct.h b/components/soc/esp32c5/include/soc/usb_serial_jtag_struct.h index 21e8d68b209..603db37ff62 100644 --- a/components/soc/esp32c5/include/soc/usb_serial_jtag_struct.h +++ b/components/soc/esp32c5/include/soc/usb_serial_jtag_struct.h @@ -130,7 +130,7 @@ typedef union { */ uint32_t test_enable:1; /** test_usb_oe : R/W; bitpos: [1]; default: 0; - * USB pad one in test + * USB pad oen in test */ uint32_t test_usb_oe:1; /** test_tx_dp : R/W; bitpos: [2]; default: 0; diff --git a/components/soc/esp32h2/include/soc/dport_access.h b/components/soc/esp32h2/include/soc/dport_access.h index bc42aa9fecc..70f97e86b48 100644 --- a/components/soc/esp32h2/include/soc/dport_access.h +++ b/components/soc/esp32h2/include/soc/dport_access.h @@ -7,8 +7,7 @@ #pragma once #include -#include "soc.h" -#include "uart_reg.h" +#include "soc/soc.h" #ifdef __cplusplus extern "C" { diff --git a/components/soc/esp32h2/include/soc/interrupt_reg.h b/components/soc/esp32h2/include/soc/interrupt_reg.h index 1eb4721c840..4faef7949b9 100644 --- a/components/soc/esp32h2/include/soc/interrupt_reg.h +++ b/components/soc/esp32h2/include/soc/interrupt_reg.h @@ -5,8 +5,8 @@ */ #pragma once -#include "interrupt_matrix_reg.h" -#include "plic_reg.h" +#include "soc/interrupt_matrix_reg.h" +#include "soc/plic_reg.h" #include "soc/soc_caps.h" #define INTERRUPT_PRIO_REG(n) (PLIC_MXINT0_PRI_REG + (n)*4) diff --git a/components/soc/esp32h2/include/soc/soc.h b/components/soc/esp32h2/include/soc/soc.h index f3d2b2a9041..b35b9cc15fa 100644 --- a/components/soc/esp32h2/include/soc/soc.h +++ b/components/soc/esp32h2/include/soc/soc.h @@ -12,7 +12,7 @@ #endif #include "esp_bit_defs.h" -#include "reg_base.h" +#include "soc/reg_base.h" #define PRO_CPU_NUM (0) diff --git a/components/soc/esp32h2/include/soc/system_reg.h b/components/soc/esp32h2/include/soc/system_reg.h index 6a52d2da700..b2cb6089eec 100644 --- a/components/soc/esp32h2/include/soc/system_reg.h +++ b/components/soc/esp32h2/include/soc/system_reg.h @@ -5,7 +5,7 @@ */ #include "soc/hp_system_reg.h" -#include "intpri_reg.h" +#include "soc/intpri_reg.h" // ESP32H2-TODO : TODO: IDF-5720 #define SYSTEM_CPU_INTR_FROM_CPU_0_REG INTPRI_CPU_INTR_FROM_CPU_0_REG diff --git a/components/soc/esp32h2/register/soc/.gitkeep b/components/soc/esp32h2/register/soc/.gitkeep deleted file mode 100644 index e69de29bb2d..00000000000 diff --git a/components/soc/esp32h2/include/soc/aes_reg.h b/components/soc/esp32h2/register/soc/aes_reg.h similarity index 100% rename from components/soc/esp32h2/include/soc/aes_reg.h rename to components/soc/esp32h2/register/soc/aes_reg.h diff --git a/components/soc/esp32h2/include/soc/aes_struct.h b/components/soc/esp32h2/register/soc/aes_struct.h similarity index 100% rename from components/soc/esp32h2/include/soc/aes_struct.h rename to components/soc/esp32h2/register/soc/aes_struct.h diff --git a/components/soc/esp32h2/include/soc/apb_saradc_reg.h b/components/soc/esp32h2/register/soc/apb_saradc_reg.h similarity index 100% rename from components/soc/esp32h2/include/soc/apb_saradc_reg.h rename to components/soc/esp32h2/register/soc/apb_saradc_reg.h diff --git a/components/soc/esp32h2/include/soc/apb_saradc_struct.h b/components/soc/esp32h2/register/soc/apb_saradc_struct.h similarity index 100% rename from components/soc/esp32h2/include/soc/apb_saradc_struct.h rename to components/soc/esp32h2/register/soc/apb_saradc_struct.h diff --git a/components/soc/esp32h2/include/soc/assist_debug_reg.h b/components/soc/esp32h2/register/soc/assist_debug_reg.h similarity index 99% rename from components/soc/esp32h2/include/soc/assist_debug_reg.h rename to components/soc/esp32h2/register/soc/assist_debug_reg.h index 8e0426dc6f5..d2b947d9466 100644 --- a/components/soc/esp32h2/include/soc/assist_debug_reg.h +++ b/components/soc/esp32h2/register/soc/assist_debug_reg.h @@ -92,7 +92,7 @@ extern "C" { #define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_V 0x00000001U #define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_S 10 /** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA : R/W; bitpos: [11]; default: 0; - * DBUS busy monitor enbale + * DBUS busy monitor enable */ #define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA (BIT(11)) #define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_M (ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_V << ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_S) @@ -270,7 +270,7 @@ extern "C" { #define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_V 0x00000001U #define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_S 10 /** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS : R/W; bitpos: [11]; default: 0; - * DBUS busy monitor interrupt enbale + * DBUS busy monitor interrupt enable */ #define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS (BIT(11)) #define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_M (ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_V << ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_S) @@ -491,7 +491,7 @@ extern "C" { */ #define ASSIST_DEBUG_CORE_0_SP_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x38) /** ASSIST_DEBUG_CORE_0_SP_MIN : R/W; bitpos: [31:0]; default: 0; - * core0 sp region configuration regsiter + * core0 sp region configuration register */ #define ASSIST_DEBUG_CORE_0_SP_MIN 0xFFFFFFFFU #define ASSIST_DEBUG_CORE_0_SP_MIN_M (ASSIST_DEBUG_CORE_0_SP_MIN_V << ASSIST_DEBUG_CORE_0_SP_MIN_S) @@ -515,7 +515,7 @@ extern "C" { */ #define ASSIST_DEBUG_CORE_0_SP_PC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x40) /** ASSIST_DEBUG_CORE_0_SP_PC : RO; bitpos: [31:0]; default: 0; - * This regsiter stores the PC when trigger stack monitor. + * This register stores the PC when trigger stack monitor. */ #define ASSIST_DEBUG_CORE_0_SP_PC 0xFFFFFFFFU #define ASSIST_DEBUG_CORE_0_SP_PC_M (ASSIST_DEBUG_CORE_0_SP_PC_V << ASSIST_DEBUG_CORE_0_SP_PC_S) @@ -542,7 +542,7 @@ extern "C" { #define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_S 1 /** ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG register - * record status regsiter + * record status register */ #define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x48) /** ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC : RO; bitpos: [31:0]; default: 0; @@ -554,7 +554,7 @@ extern "C" { #define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_S 0 /** ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG register - * record status regsiter + * record status register */ #define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG (DR_REG_ASSIST_DEBUG_BASE + 0x4c) /** ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP : RO; bitpos: [31:0]; default: 0; diff --git a/components/soc/esp32h2/include/soc/assist_debug_struct.h b/components/soc/esp32h2/register/soc/assist_debug_struct.h similarity index 98% rename from components/soc/esp32h2/include/soc/assist_debug_struct.h rename to components/soc/esp32h2/register/soc/assist_debug_struct.h index c03f5792292..62323e8dbc1 100644 --- a/components/soc/esp32h2/include/soc/assist_debug_struct.h +++ b/components/soc/esp32h2/register/soc/assist_debug_struct.h @@ -61,7 +61,7 @@ typedef union { */ uint32_t core_0_iram0_exception_monitor_ena:1; /** core_0_dram0_exception_monitor_ena : R/W; bitpos: [11]; default: 0; - * DBUS busy monitor enbale + * DBUS busy monitor enable */ uint32_t core_0_dram0_exception_monitor_ena:1; uint32_t reserved_12:20; @@ -205,7 +205,7 @@ typedef union { typedef union { struct { /** core_0_sp_min : R/W; bitpos: [31:0]; default: 0; - * core0 sp region configuration regsiter + * core0 sp region configuration register */ uint32_t core_0_sp_min:32; }; @@ -231,7 +231,7 @@ typedef union { typedef union { struct { /** core_0_sp_pc : RO; bitpos: [31:0]; default: 0; - * This regsiter stores the PC when trigger stack monitor. + * This register stores the PC when trigger stack monitor. */ uint32_t core_0_sp_pc:32; }; @@ -348,7 +348,7 @@ typedef union { */ uint32_t core_0_iram0_exception_monitor_rls:1; /** core_0_dram0_exception_monitor_rls : R/W; bitpos: [11]; default: 0; - * DBUS busy monitor interrupt enbale + * DBUS busy monitor interrupt enable */ uint32_t core_0_dram0_exception_monitor_rls:1; uint32_t reserved_12:20; @@ -415,7 +415,7 @@ typedef union { } assist_debug_core_0_intr_clr_reg_t; -/** Group: pc reording configuration register */ +/** Group: pc recording configuration register */ /** Type of core_0_rcd_en register * record enable configuration register */ @@ -435,9 +435,9 @@ typedef union { } assist_debug_core_0_rcd_en_reg_t; -/** Group: pc reording status register */ +/** Group: pc recording status register */ /** Type of core_0_rcd_pdebugpc register - * record status regsiter + * record status register */ typedef union { struct { @@ -450,7 +450,7 @@ typedef union { } assist_debug_core_0_rcd_pdebugpc_reg_t; /** Type of core_0_rcd_pdebugsp register - * record status regsiter + * record status register */ typedef union { struct { @@ -463,7 +463,7 @@ typedef union { } assist_debug_core_0_rcd_pdebugsp_reg_t; -/** Group: exception monitor regsiter */ +/** Group: exception monitor register */ /** Type of core_0_iram0_exception_monitor_0 register * exception monitor status register0 */ diff --git a/components/soc/esp32h2/include/soc/cache_reg.h b/components/soc/esp32h2/register/soc/cache_reg.h similarity index 99% rename from components/soc/esp32h2/include/soc/cache_reg.h rename to components/soc/esp32h2/register/soc/cache_reg.h index d811eda10af..30181edf326 100644 --- a/components/soc/esp32h2/include/soc/cache_reg.h +++ b/components/soc/esp32h2/register/soc/cache_reg.h @@ -4185,7 +4185,7 @@ extern "C" { #define CACHE_L1_UNALLOCATE_BUFFER_CLEAR_REG (DR_REG_CACHE_BASE + 0x244) /** CACHE_L1_ICACHE0_UNALLOC_CLR : HRO; bitpos: [0]; default: 0; * The bit is used to clear the unallocate request buffer of l1 icache0 where the - * unallocate request is responsed but not completed. + * unallocate request is responded but not completed. */ #define CACHE_L1_ICACHE0_UNALLOC_CLR (BIT(0)) #define CACHE_L1_ICACHE0_UNALLOC_CLR_M (CACHE_L1_ICACHE0_UNALLOC_CLR_V << CACHE_L1_ICACHE0_UNALLOC_CLR_S) @@ -4193,7 +4193,7 @@ extern "C" { #define CACHE_L1_ICACHE0_UNALLOC_CLR_S 0 /** CACHE_L1_ICACHE1_UNALLOC_CLR : HRO; bitpos: [1]; default: 0; * The bit is used to clear the unallocate request buffer of l1 icache1 where the - * unallocate request is responsed but not completed. + * unallocate request is responded but not completed. */ #define CACHE_L1_ICACHE1_UNALLOC_CLR (BIT(1)) #define CACHE_L1_ICACHE1_UNALLOC_CLR_M (CACHE_L1_ICACHE1_UNALLOC_CLR_V << CACHE_L1_ICACHE1_UNALLOC_CLR_S) @@ -4215,7 +4215,7 @@ extern "C" { #define CACHE_L1_ICACHE3_UNALLOC_CLR_S 3 /** CACHE_L1_CACHE_UNALLOC_CLR : R/W; bitpos: [4]; default: 0; * The bit is used to clear the unallocate request buffer of l1 cache where the - * unallocate request is responsed but not completed. + * unallocate request is responded but not completed. */ #define CACHE_L1_CACHE_UNALLOC_CLR (BIT(4)) #define CACHE_L1_CACHE_UNALLOC_CLR_M (CACHE_L1_CACHE_UNALLOC_CLR_V << CACHE_L1_CACHE_UNALLOC_CLR_S) @@ -6025,7 +6025,7 @@ extern "C" { #define CACHE_L2_UNALLOCATE_BUFFER_CLEAR_REG (DR_REG_CACHE_BASE + 0x390) /** CACHE_L2_CACHE_UNALLOC_CLR : HRO; bitpos: [5]; default: 0; * The bit is used to clear the unallocate request buffer of l2 icache where the - * unallocate request is responsed but not completed. + * unallocate request is responded but not completed. */ #define CACHE_L2_CACHE_UNALLOC_CLR (BIT(5)) #define CACHE_L2_CACHE_UNALLOC_CLR_M (CACHE_L2_CACHE_UNALLOC_CLR_V << CACHE_L2_CACHE_UNALLOC_CLR_S) diff --git a/components/soc/esp32h2/include/soc/cache_struct.h b/components/soc/esp32h2/register/soc/cache_struct.h similarity index 99% rename from components/soc/esp32h2/include/soc/cache_struct.h rename to components/soc/esp32h2/register/soc/cache_struct.h index 7398f887ab6..32ec8a069c7 100644 --- a/components/soc/esp32h2/include/soc/cache_struct.h +++ b/components/soc/esp32h2/register/soc/cache_struct.h @@ -5115,12 +5115,12 @@ typedef union { struct { /** l1_icache0_unalloc_clr : HRO; bitpos: [0]; default: 0; * The bit is used to clear the unallocate request buffer of l1 icache0 where the - * unallocate request is responsed but not completed. + * unallocate request is responded but not completed. */ uint32_t l1_icache0_unalloc_clr:1; /** l1_icache1_unalloc_clr : HRO; bitpos: [1]; default: 0; * The bit is used to clear the unallocate request buffer of l1 icache1 where the - * unallocate request is responsed but not completed. + * unallocate request is responded but not completed. */ uint32_t l1_icache1_unalloc_clr:1; /** l1_icache2_unalloc_clr : HRO; bitpos: [2]; default: 0; @@ -5133,7 +5133,7 @@ typedef union { uint32_t l1_icache3_unalloc_clr:1; /** l1_cache_unalloc_clr : R/W; bitpos: [4]; default: 0; * The bit is used to clear the unallocate request buffer of l1 cache where the - * unallocate request is responsed but not completed. + * unallocate request is responded but not completed. */ uint32_t l1_cache_unalloc_clr:1; uint32_t reserved_5:27; @@ -5149,7 +5149,7 @@ typedef union { uint32_t reserved_0:5; /** l2_cache_unalloc_clr : HRO; bitpos: [5]; default: 0; * The bit is used to clear the unallocate request buffer of l2 icache where the - * unallocate request is responsed but not completed. + * unallocate request is responded but not completed. */ uint32_t l2_cache_unalloc_clr:1; uint32_t reserved_6:26; diff --git a/components/soc/esp32h2/include/soc/clint_reg.h b/components/soc/esp32h2/register/soc/clint_reg.h similarity index 100% rename from components/soc/esp32h2/include/soc/clint_reg.h rename to components/soc/esp32h2/register/soc/clint_reg.h diff --git a/components/soc/esp32h2/include/soc/ds_reg.h b/components/soc/esp32h2/register/soc/ds_reg.h similarity index 100% rename from components/soc/esp32h2/include/soc/ds_reg.h rename to components/soc/esp32h2/register/soc/ds_reg.h diff --git a/components/soc/esp32h2/include/soc/ds_struct.h b/components/soc/esp32h2/register/soc/ds_struct.h similarity index 100% rename from components/soc/esp32h2/include/soc/ds_struct.h rename to components/soc/esp32h2/register/soc/ds_struct.h diff --git a/components/soc/esp32h2/include/soc/ecc_mult_reg.h b/components/soc/esp32h2/register/soc/ecc_mult_reg.h similarity index 97% rename from components/soc/esp32h2/include/soc/ecc_mult_reg.h rename to components/soc/esp32h2/register/soc/ecc_mult_reg.h index 5d7fa6c1c30..bd6084940fe 100644 --- a/components/soc/esp32h2/include/soc/ecc_mult_reg.h +++ b/components/soc/esp32h2/register/soc/ecc_mult_reg.h @@ -64,7 +64,7 @@ extern "C" { */ #define ECC_MULT_CONF_REG (DR_REG_ECC_MULT_BASE + 0x1c) /** ECC_MULT_START : R/W/SC; bitpos: [0]; default: 0; - * Write 1 to start caculation of ECC Accelerator. This bit will be self-cleared after + * Write 1 to start calculation of ECC Accelerator. This bit will be self-cleared after * the caculatrion is done. */ #define ECC_MULT_START (BIT(0)) @@ -97,7 +97,7 @@ extern "C" { * The work mode bits of ECC Accelerator. 0: Point Mult Mode. 1: Reserved. 2: Point * verification mode. 3: Point Verif+mult mode. 4: Jacobian Point Mult Mode. 5: Point * Add Mode. 6: Jacobian Point Verification Mode. 7: Point Verif + Jacobian Mult Mode. - * 8: mod addition. 9. mod substraction. 10: mod multiplication. 11: mod division. + * 8: mod addition. 9. mod subtraction. 10: mod multiplication. 11: mod division. */ #define ECC_MULT_WORK_MODE 0x0000000FU #define ECC_MULT_WORK_MODE_M (ECC_MULT_WORK_MODE_V << ECC_MULT_WORK_MODE_S) diff --git a/components/soc/esp32h2/include/soc/ecc_mult_struct.h b/components/soc/esp32h2/register/soc/ecc_mult_struct.h similarity index 96% rename from components/soc/esp32h2/include/soc/ecc_mult_struct.h rename to components/soc/esp32h2/register/soc/ecc_mult_struct.h index f1596693a8d..a9f458c5d96 100644 --- a/components/soc/esp32h2/include/soc/ecc_mult_struct.h +++ b/components/soc/esp32h2/register/soc/ecc_mult_struct.h @@ -79,7 +79,7 @@ typedef union { typedef union { struct { /** start : R/W/SC; bitpos: [0]; default: 0; - * Write 1 to start caculation of ECC Accelerator. This bit will be self-cleared after + * Write 1 to start calculation of ECC Accelerator. This bit will be self-cleared after * the caculatrion is done. */ uint32_t start:1; @@ -100,7 +100,7 @@ typedef union { * The work mode bits of ECC Accelerator. 0: Point Mult Mode. 1: Reserved. 2: Point * verification mode. 3: Point Verif+mult mode. 4: Jacobian Point Mult Mode. 5: Point * Add Mode. 6: Jacobian Point Verification Mode. 7: Point Verif + Jacobian Mult Mode. - * 8: mod addition. 9. mod substraction. 10: mod multiplication. 11: mod division. + * 8: mod addition. 9. mod subtraction. 10: mod multiplication. 11: mod division. */ uint32_t work_mode:4; /** security_mode : R/W; bitpos: [8]; default: 0; diff --git a/components/soc/esp32h2/include/soc/ecdsa_reg.h b/components/soc/esp32h2/register/soc/ecdsa_reg.h similarity index 97% rename from components/soc/esp32h2/include/soc/ecdsa_reg.h rename to components/soc/esp32h2/register/soc/ecdsa_reg.h index 62f2e1ad96d..88f19ad16ce 100644 --- a/components/soc/esp32h2/include/soc/ecdsa_reg.h +++ b/components/soc/esp32h2/register/soc/ecdsa_reg.h @@ -140,7 +140,7 @@ extern "C" { */ #define ECDSA_START_REG (DR_REG_ECDSA_BASE + 0x1c) /** ECDSA_START : WT; bitpos: [0]; default: 0; - * Write 1 to start caculation of ECDSA Accelerator. This bit will be self-cleared + * Write 1 to start calculation of ECDSA Accelerator. This bit will be self-cleared * after configuration. */ #define ECDSA_START (BIT(0)) @@ -220,7 +220,7 @@ extern "C" { */ #define ECDSA_SHA_START_REG (DR_REG_ECDSA_BASE + 0x210) /** ECDSA_SHA_START : WT; bitpos: [0]; default: 0; - * Write 1 to start the first caculation of SHA Calculator in ECDSA Accelerator. This + * Write 1 to start the first calculation of SHA Calculator in ECDSA Accelerator. This * bit will be self-cleared after configuration. */ #define ECDSA_SHA_START (BIT(0)) @@ -233,7 +233,7 @@ extern "C" { */ #define ECDSA_SHA_CONTINUE_REG (DR_REG_ECDSA_BASE + 0x214) /** ECDSA_SHA_CONTINUE : WT; bitpos: [0]; default: 0; - * Write 1 to start the latter caculation of SHA Calculator in ECDSA Accelerator. This + * Write 1 to start the latter calculation of SHA Calculator in ECDSA Accelerator. This * bit will be self-cleared after configuration. */ #define ECDSA_SHA_CONTINUE (BIT(0)) diff --git a/components/soc/esp32h2/include/soc/ecdsa_struct.h b/components/soc/esp32h2/register/soc/ecdsa_struct.h similarity index 97% rename from components/soc/esp32h2/include/soc/ecdsa_struct.h rename to components/soc/esp32h2/register/soc/ecdsa_struct.h index dcdd806f8ff..ca9076e5526 100644 --- a/components/soc/esp32h2/include/soc/ecdsa_struct.h +++ b/components/soc/esp32h2/register/soc/ecdsa_struct.h @@ -48,7 +48,7 @@ typedef union { typedef union { struct { /** start : WT; bitpos: [0]; default: 0; - * Write 1 to start caculation of ECDSA Accelerator. This bit will be self-cleared + * Write 1 to start calculation of ECDSA Accelerator. This bit will be self-cleared * after configuration. */ uint32_t start:1; @@ -214,7 +214,7 @@ typedef union { typedef union { struct { /** sha_start : WT; bitpos: [0]; default: 0; - * Write 1 to start the first caculation of SHA Calculator in ECDSA Accelerator. This + * Write 1 to start the first calculation of SHA Calculator in ECDSA Accelerator. This * bit will be self-cleared after configuration. */ uint32_t sha_start:1; @@ -229,7 +229,7 @@ typedef union { typedef union { struct { /** sha_continue : WT; bitpos: [0]; default: 0; - * Write 1 to start the latter caculation of SHA Calculator in ECDSA Accelerator. This + * Write 1 to start the latter calculation of SHA Calculator in ECDSA Accelerator. This * bit will be self-cleared after configuration. */ uint32_t sha_continue:1; diff --git a/components/soc/esp32h2/include/soc/efuse_reg.h b/components/soc/esp32h2/register/soc/efuse_reg.h similarity index 99% rename from components/soc/esp32h2/include/soc/efuse_reg.h rename to components/soc/esp32h2/register/soc/efuse_reg.h index 532514d5876..915c37d8481 100644 --- a/components/soc/esp32h2/include/soc/efuse_reg.h +++ b/components/soc/esp32h2/register/soc/efuse_reg.h @@ -7,7 +7,7 @@ #include #include "soc/soc.h" -#include "efuse_defs.h" +#include "soc/efuse_defs.h" #ifdef __cplusplus extern "C" { #endif @@ -261,14 +261,14 @@ extern "C" { #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V 0x00000001U #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S 20 /** EFUSE_USB_DREFH : RO; bitpos: [22:21]; default: 0; - * Represents the single-end input threhold vrefh, 1.76 V to 2 V with step of 80 mV. + * Represents the single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV. */ #define EFUSE_USB_DREFH 0x00000003U #define EFUSE_USB_DREFH_M (EFUSE_USB_DREFH_V << EFUSE_USB_DREFH_S) #define EFUSE_USB_DREFH_V 0x00000003U #define EFUSE_USB_DREFH_S 21 /** EFUSE_USB_DREFL : RO; bitpos: [24:23]; default: 0; - * Represents the single-end input threhold vrefl, 1.76 V to 2 V with step of 80 mV. + * Represents the single-end input threshold vrefl, 1.76 V to 2 V with step of 80 mV. */ #define EFUSE_USB_DREFL 0x00000003U #define EFUSE_USB_DREFL_M (EFUSE_USB_DREFL_V << EFUSE_USB_DREFL_S) @@ -2355,7 +2355,7 @@ extern "C" { #define EFUSE_CLK_EN_S 16 /** EFUSE_CONF_REG register - * eFuse operation mode configuraiton register + * eFuse operation mode configuration register */ #define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x1cc) /** EFUSE_OP_CODE : R/W; bitpos: [15:0]; default: 0; diff --git a/components/soc/esp32h2/include/soc/efuse_struct.h b/components/soc/esp32h2/register/soc/efuse_struct.h similarity index 99% rename from components/soc/esp32h2/include/soc/efuse_struct.h rename to components/soc/esp32h2/register/soc/efuse_struct.h index c64eaa140c8..ab4c17e4750 100644 --- a/components/soc/esp32h2/include/soc/efuse_struct.h +++ b/components/soc/esp32h2/register/soc/efuse_struct.h @@ -236,11 +236,11 @@ typedef union { */ uint32_t dis_download_manual_encrypt:1; /** usb_drefh : RO; bitpos: [22:21]; default: 0; - * Represents the single-end input threhold vrefh, 1.76 V to 2 V with step of 80 mV. + * Represents the single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV. */ uint32_t usb_drefh:2; /** usb_drefl : RO; bitpos: [24:23]; default: 0; - * Represents the single-end input threhold vrefl, 1.76 V to 2 V with step of 80 mV. + * Represents the single-end input threshold vrefl, 1.76 V to 2 V with step of 80 mV. */ uint32_t usb_drefl:2; /** usb_exchg_pins : RO; bitpos: [25]; default: 0; @@ -2007,7 +2007,7 @@ typedef union { } efuse_clk_reg_t; /** Type of conf register - * eFuse operation mode configuraiton register + * eFuse operation mode configuration register */ typedef union { struct { diff --git a/components/soc/esp32h2/include/soc/extmem_reg.h b/components/soc/esp32h2/register/soc/extmem_reg.h similarity index 98% rename from components/soc/esp32h2/include/soc/extmem_reg.h rename to components/soc/esp32h2/register/soc/extmem_reg.h index b53ab467314..c277ae582c2 100644 --- a/components/soc/esp32h2/include/soc/extmem_reg.h +++ b/components/soc/esp32h2/register/soc/extmem_reg.h @@ -10,7 +10,7 @@ #ifdef __cplusplus extern "C" { #endif -#include "soc.h" +#include "soc/soc.h" #define CACHE_L1_CACHE_CTRL_REG (DR_REG_CACHE_BASE + 0x4) /* CACHE_L1_CACHE_SHUT_BUS1 : R/W ;bitpos:[1] ;default: 1'h0 ; */ @@ -250,8 +250,8 @@ ould be used together with CACHE_LOCK_ADDR_REG.*/ #define CACHE_SYNC_DONE_S 4 /* CACHE_WRITEBACK_INVALIDATE_ENA : R/W/SC ;bitpos:[3] ;default: 1'h0 ; */ /*description: The bit is used to enable writeback-invalidate operation. It will be cleared by -hardware after writeback-invalidate operation done. Note that this bit and the o -ther sync-bits (invalidate_ena, clean_ena, writeback_ena) are mutually exclusive +hardware after writeback-invalidate operation done. Note that this bit and the +other sync-bits (invalidate_ena, clean_ena, writeback_ena) are mutually exclusive , that is, those bits can not be set to 1 at the same time..*/ #define CACHE_WRITEBACK_INVALIDATE_ENA (BIT(3)) #define CACHE_WRITEBACK_INVALIDATE_ENA_M (BIT(3)) @@ -269,16 +269,16 @@ those bits can not be set to 1 at the same time..*/ /* CACHE_CLEAN_ENA : R/W/SC ;bitpos:[1] ;default: 1'h0 ; */ /*description: The bit is used to enable clean operation. It will be cleared by hardware after clean operation done. Note that this bit and the other sync-bits (invalidate_ena -, writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is, thos -e bits can not be set to 1 at the same time..*/ +, writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is, those +bits can not be set to 1 at the same time..*/ #define CACHE_CLEAN_ENA (BIT(1)) #define CACHE_CLEAN_ENA_M (BIT(1)) #define CACHE_CLEAN_ENA_V 0x1 #define CACHE_CLEAN_ENA_S 1 /* CACHE_INVALIDATE_ENA : R/W/SC ;bitpos:[0] ;default: 1'h1 ; */ /*description: The bit is used to enable invalidate operation. It will be cleared by hardware a -fter invalidate operation done. Note that this bit and the other sync-bits (clea -n_ena, writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is, +after invalidate operation done. Note that this bit and the other sync-bits (clean_ena, +writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is, those bits can not be set to 1 at the same time..*/ #define CACHE_INVALIDATE_ENA (BIT(0)) #define CACHE_INVALIDATE_ENA_M (BIT(0)) @@ -499,15 +499,15 @@ SCT3_ADDR and L1_CACHE_AUTOLOAD_SCT3_ENA..*/ #define CACHE_L1_CACHE_ACS_CNT_INT_CLR_REG (DR_REG_CACHE_BASE + 0x15C) /* CACHE_L1_BUS1_OVF_INT_CLR : WT ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The bit is used to clear counters overflow interrupt and counters in L1-DCache d -ue to bus1 accesses L1-DCache..*/ +/*description: The bit is used to clear counters overflow interrupt and counters in L1-DCache +due to bus1 accesses L1-DCache..*/ #define CACHE_L1_BUS1_OVF_INT_CLR (BIT(5)) #define CACHE_L1_BUS1_OVF_INT_CLR_M (BIT(5)) #define CACHE_L1_BUS1_OVF_INT_CLR_V 0x1 #define CACHE_L1_BUS1_OVF_INT_CLR_S 5 /* CACHE_L1_BUS0_OVF_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The bit is used to clear counters overflow interrupt and counters in L1-DCache d -ue to bus0 accesses L1-DCache..*/ +/*description: The bit is used to clear counters overflow interrupt and counters in L1-DCache +due to bus0 accesses L1-DCache..*/ #define CACHE_L1_BUS0_OVF_INT_CLR (BIT(4)) #define CACHE_L1_BUS0_OVF_INT_CLR_M (BIT(4)) #define CACHE_L1_BUS0_OVF_INT_CLR_V 0x1 @@ -573,8 +573,8 @@ o cpu accesses L1-DCache..*/ #define CACHE_L1_CACHE_ACS_FAIL_INT_ST_REG (DR_REG_CACHE_BASE + 0x174) /* CACHE_L1_CACHE_FAIL_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The bit indicates the interrupt status of access fail that occurs in L1-DCache d -ue to cpu accesses L1-DCache..*/ +/*description: The bit indicates the interrupt status of access fail that occurs in L1-DCache +due to cpu accesses L1-DCache..*/ #define CACHE_L1_CACHE_FAIL_INT_ST (BIT(4)) #define CACHE_L1_CACHE_FAIL_INT_ST_M (BIT(4)) #define CACHE_L1_CACHE_FAIL_INT_ST_V 0x1 @@ -787,7 +787,7 @@ ror occurs..*/ #define CACHE_SYNC_ERR_INT_ST_V 0x1 #define CACHE_SYNC_ERR_INT_ST_S 13 /* CACHE_L1_CACHE_PLD_ERR_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: The bit indicates the status of the interrupt of L1-Cache preload-operation erro +/*description: The bit indicates the status of the interrupt of L1-Cache preload-operation error r..*/ #define CACHE_L1_CACHE_PLD_ERR_INT_ST (BIT(11)) #define CACHE_L1_CACHE_PLD_ERR_INT_ST_M (BIT(11)) @@ -825,7 +825,7 @@ load-operation is done..*/ #define CACHE_L1_CACHE_SYNC_RST_CTRL_REG (DR_REG_CACHE_BASE + 0x238) /* CACHE_L1_CACHE_SYNC_RST : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: set this bit to reset sync-logic inside L1-Cache. Recommend that this should onl +/*description: set this bit to reset sync-logic inside L1-Cache. Recommend that this should only y be used to initialize sync-logic when some fatal error of sync-logic occurs..*/ #define CACHE_L1_CACHE_SYNC_RST (BIT(4)) #define CACHE_L1_CACHE_SYNC_RST_M (BIT(4)) @@ -855,7 +855,7 @@ rks in L1-Cache..*/ #define CACHE_L1_UNALLOCATE_BUFFER_CLEAR_REG (DR_REG_CACHE_BASE + 0x244) /* CACHE_L1_CACHE_UNALLOC_CLR : R/W ;bitpos:[4] ;default: 1'b0 ; */ /*description: The bit is used to clear the unallocate request buffer of l1 cache where the una -llocate request is responsed but not completed..*/ +llocate request is responded but not completed..*/ #define CACHE_L1_CACHE_UNALLOC_CLR (BIT(4)) #define CACHE_L1_CACHE_UNALLOC_CLR_M (BIT(4)) #define CACHE_L1_CACHE_UNALLOC_CLR_V 0x1 @@ -870,7 +870,7 @@ th the others fields inside this register..*/ #define CACHE_L1_CACHE_MEM_OBJECT_V 0x1 #define CACHE_L1_CACHE_MEM_OBJECT_S 10 /* CACHE_L1_CACHE_TAG_OBJECT : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: Set this bit to set L1-Cache tag memory as object. This bit should be onehot wit +/*description: Set this bit to set L1-Cache tag memory as object. This bit should be onehot with h the others fields inside this register..*/ #define CACHE_L1_CACHE_TAG_OBJECT (BIT(4)) #define CACHE_L1_CACHE_TAG_OBJECT_M (BIT(4)) @@ -888,8 +888,8 @@ h the others fields inside this register..*/ #define CACHE_L1_CACHE_VADDR_REG (DR_REG_CACHE_BASE + 0x250) /* CACHE_L1_CACHE_VADDR : R/W ;bitpos:[31:0] ;default: 32'h40000000 ; */ -/*description: Those bits stores the virtual address which will decide where inside the specifi -ed tag memory object will be accessed..*/ +/*description: Those bits stores the virtual address which will decide where inside the specified +tag memory object will be accessed..*/ #define CACHE_L1_CACHE_VADDR 0xFFFFFFFF #define CACHE_L1_CACHE_VADDR_M ((CACHE_L1_CACHE_VADDR_V)<<(CACHE_L1_CACHE_VADDR_S)) #define CACHE_L1_CACHE_VADDR_V 0xFFFFFFFF diff --git a/components/soc/esp32h2/include/soc/extmem_struct.h b/components/soc/esp32h2/register/soc/extmem_struct.h similarity index 99% rename from components/soc/esp32h2/include/soc/extmem_struct.h rename to components/soc/esp32h2/register/soc/extmem_struct.h index d309e09235e..d43c5fcee3d 100644 --- a/components/soc/esp32h2/include/soc/extmem_struct.h +++ b/components/soc/esp32h2/register/soc/extmem_struct.h @@ -5115,12 +5115,12 @@ typedef union { struct { /** l1_icache0_unalloc_clr : HRO; bitpos: [0]; default: 0; * The bit is used to clear the unallocate request buffer of l1 icache0 where the - * unallocate request is responsed but not completed. + * unallocate request is responded but not completed. */ uint32_t l1_icache0_unalloc_clr:1; /** l1_icache1_unalloc_clr : HRO; bitpos: [1]; default: 0; * The bit is used to clear the unallocate request buffer of l1 icache1 where the - * unallocate request is responsed but not completed. + * unallocate request is responded but not completed. */ uint32_t l1_icache1_unalloc_clr:1; /** l1_icache2_unalloc_clr : HRO; bitpos: [2]; default: 0; @@ -5133,7 +5133,7 @@ typedef union { uint32_t l1_icache3_unalloc_clr:1; /** l1_cache_unalloc_clr : R/W; bitpos: [4]; default: 0; * The bit is used to clear the unallocate request buffer of l1 cache where the - * unallocate request is responsed but not completed. + * unallocate request is responded but not completed. */ uint32_t l1_cache_unalloc_clr:1; uint32_t reserved_5:27; @@ -5149,7 +5149,7 @@ typedef union { uint32_t reserved_0:5; /** l2_cache_unalloc_clr : HRO; bitpos: [5]; default: 0; * The bit is used to clear the unallocate request buffer of l2 icache where the - * unallocate request is responsed but not completed. + * unallocate request is responded but not completed. */ uint32_t l2_cache_unalloc_clr:1; uint32_t reserved_6:26; diff --git a/components/soc/esp32h2/include/soc/gdma_reg.h b/components/soc/esp32h2/register/soc/gdma_reg.h similarity index 100% rename from components/soc/esp32h2/include/soc/gdma_reg.h rename to components/soc/esp32h2/register/soc/gdma_reg.h diff --git a/components/soc/esp32h2/include/soc/gdma_struct.h b/components/soc/esp32h2/register/soc/gdma_struct.h similarity index 100% rename from components/soc/esp32h2/include/soc/gdma_struct.h rename to components/soc/esp32h2/register/soc/gdma_struct.h diff --git a/components/soc/esp32h2/include/soc/gpio_ext_reg.h b/components/soc/esp32h2/register/soc/gpio_ext_reg.h similarity index 100% rename from components/soc/esp32h2/include/soc/gpio_ext_reg.h rename to components/soc/esp32h2/register/soc/gpio_ext_reg.h diff --git a/components/soc/esp32h2/include/soc/gpio_ext_struct.h b/components/soc/esp32h2/register/soc/gpio_ext_struct.h similarity index 100% rename from components/soc/esp32h2/include/soc/gpio_ext_struct.h rename to components/soc/esp32h2/register/soc/gpio_ext_struct.h diff --git a/components/soc/esp32h2/include/soc/gpio_reg.h b/components/soc/esp32h2/register/soc/gpio_reg.h similarity index 100% rename from components/soc/esp32h2/include/soc/gpio_reg.h rename to components/soc/esp32h2/register/soc/gpio_reg.h diff --git a/components/soc/esp32h2/include/soc/gpio_struct.h b/components/soc/esp32h2/register/soc/gpio_struct.h similarity index 100% rename from components/soc/esp32h2/include/soc/gpio_struct.h rename to components/soc/esp32h2/register/soc/gpio_struct.h diff --git a/components/soc/esp32h2/include/soc/hmac_reg.h b/components/soc/esp32h2/register/soc/hmac_reg.h similarity index 100% rename from components/soc/esp32h2/include/soc/hmac_reg.h rename to components/soc/esp32h2/register/soc/hmac_reg.h diff --git a/components/soc/esp32h2/include/soc/hmac_struct.h b/components/soc/esp32h2/register/soc/hmac_struct.h similarity index 100% rename from components/soc/esp32h2/include/soc/hmac_struct.h rename to components/soc/esp32h2/register/soc/hmac_struct.h diff --git a/components/soc/esp32h2/include/soc/hp_apm_reg.h b/components/soc/esp32h2/register/soc/hp_apm_reg.h similarity index 100% rename from components/soc/esp32h2/include/soc/hp_apm_reg.h rename to components/soc/esp32h2/register/soc/hp_apm_reg.h diff --git a/components/soc/esp32h2/include/soc/hp_apm_struct.h b/components/soc/esp32h2/register/soc/hp_apm_struct.h similarity index 100% rename from components/soc/esp32h2/include/soc/hp_apm_struct.h rename to components/soc/esp32h2/register/soc/hp_apm_struct.h diff --git a/components/soc/esp32h2/include/soc/hp_system_reg.h b/components/soc/esp32h2/register/soc/hp_system_reg.h similarity index 99% rename from components/soc/esp32h2/include/soc/hp_system_reg.h rename to components/soc/esp32h2/register/soc/hp_system_reg.h index 1660509115e..842750731d8 100644 --- a/components/soc/esp32h2/include/soc/hp_system_reg.h +++ b/components/soc/esp32h2/register/soc/hp_system_reg.h @@ -78,7 +78,7 @@ extern "C" { * 0: anti-DPA disable. 1~3: anti-DPA enable with different security level. The larger * the number, the stronger the ability to resist DPA attacks and the higher the * security level, but it will increase the computational overhead of the hardware - * crypto-accelerators. Only avaliable if HP_SYSTEM_SEC_DPA_CFG_SEL is 0. + * crypto-accelerators. Only available if HP_SYSTEM_SEC_DPA_CFG_SEL is 0. */ #define HP_SYSTEM_SEC_DPA_LEVEL 0x00000003U #define HP_SYSTEM_SEC_DPA_LEVEL_M (HP_SYSTEM_SEC_DPA_LEVEL_V << HP_SYSTEM_SEC_DPA_LEVEL_S) diff --git a/components/soc/esp32h2/include/soc/hp_system_struct.h b/components/soc/esp32h2/register/soc/hp_system_struct.h similarity index 99% rename from components/soc/esp32h2/include/soc/hp_system_struct.h rename to components/soc/esp32h2/register/soc/hp_system_struct.h index 575349312bc..4dcaf955003 100644 --- a/components/soc/esp32h2/include/soc/hp_system_struct.h +++ b/components/soc/esp32h2/register/soc/hp_system_struct.h @@ -70,7 +70,7 @@ typedef union { * 0: anti-DPA disable. 1~3: anti-DPA enable with different security level. The larger * the number, the stronger the ability to resist DPA attacks and the higher the * security level, but it will increase the computational overhead of the hardware - * crypto-accelerators. Only avaliable if HP_SYS_SEC_DPA_CFG_SEL is 0. + * crypto-accelerators. Only available if HP_SYS_SEC_DPA_CFG_SEL is 0. */ uint32_t sec_dpa_level:2; /** sec_dpa_cfg_sel : R/W; bitpos: [2]; default: 0; diff --git a/components/soc/esp32h2/include/soc/i2c_ana_mst_reg.h b/components/soc/esp32h2/register/soc/i2c_ana_mst_reg.h similarity index 100% rename from components/soc/esp32h2/include/soc/i2c_ana_mst_reg.h rename to components/soc/esp32h2/register/soc/i2c_ana_mst_reg.h diff --git a/components/soc/esp32h2/include/soc/i2c_reg.h b/components/soc/esp32h2/register/soc/i2c_reg.h similarity index 100% rename from components/soc/esp32h2/include/soc/i2c_reg.h rename to components/soc/esp32h2/register/soc/i2c_reg.h diff --git a/components/soc/esp32h2/include/soc/i2c_struct.h b/components/soc/esp32h2/register/soc/i2c_struct.h similarity index 100% rename from components/soc/esp32h2/include/soc/i2c_struct.h rename to components/soc/esp32h2/register/soc/i2c_struct.h diff --git a/components/soc/esp32h2/include/soc/i2s_reg.h b/components/soc/esp32h2/register/soc/i2s_reg.h similarity index 99% rename from components/soc/esp32h2/include/soc/i2s_reg.h rename to components/soc/esp32h2/register/soc/i2s_reg.h index b79bdd298c3..95b982407e6 100644 --- a/components/soc/esp32h2/include/soc/i2s_reg.h +++ b/components/soc/esp32h2/register/soc/i2s_reg.h @@ -320,7 +320,7 @@ extern "C" { #define I2S_TX_SLAVE_MOD_V 0x00000001U #define I2S_TX_SLAVE_MOD_S 3 /** I2S_TX_STOP_EN : R/W; bitpos: [4]; default: 1; - * Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy + * Set this bit to stop disable output BCK signal and WS signal when tx FIFO is empty */ #define I2S_TX_STOP_EN (BIT(4)) #define I2S_TX_STOP_EN_M (I2S_TX_STOP_EN_V << I2S_TX_STOP_EN_S) diff --git a/components/soc/esp32h2/include/soc/i2s_struct.h b/components/soc/esp32h2/register/soc/i2s_struct.h similarity index 99% rename from components/soc/esp32h2/include/soc/i2s_struct.h rename to components/soc/esp32h2/register/soc/i2s_struct.h index 34f876838f8..0a01bf6f670 100644 --- a/components/soc/esp32h2/include/soc/i2s_struct.h +++ b/components/soc/esp32h2/register/soc/i2s_struct.h @@ -459,7 +459,7 @@ typedef union { */ uint32_t tx_slave_mod:1; /** tx_stop_en : R/W; bitpos: [4]; default: 1; - * Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy + * Set this bit to stop disable output BCK signal and WS signal when tx FIFO is empty */ uint32_t tx_stop_en:1; /** tx_chan_equal : R/W; bitpos: [5]; default: 0; diff --git a/components/soc/esp32h2/include/soc/ieee802154_reg.h b/components/soc/esp32h2/register/soc/ieee802154_reg.h similarity index 100% rename from components/soc/esp32h2/include/soc/ieee802154_reg.h rename to components/soc/esp32h2/register/soc/ieee802154_reg.h diff --git a/components/soc/esp32h2/include/soc/ieee802154_struct.h b/components/soc/esp32h2/register/soc/ieee802154_struct.h similarity index 100% rename from components/soc/esp32h2/include/soc/ieee802154_struct.h rename to components/soc/esp32h2/register/soc/ieee802154_struct.h diff --git a/components/soc/esp32h2/include/soc/interrupt_matrix_reg.h b/components/soc/esp32h2/register/soc/interrupt_matrix_reg.h similarity index 100% rename from components/soc/esp32h2/include/soc/interrupt_matrix_reg.h rename to components/soc/esp32h2/register/soc/interrupt_matrix_reg.h diff --git a/components/soc/esp32h2/include/soc/interrupt_matrix_struct.h b/components/soc/esp32h2/register/soc/interrupt_matrix_struct.h similarity index 100% rename from components/soc/esp32h2/include/soc/interrupt_matrix_struct.h rename to components/soc/esp32h2/register/soc/interrupt_matrix_struct.h diff --git a/components/soc/esp32h2/include/soc/intpri_reg.h b/components/soc/esp32h2/register/soc/intpri_reg.h similarity index 100% rename from components/soc/esp32h2/include/soc/intpri_reg.h rename to components/soc/esp32h2/register/soc/intpri_reg.h diff --git a/components/soc/esp32h2/include/soc/intpri_struct.h b/components/soc/esp32h2/register/soc/intpri_struct.h similarity index 100% rename from components/soc/esp32h2/include/soc/intpri_struct.h rename to components/soc/esp32h2/register/soc/intpri_struct.h diff --git a/components/soc/esp32h2/include/soc/io_mux_reg.h b/components/soc/esp32h2/register/soc/io_mux_reg.h similarity index 99% rename from components/soc/esp32h2/include/soc/io_mux_reg.h rename to components/soc/esp32h2/register/soc/io_mux_reg.h index 5db79e1673a..4bbb466906a 100644 --- a/components/soc/esp32h2/include/soc/io_mux_reg.h +++ b/components/soc/esp32h2/register/soc/io_mux_reg.h @@ -5,7 +5,7 @@ */ #pragma once -#include "soc.h" +#include "soc/soc.h" /* The following are the bit fields for PERIPHS_IO_MUX_x_U registers */ /* Output enable in sleep mode */ @@ -79,7 +79,7 @@ #define HYS_EN_S 16 /* HYS_SEL : R/W; bitpos: [17]; default: 0; * Select enabling signals of the pad from software and efuse hardware. - * 1: Select enabling siganl from software. + * 1: Select enabling signal from software. * 0: Select enabling signal from efuse hardware. */ #define HYS_SEL (BIT(17)) diff --git a/components/soc/esp32h2/include/soc/ledc_reg.h b/components/soc/esp32h2/register/soc/ledc_reg.h similarity index 100% rename from components/soc/esp32h2/include/soc/ledc_reg.h rename to components/soc/esp32h2/register/soc/ledc_reg.h diff --git a/components/soc/esp32h2/include/soc/ledc_struct.h b/components/soc/esp32h2/register/soc/ledc_struct.h similarity index 100% rename from components/soc/esp32h2/include/soc/ledc_struct.h rename to components/soc/esp32h2/register/soc/ledc_struct.h diff --git a/components/soc/esp32h2/include/soc/lp_analog_peri_reg.h b/components/soc/esp32h2/register/soc/lp_analog_peri_reg.h similarity index 100% rename from components/soc/esp32h2/include/soc/lp_analog_peri_reg.h rename to components/soc/esp32h2/register/soc/lp_analog_peri_reg.h diff --git a/components/soc/esp32h2/include/soc/lp_analog_peri_struct.h b/components/soc/esp32h2/register/soc/lp_analog_peri_struct.h similarity index 100% rename from components/soc/esp32h2/include/soc/lp_analog_peri_struct.h rename to components/soc/esp32h2/register/soc/lp_analog_peri_struct.h diff --git a/components/soc/esp32h2/include/soc/lp_aon_reg.h b/components/soc/esp32h2/register/soc/lp_aon_reg.h similarity index 100% rename from components/soc/esp32h2/include/soc/lp_aon_reg.h rename to components/soc/esp32h2/register/soc/lp_aon_reg.h diff --git a/components/soc/esp32h2/include/soc/lp_aon_struct.h b/components/soc/esp32h2/register/soc/lp_aon_struct.h similarity index 100% rename from components/soc/esp32h2/include/soc/lp_aon_struct.h rename to components/soc/esp32h2/register/soc/lp_aon_struct.h diff --git a/components/soc/esp32h2/include/soc/lp_apm0_reg.h b/components/soc/esp32h2/register/soc/lp_apm0_reg.h similarity index 100% rename from components/soc/esp32h2/include/soc/lp_apm0_reg.h rename to components/soc/esp32h2/register/soc/lp_apm0_reg.h diff --git a/components/soc/esp32h2/include/soc/lp_apm0_struct.h b/components/soc/esp32h2/register/soc/lp_apm0_struct.h similarity index 100% rename from components/soc/esp32h2/include/soc/lp_apm0_struct.h rename to components/soc/esp32h2/register/soc/lp_apm0_struct.h diff --git a/components/soc/esp32h2/include/soc/lp_apm_reg.h b/components/soc/esp32h2/register/soc/lp_apm_reg.h similarity index 100% rename from components/soc/esp32h2/include/soc/lp_apm_reg.h rename to components/soc/esp32h2/register/soc/lp_apm_reg.h diff --git a/components/soc/esp32h2/include/soc/lp_apm_struct.h b/components/soc/esp32h2/register/soc/lp_apm_struct.h similarity index 100% rename from components/soc/esp32h2/include/soc/lp_apm_struct.h rename to components/soc/esp32h2/register/soc/lp_apm_struct.h diff --git a/components/soc/esp32h2/include/soc/lp_clkrst_reg.h b/components/soc/esp32h2/register/soc/lp_clkrst_reg.h similarity index 100% rename from components/soc/esp32h2/include/soc/lp_clkrst_reg.h rename to components/soc/esp32h2/register/soc/lp_clkrst_reg.h diff --git a/components/soc/esp32h2/include/soc/lp_clkrst_struct.h b/components/soc/esp32h2/register/soc/lp_clkrst_struct.h similarity index 100% rename from components/soc/esp32h2/include/soc/lp_clkrst_struct.h rename to components/soc/esp32h2/register/soc/lp_clkrst_struct.h diff --git a/components/soc/esp32h2/include/soc/lp_timer_reg.h b/components/soc/esp32h2/register/soc/lp_timer_reg.h similarity index 100% rename from components/soc/esp32h2/include/soc/lp_timer_reg.h rename to components/soc/esp32h2/register/soc/lp_timer_reg.h diff --git a/components/soc/esp32h2/include/soc/lp_timer_struct.h b/components/soc/esp32h2/register/soc/lp_timer_struct.h similarity index 100% rename from components/soc/esp32h2/include/soc/lp_timer_struct.h rename to components/soc/esp32h2/register/soc/lp_timer_struct.h diff --git a/components/soc/esp32h2/include/soc/lp_wdt_reg.h b/components/soc/esp32h2/register/soc/lp_wdt_reg.h similarity index 100% rename from components/soc/esp32h2/include/soc/lp_wdt_reg.h rename to components/soc/esp32h2/register/soc/lp_wdt_reg.h diff --git a/components/soc/esp32h2/include/soc/lp_wdt_struct.h b/components/soc/esp32h2/register/soc/lp_wdt_struct.h similarity index 100% rename from components/soc/esp32h2/include/soc/lp_wdt_struct.h rename to components/soc/esp32h2/register/soc/lp_wdt_struct.h diff --git a/components/soc/esp32h2/include/soc/lpperi_reg.h b/components/soc/esp32h2/register/soc/lpperi_reg.h similarity index 100% rename from components/soc/esp32h2/include/soc/lpperi_reg.h rename to components/soc/esp32h2/register/soc/lpperi_reg.h diff --git a/components/soc/esp32h2/include/soc/lpperi_struct.h b/components/soc/esp32h2/register/soc/lpperi_struct.h similarity index 100% rename from components/soc/esp32h2/include/soc/lpperi_struct.h rename to components/soc/esp32h2/register/soc/lpperi_struct.h diff --git a/components/soc/esp32h2/include/soc/mcpwm_reg.h b/components/soc/esp32h2/register/soc/mcpwm_reg.h similarity index 99% rename from components/soc/esp32h2/include/soc/mcpwm_reg.h rename to components/soc/esp32h2/register/soc/mcpwm_reg.h index f851de75cee..a14ba71be36 100644 --- a/components/soc/esp32h2/include/soc/mcpwm_reg.h +++ b/components/soc/esp32h2/register/soc/mcpwm_reg.h @@ -894,7 +894,7 @@ extern "C" { #define MCPWM_DB0_RED_S 0 /** MCPWM_CARRIER0_CFG_REG register - * Carrier enable and configuratoin + * Carrier enable and configuration */ #define MCPWM_CARRIER0_CFG_REG (DR_REG_MCPWM_BASE + 0x64) /** MCPWM_CHOPPER0_EN : R/W; bitpos: [0]; default: 0; @@ -1575,7 +1575,7 @@ extern "C" { #define MCPWM_DB1_RED_S 0 /** MCPWM_CARRIER1_CFG_REG register - * Carrier enable and configuratoin + * Carrier enable and configuration */ #define MCPWM_CARRIER1_CFG_REG (DR_REG_MCPWM_BASE + 0x9c) /** MCPWM_CHOPPER1_EN : R/W; bitpos: [0]; default: 0; @@ -2256,7 +2256,7 @@ extern "C" { #define MCPWM_DB2_RED_S 0 /** MCPWM_CARRIER2_CFG_REG register - * Carrier enable and configuratoin + * Carrier enable and configuration */ #define MCPWM_CARRIER2_CFG_REG (DR_REG_MCPWM_BASE + 0xd4) /** MCPWM_CHOPPER2_EN : R/W; bitpos: [0]; default: 0; @@ -2621,7 +2621,7 @@ extern "C" { #define MCPWM_CAP0_MODE_V 0x00000003U #define MCPWM_CAP0_MODE_S 1 /** MCPWM_CAP0_PRESCALE : R/W; bitpos: [10:3]; default: 0; - * Value of prescaling on possitive edge of CAP0. Prescale value = PWM_CAP0_PRESCALE + + * Value of prescaling on positive edge of CAP0. Prescale value = PWM_CAP0_PRESCALE + * 1 */ #define MCPWM_CAP0_PRESCALE 0x000000FFU @@ -2664,7 +2664,7 @@ extern "C" { #define MCPWM_CAP1_MODE_V 0x00000003U #define MCPWM_CAP1_MODE_S 1 /** MCPWM_CAP1_PRESCALE : R/W; bitpos: [10:3]; default: 0; - * Value of prescaling on possitive edge of CAP1. Prescale value = PWM_CAP1_PRESCALE + + * Value of prescaling on positive edge of CAP1. Prescale value = PWM_CAP1_PRESCALE + * 1 */ #define MCPWM_CAP1_PRESCALE 0x000000FFU @@ -2707,7 +2707,7 @@ extern "C" { #define MCPWM_CAP2_MODE_V 0x00000003U #define MCPWM_CAP2_MODE_S 1 /** MCPWM_CAP2_PRESCALE : R/W; bitpos: [10:3]; default: 0; - * Value of prescaling on possitive edge of CAP2. Prescale value = PWM_CAP2_PRESCALE + + * Value of prescaling on positive edge of CAP2. Prescale value = PWM_CAP2_PRESCALE + * 1 */ #define MCPWM_CAP2_PRESCALE 0x000000FFU diff --git a/components/soc/esp32h2/include/soc/mcpwm_struct.h b/components/soc/esp32h2/register/soc/mcpwm_struct.h similarity index 99% rename from components/soc/esp32h2/include/soc/mcpwm_struct.h rename to components/soc/esp32h2/register/soc/mcpwm_struct.h index 1a91a623f6b..5fe75f3c99e 100644 --- a/components/soc/esp32h2/include/soc/mcpwm_struct.h +++ b/components/soc/esp32h2/register/soc/mcpwm_struct.h @@ -462,7 +462,7 @@ typedef union { } mcpwm_dt_red_cfg_reg_t; /** Type of carrier_cfg register - * Carrier enable and configuratoin + * Carrier enable and configuration */ typedef union { struct { @@ -734,7 +734,7 @@ typedef union { */ uint32_t capn_mode:2; /** capn_prescale : R/W; bitpos: [10:3]; default: 0; - * Value of prescaling on possitive edge of CAPn. Prescale value = PWM_CAP0_PRESCALE + + * Value of prescaling on positive edge of CAPn. Prescale value = PWM_CAP0_PRESCALE + * 1 */ uint32_t capn_prescale:8; diff --git a/components/soc/esp32h2/include/soc/mem_monitor_reg.h b/components/soc/esp32h2/register/soc/mem_monitor_reg.h similarity index 98% rename from components/soc/esp32h2/include/soc/mem_monitor_reg.h rename to components/soc/esp32h2/register/soc/mem_monitor_reg.h index bbddf93b89a..1a90e585be1 100644 --- a/components/soc/esp32h2/include/soc/mem_monitor_reg.h +++ b/components/soc/esp32h2/register/soc/mem_monitor_reg.h @@ -12,7 +12,7 @@ extern "C" { #endif /** MEM_MONITOR_LOG_SETTING_REG register - * log config regsiter + * log config register */ #define MEM_MONITOR_LOG_SETTING_REG (DR_REG_MEM_MONITOR_BASE + 0x0) /** MEM_MONITOR_LOG_ENA : R/W; bitpos: [2:0]; default: 0; @@ -39,7 +39,7 @@ extern "C" { #define MEM_MONITOR_LOG_MEM_LOOP_ENABLE_S 7 /** MEM_MONITOR_LOG_CHECK_DATA_REG register - * check data regsiter + * check data register */ #define MEM_MONITOR_LOG_CHECK_DATA_REG (DR_REG_MEM_MONITOR_BASE + 0x4) /** MEM_MONITOR_LOG_CHECK_DATA : R/W; bitpos: [31:0]; default: 0; @@ -64,7 +64,7 @@ extern "C" { #define MEM_MONITOR_LOG_DATA_MASK_S 0 /** MEM_MONITOR_LOG_MIN_REG register - * log boundary regsiter + * log boundary register */ #define MEM_MONITOR_LOG_MIN_REG (DR_REG_MEM_MONITOR_BASE + 0xc) /** MEM_MONITOR_LOG_MIN : R/W; bitpos: [31:0]; default: 0; @@ -76,7 +76,7 @@ extern "C" { #define MEM_MONITOR_LOG_MIN_S 0 /** MEM_MONITOR_LOG_MAX_REG register - * log boundary regsiter + * log boundary register */ #define MEM_MONITOR_LOG_MAX_REG (DR_REG_MEM_MONITOR_BASE + 0x10) /** MEM_MONITOR_LOG_MAX : R/W; bitpos: [31:0]; default: 0; diff --git a/components/soc/esp32h2/include/soc/mem_monitor_struct.h b/components/soc/esp32h2/register/soc/mem_monitor_struct.h similarity index 98% rename from components/soc/esp32h2/include/soc/mem_monitor_struct.h rename to components/soc/esp32h2/register/soc/mem_monitor_struct.h index 8d4628467f7..ef63ca9c264 100644 --- a/components/soc/esp32h2/include/soc/mem_monitor_struct.h +++ b/components/soc/esp32h2/register/soc/mem_monitor_struct.h @@ -12,7 +12,7 @@ extern "C" { /** Group: configuration registers */ /** Type of log_setting register - * log config regsiter + * log config register */ typedef union { struct { @@ -35,7 +35,7 @@ typedef union { } mem_monitor_log_setting_reg_t; /** Type of log_check_data register - * check data regsiter + * check data register */ typedef union { struct { @@ -63,7 +63,7 @@ typedef union { } mem_monitor_log_data_mask_reg_t; /** Type of log_min register - * log boundary regsiter + * log boundary register */ typedef union { struct { @@ -76,7 +76,7 @@ typedef union { } mem_monitor_log_min_reg_t; /** Type of log_max register - * log boundary regsiter + * log boundary register */ typedef union { struct { diff --git a/components/soc/esp32h2/include/soc/parl_io_reg.h b/components/soc/esp32h2/register/soc/parl_io_reg.h similarity index 98% rename from components/soc/esp32h2/include/soc/parl_io_reg.h rename to components/soc/esp32h2/register/soc/parl_io_reg.h index 810530ded7b..d68f5191cb2 100644 --- a/components/soc/esp32h2/include/soc/parl_io_reg.h +++ b/components/soc/esp32h2/register/soc/parl_io_reg.h @@ -252,7 +252,7 @@ extern "C" { #define PARL_IO_TX_READY_S 31 /** PARL_IO_INT_ENA_REG register - * Parallel IO interrupt enable singal configuration register. + * Parallel IO interrupt enable signal configuration register. */ #define PARL_IO_INT_ENA_REG (DR_REG_PARL_IO_BASE + 0x28) /** PARL_IO_TX_FIFO_REMPTY_INT_ENA : R/W; bitpos: [0]; default: 0; @@ -278,7 +278,7 @@ extern "C" { #define PARL_IO_TX_EOF_INT_ENA_S 2 /** PARL_IO_INT_RAW_REG register - * Parallel IO interrupt raw singal status register. + * Parallel IO interrupt raw signal status register. */ #define PARL_IO_INT_RAW_REG (DR_REG_PARL_IO_BASE + 0x2c) /** PARL_IO_TX_FIFO_REMPTY_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; @@ -304,7 +304,7 @@ extern "C" { #define PARL_IO_TX_EOF_INT_RAW_S 2 /** PARL_IO_INT_ST_REG register - * Parallel IO interrupt singal status register. + * Parallel IO interrupt signal status register. */ #define PARL_IO_INT_ST_REG (DR_REG_PARL_IO_BASE + 0x30) /** PARL_IO_TX_FIFO_REMPTY_INT_ST : RO; bitpos: [0]; default: 0; @@ -330,7 +330,7 @@ extern "C" { #define PARL_IO_TX_EOF_INT_ST_S 2 /** PARL_IO_INT_CLR_REG register - * Parallel IO interrupt clear singal configuration register. + * Parallel IO interrupt clear signal configuration register. */ #define PARL_IO_INT_CLR_REG (DR_REG_PARL_IO_BASE + 0x34) /** PARL_IO_TX_FIFO_REMPTY_INT_CLR : WT; bitpos: [0]; default: 0; diff --git a/components/soc/esp32h2/include/soc/parl_io_struct.h b/components/soc/esp32h2/register/soc/parl_io_struct.h similarity index 98% rename from components/soc/esp32h2/include/soc/parl_io_struct.h rename to components/soc/esp32h2/register/soc/parl_io_struct.h index 97dc285531d..6e501e6c579 100644 --- a/components/soc/esp32h2/include/soc/parl_io_struct.h +++ b/components/soc/esp32h2/register/soc/parl_io_struct.h @@ -251,7 +251,7 @@ typedef union { /** Group: PARL_IO Interrupt Configuration and Status */ /** Type of int_ena register - * Parallel IO interrupt enable singal configuration register. + * Parallel IO interrupt enable signal configuration register. */ typedef union { struct { @@ -273,7 +273,7 @@ typedef union { } parl_io_int_ena_reg_t; /** Type of int_raw register - * Parallel IO interrupt raw singal status register. + * Parallel IO interrupt raw signal status register. */ typedef union { struct { @@ -295,7 +295,7 @@ typedef union { } parl_io_int_raw_reg_t; /** Type of int_st register - * Parallel IO interrupt singal status register. + * Parallel IO interrupt signal status register. */ typedef union { struct { @@ -317,7 +317,7 @@ typedef union { } parl_io_int_st_reg_t; /** Type of int_clr register - * Parallel IO interrupt clear singal configuration register. + * Parallel IO interrupt clear signal configuration register. */ typedef union { struct { diff --git a/components/soc/esp32h2/include/soc/pau_reg.h b/components/soc/esp32h2/register/soc/pau_reg.h similarity index 100% rename from components/soc/esp32h2/include/soc/pau_reg.h rename to components/soc/esp32h2/register/soc/pau_reg.h diff --git a/components/soc/esp32h2/include/soc/pau_struct.h b/components/soc/esp32h2/register/soc/pau_struct.h similarity index 100% rename from components/soc/esp32h2/include/soc/pau_struct.h rename to components/soc/esp32h2/register/soc/pau_struct.h diff --git a/components/soc/esp32h2/include/soc/pcnt_reg.h b/components/soc/esp32h2/register/soc/pcnt_reg.h similarity index 100% rename from components/soc/esp32h2/include/soc/pcnt_reg.h rename to components/soc/esp32h2/register/soc/pcnt_reg.h diff --git a/components/soc/esp32h2/include/soc/pcnt_struct.h b/components/soc/esp32h2/register/soc/pcnt_struct.h similarity index 100% rename from components/soc/esp32h2/include/soc/pcnt_struct.h rename to components/soc/esp32h2/register/soc/pcnt_struct.h diff --git a/components/soc/esp32h2/include/soc/pcr_reg.h b/components/soc/esp32h2/register/soc/pcr_reg.h similarity index 99% rename from components/soc/esp32h2/include/soc/pcr_reg.h rename to components/soc/esp32h2/register/soc/pcr_reg.h index f44d7a31ea5..02d26df2db3 100644 --- a/components/soc/esp32h2/include/soc/pcr_reg.h +++ b/components/soc/esp32h2/register/soc/pcr_reg.h @@ -229,7 +229,7 @@ extern "C" { #define PCR_MSPI_CLK_CONF_REG (DR_REG_PCR_BASE + 0x1c) /** PCR_MSPI_FAST_DIV_NUM : R/W; bitpos: [7:0]; default: 0; * Set as one within (0,1,2) to generate div1(default)/div2/div4 of low-speed - * clock-source to drive clk_mspi_fast. Only avaiable whe the clck-source is a + * clock-source to drive clk_mspi_fast. Only available when the clck-source is a * low-speed clock-source such as XTAL/FOSC. */ #define PCR_MSPI_FAST_DIV_NUM 0x000000FFU @@ -1331,7 +1331,7 @@ extern "C" { #define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_V 0x0000000FU #define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_S 0 /** PCR_PVT_MONITOR_FUNC_CLK_SEL : R/W; bitpos: [20]; default: 0; - * set this field to select clock-source. 0: XTAL, 1(default): 160MHz drived by SPLL + * set this field to select clock-source. 0: XTAL, 1(default): 160MHz driven by SPLL * divided by 3. */ #define PCR_PVT_MONITOR_FUNC_CLK_SEL (BIT(20)) @@ -1904,8 +1904,8 @@ extern "C" { */ #define PCR_CPU_FREQ_CONF_REG (DR_REG_PCR_BASE + 0x114) /** PCR_CPU_DIV_NUM : R/W; bitpos: [7:0]; default: 0; - * Set this field to generate clk_cpu drived by clk_hproot. The clk_cpu is - * div1(default)/div2/div4 of clk_hproot. This field is only avaliable for low-speed + * Set this field to generate clk_cpu driven by clk_hproot. The clk_cpu is + * div1(default)/div2/div4 of clk_hproot. This field is only available for low-speed * clock-source such as XTAL/FOSC, and should be used together with PCR_AHB_DIV_NUM. */ #define PCR_CPU_DIV_NUM 0x000000FFU @@ -1918,8 +1918,8 @@ extern "C" { */ #define PCR_AHB_FREQ_CONF_REG (DR_REG_PCR_BASE + 0x118) /** PCR_AHB_DIV_NUM : R/W; bitpos: [7:0]; default: 0; - * Set this field to generate clk_ahb drived by clk_hproot. The clk_ahb is - * div1(default)/div2/div4/div8 of clk_hproot. This field is only avaliable for + * Set this field to generate clk_ahb driven by clk_hproot. The clk_ahb is + * div1(default)/div2/div4/div8 of clk_hproot. This field is only available for * low-speed clock-source such as XTAL/FOSC, and should be used together with * PCR_CPU_DIV_NUM. */ @@ -1946,7 +1946,7 @@ extern "C" { #define PCR_APB_DECREASE_DIV_NUM_V 0x000000FFU #define PCR_APB_DECREASE_DIV_NUM_S 0 /** PCR_APB_DIV_NUM : R/W; bitpos: [15:8]; default: 0; - * Set as one within (0,1,3) to generate clk_apb drived by clk_ahb. The clk_apb is + * Set as one within (0,1,3) to generate clk_apb driven by clk_ahb. The clk_apb is * div1(default)/div2/div4 of clk_ahb. */ #define PCR_APB_DIV_NUM 0x000000FFU @@ -1978,48 +1978,48 @@ extern "C" { */ #define PCR_PLL_DIV_CLK_EN_REG (DR_REG_PCR_BASE + 0x124) /** PCR_PLL_240M_CLK_EN : R/W; bitpos: [0]; default: 1; - * This field is used to open 96 MHz clock (SPLL) drived from SPLL. 0: close, 1: - * open(default). Only avaliable when high-speed clock-source SPLL is active. + * This field is used to open 96 MHz clock (SPLL) driven from SPLL. 0: close, 1: + * open(default). Only available when high-speed clock-source SPLL is active. */ #define PCR_PLL_240M_CLK_EN (BIT(0)) #define PCR_PLL_240M_CLK_EN_M (PCR_PLL_240M_CLK_EN_V << PCR_PLL_240M_CLK_EN_S) #define PCR_PLL_240M_CLK_EN_V 0x00000001U #define PCR_PLL_240M_CLK_EN_S 0 /** PCR_PLL_160M_CLK_EN : R/W; bitpos: [1]; default: 1; - * This field is used to open 64 MHz clock (div3 of SPLL) drived from SPLL. 0: close, - * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + * This field is used to open 64 MHz clock (div3 of SPLL) driven from SPLL. 0: close, + * 1: open(default). Only available when high-speed clock-source SPLL is active. */ #define PCR_PLL_160M_CLK_EN (BIT(1)) #define PCR_PLL_160M_CLK_EN_M (PCR_PLL_160M_CLK_EN_V << PCR_PLL_160M_CLK_EN_S) #define PCR_PLL_160M_CLK_EN_V 0x00000001U #define PCR_PLL_160M_CLK_EN_S 1 /** PCR_PLL_120M_CLK_EN : R/W; bitpos: [2]; default: 1; - * This field is used to open 48 MHz clock (div4 of SPLL) drived from SPLL. 0: close, - * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + * This field is used to open 48 MHz clock (div4 of SPLL) driven from SPLL. 0: close, + * 1: open(default). Only available when high-speed clock-source SPLL is active. */ #define PCR_PLL_120M_CLK_EN (BIT(2)) #define PCR_PLL_120M_CLK_EN_M (PCR_PLL_120M_CLK_EN_V << PCR_PLL_120M_CLK_EN_S) #define PCR_PLL_120M_CLK_EN_V 0x00000001U #define PCR_PLL_120M_CLK_EN_S 2 /** PCR_PLL_80M_CLK_EN : R/W; bitpos: [3]; default: 1; - * This field is used to open 32 MHz clock (div6 of SPLL) drived from SPLL. 0: close, - * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + * This field is used to open 32 MHz clock (div6 of SPLL) driven from SPLL. 0: close, + * 1: open(default). Only available when high-speed clock-source SPLL is active. */ #define PCR_PLL_80M_CLK_EN (BIT(3)) #define PCR_PLL_80M_CLK_EN_M (PCR_PLL_80M_CLK_EN_V << PCR_PLL_80M_CLK_EN_S) #define PCR_PLL_80M_CLK_EN_V 0x00000001U #define PCR_PLL_80M_CLK_EN_S 3 /** PCR_PLL_48M_CLK_EN : R/W; bitpos: [4]; default: 1; - * This field is used to open 16 MHz clock (div10 of SPLL) drived from SPLL. 0: close, - * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + * This field is used to open 16 MHz clock (div10 of SPLL) driven from SPLL. 0: close, + * 1: open(default). Only available when high-speed clock-source SPLL is active. */ #define PCR_PLL_48M_CLK_EN (BIT(4)) #define PCR_PLL_48M_CLK_EN_M (PCR_PLL_48M_CLK_EN_V << PCR_PLL_48M_CLK_EN_S) #define PCR_PLL_48M_CLK_EN_V 0x00000001U #define PCR_PLL_48M_CLK_EN_S 4 /** PCR_PLL_40M_CLK_EN : R/W; bitpos: [5]; default: 1; - * This field is used to open 8 MHz clock (div12 of SPLL) drived from SPLL. 0: close, - * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + * This field is used to open 8 MHz clock (div12 of SPLL) driven from SPLL. 0: close, + * 1: open(default). Only available when high-speed clock-source SPLL is active. */ #define PCR_PLL_40M_CLK_EN (BIT(5)) #define PCR_PLL_40M_CLK_EN_M (PCR_PLL_40M_CLK_EN_V << PCR_PLL_40M_CLK_EN_S) diff --git a/components/soc/esp32h2/include/soc/pcr_struct.h b/components/soc/esp32h2/register/soc/pcr_struct.h similarity index 98% rename from components/soc/esp32h2/include/soc/pcr_struct.h rename to components/soc/esp32h2/register/soc/pcr_struct.h index 31e49c232cc..cf1a690ac30 100644 --- a/components/soc/esp32h2/include/soc/pcr_struct.h +++ b/components/soc/esp32h2/register/soc/pcr_struct.h @@ -192,7 +192,7 @@ typedef union { struct { /** mspi_fast_div_num : R/W; bitpos: [7:0]; default: 0; * Set as one within (0,1,2) to generate div1(default)/div2/div4 of low-speed - * clock-source to drive clk_mspi_fast. Only avaiable whe the clck-source is a + * clock-source to drive clk_mspi_fast. Only available when the clck-source is a * low-speed clock-source such as XTAL/FOSC. */ uint32_t mspi_fast_div_num:8; @@ -1067,7 +1067,7 @@ typedef union { uint32_t pvt_monitor_func_clk_div_num:4; uint32_t reserved_4:16; /** pvt_monitor_func_clk_sel : R/W; bitpos: [20]; default: 0; - * set this field to select clock-source. 0: XTAL, 1(default): 160MHz drived by SPLL + * set this field to select clock-source. 0: XTAL, 1(default): 160MHz driven by SPLL * divided by 3. */ uint32_t pvt_monitor_func_clk_sel:1; @@ -1573,8 +1573,8 @@ typedef union { typedef union { struct { /** cpu_div_num : R/W; bitpos: [7:0]; default: 0; - * Set this field to generate clk_cpu drived by clk_hproot. The clk_cpu is - * div1(default)/div2/div4 of clk_hproot. This field is only avaliable for low-speed + * Set this field to generate clk_cpu driven by clk_hproot. The clk_cpu is + * div1(default)/div2/div4 of clk_hproot. This field is only available for low-speed * clock-source such as XTAL/FOSC, and should be used together with PCR_AHB_DIV_NUM. */ uint32_t cpu_div_num:8; @@ -1589,8 +1589,8 @@ typedef union { typedef union { struct { /** ahb_div_num : R/W; bitpos: [7:0]; default: 0; - * Set this field to generate clk_ahb drived by clk_hproot. The clk_ahb is - * div1(default)/div2/div4/div8 of clk_hproot. This field is only avaliable for + * Set this field to generate clk_ahb driven by clk_hproot. The clk_ahb is + * div1(default)/div2/div4/div8 of clk_hproot. This field is only available for * low-speed clock-source such as XTAL/FOSC, and should be used together with * PCR_CPU_DIV_NUM. */ @@ -1616,7 +1616,7 @@ typedef union { */ uint32_t apb_decrease_div_num:8; /** apb_div_num : R/W; bitpos: [15:8]; default: 0; - * Set as one within (0,1,3) to generate clk_apb drived by clk_ahb. The clk_apb is + * Set as one within (0,1,3) to generate clk_apb driven by clk_ahb. The clk_apb is * div1(default)/div2/div4 of clk_ahb. */ uint32_t apb_div_num:8; @@ -1631,33 +1631,33 @@ typedef union { typedef union { struct { /** pll_240m_clk_en : R/W; bitpos: [0]; default: 1; - * This field is used to open 96 MHz clock (SPLL) drived from SPLL. 0: close, 1: - * open(default). Only avaliable when high-speed clock-source SPLL is active. + * This field is used to open 96 MHz clock (SPLL) driven from SPLL. 0: close, 1: + * open(default). Only available when high-speed clock-source SPLL is active. */ uint32_t pll_240m_clk_en:1; /** pll_160m_clk_en : R/W; bitpos: [1]; default: 1; - * This field is used to open 64 MHz clock (div3 of SPLL) drived from SPLL. 0: close, - * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + * This field is used to open 64 MHz clock (div3 of SPLL) driven from SPLL. 0: close, + * 1: open(default). Only available when high-speed clock-source SPLL is active. */ uint32_t pll_160m_clk_en:1; /** pll_120m_clk_en : R/W; bitpos: [2]; default: 1; - * This field is used to open 48 MHz clock (div4 of SPLL) drived from SPLL. 0: close, - * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + * This field is used to open 48 MHz clock (div4 of SPLL) driven from SPLL. 0: close, + * 1: open(default). Only available when high-speed clock-source SPLL is active. */ uint32_t pll_120m_clk_en:1; /** pll_80m_clk_en : R/W; bitpos: [3]; default: 1; - * This field is used to open 32 MHz clock (div6 of SPLL) drived from SPLL. 0: close, - * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + * This field is used to open 32 MHz clock (div6 of SPLL) driven from SPLL. 0: close, + * 1: open(default). Only available when high-speed clock-source SPLL is active. */ uint32_t pll_80m_clk_en:1; /** pll_48m_clk_en : R/W; bitpos: [4]; default: 1; - * This field is used to open 16 MHz clock (div10 of SPLL) drived from SPLL. 0: close, - * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + * This field is used to open 16 MHz clock (div10 of SPLL) driven from SPLL. 0: close, + * 1: open(default). Only available when high-speed clock-source SPLL is active. */ uint32_t pll_48m_clk_en:1; /** pll_40m_clk_en : R/W; bitpos: [5]; default: 1; - * This field is used to open 8 MHz clock (div12 of SPLL) drived from SPLL. 0: close, - * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + * This field is used to open 8 MHz clock (div12 of SPLL) driven from SPLL. 0: close, + * 1: open(default). Only available when high-speed clock-source SPLL is active. */ uint32_t pll_40m_clk_en:1; uint32_t reserved_6:26; diff --git a/components/soc/esp32h2/include/soc/plic_reg.h b/components/soc/esp32h2/register/soc/plic_reg.h similarity index 100% rename from components/soc/esp32h2/include/soc/plic_reg.h rename to components/soc/esp32h2/register/soc/plic_reg.h diff --git a/components/soc/esp32h2/include/soc/pmu_reg.h b/components/soc/esp32h2/register/soc/pmu_reg.h similarity index 100% rename from components/soc/esp32h2/include/soc/pmu_reg.h rename to components/soc/esp32h2/register/soc/pmu_reg.h diff --git a/components/soc/esp32h2/include/soc/pmu_struct.h b/components/soc/esp32h2/register/soc/pmu_struct.h similarity index 100% rename from components/soc/esp32h2/include/soc/pmu_struct.h rename to components/soc/esp32h2/register/soc/pmu_struct.h diff --git a/components/soc/esp32h2/include/soc/reg_base.h b/components/soc/esp32h2/register/soc/reg_base.h similarity index 100% rename from components/soc/esp32h2/include/soc/reg_base.h rename to components/soc/esp32h2/register/soc/reg_base.h diff --git a/components/soc/esp32h2/include/soc/rmt_reg.h b/components/soc/esp32h2/register/soc/rmt_reg.h similarity index 100% rename from components/soc/esp32h2/include/soc/rmt_reg.h rename to components/soc/esp32h2/register/soc/rmt_reg.h diff --git a/components/soc/esp32h2/include/soc/rmt_struct.h b/components/soc/esp32h2/register/soc/rmt_struct.h similarity index 100% rename from components/soc/esp32h2/include/soc/rmt_struct.h rename to components/soc/esp32h2/register/soc/rmt_struct.h diff --git a/components/soc/esp32h2/include/soc/rsa_reg.h b/components/soc/esp32h2/register/soc/rsa_reg.h similarity index 100% rename from components/soc/esp32h2/include/soc/rsa_reg.h rename to components/soc/esp32h2/register/soc/rsa_reg.h diff --git a/components/soc/esp32h2/include/soc/rsa_struct.h b/components/soc/esp32h2/register/soc/rsa_struct.h similarity index 100% rename from components/soc/esp32h2/include/soc/rsa_struct.h rename to components/soc/esp32h2/register/soc/rsa_struct.h diff --git a/components/soc/esp32h2/include/soc/sha_reg.h b/components/soc/esp32h2/register/soc/sha_reg.h similarity index 98% rename from components/soc/esp32h2/include/soc/sha_reg.h rename to components/soc/esp32h2/register/soc/sha_reg.h index b5a4529f4e1..633d53446c7 100644 --- a/components/soc/esp32h2/include/soc/sha_reg.h +++ b/components/soc/esp32h2/register/soc/sha_reg.h @@ -156,7 +156,7 @@ extern "C" { #define SHA_DATE_S 0 /** SHA_H_MEM register - * Sha H memory which contains intermediate hash or finial hash. + * Sha H memory which contains intermediate hash or final hash. */ #define SHA_H_MEM_REG (DR_REG_SHA_BASE + 0x40) #define SHA_H_MEM_SIZE_BYTES 64 diff --git a/components/soc/esp32h2/include/soc/sha_struct.h b/components/soc/esp32h2/register/soc/sha_struct.h similarity index 100% rename from components/soc/esp32h2/include/soc/sha_struct.h rename to components/soc/esp32h2/register/soc/sha_struct.h diff --git a/components/soc/esp32h2/include/soc/soc_etm_reg.h b/components/soc/esp32h2/register/soc/soc_etm_reg.h similarity index 100% rename from components/soc/esp32h2/include/soc/soc_etm_reg.h rename to components/soc/esp32h2/register/soc/soc_etm_reg.h diff --git a/components/soc/esp32h2/include/soc/soc_etm_struct.h b/components/soc/esp32h2/register/soc/soc_etm_struct.h similarity index 100% rename from components/soc/esp32h2/include/soc/soc_etm_struct.h rename to components/soc/esp32h2/register/soc/soc_etm_struct.h diff --git a/components/soc/esp32h2/include/soc/spi_mem_reg.h b/components/soc/esp32h2/register/soc/spi_mem_reg.h similarity index 99% rename from components/soc/esp32h2/include/soc/spi_mem_reg.h rename to components/soc/esp32h2/register/soc/spi_mem_reg.h index adb74b0e0b5..1f084a0acc1 100644 --- a/components/soc/esp32h2/include/soc/spi_mem_reg.h +++ b/components/soc/esp32h2/register/soc/spi_mem_reg.h @@ -5,7 +5,7 @@ */ #pragma once -#include "soc.h" +#include "soc/soc.h" #ifdef __cplusplus extern "C" { @@ -93,23 +93,23 @@ he bit will be cleared once the operation done.1: enable 0: disable..*/ #define SPI_MEM_FLASH_DP_S 21 /* SPI_MEM_FLASH_RES : R/W/SC ;bitpos:[20] ;default: 1'b0 ; */ /*description: This bit combined with reg_resandres bit releases Flash from the power-down stat -e or high performance mode and obtains the devices ID. The bit will be cleared o -nce the operation done.1: enable 0: disable..*/ +e or high performance mode and obtains the devices ID. The bit will be cleared once +the operation done.1: enable 0: disable..*/ #define SPI_MEM_FLASH_RES (BIT(20)) #define SPI_MEM_FLASH_RES_M (BIT(20)) #define SPI_MEM_FLASH_RES_V 0x1 #define SPI_MEM_FLASH_RES_S 20 /* SPI_MEM_FLASH_HPM : R/W/SC ;bitpos:[19] ;default: 1'b0 ; */ -/*description: Drive Flash into high performance mode. The bit will be cleared once the operat -ion done.1: enable 0: disable..*/ +/*description: Drive Flash into high performance mode. The bit will be cleared once the operation +done.1: enable 0: disable..*/ #define SPI_MEM_FLASH_HPM (BIT(19)) #define SPI_MEM_FLASH_HPM_M (BIT(19)) #define SPI_MEM_FLASH_HPM_V 0x1 #define SPI_MEM_FLASH_HPM_S 19 /* SPI_MEM_USR : HRO ;bitpos:[18] ;default: 1'b0 ; */ -/*description: SPI0 USR_CMD start bit, only used when SPI_MEM_AXI_REQ_EN is cleared. An operat -ion will be triggered when the bit is set. The bit will be cleared once the oper -ation done.1: enable 0: disable..*/ +/*description: SPI0 USR_CMD start bit, only used when SPI_MEM_AXI_REQ_EN is cleared. An operation +will be triggered when the bit is set. The bit will be cleared once the operation +done.1: enable 0: disable..*/ #define SPI_MEM_USR (BIT(18)) #define SPI_MEM_USR_M (BIT(18)) #define SPI_MEM_USR_V 0x1 @@ -123,9 +123,9 @@ peration done.1: enable 0: disable..*/ #define SPI_MEM_FLASH_PE_V 0x1 #define SPI_MEM_FLASH_PE_S 17 /* SPI_MEM_SLV_ST : RO ;bitpos:[7:4] ;default: 4'b0 ; */ -/*description: The current status of SPI0 slave FSM: mspi_st. 0: idle state, 1: preparation sta -te, 2: send command state, 3: send address state, 4: wait state, 5: read data st -ate, 6:write data state, 7: done state, 8: read data end state..*/ +/*description: The current status of SPI0 slave FSM: mspi_st. 0: idle state, 1: preparation +state, 2: send command state, 3: send address state, 4: wait state, 5: read data state +, 6:write data state, 7: done state, 8: read data end state..*/ #define SPI_MEM_SLV_ST 0x0000000F #define SPI_MEM_SLV_ST_M ((SPI_MEM_SLV_ST_V)<<(SPI_MEM_SLV_ST_S)) #define SPI_MEM_SLV_ST_V 0xF @@ -157,7 +157,7 @@ lways 1. 0: Others..*/ #define SPI_MEM_DATA_IE_ALWAYS_ON_V 0x1 #define SPI_MEM_DATA_IE_ALWAYS_ON_S 31 /* SPI_MEM_DQS_IE_ALWAYS_ON : HRO ;bitpos:[30] ;default: 1'b0 ; */ -/*description: When accesses to flash, 1: the IE signals of pads connected to SPI_DQS are alway +/*description: When accesses to flash, 1: the IE signals of pads connected to SPI_DQS are always s 1. 0: Others..*/ #define SPI_MEM_DQS_IE_ALWAYS_ON (BIT(30)) #define SPI_MEM_DQS_IE_ALWAYS_ON_M (BIT(30)) @@ -229,14 +229,14 @@ UT and SPI_MEM_FREAD_DOUT. 1: enable 0: disable..*/ #define SPI_MEM_FASTRD_MODE_V 0x1 #define SPI_MEM_FASTRD_MODE_S 13 /* SPI_MEM_TX_CRC_EN : HRO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disabl +/*description: For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disable e.*/ #define SPI_MEM_TX_CRC_EN (BIT(11)) #define SPI_MEM_TX_CRC_EN_M (BIT(11)) #define SPI_MEM_TX_CRC_EN_V 0x1 #define SPI_MEM_TX_CRC_EN_S 11 /* SPI_MEM_FCS_CRC_EN : HRO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: For SPI1, initialize crc32 module before writing encrypted data to flash. Activ +/*description: For SPI1, initialize crc32 module before writing encrypted data to flash. Active e low..*/ #define SPI_MEM_FCS_CRC_EN (BIT(10)) #define SPI_MEM_FCS_CRC_EN_M (BIT(10)) @@ -392,7 +392,7 @@ y the real AXI read data back. 0: When ARSIZE 0~1, MSPI reply SLV_ERR..*/ /* SPI_MEM_CLK_MODE : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ /*description: SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delaye d one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inacti -ve 3: SPI clock is alwasy on..*/ +ve 3: SPI clock is always on..*/ #define SPI_MEM_CLK_MODE 0x00000003 #define SPI_MEM_CLK_MODE_M ((SPI_MEM_CLK_MODE_V)<<(SPI_MEM_CLK_MODE_S)) #define SPI_MEM_CLK_MODE_V 0x3 @@ -422,8 +422,8 @@ whether there is an ECC region or not..*/ #define SPI_MEM_SPLIT_TRANS_EN_V 0x1 #define SPI_MEM_SPLIT_TRANS_EN_S 24 /* SPI_MEM_ECC_16TO18_BYTE_EN : HRO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode whe -n accesses flash..*/ +/*description: Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when +accesses flash..*/ #define SPI_MEM_ECC_16TO18_BYTE_EN (BIT(14)) #define SPI_MEM_ECC_16TO18_BYTE_EN_M (BIT(14)) #define SPI_MEM_ECC_16TO18_BYTE_EN_V 0x1 @@ -803,8 +803,8 @@ he register value shall be (bit_num-1)..*/ #define SPI_MEM_SRAM_RDUMMY_CYCLELEN_V 0x3F #define SPI_MEM_SRAM_RDUMMY_CYCLELEN_S 6 /* SPI_MEM_CACHE_SRAM_USR_RCMD : HRO ;bitpos:[5] ;default: 1'b1 ; */ -/*description: For SPI0, In the external RAM mode cache read external RAM for user define comma -nd..*/ +/*description: For SPI0, In the external RAM mode cache read external RAM for user define command +..*/ #define SPI_MEM_CACHE_SRAM_USR_RCMD (BIT(5)) #define SPI_MEM_CACHE_SRAM_USR_RCMD_M (BIT(5)) #define SPI_MEM_CACHE_SRAM_USR_RCMD_V 0x1 @@ -1011,7 +1011,7 @@ e for sram..*/ #define SPI_MEM_SRAM_CLK_REG(i) (REG_SPI_MEM_BASE(i) + 0x50) /* SPI_MEM_SCLK_EQU_SYSCLK : HRO ;bitpos:[31] ;default: 1'b0 ; */ -/*description: For SPI0 external RAM interface, 1: spi_mem_clk is eqaul to system 0: spi_mem_c +/*description: For SPI0 external RAM interface, 1: spi_mem_clk is equal to system 0: spi_mem_c lk is divided from system clock..*/ #define SPI_MEM_SCLK_EQU_SYSCLK (BIT(31)) #define SPI_MEM_SCLK_EQU_SYSCLK_M (BIT(31)) @@ -1269,7 +1269,7 @@ out, status_in[15:0] is valid when two bytes of data are read out), SUS/SUS1/SUS #define SPI_MEM_FLASH_PES_EN_S 5 /* SPI_MEM_PES_PER_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */ /*description: Set this bit to enable PES end triggers PER transfer option. If this bit is 0, a -pplication should send PER after PES is done..*/ +application should send PER after PES is done..*/ #define SPI_MEM_PES_PER_EN (BIT(4)) #define SPI_MEM_PES_PER_EN_M (BIT(4)) #define SPI_MEM_PES_PER_EN_V 0x1 @@ -1291,8 +1291,8 @@ resume command is sent..*/ #define SPI_MEM_FLASH_PER_WAIT_EN_V 0x1 #define SPI_MEM_FLASH_PER_WAIT_EN_S 2 /* SPI_MEM_FLASH_PES : R/W/SC ;bitpos:[1] ;default: 1'b0 ; */ -/*description: program erase suspend bit, program erase suspend operation will be triggered whe -n the bit is set. The bit will be cleared once the operation done.1: enable 0: d +/*description: program erase suspend bit, program erase suspend operation will be triggered when +the bit is set. The bit will be cleared once the operation done.1: enable 0: d isable..*/ #define SPI_MEM_FLASH_PES (BIT(1)) #define SPI_MEM_FLASH_PES_M (BIT(1)) @@ -1536,7 +1536,7 @@ mmand is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles #define SPI_MEM_INT_RAW_REG(i) (REG_SPI_MEM_BASE(i) + 0xC8) /* SPI_MEM_BROWN_OUT_INT_RAW : R/WTC/SS ;bitpos:[10] ;default: 1'b0 ; */ /*description: The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that -chip is loosing power and RTC module sends out brown out close flash request to +chip is losing power and RTC module sends out brown out close flash request to SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered and MSPI returns to idle state. 0: Others..*/ #define SPI_MEM_BROWN_OUT_INT_RAW (BIT(10)) @@ -1580,8 +1580,8 @@ his bit is triggered when the error times of SPI0/1 ECC read external RAM are eq ual or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and SP I_SMEM_ECC_ERR_INT_EN are set, this bit is triggered when the total error times of SPI0/1 ECC read external RAM and flash are equal or bigger than SPI_MEM_ECC_E -RR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and SPI_SMEM_ECC_ERR_INT_EN are cleare -d, this bit will not be triggered..*/ +RR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and SPI_SMEM_ECC_ERR_INT_EN are clearer, +this bit will not be triggered..*/ #define SPI_MEM_ECC_ERR_INT_RAW (BIT(5)) #define SPI_MEM_ECC_ERR_INT_RAW_M (BIT(5)) #define SPI_MEM_ECC_ERR_INT_RAW_V 0x1 @@ -2371,9 +2371,9 @@ and RDATA_AFIFO are empty and spi0_mst_st is IDLE..*/ #define SPI_MEM_ALL_FIFO_EMPTY_V 0x1 #define SPI_MEM_ALL_FIFO_EMPTY_S 26 /* SPI_MEM_AXI_ERR_ADDR : R/SS/WTC ;bitpos:[25:0] ;default: 26'h0 ; */ -/*description: This bits show the first AXI write/read invalid error or AXI write flash error a -ddress. It is cleared by when SPI_MEM_AXI_WADDR_ERR_INT_CLR, SPI_MEM_AXI_WR_FLAS -H_ERR_IN_CLR or SPI_MEM_AXI_RADDR_ERR_IN_CLR bit is set..*/ +/*description: This bits show the first AXI write/read invalid error or AXI write flash error +address. It is cleared by when SPI_MEM_AXI_WADDR_ERR_INT_CLR, SPI_MEM_AXI_WR_FLASH_ERR_IN_CLR +or SPI_MEM_AXI_RADDR_ERR_IN_CLR bit is set..*/ #define SPI_MEM_AXI_ERR_ADDR 0x03FFFFFF #define SPI_MEM_AXI_ERR_ADDR_M ((SPI_MEM_AXI_ERR_ADDR_V)<<(SPI_MEM_AXI_ERR_ADDR_S)) #define SPI_MEM_AXI_ERR_ADDR_V 0x3FFFFFF @@ -2679,7 +2679,7 @@ ations..*/ #define SPI_MEM_SMEM_TIMING_CALI_V 0x1 #define SPI_MEM_SMEM_TIMING_CALI_S 1 /* SPI_MEM_SMEM_TIMING_CLK_ENA : HRO ;bitpos:[0] ;default: 1'b1 ; */ -/*description: For sram, the bit is used to enable timing adjust clock for all reading operatio +/*description: For sram, the bit is used to enable timing adjust clock for all reading operation ns..*/ #define SPI_MEM_SMEM_TIMING_CLK_ENA (BIT(0)) #define SPI_MEM_SMEM_TIMING_CLK_ENA_M (BIT(0)) @@ -2937,8 +2937,8 @@ SPI core clock cycles..*/ #define SPI_MEM_SMEM_CS_HOLD_DELAY_V 0x3F #define SPI_MEM_SMEM_CS_HOLD_DELAY_S 25 /* SPI_MEM_SMEM_ECC_16TO18_BYTE_EN : HRO ;bitpos:[16] ;default: 1'b0 ; */ -/*description: Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode whe -n accesses external RAM..*/ +/*description: Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when +accesses external RAM..*/ #define SPI_MEM_SMEM_ECC_16TO18_BYTE_EN (BIT(16)) #define SPI_MEM_SMEM_ECC_16TO18_BYTE_EN_M (BIT(16)) #define SPI_MEM_SMEM_ECC_16TO18_BYTE_EN_V 0x1 diff --git a/components/soc/esp32h2/include/soc/spi_mem_struct.h b/components/soc/esp32h2/register/soc/spi_mem_struct.h similarity index 99% rename from components/soc/esp32h2/include/soc/spi_mem_struct.h rename to components/soc/esp32h2/register/soc/spi_mem_struct.h index 95578484588..45810eb9afa 100644 --- a/components/soc/esp32h2/include/soc/spi_mem_struct.h +++ b/components/soc/esp32h2/register/soc/spi_mem_struct.h @@ -9,7 +9,7 @@ #ifdef __cplusplus extern "C" { #endif -#include "soc.h" +#include "soc/soc.h" typedef volatile struct spi_mem_dev_s { union { @@ -70,7 +70,7 @@ typedef volatile struct spi_mem_dev_s { } ctrl; union { struct { - uint32_t clk_mode : 2; /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on.*/ + uint32_t clk_mode : 2; /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is always on.*/ uint32_t cs_hold_dly_res : 10; /*After RES/DP/HPM command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 512) SPI_CLK cycles.*/ uint32_t reserved2 : 9; /*reserved*/ uint32_t reg_ar_size0_1_support_en : 1; /*1: MSPI supports ARSIZE 0~3. When ARSIZE =0~2, MSPI read address is 4*n and reply the real AXI read data back. 0: When ARSIZE 0~1, MSPI reply SLV_ERR.*/ @@ -272,7 +272,7 @@ typedef volatile struct spi_mem_dev_s { uint32_t sclkcnt_h : 8; /*For SPI0 external RAM interface, it must be floor((spi_mem_clkcnt_N+1)/2-1).*/ uint32_t sclkcnt_n : 8; /*For SPI0 external RAM interface, it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)*/ uint32_t reserved24 : 7; /*reserved*/ - uint32_t sclk_equ_sysclk : 1; /*For SPI0 external RAM interface, 1: spi_mem_clk is eqaul to system 0: spi_mem_clk is divided from system clock.*/ + uint32_t sclk_equ_sysclk : 1; /*For SPI0 external RAM interface, 1: spi_mem_clk is equal to system 0: spi_mem_clk is divided from system clock.*/ }; uint32_t val; } sram_clk; @@ -389,7 +389,7 @@ typedef volatile struct spi_mem_dev_s { uint32_t axi_raddr_err : 1; /*The raw bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read address is invalid by compared to MMU configuration. 0: Others.*/ uint32_t axi_wr_flash_err : 1; /*The raw bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI write flash request is received. 0: Others.*/ uint32_t axi_waddr_err : 1; /*The raw bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write address is invalid by compared to MMU configuration. 0: Others.*/ - uint32_t brown_out : 1; /*The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that chip is loosing power and RTC module sends out brown out close flash request to SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered and MSPI returns to idle state. 0: Others.*/ + uint32_t brown_out : 1; /*The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that chip is losing power and RTC module sends out brown out close flash request to SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered and MSPI returns to idle state. 0: Others.*/ uint32_t reserved11 : 21; /*reserved*/ }; uint32_t val; @@ -1026,7 +1026,7 @@ typedef volatile struct spi_mem_dev_s { } mmu_power_ctrl; union { struct { - uint32_t reg_crypt_security_level : 3; /*Set the security level of spi mem cryption. 0: Shut off cryption DPA funtion. 1-7: The bigger the number is, the more secure the cryption is. (Note that the performance of cryption will decrease together with this number increasing)*/ + uint32_t reg_crypt_security_level : 3; /*Set the security level of spi mem cryption. 0: Shut off cryption DPA function. 1-7: The bigger the number is, the more secure the cryption is. (Note that the performance of cryption will decrease together with this number increasing)*/ uint32_t reg_crypt_calc_d_dpa_en : 1; /*Only available when SPI_CRYPT_SECURITY_LEVEL is not 0. 1: Enable DPA in the calculation that using key 1 or key 2. 0: Enable DPA only in the calculation that using key 1.*/ uint32_t reg_crypt_dpa_selectister : 1; /*1: MSPI XTS DPA clock gate is controlled by SPI_CRYPT_CALC_D_DPA_EN and SPI_CRYPT_SECURITY_LEVEL. 0: Controlled by efuse bits.*/ uint32_t reserved5 : 27; /*reserved*/ diff --git a/components/soc/esp32h2/include/soc/spi_reg.h b/components/soc/esp32h2/register/soc/spi_reg.h similarity index 99% rename from components/soc/esp32h2/include/soc/spi_reg.h rename to components/soc/esp32h2/register/soc/spi_reg.h index 126b6b53243..44c7cf23dff 100644 --- a/components/soc/esp32h2/include/soc/spi_reg.h +++ b/components/soc/esp32h2/register/soc/spi_reg.h @@ -221,7 +221,7 @@ extern "C" { #define SPI_CLKDIV_PRE_V 0x0000000FU #define SPI_CLKDIV_PRE_S 18 /** SPI_CLK_EQU_SYSCLK : R/W; bitpos: [31]; default: 1; - * In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system + * In the master mode 1: spi_clk is equal to system 0: spi_clk is divided from system * clock. Can be configured in CONF state. */ #define SPI_CLK_EQU_SYSCLK (BIT(31)) @@ -1950,7 +1950,7 @@ extern "C" { /** SPI_CLK_MODE : R/W; bitpos: [1:0]; default: 0; * SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed * one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: - * SPI clock is alwasy on. Can be configured in CONF state. + * SPI clock is always on. Can be configured in CONF state. */ #define SPI_CLK_MODE 0x00000003U #define SPI_CLK_MODE_M (SPI_CLK_MODE_V << SPI_CLK_MODE_S) diff --git a/components/soc/esp32h2/include/soc/spi_struct.h b/components/soc/esp32h2/register/soc/spi_struct.h similarity index 99% rename from components/soc/esp32h2/include/soc/spi_struct.h rename to components/soc/esp32h2/register/soc/spi_struct.h index de7705f92c9..76644890a56 100644 --- a/components/soc/esp32h2/include/soc/spi_struct.h +++ b/components/soc/esp32h2/register/soc/spi_struct.h @@ -511,7 +511,7 @@ typedef union { /** clk_mode : R/W; bitpos: [1:0]; default: 0; * SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed * one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: - * SPI clock is alwasy on. Can be configured in CONF state. + * SPI clock is always on. Can be configured in CONF state. */ uint32_t clk_mode:2; /** clk_mode_13 : R/W; bitpos: [2]; default: 0; @@ -624,7 +624,7 @@ typedef union { uint32_t clkdiv_pre:4; uint32_t reserved_22:9; /** clk_equ_sysclk : R/W; bitpos: [31]; default: 1; - * In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system + * In the master mode 1: spi_clk is equal to system 0: spi_clk is divided from system * clock. Can be configured in CONF state. */ uint32_t clk_equ_sysclk:1; diff --git a/components/soc/esp32h2/include/soc/systimer_reg.h b/components/soc/esp32h2/register/soc/systimer_reg.h similarity index 100% rename from components/soc/esp32h2/include/soc/systimer_reg.h rename to components/soc/esp32h2/register/soc/systimer_reg.h diff --git a/components/soc/esp32h2/include/soc/systimer_struct.h b/components/soc/esp32h2/register/soc/systimer_struct.h similarity index 100% rename from components/soc/esp32h2/include/soc/systimer_struct.h rename to components/soc/esp32h2/register/soc/systimer_struct.h diff --git a/components/soc/esp32h2/include/soc/tee_reg.h b/components/soc/esp32h2/register/soc/tee_reg.h similarity index 100% rename from components/soc/esp32h2/include/soc/tee_reg.h rename to components/soc/esp32h2/register/soc/tee_reg.h diff --git a/components/soc/esp32h2/include/soc/tee_struct.h b/components/soc/esp32h2/register/soc/tee_struct.h similarity index 100% rename from components/soc/esp32h2/include/soc/tee_struct.h rename to components/soc/esp32h2/register/soc/tee_struct.h diff --git a/components/soc/esp32h2/include/soc/timer_group_reg.h b/components/soc/esp32h2/register/soc/timer_group_reg.h similarity index 100% rename from components/soc/esp32h2/include/soc/timer_group_reg.h rename to components/soc/esp32h2/register/soc/timer_group_reg.h diff --git a/components/soc/esp32h2/include/soc/timer_group_struct.h b/components/soc/esp32h2/register/soc/timer_group_struct.h similarity index 100% rename from components/soc/esp32h2/include/soc/timer_group_struct.h rename to components/soc/esp32h2/register/soc/timer_group_struct.h diff --git a/components/soc/esp32h2/include/soc/trace_reg.h b/components/soc/esp32h2/register/soc/trace_reg.h similarity index 99% rename from components/soc/esp32h2/include/soc/trace_reg.h rename to components/soc/esp32h2/register/soc/trace_reg.h index a5c3eda9dc7..b363fbd1f8e 100644 --- a/components/soc/esp32h2/include/soc/trace_reg.h +++ b/components/soc/esp32h2/register/soc/trace_reg.h @@ -154,7 +154,7 @@ extern "C" { #define TRACE_TRIGGER_OFF_V 0x00000001U #define TRACE_TRIGGER_OFF_S 1 /** TRACE_MEM_LOOP : R/W; bitpos: [2]; default: 1; - * if this reg is 1, trace will loop wrtie trace_mem. If is 0, when mem_current_addr + * if this reg is 1, trace will loop write trace_mem. If is 0, when mem_current_addr * at mem_end_addr, it will stop at the mem_end_addr */ #define TRACE_MEM_LOOP (BIT(2)) diff --git a/components/soc/esp32h2/include/soc/trace_struct.h b/components/soc/esp32h2/register/soc/trace_struct.h similarity index 99% rename from components/soc/esp32h2/include/soc/trace_struct.h rename to components/soc/esp32h2/register/soc/trace_struct.h index 41677de4288..365ac45dd06 100644 --- a/components/soc/esp32h2/include/soc/trace_struct.h +++ b/components/soc/esp32h2/register/soc/trace_struct.h @@ -156,7 +156,7 @@ typedef union { */ uint32_t trigger_off:1; /** mem_loop : R/W; bitpos: [2]; default: 1; - * if this reg is 1, trace will loop wrtie trace_mem. If is 0, when mem_current_addr + * if this reg is 1, trace will loop write trace_mem. If is 0, when mem_current_addr * at mem_end_addr, it will stop at the mem_end_addr */ uint32_t mem_loop:1; diff --git a/components/soc/esp32h2/include/soc/twai_reg.h b/components/soc/esp32h2/register/soc/twai_reg.h similarity index 100% rename from components/soc/esp32h2/include/soc/twai_reg.h rename to components/soc/esp32h2/register/soc/twai_reg.h diff --git a/components/soc/esp32h2/include/soc/twai_struct.h b/components/soc/esp32h2/register/soc/twai_struct.h similarity index 100% rename from components/soc/esp32h2/include/soc/twai_struct.h rename to components/soc/esp32h2/register/soc/twai_struct.h diff --git a/components/soc/esp32h2/include/soc/uart_reg.h b/components/soc/esp32h2/register/soc/uart_reg.h similarity index 99% rename from components/soc/esp32h2/include/soc/uart_reg.h rename to components/soc/esp32h2/register/soc/uart_reg.h index 5c8d8c01f9f..a8c550dfbb1 100644 --- a/components/soc/esp32h2/include/soc/uart_reg.h +++ b/components/soc/esp32h2/register/soc/uart_reg.h @@ -100,7 +100,7 @@ extern "C" { #define UART_RXFIFO_TOUT_INT_RAW_V 0x00000001U #define UART_RXFIFO_TOUT_INT_RAW_S 8 /** UART_SW_XON_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; - * This interrupt raw bit turns to high level when receiver recevies Xon char when + * This interrupt raw bit turns to high level when receiver receives Xon char when * uart_sw_flow_con_en is set to 1. */ #define UART_SW_XON_INT_RAW (BIT(9)) @@ -285,7 +285,7 @@ extern "C" { #define UART_TX_BRK_DONE_INT_ST_V 0x00000001U #define UART_TX_BRK_DONE_INT_ST_S 12 /** UART_TX_BRK_IDLE_DONE_INT_ST : RO; bitpos: [13]; default: 0; - * This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena + * This is the status bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena * is set to 1. */ #define UART_TX_BRK_IDLE_DONE_INT_ST (BIT(13)) @@ -760,7 +760,7 @@ extern "C" { #define UART_STOP_BIT_NUM_V 0x00000003U #define UART_STOP_BIT_NUM_S 4 /** UART_TXD_BRK : R/W; bitpos: [6]; default: 0; - * Set this bit to enbale transmitter to send NULL when the process of sending data + * Set this bit to enable transmitter to send NULL when the process of sending data * is done. */ #define UART_TXD_BRK (BIT(6)) @@ -1326,7 +1326,7 @@ extern "C" { */ #define UART_TOUT_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x64) /** UART_RX_TOUT_EN : R/W; bitpos: [0]; default: 0; - * This is the enble bit for uart receiver's timeout function. + * This is the enable bit for uart receiver's timeout function. */ #define UART_RX_TOUT_EN (BIT(0)) #define UART_RX_TOUT_EN_M (UART_RX_TOUT_EN_V << UART_RX_TOUT_EN_S) @@ -1450,7 +1450,7 @@ extern "C" { */ #define UART_HIGHPULSE_REG(i) (REG_UART_BASE(i) + 0x80) /** UART_HIGHPULSE_MIN_CNT : RO; bitpos: [11:0]; default: 4095; - * This register stores the value of the maxinum duration time for the high level + * This register stores the value of the maximum duration time for the high level * pulse. It is used in baud rate-detect process. */ #define UART_HIGHPULSE_MIN_CNT 0x00000FFFU diff --git a/components/soc/esp32h2/include/soc/uart_struct.h b/components/soc/esp32h2/register/soc/uart_struct.h similarity index 99% rename from components/soc/esp32h2/include/soc/uart_struct.h rename to components/soc/esp32h2/register/soc/uart_struct.h index 467f86ff5a4..b1ae4a2b419 100644 --- a/components/soc/esp32h2/include/soc/uart_struct.h +++ b/components/soc/esp32h2/register/soc/uart_struct.h @@ -49,7 +49,7 @@ typedef union { typedef union { struct { /** rx_tout_en : R/W; bitpos: [0]; default: 0; - * This is the enble bit for uart receiver's timeout function. + * This is the enable bit for uart receiver's timeout function. */ uint32_t rx_tout_en:1; /** rx_tout_flow_dis : R/W; bitpos: [1]; default: 0; @@ -120,7 +120,7 @@ typedef union { */ uint32_t rxfifo_tout:1; /** sw_xon : R/WTC/SS; bitpos: [9]; default: 0; - * This interrupt raw bit turns to high level when receiver recevies Xon char when + * This interrupt raw bit turns to high level when receiver receives Xon char when * uart_sw_flow_con_en is set to 1. */ uint32_t sw_xon:1; @@ -238,7 +238,7 @@ typedef union { */ uint32_t tx_brk_done:1; /** tx_brk_idle_done : RO; bitpos: [13]; default: 0; - * This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena + * This is the status bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena * is set to 1. */ uint32_t tx_brk_idle_done:1; @@ -515,7 +515,7 @@ typedef union { */ uint32_t stop_bit_num:2; /** txd_brk : R/W; bitpos: [6]; default: 0; - * Set this bit to enbale transmitter to send NULL when the process of sending data + * Set this bit to enable transmitter to send NULL when the process of sending data * is done. */ uint32_t txd_brk:1; @@ -1120,7 +1120,7 @@ typedef union { typedef union { struct { /** highpulse_min_cnt : RO; bitpos: [11:0]; default: 4095; - * This register stores the value of the maxinum duration time for the high level + * This register stores the value of the maximum duration time for the high level * pulse. It is used in baud rate-detect process. */ uint32_t highpulse_min_cnt:12; diff --git a/components/soc/esp32h2/include/soc/uhci_reg.h b/components/soc/esp32h2/register/soc/uhci_reg.h similarity index 100% rename from components/soc/esp32h2/include/soc/uhci_reg.h rename to components/soc/esp32h2/register/soc/uhci_reg.h diff --git a/components/soc/esp32h2/include/soc/uhci_struct.h b/components/soc/esp32h2/register/soc/uhci_struct.h similarity index 100% rename from components/soc/esp32h2/include/soc/uhci_struct.h rename to components/soc/esp32h2/register/soc/uhci_struct.h diff --git a/components/soc/esp32h2/include/soc/usb_serial_jtag_reg.h b/components/soc/esp32h2/register/soc/usb_serial_jtag_reg.h similarity index 99% rename from components/soc/esp32h2/include/soc/usb_serial_jtag_reg.h rename to components/soc/esp32h2/register/soc/usb_serial_jtag_reg.h index eb4b8a1e039..e188eea9111 100644 --- a/components/soc/esp32h2/include/soc/usb_serial_jtag_reg.h +++ b/components/soc/esp32h2/register/soc/usb_serial_jtag_reg.h @@ -1144,7 +1144,7 @@ extern "C" { #define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_V 0x00000001U #define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_S 3 /** USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY : RO; bitpos: [4]; default: 1; - * CDC_ACM OUTOUT async FIFO empty signal in read clock domain. + * CDC_ACM OUTPUT async FIFO empty signal in read clock domain. */ #define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY (BIT(4)) #define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_M (USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_V << USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_S) diff --git a/components/soc/esp32h2/include/soc/usb_serial_jtag_struct.h b/components/soc/esp32h2/register/soc/usb_serial_jtag_struct.h similarity index 100% rename from components/soc/esp32h2/include/soc/usb_serial_jtag_struct.h rename to components/soc/esp32h2/register/soc/usb_serial_jtag_struct.h diff --git a/components/soc/esp32h2/include/soc/xts_aes_reg.h b/components/soc/esp32h2/register/soc/xts_aes_reg.h similarity index 98% rename from components/soc/esp32h2/include/soc/xts_aes_reg.h rename to components/soc/esp32h2/register/soc/xts_aes_reg.h index ab5f66583ed..921701bc742 100644 --- a/components/soc/esp32h2/include/soc/xts_aes_reg.h +++ b/components/soc/esp32h2/register/soc/xts_aes_reg.h @@ -32,7 +32,7 @@ s. Please do not use this field..*/ #define XTS_AES_DESTINATION_REG(i) (REG_SPI_MEM_BASE(i) + 0x344) /* XTS_AES_DESTINATION : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: This bit stores the destination parameter which will be used in manual encryptio +/*description: This bit stores the destination parameter which will be used in manual encryption n calculation. 0: flash(default), 1: psram(reserved). Only default value can be used..*/ #define XTS_AES_DESTINATION (BIT(0)) @@ -54,7 +54,7 @@ size parameter..*/ /* XTS_AES_TRIGGER : WT ;bitpos:[0] ;default: 1'b0 ; */ /*description: Set this bit to trigger the process of manual encryption calculation. This actio n should only be asserted when manual encryption status is 0. After this action, - manual encryption status becomes 1. After calculation is done, manual encryptio + manual encryption status becomes 1. After calculation is done, manual encryption n status becomes 2..*/ #define XTS_AES_TRIGGER (BIT(0)) #define XTS_AES_TRIGGER_M (BIT(0)) @@ -116,7 +116,7 @@ ing key 1..*/ #define XTS_AES_CRYPT_CALC_D_DPA_EN_V 0x1 #define XTS_AES_CRYPT_CALC_D_DPA_EN_S 3 /* XTS_AES_CRYPT_SECURITY_LEVEL : R/W ;bitpos:[2:0] ;default: 3'd7 ; */ -/*description: Set the security level of spi mem cryption. 0: Shut off cryption DPA funtion. 1- +/*description: Set the security level of spi mem cryption. 0: Shut off cryption DPA function. 1- 7: The bigger the number is, the more secure the cryption is. (Note that the per formance of cryption will decrease together with this number increasing).*/ #define XTS_AES_CRYPT_SECURITY_LEVEL 0x00000007 diff --git a/components/soc/esp32p4/include/soc/usb_wrap_struct.h b/components/soc/esp32p4/include/soc/usb_wrap_struct.h index b5f36b526db..dd1b234e342 100644 --- a/components/soc/esp32p4/include/soc/usb_wrap_struct.h +++ b/components/soc/esp32p4/include/soc/usb_wrap_struct.h @@ -121,7 +121,7 @@ typedef union { */ uint32_t test_enable:1; /** test_usb_wrap_oe : R/W; bitpos: [1]; default: 0; - * USB pad one in test. + * USB pad oen in test. */ uint32_t test_usb_wrap_oe:1; /** test_tx_dp : R/W; bitpos: [2]; default: 0; From 35953a6ea7fdf8a247289739ea5d61a75e975793 Mon Sep 17 00:00:00 2001 From: Frantisek Hrbata Date: Tue, 8 Oct 2024 16:51:48 +0200 Subject: [PATCH 068/472] fix(ldgen): enable default name SORT in linker fragment Currently, the `SORT` flag mandates the inclusion of at least the `sort_by_first` argument in the grammar, despite the documentation[1] indicating that `SORT` can be utilized without any arguments, defaulting to sorting input sections by name. Fix this by modifying the grammar to allow a default `SORT` and update a test accordingly. [1] https://docs.espressif.com/projects/esp-idf/en/stable/esp32/api-guides/ linker-script-generation.html Signed-off-by: Frantisek Hrbata --- tools/ldgen/ldgen/fragments.py | 43 ++++++++++++++++++++++-------- tools/ldgen/test/test_fragments.py | 4 ++- 2 files changed, 35 insertions(+), 12 deletions(-) diff --git a/tools/ldgen/ldgen/fragments.py b/tools/ldgen/ldgen/fragments.py index 0acd81f605d..80cc167e207 100644 --- a/tools/ldgen/ldgen/fragments.py +++ b/tools/ldgen/ldgen/fragments.py @@ -1,13 +1,34 @@ # -# SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD +# SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD # SPDX-License-Identifier: Apache-2.0 # - -from typing import Any, Dict, List, Optional, Set, Tuple, Union - -from pyparsing import (Combine, Forward, Group, IndentedBlock, Keyword, LineEnd, Literal, OneOrMore, Opt, - ParseFatalException, SkipTo, Suppress, Word, ZeroOrMore, alphanums, alphas, delimited_list, - nums, rest_of_line) +from typing import Any +from typing import Dict +from typing import List +from typing import Optional +from typing import Set +from typing import Tuple +from typing import Union + +from pyparsing import alphanums +from pyparsing import alphas +from pyparsing import Combine +from pyparsing import delimited_list +from pyparsing import Forward +from pyparsing import Group +from pyparsing import IndentedBlock +from pyparsing import Keyword +from pyparsing import LineEnd +from pyparsing import Literal +from pyparsing import nums +from pyparsing import OneOrMore +from pyparsing import Opt +from pyparsing import ParseFatalException +from pyparsing import rest_of_line +from pyparsing import SkipTo +from pyparsing import Suppress +from pyparsing import Word +from pyparsing import ZeroOrMore class Empty: @@ -227,11 +248,11 @@ class Sort(EntryFlag): _keywords = Keyword('name') | Keyword('alignment') | Keyword('init_priority') SORT = (Keyword('SORT').suppress() + Suppress('(') - + _keywords.set_results_name('first') - + Opt(Suppress(',') + _keywords.set_results_name('second')) + + Opt(_keywords.set_results_name('first') + + Opt(Suppress(',') + _keywords.set_results_name('second'))) + Suppress(')')) - def __init__(self, first: str, second: Optional[str] = None): + def __init__(self, first: Optional[str] = None, second: Optional[str] = None): self.first = first self.second = second @@ -244,7 +265,7 @@ def __eq__(self, other): @staticmethod def parse(toks): - return Sort(toks.first, toks.second or None) + return Sort(toks.first or None, toks.second or None) class Flag: diff --git a/tools/ldgen/test/test_fragments.py b/tools/ldgen/test/test_fragments.py index 9cc3899e989..c7e72892eef 100755 --- a/tools/ldgen/test/test_fragments.py +++ b/tools/ldgen/test/test_fragments.py @@ -705,6 +705,7 @@ def test_sort_flag(self): archive: libmain.a entries: obj1 (default); + text->flash_text SORT(), text->flash_text SORT(name), rodata->flash_rodata SORT(alignment), data->dram0_data SORT(init_priority), @@ -717,7 +718,8 @@ def test_sort_flag(self): fragment_file = parse_fragment_file(test_fragment, self.sdkconfig) fragment = fragment_file.fragments[0] - expected = [Flag('text', 'flash_text', [Sort('name')]), + expected = [Flag('text', 'flash_text', [Sort()]), + Flag('text', 'flash_text', [Sort('name')]), Flag('rodata', 'flash_rodata', [Sort('alignment')]), Flag('data', 'dram0_data', [Sort('init_priority')]), Flag('bss', 'dram0_bss', [Sort('name', 'alignment')]), From e9bd3c01f00cc8d2e9765e8fd72c04f341b1b485 Mon Sep 17 00:00:00 2001 From: Armando Date: Fri, 27 Sep 2024 11:26:24 +0800 Subject: [PATCH 069/472] change(flash): flash ops sanitizer --- tools/test_apps/system/panic/CMakeLists.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/test_apps/system/panic/CMakeLists.txt b/tools/test_apps/system/panic/CMakeLists.txt index 3305b7b4f6f..e9db4327f57 100644 --- a/tools/test_apps/system/panic/CMakeLists.txt +++ b/tools/test_apps/system/panic/CMakeLists.txt @@ -17,7 +17,7 @@ if(CONFIG_TEST_MEMPROT) endif() endif() -if(NOT CONFIG_TEST_MEMPROT AND NOT CONFIG_ESP_COREDUMP_CAPTURE_DRAM AND NOT CONFIG_SPIRAM) +if(NOT CONFIG_TEST_MEMPROT AND NOT CONFIG_ESP_COREDUMP_CAPTURE_DRAM) # Enable UBSAN checks # # shift-base sanitizer is disabled due to the following pattern found in register header files: From b6e558d55d60fa3dcab0208e769becd5fcb95b54 Mon Sep 17 00:00:00 2001 From: "C.S.M" Date: Wed, 9 Oct 2024 16:23:23 +0800 Subject: [PATCH 070/472] fix(i2c_master): fix the sleep retention number on p4 --- components/soc/esp32p4/include/soc/retention_periph_defs.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/components/soc/esp32p4/include/soc/retention_periph_defs.h b/components/soc/esp32p4/include/soc/retention_periph_defs.h index 37c04d2071b..48cf71404c6 100644 --- a/components/soc/esp32p4/include/soc/retention_periph_defs.h +++ b/components/soc/esp32p4/include/soc/retention_periph_defs.h @@ -40,12 +40,12 @@ typedef enum periph_retention_module { SLEEP_RETENTION_MODULE_AXI_DMA_CH0 = 16, SLEEP_RETENTION_MODULE_AXI_DMA_CH1 = 17, SLEEP_RETENTION_MODULE_AXI_DMA_CH2 = 18, - SLEEP_RETENTION_MODULE_I2C0 = 19, - SLEEP_RETENTION_MODULE_I2C1 = 20, SLEEP_RETENTION_MODULE_I2S0 = 19, SLEEP_RETENTION_MODULE_I2S1 = 20, SLEEP_RETENTION_MODULE_I2S2 = 21, + SLEEP_RETENTION_MODULE_I2C0 = 22, + SLEEP_RETENTION_MODULE_I2C1 = 23, SLEEP_RETENTION_MODULE_MAX = 31 } periph_retention_module_t; From 418583a5be0c4bd06b4d25a6d6391aba68a5ff04 Mon Sep 17 00:00:00 2001 From: Roman Leonov Date: Wed, 9 Oct 2024 11:05:21 +0200 Subject: [PATCH 071/472] fix(usb_host_lib): Returned task suspend --- .../peripherals/usb/host/usb_host_lib/main/class_driver.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/examples/peripherals/usb/host/usb_host_lib/main/class_driver.c b/examples/peripherals/usb/host/usb_host_lib/main/class_driver.c index 3b7077986f2..5a89e40dea3 100644 --- a/examples/peripherals/usb/host/usb_host_lib/main/class_driver.c +++ b/examples/peripherals/usb/host/usb_host_lib/main/class_driver.c @@ -206,7 +206,7 @@ void class_driver_task(void *arg) SemaphoreHandle_t mux_lock = xSemaphoreCreateMutex(); if (mux_lock == NULL) { ESP_LOGE(TAG, "Unable to create class driver mutex"); - vTaskDelete(NULL); + vTaskSuspend(NULL); return; } @@ -256,7 +256,7 @@ void class_driver_task(void *arg) if (mux_lock != NULL) { vSemaphoreDelete(mux_lock); } - vTaskDelete(NULL); + vTaskSuspend(NULL); } void class_driver_client_deregister(void) From 04f757686f1fe4edd55472c8cd4a824ec5d1f29e Mon Sep 17 00:00:00 2001 From: weiyuhan Date: Wed, 9 Oct 2024 17:37:20 +0800 Subject: [PATCH 072/472] docs(ble): Updated one feature name in feature status table --- docs/docs_not_updated/esp32c5.txt | 33 ------------------- docs/docs_not_updated/esp32c61.txt | 33 ------------------- .../ble/ble-feature-support-status.rst | 32 +++++++++--------- .../ble/host-feature-support-status.rst | 2 +- docs/en/api-guides/ble/overview.rst | 4 +-- .../ble/ble-feature-support-status.rst | 32 +++++++++--------- .../ble/host-feature-support-status.rst | 2 +- docs/zh_CN/api-guides/ble/overview.rst | 4 +-- 8 files changed, 38 insertions(+), 104 deletions(-) diff --git a/docs/docs_not_updated/esp32c5.txt b/docs/docs_not_updated/esp32c5.txt index 78e9f9ee899..7a8cf3a65db 100644 --- a/docs/docs_not_updated/esp32c5.txt +++ b/docs/docs_not_updated/esp32c5.txt @@ -1,19 +1,12 @@ api-guides/low-power-mode.rst api-guides/RF_calibration.rst api-guides/deep-sleep-stub.rst -api-guides/blufi.rst api-guides/coexist.rst api-guides/wifi.rst -api-guides/bluetooth.rst api-guides/wireshark-user-guide.rst api-guides/esp-wifi-mesh.rst api-guides/inc/external-ram-esp32-notes.rst api-guides/current-consumption-measurement-modules.rst -api-guides/esp-ble-mesh/ble-mesh-index.rst -api-guides/esp-ble-mesh/ble-mesh-feature-list.rst -api-guides/esp-ble-mesh/ble-mesh-terminology.rst -api-guides/esp-ble-mesh/ble-mesh-architecture.rst -api-guides/esp-ble-mesh/ble-mesh-faq.rst api-guides/wifi-security.rst api-guides/openthread.rst api-reference/template.rst @@ -57,32 +50,6 @@ api-reference/system/async_memcpy.rst api-reference/system/power_management.rst api-reference/system/inc/power_management_esp32c5.rst api-reference/system/mm.rst -api-reference/bluetooth/esp_spp.rst -api-reference/bluetooth/esp_l2cap_bt.rst -api-reference/bluetooth/esp_hidd.rst -api-reference/bluetooth/esp_avrc.rst -api-reference/bluetooth/controller_vhci.rst -api-reference/bluetooth/esp_bt_defs.rst -api-reference/bluetooth/esp_hf_ag.rst -api-reference/bluetooth/esp_bt_main.rst -api-reference/bluetooth/esp_bt_device.rst -api-reference/bluetooth/esp_hidh.rst -api-reference/bluetooth/esp_gatts.rst -api-reference/bluetooth/esp_gattc.rst -api-reference/bluetooth/esp_sdp.rst -api-reference/bluetooth/bt_common.rst -api-reference/bluetooth/nimble/index.rst -api-reference/bluetooth/esp_hf_client.rst -api-reference/bluetooth/esp_a2dp.rst -api-reference/bluetooth/esp_blufi.rst -api-reference/bluetooth/bt_le.rst -api-reference/bluetooth/esp_hf_defs.rst -api-reference/bluetooth/esp_gap_bt.rst -api-reference/bluetooth/esp_gatt_defs.rst -api-reference/bluetooth/esp-ble-mesh.rst -api-reference/bluetooth/index.rst -api-reference/bluetooth/esp_gap_ble.rst -api-reference/bluetooth/classic_bt.rst api-reference/index.rst api-reference/protocols/esp_serial_slave_link.rst api-reference/protocols/esp_crt_bundle.rst diff --git a/docs/docs_not_updated/esp32c61.txt b/docs/docs_not_updated/esp32c61.txt index 7dfeaed03e7..192d4199bf7 100644 --- a/docs/docs_not_updated/esp32c61.txt +++ b/docs/docs_not_updated/esp32c61.txt @@ -7,23 +7,16 @@ api-guides/app_trace.rst api-guides/low-power-mode.rst api-guides/RF_calibration.rst api-guides/deep-sleep-stub.rst -api-guides/blufi.rst api-guides/lwip.rst api-guides/coexist.rst api-guides/wifi.rst api-guides/usb-otg-console.rst -api-guides/bluetooth.rst api-guides/wireshark-user-guide.rst api-guides/esp-wifi-mesh.rst api-guides/core_dump.rst api-guides/inc/external-ram-esp32-notes.rst api-guides/dfu.rst api-guides/current-consumption-measurement-modules.rst -api-guides/esp-ble-mesh/ble-mesh-index.rst -api-guides/esp-ble-mesh/ble-mesh-feature-list.rst -api-guides/esp-ble-mesh/ble-mesh-terminology.rst -api-guides/esp-ble-mesh/ble-mesh-architecture.rst -api-guides/esp-ble-mesh/ble-mesh-faq.rst api-guides/wifi-security.rst api-guides/index.rst api-guides/openthread.rst @@ -131,32 +124,6 @@ api-reference/system/inc/power_management_esp32c2.rst api-reference/system/inc/show-efuse-table_ESP32-S2.rst api-reference/system/mm.rst api-reference/system/index.rst -api-reference/bluetooth/esp_spp.rst -api-reference/bluetooth/esp_l2cap_bt.rst -api-reference/bluetooth/esp_hidd.rst -api-reference/bluetooth/esp_avrc.rst -api-reference/bluetooth/controller_vhci.rst -api-reference/bluetooth/esp_bt_defs.rst -api-reference/bluetooth/esp_hf_ag.rst -api-reference/bluetooth/esp_bt_main.rst -api-reference/bluetooth/esp_bt_device.rst -api-reference/bluetooth/esp_hidh.rst -api-reference/bluetooth/esp_gatts.rst -api-reference/bluetooth/esp_gattc.rst -api-reference/bluetooth/esp_sdp.rst -api-reference/bluetooth/bt_common.rst -api-reference/bluetooth/nimble/index.rst -api-reference/bluetooth/esp_hf_client.rst -api-reference/bluetooth/esp_a2dp.rst -api-reference/bluetooth/esp_blufi.rst -api-reference/bluetooth/bt_le.rst -api-reference/bluetooth/esp_hf_defs.rst -api-reference/bluetooth/esp_gap_bt.rst -api-reference/bluetooth/esp_gatt_defs.rst -api-reference/bluetooth/esp-ble-mesh.rst -api-reference/bluetooth/index.rst -api-reference/bluetooth/esp_gap_ble.rst -api-reference/bluetooth/classic_bt.rst api-reference/error-codes.rst api-reference/index.rst api-reference/protocols/icmp_echo.rst diff --git a/docs/en/api-guides/ble/ble-feature-support-status.rst b/docs/en/api-guides/ble/ble-feature-support-status.rst index 01a7aa5b3cc..a750483ad3f 100644 --- a/docs/en/api-guides/ble/ble-feature-support-status.rst +++ b/docs/en/api-guides/ble/ble-feature-support-status.rst @@ -162,7 +162,7 @@ If none of our chip series meet your needs, please contact `customer support tea - |experimental| - |experimental| * - - - Advertising Channel Index + - Randomized Advertising Channel Indexing - |unsupported| - |NA| - |NA| @@ -171,19 +171,19 @@ If none of our chip series meet your needs, please contact `customer support tea - .. only:: esp32 or esp32c3 or esp32s3 |unsupported| - .. only:: esp32c6 or esp32h2 or esp32c2 or esp32c5 + .. only:: esp32c6 or esp32h2 or esp32c2 or esp32c5 or esp32c61 |experimental| - .. only:: esp32 or esp32c3 or esp32s3 |unsupported| - .. only:: esp32c6 or esp32h2 or esp32c2 or esp32c5 + .. only:: esp32c6 or esp32h2 or esp32c2 or esp32c5 or esp32c61 |experimental| - .. only:: esp32 or esp32c3 or esp32s3 |unsupported| - .. only:: esp32c6 or esp32h2 or esp32c2 or esp32c5 + .. only:: esp32c6 or esp32h2 or esp32c2 or esp32c5 or esp32c61 |experimental| * - .. centered:: |5.2| @@ -201,14 +201,14 @@ If none of our chip series meet your needs, please contact `customer support tea - .. only:: esp32 or esp32c2 |unsupported| - .. only:: esp32c6 or esp32h2 or esp32c3 or esp32s3 or esp32c5 + .. only:: esp32c6 or esp32h2 or esp32c3 or esp32s3 or esp32c5 or esp32c61 |experimental| - |unsupported| - .. only:: esp32 or esp32c2 |unsupported| - .. only:: esp32c6 or esp32h2 or esp32c3 or esp32s3 or esp32c5 + .. only:: esp32c6 or esp32h2 or esp32c3 or esp32s3 or esp32c5 or esp31c61 |experimental| * - .. centered:: |5.3| @@ -216,31 +216,31 @@ If none of our chip series meet your needs, please contact `customer support tea - .. only:: esp32 or esp32c3 or esp32s3 |unsupported| - .. only:: esp32c6 or esp32c2 or esp32h2 or esp32c5 + .. only:: esp32c6 or esp32c2 or esp32h2 or esp32c5 or esp32c61 |supported| - .. only:: esp32 or esp32c3 or esp32s3 |unsupported| - .. only:: esp32c6 or esp32c2 or esp32h2 or esp32c5 + .. only:: esp32c6 or esp32c2 or esp32h2 or esp32c5 or esp32c61 |supported| - .. only:: esp32 or esp32c3 or esp32s3 |unsupported| - .. only:: esp32c6 or esp32c2 or esp32h2 or esp32c5 + .. only:: esp32c6 or esp32c2 or esp32h2 or esp32c5 or esp32c61 |supported| * - - LE Enhanced Connection Update (Connection Subrating) - - .. only:: esp32 or esp32c6 or esp32c2 or esp32h2 or esp32c5 + - .. only:: esp32 or esp32c6 or esp32c2 or esp32h2 or esp32c5 or esp32c61 |unsupported| .. only:: esp32c3 or esp32s3 |experimental| - |unsupported| - - .. only:: esp32 or esp32c6 or esp32c2 or esp32h2 or esp32c5 + - .. only:: esp32 or esp32c6 or esp32c2 or esp32h2 or esp32c5 or esp32c61 |unsupported| .. only:: esp32c3 or esp32s3 @@ -251,31 +251,31 @@ If none of our chip series meet your needs, please contact `customer support tea - .. only:: esp32 or esp32c3 or esp32s3 or esp32c2 |unsupported| - .. only:: esp32c6 or esp32h2 or esp32c5 + .. only:: esp32c6 or esp32h2 or esp32c5 or esp32c61 |experimental| - .. only:: esp32 or esp32c3 or esp32s3 or esp32c2 |unsupported| - .. only:: esp32c6 or esp32h2 or esp32c5 + .. only:: esp32c6 or esp32h2 or esp32c5 or esp32c61 |experimental| - .. only:: esp32 or esp32c3 or esp32s3 or esp32c2 |unsupported| - .. only:: esp32c6 or esp32h2 or esp32c5 + .. only:: esp32c6 or esp32h2 or esp32c5 or esp32c61 |experimental| * - .. centered:: |5.4| - Advertising Coding Selection - - .. only:: esp32 or esp32c6 or esp32c2 or esp32h2 or esp32c5 + - .. only:: esp32 or esp32c6 or esp32c2 or esp32h2 or esp32c5 or esp32c61 |unsupported| .. only:: esp32c3 or esp32s3 |experimental| - |unsupported| - - .. only:: esp32 or esp32c6 or esp32c2 or esp32h2 or esp32c5 + - .. only:: esp32 or esp32c6 or esp32c2 or esp32h2 or esp32c5 or esp31c61 |unsupported| .. only:: esp32c3 or esp32s3 diff --git a/docs/en/api-guides/ble/host-feature-support-status.rst b/docs/en/api-guides/ble/host-feature-support-status.rst index 1900dca3a6f..75c5c4425ec 100644 --- a/docs/en/api-guides/ble/host-feature-support-status.rst +++ b/docs/en/api-guides/ble/host-feature-support-status.rst @@ -79,7 +79,7 @@ If none of our chip series meet your needs, please contact `customer support tea - |experimental| - |experimental| * - - - Advertising Channel Index + - Randomized Advertising Channel Indexing - |NA| - |NA| * - diff --git a/docs/en/api-guides/ble/overview.rst b/docs/en/api-guides/ble/overview.rst index e360d210cd4..9058f82c8a6 100644 --- a/docs/en/api-guides/ble/overview.rst +++ b/docs/en/api-guides/ble/overview.rst @@ -13,13 +13,13 @@ This document provides an architecture overview of the Bluetooth Low Energy (Blu {IDF_TARGET_NAME} supports Bluetooth 5.0 (LE) and is certified for Bluetooth LE 5.4. -.. only:: esp32c2 or esp32c6 or esp32h2 +.. only:: esp32c2 or esp32c6 or esp32h2 or esp32c5 or esp32c61 {IDF_TARGET_NAME} supports Bluetooth 5.0 (LE) and is certified for Bluetooth LE 5.3. The Bluetooth LE stack in ESP-IDF is a layered architecture that enables Bluetooth functionality on {IDF_TARGET_NAME} chip series. The table below shows its architecture. -.. only:: esp32 or esp32s3 or esp32c3 or esp32c6 +.. only:: esp32 or esp32s3 or esp32c3 or esp32c6 or esp32c5 or esp32c61 .. figure:: ../../../_static/bluetooth-architecture.png :align: center diff --git a/docs/zh_CN/api-guides/ble/ble-feature-support-status.rst b/docs/zh_CN/api-guides/ble/ble-feature-support-status.rst index 60d3919ebb2..288f0edfe73 100644 --- a/docs/zh_CN/api-guides/ble/ble-feature-support-status.rst +++ b/docs/zh_CN/api-guides/ble/ble-feature-support-status.rst @@ -162,7 +162,7 @@ - |experimental| - |experimental| * - - - Advertising Channel Index + - Randomized Advertising Channel Indexing - |unsupported| - |NA| - |NA| @@ -171,19 +171,19 @@ - .. only:: esp32 or esp32c3 or esp32s3 |unsupported| - .. only:: esp32c6 or esp32h2 or esp32c2 or esp32c5 + .. only:: esp32c6 or esp32h2 or esp32c2 or esp32c5 or esp32c61 |experimental| - .. only:: esp32 or esp32c3 or esp32s3 |unsupported| - .. only:: esp32c6 or esp32h2 or esp32c2 or esp32c5 + .. only:: esp32c6 or esp32h2 or esp32c2 or esp32c5 or esp32c61 |experimental| - .. only:: esp32 or esp32c3 or esp32s3 |unsupported| - .. only:: esp32c6 or esp32h2 or esp32c2 or esp32c5 + .. only:: esp32c6 or esp32h2 or esp32c2 or esp32c5 or esp32c61 |experimental| * - .. centered:: |5.2| @@ -201,14 +201,14 @@ - .. only:: esp32 or esp32c2 |unsupported| - .. only:: esp32c6 or esp32h2 or esp32c3 or esp32s3 or esp32c5 + .. only:: esp32c6 or esp32h2 or esp32c3 or esp32s3 or esp32c5 or esp32c61 |experimental| - |unsupported| - .. only:: esp32 or esp32c2 |unsupported| - .. only:: esp32c6 or esp32h2 or esp32c3 or esp32s3 or esp32c5 + .. only:: esp32c6 or esp32h2 or esp32c3 or esp32s3 or esp32c5 or esp32c61 |experimental| * - .. centered:: |5.3| @@ -216,31 +216,31 @@ - .. only:: esp32 or esp32c3 or esp32s3 |unsupported| - .. only:: esp32c6 or esp32c2 or esp32h2 or esp32c5 + .. only:: esp32c6 or esp32c2 or esp32h2 or esp32c5 or esp32c61 |supported| - .. only:: esp32 or esp32c3 or esp32s3 |unsupported| - .. only:: esp32c6 or esp32c2 or esp32h2 or esp32c5 + .. only:: esp32c6 or esp32c2 or esp32h2 or esp32c5 or esp32c61 |supported| - .. only:: esp32 or esp32c3 or esp32s3 |unsupported| - .. only:: esp32c6 or esp32c2 or esp32h2 or esp32c5 + .. only:: esp32c6 or esp32c2 or esp32h2 or esp32c5 or esp32c61 |supported| * - - LE Enhanced Connection Update (Connection Subrating) - - .. only:: esp32 or esp32c6 or esp32c2 or esp32h2 or esp32c5 + - .. only:: esp32 or esp32c6 or esp32c2 or esp32h2 or esp32c5 or esp32c61 |unsupported| .. only:: esp32c3 or esp32s3 |experimental| - |unsupported| - - .. only:: esp32 or esp32c6 or esp32c2 or esp32h2 or esp32c5 + - .. only:: esp32 or esp32c6 or esp32c2 or esp32h2 or esp32c5 or esp32c61 |unsupported| .. only:: esp32c3 or esp32s3 @@ -251,31 +251,31 @@ - .. only:: esp32 or esp32c3 or esp32s3 or esp32c2 |unsupported| - .. only:: esp32c6 or esp32h2 or esp32c5 + .. only:: esp32c6 or esp32h2 or esp32c5 or esp32c61 |experimental| - .. only:: esp32 or esp32c3 or esp32s3 or esp32c2 |unsupported| - .. only:: esp32c6 or esp32h2 or esp32c5 + .. only:: esp32c6 or esp32h2 or esp32c5 or esp32c61 |experimental| - .. only:: esp32 or esp32c3 or esp32s3 or esp32c2 |unsupported| - .. only:: esp32c6 or esp32h2 or esp32c5 + .. only:: esp32c6 or esp32h2 or esp32c5 or esp32c61 |experimental| * - .. centered:: |5.4| - Advertising Coding Selection - - .. only:: esp32 or esp32c6 or esp32c2 or esp32h2 or esp32c5 + - .. only:: esp32 or esp32c6 or esp32c2 or esp32h2 or esp32c5 or esp32c61 |unsupported| .. only:: esp32c3 or esp32s3 |experimental| - |unsupported| - - .. only:: esp32 or esp32c6 or esp32c2 or esp32h2 or esp32c5 + - .. only:: esp32 or esp32c6 or esp32c2 or esp32h2 or esp32c5 or esp32c61 |unsupported| .. only:: esp32c3 or esp32s3 diff --git a/docs/zh_CN/api-guides/ble/host-feature-support-status.rst b/docs/zh_CN/api-guides/ble/host-feature-support-status.rst index 2acb0855b37..d1134e17e5b 100644 --- a/docs/zh_CN/api-guides/ble/host-feature-support-status.rst +++ b/docs/zh_CN/api-guides/ble/host-feature-support-status.rst @@ -79,7 +79,7 @@ ESP 主机主要功能支持状态 - |experimental| - |experimental| * - - - Advertising Channel Index + - Randomized Advertising Channel Indexing - |NA| - |NA| * - diff --git a/docs/zh_CN/api-guides/ble/overview.rst b/docs/zh_CN/api-guides/ble/overview.rst index 62dbc36db09..d9997eef481 100644 --- a/docs/zh_CN/api-guides/ble/overview.rst +++ b/docs/zh_CN/api-guides/ble/overview.rst @@ -13,13 +13,13 @@ {IDF_TARGET_NAME} 支持蓝牙 5.0 (LE)，并且已经获得蓝牙 LE 5.4 认证。 -.. only:: esp32c2 or esp32c6 or esp32h2 +.. only:: esp32c2 or esp32c6 or esp32h2 or esp32c5 or esp32c61 {IDF_TARGET_NAME} 支持蓝牙 5.0 (LE)，并且已经获得蓝牙 LE 5.3 认证。 ESP-IDF 中的低功耗蓝牙协议栈是一个分层架构，可在 {IDF_TARGET_NAME} 系列芯片上实现低功耗蓝牙功能，详见下。 -.. only:: esp32 or esp32s3 or esp32c3 or esp32c6 +.. only:: esp32 or esp32s3 or esp32c3 or esp32c6 or esp32c5 or esp32c61 .. figure:: ../../../_static/bluetooth-architecture.png :align: center From 0592bb68883a8ef66fae6d3e9741e476f40fe9c0 Mon Sep 17 00:00:00 2001 From: Konstantin Kondrashov Date: Wed, 9 Oct 2024 12:22:06 +0300 Subject: [PATCH 073/472] fix(examples): Fix flash_enc_wifi test in pytest_simple_ota --- .../system/ota/simple_ota_example/pytest_simple_ota.py | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/examples/system/ota/simple_ota_example/pytest_simple_ota.py b/examples/system/ota/simple_ota_example/pytest_simple_ota.py index c7c1992f032..bbc7d27be62 100644 --- a/examples/system/ota/simple_ota_example/pytest_simple_ota.py +++ b/examples/system/ota/simple_ota_example/pytest_simple_ota.py @@ -225,6 +225,11 @@ def test_examples_protocol_simple_ota_example_with_flash_encryption_wifi(dut: Du 2. Fetch OTA image over HTTPS 3. Reboot with the new OTA image """ + # CONFIG_PARTITION_TABLE_TWO_OTA_ENCRYPTED_NVS==y, it includes partitions_two_ota_encr_nvs.csv + FACTORY_ADDRESS = '0x20000' + OTA_0_ADDRESS = '0x120000' + # OTA_1_ADDRESS = '0x220000' + # start test # Erase flash dut.serial.erase_flash() @@ -234,7 +239,7 @@ def test_examples_protocol_simple_ota_example_with_flash_encryption_wifi(dut: Du thread1.daemon = True thread1.start() try: - dut.expect(f'Loaded app from partition at offset {OTA_0_ADDRESS}', timeout=30) + dut.expect(f'Loaded app from partition at offset {FACTORY_ADDRESS}', timeout=30) dut.expect('Flash encryption mode is DEVELOPMENT', timeout=10) # Parse IP address of STA env_name = 'flash_encryption_wifi_high_traffic' if dut.app.sdkconfig.get('EXAMPLE_WIFI_SSID_PWD_FROM_STDIN') is True else None @@ -245,7 +250,7 @@ def test_examples_protocol_simple_ota_example_with_flash_encryption_wifi(dut: Du dut.write(f'https://{host_ip}:8000/simple_ota.bin') dut.expect('OTA Succeed, Rebooting...', timeout=60) # after reboot - dut.expect(f'Loaded app from partition at offset {OTA_1_ADDRESS}', timeout=30) + dut.expect(f'Loaded app from partition at offset {OTA_0_ADDRESS}', timeout=30) dut.expect('Flash encryption mode is DEVELOPMENT', timeout=10) dut.expect('OTA example app_main start', timeout=10) finally: From 81dd3aab1be8af25a901f29fd2dd821767bf191d Mon Sep 17 00:00:00 2001 From: Linda Date: Wed, 9 Oct 2024 16:01:36 +0800 Subject: [PATCH 074/472] docs: fix a typo in I2C RTC clock name --- docs/en/api-reference/peripherals/i2c.rst | 2 +- docs/zh_CN/api-reference/peripherals/i2c.rst | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/docs/en/api-reference/peripherals/i2c.rst b/docs/en/api-reference/peripherals/i2c.rst index dd35c6322b5..2fbbdfc4b77 100644 --- a/docs/en/api-reference/peripherals/i2c.rst +++ b/docs/en/api-reference/peripherals/i2c.rst @@ -44,7 +44,7 @@ I2C Clock Configuration - :cpp:enumerator:`i2c_clock_source_t::I2C_CLK_SRC_DEFAULT`: Default I2C source clock. :SOC_I2C_SUPPORT_XTAL: - :cpp:enumerator:`i2c_clock_source_t::I2C_CLK_SRC_XTAL`: External crystal for I2C clock source. - :SOC_I2C_SUPPORT_RTC: - :cpp:enumerator:`i2c_clock_source_t::I2C_CLK_RC_FAST`: Internal 20 MHz RC oscillator for I2C clock source. + :SOC_I2C_SUPPORT_RTC: - :cpp:enumerator:`i2c_clock_source_t::I2C_CLK_SRC_RC_FAST`: Internal 20 MHz RC oscillator for I2C clock source. :SOC_I2C_SUPPORT_APB: - :cpp:enumerator:`i2c_clock_source_t::I2C_CLK_SRC_APB`: APB clock as I2C clock source. :SOC_I2C_SUPPORT_REF_TICK: - :cpp:enumerator:`i2c_clock_source_t::I2C_CLK_SRC_REF_TICK`: 1 MHZ clock. diff --git a/docs/zh_CN/api-reference/peripherals/i2c.rst b/docs/zh_CN/api-reference/peripherals/i2c.rst index e515082f618..f00095fdd86 100644 --- a/docs/zh_CN/api-reference/peripherals/i2c.rst +++ b/docs/zh_CN/api-reference/peripherals/i2c.rst @@ -44,7 +44,7 @@ I2C 时钟配置 - :cpp:enumerator:`i2c_clock_source_t::I2C_CLK_SRC_DEFAULT`：默认的 I2C 时钟源。 :SOC_I2C_SUPPORT_XTAL: - :cpp:enumerator:`i2c_clock_source_t::I2C_CLK_SRC_XTAL`：以外部晶振作为 I2C 时钟源。 - :SOC_I2C_SUPPORT_RTC: - :cpp:enumerator:`i2c_clock_source_t::I2C_CLK_RC_FAST`：以内部 20 MHz RC 振荡器作为 I2C 时钟源。 + :SOC_I2C_SUPPORT_RTC: - :cpp:enumerator:`i2c_clock_source_t::I2C_CLK_SRC_RC_FAST`：以内部 20 MHz RC 振荡器作为 I2C 时钟源。 :SOC_I2C_SUPPORT_APB: - :cpp:enumerator:`i2c_clock_source_t::I2C_CLK_SRC_APB`：以 APB 时钟作为 I2C 时钟源。 :SOC_I2C_SUPPORT_REF_TICK: - :cpp:enumerator:`i2c_clock_source_t::I2C_CLK_SRC_REF_TICK`：1 MHZ 时钟。 From 0797f580bc6a4ecba1677f6a5513bc4d2ea46d67 Mon Sep 17 00:00:00 2001 From: "nilesh.kale" Date: Mon, 7 Oct 2024 14:32:53 +0530 Subject: [PATCH 075/472] fix: updated pytest for https_server example as per config option --- .../simple/pytest_https_server_simple.py | 51 +++++++++---------- 1 file changed, 25 insertions(+), 26 deletions(-) diff --git a/examples/protocols/https_server/simple/pytest_https_server_simple.py b/examples/protocols/https_server/simple/pytest_https_server_simple.py index 86aa6a3f42f..b86fafde337 100644 --- a/examples/protocols/https_server/simple/pytest_https_server_simple.py +++ b/examples/protocols/https_server/simple/pytest_https_server_simple.py @@ -1,8 +1,7 @@ #!/usr/bin/env python # -# SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD +# SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD # SPDX-License-Identifier: Apache-2.0 - import http.client import logging import os @@ -149,22 +148,22 @@ def test_examples_protocol_https_server_simple(dut: Dut) -> None: logging.info('Response obtained does not match with correct response') raise RuntimeError('Failed to test SSL connection') - current_cipher = dut.expect(r'Current Ciphersuite(.*)', timeout=5)[0] - logging.info('Current Ciphersuite {}'.format(current_cipher)) - - # Close the connection - conn.close() + if dut.app.sdkconfig.get('CONFIG_EXAMPLE_ENABLE_HTTPS_USER_CALLBACK') is True: + current_cipher = dut.expect(r'Current Ciphersuite(.*)', timeout=5)[0] + logging.info('Current Ciphersuite {}'.format(current_cipher)) - logging.info('Checking user callback: Obtaining client certificate...') + logging.info('Checking user callback: Obtaining client certificate...') - serial_number = dut.expect(r'serial number\s*:([^\n]*)', timeout=5)[0] - issuer_name = dut.expect(r'issuer name\s*:([^\n]*)', timeout=5)[0] - expiry = dut.expect(r'expires on ((.*)\d{4}\-(0?[1-9]|1[012])\-(0?[1-9]|[12][0-9]|3[01])*)', timeout=5)[1].decode() + serial_number = dut.expect(r'serial number\s*:([^\n]*)', timeout=5)[0] + issuer_name = dut.expect(r'issuer name\s*:([^\n]*)', timeout=5)[0] + expiry = dut.expect(r'expires on ((.*)\d{4}\-(0?[1-9]|1[012])\-(0?[1-9]|[12][0-9]|3[01])*)', timeout=5)[1].decode() - logging.info('Serial No. {}'.format(serial_number)) - logging.info('Issuer Name {}'.format(issuer_name)) - logging.info('Expires on {}'.format(expiry)) + logging.info('Serial No. {}'.format(serial_number)) + logging.info('Issuer Name {}'.format(issuer_name)) + logging.info('Expires on {}'.format(expiry)) + # Close the connection + conn.close() logging.info('Correct response obtained') logging.info('SSL connection test successful\nClosing the connection') @@ -220,21 +219,21 @@ def test_examples_protocol_https_server_simple_dynamic_buffers(dut: Dut) -> None logging.info('Response obtained does not match with correct response') raise RuntimeError('Failed to test SSL connection') - current_cipher = dut.expect(r'Current Ciphersuite(.*)', timeout=5)[0] - logging.info('Current Ciphersuite {}'.format(current_cipher)) + if dut.app.sdkconfig.get('CONFIG_EXAMPLE_ENABLE_HTTPS_USER_CALLBACK') is True: + current_cipher = dut.expect(r'Current Ciphersuite(.*)', timeout=5)[0] + logging.info('Current Ciphersuite {}'.format(current_cipher)) - # Close the connection - conn.close() - - logging.info('Checking user callback: Obtaining client certificate...') + logging.info('Checking user callback: Obtaining client certificate...') - serial_number = dut.expect(r'serial number\s*:([^\n]*)', timeout=5)[0] - issuer_name = dut.expect(r'issuer name\s*:([^\n]*)', timeout=5)[0] - expiry = dut.expect(r'expires on\s*:((.*)\d{4}\-(0?[1-9]|1[012])\-(0?[1-9]|[12][0-9]|3[01])*)', timeout=5)[1].decode() + serial_number = dut.expect(r'serial number\s*:([^\n]*)', timeout=5)[0] + issuer_name = dut.expect(r'issuer name\s*:([^\n]*)', timeout=5)[0] + expiry = dut.expect(r'expires on\s*:((.*)\d{4}\-(0?[1-9]|1[012])\-(0?[1-9]|[12][0-9]|3[01])*)', timeout=5)[1].decode() - logging.info('Serial No. : {}'.format(serial_number)) - logging.info('Issuer Name : {}'.format(issuer_name)) - logging.info('Expires on : {}'.format(expiry)) + logging.info('Serial No. : {}'.format(serial_number)) + logging.info('Issuer Name : {}'.format(issuer_name)) + logging.info('Expires on : {}'.format(expiry)) + # Close the connection + conn.close() logging.info('Correct response obtained') logging.info('SSL connection test successful\nClosing the connection') From d8e31eb6d01a6a472b293564be65a657e2197490 Mon Sep 17 00:00:00 2001 From: Hanno Date: Sun, 9 Jul 2023 23:37:40 +0200 Subject: [PATCH 076/472] feat(mbedtls/esp_crt_bundle): Reduced RAM & stack use of cert bundle Closes https://github.com/espressif/esp-idf/pull/13204 Signed-off-by: harshal.patil --- components/mbedtls/CMakeLists.txt | 2 +- .../mbedtls/esp_crt_bundle/esp_crt_bundle.c | 341 ++++++++++++------ .../mbedtls/esp_crt_bundle/gen_crt_bundle.py | 37 +- .../test_gen_crt_bundle/baltimore_crt_bundle | Bin 392 -> 394 bytes .../test_gen_crt_bundle/entrust_crt_bundle | Bin 479 -> 481 bytes .../test_apps/main/crts/server_cert_bundle | Bin 400 -> 402 bytes 6 files changed, 256 insertions(+), 124 deletions(-) diff --git a/components/mbedtls/CMakeLists.txt b/components/mbedtls/CMakeLists.txt index 93cb165b434..94033218cef 100644 --- a/components/mbedtls/CMakeLists.txt +++ b/components/mbedtls/CMakeLists.txt @@ -61,7 +61,7 @@ if(CONFIG_MBEDTLS_CERTIFICATE_BUNDLE) list(APPEND crt_paths ${custom_bundle_path}) endif() - list(APPEND args --input ${crt_paths} -q) + list(APPEND args --input ${crt_paths} -q --max-certs "${CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_MAX_CERTS}") get_filename_component(crt_bundle ${bundle_name} diff --git a/components/mbedtls/esp_crt_bundle/esp_crt_bundle.c b/components/mbedtls/esp_crt_bundle/esp_crt_bundle.c index 2da38500877..ef2e85542f5 100644 --- a/components/mbedtls/esp_crt_bundle/esp_crt_bundle.c +++ b/components/mbedtls/esp_crt_bundle/esp_crt_bundle.c @@ -1,15 +1,54 @@ /* - * SPDX-FileCopyrightText: 2018-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2018-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ #include #include +#include + +#include "esp_check.h" #include "esp_crt_bundle.h" #include "esp_log.h" -#define BUNDLE_HEADER_OFFSET 2 -#define CRT_HEADER_OFFSET 4 +#include "mbedtls/pk.h" +#include "mbedtls/oid.h" +#include "mbedtls/asn1.h" + +/* + Format of certificate bundle: + First, n uint32 "offset" entries, each describing the start of one certificate's data in terms of + bytes from the beginning of the bundle. This offset list is immediately followed by the 1st...n-th + certificate data. Hence, the first offset entry, i.e. the uint32 at the very start of the bundle, + is equal to the size of the offset list in bytes and therefore the # of certificates in the bundle + is [first offset]/sizeof(uint32_t) + [offset of 1st certificate](u32) + [offset of 2nd certificate](u32) + ... + [offset of n-th certificate](u32) + [1st certificate](variable) + ... + [n-th certificate](variable) + + Structure of each certificate: + [length of CN](u16) + [length of key](u16) + [CN](variable) + [key](variable) + + The offset list is used for fast random access to any certificate by index. + For verification, a certificate is looked up by its CN via binary search; for this reason, + the offset list *must* be sorted by CN (ascending) and the first certificate must be the + one with the least CN in the bundle, so that the first offset in the list still refers to the + first certificate after the list (see above). + +*/ + +#define CRT_NAME_LEN_OFFSET 0 //MBEDTLS_PRIVATE(sig_pk))) { - ESP_LOGE(TAG, "Simple compare failed"); - ret = -1; + if ( unlikely( !mbedtls_pk_can_do( &pubkey, child->MBEDTLS_PRIVATE(sig_pk)) ) ) { + ESP_LOGE(TAG, "Unsuitable public key"); + ret = MBEDTLS_ERR_PK_TYPE_MISMATCH; goto cleanup; } md_info = mbedtls_md_info_from_type(child->MBEDTLS_PRIVATE(sig_md)); - if ( (ret = mbedtls_md( md_info, child->tbs.p, child->tbs.len, hash )) != 0 ) { - ESP_LOGE(TAG, "Internal mbedTLS error %X", ret); + + if( unlikely( md_info == NULL) ) { + ESP_LOGE(TAG, "Unknown message digest"); + ret = MBEDTLS_ERR_X509_FEATURE_UNAVAILABLE; goto cleanup; } - if ( (ret = mbedtls_pk_verify_ext( child->MBEDTLS_PRIVATE(sig_pk), child->MBEDTLS_PRIVATE(sig_opts), &parent.pk, - child->MBEDTLS_PRIVATE(sig_md), hash, mbedtls_md_get_size( md_info ), - child->MBEDTLS_PRIVATE(sig).p, child->MBEDTLS_PRIVATE(sig).len )) != 0 ) { + unsigned char hash[MBEDTLS_MD_MAX_SIZE]; + const unsigned char md_size = mbedtls_md_get_size(md_info); - ESP_LOGE(TAG, "PK verify failed with error %X", ret); + if ((ret = mbedtls_md(md_info, child->tbs.p, child->tbs.len, hash)) != 0) { + ESP_LOGE(TAG, "MD failed with error 0x%x", -ret); + goto cleanup; + } + + if ( unlikely( (ret = mbedtls_pk_verify_ext(child->MBEDTLS_PRIVATE(sig_pk), child->MBEDTLS_PRIVATE(sig_opts), &pubkey, + child->MBEDTLS_PRIVATE(sig_md), hash, md_size, + child->MBEDTLS_PRIVATE(sig).p, child->MBEDTLS_PRIVATE(sig).len)) != 0 ) ) { + ESP_LOGE(TAG, "PK verify failed with error 0x%x", -ret); goto cleanup; } -cleanup: - mbedtls_x509_crt_free(&parent); +cleanup: + mbedtls_pk_free(&pubkey); return ret; } +static cert_t esp_crt_find_cert(const unsigned char* const issuer, const size_t issuer_len) +{ + if (unlikely( issuer == NULL || issuer_len == 0 )) { + return NULL; + } + + int start = 0; + int end = esp_crt_get_certcount(s_crt_bundle)-1; + int middle = (start + end) / 2; + + cert_t cert = NULL; + size_t cert_name_len = 0; + + /* Look for the certificate using binary search on subject name */ + while (start <= end) { + cert = esp_crt_get_cert(s_crt_bundle, middle); + cert_name_len = esp_crt_get_name_len(cert); + + // Issuers are in DER encoding, with lengths encoded in the content; if valid DER, differing lengths + // are reflected in differing content. + // Still, we won't try to memcmp beyond the given length: + int cmp_res = memcmp(issuer, esp_crt_get_name(cert), MIN(issuer_len, cert_name_len) ); + + if ( unlikely( cmp_res == 0 ) ) { + return cert; + } else if (cmp_res < 0) { + end = middle - 1; + } else { + start = middle + 1; + } + middle = (start + end) / 2; + } + + return NULL; +} + /* This callback is called for every certificate in the chain. If the chain * is proper each intermediate certificate is validated through its parent @@ -81,9 +204,9 @@ static int esp_crt_check_signature(mbedtls_x509_crt *child, const uint8_t *pub_k * only verify the first untrusted link in the chain is signed by the * root certificate in the trusted bundle */ -int esp_crt_verify_callback(void *buf, mbedtls_x509_crt *crt, int depth, uint32_t *flags) +int esp_crt_verify_callback(void *buf, mbedtls_x509_crt* const crt, const int depth, uint32_t* const flags) { - mbedtls_x509_crt *child = crt; + const mbedtls_x509_crt* const child = crt; /* It's OK for a trusted cert to have a weak signature hash alg. as we already trust this certificate */ @@ -93,121 +216,119 @@ int esp_crt_verify_callback(void *buf, mbedtls_x509_crt *crt, int depth, uint32_ return 0; } - - if (s_crt_bundle.crts == NULL) { + if( unlikely( s_crt_bundle == NULL ) ) { ESP_LOGE(TAG, "No certificates in bundle"); return MBEDTLS_ERR_X509_FATAL_ERROR; } - ESP_LOGD(TAG, "%d certificates in bundle", s_crt_bundle.num_certs); + ESP_LOGD(TAG, "%" PRIu16 " certificates in bundle", (uint16_t)esp_crt_get_certcount(s_crt_bundle)); - size_t name_len = 0; - const uint8_t *crt_name; + cert_t cert = esp_crt_find_cert(child->issuer_raw.p, child->issuer_raw.len); - bool crt_found = false; - int start = 0; - int end = s_crt_bundle.num_certs - 1; - int middle = (end - start) / 2; + if ( likely( cert != NULL ) ) { - /* Look for the certificate using binary search on subject name */ - while (start <= end) { - name_len = s_crt_bundle.crts[middle][0] << 8 | s_crt_bundle.crts[middle][1]; - crt_name = s_crt_bundle.crts[middle] + CRT_HEADER_OFFSET; + const int ret = esp_crt_check_signature(child, esp_crt_get_key(cert), esp_crt_get_key_len(cert)); - int cmp_res = memcmp(child->issuer_raw.p, crt_name, name_len ); - if (cmp_res == 0) { - crt_found = true; - break; - } else if (cmp_res < 0) { - end = middle - 1; + if ( likely( ret == 0 ) ) { + ESP_LOGI(TAG, "Certificate validated"); + *flags = 0; + return 0; } else { - start = middle + 1; + ESP_LOGE(TAG, "Certificate matched but signature verification failed"); +#if (CONFIG_LOG_DEFAULT_LEVEL_DEBUG || CONFIG_LOG_DEFAULT_LEVEL_VERBOSE) + char *cert_name = malloc((esp_crt_get_name_len(cert) + 1) * sizeof(char)); + if (cert_name) { + memcpy(cert_name, esp_crt_get_name(cert), esp_crt_get_name_len(cert)); + cert_name[esp_crt_get_name_len(cert)] = '\0'; + ESP_LOGE(TAG, "Certificate matched with %s but signature verification failed", cert_name); + free(cert_name); + } +#endif } - middle = (start + end) / 2; - } - int ret = MBEDTLS_ERR_X509_FATAL_ERROR; - if (crt_found) { - size_t key_len = s_crt_bundle.crts[middle][2] << 8 | s_crt_bundle.crts[middle][3]; - ret = esp_crt_check_signature(child, s_crt_bundle.crts[middle] + CRT_HEADER_OFFSET + name_len, key_len); - } - - if (ret == 0) { - ESP_LOGI(TAG, "Certificate validated"); - *flags = 0; - return 0; + } else { + ESP_LOGI(TAG, "No matching trusted root certificate found"); } ESP_LOGE(TAG, "Failed to verify certificate"); - return MBEDTLS_ERR_X509_FATAL_ERROR; + return MBEDTLS_ERR_X509_CERT_VERIFY_FAILED; } - -/* Initialize the bundle into an array so we can do binary search for certs, - the bundle generated by the python utility is already presorted by subject name +/** + * @brief Perform some consistency checks on the user-provided bundle data to try and make sure + * it actually is a certificate bundle. + * + * @param x509_bundle pointer to the bundle data + * @param bundle_size size of bundle data + * @return true the given bundle data is consistent + * @return false the given bundle data is invalid */ -static esp_err_t esp_crt_bundle_init(const uint8_t *x509_bundle, size_t bundle_size) +static bool esp_crt_check_bundle(const uint8_t* const x509_bundle, const size_t bundle_size) { - if (bundle_size < BUNDLE_HEADER_OFFSET + CRT_HEADER_OFFSET) { - ESP_LOGE(TAG, "Invalid certificate bundle"); - return ESP_ERR_INVALID_ARG; + if (unlikely( x509_bundle == NULL || bundle_size <= (sizeof(uint32_t) + CRT_HEADER_SIZE)) ) { + // Bundle is too small for even one offset and one certificate + return false; } - uint16_t num_certs = (x509_bundle[0] << 8) | x509_bundle[1]; - if (num_certs > CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_MAX_CERTS) { - ESP_LOGE(TAG, "No. of certs in the certificate bundle = %d exceeds\n" - "Max allowed certificates in the certificate bundle = %d\n" - "Please update the menuconfig option with appropriate value", num_certs, CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_MAX_CERTS); - return ESP_ERR_INVALID_ARG; + // Pointer to the first offset entry + const uint32_t* offsets = (const uint32_t*)x509_bundle; + + if(unlikely( offsets[0] == 0 || (offsets[0] % sizeof(uint32_t)) != 0) ) { + // First offset is invalid. + // The first certificate must start after N uint32_t offset values. + return false; } - const uint8_t **crts = calloc(num_certs, sizeof(x509_bundle)); - if (crts == NULL) { - ESP_LOGE(TAG, "Unable to allocate memory for bundle"); - return ESP_ERR_NO_MEM; + if(unlikely( offsets[0] >= bundle_size )) { + // First cert starts beyond end of bundle + return false; } - const uint8_t *cur_crt; - /* This is the maximum region that is allowed to access */ - const uint8_t *bundle_end = x509_bundle + bundle_size; - cur_crt = x509_bundle + BUNDLE_HEADER_OFFSET; + const uint32_t num_certs = esp_crt_get_certcount(x509_bundle); - for (int i = 0; i < num_certs; i++) { - crts[i] = cur_crt; - if (cur_crt + CRT_HEADER_OFFSET > bundle_end) { - ESP_LOGE(TAG, "Invalid certificate bundle"); - free(crts); - return ESP_ERR_INVALID_ARG; + if(unlikely( num_certs > CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_MAX_CERTS )) { + ESP_LOGE(TAG, "Cert bundle certificates exceed max allowed certificates"); + return false; + } + + // Check all offsets for consistency with certificate data + for (uint32_t i = 0; i < num_certs-1; ++i ) { + const uint32_t off = offsets[i]; + cert_t cert = x509_bundle + off; + // The next offset in the list must point to right after the current cert + const uint32_t expected_next_offset = off + esp_crt_get_len(cert); + + if( unlikely( offsets[i+1] != expected_next_offset || expected_next_offset >= bundle_size ) ) { + return false; } - size_t name_len = cur_crt[0] << 8 | cur_crt[1]; - size_t key_len = cur_crt[2] << 8 | cur_crt[3]; - cur_crt = cur_crt + CRT_HEADER_OFFSET + name_len + key_len; } - if (cur_crt > bundle_end) { - ESP_LOGE(TAG, "Invalid certificate bundle"); - free(crts); + // All checks passed. + return true; +} + +/* + the bundle generated by the python utility is already presorted by subject name + */ +static esp_err_t esp_crt_bundle_init(const uint8_t* const x509_bundle, const size_t bundle_size) +{ + if ( likely( esp_crt_check_bundle(x509_bundle, bundle_size) ) ) { + s_crt_bundle = x509_bundle; + return ESP_OK; + } else { return ESP_ERR_INVALID_ARG; } - - /* The previous crt bundle is only updated when initialization of the - * current crt_bundle is successful */ - /* Free previous crt_bundle */ - free(s_crt_bundle.crts); - s_crt_bundle.num_certs = num_certs; - s_crt_bundle.crts = crts; - return ESP_OK; } esp_err_t esp_crt_bundle_attach(void *conf) { esp_err_t ret = ESP_OK; // If no bundle has been set by the user then use the bundle embedded in the binary - if (s_crt_bundle.crts == NULL) { + if (s_crt_bundle == NULL) { ret = esp_crt_bundle_init(x509_crt_imported_bundle_bin_start, x509_crt_imported_bundle_bin_end - x509_crt_imported_bundle_bin_start); } - if (ret != ESP_OK) { + if ( unlikely(ret != ESP_OK) ) { ESP_LOGE(TAG, "Failed to attach bundle"); return ret; } @@ -218,8 +339,7 @@ esp_err_t esp_crt_bundle_attach(void *conf) * cacert_ptr passes non-NULL check during handshake */ mbedtls_ssl_config *ssl_conf = (mbedtls_ssl_config *)conf; - mbedtls_x509_crt_init(&s_dummy_crt); - mbedtls_ssl_conf_ca_chain(ssl_conf, &s_dummy_crt, NULL); + mbedtls_ssl_conf_ca_chain(ssl_conf, (mbedtls_x509_crt*)&s_dummy_crt, NULL); mbedtls_ssl_conf_verify(ssl_conf, esp_crt_verify_callback, NULL); } @@ -228,8 +348,7 @@ esp_err_t esp_crt_bundle_attach(void *conf) void esp_crt_bundle_detach(mbedtls_ssl_config *conf) { - free(s_crt_bundle.crts); - s_crt_bundle.crts = NULL; + s_crt_bundle = NULL; if (conf) { mbedtls_ssl_conf_verify(conf, NULL, NULL); } diff --git a/components/mbedtls/esp_crt_bundle/gen_crt_bundle.py b/components/mbedtls/esp_crt_bundle/gen_crt_bundle.py index 0211514a460..2e5bca544b1 100755 --- a/components/mbedtls/esp_crt_bundle/gen_crt_bundle.py +++ b/components/mbedtls/esp_crt_bundle/gen_crt_bundle.py @@ -8,18 +8,16 @@ # The bundle will have the format: number of certificates; crt 1 subject name length; crt 1 public key length; # crt 1 subject name; crt 1 public key; crt 2... # -# SPDX-FileCopyrightText: 2018-2022 Espressif Systems (Shanghai) CO LTD +# SPDX-FileCopyrightText: 2018-2024 Espressif Systems (Shanghai) CO LTD # SPDX-License-Identifier: Apache-2.0 - -from __future__ import with_statement - import argparse import csv import os import re import struct import sys -from io import open + +DEFAULT_CERT_BUNDLE_MAX_CERTS = 200 try: from cryptography import x509 @@ -54,9 +52,6 @@ def __init__(self): self.certificates = [] self.compressed_crts = [] - if os.path.isfile(ca_bundle_bin_file): - os.remove(ca_bundle_bin_file) - def add_from_path(self, crts_path): found = False @@ -116,11 +111,21 @@ def add_from_der(self, crt_str): self.certificates.append(x509.load_der_x509_certificate(crt_str, default_backend())) status('Successfully added 1 certificate') - def create_bundle(self): + def create_bundle(self, max_certs=DEFAULT_CERT_BUNDLE_MAX_CERTS): + if max_certs < len(self.certificates): + critical(f'No. of certs in the certificate bundle = {len(self.certificates)} exceeds\n \ + Max allowed certificates in the certificate bundle = {max_certs} \ + Please update the menuconfig option with appropriate value') + raise ValueError + # Sort certificates in order to do binary search when looking up certificates self.certificates = sorted(self.certificates, key=lambda cert: cert.subject.public_bytes(default_backend())) - bundle = struct.pack('>H', len(self.certificates)) + # List of offsets in bytes from the start of the bundle to each certificate inside + offsets = [] + len_offsets = 4 * len(self.certificates) # final size of the offsets list + + bundle = b'' for crt in self.certificates: """ Read the public key as DER format """ @@ -132,12 +137,18 @@ def create_bundle(self): name_len = len(sub_name_der) key_len = len(pub_key_der) - len_data = struct.pack('>HH', name_len, key_len) + len_data = struct.pack('Vgx$? diff --git a/components/mbedtls/test_apps/main/crts/server_cert_bundle b/components/mbedtls/test_apps/main/crts/server_cert_bundle index 0b7f09aa06da459957cb5c4df81df1876b9597b8..5a0a2f139f52aa4576798324076a533e2a8457a2 100644 GIT binary patch delta 17 YcmbQhJc*fug@J(~g+YyRBU=|E02>tp0ssI2 delta 15 WcmbQlJb{^wfsrAFQEekf7b5@{_X7U_ From b097eb12b38894f34ca2a05ea2d07bbada2f840a Mon Sep 17 00:00:00 2001 From: "harshal.patil" Date: Fri, 28 Jun 2024 11:15:40 +0530 Subject: [PATCH 077/472] ci(mbedtls/esp_crt_bundle): Format esp_crt_bundle.c using astyle --- .../mbedtls/esp_crt_bundle/esp_crt_bundle.c | 70 +++++++++++-------- 1 file changed, 40 insertions(+), 30 deletions(-) diff --git a/components/mbedtls/esp_crt_bundle/esp_crt_bundle.c b/components/mbedtls/esp_crt_bundle/esp_crt_bundle.c index ef2e85542f5..dc75d0cff42 100644 --- a/components/mbedtls/esp_crt_bundle/esp_crt_bundle.c +++ b/components/mbedtls/esp_crt_bundle/esp_crt_bundle.c @@ -65,7 +65,8 @@ typedef const uint8_t* cert_t; static bundle_t s_crt_bundle; // Read a 16-bit value stored in little-endian format from the given address -static uint16_t get16_le (const uint8_t* ptr) { +static uint16_t get16_le(const uint8_t* ptr) +{ #if defined(__BYTE_ORDER__) && (__BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__) return *((const uint16_t*)ptr); #else @@ -73,31 +74,38 @@ static uint16_t get16_le (const uint8_t* ptr) { #endif } -static uint16_t esp_crt_get_name_len(const cert_t cert) { +static uint16_t esp_crt_get_name_len(const cert_t cert) +{ return get16_le(cert + CRT_NAME_LEN_OFFSET); } -static const uint8_t* esp_crt_get_name(const cert_t cert) { +static const uint8_t* esp_crt_get_name(const cert_t cert) +{ return cert + CRT_NAME_OFFSET; } -static uint16_t esp_crt_get_key_len(const cert_t cert) { +static uint16_t esp_crt_get_key_len(const cert_t cert) +{ return get16_le(cert + CRT_KEY_LEN_OFFSET); } -static const uint8_t* esp_crt_get_key(const cert_t cert) { +static const uint8_t* esp_crt_get_key(const cert_t cert) +{ return esp_crt_get_name(cert) + esp_crt_get_name_len(cert); } -static uint16_t esp_crt_get_len(const cert_t cert) { +static uint16_t esp_crt_get_len(const cert_t cert) +{ return CRT_HEADER_SIZE + esp_crt_get_name_len(cert) + esp_crt_get_key_len(cert); } -static uint32_t esp_crt_get_cert_offset(const bundle_t bundle, const uint32_t index) { +static uint32_t esp_crt_get_cert_offset(const bundle_t bundle, const uint32_t index) +{ return ((const uint32_t*)bundle)[index]; } -static uint32_t esp_crt_get_certcount(const bundle_t bundle) { +static uint32_t esp_crt_get_certcount(const bundle_t bundle) +{ // Offset of 1st certificate == end of offset list == size of offset list == # of certs * sizeof(uint32_t) return esp_crt_get_cert_offset(bundle, 0) / sizeof(uint32_t); } @@ -109,7 +117,8 @@ static uint32_t esp_crt_get_certcount(const bundle_t bundle) { * @param index of the certificate; must be less than \c esp_crt_get_certcount(...) ! * @return pointer to the certificate */ -static cert_t esp_crt_get_cert(const bundle_t bundle, const uint32_t index) { +static cert_t esp_crt_get_cert(const bundle_t bundle, const uint32_t index) +{ return bundle + esp_crt_get_cert_offset(bundle, index); } @@ -121,13 +130,13 @@ static int esp_crt_check_signature(const mbedtls_x509_crt* child, const uint8_t* mbedtls_pk_init(&pubkey); - if ( unlikely( (ret = mbedtls_pk_parse_public_key(&pubkey, pub_key_buf, pub_key_len)) != 0 ) ) { + if (unlikely((ret = mbedtls_pk_parse_public_key(&pubkey, pub_key_buf, pub_key_len)) != 0)) { ESP_LOGE(TAG, "PK parse failed with error 0x%x", -ret); goto cleanup; } // Fast check to avoid expensive computations when not necessary - if ( unlikely( !mbedtls_pk_can_do( &pubkey, child->MBEDTLS_PRIVATE(sig_pk)) ) ) { + if (unlikely(!mbedtls_pk_can_do(&pubkey, child->MBEDTLS_PRIVATE(sig_pk)))) { ESP_LOGE(TAG, "Unsuitable public key"); ret = MBEDTLS_ERR_PK_TYPE_MISMATCH; goto cleanup; @@ -135,7 +144,7 @@ static int esp_crt_check_signature(const mbedtls_x509_crt* child, const uint8_t* md_info = mbedtls_md_info_from_type(child->MBEDTLS_PRIVATE(sig_md)); - if( unlikely( md_info == NULL) ) { + if (unlikely(md_info == NULL)) { ESP_LOGE(TAG, "Unknown message digest"); ret = MBEDTLS_ERR_X509_FEATURE_UNAVAILABLE; goto cleanup; @@ -149,9 +158,9 @@ static int esp_crt_check_signature(const mbedtls_x509_crt* child, const uint8_t* goto cleanup; } - if ( unlikely( (ret = mbedtls_pk_verify_ext(child->MBEDTLS_PRIVATE(sig_pk), child->MBEDTLS_PRIVATE(sig_opts), &pubkey, - child->MBEDTLS_PRIVATE(sig_md), hash, md_size, - child->MBEDTLS_PRIVATE(sig).p, child->MBEDTLS_PRIVATE(sig).len)) != 0 ) ) { + if (unlikely((ret = mbedtls_pk_verify_ext(child->MBEDTLS_PRIVATE(sig_pk), child->MBEDTLS_PRIVATE(sig_opts), &pubkey, + child->MBEDTLS_PRIVATE(sig_md), hash, md_size, + child->MBEDTLS_PRIVATE(sig).p, child->MBEDTLS_PRIVATE(sig).len)) != 0)) { ESP_LOGE(TAG, "PK verify failed with error 0x%x", -ret); goto cleanup; } @@ -163,12 +172,12 @@ static int esp_crt_check_signature(const mbedtls_x509_crt* child, const uint8_t* static cert_t esp_crt_find_cert(const unsigned char* const issuer, const size_t issuer_len) { - if (unlikely( issuer == NULL || issuer_len == 0 )) { + if (unlikely(issuer == NULL || issuer_len == 0)) { return NULL; } int start = 0; - int end = esp_crt_get_certcount(s_crt_bundle)-1; + int end = esp_crt_get_certcount(s_crt_bundle) - 1; int middle = (start + end) / 2; cert_t cert = NULL; @@ -182,9 +191,9 @@ static cert_t esp_crt_find_cert(const unsigned char* const issuer, const size_t // Issuers are in DER encoding, with lengths encoded in the content; if valid DER, differing lengths // are reflected in differing content. // Still, we won't try to memcmp beyond the given length: - int cmp_res = memcmp(issuer, esp_crt_get_name(cert), MIN(issuer_len, cert_name_len) ); + int cmp_res = memcmp(issuer, esp_crt_get_name(cert), MIN(issuer_len, cert_name_len)); - if ( unlikely( cmp_res == 0 ) ) { + if (unlikely(cmp_res == 0)) { return cert; } else if (cmp_res < 0) { end = middle - 1; @@ -216,7 +225,8 @@ int esp_crt_verify_callback(void *buf, mbedtls_x509_crt* const crt, const int de return 0; } - if( unlikely( s_crt_bundle == NULL ) ) { + + if (unlikely(s_crt_bundle == NULL)) { ESP_LOGE(TAG, "No certificates in bundle"); return MBEDTLS_ERR_X509_FATAL_ERROR; } @@ -225,11 +235,11 @@ int esp_crt_verify_callback(void *buf, mbedtls_x509_crt* const crt, const int de cert_t cert = esp_crt_find_cert(child->issuer_raw.p, child->issuer_raw.len); - if ( likely( cert != NULL ) ) { + if (likely(cert != NULL)) { const int ret = esp_crt_check_signature(child, esp_crt_get_key(cert), esp_crt_get_key_len(cert)); - if ( likely( ret == 0 ) ) { + if (likely(ret == 0)) { ESP_LOGI(TAG, "Certificate validated"); *flags = 0; return 0; @@ -265,7 +275,7 @@ int esp_crt_verify_callback(void *buf, mbedtls_x509_crt* const crt, const int de */ static bool esp_crt_check_bundle(const uint8_t* const x509_bundle, const size_t bundle_size) { - if (unlikely( x509_bundle == NULL || bundle_size <= (sizeof(uint32_t) + CRT_HEADER_SIZE)) ) { + if (unlikely(x509_bundle == NULL || bundle_size <= (sizeof(uint32_t) + CRT_HEADER_SIZE))) { // Bundle is too small for even one offset and one certificate return false; } @@ -273,32 +283,32 @@ static bool esp_crt_check_bundle(const uint8_t* const x509_bundle, const size_t // Pointer to the first offset entry const uint32_t* offsets = (const uint32_t*)x509_bundle; - if(unlikely( offsets[0] == 0 || (offsets[0] % sizeof(uint32_t)) != 0) ) { + if (unlikely(offsets[0] == 0 || (offsets[0] % sizeof(uint32_t)) != 0)) { // First offset is invalid. // The first certificate must start after N uint32_t offset values. return false; } - if(unlikely( offsets[0] >= bundle_size )) { + if (unlikely(offsets[0] >= bundle_size)) { // First cert starts beyond end of bundle return false; } const uint32_t num_certs = esp_crt_get_certcount(x509_bundle); - if(unlikely( num_certs > CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_MAX_CERTS )) { + if (unlikely(num_certs > CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_MAX_CERTS)) { ESP_LOGE(TAG, "Cert bundle certificates exceed max allowed certificates"); return false; } // Check all offsets for consistency with certificate data - for (uint32_t i = 0; i < num_certs-1; ++i ) { + for (uint32_t i = 0; i < num_certs - 1; ++i) { const uint32_t off = offsets[i]; cert_t cert = x509_bundle + off; // The next offset in the list must point to right after the current cert const uint32_t expected_next_offset = off + esp_crt_get_len(cert); - if( unlikely( offsets[i+1] != expected_next_offset || expected_next_offset >= bundle_size ) ) { + if (unlikely(offsets[i + 1] != expected_next_offset || expected_next_offset >= bundle_size)) { return false; } } @@ -312,7 +322,7 @@ static bool esp_crt_check_bundle(const uint8_t* const x509_bundle, const size_t */ static esp_err_t esp_crt_bundle_init(const uint8_t* const x509_bundle, const size_t bundle_size) { - if ( likely( esp_crt_check_bundle(x509_bundle, bundle_size) ) ) { + if (likely(esp_crt_check_bundle(x509_bundle, bundle_size))) { s_crt_bundle = x509_bundle; return ESP_OK; } else { @@ -328,7 +338,7 @@ esp_err_t esp_crt_bundle_attach(void *conf) ret = esp_crt_bundle_init(x509_crt_imported_bundle_bin_start, x509_crt_imported_bundle_bin_end - x509_crt_imported_bundle_bin_start); } - if ( unlikely(ret != ESP_OK) ) { + if (unlikely(ret != ESP_OK)) { ESP_LOGE(TAG, "Failed to attach bundle"); return ret; } From 20fff296e4eb65389b4468442b6a514d9b5716f3 Mon Sep 17 00:00:00 2001 From: "harshal.patil" Date: Mon, 15 Jul 2024 20:14:31 +0530 Subject: [PATCH 078/472] test(mbedtls): Update custom cert bundle init API - bound checking testcase - Support the newer cert bundle format in the test --- .../test_apps/main/test_esp_crt_bundle.c | 133 +++++++++++++----- 1 file changed, 96 insertions(+), 37 deletions(-) diff --git a/components/mbedtls/test_apps/main/test_esp_crt_bundle.c b/components/mbedtls/test_apps/main/test_esp_crt_bundle.c index 777af0425bd..4b4ae1f927b 100644 --- a/components/mbedtls/test_apps/main/test_esp_crt_bundle.c +++ b/components/mbedtls/test_apps/main/test_esp_crt_bundle.c @@ -6,8 +6,9 @@ * * SPDX-License-Identifier: Apache-2.0 * - * SPDX-FileContributor: 2019-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileContributor: 2019-2024 Espressif Systems (Shanghai) CO LTD */ +#include #include "esp_err.h" #include "esp_log.h" @@ -41,6 +42,7 @@ extern const uint8_t server_cert_chain_pem_end[] asm("_binary_server_cert_chai extern const uint8_t server_pk_start[] asm("_binary_prvtkey_pem_start"); extern const uint8_t server_pk_end[] asm("_binary_prvtkey_pem_end"); +// `server_cert_bundle_corrupt` is created by generating the cert bundle using `server_root.pem` extern const uint8_t server_cert_bundle_start[] asm("_binary_server_cert_bundle_start"); extern const uint8_t server_cert_bundle_end[] asm("_binary_server_cert_bundle_end"); @@ -272,7 +274,7 @@ void client_task(void *pvParameters) goto exit; } - /* Test with default crt bundle that doesnt contain the ca crt */ + /* Test with default crt bundle that does not contain the ca crt */ ESP_LOGI(TAG, "Connecting to %s:%s...", SERVER_ADDRESS, SERVER_PORT); if ((ret = mbedtls_net_connect(&client.client_fd, SERVER_ADDRESS, SERVER_PORT, MBEDTLS_NET_PROTO_TCP)) != 0) { ESP_LOGE(TAG, "mbedtls_net_connect returned -%x", -ret); @@ -300,7 +302,7 @@ void client_task(void *pvParameters) } else { ESP_LOGE(TAG, "Certificate verification failed!"); } - TEST_ASSERT(res == ESP_CRT_VALIDATE_FAIL); + TEST_ASSERT_EQUAL(ESP_CRT_VALIDATE_FAIL, res); // Reset session before new connection mbedtls_ssl_close_notify(&client.ssl); @@ -338,7 +340,7 @@ void client_task(void *pvParameters) } else { ESP_LOGE(TAG, "Certificate verification failed!"); } - TEST_ASSERT(res == ESP_CRT_VALIDATE_OK); + TEST_ASSERT_EQUAL(ESP_CRT_VALIDATE_OK, res); // Reset session before new connection mbedtls_ssl_close_notify(&client.ssl); @@ -406,7 +408,7 @@ TEST_CASE("custom certificate bundle - weak hash", "[mbedtls]") mbedtls_x509_crt_init( &crt ); mbedtls_x509_crt_parse(&crt, bad_md_crt_pem_start, bad_md_crt_pem_end - bad_md_crt_pem_start); - TEST_ASSERT(mbedtls_x509_crt_verify(&crt, NULL, NULL, NULL, &flags, esp_crt_verify_callback, NULL) == 0); + TEST_ASSERT_EQUAL(0, mbedtls_x509_crt_verify(&crt, NULL, NULL, NULL, &flags, esp_crt_verify_callback, NULL)); mbedtls_x509_crt_free(&crt); @@ -426,62 +428,119 @@ TEST_CASE("custom certificate bundle - wrong signature", "[mbedtls]") /* esp32.com cert chain where 1 byte in the signature is changed */ printf("Testing certificate with wrong signature\n"); mbedtls_x509_crt_parse(&crt, wrong_sig_crt_pem_start, wrong_sig_crt_pem_end - wrong_sig_crt_pem_start); - TEST_ASSERT(mbedtls_x509_crt_verify(&crt, NULL, NULL, NULL, &flags, esp_crt_verify_callback, NULL) != 0); + TEST_ASSERT_NOT_EQUAL(0, mbedtls_x509_crt_verify(&crt, NULL, NULL, NULL, &flags, esp_crt_verify_callback, NULL)); mbedtls_x509_crt_free(&crt); mbedtls_x509_crt_init( &crt ); /* the correct esp32.com cert chain*/ printf("Testing certificate with correct signature\n"); mbedtls_x509_crt_parse(&crt, correct_sig_crt_pem_start, correct_sig_crt_pem_end - correct_sig_crt_pem_start); - TEST_ASSERT(mbedtls_x509_crt_verify(&crt, NULL, NULL, NULL, &flags, esp_crt_verify_callback, NULL) == 0); + TEST_ASSERT_EQUAL(0, mbedtls_x509_crt_verify(&crt, NULL, NULL, NULL, &flags, esp_crt_verify_callback, NULL)); mbedtls_x509_crt_free(&crt); esp_crt_bundle_detach(NULL); } -TEST_CASE("custom certificate bundle init API - bound checking", "[mbedtls]") +TEST_CASE("custom certificate bundle init API - bound checking - NULL certificate bundle", "[mbedtls]") { + esp_err_t esp_ret; + + /* The API should fail when NULL is passed as the bundle */ + esp_ret = esp_crt_bundle_set(NULL, 0); + TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, esp_ret); +} - uint8_t test_bundle[256] = {0}; +TEST_CASE("custom certificate bundle init API - bound checking - Invalid size of certificate bundle", "[mbedtls]") +{ + uint8_t test_bundle[1024] = {0}; esp_err_t esp_ret; + /* The API should fail with bundle size given as 1 */ esp_ret = esp_crt_bundle_set(test_bundle, 1); - TEST_ASSERT( esp_ret == ESP_ERR_INVALID_ARG); + TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, esp_ret); +} + +TEST_CASE("custom certificate bundle init API - bound checking - Invalid first certificate offset", "[mbedtls]") +{ + uint8_t test_bundle[1024] = {0}; + esp_err_t esp_ret; + + /* Check that the esp_crt_bundle_set API will not accept + * the first offset to be invalid */ + + /* The first certificate must start after N uint32_t offset values, + * thus, it cannot start from the 0th position */ + test_bundle[0] = 0; + esp_ret = esp_crt_bundle_set(test_bundle, sizeof(test_bundle)); + TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, esp_ret); + + /* The first certificate must start after N uint32_t offset values, thus, + * the offset from where the it would start should be divisible by sizeof(uint32_t) */ + test_bundle[0] = 1; + esp_ret = esp_crt_bundle_set(test_bundle, sizeof(test_bundle)); + TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, esp_ret); + + /* Check that the esp_crt_bundle_set API will not accept a bundle + * which in which the first cert starts beyond end of bundle*/ + uint8_t *dummy_test_bundle = test_bundle + sizeof(uint32_t); + + esp_ret = esp_crt_bundle_set(dummy_test_bundle, sizeof(test_bundle)); + TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, esp_ret); +} + +TEST_CASE("custom certificate bundle init API - bound checking - Certificates count overflow", "[mbedtls]") +{ + uint8_t test_bundle[1024] = {0}; + esp_err_t esp_ret; + + memset(test_bundle, 0, sizeof(test_bundle)); /* Check that the esp_crt_bundle_set API will not accept a bundle * which has more no. of certs than configured in * CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_MAX_CERTS */ + *((uint32_t*) test_bundle) = ((CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_MAX_CERTS + 1) * sizeof(uint32_t)); - uint8_t rand; - esp_fill_random(&rand, 1); - test_bundle[0] = rand; + esp_ret = esp_crt_bundle_set(test_bundle, sizeof(test_bundle)); + TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, esp_ret); - /* Make sure that the number of certs will always be greater than - * CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_MAX_CERTS */ - test_bundle[1] = rand + CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_MAX_CERTS; + esp_crt_bundle_detach(NULL); +} + +TEST_CASE("custom certificate bundle init API - bound checking - Incorrect certificate offset", "[mbedtls]") +{ + uint8_t test_bundle[1024] = {0}; + esp_err_t esp_ret; + + memset(test_bundle, 0, sizeof(test_bundle)); + + /* Check that the esp_crt_bundle_set API will not accept a bundle where + all offsets are not consistent with certificate data */ + + /* + | offset 1 | offset 2 | Cert 1 name len | Cert 1 key len | Cert 1 name | Cert 1 key | Cert 2 name len | ..... | + | ----- offsets ----- | + | ---------------------- Certificate 1 ---------------------- | + | ---- Certificate 2 ---- | + */ + + *((uint32_t*) &test_bundle[0]) = (2 * sizeof(uint32_t)); + *((uint16_t*) &test_bundle[8]) = 2; // Cert 1 name len + *((uint16_t*) &test_bundle[10]) = 4; // Cert 1 key len + + /* Correct offset of certificate 2 should be + = 2 * sizeof(uint32_t) (Offsets of 2 certs) + 2 * sizeof(uint16_t) (Cert name and len) + 2 (Cert 1 name len) + 4 (Cert 1 key len); + = 18 + */ + *((uint32_t*) &test_bundle[4]) = 16; // Incorrect certificate 2 offset esp_ret = esp_crt_bundle_set(test_bundle, sizeof(test_bundle)); - TEST_ASSERT( esp_ret == ESP_ERR_INVALID_ARG); + TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, esp_ret); - /* The API should fail with bundle_size < BUNDLE_HEADER_OFFSET (2) + CRT_HEADER_OFFSET (4) */ - test_bundle[0] = 0; - test_bundle[1] = 1; /* set num_certs = 1 */ - esp_ret = esp_crt_bundle_set(test_bundle, 5); - TEST_ASSERT(esp_ret == ESP_ERR_INVALID_ARG); - - /* Cert number is greater than actual certs present, The API should fail */ - /* Actual No. of certs present in bundle = 1, setting num_certs to 5 */ - test_bundle[1] = 5; /* num_certs */ - test_bundle[3] = 5; /* cert_1_name_len */ - test_bundle[5] = 10; /* cert_1_pub_key_len */ - /* Actual bundle size becomes BUNDLE_HEADER_OFFSET (2) + CRT_HEADER_OFFSET (4) + cert_1_name_len(5) + cert_1_pub_key_len(10) - * i.e. 21 bytes */ - esp_ret = esp_crt_bundle_set(test_bundle, 21); - TEST_ASSERT(esp_ret == ESP_ERR_INVALID_ARG); - - /* The API should fail if bundle_size < BUNDLE_HEADER_OFFSET (2) + CRT_HEADER_OFFSET (4) + cert_1_name_len(5) + cert_1_pub_key_len(10) */ - esp_ret = esp_crt_bundle_set(test_bundle, 20); - TEST_ASSERT(esp_ret == ESP_ERR_INVALID_ARG); + /* Check that the esp_crt_bundle_set API will not accept a bundle where + all offsets are not consistency with certificate data and the certificate + offsets exceeds the bundle size */ + *((uint32_t*) &test_bundle[4]) = sizeof(test_bundle) + 1; // Offset exceeds the test_bundle size - esp_crt_bundle_detach(NULL); + esp_ret = esp_crt_bundle_set(test_bundle, sizeof(test_bundle)); + TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, esp_ret); } From 0702fb82b0021e4812f4715febcddfbf3f534785 Mon Sep 17 00:00:00 2001 From: "harshal.patil" Date: Mon, 15 Jul 2024 17:42:20 +0530 Subject: [PATCH 079/472] ci(examples/protocols): Add more testing connections in the x509 bundle example - This adds a test to try connecting to the domains that use the most common certificate authorities with the default full cert bundle --- .../main/https_x509_bundle_example_main.c | 13 +++++++ .../pytest_https_x509_bundle.py | 36 ++++++++++--------- .../sdkconfig.ci.default_crt_bundle | 10 ++++++ 3 files changed, 42 insertions(+), 17 deletions(-) create mode 100644 examples/protocols/https_x509_bundle/sdkconfig.ci.default_crt_bundle diff --git a/examples/protocols/https_x509_bundle/main/https_x509_bundle_example_main.c b/examples/protocols/https_x509_bundle/main/https_x509_bundle_example_main.c index 966aa8173e3..33e3040cf90 100644 --- a/examples/protocols/https_x509_bundle/main/https_x509_bundle_example_main.c +++ b/examples/protocols/https_x509_bundle/main/https_x509_bundle_example_main.c @@ -43,11 +43,24 @@ #include "esp_tls.h" #include "esp_crt_bundle.h" +#if CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_DEFAULT_FULL +#define MAX_URLS 9 +#else #define MAX_URLS 2 +#endif static const char *web_urls[MAX_URLS] = { "https://www.howsmyssl.com/a/check", "https://espressif.com", +#if CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_DEFAULT_FULL + "https://letsencrypt.org", + "https://www.identrust.com", + "https://www.globalsign.com", + "https://www.sectigo.com", + "https://www.digicert.com", + "https://www.godaddy.com", + "https://rainmaker.espressif.com", // Amazon +#endif }; static const char *TAG = "example"; diff --git a/examples/protocols/https_x509_bundle/pytest_https_x509_bundle.py b/examples/protocols/https_x509_bundle/pytest_https_x509_bundle.py index 12ef0d1f1d2..2e6aa598106 100644 --- a/examples/protocols/https_x509_bundle/pytest_https_x509_bundle.py +++ b/examples/protocols/https_x509_bundle/pytest_https_x509_bundle.py @@ -1,10 +1,9 @@ -# SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD +# SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD # SPDX-License-Identifier: Unlicense OR CC0-1.0 import logging import os import pytest -from common_test_methods import get_env_config_variable from pytest_embedded import Dut @@ -21,17 +20,11 @@ def test_examples_protocol_https_x509_bundle(dut: Dut) -> None: binary_file = os.path.join(dut.app.binary_path, 'https_x509_bundle.bin') bin_size = os.path.getsize(binary_file) logging.info('https_x509_bundle_bin_size : {}KB'.format(bin_size // 1024)) - # Connect to AP - if dut.app.sdkconfig.get('EXAMPLE_WIFI_SSID_PWD_FROM_STDIN') is True: - dut.expect('Please input ssid password:') - env_name = 'wifi_ap' - ap_ssid = get_env_config_variable(env_name, 'ap_ssid') - ap_password = get_env_config_variable(env_name, 'ap_password') - dut.write(f'{ap_ssid} {ap_password}') dut.expect(r'IPv4 address: (\d+\.\d+\.\d+\.\d+)[^\d]', timeout=30) # start test num_URLS = int(dut.expect(r'Connecting to (\d+) URLs', timeout=30)[1].decode()) - dut.expect(r'Connection established to ([\s\S]*)', timeout=30) + for _ in range(num_URLS): + dut.expect(r'Connection established to ([\s\S]*)', timeout=30) dut.expect('Completed {} connections'.format(num_URLS), timeout=60) @@ -44,15 +37,24 @@ def test_examples_protocol_https_x509_bundle_dynamic_buffer(dut: Dut) -> None: binary_file = os.path.join(dut.app.binary_path, 'https_x509_bundle.bin') bin_size = os.path.getsize(binary_file) logging.info('https_x509_bundle_bin_size : {}KB'.format(bin_size // 1024)) - # Connect to AP - if dut.app.sdkconfig.get('EXAMPLE_WIFI_SSID_PWD_FROM_STDIN') is True: - dut.expect('Please input ssid password:') - env_name = 'wifi_ap' - ap_ssid = get_env_config_variable(env_name, 'ap_ssid') - ap_password = get_env_config_variable(env_name, 'ap_password') - dut.write(f'{ap_ssid} {ap_password}') dut.expect(r'IPv4 address: (\d+\.\d+\.\d+\.\d+)[^\d]', timeout=30) # start test num_URLS = int(dut.expect(r'Connecting to (\d+) URLs', timeout=30)[1].decode()) dut.expect(r'Connection established to ([\s\S]*)', timeout=30) dut.expect('Completed {} connections'.format(num_URLS), timeout=60) + + +@pytest.mark.esp32 +@pytest.mark.ethernet +@pytest.mark.parametrize('config', ['default_crt_bundle',], indirect=True) +def test_examples_protocol_https_x509_bundle_default_crt_bundle_stress_test(dut: Dut) -> None: + # check and log bin size + binary_file = os.path.join(dut.app.binary_path, 'https_x509_bundle.bin') + bin_size = os.path.getsize(binary_file) + logging.info('https_x509_bundle_bin_size : {}KB'.format(bin_size // 1024)) + dut.expect(r'IPv4 address: (\d+\.\d+\.\d+\.\d+)[^\d]', timeout=30) + # start test + num_URLS = int(dut.expect(r'Connecting to (\d+) URLs', timeout=30)[1].decode()) + for _ in range(num_URLS): + dut.expect(r'Connection established to ([\s\S]*)', timeout=30) + dut.expect('Completed {} connections'.format(num_URLS), timeout=60) diff --git a/examples/protocols/https_x509_bundle/sdkconfig.ci.default_crt_bundle b/examples/protocols/https_x509_bundle/sdkconfig.ci.default_crt_bundle new file mode 100644 index 00000000000..3f3ad687e40 --- /dev/null +++ b/examples/protocols/https_x509_bundle/sdkconfig.ci.default_crt_bundle @@ -0,0 +1,10 @@ +CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_DEFAULT_FULL=y + +CONFIG_EXAMPLE_CONNECT_ETHERNET=y +CONFIG_EXAMPLE_CONNECT_WIFI=n +CONFIG_EXAMPLE_USE_INTERNAL_ETHERNET=y +CONFIG_EXAMPLE_ETH_PHY_IP101=y +CONFIG_EXAMPLE_ETH_MDC_GPIO=23 +CONFIG_EXAMPLE_ETH_MDIO_GPIO=18 +CONFIG_EXAMPLE_ETH_PHY_RST_GPIO=5 +CONFIG_EXAMPLE_ETH_PHY_ADDR=1 From 2d6188ea765a4e842ef381cabcc8d4b79f575665 Mon Sep 17 00:00:00 2001 From: Sarvesh Bodakhe Date: Mon, 30 Sep 2024 15:25:10 +0530 Subject: [PATCH 080/472] feat(wifi): Add checks for public headers for esp32c5, esp32c61 and esp32_host Add md5sum integrity check for public header files for esp32c5, esp32c61 and esp32_host libraries. --- components/esp_wifi/test_md5/test_md5.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/components/esp_wifi/test_md5/test_md5.sh b/components/esp_wifi/test_md5/test_md5.sh index 98c29f77322..788a8744b7e 100755 --- a/components/esp_wifi/test_md5/test_md5.sh +++ b/components/esp_wifi/test_md5/test_md5.sh @@ -22,7 +22,7 @@ case $IDF_TARGET in esp32s3) PREFIX=xtensa-esp32s3-elf- ;; - esp32c2|esp32c3|esp32c6) + esp32c2|esp32c3|esp32c6|esp32c5|esp32_host|esp32c61) PREFIX=riscv32-esp-elf- ;; *) From 5cab997c15cee0d124f682a5b608547870603301 Mon Sep 17 00:00:00 2001 From: Sarvesh Bodakhe Date: Mon, 30 Sep 2024 16:09:09 +0530 Subject: [PATCH 081/472] ci: Add md5 checksum validation for WiFi public header files for new chips Add MD5 checksum validation for public header files of the following new chips: esp32c5, esp32c6, and esp32_host. --- .gitlab/ci/pre_check.yml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/.gitlab/ci/pre_check.yml b/.gitlab/ci/pre_check.yml index 7bf24fb158f..62a51338900 100644 --- a/.gitlab/ci/pre_check.yml +++ b/.gitlab/ci/pre_check.yml @@ -44,6 +44,9 @@ check_blobs: - IDF_TARGET=esp32c2 $IDF_PATH/components/esp_wifi/test_md5/test_md5.sh - IDF_TARGET=esp32c3 $IDF_PATH/components/esp_wifi/test_md5/test_md5.sh - IDF_TARGET=esp32c6 $IDF_PATH/components/esp_wifi/test_md5/test_md5.sh + - IDF_TARGET=esp32c5 $IDF_PATH/components/esp_wifi/test_md5/test_md5.sh + - IDF_TARGET=esp32c61 $IDF_PATH/components/esp_wifi/test_md5/test_md5.sh + - IDF_TARGET=esp32_host $IDF_PATH/components/esp_wifi/test_md5/test_md5.sh # Check if Coexistence library header files match between IDF and the version used when compiling the libraries - IDF_TARGET=esp32 $IDF_PATH/components/esp_coex/test_md5/test_md5.sh - IDF_TARGET=esp32s2 $IDF_PATH/components/esp_coex/test_md5/test_md5.sh From 8b4ebea87299b777758328ee04c9a66d8cabf582 Mon Sep 17 00:00:00 2001 From: Sarvesh Bodakhe Date: Tue, 8 Oct 2024 10:20:06 +0530 Subject: [PATCH 082/472] ci: Add md5 checksum validation for COEX public header files for new chips Add MD5 checksum validation for public header files of the following new chips: esp32c5 and esp32c61. --- .gitlab/ci/pre_check.yml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/.gitlab/ci/pre_check.yml b/.gitlab/ci/pre_check.yml index 62a51338900..31dfb072664 100644 --- a/.gitlab/ci/pre_check.yml +++ b/.gitlab/ci/pre_check.yml @@ -55,6 +55,8 @@ check_blobs: - IDF_TARGET=esp32c3 $IDF_PATH/components/esp_coex/test_md5/test_md5.sh - IDF_TARGET=esp32c6 $IDF_PATH/components/esp_coex/test_md5/test_md5.sh - IDF_TARGET=esp32h2 $IDF_PATH/components/esp_coex/test_md5/test_md5.sh + - IDF_TARGET=esp32c5 $IDF_PATH/components/esp_coex/test_md5/test_md5.sh + - IDF_TARGET=esp32c61 $IDF_PATH/components/esp_coex/test_md5/test_md5.sh # Check if Wi-Fi, PHY, BT blobs contain references to specific symbols - bash $IDF_PATH/tools/ci/check_blobs.sh From 1ddc11448e338c5eed05503aaaf6afcfab069d4d Mon Sep 17 00:00:00 2001 From: shenmengjing Date: Thu, 20 Jun 2024 17:46:22 +0800 Subject: [PATCH 083/472] docs: Provide Chinese translation for sd_pullup_requirements --- .../peripherals/sd_pullup_requirements.rst | 127 +++--- .../peripherals/sd_pullup_requirements.rst | 361 +++++++++++++++++- 2 files changed, 440 insertions(+), 48 deletions(-) diff --git a/docs/en/api-reference/peripherals/sd_pullup_requirements.rst b/docs/en/api-reference/peripherals/sd_pullup_requirements.rst index 399d5f424ac..21e8e1e5ed9 100644 --- a/docs/en/api-reference/peripherals/sd_pullup_requirements.rst +++ b/docs/en/api-reference/peripherals/sd_pullup_requirements.rst @@ -1,9 +1,11 @@ SD Pull-up Requirements ======================= +:link_to_translation:`zh_CN:[中文]` + Espressif hardware products are designed for multiple use cases which may require different pull states on pins. For this reason, the pull state of particular pins on certain products needs to be adjusted to provide the pull-ups required in the SD bus. -SD pull-up requirements apply to cases where {IDF_TARGET_NAME} uses the SPI or SDMMC controller to communicate with SD cards. When an SD card is operating in SPI mode or 1-bit SD mode, the CMD and DATA (DAT0 - DAT3) lines of the SD bus must be pulled up by 10 kOhm resistors. SD cards and SDIO devices should also have pull-ups on all above-mentioned lines (regardless of whether these lines are connected to the host) in order to prevent them from entering a wrong state. +SD pull-up requirements apply to cases where {IDF_TARGET_NAME} uses the SPI or SDMMC controller to communicate with SD cards. When an SD card is operating in SPI mode or 1-bit SD mode, the CMD and DATA (DAT0 - DAT3) lines of the SD bus must be pulled up by 10 kΩ resistors. SD cards and SDIO devices should also have pull-ups on all above-mentioned lines (regardless of whether these lines are connected to the host) in order to prevent them from entering a wrong state. .. only:: esp32 @@ -11,13 +13,13 @@ SD pull-up requirements apply to cases where {IDF_TARGET_NAME} uses the SPI or S .. todo:: - Add a diagram of the Bus lines and pullups + Add a diagram of the bus lines and pullups This document has the following structure: -- `Overview of compatibility`_ between the default pull states on pins of Espressif's products and the states required by the SD bus -- `Solutions`_ - ideas on how to resolve compatibility issues -- `Related information`_ - other relevant information +- :ref:`compatibility_overview_espressif_hw_sdio` between the default pull states on pins of Espressif's products and the states required by the SD bus +- :ref:`sdio_solutions` - ideas on how to resolve compatibility issues +- :ref:`related_info_sdio` - other relevant information .. _compatibility_overview_espressif_hw_sdio: @@ -28,11 +30,11 @@ Overview of Compatibility This section provides an overview of compatibility issues that might occur when using SDIO (secure digital input output). Since the SD bus needs to be connected to pull-ups, these issues should be resolved regardless of whether they are related to master (host) or slave (device). Each issue has links to its respective solution. A solution for a host and device may differ. -Systems on a Chip (SoCs) -^^^^^^^^^^^^^^^^^^^^^^^^ - .. only:: esp32 + Systems on a Chip (SoCs) + ^^^^^^^^^^^^^^^^^^^^^^^^ + - ESP32 (except for D2WD versions, see `ESP32 datasheet `_): - :ref:`sd_pull-up_no_pull-ups` @@ -45,33 +47,34 @@ Systems on a Chip (SoCs) .. only:: SOC_SDMMC_USE_GPIO_MATRIX - {IDF_TARGET_NAME} SDMMC host controller allows using any of GPIOs for any of SD interface signals. However, it is recommended to avoid using strapping GPIOs, GPIOs with internal weak pull-downs and GPIOs commonly used for other purposes to prevent conflicts: + Systems on a Chip (SoCs) + ^^^^^^^^^^^^^^^^^^^^^^^^ -.. only:: esp32s3 + {IDF_TARGET_NAME} SDMMC host controller allows using any of GPIOs for any of SD interface signals. However, it is recommended to avoid using strapping GPIOs, GPIOs with internal weak pull-downs and GPIOs commonly used for other purposes to prevent conflicts. - - GPIO0 (strapping pin) - - GPIO45, GPIO46 (strapping pins, internal weak pulldown) - - GPIO26 - GPIO32 (commonly used for SPI Flash and PSRAM) - - GPIO33 - GPIO37 (when using chips and modules with Octal SPI Flash or Octal PSRAM) - - GPIO43, GPIO44 (GPIOs used for UART0 by default) - - GPIO19, GPIO20 (GPIOs used for USB by default) + .. only:: esp32s3 + - GPIO0 (strapping pin) + - GPIO45, GPIO46 (strapping pins, internal weak pulldown) + - GPIO26 - GPIO32 (commonly used for SPI flash and PSRAM) + - GPIO33 - GPIO37 (when using chips and modules with octal SPI flash or octal PSRAM) + - GPIO43, GPIO44 (GPIOs used for UART0 by default) + - GPIO19, GPIO20 (GPIOs used for USB by default) -Systems in Packages (SIP) -^^^^^^^^^^^^^^^^^^^^^^^^^ .. only:: esp32 + Systems in Packages (SIP) + ^^^^^^^^^^^^^^^^^^^^^^^^^ + - ESP32-PICO-D4: - :ref:`sd_pull-up_no_pull-ups` - :ref:`strapping_conflicts_dat2` -Modules -^^^^^^^ - -.. only:: esp32 + Modules + ^^^^^^^ - ESP32-WROOM-32 Series, including ESP32-WROOM-32, ESP32-WROOM-32D, ESP32-WROOM-32U, and ESP32-SOLO-1 @@ -88,12 +91,12 @@ Modules - :ref:`strapping_conflicts_dat2` -.. _sdio_dev_kits: +.. only:: esp32 -Development Boards -^^^^^^^^^^^^^^^^^^ + .. _sdio_dev_kits: -.. only:: esp32 + Development Boards + ^^^^^^^^^^^^^^^^^^ - ESP32-PICO-KIT, including PICO-KIT v4.1, v4.0, and v3 @@ -132,6 +135,11 @@ Development Boards .. only:: esp32s3 + .. _sdio_dev_kits: + + Development Boards + ^^^^^^^^^^^^^^^^^^ + - ESP32-S3-DevKitC-1 - :ref:`sd_pull-up_no_pull-ups` @@ -154,6 +162,8 @@ Development Boards Please make sure that your SDIO host provides necessary pull-ups for all SD bus signals. +.. _sdio_solutions: + Solutions --------- @@ -162,10 +172,19 @@ Solutions No Pull-ups ^^^^^^^^^^^ -If you use a development board without pull-ups, you can do the following: +.. only:: esp32 or esp32s3 -- If your host and slave device are on separate boards, replace one of them with a board that has pull-ups. For the list of Espressif's development boards with pull-ups, go to :ref:`sdio_dev_kits`. -- Attach external pull-ups by connecting each pin which requires a pull-up to VDD via a 10 kOhm resistor. + When using a development board without pull-ups: + + - If your host and slave device are on separate boards, replace one of them with a board that has pull-ups. For the list of Espressif's development boards with pull-ups, go to :ref:`sdio_dev_kits`. + - Attach external pull-ups by connecting each pin which requires a pull-up to VDD via a 10 kΩ resistor. + +.. only:: not esp32 and not esp32s3 + + When using a development board without pull-ups: + + - If your host and slave device are on separate boards, replace one of them with a board that has pull-ups. + - Attach external pull-ups by connecting each pin which requires a pull-up to VDD via a 10 kΩ resistor. .. only:: esp32 @@ -180,7 +199,7 @@ If you use a development board without pull-ups, you can do the following: - Use SPI mode - Perform one of the following actions on the GPIO13 pin: - Remove the pull-down resistors - - Attach a pull-up resistor of less than 5 kOhm (2 kOhm suggested) + - Attach a pull-up resistor of less than 5 kΩ (2 kΩ suggested) - Pull it up or drive it high either by using the host or with 3.3 V on VDD in 1-bit SD mode @@ -219,20 +238,20 @@ If you use a development board without pull-ups, you can do the following: BURN VDD_SDIO setting complete. - To check the status of the eFuses, run:: + To check the status of the eFuses, run: - .. code-block:: + .. code-block:: none idf.py efuse-summary - If running from an automated flashing script, it is better to use standalone eFuse tool, ``espefuse.py``. This tool also has an option ``--do-not-confirm`` to burn eFuses without confirmation. + If running from an automated flashing script, it is better to use standalone eFuse tool ``espefuse.py``. This tool also has an option ``--do-not-confirm`` to burn eFuses without confirmation. For more details, see **{IDF_TARGET_NAME} Technical Reference Manual** [`PDF <{IDF_TARGET_TRM_EN_URL}#efuse>`__]. - 2. **If using 1-bit SD mode or SPI mode**, disconnect the DAT2 pin and make sure it is pulled high. For this, do one the following: + 2. **If using 1-bit SD mode or SPI mode**, disconnect the DAT2 pin and make sure it is pulled high. For this, you have the following options: - - Leave the host's DAT2 floating and directly connect the slave's DAT2 to VDD. - - For a slave device, build a firmware with the option ``SDIO_SLAVE_FLAG_DAT2_DISABLED`` and re-flash your device. This option helps avoid slave detecting on the DAT2 line. Note that 4-bit SD mode is no longer supported by the standard Card Common Control Register (CCCR); however, the host is not aware of that. The use of 4-bit SD mode has to be disabled on the host's side. + - Leave the host's DAT2 floating and directly connect the slave's DAT2 to VDD. + - For a slave device, build a firmware with the option ``SDIO_SLAVE_FLAG_DAT2_DISABLED`` and re-flash your device. This option helps avoid slave detecting on the DAT2 line. Note that 4-bit SD mode is no longer supported by the standard Card Common Control Register (CCCR); however, the host is not aware of that. The use of 4-bit SD mode has to be disabled on the host's side. .. _no_pull-up_on_gpio12: @@ -240,7 +259,7 @@ If you use a development board without pull-ups, you can do the following: No Pull-up on GPIO12 ^^^^^^^^^^^^^^^^^^^^ - Your module is compatible with the SDIO protocol. Just connect GPIO12 to VDD via a 10 kOhm resistor. + Your module is compatible with the SDIO protocol. Just connect GPIO12 to VDD via a 10 kΩ resistor. .. _gpio2_strapping_pin: @@ -248,25 +267,25 @@ If you use a development board without pull-ups, you can do the following: Download Mode Not Working (minor issue) ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - When the GPIO2 pin is pulled high in accordance with the SD pull-up requirements, you cannot enter Download mode because GPIO2 is a bootstrapping pin which in this case must be pulled low. + When the GPIO2 pin is pulled high in accordance with the SD pull-up requirements, you can not enter download mode because GPIO2 is a bootstrapping pin which in this case must be pulled low. - There are the following solutions: + There are following solutions: - - For boards that require shorting the GPIO0 and GPIO2 pins with a jumper, put the jumper in place, and the auto-reset circuit pulls GPIO2 low along with GPIO0 before entering Download mode. + - For boards that require shorting the GPIO0 and GPIO2 pins with a jumper, put the jumper in place, and the auto-reset circuit pulls GPIO2 low along with GPIO0 before entering download mode. - For boards with components attached to their GPIO2 pin (such as pull-down resistors and/or LEDs), check the schematic of your development board for anything connected to GPIO2. - **LEDs** would not affect operation in most cases. - **Pull-down resistors** can interfere with DAT0 signals and must be removed. - If the above solutions do not work for you, please determine if it is the host or slave device that has pull-ups affecting their GPIO2, then locate these pull-ups and remove them. + If above solutions do not work for you, please determine if it is the host or slave device that has pull-ups affecting their GPIO2, then locate these pull-ups and remove them. -.. _related_info_sdio: +.. only:: esp32 -Related Information -------------------- + .. _related_info_sdio: -.. only:: esp32 + Related Information + ------------------- .. _mtdi_strapping_pin: @@ -287,9 +306,9 @@ Related Information Internal Pull-ups and Strapping Requirements ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - Using external resistors is always preferable. However, Espressif's products have internal weak pull-up and pull-down resistors which can be enabled and used instead of external ones. Please keep in mind that this solution cannot guarantee reliable SDIO communication. + Using external resistors is always preferable. However, Espressif's products have internal weak pull-up and pull-down resistors which can be enabled and used instead of external ones. Please keep in mind that this solution can not guarantee reliable SDIO communication. - With that said, the information about these internal pull-ups and strapping requirements can still be useful. Espressif hardware products have different weak internal pull-ups/pull-downs connected to CMD and DATA pins. The table below shows the default pull-up and pull-down states of the CMD and DATA pins. + With that said, the information about these internal pull-ups and strapping requirements can still be useful. Espressif hardware products have different weak internal pull-ups and pull-downs connected to CMD and DATA pins. The table below shows the default pull-up and pull-down states of the CMD and DATA pins. The following abbreviations are used in the table: @@ -325,3 +344,17 @@ Related Information - DAT3 - WPU - + +.. only:: not esp32 + + .. _related_info_sdio: + + Related Information + ------------------- + + Internal Pull-ups and Strapping Requirements + ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + + Using external resistors is always preferable. However, Espressif's products have internal weak pull-up and pull-down resistors which can be enabled and used instead of external ones. Please keep in mind that this solution can not guarantee reliable SDIO communication. + + Generally it's not recommended to reuse strapping pins for SDIO purposes. The pullup and pulldown requirements of SD and strapping may conflict with each other. See datasheet for the strapping pins of {IDF_TARGET}. diff --git a/docs/zh_CN/api-reference/peripherals/sd_pullup_requirements.rst b/docs/zh_CN/api-reference/peripherals/sd_pullup_requirements.rst index 4b57be13f5d..16f88d6884e 100644 --- a/docs/zh_CN/api-reference/peripherals/sd_pullup_requirements.rst +++ b/docs/zh_CN/api-reference/peripherals/sd_pullup_requirements.rst @@ -1 +1,360 @@ -.. include:: ../../../en/api-reference/peripherals/sd_pullup_requirements.rst +SD 上拉需求 +=========== + +:link_to_translation:`en:[English]` + +乐鑫硬件产品适用于多种场景，这些场景可能需要不同的管脚上拉状态。因此，要调整某些产品的特定管脚上拉状态，为 SD 总线提供所需的上拉电阻。 + +{IDF_TARGET_NAME} 使用 SPI 或 SDMMC 控制器与 SD 卡通信时，需要满足 SD 卡的上拉需求。当 SD 卡在 SPI 模式或 1 位 SD 模式下运行时，SD 总线的 CMD 和 DATA (DAT0 - DAT3) 线必须通过 10 kΩ 电阻上拉。SD 卡和 SDIO 设备也应在上述所有管脚（无论是否连接到主机）上有上拉电阻，以防设备进入错误状态。 + +.. only:: esp32 + + 默认情况下，如果 flash 电压为 3.3 V，则 MTDI strapping 管脚与 DAT2 线的上拉电阻不兼容。详情请参阅 :ref:`mtdi_strapping_pin`。 + +.. todo:: + + Add a diagram of the bus lines and pullups + +本文档涵盖以下章节内容： + +- :ref:`compatibility_overview_espressif_hw_sdio` - 简要介绍乐鑫产品管脚的默认上拉状态与 SD 总线所需状态之间的兼容性 +- :ref:`sdio_solutions` - 解决兼容性问题的方案 +- :ref:`related_info_sdio` - 其他相关信息 + + +.. _compatibility_overview_espressif_hw_sdio: + +兼容性概述 +---------- + +本节概述了在使用安全数字输入输出 (SDIO) 时可能出现的兼容性问题。SD 总线需要连接上拉电阻，因此要妥善解决与主机设备及从机设备有关的兼容性问题。下面每个问题都有相应解决方案的链接，主机设备和从机设备的解决方案可能有所不同。 + + +.. only:: esp32 + + 片上系统 (SoCs) + ^^^^^^^^^^^^^^^ + + - ESP32（除 D2WD 版本外，请参阅 `ESP32 技术规格书 `_）： + + - :ref:`sd_pull-up_no_pull-ups` + - 带有 3.3 V flash 芯片的模组，请参阅 :ref:`strapping_conflicts_dat2` + + - ESP32-D2WD： + + - :ref:`sd_pull-up_no_pull-ups` + - :ref:`no_pull-up_on_gpio12` + +.. only:: SOC_SDMMC_USE_GPIO_MATRIX + + 片上系统 (SoCs) + ^^^^^^^^^^^^^^^ + + {IDF_TARGET_NAME} SDMMC 主机控制器允许 SD 接口信号使用所有 GPIO。但建议避免使用 strapping GPIO、带内部弱下拉的 GPIO 以及通常用于其他用途的 GPIO，以防出现冲突。 + + .. only:: esp32s3 + + - GPIO0（strapping 管脚） + - GPIO45、GPIO46（strapping 管脚，内部弱下拉） + - GPIO26 - GPIO32（通常用于 SPI flash 和 PSRAM） + - GPIO33 - GPIO37（用于带有八线 SPI flash 或八线 PSRAM 的芯片和模组） + - GPIO43、GPIO44（默认用于 UART0 的 GPIO） + - GPIO19、GPIO20（默认用于 USB 的 GPIO） + + +.. only:: esp32 + + 系统级封装 (SIP) + ^^^^^^^^^^^^^^^^ + + - ESP32-PICO-D4： + + - :ref:`sd_pull-up_no_pull-ups` + - :ref:`strapping_conflicts_dat2` + + + 模组 + ^^^^ + + - ESP32-WROOM-32 系列模组，包括 ESP32-WROOM-32、ESP32-WROOM-32D、ESP32-WROOM-32U 和 ESP32-SOLO-1 + + - :ref:`sd_pull-up_no_pull-ups` + - :ref:`strapping_conflicts_dat2` + + - ESP32-WROVER 系列模组，包括 ESP32-WROVER 和 ESP32-WROVER-I + + - :ref:`sd_pull-up_no_pull-ups` + + - ESP32-WROVER-B 系列模组，包括 ESP32-WROVER-B 和 ESP32-WROVER-IB + + - :ref:`sd_pull-up_no_pull-ups` + - :ref:`strapping_conflicts_dat2` + + +.. only:: esp32 + + .. _sdio_dev_kits: + + 开发板 + ^^^^^^ + + - ESP32-PICO-KIT，包括 PICO-KIT v4.1、v4.0 和 v3 + + - :ref:`sd_pull-up_no_pull-ups` + - :ref:`strapping_conflicts_dat2` + - :ref:`gpio2_strapping_pin` + + - ESP32-DevKitC，包括 ESP32-DevKitC v4 和 v2 + + - :ref:`sd_pull-up_no_pull-ups` + - :ref:`strapping_conflicts_dat2` + - :ref:`gpio2_strapping_pin` + + - ESP-WROVER-KIT + + - 提供所需的上拉电阻 + - :ref:`pull-up_conflicts_on_gpio13` （v4.1、v3、v2 和 v1） + - :ref:`strapping_conflicts_dat2` （v4.1、v2 和 v1） + - :ref:`gpio2_strapping_pin` （v2 和 v1） + + 通过查看安装在开发板上的模组，可以确定所使用的 ESP32-WROVER-KIT 的版本： + + - ESP32-WROVER-B 对应 v4.1 版本 + - ESP32-WROVER 对应 v3 版本 + - ESP32-WROOM-32 对应 v1 和 v2 版本 + + - ESP32-LyraTD-MSC + + - 提供所需的上拉电阻 + - :ref:`strapping_conflicts_dat2` + + - ESP32-LyraT + + - 提供所需的上拉电阻 + - :ref:`pull-up_conflicts_on_gpio13` + +.. only:: esp32s3 + + .. _sdio_dev_kits: + + 开发板 + ^^^^^^ + + - ESP32-S3-DevKitC-1 + + - :ref:`sd_pull-up_no_pull-ups` + + - ESP32-S3-USB-OTG + + - 该开发板可在单线和四线 SD 模式或 SPI 模式下使用。 + - 在 GPIO 33-38 上提供所需的上拉电阻。 + + - ESP32-S3-EYE + + - 该开发板仅限于单线 SD 模式下使用。 + - 在 GPIO 38-40 上提供所需的上拉电阻。 + +.. only:: SOC_SDIO_SLAVE_SUPPORTED + + 非乐鑫主机 + ^^^^^^^^^^ + + 请确保 SDIO 主机为所有 SD 总线信号提供必要的上拉电阻。 + + +.. _sdio_solutions: + +解决方案 +-------- + +.. _sd_pull-up_no_pull-ups: + +无上拉电阻 +^^^^^^^^^^ + +.. only:: esp32 or esp32s3 + + 如果所使用的开发板没有上拉电阻，可以执行以下操作： + + - 如果主机设备和从机设备在不同的开发板上，将其中一块开发板换为带有上拉电阻的开发板。如需了解哪些乐鑫开发板带有上拉电阻，请参阅 :ref:`sdio_dev_kits`。 + - 用一个 10 kΩ 的电阻将每个需要上拉的管脚连接到 VDD，从而附加外部上拉电阻。 + +.. only:: not esp32 and not esp32s3 + + 如果所使用的开发板没有上拉电阻，可以执行以下操作： + + - 如果主机设备和从机设备在不同的开发板上，将其中一块开发板换为带有上拉电阻的开发板。 + - 用一个 10 kΩ 的电阻将每个需要上拉的管脚连接到 VDD，从而附加外部上拉电阻。 + +.. only:: esp32 + + .. _pull-up_conflicts_on_gpio13: + + GPIO13 上拉冲突 + ^^^^^^^^^^^^^^^ + + 如果所用设备的 DAT3 没有正确上拉，可以参考下列操作： + + - 使用 1 位 SD 模式并将设备的 DAT3 连接到 VDD + - 使用 SPI 模式 + - 对 GPIO13 管脚执行以下操作之一： + - 移除下拉电阻 + - 附加小于 5 kΩ 的上拉电阻（建议使用 2 kΩ 的电阻） + - 在 1 位 SD 模式下，通过主机、或是通过 VDD 上的 3.3 V 电压，将管脚拉高或驱动到高电平。 + + + .. _strapping_conflicts_dat2: + + Bootstrap 与 SDIO 在 DAT2 上的冲突 + ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + + ESP32 的启动 strapping 需求与 SDIO 协议之间存在冲突。详情请参阅 :ref:`mtdi_strapping_pin`。 + + 要解决此冲突，可参考以下选项： + + 1.（推荐）烧录选择 flash 电压的 eFuse。该操作会将内部调节器的输出电压永久配置为 3.3 V，并且 GPIO12 将不再用作 strapping 管脚。烧录完成后，将上拉电阻连接到 GPIO12。 + + .. warning:: + + 烧录 eFuse 是不可逆的！上述问题清单可能已经过时，因此请确保要烧录的模组内嵌 3.3 V flash 芯片，可前往 https://www.espressif.com/ 进行确认。如果在带有 1.8 V flash 芯片的模组上烧录 3.3 V eFuse，模组将停止工作。 + + 如果确定要烧录 eFuse，请转到 ESP-IDF 目录下，通过 ``espefuse.py`` 工具运行以下命令： + + .. code-block:: bash + + components/esptool_py/esptool/espefuse.py set_flash_voltage 3.3V + + 此命令将烧录 ``XPD_SDIO_TIEH``、``XPD_SDIO_FORCE`` 和 ``XPD_SDIO_REG`` eFuse。当以上三个 eFuse 被烧录为 1 时，内部 VDD_SDIO flash 电压调节器将被永久设置为 3.3 V。如果烧录成功，将看到以下日志： + + .. code-block:: bash + + espefuse.py v2.6 + Connecting.... + + Enable internal flash voltage regulator (VDD_SDIO) to 3.3 V. + The following eFuses are burned: XPD_SDIO_FORCE, XPD_SDIO_REG, XPD_SDIO_TIEH. + This is an irreversible operation. + Type 'BURN' (all capitals) to continue. + BURN + VDD_SDIO setting complete. + + 要检查 eFuse 的状态，请运行： + + .. code-block:: none + + idf.py efuse-summary + + 如果运行自动烧录脚本，最好使用独立的 eFuse 工具 ``espefuse.py``。此工具还具有 ``--do-not-confirm`` 选项，可在无需确认的情况下烧录 eFuse。 + + 有关烧录 eFuse 的更多信息，请参阅 **{IDF_TARGET_NAME} 技术参考手册** [`PDF <{IDF_TARGET_TRM_CN_URL}#efuse>`__]。 + + 2. **如果使用 1 位 SD 模式或 SPI 模式**，请断开 DAT2 管脚并确保其被拉高。可以采取下列两个选项之一： + + - 使主机的 DAT2 管脚悬空，并将从机设备的 DAT2 直接连接到 VDD。 + - 对于从机设备，构建具有 ``SDIO_SLAVE_FLAG_DAT2_DISABLED`` 选项的固件并重新烧录设备，此选项可避免从机设备检测 DAT2 线。请注意，CCCR 寄存器将不再支持 4 位 SD 模式，但主机并不知晓这一点，因此必须在主机端禁用 4 位 SD 模式。 + + + .. _no_pull-up_on_gpio12: + + GPIO12 无上拉电阻 + ^^^^^^^^^^^^^^^^^ + + 所用模组与 SDIO 协议兼容，只需通过 10 kΩ 电阻将 GPIO12 连接到 VDD 即可。 + + + .. _gpio2_strapping_pin: + + 下载模式不起效（次要问题） + ^^^^^^^^^^^^^^^^^^^^^^^^^^ + + 当 GPIO2 管脚根据 SD 上拉需求被拉高时，将无法进入下载模式，因为 GPIO2 是一个 strapping 管脚，下载模式下必须被拉低。 + + 可参考以下解决方案： + + - 对于需要用跳线短接 GPIO0 和 GPIO2 管脚的开发板，跳线连接完成后，自动复位电路会在进入下载模式前将 GPIO2 与 GPIO0 一起拉低。 + - 对于 GPIO2 管脚上连有组件（例如下拉电阻和/或 LED）的开发板，请查看开发板的原理图，确认连接到 GPIO2 上组件的具体情况。 + + - **LED** 大多数情况下不会影响操作。 + - **下拉电阻** 可能会干扰 DAT0 信号，必须移除。 + + 如果上述解决方案无效，请检查主机或从机设备是否带有会影响 GPIO2 的上拉电阻，如有，将其移除。 + + +.. only:: esp32 + + .. _related_info_sdio: + + 相关信息 + -------- + + .. _mtdi_strapping_pin: + + MTDI strapping 管脚 + ^^^^^^^^^^^^^^^^^^^ + + MTDI (GPIO12) 为 strapping 管脚，用于选择内部调节器 (VDD_SDIO) 的输出电压，为 flash 芯片供电。该管脚带有内部下拉电阻，因此若处于未连接状态，MTDI 管脚将在启动时读取低电平，选择默认的 3.3 V 操作。 + + 除 ESP32-WROVER-B 外的所有 ESP32-WROVER 模组都使用 1.8 V flash，并在 GPIO12 上有内部上拉电阻。使用 3.3 V flash 的其他模组在 GPIO12 管脚上没有上拉电阻，并在芯片内部 GPIO12 管脚默认使能弱下拉。 + + 为 GPIO12 添加上拉电阻以进行 SD 卡操作时，请考虑以下事项： + + - 在不使用内部调节器 (VDD_SDIO) 为 flash 供电的开发板上，GPIO12 可以被拉高。 + - 在使用 1.8 V flash 芯片的开发板上，复位时 GPIO12 需要被拉高，这与 SD 卡操作完全兼容。 + - 在使用内部调节器和 3.3 V flash 芯片的开发板上，复位时 GPIO12 必须被拉低，这与 SD 卡操作不兼容。有关乐鑫开发板与 SD 卡操作之间的兼容性问题，详情请参阅 :ref:`compatibility_overview_espressif_hw_sdio`。 + + + 内部上拉和 strapping 需求 + ^^^^^^^^^^^^^^^^^^^^^^^^^ + + 使用外部电阻始终是更优选择。乐鑫产品中的内部弱上拉和下拉电阻启用后可以代替外部电阻，但此解决方案并不能保证可靠的 SDIO 通信。 + + 话虽如此，有关内部上拉和 strapping 需求的信息仍有一些参考价值。乐鑫硬件产品不同管脚（CMD 和 DATA 等）的内部弱上拉和弱下拉电阻的默认连接情况不同。下表展示了 CMD 和 DATA 管脚的默认上拉和下拉状态。 + + 表中使用了以下缩写： + + - **WPU**：SoC 内部的弱上拉电阻 + - **WPD**：SoC 内部的弱下拉电阻 + - **PU**：位于乐鑫模组内部、SoC 外部的上拉电阻 + + .. list-table:: CMD 和 DATA 管脚的默认上拉和下拉状态 + :widths: 25 25 25 25 + :header-rows: 1 + + * - GPIO 编号 + - 管脚名 + - 启动状态 + - strapping 需求 + * - **15** + - CMD + - WPU + - + * - **2** + - DAT0 + - WPD + - 下载模式要求低电平 + * - **4** + - DAT1 + - WPD + - + * - **12** + - DAT2 + - 使用 1.8 V flash 时为 PU；3.3 V flash 时为 WPD + - 使用 1.8 V flash 时要求高电平；3.3 V flash 时要求低电平 + * - **13** + - DAT3 + - WPU + - + +.. only:: not esp32 + + .. _related_info_sdio: + + 相关信息 + -------- + + 内部上拉和 strapping 需求 + ^^^^^^^^^^^^^^^^^^^^^^^^^ + + 使用外部电阻始终是更优选择。乐鑫产品中的内部弱上拉和下拉电阻启用后可以代替外部电阻，但此解决方案并不能保证可靠的 SDIO 通信。 + + 通常不建议将 strapping 管脚重复用于 SDIO 功能。SD 和 strapping 管脚的上拉、下拉需求可能会相互冲突。有关 {IDF_TARGET} strapping 管脚的详细信息，请参阅技术规格书。 From 0722aa82092a2de3a1226569441aa8ea9dacd312 Mon Sep 17 00:00:00 2001 From: morris Date: Tue, 24 Sep 2024 18:42:00 +0800 Subject: [PATCH 084/472] feat(etm): support sleep retention --- components/esp_hw_support/esp_etm.c | 70 +++++++++++++++++-- components/esp_hw_support/include/esp_etm.h | 8 ++- components/soc/CMakeLists.txt | 4 ++ components/soc/esp32c5/etm_periph.c | 44 ++++++++++++ .../esp32c5/include/soc/Kconfig.soc_caps.in | 4 ++ .../include/soc/retention_periph_defs.h | 3 + components/soc/esp32c5/include/soc/soc_caps.h | 1 + components/soc/esp32c6/etm_periph.c | 44 ++++++++++++ .../esp32c6/include/soc/Kconfig.soc_caps.in | 4 ++ .../include/soc/retention_periph_defs.h | 3 + components/soc/esp32c6/include/soc/soc_caps.h | 1 + components/soc/esp32c61/etm_periph.c | 44 ++++++++++++ .../include/soc/retention_periph_defs.h | 3 + .../soc/esp32c61/include/soc/soc_caps.h | 1 + components/soc/esp32h2/etm_periph.c | 44 ++++++++++++ .../esp32h2/include/soc/Kconfig.soc_caps.in | 4 ++ .../include/soc/retention_periph_defs.h | 3 + components/soc/esp32h2/include/soc/soc_caps.h | 1 + components/soc/esp32p4/etm_periph.c | 44 ++++++++++++ .../esp32p4/include/soc/Kconfig.soc_caps.in | 4 ++ .../include/soc/retention_periph_defs.h | 9 ++- components/soc/esp32p4/include/soc/soc_caps.h | 1 + components/soc/include/soc/etm_periph.h | 32 +++++++++ components/soc/include/soc/regdma.h | 2 + docs/en/api-reference/peripherals/etm.rst | 12 ++++ .../api-reference/system/power_management.rst | 4 +- docs/zh_CN/api-reference/peripherals/etm.rst | 12 ++++ .../api-reference/system/power_management.rst | 4 +- 28 files changed, 397 insertions(+), 13 deletions(-) create mode 100644 components/soc/esp32c5/etm_periph.c create mode 100644 components/soc/esp32c6/etm_periph.c create mode 100644 components/soc/esp32c61/etm_periph.c create mode 100644 components/soc/esp32h2/etm_periph.c create mode 100644 components/soc/esp32p4/etm_periph.c create mode 100644 components/soc/include/soc/etm_periph.h diff --git a/components/esp_hw_support/esp_etm.c b/components/esp_hw_support/esp_etm.c index 9dfbfc6cb40..b8ae6349b7c 100644 --- a/components/esp_hw_support/esp_etm.c +++ b/components/esp_hw_support/esp_etm.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -16,7 +16,7 @@ #include "freertos/FreeRTOS.h" #include "freertos/task.h" #include "soc/soc_caps.h" -#include "soc/periph_defs.h" +#include "soc/etm_periph.h" #include "esp_log.h" #include "esp_check.h" #include "esp_heap_caps.h" @@ -25,10 +25,13 @@ #include "hal/etm_ll.h" #include "esp_private/periph_ctrl.h" #include "esp_private/etm_interface.h" +#include "esp_private/sleep_retention.h" #define ETM_MEM_ALLOC_CAPS MALLOC_CAP_DEFAULT -#if CONFIG_IDF_TARGET_ESP32P4 +#define ETM_USE_RETENTION_LINK (SOC_ETM_SUPPORT_SLEEP_RETENTION && CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP) + +#if !SOC_RCC_IS_INDEPENDENT // Reset and Clock Control registers are mixing with other peripherals, so we need to use a critical section #define ETM_RCC_ATOMIC() PERIPH_RCC_ATOMIC() #else @@ -70,6 +73,32 @@ struct esp_etm_channel_t { // ETM driver platform, it's always a singleton static etm_platform_t s_platform; +#if ETM_USE_RETENTION_LINK +static esp_err_t etm_create_sleep_retention_link_cb(void *arg) +{ + etm_group_t *group = (etm_group_t *)arg; + int group_id = group->group_id; + esp_err_t err = sleep_retention_entries_create(etm_reg_retention_info[group_id].regdma_entry_array, + etm_reg_retention_info[group_id].array_size, + REGDMA_LINK_PRI_ETM, etm_reg_retention_info[group_id].module); + return err; +} + +static void etm_create_retention_module(etm_group_t *group) +{ + int group_id = group->group_id; + sleep_retention_module_t module = etm_reg_retention_info[group_id].module; + _lock_acquire(&s_platform.mutex); + if ((sleep_retention_get_inited_modules() & BIT(module)) && !(sleep_retention_get_created_modules() & BIT(module))) { + if (sleep_retention_module_allocate(module) != ESP_OK) { + // even though the sleep retention module create failed, ETM driver should still work, so just warning here + ESP_LOGW(TAG, "create retention link failed %d, power domain won't be turned off during sleep", group_id); + } + } + _lock_release(&s_platform.mutex); +} +#endif // ETM_USE_RETENTION_LINK + static etm_group_t *etm_acquire_group_handle(int group_id) { bool new_group = false; @@ -90,7 +119,22 @@ static etm_group_t *etm_acquire_group_handle(int group_id) etm_ll_enable_bus_clock(group_id, true); etm_ll_reset_register(group_id); } - +#if ETM_USE_RETENTION_LINK + sleep_retention_module_t module = etm_reg_retention_info[group_id].module; + sleep_retention_module_init_param_t init_param = { + .cbs = { + .create = { + .handle = etm_create_sleep_retention_link_cb, + .arg = group, + }, + }, + .depends = BIT(SLEEP_RETENTION_MODULE_CLOCK_SYSTEM) + }; + if (sleep_retention_module_init(module, &init_param) != ESP_OK) { + // even though the sleep retention module init failed, ETM driver may still work, so just warning here + ESP_LOGW(TAG, "init sleep retention failed %d, power domain may be turned off during sleep", group_id); + } +#endif // ETM_USE_RETENTION_LINK // initialize HAL context etm_hal_init(&group->hal); } @@ -129,6 +173,15 @@ static void etm_release_group_handle(etm_group_t *group) _lock_release(&s_platform.mutex); if (do_deinitialize) { +#if ETM_USE_RETENTION_LINK + sleep_retention_module_t module = etm_reg_retention_info[group_id].module; + if (sleep_retention_get_created_modules() & BIT(module)) { + sleep_retention_module_free(module); + } + if (sleep_retention_get_inited_modules() & BIT(module)) { + sleep_retention_module_deinit(module); + } +#endif free(group); ESP_LOGD(TAG, "del group (%d)", group_id); } @@ -192,6 +245,9 @@ esp_err_t esp_etm_new_channel(const esp_etm_channel_config_t *config, esp_etm_ch esp_err_t ret = ESP_OK; esp_etm_channel_t *chan = NULL; ESP_GOTO_ON_FALSE(config && ret_chan, ESP_ERR_INVALID_ARG, err, TAG, "invalid args"); +#if !SOC_ETM_SUPPORT_SLEEP_RETENTION + ESP_RETURN_ON_FALSE(config->flags.allow_pd == 0, ESP_ERR_NOT_SUPPORTED, TAG, "not able to power down in light sleep"); +#endif // SOC_ETM_SUPPORT_SLEEP_RETENTION chan = heap_caps_calloc(1, sizeof(esp_etm_channel_t), ETM_MEM_ALLOC_CAPS); ESP_GOTO_ON_FALSE(chan, ESP_ERR_NO_MEM, err, TAG, "no mem for channel"); @@ -201,6 +257,12 @@ esp_err_t esp_etm_new_channel(const esp_etm_channel_config_t *config, esp_etm_ch int group_id = group->group_id; int chan_id = chan->chan_id; +#if ETM_USE_RETENTION_LINK + if (config->flags.allow_pd != 0) { + etm_create_retention_module(group); + } +#endif // ETM_USE_RETENTION_LINK + chan->fsm = ETM_CHAN_FSM_INIT; ESP_LOGD(TAG, "new etm channel (%d,%d) at %p", group_id, chan_id, chan); *ret_chan = chan; diff --git a/components/esp_hw_support/include/esp_etm.h b/components/esp_hw_support/include/esp_etm.h index c0757abf8ab..daa97d76c32 100644 --- a/components/esp_hw_support/include/esp_etm.h +++ b/components/esp_hw_support/include/esp_etm.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -32,7 +32,11 @@ typedef struct esp_etm_task_t *esp_etm_task_handle_t; * @brief ETM channel configuration */ typedef struct { - + /// Extra configuration flags for ETM channel + struct etm_chan_flags { + uint32_t allow_pd : 1; /*!< If set, driver allows the power domain to be powered off when system enters sleep mode. + This can save power, but at the expense of more RAM being consumed to save register context. */ + } flags; /*!< ETM channel flags */ } esp_etm_channel_config_t; /** diff --git a/components/soc/CMakeLists.txt b/components/soc/CMakeLists.txt index 765cde298b7..59822b467f3 100644 --- a/components/soc/CMakeLists.txt +++ b/components/soc/CMakeLists.txt @@ -47,6 +47,10 @@ if(CONFIG_SOC_EMAC_SUPPORTED) list(APPEND srcs "${target_folder}/emac_periph.c") endif() +if(CONFIG_SOC_ETM_SUPPORTED) + list(APPEND srcs "${target_folder}/etm_periph.c") +endif() + if(CONFIG_SOC_GDMA_SUPPORTED) list(APPEND srcs "${target_folder}/gdma_periph.c") endif() diff --git a/components/soc/esp32c5/etm_periph.c b/components/soc/esp32c5/etm_periph.c new file mode 100644 index 00000000000..7b268c443a5 --- /dev/null +++ b/components/soc/esp32c5/etm_periph.c @@ -0,0 +1,44 @@ +/* + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/etm_periph.h" +#include "soc/soc_etm_reg.h" + +/** + * ETM Registers to be saved during sleep retention + * - Channel configuration registers, e.g.: SOC_ETM_CH0_EVT_ID_REG, SOC_ETM_CH0_TASK_ID_REG +*/ +#define ETM_RETENTION_REGS_CNT ((SOC_ETM_CH49_TASK_ID_REG - SOC_ETM_CH0_EVT_ID_REG) / 4 + 1) + +static const regdma_entries_config_t etm_regdma_entries[] = { + // backup stage: save the status of enabled channels + // restore stage: store the enabled channels + [0] = { + .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_ETM_LINK(0x00), + SOC_ETM_CH_ENA_AD0_REG, SOC_ETM_CH_ENA_AD0_SET_REG, 1, 0, 0), + .owner = ENTRY(0) | ENTRY(2), + }, + [1] = { + .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_ETM_LINK(0x01), + SOC_ETM_CH_ENA_AD1_REG, SOC_ETM_CH_ENA_AD1_SET_REG, 1, 0, 0), + .owner = ENTRY(0) | ENTRY(2), + }, + // backup stage: save configuration registers + // restore stage: restore the configuration registers + [2] = { + .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_ETM_LINK(0x02), + SOC_ETM_CH0_EVT_ID_REG, SOC_ETM_CH0_EVT_ID_REG, ETM_RETENTION_REGS_CNT, 0, 0), + .owner = ENTRY(0) | ENTRY(2), + }, +}; + +const etm_reg_retention_info_t etm_reg_retention_info[SOC_ETM_GROUPS] = { + [0] = { + .module = SLEEP_RETENTION_MODULE_ETM0, + .regdma_entry_array = etm_regdma_entries, + .array_size = ARRAY_SIZE(etm_regdma_entries) + }, +}; diff --git a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in index 23a96312324..3ca17508c5d 100644 --- a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in @@ -463,6 +463,10 @@ config SOC_ETM_CHANNELS_PER_GROUP int default 50 +config SOC_ETM_SUPPORT_SLEEP_RETENTION + bool + default y + config SOC_GPIO_PORT int default 1 diff --git a/components/soc/esp32c5/include/soc/retention_periph_defs.h b/components/soc/esp32c5/include/soc/retention_periph_defs.h index 02002a7d0fe..b21f1d3edea 100644 --- a/components/soc/esp32c5/include/soc/retention_periph_defs.h +++ b/components/soc/esp32c5/include/soc/retention_periph_defs.h @@ -37,6 +37,7 @@ typedef enum periph_retention_module { SLEEP_RETENTION_MODULE_UART0 = 14, SLEEP_RETENTION_MODULE_UART1 = 15, SLEEP_RETENTION_MODULE_I2S0 = 16, + SLEEP_RETENTION_MODULE_ETM0 = 17, /* modem module, which includes WiFi, BLE and 802.15.4 */ SLEEP_RETENTION_MODULE_WIFI_MAC = 26, @@ -76,6 +77,7 @@ typedef enum periph_retention_module_bitmap { SLEEP_RETENTION_MODULE_BM_UART0 = BIT(SLEEP_RETENTION_MODULE_UART0), SLEEP_RETENTION_MODULE_BM_UART1 = BIT(SLEEP_RETENTION_MODULE_UART1), SLEEP_RETENTION_MODULE_BM_I2S0 = BIT(SLEEP_RETENTION_MODULE_I2S0), + SLEEP_RETENTION_MODULE_BM_ETM0 = BIT(SLEEP_RETENTION_MODULE_ETM0), SLEEP_RETENTION_MODULE_BM_GDMA_CH0 = BIT(SLEEP_RETENTION_MODULE_GDMA_CH0), SLEEP_RETENTION_MODULE_BM_GDMA_CH1 = BIT(SLEEP_RETENTION_MODULE_GDMA_CH1), @@ -97,6 +99,7 @@ typedef enum periph_retention_module_bitmap { | SLEEP_RETENTION_MODULE_BM_UART0 \ | SLEEP_RETENTION_MODULE_BM_UART1 \ | SLEEP_RETENTION_MODULE_BM_I2S0 \ + | SLEEP_RETENTION_MODULE_BM_ETM0 \ ) #ifdef __cplusplus } diff --git a/components/soc/esp32c5/include/soc/soc_caps.h b/components/soc/esp32c5/include/soc/soc_caps.h index c8f1619ce98..b98bce60b93 100644 --- a/components/soc/esp32c5/include/soc/soc_caps.h +++ b/components/soc/esp32c5/include/soc/soc_caps.h @@ -191,6 +191,7 @@ /*-------------------------- ETM CAPS --------------------------------------*/ #define SOC_ETM_GROUPS 1U // Number of ETM groups #define SOC_ETM_CHANNELS_PER_GROUP 50 // Number of ETM channels in the group +#define SOC_ETM_SUPPORT_SLEEP_RETENTION 1 // Support sleep retention /*-------------------------- GPIO CAPS ---------------------------------------*/ // ESP32-C5 has 1 GPIO peripheral diff --git a/components/soc/esp32c6/etm_periph.c b/components/soc/esp32c6/etm_periph.c new file mode 100644 index 00000000000..7b268c443a5 --- /dev/null +++ b/components/soc/esp32c6/etm_periph.c @@ -0,0 +1,44 @@ +/* + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/etm_periph.h" +#include "soc/soc_etm_reg.h" + +/** + * ETM Registers to be saved during sleep retention + * - Channel configuration registers, e.g.: SOC_ETM_CH0_EVT_ID_REG, SOC_ETM_CH0_TASK_ID_REG +*/ +#define ETM_RETENTION_REGS_CNT ((SOC_ETM_CH49_TASK_ID_REG - SOC_ETM_CH0_EVT_ID_REG) / 4 + 1) + +static const regdma_entries_config_t etm_regdma_entries[] = { + // backup stage: save the status of enabled channels + // restore stage: store the enabled channels + [0] = { + .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_ETM_LINK(0x00), + SOC_ETM_CH_ENA_AD0_REG, SOC_ETM_CH_ENA_AD0_SET_REG, 1, 0, 0), + .owner = ENTRY(0) | ENTRY(2), + }, + [1] = { + .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_ETM_LINK(0x01), + SOC_ETM_CH_ENA_AD1_REG, SOC_ETM_CH_ENA_AD1_SET_REG, 1, 0, 0), + .owner = ENTRY(0) | ENTRY(2), + }, + // backup stage: save configuration registers + // restore stage: restore the configuration registers + [2] = { + .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_ETM_LINK(0x02), + SOC_ETM_CH0_EVT_ID_REG, SOC_ETM_CH0_EVT_ID_REG, ETM_RETENTION_REGS_CNT, 0, 0), + .owner = ENTRY(0) | ENTRY(2), + }, +}; + +const etm_reg_retention_info_t etm_reg_retention_info[SOC_ETM_GROUPS] = { + [0] = { + .module = SLEEP_RETENTION_MODULE_ETM0, + .regdma_entry_array = etm_regdma_entries, + .array_size = ARRAY_SIZE(etm_regdma_entries) + }, +}; diff --git a/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in index b0720119429..396d8ff0e07 100644 --- a/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in @@ -459,6 +459,10 @@ config SOC_ETM_CHANNELS_PER_GROUP int default 50 +config SOC_ETM_SUPPORT_SLEEP_RETENTION + bool + default y + config SOC_GPIO_PORT int default 1 diff --git a/components/soc/esp32c6/include/soc/retention_periph_defs.h b/components/soc/esp32c6/include/soc/retention_periph_defs.h index 5cdbc108e81..5bba74ce353 100644 --- a/components/soc/esp32c6/include/soc/retention_periph_defs.h +++ b/components/soc/esp32c6/include/soc/retention_periph_defs.h @@ -37,6 +37,7 @@ typedef enum periph_retention_module { SLEEP_RETENTION_MODULE_UART0 = 14, SLEEP_RETENTION_MODULE_UART1 = 15, SLEEP_RETENTION_MODULE_I2S0 = 16, + SLEEP_RETENTION_MODULE_ETM0 = 17, /* Modem module, which includes WiFi, BLE and 802.15.4 */ SLEEP_RETENTION_MODULE_WIFI_MAC = 26, @@ -70,6 +71,7 @@ typedef enum periph_retention_module_bitmap { SLEEP_RETENTION_MODULE_BM_UART0 = BIT(SLEEP_RETENTION_MODULE_UART0), SLEEP_RETENTION_MODULE_BM_UART1 = BIT(SLEEP_RETENTION_MODULE_UART1), SLEEP_RETENTION_MODULE_BM_I2S0 = BIT(SLEEP_RETENTION_MODULE_I2S0), + SLEEP_RETENTION_MODULE_BM_ETM0 = BIT(SLEEP_RETENTION_MODULE_ETM0), /* modem module, which includes WiFi, BLE and 802.15.4 */ SLEEP_RETENTION_MODULE_BM_WIFI_MAC = BIT(SLEEP_RETENTION_MODULE_WIFI_MAC), SLEEP_RETENTION_MODULE_BM_WIFI_BB = BIT(SLEEP_RETENTION_MODULE_WIFI_BB), @@ -93,6 +95,7 @@ typedef enum periph_retention_module_bitmap { | SLEEP_RETENTION_MODULE_BM_UART0 \ | SLEEP_RETENTION_MODULE_BM_UART1 \ | SLEEP_RETENTION_MODULE_BM_I2S0 \ + | SLEEP_RETENTION_MODULE_BM_ETM0 \ ) #ifdef __cplusplus diff --git a/components/soc/esp32c6/include/soc/soc_caps.h b/components/soc/esp32c6/include/soc/soc_caps.h index e887e685614..70835692ee8 100644 --- a/components/soc/esp32c6/include/soc/soc_caps.h +++ b/components/soc/esp32c6/include/soc/soc_caps.h @@ -178,6 +178,7 @@ /*-------------------------- ETM CAPS --------------------------------------*/ #define SOC_ETM_GROUPS 1U // Number of ETM groups #define SOC_ETM_CHANNELS_PER_GROUP 50 // Number of ETM channels in the group +#define SOC_ETM_SUPPORT_SLEEP_RETENTION 1 // Support sleep retention /*-------------------------- GPIO CAPS ---------------------------------------*/ // ESP32-C6 has 1 GPIO peripheral diff --git a/components/soc/esp32c61/etm_periph.c b/components/soc/esp32c61/etm_periph.c new file mode 100644 index 00000000000..7b268c443a5 --- /dev/null +++ b/components/soc/esp32c61/etm_periph.c @@ -0,0 +1,44 @@ +/* + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/etm_periph.h" +#include "soc/soc_etm_reg.h" + +/** + * ETM Registers to be saved during sleep retention + * - Channel configuration registers, e.g.: SOC_ETM_CH0_EVT_ID_REG, SOC_ETM_CH0_TASK_ID_REG +*/ +#define ETM_RETENTION_REGS_CNT ((SOC_ETM_CH49_TASK_ID_REG - SOC_ETM_CH0_EVT_ID_REG) / 4 + 1) + +static const regdma_entries_config_t etm_regdma_entries[] = { + // backup stage: save the status of enabled channels + // restore stage: store the enabled channels + [0] = { + .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_ETM_LINK(0x00), + SOC_ETM_CH_ENA_AD0_REG, SOC_ETM_CH_ENA_AD0_SET_REG, 1, 0, 0), + .owner = ENTRY(0) | ENTRY(2), + }, + [1] = { + .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_ETM_LINK(0x01), + SOC_ETM_CH_ENA_AD1_REG, SOC_ETM_CH_ENA_AD1_SET_REG, 1, 0, 0), + .owner = ENTRY(0) | ENTRY(2), + }, + // backup stage: save configuration registers + // restore stage: restore the configuration registers + [2] = { + .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_ETM_LINK(0x02), + SOC_ETM_CH0_EVT_ID_REG, SOC_ETM_CH0_EVT_ID_REG, ETM_RETENTION_REGS_CNT, 0, 0), + .owner = ENTRY(0) | ENTRY(2), + }, +}; + +const etm_reg_retention_info_t etm_reg_retention_info[SOC_ETM_GROUPS] = { + [0] = { + .module = SLEEP_RETENTION_MODULE_ETM0, + .regdma_entry_array = etm_regdma_entries, + .array_size = ARRAY_SIZE(etm_regdma_entries) + }, +}; diff --git a/components/soc/esp32c61/include/soc/retention_periph_defs.h b/components/soc/esp32c61/include/soc/retention_periph_defs.h index 5bc404860b7..6883ac14522 100644 --- a/components/soc/esp32c61/include/soc/retention_periph_defs.h +++ b/components/soc/esp32c61/include/soc/retention_periph_defs.h @@ -33,6 +33,7 @@ typedef enum periph_retention_module { SLEEP_RETENTION_MODULE_I2C0 = 12, SLEEP_RETENTION_MODULE_UART0 = 14, SLEEP_RETENTION_MODULE_UART1 = 15, + SLEEP_RETENTION_MODULE_ETM0 = 16, /* Modem module, which includes WiFi, BLE and 802.15.4 */ SLEEP_RETENTION_MODULE_WIFI_MAC = 26, @@ -62,6 +63,7 @@ typedef enum periph_retention_module_bitmap { SLEEP_RETENTION_MODULE_BM_I2C0 = BIT(SLEEP_RETENTION_MODULE_I2C0), SLEEP_RETENTION_MODULE_BM_UART0 = BIT(SLEEP_RETENTION_MODULE_UART0), SLEEP_RETENTION_MODULE_BM_UART1 = BIT(SLEEP_RETENTION_MODULE_UART1), + SLEEP_RETENTION_MODULE_BM_ETM0 = BIT(SLEEP_RETENTION_MODULE_ETM0), /* modem module, which includes WiFi, BLE and 802.15.4 */ SLEEP_RETENTION_MODULE_BM_WIFI_MAC = BIT(SLEEP_RETENTION_MODULE_WIFI_MAC), SLEEP_RETENTION_MODULE_BM_WIFI_BB = BIT(SLEEP_RETENTION_MODULE_WIFI_BB), @@ -81,6 +83,7 @@ typedef enum periph_retention_module_bitmap { | SLEEP_RETENTION_MODULE_BM_I2C0 \ | SLEEP_RETENTION_MODULE_BM_UART0 \ | SLEEP_RETENTION_MODULE_BM_UART1 \ + | SLEEP_RETENTION_MODULE_BM_ETM0 \ ) #ifdef __cplusplus diff --git a/components/soc/esp32c61/include/soc/soc_caps.h b/components/soc/esp32c61/include/soc/soc_caps.h index 34a34bdb91d..5e70aafba19 100644 --- a/components/soc/esp32c61/include/soc/soc_caps.h +++ b/components/soc/esp32c61/include/soc/soc_caps.h @@ -154,6 +154,7 @@ /*-------------------------- ETM CAPS --------------------------------------*/ #define SOC_ETM_GROUPS 1U // Number of ETM groups #define SOC_ETM_CHANNELS_PER_GROUP 50 // Number of ETM channels in the group +// #define SOC_ETM_SUPPORT_SLEEP_RETENTION 1 // Support sleep retention /*-------------------------- GPIO CAPS ---------------------------------------*/ // ESP32-C61 has 1 GPIO peripheral diff --git a/components/soc/esp32h2/etm_periph.c b/components/soc/esp32h2/etm_periph.c new file mode 100644 index 00000000000..7b268c443a5 --- /dev/null +++ b/components/soc/esp32h2/etm_periph.c @@ -0,0 +1,44 @@ +/* + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/etm_periph.h" +#include "soc/soc_etm_reg.h" + +/** + * ETM Registers to be saved during sleep retention + * - Channel configuration registers, e.g.: SOC_ETM_CH0_EVT_ID_REG, SOC_ETM_CH0_TASK_ID_REG +*/ +#define ETM_RETENTION_REGS_CNT ((SOC_ETM_CH49_TASK_ID_REG - SOC_ETM_CH0_EVT_ID_REG) / 4 + 1) + +static const regdma_entries_config_t etm_regdma_entries[] = { + // backup stage: save the status of enabled channels + // restore stage: store the enabled channels + [0] = { + .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_ETM_LINK(0x00), + SOC_ETM_CH_ENA_AD0_REG, SOC_ETM_CH_ENA_AD0_SET_REG, 1, 0, 0), + .owner = ENTRY(0) | ENTRY(2), + }, + [1] = { + .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_ETM_LINK(0x01), + SOC_ETM_CH_ENA_AD1_REG, SOC_ETM_CH_ENA_AD1_SET_REG, 1, 0, 0), + .owner = ENTRY(0) | ENTRY(2), + }, + // backup stage: save configuration registers + // restore stage: restore the configuration registers + [2] = { + .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_ETM_LINK(0x02), + SOC_ETM_CH0_EVT_ID_REG, SOC_ETM_CH0_EVT_ID_REG, ETM_RETENTION_REGS_CNT, 0, 0), + .owner = ENTRY(0) | ENTRY(2), + }, +}; + +const etm_reg_retention_info_t etm_reg_retention_info[SOC_ETM_GROUPS] = { + [0] = { + .module = SLEEP_RETENTION_MODULE_ETM0, + .regdma_entry_array = etm_regdma_entries, + .array_size = ARRAY_SIZE(etm_regdma_entries) + }, +}; diff --git a/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in b/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in index 0a59f3a8d66..1330fbf2332 100644 --- a/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in @@ -467,6 +467,10 @@ config SOC_ETM_CHANNELS_PER_GROUP int default 50 +config SOC_ETM_SUPPORT_SLEEP_RETENTION + bool + default y + config SOC_GPIO_PORT int default 1 diff --git a/components/soc/esp32h2/include/soc/retention_periph_defs.h b/components/soc/esp32h2/include/soc/retention_periph_defs.h index 819af3a2b35..372e43e981c 100644 --- a/components/soc/esp32h2/include/soc/retention_periph_defs.h +++ b/components/soc/esp32h2/include/soc/retention_periph_defs.h @@ -38,6 +38,7 @@ typedef enum periph_retention_module { SLEEP_RETENTION_MODULE_UART0 = 15, SLEEP_RETENTION_MODULE_UART1 = 16, SLEEP_RETENTION_MODULE_I2S0 = 17, + SLEEP_RETENTION_MODULE_ETM0 = 18, /* Modem module, which includes BLE and 802.15.4 */ SLEEP_RETENTION_MODULE_BLE_MAC = 28, @@ -70,6 +71,7 @@ typedef enum periph_retention_module_bitmap { SLEEP_RETENTION_MODULE_BM_UART0 = BIT(SLEEP_RETENTION_MODULE_UART0), SLEEP_RETENTION_MODULE_BM_UART1 = BIT(SLEEP_RETENTION_MODULE_UART1), SLEEP_RETENTION_MODULE_BM_I2S0 = BIT(SLEEP_RETENTION_MODULE_I2S0), + SLEEP_RETENTION_MODULE_BM_ETM0 = BIT(SLEEP_RETENTION_MODULE_ETM0), /* modem module, which includes BLE and 802.15.4 */ SLEEP_RETENTION_MODULE_BM_BLE_MAC = BIT(SLEEP_RETENTION_MODULE_BLE_MAC), SLEEP_RETENTION_MODULE_BM_BT_BB = BIT(SLEEP_RETENTION_MODULE_BT_BB), @@ -92,6 +94,7 @@ typedef enum periph_retention_module_bitmap { | SLEEP_RETENTION_MODULE_BM_UART0 \ | SLEEP_RETENTION_MODULE_BM_UART1 \ | SLEEP_RETENTION_MODULE_BM_I2S0 \ + | SLEEP_RETENTION_MODULE_BM_ETM0 \ ) #ifdef __cplusplus diff --git a/components/soc/esp32h2/include/soc/soc_caps.h b/components/soc/esp32h2/include/soc/soc_caps.h index 2f28d6c6a62..26110b48eba 100644 --- a/components/soc/esp32h2/include/soc/soc_caps.h +++ b/components/soc/esp32h2/include/soc/soc_caps.h @@ -181,6 +181,7 @@ /*-------------------------- ETM CAPS --------------------------------------*/ #define SOC_ETM_GROUPS 1U // Number of ETM groups #define SOC_ETM_CHANNELS_PER_GROUP 50 // Number of ETM channels in the group +#define SOC_ETM_SUPPORT_SLEEP_RETENTION 1 // Support sleep retention /*-------------------------- GPIO CAPS ---------------------------------------*/ // ESP32-H2 has 1 GPIO peripheral diff --git a/components/soc/esp32p4/etm_periph.c b/components/soc/esp32p4/etm_periph.c new file mode 100644 index 00000000000..f7b28b02bf7 --- /dev/null +++ b/components/soc/esp32p4/etm_periph.c @@ -0,0 +1,44 @@ +/* + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/etm_periph.h" +#include "soc/soc_etm_reg.h" + +/** + * ETM Registers to be saved during sleep retention + * - Channel configuration registers, e.g.: SOC_ETM_CH0_EVT_ID_REG, SOC_ETM_CH0_TASK_ID_REG +*/ +#define ETM_RETENTION_REGS_CNT ((SOC_ETM_CH49_TASK_ID_REG - SOC_ETM_CH0_EVT_ID_REG) / 4 + 1) + +static const regdma_entries_config_t etm_regdma_entries[] = { + // backup stage: save the status of enabled channels + // restore stage: store the enabled channels + [0] = { + .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_ETM_LINK(0x00), + SOC_ETM_CH_ENA_AD0_REG, SOC_ETM_CH_ENA_AD0_SET_REG, 1, 0, 0), + .owner = ENTRY(0), + }, + [1] = { + .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_ETM_LINK(0x01), + SOC_ETM_CH_ENA_AD1_REG, SOC_ETM_CH_ENA_AD1_SET_REG, 1, 0, 0), + .owner = ENTRY(0), + }, + // backup stage: save configuration registers + // restore stage: restore the configuration registers + [2] = { + .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_ETM_LINK(0x02), + SOC_ETM_CH0_EVT_ID_REG, SOC_ETM_CH0_EVT_ID_REG, ETM_RETENTION_REGS_CNT, 0, 0), + .owner = ENTRY(0), + }, +}; + +const etm_reg_retention_info_t etm_reg_retention_info[SOC_ETM_GROUPS] = { + [0] = { + .module = SLEEP_RETENTION_MODULE_ETM0, + .regdma_entry_array = etm_regdma_entries, + .array_size = ARRAY_SIZE(etm_regdma_entries) + }, +}; diff --git a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in index cefa4d0350f..f8319e722ee 100644 --- a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in @@ -595,6 +595,10 @@ config SOC_ETM_CHANNELS_PER_GROUP int default 50 +config SOC_ETM_SUPPORT_SLEEP_RETENTION + bool + default y + config SOC_GPIO_PORT int default 1 diff --git a/components/soc/esp32p4/include/soc/retention_periph_defs.h b/components/soc/esp32p4/include/soc/retention_periph_defs.h index 48cf71404c6..ab603ed24a8 100644 --- a/components/soc/esp32p4/include/soc/retention_periph_defs.h +++ b/components/soc/esp32p4/include/soc/retention_periph_defs.h @@ -46,6 +46,7 @@ typedef enum periph_retention_module { SLEEP_RETENTION_MODULE_I2S2 = 21, SLEEP_RETENTION_MODULE_I2C0 = 22, SLEEP_RETENTION_MODULE_I2C1 = 23, + SLEEP_RETENTION_MODULE_ETM0 = 24, SLEEP_RETENTION_MODULE_MAX = 31 } periph_retention_module_t; @@ -79,6 +80,7 @@ typedef enum periph_retention_module_bitmap { SLEEP_RETENTION_MODULE_BM_I2S0 = BIT(SLEEP_RETENTION_MODULE_I2S0), SLEEP_RETENTION_MODULE_BM_I2S1 = BIT(SLEEP_RETENTION_MODULE_I2S1), SLEEP_RETENTION_MODULE_BM_I2S2 = BIT(SLEEP_RETENTION_MODULE_I2S2), + SLEEP_RETENTION_MODULE_BM_ETM0 = BIT(SLEEP_RETENTION_MODULE_ETM0), SLEEP_RETENTION_MODULE_BM_ALL = (uint32_t)-1 } periph_retention_module_bitmap_t; @@ -100,9 +102,10 @@ typedef enum periph_retention_module_bitmap { | SLEEP_RETENTION_MODULE_BM_UART3 \ | SLEEP_RETENTION_MODULE_BM_UART4 \ | SLEEP_RETENTION_MODULE_BM_RMT0 \ - | SLEEP_RETENTION_MODULE_BM_I2S0 \ - | SLEEP_RETENTION_MODULE_BM_I2S1 \ - | SLEEP_RETENTION_MODULE_BM_I2S2 \ + | SLEEP_RETENTION_MODULE_BM_I2S0 \ + | SLEEP_RETENTION_MODULE_BM_I2S1 \ + | SLEEP_RETENTION_MODULE_BM_I2S2 \ + | SLEEP_RETENTION_MODULE_BM_ETM0 \ ) #ifdef __cplusplus diff --git a/components/soc/esp32p4/include/soc/soc_caps.h b/components/soc/esp32p4/include/soc/soc_caps.h index ba380964b4f..a8a90bda867 100644 --- a/components/soc/esp32p4/include/soc/soc_caps.h +++ b/components/soc/esp32p4/include/soc/soc_caps.h @@ -221,6 +221,7 @@ /*-------------------------- ETM CAPS --------------------------------------*/ #define SOC_ETM_GROUPS 1U // Number of ETM groups #define SOC_ETM_CHANNELS_PER_GROUP 50 // Number of ETM channels in the group +#define SOC_ETM_SUPPORT_SLEEP_RETENTION 1 // Support sleep retention /*-------------------------- GPIO CAPS ---------------------------------------*/ // ESP32-P4 has 1 GPIO peripheral diff --git a/components/soc/include/soc/etm_periph.h b/components/soc/include/soc/etm_periph.h new file mode 100644 index 00000000000..f7168ff7173 --- /dev/null +++ b/components/soc/include/soc/etm_periph.h @@ -0,0 +1,32 @@ +/* + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include "soc/soc_caps.h" +#include "soc/regdma.h" + +#if SOC_ETM_SUPPORT_SLEEP_RETENTION +#include "soc/retention_periph_defs.h" +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#if SOC_ETM_SUPPORT_SLEEP_RETENTION +typedef struct { + periph_retention_module_t module; + const regdma_entries_config_t *regdma_entry_array; + uint32_t array_size; +} etm_reg_retention_info_t; + +extern const etm_reg_retention_info_t etm_reg_retention_info[SOC_ETM_GROUPS]; +#endif // SOC_ETM_SUPPORT_SLEEP_RETENTION + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/include/soc/regdma.h b/components/soc/include/soc/regdma.h index c3c62081f00..15186cbb95a 100644 --- a/components/soc/include/soc/regdma.h +++ b/components/soc/include/soc/regdma.h @@ -54,6 +54,7 @@ extern "C" { #define REGDMA_TG0_TIMER_LINK(_pri) ((0x1C << 8) | _pri) #define REGDMA_TG1_TIMER_LINK(_pri) ((0x1D << 8) | _pri) #define REGDMA_I2S_LINK(_pri) ((0x1E << 8) | _pri) +#define REGDMA_ETM_LINK(_pri) ((0x1F << 8) | _pri) #define REGDMA_MODEM_FE_LINK(_pri) ((0xFF << 8) | _pri) #define REGDMA_LINK_PRI_SYS_CLK REGDMA_LINK_PRI_0 @@ -68,6 +69,7 @@ extern "C" { #define REGDMA_LINK_PRI_IEEE802154 REGDMA_LINK_PRI_GENERAL_PERIPH #define REGDMA_LINK_PRI_GDMA REGDMA_LINK_PRI_GENERAL_PERIPH #define REGDMA_LINK_PRI_RMT REGDMA_LINK_PRI_GENERAL_PERIPH +#define REGDMA_LINK_PRI_ETM REGDMA_LINK_PRI_GENERAL_PERIPH #define REGDMA_LINK_PRI_GPTIMER REGDMA_LINK_PRI_GENERAL_PERIPH #define REGDMA_LINK_PRI_I2C REGDMA_LINK_PRI_GENERAL_PERIPH #define REGDMA_LINK_PRI_I2S REGDMA_LINK_PRI_GENERAL_PERIPH diff --git a/docs/en/api-reference/peripherals/etm.rst b/docs/en/api-reference/peripherals/etm.rst index b5a6a963ddd..a462082e83c 100644 --- a/docs/en/api-reference/peripherals/etm.rst +++ b/docs/en/api-reference/peripherals/etm.rst @@ -32,6 +32,7 @@ The following sections of this document cover the typical steps to configure and - :ref:`etm-event` - describes how to allocate a new ETM event handle or fetch an existing handle from various peripherals. - :ref:`etm-task` - describes how to allocate a new ETM task handle or fetch an existing handle from various peripherals. - :ref:`etm-channel-control` - describes common ETM channel control functions. +- :ref:`etm-power-management` - describes the options and strategies provided by the driver in order to save power. - :ref:`etm-thread-safety` - lists which APIs are guaranteed to be thread-safe by the driver. - :ref:`etm-kconfig-options` - lists the supported Kconfig options that can be used to make a different effect on driver behavior. @@ -131,6 +132,17 @@ To check if the ETM channels are set with proper events and tasks, you can call The digital ID printed in the dump information is defined in the ``soc/soc_etm_source.h`` file. +.. _etm-power-management: + +Power Management +^^^^^^^^^^^^^^^^ + +When power management is enabled, i.e., :ref:`CONFIG_PM_ENABLE` is on, the system may adjust or disable the clock source, and power off the ETM peripheral before going to sleep. As a result, the existing connection between events and tasks will be lost, and the ETM channels can't work correctly after wake up. So by default, the driver will acquire a power management lock internally to forbid the system from powering off the ETM peripheral. + +.. only:: SOC_ETM_SUPPORT_SLEEP_RETENTION + + If you want to save more power, you can set :cpp:member:`esp_etm_channel_config_t::etm_chan_flags::allow_pd` to ``true``. Then ETM registers will be backed up before sleep and restored after wake up. Please note, enabling this option will increase the memory consumption for saving the register context. + .. _etm-thread-safety: Thread Safety diff --git a/docs/en/api-reference/system/power_management.rst b/docs/en/api-reference/system/power_management.rst index 8a7b9c37ba8..f583b86718c 100644 --- a/docs/en/api-reference/system/power_management.rst +++ b/docs/en/api-reference/system/power_management.rst @@ -148,10 +148,11 @@ The following peripheral drivers are not aware of DFS yet. Applications need to - INT_MTX - TEE/APM - IO_MUX / GPIO - - Timer Group 0 & Timer Group 1 - SPI0/1 - SYSTIMER + :SOC_TIMER_SUPPORT_SLEEP_RETENTION: - GPTimer :SOC_RMT_SUPPORT_SLEEP_RETENTION: - RMT + :SOC_ETM_SUPPORT_SLEEP_RETENTION: - ETM :SOC_I2C_SUPPORT_SLEEP_RETENTION: - I2C :SOC_I2S_SUPPORT_SLEEP_RETENTION: - I2S :SOC_UART_SUPPORT_SLEEP_RETENTION: - All UARTs @@ -160,7 +161,6 @@ The following peripheral drivers are not aware of DFS yet. Applications need to .. list:: - - ETM - ASSIST_DEBUG - Trace - Crypto: AES/ECC/HMAC/RSA/SHA/DS/XTA_AES/ECDSA diff --git a/docs/zh_CN/api-reference/peripherals/etm.rst b/docs/zh_CN/api-reference/peripherals/etm.rst index 9c1967dcadd..448b1be6c69 100644 --- a/docs/zh_CN/api-reference/peripherals/etm.rst +++ b/docs/zh_CN/api-reference/peripherals/etm.rst @@ -32,6 +32,7 @@ ETM 模块具有多个通道，这些通道支持用户根据需要进行配置 - :ref:`etm-event` - 介绍如何分配新的 ETM 事件句柄，以及如何从不同外设获取现有句柄。 - :ref:`etm-task` - 介绍如何分配新的 ETM 任务句柄，以及如何从不同外设获取现有句柄。 - :ref:`etm-channel-control` - 介绍常见的 ETM 通道控制函数。 +- :ref:`etm-power-management` - 介绍了驱动针对功耗管理提供的选项和策略。 - :ref:`etm-thread-safety` - 列出了驱动程序中始终线程安全的 API。 - :ref:`etm-kconfig-options` - 列出了 ETM 支持的 Kconfig 选项，这些选项对驱动程序的行为会产生不同影响。 @@ -131,6 +132,17 @@ ETM 通道分析 以上输出信息打印的数字 ID 在 ``soc/soc_etm_source.h`` 文件中定义。 +.. _etm-power-management: + +电源管理 +^^^^^^^^ + +当启用电源管理时，即 :ref:`CONFIG_PM_ENABLE` 打开的时候，系统可能会调整或禁用时钟源，并在进入睡眠前关闭 ETM 外设依赖的电源。这会导致事件和任务之间的连接信息被丢失，ETM 通道在唤醒后无法正常工作。因此，默认情况下，驱动程序会获取电源管理锁，以禁止系统关闭 ETM 外设。 + +.. only:: SOC_ETM_SUPPORT_SLEEP_RETENTION + + 如果你想节省更多电量，可以将 :cpp:member:`esp_etm_channel_config_t::etm_chan_flags::allow_pd` 设置为 ``true``。ETM 寄存器将在睡眠前备份，并在唤醒后恢复。请注意，启用此选项会增加内存消耗，用于保存寄存器上下文。 + .. _etm-thread-safety: 线程安全 diff --git a/docs/zh_CN/api-reference/system/power_management.rst b/docs/zh_CN/api-reference/system/power_management.rst index 6d1e464abc0..3ea51dc30bb 100644 --- a/docs/zh_CN/api-reference/system/power_management.rst +++ b/docs/zh_CN/api-reference/system/power_management.rst @@ -148,19 +148,19 @@ ESP-IDF 中集成的电源管理算法可以根据应用程序组件的需求， - INT_MTX - TEE/APM - IO_MUX / GPIO - - Timer Group 0 & Timer Group 1 - SPI0/1 - SYSTIMER + :SOC_TIMER_SUPPORT_SLEEP_RETENTION: - GPTimer :SOC_RMT_SUPPORT_SLEEP_RETENTION: - RMT :SOC_I2C_SUPPORT_SLEEP_RETENTION: - I2C :SOC_I2S_SUPPORT_SLEEP_RETENTION: - I2S + :SOC_ETM_SUPPORT_SLEEP_RETENTION: - ETM :SOC_UART_SUPPORT_SLEEP_RETENTION: - All UARTs 以下外设尚未支持： .. list:: - - ETM - ASSIST_DEBUG - Trace - Crypto: AES/ECC/HMAC/RSA/SHA/DS/XTA_AES/ECDSA From 05cb70cc3a0ad4fe666a7c360f9366c5c8f815d9 Mon Sep 17 00:00:00 2001 From: morris Date: Thu, 10 Oct 2024 11:43:20 +0800 Subject: [PATCH 085/472] refactor(rmt): define retention module in the soc layer --- components/esp_driver_rmt/src/rmt_common.c | 30 +++++++++------------ components/esp_driver_rmt/src/rmt_private.h | 4 --- components/hal/esp32c5/include/hal/rmt_ll.h | 2 -- components/hal/esp32c6/include/hal/rmt_ll.h | 2 -- components/hal/esp32h2/include/hal/rmt_ll.h | 2 -- components/hal/esp32p4/include/hal/rmt_ll.h | 2 -- components/soc/esp32c5/rmt_periph.c | 1 + components/soc/esp32c6/rmt_periph.c | 1 + components/soc/esp32h2/rmt_periph.c | 1 + components/soc/esp32p4/rmt_periph.c | 1 + components/soc/include/soc/rmt_periph.h | 5 ++++ 11 files changed, 22 insertions(+), 29 deletions(-) diff --git a/components/esp_driver_rmt/src/rmt_common.c b/components/esp_driver_rmt/src/rmt_common.c index d2b6f856f6f..7a3cf11ca3d 100644 --- a/components/esp_driver_rmt/src/rmt_common.c +++ b/components/esp_driver_rmt/src/rmt_common.c @@ -75,7 +75,7 @@ rmt_group_t *rmt_acquire_group_handle(int group_id) rmt_ll_reset_register(group_id); } #if RMT_USE_RETENTION_LINK - sleep_retention_module_t module = RMT_LL_SLEEP_RETENTION_MODULE_ID(group_id); + sleep_retention_module_t module = rmt_reg_retention_info[group_id].module; sleep_retention_module_init_param_t init_param = { .cbs = { .create = { @@ -85,9 +85,7 @@ rmt_group_t *rmt_acquire_group_handle(int group_id) }, .depends = BIT(SLEEP_RETENTION_MODULE_CLOCK_SYSTEM) }; - if (sleep_retention_module_init(module, &init_param) == ESP_OK) { - group->sleep_retention_module = module; - } else { + if (sleep_retention_module_init(module, &init_param) != ESP_OK) { // even though the sleep retention module init failed, RMT driver should still work, so just warning here ESP_LOGW(TAG, "init sleep retention failed %d, power domain may be turned off during sleep", group_id); } @@ -147,11 +145,12 @@ void rmt_release_group_handle(rmt_group_t *group) if (do_deinitialize) { #if RMT_USE_RETENTION_LINK - if (group->sleep_retention_module) { - if (group->retention_link_created) { - sleep_retention_module_free(group->sleep_retention_module); - } - sleep_retention_module_deinit(group->sleep_retention_module); + sleep_retention_module_t module = rmt_reg_retention_info[group_id].module; + if (sleep_retention_get_created_modules() & BIT(module)) { + sleep_retention_module_free(module); + } + if (sleep_retention_get_inited_modules() & BIT(module)) { + sleep_retention_module_deinit(module); } #endif free(group); @@ -303,24 +302,21 @@ static esp_err_t rmt_create_sleep_retention_link_cb(void *arg) { rmt_group_t *group = (rmt_group_t *)arg; int group_id = group->group_id; - sleep_retention_module_t module = group->sleep_retention_module; esp_err_t err = sleep_retention_entries_create(rmt_reg_retention_info[group_id].regdma_entry_array, rmt_reg_retention_info[group_id].array_size, - REGDMA_LINK_PRI_RMT, module); + REGDMA_LINK_PRI_RMT, rmt_reg_retention_info[group_id].module); return err; } void rmt_create_retention_module(rmt_group_t *group) { - sleep_retention_module_t module = group->sleep_retention_module; - + int group_id = group->group_id; + sleep_retention_module_t module = rmt_reg_retention_info[group_id].module; _lock_acquire(&s_platform.mutex); - if (group->retention_link_created == false) { + if ((sleep_retention_get_inited_modules() & BIT(module)) && !(sleep_retention_get_created_modules() & BIT(module))) { if (sleep_retention_module_allocate(module) != ESP_OK) { // even though the sleep retention module create failed, RMT driver should still work, so just warning here - ESP_LOGW(TAG, "create retention link failed, power domain can't be turned off"); - } else { - group->retention_link_created = true; + ESP_LOGW(TAG, "create retention link failed, power domain won't be turned off during sleep"); } } _lock_release(&s_platform.mutex); diff --git a/components/esp_driver_rmt/src/rmt_private.h b/components/esp_driver_rmt/src/rmt_private.h index 017ed9d9ab6..16efc8ca9eb 100644 --- a/components/esp_driver_rmt/src/rmt_private.h +++ b/components/esp_driver_rmt/src/rmt_private.h @@ -119,10 +119,6 @@ struct rmt_group_t { rmt_rx_channel_t *rx_channels[SOC_RMT_RX_CANDIDATES_PER_GROUP]; // array of RMT RX channels rmt_sync_manager_t *sync_manager; // sync manager, this can be extended into an array if there're more sync controllers in one RMT group int intr_priority; // RMT interrupt priority -#if RMT_USE_RETENTION_LINK - sleep_retention_module_t sleep_retention_module; // sleep retention module - bool retention_link_created; // mark if the retention link is created -#endif }; struct rmt_channel_t { diff --git a/components/hal/esp32c5/include/hal/rmt_ll.h b/components/hal/esp32c5/include/hal/rmt_ll.h index 053e27d0e9b..0e54a0b3786 100644 --- a/components/hal/esp32c5/include/hal/rmt_ll.h +++ b/components/hal/esp32c5/include/hal/rmt_ll.h @@ -38,8 +38,6 @@ extern "C" { #define RMT_LL_MAX_FILTER_VALUE 255 #define RMT_LL_MAX_IDLE_VALUE 32767 -#define RMT_LL_SLEEP_RETENTION_MODULE_ID(group_id) (SLEEP_RETENTION_MODULE_RMT0) - typedef enum { RMT_LL_MEM_OWNER_SW = 0, RMT_LL_MEM_OWNER_HW = 1, diff --git a/components/hal/esp32c6/include/hal/rmt_ll.h b/components/hal/esp32c6/include/hal/rmt_ll.h index 247d63e5fe8..9fdc75764e0 100644 --- a/components/hal/esp32c6/include/hal/rmt_ll.h +++ b/components/hal/esp32c6/include/hal/rmt_ll.h @@ -38,8 +38,6 @@ extern "C" { #define RMT_LL_MAX_FILTER_VALUE 255 #define RMT_LL_MAX_IDLE_VALUE 32767 -#define RMT_LL_SLEEP_RETENTION_MODULE_ID(group_id) (SLEEP_RETENTION_MODULE_RMT0) - typedef enum { RMT_LL_MEM_OWNER_SW = 0, RMT_LL_MEM_OWNER_HW = 1, diff --git a/components/hal/esp32h2/include/hal/rmt_ll.h b/components/hal/esp32h2/include/hal/rmt_ll.h index a3179addba5..4ebb3a1e062 100644 --- a/components/hal/esp32h2/include/hal/rmt_ll.h +++ b/components/hal/esp32h2/include/hal/rmt_ll.h @@ -38,8 +38,6 @@ extern "C" { #define RMT_LL_MAX_FILTER_VALUE 255 #define RMT_LL_MAX_IDLE_VALUE 32767 -#define RMT_LL_SLEEP_RETENTION_MODULE_ID(group_id) (SLEEP_RETENTION_MODULE_RMT0) - typedef enum { RMT_LL_MEM_OWNER_SW = 0, RMT_LL_MEM_OWNER_HW = 1, diff --git a/components/hal/esp32p4/include/hal/rmt_ll.h b/components/hal/esp32p4/include/hal/rmt_ll.h index affcc3eeacd..105aa426925 100644 --- a/components/hal/esp32p4/include/hal/rmt_ll.h +++ b/components/hal/esp32p4/include/hal/rmt_ll.h @@ -33,8 +33,6 @@ extern "C" { #define RMT_LL_EVENT_TX_MASK(channel) (RMT_LL_EVENT_TX_DONE(channel) | RMT_LL_EVENT_TX_THRES(channel) | RMT_LL_EVENT_TX_LOOP_END(channel)) #define RMT_LL_EVENT_RX_MASK(channel) (RMT_LL_EVENT_RX_DONE(channel) | RMT_LL_EVENT_RX_THRES(channel)) -#define RMT_LL_SLEEP_RETENTION_MODULE_ID(group_id) (SLEEP_RETENTION_MODULE_RMT0) - #define RMT_LL_MAX_LOOP_COUNT_PER_BATCH 1023 #define RMT_LL_MAX_FILTER_VALUE 255 #define RMT_LL_MAX_IDLE_VALUE 32767 diff --git a/components/soc/esp32c5/rmt_periph.c b/components/soc/esp32c5/rmt_periph.c index 87c00ebd260..aa92c87aea3 100644 --- a/components/soc/esp32c5/rmt_periph.c +++ b/components/soc/esp32c5/rmt_periph.c @@ -60,6 +60,7 @@ static const regdma_entries_config_t rmt_regdma_entries[] = { const rmt_reg_retention_info_t rmt_reg_retention_info[SOC_RMT_GROUPS] = { [0] = { + .module = SLEEP_RETENTION_MODULE_RMT0, .regdma_entry_array = rmt_regdma_entries, .array_size = ARRAY_SIZE(rmt_regdma_entries) }, diff --git a/components/soc/esp32c6/rmt_periph.c b/components/soc/esp32c6/rmt_periph.c index 7ca8a5ddcbd..c08da463f29 100644 --- a/components/soc/esp32c6/rmt_periph.c +++ b/components/soc/esp32c6/rmt_periph.c @@ -60,6 +60,7 @@ static const regdma_entries_config_t rmt_regdma_entries[] = { const rmt_reg_retention_info_t rmt_reg_retention_info[SOC_RMT_GROUPS] = { [0] = { + .module = SLEEP_RETENTION_MODULE_RMT0, .regdma_entry_array = rmt_regdma_entries, .array_size = ARRAY_SIZE(rmt_regdma_entries) }, diff --git a/components/soc/esp32h2/rmt_periph.c b/components/soc/esp32h2/rmt_periph.c index 7ca8a5ddcbd..c08da463f29 100644 --- a/components/soc/esp32h2/rmt_periph.c +++ b/components/soc/esp32h2/rmt_periph.c @@ -60,6 +60,7 @@ static const regdma_entries_config_t rmt_regdma_entries[] = { const rmt_reg_retention_info_t rmt_reg_retention_info[SOC_RMT_GROUPS] = { [0] = { + .module = SLEEP_RETENTION_MODULE_RMT0, .regdma_entry_array = rmt_regdma_entries, .array_size = ARRAY_SIZE(rmt_regdma_entries) }, diff --git a/components/soc/esp32p4/rmt_periph.c b/components/soc/esp32p4/rmt_periph.c index ec8625bc945..e838ccb182a 100644 --- a/components/soc/esp32p4/rmt_periph.c +++ b/components/soc/esp32p4/rmt_periph.c @@ -76,6 +76,7 @@ static const regdma_entries_config_t rmt_regdma_entries[] = { const rmt_reg_retention_info_t rmt_reg_retention_info[SOC_RMT_GROUPS] = { [0] = { + .module = SLEEP_RETENTION_MODULE_RMT0, .regdma_entry_array = rmt_regdma_entries, .array_size = ARRAY_SIZE(rmt_regdma_entries) }, diff --git a/components/soc/include/soc/rmt_periph.h b/components/soc/include/soc/rmt_periph.h index a85b5930a22..bb35a67b863 100644 --- a/components/soc/include/soc/rmt_periph.h +++ b/components/soc/include/soc/rmt_periph.h @@ -10,6 +10,10 @@ #include "soc/periph_defs.h" #include "soc/regdma.h" +#if SOC_RMT_SUPPORT_SLEEP_RETENTION +#include "soc/retention_periph_defs.h" +#endif + #ifdef __cplusplus extern "C" { #endif @@ -32,6 +36,7 @@ extern const rmt_signal_conn_t rmt_periph_signals; #if SOC_RMT_SUPPORT_SLEEP_RETENTION typedef struct { + periph_retention_module_t module; const regdma_entries_config_t *regdma_entry_array; uint32_t array_size; } rmt_reg_retention_info_t; From a4f783d4071e8dab4e5013b6728f1b9a12bec1a3 Mon Sep 17 00:00:00 2001 From: morris Date: Thu, 10 Oct 2024 11:33:36 +0800 Subject: [PATCH 086/472] test(gptimer): added etm sleep retention test --- .../esp_driver_gptimer/src/gptimer_common.c | 30 ++-- .../esp_driver_gptimer/src/gptimer_priv.h | 4 - .../gptimer/main/test_gptimer_sleep.c | 134 ++++++++++++++++++ 3 files changed, 147 insertions(+), 21 deletions(-) diff --git a/components/esp_driver_gptimer/src/gptimer_common.c b/components/esp_driver_gptimer/src/gptimer_common.c index 928ce3c84ad..8338ebb2f49 100644 --- a/components/esp_driver_gptimer/src/gptimer_common.c +++ b/components/esp_driver_gptimer/src/gptimer_common.c @@ -27,24 +27,21 @@ static esp_err_t gptimer_create_sleep_retention_link_cb(void *arg) { gptimer_group_t *group = (gptimer_group_t *)arg; int group_id = group->group_id; - sleep_retention_module_t module = group->sleep_retention_module; esp_err_t err = sleep_retention_entries_create(tg_timer_reg_retention_info[group_id].regdma_entry_array, tg_timer_reg_retention_info[group_id].array_size, - REGDMA_LINK_PRI_GPTIMER, module); - ESP_RETURN_ON_ERROR(err, TAG, "create retention link failed"); - return ESP_OK; + REGDMA_LINK_PRI_GPTIMER, tg_timer_reg_retention_info[group_id].module); + return err; } void gptimer_create_retention_module(gptimer_group_t *group) { - sleep_retention_module_t module = group->sleep_retention_module; + int group_id = group->group_id; + sleep_retention_module_t module = tg_timer_reg_retention_info[group_id].module; _lock_acquire(&s_platform.mutex); - if (group->retention_link_created == false) { + if ((sleep_retention_get_inited_modules() & BIT(module)) && !(sleep_retention_get_created_modules() & BIT(module))) { if (sleep_retention_module_allocate(module) != ESP_OK) { // even though the sleep retention module create failed, GPTimer driver should still work, so just warning here - ESP_LOGW(TAG, "create retention module for group %d retention, power domain can't turn off", group->group_id); - } else { - group->retention_link_created = true; + ESP_LOGW(TAG, "create retention link failed %d, power domain won't be turned off during sleep", group_id); } } _lock_release(&s_platform.mutex); @@ -97,9 +94,7 @@ gptimer_group_t *gptimer_acquire_group_handle(int group_id) }, .depends = BIT(SLEEP_RETENTION_MODULE_CLOCK_SYSTEM) }; - if (sleep_retention_module_init(module, &init_param) == ESP_OK) { - group->sleep_retention_module = module; - } else { + if (sleep_retention_module_init(module, &init_param) != ESP_OK) { // even though the sleep retention module init failed, RMT driver should still work, so just warning here ESP_LOGW(TAG, "init sleep retention failed %d, power domain may be turned off during sleep", group_id); } @@ -132,11 +127,12 @@ void gptimer_release_group_handle(gptimer_group_t *group) } } #if GPTIMER_USE_RETENTION_LINK - if (group->sleep_retention_module) { - if (group->retention_link_created) { - sleep_retention_module_free(group->sleep_retention_module); - } - sleep_retention_module_deinit(group->sleep_retention_module); + sleep_retention_module_t module = tg_timer_reg_retention_info[group_id].module; + if (sleep_retention_get_created_modules() & BIT(module)) { + sleep_retention_module_free(module); + } + if (sleep_retention_get_inited_modules() & BIT(module)) { + sleep_retention_module_deinit(module); } #endif free(group); diff --git a/components/esp_driver_gptimer/src/gptimer_priv.h b/components/esp_driver_gptimer/src/gptimer_priv.h index 3c117af44f9..b5d4d1c0e66 100644 --- a/components/esp_driver_gptimer/src/gptimer_priv.h +++ b/components/esp_driver_gptimer/src/gptimer_priv.h @@ -59,10 +59,6 @@ typedef struct gptimer_group_t { int group_id; portMUX_TYPE spinlock; // to protect per-group register level concurrent access gptimer_t *timers[SOC_TIMER_GROUP_TIMERS_PER_GROUP]; -#if GPTIMER_USE_RETENTION_LINK - sleep_retention_module_t sleep_retention_module; // sleep retention module - bool retention_link_created; // mark if the retention link is created -#endif } gptimer_group_t; typedef enum { diff --git a/components/esp_driver_gptimer/test_apps/gptimer/main/test_gptimer_sleep.c b/components/esp_driver_gptimer/test_apps/gptimer/main/test_gptimer_sleep.c index 34a43715989..5b7e5879d57 100644 --- a/components/esp_driver_gptimer/test_apps/gptimer/main/test_gptimer_sleep.c +++ b/components/esp_driver_gptimer/test_apps/gptimer/main/test_gptimer_sleep.c @@ -10,6 +10,8 @@ #include "freertos/task.h" #include "unity.h" #include "driver/gptimer.h" +#include "driver/gpio_etm.h" +#include "driver/gpio.h" #include "soc/soc_caps.h" #include "esp_sleep.h" #include "esp_private/sleep_cpu.h" @@ -117,3 +119,135 @@ TEST_CASE("gptimer can work after light sleep", "[gptimer]") test_gptimer_sleep_retention(true); #endif } + +#if SOC_TIMER_SUPPORT_ETM +/** + * @brief Test the GPTimer and ETM subsystem can still work after light sleep + * + * @param back_up_before_sleep Whether to back up GPTimer registers before sleep + */ +static void test_gptimer_etm_sleep_retention(bool back_up_before_sleep) +{ + const uint32_t output_gpio = 1; + // GPTimer alarm ---> ETM channel A ---> GPTimer alarm re-enable + // GPTimer alarm ---> ETM channel B ---> GPIO toggle + printf("allocate etm channel\r\n"); + esp_etm_channel_config_t etm_config = { + .flags.allow_pd = back_up_before_sleep, + }; + esp_etm_channel_handle_t etm_channel_a, etm_channel_b; + TEST_ESP_OK(esp_etm_new_channel(&etm_config, &etm_channel_a)); + TEST_ESP_OK(esp_etm_new_channel(&etm_config, &etm_channel_b)); + + printf("initialize gpio\r\n"); + gpio_config_t task_gpio_config = { + .intr_type = GPIO_INTR_DISABLE, + .mode = GPIO_MODE_OUTPUT, + .pin_bit_mask = 1ULL << output_gpio, + }; + TEST_ESP_OK(gpio_config(&task_gpio_config)); + + printf("create a gptimer\r\n"); + gptimer_handle_t gptimer = NULL; + gptimer_config_t timer_config = { + .clk_src = GPTIMER_CLK_SRC_DEFAULT, + .direction = GPTIMER_COUNT_UP, + .resolution_hz = 1 * 1000 * 1000, // 1MHz, 1 tick = 1us + .flags.backup_before_sleep = back_up_before_sleep, + }; + TEST_ESP_OK(gptimer_new_timer(&timer_config, &gptimer)); + + printf("get gptimer etm event and task handle\r\n"); + esp_etm_event_handle_t gptimer_event = NULL; + gptimer_etm_event_config_t gptimer_etm_event_conf = { + .event_type = GPTIMER_ETM_EVENT_ALARM_MATCH, + }; + TEST_ESP_OK(gptimer_new_etm_event(gptimer, &gptimer_etm_event_conf, &gptimer_event)); + esp_etm_task_handle_t gptimer_task = NULL; + gptimer_etm_task_config_t gptimer_etm_task_conf = { + .task_type = GPTIMER_ETM_TASK_EN_ALARM, + }; + TEST_ESP_OK(gptimer_new_etm_task(gptimer, &gptimer_etm_task_conf, & gptimer_task)); + + printf("connect event and task to the channel a\r\n"); + TEST_ESP_OK(esp_etm_channel_connect(etm_channel_a, gptimer_event, gptimer_task)); + + printf("enable etm channels\r\n"); + TEST_ESP_OK(esp_etm_channel_enable(etm_channel_a)); + TEST_ESP_OK(esp_etm_channel_enable(etm_channel_b)); + + printf("set timer alarm action\r\n"); + gptimer_alarm_config_t alarm_config = { + .reload_count = 0, + .alarm_count = 100, // 100us per alarm event + .flags.auto_reload_on_alarm = true, + }; + TEST_ESP_OK(gptimer_set_alarm_action(gptimer, &alarm_config)); + + // before going to sleep, ensure the gptimer is not enabled yet, otherwise it will acquire power management lock + + esp_sleep_context_t sleep_ctx; + esp_sleep_set_sleep_context(&sleep_ctx); + printf("go to light sleep for 2 seconds\r\n"); +#if ESP_SLEEP_POWER_DOWN_CPU + TEST_ESP_OK(sleep_cpu_configure(true)); +#endif + TEST_ESP_OK(esp_sleep_enable_timer_wakeup(2 * 1000 * 1000)); + TEST_ESP_OK(esp_light_sleep_start()); + + printf("Waked up! Let's see if GPTimer and ETM can still work...\r\n"); +#if ESP_SLEEP_POWER_DOWN_CPU + TEST_ESP_OK(sleep_cpu_configure(false)); +#endif + + printf("check if the sleep happened as expected\r\n"); + TEST_ASSERT_EQUAL(0, sleep_ctx.sleep_request_result); +#if SOC_RMT_SUPPORT_SLEEP_RETENTION + // check if the power domain also is powered down + TEST_ASSERT_EQUAL(back_up_before_sleep ? PMU_SLEEP_PD_TOP : 0, (sleep_ctx.sleep_flags) & PMU_SLEEP_PD_TOP); +#endif + esp_sleep_set_sleep_context(NULL); + + printf("enable and start timer\r\n"); + TEST_ESP_OK(gptimer_enable(gptimer)); + TEST_ESP_OK(gptimer_start(gptimer)); + + printf("allocate GPIO etm task\r\n"); + esp_etm_task_handle_t gpio_task = NULL; + gpio_etm_task_config_t gpio_task_config = { + .action = GPIO_ETM_TASK_ACTION_TOG, + }; + TEST_ESP_OK(gpio_new_etm_task(&gpio_task_config, &gpio_task)); + // set gpio number for the gpio etm primitives + TEST_ESP_OK(gpio_etm_task_add_gpio(gpio_task, output_gpio)); + printf("connect event and task to the channel b\r\n"); + TEST_ESP_OK(esp_etm_channel_connect(etm_channel_b, gptimer_event, gpio_task)); + + // delay sometime for us to view the waveform, should see a 5KHz square waveform + vTaskDelay(pdMS_TO_TICKS(1000)); + + // delete gptimer + TEST_ESP_OK(gptimer_stop(gptimer)); + TEST_ESP_OK(gptimer_disable(gptimer)); + TEST_ESP_OK(gptimer_del_timer(gptimer)); + + // delete etm primitives + TEST_ESP_OK(gpio_etm_task_rm_gpio(gpio_task, output_gpio)); + TEST_ESP_OK(esp_etm_del_task(gpio_task)); + TEST_ESP_OK(esp_etm_del_task(gptimer_task)); + TEST_ESP_OK(esp_etm_del_event(gptimer_event)); + TEST_ESP_OK(esp_etm_channel_disable(etm_channel_a)); + TEST_ESP_OK(esp_etm_channel_disable(etm_channel_b)); + TEST_ESP_OK(esp_etm_del_channel(etm_channel_a)); + TEST_ESP_OK(esp_etm_del_channel(etm_channel_b)); +} + +TEST_CASE("gptimer and ETM can work after light sleep", "[gptimer]") +{ + test_gptimer_etm_sleep_retention(false); +#if SOC_TIMER_SUPPORT_SLEEP_RETENTION && SOC_ETM_SUPPORT_SLEEP_RETENTION + test_gptimer_etm_sleep_retention(true); +#endif +} + +#endif // SOC_TIMER_SUPPORT_ETM From 2c500dd5eb0af4bb5cbb697a89c857681cb7e5e8 Mon Sep 17 00:00:00 2001 From: akshat Date: Thu, 10 Oct 2024 11:19:44 +0530 Subject: [PATCH 087/472] fix(wifi): Prevent overwriting of scan parameters in consecutive scans --- components/esp_wifi/lib | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/components/esp_wifi/lib b/components/esp_wifi/lib index 49187f511a1..903d1e428f1 160000 --- a/components/esp_wifi/lib +++ b/components/esp_wifi/lib @@ -1 +1 @@ -Subproject commit 49187f511a1843ea2c3a7abc69c1186d9ea0ae7d +Subproject commit 903d1e428f1b08806070be4dc7a39118a4f7e417 From b7d445389dc6a18475befab9fdbc92a49f8f0b49 Mon Sep 17 00:00:00 2001 From: shenmengjing Date: Fri, 6 Sep 2024 10:56:58 +0800 Subject: [PATCH 088/472] docs: Update CN translation for ulp-lp-core.rst --- docs/en/api-reference/system/ulp-lp-core.rst | 128 ++++++------ .../api-reference/system/ulp-lp-core.rst | 192 +++++++++++++----- 2 files changed, 198 insertions(+), 122 deletions(-) diff --git a/docs/en/api-reference/system/ulp-lp-core.rst b/docs/en/api-reference/system/ulp-lp-core.rst index 1e91c49c69d..0e8a7ca2fec 100644 --- a/docs/en/api-reference/system/ulp-lp-core.rst +++ b/docs/en/api-reference/system/ulp-lp-core.rst @@ -1,11 +1,11 @@ -ULP LP-Core Coprocessor Programming +ULP LP Core Coprocessor Programming =================================== :link_to_translation:`zh_CN:[中文]` -The ULP LP-Core (Low-power core) coprocessor is a variant of the ULP present in {IDF_TARGET_NAME}. It features ultra-low power consumption while also being able to stay powered on while the main CPU stays in low-power modes. This enables the LP-Core coprocessor to handle tasks like GPIO or sensor readings while the main CPU is in sleep mode, resulting in significant overall power savings for the entire system. +The ULP LP core (Low-power core) coprocessor is a variant of the ULP present in {IDF_TARGET_NAME}. It features ultra-low power consumption while also being able to stay powered on while the main CPU stays in low-power modes. This enables the LP core coprocessor to handle tasks like GPIO or sensor readings while the main CPU is in sleep mode, resulting in significant overall power savings for the entire system. -The ULP LP-Core coprocessor has the following features: +The ULP LP core coprocessor has the following features: * A RV32I (32-bit RISC-V ISA) processor, with the multiplication/division (M), atomic (A), and compressed (C) extensions. * Interrupt controller. @@ -13,15 +13,15 @@ The ULP LP-Core coprocessor has the following features: * Can access all of the High-power (HP) SRAM and peripherals when the entire system is active. * Can access the Low-power (LP) SRAM and peripherals when the HP system is in sleep mode. -Compiling Code for the ULP LP-Core +Compiling Code for the ULP LP Core ---------------------------------- -The ULP LP-Core code is compiled together with your ESP-IDF project as a separate binary and automatically embedded into the main project binary. There are two ways to achieve this: +The ULP LP core code is compiled together with your ESP-IDF project as a separate binary and automatically embedded into the main project binary. There are two ways to achieve this: Using ``ulp_embed_binary`` ~~~~~~~~~~~~~~~~~~~~~~~~~~~ -1. Place the ULP LP-Core code, written in C or assembly (with the ``.S`` extension), in a dedicated directory within the component directory, such as ``ulp/``. +1. Place the ULP LP core code, written in C or assembly (with the ``.S`` extension), in a dedicated directory within the component directory, such as ``ulp/``. 2. After registering the component in the ``CMakeLists.txt`` file, call the ``ulp_embed_binary`` function. Here is an example: @@ -41,7 +41,7 @@ The first argument to ``ulp_embed_binary`` specifies the ULP binary name. The na Using a Custom CMake Project ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -It is also possible to create a custom CMake project for the LP-Core. This gives more control over the build process and allows you to set compile options, link external libraries and all other things that are possible with a regular CMake project. +It is also possible to create a custom CMake project for the LP core. This gives more control over the build process and allows you to set compile options, link external libraries and all other things that are possible with a regular CMake project. To do this, add the ULP project as an external project in your component ``CMakeLists.txt`` file: @@ -90,7 +90,7 @@ Building Your Project To compile and build your project: -1. Enable both :ref:`CONFIG_ULP_COPROC_ENABLED` and :ref:`CONFIG_ULP_COPROC_TYPE` in menuconfig, and set :ref:`CONFIG_ULP_COPROC_TYPE` to ``CONFIG_ULP_COPROC_TYPE_LP_CORE``. The :ref:`CONFIG_ULP_COPROC_RESERVE_MEM` option reserves RTC memory for the ULP, and must be set to a value big enough to store both the ULP LP-Core code and data. If the application components contain multiple ULP programs, then the size of the RTC memory must be sufficient to hold the largest one. +1. Enable both :ref:`CONFIG_ULP_COPROC_ENABLED` and :ref:`CONFIG_ULP_COPROC_TYPE` in menuconfig, and set :ref:`CONFIG_ULP_COPROC_TYPE` to ``CONFIG_ULP_COPROC_TYPE_LP_CORE``. The :ref:`CONFIG_ULP_COPROC_RESERVE_MEM` option reserves RTC memory for the ULP, and must be set to a value big enough to store both the ULP LP core code and data. If the application components contain multiple ULP programs, then the size of the RTC memory must be sufficient to hold the largest one. 2. Build the application as usual (e.g., ``idf.py app``). @@ -113,12 +113,12 @@ During the build process, the following steps are taken to build ULP program: .. _ulp-lp-core-access-variables: -Accessing the ULP LP-Core Program Variables +Accessing the ULP LP Core Program Variables ------------------------------------------- -Global symbols defined in the ULP LP-Core program may be used inside the main program. +Global symbols defined in the ULP LP core program may be used inside the main program. -For example, the ULP LP-Core program may define a variable ``measurement_count`` which defines the number of GPIO measurements the program needs to make before waking up the chip from Deep-sleep. +For example, the ULP LP core program may define a variable ``measurement_count`` which defines the number of GPIO measurements the program needs to make before waking up the chip from Deep-sleep. .. code-block:: c @@ -132,7 +132,7 @@ For example, the ULP LP-Core program may define a variable ``measurement_count`` ...do something. } -The main program can access the global ULP LP-Core program variables as the build system makes this possible by generating the ``${ULP_APP_NAME}.h`` and ``${ULP_APP_NAME}.ld`` files which define the global symbols present in the ULP LP-Core program. Each global symbol defined in the ULP LP-Core program is included in these files and are prefixed with ``ulp_``. +The main program can access the global ULP LP core program variables as the build system makes this possible by generating the ``${ULP_APP_NAME}.h`` and ``${ULP_APP_NAME}.ld`` files which define the global symbols present in the ULP LP core program. Each global symbol defined in the ULP LP core program is included in these files and are prefixed with ``ulp_``. The header file contains the declaration of the symbol: @@ -148,7 +148,7 @@ The generated linker script file defines the locations of symbols in LP_MEM: PROVIDE ( ulp_measurement_count = 0x50000060 ); -To access the ULP LP-Core program variables from the main program, the generated header file should be included using an ``include`` statement. This allows the ULP LP-Core program variables to be accessed as regular variables. +To access the ULP LP core program variables from the main program, the generated header file should be included using an ``include`` statement. This allows the ULP LP core program variables to be accessed as regular variables. .. code-block:: c @@ -160,15 +160,15 @@ To access the ULP LP-Core program variables from the main program, the generated .. note:: - Variables declared in the global scope of the LP-Core program reside in either the ``.bss`` or ``.data`` section of the binary. These sections are initialized when the LP-Core binary is loaded and executed. Accessing these variables from the main program on the HP-Core before the first LP-Core run may result in undefined behavior. + Variables declared in the global scope of the LP core program reside in either the ``.bss`` or ``.data`` section of the binary. These sections are initialized when the LP core binary is loaded and executed. Accessing these variables from the main program on the HP-Core before the first LP core run may result in undefined behavior. -Starting the ULP LP-Core Program +Starting the ULP LP Core Program -------------------------------- -To run a ULP LP-Core program, the main application needs to load the ULP program into RTC memory using the :cpp:func:`ulp_lp_core_load_binary` function, and then start it using the :cpp:func:`ulp_lp_core_run` function. +To run a ULP LP core program, the main application needs to load the ULP program into RTC memory using the :cpp:func:`ulp_lp_core_load_binary` function, and then start it using the :cpp:func:`ulp_lp_core_run` function. -Each ULP LP-Core program is embedded into the ESP-IDF application as a binary blob. The application can reference this blob and load it in the following way (supposed ULP_APP_NAME was defined to ``ulp_app_name``): +Each ULP LP core program is embedded into the ESP-IDF application as a binary blob. The application can reference this blob and load it in the following way (supposed ULP_APP_NAME was defined to ``ulp_app_name``): .. code-block:: c @@ -191,17 +191,17 @@ Once the program is loaded into LP memory, the application can be configured and ESP_ERROR_CHECK( ulp_lp_core_run(&cfg) ); -ULP LP-Core Program Flow +ULP LP Core Program Flow ------------------------ -How the ULP LP-Core coprocessor is started depends on the wake-up source selected in :cpp:type:`ulp_lp_core_cfg_t`. The most common use-case is for the ULP to periodically wake up, do some measurements before either waking up the main CPU or going back to sleep again. +How the ULP LP core coprocessor is started depends on the wake-up source selected in :cpp:type:`ulp_lp_core_cfg_t`. The most common use-case is for the ULP to periodically wake up, do some measurements before either waking up the main CPU or going back to sleep again. The ULP has the following wake-up sources: - * :c:macro:`ULP_LP_CORE_WAKEUP_SOURCE_HP_CPU` - LP Core can be woken up by the HP CPU. - * :c:macro:`ULP_LP_CORE_WAKEUP_SOURCE_LP_TIMER` - LP Core can be woken up by the LP timer. - * :c:macro:`ULP_LP_CORE_WAKEUP_SOURCE_ETM` - LP Core can be woken up by a ETM event. (Not yet supported) - * :c:macro:`ULP_LP_CORE_WAKEUP_SOURCE_LP_IO` - LP Core can be woken up when LP IO level changes. (Not yet supported) - * :c:macro:`ULP_LP_CORE_WAKEUP_SOURCE_LP_UART` - LP Core can be woken up after receiving a certain number of UART RX pulses. (Not yet supported) + * :c:macro:`ULP_LP_CORE_WAKEUP_SOURCE_HP_CPU` - LP core can be woken up by the HP CPU. + * :c:macro:`ULP_LP_CORE_WAKEUP_SOURCE_LP_TIMER` - LP core can be woken up by the LP timer. + * :c:macro:`ULP_LP_CORE_WAKEUP_SOURCE_ETM` - LP core can be woken up by a ETM event. (Not yet supported) + * :c:macro:`ULP_LP_CORE_WAKEUP_SOURCE_LP_IO` - LP core can be woken up when LP IO level changes. (Not yet supported) + * :c:macro:`ULP_LP_CORE_WAKEUP_SOURCE_LP_UART` - LP core can be woken up after receiving a certain number of UART RX pulses. (Not yet supported) When the ULP is woken up, it will go through the following steps: @@ -215,10 +215,10 @@ When the ULP is woken up, it will go through the following steps: #. Call :cpp:func:`ulp_lp_core_halt` -ULP LP-Core Peripheral Support +ULP LP Core Peripheral Support ------------------------------ -To enhance the capabilities of the ULP LP-Core coprocessor, it has access to peripherals that operate in the low-power domain. The ULP LP-Core coprocessor can interact with these peripherals when the main CPU is in sleep mode, and can wake up the main CPU once a wake-up condition is reached. The following peripherals are supported: +To enhance the capabilities of the ULP LP core coprocessor, it has access to peripherals that operate in the low-power domain. The ULP LP core coprocessor can interact with these peripherals when the main CPU is in sleep mode, and can wake up the main CPU once a wake-up condition is reached. The following peripherals are supported: .. list:: @@ -229,10 +229,10 @@ To enhance the capabilities of the ULP LP-Core coprocessor, it has access to per .. only:: CONFIG_ESP_ROM_HAS_LP_ROM - ULP LP-Core ROM + ULP LP Core ROM --------------- - The ULP LP-Core ROM is a small pre-built piece of code located in LP-ROM, which can't be modified. Similar to the bootloader ROM code ran by the main CPU, this code is executed when the ULP LP-Core coprocessor is started. The ROM code initializes the ULP LP-Core coprocessor and then jumps to the user program. The ROM code also prints boot messages if the LP UART has been initialized. + The ULP LP core ROM is a small pre-built piece of code located in LP-ROM, which can't be modified. Similar to the bootloader ROM code ran by the main CPU, this code is executed when the ULP LP core coprocessor is started. The ROM code initializes the ULP LP core coprocessor and then jumps to the user program. The ROM code also prints boot messages if the LP UART has been initialized. The ROM code is not executed if :cpp:member:`ulp_lp_core_cfg_t::skip_lp_rom_boot` is set to true. This is useful when you need the ULP to wake-up as quickly as possible and the extra overhead of initializing and printing is unwanted. @@ -244,12 +244,12 @@ To enhance the capabilities of the ULP LP-Core coprocessor, it has access to per Since these functions are already present in LP-ROM no matter what, using these in your program allows you to reduce the RAM footprint of your ULP application. -ULP LP-Core Interrupts +ULP LP Core Interrupts ---------------------- -The LP-Core coprocessor can be configured to handle interrupts from various sources. Examples of such interrupts could be LP IO low/high or LP timer interrupts. To register a handler for an interrupt, simply override any of the weak handlers provided by IDF. A complete list of handlers can be found in :component_file:`ulp_lp_core_interrupts.h `. For details on which interrupts are available on a specific target, please consult **{IDF_TARGET_NAME} Technical Reference Manual** [`PDF <{IDF_TARGET_TRM_EN_URL}#ulp>`__]. +The LP core coprocessor can be configured to handle interrupts from various sources. Examples of such interrupts could be LP IO low/high or LP timer interrupts. To register a handler for an interrupt, simply override any of the weak handlers provided by IDF. A complete list of handlers can be found in :component_file:`ulp_lp_core_interrupts.h `. For details on which interrupts are available on a specific target, please consult **{IDF_TARGET_NAME} Technical Reference Manual** [`PDF <{IDF_TARGET_TRM_EN_URL}#ulp>`__]. -For example, to override the handler for the LP IO interrupt, you can define the following function in your ULP LP-Core code: +For example, to override the handler for the LP IO interrupt, you can define the following function in your ULP LP core code: .. code-block:: c @@ -260,39 +260,40 @@ For example, to override the handler for the LP IO interrupt, you can define the :c:macro:`LP_CORE_ISR_ATTR` is a macro that is used to define the interrupt handler function. This macro ensures that registers are saved and restored correctly when the interrupt handler is called. -In addition to configuring the interrupt related registers for the interrupt source you want to handle, you also need to enable the interrupts globally in the LP-Core interrupt controller. This can be done using the :cpp:func:`ulp_lp_core_intr_enable` function. +In addition to configuring the interrupt related registers for the interrupt source you want to handle, you also need to enable the interrupts globally in the LP core interrupt controller. This can be done using the :cpp:func:`ulp_lp_core_intr_enable` function. -ULP LP-Core Clock Configuration +ULP LP Core Clock Configuration ------------------------------- + {IDF_TARGET_XTAL_FREQ:default="Not updated", esp32c5="48 MHz", esp32p4="40 MHz"} -The ULP LP-Core clock source is based on the system clock ``LP_FAST_CLK``, see `TRM <{IDF_TARGET_TRM_EN_URL}>`__ > ``Reset and Clock`` for more details. +The ULP LP Core clock source is based on the system clock ``LP_FAST_CLK``, see `TRM <{IDF_TARGET_TRM_EN_URL}>`__ > ``Reset and Clock`` for more details. .. only:: SOC_CLK_LP_FAST_SUPPORT_XTAL - On {IDF_TARGET_NAME} ``LP_FAST_CLK`` supports using the external {IDF_TARGET_XTAL_FREQ} crystal (XTAL) as the source for ``LP_FAST_CLK``, which allows the ULP LP-Core to run at a higher frequency than with the default ``RTC_FAST_CLOCK`` which runs at around 20 MHz. The drawback is that this clock is normally powered down during sleep to reduce power consumption, with it selected XTAL will also stay powered on during sleep, increasing power consumption. If you only plan to use the LP-Core as a co-processor while the HP-Core is active, then this option can be used to increase both the performance and the frequency stability of the LP-Core. + On {IDF_TARGET_NAME}, ``LP_FAST_CLK`` supports using the external {IDF_TARGET_XTAL_FREQ} crystal (XTAL) as its clock source. This allows the ULP LP Core to run at a higher frequency than with the default ``RTC_FAST_CLOCK``, which runs at around 20 MHz. However, there is a trade-off: this clock is normally powered down during sleep to reduce power consumption, but if XTAL is selected as the source, it will remain powered up during sleep, which increases power consumption. If you only plan to use the LP Core as a coprocessor while the HP Core is active, then selecting XTAL can enhance both the performance and frequency stability of the LP Core. - To enable this feature set :ref:`CONFIG_RTC_FAST_CLK_SRC` to ``CONFIG_RTC_FAST_CLK_SRC_XTAL``. + To enable this feature, set :ref:`CONFIG_RTC_FAST_CLK_SRC` to ``CONFIG_RTC_FAST_CLK_SRC_XTAL``. Debugging ULP LP-Core Applications ---------------------------------- -When programming the LP-Core, it can sometimes be challenging to figure out why the program is not behaving as expected. Here are some strategies to help you debug your LP-Core program: +When programming the LP core, it can sometimes be challenging to figure out why the program is not behaving as expected. Here are some strategies to help you debug your LP core program: -* Use the LP-UART to print: the LP-Core has access to the LP-UART peripheral, which can be used for printing information independently of the main CPU sleep state. See :example:`system/ulp/lp_core/lp_uart/lp_uart_print` for an example of how to use this driver. +* Use the LP-UART to print: the LP core has access to the LP-UART peripheral, which can be used for printing information independently of the main CPU sleep state. See :example:`system/ulp/lp_core/lp_uart/lp_uart_print` for an example of how to use this driver. -* Routing :cpp:func:`lp_core_printf` to the HP-Core console UART with :ref:`CONFIG_ULP_HP_UART_CONSOLE_PRINT`. This allows you to easily print LP-Core information to the already connected HP-Core console UART. The drawback of this approach is that it requires the main CPU to be awake and since there is no synchronization between the LP and HP cores, the output may be interleaved. +* Routing :cpp:func:`lp_core_printf` to the HP-Core console UART with :ref:`CONFIG_ULP_HP_UART_CONSOLE_PRINT`. This allows you to easily print LP core information to the already connected HP-Core console UART. The drawback of this approach is that it requires the main CPU to be awake and since there is no synchronization between the LP and HP cores, the output may be interleaved. * Share program state through shared variables: as described in :ref:`ulp-lp-core-access-variables`, both the main CPU and the ULP core can easily access global variables in RTC memory. Writing state information to such a variable from the ULP and reading it from the main CPU can help you discern what is happening on the ULP core. The downside of this approach is that it requires the main CPU to be awake, which will not always be the case. Keeping the main CPU awake might even, in some cases, mask problems, as some issues may only occur when certain power domains are powered down. -* Panic handler: the LP-Core has a panic handler that can dump the state of the LP-Core registers by the LP-UART when an exception is detected. To enable the panic handler, set the :ref:`CONFIG_ULP_PANIC_OUTPUT_ENABLE` option to ``y``. This option can be kept disabled to reduce LP-RAM usage by the LP-Core application. To recover a backtrace from the panic dump, it is possible to use esp-idf-monitor_., e.g.: +* Panic handler: the LP core has a panic handler that can dump the state of the LP core registers by the LP-UART when an exception is detected. To enable the panic handler, set the :ref:`CONFIG_ULP_PANIC_OUTPUT_ENABLE` option to ``y``. This option can be kept disabled to reduce LP-RAM usage by the LP core application. To recover a backtrace from the panic dump, it is possible to use esp-idf-monitor_., e.g.: .. code-block:: bash python -m esp_idf_monitor --toolchain-prefix riscv32-esp-elf- --target {IDF_TARGET_NAME} --decode-panic backtrace PATH_TO_ULP_ELF_FILE -Debugging ULP LP-Core Applications with GDB and OpenOCD +Debugging ULP LP Core Applications with GDB and OpenOCD ------------------------------------------------------- It is also possible to debug code running on LP core using GDB and OpenOCD as you usually do for HP cores, but it has some specifics and limitations. @@ -307,7 +308,7 @@ Run OpenOCD with special config file for LP core debugging support. And then run openocd -f board/{IDF_TARGET_PATH_NAME}-lpcore-builtin.cfg riscv32-esp-elf-gdb -x gdbinit -``gdbinit`` file contents with inline comments is below. For more details see the next section. +Below is the ``gdbinit`` file content with inline comments. For more details, see the next section. .. code-block:: bash @@ -339,17 +340,17 @@ LP Core Debugging Specifics .. list:: - #. For convenient debugging you may need to add `-O0` compile option for ULP app in its CMakeLists.txt. See :example:`system/ulp/lp_core/debugging/` how to do this. - :not esp32p4: #. LP core supports limited set of HW exceptions, so, for example, writing at address `0x0` will not cause a panic as it would be for the code running on HP core. This can be overcome to some extent by enabling undefined behavior sanitizer for LP core application, so `ubsan` can help to catch some errors. But note that it will increase code size significantly and it can happen that application won't fit into RTC RAM. To enable `ubsan` for ULP app add `-fsanitize=undefined -fno-sanitize=shift-base` compile option to its CMakeLists.txt. See :example:`system/ulp/lp_core/debugging/` how to do this. - #. To be able to debug program running on LP core debug info and symbols need to be loaded to GDB. It can be done via GDB command line or in ``gdbinit`` file. See section above. - #. Upon startup LP core application is loaded into RAM, so all SW breakpoints set before that moment will get overwritten. The best moment to set breakpoints for LP core application is to do this when LP core program reaches `main` function. - #. When using IDEs it can be that it does not support breakpoint actions/commands configuration shown in ``gdbinit`` above, so in this case you have to preset all breakpoints before debug session start and disable all of them except for ``main``. When program is stopped at ``main`` manually enable remaining breakpoints and resume execution. + #. For convenient debugging, you may need to add ``-O0`` compile option for ULP app in its ``CMakeLists.txt``. See :example:`system/ulp/lp_core/debugging/` on how to do this. + :not esp32p4: #. LP core supports limited set of HW exceptions, so, for example, writing at address `0x0` will not cause a panic as it would be for the code running on HP core. This can be overcome to some extent by enabling undefined behavior sanitizer for LP core application, so `ubsan` can help to catch some errors. But note that it will increase code size significantly and it can happen that application won't fit into RTC RAM. To enable `ubsan` for ULP app, add ``-fsanitize=undefined -fno-sanitize=shift-base`` compile option to its ``CMakeLists.txt``. See :example:`system/ulp/lp_core/debugging/` on how to do this. + #. To be able to debug program running on LP core, debugging information and symbols need to be loaded to GDB. It can be done via GDB command line or in ``gdbinit`` file. See section above. + #. Upon startup, LP core application is loaded into RAM, so all SW breakpoints set before that moment will get overwritten. The best moment to set breakpoints for LP core application is to do this when LP core program reaches `main` function. + #. When using IDEs, it may lack support for configuring breakpoint actions or commands shown in ``gdbinit`` above. Consequently, you have to preset all breakpoints before debug session start and disable all of them except for ``main``. When program stops at ``main``, enable the remaining breakpoints and resume execution manually. Limitations ~~~~~~~~~~~ -#. Currently debugging is not supported when either HP or LP core enters any sleep mode. So it limits available debugging scenarios. -#. FreeRTOS support in OpenOCD is disabled when debugging LP core, so you won't be able to see tasks running in the system. Instead there will be several threads representing HP and LP cores: +#. Currently, debugging is not supported when either HP or LP core enters any sleep mode. So it limits available debugging scenarios. +#. FreeRTOS support in OpenOCD is disabled when debugging LP core, so you won't be able to see tasks running in the system. Instead, there will be several threads representing HP and LP cores: .. code-block:: bash @@ -360,28 +361,23 @@ Limitations * 2 Thread 2 "{IDF_TARGET_PATH_NAME}.cpu1" (Name: {IDF_TARGET_PATH_NAME}.cpu1, state: breakpoint) do_things (max=1000000000) at /home/user/projects/esp/esp-idf/examples/system/ulp/lp_core/debugging/main/lp_core/main.c:21 -#. When setting HW breakpoint in GDB it is set on both cores, so the number of available HW breakpoints is limited to the number of them supported by LP core ({IDF_TARGET_SOC_CPU_BREAKPOINTS_NUM} for {IDF_TARGET_NAME}). -#. OpenOCD flash support is disabled. It does not matter for LP core application because it is run completely from RAM and GDB can use SW breakpoints for it. But if you want to set a breakpoint on function from flash used by the code running on HP core (e.g. `app_main`) you should request to set HW breakpoint explicitly via ``hb`` / ``thb`` GDB commands. -#. Since main and ULP programs are linked as separate binaries it is possible for them to have global symbols (functions, variables) with the same name. When you set breakpoint for such a functions using its name GDB will set breakpoints for all of them. It could lead to the problems when one of the function is located in the flash because currently flash support is disabled in OpenOCD when debugging LP core. In that case you can use source line or address based breakpoints. +#. When setting HW breakpoint in GDB, it is set on both cores, so the number of available HW breakpoints is limited to the number of them supported by LP core ({IDF_TARGET_SOC_CPU_BREAKPOINTS_NUM} for {IDF_TARGET_NAME}). +#. OpenOCD flash support is disabled. It does not matter for LP core application because it is run completely from RAM and GDB can use SW breakpoints for it. But if you want to set a breakpoint on function from flash used by the code running on HP core (e.g., `app_main`), you should request to set HW breakpoint explicitly via ``hb`` and ``thb`` GDB commands. +#. Since the main and ULP programs are linked as separate binaries, it is possible for them to have global symbols (such as functions or variables) with the same name. If you set a breakpoint using the function name, GDB will apply it to all instances of that function. This can cause issues if one of the functions is located in the flash, as OpenOCD currently doesn't support flash when debugging the LP core. In such cases, you can set breakpoints using the source line or the function's memory address instead. Application Examples -------------------- -* :example:`system/ulp/lp_core/gpio` polls GPIO while main CPU is in Deep-sleep. - -.. only:: esp32c6 - - * :example:`system/ulp/lp_core/lp_i2c` reads external I2C ambient light sensor (BH1750) while the main CPU is in Deep-sleep and wakes up the main CPU once a threshold is met. - -* :example:`system/ulp/lp_core/lp_uart/lp_uart_echo` reads data written to a serial console and echoes it back. This example demonstrates the usage of the LP UART driver running on the LP core. - -* :example:`system/ulp/lp_core/lp_uart/lp_uart_print` shows how to print various statements from a program running on the LP core. - -* :example:`system/ulp/lp_core/interrupt` shows how to register an interrupt handler on the LP core to receive an interrupt triggered by the main CPU. -* :example:`system/ulp/lp_core/gpio_intr_pulse_counter` shows how to use GPIO interrupts to count pulses while the main CPU is in Deep-sleep mode. +.. list:: -* :example:`system/ulp/lp_core/build_system/` demonstrates how to include custom ``CMakeLists.txt`` file for the ULP app. -* :example:`system/ulp/lp_core/debugging` shows how to debug code running on LP core using GDB and OpenOCD. + - :example:`system/ulp/lp_core/gpio` polls GPIO while main CPU is in Deep-sleep. + :esp32c6: - :example:`system/ulp/lp_core/lp_i2c` reads external I2C ambient light sensor (BH1750) while the main CPU is in Deep-sleep and wakes up the main CPU once a threshold is met. + - :example:`system/ulp/lp_core/lp_uart/lp_uart_echo` reads data written to a serial console and echoes it back. This example demonstrates the usage of the LP UART driver running on the LP core. + - :example:`system/ulp/lp_core/lp_uart/lp_uart_print` shows how to print various statements from a program running on the LP core. + - :example:`system/ulp/lp_core/interrupt` shows how to register an interrupt handler on the LP core to receive an interrupt triggered by the main CPU. + - :example:`system/ulp/lp_core/gpio_intr_pulse_counter` shows how to use GPIO interrupts to count pulses while the main CPU is in Deep-sleep mode. + - :example:`system/ulp/lp_core/build_system/` demonstrates how to include custom ``CMakeLists.txt`` file for the ULP app. + - :example:`system/ulp/lp_core/debugging` shows how to debug code running on LP core using GDB and OpenOCD. API Reference ------------- diff --git a/docs/zh_CN/api-reference/system/ulp-lp-core.rst b/docs/zh_CN/api-reference/system/ulp-lp-core.rst index 70cd7ec870b..4ffeca4ad74 100644 --- a/docs/zh_CN/api-reference/system/ulp-lp-core.rst +++ b/docs/zh_CN/api-reference/system/ulp-lp-core.rst @@ -1,11 +1,11 @@ -ULP LP-Core 协处理器编程 -=================================== +ULP LP 内核协处理器编程 +======================= :link_to_translation:`en:[English]` -ULP LP-Core（低功耗内核）协处理器是 {IDF_TARGET_NAME} 中 ULP 的一个变型。它具有超低功耗，同时还能在主 CPU 处于低功耗模式时保持运行。因此，LP-Core 协处理器能够在主 CPU 处于睡眠模式时处理 GPIO 或传感器读取等任务，从而显著降低整个系统的整体功耗。 +ULP LP 内核 (Low-power core) 协处理器是 {IDF_TARGET_NAME} 中 ULP 的一个变型。它具有超低功耗，同时还能在主 CPU 处于低功耗模式时保持运行。因此，LP 内核协处理器能够在主 CPU 处于睡眠模式时处理 GPIO 或传感器读取等任务，从而显著降低整个系统的整体功耗。 -ULP LP-Core 协处理器具有以下功能： +ULP LP 内核协处理器具有以下功能： * RV32I 处理器（32 位 RISC-V ISA），支持乘法/除法 (M)、原子 (A) 和压缩 (C) 扩展。 * 中断控制器。 @@ -13,17 +13,17 @@ ULP LP-Core 协处理器具有以下功能： * 当整个系统处于 active 模式时，可以访问所有的高功耗 (HP) SRAM 和外设。 * 当 HP 系统处于睡眠模式时，可以访问低功耗 (LP) SRAM 和外设。 -编译 ULP LP-Core 代码 ----------------------------------- +编译 ULP LP 内核代码 +-------------------- -ULP LP-Core 代码会与 ESP-IDF 项目共同编译，生成一个单独的二进制文件，并自动嵌入到主项目的二进制文件中。编译可通过以下两种方式实现： +ULP LP 内核代码会与 ESP-IDF 项目共同编译，生成一个单独的二进制文件，并自动嵌入到主项目的二进制文件中。编译可通过以下两种方式实现： 使用 ``ulp_embed_binary`` ~~~~~~~~~~~~~~~~~~~~~~~~~ -1. 将用 C 语言或汇编语言编写的 ULP LP-Core 代码（带有 ``.S`` 扩展名）放在组件目录下的专用目录中，例如 ``ulp/``。 +1. 将用 C 语言或汇编语言编写的 ULP LP 内核代码（带有 ``.S`` 扩展名）放在组件目录下的专用目录中，例如 ``ulp/``。 -2. 在 CMakeLists.txt 文件中注册组件后，调用 ``ulp_embed_binary`` 函数。例如： +2. 在 ``CMakeLists.txt`` 文件中注册组件后，调用 ``ulp_embed_binary`` 函数。例如： .. code-block:: cmake @@ -41,7 +41,7 @@ ULP LP-Core 代码会与 ESP-IDF 项目共同编译，生成一个单独的二 使用自定义的 CMake 项目 ~~~~~~~~~~~~~~~~~~~~~~~ -也可以为 LP-Core 创建自定义的 CMake 项目，从而更好地控制构建过程，并实现常规 CMake 项目的操作，例如设置编译选项、链接外部库等。 +也可以为 LP 内核创建自定义的 CMake 项目，从而更好地控制构建过程，并实现常规 CMake 项目的操作，例如设置编译选项、链接外部库等。 请在组件的 ``CMakeLists.txt`` 文件中将 ULP 项目添加为外部项目： @@ -90,7 +90,7 @@ ULP LP-Core 代码会与 ESP-IDF 项目共同编译，生成一个单独的二 若想编译和构建项目，请执行以下操作： -1. 在 menuconfig 中启用 :ref:`CONFIG_ULP_COPROC_ENABLED` 和 :ref:`CONFIG_ULP_COPROC_TYPE` 选项，并将 :ref:`CONFIG_ULP_COPROC_TYPE` 设置为 ``CONFIG_ULP_COPROC_TYPE_LP_CORE``。:ref:`CONFIG_ULP_COPROC_RESERVE_MEM` 选项为 ULP 保留 RTC 内存，因此必须设置为一个足够大的值，以存储 ULP LP-Core 代码和数据。如果应用程序组件包含多个 ULP 程序，那么 RTC 内存的大小必须足够容纳其中最大的程序。 +1. 在 menuconfig 中启用 :ref:`CONFIG_ULP_COPROC_ENABLED` 和 :ref:`CONFIG_ULP_COPROC_TYPE` 选项，并将 :ref:`CONFIG_ULP_COPROC_TYPE` 设置为 ``CONFIG_ULP_COPROC_TYPE_LP_CORE``。:ref:`CONFIG_ULP_COPROC_RESERVE_MEM` 选项为 ULP 保留 RTC 内存，因此必须设置为一个足够大的值，以存储 ULP LP 内核代码和数据。如果应用程序组件包含多个 ULP 程序，那么 RTC 内存的大小必须足够容纳其中最大的程序。 2. 按照常规步骤构建应用程序（例如 ``idf.py app``）。 @@ -113,12 +113,12 @@ ULP LP-Core 代码会与 ESP-IDF 项目共同编译，生成一个单独的二 .. _ulp-lp-core-access-variables: -访问 ULP LP-Core 程序变量 -------------------------------------------- +访问 ULP LP 内核程序变量 +------------------------ -在主程序中可以使用在 ULP LP-Core 程序中定义的全局符号。 +在主程序中可以使用在 ULP LP 内核程序中定义的全局符号。 -例如，ULP LP-Core 程序定义了一个变量 ``measurement_count``，用来表示程序从深度睡眠中唤醒芯片前所需的 GPIO 测量次数。 +例如，ULP LP 内核程序定义了一个变量 ``measurement_count``，用来表示程序从深度睡眠中唤醒芯片前所需的 GPIO 测量次数。 .. code-block:: c @@ -132,7 +132,7 @@ ULP LP-Core 代码会与 ESP-IDF 项目共同编译，生成一个单独的二 ...do something. } -主程序可以访问 ULP LP-Core 程序全局变量，这是因为构建系统生成了 ``${ULP_APP_NAME}.h`` 和 ``${ULP_APP_NAME}.ld`` 文件，文件中定义了 ULP LP-Core 程序中现有的的全局符号。在 ULP LP-Core 程序中定义的每个全局符号都包含在这两个文件中，并具有前缀 ``ulp_``。 +主程序可以访问 ULP LP 内核程序全局变量，这是因为构建系统生成了 ``${ULP_APP_NAME}.h`` 和 ``${ULP_APP_NAME}.ld`` 文件，文件中定义了 ULP LP 内核程序中现有的的全局符号。在 ULP LP 内核程序中定义的每个全局符号都包含在这两个文件中，并具有前缀 ``ulp_``。 头文件中包含符号的声明： @@ -148,7 +148,7 @@ ULP LP-Core 代码会与 ESP-IDF 项目共同编译，生成一个单独的二 PROVIDE ( ulp_measurement_count = 0x50000060 ); -要从主程序访问 ULP LP-Core 程序变量，应使用 ``include`` 语句将生成的头文件包含在主程序中，这样就可以像访问常规变量一样访问 ULP LP-Core 程序变量。 +要从主程序访问 ULP LP 内核程序变量，应使用 ``include`` 语句将生成的头文件包含在主程序中，这样就可以像访问常规变量一样访问 ULP LP 内核程序变量。 .. code-block:: c @@ -160,15 +160,15 @@ ULP LP-Core 代码会与 ESP-IDF 项目共同编译，生成一个单独的二 .. note:: - LP-Core 程序全局变量存储在二进制文件的 ``.bss`` 或者 ``.data`` 部分。这些部分在加载和执行 LP-Core 二进制文件时被初始化。在首次运行 LP-Core 之前，从 HP-Core 主程序访问这些变量可能会导致未定义行为。 + LP 内核程序全局变量存储在二进制文件的 ``.bss`` 或者 ``.data`` 部分。这些部分在加载和执行 LP 内核二进制文件时被初始化。在首次运行 LP 内核之前，从 HP-Core 主程序访问这些变量可能会导致未定义行为。 -启动 ULP LP-Core 程序 --------------------------------- +启动 ULP LP 内核程序 +-------------------- -要运行 ULP LP-Core 程序，主应用程序需要先使用 :cpp:func:`ulp_lp_core_load_binary` 函数将 ULP 程序加载到 RTC 内存中，然后使用 :cpp:func:`ulp_lp_core_run` 函数进行启动。 +要运行 ULP LP 内核程序，主应用程序需要先使用 :cpp:func:`ulp_lp_core_load_binary` 函数将 ULP 程序加载到 RTC 内存中，然后使用 :cpp:func:`ulp_lp_core_run` 函数进行启动。 -每个 ULP LP-Core 程序以二进制 blob 的形式嵌入到 ESP-IDF 应用程序中。应用程序可以按照如下方式引用和加载该 blob（假设 ULP_APP_NAME 被定义为 ``ulp_app_name``）： +每个 ULP LP 内核程序以二进制 blob 的形式嵌入到 ESP-IDF 应用程序中。应用程序可以按照如下方式引用和加载该 blob（假设 ULP_APP_NAME 被定义为 ``ulp_app_name``）： .. code-block:: c @@ -191,10 +191,10 @@ ULP LP-Core 代码会与 ESP-IDF 项目共同编译，生成一个单独的二 ESP_ERROR_CHECK( ulp_lp_core_run(&cfg) ); -ULP LP-Core 程序流程 ------------------------- +ULP LP 内核程序流程 +------------------- -ULP LP-Core 协处理器如何启动取决于 :cpp:type:`ulp_lp_core_cfg_t` 中选择的唤醒源。最常见的用例是 ULP 定期唤醒，在进行一些测量后唤醒主 CPU，或者再次进入睡眠状态。 +ULP LP 内核协处理器如何启动取决于 :cpp:type:`ulp_lp_core_cfg_t` 中选择的唤醒源。最常见的用例是 ULP 定期唤醒，在进行一些测量后唤醒主 CPU，或者再次进入睡眠状态。 ULP 有以下唤醒源： * :c:macro:`ULP_LP_CORE_WAKEUP_SOURCE_HP_CPU` - LP 内核可以被 HP CPU 唤醒。 @@ -215,10 +215,10 @@ ULP 被唤醒时会经历以下步骤： #. 调用 :cpp:func:`ulp_lp_core_halt` -ULP LP-Core 支持的外设 ------------------------------- +ULP LP 内核支持的外设 +--------------------- -为了增强 ULP LP-Core 协处理器的功能，它可以访问在低功耗电源域运行的外设。ULP LP-Core 协处理器可以在主 CPU 处于睡眠模式时与这些外设进行交互，并在达到唤醒条件时唤醒主 CPU。以下为支持的外设： +为了增强 ULP LP 内核协处理器的功能，它可以访问在低功耗电源域运行的外设。ULP LP 内核协处理器可以在主 CPU 处于睡眠模式时与这些外设进行交互，并在达到唤醒条件时唤醒主 CPU。以下为支持的外设： .. list:: @@ -229,14 +229,14 @@ ULP LP-Core 支持的外设 .. only:: CONFIG_ESP_ROM_HAS_LP_ROM - ULP LP-Core ROM + ULP LP 内核 ROM --------------- - ULP LP-Core ROM 是位于 LP-ROM 中的一小段预编译代码，用户无法修改。与主 CPU 运行的引导加载程序 ROM 代码类似，ULP LP-Core ROM 也在 ULP LP-Core 协处理器启动时执行。该 ROM 代码会初始化 ULP LP-Core 协处理器，随后跳转到用户程序。如果已初始化 LP UART，该 ROM 代码还会打印启动信息。 + ULP LP 内核 ROM 是位于 LP-ROM 中的一小段预编译代码，用户无法修改。与主 CPU 运行的引导加载程序 ROM 代码类似，ULP LP 内核 ROM 也在 ULP LP 内核协处理器启动时执行。该 ROM 代码会初始化 ULP LP 内核协处理器，随后跳转到用户程序。如果已初始化 LP UART，该 ROM 代码还会打印启动信息。 - 如果已将 :cpp:member:`ulp_lp_core_cfg_t::skip_lp_rom_boot` 设置为真，则不会执行 ULP LP-Core ROM 代码。如需尽快唤醒 ULP，同时避免初始化和信息打印产生额外开销，则可使用这一功能。 + 如果已将 :cpp:member:`ulp_lp_core_cfg_t::skip_lp_rom_boot` 设置为真，则不会执行 ULP LP 内核 ROM 代码。如需尽快唤醒 ULP，同时避免初始化和信息打印产生额外开销，则可使用这一功能。 - 除上述启动代码，ULP LP-Core ROM 代码还提供以下功能和接口： + 除上述启动代码，ULP LP 内核 ROM 代码还提供以下功能和接口： * :component_file:`ROM.ld 接口 ` * :component_file:`newlib.ld 接口 ` @@ -244,12 +244,12 @@ ULP LP-Core 支持的外设 在任何情况下，这些函数都存在于 LP-ROM 中，因此在程序中使用这些函数可以减少 ULP 应用程序的 RAM 占用。 -ULP LP-Core 中断 ----------------- +ULP LP 内核中断 +--------------- -配置 LP-Core 协处理器，可以处理各种类型的中断，例如 LP IO 低/高电平中断或是 LP 定时器中断。只需重写 IDF 提供的任何一个弱处理函数，就可以注册一个中断处理程序。所有处理程序可见 :component_file:`ulp_lp_core_interrupts.h `。有关特定目标可使用的中断的详细信息，请参阅 **{IDF_TARGET_NAME} 技术参考手册** [`PDF <{IDF_TARGET_TRM_CN_URL}#ulp>`__]。 +配置 LP 内核协处理器，可以处理各种类型的中断，例如 LP IO 低/高电平中断或是 LP 定时器中断。只需重写 IDF 提供的任何一个弱处理函数，就可以注册一个中断处理程序。所有处理程序可见 :component_file:`ulp_lp_core_interrupts.h `。有关特定目标可使用的中断的详细信息，请参阅 **{IDF_TARGET_NAME} 技术参考手册** [`PDF <{IDF_TARGET_TRM_CN_URL}#ulp>`__]。 -例如，要重写 LP IO 中断的处理程序，可以在 ULP LP-Core 代码中定义以下函数： +例如，要重写 LP IO 中断的处理程序，可以在 ULP LP 内核代码中定义以下函数： .. code-block:: c @@ -260,50 +260,130 @@ ULP LP-Core 中断 :c:macro:`LP_CORE_ISR_ATTR` 宏用于定义中断处理函数，可确保调用中断处理程序时妥善保存并恢复寄存器。 -除了为需要处理的中断源配置相关的中断寄存器外，还要调用 :cpp:func:`ulp_lp_core_intr_enable` 函数，在 LP-Core 中断控制器中使能全局中断。 +除了为需要处理的中断源配置相关的中断寄存器外，还要调用 :cpp:func:`ulp_lp_core_intr_enable` 函数，在 LP 内核中断控制器中使能全局中断。 + +ULP LP 内核时钟配置 +------------------- -调试 ULP LP-Core 应用程序 -------------------------- +{IDF_TARGET_XTAL_FREQ:default="未更新", esp32c5="48 MHz", esp32p4="40 MHz"} -在编程 LP-Core 时，有时很难弄清楚程序未按预期运行的原因。请参考以下策略，调试 LP-Core 程序： +ULP LP 内核的时钟源来自系统时钟 ``LP_FAST_CLK``，详情请参见 `技术参考手册 <{IDF_TARGET_TRM_CN_URL}>`__ > ``复位和时钟``。 -* 使用 LP-UART 打印：LP-Core 可以访问 LP-UART 外设，在主 CPU 处于睡眠状态时独立打印信息。有关使用此驱动程序的示例，请参阅 :example:`system/ulp/lp_core/lp_uart/lp_uart_print`。 +.. only:: SOC_CLK_LP_FAST_SUPPORT_XTAL -* 通过 :ref:`CONFIG_ULP_HP_UART_CONSOLE_PRINT`，将 :cpp:func:`lp_core_printf` 路由到 HP-Core 控制台 UART，可以轻松地将 LP-Core 信息打印到已经连接的 HP-Core 控制台 UART。此方法的缺点是需要主 CPU 处于唤醒状态，并且由于 LP 核与 HP 核未同步，输出可能会交错。 + 在 {IDF_TARGET_NAME} 上，``LP_FAST_CLK`` 支持使用外部 {IDF_TARGET_XTAL_FREQ} 晶振 (XTAL) 作为其时钟源。默认时钟源 ``RTC_FAST_CLOCK`` 的运行频率约为 20 MHz，使用外部晶振时钟后，ULP LP 内核将以更高的频率运行。缺点在于，``LP_FAST_CLK`` 在休眠期间通常会断电以减少功耗，而选择 XTAL 作为时钟源后，休眠期间时钟仍将保持通电，造成功耗增加。因此，如果仅希望在 HP 内核活动时将 LP 内核用作协处理器，则可以使用 XTAL 以提高 LP 内核的性能和频率稳定性。 + + 要启用此功能，请将 :ref:`CONFIG_RTC_FAST_CLK_SRC` 设置为 ``CONFIG_RTC_FAST_CLK_SRC_XTAL``。 + + +调试 ULP LP 内核应用程序 +------------------------ + +在编程 LP 内核时，有时很难弄清楚程序未按预期运行的原因。请参考以下策略，调试 LP 内核程序： + +* 使用 LP-UART 打印：LP 内核可以访问 LP-UART 外设，在主 CPU 处于睡眠状态时独立打印信息。有关使用此驱动程序的示例，请参阅 :example:`system/ulp/lp_core/lp_uart/lp_uart_print`。 + +* 通过 :ref:`CONFIG_ULP_HP_UART_CONSOLE_PRINT`，将 :cpp:func:`lp_core_printf` 路由到 HP-Core 控制台 UART，可以轻松地将 LP 内核信息打印到已经连接的 HP-Core 控制台 UART。此方法的缺点是需要主 CPU 处于唤醒状态，并且由于 LP 内核与 HP 内未同步，输出可能会交错。 * 通过共享变量共享程序状态：如 :ref:`ulp-lp-core-access-variables` 所述，主 CPU 和 ULP 内核都可以轻松访问 RTC 内存中的全局变量。若想了解 ULP 内核的运行状态，可以将状态信息从 ULP 写入变量中，并通过主 CPU 读取信息。这种方法的缺点在于它需要主 CPU 一直处于唤醒状态，而这通常很难实现。另外，若主 CPU 一直处于唤醒状态，可能会掩盖某些问题，因为部分问题只会在特定电源域断电时发生。 -* 紧急处理程序：当检测到异常时，LP-Core 的紧急处理程序会把 LP-Core 寄存器的状态通过 LP-UART 发送出去。将 :ref:`CONFIG_ULP_PANIC_OUTPUT_ENABLE` 选项设置为 ``y``，可以启用紧急处理程序。禁用此选项将减少 LP-Core 应用程序的 LP-RAM 使用量。若想从紧急转储中解析栈回溯，可以使用 esp-idf-monitor_，例如： +* 紧急处理程序：当检测到异常时，LP 内核的紧急处理程序会把 LP 内核寄存器的状态通过 LP-UART 发送出去。将 :ref:`CONFIG_ULP_PANIC_OUTPUT_ENABLE` 选项设置为 ``y``，可以启用紧急处理程序。禁用此选项将减少 LP 内核应用程序的 LP-RAM 使用量。若想从紧急转储中解析栈回溯，可以使用 esp-idf-monitor_，例如： .. code-block:: bash python -m esp_idf_monitor --toolchain-prefix riscv32-esp-elf- --target {IDF_TARGET_NAME} --decode-panic backtrace PATH_TO_ULP_ELF_FILE +调试 ULP LP 内核应用程序：使用 GDB 和 OpenOCD +---------------------------------------------- -应用示例 --------- +与调试 HP 内核类似，也可以用 GDB 和 OpenOCD 来调试 LP 内核上的代码，但要注意其特殊之处和限制条件。 + +调试会话 +~~~~~~~~ -* :example:`system/ulp/lp_core/gpio` 展示了 ULP LP-Core 协处理器在主 CPU 深度睡眠时轮询 GPIO。 +使用支持 LP 内核调试的特殊配置文件来运行 OpenOCD，然后用特殊的 ``gdbinit`` 文件运行 GDB。 + +.. code-block:: bash + + openocd -f board/{IDF_TARGET_PATH_NAME}-lpcore-builtin.cfg + riscv32-esp-elf-gdb -x gdbinit + +以下是带有内联注释的 ``gdbinit`` 文件内容，详细信息请参考下一章节。 + +.. code-block:: bash + + # 连接到目标 + target extended-remote :3333 + # 重置芯片 + mon reset halt + maintenance flush register-cache + # 添加 ULP 程序的符号和调试信息 + add-symbol + # 设置临时硬件断点 + # 如果需要的断点数量超过硬件支持的数量 + thb main + commands + # 在这里设置断点 + # 此时 ULP 程序已加载到 RAM 中 + # 若无可用的硬件断点插槽，GDB 将设置软件断点 + b func1 + b func2 + b func3 + # 恢复执行 + c + end + # 重置后启动主程序 + c + +LP 内核调试特性 +~~~~~~~~~~~~~~~ -.. only:: esp32c6 +.. list:: - * :example:`system/ulp/lp_core/lp_i2c` 展示了 ULP LP-Core 协处理器在主 CPU 深度睡眠时读取外部 I2C 环境光传感器 (BH1750)，并在达到阈值时唤醒主 CPU。 + #. 为了方便调试，请在 ULP 应用的 ``CMakeLists.txt`` 文件中添加 ``-O0`` 编译选项。具体操作步骤请参见 :example:`system/ulp/lp_core/debugging/`。 + :not esp32p4: #. LP 内核支持的硬件异常类型有限，例如，写入地址 `0x0` 不会像在 HP 内核上一样造成系统崩溃。启用 LP 内核应用程序的未定义行为检测器 (`ubsan`) 可以捕捉一些错误，从而在一定程度上弥补这一限制。但请注意，这将显著增加代码量，可能会导致应用程序超出 RTC RAM 的容量限制。要启用 `ubsan`，请在 ``CMakeLists.txt`` 文件中添加 ``-fsanitize=undefined -fno-sanitize=shift-base`` 编译选项。具体操作步骤请参见 :example:`system/ulp/lp_core/debugging/`。 + #. 为了调试运行在 LP 内核上的程序，需要先将调试信息和符号加载到 GDB 中。这可以通过 GDB 命令行或在 ``gdbinit`` 文件中完成。具体操作步骤请参见上文。 + #. LP 内核应用程序会在启时会加载到 RAM 中，在此之前设置的所有软件断点都会被覆盖。设置 LP 内核应用断点的最佳时机是在 LP 内核程序运行至 ``main`` 函数之时。 + #. 使用 IDE 时，可能无法配置上述 ``gdbinit`` 文件中的断点操作或命令。因此，请在调试会话开始前预设并禁用所有断点，只保留 ``main`` 函数处的断点。当程序在 ``main`` 处停止时，手动启用其余断点并恢复执行。 -* :example:`system/ulp/lp_core/lp_uart/lp_uart_echo` 展示了低功耗内核上运行的 LP UART 驱动程序如何读取并回显写入串行控制台的数据。 +限制 +~~~~ -* :example:`system/ulp/lp_core/lp_uart/lp_uart_print` 展示了如何在低功耗内核上使用串口打印功能。 +#. 调试场景有限制：目前，当 HP 内核或 LP 内核进入睡眠模式时，将无法调适。 +#. 调试 内核时，OpenOCD 不支持 FreeRTOS，因此无法看到系统中正在运行的任务，但会有几个线程代表 HP 和 LP 内核： -* :example:`system/ulp/lp_core/interrupt` 展示了如何在 LP 内核上注册中断处理程序，接收由主 CPU 触发的中断。 +.. code-block:: bash -* :example:`system/ulp/lp_core/gpio_intr_pulse_counter` 展示了如何在主 CPU 处于 Deep-sleep 模式时，使用 GPIO 中断为脉冲计数。 + (gdb) info thread + Id Target Id Frame + 1 Thread 1 "{IDF_TARGET_PATH_NAME}.cpu0" (Name: {IDF_TARGET_PATH_NAME}.cpu0, state: debug-request) 0x40803772 in esp_cpu_wait_for_intr () + at /home/user/projects/esp/esp-idf/components/esp_hw_support/cpu.c:64 + * 2 Thread 2 "{IDF_TARGET_PATH_NAME}.cpu1" (Name: {IDF_TARGET_PATH_NAME}.cpu1, state: breakpoint) do_things (max=1000000000) + at /home/user/projects/esp/esp-idf/examples/system/ulp/lp_core/debugging/main/lp_core/main.c:21 -* :example:`system/ulp/lp_core/build_system/` 演示了如何为 ULP 应用程序添加自定义的 ``CMakeLists.txt`` 文件。 +#. 在 GDB 中设置硬件断点时，这些断点会同时应用到两个内核上，因此可用的硬件断点数量受 LP 内核支持数量（{IDF_TARGET_NAME} 有 {IDF_TARGET_SOC_CPU_BREAKPOINTS_NUM} 个）所限。 +#. OpenOCD 的 flash 支持被禁用。LP 内核应用程序完全在 RAM 中运行，且 GDB 可以为其使用软件断点，因而该限制无关紧要。但若想在 HP 内核运行的代码中调用的 flash 函数（例如 `app_main`）上设置断点，则需要通过 ``hb`` 和 ``thb`` GDB 命令显式请求设置硬件断点。 +#. 由于主程序和 ULP 程序被链接为独立的二进制文件，它们可能会拥有相同名称的全局符号（如函数或变量）。若通过函数名称设置断点，则 GDB 将为所有同名函数设置断点。在调试 LP 内核时，OpenOCD 不支持 flash，因此如果上述函数位于 flash 中，可能会引发问题。此时建议通过源代码行号或函数的内存地址来设置断点。 + +应用示例 +-------- + +.. list:: + + - :example:`system/ulp/lp_core/gpio` 展示了 ULP LP 内核协处理器在主 CPU 深度睡眠时轮询 GPIO。 + :esp32c6: - :example:`system/ulp/lp_core/lp_i2c` 展示了 ULP LP 内核协处理器在主 CPU 深度睡眠时读取外部 I2C 环境光传感器 (BH1750)，并在达到阈值时唤醒主 CPU。 + - :example:`system/ulp/lp_core/lp_uart/lp_uart_echo` 展示了低功耗内核上运行的 LP UART 驱动程序如何读取并回显写入串行控制台的数据。 + - :example:`system/ulp/lp_core/lp_uart/lp_uart_print` 展示了如何在低功耗内核上使用串口打印功能。 + - :example:`system/ulp/lp_core/interrupt` 展示了如何在 LP 内核上注册中断处理程序，接收由主 CPU 触发的中断。 + - :example:`system/ulp/lp_core/gpio_intr_pulse_counter` 展示了如何在主 CPU 处于 Deep-sleep 模式时，使用 GPIO 中断为脉冲计数。 + - :example:`system/ulp/lp_core/build_system/` 演示了如何为 ULP 应用程序添加自定义的 ``CMakeLists.txt`` 文件。 + - :example:`system/ulp/lp_core/debugging` 演示了如何使用 GDB 和 OpenOCD 来调试运行在 LP 内核上的代码。 API 参考 -------------- +-------- 主 CPU API 参考 -~~~~~~~~~~~~~~~~~~~~~~ +~~~~~~~~~~~~~~~ .. include-build-file:: inc/ulp_lp_core.inc .. include-build-file:: inc/lp_core_i2c.inc @@ -320,7 +400,7 @@ API 参考 .. include-build-file:: inc/lp_core_types.inc LP 内核 API 参考 -~~~~~~~~~~~~~~~~~~~~~~ +~~~~~~~~~~~~~~~~ .. include-build-file:: inc/ulp_lp_core_utils.inc .. include-build-file:: inc/ulp_lp_core_gpio.inc From 6f306e2dbde9ead3de2f158fe370e08a4037046a Mon Sep 17 00:00:00 2001 From: GengYuchao Date: Thu, 10 Oct 2024 14:42:17 +0800 Subject: [PATCH 089/472] feat: Enable direction finding feature in nimble host only mode --- components/bt/host/nimble/Kconfig.in | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/components/bt/host/nimble/Kconfig.in b/components/bt/host/nimble/Kconfig.in index cfde045be4d..6984cc02923 100644 --- a/components/bt/host/nimble/Kconfig.in +++ b/components/bt/host/nimble/Kconfig.in @@ -648,7 +648,7 @@ config BT_NIMBLE_PERIODIC_ADV_ENH config BT_NIMBLE_AOA_AOD bool "Direction Finding" - depends on BT_NIMBLE_50_FEATURE_SUPPORT && SOC_BLE_CTE_SUPPORTED + depends on BT_NIMBLE_50_FEATURE_SUPPORT && (BT_CONTROLLER_DISABLED || SOC_BLE_CTE_SUPPORTED) default n help Enable support for Connectionless and Connection Oriented Direction Finding From 611fb654ce44966c6e24f1e08d47ac0bc60adf19 Mon Sep 17 00:00:00 2001 From: morris Date: Sat, 21 Sep 2024 23:02:27 +0800 Subject: [PATCH 090/472] refactor(lcd): clean up GPIO initialization --- .../include/esp_private/gpio.h | 11 +++ components/esp_driver_gpio/src/gpio.c | 2 +- components/esp_lcd/Kconfig | 2 +- components/esp_lcd/i80/esp_lcd_panel_io_i2s.c | 30 ++++---- components/esp_lcd/i80/esp_lcd_panel_io_i80.c | 69 +++++++++---------- components/esp_lcd/include/esp_lcd_io_i80.h | 2 +- components/esp_lcd/linker.lf | 7 +- .../esp_lcd/priv_include/esp_lcd_common.h | 2 + components/esp_lcd/rgb/esp_lcd_panel_rgb.c | 38 +++++----- .../test_apps/rgb_lcd/sdkconfig.ci.iram_safe | 3 - 10 files changed, 81 insertions(+), 85 deletions(-) diff --git a/components/esp_driver_gpio/include/esp_private/gpio.h b/components/esp_driver_gpio/include/esp_private/gpio.h index b2186295c0a..2e06192f633 100644 --- a/components/esp_driver_gpio/include/esp_private/gpio.h +++ b/components/esp_driver_gpio/include/esp_private/gpio.h @@ -52,6 +52,17 @@ esp_err_t gpio_sleep_pupd_config_unapply(gpio_num_t gpio_num); */ esp_err_t gpio_func_sel(gpio_num_t gpio_num, uint32_t func); +/** + * @brief Enable output for an IO + * + * @param gpio_num GPIO number + * + * @return + * - ESP_OK Success + * - ESP_ERR_INVALID_ARG GPIO number error + */ +esp_err_t gpio_output_enable(gpio_num_t gpio_num); + /** * @brief Disable output for an IO * diff --git a/components/esp_driver_gpio/src/gpio.c b/components/esp_driver_gpio/src/gpio.c index cffca8e8e83..a63ab11375a 100644 --- a/components/esp_driver_gpio/src/gpio.c +++ b/components/esp_driver_gpio/src/gpio.c @@ -211,7 +211,7 @@ esp_err_t gpio_output_disable(gpio_num_t gpio_num) return ESP_OK; } -static esp_err_t gpio_output_enable(gpio_num_t gpio_num) +esp_err_t gpio_output_enable(gpio_num_t gpio_num) { GPIO_CHECK(GPIO_IS_VALID_OUTPUT_GPIO(gpio_num), "GPIO output gpio_num error", ESP_ERR_INVALID_ARG); gpio_hal_matrix_out_default(gpio_context.gpio_hal, gpio_num); // No peripheral output signal routed to the pin, just as a simple GPIO output diff --git a/components/esp_lcd/Kconfig b/components/esp_lcd/Kconfig index 1e6ee9407cb..76d9aaa8aef 100644 --- a/components/esp_lcd/Kconfig +++ b/components/esp_lcd/Kconfig @@ -12,6 +12,7 @@ menu "LCD and Touch Panel" if SOC_LCD_RGB_SUPPORTED config LCD_RGB_ISR_IRAM_SAFE bool "RGB LCD ISR IRAM-Safe" + select GDMA_ISR_IRAM_SAFE # bounce buffer mode relies on GDMA EOF interrupt default n help Ensure the LCD interrupt is IRAM-Safe by allowing the interrupt handler to be @@ -22,7 +23,6 @@ menu "LCD and Touch Panel" config LCD_RGB_RESTART_IN_VSYNC bool "Restart transmission in VSYNC" default n - select GDMA_CTRL_FUNC_IN_IRAM # need to restart GDMA in the LCD ISR help Reset the GDMA channel every VBlank to stop permanent desyncs from happening. Only need to enable it when in your application, the DMA can't deliver data diff --git a/components/esp_lcd/i80/esp_lcd_panel_io_i2s.c b/components/esp_lcd/i80/esp_lcd_panel_io_i2s.c index 0851381033e..e5cbf45a654 100644 --- a/components/esp_lcd/i80/esp_lcd_panel_io_i2s.c +++ b/components/esp_lcd/i80/esp_lcd_panel_io_i2s.c @@ -39,14 +39,12 @@ #include "esp_private/periph_ctrl.h" #include "esp_private/i2s_platform.h" #include "esp_private/gdma_link.h" +#include "esp_private/gpio.h" #include "soc/lcd_periph.h" #include "hal/i2s_hal.h" #include "hal/i2s_ll.h" #include "hal/i2s_types.h" -// the DMA descriptor used by esp32 and esp32s2, each descriptor can carry 4095 bytes at most -#define LCD_DMA_DESCRIPTOR_BUFFER_MAX_SIZE 4095 - static const char *TAG = "lcd_panel.io.i80"; typedef struct esp_lcd_i80_bus_t esp_lcd_i80_bus_t; @@ -61,7 +59,7 @@ static esp_err_t i2s_lcd_init_dma_link(esp_lcd_i80_bus_handle_t bus); static esp_err_t i2s_lcd_configure_gpio(esp_lcd_i80_bus_handle_t bus, const esp_lcd_i80_bus_config_t *bus_config); static void i2s_lcd_trigger_quick_trans_done_event(esp_lcd_i80_bus_handle_t bus); static void lcd_i80_switch_devices(lcd_panel_io_i80_t *cur_device, lcd_panel_io_i80_t *next_device); -static void lcd_default_isr_handler(void *args); +static void i2s_lcd_default_isr_handler(void *args); static esp_err_t panel_io_i80_register_event_callbacks(esp_lcd_panel_io_handle_t io, const esp_lcd_panel_io_callbacks_t *cbs, void *user_ctx); struct esp_lcd_i80_bus_t { @@ -188,7 +186,7 @@ esp_err_t esp_lcd_new_i80_bus(const esp_lcd_i80_bus_config_t *bus_config, esp_lc int isr_flags = LCD_I80_INTR_ALLOC_FLAGS | ESP_INTR_FLAG_SHARED | ESP_INTR_FLAG_LOWMED; ret = esp_intr_alloc_intrstatus(lcd_periph_i2s_signals.buses[bus->bus_id].irq_id, isr_flags, (uint32_t)i2s_ll_get_intr_status_reg(bus->hal.dev), - I2S_LL_EVENT_TX_EOF, lcd_default_isr_handler, bus, &bus->intr); + I2S_LL_EVENT_TX_EOF, i2s_lcd_default_isr_handler, bus, &bus->intr); ESP_GOTO_ON_ERROR(ret, err, TAG, "install interrupt failed"); i2s_ll_enable_intr(bus->hal.dev, I2S_LL_EVENT_TX_EOF, false); // disable interrupt temporarily i2s_ll_clear_intr_status(bus->hal.dev, I2S_LL_EVENT_TX_EOF); // clear pending interrupt @@ -317,8 +315,8 @@ esp_err_t esp_lcd_new_panel_io_i80(esp_lcd_i80_bus_handle_t bus, const esp_lcd_p if (io_config->cs_gpio_num >= 0) { // CS signal is controlled by software gpio_set_level(io_config->cs_gpio_num, !io_config->flags.cs_active_high); // de-assert by default - gpio_set_direction(io_config->cs_gpio_num, GPIO_MODE_OUTPUT); - gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[io_config->cs_gpio_num], PIN_FUNC_GPIO); + gpio_func_sel(io_config->cs_gpio_num, PIN_FUNC_GPIO); + gpio_output_enable(io_config->cs_gpio_num); } *ret_io = &(i80_device->base); ESP_LOGD(TAG, "new i80 lcd panel io @%p on bus(%d), pclk=%"PRIu32"Hz", i80_device, bus->bus_id, i80_device->pclk_hz); @@ -362,9 +360,8 @@ static esp_err_t panel_io_i80_del(esp_lcd_panel_io_t *io) LIST_REMOVE(i80_device, device_list_entry); portEXIT_CRITICAL(&bus->spinlock); - // reset CS GPIO if (i80_device->cs_gpio_num >= 0) { - gpio_reset_pin(i80_device->cs_gpio_num); + gpio_output_disable(i80_device->cs_gpio_num); } ESP_LOGD(TAG, "del i80 lcd panel io @%p", i80_device); @@ -648,7 +645,7 @@ static esp_err_t panel_io_i80_tx_color(esp_lcd_panel_io_t *io, int lcd_cmd, cons xQueueSend(next_device->trans_queue, &trans_desc, portMAX_DELAY); next_device->num_trans_inflight++; // enable interrupt and go into isr handler, where we fetch the transactions from trans_queue and start it - // we will go into `lcd_default_isr_handler` almost at once, because the "trans done" event is active at the moment + // we will go into `i2s_lcd_default_isr_handler` almost at once, because the "trans done" event is active at the moment esp_intr_enable(bus->intr); return ESP_OK; } @@ -698,21 +695,20 @@ static esp_err_t i2s_lcd_configure_gpio(esp_lcd_i80_bus_handle_t bus, const esp_ // connect peripheral signals via GPIO matrix // data line for (size_t i = 0; i < bus_config->bus_width; i++) { - gpio_set_direction(bus_config->data_gpio_nums[i], GPIO_MODE_OUTPUT); + gpio_func_sel(bus_config->data_gpio_nums[i], PIN_FUNC_GPIO); + // the esp_rom_gpio_connect_out_signal function will also help enable the output path properly #if SOC_I2S_TRANS_SIZE_ALIGN_WORD esp_rom_gpio_connect_out_signal(bus_config->data_gpio_nums[i], lcd_periph_i2s_signals.buses[bus_id].data_sigs[i + 8], false, false); #else esp_rom_gpio_connect_out_signal(bus_config->data_gpio_nums[i], lcd_periph_i2s_signals.buses[bus_id].data_sigs[i + SOC_I2S_MAX_DATA_WIDTH - bus_config->bus_width], false, false); #endif - gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[bus_config->data_gpio_nums[i]], PIN_FUNC_GPIO); } // WR signal (pclk) - gpio_set_direction(bus_config->wr_gpio_num, GPIO_MODE_OUTPUT); + gpio_func_sel(bus_config->wr_gpio_num, PIN_FUNC_GPIO); esp_rom_gpio_connect_out_signal(bus_config->wr_gpio_num, lcd_periph_i2s_signals.buses[bus_id].wr_sig, true, false); - gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[bus_config->wr_gpio_num], PIN_FUNC_GPIO); // DC signal is controlled by software, set as general purpose IO - gpio_set_direction(bus_config->dc_gpio_num, GPIO_MODE_OUTPUT); - gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[bus_config->dc_gpio_num], PIN_FUNC_GPIO); + gpio_func_sel(bus_config->dc_gpio_num, PIN_FUNC_GPIO); + gpio_output_enable(bus_config->dc_gpio_num); return ESP_OK; } @@ -756,7 +752,7 @@ static void lcd_i80_switch_devices(lcd_panel_io_i80_t *cur_device, lcd_panel_io_ bus->cur_device = next_device; } -static IRAM_ATTR void lcd_default_isr_handler(void *args) +static IRAM_ATTR void i2s_lcd_default_isr_handler(void *args) { esp_lcd_i80_bus_t *bus = (esp_lcd_i80_bus_t *)args; lcd_i80_trans_descriptor_t *trans_desc = NULL; diff --git a/components/esp_lcd/i80/esp_lcd_panel_io_i80.c b/components/esp_lcd/i80/esp_lcd_panel_io_i80.c index 96b8fb4ca8b..d7a29f44504 100644 --- a/components/esp_lcd/i80/esp_lcd_panel_io_i80.c +++ b/components/esp_lcd/i80/esp_lcd_panel_io_i80.c @@ -43,8 +43,6 @@ #include "hal/cache_ll.h" #include "hal/cache_hal.h" -#define LCD_DMA_DESCRIPTOR_BUFFER_MAX_SIZE 4095 - #if defined(SOC_GDMA_TRIG_PERIPH_LCD0_BUS) && (SOC_GDMA_TRIG_PERIPH_LCD0_BUS == SOC_GDMA_BUS_AHB) #define LCD_GDMA_NEW_CHANNEL gdma_new_ahb_channel #define LCD_GDMA_DESCRIPTOR_ALIGN 4 @@ -76,7 +74,7 @@ static esp_err_t lcd_i80_select_periph_clock(esp_lcd_i80_bus_handle_t bus, lcd_c static esp_err_t lcd_i80_bus_configure_gpio(esp_lcd_i80_bus_handle_t bus, const esp_lcd_i80_bus_config_t *bus_config); static void lcd_i80_switch_devices(lcd_panel_io_i80_t *cur_device, lcd_panel_io_i80_t *next_device); static void lcd_start_transaction(esp_lcd_i80_bus_t *bus, lcd_i80_trans_descriptor_t *trans_desc); -static void lcd_default_isr_handler(void *args); +static void i80_lcd_default_isr_handler(void *args); static esp_err_t panel_io_i80_register_event_callbacks(esp_lcd_panel_io_handle_t io, const esp_lcd_panel_io_callbacks_t *cbs, void *user_ctx); struct esp_lcd_i80_bus_t { @@ -157,18 +155,6 @@ esp_err_t esp_lcd_new_i80_bus(const esp_lcd_i80_bus_config_t *bus_config, esp_lc // allocate i80 bus memory bus = heap_caps_calloc(1, sizeof(esp_lcd_i80_bus_t), LCD_I80_MEM_ALLOC_CAPS); ESP_GOTO_ON_FALSE(bus, ESP_ERR_NO_MEM, err, TAG, "no mem for i80 bus"); - size_t num_dma_nodes = bus_config->max_transfer_bytes / LCD_DMA_DESCRIPTOR_BUFFER_MAX_SIZE + 1; - // create DMA link list - gdma_link_list_config_t dma_link_config = { - .buffer_alignment = 1, // no special buffer alignment for LCD TX buffer - .item_alignment = LCD_GDMA_DESCRIPTOR_ALIGN, - .num_items = num_dma_nodes, - .flags = { - .check_owner = true, - }, - }; - ESP_GOTO_ON_ERROR(gdma_new_link_list(&dma_link_config, &bus->dma_link), err, TAG, "create DMA link list failed"); - bus->num_dma_nodes = num_dma_nodes; bus->bus_width = bus_config->bus_width; bus->bus_id = -1; // allocate the format buffer from internal memory, with DMA capability @@ -208,7 +194,7 @@ esp_err_t esp_lcd_new_i80_bus(const esp_lcd_i80_bus_config_t *bus_config, esp_lc int isr_flags = LCD_I80_INTR_ALLOC_FLAGS | ESP_INTR_FLAG_SHARED | ESP_INTR_FLAG_LOWMED; ret = esp_intr_alloc_intrstatus(lcd_periph_i80_signals.buses[bus_id].irq_id, isr_flags, (uint32_t)lcd_ll_get_interrupt_status_reg(bus->hal.dev), - LCD_LL_EVENT_TRANS_DONE, lcd_default_isr_handler, bus, &bus->intr); + LCD_LL_EVENT_TRANS_DONE, i80_lcd_default_isr_handler, bus, &bus->intr); ESP_GOTO_ON_ERROR(ret, err, TAG, "install interrupt failed"); lcd_ll_enable_interrupt(bus->hal.dev, LCD_LL_EVENT_TRANS_DONE, false); // disable all interrupts lcd_ll_clear_interrupt_status(bus->hal.dev, UINT32_MAX); // clear pending interrupt @@ -355,9 +341,10 @@ esp_err_t esp_lcd_new_panel_io_i80(esp_lcd_i80_bus_handle_t bus, const esp_lcd_p // we only configure the CS GPIO as output, don't connect to the peripheral signal at the moment // we will connect the CS GPIO to peripheral signal when switching devices in lcd_i80_switch_devices() if (io_config->cs_gpio_num >= 0) { - gpio_set_level(io_config->cs_gpio_num, !io_config->flags.cs_active_high); - gpio_set_direction(io_config->cs_gpio_num, GPIO_MODE_OUTPUT); + // CS signal is controlled by software + gpio_set_level(io_config->cs_gpio_num, !io_config->flags.cs_active_high); // de-assert by default gpio_func_sel(io_config->cs_gpio_num, PIN_FUNC_GPIO); + gpio_output_enable(io_config->cs_gpio_num); } *ret_io = &(i80_device->base); ESP_LOGD(TAG, "new i80 lcd panel io @%p on bus(%d)", i80_device, bus->bus_id); @@ -393,9 +380,8 @@ static esp_err_t panel_io_i80_del(esp_lcd_panel_io_t *io) LIST_REMOVE(i80_device, device_list_entry); portEXIT_CRITICAL(&bus->spinlock); - // reset CS to normal GPIO if (i80_device->cs_gpio_num >= 0) { - gpio_reset_pin(i80_device->cs_gpio_num); + gpio_output_disable(i80_device->cs_gpio_num); } ESP_LOGD(TAG, "del i80 lcd panel io @%p", i80_device); @@ -572,7 +558,7 @@ static esp_err_t panel_io_i80_tx_color(esp_lcd_panel_io_t *io, int lcd_cmd, cons xQueueSend(i80_device->trans_queue, &trans_desc, portMAX_DELAY); i80_device->num_trans_inflight++; // enable interrupt and go into isr handler, where we fetch the transactions from trans_queue and start it - // we will go into `lcd_default_isr_handler` almost at once, because the "trans done" event is active at the moment + // we will go into `i80_lcd_default_isr_handler` almost at once, because the "trans done" event is active at the moment esp_intr_enable(bus->intr); return ESP_OK; } @@ -609,7 +595,7 @@ static esp_err_t lcd_i80_init_dma_link(esp_lcd_i80_bus_handle_t bus, const esp_l .direction = GDMA_CHANNEL_DIRECTION_TX, }; ret = LCD_GDMA_NEW_CHANNEL(&dma_chan_config, &bus->dma_chan); - ESP_GOTO_ON_ERROR(ret, err, TAG, "alloc DMA channel failed"); + ESP_RETURN_ON_ERROR(ret, TAG, "alloc DMA channel failed"); gdma_connect(bus->dma_chan, GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_LCD, 0)); gdma_strategy_config_t strategy_config = { .auto_update_desc = true, @@ -621,14 +607,23 @@ static esp_err_t lcd_i80_init_dma_link(esp_lcd_i80_bus_handle_t bus, const esp_l .max_data_burst_size = bus_config->dma_burst_size ? bus_config->dma_burst_size : 16, // Enable DMA burst transfer for better performance .access_ext_mem = true, // the LCD can carry pixel buffer from the external memory }; - ESP_GOTO_ON_ERROR(gdma_config_transfer(bus->dma_chan, &trans_cfg), err, TAG, "config DMA transfer failed"); + ESP_RETURN_ON_ERROR(gdma_config_transfer(bus->dma_chan, &trans_cfg), TAG, "config DMA transfer failed"); gdma_get_alignment_constraints(bus->dma_chan, &bus->int_mem_align, &bus->ext_mem_align); + + size_t num_dma_nodes = bus_config->max_transfer_bytes / LCD_DMA_DESCRIPTOR_BUFFER_MAX_SIZE + 1; + // create DMA link list + gdma_link_list_config_t dma_link_config = { + .buffer_alignment = MAX(bus->int_mem_align, bus->ext_mem_align), + .item_alignment = LCD_GDMA_DESCRIPTOR_ALIGN, + .num_items = num_dma_nodes, + .flags = { + .check_owner = true, + }, + }; + ESP_RETURN_ON_ERROR(gdma_new_link_list(&dma_link_config, &bus->dma_link), TAG, "create DMA link list failed"); + bus->num_dma_nodes = num_dma_nodes; + return ESP_OK; -err: - if (bus->dma_chan) { - gdma_del_channel(bus->dma_chan); - } - return ret; } void *esp_lcd_i80_alloc_draw_buffer(esp_lcd_panel_io_handle_t io, size_t size, uint32_t caps) @@ -660,17 +655,18 @@ static esp_err_t lcd_i80_bus_configure_gpio(esp_lcd_i80_bus_handle_t bus, const // Set the number of output data lines lcd_ll_set_data_wire_width(bus->hal.dev, bus_config->bus_width); // connect peripheral signals via GPIO matrix + // data lines for (size_t i = 0; i < bus_config->bus_width; i++) { - gpio_set_direction(bus_config->data_gpio_nums[i], GPIO_MODE_OUTPUT); - esp_rom_gpio_connect_out_signal(bus_config->data_gpio_nums[i], lcd_periph_i80_signals.buses[bus_id].data_sigs[i], false, false); gpio_func_sel(bus_config->data_gpio_nums[i], PIN_FUNC_GPIO); + // the esp_rom_gpio_connect_out_signal function will also help enable the output path properly + esp_rom_gpio_connect_out_signal(bus_config->data_gpio_nums[i], lcd_periph_i80_signals.buses[bus_id].data_sigs[i], false, false); } - gpio_set_direction(bus_config->dc_gpio_num, GPIO_MODE_OUTPUT); - esp_rom_gpio_connect_out_signal(bus_config->dc_gpio_num, lcd_periph_i80_signals.buses[bus_id].dc_sig, false, false); + // D/C signal gpio_func_sel(bus_config->dc_gpio_num, PIN_FUNC_GPIO); - gpio_set_direction(bus_config->wr_gpio_num, GPIO_MODE_OUTPUT); - esp_rom_gpio_connect_out_signal(bus_config->wr_gpio_num, lcd_periph_i80_signals.buses[bus_id].wr_sig, false, false); + esp_rom_gpio_connect_out_signal(bus_config->dc_gpio_num, lcd_periph_i80_signals.buses[bus_id].dc_sig, false, false); + // WR signal (PCLK) gpio_func_sel(bus_config->wr_gpio_num, PIN_FUNC_GPIO); + esp_rom_gpio_connect_out_signal(bus_config->wr_gpio_num, lcd_periph_i80_signals.buses[bus_id].wr_sig, false, false); return ESP_OK; } @@ -722,8 +718,7 @@ static void lcd_i80_switch_devices(lcd_panel_io_i80_t *cur_device, lcd_panel_io_ lcd_ll_set_dc_level(bus->hal.dev, next_device->dc_levels.dc_idle_level, next_device->dc_levels.dc_cmd_level, next_device->dc_levels.dc_dummy_level, next_device->dc_levels.dc_data_level); if (cur_device && cur_device->cs_gpio_num >= 0) { - // disconnect current CS GPIO from peripheral signal - esp_rom_gpio_connect_out_signal(cur_device->cs_gpio_num, SIG_GPIO_OUT_IDX, false, false); + gpio_output_disable(cur_device->cs_gpio_num); } if (next_device->cs_gpio_num >= 0) { // connect CS signal to the new device @@ -733,7 +728,7 @@ static void lcd_i80_switch_devices(lcd_panel_io_i80_t *cur_device, lcd_panel_io_ } } -IRAM_ATTR static void lcd_default_isr_handler(void *args) +IRAM_ATTR static void i80_lcd_default_isr_handler(void *args) { esp_lcd_i80_bus_t *bus = (esp_lcd_i80_bus_t *)args; lcd_i80_trans_descriptor_t *trans_desc = NULL; diff --git a/components/esp_lcd/include/esp_lcd_io_i80.h b/components/esp_lcd/include/esp_lcd_io_i80.h index 7b6bd90422f..f2885390f5f 100644 --- a/components/esp_lcd/include/esp_lcd_io_i80.h +++ b/components/esp_lcd/include/esp_lcd_io_i80.h @@ -30,7 +30,7 @@ typedef struct { size_t bus_width; /*!< Number of data lines, 8 or 16 */ size_t max_transfer_bytes; /*!< Maximum transfer size, this determines the length of internal DMA link */ union { - size_t psram_trans_align; /*!< DMA transfer alignment for data allocated from PSRAM */ + size_t psram_trans_align __attribute__((deprecated)); /*!< DMA transfer alignment for data allocated from PSRAM */ size_t dma_burst_size; /*!< DMA burst size, in bytes */ }; size_t sram_trans_align __attribute__((deprecated)); /*!< DMA transfer alignment for data allocated from SRAM */ diff --git a/components/esp_lcd/linker.lf b/components/esp_lcd/linker.lf index 6e3aa0d3cda..513429d536e 100644 --- a/components/esp_lcd/linker.lf +++ b/components/esp_lcd/linker.lf @@ -1,8 +1,9 @@ -[mapping:esp_lcd_driver] -archive: libesp_lcd.a +[mapping:esp_lcd_gdma] +archive: libesp_hw_support.a entries: if LCD_RGB_ISR_IRAM_SAFE = y: - esp_lcd_common: lcd_com_mount_dma_data (noflash) + gdma: gdma_reset (noflash) + gdma: gdma_start (noflash) [mapping:esp_lcd_hal] archive: libhal.a diff --git a/components/esp_lcd/priv_include/esp_lcd_common.h b/components/esp_lcd/priv_include/esp_lcd_common.h index a7b8ae6161e..b57d37a787c 100644 --- a/components/esp_lcd/priv_include/esp_lcd_common.h +++ b/components/esp_lcd/priv_include/esp_lcd_common.h @@ -33,6 +33,8 @@ extern "C" { #define LCD_CLOCK_SRC_ATOMIC() #endif +#define LCD_DMA_DESCRIPTOR_BUFFER_MAX_SIZE 4095 + #if SOC_LCDCAM_SUPPORTED typedef enum { diff --git a/components/esp_lcd/rgb/esp_lcd_panel_rgb.c b/components/esp_lcd/rgb/esp_lcd_panel_rgb.c index 60165fc1c53..f105ddf7cc4 100644 --- a/components/esp_lcd/rgb/esp_lcd_panel_rgb.c +++ b/components/esp_lcd/rgb/esp_lcd_panel_rgb.c @@ -28,17 +28,17 @@ #include "soc/soc_caps.h" #include "esp_clk_tree.h" #include "hal/dma_types.h" -#include "hal/gpio_hal.h" #include "esp_private/gdma.h" #include "driver/gpio.h" #include "esp_bit_defs.h" #include "esp_private/esp_clk_tree_common.h" #include "esp_private/periph_ctrl.h" +#include "esp_private/gpio.h" #include "esp_psram.h" #include "esp_lcd_common.h" #include "esp_memory_utils.h" #include "soc/lcd_periph.h" -#include "soc/soc_caps.h" +#include "soc/io_mux_reg.h" #include "hal/lcd_hal.h" #include "hal/lcd_ll.h" #include "hal/cache_hal.h" @@ -84,7 +84,7 @@ static esp_err_t lcd_rgb_create_dma_channel(esp_rgb_panel_t *panel); static void lcd_rgb_panel_init_trans_link(esp_rgb_panel_t *panel); static esp_err_t lcd_rgb_panel_configure_gpio(esp_rgb_panel_t *panel, const esp_lcd_rgb_panel_config_t *panel_config); static void lcd_rgb_panel_start_transmission(esp_rgb_panel_t *rgb_panel); -static void lcd_default_isr_handler(void *args); +static void rgb_lcd_default_isr_handler(void *args); struct esp_rgb_panel_t { esp_lcd_panel_t base; // Base class of generic lcd panel @@ -336,7 +336,7 @@ esp_err_t esp_lcd_new_rgb_panel(const esp_lcd_rgb_panel_config_t *rgb_panel_conf int isr_flags = LCD_RGB_INTR_ALLOC_FLAGS | ESP_INTR_FLAG_SHARED | ESP_INTR_FLAG_LOWMED; ret = esp_intr_alloc_intrstatus(lcd_periph_rgb_signals.panels[panel_id].irq_id, isr_flags, (uint32_t)lcd_ll_get_interrupt_status_reg(rgb_panel->hal.dev), - LCD_LL_EVENT_VSYNC_END, lcd_default_isr_handler, rgb_panel, &rgb_panel->intr); + LCD_LL_EVENT_VSYNC_END, rgb_lcd_default_isr_handler, rgb_panel, &rgb_panel->intr); ESP_GOTO_ON_ERROR(ret, err, TAG, "install interrupt failed"); lcd_ll_enable_interrupt(rgb_panel->hal.dev, LCD_LL_EVENT_VSYNC_END, false); // disable all interrupts lcd_ll_clear_interrupt_status(rgb_panel->hal.dev, UINT32_MAX); // clear pending interrupt @@ -848,51 +848,45 @@ static esp_err_t rgb_panel_disp_on_off(esp_lcd_panel_t *panel, bool on_off) return ESP_OK; } -static esp_err_t lcd_rgb_panel_configure_gpio(esp_rgb_panel_t *panel, const esp_lcd_rgb_panel_config_t *panel_config) +static esp_err_t lcd_rgb_panel_configure_gpio(esp_rgb_panel_t *rgb_panel, const esp_lcd_rgb_panel_config_t *panel_config) { - int panel_id = panel->panel_id; + int panel_id = rgb_panel->panel_id; // Set the number of output data lines - lcd_ll_set_data_wire_width(panel->hal.dev, panel_config->data_width); + lcd_ll_set_data_wire_width(rgb_panel->hal.dev, panel_config->data_width); // connect peripheral signals via GPIO matrix for (size_t i = 0; i < panel_config->data_width; i++) { if (panel_config->data_gpio_nums[i] >= 0) { - gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[panel_config->data_gpio_nums[i]], PIN_FUNC_GPIO); - gpio_set_direction(panel_config->data_gpio_nums[i], GPIO_MODE_OUTPUT); + gpio_func_sel(panel_config->data_gpio_nums[i], PIN_FUNC_GPIO); esp_rom_gpio_connect_out_signal(panel_config->data_gpio_nums[i], lcd_periph_rgb_signals.panels[panel_id].data_sigs[i], false, false); } } if (panel_config->hsync_gpio_num >= 0) { - gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[panel_config->hsync_gpio_num], PIN_FUNC_GPIO); - gpio_set_direction(panel_config->hsync_gpio_num, GPIO_MODE_OUTPUT); + gpio_func_sel(panel_config->hsync_gpio_num, PIN_FUNC_GPIO); esp_rom_gpio_connect_out_signal(panel_config->hsync_gpio_num, lcd_periph_rgb_signals.panels[panel_id].hsync_sig, false, false); } if (panel_config->vsync_gpio_num >= 0) { - gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[panel_config->vsync_gpio_num], PIN_FUNC_GPIO); - gpio_set_direction(panel_config->vsync_gpio_num, GPIO_MODE_OUTPUT); + gpio_func_sel(panel_config->vsync_gpio_num, PIN_FUNC_GPIO); esp_rom_gpio_connect_out_signal(panel_config->vsync_gpio_num, lcd_periph_rgb_signals.panels[panel_id].vsync_sig, false, false); } // PCLK may not be necessary in some cases (i.e. VGA output) if (panel_config->pclk_gpio_num >= 0) { - gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[panel_config->pclk_gpio_num], PIN_FUNC_GPIO); - gpio_set_direction(panel_config->pclk_gpio_num, GPIO_MODE_OUTPUT); + gpio_func_sel(panel_config->pclk_gpio_num, PIN_FUNC_GPIO); esp_rom_gpio_connect_out_signal(panel_config->pclk_gpio_num, lcd_periph_rgb_signals.panels[panel_id].pclk_sig, false, false); } // DE signal might not be necessary for some RGB LCD if (panel_config->de_gpio_num >= 0) { - gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[panel_config->de_gpio_num], PIN_FUNC_GPIO); - gpio_set_direction(panel_config->de_gpio_num, GPIO_MODE_OUTPUT); + gpio_func_sel(panel_config->de_gpio_num, PIN_FUNC_GPIO); esp_rom_gpio_connect_out_signal(panel_config->de_gpio_num, lcd_periph_rgb_signals.panels[panel_id].de_sig, false, false); } - // disp enable GPIO is optional + // disp enable GPIO is optional, it is a general purpose output GPIO if (panel_config->disp_gpio_num >= 0) { - gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[panel_config->disp_gpio_num], PIN_FUNC_GPIO); - gpio_set_direction(panel_config->disp_gpio_num, GPIO_MODE_OUTPUT); - esp_rom_gpio_connect_out_signal(panel_config->disp_gpio_num, SIG_GPIO_OUT_IDX, false, false); + gpio_func_sel(panel_config->disp_gpio_num, PIN_FUNC_GPIO); + gpio_output_enable(panel_config->disp_gpio_num); } return ESP_OK; } @@ -1147,7 +1141,7 @@ IRAM_ATTR static void lcd_rgb_panel_try_update_pclk(esp_rgb_panel_t *rgb_panel) portEXIT_CRITICAL_ISR(&rgb_panel->spinlock); } -IRAM_ATTR static void lcd_default_isr_handler(void *args) +IRAM_ATTR static void rgb_lcd_default_isr_handler(void *args) { esp_rgb_panel_t *rgb_panel = (esp_rgb_panel_t *)args; bool need_yield = false; diff --git a/components/esp_lcd/test_apps/rgb_lcd/sdkconfig.ci.iram_safe b/components/esp_lcd/test_apps/rgb_lcd/sdkconfig.ci.iram_safe index 0643ce8884a..a0efad79df1 100644 --- a/components/esp_lcd/test_apps/rgb_lcd/sdkconfig.ci.iram_safe +++ b/components/esp_lcd/test_apps/rgb_lcd/sdkconfig.ci.iram_safe @@ -1,8 +1,5 @@ CONFIG_COMPILER_DUMP_RTL_FILES=y CONFIG_LCD_RGB_ISR_IRAM_SAFE=y -CONFIG_GDMA_CTRL_FUNC_IN_IRAM=y -# bounce buffer mode relies on GDMA EOF interrupt to be service-able -CONFIG_GDMA_ISR_IRAM_SAFE=y CONFIG_COMPILER_OPTIMIZATION_NONE=y # silent the error check, as the error string are stored in rodata, causing RTL check failure CONFIG_COMPILER_OPTIMIZATION_CHECKS_SILENT=y From d6ac628f7ae9d354f5672d1ae0e3eb71a7f82d4b Mon Sep 17 00:00:00 2001 From: morris Date: Thu, 10 Oct 2024 15:56:55 +0800 Subject: [PATCH 091/472] change(esp_rom): comment out conflict gpio functions The GPIO function names has conflict with the public API used by esp_driver_gpio component. For now, we simply comment out the conflict ones. Later, we should consider reusing the GPIO rom APIs. --- components/esp_rom/esp32c2/ld/esp32c2.rom.ld | 4 ++-- components/esp_rom/esp32c3/ld/esp32c3.rom.ld | 4 ++-- components/esp_rom/esp32c5/ld/esp32c5.rom.ld | 4 ++-- components/esp_rom/esp32c6/ld/esp32c6.rom.ld | 4 ++-- components/esp_rom/esp32c61/ld/esp32c61.rom.ld | 4 ++-- components/esp_rom/esp32h2/ld/esp32h2.rom.ld | 4 ++-- components/esp_rom/esp32p4/ld/esp32p4.rom.ld | 4 ++-- components/esp_rom/esp32p4/ld/esp32p4lp.rom.ld | 4 ++-- components/esp_rom/esp32s3/ld/esp32s3.rom.ld | 4 ++-- 9 files changed, 18 insertions(+), 18 deletions(-) diff --git a/components/esp_rom/esp32c2/ld/esp32c2.rom.ld b/components/esp_rom/esp32c2/ld/esp32c2.rom.ld index 5aad6135888..dd40a0253b9 100644 --- a/components/esp_rom/esp32c2/ld/esp32c2.rom.ld +++ b/components/esp_rom/esp32c2/ld/esp32c2.rom.ld @@ -361,8 +361,8 @@ ets_get_xtal_freq = 0x40000784; gpio_input_get = 0x40000788; gpio_matrix_in = 0x4000078c; gpio_matrix_out = 0x40000790; -gpio_output_disable = 0x40000794; -gpio_output_enable = 0x40000798; +/* gpio_output_disable = 0x40000794; */ +/* gpio_output_enable = 0x40000798; */ gpio_output_set = 0x4000079c; gpio_pad_hold = 0x400007a0; gpio_pad_input_disable = 0x400007a4; diff --git a/components/esp_rom/esp32c3/ld/esp32c3.rom.ld b/components/esp_rom/esp32c3/ld/esp32c3.rom.ld index 559f5cade6e..1299d2f21a6 100644 --- a/components/esp_rom/esp32c3/ld/esp32c3.rom.ld +++ b/components/esp_rom/esp32c3/ld/esp32c3.rom.ld @@ -366,8 +366,8 @@ ets_get_xtal_freq = 0x40000598; gpio_input_get = 0x4000059c; gpio_matrix_in = 0x400005a0; gpio_matrix_out = 0x400005a4; -gpio_output_disable = 0x400005a8; -gpio_output_enable = 0x400005ac; +/* gpio_output_disable = 0x400005a8; */ +/* gpio_output_enable = 0x400005ac; */ gpio_output_set = 0x400005b0; gpio_pad_hold = 0x400005b4; gpio_pad_input_disable = 0x400005b8; diff --git a/components/esp_rom/esp32c5/ld/esp32c5.rom.ld b/components/esp_rom/esp32c5/ld/esp32c5.rom.ld index 3f5b833a297..7f5148d682f 100644 --- a/components/esp_rom/esp32c5/ld/esp32c5.rom.ld +++ b/components/esp_rom/esp32c5/ld/esp32c5.rom.ld @@ -258,8 +258,8 @@ gpio_get_input_level = 0x4000070c; gpio_matrix_in = 0x40000710; gpio_matrix_out = 0x40000714; gpio_bypass_matrix_in = 0x40000718; -gpio_output_disable = 0x4000071c; -gpio_output_enable = 0x40000720; +/* gpio_output_disable = 0x4000071c; */ +/* gpio_output_enable = 0x40000720; */ gpio_pad_input_disable = 0x40000724; gpio_pad_input_enable = 0x40000728; gpio_pad_pulldown = 0x4000072c; diff --git a/components/esp_rom/esp32c6/ld/esp32c6.rom.ld b/components/esp_rom/esp32c6/ld/esp32c6.rom.ld index f8ea9d4d3e4..2af963d5087 100644 --- a/components/esp_rom/esp32c6/ld/esp32c6.rom.ld +++ b/components/esp_rom/esp32c6/ld/esp32c6.rom.ld @@ -238,8 +238,8 @@ ets_clk_mspi_apb_wait_ready = 0x400006d0; gpio_input_get = 0x400006d4; gpio_matrix_in = 0x400006d8; gpio_matrix_out = 0x400006dc; -gpio_output_disable = 0x400006e0; -gpio_output_enable = 0x400006e4; +/* gpio_output_disable = 0x400006e0; */ +/* gpio_output_enable = 0x400006e4; */ gpio_output_set = 0x400006e8; gpio_pad_hold = 0x400006ec; gpio_pad_input_disable = 0x400006f0; diff --git a/components/esp_rom/esp32c61/ld/esp32c61.rom.ld b/components/esp_rom/esp32c61/ld/esp32c61.rom.ld index 7ef283388df..645b536924c 100644 --- a/components/esp_rom/esp32c61/ld/esp32c61.rom.ld +++ b/components/esp_rom/esp32c61/ld/esp32c61.rom.ld @@ -260,8 +260,8 @@ gpio_get_input_level = 0x400006f0; gpio_matrix_in = 0x400006f4; gpio_matrix_out = 0x400006f8; gpio_bypass_matrix_in = 0x400006fc; -gpio_output_disable = 0x40000700; -gpio_output_enable = 0x40000704; +/* gpio_output_disable = 0x40000700; */ +/* gpio_output_enable = 0x40000704; */ gpio_pad_input_disable = 0x40000708; gpio_pad_input_enable = 0x4000070c; gpio_pad_pulldown = 0x40000710; diff --git a/components/esp_rom/esp32h2/ld/esp32h2.rom.ld b/components/esp_rom/esp32h2/ld/esp32h2.rom.ld index 8000e80f1c2..b7b8775614e 100644 --- a/components/esp_rom/esp32h2/ld/esp32h2.rom.ld +++ b/components/esp_rom/esp32h2/ld/esp32h2.rom.ld @@ -226,8 +226,8 @@ ets_clk_get_cpu_freq = 0x4000069c; gpio_input_get = 0x400006a0; gpio_matrix_in = 0x400006a4; gpio_matrix_out = 0x400006a8; -gpio_output_disable = 0x400006ac; -gpio_output_enable = 0x400006b0; +/* gpio_output_disable = 0x400006ac; */ +/* gpio_output_enable = 0x400006b0; */ gpio_output_set = 0x400006b4; gpio_pad_hold = 0x400006b8; gpio_pad_input_disable = 0x400006bc; diff --git a/components/esp_rom/esp32p4/ld/esp32p4.rom.ld b/components/esp_rom/esp32p4/ld/esp32p4.rom.ld index 6b8f14bf60e..1ddf2b79451 100644 --- a/components/esp_rom/esp32p4/ld/esp32p4.rom.ld +++ b/components/esp_rom/esp32p4/ld/esp32p4.rom.ld @@ -301,8 +301,8 @@ gpio_get_input_level = 0x4fc00568; gpio_matrix_in = 0x4fc0056c; gpio_matrix_out = 0x4fc00570; gpio_bypass_matrix_in = 0x4fc00574; -gpio_output_disable = 0x4fc00578; -gpio_output_enable = 0x4fc0057c; +/* gpio_output_disable = 0x4fc00578; */ +/* gpio_output_enable = 0x4fc0057c; */ gpio_pad_input_disable = 0x4fc00580; gpio_pad_input_enable = 0x4fc00584; gpio_pad_pulldown = 0x4fc00588; diff --git a/components/esp_rom/esp32p4/ld/esp32p4lp.rom.ld b/components/esp_rom/esp32p4/ld/esp32p4lp.rom.ld index ad9dbf3971b..7fba13bd4bd 100644 --- a/components/esp_rom/esp32p4/ld/esp32p4lp.rom.ld +++ b/components/esp_rom/esp32p4/ld/esp32p4lp.rom.ld @@ -44,8 +44,8 @@ gpio_matrix_in = 0x501000d4; gpio_matrix_out = 0x501000d8; gpio_bypass_matrix_in = 0x501000dc; gpio_output_disable = 0x501000e0; -gpio_output_enable = 0x501000e4; -gpio_pad_input_disable = 0x501000e8; +/* gpio_output_enable = 0x501000e4; */ +/* gpio_pad_input_disable = 0x501000e8; */ gpio_pad_input_enable = 0x501000ec; gpio_pad_pulldown = 0x501000f0; gpio_pad_pullup = 0x501000f4; diff --git a/components/esp_rom/esp32s3/ld/esp32s3.rom.ld b/components/esp_rom/esp32s3/ld/esp32s3.rom.ld index a8818575a66..0b277966fa0 100644 --- a/components/esp_rom/esp32s3/ld/esp32s3.rom.ld +++ b/components/esp_rom/esp32s3/ld/esp32s3.rom.ld @@ -458,8 +458,8 @@ ets_get_xtal_freq = 0x40001a7c; gpio_input_get = 0x40001a88; gpio_matrix_in = 0x40001a94; gpio_matrix_out = 0x40001aa0; -gpio_output_disable = 0x40001aac; -gpio_output_enable = 0x40001ab8; +/* gpio_output_disable = 0x40001aac; */ +/* gpio_output_enable = 0x40001ab8; */ gpio_output_set = 0x40001ac4; gpio_pad_hold = 0x40001ad0; gpio_pad_input_disable = 0x40001adc; From 6d85d86fe198ca3af86a4c3290202d699815c61d Mon Sep 17 00:00:00 2001 From: Jin Cheng Date: Thu, 26 Sep 2024 14:20:16 +0800 Subject: [PATCH 092/472] Revert "Disable sniff mode during (e)SCO connection." This reverts commit 39a5eb84f3c6e48cce8cecd25927ad6b1e0fe383. --- components/bt/host/bluedroid/bta/dm/bta_dm_cfg.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/components/bt/host/bluedroid/bta/dm/bta_dm_cfg.c b/components/bt/host/bluedroid/bta/dm/bta_dm_cfg.c index a4792ce8469..d19fca0d6e2 100644 --- a/components/bt/host/bluedroid/bta/dm/bta_dm_cfg.c +++ b/components/bt/host/bluedroid/bta/dm/bta_dm_cfg.c @@ -231,9 +231,9 @@ tBTA_DM_PM_TYPE_QUALIFIER tBTA_DM_PM_SPEC bta_dm_pm_spec[BTA_DM_NUM_PM_SPEC] = { {{BTA_DM_PM_NO_PREF, 0}, {BTA_DM_PM_NO_ACTION, 0}}, /* conn close */ {{BTA_DM_PM_NO_ACTION, 0}, {BTA_DM_PM_NO_ACTION, 0}}, /* app open */ {{BTA_DM_PM_NO_ACTION, 0}, {BTA_DM_PM_NO_ACTION, 0}}, /* app close */ - {{BTA_DM_PM_NO_ACTION, 0}, {BTA_DM_PM_NO_ACTION, 0}}, /* sco open, active */ - {{BTA_DM_PM_NO_ACTION, 0}, {BTA_DM_PM_NO_ACTION, 0}}, /* sco close sniff */ - {{BTA_DM_PM_NO_ACTION, 0}, {BTA_DM_PM_NO_ACTION, 0}}, /* idle */ + {{BTA_DM_PM_SNIFF3, 7000 + BTA_DM_PM_SPEC_TO_OFFSET}, {BTA_DM_PM_NO_ACTION, 0}}, /* sco open, active */ + {{BTA_DM_PM_SNIFF, 7000 + BTA_DM_PM_SPEC_TO_OFFSET}, {BTA_DM_PM_NO_ACTION, 0}}, /* sco close sniff */ + {{BTA_DM_PM_SNIFF, 7000 + BTA_DM_PM_SPEC_TO_OFFSET}, {BTA_DM_PM_NO_ACTION, 0}}, /* idle */ {{BTA_DM_PM_ACTIVE, 0}, {BTA_DM_PM_NO_ACTION, 0}}, /* busy */ {{BTA_DM_PM_RETRY, 7000 + BTA_DM_PM_SPEC_TO_OFFSET}, {BTA_DM_PM_NO_ACTION, 0}} /* mode change retry */ } From 9872a7bbd124869a71706ff44e3ebce21866d4d5 Mon Sep 17 00:00:00 2001 From: Jin Cheng Date: Thu, 26 Sep 2024 14:20:12 +0800 Subject: [PATCH 093/472] fix(bt/bluedroid): fixed AG and HF client cannot enter/exit sniff mode --- components/bt/host/bluedroid/bta/dm/bta_dm_cfg.c | 10 +++++----- .../host/bluedroid/bta/hf_client/bta_hf_client_act.c | 2 ++ .../bt/host/bluedroid/bta/include/bta/bta_api.h | 12 ++++++++++++ 3 files changed, 19 insertions(+), 5 deletions(-) diff --git a/components/bt/host/bluedroid/bta/dm/bta_dm_cfg.c b/components/bt/host/bluedroid/bta/dm/bta_dm_cfg.c index d19fca0d6e2..81bbd4667f8 100644 --- a/components/bt/host/bluedroid/bta/dm/bta_dm_cfg.c +++ b/components/bt/host/bluedroid/bta/dm/bta_dm_cfg.c @@ -151,13 +151,13 @@ tBTA_DM_PM_TYPE_QUALIFIER tBTA_DM_PM_SPEC bta_dm_pm_spec[BTA_DM_NUM_PM_SPEC] = { (BTA_DM_PM_SSR2), /* the SSR entry */ #endif { - {{BTA_DM_PM_SNIFF_A2DP_IDX, 7000 + BTA_DM_PM_SPEC_TO_OFFSET}, {BTA_DM_PM_NO_ACTION, 0}}, /* conn open sniff */ + {{BTA_DM_PM_SNIFF_AG_OPEN_IDX, 7000 + BTA_DM_PM_SPEC_TO_OFFSET}, {BTA_DM_PM_NO_ACTION, 0}}, /* conn open sniff */ {{BTA_DM_PM_NO_PREF, 0}, {BTA_DM_PM_NO_ACTION, 0}}, /* conn close */ {{BTA_DM_PM_NO_ACTION, 0}, {BTA_DM_PM_NO_ACTION, 0}}, /* app open */ {{BTA_DM_PM_NO_ACTION, 0}, {BTA_DM_PM_NO_ACTION, 0}}, /* app close */ {{BTA_DM_PM_SNIFF_SCO_OPEN_IDX, 7000 + BTA_DM_PM_SPEC_TO_OFFSET}, {BTA_DM_PM_NO_ACTION, 0}}, /* sco open, active */ - {{BTA_DM_PM_SNIFF_A2DP_IDX, 7000 + BTA_DM_PM_SPEC_TO_OFFSET}, {BTA_DM_PM_NO_ACTION, 0}}, /* sco close sniff */ - {{BTA_DM_PM_NO_ACTION, 0}, {BTA_DM_PM_NO_ACTION, 0}}, /* idle */ + {{BTA_DM_PM_SNIFF_SCO_CLOSE_IDX, 7000 + BTA_DM_PM_SPEC_TO_OFFSET}, {BTA_DM_PM_NO_ACTION, 0}}, /* sco close sniff */ + {{BTA_DM_PM_SNIFF_AG_IDLE_IDX, 7000 + BTA_DM_PM_SPEC_TO_OFFSET}, {BTA_DM_PM_NO_ACTION, 0}}, /* idle */ {{BTA_DM_PM_ACTIVE, 0}, {BTA_DM_PM_NO_ACTION, 0}}, /* busy */ {{BTA_DM_PM_RETRY, 7000 + BTA_DM_PM_SPEC_TO_OFFSET}, {BTA_DM_PM_NO_ACTION, 0}} /* mode change retry */ } @@ -409,7 +409,7 @@ tBTA_DM_SSR_SPEC bta_dm_ssr_spec[] = { /*max_lat, min_rmt_to, min_loc_to*/ {0, 0, 0}, /* BTA_DM_PM_SSR0 - do not use SSR */ {0, 0, 2}, /* BTA_DM_PM_SSR1 - HH, can NOT share entry with any other profile, - seting default max latency and min remote timeout as 0, + setting default max latency and min remote timeout as 0, and always read individual device preference from HH module */ {1200, 2, 2}, /* BTA_DM_PM_SSR2 - others (as long as sniff is allowed)*/ {360, 160, 1600} /* BTA_DM_PM_SSR3 - HD */ @@ -466,7 +466,7 @@ tBTA_DM_EIR_CONF bta_dm_eir_cfg = { { /* mask of UUID list in EIR */ 0xFFFFFFFF, /* LSB is the first UUID of the first 32 UUIDs in BTM_EIR_UUID_LKUP_TBL */ 0xFFFFFFFF /* LSB is the first UUID of the next 32 UUIDs in BTM_EIR_UUID_LKUP_TBL */ - /* BTM_EIR_UUID_LKUP_TBL can be overrided */ + /* BTM_EIR_UUID_LKUP_TBL can be overridden */ }, #endif // BTA_EIR_CANNED_UUID_LIST FALSE, /* Not included TX power*/ diff --git a/components/bt/host/bluedroid/bta/hf_client/bta_hf_client_act.c b/components/bt/host/bluedroid/bta/hf_client/bta_hf_client_act.c index 0e0c43addf6..930f30a57d4 100644 --- a/components/bt/host/bluedroid/bta/hf_client/bta_hf_client_act.c +++ b/components/bt/host/bluedroid/bta/hf_client/bta_hf_client_act.c @@ -511,7 +511,9 @@ void bta_hf_client_rfc_data(tBTA_HF_CLIENT_DATA *p_data) break; } + bta_sys_busy(BTA_ID_HS, 1, bta_hf_client_cb.scb.peer_addr); bta_hf_client_at_parse(buf, len); + bta_sys_idle(BTA_ID_HS, 1, bta_hf_client_cb.scb.peer_addr); /* no more data to read, we're done */ if (len < BTA_HF_CLIENT_RFC_READ_MAX) { diff --git a/components/bt/host/bluedroid/bta/include/bta/bta_api.h b/components/bt/host/bluedroid/bta/include/bta/bta_api.h index 32dc716bc65..2ba9707de5f 100644 --- a/components/bt/host/bluedroid/bta/include/bta/bta_api.h +++ b/components/bt/host/bluedroid/bta/include/bta/bta_api.h @@ -1351,10 +1351,22 @@ typedef UINT8 tBTA_DM_PM_ACTION; #define BTA_DM_PM_SNIFF_HD_IDLE_IDX BTA_DM_PM_SNIFF4 #endif +#ifndef BTA_DM_PM_SNIFF_AG_OPEN_IDX +#define BTA_DM_PM_SNIFF_AG_OPEN_IDX BTA_DM_PM_SNIFF +#endif + +#ifndef BTA_DM_PM_SNIFF_AG_IDLE_IDX +#define BTA_DM_PM_SNIFF_AG_IDLE_IDX BTA_DM_PM_SNIFF +#endif + #ifndef BTA_DM_PM_SNIFF_SCO_OPEN_IDX #define BTA_DM_PM_SNIFF_SCO_OPEN_IDX BTA_DM_PM_SNIFF3 #endif +#ifndef BTA_DM_PM_SNIFF_SCO_CLOSE_IDX +#define BTA_DM_PM_SNIFF_SCO_CLOSE_IDX BTA_DM_PM_SNIFF +#endif + #ifndef BTA_DM_PM_SNIFF_HD_ACTIVE_IDX #define BTA_DM_PM_SNIFF_HD_ACTIVE_IDX BTA_DM_PM_SNIFF5 #endif From 3dc0f88dc691a7c0ca138db79e0e40e0a04f4d5c Mon Sep 17 00:00:00 2001 From: "hrushikesh.bhosale" Date: Thu, 10 Oct 2024 14:11:18 +0530 Subject: [PATCH 094/472] fix(protocols): Erased the storage partition for http_server ci test Added api to erase storage partition for http_server ci test --- .../file_serving/pytest_http_server_file_serving.py | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/examples/protocols/http_server/file_serving/pytest_http_server_file_serving.py b/examples/protocols/http_server/file_serving/pytest_http_server_file_serving.py index 66f1faa9db4..ff0c0e8ef55 100644 --- a/examples/protocols/http_server/file_serving/pytest_http_server_file_serving.py +++ b/examples/protocols/http_server/file_serving/pytest_http_server_file_serving.py @@ -31,11 +31,12 @@ def test_examples_protocol_http_server_file_serving(dut: Dut) -> None: binary_file = os.path.join(dut.app.binary_path, 'file_server.bin') bin_size = os.path.getsize(binary_file) logging.info('file_server_bin_size : {}KB'.format(bin_size // 1024)) - logging.info('Erasing the flash on the chip') + logging.info('Erasing the storage partition on the chip') + dut.serial.erase_partition('storage') # Upload binary and start testing logging.info('Starting http file serving simple test app') - dut.expect('Initializing SPIFFS', timeout=30) + dut.expect('Initializing SPIFFS', timeout=60) if dut.app.sdkconfig.get('EXAMPLE_WIFI_SSID_PWD_FROM_STDIN') is True: dut.expect('Please input ssid password:') From 84ba1a323c9873957cb691ae97c67b337157595c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Tom=C3=A1=C5=A1=20Rohl=C3=ADnek?= Date: Wed, 29 May 2024 14:12:43 +0200 Subject: [PATCH 095/472] fix(storage/fatfs): move test app to correct directory --- examples/storage/.build-test-rules.yml | 8 -------- examples/storage/README.md | 1 - tools/test_apps/storage/.build-test-rules.yml | 8 ++++++++ .../test_apps}/storage/fatfsgen/CMakeLists.txt | 0 {examples => tools/test_apps}/storage/fatfsgen/README.md | 0 .../test_apps}/storage/fatfsgen/fatfs_image/hello.txt | 0 .../test_apps}/storage/fatfsgen/fatfs_image/sub/test.txt | 0 .../fatfsgen/fatfs_long_name_image/hellolongname.txt | 0 .../sublongnames/testlongfilenames.txt | 0 .../test_apps}/storage/fatfsgen/main/CMakeLists.txt | 0 .../test_apps}/storage/fatfsgen/main/Kconfig.projbuild | 0 .../storage/fatfsgen/main/fatfsgen_example_main.c | 0 .../test_apps}/storage/fatfsgen/partitions_example.csv | 0 .../storage/fatfsgen/pytest_fatfsgen_example.py | 0 .../fatfsgen/sdkconfig.ci.test_read_only_partition_gen | 0 .../sdkconfig.ci.test_read_only_partition_gen_default_dt | 0 .../fatfsgen/sdkconfig.ci.test_read_only_partition_gen_ln | 0 ...dkconfig.ci.test_read_only_partition_gen_ln_default_dt | 0 .../fatfsgen/sdkconfig.ci.test_read_write_partition_gen | 0 .../sdkconfig.ci.test_read_write_partition_gen_default_dt | 0 .../sdkconfig.ci.test_read_write_partition_gen_ln | 0 ...kconfig.ci.test_read_write_partition_gen_ln_default_dt | 0 .../test_apps}/storage/fatfsgen/sdkconfig.defaults | 0 23 files changed, 8 insertions(+), 9 deletions(-) rename {examples => tools/test_apps}/storage/fatfsgen/CMakeLists.txt (100%) rename {examples => tools/test_apps}/storage/fatfsgen/README.md (100%) rename {examples => tools/test_apps}/storage/fatfsgen/fatfs_image/hello.txt (100%) rename {examples => tools/test_apps}/storage/fatfsgen/fatfs_image/sub/test.txt (100%) rename {examples => tools/test_apps}/storage/fatfsgen/fatfs_long_name_image/hellolongname.txt (100%) rename {examples => tools/test_apps}/storage/fatfsgen/fatfs_long_name_image/sublongnames/testlongfilenames.txt (100%) rename {examples => tools/test_apps}/storage/fatfsgen/main/CMakeLists.txt (100%) rename {examples => tools/test_apps}/storage/fatfsgen/main/Kconfig.projbuild (100%) rename {examples => tools/test_apps}/storage/fatfsgen/main/fatfsgen_example_main.c (100%) rename {examples => tools/test_apps}/storage/fatfsgen/partitions_example.csv (100%) rename {examples => tools/test_apps}/storage/fatfsgen/pytest_fatfsgen_example.py (100%) rename {examples => tools/test_apps}/storage/fatfsgen/sdkconfig.ci.test_read_only_partition_gen (100%) rename {examples => tools/test_apps}/storage/fatfsgen/sdkconfig.ci.test_read_only_partition_gen_default_dt (100%) rename {examples => tools/test_apps}/storage/fatfsgen/sdkconfig.ci.test_read_only_partition_gen_ln (100%) rename {examples => tools/test_apps}/storage/fatfsgen/sdkconfig.ci.test_read_only_partition_gen_ln_default_dt (100%) rename {examples => tools/test_apps}/storage/fatfsgen/sdkconfig.ci.test_read_write_partition_gen (100%) rename {examples => tools/test_apps}/storage/fatfsgen/sdkconfig.ci.test_read_write_partition_gen_default_dt (100%) rename {examples => tools/test_apps}/storage/fatfsgen/sdkconfig.ci.test_read_write_partition_gen_ln (100%) rename {examples => tools/test_apps}/storage/fatfsgen/sdkconfig.ci.test_read_write_partition_gen_ln_default_dt (100%) rename {examples => tools/test_apps}/storage/fatfsgen/sdkconfig.defaults (100%) diff --git a/examples/storage/.build-test-rules.yml b/examples/storage/.build-test-rules.yml index 4e7e8c66cbe..341e0f595a8 100644 --- a/examples/storage/.build-test-rules.yml +++ b/examples/storage/.build-test-rules.yml @@ -34,14 +34,6 @@ examples/storage/ext_flash_fatfs: temporary: true reason: lack of runners -examples/storage/fatfsgen: - depends_components: - - fatfs - - vfs - disable_test: - - if: IDF_TARGET != "esp32" - reason: only one target needed - examples/storage/nvs_rw_blob: depends_components: - nvs_flash diff --git a/examples/storage/README.md b/examples/storage/README.md index bb5c821fe89..4705e726151 100644 --- a/examples/storage/README.md +++ b/examples/storage/README.md @@ -10,7 +10,6 @@ The examples are grouped into sub-directories by category. Each category directo * `custom_flash_driver` example demonstrates how to implement your own flash chip driver by overriding the default driver. * `emmc` example demonstrates how to use an eMMC chip with an ESP device. * `ext_flash_fatfs` example demonstrates how to use FATFS partition with external SPI FLASH chip. -* `fatfsgen` example demonstrates how to use FATFS partition * `nvs_rw_blob` example demonstrates how to read and write a single integer value and a blob (binary large object) using NVS to preserve them between ESP module restarts. * `nvs_rw_value` example demonstrates how to read and write a single integer value using NVS. * `nvs_rw_value_cxx` example demonstrates how to read and write a single integer value using NVS (it uses the C++ NVS handle API). diff --git a/tools/test_apps/storage/.build-test-rules.yml b/tools/test_apps/storage/.build-test-rules.yml index d27c0ab8933..f0ab55097ce 100644 --- a/tools/test_apps/storage/.build-test-rules.yml +++ b/tools/test_apps/storage/.build-test-rules.yml @@ -1,5 +1,13 @@ # Documentation: .gitlab/ci/README.md#manifest-file-to-control-the-buildtest-apps +tools/test_apps/storage/fatfsgen: + depends_components: + - fatfs + - vfs + disable_test: + - if: IDF_TARGET != "esp32" + reason: only one target needed + tools/test_apps/storage/partition_table_readonly: disable_test: - if: IDF_TARGET not in ["esp32", "esp32c3"] diff --git a/examples/storage/fatfsgen/CMakeLists.txt b/tools/test_apps/storage/fatfsgen/CMakeLists.txt similarity index 100% rename from examples/storage/fatfsgen/CMakeLists.txt rename to tools/test_apps/storage/fatfsgen/CMakeLists.txt diff --git a/examples/storage/fatfsgen/README.md b/tools/test_apps/storage/fatfsgen/README.md similarity index 100% rename from examples/storage/fatfsgen/README.md rename to tools/test_apps/storage/fatfsgen/README.md diff --git a/examples/storage/fatfsgen/fatfs_image/hello.txt b/tools/test_apps/storage/fatfsgen/fatfs_image/hello.txt similarity index 100% rename from examples/storage/fatfsgen/fatfs_image/hello.txt rename to tools/test_apps/storage/fatfsgen/fatfs_image/hello.txt diff --git a/examples/storage/fatfsgen/fatfs_image/sub/test.txt b/tools/test_apps/storage/fatfsgen/fatfs_image/sub/test.txt similarity index 100% rename from examples/storage/fatfsgen/fatfs_image/sub/test.txt rename to tools/test_apps/storage/fatfsgen/fatfs_image/sub/test.txt diff --git a/examples/storage/fatfsgen/fatfs_long_name_image/hellolongname.txt b/tools/test_apps/storage/fatfsgen/fatfs_long_name_image/hellolongname.txt similarity index 100% rename from examples/storage/fatfsgen/fatfs_long_name_image/hellolongname.txt rename to tools/test_apps/storage/fatfsgen/fatfs_long_name_image/hellolongname.txt diff --git a/examples/storage/fatfsgen/fatfs_long_name_image/sublongnames/testlongfilenames.txt b/tools/test_apps/storage/fatfsgen/fatfs_long_name_image/sublongnames/testlongfilenames.txt similarity index 100% rename from examples/storage/fatfsgen/fatfs_long_name_image/sublongnames/testlongfilenames.txt rename to tools/test_apps/storage/fatfsgen/fatfs_long_name_image/sublongnames/testlongfilenames.txt diff --git a/examples/storage/fatfsgen/main/CMakeLists.txt b/tools/test_apps/storage/fatfsgen/main/CMakeLists.txt similarity index 100% rename from examples/storage/fatfsgen/main/CMakeLists.txt rename to tools/test_apps/storage/fatfsgen/main/CMakeLists.txt diff --git a/examples/storage/fatfsgen/main/Kconfig.projbuild b/tools/test_apps/storage/fatfsgen/main/Kconfig.projbuild similarity index 100% rename from examples/storage/fatfsgen/main/Kconfig.projbuild rename to tools/test_apps/storage/fatfsgen/main/Kconfig.projbuild diff --git a/examples/storage/fatfsgen/main/fatfsgen_example_main.c b/tools/test_apps/storage/fatfsgen/main/fatfsgen_example_main.c similarity index 100% rename from examples/storage/fatfsgen/main/fatfsgen_example_main.c rename to tools/test_apps/storage/fatfsgen/main/fatfsgen_example_main.c diff --git a/examples/storage/fatfsgen/partitions_example.csv b/tools/test_apps/storage/fatfsgen/partitions_example.csv similarity index 100% rename from examples/storage/fatfsgen/partitions_example.csv rename to tools/test_apps/storage/fatfsgen/partitions_example.csv diff --git a/examples/storage/fatfsgen/pytest_fatfsgen_example.py b/tools/test_apps/storage/fatfsgen/pytest_fatfsgen_example.py similarity index 100% rename from examples/storage/fatfsgen/pytest_fatfsgen_example.py rename to tools/test_apps/storage/fatfsgen/pytest_fatfsgen_example.py diff --git a/examples/storage/fatfsgen/sdkconfig.ci.test_read_only_partition_gen b/tools/test_apps/storage/fatfsgen/sdkconfig.ci.test_read_only_partition_gen similarity index 100% rename from examples/storage/fatfsgen/sdkconfig.ci.test_read_only_partition_gen rename to tools/test_apps/storage/fatfsgen/sdkconfig.ci.test_read_only_partition_gen diff --git a/examples/storage/fatfsgen/sdkconfig.ci.test_read_only_partition_gen_default_dt b/tools/test_apps/storage/fatfsgen/sdkconfig.ci.test_read_only_partition_gen_default_dt similarity index 100% rename from examples/storage/fatfsgen/sdkconfig.ci.test_read_only_partition_gen_default_dt rename to tools/test_apps/storage/fatfsgen/sdkconfig.ci.test_read_only_partition_gen_default_dt diff --git a/examples/storage/fatfsgen/sdkconfig.ci.test_read_only_partition_gen_ln b/tools/test_apps/storage/fatfsgen/sdkconfig.ci.test_read_only_partition_gen_ln similarity index 100% rename from examples/storage/fatfsgen/sdkconfig.ci.test_read_only_partition_gen_ln rename to tools/test_apps/storage/fatfsgen/sdkconfig.ci.test_read_only_partition_gen_ln diff --git a/examples/storage/fatfsgen/sdkconfig.ci.test_read_only_partition_gen_ln_default_dt b/tools/test_apps/storage/fatfsgen/sdkconfig.ci.test_read_only_partition_gen_ln_default_dt similarity index 100% rename from examples/storage/fatfsgen/sdkconfig.ci.test_read_only_partition_gen_ln_default_dt rename to tools/test_apps/storage/fatfsgen/sdkconfig.ci.test_read_only_partition_gen_ln_default_dt diff --git a/examples/storage/fatfsgen/sdkconfig.ci.test_read_write_partition_gen b/tools/test_apps/storage/fatfsgen/sdkconfig.ci.test_read_write_partition_gen similarity index 100% rename from examples/storage/fatfsgen/sdkconfig.ci.test_read_write_partition_gen rename to tools/test_apps/storage/fatfsgen/sdkconfig.ci.test_read_write_partition_gen diff --git a/examples/storage/fatfsgen/sdkconfig.ci.test_read_write_partition_gen_default_dt b/tools/test_apps/storage/fatfsgen/sdkconfig.ci.test_read_write_partition_gen_default_dt similarity index 100% rename from examples/storage/fatfsgen/sdkconfig.ci.test_read_write_partition_gen_default_dt rename to tools/test_apps/storage/fatfsgen/sdkconfig.ci.test_read_write_partition_gen_default_dt diff --git a/examples/storage/fatfsgen/sdkconfig.ci.test_read_write_partition_gen_ln b/tools/test_apps/storage/fatfsgen/sdkconfig.ci.test_read_write_partition_gen_ln similarity index 100% rename from examples/storage/fatfsgen/sdkconfig.ci.test_read_write_partition_gen_ln rename to tools/test_apps/storage/fatfsgen/sdkconfig.ci.test_read_write_partition_gen_ln diff --git a/examples/storage/fatfsgen/sdkconfig.ci.test_read_write_partition_gen_ln_default_dt b/tools/test_apps/storage/fatfsgen/sdkconfig.ci.test_read_write_partition_gen_ln_default_dt similarity index 100% rename from examples/storage/fatfsgen/sdkconfig.ci.test_read_write_partition_gen_ln_default_dt rename to tools/test_apps/storage/fatfsgen/sdkconfig.ci.test_read_write_partition_gen_ln_default_dt diff --git a/examples/storage/fatfsgen/sdkconfig.defaults b/tools/test_apps/storage/fatfsgen/sdkconfig.defaults similarity index 100% rename from examples/storage/fatfsgen/sdkconfig.defaults rename to tools/test_apps/storage/fatfsgen/sdkconfig.defaults From b9a54fb1f3f9fc992f5db142b30f130212d6c156 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Tom=C3=A1=C5=A1=20Rohl=C3=ADnek?= Date: Wed, 29 May 2024 10:10:38 +0200 Subject: [PATCH 096/472] feat(storage/fatfs): add minimal FatFS example --- examples/storage/.build-test-rules.yml | 8 ++ examples/storage/README.md | 1 + examples/storage/fatfs_basic/CMakeLists.txt | 6 ++ examples/storage/fatfs_basic/README.md | 43 +++++++++ .../storage/fatfs_basic/main/CMakeLists.txt | 2 + .../fatfs_basic/main/fat_example_main.c | 87 +++++++++++++++++++ .../fatfs_basic/partitions_example.csv | 6 ++ .../storage/fatfs_basic/pytest_fat_example.py | 17 ++++ .../storage/fatfs_basic/sdkconfig.defaults | 4 + 9 files changed, 174 insertions(+) create mode 100644 examples/storage/fatfs_basic/CMakeLists.txt create mode 100644 examples/storage/fatfs_basic/README.md create mode 100644 examples/storage/fatfs_basic/main/CMakeLists.txt create mode 100644 examples/storage/fatfs_basic/main/fat_example_main.c create mode 100644 examples/storage/fatfs_basic/partitions_example.csv create mode 100644 examples/storage/fatfs_basic/pytest_fat_example.py create mode 100644 examples/storage/fatfs_basic/sdkconfig.defaults diff --git a/examples/storage/.build-test-rules.yml b/examples/storage/.build-test-rules.yml index 341e0f595a8..a15e95e333b 100644 --- a/examples/storage/.build-test-rules.yml +++ b/examples/storage/.build-test-rules.yml @@ -34,6 +34,14 @@ examples/storage/ext_flash_fatfs: temporary: true reason: lack of runners +examples/storage/fatfs_basic: + depends_components: + - fatfs + - vfs + disable_test: + - if: IDF_TARGET != "esp32" + reason: only one target needed + examples/storage/nvs_rw_blob: depends_components: - nvs_flash diff --git a/examples/storage/README.md b/examples/storage/README.md index 4705e726151..ade0b883a1a 100644 --- a/examples/storage/README.md +++ b/examples/storage/README.md @@ -7,6 +7,7 @@ This directory contains a range of examples ESP-IDF projects. These are intended The examples are grouped into sub-directories by category. Each category directory contains one or more example projects: +* `fatfs_basic` minimal example of FatFS usage on SPI FLASH * `custom_flash_driver` example demonstrates how to implement your own flash chip driver by overriding the default driver. * `emmc` example demonstrates how to use an eMMC chip with an ESP device. * `ext_flash_fatfs` example demonstrates how to use FATFS partition with external SPI FLASH chip. diff --git a/examples/storage/fatfs_basic/CMakeLists.txt b/examples/storage/fatfs_basic/CMakeLists.txt new file mode 100644 index 00000000000..1c0c2b8a1a2 --- /dev/null +++ b/examples/storage/fatfs_basic/CMakeLists.txt @@ -0,0 +1,6 @@ +# The following lines of boilerplate have to be in your project's CMakeLists +# in this exact order for cmake to work correctly +cmake_minimum_required(VERSION 3.16) + +include($ENV{IDF_PATH}/tools/cmake/project.cmake) +project(fatfsgen) diff --git a/examples/storage/fatfs_basic/README.md b/examples/storage/fatfs_basic/README.md new file mode 100644 index 00000000000..0ee84f105df --- /dev/null +++ b/examples/storage/fatfs_basic/README.md @@ -0,0 +1,43 @@ +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | + +# FATFS minimal example + +(See the README.md file in the upper level 'examples' directory for more information about examples.) + +This example demonstrates the minimal setup required to store persistent data on SPI Flash using the FAT filesystem. +Beware that the minimal required size of the flash is 4 MB. + +## How to use example + +### Build and flash + +To run the example, type the following command: + +```CMake +# CMake +idf.py -p PORT flash monitor +``` + +(To exit the serial monitor, type ``Ctrl-]``.) + +See the Getting Started Guide for full steps to configure and use ESP-IDF to build projects. + +## Example output + +Here is the example's console output: + +``` +... +I (339) example: Mounting FAT filesystem +I (339) example: Filesystem mounted +I (339) example: Opening file +I (729) example: File written +I (729) example: Reading file +I (739) example: Read from file: 'This is written by the device' +I (739) example: Unmounting FAT filesystem +I (849) example: Done +``` + +The logic of the example is contained in a [single source file](./main/fat_example_main.c), +and it should be relatively simple to match points in its execution with the log outputs above. diff --git a/examples/storage/fatfs_basic/main/CMakeLists.txt b/examples/storage/fatfs_basic/main/CMakeLists.txt new file mode 100644 index 00000000000..827c3c2e8e0 --- /dev/null +++ b/examples/storage/fatfs_basic/main/CMakeLists.txt @@ -0,0 +1,2 @@ +idf_component_register(SRCS "fat_example_main.c" + INCLUDE_DIRS ".") diff --git a/examples/storage/fatfs_basic/main/fat_example_main.c b/examples/storage/fatfs_basic/main/fat_example_main.c new file mode 100644 index 00000000000..2a57821e70d --- /dev/null +++ b/examples/storage/fatfs_basic/main/fat_example_main.c @@ -0,0 +1,87 @@ +/* + * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Unlicense OR CC0-1.0 + */ + +#include +#include +#include +#include "esp_vfs.h" +#include "esp_vfs_fat.h" +#include "sdkconfig.h" + +static const char *TAG = "example"; + +// Mount path for the partition +const char *base_path = "/spiflash"; + +// Handle of the wear levelling library instance +static wl_handle_t s_wl_handle = WL_INVALID_HANDLE; + +void app_main(void) +{ + ESP_LOGI(TAG, "Mounting FAT filesystem"); + // To mount device we need name of device partition, define base_path + // and allow format partition in case if it is new one and was not formatted before + const esp_vfs_fat_mount_config_t mount_config = { + .max_files = 4, // Number of files that can be open at a time + .format_if_mount_failed = true, // If true, try to format the partition if mount fails + .allocation_unit_size = CONFIG_WL_SECTOR_SIZE, // Size of allocation unit, cluster size. + .use_one_fat = false, // Use only one FAT table (reduce memory usage), but decrease reliability of file system in case of power failure. + }; + + esp_err_t err = esp_vfs_fat_spiflash_mount_rw_wl(base_path, "storage", &mount_config, &s_wl_handle); + + if (err != ESP_OK) { + ESP_LOGE(TAG, "Failed to mount FATFS (%s)", esp_err_to_name(err)); + return; + } + + ESP_LOGI(TAG, "Filesystem mounted"); + + ESP_LOGI(TAG, "Opening file"); + + const char *filename = "/spiflash/example.txt"; + + FILE *f = fopen(filename, "wb"); + if (f == NULL) { + perror("fopen"); + ESP_LOGE(TAG, "Failed to open file for writing"); + return; + } + + fprintf(f, "This is written by the device"); + fclose(f); + + ESP_LOGI(TAG, "File written"); + + // Open file for reading + ESP_LOGI(TAG, "Reading file"); + + f = fopen(filename, "r"); + if (f == NULL) { + ESP_LOGE(TAG, "Failed to open file for reading"); + return; + } + + char line[128]; + + fgets(line, sizeof(line), f); + fclose(f); + + // strip newline + char *pos = strchr(line, '\n'); + if (pos) { + *pos = '\0'; + } + + ESP_LOGI(TAG, "Read from file: '%s'", line); + + // Unmount FATFS + ESP_LOGI(TAG, "Unmounting FAT filesystem"); + + ESP_ERROR_CHECK(esp_vfs_fat_spiflash_unmount_rw_wl(base_path, s_wl_handle)); + + ESP_LOGI(TAG, "Done"); +} diff --git a/examples/storage/fatfs_basic/partitions_example.csv b/examples/storage/fatfs_basic/partitions_example.csv new file mode 100644 index 00000000000..1c79321a107 --- /dev/null +++ b/examples/storage/fatfs_basic/partitions_example.csv @@ -0,0 +1,6 @@ +# Name, Type, SubType, Offset, Size, Flags +# Note: if you have increased the bootloader size, make sure to update the offsets to avoid overlap +nvs, data, nvs, 0x9000, 0x6000, +phy_init, data, phy, 0xf000, 0x1000, +factory, app, factory, 0x10000, 1M, +storage, data, fat, , 1M, diff --git a/examples/storage/fatfs_basic/pytest_fat_example.py b/examples/storage/fatfs_basic/pytest_fat_example.py new file mode 100644 index 00000000000..7abafe062de --- /dev/null +++ b/examples/storage/fatfs_basic/pytest_fat_example.py @@ -0,0 +1,17 @@ +# SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD +# SPDX-License-Identifier: Unlicense OR CC0-1.0 +import pytest +from pytest_embedded import Dut + + +@pytest.mark.esp32 +@pytest.mark.generic +def test_examples_fatfs_basic(dut: Dut) -> None: + dut.expect('example: Mounting FAT filesystem', timeout=90) + dut.expect('example: Filesystem mounted', timeout=90) + dut.expect('example: Opening file', timeout=90) + dut.expect('example: File written', timeout=90) + dut.expect('example: Reading file', timeout=90) + dut.expect('example: Read from file: \'This is written by the device\'', timeout=90) + dut.expect('example: Unmounting FAT filesystem', timeout=90) + dut.expect('example: Done', timeout=90) diff --git a/examples/storage/fatfs_basic/sdkconfig.defaults b/examples/storage/fatfs_basic/sdkconfig.defaults new file mode 100644 index 00000000000..47363c32d51 --- /dev/null +++ b/examples/storage/fatfs_basic/sdkconfig.defaults @@ -0,0 +1,4 @@ +CONFIG_PARTITION_TABLE_CUSTOM=y +CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="partitions_example.csv" +CONFIG_PARTITION_TABLE_FILENAME="partitions_example.csv" +CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y From f633839eceffd424c20dacbec8f597ed46d1294e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Tom=C3=A1=C5=A1=20Rohl=C3=ADnek?= Date: Mon, 3 Jun 2024 08:22:52 +0200 Subject: [PATCH 097/472] feat(storage/fatfs): add advanced example for fatfs --- examples/storage/.build-test-rules.yml | 8 + examples/storage/README.md | 1 + .../storage/fatfs_advanced/CMakeLists.txt | 6 + examples/storage/fatfs_advanced/README.md | 69 +++++++++ .../filegeneratedonhost.txt | 1 + .../subdirectoryfromhost/innerfile.txt | 1 + .../fatfs_advanced/main/CMakeLists.txt | 26 ++++ .../fatfs_advanced/main/Kconfig.projbuild | 24 +++ .../main/fatfs_advanced_example_main.c | 138 ++++++++++++++++++ .../fatfs_advanced/partitions_example.csv | 6 + .../pytest_fatfs_advanced_example.py | 112 ++++++++++++++ .../sdkconfig.ci.test_read_only_partition_gen | 5 + ...ci.test_read_only_partition_gen_default_dt | 6 + ...sdkconfig.ci.test_read_write_partition_gen | 5 + ...i.test_read_write_partition_gen_default_dt | 6 + .../storage/fatfs_advanced/sdkconfig.defaults | 7 + 16 files changed, 421 insertions(+) create mode 100644 examples/storage/fatfs_advanced/CMakeLists.txt create mode 100644 examples/storage/fatfs_advanced/README.md create mode 100644 examples/storage/fatfs_advanced/fatfs_long_name_image/filegeneratedonhost.txt create mode 100644 examples/storage/fatfs_advanced/fatfs_long_name_image/subdirectoryfromhost/innerfile.txt create mode 100644 examples/storage/fatfs_advanced/main/CMakeLists.txt create mode 100644 examples/storage/fatfs_advanced/main/Kconfig.projbuild create mode 100644 examples/storage/fatfs_advanced/main/fatfs_advanced_example_main.c create mode 100644 examples/storage/fatfs_advanced/partitions_example.csv create mode 100644 examples/storage/fatfs_advanced/pytest_fatfs_advanced_example.py create mode 100644 examples/storage/fatfs_advanced/sdkconfig.ci.test_read_only_partition_gen create mode 100644 examples/storage/fatfs_advanced/sdkconfig.ci.test_read_only_partition_gen_default_dt create mode 100644 examples/storage/fatfs_advanced/sdkconfig.ci.test_read_write_partition_gen create mode 100644 examples/storage/fatfs_advanced/sdkconfig.ci.test_read_write_partition_gen_default_dt create mode 100644 examples/storage/fatfs_advanced/sdkconfig.defaults diff --git a/examples/storage/.build-test-rules.yml b/examples/storage/.build-test-rules.yml index a15e95e333b..5999ae95eac 100644 --- a/examples/storage/.build-test-rules.yml +++ b/examples/storage/.build-test-rules.yml @@ -34,6 +34,14 @@ examples/storage/ext_flash_fatfs: temporary: true reason: lack of runners +examples/storage/fatfs_advanced: + depends_components: + - fatfs + - vfs + disable_test: + - if: IDF_TARGET != "esp32" + reason: only one target needed + examples/storage/fatfs_basic: depends_components: - fatfs diff --git a/examples/storage/README.md b/examples/storage/README.md index ade0b883a1a..ebfb75833d5 100644 --- a/examples/storage/README.md +++ b/examples/storage/README.md @@ -8,6 +8,7 @@ This directory contains a range of examples ESP-IDF projects. These are intended The examples are grouped into sub-directories by category. Each category directory contains one or more example projects: * `fatfs_basic` minimal example of FatFS usage on SPI FLASH +* `fatfs_advanced` example demonstrates how to use advanced features for working with FatFS such as automatic partition generation * `custom_flash_driver` example demonstrates how to implement your own flash chip driver by overriding the default driver. * `emmc` example demonstrates how to use an eMMC chip with an ESP device. * `ext_flash_fatfs` example demonstrates how to use FATFS partition with external SPI FLASH chip. diff --git a/examples/storage/fatfs_advanced/CMakeLists.txt b/examples/storage/fatfs_advanced/CMakeLists.txt new file mode 100644 index 00000000000..1c0c2b8a1a2 --- /dev/null +++ b/examples/storage/fatfs_advanced/CMakeLists.txt @@ -0,0 +1,6 @@ +# The following lines of boilerplate have to be in your project's CMakeLists +# in this exact order for cmake to work correctly +cmake_minimum_required(VERSION 3.16) + +include($ENV{IDF_PATH}/tools/cmake/project.cmake) +project(fatfsgen) diff --git a/examples/storage/fatfs_advanced/README.md b/examples/storage/fatfs_advanced/README.md new file mode 100644 index 00000000000..34ab038fc54 --- /dev/null +++ b/examples/storage/fatfs_advanced/README.md @@ -0,0 +1,69 @@ +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | + +# FATFS partition generation example + +(See the README.md file in the upper level 'examples' directory for more information about examples.) + +This example demonstrates how to use the FATFS partition +generation tool [fatfsgen.py](../../../components/fatfs/fatfsgen.py) to automatically create a FATFS +filesystem image from the contents of a host folder during build, with an option of +automatically flashing the created image on invocation of `idf.py -p PORT flash` as well as usage of long file names for FATFS. +Beware that the minimal required size of the flash is 4 MB. +You can specify using menuconfig weather example will use read-only or read-write mode. The default option is read-write mode. +To change it just use menuconfig: + +```shell +idf.py menuconfig +``` + +Then select `Example Configuration` a chose `Mode for generated FATFS image` either `Read-Write Mode` or `Read-Only Mode`. +`Read-Only` option indicates generating raw fatfs image without wear levelling support. +On the other hand, for `Read-Write` the generated fatfs image will support wear levelling thus can be mounted in read-write mode. + + +The following gives an overview of the example: + +1. There is a directory `fatfs_image` from which the FATFS filesystem image will be created. + +2. The function `fatfs_create_rawflash_image` is used to specify that a FATFS image +should be created during build for the `storage` partition. +For CMake, it is called from [the main component's CMakeLists.txt](./main/CMakeLists.txt). +`FLASH_IN_PROJECT` specifies that the created image +should be flashed on invocation of `idf.py -p PORT flash` together with app, bootloader, partition table, etc. +The image is created on the example's build directory with the output filename `storage.bin`. + +3. Upon invocation of `idf.py -p PORT flash monitor`, application loads and +finds there is already a valid FATFS filesystem in the `storage` partition with files same as those in `fatfs_image` directory. The application is then +able to read those files. + +## How to use example + +### Build and flash + +To run the example, type the following command: + +```CMake +# CMake +idf.py -p PORT flash monitor +``` + +(To exit the serial monitor, type ``Ctrl-]``.) + +See the Getting Started Guide for full steps to configure and use ESP-IDF to build projects. + +## Example output + +Here is the example's console output: + +``` +... +I (322) example: Mounting FAT filesystem +I (332) example: Reading file +I (332) example: Read from file: 'this is test' +I (332) example: Unmounting FAT filesystem +I (342) example: Done +``` + +The logic of the example is contained in a [single source file](./main/fatfsgen_example_main.c), +and it should be relatively simple to match points in its execution with the log outputs above. diff --git a/examples/storage/fatfs_advanced/fatfs_long_name_image/filegeneratedonhost.txt b/examples/storage/fatfs_advanced/fatfs_long_name_image/filegeneratedonhost.txt new file mode 100644 index 00000000000..33f47c9b1db --- /dev/null +++ b/examples/storage/fatfs_advanced/fatfs_long_name_image/filegeneratedonhost.txt @@ -0,0 +1 @@ +This is generated on the host; it has long name diff --git a/examples/storage/fatfs_advanced/fatfs_long_name_image/subdirectoryfromhost/innerfile.txt b/examples/storage/fatfs_advanced/fatfs_long_name_image/subdirectoryfromhost/innerfile.txt new file mode 100644 index 00000000000..84505e3d3e7 --- /dev/null +++ b/examples/storage/fatfs_advanced/fatfs_long_name_image/subdirectoryfromhost/innerfile.txt @@ -0,0 +1 @@ +this is test; it has long name diff --git a/examples/storage/fatfs_advanced/main/CMakeLists.txt b/examples/storage/fatfs_advanced/main/CMakeLists.txt new file mode 100644 index 00000000000..28eed4c7c32 --- /dev/null +++ b/examples/storage/fatfs_advanced/main/CMakeLists.txt @@ -0,0 +1,26 @@ +idf_component_register(SRCS "fatfs_advanced_example_main.c" + INCLUDE_DIRS ".") + +# Create a FATFS image from the contents of the 'fatfs_image' directory +# that fits the partition named 'storage'. FLASH_IN_PROJECT indicates that +# the generated image should be flashed when the entire project is flashed to +# the target with 'idf.py -p PORT flash'. +# If read-only mode is set (CONFIG_EXAMPLE_FATFS_MODE_READ_ONLY) +# the generated image will be raw without wear levelling support. +# Otherwise it will support wear levelling and thus enable read-write mounting of the image in the device. + +set(image ../fatfs_long_name_image) + +if(CONFIG_EXAMPLE_FATFS_MODE_READ_ONLY) + if(CONFIG_EXAMPLE_FATFS_DEFAULT_DATETIME) + fatfs_create_rawflash_image(storage ${image} FLASH_IN_PROJECT) + else() + fatfs_create_rawflash_image(storage ${image} FLASH_IN_PROJECT PRESERVE_TIME) + endif() +else() + if(CONFIG_EXAMPLE_FATFS_DEFAULT_DATETIME) + fatfs_create_spiflash_image(storage ${image} FLASH_IN_PROJECT) + else() + fatfs_create_spiflash_image(storage ${image} FLASH_IN_PROJECT PRESERVE_TIME) + endif() +endif() diff --git a/examples/storage/fatfs_advanced/main/Kconfig.projbuild b/examples/storage/fatfs_advanced/main/Kconfig.projbuild new file mode 100644 index 00000000000..b715c917b84 --- /dev/null +++ b/examples/storage/fatfs_advanced/main/Kconfig.projbuild @@ -0,0 +1,24 @@ +menu "Example Configuration" + + config EXAMPLE_FATFS_MODE_READ_ONLY + bool "Read only mode for generated FATFS image" + default n + help + If read-only mode is set, the generated fatfs image will be raw (without wear levelling support). + Otherwise it will support wear levelling that enables read-write mounting. + + config EXAMPLE_FATFS_WRITE_COUNT + int "Number of volumes" + default 1 + range 1 600 + help + Number of writes to the file (for testing purposes). + + config EXAMPLE_FATFS_DEFAULT_DATETIME + bool "Default modification date and time for generated FATFS image" + default n + help + If default datetime is set, all files created in the generated FATFS partition have default time + equal to FATFS origin time (1 January 1980) + +endmenu diff --git a/examples/storage/fatfs_advanced/main/fatfs_advanced_example_main.c b/examples/storage/fatfs_advanced/main/fatfs_advanced_example_main.c new file mode 100644 index 00000000000..3d8032b163e --- /dev/null +++ b/examples/storage/fatfs_advanced/main/fatfs_advanced_example_main.c @@ -0,0 +1,138 @@ +/* + * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Unlicense OR CC0-1.0 + */ + +#include +#include +#include +#include +#include "esp_vfs.h" +#include "esp_vfs_fat.h" +#include "sdkconfig.h" + +static const char *TAG = "example"; + +// Mount path for the partition +const char *base_path = "/spiflash"; + +void write_file(const char *filename, const char *data) +{ + ESP_LOGI(TAG, "Opening file '%s' for writing", filename); + + FILE *f = fopen(filename, "w"); + if (f == NULL) { + ESP_LOGE(TAG, "Failed to open file for writing: %s", strerror(errno)); + return; + } + + ESP_LOGI(TAG, "Writing to file"); + + fputs(data, f); + + ESP_LOGI(TAG, "File written"); + + ESP_LOGI(TAG, "Closing file"); + fclose(f); +} + +void read_file(const char *filename) +{ + ESP_LOGI(TAG, "Opening file '%s' for reading", filename); + + FILE *f = fopen(filename, "r"); + if (f == NULL) { + ESP_LOGE(TAG, "Failed to open file for reading: %s", strerror(errno)); + return; + } + + ESP_LOGI(TAG, "Reading from file"); + + char line[128]; + fgets(line, sizeof(line), f); + + // strip newline + char *pos = strchr(line, '\n'); + if (pos) { + *pos = '\0'; // strip newline + } + + ESP_LOGI(TAG, "Read from file: '%s'", line); + + ESP_LOGI(TAG, "Closing file '%s'", filename); + fclose(f); +} + +void stat_file(const char *filename) +{ + + struct stat info; + struct tm timeinfo; + char buffer[32]; + + ESP_LOGI(TAG, "Stating file '%s' for modification time", filename); + + if(stat(filename, &info) < 0){ + ESP_LOGE(TAG, "Failed to read file stats: %s", strerror(errno)); + return; + } + localtime_r(&info.st_mtime, &timeinfo); + strftime(buffer, sizeof(buffer), "%Y-%m-%d", &timeinfo); + + ESP_LOGI(TAG, "The file '%s' was modified at date: %s", filename, buffer); +} + +void app_main(void) +{ + ESP_LOGI(TAG, "Mounting FAT filesystem"); + + // To mount device we need name of device partition, define base_path + // and allow format partition in case if it is new one and was not formatted before + const esp_vfs_fat_mount_config_t mount_config = { + .max_files = 4, + .format_if_mount_failed = false, + .allocation_unit_size = CONFIG_WL_SECTOR_SIZE, + .use_one_fat = false, + }; + + esp_err_t err; + +#ifdef CONFIG_EXAMPLE_FATFS_MODE_READ_ONLY + err = esp_vfs_fat_spiflash_mount_ro(base_path, "storage", &mount_config); +#else // CONFIG_EXAMPLE_FATFS_MODE_READ_ONLY + + // Handle of the wear levelling library instance + wl_handle_t wl_handle = WL_INVALID_HANDLE; + err = esp_vfs_fat_spiflash_mount_rw_wl(base_path, "storage", &mount_config, &wl_handle); +#endif // CONFIG_EXAMPLE_FATFS_MODE_READ_ONLY + + if (err != ESP_OK) { + ESP_LOGE(TAG, "Failed to mount FATFS (%s)python $IDF_PATH/tools/ci/ci_build_apps.py . --target esp32 -vv --pytest-apps", esp_err_to_name(err)); + return; + } + + // Read contents of a file + read_file("/spiflash/filegeneratedonhost.txt"); + + +#ifndef CONFIG_EXAMPLE_FATFS_MODE_READ_ONLY + // Create and write to a file + write_file("/spiflash/messagefromthedevice.txt", "This is written by the device"); + read_file("/spiflash/messagefromthedevice.txt"); +#endif // CONFIG_EXAMPLE_FATFS_MODE_READ_ONLY + + // Check when the file was last modified + stat_file("/spiflash/subdirectoryfromhost/innerfile.txt"); + + // Unmount FATFS + ESP_LOGI(TAG, "Unmounting FAT filesystem"); + +#ifdef CONFIG_EXAMPLE_FATFS_MODE_READ_ONLY + ESP_ERROR_CHECK(esp_vfs_fat_spiflash_unmount_ro(base_path, "storage")); +#else // CONFIG_EXAMPLE_FATFS_MODE_READ_ONLY + ESP_ERROR_CHECK(esp_vfs_fat_spiflash_unmount_rw_wl(base_path, wl_handle)); +#endif // CONFIG_EXAMPLE_FATFS_MODE_READ_ONLY + + ESP_LOGI(TAG, "Done"); +} diff --git a/examples/storage/fatfs_advanced/partitions_example.csv b/examples/storage/fatfs_advanced/partitions_example.csv new file mode 100644 index 00000000000..1c79321a107 --- /dev/null +++ b/examples/storage/fatfs_advanced/partitions_example.csv @@ -0,0 +1,6 @@ +# Name, Type, SubType, Offset, Size, Flags +# Note: if you have increased the bootloader size, make sure to update the offsets to avoid overlap +nvs, data, nvs, 0x9000, 0x6000, +phy_init, data, phy, 0xf000, 0x1000, +factory, app, factory, 0x10000, 1M, +storage, data, fat, , 1M, diff --git a/examples/storage/fatfs_advanced/pytest_fatfs_advanced_example.py b/examples/storage/fatfs_advanced/pytest_fatfs_advanced_example.py new file mode 100644 index 00000000000..ea7f491a8f7 --- /dev/null +++ b/examples/storage/fatfs_advanced/pytest_fatfs_advanced_example.py @@ -0,0 +1,112 @@ +# SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD +# SPDX-License-Identifier: Unlicense OR CC0-1.0 +import re +from datetime import datetime +from typing import List + +import pytest +from pytest_embedded import Dut + + +@pytest.mark.esp32 +@pytest.mark.generic +@pytest.mark.parametrize( + 'config', + [ + 'test_read_only_partition_gen', + 'test_read_only_partition_gen_default_dt', + 'test_read_write_partition_gen', + 'test_read_write_partition_gen_default_dt', + ], + indirect=True, +) +def test_examples_fatfs_advanced(config: str, dut: Dut) -> None: + # Expects list of strings sequentially + def expect_all(msg_list: List[str], to: int) -> None: + for msg in msg_list: + dut.expect(msg, timeout=to) + + # Expects prefix string followed by date in the format 'yyyy-mm-dd' + def expect_date(prefix: str, to: int) -> datetime: + expect_str = prefix + '(\\d+)-(\\d+)-(\\d+)' + match_ = dut.expect(re.compile(str.encode(expect_str)), timeout=to) + year_ = int(match_[1].decode()) + month_ = int(match_[2].decode()) + day_ = int(match_[3].decode()) + return datetime(year_, month_, day_) + + # Calculates absolute difference in days between date_reference and date_actual. + # Raises exception if difference exceeds tolerance + def evaluate_dates( + date_reference: datetime, date_actual: datetime, days_tolerance: int + ) -> None: + td = date_actual - date_reference + if abs(td.days) > days_tolerance: + raise Exception( + f'Too big date difference. Actual: {date_actual}, reference: {date_reference}, tolerance: {days_tolerance} day(s)' + ) + + # Expect timeout + timeout = 20 + + # We tolerate 30 days difference between actual file creation and date when test was executed. + tolerance = 30 + + expected_date = ( + datetime(1980, 1, 1) if config.endswith('default_dt') else datetime.today() + ) + + base_path = '/spiflash/' + folder_name = 'subdirectoryfromhost/' + read_filename = base_path + 'filegeneratedonhost.txt' + write_filename = base_path + 'messagefromthedevice.txt' + stat_filename = base_path + folder_name + 'innerfile.txt' + + dut.expect('example: Mounting FAT filesystem', timeout=timeout) + + # Check read + expect_all( + [ + f'example: Opening file \'{read_filename}\' for reading', + f'example: Reading from file', + 'example: Read from file: \'This is generated on the host; it has long name\'', + f'example: Closing file \'{read_filename}\'', + ], + timeout, + ) + + # Check write + if config.startswith('test_read_write'): + expect_all( + [ + f'example: Opening file \'{write_filename}\' for writing', + 'example: Writing to file', + 'example: File written', + 'example: Closing file', + f'example: Opening file \'{write_filename}\' for reading', + f'example: Reading from file', + 'example: Read from file: \'This is written by the device\'', + f'example: Closing file \'{write_filename}\'', + ], + timeout, + ) + + # Check date using stat + dut.expect( + f'example: Stating file \'{stat_filename}\' for modification time', timeout=timeout + ) + + actual_date = expect_date( + f'The file \'{stat_filename}\' was modified at date: ', timeout + ) + + evaluate_dates(expected_date, actual_date, tolerance) + + # Finish + expect_all( + [ + 'example: Unmounting FAT filesystem', + 'example: Done', + ], + timeout, + ) diff --git a/examples/storage/fatfs_advanced/sdkconfig.ci.test_read_only_partition_gen b/examples/storage/fatfs_advanced/sdkconfig.ci.test_read_only_partition_gen new file mode 100644 index 00000000000..21a7938068c --- /dev/null +++ b/examples/storage/fatfs_advanced/sdkconfig.ci.test_read_only_partition_gen @@ -0,0 +1,5 @@ +CONFIG_EXAMPLE_FATFS_MODE_READ_ONLY=y +CONFIG_FATFS_LFN_HEAP=y +CONFIG_FATFS_LFN_STACK=n +CONFIG_FATFS_LFN_NONE=n +CONFIG_EXAMPLE_FATFS_WRITE_COUNT=300 diff --git a/examples/storage/fatfs_advanced/sdkconfig.ci.test_read_only_partition_gen_default_dt b/examples/storage/fatfs_advanced/sdkconfig.ci.test_read_only_partition_gen_default_dt new file mode 100644 index 00000000000..ed0be2575ba --- /dev/null +++ b/examples/storage/fatfs_advanced/sdkconfig.ci.test_read_only_partition_gen_default_dt @@ -0,0 +1,6 @@ +CONFIG_EXAMPLE_FATFS_MODE_READ_ONLY=y +CONFIG_FATFS_LFN_HEAP=y +CONFIG_FATFS_LFN_STACK=n +CONFIG_FATFS_LFN_NONE=n +CONFIG_EXAMPLE_FATFS_DEFAULT_DATETIME=y +CONFIG_EXAMPLE_FATFS_WRITE_COUNT=300 diff --git a/examples/storage/fatfs_advanced/sdkconfig.ci.test_read_write_partition_gen b/examples/storage/fatfs_advanced/sdkconfig.ci.test_read_write_partition_gen new file mode 100644 index 00000000000..4ffa5532339 --- /dev/null +++ b/examples/storage/fatfs_advanced/sdkconfig.ci.test_read_write_partition_gen @@ -0,0 +1,5 @@ +CONFIG_EXAMPLE_FATFS_MODE_READ_ONLY=n +CONFIG_FATFS_LFN_HEAP=y +CONFIG_FATFS_LFN_STACK=n +CONFIG_FATFS_LFN_NONE=n +CONFIG_EXAMPLE_FATFS_WRITE_COUNT=300 diff --git a/examples/storage/fatfs_advanced/sdkconfig.ci.test_read_write_partition_gen_default_dt b/examples/storage/fatfs_advanced/sdkconfig.ci.test_read_write_partition_gen_default_dt new file mode 100644 index 00000000000..6413768f3e5 --- /dev/null +++ b/examples/storage/fatfs_advanced/sdkconfig.ci.test_read_write_partition_gen_default_dt @@ -0,0 +1,6 @@ +CONFIG_EXAMPLE_FATFS_MODE_READ_ONLY=n +CONFIG_FATFS_LFN_HEAP=y +CONFIG_FATFS_LFN_STACK=n +CONFIG_FATFS_LFN_NONE=n +CONFIG_EXAMPLE_FATFS_DEFAULT_DATETIME=y +CONFIG_EXAMPLE_FATFS_WRITE_COUNT=300 diff --git a/examples/storage/fatfs_advanced/sdkconfig.defaults b/examples/storage/fatfs_advanced/sdkconfig.defaults new file mode 100644 index 00000000000..e5ac9375337 --- /dev/null +++ b/examples/storage/fatfs_advanced/sdkconfig.defaults @@ -0,0 +1,7 @@ +CONFIG_PARTITION_TABLE_CUSTOM=y +CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="partitions_example.csv" +CONFIG_PARTITION_TABLE_FILENAME="partitions_example.csv" +CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y +CONFIG_FATFS_LFN_HEAP=y +CONFIG_FATFS_LFN_NONE=n +CONFIG_FATFS_LFN_STACK=n From 85b5869053e2ba928c3b5553379fa605f85fd491 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Tom=C3=A1=C5=A1=20Rohl=C3=ADnek?= Date: Mon, 5 Aug 2024 14:09:09 +0200 Subject: [PATCH 098/472] feat(storage/fatfs): restructure basic example --- examples/storage/.build-test-rules.yml | 8 ------- examples/storage/fatfs/.build-test-rules.yml | 9 ++++++++ .../getting_started}/CMakeLists.txt | 0 .../getting_started}/README.md | 23 ++++++++++--------- .../fatfs/getting_started/main/CMakeLists.txt | 2 ++ .../main/fatfs_getting_started_main.c} | 6 ++--- .../getting_started}/partitions_example.csv | 0 .../pytest_fatfs_getting_started_example.py} | 4 ++-- .../getting_started}/sdkconfig.defaults | 0 .../storage/fatfs_basic/main/CMakeLists.txt | 2 -- 10 files changed, 28 insertions(+), 26 deletions(-) create mode 100644 examples/storage/fatfs/.build-test-rules.yml rename examples/storage/{fatfs_basic => fatfs/getting_started}/CMakeLists.txt (100%) rename examples/storage/{fatfs_basic => fatfs/getting_started}/README.md (67%) create mode 100644 examples/storage/fatfs/getting_started/main/CMakeLists.txt rename examples/storage/{fatfs_basic/main/fat_example_main.c => fatfs/getting_started/main/fatfs_getting_started_main.c} (93%) rename examples/storage/{fatfs_basic => fatfs/getting_started}/partitions_example.csv (100%) rename examples/storage/{fatfs_basic/pytest_fat_example.py => fatfs/getting_started/pytest_fatfs_getting_started_example.py} (81%) rename examples/storage/{fatfs_basic => fatfs/getting_started}/sdkconfig.defaults (100%) delete mode 100644 examples/storage/fatfs_basic/main/CMakeLists.txt diff --git a/examples/storage/.build-test-rules.yml b/examples/storage/.build-test-rules.yml index 5999ae95eac..8ec3101a5a3 100644 --- a/examples/storage/.build-test-rules.yml +++ b/examples/storage/.build-test-rules.yml @@ -42,14 +42,6 @@ examples/storage/fatfs_advanced: - if: IDF_TARGET != "esp32" reason: only one target needed -examples/storage/fatfs_basic: - depends_components: - - fatfs - - vfs - disable_test: - - if: IDF_TARGET != "esp32" - reason: only one target needed - examples/storage/nvs_rw_blob: depends_components: - nvs_flash diff --git a/examples/storage/fatfs/.build-test-rules.yml b/examples/storage/fatfs/.build-test-rules.yml new file mode 100644 index 00000000000..f652dd52d8e --- /dev/null +++ b/examples/storage/fatfs/.build-test-rules.yml @@ -0,0 +1,9 @@ +# Documentation: .gitlab/ci/README.md#manifest-file-to-control-the-buildtest-apps + +examples/storage/fatfs: + depends_components: + - fatfs + - vfs + disable_test: + - if: IDF_TARGET != "esp32" + reason: only one target needed diff --git a/examples/storage/fatfs_basic/CMakeLists.txt b/examples/storage/fatfs/getting_started/CMakeLists.txt similarity index 100% rename from examples/storage/fatfs_basic/CMakeLists.txt rename to examples/storage/fatfs/getting_started/CMakeLists.txt diff --git a/examples/storage/fatfs_basic/README.md b/examples/storage/fatfs/getting_started/README.md similarity index 67% rename from examples/storage/fatfs_basic/README.md rename to examples/storage/fatfs/getting_started/README.md index 0ee84f105df..626f9323cbb 100644 --- a/examples/storage/fatfs_basic/README.md +++ b/examples/storage/fatfs/getting_started/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- | # FATFS minimal example @@ -29,15 +29,16 @@ Here is the example's console output: ``` ... -I (339) example: Mounting FAT filesystem -I (339) example: Filesystem mounted -I (339) example: Opening file -I (729) example: File written -I (729) example: Reading file -I (739) example: Read from file: 'This is written by the device' -I (739) example: Unmounting FAT filesystem -I (849) example: Done +I (321) example: Mounting FAT filesystem +I (331) example: Filesystem mounted +I (331) example: Opening file +I (731) example: File written +I (731) example: Reading file +I (741) example: Read from file: 'Hello World!' +I (741) example: Unmounting FAT filesystem +I (851) example: Done +... ``` -The logic of the example is contained in a [single source file](./main/fat_example_main.c), +The logic of the example is contained in a [single source file](./main/fatfs_getting_started_main.c), and it should be relatively simple to match points in its execution with the log outputs above. diff --git a/examples/storage/fatfs/getting_started/main/CMakeLists.txt b/examples/storage/fatfs/getting_started/main/CMakeLists.txt new file mode 100644 index 00000000000..fec5d19cada --- /dev/null +++ b/examples/storage/fatfs/getting_started/main/CMakeLists.txt @@ -0,0 +1,2 @@ +idf_component_register(SRCS "fatfs_getting_started_main.c" + INCLUDE_DIRS ".") diff --git a/examples/storage/fatfs_basic/main/fat_example_main.c b/examples/storage/fatfs/getting_started/main/fatfs_getting_started_main.c similarity index 93% rename from examples/storage/fatfs_basic/main/fat_example_main.c rename to examples/storage/fatfs/getting_started/main/fatfs_getting_started_main.c index 2a57821e70d..ae8529160e0 100644 --- a/examples/storage/fatfs_basic/main/fat_example_main.c +++ b/examples/storage/fatfs/getting_started/main/fatfs_getting_started_main.c @@ -31,8 +31,8 @@ void app_main(void) .use_one_fat = false, // Use only one FAT table (reduce memory usage), but decrease reliability of file system in case of power failure. }; + // Mount FATFS filesystem located on "storage" partition in read-write mode esp_err_t err = esp_vfs_fat_spiflash_mount_rw_wl(base_path, "storage", &mount_config, &s_wl_handle); - if (err != ESP_OK) { ESP_LOGE(TAG, "Failed to mount FATFS (%s)", esp_err_to_name(err)); return; @@ -46,12 +46,12 @@ void app_main(void) FILE *f = fopen(filename, "wb"); if (f == NULL) { - perror("fopen"); + perror("fopen"); // Print reason why fopen failed ESP_LOGE(TAG, "Failed to open file for writing"); return; } - fprintf(f, "This is written by the device"); + fprintf(f, "Hello World!\n"); fclose(f); ESP_LOGI(TAG, "File written"); diff --git a/examples/storage/fatfs_basic/partitions_example.csv b/examples/storage/fatfs/getting_started/partitions_example.csv similarity index 100% rename from examples/storage/fatfs_basic/partitions_example.csv rename to examples/storage/fatfs/getting_started/partitions_example.csv diff --git a/examples/storage/fatfs_basic/pytest_fat_example.py b/examples/storage/fatfs/getting_started/pytest_fatfs_getting_started_example.py similarity index 81% rename from examples/storage/fatfs_basic/pytest_fat_example.py rename to examples/storage/fatfs/getting_started/pytest_fatfs_getting_started_example.py index 7abafe062de..e7f9d7d78a7 100644 --- a/examples/storage/fatfs_basic/pytest_fat_example.py +++ b/examples/storage/fatfs/getting_started/pytest_fatfs_getting_started_example.py @@ -6,12 +6,12 @@ @pytest.mark.esp32 @pytest.mark.generic -def test_examples_fatfs_basic(dut: Dut) -> None: +def test_examples_fatfs_getting_started(dut: Dut) -> None: dut.expect('example: Mounting FAT filesystem', timeout=90) dut.expect('example: Filesystem mounted', timeout=90) dut.expect('example: Opening file', timeout=90) dut.expect('example: File written', timeout=90) dut.expect('example: Reading file', timeout=90) - dut.expect('example: Read from file: \'This is written by the device\'', timeout=90) + dut.expect('example: Read from file: \'Hello World!\'', timeout=90) dut.expect('example: Unmounting FAT filesystem', timeout=90) dut.expect('example: Done', timeout=90) diff --git a/examples/storage/fatfs_basic/sdkconfig.defaults b/examples/storage/fatfs/getting_started/sdkconfig.defaults similarity index 100% rename from examples/storage/fatfs_basic/sdkconfig.defaults rename to examples/storage/fatfs/getting_started/sdkconfig.defaults diff --git a/examples/storage/fatfs_basic/main/CMakeLists.txt b/examples/storage/fatfs_basic/main/CMakeLists.txt deleted file mode 100644 index 827c3c2e8e0..00000000000 --- a/examples/storage/fatfs_basic/main/CMakeLists.txt +++ /dev/null @@ -1,2 +0,0 @@ -idf_component_register(SRCS "fat_example_main.c" - INCLUDE_DIRS ".") From 587290567d8a6df7820e0f809c55a17385c479f8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Tom=C3=A1=C5=A1=20Rohl=C3=ADnek?= Date: Mon, 5 Aug 2024 14:12:16 +0200 Subject: [PATCH 099/472] feat(storage/fatfs): restructure advanced example --- examples/storage/.build-test-rules.yml | 8 - .../fs_operations}/CMakeLists.txt | 0 .../storage/fatfs/fs_operations/README.md | 94 ++++++++ .../fatfs/fs_operations/main/CMakeLists.txt | 2 + .../main/fatfs_fs_operations_example_main.c | 207 ++++++++++++++++++ .../fs_operations}/partitions_example.csv | 0 .../pytest_fatfs_fs_operations_example.py | 80 +++++++ .../fs_operations}/sdkconfig.defaults | 0 examples/storage/fatfs_advanced/README.md | 69 ------ .../filegeneratedonhost.txt | 1 - .../subdirectoryfromhost/innerfile.txt | 1 - .../fatfs_advanced/main/CMakeLists.txt | 26 --- .../fatfs_advanced/main/Kconfig.projbuild | 24 -- .../main/fatfs_advanced_example_main.c | 138 ------------ .../pytest_fatfs_advanced_example.py | 112 ---------- .../sdkconfig.ci.test_read_only_partition_gen | 5 - ...ci.test_read_only_partition_gen_default_dt | 6 - ...sdkconfig.ci.test_read_write_partition_gen | 5 - ...i.test_read_write_partition_gen_default_dt | 6 - 19 files changed, 383 insertions(+), 401 deletions(-) rename examples/storage/{fatfs_advanced => fatfs/fs_operations}/CMakeLists.txt (100%) create mode 100644 examples/storage/fatfs/fs_operations/README.md create mode 100644 examples/storage/fatfs/fs_operations/main/CMakeLists.txt create mode 100644 examples/storage/fatfs/fs_operations/main/fatfs_fs_operations_example_main.c rename examples/storage/{fatfs_advanced => fatfs/fs_operations}/partitions_example.csv (100%) create mode 100644 examples/storage/fatfs/fs_operations/pytest_fatfs_fs_operations_example.py rename examples/storage/{fatfs_advanced => fatfs/fs_operations}/sdkconfig.defaults (100%) delete mode 100644 examples/storage/fatfs_advanced/README.md delete mode 100644 examples/storage/fatfs_advanced/fatfs_long_name_image/filegeneratedonhost.txt delete mode 100644 examples/storage/fatfs_advanced/fatfs_long_name_image/subdirectoryfromhost/innerfile.txt delete mode 100644 examples/storage/fatfs_advanced/main/CMakeLists.txt delete mode 100644 examples/storage/fatfs_advanced/main/Kconfig.projbuild delete mode 100644 examples/storage/fatfs_advanced/main/fatfs_advanced_example_main.c delete mode 100644 examples/storage/fatfs_advanced/pytest_fatfs_advanced_example.py delete mode 100644 examples/storage/fatfs_advanced/sdkconfig.ci.test_read_only_partition_gen delete mode 100644 examples/storage/fatfs_advanced/sdkconfig.ci.test_read_only_partition_gen_default_dt delete mode 100644 examples/storage/fatfs_advanced/sdkconfig.ci.test_read_write_partition_gen delete mode 100644 examples/storage/fatfs_advanced/sdkconfig.ci.test_read_write_partition_gen_default_dt diff --git a/examples/storage/.build-test-rules.yml b/examples/storage/.build-test-rules.yml index 8ec3101a5a3..341e0f595a8 100644 --- a/examples/storage/.build-test-rules.yml +++ b/examples/storage/.build-test-rules.yml @@ -34,14 +34,6 @@ examples/storage/ext_flash_fatfs: temporary: true reason: lack of runners -examples/storage/fatfs_advanced: - depends_components: - - fatfs - - vfs - disable_test: - - if: IDF_TARGET != "esp32" - reason: only one target needed - examples/storage/nvs_rw_blob: depends_components: - nvs_flash diff --git a/examples/storage/fatfs_advanced/CMakeLists.txt b/examples/storage/fatfs/fs_operations/CMakeLists.txt similarity index 100% rename from examples/storage/fatfs_advanced/CMakeLists.txt rename to examples/storage/fatfs/fs_operations/CMakeLists.txt diff --git a/examples/storage/fatfs/fs_operations/README.md b/examples/storage/fatfs/fs_operations/README.md new file mode 100644 index 00000000000..e11f3077b50 --- /dev/null +++ b/examples/storage/fatfs/fs_operations/README.md @@ -0,0 +1,94 @@ +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- | + +# FATFS Filesystem Operations Example + +(See the README.md file in the upper level 'examples' directory for more information about examples.) + +This example demonstrates some of the POSIX functions available for working with the FATFS filesystem. +Including basic read and write operations, as well as creating moving, and deleting files and directories. + +## Overview + +1. Partition labeled `storage` is mounted (and formatted if necessary) as FATFS filesystem to `/spiflash` mountpoint. + +2. All existing files and directories in the root directory are deleted. + +3. File `hello.txt` is created and written to. + +4. File `hello.txt` is inspected using `fstat` function showing file size and last modification time. + +5. File `hello.txt` is written to again, appending to the end of the file. + +6. File `hello.txt` is read from and the contents are printed to the console. + +7. New directory `new_dir` is created. + +8. All files and directories in the root directory are listed. + +9. File `hello.txt` is moved and renamed to `new_dir/hello_renamed.txt`. + +## How to use example + +### Build and flash + +To run the example, type the following command: + +```CMake +# CMake +idf.py -p PORT flash monitor +``` + +(To exit the serial monitor, type ``Ctrl-]``.) + +See the Getting Started Guide for full steps to configure and use ESP-IDF to build projects. + +## Example output + +Here is the example's console output: + +``` +... +I (323) example: Mounting FAT filesystem +I (333) example: Deleting everything in /spiflash: +I (333) example: Deleting everything in /spiflash/new_dir: +I (673) example: Creating a file +I (683) example: Writing to the file +I (733) example: File stats: + File size: 13 bytes + File modification time: Thu Jan 1 00:00:00 1970 + +I (743) example: Wait for 1 seconds +I (1743) example: Write more to the file +I (1743) example: File stats: + File size: 26 bytes + File modification time: Thu Jan 1 00:00:00 1970 + +I (1743) example: Go to the beginning of the file +I (1753) example: Reading from file: +Hello World! +Hello World! + +I (1753) example: Closing file +I (1993) example: Listing files in /spiflash: +/spiflash: + file : hello.txt +I (1993) example: Creating a new directory +I (2383) example: Listing files in /spiflash: +/spiflash: + file : hello.txt + directory: new_dir +I (2383) example: Rename a file +I (2503) example: Listing files in /spiflash: +/spiflash: + directory: new_dir +I (2503) example: Listing files in /spiflash/new_dir: +/spiflash/new_dir: + file : hello_renamed.txt +I (2513) example: Unmounting FAT filesystem +I (2643) example: Done +... +``` + +The logic of the example is contained in a [single source file](./main/fatfs_fs_operations_example_main.c), +and it should be relatively simple to match points in its execution with the log outputs above. diff --git a/examples/storage/fatfs/fs_operations/main/CMakeLists.txt b/examples/storage/fatfs/fs_operations/main/CMakeLists.txt new file mode 100644 index 00000000000..a5ae965fc4c --- /dev/null +++ b/examples/storage/fatfs/fs_operations/main/CMakeLists.txt @@ -0,0 +1,2 @@ +idf_component_register(SRCS "fatfs_fs_operations_example_main.c" + INCLUDE_DIRS ".") diff --git a/examples/storage/fatfs/fs_operations/main/fatfs_fs_operations_example_main.c b/examples/storage/fatfs/fs_operations/main/fatfs_fs_operations_example_main.c new file mode 100644 index 00000000000..c2dd5bc226a --- /dev/null +++ b/examples/storage/fatfs/fs_operations/main/fatfs_fs_operations_example_main.c @@ -0,0 +1,207 @@ +/* + * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Unlicense OR CC0-1.0 + */ + +#include +#include +#include +#include +#include +#include +#include +#include "esp_vfs.h" +#include "esp_vfs_fat.h" +#include "sdkconfig.h" + +static const char *TAG = "example"; + +// Mount path for the partition +static const char *base_path = "/spiflash"; + +// File name +static const char *filename = "/spiflash/hello.txt"; + +// Function to dump contents of a directory +static void list_dir(const char *path); + +// Best effort recursive function to clean a directory +static void clean_dir(const char *path); + +void app_main(void) +{ + ESP_LOGI(TAG, "Mounting FAT filesystem"); + + // To mount device we need name of device partition, define base_path + // and allow format partition in case if it is new one and was not formatted before + const esp_vfs_fat_mount_config_t mount_config = { + .max_files = 4, + .format_if_mount_failed = true, + .allocation_unit_size = CONFIG_WL_SECTOR_SIZE, + .use_one_fat = false, + }; + + wl_handle_t wl_handle = WL_INVALID_HANDLE; + + esp_err_t err = ESP_OK; + + err = esp_vfs_fat_spiflash_mount_rw_wl(base_path, "storage", &mount_config, &wl_handle); + if (err != ESP_OK) { + ESP_LOGE(TAG, "Failed to mount FATFS (%s)", esp_err_to_name(err)); + return; + } + + // Ensure the working directory is empty + clean_dir(base_path); + + ESP_LOGI(TAG, "Creating a file"); + + // Unlike C standard library which uses FILE*, POSIX API uses file descriptors for file operations + int fd = open(filename, O_RDWR | O_CREAT | O_TRUNC, 0); + if (fd < 0) { + ESP_LOGE(TAG, "Failed to open file for writing"); + return; + } + + ESP_LOGI(TAG, "Writing to the file"); + const char *text = "Hello World!\n"; + write(fd, text, strlen(text)); + + struct stat info; + // We have to use `stat` instead of `fstat`, because `fstat` currently isn't fully supported + if (stat(filename, &info) < 0) { + ESP_LOGE(TAG, "Failed to stat file: %s", strerror(errno)); + close(fd); + return; + } + + ESP_LOGI( + TAG, + "File stats:\n" + "\tFile size: %ld bytes\n" + "\tFile modification time: %s", + info.st_size, + ctime(&info.st_mtime) + ); + + ESP_LOGI(TAG, "Wait for 3 seconds"); + sleep(3); + + ESP_LOGI(TAG, "Write more to the file"); + write(fd, text, strlen(text)); + + ESP_LOGI(TAG, "Force cached data and metadata to the filesystem"); + fsync(fd); + + if (stat(filename, &info) < 0) { + ESP_LOGE(TAG, "Failed to stat file: %s", strerror(errno)); + close(fd); + return; + } + + ESP_LOGI( + TAG, + "File stats:\n" + "\tFile size: %ld bytes\n" + "\tFile modification time: %s", + info.st_size, + ctime(&info.st_mtime) + ); + + ESP_LOGI(TAG, "Go to the beginning of the file"); + lseek(fd, 0, SEEK_SET); + + ESP_LOGI(TAG, "Reading from file:"); + + char buf[128] = {0}; + + ssize_t len = read(fd, buf, sizeof(buf) - 1); + if (len < 0) { + ESP_LOGE(TAG, "Failed to read file: %s", strerror(errno)); + close(fd); + return; + } + + printf("%.*s\n", len, buf); + + ESP_LOGI(TAG, "Closing file"); + close(fd); + + // List files in the directory + list_dir(base_path); + + ESP_LOGI(TAG, "Creating a new directory"); + if (mkdir("/spiflash/new_dir", 0777) < 0) { + ESP_LOGE(TAG, "Failed to create a new directory: %s", strerror(errno)); + return; + } + + // List files in the directory + list_dir(base_path); + + ESP_LOGI(TAG, "Rename a file"); + + if (rename(filename, "/spiflash/new_dir/hello_renamed.txt") < 0) { + ESP_LOGE(TAG, "Failed to rename file: %s", strerror(errno)); + return; + } + + // List files in the directory + list_dir(base_path); + list_dir("/spiflash/new_dir"); + + ESP_LOGI(TAG, "Unmounting FAT filesystem"); + ESP_ERROR_CHECK(esp_vfs_fat_spiflash_unmount_rw_wl(base_path, wl_handle)); + + ESP_LOGI(TAG, "Done"); +} + +void list_dir(const char *path) +{ + ESP_LOGI(TAG, "Listing files in %s:", path); + + DIR *dir = opendir(path); + if (!dir) { + ESP_LOGE(TAG, "Failed to open directory: %s", strerror(errno)); + return; + } + + printf("%s:\n", path); + struct dirent *entry; + while ((entry = readdir(dir)) != NULL) { + printf( + " %s: %s\n", + (entry->d_type == DT_DIR) + ? "directory" + : "file ", + entry->d_name + ); + } + + closedir(dir); +} + +void clean_dir(const char *path) +{ + ESP_LOGI(TAG, "Deleting everything in %s:", path); + + DIR *dir = opendir(path); + if (!dir) { + ESP_LOGE(TAG, "Failed to open directory: %s", strerror(errno)); + return; + } + + struct dirent *entry; + while ((entry = readdir(dir)) != NULL) { + char full_path[64] = {0}; + snprintf(full_path, sizeof(full_path), "%.20s/%.40s", path, entry->d_name); + if (entry->d_type == DT_DIR) + clean_dir(full_path); + if (remove(full_path) != 0) { + ESP_LOGE(TAG, "Failed to remove %s: %s", full_path, strerror(errno)); + } + } + + closedir(dir); +} diff --git a/examples/storage/fatfs_advanced/partitions_example.csv b/examples/storage/fatfs/fs_operations/partitions_example.csv similarity index 100% rename from examples/storage/fatfs_advanced/partitions_example.csv rename to examples/storage/fatfs/fs_operations/partitions_example.csv diff --git a/examples/storage/fatfs/fs_operations/pytest_fatfs_fs_operations_example.py b/examples/storage/fatfs/fs_operations/pytest_fatfs_fs_operations_example.py new file mode 100644 index 00000000000..4067c80d134 --- /dev/null +++ b/examples/storage/fatfs/fs_operations/pytest_fatfs_fs_operations_example.py @@ -0,0 +1,80 @@ +# SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD +# SPDX-License-Identifier: Unlicense OR CC0-1.0 +from datetime import datetime +from typing import List + +import pytest +from pytest_embedded import Dut + + +@pytest.mark.esp32 +@pytest.mark.generic +def test_examples_fatfs_fs_operations(config: str, dut: Dut) -> None: + # Expects list of strings sequentially + def expect_all(msg_list: List[str], to: int) -> None: + for msg in msg_list: + dut.expect(msg, timeout=to) + + def parse_date() -> datetime: + months = ['Jan', 'Feb', 'Mar', 'Apr', 'May', 'Jun', 'Jul', 'Aug', 'Sep', 'Oct', 'Nov', 'Dec'] + + pattern = r'([A-Z][a-z]{2}) ([A-Z][a-z]{2}) ([ \d]\d) (\d{2}):(\d{2}):(\d{2}) (\d{4})' + + match = dut.expect(pattern) + return datetime( + month=months.index(match[2].decode('utf-8')) + 1, + day=int(match[3]), + hour=int(match[4]), + minute=int(match[5]), + second=int(match[6]), + year=int(match[7]), + ) + + expect_all( + [ + 'example: Mounting FAT filesystem', + 'example: Creating a file', + 'example: Writing to the file', + 'example: File stats:', + 'File size:', + ], + 5 + ) + + original = parse_date() + + expect_all( + [ + 'example: Wait for 3 seconds', + 'example: Write more to the file', + 'example: Force cached data and metadata to the filesystem', + 'File size:', + ], + 5 + ) + + updated = parse_date() + + assert updated > original + + expect_all( + [ + 'example: Go to the beginning of the file', + 'example: Reading from file', + 'Hello World!', + 'Hello World!', + 'example: Closing file', + 'example: Listing files in /spiflash:', + 'hello.txt', + 'example: Creating a new directory', + 'example: Listing files in /spiflash:', + 'hello.txt', + 'new_dir', + 'example: Rename a file', + 'example: Listing files in /spiflash:', + 'new_dir', + 'example: Listing files in /spiflash/new_dir:', + 'hello_renamed.txt', + ], + 5 + ) diff --git a/examples/storage/fatfs_advanced/sdkconfig.defaults b/examples/storage/fatfs/fs_operations/sdkconfig.defaults similarity index 100% rename from examples/storage/fatfs_advanced/sdkconfig.defaults rename to examples/storage/fatfs/fs_operations/sdkconfig.defaults diff --git a/examples/storage/fatfs_advanced/README.md b/examples/storage/fatfs_advanced/README.md deleted file mode 100644 index 34ab038fc54..00000000000 --- a/examples/storage/fatfs_advanced/README.md +++ /dev/null @@ -1,69 +0,0 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | - -# FATFS partition generation example - -(See the README.md file in the upper level 'examples' directory for more information about examples.) - -This example demonstrates how to use the FATFS partition -generation tool [fatfsgen.py](../../../components/fatfs/fatfsgen.py) to automatically create a FATFS -filesystem image from the contents of a host folder during build, with an option of -automatically flashing the created image on invocation of `idf.py -p PORT flash` as well as usage of long file names for FATFS. -Beware that the minimal required size of the flash is 4 MB. -You can specify using menuconfig weather example will use read-only or read-write mode. The default option is read-write mode. -To change it just use menuconfig: - -```shell -idf.py menuconfig -``` - -Then select `Example Configuration` a chose `Mode for generated FATFS image` either `Read-Write Mode` or `Read-Only Mode`. -`Read-Only` option indicates generating raw fatfs image without wear levelling support. -On the other hand, for `Read-Write` the generated fatfs image will support wear levelling thus can be mounted in read-write mode. - - -The following gives an overview of the example: - -1. There is a directory `fatfs_image` from which the FATFS filesystem image will be created. - -2. The function `fatfs_create_rawflash_image` is used to specify that a FATFS image -should be created during build for the `storage` partition. -For CMake, it is called from [the main component's CMakeLists.txt](./main/CMakeLists.txt). -`FLASH_IN_PROJECT` specifies that the created image -should be flashed on invocation of `idf.py -p PORT flash` together with app, bootloader, partition table, etc. -The image is created on the example's build directory with the output filename `storage.bin`. - -3. Upon invocation of `idf.py -p PORT flash monitor`, application loads and -finds there is already a valid FATFS filesystem in the `storage` partition with files same as those in `fatfs_image` directory. The application is then -able to read those files. - -## How to use example - -### Build and flash - -To run the example, type the following command: - -```CMake -# CMake -idf.py -p PORT flash monitor -``` - -(To exit the serial monitor, type ``Ctrl-]``.) - -See the Getting Started Guide for full steps to configure and use ESP-IDF to build projects. - -## Example output - -Here is the example's console output: - -``` -... -I (322) example: Mounting FAT filesystem -I (332) example: Reading file -I (332) example: Read from file: 'this is test' -I (332) example: Unmounting FAT filesystem -I (342) example: Done -``` - -The logic of the example is contained in a [single source file](./main/fatfsgen_example_main.c), -and it should be relatively simple to match points in its execution with the log outputs above. diff --git a/examples/storage/fatfs_advanced/fatfs_long_name_image/filegeneratedonhost.txt b/examples/storage/fatfs_advanced/fatfs_long_name_image/filegeneratedonhost.txt deleted file mode 100644 index 33f47c9b1db..00000000000 --- a/examples/storage/fatfs_advanced/fatfs_long_name_image/filegeneratedonhost.txt +++ /dev/null @@ -1 +0,0 @@ -This is generated on the host; it has long name diff --git a/examples/storage/fatfs_advanced/fatfs_long_name_image/subdirectoryfromhost/innerfile.txt b/examples/storage/fatfs_advanced/fatfs_long_name_image/subdirectoryfromhost/innerfile.txt deleted file mode 100644 index 84505e3d3e7..00000000000 --- a/examples/storage/fatfs_advanced/fatfs_long_name_image/subdirectoryfromhost/innerfile.txt +++ /dev/null @@ -1 +0,0 @@ -this is test; it has long name diff --git a/examples/storage/fatfs_advanced/main/CMakeLists.txt b/examples/storage/fatfs_advanced/main/CMakeLists.txt deleted file mode 100644 index 28eed4c7c32..00000000000 --- a/examples/storage/fatfs_advanced/main/CMakeLists.txt +++ /dev/null @@ -1,26 +0,0 @@ -idf_component_register(SRCS "fatfs_advanced_example_main.c" - INCLUDE_DIRS ".") - -# Create a FATFS image from the contents of the 'fatfs_image' directory -# that fits the partition named 'storage'. FLASH_IN_PROJECT indicates that -# the generated image should be flashed when the entire project is flashed to -# the target with 'idf.py -p PORT flash'. -# If read-only mode is set (CONFIG_EXAMPLE_FATFS_MODE_READ_ONLY) -# the generated image will be raw without wear levelling support. -# Otherwise it will support wear levelling and thus enable read-write mounting of the image in the device. - -set(image ../fatfs_long_name_image) - -if(CONFIG_EXAMPLE_FATFS_MODE_READ_ONLY) - if(CONFIG_EXAMPLE_FATFS_DEFAULT_DATETIME) - fatfs_create_rawflash_image(storage ${image} FLASH_IN_PROJECT) - else() - fatfs_create_rawflash_image(storage ${image} FLASH_IN_PROJECT PRESERVE_TIME) - endif() -else() - if(CONFIG_EXAMPLE_FATFS_DEFAULT_DATETIME) - fatfs_create_spiflash_image(storage ${image} FLASH_IN_PROJECT) - else() - fatfs_create_spiflash_image(storage ${image} FLASH_IN_PROJECT PRESERVE_TIME) - endif() -endif() diff --git a/examples/storage/fatfs_advanced/main/Kconfig.projbuild b/examples/storage/fatfs_advanced/main/Kconfig.projbuild deleted file mode 100644 index b715c917b84..00000000000 --- a/examples/storage/fatfs_advanced/main/Kconfig.projbuild +++ /dev/null @@ -1,24 +0,0 @@ -menu "Example Configuration" - - config EXAMPLE_FATFS_MODE_READ_ONLY - bool "Read only mode for generated FATFS image" - default n - help - If read-only mode is set, the generated fatfs image will be raw (without wear levelling support). - Otherwise it will support wear levelling that enables read-write mounting. - - config EXAMPLE_FATFS_WRITE_COUNT - int "Number of volumes" - default 1 - range 1 600 - help - Number of writes to the file (for testing purposes). - - config EXAMPLE_FATFS_DEFAULT_DATETIME - bool "Default modification date and time for generated FATFS image" - default n - help - If default datetime is set, all files created in the generated FATFS partition have default time - equal to FATFS origin time (1 January 1980) - -endmenu diff --git a/examples/storage/fatfs_advanced/main/fatfs_advanced_example_main.c b/examples/storage/fatfs_advanced/main/fatfs_advanced_example_main.c deleted file mode 100644 index 3d8032b163e..00000000000 --- a/examples/storage/fatfs_advanced/main/fatfs_advanced_example_main.c +++ /dev/null @@ -1,138 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Unlicense OR CC0-1.0 - */ - -#include -#include -#include -#include -#include "esp_vfs.h" -#include "esp_vfs_fat.h" -#include "sdkconfig.h" - -static const char *TAG = "example"; - -// Mount path for the partition -const char *base_path = "/spiflash"; - -void write_file(const char *filename, const char *data) -{ - ESP_LOGI(TAG, "Opening file '%s' for writing", filename); - - FILE *f = fopen(filename, "w"); - if (f == NULL) { - ESP_LOGE(TAG, "Failed to open file for writing: %s", strerror(errno)); - return; - } - - ESP_LOGI(TAG, "Writing to file"); - - fputs(data, f); - - ESP_LOGI(TAG, "File written"); - - ESP_LOGI(TAG, "Closing file"); - fclose(f); -} - -void read_file(const char *filename) -{ - ESP_LOGI(TAG, "Opening file '%s' for reading", filename); - - FILE *f = fopen(filename, "r"); - if (f == NULL) { - ESP_LOGE(TAG, "Failed to open file for reading: %s", strerror(errno)); - return; - } - - ESP_LOGI(TAG, "Reading from file"); - - char line[128]; - fgets(line, sizeof(line), f); - - // strip newline - char *pos = strchr(line, '\n'); - if (pos) { - *pos = '\0'; // strip newline - } - - ESP_LOGI(TAG, "Read from file: '%s'", line); - - ESP_LOGI(TAG, "Closing file '%s'", filename); - fclose(f); -} - -void stat_file(const char *filename) -{ - - struct stat info; - struct tm timeinfo; - char buffer[32]; - - ESP_LOGI(TAG, "Stating file '%s' for modification time", filename); - - if(stat(filename, &info) < 0){ - ESP_LOGE(TAG, "Failed to read file stats: %s", strerror(errno)); - return; - } - localtime_r(&info.st_mtime, &timeinfo); - strftime(buffer, sizeof(buffer), "%Y-%m-%d", &timeinfo); - - ESP_LOGI(TAG, "The file '%s' was modified at date: %s", filename, buffer); -} - -void app_main(void) -{ - ESP_LOGI(TAG, "Mounting FAT filesystem"); - - // To mount device we need name of device partition, define base_path - // and allow format partition in case if it is new one and was not formatted before - const esp_vfs_fat_mount_config_t mount_config = { - .max_files = 4, - .format_if_mount_failed = false, - .allocation_unit_size = CONFIG_WL_SECTOR_SIZE, - .use_one_fat = false, - }; - - esp_err_t err; - -#ifdef CONFIG_EXAMPLE_FATFS_MODE_READ_ONLY - err = esp_vfs_fat_spiflash_mount_ro(base_path, "storage", &mount_config); -#else // CONFIG_EXAMPLE_FATFS_MODE_READ_ONLY - - // Handle of the wear levelling library instance - wl_handle_t wl_handle = WL_INVALID_HANDLE; - err = esp_vfs_fat_spiflash_mount_rw_wl(base_path, "storage", &mount_config, &wl_handle); -#endif // CONFIG_EXAMPLE_FATFS_MODE_READ_ONLY - - if (err != ESP_OK) { - ESP_LOGE(TAG, "Failed to mount FATFS (%s)python $IDF_PATH/tools/ci/ci_build_apps.py . --target esp32 -vv --pytest-apps", esp_err_to_name(err)); - return; - } - - // Read contents of a file - read_file("/spiflash/filegeneratedonhost.txt"); - - -#ifndef CONFIG_EXAMPLE_FATFS_MODE_READ_ONLY - // Create and write to a file - write_file("/spiflash/messagefromthedevice.txt", "This is written by the device"); - read_file("/spiflash/messagefromthedevice.txt"); -#endif // CONFIG_EXAMPLE_FATFS_MODE_READ_ONLY - - // Check when the file was last modified - stat_file("/spiflash/subdirectoryfromhost/innerfile.txt"); - - // Unmount FATFS - ESP_LOGI(TAG, "Unmounting FAT filesystem"); - -#ifdef CONFIG_EXAMPLE_FATFS_MODE_READ_ONLY - ESP_ERROR_CHECK(esp_vfs_fat_spiflash_unmount_ro(base_path, "storage")); -#else // CONFIG_EXAMPLE_FATFS_MODE_READ_ONLY - ESP_ERROR_CHECK(esp_vfs_fat_spiflash_unmount_rw_wl(base_path, wl_handle)); -#endif // CONFIG_EXAMPLE_FATFS_MODE_READ_ONLY - - ESP_LOGI(TAG, "Done"); -} diff --git a/examples/storage/fatfs_advanced/pytest_fatfs_advanced_example.py b/examples/storage/fatfs_advanced/pytest_fatfs_advanced_example.py deleted file mode 100644 index ea7f491a8f7..00000000000 --- a/examples/storage/fatfs_advanced/pytest_fatfs_advanced_example.py +++ /dev/null @@ -1,112 +0,0 @@ -# SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD -# SPDX-License-Identifier: Unlicense OR CC0-1.0 -import re -from datetime import datetime -from typing import List - -import pytest -from pytest_embedded import Dut - - -@pytest.mark.esp32 -@pytest.mark.generic -@pytest.mark.parametrize( - 'config', - [ - 'test_read_only_partition_gen', - 'test_read_only_partition_gen_default_dt', - 'test_read_write_partition_gen', - 'test_read_write_partition_gen_default_dt', - ], - indirect=True, -) -def test_examples_fatfs_advanced(config: str, dut: Dut) -> None: - # Expects list of strings sequentially - def expect_all(msg_list: List[str], to: int) -> None: - for msg in msg_list: - dut.expect(msg, timeout=to) - - # Expects prefix string followed by date in the format 'yyyy-mm-dd' - def expect_date(prefix: str, to: int) -> datetime: - expect_str = prefix + '(\\d+)-(\\d+)-(\\d+)' - match_ = dut.expect(re.compile(str.encode(expect_str)), timeout=to) - year_ = int(match_[1].decode()) - month_ = int(match_[2].decode()) - day_ = int(match_[3].decode()) - return datetime(year_, month_, day_) - - # Calculates absolute difference in days between date_reference and date_actual. - # Raises exception if difference exceeds tolerance - def evaluate_dates( - date_reference: datetime, date_actual: datetime, days_tolerance: int - ) -> None: - td = date_actual - date_reference - if abs(td.days) > days_tolerance: - raise Exception( - f'Too big date difference. Actual: {date_actual}, reference: {date_reference}, tolerance: {days_tolerance} day(s)' - ) - - # Expect timeout - timeout = 20 - - # We tolerate 30 days difference between actual file creation and date when test was executed. - tolerance = 30 - - expected_date = ( - datetime(1980, 1, 1) if config.endswith('default_dt') else datetime.today() - ) - - base_path = '/spiflash/' - folder_name = 'subdirectoryfromhost/' - read_filename = base_path + 'filegeneratedonhost.txt' - write_filename = base_path + 'messagefromthedevice.txt' - stat_filename = base_path + folder_name + 'innerfile.txt' - - dut.expect('example: Mounting FAT filesystem', timeout=timeout) - - # Check read - expect_all( - [ - f'example: Opening file \'{read_filename}\' for reading', - f'example: Reading from file', - 'example: Read from file: \'This is generated on the host; it has long name\'', - f'example: Closing file \'{read_filename}\'', - ], - timeout, - ) - - # Check write - if config.startswith('test_read_write'): - expect_all( - [ - f'example: Opening file \'{write_filename}\' for writing', - 'example: Writing to file', - 'example: File written', - 'example: Closing file', - f'example: Opening file \'{write_filename}\' for reading', - f'example: Reading from file', - 'example: Read from file: \'This is written by the device\'', - f'example: Closing file \'{write_filename}\'', - ], - timeout, - ) - - # Check date using stat - dut.expect( - f'example: Stating file \'{stat_filename}\' for modification time', timeout=timeout - ) - - actual_date = expect_date( - f'The file \'{stat_filename}\' was modified at date: ', timeout - ) - - evaluate_dates(expected_date, actual_date, tolerance) - - # Finish - expect_all( - [ - 'example: Unmounting FAT filesystem', - 'example: Done', - ], - timeout, - ) diff --git a/examples/storage/fatfs_advanced/sdkconfig.ci.test_read_only_partition_gen b/examples/storage/fatfs_advanced/sdkconfig.ci.test_read_only_partition_gen deleted file mode 100644 index 21a7938068c..00000000000 --- a/examples/storage/fatfs_advanced/sdkconfig.ci.test_read_only_partition_gen +++ /dev/null @@ -1,5 +0,0 @@ -CONFIG_EXAMPLE_FATFS_MODE_READ_ONLY=y -CONFIG_FATFS_LFN_HEAP=y -CONFIG_FATFS_LFN_STACK=n -CONFIG_FATFS_LFN_NONE=n -CONFIG_EXAMPLE_FATFS_WRITE_COUNT=300 diff --git a/examples/storage/fatfs_advanced/sdkconfig.ci.test_read_only_partition_gen_default_dt b/examples/storage/fatfs_advanced/sdkconfig.ci.test_read_only_partition_gen_default_dt deleted file mode 100644 index ed0be2575ba..00000000000 --- a/examples/storage/fatfs_advanced/sdkconfig.ci.test_read_only_partition_gen_default_dt +++ /dev/null @@ -1,6 +0,0 @@ -CONFIG_EXAMPLE_FATFS_MODE_READ_ONLY=y -CONFIG_FATFS_LFN_HEAP=y -CONFIG_FATFS_LFN_STACK=n -CONFIG_FATFS_LFN_NONE=n -CONFIG_EXAMPLE_FATFS_DEFAULT_DATETIME=y -CONFIG_EXAMPLE_FATFS_WRITE_COUNT=300 diff --git a/examples/storage/fatfs_advanced/sdkconfig.ci.test_read_write_partition_gen b/examples/storage/fatfs_advanced/sdkconfig.ci.test_read_write_partition_gen deleted file mode 100644 index 4ffa5532339..00000000000 --- a/examples/storage/fatfs_advanced/sdkconfig.ci.test_read_write_partition_gen +++ /dev/null @@ -1,5 +0,0 @@ -CONFIG_EXAMPLE_FATFS_MODE_READ_ONLY=n -CONFIG_FATFS_LFN_HEAP=y -CONFIG_FATFS_LFN_STACK=n -CONFIG_FATFS_LFN_NONE=n -CONFIG_EXAMPLE_FATFS_WRITE_COUNT=300 diff --git a/examples/storage/fatfs_advanced/sdkconfig.ci.test_read_write_partition_gen_default_dt b/examples/storage/fatfs_advanced/sdkconfig.ci.test_read_write_partition_gen_default_dt deleted file mode 100644 index 6413768f3e5..00000000000 --- a/examples/storage/fatfs_advanced/sdkconfig.ci.test_read_write_partition_gen_default_dt +++ /dev/null @@ -1,6 +0,0 @@ -CONFIG_EXAMPLE_FATFS_MODE_READ_ONLY=n -CONFIG_FATFS_LFN_HEAP=y -CONFIG_FATFS_LFN_STACK=n -CONFIG_FATFS_LFN_NONE=n -CONFIG_EXAMPLE_FATFS_DEFAULT_DATETIME=y -CONFIG_EXAMPLE_FATFS_WRITE_COUNT=300 From 33788de97955d9e57508313661099c9cf39e66fe Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Tom=C3=A1=C5=A1=20Rohl=C3=ADnek?= Date: Mon, 5 Aug 2024 14:16:58 +0200 Subject: [PATCH 100/472] feat(storage/fatfs): restructure ext_flash example --- examples/storage/.build-test-rules.yml | 15 --------------- .../storage/ext_flash_fatfs/main/CMakeLists.txt | 1 - examples/storage/fatfs/.build-test-rules.yml | 15 +++++++++++++++ .../ext_flash}/CMakeLists.txt | 0 .../ext_flash}/README.md | 0 .../storage/fatfs/ext_flash/main/CMakeLists.txt | 1 + .../main/fatfs_ext_flash_example_main.c} | 5 +++++ .../ext_flash/pytest_fatfs_ext_flash.py} | 2 -- tools/ci/check_copyright_ignore.txt | 1 - 9 files changed, 21 insertions(+), 19 deletions(-) delete mode 100644 examples/storage/ext_flash_fatfs/main/CMakeLists.txt rename examples/storage/{ext_flash_fatfs => fatfs/ext_flash}/CMakeLists.txt (100%) rename examples/storage/{ext_flash_fatfs => fatfs/ext_flash}/README.md (100%) create mode 100644 examples/storage/fatfs/ext_flash/main/CMakeLists.txt rename examples/storage/{ext_flash_fatfs/main/ext_flash_fatfs_example_main.c => fatfs/ext_flash/main/fatfs_ext_flash_example_main.c} (98%) rename examples/storage/{ext_flash_fatfs/pytest_ext_flash_fatfs.py => fatfs/ext_flash/pytest_fatfs_ext_flash.py} (99%) diff --git a/examples/storage/.build-test-rules.yml b/examples/storage/.build-test-rules.yml index 341e0f595a8..967d8ed5b8e 100644 --- a/examples/storage/.build-test-rules.yml +++ b/examples/storage/.build-test-rules.yml @@ -19,21 +19,6 @@ examples/storage/emmc: - if: IDF_TARGET == "esp32s3" reason: only support on esp32s3 -examples/storage/ext_flash_fatfs: - depends_components: - - fatfs - - vfs - - spi_flash - - driver - disable: - - if: IDF_TARGET in ["esp32p4", "esp32c5", "esp32c61"] - temporary: true - reason: not supported on p4 and c5 # TODO: [ESP32C5] IDF-8715, [ESP32C61] IDF-9314 - disable_test: - - if: IDF_TARGET not in ["esp32"] - temporary: true - reason: lack of runners - examples/storage/nvs_rw_blob: depends_components: - nvs_flash diff --git a/examples/storage/ext_flash_fatfs/main/CMakeLists.txt b/examples/storage/ext_flash_fatfs/main/CMakeLists.txt deleted file mode 100644 index c8a5c30e46b..00000000000 --- a/examples/storage/ext_flash_fatfs/main/CMakeLists.txt +++ /dev/null @@ -1 +0,0 @@ -idf_component_register(SRCS "ext_flash_fatfs_example_main.c") diff --git a/examples/storage/fatfs/.build-test-rules.yml b/examples/storage/fatfs/.build-test-rules.yml index f652dd52d8e..4f3ae3aa16a 100644 --- a/examples/storage/fatfs/.build-test-rules.yml +++ b/examples/storage/fatfs/.build-test-rules.yml @@ -7,3 +7,18 @@ examples/storage/fatfs: disable_test: - if: IDF_TARGET != "esp32" reason: only one target needed + +examples/storage/fatfs/ext_flash: + depends_components: + - fatfs + - vfs + - spi_flash + - driver + disable: + - if: IDF_TARGET in ["esp32p4", "esp32c5", "esp32c61"] + temporary: true + reason: not supported on p4 and c5 # TODO: [ESP32C5] IDF-8715, [ESP32C61] IDF-9314 + disable_test: + - if: IDF_TARGET not in ["esp32"] + temporary: true + reason: lack of runners diff --git a/examples/storage/ext_flash_fatfs/CMakeLists.txt b/examples/storage/fatfs/ext_flash/CMakeLists.txt similarity index 100% rename from examples/storage/ext_flash_fatfs/CMakeLists.txt rename to examples/storage/fatfs/ext_flash/CMakeLists.txt diff --git a/examples/storage/ext_flash_fatfs/README.md b/examples/storage/fatfs/ext_flash/README.md similarity index 100% rename from examples/storage/ext_flash_fatfs/README.md rename to examples/storage/fatfs/ext_flash/README.md diff --git a/examples/storage/fatfs/ext_flash/main/CMakeLists.txt b/examples/storage/fatfs/ext_flash/main/CMakeLists.txt new file mode 100644 index 00000000000..dea52d1cb4a --- /dev/null +++ b/examples/storage/fatfs/ext_flash/main/CMakeLists.txt @@ -0,0 +1 @@ +idf_component_register(SRCS "fatfs_ext_flash_example_main.c") diff --git a/examples/storage/ext_flash_fatfs/main/ext_flash_fatfs_example_main.c b/examples/storage/fatfs/ext_flash/main/fatfs_ext_flash_example_main.c similarity index 98% rename from examples/storage/ext_flash_fatfs/main/ext_flash_fatfs_example_main.c rename to examples/storage/fatfs/ext_flash/main/fatfs_ext_flash_example_main.c index aa2a2c0990b..4e10057d10f 100644 --- a/examples/storage/ext_flash_fatfs/main/ext_flash_fatfs_example_main.c +++ b/examples/storage/fatfs/ext_flash/main/fatfs_ext_flash_example_main.c @@ -1,3 +1,8 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Unlicense OR CC0-1.0 + */ /* Example of FAT filesystem on external Flash. This example code is in the Public Domain (or CC0 licensed, at your option.) diff --git a/examples/storage/ext_flash_fatfs/pytest_ext_flash_fatfs.py b/examples/storage/fatfs/ext_flash/pytest_fatfs_ext_flash.py similarity index 99% rename from examples/storage/ext_flash_fatfs/pytest_ext_flash_fatfs.py rename to examples/storage/fatfs/ext_flash/pytest_fatfs_ext_flash.py index afe81763a3a..56dd334a49a 100644 --- a/examples/storage/ext_flash_fatfs/pytest_ext_flash_fatfs.py +++ b/examples/storage/fatfs/ext_flash/pytest_fatfs_ext_flash.py @@ -1,7 +1,5 @@ # SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD # SPDX-License-Identifier: Unlicense OR CC0-1.0 - - import pytest from pytest_embedded import Dut diff --git a/tools/ci/check_copyright_ignore.txt b/tools/ci/check_copyright_ignore.txt index f605b7cd054..8ffb0dc2e2a 100644 --- a/tools/ci/check_copyright_ignore.txt +++ b/tools/ci/check_copyright_ignore.txt @@ -1023,7 +1023,6 @@ examples/security/flash_encryption/main/flash_encrypt_main.c examples/storage/custom_flash_driver/components/custom_chip_driver/chip_drivers.c examples/storage/custom_flash_driver/components/custom_chip_driver/spi_flash_chip_eon.c examples/storage/custom_flash_driver/main/main.c -examples/storage/ext_flash_fatfs/main/ext_flash_fatfs_example_main.c examples/storage/nvs_rw_blob/main/nvs_blob_example_main.c examples/storage/nvs_rw_value/main/nvs_value_example_main.c examples/storage/nvs_rw_value_cxx/main/nvs_value_example_main.cpp From d43669b2d7bb9c88a669eab661cff56aef730f0b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Tom=C3=A1=C5=A1=20Rohl=C3=ADnek?= Date: Thu, 8 Aug 2024 10:13:41 +0200 Subject: [PATCH 101/472] feat(storage/fatfs): restructure fatfsgen example --- .../storage/fatfs/fatfsgen/CMakeLists.txt | 6 ++ examples/storage/fatfs/fatfsgen/README.md | 69 ++++++++++++++ .../fatfsgen/fatfs_image/hellolongname.txt | 1 + .../fatfs_image/subdir/testlongfilenames.txt | 1 + .../fatfs/fatfsgen/main/CMakeLists.txt | 18 ++++ .../fatfs/fatfsgen/main/Kconfig.projbuild | 10 ++ .../fatfsgen/main/fatfsgen_example_main.c | 92 +++++++++++++++++++ .../fatfs/fatfsgen/partitions_example.csv | 6 ++ .../fatfsgen/pytest_fatfs_fatfsgen_example.py | 72 +++++++++++++++ ...kconfig.ci.test_read_only_partition_gen_ln | 4 + ...config.ci.test_read_write_partition_gen_ln | 4 + .../storage/fatfs/fatfsgen/sdkconfig.defaults | 4 + 12 files changed, 287 insertions(+) create mode 100644 examples/storage/fatfs/fatfsgen/CMakeLists.txt create mode 100644 examples/storage/fatfs/fatfsgen/README.md create mode 100644 examples/storage/fatfs/fatfsgen/fatfs_image/hellolongname.txt create mode 100644 examples/storage/fatfs/fatfsgen/fatfs_image/subdir/testlongfilenames.txt create mode 100644 examples/storage/fatfs/fatfsgen/main/CMakeLists.txt create mode 100644 examples/storage/fatfs/fatfsgen/main/Kconfig.projbuild create mode 100644 examples/storage/fatfs/fatfsgen/main/fatfsgen_example_main.c create mode 100644 examples/storage/fatfs/fatfsgen/partitions_example.csv create mode 100644 examples/storage/fatfs/fatfsgen/pytest_fatfs_fatfsgen_example.py create mode 100644 examples/storage/fatfs/fatfsgen/sdkconfig.ci.test_read_only_partition_gen_ln create mode 100644 examples/storage/fatfs/fatfsgen/sdkconfig.ci.test_read_write_partition_gen_ln create mode 100644 examples/storage/fatfs/fatfsgen/sdkconfig.defaults diff --git a/examples/storage/fatfs/fatfsgen/CMakeLists.txt b/examples/storage/fatfs/fatfsgen/CMakeLists.txt new file mode 100644 index 00000000000..1c0c2b8a1a2 --- /dev/null +++ b/examples/storage/fatfs/fatfsgen/CMakeLists.txt @@ -0,0 +1,6 @@ +# The following lines of boilerplate have to be in your project's CMakeLists +# in this exact order for cmake to work correctly +cmake_minimum_required(VERSION 3.16) + +include($ENV{IDF_PATH}/tools/cmake/project.cmake) +project(fatfsgen) diff --git a/examples/storage/fatfs/fatfsgen/README.md b/examples/storage/fatfs/fatfsgen/README.md new file mode 100644 index 00000000000..aa203d8356d --- /dev/null +++ b/examples/storage/fatfs/fatfsgen/README.md @@ -0,0 +1,69 @@ +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- | + +# FATFS partition generation example + +(See the README.md file in the upper level 'examples' directory for more information about examples.) + +This example demonstrates how to use the FATFS partition +generation tool [fatfsgen.py](../../../components/fatfs/fatfsgen.py) to automatically create a FATFS +filesystem image from the contents of a host folder during build, with an option of +automatically flashing the created image on invocation of `idf.py -p PORT flash`. +Beware that the minimal required size of the flash is 4 MB. +You can specify using menuconfig weather example will use read-only or read-write mode. The default option is read-write mode. +To change it just use menuconfig: + +```shell +idf.py menuconfig +``` + +Then select `Example Configuration` a chose `Mode for generated FATFS image` either `Read-Write Mode` or `Read-Only Mode`. +`Read-Only` option indicates generating raw fatfs image without wear levelling support. +On the other hand, for `Read-Write` the generated fatfs image will support wear levelling thus can be mounted in read-write mode. + + +The following gives an overview of the example: + +1. There is a directory `fatfs_long_name_image` from which the FATFS filesystem image will be created. + +2. Based on the RO/RW configuration either `fatfs_create_rawflash_image` or `fatfs_create_spiflash_image` respectively, +is used to specify that a FATFS image should be created during build for the `storage` partition. +For CMake, it is called from [the main component's CMakeLists.txt](./main/CMakeLists.txt). +`FLASH_IN_PROJECT` specifies that the created image +should be flashed on invocation of `idf.py -p PORT flash` together with app, bootloader, partition table, etc. +The image is created on the example's build directory with the output filename `storage.bin`. + +3. Upon invocation of `idf.py -p PORT flash monitor`, application loads and +finds there is already a valid FATFS filesystem in the `storage` partition with files same as those in `fatfs_image` directory. The application is then +able to read those files. + +## How to use example + +### Build and flash + +To run the example, type the following command: + +```CMake +# CMake +idf.py -p PORT flash monitor +``` + +(To exit the serial monitor, type ``Ctrl-]``.) + +See the Getting Started Guide for full steps to configure and use ESP-IDF to build projects. + +## Example output + +Here is the example's console output: + +``` +... +I (322) example: Mounting FAT filesystem +I (332) example: Reading file +I (332) example: Read from file: 'this is test' +I (332) example: Unmounting FAT filesystem +I (342) example: Done +``` + +The logic of the example is contained in a [single source file](./main/fatfsgen_example_main.c), +and it should be relatively simple to match points in its execution with the log outputs above. diff --git a/examples/storage/fatfs/fatfsgen/fatfs_image/hellolongname.txt b/examples/storage/fatfs/fatfsgen/fatfs_image/hellolongname.txt new file mode 100644 index 00000000000..45caad27256 --- /dev/null +++ b/examples/storage/fatfs/fatfsgen/fatfs_image/hellolongname.txt @@ -0,0 +1 @@ +This is generated on the host; long name it has diff --git a/examples/storage/fatfs/fatfsgen/fatfs_image/subdir/testlongfilenames.txt b/examples/storage/fatfs/fatfsgen/fatfs_image/subdir/testlongfilenames.txt new file mode 100644 index 00000000000..e8c8c6d51ff --- /dev/null +++ b/examples/storage/fatfs/fatfsgen/fatfs_image/subdir/testlongfilenames.txt @@ -0,0 +1 @@ +this is test; long name it has diff --git a/examples/storage/fatfs/fatfsgen/main/CMakeLists.txt b/examples/storage/fatfs/fatfsgen/main/CMakeLists.txt new file mode 100644 index 00000000000..1b625a37226 --- /dev/null +++ b/examples/storage/fatfs/fatfsgen/main/CMakeLists.txt @@ -0,0 +1,18 @@ +idf_component_register(SRCS "fatfsgen_example_main.c" + INCLUDE_DIRS ".") + +# Create a FATFS image from the contents of the 'fatfs_long_name_image' directory +# that fits the partition named 'storage'. FLASH_IN_PROJECT indicates that +# the generated image should be flashed when the entire project is flashed to +# the target with 'idf.py -p PORT flash'. +# If read-only mode is set (CONFIG_EXAMPLE_FATFS_MODE_READ_ONLY) +# the generated image will be raw without wear levelling support. +# Otherwise it will support wear levelling and thus enable read-write mounting of the image in the device. + +set(image ../fatfs_image) + +if(CONFIG_EXAMPLE_FATFS_MODE_READ_ONLY) + fatfs_create_rawflash_image(storage ${image} FLASH_IN_PROJECT PRESERVE_TIME) +else() + fatfs_create_spiflash_image(storage ${image} FLASH_IN_PROJECT PRESERVE_TIME) +endif() diff --git a/examples/storage/fatfs/fatfsgen/main/Kconfig.projbuild b/examples/storage/fatfs/fatfsgen/main/Kconfig.projbuild new file mode 100644 index 00000000000..ef79d394562 --- /dev/null +++ b/examples/storage/fatfs/fatfsgen/main/Kconfig.projbuild @@ -0,0 +1,10 @@ +menu "Example Configuration" + + config EXAMPLE_FATFS_MODE_READ_ONLY + bool "Read only mode for generated FATFS image" + default y + help + If read-only mode is set, the generated fatfs image will be raw (without wear levelling support). + Otherwise it will support wear levelling that enables read-write mounting. + +endmenu diff --git a/examples/storage/fatfs/fatfsgen/main/fatfsgen_example_main.c b/examples/storage/fatfs/fatfsgen/main/fatfsgen_example_main.c new file mode 100644 index 00000000000..abc01a900a8 --- /dev/null +++ b/examples/storage/fatfs/fatfsgen/main/fatfsgen_example_main.c @@ -0,0 +1,92 @@ +/* + * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Unlicense OR CC0-1.0 + */ + +#include +#include +#include +#include "esp_vfs.h" +#include "esp_vfs_fat.h" +#include "esp_err.h" +#include "sdkconfig.h" + +static const char *TAG = "example"; + +// Mount path for the partition +const char *base_path = "/spiflash"; + + +void app_main(void) +{ + // To mount device we need name of device partition, define base_path + // and allow format partition in case if it is new one and was not formatted before + const esp_vfs_fat_mount_config_t mount_config = { + .max_files = 4, + .format_if_mount_failed = false, + .allocation_unit_size = CONFIG_WL_SECTOR_SIZE, + .use_one_fat = false, + }; + +#if CONFIG_EXAMPLE_FATFS_MODE_READ_ONLY + ESP_LOGI(TAG, "Mounting FAT filesystem in read-only mode"); + esp_err_t err = esp_vfs_fat_spiflash_mount_ro(base_path, "storage", &mount_config); +#else + ESP_LOGI(TAG, "Mounting FAT filesystem in read/write mode"); + static wl_handle_t wl_handle = WL_INVALID_HANDLE; + esp_err_t err = esp_vfs_fat_spiflash_mount_rw_wl(base_path, "storage", &mount_config, &wl_handle); +#endif + + if (err != ESP_OK) { + ESP_LOGE(TAG, "Failed to mount FATFS (%s)", esp_err_to_name(err)); + return; + } + + char line[128]; + + FILE *f; + char *pos; + ESP_LOGI(TAG, "Reading file"); + + const char *host_filename1 = "/spiflash/subdir/testlongfilenames.txt"; + + struct stat info; + struct tm timeinfo; + char buffer[32]; + + if(stat(host_filename1, &info) < 0){ + ESP_LOGE(TAG, "Failed to read file stats"); + return; + } + localtime_r(&info.st_mtime, &timeinfo); + strftime(buffer, sizeof(buffer), "%Y-%m-%d", &timeinfo); + + ESP_LOGI(TAG, "The file '%s' was modified at date: %s", host_filename1, buffer); + + + f = fopen(host_filename1, "rb"); + if (f == NULL) { + ESP_LOGE(TAG, "Failed to open file for reading"); + return; + } + fgets(line, sizeof(line), f); + fclose(f); + // strip newline + pos = strchr(line, '\n'); + if (pos) { + *pos = '\0'; + } + ESP_LOGI(TAG, "Read from file: '%s'", line); + + // Unmount FATFS + ESP_LOGI(TAG, "Unmounting FAT filesystem"); + +#if CONFIG_EXAMPLE_FATFS_MODE_READ_ONLY + ESP_ERROR_CHECK(esp_vfs_fat_spiflash_unmount_ro(base_path, "storage")); +#else + ESP_ERROR_CHECK(esp_vfs_fat_spiflash_unmount_rw_wl(base_path, wl_handle)); +#endif + + ESP_LOGI(TAG, "Done"); +} diff --git a/examples/storage/fatfs/fatfsgen/partitions_example.csv b/examples/storage/fatfs/fatfsgen/partitions_example.csv new file mode 100644 index 00000000000..a3fee302e29 --- /dev/null +++ b/examples/storage/fatfs/fatfsgen/partitions_example.csv @@ -0,0 +1,6 @@ +# Name, Type, SubType, Offset, Size, Flags +# Note: if you have increased the bootloader size, make sure to update the offsets to avoid overlap +nvs, data, nvs, 0x9000, 0x6000, +phy_init, data, phy, 0xf000, 0x1000, +factory, app, factory, 0x10000, 1M, +storage, data, fat, , 1M, diff --git a/examples/storage/fatfs/fatfsgen/pytest_fatfs_fatfsgen_example.py b/examples/storage/fatfs/fatfsgen/pytest_fatfs_fatfsgen_example.py new file mode 100644 index 00000000000..e0966604ebe --- /dev/null +++ b/examples/storage/fatfs/fatfsgen/pytest_fatfs_fatfsgen_example.py @@ -0,0 +1,72 @@ +# SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD +# SPDX-License-Identifier: Unlicense OR CC0-1.0 +import os +import re +from datetime import datetime +from typing import List + +import pytest +from pytest_embedded import Dut + +idf_path = os.environ['IDF_PATH'] # get value of IDF_PATH from environment +parttool_dir = os.path.join(idf_path, 'components', 'partition_table') + + +@pytest.mark.esp32 +@pytest.mark.generic +@pytest.mark.parametrize('config', ['test_read_only_partition_gen_ln', + 'test_read_write_partition_gen_ln', + ], indirect=True) +def test_examples_fatfs_fatfsgen(config: str, dut: Dut) -> None: + # Expects list of strings sequentially + def expect_all(msg_list: List[str], to: int) -> None: + for msg in msg_list: + dut.expect(msg, timeout=to) + + # Expects prefix string followed by date in the format 'yyyy-mm-dd' + def expect_date(prefix: str, to: int) -> datetime: + expect_str = prefix + '(\\d+)-(\\d+)-(\\d+)' + match_ = dut.expect(re.compile(str.encode(expect_str)), timeout=to) + year_ = int(match_[1].decode()) + month_ = int(match_[2].decode()) + day_ = int(match_[3].decode()) + return datetime(year_, month_, day_) + + # Calculates absolute difference in days between date_reference and date_actual. + # Raises exception if difference exceeds tolerance + def evaluate_dates(date_reference: datetime, date_actual: datetime, days_tolerance: int) -> None: + td = date_actual - date_reference + if abs(td.days) > days_tolerance: + raise Exception(f'Too big date difference. Actual: {date_actual}, reference: {date_reference}, tolerance: {days_tolerance} day(s)') + + # Expect timeout + timeout = 20 + + # We tolerate 30 days difference between actual file creation and date when test was executed. + tolerance = 30 + filename = 'sublongnames/testlongfilenames.txt' + date_ref = datetime.today() + + if config in ['test_read_write_partition_gen']: + filename_expected = f'/spiflash/{filename}' + expect_all(['example: Mounting FAT filesystem', + 'example: Opening file', + 'example: File written', + 'example: Reading file', + 'example: Read from file: \'This is written by the device\'', + 'example: Reading file'], timeout) + date_act = expect_date(f'The file \'{filename_expected}\' was modified at date: ', timeout) + evaluate_dates(date_ref, date_act, tolerance) + expect_all(['example: Read from file: \'This is generated on the host\'', + 'example: Unmounting FAT filesystem', + 'example: Done'], timeout) + + elif config in ['test_read_only_partition_gen']: + filename_expected = f'/spiflash/{filename}' + expect_all(['example: Mounting FAT filesystem', + 'example: Reading file'], timeout) + date_act = expect_date(f'The file \'{filename_expected}\' was modified at date: ', timeout) + evaluate_dates(date_ref, date_act, tolerance) + expect_all(['example: Read from file: \'this is test\'', + 'example: Unmounting FAT filesystem', + 'example: Done'], timeout) diff --git a/examples/storage/fatfs/fatfsgen/sdkconfig.ci.test_read_only_partition_gen_ln b/examples/storage/fatfs/fatfsgen/sdkconfig.ci.test_read_only_partition_gen_ln new file mode 100644 index 00000000000..5122126dcbc --- /dev/null +++ b/examples/storage/fatfs/fatfsgen/sdkconfig.ci.test_read_only_partition_gen_ln @@ -0,0 +1,4 @@ +CONFIG_EXAMPLE_FATFS_MODE_READ_ONLY=y +CONFIG_FATFS_LFN_HEAP=y +CONFIG_FATFS_LFN_NONE=n +CONFIG_FATFS_LFN_STACK=n diff --git a/examples/storage/fatfs/fatfsgen/sdkconfig.ci.test_read_write_partition_gen_ln b/examples/storage/fatfs/fatfsgen/sdkconfig.ci.test_read_write_partition_gen_ln new file mode 100644 index 00000000000..33a0ccfad3d --- /dev/null +++ b/examples/storage/fatfs/fatfsgen/sdkconfig.ci.test_read_write_partition_gen_ln @@ -0,0 +1,4 @@ +CONFIG_EXAMPLE_FATFS_MODE_READ_ONLY=n +CONFIG_FATFS_LFN_HEAP=y +CONFIG_FATFS_LFN_NONE=n +CONFIG_FATFS_LFN_STACK=n diff --git a/examples/storage/fatfs/fatfsgen/sdkconfig.defaults b/examples/storage/fatfs/fatfsgen/sdkconfig.defaults new file mode 100644 index 00000000000..7dd3c63608f --- /dev/null +++ b/examples/storage/fatfs/fatfsgen/sdkconfig.defaults @@ -0,0 +1,4 @@ +CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y +CONFIG_PARTITION_TABLE_CUSTOM=y +CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="partitions_example.csv" +CONFIG_FATFS_LFN_HEAP=y From 46982e69da245da50119c3ee6446abc23f922a56 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Tom=C3=A1=C5=A1=20Rohl=C3=ADnek?= Date: Tue, 3 Sep 2024 13:30:45 +0200 Subject: [PATCH 102/472] feat(storage/vfs): update example references in documentation --- docs/en/api-reference/storage/fatfs.rst | 4 +- docs/en/api-reference/storage/index.rst | 64 ++++++++++++++++++------- 2 files changed, 49 insertions(+), 19 deletions(-) diff --git a/docs/en/api-reference/storage/fatfs.rst b/docs/en/api-reference/storage/fatfs.rst index f45007607ce..20bdbac6a32 100644 --- a/docs/en/api-reference/storage/fatfs.rst +++ b/docs/en/api-reference/storage/fatfs.rst @@ -123,7 +123,7 @@ If you decide for any reason to use ``fatfs_create_rawflash_image`` (without wea The arguments of the function are as follows: -#. partition - the name of the partition as defined in the partition table (e.g., :example_file:`storage/fatfsgen/partitions_example.csv`). +#. partition - the name of the partition as defined in the partition table (e.g., :example_file:`storage/fatfs/fatfsgen/partitions_example.csv`). #. base_dir - the directory that will be encoded to FatFs partition and optionally flashed into the device. Beware that you have to specify the suitable size of the partition in the partition table. @@ -139,7 +139,7 @@ For example:: If FLASH_IN_PROJECT is not specified, the image will still be generated, but you will have to flash it manually using ``esptool.py`` or a custom build system target. -For an example, see :example:`storage/fatfsgen`. +For an example, see :example:`storage/fatfs/fatfsgen`. .. _fatfs-partition-analyzer: diff --git a/docs/en/api-reference/storage/index.rst b/docs/en/api-reference/storage/index.rst index 19bf5b6b929..22d5197fcb3 100644 --- a/docs/en/api-reference/storage/index.rst +++ b/docs/en/api-reference/storage/index.rst @@ -37,22 +37,15 @@ For information about storage security, please refer to :doc:`Storage Security < wear-levelling storage-security.rst -.. list-table:: Code Examples for Storage API +Examples +-------- + +.. list-table:: NVS API examples :widths: 25 75 :header-rows: 0 * - **Code Example** - **Description** - * - :doc:`fatfs` - - - * - :example:`wear_leveling ` - - Demonstrates using FATFS over wear leveling on internal flash. - * - :example:`ext_flash_fatfs ` - - Demonstrates using FATFS over wear leveling on external flash. - * - :example:`fatfsgen ` - - Demonstrates the capabilities of Python-based tooling for FATFS images available on host computers. - * - :doc:`nvs_flash` - - * - :example:`nvs_rw_blob ` - Shows the use of the C-style API to read and write blob data types in NVS flash. * - :example:`nvs_rw_value ` @@ -61,20 +54,57 @@ For information about storage security, please refer to :doc:`Storage Security < - Shows the use of the C++-style API to read and write integer data types in NVS flash. * - :example:`nvsgen ` - Demonstrates how to use the Python-based NVS image generation tool to create an NVS partition image from the contents of a CSV file. - * - :doc:`spiffs` - - + +.. list-table:: Common Filesystem API + :widths: 25 75 + :header-rows: 0 + + * - **Code Example** + - **Description** + * - :example:`fatfs/getting_started ` + - Demonstrates basic common file API(stdio.h) usage over internal flash using FATFS. + * - :example:`fatfs/fs_operations ` + - Demonstrates POSIX API for filesystem manipulation, such as moving, removing and renaming files. + +.. list-table:: FATFS API examples + :widths: 25 75 + :header-rows: 0 + + * - :example:`fatfsgen ` + - Demonstrates the capabilities of Python-based tooling for FATFS images available on host computers. + * - :example:`ext_flash_fatfs ` + - Demonstrates using FATFS over wear leveling on external flash. + * - :example:`wear_leveling ` + - Demonstrates using FATFS over wear leveling on internal flash. + +.. list-table:: SPIFFS API examples + :widths: 25 75 + :header-rows: 0 + + * - **Code Example** + - **Description** * - :example:`spiffs ` - Shows the use of the SPIFFS API to initialize the filesystem and work with files using POSIX functions. * - :example:`spiffsgen ` - Demonstrates the capabilities of Python-based tooling for SPIFFS images available on host computers. - * - :doc:`partition` - - + +.. list-table:: Partition API examples + :widths: 25 75 + :header-rows: 0 + + * - **Code Example** + - **Description** * - :example:`partition_api ` - Provides an overview of API functions to look up particular partitions, perform basic I/O operations, and use partitions via CPU memory mapping. * - :example:`parttool ` - Demonstrates the capabilities of Python-based tooling for partition images available on host computers. - * - :doc:`vfs` - - + +.. list-table:: VFS related examples + :widths: 25 75 + :header-rows: 0 + + * - **Code Example** + - **Description** * - :example:`littlefs ` - Shows the use of the LittleFS component to initialize the filesystem and work with a file using POSIX functions. * - :example:`semihost_vfs ` From ebe5ac900bc17be361f0d2f78754b60116f475bf Mon Sep 17 00:00:00 2001 From: renpeiying Date: Wed, 18 Sep 2024 14:39:24 +0800 Subject: [PATCH 103/472] docs: Update CN translation for api-reference/storage/index.rst --- docs/en/api-reference/storage/index.rst | 4 +- docs/zh_CN/api-reference/storage/index.rst | 66 ++++++++++++++++------ 2 files changed, 52 insertions(+), 18 deletions(-) diff --git a/docs/en/api-reference/storage/index.rst b/docs/en/api-reference/storage/index.rst index 22d5197fcb3..f3f184270f2 100644 --- a/docs/en/api-reference/storage/index.rst +++ b/docs/en/api-reference/storage/index.rst @@ -62,7 +62,7 @@ Examples * - **Code Example** - **Description** * - :example:`fatfs/getting_started ` - - Demonstrates basic common file API(stdio.h) usage over internal flash using FATFS. + - Demonstrates basic common file API (stdio.h) usage over internal flash using FATFS. * - :example:`fatfs/fs_operations ` - Demonstrates POSIX API for filesystem manipulation, such as moving, removing and renaming files. @@ -70,6 +70,8 @@ Examples :widths: 25 75 :header-rows: 0 + * - **Code Example** + - **Description** * - :example:`fatfsgen ` - Demonstrates the capabilities of Python-based tooling for FATFS images available on host computers. * - :example:`ext_flash_fatfs ` diff --git a/docs/zh_CN/api-reference/storage/index.rst b/docs/zh_CN/api-reference/storage/index.rst index 0687d98c054..820987a555f 100644 --- a/docs/zh_CN/api-reference/storage/index.rst +++ b/docs/zh_CN/api-reference/storage/index.rst @@ -37,44 +37,76 @@ wear-levelling storage-security.rst +示例 +---- + .. list-table:: 存储 API 相关例程 :widths: 25 75 :header-rows: 0 * - **例程** - **描述** - * - :doc:`fatfs` - - - * - :example:`wear_leveling ` - - 演示了如何在内部 flash 上使用 FATFS 磨损均衡。 - * - :example:`ext_flash_fatfs ` - - 演示了如何在外部 flash 上使用 FATFS 磨损均衡。 - * - :example:`fatfsgen ` - - 演示了在主机计算机上使用 Python 工具生成 FATFS 镜像的功能。 - * - :doc:`nvs_flash` - - * - :example:`nvs_rw_blob ` - 演示了如何在 NVS flash 中使用 C 语言 API 读写 blob 数据类型。 * - :example:`nvs_rw_value ` - 演示了如何在 NVS flash 中使用 C 语言 API 读写整数数据类型。 - * - :example:`nvs_rw_value_cxx ` + * - :example:`nvs_rw_value ` - 演示了如何在 NVS flash 中使用 C++ 语言 API 读写整数数据类型。 * - :example:`nvsgen ` - 演示了如何使用基于 Python 的 NVS 镜像生成工具，根据 CSV 文件内容创建 NVS 分区镜像。 - * - :doc:`spiffs` - - + +.. list-table:: 常用文件系统 API + :widths: 25 75 + :header-rows: 0 + + * - **代码示例** + - **描述** + * - :example:`fatfs/getting_started ` + - 演示了使用 FATFS 库在内部 flash 上应用标准文件 API (stdio.h)。 + * - :example:`fatfs/fs_operations ` + - 演示了使用 POSIX API 进行文件系统操作，如移动、删除和重命名文件等。 + +.. list-table:: FATFS API 示例 + :widths: 25 75 + :header-rows: 0 + + * - **代码示例** + - **描述** + * - :example:`fatfsgen ` + - 演示了在主机上使用 Python 工具生成 FATFS 镜像的相关功能。 + * - :example:`ext_flash_fatfs ` + - 演示了在外部 flash 上使用带有损耗均衡功能的 FATFS。 + * - :example:`wear_leveling ` + - 演示了在内部 flash 上使用带有损耗均衡功能的 FATFS。 + +.. list-table:: SPIFFS API 示例 + :widths: 25 75 + :header-rows： 0 + + * - **代码示例** + - **描述** * - :example:`spiffs ` - 演示了如何使用 SPIFFS API 初始化文件系统，并使用 POSIX 函数处理文件。 * - :example:`spiffsgen ` - 演示了在主机计算机上使用 Python 工具生成 SPIFFS 镜像的功能。 - * - :doc:`partition` - - + +.. list-table:: 分区 API 示例 + :widths: 25 75 + :header-rows: 0 + + * - **代码示例** + - **描述** * - :example:`partition_api ` - 介绍了用于查找特定分区、执行基本 I/O 操作以及通过 CPU 内存映射使用分区的 API 函数。 * - :example:`parttool ` - 演示了在主机计算机上使用 Python 工具生成分区镜像的功能。 - * - :doc:`vfs` - - + +.. list-table:: VFS 相关示例 + :widths: 25 75 + :header-rows: 0 + + * - **代码示例** + - **描述** * - :example:`littlefs ` - 演示了如何使用 LittleFS 组件初始化文件系统，并使用 POSIX 函数处理文件。 * - :example:`semihost_vfs ` From 908c4c7ce632d107c942cd99d6a0a1dbf8691429 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Tom=C3=A1=C5=A1=20Rohl=C3=ADnek?= Date: Wed, 18 Sep 2024 10:13:01 +0200 Subject: [PATCH 104/472] docs(storage/fatfs): fix fatfs example links in docs --- docs/en/api-guides/file-system-considerations.rst | 2 +- docs/en/api-guides/performance/speed.rst | 4 ++-- docs/zh_CN/api-guides/performance/speed.rst | 4 ++-- docs/zh_CN/api-reference/storage/fatfs.rst | 4 ++-- docs/zh_CN/api-reference/storage/index.rst | 2 +- 5 files changed, 8 insertions(+), 8 deletions(-) diff --git a/docs/en/api-guides/file-system-considerations.rst b/docs/en/api-guides/file-system-considerations.rst index a57ab01c878..2cf5c176614 100644 --- a/docs/en/api-guides/file-system-considerations.rst +++ b/docs/en/api-guides/file-system-considerations.rst @@ -105,7 +105,7 @@ The most supported file system, recommended for common applications - file/direc **Examples:** * :example:`storage/sd_card`: access the SD card which uses the FAT file system -* :example:`storage/ext_flash_fatfs`: access the external flash chip which uses the FAT file system +* :example:`storage/fatfs/ext_flash`: access the external flash chip which uses the FAT file system .. _spiffs-fs-section: diff --git a/docs/en/api-guides/performance/speed.rst b/docs/en/api-guides/performance/speed.rst index 0cce05a5717..c374a327462 100644 --- a/docs/en/api-guides/performance/speed.rst +++ b/docs/en/api-guides/performance/speed.rst @@ -301,9 +301,9 @@ Improving I/O Performance Using standard C library functions like ``fread`` and ``fwrite`` instead of platform-specific unbuffered syscalls such as ``read`` and ``write``, may result in slower performance. -The ``fread`` and ``fwrite`` functions are designed for portability rather than speed, introducing some overhead due to their buffered nature. Check the example :example:`storage/fatfsgen` to see how to use these two functions. +The ``fread`` and ``fwrite`` functions are designed for portability rather than speed, introducing some overhead due to their buffered nature. Check the example :example:`storage/fatfs/getting_started` to see how to use these two functions. -In contrast, the ``read`` and ``write`` functions are standard POSIX APIs that can be used directly when working with FatFs through VFS, with ESP-IDF handling the underlying implementation. Check the example :example:`storage/perf_benchmark` to see how to use the two functions. +In contrast, the ``read`` and ``write`` functions are standard POSIX APIs that can be used directly when working with FatFs through VFS, with ESP-IDF handling the underlying implementation. Check the example :example:`storage/fatfs/fs_operations` to see how to use the two functions. Additional tips are provided below, and further details can be found in :doc:`/api-reference/storage/fatfs`. diff --git a/docs/zh_CN/api-guides/performance/speed.rst b/docs/zh_CN/api-guides/performance/speed.rst index 25601b4dadf..55f0a2da747 100644 --- a/docs/zh_CN/api-guides/performance/speed.rst +++ b/docs/zh_CN/api-guides/performance/speed.rst @@ -301,9 +301,9 @@ ESP-IDF 支持动态 :doc:`/api-reference/system/intr_alloc` 和中断抢占。 使用标准 C 库函数，如 ``fread`` 和 ``fwrite``，相较于使用平台特定的不带缓冲系统调用，如 ``read`` 和 ``write``，可能会导致 I/O 性能下降。 -``fread`` 与 ``fwrite`` 函数是为可移植性而设计的，而非速度，其缓冲性质会引入一些额外的开销。关于如何使用这两个函数，请参考示例 :example:`storage/fatfsgen`。 +``fread`` 与 ``fwrite`` 函数是为可移植性而设计的，而非速度，其缓冲性质会引入一些额外的开销。关于如何使用这两个函数，请参考示例 :example:`storage/fatfs/getting_started`。 -与之相比，``read`` 与 ``write`` 函数是标准的 POSIX API，可直接通过 VFS 处理 FatFs，由 ESP-IDF 负责底层实现。关于如何使用这两个函数，请参考示例 :example:`storage/perf_benchmark`。 +与之相比，``read`` 与 ``write`` 函数是标准的 POSIX API，可直接通过 VFS 处理 FatFs，由 ESP-IDF 负责底层实现。关于如何使用这两个函数，请参考示例 :example:`storage/fatfs/fs_operations`。 下面提供了一些提示，更多信息请见 :doc:`/api-reference/storage/fatfs`。 diff --git a/docs/zh_CN/api-reference/storage/fatfs.rst b/docs/zh_CN/api-reference/storage/fatfs.rst index 65f281bd790..bc3671659f8 100644 --- a/docs/zh_CN/api-reference/storage/fatfs.rst +++ b/docs/zh_CN/api-reference/storage/fatfs.rst @@ -123,7 +123,7 @@ FatFs 分区生成器 该函数的参数如下： -#. partition - 分区的名称，需要在分区表中定义（如 :example_file:`storage/fatfsgen/partitions_example.csv`）。 +#. partition - 分区的名称，需要在分区表中定义（如 :example_file:`storage/fatfs/fatfsgen/partitions_example.csv`）。 #. base_dir - 目录名称，该目录会被编码为 FatFs 分区，也可以选择将其被烧录进设备。但注意必须在分区表中指定合适的分区大小。 @@ -139,7 +139,7 @@ FatFs 分区生成器 没有指定 FLASH_IN_PROJECT 时也可以生成分区镜像，但是用户需要使用 ``esptool.py`` 或自定义的构建系统目标对其手动烧录。 -相关示例请查看 :example:`storage/fatfsgen`。 +相关示例请查看 :example:`storage/fatfs/fatfsgen`。 .. _fatfs-partition-analyzer: diff --git a/docs/zh_CN/api-reference/storage/index.rst b/docs/zh_CN/api-reference/storage/index.rst index 820987a555f..b643c2b7de8 100644 --- a/docs/zh_CN/api-reference/storage/index.rst +++ b/docs/zh_CN/api-reference/storage/index.rst @@ -74,7 +74,7 @@ - **描述** * - :example:`fatfsgen ` - 演示了在主机上使用 Python 工具生成 FATFS 镜像的相关功能。 - * - :example:`ext_flash_fatfs ` + * - :example:`ext_flash_fatfs ` - 演示了在外部 flash 上使用带有损耗均衡功能的 FATFS。 * - :example:`wear_leveling ` - 演示了在内部 flash 上使用带有损耗均衡功能的 FATFS。 From bcc060b98e81b1ddfa39a00f45f40636c3cb6d78 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Tom=C3=A1=C5=A1=20Rohl=C3=ADnek?= Date: Fri, 20 Sep 2024 09:42:27 +0200 Subject: [PATCH 105/472] docs(storage/fatfs): fix relative links in fatfs examples --- examples/storage/fatfs/ext_flash/README.md | 2 +- examples/storage/fatfs/fatfsgen/README.md | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/examples/storage/fatfs/ext_flash/README.md b/examples/storage/fatfs/ext_flash/README.md index 0014bd8d314..349fd1ba3ee 100644 --- a/examples/storage/fatfs/ext_flash/README.md +++ b/examples/storage/fatfs/ext_flash/README.md @@ -5,7 +5,7 @@ (See the README.md file in the upper level 'examples' directory for more information about examples.) -This example is similar to the [wear levelling](../wear_levelling/README.md) example, except that it uses an external SPI Flash chip. This can be useful if you need to add more storage to a module with only 4 MB flash size. +This example is similar to the [wear levelling](../../wear_levelling/README.md) example, except that it uses an external SPI Flash chip. This can be useful if you need to add more storage to a module with only 4 MB flash size. The flow of the example is as follows: diff --git a/examples/storage/fatfs/fatfsgen/README.md b/examples/storage/fatfs/fatfsgen/README.md index aa203d8356d..772cf9cd8e8 100644 --- a/examples/storage/fatfs/fatfsgen/README.md +++ b/examples/storage/fatfs/fatfsgen/README.md @@ -6,7 +6,7 @@ (See the README.md file in the upper level 'examples' directory for more information about examples.) This example demonstrates how to use the FATFS partition -generation tool [fatfsgen.py](../../../components/fatfs/fatfsgen.py) to automatically create a FATFS +generation tool [fatfsgen.py](../../../../components/fatfs/fatfsgen.py) to automatically create a FATFS filesystem image from the contents of a host folder during build, with an option of automatically flashing the created image on invocation of `idf.py -p PORT flash`. Beware that the minimal required size of the flash is 4 MB. From 5ccc9d19787057679f28850ce57a1b88b6f0d278 Mon Sep 17 00:00:00 2001 From: Euripedes Rocha Date: Thu, 10 Oct 2024 10:49:36 +0200 Subject: [PATCH 106/472] ci(mqtt): Set partition to large for c6 on custom outbox example Example failed to build on CI for c6 target due to partition size. --- examples/protocols/mqtt/custom_outbox/sdkconfig.ci.esp32c6 | 1 + 1 file changed, 1 insertion(+) create mode 100644 examples/protocols/mqtt/custom_outbox/sdkconfig.ci.esp32c6 diff --git a/examples/protocols/mqtt/custom_outbox/sdkconfig.ci.esp32c6 b/examples/protocols/mqtt/custom_outbox/sdkconfig.ci.esp32c6 new file mode 100644 index 00000000000..1686559de40 --- /dev/null +++ b/examples/protocols/mqtt/custom_outbox/sdkconfig.ci.esp32c6 @@ -0,0 +1 @@ +CONFIG_PARTITION_TABLE_SINGLE_APP_LARGE=y From 66ebdd0b32b191783e1ce8d3155b06b488d6afea Mon Sep 17 00:00:00 2001 From: "hrushikesh.bhosale" Date: Thu, 10 Oct 2024 11:43:21 +0530 Subject: [PATCH 107/472] feat(ota): Added support of otatool for esp32c61 Enabled the test for esp32c61 for otatool --- examples/system/.build-test-rules.yml | 10 ++-------- examples/system/ota/otatool/README.md | 4 ++-- examples/system/ota/otatool/pytest_otatool.py | 9 +-------- 3 files changed, 5 insertions(+), 18 deletions(-) diff --git a/examples/system/.build-test-rules.yml b/examples/system/.build-test-rules.yml index 3152b243fde..ec614792289 100644 --- a/examples/system/.build-test-rules.yml +++ b/examples/system/.build-test-rules.yml @@ -173,14 +173,8 @@ examples/system/ota/native_ota_example: - protocol_examples_common examples/system/ota/otatool: - disable: - - if: IDF_TARGET in ["esp32h2"] - temporary: true - reason: target esp32h2 is not supported yet - disable_test: - - if: IDF_TARGET in ["esp32c61"] - reason: target esp32c61 is not supported yet - + enable: + - if: INCLUDE_DEFAULT == 1 or IDF_TARGET in ["esp32c5", "esp32c61"] examples/system/ota/pre_encrypted_ota: disable: diff --git a/examples/system/ota/otatool/README.md b/examples/system/ota/otatool/README.md index 255b2232003..859fb55977c 100644 --- a/examples/system/ota/otatool/README.md +++ b/examples/system/ota/otatool/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-P4 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- | # OTA Tool Example diff --git a/examples/system/ota/otatool/pytest_otatool.py b/examples/system/ota/otatool/pytest_otatool.py index 8a9d0b21af7..c0770347369 100644 --- a/examples/system/ota/otatool/pytest_otatool.py +++ b/examples/system/ota/otatool/pytest_otatool.py @@ -26,14 +26,7 @@ def _real_test_func(dut: Dut) -> None: subprocess.check_call([sys.executable, script_path, '--binary', binary_path]) -@pytest.mark.esp32 -@pytest.mark.esp32s2 -@pytest.mark.esp32c3 -@pytest.mark.esp32s3 -@pytest.mark.esp32c5 -# @pytest.mark.esp32c61 #IDF-11309 -@pytest.mark.esp32c6 -@pytest.mark.esp32p4 +@pytest.mark.supported_targets @pytest.mark.generic def test_otatool_example(dut: Dut) -> None: _real_test_func(dut) From b12ea21f49ca2d4b48f1f37c7f5e37f65a5fc31a Mon Sep 17 00:00:00 2001 From: Rahul Tank Date: Tue, 8 Oct 2024 13:57:23 +0530 Subject: [PATCH 108/472] fix(nimble): Update sbom file to correct nimble version --- components/bt/host/nimble/nimble | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/components/bt/host/nimble/nimble b/components/bt/host/nimble/nimble index 87dd8bdc037..24ff17de7c0 160000 --- a/components/bt/host/nimble/nimble +++ b/components/bt/host/nimble/nimble @@ -1 +1 @@ -Subproject commit 87dd8bdc0374572bfde0067b068fafb7bf2374e1 +Subproject commit 24ff17de7c07d53f2db2940052c52bfc48f8414c From fef1d6278eee34e2ca2a3c3232cfb02a620c83e0 Mon Sep 17 00:00:00 2001 From: renpeiying Date: Mon, 23 Sep 2024 14:53:27 +0800 Subject: [PATCH 109/472] docs: update CN trans according to review --- docs/zh_CN/api-reference/storage/index.rst | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/docs/zh_CN/api-reference/storage/index.rst b/docs/zh_CN/api-reference/storage/index.rst index b643c2b7de8..3b71db1be00 100644 --- a/docs/zh_CN/api-reference/storage/index.rst +++ b/docs/zh_CN/api-reference/storage/index.rst @@ -62,9 +62,9 @@ * - **代码示例** - **描述** * - :example:`fatfs/getting_started ` - - 演示了使用 FATFS 库在内部 flash 上应用标准文件 API (stdio.h)。 + - 演示了如何使用 FATFS 库在内部 flash 上应用标准文件 API (stdio.h)。 * - :example:`fatfs/fs_operations ` - - 演示了使用 POSIX API 进行文件系统操作，如移动、删除和重命名文件等。 + - 演示了如何使用 POSIX API 进行文件系统操作，如移动、删除和重命名文件等。 .. list-table:: FATFS API 示例 :widths: 25 75 @@ -75,13 +75,13 @@ * - :example:`fatfsgen ` - 演示了在主机上使用 Python 工具生成 FATFS 镜像的相关功能。 * - :example:`ext_flash_fatfs ` - - 演示了在外部 flash 上使用带有损耗均衡功能的 FATFS。 + - 演示了在外部 flash 上使用带有磨损均衡功能的 FATFS。 * - :example:`wear_leveling ` - - 演示了在内部 flash 上使用带有损耗均衡功能的 FATFS。 + - 演示了在内部 flash 上使用带有磨损均衡功能的 FATFS。 .. list-table:: SPIFFS API 示例 :widths: 25 75 - :header-rows： 0 + :header-rows: 0 * - **代码示例** - **描述** From ff4620fd70a20e43cbb12e446c9baeb4d3fd407a Mon Sep 17 00:00:00 2001 From: Sajia Date: Sun, 29 Sep 2024 18:30:30 +0530 Subject: [PATCH 110/472] fix(wifi): Add a check on hostapd instance while handling an Auth frame --- components/wpa_supplicant/esp_supplicant/src/esp_wpa3.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/components/wpa_supplicant/esp_supplicant/src/esp_wpa3.c b/components/wpa_supplicant/esp_supplicant/src/esp_wpa3.c index 76fa0f5f32e..e66b2a745d8 100644 --- a/components/wpa_supplicant/esp_supplicant/src/esp_wpa3.c +++ b/components/wpa_supplicant/esp_supplicant/src/esp_wpa3.c @@ -647,6 +647,9 @@ bool wpa3_hostap_auth_deinit(void) static int wpa3_hostap_handle_auth(u8 *buf, size_t len, u32 auth_transaction, u16 status, u8 *bssid) { struct hostapd_data *hapd = (struct hostapd_data *)esp_wifi_get_hostap_private_internal(); + if (!hapd) { + return ESP_FAIL; + } struct sta_info *sta = ap_get_sta(hapd, bssid); if (auth_transaction == SAE_MSG_COMMIT) { if (sta && sta->sae_commit_processing) { From 13e52cfa213c1caadf021b2f99e7305db2982dd2 Mon Sep 17 00:00:00 2001 From: laokaiyao Date: Fri, 11 Oct 2024 11:19:45 +0800 Subject: [PATCH 111/472] fix(touch): fixed the deep sleep wakeup issue on P4 --- .../hw_ver3/touch_version_specific.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/components/esp_driver_touch_sens/hw_ver3/touch_version_specific.c b/components/esp_driver_touch_sens/hw_ver3/touch_version_specific.c index ebf9acecdd6..e9335d39652 100644 --- a/components/esp_driver_touch_sens/hw_ver3/touch_version_specific.c +++ b/components/esp_driver_touch_sens/hw_ver3/touch_version_specific.c @@ -331,8 +331,9 @@ esp_err_t touch_sensor_config_sleep_wakeup(touch_sensor_handle_t sens_handle, co ESP_ERR_INVALID_ARG, err, TAG, "Invalid sleep level"); /* Enabled touch sensor as wake-up source */ ESP_GOTO_ON_ERROR(esp_sleep_enable_touchpad_wakeup(), err, TAG, "Failed to enable touch sensor wakeup"); -#if SOC_PM_SUPPORT_RC_FAST_PD - ESP_GOTO_ON_ERROR(esp_sleep_pd_config(ESP_PD_DOMAIN_RC_FAST, ESP_PD_OPTION_ON), err, TAG, "Failed to keep touch sensor module clock during the sleep"); +#if SOC_PM_SUPPORT_RTC_PERIPH_PD + // Keep ESP_PD_DOMAIN_RTC_PERIPH power domain on during the light/deep sleep, so that to keep the touch sensor working + ESP_GOTO_ON_ERROR(esp_sleep_pd_config(ESP_PD_DOMAIN_RTC_PERIPH, ESP_PD_OPTION_ON), err, TAG, "Failed to keep touch sensor module clock during the sleep"); #endif /* If set the deep sleep channel (i.e., enable deep sleep wake-up), @@ -360,10 +361,10 @@ esp_err_t touch_sensor_config_sleep_wakeup(touch_sensor_handle_t sens_handle, co } else { /* Disable the touch sensor as wake-up source */ esp_sleep_disable_wakeup_source(ESP_SLEEP_WAKEUP_TOUCHPAD); -#if SOC_PM_SUPPORT_RC_FAST_PD - esp_sleep_pd_config(ESP_PD_DOMAIN_RC_FAST, ESP_PD_OPTION_AUTO); +#if SOC_PM_SUPPORT_RTC_PERIPH_PD + esp_sleep_pd_config(ESP_PD_DOMAIN_RTC_PERIPH, ESP_PD_OPTION_AUTO); #endif - + sens_handle->deep_slp_chan = NULL; sens_handle->sleep_en = false; } From aa7b7f225accfcef21fd1a05d6ec1d851d12a4c8 Mon Sep 17 00:00:00 2001 From: Lou Tianhao Date: Tue, 24 Sep 2024 11:04:12 +0800 Subject: [PATCH 112/472] change(esp_hw_support): change modem clock implementation --- components/esp_hw_support/modem_clock.c | 2 +- components/hal/esp32c5/modem_clock_hal.c | 8 ++++---- components/hal/esp32c6/modem_clock_hal.c | 2 +- components/hal/esp32c61/modem_clock_hal.c | 8 ++++---- components/hal/esp32h2/modem_clock_hal.c | 2 +- components/hal/include/hal/modem_clock_hal.h | 2 +- 6 files changed, 12 insertions(+), 12 deletions(-) diff --git a/components/esp_hw_support/modem_clock.c b/components/esp_hw_support/modem_clock.c index 63066d6302f..cd3f68a3e11 100644 --- a/components/esp_hw_support/modem_clock.c +++ b/components/esp_hw_support/modem_clock.c @@ -108,7 +108,7 @@ static void IRAM_ATTR modem_clock_coex_configure(modem_clock_context_t *ctx, boo static void IRAM_ATTR modem_clock_modem_adc_common_fe_configure(modem_clock_context_t *ctx, bool enable) { - modem_clock_hal_enable_modem_adc_common_fe_clock(ctx->hal, enable); + modem_clock_hal_enable_modem_common_fe_clock(ctx->hal, enable); } static void IRAM_ATTR modem_clock_modem_private_fe_configure(modem_clock_context_t *ctx, bool enable) diff --git a/components/hal/esp32c5/modem_clock_hal.c b/components/hal/esp32c5/modem_clock_hal.c index 0c6370faa08..554aaa94735 100644 --- a/components/hal/esp32c5/modem_clock_hal.c +++ b/components/hal/esp32c5/modem_clock_hal.c @@ -101,12 +101,9 @@ uint32_t IRAM_ATTR modem_clock_hal_get_clock_domain_icg_bitmap(modem_clock_hal_c return bitmap; } -void IRAM_ATTR modem_clock_hal_enable_modem_adc_common_fe_clock(modem_clock_hal_context_t *hal, bool enable) +void IRAM_ATTR modem_clock_hal_enable_modem_common_fe_clock(modem_clock_hal_context_t *hal, bool enable) { if (enable) { - modem_syscon_ll_enable_fe_adc_clock(hal->syscon_dev, enable); - modem_syscon_ll_enable_fe_dac_clock(hal->syscon_dev, enable); - modem_syscon_ll_enable_fe_pwdet_clock(hal->syscon_dev, enable); modem_syscon_ll_enable_fe_apb_clock(hal->syscon_dev, enable); modem_syscon_ll_enable_fe_80m_clock(hal->syscon_dev, enable); } @@ -116,6 +113,9 @@ void IRAM_ATTR modem_clock_hal_enable_modem_private_fe_clock(modem_clock_hal_con { if (enable) { modem_syscon_ll_enable_fe_160m_clock(hal->syscon_dev, enable); + modem_syscon_ll_enable_fe_dac_clock(hal->syscon_dev, enable); + modem_syscon_ll_enable_fe_pwdet_clock(hal->syscon_dev, enable); + modem_syscon_ll_enable_fe_adc_clock(hal->syscon_dev, enable); } } diff --git a/components/hal/esp32c6/modem_clock_hal.c b/components/hal/esp32c6/modem_clock_hal.c index ed242febec4..7901b829dab 100644 --- a/components/hal/esp32c6/modem_clock_hal.c +++ b/components/hal/esp32c6/modem_clock_hal.c @@ -101,7 +101,7 @@ uint32_t IRAM_ATTR modem_clock_hal_get_clock_domain_icg_bitmap(modem_clock_hal_c return bitmap; } -void IRAM_ATTR modem_clock_hal_enable_modem_adc_common_fe_clock(modem_clock_hal_context_t *hal, bool enable) +void IRAM_ATTR modem_clock_hal_enable_modem_common_fe_clock(modem_clock_hal_context_t *hal, bool enable) { if (enable) { modem_syscon_ll_enable_fe_apb_clock(hal->syscon_dev, enable); diff --git a/components/hal/esp32c61/modem_clock_hal.c b/components/hal/esp32c61/modem_clock_hal.c index fe84dcfb850..3af99192403 100644 --- a/components/hal/esp32c61/modem_clock_hal.c +++ b/components/hal/esp32c61/modem_clock_hal.c @@ -101,12 +101,9 @@ uint32_t IRAM_ATTR modem_clock_hal_get_clock_domain_icg_bitmap(modem_clock_hal_c return bitmap; } -void IRAM_ATTR modem_clock_hal_enable_modem_adc_common_fe_clock(modem_clock_hal_context_t *hal, bool enable) +void IRAM_ATTR modem_clock_hal_enable_modem_common_fe_clock(modem_clock_hal_context_t *hal, bool enable) { if (enable) { - modem_syscon_ll_enable_fe_adc_clock(hal->syscon_dev, enable); - modem_syscon_ll_enable_fe_dac_clock(hal->syscon_dev, enable); - modem_syscon_ll_enable_fe_pwdet_clock(hal->syscon_dev, enable); modem_syscon_ll_enable_fe_apb_clock(hal->syscon_dev, enable); modem_syscon_ll_enable_fe_80m_clock(hal->syscon_dev, enable); } @@ -116,6 +113,9 @@ void IRAM_ATTR modem_clock_hal_enable_modem_private_fe_clock(modem_clock_hal_con { if (enable) { modem_syscon_ll_enable_fe_160m_clock(hal->syscon_dev, enable); + modem_syscon_ll_enable_fe_adc_clock(hal->syscon_dev, enable); + modem_syscon_ll_enable_fe_dac_clock(hal->syscon_dev, enable); + modem_syscon_ll_enable_fe_pwdet_clock(hal->syscon_dev, enable); } } diff --git a/components/hal/esp32h2/modem_clock_hal.c b/components/hal/esp32h2/modem_clock_hal.c index 879e694d2a4..851e0c01ffc 100644 --- a/components/hal/esp32h2/modem_clock_hal.c +++ b/components/hal/esp32h2/modem_clock_hal.c @@ -19,7 +19,7 @@ typedef enum { MODEM_CLOCK_EXT32K_CODE = 2 } modem_clock_32k_clk_src_code_t; -void IRAM_ATTR modem_clock_hal_enable_modem_adc_common_fe_clock(modem_clock_hal_context_t *hal, bool enable) +void IRAM_ATTR modem_clock_hal_enable_modem_common_fe_clock(modem_clock_hal_context_t *hal, bool enable) { modem_syscon_ll_enable_fe_apb_clock(hal->syscon_dev, enable); modem_syscon_ll_enable_fe_32m_clock(hal->syscon_dev, enable); diff --git a/components/hal/include/hal/modem_clock_hal.h b/components/hal/include/hal/modem_clock_hal.h index dfc5009741b..ec04d18d718 100644 --- a/components/hal/include/hal/modem_clock_hal.h +++ b/components/hal/include/hal/modem_clock_hal.h @@ -29,7 +29,7 @@ void modem_clock_hal_set_clock_domain_icg_bitmap(modem_clock_hal_context_t *hal, uint32_t modem_clock_hal_get_clock_domain_icg_bitmap(modem_clock_hal_context_t *hal, modem_clock_domain_t domain); #endif -void modem_clock_hal_enable_modem_adc_common_fe_clock(modem_clock_hal_context_t *hal, bool enable); +void modem_clock_hal_enable_modem_common_fe_clock(modem_clock_hal_context_t *hal, bool enable); void modem_clock_hal_enable_modem_private_fe_clock(modem_clock_hal_context_t *hal, bool enable); #if SOC_BT_SUPPORTED From 0738314308ad36a73601ddb8bb82f1dcbfe1f550 Mon Sep 17 00:00:00 2001 From: Ondrej Kosta Date: Thu, 19 Sep 2024 15:54:26 +0200 Subject: [PATCH 113/472] feat(esp_eth): added new generic PHY driver --- components/esp_eth/CMakeLists.txt | 1 + components/esp_eth/include/esp_eth_phy.h | 44 ++++-- .../esp_eth/include/esp_eth_phy_802_3.h | 29 ++-- .../esp_eth/src/phy/esp_eth_phy_802_3.c | 129 +++++++++++++++--- .../esp_eth/src/phy/esp_eth_phy_generic.c | 37 +++++ .../esp_eth/src/phy/esp_eth_phy_ip101.c | 19 ++- .../esp_eth/src/phy/esp_eth_phy_lan87xx.c | 22 +-- .../esp_eth/src/phy/esp_eth_phy_rtl8201.c | 22 ++- docs/en/api-reference/network/esp_eth.rst | 20 ++- .../Kconfig.projbuild | 9 ++ .../protocol_examples_common/eth_connect.c | 4 +- .../ethernet_init/Kconfig.projbuild | 9 ++ .../components/ethernet_init/ethernet_init.c | 4 +- examples/ethernet/basic/pytest_eth_basic.py | 1 + .../basic/sdkconfig.ci.default_generic | 11 ++ 15 files changed, 283 insertions(+), 78 deletions(-) create mode 100644 components/esp_eth/src/phy/esp_eth_phy_generic.c create mode 100644 examples/ethernet/basic/sdkconfig.ci.default_generic diff --git a/components/esp_eth/CMakeLists.txt b/components/esp_eth/CMakeLists.txt index 132f01a3011..6a6941397d6 100644 --- a/components/esp_eth/CMakeLists.txt +++ b/components/esp_eth/CMakeLists.txt @@ -30,6 +30,7 @@ if(CONFIG_ETH_ENABLED) list(APPEND srcs "src/mac/esp_eth_mac_esp.c" "src/mac/esp_eth_mac_esp_dma.c" "src/mac/esp_eth_mac_esp_gpio.c" + "src/phy/esp_eth_phy_generic.c" "src/phy/esp_eth_phy_dp83848.c" "src/phy/esp_eth_phy_ip101.c" "src/phy/esp_eth_phy_ksz80xx.c" diff --git a/components/esp_eth/include/esp_eth_phy.h b/components/esp_eth/include/esp_eth_phy.h index 82c16aef41d..109a8014dc4 100644 --- a/components/esp_eth/include/esp_eth_phy.h +++ b/components/esp_eth/include/esp_eth_phy.h @@ -13,7 +13,8 @@ extern "C" { #endif -#define ESP_ETH_PHY_ADDR_AUTO (-1) +#define ESP_ETH_PHY_ADDR_AUTO (-1) +#define ESP_ETH_NO_POST_HW_RESET_DELAY (-1) /** * @brief Auto-negotiation control commands @@ -273,24 +274,45 @@ struct esp_eth_phy_s { * */ typedef struct { - int32_t phy_addr; /*!< PHY address, set -1 to enable PHY address detection at initialization stage */ - uint32_t reset_timeout_ms; /*!< Reset timeout value (Unit: ms) */ - uint32_t autonego_timeout_ms; /*!< Auto-negotiation timeout value (Unit: ms) */ - int reset_gpio_num; /*!< Reset GPIO number, -1 means no hardware reset */ + int32_t phy_addr; /*!< PHY address, set -1 to enable PHY address detection at initialization stage */ + uint32_t reset_timeout_ms; /*!< Reset timeout value (Unit: ms) */ + uint32_t autonego_timeout_ms; /*!< Auto-negotiation timeout value (Unit: ms) */ + int reset_gpio_num; /*!< Reset GPIO number, -1 means no hardware reset */ + int32_t hw_reset_assert_time_us; /*!< Time the reset pin is asserted (Unit: us), 0 to use chip specific default */ + int32_t post_hw_reset_delay_ms; /*!< Time to wait after the HW reset (Unit: ms), 0 to use chip specific default, -1 means no wait */ } eth_phy_config_t; /** * @brief Default configuration for Ethernet PHY object * */ -#define ETH_PHY_DEFAULT_CONFIG() \ - { \ - .phy_addr = ESP_ETH_PHY_ADDR_AUTO, \ - .reset_timeout_ms = 100, \ - .autonego_timeout_ms = 4000, \ - .reset_gpio_num = 5, \ +#define ETH_PHY_DEFAULT_CONFIG() \ + { \ + .phy_addr = ESP_ETH_PHY_ADDR_AUTO, \ + .reset_timeout_ms = 100, \ + .autonego_timeout_ms = 4000, \ + .reset_gpio_num = 5, \ + .hw_reset_assert_time_us = 0, \ + .post_hw_reset_delay_ms = 0 \ } +/** +* @brief Create a PHY instance of generic chip which conforms with IEEE 802.3 +* +* @note Default reset timing configuration is set conservatively( @c DEFAULT_PHY_RESET_ASSERTION_TIME_US ). +* If you need faster response and your chip supports it, configure it via @c config parameter. +* +* @warning While basic functionality should always work, some specific features might be limited, +* even if the PHY meets IEEE 802.3 standard. A typical example is loopback functionality, +* where certain PHYs may require setting a specific speed mode to operate correctly. +* +* @param[in] config configuration of PHY +* @return +* - instance: create PHY instance successfully +* - NULL: create PHY instance failed because some error occurred + */ +esp_eth_phy_t *esp_eth_phy_new_generic(const eth_phy_config_t *config); + /** * @brief Create a PHY instance of IP101 * diff --git a/components/esp_eth/include/esp_eth_phy_802_3.h b/components/esp_eth/include/esp_eth_phy_802_3.h index 0cc83ed1390..e90646bd37d 100644 --- a/components/esp_eth/include/esp_eth_phy_802_3.h +++ b/components/esp_eth/include/esp_eth_phy_802_3.h @@ -19,13 +19,15 @@ extern "C" { * */ typedef struct { - esp_eth_phy_t parent; /*!< Parent Ethernet PHY instance */ - esp_eth_mediator_t *eth; /*!< Mediator of Ethernet driver */ - int addr; /*!< PHY address */ - uint32_t reset_timeout_ms; /*!< Reset timeout value (Unit: ms) */ - uint32_t autonego_timeout_ms; /*!< Auto-negotiation timeout value (Unit: ms) */ - eth_link_t link_status; /*!< Current Link status */ - int reset_gpio_num; /*!< Reset GPIO number, -1 means no hardware reset */ + esp_eth_phy_t parent; /*!< Parent Ethernet PHY instance */ + esp_eth_mediator_t *eth; /*!< Mediator of Ethernet driver */ + int addr; /*!< PHY address */ + uint32_t reset_timeout_ms; /*!< Reset timeout value (Unit: ms) */ + uint32_t autonego_timeout_ms; /*!< Auto-negotiation timeout value (Unit: ms) */ + eth_link_t link_status; /*!< Current Link status */ + int reset_gpio_num; /*!< Reset GPIO number, -1 means no hardware reset */ + int32_t hw_reset_assert_time_us; /*!< Time the reset pin is asserted (Unit: us) */ + int32_t post_hw_reset_delay_ms; /*!< Time to wait after the HW reset (Unit: ms) */ } phy_802_3_t; /** @@ -73,6 +75,16 @@ esp_err_t esp_eth_phy_802_3_reset(phy_802_3_t *phy_802_3); */ esp_err_t esp_eth_phy_802_3_autonego_ctrl(phy_802_3_t *phy_802_3, eth_phy_autoneg_cmd_t cmd, bool *autonego_en_stat); +/** + * @brief Retrieve link status and propagate the status to higher layers if the status changed + * + * @param phy_802_3 IEEE 802.3 PHY object infostructure + * @return + * - ESP_OK: Ethernet PHY link status retrieved successfully + * - ESP_FAIL: Error occurred during reading registry + */ +esp_err_t esp_eth_phy_802_3_updt_link_dup_spd(phy_802_3_t *phy_802_3); + /** * @brief Power control of Ethernet PHY * @@ -183,7 +195,7 @@ esp_err_t esp_eth_phy_802_3_deinit(phy_802_3_t *phy_802_3); * * @param phy_802_3 IEEE 802.3 PHY object infostructure * @return - * - ESP_OK: Ethrnet PHY infostructure deleted + * - ESP_OK: Ethernet PHY infostructure deleted */ esp_err_t esp_eth_phy_802_3_del(phy_802_3_t *phy_802_3); @@ -194,6 +206,7 @@ esp_err_t esp_eth_phy_802_3_del(phy_802_3_t *phy_802_3); * @param reset_assert_us Hardware reset pin assertion time * @return * - ESP_OK: reset Ethernet PHY successfully + * - ESP_ERR_NOT_ALLOWED: reset GPIO not defined */ esp_err_t esp_eth_phy_802_3_reset_hw(phy_802_3_t *phy_802_3, uint32_t reset_assert_us); diff --git a/components/esp_eth/src/phy/esp_eth_phy_802_3.c b/components/esp_eth/src/phy/esp_eth_phy_802_3.c index f120821187f..b0c22cb53f4 100644 --- a/components/esp_eth/src/phy/esp_eth_phy_802_3.c +++ b/components/esp_eth/src/phy/esp_eth_phy_802_3.c @@ -16,11 +16,14 @@ #include "esp_rom_sys.h" #include "esp_eth_phy_802_3.h" -// Default reset assertion time is selected to be 100us as it is most commonly used value among PHY chips. +// Default reset assertion time is selected to be 100us as it is most commonly used value among ESP-IDF supported PHY chips. #define PHY_RESET_ASSERTION_TIME_US 100 static const char *TAG = "eth_phy_802_3"; +// TODO: IDF-11362 (should be renamed to esp_eth_phy_802_3_reset_hw with the next major release) +static esp_err_t esp_eth_phy_802_3_reset_hw_internal(phy_802_3_t *phy_802_3); + static esp_err_t set_mediator(esp_eth_phy_t *phy, esp_eth_mediator_t *eth) { phy_802_3_t *phy_802_3 = esp_eth_phy_into_phy_802_3(phy); @@ -33,10 +36,10 @@ static esp_err_t reset(esp_eth_phy_t *phy) return esp_eth_phy_802_3_reset(phy_802_3); } -static esp_err_t reset_hw_default(esp_eth_phy_t *phy) +static esp_err_t reset_hw(esp_eth_phy_t *phy) { phy_802_3_t *phy_802_3 = esp_eth_phy_into_phy_802_3(phy); - return esp_eth_phy_802_3_reset_hw(phy_802_3, PHY_RESET_ASSERTION_TIME_US); + return esp_eth_phy_802_3_reset_hw_internal(phy_802_3); } static esp_err_t autonego_ctrl(esp_eth_phy_t *phy, eth_phy_autoneg_cmd_t cmd, bool *autonego_en_stat) @@ -93,6 +96,14 @@ static esp_err_t set_link(esp_eth_phy_t *phy, eth_link_t link) return esp_eth_phy_802_3_set_link(phy_802_3, link); } +static esp_err_t get_link(esp_eth_phy_t *phy) +{ + phy_802_3_t *phy_802_3 = esp_eth_phy_into_phy_802_3(phy); + + /* Update information about link, speed, duplex */ + return esp_eth_phy_802_3_updt_link_dup_spd(phy_802_3); +} + static esp_err_t init(esp_eth_phy_t *phy) { phy_802_3_t *phy_802_3 = esp_eth_phy_into_phy_802_3(phy); @@ -143,21 +154,6 @@ esp_err_t esp_eth_phy_802_3_reset(phy_802_3_t *phy_802_3) return ret; } -/** - * @brief PHY hardware reset with default assert time - * - * @note Default reset assertion time is selected to be 100us as it is most commonly used value among PHY chips. - * If your PHY chip requires different value, redefine the `reset_hw` function in derived PHY specific driver structure. - * - * @param phy Ethernet PHY instance - * @return - * - ESP_OK on success - */ -esp_err_t esp_eth_phy_802_3_reset_hw_default(phy_802_3_t *phy_802_3) -{ - return esp_eth_phy_802_3_reset_hw(phy_802_3, PHY_RESET_ASSERTION_TIME_US); -} - esp_err_t esp_eth_phy_802_3_autonego_ctrl(phy_802_3_t *phy_802_3, eth_phy_autoneg_cmd_t cmd, bool *autonego_en_stat) { esp_err_t ret = ESP_OK; @@ -220,6 +216,67 @@ esp_err_t esp_eth_phy_802_3_autonego_ctrl(phy_802_3_t *phy_802_3, eth_phy_autone return ret; } +esp_err_t esp_eth_phy_802_3_updt_link_dup_spd(phy_802_3_t *phy_802_3) +{ + esp_err_t ret = ESP_OK; + esp_eth_mediator_t *eth = phy_802_3->eth; + uint32_t addr = phy_802_3->addr; + eth_speed_t speed = ETH_SPEED_10M; + eth_duplex_t duplex = ETH_DUPLEX_HALF; + uint32_t peer_pause_ability = false; + bmcr_reg_t bmcr; + bmsr_reg_t bmsr; + anar_reg_t anar; + anlpar_reg_t anlpar; + + ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, addr, ETH_PHY_BMSR_REG_ADDR, &(bmsr.val)), err, TAG, "read BMSR failed"); + eth_link_t link = bmsr.link_status ? ETH_LINK_UP : ETH_LINK_DOWN; + /* check if link status changed */ + if (phy_802_3->link_status != link) { + /* when link up, read negotiation result */ + if (link == ETH_LINK_UP) { + ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, addr, ETH_PHY_BMCR_REG_ADDR, &(bmcr.val)), err, TAG, "read BMCR failed"); + ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, addr, ETH_PHY_ANAR_REG_ADDR, &(anar.val)), err, TAG, "read ANAR failed"); + ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, addr, ETH_PHY_ANLPAR_REG_ADDR, &(anlpar.val)), err, TAG, "read ANLPAR failed"); + if (bmcr.en_auto_nego) { + if (anar.base100_tx_fd && anlpar.base100_tx_fd) { + speed = ETH_SPEED_100M; + duplex = ETH_DUPLEX_FULL; + } else if (anar.base100_tx && anlpar.base100_tx) { + speed = ETH_SPEED_100M; + duplex = ETH_DUPLEX_HALF; + } else if (anar.base10_t_fd && anlpar.base10_t_fd) { + speed = ETH_SPEED_10M; + duplex = ETH_DUPLEX_FULL; + } else if (anar.base10_t && anlpar.base10_t) { + speed = ETH_SPEED_10M; + duplex = ETH_DUPLEX_HALF; + } else { + ESP_GOTO_ON_FALSE(false, ESP_FAIL, err, TAG, "invalid auto-nego speed/duplex advertising"); + } + } else { + speed = bmcr.speed_select ? ETH_SPEED_100M : ETH_SPEED_10M; + duplex = bmcr.duplex_mode ? ETH_DUPLEX_FULL : ETH_DUPLEX_HALF; + } + + ESP_GOTO_ON_ERROR(eth->on_state_changed(eth, ETH_STATE_SPEED, (void *)speed), err, TAG, "change speed failed"); + ESP_GOTO_ON_ERROR(eth->on_state_changed(eth, ETH_STATE_DUPLEX, (void *)duplex), err, TAG, "change duplex failed"); + /* if we're in duplex mode, and peer has the flow control ability */ + if (duplex == ETH_DUPLEX_FULL && anlpar.symmetric_pause) { + peer_pause_ability = 1; + } else { + peer_pause_ability = 0; + } + ESP_GOTO_ON_ERROR(eth->on_state_changed(eth, ETH_STATE_PAUSE, (void *)peer_pause_ability), err, TAG, "change pause ability failed"); + } + ESP_GOTO_ON_ERROR(eth->on_state_changed(eth, ETH_STATE_LINK, (void *)link), err, TAG, "change link failed"); + phy_802_3->link_status = link; + } + return ESP_OK; +err: + return ret; +} + esp_err_t esp_eth_phy_802_3_pwrctl(phy_802_3_t *phy_802_3, bool enable) { esp_err_t ret = ESP_OK; @@ -392,8 +449,28 @@ esp_err_t esp_eth_phy_802_3_reset_hw(phy_802_3_t *phy_802_3, uint32_t reset_asse vTaskDelay(pdMS_TO_TICKS(reset_assert_us/1000)); } gpio_set_level(phy_802_3->reset_gpio_num, 1); + return ESP_OK; } - return ESP_OK; + return ESP_ERR_NOT_ALLOWED; +} + +/** + * @brief Hardware reset with internal timing configuration defined during initialization + * + * @param phy_802_3 IEEE 802.3 PHY object infostructure + * @return + * - ESP_OK: reset Ethernet PHY successfully + * - ESP_ERR_NOT_ALLOWED: reset GPIO not defined + */ +static esp_err_t esp_eth_phy_802_3_reset_hw_internal(phy_802_3_t *phy_802_3) +{ + esp_err_t ret = ESP_OK; + if ((ret = esp_eth_phy_802_3_reset_hw(phy_802_3, phy_802_3->hw_reset_assert_time_us)) == ESP_OK) { + if (phy_802_3->post_hw_reset_delay_ms > 0) { + vTaskDelay(pdMS_TO_TICKS(phy_802_3->post_hw_reset_delay_ms)); + } + } + return ret; } esp_err_t esp_eth_phy_802_3_detect_phy_addr(esp_eth_mediator_t *eth, int *detected_addr) @@ -601,9 +678,19 @@ esp_err_t esp_eth_phy_802_3_obj_config_init(phy_802_3_t *phy_802_3, const eth_ph phy_802_3->reset_timeout_ms = config->reset_timeout_ms; phy_802_3->reset_gpio_num = config->reset_gpio_num; phy_802_3->autonego_timeout_ms = config->autonego_timeout_ms; + if (config->hw_reset_assert_time_us > 0) { + phy_802_3->hw_reset_assert_time_us = config->hw_reset_assert_time_us; + } else { + phy_802_3->hw_reset_assert_time_us = PHY_RESET_ASSERTION_TIME_US; + } + if (config->post_hw_reset_delay_ms > 0) { + phy_802_3->post_hw_reset_delay_ms = config->post_hw_reset_delay_ms; + } else { + phy_802_3->post_hw_reset_delay_ms = ESP_ETH_NO_POST_HW_RESET_DELAY; + } phy_802_3->parent.reset = reset; - phy_802_3->parent.reset_hw = reset_hw_default; + phy_802_3->parent.reset_hw = reset_hw; phy_802_3->parent.init = init; phy_802_3->parent.deinit = deinit; phy_802_3->parent.set_mediator = set_mediator; @@ -617,7 +704,7 @@ esp_err_t esp_eth_phy_802_3_obj_config_init(phy_802_3_t *phy_802_3, const eth_ph phy_802_3->parent.set_duplex = set_duplex; phy_802_3->parent.del = del; phy_802_3->parent.set_link = set_link; - phy_802_3->parent.get_link = NULL; + phy_802_3->parent.get_link = get_link; phy_802_3->parent.custom_ioctl = NULL; err: diff --git a/components/esp_eth/src/phy/esp_eth_phy_generic.c b/components/esp_eth/src/phy/esp_eth_phy_generic.c new file mode 100644 index 00000000000..0003758bf86 --- /dev/null +++ b/components/esp_eth/src/phy/esp_eth_phy_generic.c @@ -0,0 +1,37 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include "esp_log.h" +#include "esp_check.h" +#include "esp_eth.h" +#include "esp_eth_phy_802_3.h" + +static const char *TAG = "eth_phy_generic"; + +// Default reset timing is intentionally conservative +#define DEFAULT_PHY_GENERIC_RESET_ASSERTION_TIME_US 10000 +#define DEFAULT_PHY_GENERIC_POST_RESET_DELAY_MS 500 + +esp_eth_phy_t *esp_eth_phy_new_generic(const eth_phy_config_t *config) +{ + esp_eth_phy_t *ret = NULL; + phy_802_3_t *phy_802_3 = calloc(1, sizeof(phy_802_3_t)); + eth_phy_config_t phy_802_3_config = *config; + // default chip specific configuration if not defined by user + if (config->hw_reset_assert_time_us == 0) { + phy_802_3_config.hw_reset_assert_time_us = DEFAULT_PHY_GENERIC_RESET_ASSERTION_TIME_US; + } + if (config->post_hw_reset_delay_ms == 0) { + phy_802_3_config.post_hw_reset_delay_ms = DEFAULT_PHY_GENERIC_POST_RESET_DELAY_MS; + } + ESP_GOTO_ON_FALSE(esp_eth_phy_802_3_obj_config_init(phy_802_3, &phy_802_3_config) == ESP_OK, + NULL, err, TAG, "configuration initialization of PHY 802.3 failed"); + + return &phy_802_3->parent; +err: + return ret; +} diff --git a/components/esp_eth/src/phy/esp_eth_phy_ip101.c b/components/esp_eth/src/phy/esp_eth_phy_ip101.c index e66fb78b93e..42fce95b317 100644 --- a/components/esp_eth/src/phy/esp_eth_phy_ip101.c +++ b/components/esp_eth/src/phy/esp_eth_phy_ip101.c @@ -173,14 +173,6 @@ static esp_err_t ip101_get_link(esp_eth_phy_t *phy) return ret; } -static esp_err_t ip101_reset_hw(esp_eth_phy_t *phy) -{ - phy_802_3_t *phy_802_3 = esp_eth_phy_into_phy_802_3(phy); - esp_err_t ret = esp_eth_phy_802_3_reset_hw(phy_802_3, IP101_PHY_RESET_ASSERTION_TIME_US); - vTaskDelay(pdMS_TO_TICKS(IP101_PHY_POST_RESET_INIT_TIME_MS)); - return ret; -} - static esp_err_t ip101_init(esp_eth_phy_t *phy) { esp_err_t ret = ESP_OK; @@ -206,13 +198,20 @@ esp_eth_phy_t *esp_eth_phy_new_ip101(const eth_phy_config_t *config) esp_eth_phy_t *ret = NULL; phy_ip101_t *ip101 = calloc(1, sizeof(phy_ip101_t)); ESP_GOTO_ON_FALSE(ip101, NULL, err, TAG, "calloc ip101 failed"); - ESP_GOTO_ON_FALSE(esp_eth_phy_802_3_obj_config_init(&ip101->phy_802_3, config) == ESP_OK, + eth_phy_config_t ip101_config = *config; + // default chip specific configuration + if (config->hw_reset_assert_time_us == 0) { + ip101_config.hw_reset_assert_time_us = IP101_PHY_RESET_ASSERTION_TIME_US; + } + if (config->post_hw_reset_delay_ms == 0) { + ip101_config.post_hw_reset_delay_ms = IP101_PHY_POST_RESET_INIT_TIME_MS; + } + ESP_GOTO_ON_FALSE(esp_eth_phy_802_3_obj_config_init(&ip101->phy_802_3, &ip101_config) == ESP_OK, NULL, err, TAG, "configuration initialization of PHY 802.3 failed"); // redefine functions which need to be customized for sake of IP101 ip101->phy_802_3.parent.init = ip101_init; ip101->phy_802_3.parent.get_link = ip101_get_link; - ip101->phy_802_3.parent.reset_hw = ip101_reset_hw; return &ip101->phy_802_3.parent; err: diff --git a/components/esp_eth/src/phy/esp_eth_phy_lan87xx.c b/components/esp_eth/src/phy/esp_eth_phy_lan87xx.c index d6f8e148fd1..1d9f666f9a7 100644 --- a/components/esp_eth/src/phy/esp_eth_phy_lan87xx.c +++ b/components/esp_eth/src/phy/esp_eth_phy_lan87xx.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2019-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -14,6 +14,9 @@ static const char *TAG = "lan87xx"; +/* It was observed that assert nRST signal on LAN87xx needs to be a little longer than the minimum specified in datasheet */ +#define LAN87XX_PHY_RESET_ASSERTION_TIME_US 150 + /***************List of Supported Models***************/ // See Microchip's Application Note AN25.3 summarizing differences among below models @@ -287,12 +290,6 @@ static esp_err_t lan87xx_get_link(esp_eth_phy_t *phy) return ret; } -static esp_err_t lan87xx_reset_hw(esp_eth_phy_t *phy) -{ - /* It was observed that assert nRST signal on LAN87xx needs to be a little longer than the minimum specified in datasheet */ - return esp_eth_phy_802_3_reset_hw(esp_eth_phy_into_phy_802_3(phy), 150); -} - static esp_err_t lan87xx_autonego_ctrl(esp_eth_phy_t *phy, eth_phy_autoneg_cmd_t cmd, bool *autonego_en_stat) { esp_err_t ret = ESP_OK; @@ -366,11 +363,18 @@ esp_eth_phy_t *esp_eth_phy_new_lan87xx(const eth_phy_config_t *config) esp_eth_phy_t *ret = NULL; phy_lan87xx_t *lan87xx = calloc(1, sizeof(phy_lan87xx_t)); ESP_GOTO_ON_FALSE(lan87xx, NULL, err, TAG, "calloc lan87xx failed"); - ESP_GOTO_ON_FALSE(esp_eth_phy_802_3_obj_config_init(&lan87xx->phy_802_3, config) == ESP_OK, + eth_phy_config_t lan87xx_config = *config; + // default chip specific configuration + if (config->hw_reset_assert_time_us == 0) { + lan87xx_config.hw_reset_assert_time_us = LAN87XX_PHY_RESET_ASSERTION_TIME_US; + } + if (config->post_hw_reset_delay_ms == 0) { + lan87xx_config.post_hw_reset_delay_ms = ESP_ETH_NO_POST_HW_RESET_DELAY; + } + ESP_GOTO_ON_FALSE(esp_eth_phy_802_3_obj_config_init(&lan87xx->phy_802_3, &lan87xx_config) == ESP_OK, NULL, err, TAG, "configuration initialization of PHY 802.3 failed"); // redefine functions which need to be customized for sake of LAN87xx - lan87xx->phy_802_3.parent.reset_hw = lan87xx_reset_hw; lan87xx->phy_802_3.parent.init = lan87xx_init; lan87xx->phy_802_3.parent.get_link = lan87xx_get_link; lan87xx->phy_802_3.parent.autonego_ctrl = lan87xx_autonego_ctrl; diff --git a/components/esp_eth/src/phy/esp_eth_phy_rtl8201.c b/components/esp_eth/src/phy/esp_eth_phy_rtl8201.c index 4f3a9337b4f..c2bf0900e3a 100644 --- a/components/esp_eth/src/phy/esp_eth_phy_rtl8201.c +++ b/components/esp_eth/src/phy/esp_eth_phy_rtl8201.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2019-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -149,15 +149,6 @@ static esp_err_t rtl8201_loopback(esp_eth_phy_t *phy, bool enable) return ret; } -static esp_err_t rtl8201_reset_hw(esp_eth_phy_t *phy) -{ - phy_802_3_t *phy_802_3 = esp_eth_phy_into_phy_802_3(phy); - esp_err_t ret = esp_eth_phy_802_3_reset_hw(phy_802_3, RTL8201_PHY_RESET_ASSERTION_TIME_US); - vTaskDelay(pdMS_TO_TICKS(RTL8201_PHY_POST_RESET_INIT_TIME_MS)); - return ret; -} - - static esp_err_t rtl8201_init(esp_eth_phy_t *phy) { esp_err_t ret = ESP_OK; @@ -183,7 +174,15 @@ esp_eth_phy_t *esp_eth_phy_new_rtl8201(const eth_phy_config_t *config) esp_eth_phy_t *ret = NULL; phy_rtl8201_t *rtl8201 = calloc(1, sizeof(phy_rtl8201_t)); ESP_GOTO_ON_FALSE(rtl8201, NULL, err, TAG, "calloc rtl8201 failed"); - ESP_GOTO_ON_FALSE(esp_eth_phy_802_3_obj_config_init(&rtl8201->phy_802_3, config) == ESP_OK, + eth_phy_config_t rtl8201_config = *config; + // default chip specific configuration + if (config->hw_reset_assert_time_us == 0) { + rtl8201_config.hw_reset_assert_time_us = RTL8201_PHY_RESET_ASSERTION_TIME_US; + } + if (config->post_hw_reset_delay_ms == 0) { + rtl8201_config.post_hw_reset_delay_ms = RTL8201_PHY_POST_RESET_INIT_TIME_MS; + } + ESP_GOTO_ON_FALSE(esp_eth_phy_802_3_obj_config_init(&rtl8201->phy_802_3, &rtl8201_config) == ESP_OK, NULL, err, TAG, "configuration initialization of PHY 802.3 failed"); // redefine functions which need to be customized for sake of RTL8201 @@ -191,7 +190,6 @@ esp_eth_phy_t *esp_eth_phy_new_rtl8201(const eth_phy_config_t *config) rtl8201->phy_802_3.parent.get_link = rtl8201_get_link; rtl8201->phy_802_3.parent.autonego_ctrl = rtl8201_autonego_ctrl; rtl8201->phy_802_3.parent.loopback = rtl8201_loopback; - rtl8201->phy_802_3.parent.reset_hw = rtl8201_reset_hw; return &rtl8201->phy_802_3.parent; err: diff --git a/docs/en/api-reference/network/esp_eth.rst b/docs/en/api-reference/network/esp_eth.rst index bf22ff5b8c3..ced34bb9822 100644 --- a/docs/en/api-reference/network/esp_eth.rst +++ b/docs/en/api-reference/network/esp_eth.rst @@ -269,6 +269,10 @@ Configuration for PHY is described in :cpp:class:`eth_phy_config_t`, including: * :cpp:member:`eth_phy_config_t::reset_gpio_num`: if your board also connects the PHY reset pin to one of the GPIO, then set it here. Otherwise, set this field to ``-1``. + * :cpp:member:`eth_phy_config_t::hw_reset_assert_time_us`: Time the PHY reset pin is asserted in usec. Set this field to ``0`` to use chip specific default timing. + + * :cpp:member:`eth_phy_config_t::post_hw_reset_delay_ms`: Time to wait after the PHY hardware reset is done in msec. Set this field to ``0`` to use chip specific default timing. Set this field to ``-1`` to not wait after the PHY hardware reset. + ESP-IDF provides a default configuration for MAC and PHY in macro :c:macro:`ETH_MAC_DEFAULT_CONFIG` and :c:macro:`ETH_PHY_DEFAULT_CONFIG`. @@ -288,19 +292,23 @@ The Ethernet driver is implemented in an Object-Oriented style. Any operation on eth_mac_config_t mac_config = ETH_MAC_DEFAULT_CONFIG(); // apply default common MAC configuration eth_esp32_emac_config_t esp32_emac_config = ETH_ESP32_EMAC_DEFAULT_CONFIG(); // apply default vendor-specific MAC configuration - esp32_emac_config.smi_mdc_gpio_num = CONFIG_EXAMPLE_ETH_MDC_GPIO; // alter the GPIO used for MDC signal - esp32_emac_config.smi_mdio_gpio_num = CONFIG_EXAMPLE_ETH_MDIO_GPIO; // alter the GPIO used for MDIO signal + esp32_emac_config.smi_gpio.mdc_num = CONFIG_EXAMPLE_ETH_MDC_GPIO; // alter the GPIO used for MDC signal + esp32_emac_config.smi_gpio.mdio_num = CONFIG_EXAMPLE_ETH_MDIO_GPIO; // alter the GPIO used for MDIO signa esp_eth_mac_t *mac = esp_eth_mac_new_esp32(&esp32_emac_config, &mac_config); // create MAC instance eth_phy_config_t phy_config = ETH_PHY_DEFAULT_CONFIG(); // apply default PHY configuration phy_config.phy_addr = CONFIG_EXAMPLE_ETH_PHY_ADDR; // alter the PHY address according to your board design phy_config.reset_gpio_num = CONFIG_EXAMPLE_ETH_PHY_RST_GPIO; // alter the GPIO used for PHY reset - esp_eth_phy_t *phy = esp_eth_phy_new_ip101(&phy_config); // create PHY instance - // ESP-IDF officially supports several different Ethernet PHY chip driver + esp_eth_phy_t *phy = esp_eth_phy_new_generic(&phy_config); // create generic PHY instance + // ESP-IDF officially supports several different specific Ethernet PHY chip driver + // esp_eth_phy_t *phy = esp_eth_phy_new_ip101(&phy_config); // esp_eth_phy_t *phy = esp_eth_phy_new_rtl8201(&phy_config); // esp_eth_phy_t *phy = esp_eth_phy_new_lan8720(&phy_config); // esp_eth_phy_t *phy = esp_eth_phy_new_dp83848(&phy_config); + .. note:: + Any Ethernet PHY chip compliant with IEEE 802.3 can be used when creating new PHY instance with :cpp:func:`esp_eth_phy_new_generic`. However, while basic functionality should always work, some specific features might be limited, even if the PHY meets IEEE 802.3 standard. A typical example is loopback functionality, where certain PHYs may require setting a specific speed mode to operate correctly. If this is the concern and you need PHY driver specifically tailored to your chip needs, use drivers for PHY chips the ESP-IDF already officially supports or consult with :ref:`Custom PHY Driver ` section to create a new custom driver. + Optional Runtime MAC Clock Configuration ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -557,10 +565,12 @@ Application Examples Advanced Topics --------------- +.. _custom-phy-driver: + Custom PHY Driver ^^^^^^^^^^^^^^^^^ -There are multiple PHY manufacturers with wide portfolios of chips available. The ESP-IDF already supports several PHY chips however one can easily get to a point where none of them satisfies the user's actual needs due to price, features, stock availability, etc. +There are multiple PHY manufacturers with wide portfolios of chips available. The ESP-IDF supports ``Generic PHY`` and also several specific PHY chips however one can easily get to a point where none of them satisfies the user's actual needs due to price, features, stock availability, etc. Luckily, a management interface between EMAC and PHY is standardized by IEEE 802.3 in Section 22.2.4 Management Functions. It defines provisions of the so-called "MII Management Interface" to control the PHY and gather status from the PHY. A set of management registers is defined to control chip behavior, link properties, auto-negotiation configuration, etc. This basic management functionality is addressed by :component_file:`esp_eth/src/phy/esp_eth_phy_802_3.c` in ESP-IDF and so it makes the creation of a new custom PHY chip driver quite a simple task. diff --git a/examples/common_components/protocol_examples_common/Kconfig.projbuild b/examples/common_components/protocol_examples_common/Kconfig.projbuild index 800f136a09c..a890bfbe07f 100644 --- a/examples/common_components/protocol_examples_common/Kconfig.projbuild +++ b/examples/common_components/protocol_examples_common/Kconfig.projbuild @@ -183,6 +183,15 @@ menu "Example Connection Configuration" help Select the Ethernet PHY device to use in the example. + config EXAMPLE_ETH_PHY_GENERIC + bool "Generic 802.3 PHY" + help + Any Ethernet PHY chip compliant with IEEE 802.3 can be used. However, while + basic functionality should always work, some specific features might be limited, + even if the PHY meets IEEE 802.3 standard. A typical example is loopback + functionality, where certain PHYs may require setting a specific speed mode to + operate correctly. + config EXAMPLE_ETH_PHY_IP101 bool "IP101" help diff --git a/examples/common_components/protocol_examples_common/eth_connect.c b/examples/common_components/protocol_examples_common/eth_connect.c index 8e89dbe28eb..86e856527c2 100644 --- a/examples/common_components/protocol_examples_common/eth_connect.c +++ b/examples/common_components/protocol_examples_common/eth_connect.c @@ -103,7 +103,9 @@ static esp_netif_t *eth_start(void) esp32_emac_config.smi_gpio.mdc_num = CONFIG_EXAMPLE_ETH_MDC_GPIO; esp32_emac_config.smi_gpio.mdio_num = CONFIG_EXAMPLE_ETH_MDIO_GPIO; s_mac = esp_eth_mac_new_esp32(&esp32_emac_config, &mac_config); -#if CONFIG_EXAMPLE_ETH_PHY_IP101 +#if CONFIG_EXAMPLE_ETH_PHY_GENERIC + s_phy = esp_eth_phy_new_generic(&phy_config); +#elif CONFIG_EXAMPLE_ETH_PHY_IP101 s_phy = esp_eth_phy_new_ip101(&phy_config); #elif CONFIG_EXAMPLE_ETH_PHY_RTL8201 s_phy = esp_eth_phy_new_rtl8201(&phy_config); diff --git a/examples/ethernet/basic/components/ethernet_init/Kconfig.projbuild b/examples/ethernet/basic/components/ethernet_init/Kconfig.projbuild index caca0c4211a..325908b5753 100644 --- a/examples/ethernet/basic/components/ethernet_init/Kconfig.projbuild +++ b/examples/ethernet/basic/components/ethernet_init/Kconfig.projbuild @@ -17,6 +17,15 @@ menu "Example Ethernet Configuration" help Select the Ethernet PHY device to use in the example. + config EXAMPLE_ETH_PHY_GENERIC + bool "Generic 802.3 PHY" + help + Any Ethernet PHY chip compliant with IEEE 802.3 can be used. However, while + basic functionality should always work, some specific features might be limited, + even if the PHY meets IEEE 802.3 standard. A typical example is loopback + functionality, where certain PHYs may require setting a specific speed mode to + operate correctly. + config EXAMPLE_ETH_PHY_IP101 bool "IP101" help diff --git a/examples/ethernet/basic/components/ethernet_init/ethernet_init.c b/examples/ethernet/basic/components/ethernet_init/ethernet_init.c index b34304e4a37..831e8cb2079 100644 --- a/examples/ethernet/basic/components/ethernet_init/ethernet_init.c +++ b/examples/ethernet/basic/components/ethernet_init/ethernet_init.c @@ -83,7 +83,9 @@ static esp_eth_handle_t eth_init_internal(esp_eth_mac_t **mac_out, esp_eth_phy_t // Create new ESP32 Ethernet MAC instance esp_eth_mac_t *mac = esp_eth_mac_new_esp32(&esp32_emac_config, &mac_config); // Create new PHY instance based on board configuration -#if CONFIG_EXAMPLE_ETH_PHY_IP101 +#if CONFIG_EXAMPLE_ETH_PHY_GENERIC + esp_eth_phy_t *phy = esp_eth_phy_new_generic(&phy_config); +#elif CONFIG_EXAMPLE_ETH_PHY_IP101 esp_eth_phy_t *phy = esp_eth_phy_new_ip101(&phy_config); #elif CONFIG_EXAMPLE_ETH_PHY_RTL8201 esp_eth_phy_t *phy = esp_eth_phy_new_rtl8201(&phy_config); diff --git a/examples/ethernet/basic/pytest_eth_basic.py b/examples/ethernet/basic/pytest_eth_basic.py index 44ce6db4af2..74c5a2ac63f 100644 --- a/examples/ethernet/basic/pytest_eth_basic.py +++ b/examples/ethernet/basic/pytest_eth_basic.py @@ -10,6 +10,7 @@ @pytest.mark.esp32 @pytest.mark.parametrize('config', [ pytest.param('default_ip101', marks=[pytest.mark.ethernet_router]), + pytest.param('default_generic', marks=[pytest.mark.ethernet_router]), pytest.param('default_dm9051', marks=[pytest.mark.eth_dm9051]), ], indirect=True) def test_esp_eth_basic( diff --git a/examples/ethernet/basic/sdkconfig.ci.default_generic b/examples/ethernet/basic/sdkconfig.ci.default_generic new file mode 100644 index 00000000000..dae839a7c87 --- /dev/null +++ b/examples/ethernet/basic/sdkconfig.ci.default_generic @@ -0,0 +1,11 @@ +CONFIG_EXAMPLE_USE_INTERNAL_ETHERNET=y +CONFIG_EXAMPLE_ETH_PHY_GENERIC=y +CONFIG_EXAMPLE_ETH_MDC_GPIO=23 +CONFIG_EXAMPLE_ETH_MDIO_GPIO=18 +CONFIG_EXAMPLE_ETH_PHY_RST_GPIO=5 +CONFIG_EXAMPLE_ETH_PHY_ADDR=1 + +CONFIG_ETH_ENABLED=y +CONFIG_ETH_USE_ESP32_EMAC=y +CONFIG_ETH_PHY_INTERFACE_RMII=y +CONFIG_ETH_RMII_CLK_INPUT=y From c079f30295f35f30b8a18490d4095b52c32e7b9b Mon Sep 17 00:00:00 2001 From: laokaiyao Date: Fri, 6 Sep 2024 16:36:02 +0800 Subject: [PATCH 114/472] refactor(soc): sort esp32c3 soc headers --- .../soc/esp32c3/include/soc/dport_access.h | 3 +- .../soc/esp32c3/include/soc/interrupt_reg.h | 2 +- components/soc/esp32c3/include/soc/soc.h | 2 +- components/soc/esp32c3/register/soc/.gitkeep | 0 .../{include => register}/soc/apb_ctrl_reg.h | 2 +- .../soc/apb_ctrl_struct.h | 0 .../soc/apb_saradc_reg.h | 20 ++++--------- .../soc/apb_saradc_struct.h | 0 .../soc/assist_debug_reg.h | 20 ++++--------- .../{include => register}/soc/efuse_reg.h | 4 +-- .../{include => register}/soc/efuse_struct.h | 2 +- .../{include => register}/soc/extmem_reg.h | 20 ++++--------- .../{include => register}/soc/gdma_reg.h | 0 .../{include => register}/soc/gdma_struct.h | 0 .../{include => register}/soc/gpio_reg.h | 20 ++++--------- .../{include => register}/soc/gpio_sd_reg.h | 2 +- .../soc/gpio_sd_struct.h | 0 .../{include => register}/soc/gpio_struct.h | 18 ++++------- .../{include => register}/soc/i2c_reg.h | 20 ++++--------- .../{include => register}/soc/i2c_struct.h | 2 +- .../{include => register}/soc/i2s_reg.h | 4 +-- .../{include => register}/soc/i2s_struct.h | 2 +- .../soc/interrupt_core0_reg.h | 20 ++++--------- .../{include => register}/soc/io_mux_reg.h | 2 +- .../{include => register}/soc/ledc_reg.h | 20 ++++--------- .../{include => register}/soc/ledc_struct.h | 0 .../{include => register}/soc/nrx_reg.h | 18 ++++------- .../{include => register}/soc/reg_base.h | 2 +- .../{include => register}/soc/rmt_reg.h | 2 +- .../{include => register}/soc/rmt_struct.h | 0 .../{include => register}/soc/rtc_cntl_reg.h | 12 ++++---- .../soc/rtc_cntl_struct.h | 10 +++---- .../{include => register}/soc/rtc_i2c_reg.h | 20 ++++--------- .../soc/rtc_i2c_struct.h | 0 .../{include => register}/soc/sensitive_reg.h | 20 ++++--------- .../soc/sensitive_struct.h | 20 ++++--------- .../{include => register}/soc/spi_mem_reg.h | 22 +++++--------- .../soc/spi_mem_struct.h | 2 +- .../{include => register}/soc/spi_reg.h | 18 +++++------ .../{include => register}/soc/spi_struct.h | 4 +-- .../{include => register}/soc/syscon_reg.h | 4 +-- .../{include => register}/soc/syscon_struct.h | 0 .../{include => register}/soc/system_reg.h | 2 +- .../{include => register}/soc/system_struct.h | 2 +- .../{include => register}/soc/systimer_reg.h | 15 ++-------- .../soc/systimer_struct.h | 15 ++-------- .../soc/timer_group_reg.h | 0 .../soc/timer_group_struct.h | 0 .../{include => register}/soc/twai_struct.h | 0 .../{include => register}/soc/uart_reg.h | 30 +++++++------------ .../{include => register}/soc/uart_struct.h | 10 +++---- .../{include => register}/soc/uhci_reg.h | 20 ++++--------- .../{include => register}/soc/uhci_struct.h | 0 .../soc/usb_serial_jtag_reg.h | 10 +++---- .../soc/usb_serial_jtag_struct.h | 20 ++++--------- .../{include => register}/soc/xts_aes_reg.h | 2 +- tools/ci/check_copyright_ignore.txt | 26 ---------------- 57 files changed, 159 insertions(+), 332 deletions(-) delete mode 100644 components/soc/esp32c3/register/soc/.gitkeep rename components/soc/esp32c3/{include => register}/soc/apb_ctrl_reg.h (99%) rename components/soc/esp32c3/{include => register}/soc/apb_ctrl_struct.h (100%) rename components/soc/esp32c3/{include => register}/soc/apb_saradc_reg.h (97%) rename components/soc/esp32c3/{include => register}/soc/apb_saradc_struct.h (100%) rename components/soc/esp32c3/{include => register}/soc/assist_debug_reg.h (98%) rename components/soc/esp32c3/{include => register}/soc/efuse_reg.h (99%) rename components/soc/esp32c3/{include => register}/soc/efuse_struct.h (99%) rename components/soc/esp32c3/{include => register}/soc/extmem_reg.h (98%) rename components/soc/esp32c3/{include => register}/soc/gdma_reg.h (100%) rename components/soc/esp32c3/{include => register}/soc/gdma_struct.h (100%) rename components/soc/esp32c3/{include => register}/soc/gpio_reg.h (99%) rename components/soc/esp32c3/{include => register}/soc/gpio_sd_reg.h (99%) rename components/soc/esp32c3/{include => register}/soc/gpio_sd_struct.h (100%) rename components/soc/esp32c3/{include => register}/soc/gpio_struct.h (94%) rename components/soc/esp32c3/{include => register}/soc/i2c_reg.h (98%) rename components/soc/esp32c3/{include => register}/soc/i2c_struct.h (99%) rename components/soc/esp32c3/{include => register}/soc/i2s_reg.h (99%) rename components/soc/esp32c3/{include => register}/soc/i2s_struct.h (99%) rename components/soc/esp32c3/{include => register}/soc/interrupt_core0_reg.h (98%) rename components/soc/esp32c3/{include => register}/soc/io_mux_reg.h (99%) rename components/soc/esp32c3/{include => register}/soc/ledc_reg.h (98%) rename components/soc/esp32c3/{include => register}/soc/ledc_struct.h (100%) rename components/soc/esp32c3/{include => register}/soc/nrx_reg.h (67%) rename components/soc/esp32c3/{include => register}/soc/reg_base.h (97%) rename components/soc/esp32c3/{include => register}/soc/rmt_reg.h (99%) rename components/soc/esp32c3/{include => register}/soc/rmt_struct.h (100%) rename components/soc/esp32c3/{include => register}/soc/rtc_cntl_reg.h (99%) rename components/soc/esp32c3/{include => register}/soc/rtc_cntl_struct.h (99%) rename components/soc/esp32c3/{include => register}/soc/rtc_i2c_reg.h (97%) rename components/soc/esp32c3/{include => register}/soc/rtc_i2c_struct.h (100%) rename components/soc/esp32c3/{include => register}/soc/sensitive_reg.h (99%) rename components/soc/esp32c3/{include => register}/soc/sensitive_struct.h (99%) rename components/soc/esp32c3/{include => register}/soc/spi_mem_reg.h (98%) rename components/soc/esp32c3/{include => register}/soc/spi_mem_struct.h (99%) rename components/soc/esp32c3/{include => register}/soc/spi_reg.h (99%) rename components/soc/esp32c3/{include => register}/soc/spi_struct.h (99%) rename components/soc/esp32c3/{include => register}/soc/syscon_reg.h (99%) rename components/soc/esp32c3/{include => register}/soc/syscon_struct.h (100%) rename components/soc/esp32c3/{include => register}/soc/system_reg.h (99%) rename components/soc/esp32c3/{include => register}/soc/system_struct.h (99%) rename components/soc/esp32c3/{include => register}/soc/systimer_reg.h (97%) rename components/soc/esp32c3/{include => register}/soc/systimer_struct.h (94%) rename components/soc/esp32c3/{include => register}/soc/timer_group_reg.h (100%) rename components/soc/esp32c3/{include => register}/soc/timer_group_struct.h (100%) rename components/soc/esp32c3/{include => register}/soc/twai_struct.h (100%) rename components/soc/esp32c3/{include => register}/soc/uart_reg.h (98%) rename components/soc/esp32c3/{include => register}/soc/uart_struct.h (98%) rename components/soc/esp32c3/{include => register}/soc/uhci_reg.h (97%) rename components/soc/esp32c3/{include => register}/soc/uhci_struct.h (100%) rename components/soc/esp32c3/{include => register}/soc/usb_serial_jtag_reg.h (99%) rename components/soc/esp32c3/{include => register}/soc/usb_serial_jtag_struct.h (96%) rename components/soc/esp32c3/{include => register}/soc/xts_aes_reg.h (98%) diff --git a/components/soc/esp32c3/include/soc/dport_access.h b/components/soc/esp32c3/include/soc/dport_access.h index 5a847ca4842..e499a791bdd 100644 --- a/components/soc/esp32c3/include/soc/dport_access.h +++ b/components/soc/esp32c3/include/soc/dport_access.h @@ -8,8 +8,7 @@ #define _DPORT_ACCESS_H_ #include -#include "soc.h" -#include "uart_reg.h" +#include "soc/soc.h" #ifdef __cplusplus extern "C" { diff --git a/components/soc/esp32c3/include/soc/interrupt_reg.h b/components/soc/esp32c3/include/soc/interrupt_reg.h index 749a2e92167..d02c2d5c20c 100644 --- a/components/soc/esp32c3/include/soc/interrupt_reg.h +++ b/components/soc/esp32c3/include/soc/interrupt_reg.h @@ -5,7 +5,7 @@ */ #pragma once -#include "interrupt_core0_reg.h" +#include "soc/interrupt_core0_reg.h" #define INTERRUPT_CURRENT_CORE_INT_THRESH_REG INTERRUPT_CORE0_CPU_INT_THRESH_REG #define INTERRUPT_PRIO_REG(n) (INTERRUPT_CORE0_CPU_INT_PRI_0_REG + (n)*4) diff --git a/components/soc/esp32c3/include/soc/soc.h b/components/soc/esp32c3/include/soc/soc.h index d661c4eb126..1b47dd70fb1 100644 --- a/components/soc/esp32c3/include/soc/soc.h +++ b/components/soc/esp32c3/include/soc/soc.h @@ -12,7 +12,7 @@ #endif #include "esp_bit_defs.h" -#include "reg_base.h" +#include "soc/reg_base.h" #define PRO_CPU_NUM (0) diff --git a/components/soc/esp32c3/register/soc/.gitkeep b/components/soc/esp32c3/register/soc/.gitkeep deleted file mode 100644 index e69de29bb2d..00000000000 diff --git a/components/soc/esp32c3/include/soc/apb_ctrl_reg.h b/components/soc/esp32c3/register/soc/apb_ctrl_reg.h similarity index 99% rename from components/soc/esp32c3/include/soc/apb_ctrl_reg.h rename to components/soc/esp32c3/register/soc/apb_ctrl_reg.h index cb1966505e8..f7fb4f1ba97 100644 --- a/components/soc/esp32c3/include/soc/apb_ctrl_reg.h +++ b/components/soc/esp32c3/register/soc/apb_ctrl_reg.h @@ -11,7 +11,7 @@ #ifdef __cplusplus extern "C" { #endif -#include "soc.h" +#include "soc/soc.h" #define APB_CTRL_SYSCLK_CONF_REG (DR_REG_APB_CTRL_BASE + 0x000) /* APB_CTRL_RST_TICK_CNT : R/W ;bitpos:[12] ;default: 1'b0 ; */ /*description: */ diff --git a/components/soc/esp32c3/include/soc/apb_ctrl_struct.h b/components/soc/esp32c3/register/soc/apb_ctrl_struct.h similarity index 100% rename from components/soc/esp32c3/include/soc/apb_ctrl_struct.h rename to components/soc/esp32c3/register/soc/apb_ctrl_struct.h diff --git a/components/soc/esp32c3/include/soc/apb_saradc_reg.h b/components/soc/esp32c3/register/soc/apb_saradc_reg.h similarity index 97% rename from components/soc/esp32c3/include/soc/apb_saradc_reg.h rename to components/soc/esp32c3/register/soc/apb_saradc_reg.h index 69785ca84da..87deea2d3e9 100644 --- a/components/soc/esp32c3/include/soc/apb_saradc_reg.h +++ b/components/soc/esp32c3/register/soc/apb_saradc_reg.h @@ -1,16 +1,8 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef _SOC_APB_SARADC_REG_H_ #define _SOC_APB_SARADC_REG_H_ @@ -18,7 +10,7 @@ #ifdef __cplusplus extern "C" { #endif -#include "soc.h" +#include "soc/soc.h" #define APB_SARADC_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x000) /* APB_SARADC_WAIT_ARB_CYCLE : R/W ;bitpos:[31:30] ;default: 2'd1 ; */ /*description: wait arbit signal stable after sar_done*/ diff --git a/components/soc/esp32c3/include/soc/apb_saradc_struct.h b/components/soc/esp32c3/register/soc/apb_saradc_struct.h similarity index 100% rename from components/soc/esp32c3/include/soc/apb_saradc_struct.h rename to components/soc/esp32c3/register/soc/apb_saradc_struct.h diff --git a/components/soc/esp32c3/include/soc/assist_debug_reg.h b/components/soc/esp32c3/register/soc/assist_debug_reg.h similarity index 98% rename from components/soc/esp32c3/include/soc/assist_debug_reg.h rename to components/soc/esp32c3/register/soc/assist_debug_reg.h index 2b13d1f5f41..615964bd740 100644 --- a/components/soc/esp32c3/include/soc/assist_debug_reg.h +++ b/components/soc/esp32c3/register/soc/assist_debug_reg.h @@ -1,16 +1,8 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef _SOC_ASSIST_DEBUG_REG_H_ #define _SOC_ASSIST_DEBUG_REG_H_ @@ -18,7 +10,7 @@ #ifdef __cplusplus extern "C" { #endif -#include "soc.h" +#include "soc/soc.h" #define ASSIST_DEBUG_CORE_0_INTR_ENA_REG (DR_REG_ASSIST_DEBUG_BASE + 0x000) /* ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ /*description: */ diff --git a/components/soc/esp32c3/include/soc/efuse_reg.h b/components/soc/esp32c3/register/soc/efuse_reg.h similarity index 99% rename from components/soc/esp32c3/include/soc/efuse_reg.h rename to components/soc/esp32c3/register/soc/efuse_reg.h index 4d6781c976b..39db7b9abb4 100644 --- a/components/soc/esp32c3/include/soc/efuse_reg.h +++ b/components/soc/esp32c3/register/soc/efuse_reg.h @@ -7,7 +7,7 @@ #include #include "soc/soc.h" -#include "efuse_defs.h" +#include "soc/efuse_defs.h" #ifdef __cplusplus extern "C" { #endif @@ -2376,7 +2376,7 @@ extern "C" { #define EFUSE_CLK_EN_S 16 /** EFUSE_CONF_REG register - * eFuse operation mode configuraiton register; + * eFuse operation mode configuration register; */ #define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x1cc) /** EFUSE_OP_CODE : R/W; bitpos: [15:0]; default: 0; diff --git a/components/soc/esp32c3/include/soc/efuse_struct.h b/components/soc/esp32c3/register/soc/efuse_struct.h similarity index 99% rename from components/soc/esp32c3/include/soc/efuse_struct.h rename to components/soc/esp32c3/register/soc/efuse_struct.h index 99f8c39ec57..f12563cebd0 100644 --- a/components/soc/esp32c3/include/soc/efuse_struct.h +++ b/components/soc/esp32c3/register/soc/efuse_struct.h @@ -2015,7 +2015,7 @@ typedef union { } efuse_clk_reg_t; /** Type of conf register - * eFuse operation mode configuraiton register; + * eFuse operation mode configuration register; */ typedef union { struct { diff --git a/components/soc/esp32c3/include/soc/extmem_reg.h b/components/soc/esp32c3/register/soc/extmem_reg.h similarity index 98% rename from components/soc/esp32c3/include/soc/extmem_reg.h rename to components/soc/esp32c3/register/soc/extmem_reg.h index 71ab60f6400..7a94ea7e66b 100644 --- a/components/soc/esp32c3/include/soc/extmem_reg.h +++ b/components/soc/esp32c3/register/soc/extmem_reg.h @@ -1,16 +1,8 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef _SOC_EXTMEM_REG_H_ #define _SOC_EXTMEM_REG_H_ @@ -18,7 +10,7 @@ #ifdef __cplusplus extern "C" { #endif -#include "soc.h" +#include "soc/soc.h" #define EXTMEM_ICACHE_CTRL_REG (DR_REG_EXTMEM_BASE + 0x000) /* EXTMEM_ICACHE_ENABLE : R/W ;bitpos:[0] ;default: 1'b0 ; */ /*description: The bit is used to activate the data cache. 0: disable 1: enable*/ diff --git a/components/soc/esp32c3/include/soc/gdma_reg.h b/components/soc/esp32c3/register/soc/gdma_reg.h similarity index 100% rename from components/soc/esp32c3/include/soc/gdma_reg.h rename to components/soc/esp32c3/register/soc/gdma_reg.h diff --git a/components/soc/esp32c3/include/soc/gdma_struct.h b/components/soc/esp32c3/register/soc/gdma_struct.h similarity index 100% rename from components/soc/esp32c3/include/soc/gdma_struct.h rename to components/soc/esp32c3/register/soc/gdma_struct.h diff --git a/components/soc/esp32c3/include/soc/gpio_reg.h b/components/soc/esp32c3/register/soc/gpio_reg.h similarity index 99% rename from components/soc/esp32c3/include/soc/gpio_reg.h rename to components/soc/esp32c3/register/soc/gpio_reg.h index a674277f994..b92e195e36d 100644 --- a/components/soc/esp32c3/include/soc/gpio_reg.h +++ b/components/soc/esp32c3/register/soc/gpio_reg.h @@ -1,16 +1,8 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef _SOC_GPIO_REG_H_ #define _SOC_GPIO_REG_H_ @@ -18,7 +10,7 @@ #ifdef __cplusplus extern "C" { #endif -#include "soc.h" +#include "soc/soc.h" #define GPIO_PIN_CONFIG_MSB 12 #define GPIO_PIN_CONFIG_LSB 11 #define GPIO_PIN_CONFIG_MASK 0x00001800 diff --git a/components/soc/esp32c3/include/soc/gpio_sd_reg.h b/components/soc/esp32c3/register/soc/gpio_sd_reg.h similarity index 99% rename from components/soc/esp32c3/include/soc/gpio_sd_reg.h rename to components/soc/esp32c3/register/soc/gpio_sd_reg.h index 3c72df5d404..57d66a44c0c 100644 --- a/components/soc/esp32c3/include/soc/gpio_sd_reg.h +++ b/components/soc/esp32c3/register/soc/gpio_sd_reg.h @@ -6,7 +6,7 @@ #pragma once -#include "soc.h" +#include "soc/soc.h" #ifdef __cplusplus extern "C" { diff --git a/components/soc/esp32c3/include/soc/gpio_sd_struct.h b/components/soc/esp32c3/register/soc/gpio_sd_struct.h similarity index 100% rename from components/soc/esp32c3/include/soc/gpio_sd_struct.h rename to components/soc/esp32c3/register/soc/gpio_sd_struct.h diff --git a/components/soc/esp32c3/include/soc/gpio_struct.h b/components/soc/esp32c3/register/soc/gpio_struct.h similarity index 94% rename from components/soc/esp32c3/include/soc/gpio_struct.h rename to components/soc/esp32c3/register/soc/gpio_struct.h index 45f5e55412c..1fbb0779b47 100644 --- a/components/soc/esp32c3/include/soc/gpio_struct.h +++ b/components/soc/esp32c3/register/soc/gpio_struct.h @@ -1,16 +1,8 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef _SOC_GPIO_STRUCT_H_ #define _SOC_GPIO_STRUCT_H_ #include diff --git a/components/soc/esp32c3/include/soc/i2c_reg.h b/components/soc/esp32c3/register/soc/i2c_reg.h similarity index 98% rename from components/soc/esp32c3/include/soc/i2c_reg.h rename to components/soc/esp32c3/register/soc/i2c_reg.h index 6a45d008276..03ec35dad0f 100644 --- a/components/soc/esp32c3/include/soc/i2c_reg.h +++ b/components/soc/esp32c3/register/soc/i2c_reg.h @@ -1,16 +1,8 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef _SOC_I2C_REG_H_ #define _SOC_I2C_REG_H_ @@ -18,7 +10,7 @@ #ifdef __cplusplus extern "C" { #endif -#include "soc.h" +#include "soc/soc.h" #define I2C_SCL_LOW_PERIOD_REG(i) (REG_I2C_BASE(i) + 0x0) /* I2C_SCL_LOW_PERIOD : R/W ;bitpos:[8:0] ;default: 9'b0 ; */ diff --git a/components/soc/esp32c3/include/soc/i2c_struct.h b/components/soc/esp32c3/register/soc/i2c_struct.h similarity index 99% rename from components/soc/esp32c3/include/soc/i2c_struct.h rename to components/soc/esp32c3/register/soc/i2c_struct.h index 1009fedd6e0..eb32d5a9cf9 100644 --- a/components/soc/esp32c3/include/soc/i2c_struct.h +++ b/components/soc/esp32c3/register/soc/i2c_struct.h @@ -10,7 +10,7 @@ #ifdef __cplusplus extern "C" { #endif -#include "soc.h" +#include "soc/soc.h" typedef volatile struct i2c_dev_s { union { diff --git a/components/soc/esp32c3/include/soc/i2s_reg.h b/components/soc/esp32c3/register/soc/i2s_reg.h similarity index 99% rename from components/soc/esp32c3/include/soc/i2s_reg.h rename to components/soc/esp32c3/register/soc/i2s_reg.h index 2b3ed91f610..7412fe1a13d 100644 --- a/components/soc/esp32c3/include/soc/i2s_reg.h +++ b/components/soc/esp32c3/register/soc/i2s_reg.h @@ -10,7 +10,7 @@ #ifdef __cplusplus extern "C" { #endif -#include "soc.h" +#include "soc/soc.h" #define I2S_INT_RAW_REG(i) (REG_I2S_BASE(i) + 0x000c) /* I2S_TX_HUNG_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ /*description: The raw interrupt status bit for the i2s_tx_hung_int interrupt*/ @@ -280,7 +280,7 @@ extern "C" { #define I2S_TX_LEFT_ALIGN_S 15 /* I2S_TX_STOP_EN : R/W ;bitpos:[13] ;default: 1'h1 ; */ /*description: Set this bit to stop disable output BCK signal and WS signal - when tx FIFO is emtpy*/ + when tx FIFO is empty*/ #define I2S_TX_STOP_EN (BIT(13)) #define I2S_TX_STOP_EN_M (BIT(13)) #define I2S_TX_STOP_EN_V 0x1 diff --git a/components/soc/esp32c3/include/soc/i2s_struct.h b/components/soc/esp32c3/register/soc/i2s_struct.h similarity index 99% rename from components/soc/esp32c3/include/soc/i2s_struct.h rename to components/soc/esp32c3/register/soc/i2s_struct.h index e0c10e91e97..29093ad2d97 100644 --- a/components/soc/esp32c3/include/soc/i2s_struct.h +++ b/components/soc/esp32c3/register/soc/i2s_struct.h @@ -95,7 +95,7 @@ typedef volatile struct i2s_dev_s { uint32_t tx_mono_fst_vld: 1; /*1: The first channel data value is valid in I2S TX mono mode. 0: The second channel data value is valid in I2S TX mono mode.*/ uint32_t tx_pcm_conf: 2; /*I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress 1 (ltoa) : A-Law compress 2 (utol) : u-Law decompress 3 (ltou) : u-Law compress. &*/ uint32_t tx_pcm_bypass: 1; /*Set this bit to bypass Compress/Decompress module for transmitted data.*/ - uint32_t tx_stop_en: 1; /*Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy*/ + uint32_t tx_stop_en: 1; /*Set this bit to stop disable output BCK signal and WS signal when tx FIFO is empty*/ uint32_t reserved14: 1; uint32_t tx_left_align: 1; /*1: I2S TX left alignment mode. 0: I2S TX right alignment mode.*/ uint32_t tx_24_fill_en: 1; /*1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode*/ diff --git a/components/soc/esp32c3/include/soc/interrupt_core0_reg.h b/components/soc/esp32c3/register/soc/interrupt_core0_reg.h similarity index 98% rename from components/soc/esp32c3/include/soc/interrupt_core0_reg.h rename to components/soc/esp32c3/register/soc/interrupt_core0_reg.h index f606cdafcaf..f587f5c73c1 100644 --- a/components/soc/esp32c3/include/soc/interrupt_core0_reg.h +++ b/components/soc/esp32c3/register/soc/interrupt_core0_reg.h @@ -1,16 +1,8 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef _SOC_INTERRUPT_CORE0_REG_H_ #define _SOC_INTERRUPT_CORE0_REG_H_ @@ -18,7 +10,7 @@ #ifdef __cplusplus extern "C" { #endif -#include "soc.h" +#include "soc/soc.h" #define DR_REG_INTERRUPT_CORE0_BASE DR_REG_INTERRUPT_BASE diff --git a/components/soc/esp32c3/include/soc/io_mux_reg.h b/components/soc/esp32c3/register/soc/io_mux_reg.h similarity index 99% rename from components/soc/esp32c3/include/soc/io_mux_reg.h rename to components/soc/esp32c3/register/soc/io_mux_reg.h index f5abe8ee5e8..a85a3434dd0 100644 --- a/components/soc/esp32c3/include/soc/io_mux_reg.h +++ b/components/soc/esp32c3/register/soc/io_mux_reg.h @@ -6,7 +6,7 @@ #ifndef _SOC_IO_MUX_REG_H_ #define _SOC_IO_MUX_REG_H_ -#include "soc.h" +#include "soc/soc.h" /* The following are the bit fields for PERIPHS_IO_MUX_x_U registers */ /* Output enable in sleep mode */ diff --git a/components/soc/esp32c3/include/soc/ledc_reg.h b/components/soc/esp32c3/register/soc/ledc_reg.h similarity index 98% rename from components/soc/esp32c3/include/soc/ledc_reg.h rename to components/soc/esp32c3/register/soc/ledc_reg.h index 0cc9334130b..c956e9e7dad 100644 --- a/components/soc/esp32c3/include/soc/ledc_reg.h +++ b/components/soc/esp32c3/register/soc/ledc_reg.h @@ -1,16 +1,8 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef _SOC_LEDC_REG_H_ #define _SOC_LEDC_REG_H_ @@ -18,7 +10,7 @@ #ifdef __cplusplus extern "C" { #endif -#include "soc.h" +#include "soc/soc.h" #define LEDC_LSCH0_CONF0_REG (DR_REG_LEDC_BASE + 0x0000) /* LEDC_OVF_CNT_RESET_LSCH0 : WO ;bitpos:[16] ;default: 1'b0 ; */ /*description: */ diff --git a/components/soc/esp32c3/include/soc/ledc_struct.h b/components/soc/esp32c3/register/soc/ledc_struct.h similarity index 100% rename from components/soc/esp32c3/include/soc/ledc_struct.h rename to components/soc/esp32c3/register/soc/ledc_struct.h diff --git a/components/soc/esp32c3/include/soc/nrx_reg.h b/components/soc/esp32c3/register/soc/nrx_reg.h similarity index 67% rename from components/soc/esp32c3/include/soc/nrx_reg.h rename to components/soc/esp32c3/register/soc/nrx_reg.h index d80cb2a1785..16e6e148497 100644 --- a/components/soc/esp32c3/include/soc/nrx_reg.h +++ b/components/soc/esp32c3/register/soc/nrx_reg.h @@ -1,16 +1,8 @@ -// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #pragma once diff --git a/components/soc/esp32c3/include/soc/reg_base.h b/components/soc/esp32c3/register/soc/reg_base.h similarity index 97% rename from components/soc/esp32c3/include/soc/reg_base.h rename to components/soc/esp32c3/register/soc/reg_base.h index 4ec808f0ab9..cf38bd9dbda 100644 --- a/components/soc/esp32c3/include/soc/reg_base.h +++ b/components/soc/esp32c3/register/soc/reg_base.h @@ -46,5 +46,5 @@ #define DR_REG_USB_SERIAL_JTAG_BASE 0x60043000 #define DR_REG_XTS_AES_BASE 0x600CC000 -/* For backward compatability with the older register names */ +/* For backward compatibility with the older register names */ #define DR_REG_AES_XTS_BASE DR_REG_XTS_AES_BASE diff --git a/components/soc/esp32c3/include/soc/rmt_reg.h b/components/soc/esp32c3/register/soc/rmt_reg.h similarity index 99% rename from components/soc/esp32c3/include/soc/rmt_reg.h rename to components/soc/esp32c3/register/soc/rmt_reg.h index 106fc786495..1ac39c2af35 100644 --- a/components/soc/esp32c3/include/soc/rmt_reg.h +++ b/components/soc/esp32c3/register/soc/rmt_reg.h @@ -5,7 +5,7 @@ */ #pragma once -#include "soc.h" +#include "soc/soc.h" #ifdef __cplusplus extern "C" { diff --git a/components/soc/esp32c3/include/soc/rmt_struct.h b/components/soc/esp32c3/register/soc/rmt_struct.h similarity index 100% rename from components/soc/esp32c3/include/soc/rmt_struct.h rename to components/soc/esp32c3/register/soc/rmt_struct.h diff --git a/components/soc/esp32c3/include/soc/rtc_cntl_reg.h b/components/soc/esp32c3/register/soc/rtc_cntl_reg.h similarity index 99% rename from components/soc/esp32c3/include/soc/rtc_cntl_reg.h rename to components/soc/esp32c3/register/soc/rtc_cntl_reg.h index 433ca196b3c..e67f6ed93d8 100644 --- a/components/soc/esp32c3/include/soc/rtc_cntl_reg.h +++ b/components/soc/esp32c3/register/soc/rtc_cntl_reg.h @@ -9,7 +9,7 @@ #ifdef __cplusplus extern "C" { #endif -#include "soc.h" +#include "soc/soc.h" #define RTC_CNTL_TIME0_REG RTC_CNTL_TIME_LOW0_REG #define RTC_CNTL_TIME1_REG RTC_CNTL_TIME_HIGH0_REG @@ -567,7 +567,7 @@ extern "C" { #define RTC_CNTL_BBPLL_CAL_INT_ENA_V 0x1 #define RTC_CNTL_BBPLL_CAL_INT_ENA_S 20 /* RTC_CNTL_GLITCH_DET_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */ -/*description: enbale gitch det interrupt*/ +/*description: enable gitch det interrupt*/ #define RTC_CNTL_GLITCH_DET_INT_ENA (BIT(19)) #define RTC_CNTL_GLITCH_DET_INT_ENA_M (BIT(19)) #define RTC_CNTL_GLITCH_DET_INT_ENA_V 0x1 @@ -1712,7 +1712,7 @@ extern "C" { #define RTC_CNTL_SWD_AUTO_FEED_EN_V 0x1 #define RTC_CNTL_SWD_AUTO_FEED_EN_S 31 /* RTC_CNTL_SWD_DISABLE : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: disabel SWD*/ +/*description: disable SWD*/ #define RTC_CNTL_SWD_DISABLE (BIT(30)) #define RTC_CNTL_SWD_DISABLE_M (BIT(30)) #define RTC_CNTL_SWD_DISABLE_V 0x1 @@ -2138,7 +2138,7 @@ extern "C" { #define RTC_CNTL_XTAL32K_RESTART_WAIT_V 0xFFFF #define RTC_CNTL_XTAL32K_RESTART_WAIT_S 4 /* RTC_CNTL_XTAL32K_RETURN_WAIT : R/W ;bitpos:[3:0] ;default: 4'h0 ; */ -/*description: cycles to wait to return noral xtal 32k*/ +/*description: cycles to wait to return normal xtal 32k*/ #define RTC_CNTL_XTAL32K_RETURN_WAIT 0x0000000F #define RTC_CNTL_XTAL32K_RETURN_WAIT_M ((RTC_CNTL_XTAL32K_RETURN_WAIT_V)<<(RTC_CNTL_XTAL32K_RETURN_WAIT_S)) #define RTC_CNTL_XTAL32K_RETURN_WAIT_V 0xF @@ -2192,7 +2192,7 @@ extern "C" { #define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TS_V 0x1 #define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TS_S 20 /* RTC_CNTL_GLITCH_DET_INT_ENA_W1TS : WO ;bitpos:[19] ;default: 1'b0 ; */ -/*description: enbale gitch det interrupt*/ +/*description: enable gitch det interrupt*/ #define RTC_CNTL_GLITCH_DET_INT_ENA_W1TS (BIT(19)) #define RTC_CNTL_GLITCH_DET_INT_ENA_W1TS_M (BIT(19)) #define RTC_CNTL_GLITCH_DET_INT_ENA_W1TS_V 0x1 @@ -2248,7 +2248,7 @@ extern "C" { #define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TC_V 0x1 #define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TC_S 20 /* RTC_CNTL_GLITCH_DET_INT_ENA_W1TC : WO ;bitpos:[19] ;default: 1'b0 ; */ -/*description: enbale gitch det interrupt*/ +/*description: enable gitch det interrupt*/ #define RTC_CNTL_GLITCH_DET_INT_ENA_W1TC (BIT(19)) #define RTC_CNTL_GLITCH_DET_INT_ENA_W1TC_M (BIT(19)) #define RTC_CNTL_GLITCH_DET_INT_ENA_W1TC_V 0x1 diff --git a/components/soc/esp32c3/include/soc/rtc_cntl_struct.h b/components/soc/esp32c3/register/soc/rtc_cntl_struct.h similarity index 99% rename from components/soc/esp32c3/include/soc/rtc_cntl_struct.h rename to components/soc/esp32c3/register/soc/rtc_cntl_struct.h index 8b6bd3ad509..5c57701f695 100644 --- a/components/soc/esp32c3/include/soc/rtc_cntl_struct.h +++ b/components/soc/esp32c3/register/soc/rtc_cntl_struct.h @@ -195,7 +195,7 @@ typedef volatile struct rtc_cntl_dev_s { uint32_t rtc_swd: 1; /*enable super watch dog interrupt*/ uint32_t rtc_xtal32k_dead: 1; /*enable xtal32k_dead interrupt*/ uint32_t reserved17: 2; /*enable touch timeout interrupt*/ - uint32_t rtc_glitch_det: 1; /*enbale gitch det interrupt*/ + uint32_t rtc_glitch_det: 1; /*enable gitch det interrupt*/ uint32_t rtc_bbpll_cal: 1; uint32_t reserved21: 11; }; @@ -498,7 +498,7 @@ typedef volatile struct rtc_cntl_dev_s { uint32_t swd_signal_width:10; /*adjust signal width send to swd*/ uint32_t swd_rst_flag_clr: 1; /*reset swd reset flag*/ uint32_t swd_feed: 1; /*Sw feed swd*/ - uint32_t swd_disable: 1; /*disabel SWD*/ + uint32_t swd_disable: 1; /*disable SWD*/ uint32_t swd_auto_feed_en: 1; /*automatically feed swd when int comes*/ }; uint32_t val; @@ -591,7 +591,7 @@ typedef volatile struct rtc_cntl_dev_s { uint32_t xtal32k_clk_factor; /*xtal 32k watch dog backup clock factor*/ union { struct { - uint32_t xtal32k_return_wait: 4; /*cycles to wait to return noral xtal 32k*/ + uint32_t xtal32k_return_wait: 4; /*cycles to wait to return normal xtal 32k*/ uint32_t xtal32k_restart_wait:16; /*cycles to wait to repower on xtal 32k*/ uint32_t xtal32k_wdt_timeout: 8; /*If no clock detected for this amount of time*/ uint32_t xtal32k_stable_thres: 4; /*if restarted xtal32k period is smaller than this*/ @@ -647,7 +647,7 @@ typedef volatile struct rtc_cntl_dev_s { uint32_t rtc_swd_w1ts: 1; /*enable super watch dog interrupt*/ uint32_t rtc_xtal32k_dead_w1ts: 1; /*enable xtal32k_dead interrupt*/ uint32_t reserved17: 2; - uint32_t rtc_glitch_det_w1ts: 1; /*enbale gitch det interrupt*/ + uint32_t rtc_glitch_det_w1ts: 1; /*enable gitch det interrupt*/ uint32_t rtc_bbpll_cal_w1ts: 1; uint32_t reserved21: 11; }; @@ -666,7 +666,7 @@ typedef volatile struct rtc_cntl_dev_s { uint32_t rtc_swd_w1tc: 1; /*enable super watch dog interrupt*/ uint32_t rtc_xtal32k_dead_w1tc: 1; /*enable xtal32k_dead interrupt*/ uint32_t reserved17: 2; - uint32_t rtc_glitch_det_w1tc: 1; /*enbale gitch det interrupt*/ + uint32_t rtc_glitch_det_w1tc: 1; /*enable gitch det interrupt*/ uint32_t rtc_bbpll_cal_w1tc: 1; uint32_t reserved21: 11; }; diff --git a/components/soc/esp32c3/include/soc/rtc_i2c_reg.h b/components/soc/esp32c3/register/soc/rtc_i2c_reg.h similarity index 97% rename from components/soc/esp32c3/include/soc/rtc_i2c_reg.h rename to components/soc/esp32c3/register/soc/rtc_i2c_reg.h index 52bdefc0e56..eba7d42df63 100644 --- a/components/soc/esp32c3/include/soc/rtc_i2c_reg.h +++ b/components/soc/esp32c3/register/soc/rtc_i2c_reg.h @@ -1,16 +1,8 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef _SOC_RTC_I2C_REG_H_ #define _SOC_RTC_I2C_REG_H_ @@ -18,7 +10,7 @@ #ifdef __cplusplus extern "C" { #endif -#include "soc.h" +#include "soc/soc.h" #define RTC_I2C_SCL_LOW_PERIOD_REG (DR_REG_RTC_I2C_BASE + 0x0000) /* RTC_I2C_SCL_LOW_PERIOD : R/W ;bitpos:[19:0] ;default: 20'h100 ; */ /*description: time period that scl = 0*/ diff --git a/components/soc/esp32c3/include/soc/rtc_i2c_struct.h b/components/soc/esp32c3/register/soc/rtc_i2c_struct.h similarity index 100% rename from components/soc/esp32c3/include/soc/rtc_i2c_struct.h rename to components/soc/esp32c3/register/soc/rtc_i2c_struct.h diff --git a/components/soc/esp32c3/include/soc/sensitive_reg.h b/components/soc/esp32c3/register/soc/sensitive_reg.h similarity index 99% rename from components/soc/esp32c3/include/soc/sensitive_reg.h rename to components/soc/esp32c3/register/soc/sensitive_reg.h index e1ce7d93ef7..18fcf2e8db9 100644 --- a/components/soc/esp32c3/include/soc/sensitive_reg.h +++ b/components/soc/esp32c3/register/soc/sensitive_reg.h @@ -1,16 +1,8 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef _SOC_SENSITIVE_REG_H_ #define _SOC_SENSITIVE_REG_H_ @@ -18,7 +10,7 @@ #ifdef __cplusplus extern "C" { #endif -#include "soc.h" +#include "soc/soc.h" #define SENSITIVE_ROM_TABLE_LOCK_REG (DR_REG_SENSITIVE_BASE + 0x000) /* SENSITIVE_ROM_TABLE_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ /*description: */ diff --git a/components/soc/esp32c3/include/soc/sensitive_struct.h b/components/soc/esp32c3/register/soc/sensitive_struct.h similarity index 99% rename from components/soc/esp32c3/include/soc/sensitive_struct.h rename to components/soc/esp32c3/register/soc/sensitive_struct.h index ba860e45cd7..d71d81fc4dc 100644 --- a/components/soc/esp32c3/include/soc/sensitive_struct.h +++ b/components/soc/esp32c3/register/soc/sensitive_struct.h @@ -1,16 +1,8 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef _SOC_SENSITIVE_STRUCT_H_ #define _SOC_SENSITIVE_STRUCT_H_ @@ -18,7 +10,7 @@ #ifdef __cplusplus extern "C" { #endif -#include "soc.h" +#include "soc/soc.h" typedef volatile struct sensitive_dev_s { union { diff --git a/components/soc/esp32c3/include/soc/spi_mem_reg.h b/components/soc/esp32c3/register/soc/spi_mem_reg.h similarity index 98% rename from components/soc/esp32c3/include/soc/spi_mem_reg.h rename to components/soc/esp32c3/register/soc/spi_mem_reg.h index fcf3e292481..22d6b26377e 100644 --- a/components/soc/esp32c3/include/soc/spi_mem_reg.h +++ b/components/soc/esp32c3/register/soc/spi_mem_reg.h @@ -1,16 +1,8 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef _SOC_SPI_MEM_REG_H_ #define _SOC_SPI_MEM_REG_H_ @@ -18,7 +10,7 @@ #ifdef __cplusplus extern "C" { #endif -#include "soc.h" +#include "soc/soc.h" #define SPI_MEM_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0x000) /* SPI_MEM_FLASH_READ : R/W/SC ;bitpos:[31] ;default: 1'b0 ; */ /*description: Read flash enable. Read flash operation will be triggered when @@ -270,7 +262,7 @@ extern "C" { #define SPI_MEM_CS_HOLD_DLY_RES_S 2 /* SPI_MEM_CLK_MODE : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ /*description: SPI clock mode bits. 0: SPI clock is off when CS inactive 1: - SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on.*/ + SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is always on.*/ #define SPI_MEM_CLK_MODE 0x00000003 #define SPI_MEM_CLK_MODE_M ((SPI_MEM_CLK_MODE_V)<<(SPI_MEM_CLK_MODE_S)) #define SPI_MEM_CLK_MODE_V 0x3 diff --git a/components/soc/esp32c3/include/soc/spi_mem_struct.h b/components/soc/esp32c3/register/soc/spi_mem_struct.h similarity index 99% rename from components/soc/esp32c3/include/soc/spi_mem_struct.h rename to components/soc/esp32c3/register/soc/spi_mem_struct.h index d816a9a290a..95a0aae1ecf 100644 --- a/components/soc/esp32c3/include/soc/spi_mem_struct.h +++ b/components/soc/esp32c3/register/soc/spi_mem_struct.h @@ -63,7 +63,7 @@ typedef volatile struct spi_mem_dev_s { } ctrl; union { struct { - uint32_t clk_mode: 2; /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on.*/ + uint32_t clk_mode: 2; /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is always on.*/ uint32_t cs_hold_dly_res: 10; /*After RES/DP/HPM command is sent SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 512) SPI_CLK cycles.*/ uint32_t reserved2: 18; /*reserved*/ uint32_t rxfifo_rst: 1; /*SPI0 RX FIFO reset signal.*/ diff --git a/components/soc/esp32c3/include/soc/spi_reg.h b/components/soc/esp32c3/register/soc/spi_reg.h similarity index 99% rename from components/soc/esp32c3/include/soc/spi_reg.h rename to components/soc/esp32c3/register/soc/spi_reg.h index 361f58ba5c5..e8e9fec283f 100644 --- a/components/soc/esp32c3/include/soc/spi_reg.h +++ b/components/soc/esp32c3/register/soc/spi_reg.h @@ -6,7 +6,7 @@ #ifndef _SOC_SPI_REG_H_ #define _SOC_SPI_REG_H_ -#include "soc.h" +#include "soc/soc.h" #ifdef __cplusplus extern "C" { @@ -138,7 +138,7 @@ be configured in CONF state..*/ #define SPI_CLOCK_REG(i) (REG_SPI_BASE(i) + 0xC) /* SPI_CLK_EQU_SYSCLK : R/W ;bitpos:[31] ;default: 1'b1 ; */ -/*description: In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from syst +/*description: In the master mode 1: spi_clk is equal to system 0: spi_clk is divided from syst em clock. Can be configured in CONF state..*/ #define SPI_CLK_EQU_SYSCLK (BIT(31)) #define SPI_CLK_EQU_SYSCLK_M (BIT(31)) @@ -175,15 +175,15 @@ e 0. Can be configured in CONF state..*/ #define SPI_USER_REG(i) (REG_SPI_BASE(i) + 0x10) /* SPI_USR_COMMAND : R/W ;bitpos:[31] ;default: 1'b1 ; */ -/*description: This bit enable the command phase of an operation. Can be configured in CONF sta -te..*/ +/*description: This bit enable the command phase of an operation. Can be configured in CONF +state..*/ #define SPI_USR_COMMAND (BIT(31)) #define SPI_USR_COMMAND_M (BIT(31)) #define SPI_USR_COMMAND_V 0x1 #define SPI_USR_COMMAND_S 31 /* SPI_USR_ADDR : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: This bit enable the address phase of an operation. Can be configured in CONF sta -te..*/ +/*description: This bit enable the address phase of an operation. Can be configured in CONF +state..*/ #define SPI_USR_ADDR (BIT(30)) #define SPI_USR_ADDR_M (BIT(30)) #define SPI_USR_ADDR_V 0x1 @@ -357,7 +357,7 @@ n be configured in CONF state..*/ #define SPI_USR_COMMAND_BITLEN_S 28 /* SPI_MST_REMPTY_ERR_END_EN : R/W ;bitpos:[27] ;default: 1'b1 ; */ /*description: 1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI m -aster FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty erro +aster FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error r is valid in GP-SPI master FD/HD-mode..*/ #define SPI_MST_REMPTY_ERR_END_EN (BIT(27)) #define SPI_MST_REMPTY_ERR_END_EN_M (BIT(27)) @@ -927,7 +927,7 @@ AFIFO read-empty error when SPI outputs data in master mode. 0: Others..*/ #define SPI_SLV_CMD_ERR_INT_RAW_V 0x1 #define SPI_SLV_CMD_ERR_INT_RAW_S 16 /* SPI_SLV_BUF_ADDR_ERR_INT_RAW : R/W/WTC/SS ;bitpos:[15] ;default: 1'b0 ; */ -/*description: The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data addres +/*description: The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address s of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is bigger than 63. 0: Others..*/ #define SPI_SLV_BUF_ADDR_ERR_INT_RAW (BIT(15)) @@ -1370,7 +1370,7 @@ dge 0: output data at tsck posedge .*/ /* SPI_CLK_MODE : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ /*description: SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delaye d one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inacti -ve 3: SPI clock is alwasy on. Can be configured in CONF state..*/ +ve 3: SPI clock is always on. Can be configured in CONF state..*/ #define SPI_CLK_MODE 0x00000003 #define SPI_CLK_MODE_M ((SPI_CLK_MODE_V)<<(SPI_CLK_MODE_S)) #define SPI_CLK_MODE_V 0x3 diff --git a/components/soc/esp32c3/include/soc/spi_struct.h b/components/soc/esp32c3/register/soc/spi_struct.h similarity index 99% rename from components/soc/esp32c3/include/soc/spi_struct.h rename to components/soc/esp32c3/register/soc/spi_struct.h index 8cb6a7ee97a..88d7476caf9 100644 --- a/components/soc/esp32c3/include/soc/spi_struct.h +++ b/components/soc/esp32c3/register/soc/spi_struct.h @@ -55,7 +55,7 @@ typedef volatile struct spi_dev_s { uint32_t clkcnt_n : 6; /*In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state.*/ uint32_t clkdiv_pre : 4; /*In the master mode it is pre-divider of spi_clk. Can be configured in CONF state.*/ uint32_t reserved22 : 9; /*reserved*/ - uint32_t clk_equ_sysclk : 1; /*In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock. Can be configured in CONF state.*/ + uint32_t clk_equ_sysclk : 1; /*In the master mode 1: spi_clk is equal to system 0: spi_clk is divided from system clock. Can be configured in CONF state.*/ }; uint32_t val; } clock; @@ -317,7 +317,7 @@ typedef volatile struct spi_dev_s { uint32_t reserved_dc; union { struct { - uint32_t clk_mode : 2; /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state.*/ + uint32_t clk_mode : 2; /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is always on. Can be configured in CONF state.*/ uint32_t clk_mode_13 : 1; /*{CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7]. 0: support spi clk mode 0 and 2, first edge output data B[1]/B[6].*/ uint32_t rsck_data_out : 1; /*It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge 0: output data at tsck posedge */ uint32_t reserved4 : 4; /*reserved*/ diff --git a/components/soc/esp32c3/include/soc/syscon_reg.h b/components/soc/esp32c3/register/soc/syscon_reg.h similarity index 99% rename from components/soc/esp32c3/include/soc/syscon_reg.h rename to components/soc/esp32c3/register/soc/syscon_reg.h index e61f84eda35..1aff9a57484 100644 --- a/components/soc/esp32c3/include/soc/syscon_reg.h +++ b/components/soc/esp32c3/register/soc/syscon_reg.h @@ -10,7 +10,7 @@ #ifdef __cplusplus extern "C" { #endif -#include "soc.h" +#include "soc/soc.h" #define SYSCON_SYSCLK_CONF_REG (DR_REG_SYSCON_BASE + 0x000) /* SYSCON_RST_TICK_CNT : R/W ;bitpos:[12] ;default: 1'b0 ; */ /*description: */ @@ -206,7 +206,7 @@ extern "C" { #define SYSTEM_MACPWR_RST BIT(8) #define SYSTEM_RW_BTMAC_RST BIT(9) /* Bluetooth MAC */ #define SYSTEM_RW_BTLP_RST BIT(10) /* Bluetooth Low Power Module */ -#define SYSTEM_RW_BTMAC_REG_RST BIT(11) /* Bluetooth MAC Regsiters */ +#define SYSTEM_RW_BTMAC_REG_RST BIT(11) /* Bluetooth MAC Registers */ #define SYSTEM_RW_BTLP_REG_RST BIT(12) /* Bluetooth Low Power Registers */ #define SYSTEM_BTBB_REG_RST BIT(13) /* Bluetooth Baseband Registers */ diff --git a/components/soc/esp32c3/include/soc/syscon_struct.h b/components/soc/esp32c3/register/soc/syscon_struct.h similarity index 100% rename from components/soc/esp32c3/include/soc/syscon_struct.h rename to components/soc/esp32c3/register/soc/syscon_struct.h diff --git a/components/soc/esp32c3/include/soc/system_reg.h b/components/soc/esp32c3/register/soc/system_reg.h similarity index 99% rename from components/soc/esp32c3/include/soc/system_reg.h rename to components/soc/esp32c3/register/soc/system_reg.h index 7bcb904214d..7302066bbc8 100644 --- a/components/soc/esp32c3/include/soc/system_reg.h +++ b/components/soc/esp32c3/register/soc/system_reg.h @@ -10,7 +10,7 @@ #ifdef __cplusplus extern "C" { #endif -#include "soc.h" +#include "soc/soc.h" #define SYSTEM_CPU_PERI_CLK_EN_REG (DR_REG_SYSTEM_BASE + 0x000) /* SYSTEM_CLK_EN_DEDICATED_GPIO : R/W ;bitpos:[7] ;default: 1'b0 ; */ /*description: */ diff --git a/components/soc/esp32c3/include/soc/system_struct.h b/components/soc/esp32c3/register/soc/system_struct.h similarity index 99% rename from components/soc/esp32c3/include/soc/system_struct.h rename to components/soc/esp32c3/register/soc/system_struct.h index f4cb995aa22..bc2c1b3a240 100644 --- a/components/soc/esp32c3/include/soc/system_struct.h +++ b/components/soc/esp32c3/register/soc/system_struct.h @@ -10,7 +10,7 @@ #ifdef __cplusplus extern "C" { #endif -#include "soc.h" +#include "soc/soc.h" typedef volatile struct system_dev_s { union { diff --git a/components/soc/esp32c3/include/soc/systimer_reg.h b/components/soc/esp32c3/register/soc/systimer_reg.h similarity index 97% rename from components/soc/esp32c3/include/soc/systimer_reg.h rename to components/soc/esp32c3/register/soc/systimer_reg.h index 4e9f64fffa8..55316915df1 100644 --- a/components/soc/esp32c3/include/soc/systimer_reg.h +++ b/components/soc/esp32c3/register/soc/systimer_reg.h @@ -1,16 +1,7 @@ -/** Copyright 2021 Espressif Systems (Shanghai) PTE LTD +/* + * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. + * SPDX-License-Identifier: Apache-2.0 */ #pragma once diff --git a/components/soc/esp32c3/include/soc/systimer_struct.h b/components/soc/esp32c3/register/soc/systimer_struct.h similarity index 94% rename from components/soc/esp32c3/include/soc/systimer_struct.h rename to components/soc/esp32c3/register/soc/systimer_struct.h index 47e7b7d30c2..cf10afab1c3 100644 --- a/components/soc/esp32c3/include/soc/systimer_struct.h +++ b/components/soc/esp32c3/register/soc/systimer_struct.h @@ -1,16 +1,7 @@ -/** Copyright 2021 Espressif Systems (Shanghai) PTE LTD +/* + * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. + * SPDX-License-Identifier: Apache-2.0 */ #pragma once diff --git a/components/soc/esp32c3/include/soc/timer_group_reg.h b/components/soc/esp32c3/register/soc/timer_group_reg.h similarity index 100% rename from components/soc/esp32c3/include/soc/timer_group_reg.h rename to components/soc/esp32c3/register/soc/timer_group_reg.h diff --git a/components/soc/esp32c3/include/soc/timer_group_struct.h b/components/soc/esp32c3/register/soc/timer_group_struct.h similarity index 100% rename from components/soc/esp32c3/include/soc/timer_group_struct.h rename to components/soc/esp32c3/register/soc/timer_group_struct.h diff --git a/components/soc/esp32c3/include/soc/twai_struct.h b/components/soc/esp32c3/register/soc/twai_struct.h similarity index 100% rename from components/soc/esp32c3/include/soc/twai_struct.h rename to components/soc/esp32c3/register/soc/twai_struct.h diff --git a/components/soc/esp32c3/include/soc/uart_reg.h b/components/soc/esp32c3/register/soc/uart_reg.h similarity index 98% rename from components/soc/esp32c3/include/soc/uart_reg.h rename to components/soc/esp32c3/register/soc/uart_reg.h index a0d6c72735b..c26bab99382 100644 --- a/components/soc/esp32c3/include/soc/uart_reg.h +++ b/components/soc/esp32c3/register/soc/uart_reg.h @@ -1,16 +1,8 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef _SOC_UART_REG_H_ #define _SOC_UART_REG_H_ @@ -18,7 +10,7 @@ #ifdef __cplusplus extern "C" { #endif -#include "soc.h" +#include "soc/soc.h" #define UART_FIFO_REG(i) (REG_UART_BASE(i) + 0x0) /* UART_RXFIFO_RD_BYTE : RO ;bitpos:[7:0] ;default: 8'b0 ; */ /*description: UART $n accesses FIFO via this register.*/ @@ -99,7 +91,7 @@ extern "C" { #define UART_SW_XOFF_INT_RAW_V 0x1 #define UART_SW_XOFF_INT_RAW_S 10 /* UART_SW_XON_INT_RAW : R/WTC/SS ;bitpos:[9] ;default: 1'b0 ; */ -/*description: This interrupt raw bit turns to high level when receiver recevies +/*description: This interrupt raw bit turns to high level when receiver receives Xon char when uart_sw_flow_con_en is set to 1.*/ #define UART_SW_XON_INT_RAW (BIT(9)) #define UART_SW_XON_INT_RAW_M (BIT(9)) @@ -212,7 +204,7 @@ extern "C" { #define UART_TX_DONE_INT_ST_V 0x1 #define UART_TX_DONE_INT_ST_S 14 /* UART_TX_BRK_IDLE_DONE_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena +/*description: This is the status bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1.*/ #define UART_TX_BRK_IDLE_DONE_INT_ST (BIT(13)) #define UART_TX_BRK_IDLE_DONE_INT_ST_M (BIT(13)) @@ -751,7 +743,7 @@ extern "C" { #define UART_IRDA_DPLX_V 0x1 #define UART_IRDA_DPLX_S 9 /* UART_TXD_BRK : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: Set this bit to enbale transmitter to send NULL when the process +/*description: Set this bit to enable transmitter to send NULL when the process of sending data is done.*/ #define UART_TXD_BRK (BIT(8)) #define UART_TXD_BRK_M (BIT(8)) @@ -798,7 +790,7 @@ extern "C" { #define UART_CONF1_REG(i) (REG_UART_BASE(i) + 0x24) /* UART_RX_TOUT_EN : R/W ;bitpos:[21] ;default: 1'b0 ; */ -/*description: This is the enble bit for uart receiver's timeout function.*/ +/*description: This is the enable bit for uart receiver's timeout function.*/ #define UART_RX_TOUT_EN (BIT(21)) #define UART_RX_TOUT_EN_M (BIT(21)) #define UART_RX_TOUT_EN_V 0x1 @@ -847,7 +839,7 @@ extern "C" { #define UART_HIGHPULSE_REG(i) (REG_UART_BASE(i) + 0x2C) /* UART_HIGHPULSE_MIN_CNT : RO ;bitpos:[11:0] ;default: 12'hFFF ; */ -/*description: This register stores the value of the maxinum duration time +/*description: This register stores the value of the maximum duration time for the high level pulse. It is used in baud rate-detect process.*/ #define UART_HIGHPULSE_MIN_CNT 0x00000FFF #define UART_HIGHPULSE_MIN_CNT_M ((UART_HIGHPULSE_MIN_CNT_V)<<(UART_HIGHPULSE_MIN_CNT_S)) diff --git a/components/soc/esp32c3/include/soc/uart_struct.h b/components/soc/esp32c3/register/soc/uart_struct.h similarity index 98% rename from components/soc/esp32c3/include/soc/uart_struct.h rename to components/soc/esp32c3/register/soc/uart_struct.h index b14191f3ff0..8c76d475fb2 100644 --- a/components/soc/esp32c3/include/soc/uart_struct.h +++ b/components/soc/esp32c3/register/soc/uart_struct.h @@ -28,7 +28,7 @@ typedef volatile struct uart_dev_s { uint32_t cts_chg: 1; /*This interrupt raw bit turns to high level when receiver detects the edge change of CTSn signal.*/ uint32_t brk_det: 1; /*This interrupt raw bit turns to high level when receiver detects a 0 after the stop bit.*/ uint32_t rxfifo_tout: 1; /*This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte.*/ - uint32_t sw_xon: 1; /*This interrupt raw bit turns to high level when receiver recevies Xon char when uart_sw_flow_con_en is set to 1.*/ + uint32_t sw_xon: 1; /*This interrupt raw bit turns to high level when receiver receives Xon char when uart_sw_flow_con_en is set to 1.*/ uint32_t sw_xoff: 1; /*This interrupt raw bit turns to high level when receiver receives Xoff char when uart_sw_flow_con_en is set to 1.*/ uint32_t glitch_det: 1; /*This interrupt raw bit turns to high level when receiver detects a glitch in the middle of a start bit.*/ uint32_t tx_brk_done: 1; /*This interrupt raw bit turns to high level when transmitter completes sending NULL characters after all data in Tx-FIFO are sent.*/ @@ -58,7 +58,7 @@ typedef volatile struct uart_dev_s { uint32_t sw_xoff: 1; /*This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.*/ uint32_t glitch_det: 1; /*This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1.*/ uint32_t tx_brk_done: 1; /*This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1.*/ - uint32_t tx_brk_idle_done: 1; /*This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1.*/ + uint32_t tx_brk_idle_done: 1; /*This is the status bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1.*/ uint32_t tx_done: 1; /*This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.*/ uint32_t rs485_parity_err: 1; /*This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is set to 1.*/ uint32_t rs485_frm_err: 1; /*This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is set to 1.*/ @@ -161,7 +161,7 @@ typedef volatile struct uart_dev_s { uint32_t stop_bit_num: 2; /*This register is used to set the length of stop bit.*/ uint32_t sw_rts: 1; /*This register is used to configure the software rts signal which is used in software flow control.*/ uint32_t sw_dtr: 1; /*This register is used to configure the software dtr signal which is used in software flow control.*/ - uint32_t txd_brk: 1; /*Set this bit to enbale transmitter to send NULL when the process of sending data is done.*/ + uint32_t txd_brk: 1; /*Set this bit to enable transmitter to send NULL when the process of sending data is done.*/ uint32_t irda_dplx: 1; /*Set this bit to enable IrDA loopback mode.*/ uint32_t irda_tx_en: 1; /*This is the start enable bit for IrDA transmitter.*/ uint32_t irda_wctl: 1; /*1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA transmitter's 11th bit to 0.*/ @@ -193,7 +193,7 @@ typedef volatile struct uart_dev_s { uint32_t dis_rx_dat_ovf: 1; /*Disable UART Rx data overflow detect.*/ uint32_t rx_tout_flow_dis: 1; /*Set this bit to stop accumulating idle_cnt when hardware flow control works.*/ uint32_t rx_flow_en: 1; /*This is the flow enable bit for UART receiver.*/ - uint32_t rx_tout_en: 1; /*This is the enble bit for uart receiver's timeout function.*/ + uint32_t rx_tout_en: 1; /*This is the enable bit for uart receiver's timeout function.*/ uint32_t reserved22: 10; }; uint32_t val; @@ -207,7 +207,7 @@ typedef volatile struct uart_dev_s { } lowpulse; union { struct { - uint32_t min_cnt: 12; /*This register stores the value of the maxinum duration time for the high level pulse. It is used in baud rate-detect process.*/ + uint32_t min_cnt: 12; /*This register stores the value of the maximum duration time for the high level pulse. It is used in baud rate-detect process.*/ uint32_t reserved12: 20; /*Reserved*/ }; uint32_t val; diff --git a/components/soc/esp32c3/include/soc/uhci_reg.h b/components/soc/esp32c3/register/soc/uhci_reg.h similarity index 97% rename from components/soc/esp32c3/include/soc/uhci_reg.h rename to components/soc/esp32c3/register/soc/uhci_reg.h index 3a41dedb800..f387de7963a 100644 --- a/components/soc/esp32c3/include/soc/uhci_reg.h +++ b/components/soc/esp32c3/register/soc/uhci_reg.h @@ -1,16 +1,8 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef _SOC_UHCI_REG_H_ #define _SOC_UHCI_REG_H_ @@ -18,7 +10,7 @@ #ifdef __cplusplus extern "C" { #endif -#include "soc.h" +#include "soc/soc.h" #define UHCI_CONF0_REG(i) (REG_UHCI_BASE(i) + 0x0) /* UHCI_UART_RX_BRK_EOF_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */ /*description: If this bit is set to 1 UHCI will end payload receive process diff --git a/components/soc/esp32c3/include/soc/uhci_struct.h b/components/soc/esp32c3/register/soc/uhci_struct.h similarity index 100% rename from components/soc/esp32c3/include/soc/uhci_struct.h rename to components/soc/esp32c3/register/soc/uhci_struct.h diff --git a/components/soc/esp32c3/include/soc/usb_serial_jtag_reg.h b/components/soc/esp32c3/register/soc/usb_serial_jtag_reg.h similarity index 99% rename from components/soc/esp32c3/include/soc/usb_serial_jtag_reg.h rename to components/soc/esp32c3/register/soc/usb_serial_jtag_reg.h index f4cf387fe6c..6d908baec1b 100644 --- a/components/soc/esp32c3/include/soc/usb_serial_jtag_reg.h +++ b/components/soc/esp32c3/register/soc/usb_serial_jtag_reg.h @@ -1,9 +1,9 @@ - -/** Copyright 2021 Espressif Systems (Shanghai) Co. Ltd. - * SPDX-License-Identifier: Apache-2.0 +/* + * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 */ - #pragma once #include @@ -155,7 +155,7 @@ extern "C" { #define USB_SERIAL_JTAG_TEST_ENABLE_V 0x00000001 #define USB_SERIAL_JTAG_TEST_ENABLE_S 0 /* USB_SERIAL_JTAG_TEST_USB_OE : R/W; bitpos: [1]; default: 0; - * USB pad oen in + * USB pad one in * test */ #define USB_SERIAL_JTAG_TEST_USB_OE (BIT(1)) diff --git a/components/soc/esp32c3/include/soc/usb_serial_jtag_struct.h b/components/soc/esp32c3/register/soc/usb_serial_jtag_struct.h similarity index 96% rename from components/soc/esp32c3/include/soc/usb_serial_jtag_struct.h rename to components/soc/esp32c3/register/soc/usb_serial_jtag_struct.h index c1cfced04bb..98b15060a42 100644 --- a/components/soc/esp32c3/include/soc/usb_serial_jtag_struct.h +++ b/components/soc/esp32c3/register/soc/usb_serial_jtag_struct.h @@ -1,16 +1,8 @@ -// Copyright 2021 Espressif Systems (Shanghai) Co. Ltd. -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef _SOC_USB_SERIAL_JTAG_STRUCT_H_ #define _SOC_USB_SERIAL_JTAG_STRUCT_H_ @@ -18,7 +10,7 @@ #ifdef __cplusplus extern "C" { #endif -#include "soc.h" +#include "soc/soc.h" typedef volatile struct usb_serial_jtag_dev_s { union { diff --git a/components/soc/esp32c3/include/soc/xts_aes_reg.h b/components/soc/esp32c3/register/soc/xts_aes_reg.h similarity index 98% rename from components/soc/esp32c3/include/soc/xts_aes_reg.h rename to components/soc/esp32c3/register/soc/xts_aes_reg.h index 9845d0b0582..6a6e64539c5 100644 --- a/components/soc/esp32c3/include/soc/xts_aes_reg.h +++ b/components/soc/esp32c3/register/soc/xts_aes_reg.h @@ -119,7 +119,7 @@ extern "C" { #define XTS_AES_DATE_V 0x3FFFFFFFU #define XTS_AES_DATE_S 0 -/* For backward compatability with the older register names */ +/* For backward compatibility with the older register names */ #define AES_XTS_PLAIN_BASE XTS_AES_PLAIN_MEM #define AES_XTS_SIZE_REG XTS_AES_LINESIZE_REG #define AES_XTS_DESTINATION_REG XTS_AES_DESTINATION_REG diff --git a/tools/ci/check_copyright_ignore.txt b/tools/ci/check_copyright_ignore.txt index f605b7cd054..51fb864c98c 100644 --- a/tools/ci/check_copyright_ignore.txt +++ b/tools/ci/check_copyright_ignore.txt @@ -524,32 +524,6 @@ components/soc/esp32/include/soc/touch_sensor_channel.h components/soc/esp32/include/soc/uart_pins.h components/soc/esp32/include/soc/wdev_reg.h components/soc/esp32/ledc_periph.c -components/soc/esp32c3/include/soc/apb_saradc_reg.h -components/soc/esp32c3/include/soc/assist_debug_reg.h -components/soc/esp32c3/include/soc/bb_reg.h -components/soc/esp32c3/include/soc/boot_mode.h -components/soc/esp32c3/include/soc/extmem_reg.h -components/soc/esp32c3/include/soc/fe_reg.h -components/soc/esp32c3/include/soc/gpio_reg.h -components/soc/esp32c3/include/soc/gpio_struct.h -components/soc/esp32c3/include/soc/i2c_reg.h -components/soc/esp32c3/include/soc/interrupt_core0_reg.h -components/soc/esp32c3/include/soc/ledc_reg.h -components/soc/esp32c3/include/soc/nrx_reg.h -components/soc/esp32c3/include/soc/reset_reasons.h -components/soc/esp32c3/include/soc/rtc_i2c_reg.h -components/soc/esp32c3/include/soc/sensitive_reg.h -components/soc/esp32c3/include/soc/sensitive_struct.h -components/soc/esp32c3/include/soc/soc_pins.h -components/soc/esp32c3/include/soc/spi_mem_reg.h -components/soc/esp32c3/include/soc/systimer_reg.h -components/soc/esp32c3/include/soc/systimer_struct.h -components/soc/esp32c3/include/soc/uart_pins.h -components/soc/esp32c3/include/soc/uart_reg.h -components/soc/esp32c3/include/soc/uhci_reg.h -components/soc/esp32c3/include/soc/usb_serial_jtag_reg.h -components/soc/esp32c3/include/soc/usb_serial_jtag_struct.h -components/soc/esp32c3/include/soc/wdev_reg.h components/soc/esp32c3/interrupts.c components/soc/esp32c3/ledc_periph.c components/soc/esp32s2/adc_periph.c From c3e0dd610a889b22575adc0f5ed385771aed114a Mon Sep 17 00:00:00 2001 From: laokaiyao Date: Wed, 25 Sep 2024 14:33:50 +0800 Subject: [PATCH 115/472] refactor(soc): sort esp32s3 soc headers --- .../soc/esp32s3/include/soc/dport_reg.h | 13 +-- components/soc/esp32s3/include/soc/soc.h | 2 +- .../soc/esp32s3/include/soc/usb_dwc_struct.h | 2 +- components/soc/esp32s3/register/soc/.gitkeep | 0 .../{include => register}/soc/apb_ctrl_reg.h | 2 +- .../soc/apb_ctrl_struct.h | 0 .../soc/apb_saradc_reg.h | 20 +--- .../soc/apb_saradc_struct.h | 0 .../soc/assist_debug_reg.h | 20 +--- .../soc/assist_debug_struct.h | 18 +-- .../{include => register}/soc/efuse_reg.h | 6 +- .../{include => register}/soc/efuse_struct.h | 4 +- .../{include => register}/soc/extmem_reg.h | 58 ++++------ .../{include => register}/soc/extmem_struct.h | 18 +-- .../{include => register}/soc/gdma_reg.h | 2 +- .../{include => register}/soc/gdma_struct.h | 0 .../{include => register}/soc/gpio_reg.h | 22 ++-- .../{include => register}/soc/gpio_sd_reg.h | 2 +- .../soc/gpio_sd_struct.h | 0 .../{include => register}/soc/gpio_struct.h | 0 .../{include => register}/soc/hinf_reg.h | 20 +--- .../{include => register}/soc/hinf_struct.h | 18 +-- .../{include => register}/soc/host_reg.h | 20 +--- .../{include => register}/soc/host_struct.h | 20 +--- .../{include => register}/soc/i2c_reg.h | 15 +-- .../{include => register}/soc/i2c_struct.h | 15 +-- .../{include => register}/soc/i2s_reg.h | 34 +++--- .../{include => register}/soc/i2s_struct.h | 2 +- .../soc/interrupt_core0_reg.h | 20 +--- .../soc/interrupt_core0_struct.h | 18 +-- .../soc/interrupt_core1_reg.h | 20 +--- .../soc/interrupt_core1_struct.h | 18 +-- .../{include => register}/soc/io_mux_reg.h | 2 +- .../{include => register}/soc/lcd_cam_reg.h | 0 .../soc/lcd_cam_struct.h | 0 .../{include => register}/soc/ledc_reg.h | 22 ++-- .../{include => register}/soc/ledc_struct.h | 18 +-- .../{include => register}/soc/mcpwm_reg.h | 14 +-- .../{include => register}/soc/mcpwm_struct.h | 4 +- .../{include => register}/soc/pcnt_reg.h | 0 .../{include => register}/soc/pcnt_struct.h | 0 .../soc/peri_backup_reg.h | 20 +--- .../soc/peri_backup_struct.h | 18 +-- .../{include => register}/soc/reg_base.h | 0 .../{include => register}/soc/rmt_reg.h | 0 .../{include => register}/soc/rmt_struct.h | 0 .../{include => register}/soc/rtc_cntl_reg.h | 2 +- .../soc/rtc_cntl_struct.h | 10 +- .../{include => register}/soc/rtc_i2c_reg.h | 15 +-- .../soc/rtc_i2c_struct.h | 15 +-- .../{include => register}/soc/rtc_io_reg.h | 108 ++++++++---------- .../{include => register}/soc/rtc_io_struct.h | 18 +-- .../{include => register}/soc/sdmmc_reg.h | 20 +--- .../{include => register}/soc/sdmmc_struct.h | 0 .../{include => register}/soc/sens_reg.h | 2 +- .../{include => register}/soc/sens_struct.h | 0 .../{include => register}/soc/sensitive_reg.h | 20 +--- .../soc/sensitive_struct.h | 18 +-- .../{include => register}/soc/spi_mem_reg.h | 64 +++++------ .../soc/spi_mem_struct.h | 20 +--- .../{include => register}/soc/spi_reg.h | 36 +++--- .../{include => register}/soc/spi_struct.h | 22 ++-- .../{include => register}/soc/syscon_reg.h | 4 +- .../{include => register}/soc/syscon_struct.h | 18 +-- .../{include => register}/soc/system_reg.h | 20 +--- .../{include => register}/soc/system_struct.h | 18 +-- .../{include => register}/soc/systimer_reg.h | 15 +-- .../soc/systimer_struct.h | 15 +-- .../soc/timer_group_reg.h | 15 +-- .../soc/timer_group_struct.h | 0 .../{include => register}/soc/twai_struct.h | 0 .../{include => register}/soc/uart_reg.h | 25 ++-- .../{include => register}/soc/uart_struct.h | 25 ++-- .../{include => register}/soc/uhci_reg.h | 20 +--- .../{include => register}/soc/uhci_struct.h | 0 .../{include => register}/soc/usb_reg.h | 62 +++++----- .../soc/usb_serial_jtag_reg.h | 14 +-- .../soc/usb_serial_jtag_struct.h | 20 +--- .../{include => register}/soc/usb_struct.h | 2 +- .../{include => register}/soc/usb_wrap_reg.h | 20 +--- .../soc/usb_wrap_struct.h | 15 +-- .../soc/world_controller_reg.h | 0 .../soc/world_controller_struct.h | 0 tools/ci/check_copyright_ignore.txt | 53 --------- 84 files changed, 415 insertions(+), 823 deletions(-) delete mode 100644 components/soc/esp32s3/register/soc/.gitkeep rename components/soc/esp32s3/{include => register}/soc/apb_ctrl_reg.h (99%) rename components/soc/esp32s3/{include => register}/soc/apb_ctrl_struct.h (100%) rename components/soc/esp32s3/{include => register}/soc/apb_saradc_reg.h (97%) rename components/soc/esp32s3/{include => register}/soc/apb_saradc_struct.h (100%) rename components/soc/esp32s3/{include => register}/soc/assist_debug_reg.h (99%) rename components/soc/esp32s3/{include => register}/soc/assist_debug_struct.h (96%) rename components/soc/esp32s3/{include => register}/soc/efuse_reg.h (99%) rename components/soc/esp32s3/{include => register}/soc/efuse_struct.h (99%) rename components/soc/esp32s3/{include => register}/soc/extmem_reg.h (98%) rename components/soc/esp32s3/{include => register}/soc/extmem_struct.h (98%) rename components/soc/esp32s3/{include => register}/soc/gdma_reg.h (99%) rename components/soc/esp32s3/{include => register}/soc/gdma_struct.h (100%) rename components/soc/esp32s3/{include => register}/soc/gpio_reg.h (99%) rename components/soc/esp32s3/{include => register}/soc/gpio_sd_reg.h (99%) rename components/soc/esp32s3/{include => register}/soc/gpio_sd_struct.h (100%) rename components/soc/esp32s3/{include => register}/soc/gpio_struct.h (100%) rename components/soc/esp32s3/{include => register}/soc/hinf_reg.h (93%) rename components/soc/esp32s3/{include => register}/soc/hinf_struct.h (84%) rename components/soc/esp32s3/{include => register}/soc/host_reg.h (99%) rename components/soc/esp32s3/{include => register}/soc/host_struct.h (97%) rename components/soc/esp32s3/{include => register}/soc/i2c_reg.h (99%) rename components/soc/esp32s3/{include => register}/soc/i2c_struct.h (98%) rename components/soc/esp32s3/{include => register}/soc/i2s_reg.h (98%) rename components/soc/esp32s3/{include => register}/soc/i2s_struct.h (99%) rename components/soc/esp32s3/{include => register}/soc/interrupt_core0_reg.h (98%) rename components/soc/esp32s3/{include => register}/soc/interrupt_core0_struct.h (98%) rename components/soc/esp32s3/{include => register}/soc/interrupt_core1_reg.h (98%) rename components/soc/esp32s3/{include => register}/soc/interrupt_core1_struct.h (98%) rename components/soc/esp32s3/{include => register}/soc/io_mux_reg.h (99%) rename components/soc/esp32s3/{include => register}/soc/lcd_cam_reg.h (100%) rename components/soc/esp32s3/{include => register}/soc/lcd_cam_struct.h (100%) rename components/soc/esp32s3/{include => register}/soc/ledc_reg.h (98%) rename components/soc/esp32s3/{include => register}/soc/ledc_struct.h (92%) rename components/soc/esp32s3/{include => register}/soc/mcpwm_reg.h (99%) rename components/soc/esp32s3/{include => register}/soc/mcpwm_struct.h (99%) rename components/soc/esp32s3/{include => register}/soc/pcnt_reg.h (100%) rename components/soc/esp32s3/{include => register}/soc/pcnt_struct.h (100%) rename components/soc/esp32s3/{include => register}/soc/peri_backup_reg.h (92%) rename components/soc/esp32s3/{include => register}/soc/peri_backup_struct.h (85%) rename components/soc/esp32s3/{include => register}/soc/reg_base.h (100%) rename components/soc/esp32s3/{include => register}/soc/rmt_reg.h (100%) rename components/soc/esp32s3/{include => register}/soc/rmt_struct.h (100%) rename components/soc/esp32s3/{include => register}/soc/rtc_cntl_reg.h (99%) rename components/soc/esp32s3/{include => register}/soc/rtc_cntl_struct.h (99%) rename components/soc/esp32s3/{include => register}/soc/rtc_i2c_reg.h (98%) rename components/soc/esp32s3/{include => register}/soc/rtc_i2c_struct.h (96%) rename components/soc/esp32s3/{include => register}/soc/rtc_io_reg.h (98%) rename components/soc/esp32s3/{include => register}/soc/rtc_io_struct.h (95%) rename components/soc/esp32s3/{include => register}/soc/sdmmc_reg.h (85%) rename components/soc/esp32s3/{include => register}/soc/sdmmc_struct.h (100%) rename components/soc/esp32s3/{include => register}/soc/sens_reg.h (99%) rename components/soc/esp32s3/{include => register}/soc/sens_struct.h (100%) rename components/soc/esp32s3/{include => register}/soc/sensitive_reg.h (99%) rename components/soc/esp32s3/{include => register}/soc/sensitive_struct.h (99%) rename components/soc/esp32s3/{include => register}/soc/spi_mem_reg.h (98%) rename components/soc/esp32s3/{include => register}/soc/spi_mem_struct.h (98%) rename components/soc/esp32s3/{include => register}/soc/spi_reg.h (98%) rename components/soc/esp32s3/{include => register}/soc/spi_struct.h (98%) rename components/soc/esp32s3/{include => register}/soc/syscon_reg.h (99%) rename components/soc/esp32s3/{include => register}/soc/syscon_struct.h (96%) rename components/soc/esp32s3/{include => register}/soc/system_reg.h (98%) rename components/soc/esp32s3/{include => register}/soc/system_struct.h (98%) rename components/soc/esp32s3/{include => register}/soc/systimer_reg.h (97%) rename components/soc/esp32s3/{include => register}/soc/systimer_struct.h (94%) rename components/soc/esp32s3/{include => register}/soc/timer_group_reg.h (97%) rename components/soc/esp32s3/{include => register}/soc/timer_group_struct.h (100%) rename components/soc/esp32s3/{include => register}/soc/twai_struct.h (100%) rename components/soc/esp32s3/{include => register}/soc/uart_reg.h (98%) rename components/soc/esp32s3/{include => register}/soc/uart_struct.h (97%) rename components/soc/esp32s3/{include => register}/soc/uhci_reg.h (97%) rename components/soc/esp32s3/{include => register}/soc/uhci_struct.h (100%) rename components/soc/esp32s3/{include => register}/soc/usb_reg.h (99%) rename components/soc/esp32s3/{include => register}/soc/usb_serial_jtag_reg.h (99%) rename components/soc/esp32s3/{include => register}/soc/usb_serial_jtag_struct.h (96%) rename components/soc/esp32s3/{include => register}/soc/usb_struct.h (98%) rename components/soc/esp32s3/{include => register}/soc/usb_wrap_reg.h (93%) rename components/soc/esp32s3/{include => register}/soc/usb_wrap_struct.h (95%) rename components/soc/esp32s3/{include => register}/soc/world_controller_reg.h (100%) rename components/soc/esp32s3/{include => register}/soc/world_controller_struct.h (100%) diff --git a/components/soc/esp32s3/include/soc/dport_reg.h b/components/soc/esp32s3/include/soc/dport_reg.h index e17afb79b5c..e9f3de4c442 100644 --- a/components/soc/esp32s3/include/soc/dport_reg.h +++ b/components/soc/esp32s3/include/soc/dport_reg.h @@ -5,20 +5,19 @@ */ #pragma once -#include "soc.h" +#include "soc/interrupt_reg.h" +#include "soc/system_reg.h" +#include "soc/sensitive_reg.h" +#include "soc/soc.h" + #ifdef __cplusplus extern "C" { #endif -#include "interrupt_reg.h" -#include "system_reg.h" -#include "sensitive_reg.h" -#include "soc.h" - #define DPORT_DATE_REG SYSTEM_DATE_REG #ifndef __ASSEMBLER__ -#include "dport_access.h" +#include "soc/dport_access.h" #endif #ifdef __cplusplus diff --git a/components/soc/esp32s3/include/soc/soc.h b/components/soc/esp32s3/include/soc/soc.h index 056c6d9f4e5..78a29ee2c30 100644 --- a/components/soc/esp32s3/include/soc/soc.h +++ b/components/soc/esp32s3/include/soc/soc.h @@ -12,7 +12,7 @@ #endif #include "esp_bit_defs.h" -#include "reg_base.h" +#include "soc/reg_base.h" #define PRO_CPU_NUM (0) #define APP_CPU_NUM (1) diff --git a/components/soc/esp32s3/include/soc/usb_dwc_struct.h b/components/soc/esp32s3/include/soc/usb_dwc_struct.h index 5fd5800715e..70f73e37b7a 100644 --- a/components/soc/esp32s3/include/soc/usb_dwc_struct.h +++ b/components/soc/esp32s3/include/soc/usb_dwc_struct.h @@ -33,7 +33,7 @@ typedef union { uint32_t hnpreq: 1; uint32_t hstsethnpen: 1; uint32_t devhnpen: 1; - uint32_t ehen: 1; + uint32_t ehen: 1; // codespell:ignore ehen uint32_t reserved_13: 2; uint32_t dbncefltrbypass: 1; uint32_t conidsts: 1; diff --git a/components/soc/esp32s3/register/soc/.gitkeep b/components/soc/esp32s3/register/soc/.gitkeep deleted file mode 100644 index e69de29bb2d..00000000000 diff --git a/components/soc/esp32s3/include/soc/apb_ctrl_reg.h b/components/soc/esp32s3/register/soc/apb_ctrl_reg.h similarity index 99% rename from components/soc/esp32s3/include/soc/apb_ctrl_reg.h rename to components/soc/esp32s3/register/soc/apb_ctrl_reg.h index 845394f702e..809463766ae 100644 --- a/components/soc/esp32s3/include/soc/apb_ctrl_reg.h +++ b/components/soc/esp32s3/register/soc/apb_ctrl_reg.h @@ -8,7 +8,7 @@ #warning "apb_ctrl_reg is deprecated due to duplicated with syscon_reg, please use syscon_reg instead, they are same" -#include "soc.h" +#include "soc/soc.h" #ifdef __cplusplus extern "C" { #endif diff --git a/components/soc/esp32s3/include/soc/apb_ctrl_struct.h b/components/soc/esp32s3/register/soc/apb_ctrl_struct.h similarity index 100% rename from components/soc/esp32s3/include/soc/apb_ctrl_struct.h rename to components/soc/esp32s3/register/soc/apb_ctrl_struct.h diff --git a/components/soc/esp32s3/include/soc/apb_saradc_reg.h b/components/soc/esp32s3/register/soc/apb_saradc_reg.h similarity index 97% rename from components/soc/esp32s3/include/soc/apb_saradc_reg.h rename to components/soc/esp32s3/register/soc/apb_saradc_reg.h index b9c88f22547..61d99974db4 100644 --- a/components/soc/esp32s3/include/soc/apb_saradc_reg.h +++ b/components/soc/esp32s3/register/soc/apb_saradc_reg.h @@ -1,21 +1,13 @@ -// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef _SOC_APB_SARADC_REG_H_ #define _SOC_APB_SARADC_REG_H_ -#include "soc.h" +#include "soc/soc.h" #ifdef __cplusplus extern "C" { #endif diff --git a/components/soc/esp32s3/include/soc/apb_saradc_struct.h b/components/soc/esp32s3/register/soc/apb_saradc_struct.h similarity index 100% rename from components/soc/esp32s3/include/soc/apb_saradc_struct.h rename to components/soc/esp32s3/register/soc/apb_saradc_struct.h diff --git a/components/soc/esp32s3/include/soc/assist_debug_reg.h b/components/soc/esp32s3/register/soc/assist_debug_reg.h similarity index 99% rename from components/soc/esp32s3/include/soc/assist_debug_reg.h rename to components/soc/esp32s3/register/soc/assist_debug_reg.h index 0bf71c44d33..35a89cadabb 100644 --- a/components/soc/esp32s3/include/soc/assist_debug_reg.h +++ b/components/soc/esp32s3/register/soc/assist_debug_reg.h @@ -1,21 +1,13 @@ -// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef _SOC_ASSIST_DEBUG_REG_H_ #define _SOC_ASSIST_DEBUG_REG_H_ -#include "soc.h" +#include "soc/soc.h" #ifdef __cplusplus extern "C" { #endif diff --git a/components/soc/esp32s3/include/soc/assist_debug_struct.h b/components/soc/esp32s3/register/soc/assist_debug_struct.h similarity index 96% rename from components/soc/esp32s3/include/soc/assist_debug_struct.h rename to components/soc/esp32s3/register/soc/assist_debug_struct.h index a6152af468c..a66c4ecb772 100644 --- a/components/soc/esp32s3/include/soc/assist_debug_struct.h +++ b/components/soc/esp32s3/register/soc/assist_debug_struct.h @@ -1,16 +1,8 @@ -// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef _SOC_ASSIST_DEBUG_STRUCT_H_ #define _SOC_ASSIST_DEBUG_STRUCT_H_ diff --git a/components/soc/esp32s3/include/soc/efuse_reg.h b/components/soc/esp32s3/register/soc/efuse_reg.h similarity index 99% rename from components/soc/esp32s3/include/soc/efuse_reg.h rename to components/soc/esp32s3/register/soc/efuse_reg.h index c4b8a5ed47a..0c89dd3808e 100644 --- a/components/soc/esp32s3/include/soc/efuse_reg.h +++ b/components/soc/esp32s3/register/soc/efuse_reg.h @@ -7,7 +7,7 @@ #include #include "soc/soc.h" -#include "efuse_defs.h" +#include "soc/efuse_defs.h" #ifdef __cplusplus extern "C" { #endif @@ -553,7 +553,7 @@ extern "C" { #define EFUSE_DIS_DIRECT_BOOT_V 0x00000001U #define EFUSE_DIS_DIRECT_BOOT_S 1 /** EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT : RO; bitpos: [2]; default: 0; - * Selectes the default UART print channel. 0: UART0. 1: UART1. + * Selects the default UART print channel. 0: UART0. 1: UART1. */ #define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT (BIT(2)) #define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_M (EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V << EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S) @@ -2638,7 +2638,7 @@ extern "C" { #define EFUSE_CLK_EN_S 16 /** EFUSE_CONF_REG register - * eFuse operation mode configuraiton register + * eFuse operation mode configuration register */ #define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x1cc) /** EFUSE_OP_CODE : R/W; bitpos: [15:0]; default: 0; diff --git a/components/soc/esp32s3/include/soc/efuse_struct.h b/components/soc/esp32s3/register/soc/efuse_struct.h similarity index 99% rename from components/soc/esp32s3/include/soc/efuse_struct.h rename to components/soc/esp32s3/register/soc/efuse_struct.h index a3c589f543c..2b2639c7522 100644 --- a/components/soc/esp32s3/include/soc/efuse_struct.h +++ b/components/soc/esp32s3/register/soc/efuse_struct.h @@ -423,7 +423,7 @@ typedef union { */ uint32_t dis_direct_boot:1; /** dis_usb_serial_jtag_rom_print : RO; bitpos: [2]; default: 0; - * Selectes the default UART print channel. 0: UART0. 1: UART1. + * Selects the default UART print channel. 0: UART0. 1: UART1. */ uint32_t dis_usb_serial_jtag_rom_print:1; /** flash_ecc_mode : RO; bitpos: [3]; default: 0; @@ -2163,7 +2163,7 @@ typedef union { } efuse_clk_reg_t; /** Type of conf register - * eFuse operation mode configuraiton register + * eFuse operation mode configuration register */ typedef union { struct { diff --git a/components/soc/esp32s3/include/soc/extmem_reg.h b/components/soc/esp32s3/register/soc/extmem_reg.h similarity index 98% rename from components/soc/esp32s3/include/soc/extmem_reg.h rename to components/soc/esp32s3/register/soc/extmem_reg.h index 5763ec6df77..4929c47f86c 100644 --- a/components/soc/esp32s3/include/soc/extmem_reg.h +++ b/components/soc/esp32s3/register/soc/extmem_reg.h @@ -1,21 +1,13 @@ -// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef _SOC_EXTMEM_REG_H_ #define _SOC_EXTMEM_REG_H_ -#include "soc.h" +#include "soc/soc.h" #ifdef __cplusplus extern "C" { #endif @@ -112,15 +104,15 @@ which is combined with DCACHE_PRELOCK_SCT0_SIZE_REG.*/ #define EXTMEM_DCACHE_PRELOCK_SCT_SIZE_REG (DR_REG_EXTMEM_BASE + 0x18) /* EXTMEM_DCACHE_PRELOCK_SCT0_SIZE : R/W ;bitpos:[31:16] ;default: 16'h0 ; */ -/*description: The bits are used to configure the first length of data locking, which is combin -ed with DCACHE_PRELOCK_SCT0_ADDR_REG.*/ +/*description: The bits are used to configure the first length of data locking, which is +combined with DCACHE_PRELOCK_SCT0_ADDR_REG.*/ #define EXTMEM_DCACHE_PRELOCK_SCT0_SIZE 0x0000FFFF #define EXTMEM_DCACHE_PRELOCK_SCT0_SIZE_M ((EXTMEM_DCACHE_PRELOCK_SCT0_SIZE_V)<<(EXTMEM_DCACHE_PRELOCK_SCT0_SIZE_S)) #define EXTMEM_DCACHE_PRELOCK_SCT0_SIZE_V 0xFFFF #define EXTMEM_DCACHE_PRELOCK_SCT0_SIZE_S 16 /* EXTMEM_DCACHE_PRELOCK_SCT1_SIZE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: The bits are used to configure the second length of data locking, which is combi -ned with DCACHE_PRELOCK_SCT1_ADDR_REG.*/ +/*description: The bits are used to configure the second length of data locking, which is +combined with DCACHE_PRELOCK_SCT1_ADDR_REG.*/ #define EXTMEM_DCACHE_PRELOCK_SCT1_SIZE 0x0000FFFF #define EXTMEM_DCACHE_PRELOCK_SCT1_SIZE_M ((EXTMEM_DCACHE_PRELOCK_SCT1_SIZE_V)<<(EXTMEM_DCACHE_PRELOCK_SCT1_SIZE_S)) #define EXTMEM_DCACHE_PRELOCK_SCT1_SIZE_V 0xFFFF @@ -189,7 +181,7 @@ ter writeback operation done..*/ #define EXTMEM_DCACHE_WRITEBACK_ENA_S 1 /* EXTMEM_DCACHE_INVALIDATE_ENA : R/W ;bitpos:[0] ;default: 1'b1 ; */ /*description: The bit is used to enable invalidate operation. It will be cleared by hardware a -fter invalidate operation done..*/ +after invalidate operation done..*/ #define EXTMEM_DCACHE_INVALIDATE_ENA (BIT(0)) #define EXTMEM_DCACHE_INVALIDATE_ENA_M (BIT(0)) #define EXTMEM_DCACHE_INVALIDATE_ENA_V 0x1 @@ -342,8 +334,8 @@ ache_autoload_done. 1: enable, 0: disable. .*/ #define EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR_REG (DR_REG_EXTMEM_BASE + 0x50) /* EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: The bits are used to configure the start virtual address of the first section fo -r autoload operation. It should be combined with dcache_autoload_sct0_ena..*/ +/*description: The bits are used to configure the start virtual address of the first section +for autoload operation. It should be combined with dcache_autoload_sct0_ena..*/ #define EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR 0xFFFFFFFF #define EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR_M ((EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR_V)<<(EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR_S)) #define EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR_V 0xFFFFFFFF @@ -472,15 +464,15 @@ which is combined with ICACHE_PRELOCK_SCT0_SIZE_REG.*/ #define EXTMEM_ICACHE_PRELOCK_SCT_SIZE_REG (DR_REG_EXTMEM_BASE + 0x78) /* EXTMEM_ICACHE_PRELOCK_SCT0_SIZE : R/W ;bitpos:[31:16] ;default: 16'h0 ; */ -/*description: The bits are used to configure the first length of data locking, which is combin -ed with ICACHE_PRELOCK_SCT0_ADDR_REG.*/ +/*description: The bits are used to configure the first length of data locking, which is +combined with ICACHE_PRELOCK_SCT0_ADDR_REG.*/ #define EXTMEM_ICACHE_PRELOCK_SCT0_SIZE 0x0000FFFF #define EXTMEM_ICACHE_PRELOCK_SCT0_SIZE_M ((EXTMEM_ICACHE_PRELOCK_SCT0_SIZE_V)<<(EXTMEM_ICACHE_PRELOCK_SCT0_SIZE_S)) #define EXTMEM_ICACHE_PRELOCK_SCT0_SIZE_V 0xFFFF #define EXTMEM_ICACHE_PRELOCK_SCT0_SIZE_S 16 /* EXTMEM_ICACHE_PRELOCK_SCT1_SIZE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: The bits are used to configure the second length of data locking, which is combi -ned with ICACHE_PRELOCK_SCT1_ADDR_REG.*/ +/*description: The bits are used to configure the second length of data locking, which is +combined with ICACHE_PRELOCK_SCT1_ADDR_REG.*/ #define EXTMEM_ICACHE_PRELOCK_SCT1_SIZE 0x0000FFFF #define EXTMEM_ICACHE_PRELOCK_SCT1_SIZE_M ((EXTMEM_ICACHE_PRELOCK_SCT1_SIZE_V)<<(EXTMEM_ICACHE_PRELOCK_SCT1_SIZE_S)) #define EXTMEM_ICACHE_PRELOCK_SCT1_SIZE_V 0xFFFF @@ -535,7 +527,7 @@ counts of cache block. It should be combined with ICACHE_LOCK_ADDR_REG..*/ #define EXTMEM_ICACHE_SYNC_DONE_S 1 /* EXTMEM_ICACHE_INVALIDATE_ENA : R/W ;bitpos:[0] ;default: 1'b1 ; */ /*description: The bit is used to enable invalidate operation. It will be cleared by hardware a -fter invalidate operation done..*/ +after invalidate operation done..*/ #define EXTMEM_ICACHE_INVALIDATE_ENA (BIT(0)) #define EXTMEM_ICACHE_INVALIDATE_ENA_M (BIT(0)) #define EXTMEM_ICACHE_INVALIDATE_ENA_V 0x1 @@ -655,8 +647,8 @@ ache_autoload_done. 1: enable, 0: disable. .*/ #define EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_REG (DR_REG_EXTMEM_BASE + 0xA4) /* EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: The bits are used to configure the start virtual address of the first section fo -r autoload operation. It should be combined with icache_autoload_sct0_ena..*/ +/*description: The bits are used to configure the start virtual address of the first section +for autoload operation. It should be combined with icache_autoload_sct0_ena..*/ #define EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR 0xFFFFFFFF #define EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_M ((EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_V)<<(EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_S)) #define EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_V 0xFFFFFFFF @@ -855,7 +847,7 @@ cks all have been occupied by occupy-mode..*/ #define EXTMEM_IBUS_CNT_OVF_INT_CLR_V 0x1 #define EXTMEM_IBUS_CNT_OVF_INT_CLR_S 7 /* EXTMEM_DCACHE_OCCUPY_EXC_INT_CLR : WOD ;bitpos:[6] ;default: 1'b0 ; */ -/*description: The bit is used to clear interrupt by dcache trying to replace a line whose bloc +/*description: The bit is used to clear interrupt by dcache trying to replace a line whose block ks all have been occupied by occupy-mode..*/ #define EXTMEM_DCACHE_OCCUPY_EXC_INT_CLR (BIT(6)) #define EXTMEM_DCACHE_OCCUPY_EXC_INT_CLR_M (BIT(6)) @@ -914,7 +906,7 @@ w..*/ #define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST_V 0x1 #define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST_S 10 /* EXTMEM_DBUS_ACS_CNT_OVF_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: The bit is used to indicate interrupt by dbus access flash/spiram counter overfl +/*description: The bit is used to indicate interrupt by dbus access flash/spiram counter overflow ow..*/ #define EXTMEM_DBUS_ACS_CNT_OVF_ST (BIT(9)) #define EXTMEM_DBUS_ACS_CNT_OVF_ST_M (BIT(9)) @@ -928,7 +920,7 @@ verflow..*/ #define EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST_V 0x1 #define EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST_S 8 /* EXTMEM_IBUS_ACS_CNT_OVF_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: The bit is used to indicate interrupt by ibus access flash/spiram counter overfl +/*description: The bit is used to indicate interrupt by ibus access flash/spiram counter overflow ow..*/ #define EXTMEM_IBUS_ACS_CNT_OVF_ST (BIT(7)) #define EXTMEM_IBUS_ACS_CNT_OVF_ST_M (BIT(7)) @@ -1642,8 +1634,8 @@ the others fields inside this register..*/ #define EXTMEM_CACHE_VADDR_REG (DR_REG_EXTMEM_BASE + 0x188) /* EXTMEM_CACHE_VADDR : R/W ;bitpos:[31:0] ;default: 32'h00000000 ; */ -/*description: Those bits stores the virtual address which will decide where inside the specifi -ed tag memory object will be accessed..*/ +/*description: Those bits stores the virtual address which will decide where inside the +specified tag memory object will be accessed..*/ #define EXTMEM_CACHE_VADDR 0xFFFFFFFF #define EXTMEM_CACHE_VADDR_M ((EXTMEM_CACHE_VADDR_V)<<(EXTMEM_CACHE_VADDR_S)) #define EXTMEM_CACHE_VADDR_V 0xFFFFFFFF diff --git a/components/soc/esp32s3/include/soc/extmem_struct.h b/components/soc/esp32s3/register/soc/extmem_struct.h similarity index 98% rename from components/soc/esp32s3/include/soc/extmem_struct.h rename to components/soc/esp32s3/register/soc/extmem_struct.h index 58ca6462942..8e2a9aad3c2 100644 --- a/components/soc/esp32s3/include/soc/extmem_struct.h +++ b/components/soc/esp32s3/register/soc/extmem_struct.h @@ -1,16 +1,8 @@ -// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef _SOC_EXTMEM_STRUCT_H_ #define _SOC_EXTMEM_STRUCT_H_ diff --git a/components/soc/esp32s3/include/soc/gdma_reg.h b/components/soc/esp32s3/register/soc/gdma_reg.h similarity index 99% rename from components/soc/esp32s3/include/soc/gdma_reg.h rename to components/soc/esp32s3/register/soc/gdma_reg.h index 53e76bdc6ff..7c37c513ef9 100644 --- a/components/soc/esp32s3/include/soc/gdma_reg.h +++ b/components/soc/esp32s3/register/soc/gdma_reg.h @@ -7,7 +7,7 @@ #define _SOC_GDMA_REG_H_ -#include "soc.h" +#include "soc/soc.h" #ifdef __cplusplus extern "C" { #endif diff --git a/components/soc/esp32s3/include/soc/gdma_struct.h b/components/soc/esp32s3/register/soc/gdma_struct.h similarity index 100% rename from components/soc/esp32s3/include/soc/gdma_struct.h rename to components/soc/esp32s3/register/soc/gdma_struct.h diff --git a/components/soc/esp32s3/include/soc/gpio_reg.h b/components/soc/esp32s3/register/soc/gpio_reg.h similarity index 99% rename from components/soc/esp32s3/include/soc/gpio_reg.h rename to components/soc/esp32s3/register/soc/gpio_reg.h index 39656ffce35..8a109f6dd20 100644 --- a/components/soc/esp32s3/include/soc/gpio_reg.h +++ b/components/soc/esp32s3/register/soc/gpio_reg.h @@ -1,26 +1,18 @@ -// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef _SOC_GPIO_REG_H_ #define _SOC_GPIO_REG_H_ -#include "soc.h" +#include "soc/soc.h" #ifdef __cplusplus extern "C" { #endif -#include "soc.h" +#include "soc/soc.h" #define GPIO_PIN_CONFIG_MSB 12 #define GPIO_PIN_CONFIG_LSB 11 diff --git a/components/soc/esp32s3/include/soc/gpio_sd_reg.h b/components/soc/esp32s3/register/soc/gpio_sd_reg.h similarity index 99% rename from components/soc/esp32s3/include/soc/gpio_sd_reg.h rename to components/soc/esp32s3/register/soc/gpio_sd_reg.h index 4aa1fe8f86f..f171b12dae5 100644 --- a/components/soc/esp32s3/include/soc/gpio_sd_reg.h +++ b/components/soc/esp32s3/register/soc/gpio_sd_reg.h @@ -6,7 +6,7 @@ #pragma once -#include "soc.h" +#include "soc/soc.h" #ifdef __cplusplus extern "C" { diff --git a/components/soc/esp32s3/include/soc/gpio_sd_struct.h b/components/soc/esp32s3/register/soc/gpio_sd_struct.h similarity index 100% rename from components/soc/esp32s3/include/soc/gpio_sd_struct.h rename to components/soc/esp32s3/register/soc/gpio_sd_struct.h diff --git a/components/soc/esp32s3/include/soc/gpio_struct.h b/components/soc/esp32s3/register/soc/gpio_struct.h similarity index 100% rename from components/soc/esp32s3/include/soc/gpio_struct.h rename to components/soc/esp32s3/register/soc/gpio_struct.h diff --git a/components/soc/esp32s3/include/soc/hinf_reg.h b/components/soc/esp32s3/register/soc/hinf_reg.h similarity index 93% rename from components/soc/esp32s3/include/soc/hinf_reg.h rename to components/soc/esp32s3/register/soc/hinf_reg.h index 212fe817ca2..d419cf129e0 100644 --- a/components/soc/esp32s3/include/soc/hinf_reg.h +++ b/components/soc/esp32s3/register/soc/hinf_reg.h @@ -1,19 +1,11 @@ -// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #pragma once -#include "soc.h" +#include "soc/soc.h" #define HINF_CFG_DATA0_REG (DR_REG_HINF_BASE + 0x0) /* HINF_DEVICE_ID_FN1 : R/W ;bitpos:[31:16] ;default: 16'h2222 ; */ diff --git a/components/soc/esp32s3/include/soc/hinf_struct.h b/components/soc/esp32s3/register/soc/hinf_struct.h similarity index 84% rename from components/soc/esp32s3/include/soc/hinf_struct.h rename to components/soc/esp32s3/register/soc/hinf_struct.h index 965f8bd43c1..cf0713461bf 100644 --- a/components/soc/esp32s3/include/soc/hinf_struct.h +++ b/components/soc/esp32s3/register/soc/hinf_struct.h @@ -1,16 +1,8 @@ -// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #pragma once #include diff --git a/components/soc/esp32s3/include/soc/host_reg.h b/components/soc/esp32s3/register/soc/host_reg.h similarity index 99% rename from components/soc/esp32s3/include/soc/host_reg.h rename to components/soc/esp32s3/register/soc/host_reg.h index afcd67d85f2..4dc04161fca 100644 --- a/components/soc/esp32s3/include/soc/host_reg.h +++ b/components/soc/esp32s3/register/soc/host_reg.h @@ -1,21 +1,13 @@ -// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef _SOC_HOST_REG_H_ #define _SOC_HOST_REG_H_ -#include "soc.h" +#include "soc/soc.h" #ifdef __cplusplus extern "C" { #endif diff --git a/components/soc/esp32s3/include/soc/host_struct.h b/components/soc/esp32s3/register/soc/host_struct.h similarity index 97% rename from components/soc/esp32s3/include/soc/host_struct.h rename to components/soc/esp32s3/register/soc/host_struct.h index 1a6b89e2817..79a830ef145 100644 --- a/components/soc/esp32s3/include/soc/host_struct.h +++ b/components/soc/esp32s3/register/soc/host_struct.h @@ -1,16 +1,8 @@ -// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef _SOC_HOST_STRUCT_H_ #define _SOC_HOST_STRUCT_H_ @@ -459,7 +451,7 @@ typedef volatile struct host_dev_s { uint32_t reserved_f0; union { struct { - uint32_t infor : 20; + uint32_t infor : 20; // codespell:ignore infor uint32_t reserved20 : 12; }; uint32_t val; diff --git a/components/soc/esp32s3/include/soc/i2c_reg.h b/components/soc/esp32s3/register/soc/i2c_reg.h similarity index 99% rename from components/soc/esp32s3/include/soc/i2c_reg.h rename to components/soc/esp32s3/register/soc/i2c_reg.h index 5d19afa1c32..0585f139b32 100644 --- a/components/soc/esp32s3/include/soc/i2c_reg.h +++ b/components/soc/esp32s3/register/soc/i2c_reg.h @@ -1,16 +1,7 @@ -/** Copyright 2021 Espressif Systems (Shanghai) PTE LTD +/* + * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. + * SPDX-License-Identifier: Apache-2.0 */ #pragma once diff --git a/components/soc/esp32s3/include/soc/i2c_struct.h b/components/soc/esp32s3/register/soc/i2c_struct.h similarity index 98% rename from components/soc/esp32s3/include/soc/i2c_struct.h rename to components/soc/esp32s3/register/soc/i2c_struct.h index 807ffa508d1..fe3695f44fd 100644 --- a/components/soc/esp32s3/include/soc/i2c_struct.h +++ b/components/soc/esp32s3/register/soc/i2c_struct.h @@ -1,16 +1,7 @@ -/** Copyright 2021 Espressif Systems (Shanghai) CO LTD +/* + * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. + * SPDX-License-Identifier: Apache-2.0 */ #pragma once diff --git a/components/soc/esp32s3/include/soc/i2s_reg.h b/components/soc/esp32s3/register/soc/i2s_reg.h similarity index 98% rename from components/soc/esp32s3/include/soc/i2s_reg.h rename to components/soc/esp32s3/register/soc/i2s_reg.h index 3200bd25bc8..16293844343 100644 --- a/components/soc/esp32s3/include/soc/i2s_reg.h +++ b/components/soc/esp32s3/register/soc/i2s_reg.h @@ -7,7 +7,7 @@ #define _SOC_I2S_REG_H_ -#include "soc.h" +#include "soc/soc.h" #ifdef __cplusplus extern "C" { #endif @@ -151,7 +151,7 @@ MSB is received first..*/ #define I2S_RX_BIT_ORDER_S 18 /* I2S_RX_WS_IDLE_POL : R/W ;bitpos:[17] ;default: 1'h0 ; */ /*description: 0: WS should be 0 when receiving left channel data, and WS is 1in right channel. - 1: WS should be 1 when receiving left channel data, and WS is 0in right channe + 1: WS should be 1 when receiving left channel data, and WS is 0in right channel l. .*/ #define I2S_RX_WS_IDLE_POL (BIT(17)) #define I2S_RX_WS_IDLE_POL_M (BIT(17)) @@ -330,7 +330,7 @@ his bit will be cleared by hardware after update register done..*/ #define I2S_TX_UPDATE_S 8 /* I2S_TX_BIG_ENDIAN : R/W ;bitpos:[7] ;default: 1'b0 ; */ /*description: I2S Tx byte endian, 1: low addr value to high addr. 0: low addr with low addr v -alue..*/ +value..*/ #define I2S_TX_BIG_ENDIAN (BIT(7)) #define I2S_TX_BIG_ENDIAN_M (BIT(7)) #define I2S_TX_BIG_ENDIAN_V 0x1 @@ -530,7 +530,7 @@ I2S_RX_CLKM_DIV_YN1 is 1. .*/ #define I2S_RX_CLKM_DIV_YN1_V 0x1 #define I2S_RX_CLKM_DIV_YN1_S 27 /* I2S_RX_CLKM_DIV_X : R/W ;bitpos:[26:18] ;default: 9'h0 ; */ -/*description: For b <= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the valu +/*description: For b <= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value e of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1. .*/ #define I2S_RX_CLKM_DIV_X 0x000001FF #define I2S_RX_CLKM_DIV_X_M ((I2S_RX_CLKM_DIV_X_V)<<(I2S_RX_CLKM_DIV_X_S)) @@ -560,7 +560,7 @@ I2S_TX_CLKM_DIV_YN1 is 1. .*/ #define I2S_TX_CLKM_DIV_YN1_V 0x1 #define I2S_TX_CLKM_DIV_YN1_S 27 /* I2S_TX_CLKM_DIV_X : R/W ;bitpos:[26:18] ;default: 9'h0 ; */ -/*description: For b <= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the valu +/*description: For b <= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value e of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1. .*/ #define I2S_TX_CLKM_DIV_X 0x000001FF #define I2S_TX_CLKM_DIV_X_M ((I2S_TX_CLKM_DIV_X_V)<<(I2S_TX_CLKM_DIV_X_S)) @@ -747,56 +747,56 @@ T12_5[2:0]).*/ #define I2S_RX_TDM_CHAN8_EN_V 0x1 #define I2S_RX_TDM_CHAN8_EN_S 8 /* I2S_RX_TDM_PDM_CHAN7_EN : R/W ;bitpos:[7] ;default: 1'h1 ; */ -/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, jus +/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just t input 0 in this channel..*/ #define I2S_RX_TDM_PDM_CHAN7_EN (BIT(7)) #define I2S_RX_TDM_PDM_CHAN7_EN_M (BIT(7)) #define I2S_RX_TDM_PDM_CHAN7_EN_V 0x1 #define I2S_RX_TDM_PDM_CHAN7_EN_S 7 /* I2S_RX_TDM_PDM_CHAN6_EN : R/W ;bitpos:[6] ;default: 1'h1 ; */ -/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, jus +/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just t input 0 in this channel..*/ #define I2S_RX_TDM_PDM_CHAN6_EN (BIT(6)) #define I2S_RX_TDM_PDM_CHAN6_EN_M (BIT(6)) #define I2S_RX_TDM_PDM_CHAN6_EN_V 0x1 #define I2S_RX_TDM_PDM_CHAN6_EN_S 6 /* I2S_RX_TDM_PDM_CHAN5_EN : R/W ;bitpos:[5] ;default: 1'h1 ; */ -/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, jus +/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just t input 0 in this channel..*/ #define I2S_RX_TDM_PDM_CHAN5_EN (BIT(5)) #define I2S_RX_TDM_PDM_CHAN5_EN_M (BIT(5)) #define I2S_RX_TDM_PDM_CHAN5_EN_V 0x1 #define I2S_RX_TDM_PDM_CHAN5_EN_S 5 /* I2S_RX_TDM_PDM_CHAN4_EN : R/W ;bitpos:[4] ;default: 1'h1 ; */ -/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, jus +/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just t input 0 in this channel..*/ #define I2S_RX_TDM_PDM_CHAN4_EN (BIT(4)) #define I2S_RX_TDM_PDM_CHAN4_EN_M (BIT(4)) #define I2S_RX_TDM_PDM_CHAN4_EN_V 0x1 #define I2S_RX_TDM_PDM_CHAN4_EN_S 4 /* I2S_RX_TDM_PDM_CHAN3_EN : R/W ;bitpos:[3] ;default: 1'h1 ; */ -/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, jus +/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just t input 0 in this channel..*/ #define I2S_RX_TDM_PDM_CHAN3_EN (BIT(3)) #define I2S_RX_TDM_PDM_CHAN3_EN_M (BIT(3)) #define I2S_RX_TDM_PDM_CHAN3_EN_V 0x1 #define I2S_RX_TDM_PDM_CHAN3_EN_S 3 /* I2S_RX_TDM_PDM_CHAN2_EN : R/W ;bitpos:[2] ;default: 1'h1 ; */ -/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, jus +/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just t input 0 in this channel..*/ #define I2S_RX_TDM_PDM_CHAN2_EN (BIT(2)) #define I2S_RX_TDM_PDM_CHAN2_EN_M (BIT(2)) #define I2S_RX_TDM_PDM_CHAN2_EN_V 0x1 #define I2S_RX_TDM_PDM_CHAN2_EN_S 2 /* I2S_RX_TDM_PDM_CHAN1_EN : R/W ;bitpos:[1] ;default: 1'h1 ; */ -/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, jus +/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just t input 0 in this channel..*/ #define I2S_RX_TDM_PDM_CHAN1_EN (BIT(1)) #define I2S_RX_TDM_PDM_CHAN1_EN_M (BIT(1)) #define I2S_RX_TDM_PDM_CHAN1_EN_V 0x1 #define I2S_RX_TDM_PDM_CHAN1_EN_S 1 /* I2S_RX_TDM_PDM_CHAN0_EN : R/W ;bitpos:[0] ;default: 1'h1 ; */ -/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, jus +/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just t input 0 in this channel..*/ #define I2S_RX_TDM_PDM_CHAN0_EN (BIT(0)) #define I2S_RX_TDM_PDM_CHAN0_EN_M (BIT(0)) @@ -805,8 +805,8 @@ t input 0 in this channel..*/ #define I2S_TX_TDM_CTRL_REG(i) (REG_I2S_BASE(i) + 0x54) /* I2S_TX_TDM_SKIP_MSK_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */ -/*description: When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1) channels, a -nd only the data of the enabled channels is sent, then this bit should be set. C +/*description: When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1) channels, +and only the data of the enabled channels is sent, then this bit should be set. C lear it when all the data stored in DMA TX buffer is for enabled channels..*/ #define I2S_TX_TDM_SKIP_MSK_EN (BIT(20)) #define I2S_TX_TDM_SKIP_MSK_EN_M (BIT(20)) @@ -1041,8 +1041,8 @@ delay by neg edge. 3: not used..*/ #define I2S_LC_FIFO_TIMEOUT_ENA_V 0x1 #define I2S_LC_FIFO_TIMEOUT_ENA_S 11 /* I2S_LC_FIFO_TIMEOUT_SHIFT : R/W ;bitpos:[10:8] ;default: 3'b0 ; */ -/*description: The bits are used to scale tick counter threshold. The tick counter is reset whe -n counter value >= 88000/2^i2s_lc_fifo_timeout_shift.*/ +/*description: The bits are used to scale tick counter threshold. The tick counter is reset +when counter value >= 88000/2^i2s_lc_fifo_timeout_shift.*/ #define I2S_LC_FIFO_TIMEOUT_SHIFT 0x00000007 #define I2S_LC_FIFO_TIMEOUT_SHIFT_M ((I2S_LC_FIFO_TIMEOUT_SHIFT_V)<<(I2S_LC_FIFO_TIMEOUT_SHIFT_S)) #define I2S_LC_FIFO_TIMEOUT_SHIFT_V 0x7 diff --git a/components/soc/esp32s3/include/soc/i2s_struct.h b/components/soc/esp32s3/register/soc/i2s_struct.h similarity index 99% rename from components/soc/esp32s3/include/soc/i2s_struct.h rename to components/soc/esp32s3/register/soc/i2s_struct.h index 2ad9b84d512..c7500479b10 100644 --- a/components/soc/esp32s3/include/soc/i2s_struct.h +++ b/components/soc/esp32s3/register/soc/i2s_struct.h @@ -97,7 +97,7 @@ typedef volatile struct i2s_dev_s { uint32_t tx_mono_fst_vld : 1; /*1: The first channel data value is valid in I2S TX mono mode. 0: The second channel data value is valid in I2S TX mono mode.*/ uint32_t tx_pcm_conf : 2; /*I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &*/ uint32_t tx_pcm_bypass : 1; /*Set this bit to bypass Compress/Decompress module for transmitted data.*/ - uint32_t tx_stop_en : 1; /*Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy*/ + uint32_t tx_stop_en : 1; /*Set this bit to stop disable output BCK signal and WS signal when tx FIFO is empty*/ uint32_t reserved14 : 1; /* Reserved*/ uint32_t tx_left_align : 1; /*1: I2S TX left alignment mode. 0: I2S TX right alignment mode.*/ uint32_t tx_24_fill_en : 1; /*1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode*/ diff --git a/components/soc/esp32s3/include/soc/interrupt_core0_reg.h b/components/soc/esp32s3/register/soc/interrupt_core0_reg.h similarity index 98% rename from components/soc/esp32s3/include/soc/interrupt_core0_reg.h rename to components/soc/esp32s3/register/soc/interrupt_core0_reg.h index f686720be44..132bb9f98ed 100644 --- a/components/soc/esp32s3/include/soc/interrupt_core0_reg.h +++ b/components/soc/esp32s3/register/soc/interrupt_core0_reg.h @@ -1,21 +1,13 @@ -// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef _SOC_INTERRUPT_CORE0_REG_H_ #define _SOC_INTERRUPT_CORE0_REG_H_ -#include "soc.h" +#include "soc/soc.h" #ifdef __cplusplus extern "C" { #endif diff --git a/components/soc/esp32s3/include/soc/interrupt_core0_struct.h b/components/soc/esp32s3/register/soc/interrupt_core0_struct.h similarity index 98% rename from components/soc/esp32s3/include/soc/interrupt_core0_struct.h rename to components/soc/esp32s3/register/soc/interrupt_core0_struct.h index aa27462fb00..4a909495068 100644 --- a/components/soc/esp32s3/include/soc/interrupt_core0_struct.h +++ b/components/soc/esp32s3/register/soc/interrupt_core0_struct.h @@ -1,16 +1,8 @@ -// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef _SOC_INTERRUPT_CORE0_STRUCT_H_ #define _SOC_INTERRUPT_CORE0_STRUCT_H_ #include diff --git a/components/soc/esp32s3/include/soc/interrupt_core1_reg.h b/components/soc/esp32s3/register/soc/interrupt_core1_reg.h similarity index 98% rename from components/soc/esp32s3/include/soc/interrupt_core1_reg.h rename to components/soc/esp32s3/register/soc/interrupt_core1_reg.h index 82d77e2f0d1..854106dbf52 100644 --- a/components/soc/esp32s3/include/soc/interrupt_core1_reg.h +++ b/components/soc/esp32s3/register/soc/interrupt_core1_reg.h @@ -1,21 +1,13 @@ -// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef _SOC_INTERRUPT_CORE1_REG_H_ #define _SOC_INTERRUPT_CORE1_REG_H_ -#include "soc.h" +#include "soc/soc.h" #ifdef __cplusplus extern "C" { #endif diff --git a/components/soc/esp32s3/include/soc/interrupt_core1_struct.h b/components/soc/esp32s3/register/soc/interrupt_core1_struct.h similarity index 98% rename from components/soc/esp32s3/include/soc/interrupt_core1_struct.h rename to components/soc/esp32s3/register/soc/interrupt_core1_struct.h index d4dee29ae50..850cc4dc777 100644 --- a/components/soc/esp32s3/include/soc/interrupt_core1_struct.h +++ b/components/soc/esp32s3/register/soc/interrupt_core1_struct.h @@ -1,16 +1,8 @@ -// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef _SOC_INTERRUPT_CORE1_STRUCT_H_ #define _SOC_INTERRUPT_CORE1_STRUCT_H_ #include diff --git a/components/soc/esp32s3/include/soc/io_mux_reg.h b/components/soc/esp32s3/register/soc/io_mux_reg.h similarity index 99% rename from components/soc/esp32s3/include/soc/io_mux_reg.h rename to components/soc/esp32s3/register/soc/io_mux_reg.h index 3ca2cd04989..fa72d363064 100644 --- a/components/soc/esp32s3/include/soc/io_mux_reg.h +++ b/components/soc/esp32s3/register/soc/io_mux_reg.h @@ -5,7 +5,7 @@ */ #pragma once -#include "soc.h" +#include "soc/soc.h" /* The following are the bit fields for PERIPHS_IO_MUX_x_U registers */ /* Output enable in sleep mode */ diff --git a/components/soc/esp32s3/include/soc/lcd_cam_reg.h b/components/soc/esp32s3/register/soc/lcd_cam_reg.h similarity index 100% rename from components/soc/esp32s3/include/soc/lcd_cam_reg.h rename to components/soc/esp32s3/register/soc/lcd_cam_reg.h diff --git a/components/soc/esp32s3/include/soc/lcd_cam_struct.h b/components/soc/esp32s3/register/soc/lcd_cam_struct.h similarity index 100% rename from components/soc/esp32s3/include/soc/lcd_cam_struct.h rename to components/soc/esp32s3/register/soc/lcd_cam_struct.h diff --git a/components/soc/esp32s3/include/soc/ledc_reg.h b/components/soc/esp32s3/register/soc/ledc_reg.h similarity index 98% rename from components/soc/esp32s3/include/soc/ledc_reg.h rename to components/soc/esp32s3/register/soc/ledc_reg.h index 23f5a5f8899..1a4d70e2635 100644 --- a/components/soc/esp32s3/include/soc/ledc_reg.h +++ b/components/soc/esp32s3/register/soc/ledc_reg.h @@ -1,24 +1,16 @@ -// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #pragma once -#include "soc.h" +#include "soc/soc.h" #ifdef __cplusplus extern "C" { #endif -#include "soc.h" +#include "soc/soc.h" #define LEDC_LSCH0_CONF0_REG (DR_REG_LEDC_BASE + 0x0000) /* LEDC_OVF_CNT_RESET_ST_LSCH0 : RO ;bitpos:[17] ;default: 1'b0 ; */ diff --git a/components/soc/esp32s3/include/soc/ledc_struct.h b/components/soc/esp32s3/register/soc/ledc_struct.h similarity index 92% rename from components/soc/esp32s3/include/soc/ledc_struct.h rename to components/soc/esp32s3/register/soc/ledc_struct.h index 85cea78e582..c3e0765a400 100644 --- a/components/soc/esp32s3/include/soc/ledc_struct.h +++ b/components/soc/esp32s3/register/soc/ledc_struct.h @@ -1,16 +1,8 @@ -// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #pragma once #include diff --git a/components/soc/esp32s3/include/soc/mcpwm_reg.h b/components/soc/esp32s3/register/soc/mcpwm_reg.h similarity index 99% rename from components/soc/esp32s3/include/soc/mcpwm_reg.h rename to components/soc/esp32s3/register/soc/mcpwm_reg.h index 6a370aa6910..c8e749dac0c 100644 --- a/components/soc/esp32s3/include/soc/mcpwm_reg.h +++ b/components/soc/esp32s3/register/soc/mcpwm_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -921,7 +921,7 @@ extern "C" { #define MCPWM_DT0_RED_S 0 /** MCPWM_CARRIER0_CFG_REG register - * PWM generator 0 carrier enable and configuratoin + * PWM generator 0 carrier enable and configuration */ #define MCPWM_CARRIER0_CFG_REG(i) (DR_REG_MCPWM_BASE(i) + 0x64) /** MCPWM_CARRIER0_EN : R/W; bitpos: [0]; default: 0; @@ -1625,7 +1625,7 @@ extern "C" { #define MCPWM_DT1_RED_S 0 /** MCPWM_CARRIER1_CFG_REG register - * PWM generator 1 carrier enable and configuratoin + * PWM generator 1 carrier enable and configuration */ #define MCPWM_CARRIER1_CFG_REG(i) (DR_REG_MCPWM_BASE(i) + 0x9c) /** MCPWM_CARRIER1_EN : R/W; bitpos: [0]; default: 0; @@ -2328,7 +2328,7 @@ extern "C" { #define MCPWM_DT2_RED_S 0 /** MCPWM_CARRIER2_CFG_REG register - * PWM generator 2 carrier enable and configuratoin + * PWM generator 2 carrier enable and configuration */ #define MCPWM_CARRIER2_CFG_REG(i) (DR_REG_MCPWM_BASE(i) + 0xd4) /** MCPWM_CARRIER2_EN : R/W; bitpos: [0]; default: 0; @@ -2693,7 +2693,7 @@ extern "C" { #define MCPWM_CAP0_MODE_V 0x00000003U #define MCPWM_CAP0_MODE_S 1 /** MCPWM_CAP0_PRESCALE : R/W; bitpos: [10:3]; default: 0; - * Value of prescaling on possitive edge of CAP0. Prescale value = PWM_CAP0_PRESCALE + + * Value of prescaling on positive edge of CAP0. Prescale value = PWM_CAP0_PRESCALE + * 1 */ #define MCPWM_CAP0_PRESCALE 0x000000FFU @@ -2736,7 +2736,7 @@ extern "C" { #define MCPWM_CAP1_MODE_V 0x00000003U #define MCPWM_CAP1_MODE_S 1 /** MCPWM_CAP1_PRESCALE : R/W; bitpos: [10:3]; default: 0; - * Value of prescaling on possitive edge of CAP1. Prescale value = PWM_CAP1_PRESCALE + + * Value of prescaling on positive edge of CAP1. Prescale value = PWM_CAP1_PRESCALE + * 1 */ #define MCPWM_CAP1_PRESCALE 0x000000FFU @@ -2779,7 +2779,7 @@ extern "C" { #define MCPWM_CAP2_MODE_V 0x00000003U #define MCPWM_CAP2_MODE_S 1 /** MCPWM_CAP2_PRESCALE : R/W; bitpos: [10:3]; default: 0; - * Value of prescaling on possitive edge of CAP2. Prescale value = PWM_CAP2_PRESCALE + + * Value of prescaling on positive edge of CAP2. Prescale value = PWM_CAP2_PRESCALE + * 1 */ #define MCPWM_CAP2_PRESCALE 0x000000FFU diff --git a/components/soc/esp32s3/include/soc/mcpwm_struct.h b/components/soc/esp32s3/register/soc/mcpwm_struct.h similarity index 99% rename from components/soc/esp32s3/include/soc/mcpwm_struct.h rename to components/soc/esp32s3/register/soc/mcpwm_struct.h index e2f4d32eba9..9040142e67e 100644 --- a/components/soc/esp32s3/include/soc/mcpwm_struct.h +++ b/components/soc/esp32s3/register/soc/mcpwm_struct.h @@ -474,7 +474,7 @@ typedef union { } mcpwm_dt_red_cfg_reg_t; /** Type of carrier_cfg register - * PWM generator carrier enable and configuratoin + * PWM generator carrier enable and configuration */ typedef union { struct { @@ -746,7 +746,7 @@ typedef union { */ uint32_t capn_mode: 2; /** capn_prescale : R/W; bitpos: [10:3]; default: 0; - * Value of prescaling on possitive edge of CAPn. Prescale value = PWM_CAPn_PRESCALE + + * Value of prescaling on positive edge of CAPn. Prescale value = PWM_CAPn_PRESCALE + * 1 */ uint32_t capn_prescale: 8; diff --git a/components/soc/esp32s3/include/soc/pcnt_reg.h b/components/soc/esp32s3/register/soc/pcnt_reg.h similarity index 100% rename from components/soc/esp32s3/include/soc/pcnt_reg.h rename to components/soc/esp32s3/register/soc/pcnt_reg.h diff --git a/components/soc/esp32s3/include/soc/pcnt_struct.h b/components/soc/esp32s3/register/soc/pcnt_struct.h similarity index 100% rename from components/soc/esp32s3/include/soc/pcnt_struct.h rename to components/soc/esp32s3/register/soc/pcnt_struct.h diff --git a/components/soc/esp32s3/include/soc/peri_backup_reg.h b/components/soc/esp32s3/register/soc/peri_backup_reg.h similarity index 92% rename from components/soc/esp32s3/include/soc/peri_backup_reg.h rename to components/soc/esp32s3/register/soc/peri_backup_reg.h index 71907355b0c..b627104fc3b 100644 --- a/components/soc/esp32s3/include/soc/peri_backup_reg.h +++ b/components/soc/esp32s3/register/soc/peri_backup_reg.h @@ -1,21 +1,13 @@ -// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef _SOC_PERI_BACKUP_REG_H_ #define _SOC_PERI_BACKUP_REG_H_ -#include "soc.h" +#include "soc/soc.h" #ifdef __cplusplus extern "C" { #endif diff --git a/components/soc/esp32s3/include/soc/peri_backup_struct.h b/components/soc/esp32s3/register/soc/peri_backup_struct.h similarity index 85% rename from components/soc/esp32s3/include/soc/peri_backup_struct.h rename to components/soc/esp32s3/register/soc/peri_backup_struct.h index 20d6673f2ec..bc0563f7156 100644 --- a/components/soc/esp32s3/include/soc/peri_backup_struct.h +++ b/components/soc/esp32s3/register/soc/peri_backup_struct.h @@ -1,16 +1,8 @@ -// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef _SOC_PERI_BACKUP_STRUCT_H_ #define _SOC_PERI_BACKUP_STRUCT_H_ diff --git a/components/soc/esp32s3/include/soc/reg_base.h b/components/soc/esp32s3/register/soc/reg_base.h similarity index 100% rename from components/soc/esp32s3/include/soc/reg_base.h rename to components/soc/esp32s3/register/soc/reg_base.h diff --git a/components/soc/esp32s3/include/soc/rmt_reg.h b/components/soc/esp32s3/register/soc/rmt_reg.h similarity index 100% rename from components/soc/esp32s3/include/soc/rmt_reg.h rename to components/soc/esp32s3/register/soc/rmt_reg.h diff --git a/components/soc/esp32s3/include/soc/rmt_struct.h b/components/soc/esp32s3/register/soc/rmt_struct.h similarity index 100% rename from components/soc/esp32s3/include/soc/rmt_struct.h rename to components/soc/esp32s3/register/soc/rmt_struct.h diff --git a/components/soc/esp32s3/include/soc/rtc_cntl_reg.h b/components/soc/esp32s3/register/soc/rtc_cntl_reg.h similarity index 99% rename from components/soc/esp32s3/include/soc/rtc_cntl_reg.h rename to components/soc/esp32s3/register/soc/rtc_cntl_reg.h index 33e0fd40629..00958eb0dba 100644 --- a/components/soc/esp32s3/include/soc/rtc_cntl_reg.h +++ b/components/soc/esp32s3/register/soc/rtc_cntl_reg.h @@ -8,7 +8,7 @@ #define _SOC_RTC_CNTL_REG_H_ -#include "soc.h" +#include "soc/soc.h" #ifdef __cplusplus extern "C" { #endif diff --git a/components/soc/esp32s3/include/soc/rtc_cntl_struct.h b/components/soc/esp32s3/register/soc/rtc_cntl_struct.h similarity index 99% rename from components/soc/esp32s3/include/soc/rtc_cntl_struct.h rename to components/soc/esp32s3/register/soc/rtc_cntl_struct.h index 56e5f2d47e8..7ef1825ebdf 100644 --- a/components/soc/esp32s3/include/soc/rtc_cntl_struct.h +++ b/components/soc/esp32s3/register/soc/rtc_cntl_struct.h @@ -207,7 +207,7 @@ typedef volatile struct rtc_cntl_dev_s { uint32_t rtc_xtal32k_dead : 1; /*enable xtal32k_dead interrupt*/ uint32_t rtc_cocpu_trap : 1; /*enable cocpu trap interrupt*/ uint32_t rtc_touch_timeout : 1; /*enable touch timeout interrupt*/ - uint32_t rtc_glitch_det : 1; /*enbale gitch det interrupt*/ + uint32_t rtc_glitch_det : 1; /*enable gitch det interrupt*/ uint32_t rtc_touch_approach_loop_done : 1; uint32_t reserved21 : 11; }; @@ -565,7 +565,7 @@ typedef volatile struct rtc_cntl_dev_s { uint32_t swd_signal_width : 10; /*adjust signal width send to swd*/ uint32_t swd_rst_flag_clr : 1; /*reset swd reset flag*/ uint32_t swd_feed : 1; /*Sw feed swd*/ - uint32_t swd_disable : 1; /*disabel SWD*/ + uint32_t swd_disable : 1; /*disable SWD*/ uint32_t swd_auto_feed_en : 1; /*automatically feed swd when int comes*/ }; uint32_t val; @@ -689,7 +689,7 @@ typedef volatile struct rtc_cntl_dev_s { uint32_t xtal32k_clk_factor; union { struct { - uint32_t xtal32k_return_wait : 4; /*cycles to wait to return noral xtal 32k*/ + uint32_t xtal32k_return_wait : 4; /*cycles to wait to return normal xtal 32k*/ uint32_t xtal32k_restart_wait : 16; /*cycles to wait to repower on xtal 32k*/ uint32_t xtal32k_wdt_timeout : 8; /*If no clock detected for this amount of time*/ uint32_t xtal32k_stable_thres : 4; /*if restarted xtal32k period is smaller than this*/ @@ -894,7 +894,7 @@ typedef volatile struct rtc_cntl_dev_s { uint32_t rtc_xtal32k_dead_w1ts : 1; /*enable xtal32k_dead interrupt*/ uint32_t rtc_cocpu_trap_w1ts : 1; /*enable cocpu trap interrupt*/ uint32_t rtc_touch_timeout_w1ts : 1; /*enable touch timeout interrupt*/ - uint32_t rtc_glitch_det_w1ts : 1; /*enbale gitch det interrupt*/ + uint32_t rtc_glitch_det_w1ts : 1; /*enable gitch det interrupt*/ uint32_t rtc_touch_approach_loop_done_w1ts: 1; uint32_t reserved21 : 11; }; @@ -921,7 +921,7 @@ typedef volatile struct rtc_cntl_dev_s { uint32_t rtc_xtal32k_dead_w1tc : 1; /*enable xtal32k_dead interrupt*/ uint32_t rtc_cocpu_trap_w1tc : 1; /*enable cocpu trap interrupt*/ uint32_t rtc_touch_timeout_w1tc : 1; /*enable touch timeout interrupt*/ - uint32_t rtc_glitch_det_w1tc : 1; /*enbale gitch det interrupt*/ + uint32_t rtc_glitch_det_w1tc : 1; /*enable gitch det interrupt*/ uint32_t rtc_touch_approach_loop_done_w1tc: 1; uint32_t reserved21 : 11; }; diff --git a/components/soc/esp32s3/include/soc/rtc_i2c_reg.h b/components/soc/esp32s3/register/soc/rtc_i2c_reg.h similarity index 98% rename from components/soc/esp32s3/include/soc/rtc_i2c_reg.h rename to components/soc/esp32s3/register/soc/rtc_i2c_reg.h index 322f28192e2..ba10ed02330 100644 --- a/components/soc/esp32s3/include/soc/rtc_i2c_reg.h +++ b/components/soc/esp32s3/register/soc/rtc_i2c_reg.h @@ -1,16 +1,7 @@ -/** Copyright 2021 Espressif Systems (Shanghai) PTE LTD +/* + * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. + * SPDX-License-Identifier: Apache-2.0 */ #pragma once diff --git a/components/soc/esp32s3/include/soc/rtc_i2c_struct.h b/components/soc/esp32s3/register/soc/rtc_i2c_struct.h similarity index 96% rename from components/soc/esp32s3/include/soc/rtc_i2c_struct.h rename to components/soc/esp32s3/register/soc/rtc_i2c_struct.h index 2bac2fa5804..0d42c68906d 100644 --- a/components/soc/esp32s3/include/soc/rtc_i2c_struct.h +++ b/components/soc/esp32s3/register/soc/rtc_i2c_struct.h @@ -1,16 +1,7 @@ -/** Copyright 2021 Espressif Systems (Shanghai) PTE LTD +/* + * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. + * SPDX-License-Identifier: Apache-2.0 */ #pragma once diff --git a/components/soc/esp32s3/include/soc/rtc_io_reg.h b/components/soc/esp32s3/register/soc/rtc_io_reg.h similarity index 98% rename from components/soc/esp32s3/include/soc/rtc_io_reg.h rename to components/soc/esp32s3/register/soc/rtc_io_reg.h index a324329117a..0ce66dde613 100644 --- a/components/soc/esp32s3/include/soc/rtc_io_reg.h +++ b/components/soc/esp32s3/register/soc/rtc_io_reg.h @@ -1,21 +1,13 @@ -// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef _SOC_RTC_IO_REG_H_ #define _SOC_RTC_IO_REG_H_ -#include "soc.h" +#include "soc/soc.h" #ifdef __cplusplus extern "C" { #endif @@ -109,8 +101,8 @@ extern "C" { #define RTC_GPIO_PIN0_WAKEUP_ENABLE_S 10 /* RTC_GPIO_PIN0_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ /*description: if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set -to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low leve -l trigger, if set to 5: high level trigger.*/ +to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low +level trigger, if set to 5: high level trigger.*/ #define RTC_GPIO_PIN0_INT_TYPE 0x00000007 #define RTC_GPIO_PIN0_INT_TYPE_M ((RTC_GPIO_PIN0_INT_TYPE_V)<<(RTC_GPIO_PIN0_INT_TYPE_S)) #define RTC_GPIO_PIN0_INT_TYPE_V 0x7 @@ -131,8 +123,8 @@ l trigger, if set to 5: high level trigger.*/ #define RTC_GPIO_PIN1_WAKEUP_ENABLE_S 10 /* RTC_GPIO_PIN1_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ /*description: if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set -to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low leve -l trigger, if set to 5: high level trigger.*/ +to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low +level trigger, if set to 5: high level trigger.*/ #define RTC_GPIO_PIN1_INT_TYPE 0x00000007 #define RTC_GPIO_PIN1_INT_TYPE_M ((RTC_GPIO_PIN1_INT_TYPE_V)<<(RTC_GPIO_PIN1_INT_TYPE_S)) #define RTC_GPIO_PIN1_INT_TYPE_V 0x7 @@ -153,8 +145,8 @@ l trigger, if set to 5: high level trigger.*/ #define RTC_GPIO_PIN2_WAKEUP_ENABLE_S 10 /* RTC_GPIO_PIN2_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ /*description: if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set -to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low leve -l trigger, if set to 5: high level trigger.*/ +to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low +level trigger, if set to 5: high level trigger.*/ #define RTC_GPIO_PIN2_INT_TYPE 0x00000007 #define RTC_GPIO_PIN2_INT_TYPE_M ((RTC_GPIO_PIN2_INT_TYPE_V)<<(RTC_GPIO_PIN2_INT_TYPE_S)) #define RTC_GPIO_PIN2_INT_TYPE_V 0x7 @@ -175,8 +167,8 @@ l trigger, if set to 5: high level trigger.*/ #define RTC_GPIO_PIN3_WAKEUP_ENABLE_S 10 /* RTC_GPIO_PIN3_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ /*description: if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set -to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low leve -l trigger, if set to 5: high level trigger.*/ +to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low +level trigger, if set to 5: high level trigger.*/ #define RTC_GPIO_PIN3_INT_TYPE 0x00000007 #define RTC_GPIO_PIN3_INT_TYPE_M ((RTC_GPIO_PIN3_INT_TYPE_V)<<(RTC_GPIO_PIN3_INT_TYPE_S)) #define RTC_GPIO_PIN3_INT_TYPE_V 0x7 @@ -197,8 +189,8 @@ l trigger, if set to 5: high level trigger.*/ #define RTC_GPIO_PIN4_WAKEUP_ENABLE_S 10 /* RTC_GPIO_PIN4_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ /*description: if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set -to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low leve -l trigger, if set to 5: high level trigger.*/ +to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low +level trigger, if set to 5: high level trigger.*/ #define RTC_GPIO_PIN4_INT_TYPE 0x00000007 #define RTC_GPIO_PIN4_INT_TYPE_M ((RTC_GPIO_PIN4_INT_TYPE_V)<<(RTC_GPIO_PIN4_INT_TYPE_S)) #define RTC_GPIO_PIN4_INT_TYPE_V 0x7 @@ -219,8 +211,8 @@ l trigger, if set to 5: high level trigger.*/ #define RTC_GPIO_PIN5_WAKEUP_ENABLE_S 10 /* RTC_GPIO_PIN5_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ /*description: if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set -to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low leve -l trigger, if set to 5: high level trigger.*/ +to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low +level trigger, if set to 5: high level trigger.*/ #define RTC_GPIO_PIN5_INT_TYPE 0x00000007 #define RTC_GPIO_PIN5_INT_TYPE_M ((RTC_GPIO_PIN5_INT_TYPE_V)<<(RTC_GPIO_PIN5_INT_TYPE_S)) #define RTC_GPIO_PIN5_INT_TYPE_V 0x7 @@ -241,8 +233,8 @@ l trigger, if set to 5: high level trigger.*/ #define RTC_GPIO_PIN6_WAKEUP_ENABLE_S 10 /* RTC_GPIO_PIN6_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ /*description: if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set -to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low leve -l trigger, if set to 5: high level trigger.*/ +to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low +level trigger, if set to 5: high level trigger.*/ #define RTC_GPIO_PIN6_INT_TYPE 0x00000007 #define RTC_GPIO_PIN6_INT_TYPE_M ((RTC_GPIO_PIN6_INT_TYPE_V)<<(RTC_GPIO_PIN6_INT_TYPE_S)) #define RTC_GPIO_PIN6_INT_TYPE_V 0x7 @@ -263,8 +255,8 @@ l trigger, if set to 5: high level trigger.*/ #define RTC_GPIO_PIN7_WAKEUP_ENABLE_S 10 /* RTC_GPIO_PIN7_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ /*description: if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set -to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low leve -l trigger, if set to 5: high level trigger.*/ +to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low +level trigger, if set to 5: high level trigger.*/ #define RTC_GPIO_PIN7_INT_TYPE 0x00000007 #define RTC_GPIO_PIN7_INT_TYPE_M ((RTC_GPIO_PIN7_INT_TYPE_V)<<(RTC_GPIO_PIN7_INT_TYPE_S)) #define RTC_GPIO_PIN7_INT_TYPE_V 0x7 @@ -285,8 +277,8 @@ l trigger, if set to 5: high level trigger.*/ #define RTC_GPIO_PIN8_WAKEUP_ENABLE_S 10 /* RTC_GPIO_PIN8_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ /*description: if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set -to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low leve -l trigger, if set to 5: high level trigger.*/ +to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low +level trigger, if set to 5: high level trigger.*/ #define RTC_GPIO_PIN8_INT_TYPE 0x00000007 #define RTC_GPIO_PIN8_INT_TYPE_M ((RTC_GPIO_PIN8_INT_TYPE_V)<<(RTC_GPIO_PIN8_INT_TYPE_S)) #define RTC_GPIO_PIN8_INT_TYPE_V 0x7 @@ -307,8 +299,8 @@ l trigger, if set to 5: high level trigger.*/ #define RTC_GPIO_PIN9_WAKEUP_ENABLE_S 10 /* RTC_GPIO_PIN9_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ /*description: if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set -to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low leve -l trigger, if set to 5: high level trigger.*/ +to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low +level trigger, if set to 5: high level trigger.*/ #define RTC_GPIO_PIN9_INT_TYPE 0x00000007 #define RTC_GPIO_PIN9_INT_TYPE_M ((RTC_GPIO_PIN9_INT_TYPE_V)<<(RTC_GPIO_PIN9_INT_TYPE_S)) #define RTC_GPIO_PIN9_INT_TYPE_V 0x7 @@ -329,8 +321,8 @@ l trigger, if set to 5: high level trigger.*/ #define RTC_GPIO_PIN10_WAKEUP_ENABLE_S 10 /* RTC_GPIO_PIN10_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ /*description: if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set -to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low leve -l trigger, if set to 5: high level trigger.*/ +to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low +level trigger, if set to 5: high level trigger.*/ #define RTC_GPIO_PIN10_INT_TYPE 0x00000007 #define RTC_GPIO_PIN10_INT_TYPE_M ((RTC_GPIO_PIN10_INT_TYPE_V)<<(RTC_GPIO_PIN10_INT_TYPE_S)) #define RTC_GPIO_PIN10_INT_TYPE_V 0x7 @@ -351,8 +343,8 @@ l trigger, if set to 5: high level trigger.*/ #define RTC_GPIO_PIN11_WAKEUP_ENABLE_S 10 /* RTC_GPIO_PIN11_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ /*description: if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set -to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low leve -l trigger, if set to 5: high level trigger.*/ +to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low +level trigger, if set to 5: high level trigger.*/ #define RTC_GPIO_PIN11_INT_TYPE 0x00000007 #define RTC_GPIO_PIN11_INT_TYPE_M ((RTC_GPIO_PIN11_INT_TYPE_V)<<(RTC_GPIO_PIN11_INT_TYPE_S)) #define RTC_GPIO_PIN11_INT_TYPE_V 0x7 @@ -373,8 +365,8 @@ l trigger, if set to 5: high level trigger.*/ #define RTC_GPIO_PIN12_WAKEUP_ENABLE_S 10 /* RTC_GPIO_PIN12_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ /*description: if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set -to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low leve -l trigger, if set to 5: high level trigger.*/ +to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low +level trigger, if set to 5: high level trigger.*/ #define RTC_GPIO_PIN12_INT_TYPE 0x00000007 #define RTC_GPIO_PIN12_INT_TYPE_M ((RTC_GPIO_PIN12_INT_TYPE_V)<<(RTC_GPIO_PIN12_INT_TYPE_S)) #define RTC_GPIO_PIN12_INT_TYPE_V 0x7 @@ -395,8 +387,8 @@ l trigger, if set to 5: high level trigger.*/ #define RTC_GPIO_PIN13_WAKEUP_ENABLE_S 10 /* RTC_GPIO_PIN13_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ /*description: if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set -to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low leve -l trigger, if set to 5: high level trigger.*/ +to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low +level trigger, if set to 5: high level trigger.*/ #define RTC_GPIO_PIN13_INT_TYPE 0x00000007 #define RTC_GPIO_PIN13_INT_TYPE_M ((RTC_GPIO_PIN13_INT_TYPE_V)<<(RTC_GPIO_PIN13_INT_TYPE_S)) #define RTC_GPIO_PIN13_INT_TYPE_V 0x7 @@ -417,8 +409,8 @@ l trigger, if set to 5: high level trigger.*/ #define RTC_GPIO_PIN14_WAKEUP_ENABLE_S 10 /* RTC_GPIO_PIN14_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ /*description: if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set -to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low leve -l trigger, if set to 5: high level trigger.*/ +to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low +level trigger, if set to 5: high level trigger.*/ #define RTC_GPIO_PIN14_INT_TYPE 0x00000007 #define RTC_GPIO_PIN14_INT_TYPE_M ((RTC_GPIO_PIN14_INT_TYPE_V)<<(RTC_GPIO_PIN14_INT_TYPE_S)) #define RTC_GPIO_PIN14_INT_TYPE_V 0x7 @@ -439,8 +431,8 @@ l trigger, if set to 5: high level trigger.*/ #define RTC_GPIO_PIN15_WAKEUP_ENABLE_S 10 /* RTC_GPIO_PIN15_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ /*description: if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set -to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low leve -l trigger, if set to 5: high level trigger.*/ +to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low +level trigger, if set to 5: high level trigger.*/ #define RTC_GPIO_PIN15_INT_TYPE 0x00000007 #define RTC_GPIO_PIN15_INT_TYPE_M ((RTC_GPIO_PIN15_INT_TYPE_V)<<(RTC_GPIO_PIN15_INT_TYPE_S)) #define RTC_GPIO_PIN15_INT_TYPE_V 0x7 @@ -461,8 +453,8 @@ l trigger, if set to 5: high level trigger.*/ #define RTC_GPIO_PIN16_WAKEUP_ENABLE_S 10 /* RTC_GPIO_PIN16_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ /*description: if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set -to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low leve -l trigger, if set to 5: high level trigger.*/ +to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low +level trigger, if set to 5: high level trigger.*/ #define RTC_GPIO_PIN16_INT_TYPE 0x00000007 #define RTC_GPIO_PIN16_INT_TYPE_M ((RTC_GPIO_PIN16_INT_TYPE_V)<<(RTC_GPIO_PIN16_INT_TYPE_S)) #define RTC_GPIO_PIN16_INT_TYPE_V 0x7 @@ -483,8 +475,8 @@ l trigger, if set to 5: high level trigger.*/ #define RTC_GPIO_PIN17_WAKEUP_ENABLE_S 10 /* RTC_GPIO_PIN17_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ /*description: if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set -to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low leve -l trigger, if set to 5: high level trigger.*/ +to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low +level trigger, if set to 5: high level trigger.*/ #define RTC_GPIO_PIN17_INT_TYPE 0x00000007 #define RTC_GPIO_PIN17_INT_TYPE_M ((RTC_GPIO_PIN17_INT_TYPE_V)<<(RTC_GPIO_PIN17_INT_TYPE_S)) #define RTC_GPIO_PIN17_INT_TYPE_V 0x7 @@ -505,8 +497,8 @@ l trigger, if set to 5: high level trigger.*/ #define RTC_GPIO_PIN18_WAKEUP_ENABLE_S 10 /* RTC_GPIO_PIN18_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ /*description: if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set -to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low leve -l trigger, if set to 5: high level trigger.*/ +to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low +level trigger, if set to 5: high level trigger.*/ #define RTC_GPIO_PIN18_INT_TYPE 0x00000007 #define RTC_GPIO_PIN18_INT_TYPE_M ((RTC_GPIO_PIN18_INT_TYPE_V)<<(RTC_GPIO_PIN18_INT_TYPE_S)) #define RTC_GPIO_PIN18_INT_TYPE_V 0x7 @@ -527,8 +519,8 @@ l trigger, if set to 5: high level trigger.*/ #define RTC_GPIO_PIN19_WAKEUP_ENABLE_S 10 /* RTC_GPIO_PIN19_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ /*description: if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set -to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low leve -l trigger, if set to 5: high level trigger.*/ +to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low +level trigger, if set to 5: high level trigger.*/ #define RTC_GPIO_PIN19_INT_TYPE 0x00000007 #define RTC_GPIO_PIN19_INT_TYPE_M ((RTC_GPIO_PIN19_INT_TYPE_V)<<(RTC_GPIO_PIN19_INT_TYPE_S)) #define RTC_GPIO_PIN19_INT_TYPE_V 0x7 @@ -549,8 +541,8 @@ l trigger, if set to 5: high level trigger.*/ #define RTC_GPIO_PIN20_WAKEUP_ENABLE_S 10 /* RTC_GPIO_PIN20_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ /*description: if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set -to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low leve -l trigger, if set to 5: high level trigger.*/ +to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low +level trigger, if set to 5: high level trigger.*/ #define RTC_GPIO_PIN20_INT_TYPE 0x00000007 #define RTC_GPIO_PIN20_INT_TYPE_M ((RTC_GPIO_PIN20_INT_TYPE_V)<<(RTC_GPIO_PIN20_INT_TYPE_S)) #define RTC_GPIO_PIN20_INT_TYPE_V 0x7 @@ -571,8 +563,8 @@ l trigger, if set to 5: high level trigger.*/ #define RTC_GPIO_PIN21_WAKEUP_ENABLE_S 10 /* RTC_GPIO_PIN21_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ /*description: if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set -to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low leve -l trigger, if set to 5: high level trigger.*/ +to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low +level trigger, if set to 5: high level trigger.*/ #define RTC_GPIO_PIN21_INT_TYPE 0x00000007 #define RTC_GPIO_PIN21_INT_TYPE_M ((RTC_GPIO_PIN21_INT_TYPE_V)<<(RTC_GPIO_PIN21_INT_TYPE_S)) #define RTC_GPIO_PIN21_INT_TYPE_V 0x7 diff --git a/components/soc/esp32s3/include/soc/rtc_io_struct.h b/components/soc/esp32s3/register/soc/rtc_io_struct.h similarity index 95% rename from components/soc/esp32s3/include/soc/rtc_io_struct.h rename to components/soc/esp32s3/register/soc/rtc_io_struct.h index 1154be038b3..d91204e18da 100644 --- a/components/soc/esp32s3/include/soc/rtc_io_struct.h +++ b/components/soc/esp32s3/register/soc/rtc_io_struct.h @@ -1,16 +1,8 @@ -// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef _SOC_RTC_IO_STRUCT_H_ #define _SOC_RTC_IO_STRUCT_H_ diff --git a/components/soc/esp32s3/include/soc/sdmmc_reg.h b/components/soc/esp32s3/register/soc/sdmmc_reg.h similarity index 85% rename from components/soc/esp32s3/include/soc/sdmmc_reg.h rename to components/soc/esp32s3/register/soc/sdmmc_reg.h index 41c191eb68f..4d0a141781d 100644 --- a/components/soc/esp32s3/include/soc/sdmmc_reg.h +++ b/components/soc/esp32s3/register/soc/sdmmc_reg.h @@ -1,19 +1,11 @@ -// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #pragma once -#include "soc.h" +#include "soc/soc.h" #define SDMMC_CTRL_REG (DR_REG_SDMMC_BASE + 0x00) #define SDMMC_PWREN_REG (DR_REG_SDMMC_BASE + 0x04) diff --git a/components/soc/esp32s3/include/soc/sdmmc_struct.h b/components/soc/esp32s3/register/soc/sdmmc_struct.h similarity index 100% rename from components/soc/esp32s3/include/soc/sdmmc_struct.h rename to components/soc/esp32s3/register/soc/sdmmc_struct.h diff --git a/components/soc/esp32s3/include/soc/sens_reg.h b/components/soc/esp32s3/register/soc/sens_reg.h similarity index 99% rename from components/soc/esp32s3/include/soc/sens_reg.h rename to components/soc/esp32s3/register/soc/sens_reg.h index ca14d862dc9..350804cf20e 100644 --- a/components/soc/esp32s3/include/soc/sens_reg.h +++ b/components/soc/esp32s3/register/soc/sens_reg.h @@ -7,7 +7,7 @@ #define _SOC_SENS_REG_H_ -#include "soc.h" +#include "soc/soc.h" #ifdef __cplusplus extern "C" { #endif diff --git a/components/soc/esp32s3/include/soc/sens_struct.h b/components/soc/esp32s3/register/soc/sens_struct.h similarity index 100% rename from components/soc/esp32s3/include/soc/sens_struct.h rename to components/soc/esp32s3/register/soc/sens_struct.h diff --git a/components/soc/esp32s3/include/soc/sensitive_reg.h b/components/soc/esp32s3/register/soc/sensitive_reg.h similarity index 99% rename from components/soc/esp32s3/include/soc/sensitive_reg.h rename to components/soc/esp32s3/register/soc/sensitive_reg.h index a3393c5c056..3c17e73cce0 100644 --- a/components/soc/esp32s3/include/soc/sensitive_reg.h +++ b/components/soc/esp32s3/register/soc/sensitive_reg.h @@ -1,21 +1,13 @@ -// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef _SOC_SENSITIVE_REG_H_ #define _SOC_SENSITIVE_REG_H_ -#include "soc.h" +#include "soc/soc.h" #ifdef __cplusplus extern "C" { #endif diff --git a/components/soc/esp32s3/include/soc/sensitive_struct.h b/components/soc/esp32s3/register/soc/sensitive_struct.h similarity index 99% rename from components/soc/esp32s3/include/soc/sensitive_struct.h rename to components/soc/esp32s3/register/soc/sensitive_struct.h index e9919cb0a69..c6102c055b5 100644 --- a/components/soc/esp32s3/include/soc/sensitive_struct.h +++ b/components/soc/esp32s3/register/soc/sensitive_struct.h @@ -1,16 +1,8 @@ -// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef _SOC_SENSITIVE_STRUCT_H_ #define _SOC_SENSITIVE_STRUCT_H_ diff --git a/components/soc/esp32s3/include/soc/spi_mem_reg.h b/components/soc/esp32s3/register/soc/spi_mem_reg.h similarity index 98% rename from components/soc/esp32s3/include/soc/spi_mem_reg.h rename to components/soc/esp32s3/register/soc/spi_mem_reg.h index aa4639ed8d8..16a8ec5f9c5 100644 --- a/components/soc/esp32s3/include/soc/spi_mem_reg.h +++ b/components/soc/esp32s3/register/soc/spi_mem_reg.h @@ -1,21 +1,13 @@ -// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef _SOC_SPI_MEM_REG_H_ #define _SOC_SPI_MEM_REG_H_ -#include "soc.h" +#include "soc/soc.h" #ifdef __cplusplus extern "C" { #endif @@ -209,14 +201,14 @@ QUAD or SPI_MEM_FREAD_DUAL is set..*/ #define SPI_MEM_FASTRD_MODE_V 0x1 #define SPI_MEM_FASTRD_MODE_S 13 /* SPI_MEM_TX_CRC_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disabl +/*description: For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disable e.*/ #define SPI_MEM_TX_CRC_EN (BIT(11)) #define SPI_MEM_TX_CRC_EN_M (BIT(11)) #define SPI_MEM_TX_CRC_EN_V 0x1 #define SPI_MEM_TX_CRC_EN_S 11 /* SPI_MEM_FCS_CRC_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: For SPI1, initialize crc32 module before writing encrypted data to flash. Activ +/*description: For SPI1, initialize crc32 module before writing encrypted data to flash. Active e low..*/ #define SPI_MEM_FCS_CRC_EN (BIT(10)) #define SPI_MEM_FCS_CRC_EN_M (BIT(10)) @@ -826,8 +818,8 @@ tive 1: SPI_CLK is delayed one cycle after CS inactive 2: SPI_CLK is delayed two #define SPI_MEM_SRAM_DRD_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0x48) /* SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN : R/W ;bitpos:[31:28] ;default: 4'h0 ; */ -/*description: When SPI0 reads Ext_RAM, it is the length in bits of CMD phase. The register val -ue shall be (bit_num-1)..*/ +/*description: When SPI0 reads Ext_RAM, it is the length in bits of CMD phase. The register +value shall be (bit_num-1)..*/ #define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN 0x0000000F #define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_M ((SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_V)<<(SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_S)) #define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_V 0xF @@ -1072,8 +1064,8 @@ ES command is sent..*/ #define SPI_MEM_FLASH_PER_WAIT_EN_V 0x1 #define SPI_MEM_FLASH_PER_WAIT_EN_S 2 /* SPI_MEM_FLASH_PES : R/W/SS/SC ;bitpos:[1] ;default: 1'b0 ; */ -/*description: program erase suspend bit, program erase suspend operation will be triggered whe -n the bit is set. The bit will be cleared once the operation done.1: enable 0: d +/*description: program erase suspend bit, program erase suspend operation will be triggered +when the bit is set. The bit will be cleared once the operation done.1: enable 0: d isable. .*/ #define SPI_MEM_FLASH_PES (BIT(1)) #define SPI_MEM_FLASH_PES_M (BIT(1)) @@ -1166,7 +1158,7 @@ PI_MEM_TIMING_CALI bit is set..*/ #define SPI_MEM_EXTRA_DUMMY_CYCLELEN_V 0x7 #define SPI_MEM_EXTRA_DUMMY_CYCLELEN_S 2 /* SPI_MEM_TIMING_CALI : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: Set this bit to add extra SPI_CLK cycles in DUMMY phase for all reading operatio +/*description: Set this bit to add extra SPI_CLK cycles in DUMMY phase for all reading operation ns..*/ #define SPI_MEM_TIMING_CALI (BIT(1)) #define SPI_MEM_TIMING_CALI_M (BIT(1)) @@ -1174,7 +1166,7 @@ ns..*/ #define SPI_MEM_TIMING_CALI_S 1 /* SPI_MEM_TIMING_CLK_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ /*description: Set this bit to power on HCLK. When PLL is powered on, the frequency of HCLK equ -als to that of PLL. Otherwise, the frequency equals to that of XTAL..*/ +also to that of PLL. Otherwise, the frequency equals to that of XTAL..*/ #define SPI_MEM_TIMING_CLK_ENA (BIT(0)) #define SPI_MEM_TIMING_CLK_ENA_M (BIT(0)) #define SPI_MEM_TIMING_CLK_ENA_V 0x1 @@ -1245,8 +1237,8 @@ cles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge..*/ /*description: SPI_HD input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCL K positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_ -MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK neg -ative edge. 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and +MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK +nagetive edge. 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN$n_NUM+1) cyc les at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge..*/ #define SPI_MEM_DIN3_MODE 0x00000007 @@ -1257,8 +1249,8 @@ les at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge..*/ /*description: SPI_WP input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCL K positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_ -MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK neg -ative edge. 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and +MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK +nagetive edge. 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN$n_NUM+1) cyc les at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge..*/ #define SPI_MEM_DIN2_MODE 0x00000007 @@ -1420,7 +1412,7 @@ esses to Ext_RAM. Active when SPI_SMEM_TIMING_CALI bit is set..*/ #define SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_V 0x7 #define SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_S 2 /* SPI_MEM_SPI_SMEM_TIMING_CALI : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: Set this bit to add extra SPI_CLK cycles in DUMMY phase for all reading operatio +/*description: Set this bit to add extra SPI_CLK cycles in DUMMY phase for all reading operation ns..*/ #define SPI_MEM_SPI_SMEM_TIMING_CALI (BIT(1)) #define SPI_MEM_SPI_SMEM_TIMING_CALI_M (BIT(1)) @@ -1428,7 +1420,7 @@ ns..*/ #define SPI_MEM_SPI_SMEM_TIMING_CALI_S 1 /* SPI_MEM_SPI_SMEM_TIMING_CLK_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ /*description: Set this bit to power on HCLK. When PLL is powered on, the frequency of HCLK equ -als to that of PLL. Otherwise, the frequency equals to that of XTAL..*/ +also to that of PLL. Otherwise, the frequency equals to that of XTAL..*/ #define SPI_MEM_SPI_SMEM_TIMING_CLK_ENA (BIT(0)) #define SPI_MEM_SPI_SMEM_TIMING_CLK_ENA_M (BIT(0)) #define SPI_MEM_SPI_SMEM_TIMING_CLK_ENA_V 0x1 @@ -1524,8 +1516,8 @@ and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN$n_NUM+1 at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HC LK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI _SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK n -egative edge. 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge a -nd one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN$n_NUM+1) +egative edge. 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge +and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge..*/ #define SPI_MEM_SPI_SMEM_DIN1_MODE 0x00000007 #define SPI_MEM_SPI_SMEM_DIN1_MODE_M ((SPI_MEM_SPI_SMEM_DIN1_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN1_MODE_S)) @@ -1536,8 +1528,8 @@ nd one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN$n_NUM+1) at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HC LK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI _SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK n -egative edge. 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge a -nd one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN$n_NUM+1) +egative edge. 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge +and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge..*/ #define SPI_MEM_SPI_SMEM_DIN0_MODE 0x00000007 #define SPI_MEM_SPI_SMEM_DIN0_MODE_M ((SPI_MEM_SPI_SMEM_DIN0_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN0_MODE_S)) @@ -1708,8 +1700,8 @@ INT_CLR bit..*/ #define SPI_MEM_ECC_BYTE_ERR_V 0x1 #define SPI_MEM_ECC_BYTE_ERR_S 16 /* SPI_MEM_ECC_CHK_ERR_BIT : R/SS/WTC ;bitpos:[15:13] ;default: 3'd0 ; */ -/*description: When SPI_MEM_ECC_BYTE_ERR is set, these bits show the error bit number of ECC by -te..*/ +/*description: When SPI_MEM_ECC_BYTE_ERR is set, these bits show the error bit number of ECC +byte..*/ #define SPI_MEM_ECC_CHK_ERR_BIT 0x00000007 #define SPI_MEM_ECC_CHK_ERR_BIT_M ((SPI_MEM_ECC_CHK_ERR_BIT_V)<<(SPI_MEM_ECC_CHK_ERR_BIT_S)) #define SPI_MEM_ECC_CHK_ERR_BIT_V 0x7 @@ -2126,7 +2118,7 @@ or times of SPI0/1 ECC read flash are equal or bigger than APB_CTRL_ECC_ERR_INT_ NUM. When APB_CTRL_FECC_ERR_INT_EN is cleared and APB_CTRL_SECC_ERR_INT_EN is s et, this bit is triggered when the error times of SPI0/1 ECC read external RAM a re equal or bigger than APB_CTRL_ECC_ERR_INT_NUM. When APB_CTRL_FECC_ERR_INT_EN -and APB_CTRL_SECC_ERR_INT_EN are set, this bit is triggered when the total erro +and APB_CTRL_SECC_ERR_INT_EN are set, this bit is triggered when the total error r times of SPI0/1 ECC read external RAM and flash are equal or bigger than APB_C TRL_ECC_ERR_INT_NUM. When APB_CTRL_FECC_ERR_INT_EN and APB_CTRL_SECC_ERR_INT_EN are cleared, this bit will not be triggered..*/ @@ -2136,7 +2128,7 @@ TRL_ECC_ERR_INT_NUM. When APB_CTRL_FECC_ERR_INT_EN and APB_CTRL_SECC_ERR_INT_EN #define SPI_MEM_ECC_ERR_INT_RAW_S 4 /* SPI_MEM_BROWN_OUT_INT_RAW : R/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */ /*description: The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that -chip is loosing power and RTC module sends out brown out close flash request to +chip is losing power and RTC module sends out brown out close flash request to SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered and MSPI returns to idle state. 0: Others..*/ #define SPI_MEM_BROWN_OUT_INT_RAW (BIT(3)) diff --git a/components/soc/esp32s3/include/soc/spi_mem_struct.h b/components/soc/esp32s3/register/soc/spi_mem_struct.h similarity index 98% rename from components/soc/esp32s3/include/soc/spi_mem_struct.h rename to components/soc/esp32s3/register/soc/spi_mem_struct.h index aa6f388653c..07d352bb184 100644 --- a/components/soc/esp32s3/include/soc/spi_mem_struct.h +++ b/components/soc/esp32s3/register/soc/spi_mem_struct.h @@ -1,16 +1,8 @@ -// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef _SOC_SPI_MEM_STRUCT_H_ #define _SOC_SPI_MEM_STRUCT_H_ @@ -551,7 +543,7 @@ typedef volatile struct spi_mem_dev_s { uint32_t per_end_int_raw : 1; /*The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume command (0x7A) is sent and flash is resumed successfully. 0: Others.*/ uint32_t pes_end_int_raw : 1; /*The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend command (0x75) is sent and flash is suspended successfully. 0: Others.*/ uint32_t total_trans_end_int_raw : 1; /*The raw bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt. 1: Triggered when SPI1 transfer is done and flash is already idle. When WRSR/PP/SE/BE/CE is sent and PES/PER command is sent, this bit is set when WRSR/PP/SE/BE/CE is success. 0: Others.*/ - uint32_t brown_out_int_raw : 1; /*The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that chip is loosing power and RTC module sends out brown out close flash request to SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered and MSPI returns to idle state. 0: Others.*/ + uint32_t brown_out_int_raw : 1; /*The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that chip is losing power and RTC module sends out brown out close flash request to SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered and MSPI returns to idle state. 0: Others.*/ uint32_t ecc_err_int_raw : 1; /*The raw bit for SPI_MEM_ECC_ERR_INT interrupt. When APB_CTRL_FECC_ERR_INT_EN is set and APB_CTRL_SECC_ERR_INT_EN is cleared, this bit is triggered when the error times of SPI0/1 ECC read flash are equal or bigger than APB_CTRL_ECC_ERR_INT_NUM. When APB_CTRL_FECC_ERR_INT_EN is cleared and APB_CTRL_SECC_ERR_INT_EN is set, this bit is triggered when the error times of SPI0/1 ECC read external RAM are equal or bigger than APB_CTRL_ECC_ERR_INT_NUM. When APB_CTRL_FECC_ERR_INT_EN and APB_CTRL_SECC_ERR_INT_EN are set, this bit is triggered when the total error times of SPI0/1 ECC read external RAM and flash are equal or bigger than APB_CTRL_ECC_ERR_INT_NUM. When APB_CTRL_FECC_ERR_INT_EN and APB_CTRL_SECC_ERR_INT_EN are cleared, this bit will not be triggered.*/ uint32_t reserved5 : 27; /*reserved*/ }; diff --git a/components/soc/esp32s3/include/soc/spi_reg.h b/components/soc/esp32s3/register/soc/spi_reg.h similarity index 98% rename from components/soc/esp32s3/include/soc/spi_reg.h rename to components/soc/esp32s3/register/soc/spi_reg.h index 533158870ae..a5870547124 100644 --- a/components/soc/esp32s3/include/soc/spi_reg.h +++ b/components/soc/esp32s3/register/soc/spi_reg.h @@ -1,21 +1,13 @@ -// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef _SOC_SPI_REG_H_ #define _SOC_SPI_REG_H_ -#include "soc.h" +#include "soc/soc.h" #ifdef __cplusplus extern "C" { #endif @@ -167,7 +159,7 @@ e, the FSPI bus signals are output. Can be configured in CONF state..*/ #define SPI_CLOCK_REG(i) (REG_SPI_BASE(i) + 0xC) /* SPI_CLK_EQU_SYSCLK : R/W ;bitpos:[31] ;default: 1'b1 ; */ -/*description: In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from syst +/*description: In the master mode 1: spi_clk is equal to system 0: spi_clk is divided from syst em clock. Can be configured in CONF state..*/ #define SPI_CLK_EQU_SYSCLK (BIT(31)) #define SPI_CLK_EQU_SYSCLK_M (BIT(31)) @@ -204,15 +196,15 @@ e 0. Can be configured in CONF state..*/ #define SPI_USER_REG(i) (REG_SPI_BASE(i) + 0x10) /* SPI_USR_COMMAND : R/W ;bitpos:[31] ;default: 1'b1 ; */ -/*description: This bit enable the command phase of an operation. Can be configured in CONF sta -te..*/ +/*description: This bit enable the command phase of an operation. Can be configured in CONF +state..*/ #define SPI_USR_COMMAND (BIT(31)) #define SPI_USR_COMMAND_M (BIT(31)) #define SPI_USR_COMMAND_V 0x1 #define SPI_USR_COMMAND_S 31 /* SPI_USR_ADDR : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: This bit enable the address phase of an operation. Can be configured in CONF sta -te..*/ +/*description: This bit enable the address phase of an operation. Can be configured in CONF +state..*/ #define SPI_USR_ADDR (BIT(30)) #define SPI_USR_ADDR_M (BIT(30)) #define SPI_USR_ADDR_V 0x1 @@ -400,7 +392,7 @@ n be configured in CONF state..*/ #define SPI_USR_COMMAND_BITLEN_S 28 /* SPI_MST_REMPTY_ERR_END_EN : R/W ;bitpos:[27] ;default: 1'b1 ; */ /*description: 1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI m -aster FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty erro +aster FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error r is valid in GP-SPI master FD/HD-mode..*/ #define SPI_MST_REMPTY_ERR_END_EN (BIT(27)) #define SPI_MST_REMPTY_ERR_END_EN_M (BIT(27)) @@ -1121,7 +1113,7 @@ AFIFO read-empty error when SPI outputs data in master mode. 0: Others..*/ #define SPI_SLV_CMD_ERR_INT_RAW_V 0x1 #define SPI_SLV_CMD_ERR_INT_RAW_S 16 /* SPI_SLV_BUF_ADDR_ERR_INT_RAW : R/WTC/SS ;bitpos:[15] ;default: 1'b0 ; */ -/*description: The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data addres +/*description: The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address s of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is bigger than 63. 0: Others..*/ #define SPI_SLV_BUF_ADDR_ERR_INT_RAW (BIT(15)) @@ -1692,7 +1684,7 @@ dge 0: output data at tsck posedge .*/ /* SPI_CLK_MODE : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ /*description: SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delaye d one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inacti -ve 3: SPI clock is alwasy on. Can be configured in CONF state..*/ +ve 3: SPI clock is always on. Can be configured in CONF state..*/ #define SPI_CLK_MODE 0x00000003 #define SPI_CLK_MODE_M ((SPI_CLK_MODE_V)<<(SPI_CLK_MODE_S)) #define SPI_CLK_MODE_V 0x3 diff --git a/components/soc/esp32s3/include/soc/spi_struct.h b/components/soc/esp32s3/register/soc/spi_struct.h similarity index 98% rename from components/soc/esp32s3/include/soc/spi_struct.h rename to components/soc/esp32s3/register/soc/spi_struct.h index 2a3abd257c1..e9d62932e2b 100644 --- a/components/soc/esp32s3/include/soc/spi_struct.h +++ b/components/soc/esp32s3/register/soc/spi_struct.h @@ -1,16 +1,8 @@ -// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef _SOC_SPI_STRUCT_H_ #define _SOC_SPI_STRUCT_H_ @@ -66,7 +58,7 @@ typedef volatile struct spi_dev_s { uint32_t clkcnt_n : 6; /*In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state.*/ uint32_t clkdiv_pre : 4; /*In the master mode it is pre-divider of spi_clk. Can be configured in CONF state.*/ uint32_t reserved22 : 9; /*reserved*/ - uint32_t clk_equ_sysclk : 1; /*In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock. Can be configured in CONF state.*/ + uint32_t clk_equ_sysclk : 1; /*In the master mode 1: spi_clk is equal to system 0: spi_clk is divided from system clock. Can be configured in CONF state.*/ }; uint32_t val; } clock; @@ -374,7 +366,7 @@ typedef volatile struct spi_dev_s { uint32_t reserved_dc; union { struct { - uint32_t clk_mode : 2; /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state.*/ + uint32_t clk_mode : 2; /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is always on. Can be configured in CONF state.*/ uint32_t clk_mode_13 : 1; /*{CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7]. 0: support spi clk mode 0 and 2, first edge output data B[1]/B[6].*/ uint32_t rsck_data_out : 1; /*It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge 0: output data at tsck posedge */ uint32_t reserved4 : 4; /*reserved*/ diff --git a/components/soc/esp32s3/include/soc/syscon_reg.h b/components/soc/esp32s3/register/soc/syscon_reg.h similarity index 99% rename from components/soc/esp32s3/include/soc/syscon_reg.h rename to components/soc/esp32s3/register/soc/syscon_reg.h index e22f18c92ee..75a58fcdb52 100644 --- a/components/soc/esp32s3/include/soc/syscon_reg.h +++ b/components/soc/esp32s3/register/soc/syscon_reg.h @@ -7,7 +7,7 @@ #define _SOC_SYSCON_REG_H_ -#include "soc.h" +#include "soc/soc.h" #ifdef __cplusplus extern "C" { #endif @@ -210,7 +210,7 @@ extern "C" { #define SYSTEM_MACPWR_RST BIT(8) #define SYSTEM_RW_BTMAC_RST BIT(9) /* Bluetooth MAC */ #define SYSTEM_RW_BTLP_RST BIT(10) /* Bluetooth Low Power Module */ -#define SYSTEM_RW_BTMAC_REG_RST BIT(11) /* Bluetooth MAC Regsiters */ +#define SYSTEM_RW_BTMAC_REG_RST BIT(11) /* Bluetooth MAC Registers */ #define SYSTEM_RW_BTLP_REG_RST BIT(12) /* Bluetooth Low Power Registers */ #define SYSTEM_BTBB_REG_RST BIT(13) /* Bluetooth Baseband Registers */ diff --git a/components/soc/esp32s3/include/soc/syscon_struct.h b/components/soc/esp32s3/register/soc/syscon_struct.h similarity index 96% rename from components/soc/esp32s3/include/soc/syscon_struct.h rename to components/soc/esp32s3/register/soc/syscon_struct.h index a392939e422..e01c7153497 100644 --- a/components/soc/esp32s3/include/soc/syscon_struct.h +++ b/components/soc/esp32s3/register/soc/syscon_struct.h @@ -1,16 +1,8 @@ -// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef _SOC_SYSCON_STRUCT_H_ #define _SOC_SYSCON_STRUCT_H_ diff --git a/components/soc/esp32s3/include/soc/system_reg.h b/components/soc/esp32s3/register/soc/system_reg.h similarity index 98% rename from components/soc/esp32s3/include/soc/system_reg.h rename to components/soc/esp32s3/register/soc/system_reg.h index 49a02b007eb..736e90a84a4 100644 --- a/components/soc/esp32s3/include/soc/system_reg.h +++ b/components/soc/esp32s3/register/soc/system_reg.h @@ -1,21 +1,13 @@ -// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef _SOC_SYSTEM_REG_H_ #define _SOC_SYSTEM_REG_H_ -#include "soc.h" +#include "soc/soc.h" #ifdef __cplusplus extern "C" { #endif diff --git a/components/soc/esp32s3/include/soc/system_struct.h b/components/soc/esp32s3/register/soc/system_struct.h similarity index 98% rename from components/soc/esp32s3/include/soc/system_struct.h rename to components/soc/esp32s3/register/soc/system_struct.h index 6c4ce1f1182..b0e5f2a712e 100644 --- a/components/soc/esp32s3/include/soc/system_struct.h +++ b/components/soc/esp32s3/register/soc/system_struct.h @@ -1,16 +1,8 @@ -// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef _SOC_SYSTEM_STRUCT_H_ #define _SOC_SYSTEM_STRUCT_H_ diff --git a/components/soc/esp32s3/include/soc/systimer_reg.h b/components/soc/esp32s3/register/soc/systimer_reg.h similarity index 97% rename from components/soc/esp32s3/include/soc/systimer_reg.h rename to components/soc/esp32s3/register/soc/systimer_reg.h index 869012065b0..45873735b42 100644 --- a/components/soc/esp32s3/include/soc/systimer_reg.h +++ b/components/soc/esp32s3/register/soc/systimer_reg.h @@ -1,16 +1,7 @@ -/** Copyright 2021 Espressif Systems (Shanghai) PTE LTD +/* + * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. + * SPDX-License-Identifier: Apache-2.0 */ #pragma once diff --git a/components/soc/esp32s3/include/soc/systimer_struct.h b/components/soc/esp32s3/register/soc/systimer_struct.h similarity index 94% rename from components/soc/esp32s3/include/soc/systimer_struct.h rename to components/soc/esp32s3/register/soc/systimer_struct.h index a28ef359f16..4216561c3c2 100644 --- a/components/soc/esp32s3/include/soc/systimer_struct.h +++ b/components/soc/esp32s3/register/soc/systimer_struct.h @@ -1,16 +1,7 @@ -/** Copyright 2021 Espressif Systems (Shanghai) PTE LTD +/* + * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. + * SPDX-License-Identifier: Apache-2.0 */ #pragma once diff --git a/components/soc/esp32s3/include/soc/timer_group_reg.h b/components/soc/esp32s3/register/soc/timer_group_reg.h similarity index 97% rename from components/soc/esp32s3/include/soc/timer_group_reg.h rename to components/soc/esp32s3/register/soc/timer_group_reg.h index 7252d250673..e712afc168f 100644 --- a/components/soc/esp32s3/include/soc/timer_group_reg.h +++ b/components/soc/esp32s3/register/soc/timer_group_reg.h @@ -1,16 +1,7 @@ -/** Copyright 2021 Espressif Systems (Shanghai) PTE LTD +/* + * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. + * SPDX-License-Identifier: Apache-2.0 */ #pragma once diff --git a/components/soc/esp32s3/include/soc/timer_group_struct.h b/components/soc/esp32s3/register/soc/timer_group_struct.h similarity index 100% rename from components/soc/esp32s3/include/soc/timer_group_struct.h rename to components/soc/esp32s3/register/soc/timer_group_struct.h diff --git a/components/soc/esp32s3/include/soc/twai_struct.h b/components/soc/esp32s3/register/soc/twai_struct.h similarity index 100% rename from components/soc/esp32s3/include/soc/twai_struct.h rename to components/soc/esp32s3/register/soc/twai_struct.h diff --git a/components/soc/esp32s3/include/soc/uart_reg.h b/components/soc/esp32s3/register/soc/uart_reg.h similarity index 98% rename from components/soc/esp32s3/include/soc/uart_reg.h rename to components/soc/esp32s3/register/soc/uart_reg.h index 73c2d80b9d8..ecae7cb6462 100644 --- a/components/soc/esp32s3/include/soc/uart_reg.h +++ b/components/soc/esp32s3/register/soc/uart_reg.h @@ -1,16 +1,7 @@ -/** Copyright 2021 Espressif Systems (Shanghai) PTE LTD +/* + * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. + * SPDX-License-Identifier: Apache-2.0 */ #pragma once @@ -109,7 +100,7 @@ extern "C" { #define UART_RXFIFO_TOUT_INT_RAW_V 0x00000001U #define UART_RXFIFO_TOUT_INT_RAW_S 8 /** UART_SW_XON_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; - * This interrupt raw bit turns to high level when receiver recevies Xon char when + * This interrupt raw bit turns to high level when receiver receives Xon char when * uart_sw_flow_con_en is set to 1. */ #define UART_SW_XON_INT_RAW (BIT(9)) @@ -294,7 +285,7 @@ extern "C" { #define UART_TX_BRK_DONE_INT_ST_V 0x00000001U #define UART_TX_BRK_DONE_INT_ST_S 12 /** UART_TX_BRK_IDLE_DONE_INT_ST : RO; bitpos: [13]; default: 0; - * This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena + * This is the status bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena * is set to 1. */ #define UART_TX_BRK_IDLE_DONE_INT_ST (BIT(13)) @@ -785,7 +776,7 @@ extern "C" { #define UART_SW_DTR_V 0x00000001U #define UART_SW_DTR_S 7 /** UART_TXD_BRK : R/W; bitpos: [8]; default: 0; - * Set this bit to enbale transmitter to send NULL when the process of sending data + * Set this bit to enable transmitter to send NULL when the process of sending data * is done. */ #define UART_TXD_BRK (BIT(8)) @@ -978,7 +969,7 @@ extern "C" { #define UART_RX_FLOW_EN_V 0x00000001U #define UART_RX_FLOW_EN_S 22 /** UART_RX_TOUT_EN : R/W; bitpos: [23]; default: 0; - * This is the enble bit for uart receiver's timeout function. + * This is the enable bit for uart receiver's timeout function. */ #define UART_RX_TOUT_EN (BIT(23)) #define UART_RX_TOUT_EN_M (UART_RX_TOUT_EN_V << UART_RX_TOUT_EN_S) @@ -1003,7 +994,7 @@ extern "C" { */ #define UART_HIGHPULSE_REG(i) (REG_UART_BASE(i) + 0x2c) /** UART_HIGHPULSE_MIN_CNT : RO; bitpos: [11:0]; default: 4095; - * This register stores the value of the maxinum duration time for the high level + * This register stores the value of the maximum duration time for the high level * pulse. It is used in baud rate-detect process. */ #define UART_HIGHPULSE_MIN_CNT 0x00000FFFU diff --git a/components/soc/esp32s3/include/soc/uart_struct.h b/components/soc/esp32s3/register/soc/uart_struct.h similarity index 97% rename from components/soc/esp32s3/include/soc/uart_struct.h rename to components/soc/esp32s3/register/soc/uart_struct.h index 23d6d15450e..a5e7dc12e00 100644 --- a/components/soc/esp32s3/include/soc/uart_struct.h +++ b/components/soc/esp32s3/register/soc/uart_struct.h @@ -1,16 +1,7 @@ -/** Copyright 2021 Espressif Systems (Shanghai) PTE LTD +/* + * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. + * SPDX-License-Identifier: Apache-2.0 */ #pragma once @@ -129,7 +120,7 @@ typedef union { */ uint32_t rxfifo_tout_int_raw:1; /** sw_xon_int_raw : R/WTC/SS; bitpos: [9]; default: 0; - * This interrupt raw bit turns to high level when receiver recevies Xon char when + * This interrupt raw bit turns to high level when receiver receives Xon char when * uart_sw_flow_con_en is set to 1. */ uint32_t sw_xon_int_raw:1; @@ -247,7 +238,7 @@ typedef union { */ uint32_t tx_brk_done_int_st:1; /** tx_brk_idle_done_int_st : RO; bitpos: [13]; default: 0; - * This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena + * This is the status bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena * is set to 1. */ uint32_t tx_brk_idle_done_int_st:1; @@ -534,7 +525,7 @@ typedef union { */ uint32_t sw_dtr:1; /** txd_brk : R/W; bitpos: [8]; default: 0; - * Set this bit to enbale transmitter to send NULL when the process of sending data + * Set this bit to enable transmitter to send NULL when the process of sending data * is done. */ uint32_t txd_brk:1; @@ -654,7 +645,7 @@ typedef union { */ uint32_t rx_flow_en:1; /** rx_tout_en : R/W; bitpos: [23]; default: 0; - * This is the enble bit for uart receiver's timeout function. + * This is the enable bit for uart receiver's timeout function. */ uint32_t rx_tout_en:1; uint32_t reserved_24:8; @@ -1001,7 +992,7 @@ typedef union { typedef union { struct { /** highpulse_min_cnt : RO; bitpos: [11:0]; default: 4095; - * This register stores the value of the maxinum duration time for the high level + * This register stores the value of the maximum duration time for the high level * pulse. It is used in baud rate-detect process. */ uint32_t highpulse_min_cnt:12; diff --git a/components/soc/esp32s3/include/soc/uhci_reg.h b/components/soc/esp32s3/register/soc/uhci_reg.h similarity index 97% rename from components/soc/esp32s3/include/soc/uhci_reg.h rename to components/soc/esp32s3/register/soc/uhci_reg.h index 280bafd55c7..19fefc9f35e 100644 --- a/components/soc/esp32s3/include/soc/uhci_reg.h +++ b/components/soc/esp32s3/register/soc/uhci_reg.h @@ -1,21 +1,13 @@ -// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef _SOC_UHCI_REG_H_ #define _SOC_UHCI_REG_H_ -#include "soc.h" +#include "soc/soc.h" #ifdef __cplusplus extern "C" { #endif diff --git a/components/soc/esp32s3/include/soc/uhci_struct.h b/components/soc/esp32s3/register/soc/uhci_struct.h similarity index 100% rename from components/soc/esp32s3/include/soc/uhci_struct.h rename to components/soc/esp32s3/register/soc/uhci_struct.h diff --git a/components/soc/esp32s3/include/soc/usb_reg.h b/components/soc/esp32s3/register/soc/usb_reg.h similarity index 99% rename from components/soc/esp32s3/include/soc/usb_reg.h rename to components/soc/esp32s3/register/soc/usb_reg.h index 90bc61d71ac..d98ebf419b6 100644 --- a/components/soc/esp32s3/include/soc/usb_reg.h +++ b/components/soc/esp32s3/register/soc/usb_reg.h @@ -8,7 +8,7 @@ #include #include "soc/soc.h" -#include "soc.h" +#include "soc/soc.h" #ifdef __cplusplus extern "C" { #endif @@ -608,7 +608,7 @@ extern "C" { #define USB_H_LSPDDEV0_V 0x00000001 #define USB_H_LSPDDEV0_S 17 /** USB_H_EPTYPE0 : R/W; bitpos: [20:18]; default: 0; - * 0x0 (CTRL): Contro + * 0x0 (CTRL): Control * 0x1 (ISOC): Isochronous * 0x2 (BULK): Bulk * 0x3 (INTERR): Interrupt @@ -647,7 +647,7 @@ extern "C" { #define USB_H_ODDFRM0_S 29 /** USB_H_CHDIS0 : R/W; bitpos: [30]; default: 0; * Channel Disable - * 0x0 : Transmit/Recieve norma + * 0x0 : Transmit/Receive norma * 0x1 : Stop transmitting/receiving data on channel */ #define USB_H_CHDIS0 (BIT(30)) @@ -720,7 +720,7 @@ extern "C" { #define USB_H_LSPDDEV1_V 0x00000001 #define USB_H_LSPDDEV1_S 17 /** USB_H_EPTYPE1 : R/W; bitpos: [20:18]; default: 0; - * 0x0 (CTRL): Contro + * 0x0 (CTRL): Control * 0x1 (ISOC): Isochronous * 0x2 (BULK): Bulk * 0x3 (INTERR): Interrupt @@ -759,7 +759,7 @@ extern "C" { #define USB_H_ODDFRM1_S 29 /** USB_H_CHDIS1 : R/W; bitpos: [30]; default: 0; * Channel Disable - * 0x0 : Transmit/Recieve norma + * 0x0 : Transmit/Receive norma * 0x1 : Stop transmitting/receiving data on channel */ #define USB_H_CHDIS1 (BIT(30)) @@ -832,7 +832,7 @@ extern "C" { #define USB_H_LSPDDEV2_V 0x00000001 #define USB_H_LSPDDEV2_S 17 /** USB_H_EPTYPE2 : R/W; bitpos: [20:18]; default: 0; - * 0x0 (CTRL): Contro + * 0x0 (CTRL): Control * 0x1 (ISOC): Isochronous * 0x2 (BULK): Bulk * 0x3 (INTERR): Interrupt @@ -871,7 +871,7 @@ extern "C" { #define USB_H_ODDFRM2_S 29 /** USB_H_CHDIS2 : R/W; bitpos: [30]; default: 0; * Channel Disable - * 0x0 : Transmit/Recieve norma + * 0x0 : Transmit/Receive norma * 0x1 : Stop transmitting/receiving data on channel */ #define USB_H_CHDIS2 (BIT(30)) @@ -944,7 +944,7 @@ extern "C" { #define USB_H_LSPDDEV3_V 0x00000001 #define USB_H_LSPDDEV3_S 17 /** USB_H_EPTYPE3 : R/W; bitpos: [20:18]; default: 0; - * 0x0 (CTRL): Contro + * 0x0 (CTRL): Control * 0x1 (ISOC): Isochronous * 0x2 (BULK): Bulk * 0x3 (INTERR): Interrupt @@ -983,7 +983,7 @@ extern "C" { #define USB_H_ODDFRM3_S 29 /** USB_H_CHDIS3 : R/W; bitpos: [30]; default: 0; * Channel Disable - * 0x0 : Transmit/Recieve norma + * 0x0 : Transmit/Receive norma * 0x1 : Stop transmitting/receiving data on channel */ #define USB_H_CHDIS3 (BIT(30)) @@ -1056,7 +1056,7 @@ extern "C" { #define USB_H_LSPDDEV4_V 0x00000001 #define USB_H_LSPDDEV4_S 17 /** USB_H_EPTYPE4 : R/W; bitpos: [20:18]; default: 0; - * 0x0 (CTRL): Contro + * 0x0 (CTRL): Control * 0x1 (ISOC): Isochronous * 0x2 (BULK): Bulk * 0x3 (INTERR): Interrupt @@ -1095,7 +1095,7 @@ extern "C" { #define USB_H_ODDFRM4_S 29 /** USB_H_CHDIS4 : R/W; bitpos: [30]; default: 0; * Channel Disable - * 0x0 : Transmit/Recieve norma + * 0x0 : Transmit/Receive norma * 0x1 : Stop transmitting/receiving data on channel */ #define USB_H_CHDIS4 (BIT(30)) @@ -1168,7 +1168,7 @@ extern "C" { #define USB_H_LSPDDEV5_V 0x00000001 #define USB_H_LSPDDEV5_S 17 /** USB_H_EPTYPE5 : R/W; bitpos: [20:18]; default: 0; - * 0x0 (CTRL): Contro + * 0x0 (CTRL): Control * 0x1 (ISOC): Isochronous * 0x2 (BULK): Bulk * 0x3 (INTERR): Interrupt @@ -1207,7 +1207,7 @@ extern "C" { #define USB_H_ODDFRM5_S 29 /** USB_H_CHDIS5 : R/W; bitpos: [30]; default: 0; * Channel Disable - * 0x0 : Transmit/Recieve norma + * 0x0 : Transmit/Receive norma * 0x1 : Stop transmitting/receiving data on channel */ #define USB_H_CHDIS5 (BIT(30)) @@ -1280,7 +1280,7 @@ extern "C" { #define USB_H_LSPDDEV6_V 0x00000001 #define USB_H_LSPDDEV6_S 17 /** USB_H_EPTYPE6 : R/W; bitpos: [20:18]; default: 0; - * 0x0 (CTRL): Contro + * 0x0 (CTRL): Control * 0x1 (ISOC): Isochronous * 0x2 (BULK): Bulk * 0x3 (INTERR): Interrupt @@ -1319,7 +1319,7 @@ extern "C" { #define USB_H_ODDFRM6_S 29 /** USB_H_CHDIS6 : R/W; bitpos: [30]; default: 0; * Channel Disable - * 0x0 : Transmit/Recieve norma + * 0x0 : Transmit/Receive norma * 0x1 : Stop transmitting/receiving data on channel */ #define USB_H_CHDIS6 (BIT(30)) @@ -1392,7 +1392,7 @@ extern "C" { #define USB_H_LSPDDEV7_V 0x00000001 #define USB_H_LSPDDEV7_S 17 /** USB_H_EPTYPE7 : R/W; bitpos: [20:18]; default: 0; - * 0x0 (CTRL): Contro + * 0x0 (CTRL): Control * 0x1 (ISOC): Isochronous * 0x2 (BULK): Bulk * 0x3 (INTERR): Interrupt @@ -1431,7 +1431,7 @@ extern "C" { #define USB_H_ODDFRM7_S 29 /** USB_H_CHDIS7 : R/W; bitpos: [30]; default: 0; * Channel Disable - * 0x0 : Transmit/Recieve norma + * 0x0 : Transmit/Receive norma * 0x1 : Stop transmitting/receiving data on channel */ #define USB_H_CHDIS7 (BIT(30)) @@ -1476,7 +1476,7 @@ extern "C" { /** USB_NZSTSOUTHSHK : R/W; bitpos: [2]; default: 0; * 1'b0: Send the received OUT packet to the application (zero-length or non-zero * length) and send a handshake based on NAK and STALL bits for the endpoint in the - * Devce Endpoint Control Register + * Device Endpoint Control Register * 1'b1: Send a STALL handshake on a nonzero-length status OUT transaction and do not * send the received OUT packet to the application */ @@ -1488,7 +1488,7 @@ extern "C" { * This bit can be set only if FS PHY interface is selected. * Otherwise, this bit needs to be set to zero. * 1'b0: USB 1.1 Full-Speed Serial transiver not selected - * 1'b1: If FS PHY interface is choosen and this bit is set, the PHY clock during Suspend + * 1'b1: If FS PHY interface is chosen and this bit is set, the PHY clock during Suspend * must be switched from 48 MHz to 32 KHz */ #define USB_ENA32KHZSUSP (BIT(3)) @@ -1580,7 +1580,7 @@ extern "C" { #define USB_DCTL_REG (SOC_DPORT_USB_BASE + 0x804) /** USB_RMTWKUPSIG : R/W; bitpos: [0]; default: 0; * 0x0 : Core does not send Remote Wakeup Signaling - * 0x1 : Core sends Remote Wakeup Signalin + * 0x1 : Core sends Remote Wakeup Signaling */ #define USB_RMTWKUPSIG (BIT(0)) #define USB_RMTWKUPSIG_M (USB_RMTWKUPSIG_V << USB_RMTWKUPSIG_S) @@ -4729,7 +4729,7 @@ extern "C" { #define USB_H_NACK0_S 4 /** USB_H_ACK0 : R/W1C; bitpos: [5]; default: 0; * 1'b0: No ACK Response Received or Transmitted Interrupt - * 1'b1: ACK Response Received or Transmitted Interrup + * 1'b1: ACK Response Received or Transmitted Interrupt */ #define USB_H_ACK0 (BIT(5)) #define USB_H_ACK0_M (USB_H_ACK0_V << USB_H_ACK0_S) @@ -4965,7 +4965,7 @@ extern "C" { #define USB_H_NACK1_S 4 /** USB_H_ACK1 : R/W1C; bitpos: [5]; default: 0; * 1'b0: No ACK Response Received or Transmitted Interrupt - * 1'b1: ACK Response Received or Transmitted Interrup + * 1'b1: ACK Response Received or Transmitted Interrupt */ #define USB_H_ACK1 (BIT(5)) #define USB_H_ACK1_M (USB_H_ACK1_V << USB_H_ACK1_S) @@ -5201,7 +5201,7 @@ extern "C" { #define USB_H_NACK2_S 4 /** USB_H_ACK2 : R/W1C; bitpos: [5]; default: 0; * 1'b0: No ACK Response Received or Transmitted Interrupt - * 1'b1: ACK Response Received or Transmitted Interrup + * 1'b1: ACK Response Received or Transmitted Interrupt */ #define USB_H_ACK2 (BIT(5)) #define USB_H_ACK2_M (USB_H_ACK2_V << USB_H_ACK2_S) @@ -5437,7 +5437,7 @@ extern "C" { #define USB_H_NACK3_S 4 /** USB_H_ACK3 : R/W1C; bitpos: [5]; default: 0; * 1'b0: No ACK Response Received or Transmitted Interrupt - * 1'b1: ACK Response Received or Transmitted Interrup + * 1'b1: ACK Response Received or Transmitted Interrupt */ #define USB_H_ACK3 (BIT(5)) #define USB_H_ACK3_M (USB_H_ACK3_V << USB_H_ACK3_S) @@ -5673,7 +5673,7 @@ extern "C" { #define USB_H_NACK4_S 4 /** USB_H_ACK4 : R/W1C; bitpos: [5]; default: 0; * 1'b0: No ACK Response Received or Transmitted Interrupt - * 1'b1: ACK Response Received or Transmitted Interrup + * 1'b1: ACK Response Received or Transmitted Interrupt */ #define USB_H_ACK4 (BIT(5)) #define USB_H_ACK4_M (USB_H_ACK4_V << USB_H_ACK4_S) @@ -5909,7 +5909,7 @@ extern "C" { #define USB_H_NACK5_S 4 /** USB_H_ACK5 : R/W1C; bitpos: [5]; default: 0; * 1'b0: No ACK Response Received or Transmitted Interrupt - * 1'b1: ACK Response Received or Transmitted Interrup + * 1'b1: ACK Response Received or Transmitted Interrupt */ #define USB_H_ACK5 (BIT(5)) #define USB_H_ACK5_M (USB_H_ACK5_V << USB_H_ACK5_S) @@ -6145,7 +6145,7 @@ extern "C" { #define USB_H_NACK6_S 4 /** USB_H_ACK6 : R/W1C; bitpos: [5]; default: 0; * 1'b0: No ACK Response Received or Transmitted Interrupt - * 1'b1: ACK Response Received or Transmitted Interrup + * 1'b1: ACK Response Received or Transmitted Interrupt */ #define USB_H_ACK6 (BIT(5)) #define USB_H_ACK6_M (USB_H_ACK6_V << USB_H_ACK6_S) @@ -6381,7 +6381,7 @@ extern "C" { #define USB_H_NACK7_S 4 /** USB_H_ACK7 : R/W1C; bitpos: [5]; default: 0; * 1'b0: No ACK Response Received or Transmitted Interrupt - * 1'b1: ACK Response Received or Transmitted Interrup + * 1'b1: ACK Response Received or Transmitted Interrupt */ #define USB_H_ACK7 (BIT(5)) #define USB_H_ACK7_M (USB_H_ACK7_V << USB_H_ACK7_S) @@ -8915,9 +8915,9 @@ extern "C" { #define USB_AHBSINGLE_V 0x00000001 #define USB_AHBSINGLE_S 23 /** USB_INVDESCENDIANESS : R/W; bitpos: [24]; default: 0; - * Invert Descriptor Endianess + * Invert Descriptor Endianness * 1'b0: Descriptor Endianness is same as AHB Master Endianness - * 1'b1:Invert Descriptor Endianess according to AHB Master endianness + * 1'b1:Invert Descriptor Endianness according to AHB Master endianness */ #define USB_INVDESCENDIANESS (BIT(24)) #define USB_INVDESCENDIANESS_M (USB_INVDESCENDIANESS_V << USB_INVDESCENDIANESS_S) @@ -9678,7 +9678,7 @@ extern "C" { /** USB_GSNPSID_REG register - * Synopsys ID Register + * ID Register */ #define USB_GSNPSID_REG (SOC_DPORT_USB_BASE + 0x40) /** USB_SYNOPSYSID : RO; bitpos: [32:0]; default: 1330921482; diff --git a/components/soc/esp32s3/include/soc/usb_serial_jtag_reg.h b/components/soc/esp32s3/register/soc/usb_serial_jtag_reg.h similarity index 99% rename from components/soc/esp32s3/include/soc/usb_serial_jtag_reg.h rename to components/soc/esp32s3/register/soc/usb_serial_jtag_reg.h index 5774f2d711a..2338bc6a4de 100644 --- a/components/soc/esp32s3/include/soc/usb_serial_jtag_reg.h +++ b/components/soc/esp32s3/register/soc/usb_serial_jtag_reg.h @@ -9,7 +9,7 @@ #ifdef __cplusplus extern "C" { #endif -#include "soc.h" +#include "soc/soc.h" #define USB_SERIAL_JTAG_EP1_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x0) /* USB_SERIAL_JTAG_RDWR_BYTE : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ @@ -31,8 +31,8 @@ ived, then read data from UART Rx FIFO..*/ #define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_V 0x1 #define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_S 2 /* USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE : RO ;bitpos:[1] ;default: 1'b1 ; */ -/*description: 1'b1: Indicate UART Tx FIFO is not full and can write data into in. After writin -g USB_SERIAL_JTAG_WR_DONE, this bit would be 0 until data in UART Tx FIFO is read by +/*description: 1'b1: Indicate UART Tx FIFO is not full and can write data into in. After +writing USB_SERIAL_JTAG_WR_DONE, this bit would be 0 until data in UART Tx FIFO is read by USB Host..*/ #define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE (BIT(1)) #define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_M (BIT(1)) @@ -117,8 +117,8 @@ eived..*/ #define USB_SERIAL_JTAG_SOF_INT_RAW_V 0x1 #define USB_SERIAL_JTAG_SOF_INT_RAW_S 1 /* USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when flush cmd is received for IN endp -oint 2 of JTAG..*/ +/*description: The raw interrupt bit turns to high level when flush cmd is received for IN +endpoint 2 of JTAG..*/ #define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW (BIT(0)) #define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_M (BIT(0)) #define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_V 0x1 @@ -146,7 +146,7 @@ pt..*/ #define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_V 0x1 #define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_S 9 /* USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT interrup +/*description: The raw interrupt status bit for the USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT interrupt t..*/ #define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST (BIT(8)) #define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_M (BIT(8)) @@ -183,7 +183,7 @@ t..*/ #define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_V 0x1 #define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_S 3 /* USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrup +/*description: The raw interrupt status bit for the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt t..*/ #define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST (BIT(2)) #define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_M (BIT(2)) diff --git a/components/soc/esp32s3/include/soc/usb_serial_jtag_struct.h b/components/soc/esp32s3/register/soc/usb_serial_jtag_struct.h similarity index 96% rename from components/soc/esp32s3/include/soc/usb_serial_jtag_struct.h rename to components/soc/esp32s3/register/soc/usb_serial_jtag_struct.h index 539717f267b..aeb3bb47caa 100644 --- a/components/soc/esp32s3/include/soc/usb_serial_jtag_struct.h +++ b/components/soc/esp32s3/register/soc/usb_serial_jtag_struct.h @@ -1,16 +1,8 @@ -// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef _SOC_USB_SERIAL_JTAG_STRUCT_H_ #define _SOC_USB_SERIAL_JTAG_STRUCT_H_ @@ -18,7 +10,7 @@ #ifdef __cplusplus extern "C" { #endif -#include "soc.h" +#include "soc/soc.h" typedef volatile struct usb_serial_jtag_dev_s { union { diff --git a/components/soc/esp32s3/include/soc/usb_struct.h b/components/soc/esp32s3/register/soc/usb_struct.h similarity index 98% rename from components/soc/esp32s3/include/soc/usb_struct.h rename to components/soc/esp32s3/register/soc/usb_struct.h index 697c79e416f..a07aa34f533 100644 --- a/components/soc/esp32s3/include/soc/usb_struct.h +++ b/components/soc/esp32s3/register/soc/usb_struct.h @@ -50,7 +50,7 @@ typedef struct usb_reg { volatile uint32_t gnptxfsiz; // 0x0028 Non-periodic Transmit FIFO Size Register volatile uint32_t gnptxsts; // 0x002c Non-periodic Transmit FIFO/Queue Status Register uint32_t reserved_0x0030_0x0040[4]; // 0x0030 to 0x0040 - volatile uint32_t gsnpsid; // 0x0040 Synopsys ID Register + volatile uint32_t gsnpsid; // 0x0040 ID Register volatile uint32_t ghwcfg1; // 0x0044 User Hardware Configuration 1 Register volatile uint32_t ghwcfg2; // 0x0048 User Hardware Configuration 2 Register volatile uint32_t ghwcfg3; // 0x004c User Hardware Configuration 3 Register diff --git a/components/soc/esp32s3/include/soc/usb_wrap_reg.h b/components/soc/esp32s3/register/soc/usb_wrap_reg.h similarity index 93% rename from components/soc/esp32s3/include/soc/usb_wrap_reg.h rename to components/soc/esp32s3/register/soc/usb_wrap_reg.h index 45502289cdf..9b8ea950a24 100644 --- a/components/soc/esp32s3/include/soc/usb_wrap_reg.h +++ b/components/soc/esp32s3/register/soc/usb_wrap_reg.h @@ -1,21 +1,13 @@ -// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef _SOC_USB_WRAP_REG_H_ #define _SOC_USB_WRAP_REG_H_ -#include "soc.h" +#include "soc/soc.h" #ifdef __cplusplus extern "C" { #endif diff --git a/components/soc/esp32s3/include/soc/usb_wrap_struct.h b/components/soc/esp32s3/register/soc/usb_wrap_struct.h similarity index 95% rename from components/soc/esp32s3/include/soc/usb_wrap_struct.h rename to components/soc/esp32s3/register/soc/usb_wrap_struct.h index 71013fe25f7..9f440d17e9a 100644 --- a/components/soc/esp32s3/include/soc/usb_wrap_struct.h +++ b/components/soc/esp32s3/register/soc/usb_wrap_struct.h @@ -1,16 +1,7 @@ -/** Copyright 2020 Espressif Systems (Shanghai) PTE LTD +/* + * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. + * SPDX-License-Identifier: Apache-2.0 */ #pragma once diff --git a/components/soc/esp32s3/include/soc/world_controller_reg.h b/components/soc/esp32s3/register/soc/world_controller_reg.h similarity index 100% rename from components/soc/esp32s3/include/soc/world_controller_reg.h rename to components/soc/esp32s3/register/soc/world_controller_reg.h diff --git a/components/soc/esp32s3/include/soc/world_controller_struct.h b/components/soc/esp32s3/register/soc/world_controller_struct.h similarity index 100% rename from components/soc/esp32s3/include/soc/world_controller_struct.h rename to components/soc/esp32s3/register/soc/world_controller_struct.h diff --git a/tools/ci/check_copyright_ignore.txt b/tools/ci/check_copyright_ignore.txt index f605b7cd054..d90fd8540bc 100644 --- a/tools/ci/check_copyright_ignore.txt +++ b/tools/ci/check_copyright_ignore.txt @@ -565,60 +565,7 @@ components/soc/esp32s2/include/soc/touch_sensor_pins.h components/soc/esp32s2/include/soc/uart_pins.h components/soc/esp32s2/include/soc/wdev_reg.h components/soc/esp32s2/ledc_periph.c -components/soc/esp32s3/include/soc/apb_saradc_reg.h -components/soc/esp32s3/include/soc/assist_debug_reg.h -components/soc/esp32s3/include/soc/assist_debug_struct.h -components/soc/esp32s3/include/soc/bb_reg.h -components/soc/esp32s3/include/soc/boot_mode.h -components/soc/esp32s3/include/soc/extmem_reg.h -components/soc/esp32s3/include/soc/extmem_struct.h -components/soc/esp32s3/include/soc/fe_reg.h -components/soc/esp32s3/include/soc/gpio_reg.h -components/soc/esp32s3/include/soc/hinf_reg.h -components/soc/esp32s3/include/soc/hinf_struct.h -components/soc/esp32s3/include/soc/host_reg.h -components/soc/esp32s3/include/soc/host_struct.h -components/soc/esp32s3/include/soc/i2c_reg.h -components/soc/esp32s3/include/soc/i2c_struct.h -components/soc/esp32s3/include/soc/interrupt_core0_reg.h -components/soc/esp32s3/include/soc/interrupt_core0_struct.h -components/soc/esp32s3/include/soc/interrupt_core1_reg.h -components/soc/esp32s3/include/soc/interrupt_core1_struct.h -components/soc/esp32s3/include/soc/interrupt_struct.h -components/soc/esp32s3/include/soc/ledc_reg.h -components/soc/esp32s3/include/soc/ledc_struct.h components/soc/esp32s3/include/soc/mpu_caps.h -components/soc/esp32s3/include/soc/nrx_reg.h -components/soc/esp32s3/include/soc/peri_backup_reg.h -components/soc/esp32s3/include/soc/peri_backup_struct.h -components/soc/esp32s3/include/soc/reset_reasons.h -components/soc/esp32s3/include/soc/rtc_i2c_reg.h -components/soc/esp32s3/include/soc/rtc_i2c_struct.h -components/soc/esp32s3/include/soc/rtc_io_reg.h -components/soc/esp32s3/include/soc/rtc_io_struct.h -components/soc/esp32s3/include/soc/sdmmc_pins.h -components/soc/esp32s3/include/soc/sdmmc_reg.h -components/soc/esp32s3/include/soc/sensitive_reg.h -components/soc/esp32s3/include/soc/sensitive_struct.h -components/soc/esp32s3/include/soc/soc_ulp.h -components/soc/esp32s3/include/soc/spi_mem_reg.h -components/soc/esp32s3/include/soc/spi_mem_struct.h -components/soc/esp32s3/include/soc/spi_reg.h -components/soc/esp32s3/include/soc/spi_struct.h -components/soc/esp32s3/include/soc/syscon_struct.h -components/soc/esp32s3/include/soc/system_reg.h -components/soc/esp32s3/include/soc/system_struct.h -components/soc/esp32s3/include/soc/systimer_reg.h -components/soc/esp32s3/include/soc/systimer_struct.h -components/soc/esp32s3/include/soc/touch_channel.h -components/soc/esp32s3/include/soc/uart_pins.h -components/soc/esp32s3/include/soc/uart_reg.h -components/soc/esp32s3/include/soc/uart_struct.h -components/soc/esp32s3/include/soc/uhci_reg.h -components/soc/esp32s3/include/soc/usb_serial_jtag_struct.h -components/soc/esp32s3/include/soc/usb_wrap_reg.h -components/soc/esp32s3/include/soc/usb_wrap_struct.h -components/soc/esp32s3/include/soc/wdev_reg.h components/soc/esp32s3/ledc_periph.c components/soc/include/soc/gpio_periph.h components/soc/include/soc/ledc_periph.h From 25bd7a670cc013f73528c18846864bb88ca09d6e Mon Sep 17 00:00:00 2001 From: laokaiyao Date: Fri, 6 Sep 2024 18:39:50 +0800 Subject: [PATCH 116/472] refactor(soc): sort esp32c61 soc headers --- components/soc/esp32c61/include/soc/dport_access.h | 1 - components/soc/esp32c61/include/soc/soc.h | 2 +- components/soc/esp32c61/include/soc/system_reg.h | 2 +- components/soc/esp32c61/register/soc/.gitkeep | 0 .../esp32c61/{include => register}/soc/ahb_dma_reg.h | 0 .../{include => register}/soc/ahb_dma_struct.h | 0 .../{include => register}/soc/apb_saradc_reg.h | 0 .../{include => register}/soc/apb_saradc_struct.h | 0 .../{include => register}/soc/assist_debug_reg.h | 4 ++-- .../{include => register}/soc/assist_debug_struct.h | 10 +++++----- .../soc/esp32c61/{include => register}/soc/cache_reg.h | 8 ++++---- .../esp32c61/{include => register}/soc/cache_struct.h | 8 ++++---- .../soc/esp32c61/{include => register}/soc/clic_reg.h | 0 .../soc/esp32c61/{include => register}/soc/clint_reg.h | 0 .../esp32c61/{include => register}/soc/ecc_mult_reg.h | 0 .../{include => register}/soc/ecc_mult_struct.h | 0 .../soc/esp32c61/{include => register}/soc/ecdsa_reg.h | 6 +++--- .../esp32c61/{include => register}/soc/ecdsa_struct.h | 6 +++--- .../soc/esp32c61/{include => register}/soc/efuse_reg.h | 0 .../esp32c61/{include => register}/soc/efuse_struct.h | 0 .../esp32c61/{include => register}/soc/gpio_ext_reg.h | 2 +- .../{include => register}/soc/gpio_ext_struct.h | 2 +- .../soc/esp32c61/{include => register}/soc/gpio_reg.h | 0 .../esp32c61/{include => register}/soc/gpio_struct.h | 0 .../esp32c61/{include => register}/soc/hp_apm_reg.h | 0 .../esp32c61/{include => register}/soc/hp_apm_struct.h | 0 .../esp32c61/{include => register}/soc/hp_system_reg.h | 0 .../{include => register}/soc/hp_system_struct.h | 0 .../{include => register}/soc/i2c_ana_mst_reg.h | 0 .../soc/esp32c61/{include => register}/soc/i2c_reg.h | 0 .../esp32c61/{include => register}/soc/i2c_struct.h | 0 .../soc/esp32c61/{include => register}/soc/i2s_reg.h | 2 +- .../esp32c61/{include => register}/soc/i2s_struct.h | 2 +- .../{include => register}/soc/interrupt_matrix_reg.h | 0 .../soc/interrupt_matrix_struct.h | 0 .../esp32c61/{include => register}/soc/intpri_reg.h | 0 .../esp32c61/{include => register}/soc/intpri_struct.h | 0 .../esp32c61/{include => register}/soc/io_mux_reg.h | 0 .../esp32c61/{include => register}/soc/io_mux_struct.h | 0 .../soc/esp32c61/{include => register}/soc/ledc_reg.h | 0 .../esp32c61/{include => register}/soc/ledc_struct.h | 0 .../{include => register}/soc/lp_analog_peri_reg.h | 0 .../{include => register}/soc/lp_analog_peri_struct.h | 0 .../esp32c61/{include => register}/soc/lp_aon_reg.h | 0 .../esp32c61/{include => register}/soc/lp_aon_struct.h | 0 .../esp32c61/{include => register}/soc/lp_apm_reg.h | 0 .../esp32c61/{include => register}/soc/lp_apm_struct.h | 0 .../esp32c61/{include => register}/soc/lp_clkrst_reg.h | 2 +- .../{include => register}/soc/lp_clkrst_struct.h | 2 +- .../esp32c61/{include => register}/soc/lp_gpio_reg.h | 0 .../{include => register}/soc/lp_gpio_struct.h | 0 .../esp32c61/{include => register}/soc/lp_iomux_reg.h | 0 .../{include => register}/soc/lp_iomux_struct.h | 0 .../esp32c61/{include => register}/soc/lp_tee_reg.h | 0 .../esp32c61/{include => register}/soc/lp_tee_struct.h | 0 .../esp32c61/{include => register}/soc/lp_timer_reg.h | 0 .../{include => register}/soc/lp_timer_struct.h | 0 .../esp32c61/{include => register}/soc/lp_wdt_reg.h | 0 .../esp32c61/{include => register}/soc/lp_wdt_struct.h | 0 .../esp32c61/{include => register}/soc/lpperi_reg.h | 0 .../esp32c61/{include => register}/soc/lpperi_struct.h | 0 .../{include => register}/soc/mem_monitor_reg.h | 0 .../{include => register}/soc/mem_monitor_struct.h | 0 .../soc/esp32c61/{include => register}/soc/pau_reg.h | 0 .../esp32c61/{include => register}/soc/pau_struct.h | 0 .../soc/esp32c61/{include => register}/soc/pcr_reg.h | 0 .../esp32c61/{include => register}/soc/pcr_struct.h | 0 .../soc/esp32c61/{include => register}/soc/pmu_reg.h | 0 .../esp32c61/{include => register}/soc/pmu_struct.h | 2 +- .../soc/esp32c61/{include => register}/soc/pvt_reg.h | 0 .../esp32c61/{include => register}/soc/pvt_struct.h | 0 .../soc/esp32c61/{include => register}/soc/reg_base.h | 0 .../soc/esp32c61/{include => register}/soc/sha_reg.h | 2 +- .../esp32c61/{include => register}/soc/sha_struct.h | 0 .../esp32c61/{include => register}/soc/soc_etm_reg.h | 0 .../{include => register}/soc/soc_etm_struct.h | 0 .../esp32c61/{include => register}/soc/spi1_mem_reg.h | 0 .../{include => register}/soc/spi1_mem_struct.h | 0 .../esp32c61/{include => register}/soc/spi_mem_c_reg.h | 0 .../{include => register}/soc/spi_mem_c_struct.h | 0 .../soc/esp32c61/{include => register}/soc/spi_reg.h | 2 +- .../esp32c61/{include => register}/soc/spi_struct.h | 2 +- .../esp32c61/{include => register}/soc/systimer_reg.h | 0 .../{include => register}/soc/systimer_struct.h | 0 .../soc/esp32c61/{include => register}/soc/tee_reg.h | 0 .../esp32c61/{include => register}/soc/tee_struct.h | 0 .../{include => register}/soc/timer_group_reg.h | 0 .../{include => register}/soc/timer_group_struct.h | 0 .../soc/esp32c61/{include => register}/soc/trace_reg.h | 10 +++++----- .../esp32c61/{include => register}/soc/trace_struct.h | 10 +++++----- .../soc/esp32c61/{include => register}/soc/uart_reg.h | 0 .../esp32c61/{include => register}/soc/uart_struct.h | 0 .../{include => register}/soc/usb_serial_jtag_reg.h | 2 +- .../{include => register}/soc/usb_serial_jtag_struct.h | 0 .../esp32c61/{include => register}/soc/xts_aes_reg.h | 6 +++--- 95 files changed, 47 insertions(+), 48 deletions(-) delete mode 100644 components/soc/esp32c61/register/soc/.gitkeep rename components/soc/esp32c61/{include => register}/soc/ahb_dma_reg.h (100%) rename components/soc/esp32c61/{include => register}/soc/ahb_dma_struct.h (100%) rename components/soc/esp32c61/{include => register}/soc/apb_saradc_reg.h (100%) rename components/soc/esp32c61/{include => register}/soc/apb_saradc_struct.h (100%) rename components/soc/esp32c61/{include => register}/soc/assist_debug_reg.h (99%) rename components/soc/esp32c61/{include => register}/soc/assist_debug_struct.h (99%) rename components/soc/esp32c61/{include => register}/soc/cache_reg.h (99%) rename components/soc/esp32c61/{include => register}/soc/cache_struct.h (99%) rename components/soc/esp32c61/{include => register}/soc/clic_reg.h (100%) rename components/soc/esp32c61/{include => register}/soc/clint_reg.h (100%) rename components/soc/esp32c61/{include => register}/soc/ecc_mult_reg.h (100%) rename components/soc/esp32c61/{include => register}/soc/ecc_mult_struct.h (100%) rename components/soc/esp32c61/{include => register}/soc/ecdsa_reg.h (98%) rename components/soc/esp32c61/{include => register}/soc/ecdsa_struct.h (97%) rename components/soc/esp32c61/{include => register}/soc/efuse_reg.h (100%) rename components/soc/esp32c61/{include => register}/soc/efuse_struct.h (100%) rename components/soc/esp32c61/{include => register}/soc/gpio_ext_reg.h (99%) rename components/soc/esp32c61/{include => register}/soc/gpio_ext_struct.h (99%) rename components/soc/esp32c61/{include => register}/soc/gpio_reg.h (100%) rename components/soc/esp32c61/{include => register}/soc/gpio_struct.h (100%) rename components/soc/esp32c61/{include => register}/soc/hp_apm_reg.h (100%) rename components/soc/esp32c61/{include => register}/soc/hp_apm_struct.h (100%) rename components/soc/esp32c61/{include => register}/soc/hp_system_reg.h (100%) rename components/soc/esp32c61/{include => register}/soc/hp_system_struct.h (100%) rename components/soc/esp32c61/{include => register}/soc/i2c_ana_mst_reg.h (100%) rename components/soc/esp32c61/{include => register}/soc/i2c_reg.h (100%) rename components/soc/esp32c61/{include => register}/soc/i2c_struct.h (100%) rename components/soc/esp32c61/{include => register}/soc/i2s_reg.h (99%) rename components/soc/esp32c61/{include => register}/soc/i2s_struct.h (99%) rename components/soc/esp32c61/{include => register}/soc/interrupt_matrix_reg.h (100%) rename components/soc/esp32c61/{include => register}/soc/interrupt_matrix_struct.h (100%) rename components/soc/esp32c61/{include => register}/soc/intpri_reg.h (100%) rename components/soc/esp32c61/{include => register}/soc/intpri_struct.h (100%) rename components/soc/esp32c61/{include => register}/soc/io_mux_reg.h (100%) rename components/soc/esp32c61/{include => register}/soc/io_mux_struct.h (100%) rename components/soc/esp32c61/{include => register}/soc/ledc_reg.h (100%) rename components/soc/esp32c61/{include => register}/soc/ledc_struct.h (100%) rename components/soc/esp32c61/{include => register}/soc/lp_analog_peri_reg.h (100%) rename components/soc/esp32c61/{include => register}/soc/lp_analog_peri_struct.h (100%) rename components/soc/esp32c61/{include => register}/soc/lp_aon_reg.h (100%) rename components/soc/esp32c61/{include => register}/soc/lp_aon_struct.h (100%) rename components/soc/esp32c61/{include => register}/soc/lp_apm_reg.h (100%) rename components/soc/esp32c61/{include => register}/soc/lp_apm_struct.h (100%) rename components/soc/esp32c61/{include => register}/soc/lp_clkrst_reg.h (99%) rename components/soc/esp32c61/{include => register}/soc/lp_clkrst_struct.h (99%) rename components/soc/esp32c61/{include => register}/soc/lp_gpio_reg.h (100%) rename components/soc/esp32c61/{include => register}/soc/lp_gpio_struct.h (100%) rename components/soc/esp32c61/{include => register}/soc/lp_iomux_reg.h (100%) rename components/soc/esp32c61/{include => register}/soc/lp_iomux_struct.h (100%) rename components/soc/esp32c61/{include => register}/soc/lp_tee_reg.h (100%) rename components/soc/esp32c61/{include => register}/soc/lp_tee_struct.h (100%) rename components/soc/esp32c61/{include => register}/soc/lp_timer_reg.h (100%) rename components/soc/esp32c61/{include => register}/soc/lp_timer_struct.h (100%) rename components/soc/esp32c61/{include => register}/soc/lp_wdt_reg.h (100%) rename components/soc/esp32c61/{include => register}/soc/lp_wdt_struct.h (100%) rename components/soc/esp32c61/{include => register}/soc/lpperi_reg.h (100%) rename components/soc/esp32c61/{include => register}/soc/lpperi_struct.h (100%) rename components/soc/esp32c61/{include => register}/soc/mem_monitor_reg.h (100%) rename components/soc/esp32c61/{include => register}/soc/mem_monitor_struct.h (100%) rename components/soc/esp32c61/{include => register}/soc/pau_reg.h (100%) rename components/soc/esp32c61/{include => register}/soc/pau_struct.h (100%) rename components/soc/esp32c61/{include => register}/soc/pcr_reg.h (100%) rename components/soc/esp32c61/{include => register}/soc/pcr_struct.h (100%) rename components/soc/esp32c61/{include => register}/soc/pmu_reg.h (100%) rename components/soc/esp32c61/{include => register}/soc/pmu_struct.h (99%) rename components/soc/esp32c61/{include => register}/soc/pvt_reg.h (100%) rename components/soc/esp32c61/{include => register}/soc/pvt_struct.h (100%) rename components/soc/esp32c61/{include => register}/soc/reg_base.h (100%) rename components/soc/esp32c61/{include => register}/soc/sha_reg.h (98%) rename components/soc/esp32c61/{include => register}/soc/sha_struct.h (100%) rename components/soc/esp32c61/{include => register}/soc/soc_etm_reg.h (100%) rename components/soc/esp32c61/{include => register}/soc/soc_etm_struct.h (100%) rename components/soc/esp32c61/{include => register}/soc/spi1_mem_reg.h (100%) rename components/soc/esp32c61/{include => register}/soc/spi1_mem_struct.h (100%) rename components/soc/esp32c61/{include => register}/soc/spi_mem_c_reg.h (100%) rename components/soc/esp32c61/{include => register}/soc/spi_mem_c_struct.h (100%) rename components/soc/esp32c61/{include => register}/soc/spi_reg.h (99%) rename components/soc/esp32c61/{include => register}/soc/spi_struct.h (99%) rename components/soc/esp32c61/{include => register}/soc/systimer_reg.h (100%) rename components/soc/esp32c61/{include => register}/soc/systimer_struct.h (100%) rename components/soc/esp32c61/{include => register}/soc/tee_reg.h (100%) rename components/soc/esp32c61/{include => register}/soc/tee_struct.h (100%) rename components/soc/esp32c61/{include => register}/soc/timer_group_reg.h (100%) rename components/soc/esp32c61/{include => register}/soc/timer_group_struct.h (100%) rename components/soc/esp32c61/{include => register}/soc/trace_reg.h (98%) rename components/soc/esp32c61/{include => register}/soc/trace_struct.h (98%) rename components/soc/esp32c61/{include => register}/soc/uart_reg.h (100%) rename components/soc/esp32c61/{include => register}/soc/uart_struct.h (100%) rename components/soc/esp32c61/{include => register}/soc/usb_serial_jtag_reg.h (99%) rename components/soc/esp32c61/{include => register}/soc/usb_serial_jtag_struct.h (100%) rename components/soc/esp32c61/{include => register}/soc/xts_aes_reg.h (98%) diff --git a/components/soc/esp32c61/include/soc/dport_access.h b/components/soc/esp32c61/include/soc/dport_access.h index 85bdb9e6b8f..feacddca468 100644 --- a/components/soc/esp32c61/include/soc/dport_access.h +++ b/components/soc/esp32c61/include/soc/dport_access.h @@ -9,7 +9,6 @@ #include #include "soc.h" -#include "uart_reg.h" #ifdef __cplusplus extern "C" { diff --git a/components/soc/esp32c61/include/soc/soc.h b/components/soc/esp32c61/include/soc/soc.h index cd1b6e7537f..ca6ee32e031 100644 --- a/components/soc/esp32c61/include/soc/soc.h +++ b/components/soc/esp32c61/include/soc/soc.h @@ -12,7 +12,7 @@ #endif #include "esp_bit_defs.h" -#include "reg_base.h" +#include "soc/reg_base.h" #define PRO_CPU_NUM (0) diff --git a/components/soc/esp32c61/include/soc/system_reg.h b/components/soc/esp32c61/include/soc/system_reg.h index 4577fecbeb7..690bb496eb8 100644 --- a/components/soc/esp32c61/include/soc/system_reg.h +++ b/components/soc/esp32c61/include/soc/system_reg.h @@ -6,6 +6,6 @@ #include "soc/hp_system_reg.h" -#include "intpri_reg.h" +#include "soc/intpri_reg.h" #define SYSTEM_CPU_INTR_FROM_CPU_0_REG INTPRI_CPU_INTR_FROM_CPU_0_REG #define SYSTEM_CPU_INTR_FROM_CPU_0 INTPRI_CPU_INTR_FROM_CPU_0 diff --git a/components/soc/esp32c61/register/soc/.gitkeep b/components/soc/esp32c61/register/soc/.gitkeep deleted file mode 100644 index e69de29bb2d..00000000000 diff --git a/components/soc/esp32c61/include/soc/ahb_dma_reg.h b/components/soc/esp32c61/register/soc/ahb_dma_reg.h similarity index 100% rename from components/soc/esp32c61/include/soc/ahb_dma_reg.h rename to components/soc/esp32c61/register/soc/ahb_dma_reg.h diff --git a/components/soc/esp32c61/include/soc/ahb_dma_struct.h b/components/soc/esp32c61/register/soc/ahb_dma_struct.h similarity index 100% rename from components/soc/esp32c61/include/soc/ahb_dma_struct.h rename to components/soc/esp32c61/register/soc/ahb_dma_struct.h diff --git a/components/soc/esp32c61/include/soc/apb_saradc_reg.h b/components/soc/esp32c61/register/soc/apb_saradc_reg.h similarity index 100% rename from components/soc/esp32c61/include/soc/apb_saradc_reg.h rename to components/soc/esp32c61/register/soc/apb_saradc_reg.h diff --git a/components/soc/esp32c61/include/soc/apb_saradc_struct.h b/components/soc/esp32c61/register/soc/apb_saradc_struct.h similarity index 100% rename from components/soc/esp32c61/include/soc/apb_saradc_struct.h rename to components/soc/esp32c61/register/soc/apb_saradc_struct.h diff --git a/components/soc/esp32c61/include/soc/assist_debug_reg.h b/components/soc/esp32c61/register/soc/assist_debug_reg.h similarity index 99% rename from components/soc/esp32c61/include/soc/assist_debug_reg.h rename to components/soc/esp32c61/register/soc/assist_debug_reg.h index 4b7e6b6ff55..042490974ba 100644 --- a/components/soc/esp32c61/include/soc/assist_debug_reg.h +++ b/components/soc/esp32c61/register/soc/assist_debug_reg.h @@ -115,7 +115,7 @@ extern "C" { #define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_V 0x00000001U #define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_S 10 /** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA : R/W; bitpos: [11]; default: 0; - * DBUS busy monitor enbale + * DBUS busy monitor enable */ #define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA (BIT(11)) #define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_M (ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_V << ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_S) @@ -295,7 +295,7 @@ extern "C" { #define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_INTR_ENA_V 0x00000001U #define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_INTR_ENA_S 10 /** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA : R/W; bitpos: [11]; default: 0; - * DBUS busy monitor interrupt enbale + * DBUS busy monitor interrupt enable */ #define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA (BIT(11)) #define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA_M (ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA_V << ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA_S) diff --git a/components/soc/esp32c61/include/soc/assist_debug_struct.h b/components/soc/esp32c61/register/soc/assist_debug_struct.h similarity index 99% rename from components/soc/esp32c61/include/soc/assist_debug_struct.h rename to components/soc/esp32c61/register/soc/assist_debug_struct.h index 243b6959aa0..ca55d0cb8f6 100644 --- a/components/soc/esp32c61/include/soc/assist_debug_struct.h +++ b/components/soc/esp32c61/register/soc/assist_debug_struct.h @@ -83,7 +83,7 @@ typedef union { */ uint32_t core_0_iram0_exception_monitor_ena:1; /** core_0_dram0_exception_monitor_ena : R/W; bitpos: [11]; default: 0; - * DBUS busy monitor enbale + * DBUS busy monitor enable */ uint32_t core_0_dram0_exception_monitor_ena:1; uint32_t reserved_12:20; @@ -372,7 +372,7 @@ typedef union { */ uint32_t core_0_iram0_exception_monitor_intr_ena:1; /** core_0_dram0_exception_monitor_intr_ena : R/W; bitpos: [11]; default: 0; - * DBUS busy monitor interrupt enbale + * DBUS busy monitor interrupt enable */ uint32_t core_0_dram0_exception_monitor_intr_ena:1; uint32_t reserved_12:20; @@ -441,7 +441,7 @@ typedef union { } assist_debug_core_0_intr_clr_reg_t; -/** Group: pc reording configuration register */ +/** Group: pc recording configuration register */ /** Type of core_0_rcd_en register * HP CPU PC logging enable register */ @@ -465,7 +465,7 @@ typedef union { } assist_debug_core_0_rcd_en_reg_t; -/** Group: pc reording status register */ +/** Group: pc recording status register */ /** Type of core_0_rcd_pdebugpc register * PC logging register */ @@ -493,7 +493,7 @@ typedef union { } assist_debug_core_0_rcd_pdebugsp_reg_t; -/** Group: exception monitor regsiter */ +/** Group: exception monitor register */ /** Type of core_0_iram0_exception_monitor_0 register * exception monitor status register0 */ diff --git a/components/soc/esp32c61/include/soc/cache_reg.h b/components/soc/esp32c61/register/soc/cache_reg.h similarity index 99% rename from components/soc/esp32c61/include/soc/cache_reg.h rename to components/soc/esp32c61/register/soc/cache_reg.h index 98390f8e1ae..d0e294a28cb 100644 --- a/components/soc/esp32c61/include/soc/cache_reg.h +++ b/components/soc/esp32c61/register/soc/cache_reg.h @@ -4077,7 +4077,7 @@ extern "C" { #define CACHE_L1_UNALLOCATE_BUFFER_CLEAR_REG (DR_REG_CACHE_BASE + 0x254) /** CACHE_L1_ICACHE0_UNALLOC_CLR : HRO; bitpos: [0]; default: 0; * The bit is used to clear the unallocate request buffer of l1 icache0 where the - * unallocate request is responsed but not completed. + * unallocate request is responded but not completed. */ #define CACHE_L1_ICACHE0_UNALLOC_CLR (BIT(0)) #define CACHE_L1_ICACHE0_UNALLOC_CLR_M (CACHE_L1_ICACHE0_UNALLOC_CLR_V << CACHE_L1_ICACHE0_UNALLOC_CLR_S) @@ -4085,7 +4085,7 @@ extern "C" { #define CACHE_L1_ICACHE0_UNALLOC_CLR_S 0 /** CACHE_L1_ICACHE1_UNALLOC_CLR : HRO; bitpos: [1]; default: 0; * The bit is used to clear the unallocate request buffer of l1 icache1 where the - * unallocate request is responsed but not completed. + * unallocate request is responded but not completed. */ #define CACHE_L1_ICACHE1_UNALLOC_CLR (BIT(1)) #define CACHE_L1_ICACHE1_UNALLOC_CLR_M (CACHE_L1_ICACHE1_UNALLOC_CLR_V << CACHE_L1_ICACHE1_UNALLOC_CLR_S) @@ -4107,7 +4107,7 @@ extern "C" { #define CACHE_L1_ICACHE3_UNALLOC_CLR_S 3 /** CACHE_L1_CACHE_UNALLOC_CLR : R/W; bitpos: [4]; default: 0; * The bit is used to clear the unallocate request buffer of l1 cache where the - * unallocate request is responsed but not completed. + * unallocate request is responded but not completed. */ #define CACHE_L1_CACHE_UNALLOC_CLR (BIT(4)) #define CACHE_L1_CACHE_UNALLOC_CLR_M (CACHE_L1_CACHE_UNALLOC_CLR_V << CACHE_L1_CACHE_UNALLOC_CLR_S) @@ -5937,7 +5937,7 @@ extern "C" { #define CACHE_L2_UNALLOCATE_BUFFER_CLEAR_REG (DR_REG_CACHE_BASE + 0x3b0) /** CACHE_L2_CACHE_UNALLOC_CLR : HRO; bitpos: [5]; default: 0; * The bit is used to clear the unallocate request buffer of l2 icache where the - * unallocate request is responsed but not completed. + * unallocate request is responded but not completed. */ #define CACHE_L2_CACHE_UNALLOC_CLR (BIT(5)) #define CACHE_L2_CACHE_UNALLOC_CLR_M (CACHE_L2_CACHE_UNALLOC_CLR_V << CACHE_L2_CACHE_UNALLOC_CLR_S) diff --git a/components/soc/esp32c61/include/soc/cache_struct.h b/components/soc/esp32c61/register/soc/cache_struct.h similarity index 99% rename from components/soc/esp32c61/include/soc/cache_struct.h rename to components/soc/esp32c61/register/soc/cache_struct.h index f98620a26b3..408c01c2c78 100644 --- a/components/soc/esp32c61/include/soc/cache_struct.h +++ b/components/soc/esp32c61/register/soc/cache_struct.h @@ -5100,12 +5100,12 @@ typedef union { struct { /** l1_icache0_unalloc_clr : HRO; bitpos: [0]; default: 0; * The bit is used to clear the unallocate request buffer of l1 icache0 where the - * unallocate request is responsed but not completed. + * unallocate request is responded but not completed. */ uint32_t l1_icache0_unalloc_clr:1; /** l1_icache1_unalloc_clr : HRO; bitpos: [1]; default: 0; * The bit is used to clear the unallocate request buffer of l1 icache1 where the - * unallocate request is responsed but not completed. + * unallocate request is responded but not completed. */ uint32_t l1_icache1_unalloc_clr:1; /** l1_icache2_unalloc_clr : HRO; bitpos: [2]; default: 0; @@ -5118,7 +5118,7 @@ typedef union { uint32_t l1_icache3_unalloc_clr:1; /** l1_cache_unalloc_clr : R/W; bitpos: [4]; default: 0; * The bit is used to clear the unallocate request buffer of l1 cache where the - * unallocate request is responsed but not completed. + * unallocate request is responded but not completed. */ uint32_t l1_cache_unalloc_clr:1; uint32_t reserved_5:27; @@ -5134,7 +5134,7 @@ typedef union { uint32_t reserved_0:5; /** l2_cache_unalloc_clr : HRO; bitpos: [5]; default: 0; * The bit is used to clear the unallocate request buffer of l2 icache where the - * unallocate request is responsed but not completed. + * unallocate request is responded but not completed. */ uint32_t l2_cache_unalloc_clr:1; uint32_t reserved_6:26; diff --git a/components/soc/esp32c61/include/soc/clic_reg.h b/components/soc/esp32c61/register/soc/clic_reg.h similarity index 100% rename from components/soc/esp32c61/include/soc/clic_reg.h rename to components/soc/esp32c61/register/soc/clic_reg.h diff --git a/components/soc/esp32c61/include/soc/clint_reg.h b/components/soc/esp32c61/register/soc/clint_reg.h similarity index 100% rename from components/soc/esp32c61/include/soc/clint_reg.h rename to components/soc/esp32c61/register/soc/clint_reg.h diff --git a/components/soc/esp32c61/include/soc/ecc_mult_reg.h b/components/soc/esp32c61/register/soc/ecc_mult_reg.h similarity index 100% rename from components/soc/esp32c61/include/soc/ecc_mult_reg.h rename to components/soc/esp32c61/register/soc/ecc_mult_reg.h diff --git a/components/soc/esp32c61/include/soc/ecc_mult_struct.h b/components/soc/esp32c61/register/soc/ecc_mult_struct.h similarity index 100% rename from components/soc/esp32c61/include/soc/ecc_mult_struct.h rename to components/soc/esp32c61/register/soc/ecc_mult_struct.h diff --git a/components/soc/esp32c61/include/soc/ecdsa_reg.h b/components/soc/esp32c61/register/soc/ecdsa_reg.h similarity index 98% rename from components/soc/esp32c61/include/soc/ecdsa_reg.h rename to components/soc/esp32c61/register/soc/ecdsa_reg.h index aca4b64b199..4893390ced6 100644 --- a/components/soc/esp32c61/include/soc/ecdsa_reg.h +++ b/components/soc/esp32c61/register/soc/ecdsa_reg.h @@ -211,7 +211,7 @@ extern "C" { */ #define ECDSA_START_REG (DR_REG_ECDSA_BASE + 0x1c) /** ECDSA_START : WT; bitpos: [0]; default: 0; - * Write 1 to start caculation of ECDSA Accelerator. This bit will be self-cleared + * Write 1 to start calculation of ECDSA Accelerator. This bit will be self-cleared * after configuration. */ #define ECDSA_START (BIT(0)) @@ -299,7 +299,7 @@ extern "C" { */ #define ECDSA_SHA_START_REG (DR_REG_ECDSA_BASE + 0x210) /** ECDSA_SHA_START : WT; bitpos: [0]; default: 0; - * Write 1 to start the first caculation of SHA Calculator in ECDSA Accelerator. This + * Write 1 to start the first calculation of SHA Calculator in ECDSA Accelerator. This * bit will be self-cleared after configuration. */ #define ECDSA_SHA_START (BIT(0)) @@ -312,7 +312,7 @@ extern "C" { */ #define ECDSA_SHA_CONTINUE_REG (DR_REG_ECDSA_BASE + 0x214) /** ECDSA_SHA_CONTINUE : WT; bitpos: [0]; default: 0; - * Write 1 to start the latter caculation of SHA Calculator in ECDSA Accelerator. This + * Write 1 to start the latter calculation of SHA Calculator in ECDSA Accelerator. This * bit will be self-cleared after configuration. */ #define ECDSA_SHA_CONTINUE (BIT(0)) diff --git a/components/soc/esp32c61/include/soc/ecdsa_struct.h b/components/soc/esp32c61/register/soc/ecdsa_struct.h similarity index 97% rename from components/soc/esp32c61/include/soc/ecdsa_struct.h rename to components/soc/esp32c61/register/soc/ecdsa_struct.h index bed383c9da0..858a4ffc5f8 100644 --- a/components/soc/esp32c61/include/soc/ecdsa_struct.h +++ b/components/soc/esp32c61/register/soc/ecdsa_struct.h @@ -57,7 +57,7 @@ typedef union { typedef union { struct { /** start : WT; bitpos: [0]; default: 0; - * Write 1 to start caculation of ECDSA Accelerator. This bit will be self-cleared + * Write 1 to start calculation of ECDSA Accelerator. This bit will be self-cleared * after configuration. */ uint32_t start:1; @@ -260,7 +260,7 @@ typedef union { typedef union { struct { /** sha_start : WT; bitpos: [0]; default: 0; - * Write 1 to start the first caculation of SHA Calculator in ECDSA Accelerator. This + * Write 1 to start the first calculation of SHA Calculator in ECDSA Accelerator. This * bit will be self-cleared after configuration. */ uint32_t sha_start:1; @@ -275,7 +275,7 @@ typedef union { typedef union { struct { /** sha_continue : WT; bitpos: [0]; default: 0; - * Write 1 to start the latter caculation of SHA Calculator in ECDSA Accelerator. This + * Write 1 to start the latter calculation of SHA Calculator in ECDSA Accelerator. This * bit will be self-cleared after configuration. */ uint32_t sha_continue:1; diff --git a/components/soc/esp32c61/include/soc/efuse_reg.h b/components/soc/esp32c61/register/soc/efuse_reg.h similarity index 100% rename from components/soc/esp32c61/include/soc/efuse_reg.h rename to components/soc/esp32c61/register/soc/efuse_reg.h diff --git a/components/soc/esp32c61/include/soc/efuse_struct.h b/components/soc/esp32c61/register/soc/efuse_struct.h similarity index 100% rename from components/soc/esp32c61/include/soc/efuse_struct.h rename to components/soc/esp32c61/register/soc/efuse_struct.h diff --git a/components/soc/esp32c61/include/soc/gpio_ext_reg.h b/components/soc/esp32c61/register/soc/gpio_ext_reg.h similarity index 99% rename from components/soc/esp32c61/include/soc/gpio_ext_reg.h rename to components/soc/esp32c61/register/soc/gpio_ext_reg.h index 26effdee28f..2385576c333 100644 --- a/components/soc/esp32c61/include/soc/gpio_ext_reg.h +++ b/components/soc/esp32c61/register/soc/gpio_ext_reg.h @@ -37,7 +37,7 @@ extern "C" { #define GPIO_EXT_XPD_COMP_0_V 0x00000001U #define GPIO_EXT_XPD_COMP_0_S 0 /** GPIO_EXT_MODE_COMP_0 : R/W; bitpos: [1]; default: 0; - * Configures the reference voltage for analog PAD voltage comparater.. \\ + * Configures the reference voltage for analog PAD voltage comparator.. \\ * 0: Reference voltage is the internal reference voltage, meanwhile GPIO8 PAD can be * used as a regular GPIO\\ * 1: Reference voltage is the voltage on the GPIO8 PAD\\ diff --git a/components/soc/esp32c61/include/soc/gpio_ext_struct.h b/components/soc/esp32c61/register/soc/gpio_ext_struct.h similarity index 99% rename from components/soc/esp32c61/include/soc/gpio_ext_struct.h rename to components/soc/esp32c61/register/soc/gpio_ext_struct.h index f02a5fec8a1..a31ace9505e 100644 --- a/components/soc/esp32c61/include/soc/gpio_ext_struct.h +++ b/components/soc/esp32c61/register/soc/gpio_ext_struct.h @@ -39,7 +39,7 @@ typedef union { */ uint32_t xpd_comp_0:1; /** mode_comp_0 : R/W; bitpos: [1]; default: 0; - * Configures the reference voltage for analog PAD voltage comparater.. \\ + * Configures the reference voltage for analog PAD voltage comparator.. \\ * 0: Reference voltage is the internal reference voltage, meanwhile GPIO8 PAD can be * used as a regular GPIO\\ * 1: Reference voltage is the voltage on the GPIO8 PAD\\ diff --git a/components/soc/esp32c61/include/soc/gpio_reg.h b/components/soc/esp32c61/register/soc/gpio_reg.h similarity index 100% rename from components/soc/esp32c61/include/soc/gpio_reg.h rename to components/soc/esp32c61/register/soc/gpio_reg.h diff --git a/components/soc/esp32c61/include/soc/gpio_struct.h b/components/soc/esp32c61/register/soc/gpio_struct.h similarity index 100% rename from components/soc/esp32c61/include/soc/gpio_struct.h rename to components/soc/esp32c61/register/soc/gpio_struct.h diff --git a/components/soc/esp32c61/include/soc/hp_apm_reg.h b/components/soc/esp32c61/register/soc/hp_apm_reg.h similarity index 100% rename from components/soc/esp32c61/include/soc/hp_apm_reg.h rename to components/soc/esp32c61/register/soc/hp_apm_reg.h diff --git a/components/soc/esp32c61/include/soc/hp_apm_struct.h b/components/soc/esp32c61/register/soc/hp_apm_struct.h similarity index 100% rename from components/soc/esp32c61/include/soc/hp_apm_struct.h rename to components/soc/esp32c61/register/soc/hp_apm_struct.h diff --git a/components/soc/esp32c61/include/soc/hp_system_reg.h b/components/soc/esp32c61/register/soc/hp_system_reg.h similarity index 100% rename from components/soc/esp32c61/include/soc/hp_system_reg.h rename to components/soc/esp32c61/register/soc/hp_system_reg.h diff --git a/components/soc/esp32c61/include/soc/hp_system_struct.h b/components/soc/esp32c61/register/soc/hp_system_struct.h similarity index 100% rename from components/soc/esp32c61/include/soc/hp_system_struct.h rename to components/soc/esp32c61/register/soc/hp_system_struct.h diff --git a/components/soc/esp32c61/include/soc/i2c_ana_mst_reg.h b/components/soc/esp32c61/register/soc/i2c_ana_mst_reg.h similarity index 100% rename from components/soc/esp32c61/include/soc/i2c_ana_mst_reg.h rename to components/soc/esp32c61/register/soc/i2c_ana_mst_reg.h diff --git a/components/soc/esp32c61/include/soc/i2c_reg.h b/components/soc/esp32c61/register/soc/i2c_reg.h similarity index 100% rename from components/soc/esp32c61/include/soc/i2c_reg.h rename to components/soc/esp32c61/register/soc/i2c_reg.h diff --git a/components/soc/esp32c61/include/soc/i2c_struct.h b/components/soc/esp32c61/register/soc/i2c_struct.h similarity index 100% rename from components/soc/esp32c61/include/soc/i2c_struct.h rename to components/soc/esp32c61/register/soc/i2c_struct.h diff --git a/components/soc/esp32c61/include/soc/i2s_reg.h b/components/soc/esp32c61/register/soc/i2s_reg.h similarity index 99% rename from components/soc/esp32c61/include/soc/i2s_reg.h rename to components/soc/esp32c61/register/soc/i2s_reg.h index a7f16f4d612..b82a41f3218 100644 --- a/components/soc/esp32c61/include/soc/i2s_reg.h +++ b/components/soc/esp32c61/register/soc/i2s_reg.h @@ -320,7 +320,7 @@ extern "C" { #define I2S_TX_SLAVE_MOD_V 0x00000001U #define I2S_TX_SLAVE_MOD_S 3 /** I2S_TX_STOP_EN : R/W; bitpos: [4]; default: 1; - * Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy + * Set this bit to stop disable output BCK signal and WS signal when tx FIFO is empty */ #define I2S_TX_STOP_EN (BIT(4)) #define I2S_TX_STOP_EN_M (I2S_TX_STOP_EN_V << I2S_TX_STOP_EN_S) diff --git a/components/soc/esp32c61/include/soc/i2s_struct.h b/components/soc/esp32c61/register/soc/i2s_struct.h similarity index 99% rename from components/soc/esp32c61/include/soc/i2s_struct.h rename to components/soc/esp32c61/register/soc/i2s_struct.h index a0ff42939e7..9cb119af5e6 100644 --- a/components/soc/esp32c61/include/soc/i2s_struct.h +++ b/components/soc/esp32c61/register/soc/i2s_struct.h @@ -410,7 +410,7 @@ typedef union { */ uint32_t tx_slave_mod:1; /** tx_stop_en : R/W; bitpos: [4]; default: 1; - * Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy + * Set this bit to stop disable output BCK signal and WS signal when tx FIFO is empty */ uint32_t tx_stop_en:1; /** tx_chan_equal : R/W; bitpos: [5]; default: 0; diff --git a/components/soc/esp32c61/include/soc/interrupt_matrix_reg.h b/components/soc/esp32c61/register/soc/interrupt_matrix_reg.h similarity index 100% rename from components/soc/esp32c61/include/soc/interrupt_matrix_reg.h rename to components/soc/esp32c61/register/soc/interrupt_matrix_reg.h diff --git a/components/soc/esp32c61/include/soc/interrupt_matrix_struct.h b/components/soc/esp32c61/register/soc/interrupt_matrix_struct.h similarity index 100% rename from components/soc/esp32c61/include/soc/interrupt_matrix_struct.h rename to components/soc/esp32c61/register/soc/interrupt_matrix_struct.h diff --git a/components/soc/esp32c61/include/soc/intpri_reg.h b/components/soc/esp32c61/register/soc/intpri_reg.h similarity index 100% rename from components/soc/esp32c61/include/soc/intpri_reg.h rename to components/soc/esp32c61/register/soc/intpri_reg.h diff --git a/components/soc/esp32c61/include/soc/intpri_struct.h b/components/soc/esp32c61/register/soc/intpri_struct.h similarity index 100% rename from components/soc/esp32c61/include/soc/intpri_struct.h rename to components/soc/esp32c61/register/soc/intpri_struct.h diff --git a/components/soc/esp32c61/include/soc/io_mux_reg.h b/components/soc/esp32c61/register/soc/io_mux_reg.h similarity index 100% rename from components/soc/esp32c61/include/soc/io_mux_reg.h rename to components/soc/esp32c61/register/soc/io_mux_reg.h diff --git a/components/soc/esp32c61/include/soc/io_mux_struct.h b/components/soc/esp32c61/register/soc/io_mux_struct.h similarity index 100% rename from components/soc/esp32c61/include/soc/io_mux_struct.h rename to components/soc/esp32c61/register/soc/io_mux_struct.h diff --git a/components/soc/esp32c61/include/soc/ledc_reg.h b/components/soc/esp32c61/register/soc/ledc_reg.h similarity index 100% rename from components/soc/esp32c61/include/soc/ledc_reg.h rename to components/soc/esp32c61/register/soc/ledc_reg.h diff --git a/components/soc/esp32c61/include/soc/ledc_struct.h b/components/soc/esp32c61/register/soc/ledc_struct.h similarity index 100% rename from components/soc/esp32c61/include/soc/ledc_struct.h rename to components/soc/esp32c61/register/soc/ledc_struct.h diff --git a/components/soc/esp32c61/include/soc/lp_analog_peri_reg.h b/components/soc/esp32c61/register/soc/lp_analog_peri_reg.h similarity index 100% rename from components/soc/esp32c61/include/soc/lp_analog_peri_reg.h rename to components/soc/esp32c61/register/soc/lp_analog_peri_reg.h diff --git a/components/soc/esp32c61/include/soc/lp_analog_peri_struct.h b/components/soc/esp32c61/register/soc/lp_analog_peri_struct.h similarity index 100% rename from components/soc/esp32c61/include/soc/lp_analog_peri_struct.h rename to components/soc/esp32c61/register/soc/lp_analog_peri_struct.h diff --git a/components/soc/esp32c61/include/soc/lp_aon_reg.h b/components/soc/esp32c61/register/soc/lp_aon_reg.h similarity index 100% rename from components/soc/esp32c61/include/soc/lp_aon_reg.h rename to components/soc/esp32c61/register/soc/lp_aon_reg.h diff --git a/components/soc/esp32c61/include/soc/lp_aon_struct.h b/components/soc/esp32c61/register/soc/lp_aon_struct.h similarity index 100% rename from components/soc/esp32c61/include/soc/lp_aon_struct.h rename to components/soc/esp32c61/register/soc/lp_aon_struct.h diff --git a/components/soc/esp32c61/include/soc/lp_apm_reg.h b/components/soc/esp32c61/register/soc/lp_apm_reg.h similarity index 100% rename from components/soc/esp32c61/include/soc/lp_apm_reg.h rename to components/soc/esp32c61/register/soc/lp_apm_reg.h diff --git a/components/soc/esp32c61/include/soc/lp_apm_struct.h b/components/soc/esp32c61/register/soc/lp_apm_struct.h similarity index 100% rename from components/soc/esp32c61/include/soc/lp_apm_struct.h rename to components/soc/esp32c61/register/soc/lp_apm_struct.h diff --git a/components/soc/esp32c61/include/soc/lp_clkrst_reg.h b/components/soc/esp32c61/register/soc/lp_clkrst_reg.h similarity index 99% rename from components/soc/esp32c61/include/soc/lp_clkrst_reg.h rename to components/soc/esp32c61/register/soc/lp_clkrst_reg.h index 55d2fb2315f..755a7c3c635 100644 --- a/components/soc/esp32c61/include/soc/lp_clkrst_reg.h +++ b/components/soc/esp32c61/register/soc/lp_clkrst_reg.h @@ -211,7 +211,7 @@ extern "C" { #define LP_CLKRST_ANA_PERI_RESET_EN_S 31 /** LP_CLKRST_RESET_CAUSE_REG register - * Represents the reset casue + * Represents the reset cause */ #define LP_CLKRST_RESET_CAUSE_REG (DR_REG_LP_CLKRST_BASE + 0x10) /** LP_CLKRST_RESET_CAUSE : RO; bitpos: [4:0]; default: 0; diff --git a/components/soc/esp32c61/include/soc/lp_clkrst_struct.h b/components/soc/esp32c61/register/soc/lp_clkrst_struct.h similarity index 99% rename from components/soc/esp32c61/include/soc/lp_clkrst_struct.h rename to components/soc/esp32c61/register/soc/lp_clkrst_struct.h index 685b5245872..2c69f169a57 100644 --- a/components/soc/esp32c61/include/soc/lp_clkrst_struct.h +++ b/components/soc/esp32c61/register/soc/lp_clkrst_struct.h @@ -171,7 +171,7 @@ typedef union { } lp_clkrst_lp_rst_en_reg_t; /** Type of reset_cause register - * Represents the reset casue + * Represents the reset cause */ typedef union { struct { diff --git a/components/soc/esp32c61/include/soc/lp_gpio_reg.h b/components/soc/esp32c61/register/soc/lp_gpio_reg.h similarity index 100% rename from components/soc/esp32c61/include/soc/lp_gpio_reg.h rename to components/soc/esp32c61/register/soc/lp_gpio_reg.h diff --git a/components/soc/esp32c61/include/soc/lp_gpio_struct.h b/components/soc/esp32c61/register/soc/lp_gpio_struct.h similarity index 100% rename from components/soc/esp32c61/include/soc/lp_gpio_struct.h rename to components/soc/esp32c61/register/soc/lp_gpio_struct.h diff --git a/components/soc/esp32c61/include/soc/lp_iomux_reg.h b/components/soc/esp32c61/register/soc/lp_iomux_reg.h similarity index 100% rename from components/soc/esp32c61/include/soc/lp_iomux_reg.h rename to components/soc/esp32c61/register/soc/lp_iomux_reg.h diff --git a/components/soc/esp32c61/include/soc/lp_iomux_struct.h b/components/soc/esp32c61/register/soc/lp_iomux_struct.h similarity index 100% rename from components/soc/esp32c61/include/soc/lp_iomux_struct.h rename to components/soc/esp32c61/register/soc/lp_iomux_struct.h diff --git a/components/soc/esp32c61/include/soc/lp_tee_reg.h b/components/soc/esp32c61/register/soc/lp_tee_reg.h similarity index 100% rename from components/soc/esp32c61/include/soc/lp_tee_reg.h rename to components/soc/esp32c61/register/soc/lp_tee_reg.h diff --git a/components/soc/esp32c61/include/soc/lp_tee_struct.h b/components/soc/esp32c61/register/soc/lp_tee_struct.h similarity index 100% rename from components/soc/esp32c61/include/soc/lp_tee_struct.h rename to components/soc/esp32c61/register/soc/lp_tee_struct.h diff --git a/components/soc/esp32c61/include/soc/lp_timer_reg.h b/components/soc/esp32c61/register/soc/lp_timer_reg.h similarity index 100% rename from components/soc/esp32c61/include/soc/lp_timer_reg.h rename to components/soc/esp32c61/register/soc/lp_timer_reg.h diff --git a/components/soc/esp32c61/include/soc/lp_timer_struct.h b/components/soc/esp32c61/register/soc/lp_timer_struct.h similarity index 100% rename from components/soc/esp32c61/include/soc/lp_timer_struct.h rename to components/soc/esp32c61/register/soc/lp_timer_struct.h diff --git a/components/soc/esp32c61/include/soc/lp_wdt_reg.h b/components/soc/esp32c61/register/soc/lp_wdt_reg.h similarity index 100% rename from components/soc/esp32c61/include/soc/lp_wdt_reg.h rename to components/soc/esp32c61/register/soc/lp_wdt_reg.h diff --git a/components/soc/esp32c61/include/soc/lp_wdt_struct.h b/components/soc/esp32c61/register/soc/lp_wdt_struct.h similarity index 100% rename from components/soc/esp32c61/include/soc/lp_wdt_struct.h rename to components/soc/esp32c61/register/soc/lp_wdt_struct.h diff --git a/components/soc/esp32c61/include/soc/lpperi_reg.h b/components/soc/esp32c61/register/soc/lpperi_reg.h similarity index 100% rename from components/soc/esp32c61/include/soc/lpperi_reg.h rename to components/soc/esp32c61/register/soc/lpperi_reg.h diff --git a/components/soc/esp32c61/include/soc/lpperi_struct.h b/components/soc/esp32c61/register/soc/lpperi_struct.h similarity index 100% rename from components/soc/esp32c61/include/soc/lpperi_struct.h rename to components/soc/esp32c61/register/soc/lpperi_struct.h diff --git a/components/soc/esp32c61/include/soc/mem_monitor_reg.h b/components/soc/esp32c61/register/soc/mem_monitor_reg.h similarity index 100% rename from components/soc/esp32c61/include/soc/mem_monitor_reg.h rename to components/soc/esp32c61/register/soc/mem_monitor_reg.h diff --git a/components/soc/esp32c61/include/soc/mem_monitor_struct.h b/components/soc/esp32c61/register/soc/mem_monitor_struct.h similarity index 100% rename from components/soc/esp32c61/include/soc/mem_monitor_struct.h rename to components/soc/esp32c61/register/soc/mem_monitor_struct.h diff --git a/components/soc/esp32c61/include/soc/pau_reg.h b/components/soc/esp32c61/register/soc/pau_reg.h similarity index 100% rename from components/soc/esp32c61/include/soc/pau_reg.h rename to components/soc/esp32c61/register/soc/pau_reg.h diff --git a/components/soc/esp32c61/include/soc/pau_struct.h b/components/soc/esp32c61/register/soc/pau_struct.h similarity index 100% rename from components/soc/esp32c61/include/soc/pau_struct.h rename to components/soc/esp32c61/register/soc/pau_struct.h diff --git a/components/soc/esp32c61/include/soc/pcr_reg.h b/components/soc/esp32c61/register/soc/pcr_reg.h similarity index 100% rename from components/soc/esp32c61/include/soc/pcr_reg.h rename to components/soc/esp32c61/register/soc/pcr_reg.h diff --git a/components/soc/esp32c61/include/soc/pcr_struct.h b/components/soc/esp32c61/register/soc/pcr_struct.h similarity index 100% rename from components/soc/esp32c61/include/soc/pcr_struct.h rename to components/soc/esp32c61/register/soc/pcr_struct.h diff --git a/components/soc/esp32c61/include/soc/pmu_reg.h b/components/soc/esp32c61/register/soc/pmu_reg.h similarity index 100% rename from components/soc/esp32c61/include/soc/pmu_reg.h rename to components/soc/esp32c61/register/soc/pmu_reg.h diff --git a/components/soc/esp32c61/include/soc/pmu_struct.h b/components/soc/esp32c61/register/soc/pmu_struct.h similarity index 99% rename from components/soc/esp32c61/include/soc/pmu_struct.h rename to components/soc/esp32c61/register/soc/pmu_struct.h index 3e2f9fb16f6..e59470be4e9 100644 --- a/components/soc/esp32c61/include/soc/pmu_struct.h +++ b/components/soc/esp32c61/register/soc/pmu_struct.h @@ -11,7 +11,7 @@ extern "C" { #endif -#include "soc.h" +#include "soc/soc.h" #include "soc/pmu_reg.h" typedef union { diff --git a/components/soc/esp32c61/include/soc/pvt_reg.h b/components/soc/esp32c61/register/soc/pvt_reg.h similarity index 100% rename from components/soc/esp32c61/include/soc/pvt_reg.h rename to components/soc/esp32c61/register/soc/pvt_reg.h diff --git a/components/soc/esp32c61/include/soc/pvt_struct.h b/components/soc/esp32c61/register/soc/pvt_struct.h similarity index 100% rename from components/soc/esp32c61/include/soc/pvt_struct.h rename to components/soc/esp32c61/register/soc/pvt_struct.h diff --git a/components/soc/esp32c61/include/soc/reg_base.h b/components/soc/esp32c61/register/soc/reg_base.h similarity index 100% rename from components/soc/esp32c61/include/soc/reg_base.h rename to components/soc/esp32c61/register/soc/reg_base.h diff --git a/components/soc/esp32c61/include/soc/sha_reg.h b/components/soc/esp32c61/register/soc/sha_reg.h similarity index 98% rename from components/soc/esp32c61/include/soc/sha_reg.h rename to components/soc/esp32c61/register/soc/sha_reg.h index ab9f346e774..4dd7f4a2d9d 100644 --- a/components/soc/esp32c61/include/soc/sha_reg.h +++ b/components/soc/esp32c61/register/soc/sha_reg.h @@ -161,7 +161,7 @@ extern "C" { #define SHA_DATE_S 0 /** SHA_H_MEM register - * Sha H memory which contains intermediate hash or finial hash. + * Sha H memory which contains intermediate hash or final hash. */ #define SHA_H_MEM (DR_REG_SHA_BASE + 0x40) #define SHA_H_MEM_SIZE_BYTES 64 diff --git a/components/soc/esp32c61/include/soc/sha_struct.h b/components/soc/esp32c61/register/soc/sha_struct.h similarity index 100% rename from components/soc/esp32c61/include/soc/sha_struct.h rename to components/soc/esp32c61/register/soc/sha_struct.h diff --git a/components/soc/esp32c61/include/soc/soc_etm_reg.h b/components/soc/esp32c61/register/soc/soc_etm_reg.h similarity index 100% rename from components/soc/esp32c61/include/soc/soc_etm_reg.h rename to components/soc/esp32c61/register/soc/soc_etm_reg.h diff --git a/components/soc/esp32c61/include/soc/soc_etm_struct.h b/components/soc/esp32c61/register/soc/soc_etm_struct.h similarity index 100% rename from components/soc/esp32c61/include/soc/soc_etm_struct.h rename to components/soc/esp32c61/register/soc/soc_etm_struct.h diff --git a/components/soc/esp32c61/include/soc/spi1_mem_reg.h b/components/soc/esp32c61/register/soc/spi1_mem_reg.h similarity index 100% rename from components/soc/esp32c61/include/soc/spi1_mem_reg.h rename to components/soc/esp32c61/register/soc/spi1_mem_reg.h diff --git a/components/soc/esp32c61/include/soc/spi1_mem_struct.h b/components/soc/esp32c61/register/soc/spi1_mem_struct.h similarity index 100% rename from components/soc/esp32c61/include/soc/spi1_mem_struct.h rename to components/soc/esp32c61/register/soc/spi1_mem_struct.h diff --git a/components/soc/esp32c61/include/soc/spi_mem_c_reg.h b/components/soc/esp32c61/register/soc/spi_mem_c_reg.h similarity index 100% rename from components/soc/esp32c61/include/soc/spi_mem_c_reg.h rename to components/soc/esp32c61/register/soc/spi_mem_c_reg.h diff --git a/components/soc/esp32c61/include/soc/spi_mem_c_struct.h b/components/soc/esp32c61/register/soc/spi_mem_c_struct.h similarity index 100% rename from components/soc/esp32c61/include/soc/spi_mem_c_struct.h rename to components/soc/esp32c61/register/soc/spi_mem_c_struct.h diff --git a/components/soc/esp32c61/include/soc/spi_reg.h b/components/soc/esp32c61/register/soc/spi_reg.h similarity index 99% rename from components/soc/esp32c61/include/soc/spi_reg.h rename to components/soc/esp32c61/register/soc/spi_reg.h index 66a09daf9f3..a0e934fcc24 100644 --- a/components/soc/esp32c61/include/soc/spi_reg.h +++ b/components/soc/esp32c61/register/soc/spi_reg.h @@ -273,7 +273,7 @@ extern "C" { /** SPI_CLK_EQU_SYSCLK : R/W; bitpos: [31]; default: 1; * Configures whether or not the SPI_CLK is equal to APB_CLK in master transfer.\\ * 0: SPI_CLK is divided from APB_CLK.\\ - * 1: SPI_CLK is eqaul to APB_CLK.\\ + * 1: SPI_CLK is equal to APB_CLK.\\ * Can be configured in CONF state. */ #define SPI_CLK_EQU_SYSCLK (BIT(31)) diff --git a/components/soc/esp32c61/include/soc/spi_struct.h b/components/soc/esp32c61/register/soc/spi_struct.h similarity index 99% rename from components/soc/esp32c61/include/soc/spi_struct.h rename to components/soc/esp32c61/register/soc/spi_struct.h index 7b84c9d658d..88690647ed5 100644 --- a/components/soc/esp32c61/include/soc/spi_struct.h +++ b/components/soc/esp32c61/register/soc/spi_struct.h @@ -819,7 +819,7 @@ typedef union { /** clk_equ_sysclk : R/W; bitpos: [31]; default: 1; * Configures whether or not the SPI_CLK is equal to APB_CLK in master transfer.\\ * 0: SPI_CLK is divided from APB_CLK.\\ - * 1: SPI_CLK is eqaul to APB_CLK.\\ + * 1: SPI_CLK is equal to APB_CLK.\\ * Can be configured in CONF state. */ uint32_t clk_equ_sysclk:1; diff --git a/components/soc/esp32c61/include/soc/systimer_reg.h b/components/soc/esp32c61/register/soc/systimer_reg.h similarity index 100% rename from components/soc/esp32c61/include/soc/systimer_reg.h rename to components/soc/esp32c61/register/soc/systimer_reg.h diff --git a/components/soc/esp32c61/include/soc/systimer_struct.h b/components/soc/esp32c61/register/soc/systimer_struct.h similarity index 100% rename from components/soc/esp32c61/include/soc/systimer_struct.h rename to components/soc/esp32c61/register/soc/systimer_struct.h diff --git a/components/soc/esp32c61/include/soc/tee_reg.h b/components/soc/esp32c61/register/soc/tee_reg.h similarity index 100% rename from components/soc/esp32c61/include/soc/tee_reg.h rename to components/soc/esp32c61/register/soc/tee_reg.h diff --git a/components/soc/esp32c61/include/soc/tee_struct.h b/components/soc/esp32c61/register/soc/tee_struct.h similarity index 100% rename from components/soc/esp32c61/include/soc/tee_struct.h rename to components/soc/esp32c61/register/soc/tee_struct.h diff --git a/components/soc/esp32c61/include/soc/timer_group_reg.h b/components/soc/esp32c61/register/soc/timer_group_reg.h similarity index 100% rename from components/soc/esp32c61/include/soc/timer_group_reg.h rename to components/soc/esp32c61/register/soc/timer_group_reg.h diff --git a/components/soc/esp32c61/include/soc/timer_group_struct.h b/components/soc/esp32c61/register/soc/timer_group_struct.h similarity index 100% rename from components/soc/esp32c61/include/soc/timer_group_struct.h rename to components/soc/esp32c61/register/soc/timer_group_struct.h diff --git a/components/soc/esp32c61/include/soc/trace_reg.h b/components/soc/esp32c61/register/soc/trace_reg.h similarity index 98% rename from components/soc/esp32c61/include/soc/trace_reg.h rename to components/soc/esp32c61/register/soc/trace_reg.h index 1abfbbcd045..785965af2c7 100644 --- a/components/soc/esp32c61/include/soc/trace_reg.h +++ b/components/soc/esp32c61/register/soc/trace_reg.h @@ -76,7 +76,7 @@ extern "C" { #define TRACE_FIFO_EMPTY_S 0 /** TRACE_WORK_STATUS : RO; bitpos: [2:1]; default: 0; * Represent the state of the encoder: \\0: Idle state \\1: Working state\\ 2: Wait - * state becasue hart is halted or in reset \\3: Lost state\\ + * state because hart is halted or in reset \\3: Lost state\\ */ #define TRACE_WORK_STATUS 0x00000003U #define TRACE_WORK_STATUS_M (TRACE_WORK_STATUS_V << TRACE_WORK_STATUS_S) @@ -186,7 +186,7 @@ extern "C" { #define TRACE_DM_TRIGGER_ENA_V 0x00000001U #define TRACE_DM_TRIGGER_ENA_S 0 /** TRACE_RESET_ENA : R/W; bitpos: [1]; default: 0; - * Configure whether to reset, when enabeld, if cpu have reset, the encoder will + * Configure whether to reset, when enabled, if cpu have reset, the encoder will * output a packet to report the address of the last instruction, and upon reset * deassertion, the encoder start again.\\0: Disable\\0: Enable\\ */ @@ -216,7 +216,7 @@ extern "C" { #define TRACE_FULL_ADDRESS_V 0x00000001U #define TRACE_FULL_ADDRESS_S 4 /** TRACE_IMPLICIT_EXCEPT : R/W; bitpos: [5]; default: 0; - * Configure whether or not enabel implicit exception mode. When enabled,, do not sent + * Configure whether or not enable implicit exception mode. When enabled,, do not sent * exception address, only exception cause in exception packets.\\1: enabled\\0: * disabled\\ */ @@ -418,7 +418,7 @@ extern "C" { */ #define TRACE_AHB_CONFIG_REG (DR_REG_TRACE_BASE + 0x40) /** TRACE_HBURST : R/W; bitpos: [2:0]; default: 0; - * Configures the AHB burst mode. \\0: SIGNLE \\1: INCR(length not defined) \\2:INCR4 + * Configures the AHB burst mode. \\0: SINGLE \\1: INCR(length not defined) \\2:INCR4 * \\4:INCR8 \\Others:Invalid */ #define TRACE_HBURST 0x00000007U @@ -440,7 +440,7 @@ extern "C" { /** TRACE_CLK_EN : R/W; bitpos: [0]; default: 1; * Configures register clock gating. \\0: Support clock only when the application * writes registers to save power. \\1:Always force the clock on for registers \\ This - * bit does't affect register access. + * bit doesn't affect register access. */ #define TRACE_CLK_EN (BIT(0)) #define TRACE_CLK_EN_M (TRACE_CLK_EN_V << TRACE_CLK_EN_S) diff --git a/components/soc/esp32c61/include/soc/trace_struct.h b/components/soc/esp32c61/register/soc/trace_struct.h similarity index 98% rename from components/soc/esp32c61/include/soc/trace_struct.h rename to components/soc/esp32c61/register/soc/trace_struct.h index a8337ed0fdb..1b73fe2666f 100644 --- a/components/soc/esp32c61/include/soc/trace_struct.h +++ b/components/soc/esp32c61/register/soc/trace_struct.h @@ -81,7 +81,7 @@ typedef union { uint32_t fifo_empty:1; /** work_status : RO; bitpos: [2:1]; default: 0; * Represent the state of the encoder: \\0: Idle state \\1: Working state\\ 2: Wait - * state becasue hart is halted or in reset \\3: Lost state\\ + * state because hart is halted or in reset \\3: Lost state\\ */ uint32_t work_status:2; uint32_t reserved_3:29; @@ -184,7 +184,7 @@ typedef union { */ uint32_t dm_trigger_ena:1; /** reset_ena : R/W; bitpos: [1]; default: 0; - * Configure whether to reset, when enabeld, if cpu have reset, the encoder will + * Configure whether to reset, when enabled, if cpu have reset, the encoder will * output a packet to report the address of the last instruction, and upon reset * deassertion, the encoder start again.\\0: Disable\\0: Enable\\ */ @@ -202,7 +202,7 @@ typedef union { */ uint32_t full_address:1; /** implicit_except : R/W; bitpos: [5]; default: 0; - * Configure whether or not enabel implicit exception mode. When enabled,, do not sent + * Configure whether or not enable implicit exception mode. When enabled,, do not sent * exception address, only exception cause in exception packets.\\1: enabled\\0: * disabled\\ */ @@ -381,7 +381,7 @@ typedef union { typedef union { struct { /** hburst : R/W; bitpos: [2:0]; default: 0; - * Configures the AHB burst mode. \\0: SIGNLE \\1: INCR(length not defined) \\2:INCR4 + * Configures the AHB burst mode. \\0: SINGLE \\1: INCR(length not defined) \\2:INCR4 * \\4:INCR8 \\Others:Invalid */ uint32_t hburst:3; @@ -404,7 +404,7 @@ typedef union { /** clk_en : R/W; bitpos: [0]; default: 1; * Configures register clock gating. \\0: Support clock only when the application * writes registers to save power. \\1:Always force the clock on for registers \\ This - * bit does't affect register access. + * bit doesn't affect register access. */ uint32_t clk_en:1; uint32_t reserved_1:31; diff --git a/components/soc/esp32c61/include/soc/uart_reg.h b/components/soc/esp32c61/register/soc/uart_reg.h similarity index 100% rename from components/soc/esp32c61/include/soc/uart_reg.h rename to components/soc/esp32c61/register/soc/uart_reg.h diff --git a/components/soc/esp32c61/include/soc/uart_struct.h b/components/soc/esp32c61/register/soc/uart_struct.h similarity index 100% rename from components/soc/esp32c61/include/soc/uart_struct.h rename to components/soc/esp32c61/register/soc/uart_struct.h diff --git a/components/soc/esp32c61/include/soc/usb_serial_jtag_reg.h b/components/soc/esp32c61/register/soc/usb_serial_jtag_reg.h similarity index 99% rename from components/soc/esp32c61/include/soc/usb_serial_jtag_reg.h rename to components/soc/esp32c61/register/soc/usb_serial_jtag_reg.h index e9e9b833733..255d08ed4bb 100644 --- a/components/soc/esp32c61/include/soc/usb_serial_jtag_reg.h +++ b/components/soc/esp32c61/register/soc/usb_serial_jtag_reg.h @@ -1144,7 +1144,7 @@ extern "C" { #define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_V 0x00000001U #define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_S 3 /** USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY : RO; bitpos: [4]; default: 1; - * CDC_ACM OUTOUT async FIFO empty signal in read clock domain. + * CDC_ACM OUTPUT async FIFO empty signal in read clock domain. */ #define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY (BIT(4)) #define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_M (USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_V << USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_S) diff --git a/components/soc/esp32c61/include/soc/usb_serial_jtag_struct.h b/components/soc/esp32c61/register/soc/usb_serial_jtag_struct.h similarity index 100% rename from components/soc/esp32c61/include/soc/usb_serial_jtag_struct.h rename to components/soc/esp32c61/register/soc/usb_serial_jtag_struct.h diff --git a/components/soc/esp32c61/include/soc/xts_aes_reg.h b/components/soc/esp32c61/register/soc/xts_aes_reg.h similarity index 98% rename from components/soc/esp32c61/include/soc/xts_aes_reg.h rename to components/soc/esp32c61/register/soc/xts_aes_reg.h index 55e0e19beb1..c3e08778d13 100644 --- a/components/soc/esp32c61/include/soc/xts_aes_reg.h +++ b/components/soc/esp32c61/register/soc/xts_aes_reg.h @@ -32,7 +32,7 @@ s. Please do not use this field..*/ #define XTS_AES_DESTINATION_REG(i) (REG_SPI_MEM_BASE(i) + 0x344) /* XTS_AES_DESTINATION : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: This bit stores the destination parameter which will be used in manual encryptio +/*description: This bit stores the destination parameter which will be used in manual encryption n calculation. 0: flash(default), 1: psram(reserved). Only default value can be used..*/ #define XTS_AES_DESTINATION (BIT(0)) @@ -54,7 +54,7 @@ size parameter..*/ /* XTS_AES_TRIGGER : WT ;bitpos:[0] ;default: 1'b0 ; */ /*description: Set this bit to trigger the process of manual encryption calculation. This actio n should only be asserted when manual encryption status is 0. After this action, - manual encryption status becomes 1. After calculation is done, manual encryptio + manual encryption status becomes 1. After calculation is done, manual encryption n status becomes 2..*/ #define XTS_AES_TRIGGER (BIT(0)) #define XTS_AES_TRIGGER_M (BIT(0)) @@ -115,7 +115,7 @@ ing key 1..*/ #define XTS_AES_CRYPT_CALC_D_DPA_EN_V 0x1 #define XTS_AES_CRYPT_CALC_D_DPA_EN_S 3 /* XTS_AES_CRYPT_SECURITY_LEVEL : R/W ;bitpos:[2:0] ;default: 3'd7 ; */ -/*description: Set the security level of spi mem cryption. 0: Shut off cryption DPA funtion. 1- +/*description: Set the security level of spi mem cryption. 0: Shut off cryption DPA function. 1- 7: The bigger the number is, the more secure the cryption is. (Note that the per formance of cryption will decrease together with this number increasing).*/ #define XTS_AES_CRYPT_SECURITY_LEVEL 0x00000007 From 55493e933eeb4d1627158a094b48c54c56b05e52 Mon Sep 17 00:00:00 2001 From: laokaiyao Date: Fri, 6 Sep 2024 17:55:53 +0800 Subject: [PATCH 117/472] refactor(soc): sort esp32p4 soc headers --- .../soc/esp32p4/include/soc/dport_access.h | 1 - .../soc/esp32p4/include/soc/reset_reasons.h | 2 +- components/soc/esp32p4/include/soc/soc.h | 2 +- .../soc/esp32p4/include/soc/usb_dwc_struct.h | 2 +- components/soc/esp32p4/register/soc/.gitkeep | 0 .../{include => register}/soc/adc_reg.h | 0 .../{include => register}/soc/adc_struct.h | 0 .../{include => register}/soc/aes_reg.h | 0 .../{include => register}/soc/aes_struct.h | 0 .../{include => register}/soc/ahb_dma_reg.h | 0 .../soc/ahb_dma_struct.h | 0 .../soc/assist_debug_reg.h | 16 +++++------ .../soc/assist_debug_struct.h | 22 +++++++-------- .../{include => register}/soc/axi_dma_reg.h | 20 ++++++------- .../soc/axi_dma_struct.h | 0 .../soc/bitscrambler_reg.h | 4 +-- .../soc/bitscrambler_struct.h | 4 +-- .../{include => register}/soc/cache_reg.h | 8 +++--- .../{include => register}/soc/cache_struct.h | 0 .../{include => register}/soc/dma2d_reg.h | 0 .../{include => register}/soc/dma2d_struct.h | 0 .../{include => register}/soc/dma_pms_reg.h | 0 .../soc/dma_pms_struct.h | 0 .../{include => register}/soc/ds_reg.h | 0 .../{include => register}/soc/ds_struct.h | 0 .../{include => register}/soc/dw_gdma_reg.h | 0 .../soc/dw_gdma_struct.h | 0 .../{include => register}/soc/ecc_mult_reg.h | 4 +-- .../soc/ecc_mult_struct.h | 4 +-- .../{include => register}/soc/ecdsa_reg.h | 6 ++-- .../{include => register}/soc/ecdsa_struct.h | 6 ++-- .../{include => register}/soc/efuse_reg.h | 2 +- .../{include => register}/soc/efuse_struct.h | 0 .../soc/emac_dma_struct.h | 0 .../soc/emac_mac_struct.h | 0 .../{include => register}/soc/gpio_ext_reg.h | 0 .../soc/gpio_ext_struct.h | 0 .../{include => register}/soc/gpio_reg.h | 4 +-- .../{include => register}/soc/gpio_struct.h | 4 +-- .../{include => register}/soc/h264_dma_reg.h | 0 .../soc/h264_dma_struct.h | 0 .../{include => register}/soc/h264_reg.h | 0 .../{include => register}/soc/h264_struct.h | 0 .../{include => register}/soc/hmac_reg.h | 0 .../{include => register}/soc/hmac_struct.h | 0 .../soc/hp2lp_peri_pms_reg.h | 0 .../soc/hp2lp_peri_pms_struct.h | 0 .../soc/hp_peri_pms_reg.h | 0 .../soc/hp_peri_pms_struct.h | 0 .../soc/hp_sys_clkrst_reg.h | 0 .../soc/hp_sys_clkrst_struct.h | 0 .../{include => register}/soc/hp_system_reg.h | 26 ++++++++--------- .../soc/hp_system_struct.h | 28 +++++++++---------- .../{include => register}/soc/huk_reg.h | 0 .../{include => register}/soc/huk_struct.h | 0 .../soc/i2c_ana_mst_reg.h | 0 .../soc/i2c_ana_mst_struct.h | 0 .../{include => register}/soc/i2c_reg.h | 0 .../{include => register}/soc/i2c_struct.h | 0 .../{include => register}/soc/i2s_reg.h | 2 +- .../{include => register}/soc/i2s_struct.h | 2 +- .../soc/i3c_mst_mem_reg.h | 0 .../soc/i3c_mst_mem_struct.h | 0 .../{include => register}/soc/i3c_mst_reg.h | 0 .../soc/i3c_mst_struct.h | 0 .../{include => register}/soc/i3c_slv_reg.h | 2 +- .../soc/i3c_slv_struct.h | 6 ++-- .../soc/icm_sys_qos_reg.h | 0 .../soc/icm_sys_qos_struct.h | 0 .../{include => register}/soc/icm_sys_reg.h | 0 .../soc/icm_sys_struct.h | 0 .../soc/interrupt_core0_reg.h | 0 .../soc/interrupt_core0_struct.h | 0 .../soc/interrupt_core1_reg.h | 0 .../soc/interrupt_core1_struct.h | 0 .../{include => register}/soc/io_mux_reg.h | 2 +- .../{include => register}/soc/io_mux_struct.h | 0 .../soc/iomux_mspi_pin_reg.h | 0 .../soc/iomux_mspi_pin_struct.h | 0 .../{include => register}/soc/isp_reg.h | 28 +++++++++---------- .../{include => register}/soc/isp_struct.h | 0 .../{include => register}/soc/jpeg_reg.h | 0 .../{include => register}/soc/jpeg_struct.h | 0 .../{include => register}/soc/keymng_reg.h | 0 .../{include => register}/soc/keymng_struct.h | 0 .../soc/l2mem_monitor_reg.h | 0 .../soc/l2mem_monitor_struct.h | 10 +++---- .../{include => register}/soc/lcd_cam_reg.h | 0 .../soc/lcd_cam_struct.h | 0 .../{include => register}/soc/ledc_reg.h | 0 .../{include => register}/soc/ledc_struct.h | 0 .../soc/lp2hp_peri_pms_reg.h | 0 .../soc/lp2hp_peri_pms_struct.h | 0 .../{include => register}/soc/lp_adc_reg.h | 0 .../{include => register}/soc/lp_adc_struct.h | 0 .../soc/lp_analog_peri_reg.h | 0 .../soc/lp_analog_peri_struct.h | 0 .../{include => register}/soc/lp_clkrst_reg.h | 2 +- .../soc/lp_clkrst_struct.h | 2 +- .../{include => register}/soc/lp_gpio_reg.h | 0 .../soc/lp_gpio_struct.h | 0 .../{include => register}/soc/lp_i2c_reg.h | 0 .../{include => register}/soc/lp_i2c_struct.h | 0 .../{include => register}/soc/lp_i2s_reg.h | 0 .../{include => register}/soc/lp_i2s_struct.h | 0 .../{include => register}/soc/lp_intr_reg.h | 0 .../soc/lp_intr_struct.h | 0 .../{include => register}/soc/lp_iomux_reg.h | 0 .../soc/lp_iomux_struct.h | 0 .../soc/lp_mailbox_reg.h | 0 .../soc/lp_mailbox_struct.h | 0 .../soc/lp_peri_pms_reg.h | 0 .../soc/lp_peri_pms_struct.h | 0 .../{include => register}/soc/lp_spi_reg.h | 4 +-- .../{include => register}/soc/lp_spi_struct.h | 0 .../{include => register}/soc/lp_system_reg.h | 0 .../soc/lp_system_struct.h | 0 .../{include => register}/soc/lp_timer_reg.h | 0 .../soc/lp_timer_struct.h | 0 .../{include => register}/soc/lp_uart_reg.h | 8 +++--- .../soc/lp_uart_struct.h | 8 +++--- .../{include => register}/soc/lp_wdt_reg.h | 0 .../{include => register}/soc/lp_wdt_struct.h | 0 .../{include => register}/soc/lpperi_reg.h | 0 .../{include => register}/soc/lpperi_struct.h | 0 .../{include => register}/soc/mcpwm_reg.h | 6 ++-- .../{include => register}/soc/mcpwm_struct.h | 2 +- .../soc/mipi_csi_bridge_reg.h | 0 .../soc/mipi_csi_bridge_struct.h | 0 .../soc/mipi_csi_host_reg.h | 0 .../soc/mipi_csi_host_struct.h | 0 .../soc/mipi_dsi_bridge_reg.h | 0 .../soc/mipi_dsi_bridge_struct.h | 0 .../soc/mipi_dsi_host_reg.h | 0 .../soc/mipi_dsi_host_struct.h | 0 .../{include => register}/soc/parl_io_reg.h | 8 +++--- .../soc/parl_io_struct.h | 8 +++--- .../{include => register}/soc/pau_reg.h | 0 .../{include => register}/soc/pau_struct.h | 0 .../{include => register}/soc/pcnt_reg.h | 0 .../{include => register}/soc/pcnt_struct.h | 0 .../{include => register}/soc/pmu_reg.h | 0 .../{include => register}/soc/pmu_struct.h | 0 .../{include => register}/soc/ppa_reg.h | 6 ++-- .../{include => register}/soc/ppa_struct.h | 6 ++-- .../{include => register}/soc/pvt_reg.h | 0 .../{include => register}/soc/pvt_struct.h | 0 .../{include => register}/soc/reg_base.h | 0 .../{include => register}/soc/rmt_reg.h | 0 .../{include => register}/soc/rmt_struct.h | 0 .../{include => register}/soc/rsa_reg.h | 0 .../{include => register}/soc/rsa_struct.h | 0 .../soc/rtclockcali_reg.h | 16 +++++------ .../soc/rtclockcali_struct.h | 16 +++++------ .../{include => register}/soc/sdmmc_reg.h | 12 ++++---- .../{include => register}/soc/sdmmc_struct.h | 12 ++++---- .../{include => register}/soc/sha_reg.h | 2 +- .../{include => register}/soc/sha_struct.h | 0 .../{include => register}/soc/soc_etm_reg.h | 0 .../soc/soc_etm_struct.h | 0 .../soc/spi1_mem_c_reg.h | 4 +-- .../soc/spi1_mem_c_struct.h | 4 +-- .../soc/spi1_mem_s_reg.h | 4 +-- .../soc/spi1_mem_s_struct.h | 4 +-- .../{include => register}/soc/spi_mem_c_reg.h | 4 +-- .../soc/spi_mem_c_struct.h | 4 +-- .../{include => register}/soc/spi_mem_s_reg.h | 6 ++-- .../soc/spi_mem_s_struct.h | 6 ++-- .../{include => register}/soc/spi_reg.h | 4 +-- .../{include => register}/soc/spi_struct.h | 4 +-- .../{include => register}/soc/systimer_reg.h | 0 .../soc/systimer_struct.h | 0 .../soc/tcm_monitor_reg.h | 10 +++---- .../soc/tcm_monitor_struct.h | 10 +++---- .../soc/timer_group_reg.h | 0 .../soc/timer_group_struct.h | 0 .../{include => register}/soc/touch_reg.h | 0 .../{include => register}/soc/touch_struct.h | 0 .../{include => register}/soc/trace_reg.h | 0 .../{include => register}/soc/trace_struct.h | 0 .../{include => register}/soc/tsens_reg.h | 0 .../{include => register}/soc/tsens_struct.h | 0 .../{include => register}/soc/twai_reg.h | 0 .../{include => register}/soc/twai_struct.h | 0 .../{include => register}/soc/uart_reg.h | 10 +++---- .../{include => register}/soc/uart_struct.h | 10 +++---- .../{include => register}/soc/uhci_reg.h | 0 .../{include => register}/soc/uhci_struct.h | 0 .../soc/usb_serial_jtag_reg.h | 2 +- .../soc/usb_serial_jtag_struct.h | 0 .../{include => register}/soc/usb_wrap_reg.h | 0 .../soc/usb_wrap_struct.h | 0 192 files changed, 210 insertions(+), 211 deletions(-) delete mode 100644 components/soc/esp32p4/register/soc/.gitkeep rename components/soc/esp32p4/{include => register}/soc/adc_reg.h (100%) rename components/soc/esp32p4/{include => register}/soc/adc_struct.h (100%) rename components/soc/esp32p4/{include => register}/soc/aes_reg.h (100%) rename components/soc/esp32p4/{include => register}/soc/aes_struct.h (100%) rename components/soc/esp32p4/{include => register}/soc/ahb_dma_reg.h (100%) rename components/soc/esp32p4/{include => register}/soc/ahb_dma_struct.h (100%) rename components/soc/esp32p4/{include => register}/soc/assist_debug_reg.h (99%) rename components/soc/esp32p4/{include => register}/soc/assist_debug_struct.h (98%) rename components/soc/esp32p4/{include => register}/soc/axi_dma_reg.h (99%) rename components/soc/esp32p4/{include => register}/soc/axi_dma_struct.h (100%) rename components/soc/esp32p4/{include => register}/soc/bitscrambler_reg.h (99%) rename components/soc/esp32p4/{include => register}/soc/bitscrambler_struct.h (99%) rename components/soc/esp32p4/{include => register}/soc/cache_reg.h (99%) rename components/soc/esp32p4/{include => register}/soc/cache_struct.h (100%) rename components/soc/esp32p4/{include => register}/soc/dma2d_reg.h (100%) rename components/soc/esp32p4/{include => register}/soc/dma2d_struct.h (100%) rename components/soc/esp32p4/{include => register}/soc/dma_pms_reg.h (100%) rename components/soc/esp32p4/{include => register}/soc/dma_pms_struct.h (100%) rename components/soc/esp32p4/{include => register}/soc/ds_reg.h (100%) rename components/soc/esp32p4/{include => register}/soc/ds_struct.h (100%) rename components/soc/esp32p4/{include => register}/soc/dw_gdma_reg.h (100%) rename components/soc/esp32p4/{include => register}/soc/dw_gdma_struct.h (100%) rename components/soc/esp32p4/{include => register}/soc/ecc_mult_reg.h (97%) rename components/soc/esp32p4/{include => register}/soc/ecc_mult_struct.h (96%) rename components/soc/esp32p4/{include => register}/soc/ecdsa_reg.h (98%) rename components/soc/esp32p4/{include => register}/soc/ecdsa_struct.h (97%) rename components/soc/esp32p4/{include => register}/soc/efuse_reg.h (99%) rename components/soc/esp32p4/{include => register}/soc/efuse_struct.h (100%) rename components/soc/esp32p4/{include => register}/soc/emac_dma_struct.h (100%) rename components/soc/esp32p4/{include => register}/soc/emac_mac_struct.h (100%) rename components/soc/esp32p4/{include => register}/soc/gpio_ext_reg.h (100%) rename components/soc/esp32p4/{include => register}/soc/gpio_ext_struct.h (100%) rename components/soc/esp32p4/{include => register}/soc/gpio_reg.h (99%) rename components/soc/esp32p4/{include => register}/soc/gpio_struct.h (99%) rename components/soc/esp32p4/{include => register}/soc/h264_dma_reg.h (100%) rename components/soc/esp32p4/{include => register}/soc/h264_dma_struct.h (100%) rename components/soc/esp32p4/{include => register}/soc/h264_reg.h (100%) rename components/soc/esp32p4/{include => register}/soc/h264_struct.h (100%) rename components/soc/esp32p4/{include => register}/soc/hmac_reg.h (100%) rename components/soc/esp32p4/{include => register}/soc/hmac_struct.h (100%) rename components/soc/esp32p4/{include => register}/soc/hp2lp_peri_pms_reg.h (100%) rename components/soc/esp32p4/{include => register}/soc/hp2lp_peri_pms_struct.h (100%) rename components/soc/esp32p4/{include => register}/soc/hp_peri_pms_reg.h (100%) rename components/soc/esp32p4/{include => register}/soc/hp_peri_pms_struct.h (100%) rename components/soc/esp32p4/{include => register}/soc/hp_sys_clkrst_reg.h (100%) rename components/soc/esp32p4/{include => register}/soc/hp_sys_clkrst_struct.h (100%) rename components/soc/esp32p4/{include => register}/soc/hp_system_reg.h (99%) rename components/soc/esp32p4/{include => register}/soc/hp_system_struct.h (98%) rename components/soc/esp32p4/{include => register}/soc/huk_reg.h (100%) rename components/soc/esp32p4/{include => register}/soc/huk_struct.h (100%) rename components/soc/esp32p4/{include => register}/soc/i2c_ana_mst_reg.h (100%) rename components/soc/esp32p4/{include => register}/soc/i2c_ana_mst_struct.h (100%) rename components/soc/esp32p4/{include => register}/soc/i2c_reg.h (100%) rename components/soc/esp32p4/{include => register}/soc/i2c_struct.h (100%) rename components/soc/esp32p4/{include => register}/soc/i2s_reg.h (99%) rename components/soc/esp32p4/{include => register}/soc/i2s_struct.h (99%) rename components/soc/esp32p4/{include => register}/soc/i3c_mst_mem_reg.h (100%) rename components/soc/esp32p4/{include => register}/soc/i3c_mst_mem_struct.h (100%) rename components/soc/esp32p4/{include => register}/soc/i3c_mst_reg.h (100%) rename components/soc/esp32p4/{include => register}/soc/i3c_mst_struct.h (100%) rename components/soc/esp32p4/{include => register}/soc/i3c_slv_reg.h (99%) rename components/soc/esp32p4/{include => register}/soc/i3c_slv_struct.h (99%) rename components/soc/esp32p4/{include => register}/soc/icm_sys_qos_reg.h (100%) rename components/soc/esp32p4/{include => register}/soc/icm_sys_qos_struct.h (100%) rename components/soc/esp32p4/{include => register}/soc/icm_sys_reg.h (100%) rename components/soc/esp32p4/{include => register}/soc/icm_sys_struct.h (100%) rename components/soc/esp32p4/{include => register}/soc/interrupt_core0_reg.h (100%) rename components/soc/esp32p4/{include => register}/soc/interrupt_core0_struct.h (100%) rename components/soc/esp32p4/{include => register}/soc/interrupt_core1_reg.h (100%) rename components/soc/esp32p4/{include => register}/soc/interrupt_core1_struct.h (100%) rename components/soc/esp32p4/{include => register}/soc/io_mux_reg.h (99%) rename components/soc/esp32p4/{include => register}/soc/io_mux_struct.h (100%) rename components/soc/esp32p4/{include => register}/soc/iomux_mspi_pin_reg.h (100%) rename components/soc/esp32p4/{include => register}/soc/iomux_mspi_pin_struct.h (100%) rename components/soc/esp32p4/{include => register}/soc/isp_reg.h (99%) rename components/soc/esp32p4/{include => register}/soc/isp_struct.h (100%) rename components/soc/esp32p4/{include => register}/soc/jpeg_reg.h (100%) rename components/soc/esp32p4/{include => register}/soc/jpeg_struct.h (100%) rename components/soc/esp32p4/{include => register}/soc/keymng_reg.h (100%) rename components/soc/esp32p4/{include => register}/soc/keymng_struct.h (100%) rename components/soc/esp32p4/{include => register}/soc/l2mem_monitor_reg.h (100%) rename components/soc/esp32p4/{include => register}/soc/l2mem_monitor_struct.h (98%) rename components/soc/esp32p4/{include => register}/soc/lcd_cam_reg.h (100%) rename components/soc/esp32p4/{include => register}/soc/lcd_cam_struct.h (100%) rename components/soc/esp32p4/{include => register}/soc/ledc_reg.h (100%) rename components/soc/esp32p4/{include => register}/soc/ledc_struct.h (100%) rename components/soc/esp32p4/{include => register}/soc/lp2hp_peri_pms_reg.h (100%) rename components/soc/esp32p4/{include => register}/soc/lp2hp_peri_pms_struct.h (100%) rename components/soc/esp32p4/{include => register}/soc/lp_adc_reg.h (100%) rename components/soc/esp32p4/{include => register}/soc/lp_adc_struct.h (100%) rename components/soc/esp32p4/{include => register}/soc/lp_analog_peri_reg.h (100%) rename components/soc/esp32p4/{include => register}/soc/lp_analog_peri_struct.h (100%) rename components/soc/esp32p4/{include => register}/soc/lp_clkrst_reg.h (99%) rename components/soc/esp32p4/{include => register}/soc/lp_clkrst_struct.h (99%) rename components/soc/esp32p4/{include => register}/soc/lp_gpio_reg.h (100%) rename components/soc/esp32p4/{include => register}/soc/lp_gpio_struct.h (100%) rename components/soc/esp32p4/{include => register}/soc/lp_i2c_reg.h (100%) rename components/soc/esp32p4/{include => register}/soc/lp_i2c_struct.h (100%) rename components/soc/esp32p4/{include => register}/soc/lp_i2s_reg.h (100%) rename components/soc/esp32p4/{include => register}/soc/lp_i2s_struct.h (100%) rename components/soc/esp32p4/{include => register}/soc/lp_intr_reg.h (100%) rename components/soc/esp32p4/{include => register}/soc/lp_intr_struct.h (100%) rename components/soc/esp32p4/{include => register}/soc/lp_iomux_reg.h (100%) rename components/soc/esp32p4/{include => register}/soc/lp_iomux_struct.h (100%) rename components/soc/esp32p4/{include => register}/soc/lp_mailbox_reg.h (100%) rename components/soc/esp32p4/{include => register}/soc/lp_mailbox_struct.h (100%) rename components/soc/esp32p4/{include => register}/soc/lp_peri_pms_reg.h (100%) rename components/soc/esp32p4/{include => register}/soc/lp_peri_pms_struct.h (100%) rename components/soc/esp32p4/{include => register}/soc/lp_spi_reg.h (99%) rename components/soc/esp32p4/{include => register}/soc/lp_spi_struct.h (100%) rename components/soc/esp32p4/{include => register}/soc/lp_system_reg.h (100%) rename components/soc/esp32p4/{include => register}/soc/lp_system_struct.h (100%) rename components/soc/esp32p4/{include => register}/soc/lp_timer_reg.h (100%) rename components/soc/esp32p4/{include => register}/soc/lp_timer_struct.h (100%) rename components/soc/esp32p4/{include => register}/soc/lp_uart_reg.h (99%) rename components/soc/esp32p4/{include => register}/soc/lp_uart_struct.h (99%) rename components/soc/esp32p4/{include => register}/soc/lp_wdt_reg.h (100%) rename components/soc/esp32p4/{include => register}/soc/lp_wdt_struct.h (100%) rename components/soc/esp32p4/{include => register}/soc/lpperi_reg.h (100%) rename components/soc/esp32p4/{include => register}/soc/lpperi_struct.h (100%) rename components/soc/esp32p4/{include => register}/soc/mcpwm_reg.h (99%) rename components/soc/esp32p4/{include => register}/soc/mcpwm_struct.h (99%) rename components/soc/esp32p4/{include => register}/soc/mipi_csi_bridge_reg.h (100%) rename components/soc/esp32p4/{include => register}/soc/mipi_csi_bridge_struct.h (100%) rename components/soc/esp32p4/{include => register}/soc/mipi_csi_host_reg.h (100%) rename components/soc/esp32p4/{include => register}/soc/mipi_csi_host_struct.h (100%) rename components/soc/esp32p4/{include => register}/soc/mipi_dsi_bridge_reg.h (100%) rename components/soc/esp32p4/{include => register}/soc/mipi_dsi_bridge_struct.h (100%) rename components/soc/esp32p4/{include => register}/soc/mipi_dsi_host_reg.h (100%) rename components/soc/esp32p4/{include => register}/soc/mipi_dsi_host_struct.h (100%) rename components/soc/esp32p4/{include => register}/soc/parl_io_reg.h (98%) rename components/soc/esp32p4/{include => register}/soc/parl_io_struct.h (98%) rename components/soc/esp32p4/{include => register}/soc/pau_reg.h (100%) rename components/soc/esp32p4/{include => register}/soc/pau_struct.h (100%) rename components/soc/esp32p4/{include => register}/soc/pcnt_reg.h (100%) rename components/soc/esp32p4/{include => register}/soc/pcnt_struct.h (100%) rename components/soc/esp32p4/{include => register}/soc/pmu_reg.h (100%) rename components/soc/esp32p4/{include => register}/soc/pmu_struct.h (100%) rename components/soc/esp32p4/{include => register}/soc/ppa_reg.h (99%) rename components/soc/esp32p4/{include => register}/soc/ppa_struct.h (99%) rename components/soc/esp32p4/{include => register}/soc/pvt_reg.h (100%) rename components/soc/esp32p4/{include => register}/soc/pvt_struct.h (100%) rename components/soc/esp32p4/{include => register}/soc/reg_base.h (100%) rename components/soc/esp32p4/{include => register}/soc/rmt_reg.h (100%) rename components/soc/esp32p4/{include => register}/soc/rmt_struct.h (100%) rename components/soc/esp32p4/{include => register}/soc/rsa_reg.h (100%) rename components/soc/esp32p4/{include => register}/soc/rsa_struct.h (100%) rename components/soc/esp32p4/{include => register}/soc/rtclockcali_reg.h (98%) rename components/soc/esp32p4/{include => register}/soc/rtclockcali_struct.h (97%) rename components/soc/esp32p4/{include => register}/soc/sdmmc_reg.h (99%) rename components/soc/esp32p4/{include => register}/soc/sdmmc_struct.h (99%) rename components/soc/esp32p4/{include => register}/soc/sha_reg.h (98%) rename components/soc/esp32p4/{include => register}/soc/sha_struct.h (100%) rename components/soc/esp32p4/{include => register}/soc/soc_etm_reg.h (100%) rename components/soc/esp32p4/{include => register}/soc/soc_etm_struct.h (100%) rename components/soc/esp32p4/{include => register}/soc/spi1_mem_c_reg.h (99%) rename components/soc/esp32p4/{include => register}/soc/spi1_mem_c_struct.h (99%) rename components/soc/esp32p4/{include => register}/soc/spi1_mem_s_reg.h (99%) rename components/soc/esp32p4/{include => register}/soc/spi1_mem_s_struct.h (99%) rename components/soc/esp32p4/{include => register}/soc/spi_mem_c_reg.h (99%) rename components/soc/esp32p4/{include => register}/soc/spi_mem_c_struct.h (99%) rename components/soc/esp32p4/{include => register}/soc/spi_mem_s_reg.h (99%) rename components/soc/esp32p4/{include => register}/soc/spi_mem_s_struct.h (99%) rename components/soc/esp32p4/{include => register}/soc/spi_reg.h (99%) rename components/soc/esp32p4/{include => register}/soc/spi_struct.h (99%) rename components/soc/esp32p4/{include => register}/soc/systimer_reg.h (100%) rename components/soc/esp32p4/{include => register}/soc/systimer_struct.h (100%) rename components/soc/esp32p4/{include => register}/soc/tcm_monitor_reg.h (98%) rename components/soc/esp32p4/{include => register}/soc/tcm_monitor_struct.h (98%) rename components/soc/esp32p4/{include => register}/soc/timer_group_reg.h (100%) rename components/soc/esp32p4/{include => register}/soc/timer_group_struct.h (100%) rename components/soc/esp32p4/{include => register}/soc/touch_reg.h (100%) rename components/soc/esp32p4/{include => register}/soc/touch_struct.h (100%) rename components/soc/esp32p4/{include => register}/soc/trace_reg.h (100%) rename components/soc/esp32p4/{include => register}/soc/trace_struct.h (100%) rename components/soc/esp32p4/{include => register}/soc/tsens_reg.h (100%) rename components/soc/esp32p4/{include => register}/soc/tsens_struct.h (100%) rename components/soc/esp32p4/{include => register}/soc/twai_reg.h (100%) rename components/soc/esp32p4/{include => register}/soc/twai_struct.h (100%) rename components/soc/esp32p4/{include => register}/soc/uart_reg.h (99%) rename components/soc/esp32p4/{include => register}/soc/uart_struct.h (99%) rename components/soc/esp32p4/{include => register}/soc/uhci_reg.h (100%) rename components/soc/esp32p4/{include => register}/soc/uhci_struct.h (100%) rename components/soc/esp32p4/{include => register}/soc/usb_serial_jtag_reg.h (99%) rename components/soc/esp32p4/{include => register}/soc/usb_serial_jtag_struct.h (100%) rename components/soc/esp32p4/{include => register}/soc/usb_wrap_reg.h (100%) rename components/soc/esp32p4/{include => register}/soc/usb_wrap_struct.h (100%) diff --git a/components/soc/esp32p4/include/soc/dport_access.h b/components/soc/esp32p4/include/soc/dport_access.h index 3747073d224..189fc786b83 100644 --- a/components/soc/esp32p4/include/soc/dport_access.h +++ b/components/soc/esp32p4/include/soc/dport_access.h @@ -9,7 +9,6 @@ #include #include "soc.h" -#include "uart_reg.h" #ifdef __cplusplus extern "C" { diff --git a/components/soc/esp32p4/include/soc/reset_reasons.h b/components/soc/esp32p4/include/soc/reset_reasons.h index 39b792e549e..4e6952d555b 100644 --- a/components/soc/esp32p4/include/soc/reset_reasons.h +++ b/components/soc/esp32p4/include/soc/reset_reasons.h @@ -45,7 +45,7 @@ typedef enum { RESET_REASON_CORE_USB_JTAG = 0x16, // USB Serial/JTAG controller's JTAG resets the digital core RESET_REASON_CORE_USB_UART = 0x17, // USB Serial/JTAG controller's UART resets the digital core RESET_REASON_CPU_JTAG = 0x18, // Triggered when a reset command from JTAG is received - RESET_REASON_CPU_LOCKUP = 0x1A, // Triggered when the CPU enters lockup (exception inside the execption handler would cause this) + RESET_REASON_CPU_LOCKUP = 0x1A, // Triggered when the CPU enters lockup (exception inside the exception handler would cause this) } soc_reset_reason_t; diff --git a/components/soc/esp32p4/include/soc/soc.h b/components/soc/esp32p4/include/soc/soc.h index baf879c9e5e..e8e79a9d07d 100644 --- a/components/soc/esp32p4/include/soc/soc.h +++ b/components/soc/esp32p4/include/soc/soc.h @@ -12,7 +12,7 @@ #endif #include "esp_bit_defs.h" -#include "reg_base.h" +#include "soc/reg_base.h" #define PRO_CPU_NUM (0) diff --git a/components/soc/esp32p4/include/soc/usb_dwc_struct.h b/components/soc/esp32p4/include/soc/usb_dwc_struct.h index 728be16b0f6..206d566277e 100644 --- a/components/soc/esp32p4/include/soc/usb_dwc_struct.h +++ b/components/soc/esp32p4/include/soc/usb_dwc_struct.h @@ -33,7 +33,7 @@ typedef union { uint32_t hnpreq: 1; uint32_t hstsethnpen: 1; uint32_t devhnpen: 1; - uint32_t ehen: 1; + uint32_t ehen: 1; // codespell:ignore ehen uint32_t reserved_13: 2; uint32_t dbncefltrbypass: 1; uint32_t conidsts: 1; diff --git a/components/soc/esp32p4/register/soc/.gitkeep b/components/soc/esp32p4/register/soc/.gitkeep deleted file mode 100644 index e69de29bb2d..00000000000 diff --git a/components/soc/esp32p4/include/soc/adc_reg.h b/components/soc/esp32p4/register/soc/adc_reg.h similarity index 100% rename from components/soc/esp32p4/include/soc/adc_reg.h rename to components/soc/esp32p4/register/soc/adc_reg.h diff --git a/components/soc/esp32p4/include/soc/adc_struct.h b/components/soc/esp32p4/register/soc/adc_struct.h similarity index 100% rename from components/soc/esp32p4/include/soc/adc_struct.h rename to components/soc/esp32p4/register/soc/adc_struct.h diff --git a/components/soc/esp32p4/include/soc/aes_reg.h b/components/soc/esp32p4/register/soc/aes_reg.h similarity index 100% rename from components/soc/esp32p4/include/soc/aes_reg.h rename to components/soc/esp32p4/register/soc/aes_reg.h diff --git a/components/soc/esp32p4/include/soc/aes_struct.h b/components/soc/esp32p4/register/soc/aes_struct.h similarity index 100% rename from components/soc/esp32p4/include/soc/aes_struct.h rename to components/soc/esp32p4/register/soc/aes_struct.h diff --git a/components/soc/esp32p4/include/soc/ahb_dma_reg.h b/components/soc/esp32p4/register/soc/ahb_dma_reg.h similarity index 100% rename from components/soc/esp32p4/include/soc/ahb_dma_reg.h rename to components/soc/esp32p4/register/soc/ahb_dma_reg.h diff --git a/components/soc/esp32p4/include/soc/ahb_dma_struct.h b/components/soc/esp32p4/register/soc/ahb_dma_struct.h similarity index 100% rename from components/soc/esp32p4/include/soc/ahb_dma_struct.h rename to components/soc/esp32p4/register/soc/ahb_dma_struct.h diff --git a/components/soc/esp32p4/include/soc/assist_debug_reg.h b/components/soc/esp32p4/register/soc/assist_debug_reg.h similarity index 99% rename from components/soc/esp32p4/include/soc/assist_debug_reg.h rename to components/soc/esp32p4/register/soc/assist_debug_reg.h index 89c49a9cc6f..f8f13c35319 100644 --- a/components/soc/esp32p4/include/soc/assist_debug_reg.h +++ b/components/soc/esp32p4/register/soc/assist_debug_reg.h @@ -435,7 +435,7 @@ extern "C" { */ #define ASSIST_DEBUG_CORE_0_SP_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x38) /** ASSIST_DEBUG_CORE_0_SP_MIN : R/W; bitpos: [31:0]; default: 0; - * core0 sp region configuration regsiter + * core0 sp region configuration register */ #define ASSIST_DEBUG_CORE_0_SP_MIN 0xFFFFFFFFU #define ASSIST_DEBUG_CORE_0_SP_MIN_M (ASSIST_DEBUG_CORE_0_SP_MIN_V << ASSIST_DEBUG_CORE_0_SP_MIN_S) @@ -459,7 +459,7 @@ extern "C" { */ #define ASSIST_DEBUG_CORE_0_SP_PC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x40) /** ASSIST_DEBUG_CORE_0_SP_PC : RO; bitpos: [31:0]; default: 0; - * This regsiter stores the PC when trigger stack monitor. + * This register stores the PC when trigger stack monitor. */ #define ASSIST_DEBUG_CORE_0_SP_PC 0xFFFFFFFFU #define ASSIST_DEBUG_CORE_0_SP_PC_M (ASSIST_DEBUG_CORE_0_SP_PC_V << ASSIST_DEBUG_CORE_0_SP_PC_S) @@ -486,7 +486,7 @@ extern "C" { #define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_S 1 /** ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG register - * record status regsiter + * record status register */ #define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x48) /** ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC : RO; bitpos: [31:0]; default: 0; @@ -498,7 +498,7 @@ extern "C" { #define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_S 0 /** ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG register - * record status regsiter + * record status register */ #define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG (DR_REG_ASSIST_DEBUG_BASE + 0x4c) /** ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP : RO; bitpos: [31:0]; default: 0; @@ -1103,7 +1103,7 @@ extern "C" { */ #define ASSIST_DEBUG_CORE_1_SP_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0xb8) /** ASSIST_DEBUG_CORE_1_SP_MIN : R/W; bitpos: [31:0]; default: 0; - * core1 sp region configuration regsiter + * core1 sp region configuration register */ #define ASSIST_DEBUG_CORE_1_SP_MIN 0xFFFFFFFFU #define ASSIST_DEBUG_CORE_1_SP_MIN_M (ASSIST_DEBUG_CORE_1_SP_MIN_V << ASSIST_DEBUG_CORE_1_SP_MIN_S) @@ -1127,7 +1127,7 @@ extern "C" { */ #define ASSIST_DEBUG_CORE_1_SP_PC_REG (DR_REG_ASSIST_DEBUG_BASE + 0xc0) /** ASSIST_DEBUG_CORE_1_SP_PC : RO; bitpos: [31:0]; default: 0; - * This regsiter stores the PC when trigger stack monitor. + * This register stores the PC when trigger stack monitor. */ #define ASSIST_DEBUG_CORE_1_SP_PC 0xFFFFFFFFU #define ASSIST_DEBUG_CORE_1_SP_PC_M (ASSIST_DEBUG_CORE_1_SP_PC_V << ASSIST_DEBUG_CORE_1_SP_PC_S) @@ -1154,7 +1154,7 @@ extern "C" { #define ASSIST_DEBUG_CORE_1_RCD_PDEBUGEN_S 1 /** ASSIST_DEBUG_CORE_1_RCD_PDEBUGPC_REG register - * record status regsiter + * record status register */ #define ASSIST_DEBUG_CORE_1_RCD_PDEBUGPC_REG (DR_REG_ASSIST_DEBUG_BASE + 0xc8) /** ASSIST_DEBUG_CORE_1_RCD_PDEBUGPC : RO; bitpos: [31:0]; default: 0; @@ -1166,7 +1166,7 @@ extern "C" { #define ASSIST_DEBUG_CORE_1_RCD_PDEBUGPC_S 0 /** ASSIST_DEBUG_CORE_1_RCD_PDEBUGSP_REG register - * record status regsiter + * record status register */ #define ASSIST_DEBUG_CORE_1_RCD_PDEBUGSP_REG (DR_REG_ASSIST_DEBUG_BASE + 0xcc) /** ASSIST_DEBUG_CORE_1_RCD_PDEBUGSP : RO; bitpos: [31:0]; default: 0; diff --git a/components/soc/esp32p4/include/soc/assist_debug_struct.h b/components/soc/esp32p4/register/soc/assist_debug_struct.h similarity index 98% rename from components/soc/esp32p4/include/soc/assist_debug_struct.h rename to components/soc/esp32p4/register/soc/assist_debug_struct.h index 88dd72df88e..645e5a1cf08 100644 --- a/components/soc/esp32p4/include/soc/assist_debug_struct.h +++ b/components/soc/esp32p4/register/soc/assist_debug_struct.h @@ -197,7 +197,7 @@ typedef union { typedef union { struct { /** core_0_sp_min : R/W; bitpos: [31:0]; default: 0; - * core0 sp region configuration regsiter + * core0 sp region configuration register */ uint32_t core_0_sp_min:32; }; @@ -223,7 +223,7 @@ typedef union { typedef union { struct { /** core_0_sp_pc : RO; bitpos: [31:0]; default: 0; - * This regsiter stores the PC when trigger stack monitor. + * This register stores the PC when trigger stack monitor. */ uint32_t core_0_sp_pc:32; }; @@ -416,7 +416,7 @@ typedef union { typedef union { struct { /** core_1_sp_min : R/W; bitpos: [31:0]; default: 0; - * core1 sp region configuration regsiter + * core1 sp region configuration register */ uint32_t core_1_sp_min:32; }; @@ -442,7 +442,7 @@ typedef union { typedef union { struct { /** core_1_sp_pc : RO; bitpos: [31:0]; default: 0; - * This regsiter stores the PC when trigger stack monitor. + * This register stores the PC when trigger stack monitor. */ uint32_t core_1_sp_pc:32; }; @@ -752,7 +752,7 @@ typedef union { } assist_debug_core_1_intr_clr_reg_t; -/** Group: pc reording configuration register */ +/** Group: pc recording configuration register */ /** Type of core_0_rcd_en register * record enable configuration register */ @@ -790,9 +790,9 @@ typedef union { } assist_debug_core_1_rcd_en_reg_t; -/** Group: pc reording status register */ +/** Group: pc recording status register */ /** Type of core_0_rcd_pdebugpc register - * record status regsiter + * record status register */ typedef union { struct { @@ -805,7 +805,7 @@ typedef union { } assist_debug_core_0_rcd_pdebugpc_reg_t; /** Type of core_0_rcd_pdebugsp register - * record status regsiter + * record status register */ typedef union { struct { @@ -818,7 +818,7 @@ typedef union { } assist_debug_core_0_rcd_pdebugsp_reg_t; /** Type of core_1_rcd_pdebugpc register - * record status regsiter + * record status register */ typedef union { struct { @@ -831,7 +831,7 @@ typedef union { } assist_debug_core_1_rcd_pdebugpc_reg_t; /** Type of core_1_rcd_pdebugsp register - * record status regsiter + * record status register */ typedef union { struct { @@ -844,7 +844,7 @@ typedef union { } assist_debug_core_1_rcd_pdebugsp_reg_t; -/** Group: exception monitor regsiter */ +/** Group: exception monitor register */ /** Type of core_0_iram0_exception_monitor_0 register * exception monitor status register0 */ diff --git a/components/soc/esp32p4/include/soc/axi_dma_reg.h b/components/soc/esp32p4/register/soc/axi_dma_reg.h similarity index 99% rename from components/soc/esp32p4/include/soc/axi_dma_reg.h rename to components/soc/esp32p4/register/soc/axi_dma_reg.h index e3dfc907dbd..8f2775e7959 100644 --- a/components/soc/esp32p4/include/soc/axi_dma_reg.h +++ b/components/soc/esp32p4/register/soc/axi_dma_reg.h @@ -770,7 +770,7 @@ extern "C" { #define AXI_DMA_RX_CH_ARB_WEIGH_CH0_V 0x0000000FU #define AXI_DMA_RX_CH_ARB_WEIGH_CH0_S 4 /** AXI_DMA_RX_ARB_WEIGH_OPT_DIR_CH0 : R/W; bitpos: [8]; default: 0; - * 0: mean not optimazation weight function ,1: mean optimazation + * 0: mean not optimization weight function ,1: mean optimization */ #define AXI_DMA_RX_ARB_WEIGH_OPT_DIR_CH0 (BIT(8)) #define AXI_DMA_RX_ARB_WEIGH_OPT_DIR_CH0_M (AXI_DMA_RX_ARB_WEIGH_OPT_DIR_CH0_V << AXI_DMA_RX_ARB_WEIGH_OPT_DIR_CH0_S) @@ -1654,7 +1654,7 @@ extern "C" { #define AXI_DMA_RX_CH_ARB_WEIGH_CH1_V 0x0000000FU #define AXI_DMA_RX_CH_ARB_WEIGH_CH1_S 4 /** AXI_DMA_RX_ARB_WEIGH_OPT_DIR_CH1 : R/W; bitpos: [8]; default: 0; - * 0: mean not optimazation weight function ,1: mean optimazation + * 0: mean not optimization weight function ,1: mean optimization */ #define AXI_DMA_RX_ARB_WEIGH_OPT_DIR_CH1 (BIT(8)) #define AXI_DMA_RX_ARB_WEIGH_OPT_DIR_CH1_M (AXI_DMA_RX_ARB_WEIGH_OPT_DIR_CH1_V << AXI_DMA_RX_ARB_WEIGH_OPT_DIR_CH1_S) @@ -2538,7 +2538,7 @@ extern "C" { #define AXI_DMA_RX_CH_ARB_WEIGH_CH2_V 0x0000000FU #define AXI_DMA_RX_CH_ARB_WEIGH_CH2_S 4 /** AXI_DMA_RX_ARB_WEIGH_OPT_DIR_CH2 : R/W; bitpos: [8]; default: 0; - * 0: mean not optimazation weight function ,1: mean optimazation + * 0: mean not optimization weight function ,1: mean optimization */ #define AXI_DMA_RX_ARB_WEIGH_OPT_DIR_CH2 (BIT(8)) #define AXI_DMA_RX_ARB_WEIGH_OPT_DIR_CH2_M (AXI_DMA_RX_ARB_WEIGH_OPT_DIR_CH2_V << AXI_DMA_RX_ARB_WEIGH_OPT_DIR_CH2_S) @@ -3384,7 +3384,7 @@ extern "C" { #define AXI_DMA_TX_CH_ARB_WEIGH_CH0_V 0x0000000FU #define AXI_DMA_TX_CH_ARB_WEIGH_CH0_S 4 /** AXI_DMA_TX_ARB_WEIGH_OPT_DIR_CH0 : R/W; bitpos: [8]; default: 0; - * 0: mean not optimazation weight function ,1: mean optimazation + * 0: mean not optimization weight function ,1: mean optimization */ #define AXI_DMA_TX_ARB_WEIGH_OPT_DIR_CH0 (BIT(8)) #define AXI_DMA_TX_ARB_WEIGH_OPT_DIR_CH0_M (AXI_DMA_TX_ARB_WEIGH_OPT_DIR_CH0_V << AXI_DMA_TX_ARB_WEIGH_OPT_DIR_CH0_S) @@ -4230,7 +4230,7 @@ extern "C" { #define AXI_DMA_TX_CH_ARB_WEIGH_CH1_V 0x0000000FU #define AXI_DMA_TX_CH_ARB_WEIGH_CH1_S 4 /** AXI_DMA_TX_ARB_WEIGH_OPT_DIR_CH1 : R/W; bitpos: [8]; default: 0; - * 0: mean not optimazation weight function ,1: mean optimazation + * 0: mean not optimization weight function ,1: mean optimization */ #define AXI_DMA_TX_ARB_WEIGH_OPT_DIR_CH1 (BIT(8)) #define AXI_DMA_TX_ARB_WEIGH_OPT_DIR_CH1_M (AXI_DMA_TX_ARB_WEIGH_OPT_DIR_CH1_V << AXI_DMA_TX_ARB_WEIGH_OPT_DIR_CH1_S) @@ -5076,7 +5076,7 @@ extern "C" { #define AXI_DMA_TX_CH_ARB_WEIGH_CH2_V 0x0000000FU #define AXI_DMA_TX_CH_ARB_WEIGH_CH2_S 4 /** AXI_DMA_TX_ARB_WEIGH_OPT_DIR_CH2 : R/W; bitpos: [8]; default: 0; - * 0: mean not optimazation weight function ,1: mean optimazation + * 0: mean not optimization weight function ,1: mean optimization */ #define AXI_DMA_TX_ARB_WEIGH_OPT_DIR_CH2 (BIT(8)) #define AXI_DMA_TX_ARB_WEIGH_OPT_DIR_CH2_M (AXI_DMA_TX_ARB_WEIGH_OPT_DIR_CH2_V << AXI_DMA_TX_ARB_WEIGH_OPT_DIR_CH2_S) @@ -5490,11 +5490,11 @@ extern "C" { #define AXI_DMA_RDN_ECO_LOW_S 0 /** AXI_DMA_WRESP_CNT_REG register - * AXI wr responce cnt register. + * AXI wr response cnt register. */ #define AXI_DMA_WRESP_CNT_REG (DR_REG_AXI_DMA_BASE + 0x2b8) /** AXI_DMA_WRESP_CNT : RO; bitpos: [3:0]; default: 0; - * axi wr responce cnt reg. + * axi wr response cnt reg. */ #define AXI_DMA_WRESP_CNT 0x0000000FU #define AXI_DMA_WRESP_CNT_M (AXI_DMA_WRESP_CNT_V << AXI_DMA_WRESP_CNT_S) @@ -5502,11 +5502,11 @@ extern "C" { #define AXI_DMA_WRESP_CNT_S 0 /** AXI_DMA_RRESP_CNT_REG register - * AXI wr responce cnt register. + * AXI wr response cnt register. */ #define AXI_DMA_RRESP_CNT_REG (DR_REG_AXI_DMA_BASE + 0x2bc) /** AXI_DMA_RRESP_CNT : RO; bitpos: [3:0]; default: 0; - * axi rd responce cnt reg. + * axi rd response cnt reg. */ #define AXI_DMA_RRESP_CNT 0x0000000FU #define AXI_DMA_RRESP_CNT_M (AXI_DMA_RRESP_CNT_V << AXI_DMA_RRESP_CNT_S) diff --git a/components/soc/esp32p4/include/soc/axi_dma_struct.h b/components/soc/esp32p4/register/soc/axi_dma_struct.h similarity index 100% rename from components/soc/esp32p4/include/soc/axi_dma_struct.h rename to components/soc/esp32p4/register/soc/axi_dma_struct.h diff --git a/components/soc/esp32p4/include/soc/bitscrambler_reg.h b/components/soc/esp32p4/register/soc/bitscrambler_reg.h similarity index 99% rename from components/soc/esp32p4/include/soc/bitscrambler_reg.h rename to components/soc/esp32p4/register/soc/bitscrambler_reg.h index 44bfc3c8745..4b8fbe5df57 100644 --- a/components/soc/esp32p4/include/soc/bitscrambler_reg.h +++ b/components/soc/esp32p4/register/soc/bitscrambler_reg.h @@ -216,7 +216,7 @@ extern "C" { #define BITSCRAMBLER_TX_COND_MODE_S 4 /** BITSCRAMBLER_TX_FETCH_MODE : R/W; bitpos: [5]; default: 0; * write this bit to set the bitscrambler tx core fetch instruction mode, 0: prefetch - * by reset, 1: fetch by instrutions + * by reset, 1: fetch by instructions */ #define BITSCRAMBLER_TX_FETCH_MODE (BIT(5)) #define BITSCRAMBLER_TX_FETCH_MODE_M (BITSCRAMBLER_TX_FETCH_MODE_V << BITSCRAMBLER_TX_FETCH_MODE_S) @@ -291,7 +291,7 @@ extern "C" { #define BITSCRAMBLER_RX_COND_MODE_S 4 /** BITSCRAMBLER_RX_FETCH_MODE : R/W; bitpos: [5]; default: 0; * write this bit to set the bitscrambler rx core fetch instruction mode, 0: prefetch - * by reset, 1: fetch by instrutions + * by reset, 1: fetch by instructions */ #define BITSCRAMBLER_RX_FETCH_MODE (BIT(5)) #define BITSCRAMBLER_RX_FETCH_MODE_M (BITSCRAMBLER_RX_FETCH_MODE_V << BITSCRAMBLER_RX_FETCH_MODE_S) diff --git a/components/soc/esp32p4/include/soc/bitscrambler_struct.h b/components/soc/esp32p4/register/soc/bitscrambler_struct.h similarity index 99% rename from components/soc/esp32p4/include/soc/bitscrambler_struct.h rename to components/soc/esp32p4/register/soc/bitscrambler_struct.h index 007c244d505..6a451171ba1 100644 --- a/components/soc/esp32p4/include/soc/bitscrambler_struct.h +++ b/components/soc/esp32p4/register/soc/bitscrambler_struct.h @@ -208,7 +208,7 @@ typedef union { uint32_t tx_cond_mode:1; /** tx_fetch_mode : R/W; bitpos: [5]; default: 0; * write this bit to set the bitscrambler tx core fetch instruction mode, 0: prefetch - * by reset, 1: fetch by instrutions + * by reset, 1: fetch by instructions */ uint32_t tx_fetch_mode:1; /** tx_halt_mode : R/W; bitpos: [6]; default: 0; @@ -261,7 +261,7 @@ typedef union { uint32_t rx_cond_mode:1; /** rx_fetch_mode : R/W; bitpos: [5]; default: 0; * write this bit to set the bitscrambler rx core fetch instruction mode, 0: prefetch - * by reset, 1: fetch by instrutions + * by reset, 1: fetch by instructions */ uint32_t rx_fetch_mode:1; /** rx_halt_mode : R/W; bitpos: [6]; default: 0; diff --git a/components/soc/esp32p4/include/soc/cache_reg.h b/components/soc/esp32p4/register/soc/cache_reg.h similarity index 99% rename from components/soc/esp32p4/include/soc/cache_reg.h rename to components/soc/esp32p4/register/soc/cache_reg.h index b3cc3cd039c..e80afcd41bd 100644 --- a/components/soc/esp32p4/include/soc/cache_reg.h +++ b/components/soc/esp32p4/register/soc/cache_reg.h @@ -4270,7 +4270,7 @@ extern "C" { #define CACHE_L1_UNALLOCATE_BUFFER_CLEAR_REG (DR_REG_CACHE_BASE + 0x258) /** CACHE_L1_ICACHE0_UNALLOC_CLR : R/W; bitpos: [0]; default: 0; * The bit is used to clear the unallocate request buffer of l1 icache0 where the - * unallocate request is responsed but not completed. + * unallocate request is responded but not completed. */ #define CACHE_L1_ICACHE0_UNALLOC_CLR (BIT(0)) #define CACHE_L1_ICACHE0_UNALLOC_CLR_M (CACHE_L1_ICACHE0_UNALLOC_CLR_V << CACHE_L1_ICACHE0_UNALLOC_CLR_S) @@ -4278,7 +4278,7 @@ extern "C" { #define CACHE_L1_ICACHE0_UNALLOC_CLR_S 0 /** CACHE_L1_ICACHE1_UNALLOC_CLR : R/W; bitpos: [1]; default: 0; * The bit is used to clear the unallocate request buffer of l1 icache1 where the - * unallocate request is responsed but not completed. + * unallocate request is responded but not completed. */ #define CACHE_L1_ICACHE1_UNALLOC_CLR (BIT(1)) #define CACHE_L1_ICACHE1_UNALLOC_CLR_M (CACHE_L1_ICACHE1_UNALLOC_CLR_V << CACHE_L1_ICACHE1_UNALLOC_CLR_S) @@ -4300,7 +4300,7 @@ extern "C" { #define CACHE_L1_ICACHE3_UNALLOC_CLR_S 3 /** CACHE_L1_DCACHE_UNALLOC_CLR : R/W; bitpos: [4]; default: 0; * The bit is used to clear the unallocate request buffer of l1 dcache where the - * unallocate request is responsed but not completed. + * unallocate request is responded but not completed. */ #define CACHE_L1_DCACHE_UNALLOC_CLR (BIT(4)) #define CACHE_L1_DCACHE_UNALLOC_CLR_M (CACHE_L1_DCACHE_UNALLOC_CLR_V << CACHE_L1_DCACHE_UNALLOC_CLR_S) @@ -6156,7 +6156,7 @@ extern "C" { #define CACHE_L2_UNALLOCATE_BUFFER_CLEAR_REG (DR_REG_CACHE_BASE + 0x3b8) /** CACHE_L2_CACHE_UNALLOC_CLR : R/W; bitpos: [5]; default: 0; * The bit is used to clear the unallocate request buffer of l2 icache where the - * unallocate request is responsed but not completed. + * unallocate request is responded but not completed. */ #define CACHE_L2_CACHE_UNALLOC_CLR (BIT(5)) #define CACHE_L2_CACHE_UNALLOC_CLR_M (CACHE_L2_CACHE_UNALLOC_CLR_V << CACHE_L2_CACHE_UNALLOC_CLR_S) diff --git a/components/soc/esp32p4/include/soc/cache_struct.h b/components/soc/esp32p4/register/soc/cache_struct.h similarity index 100% rename from components/soc/esp32p4/include/soc/cache_struct.h rename to components/soc/esp32p4/register/soc/cache_struct.h diff --git a/components/soc/esp32p4/include/soc/dma2d_reg.h b/components/soc/esp32p4/register/soc/dma2d_reg.h similarity index 100% rename from components/soc/esp32p4/include/soc/dma2d_reg.h rename to components/soc/esp32p4/register/soc/dma2d_reg.h diff --git a/components/soc/esp32p4/include/soc/dma2d_struct.h b/components/soc/esp32p4/register/soc/dma2d_struct.h similarity index 100% rename from components/soc/esp32p4/include/soc/dma2d_struct.h rename to components/soc/esp32p4/register/soc/dma2d_struct.h diff --git a/components/soc/esp32p4/include/soc/dma_pms_reg.h b/components/soc/esp32p4/register/soc/dma_pms_reg.h similarity index 100% rename from components/soc/esp32p4/include/soc/dma_pms_reg.h rename to components/soc/esp32p4/register/soc/dma_pms_reg.h diff --git a/components/soc/esp32p4/include/soc/dma_pms_struct.h b/components/soc/esp32p4/register/soc/dma_pms_struct.h similarity index 100% rename from components/soc/esp32p4/include/soc/dma_pms_struct.h rename to components/soc/esp32p4/register/soc/dma_pms_struct.h diff --git a/components/soc/esp32p4/include/soc/ds_reg.h b/components/soc/esp32p4/register/soc/ds_reg.h similarity index 100% rename from components/soc/esp32p4/include/soc/ds_reg.h rename to components/soc/esp32p4/register/soc/ds_reg.h diff --git a/components/soc/esp32p4/include/soc/ds_struct.h b/components/soc/esp32p4/register/soc/ds_struct.h similarity index 100% rename from components/soc/esp32p4/include/soc/ds_struct.h rename to components/soc/esp32p4/register/soc/ds_struct.h diff --git a/components/soc/esp32p4/include/soc/dw_gdma_reg.h b/components/soc/esp32p4/register/soc/dw_gdma_reg.h similarity index 100% rename from components/soc/esp32p4/include/soc/dw_gdma_reg.h rename to components/soc/esp32p4/register/soc/dw_gdma_reg.h diff --git a/components/soc/esp32p4/include/soc/dw_gdma_struct.h b/components/soc/esp32p4/register/soc/dw_gdma_struct.h similarity index 100% rename from components/soc/esp32p4/include/soc/dw_gdma_struct.h rename to components/soc/esp32p4/register/soc/dw_gdma_struct.h diff --git a/components/soc/esp32p4/include/soc/ecc_mult_reg.h b/components/soc/esp32p4/register/soc/ecc_mult_reg.h similarity index 97% rename from components/soc/esp32p4/include/soc/ecc_mult_reg.h rename to components/soc/esp32p4/register/soc/ecc_mult_reg.h index 2bec4bb8c79..54033489df3 100644 --- a/components/soc/esp32p4/include/soc/ecc_mult_reg.h +++ b/components/soc/esp32p4/register/soc/ecc_mult_reg.h @@ -64,7 +64,7 @@ extern "C" { */ #define ECC_MULT_CONF_REG (DR_REG_ECC_MULT_BASE + 0x1c) /** ECC_MULT_START : R/W/SC; bitpos: [0]; default: 0; - * Write 1 to start caculation of ECC Accelerator. This bit will be self-cleared after + * Write 1 to start calculation of ECC Accelerator. This bit will be self-cleared after * the caculatrion is done. */ #define ECC_MULT_START (BIT(0)) @@ -97,7 +97,7 @@ extern "C" { * The work mode bits of ECC Accelerator. 0: Point Mult Mode. 1: Reserved. 2: Point * verification mode. 3: Point Verif+mult mode. 4: Jacobian Point Mult Mode. 5: Point * Add Mode. 6: Jacobian Point Verification Mode. 7: Point Verif + Jacobian Mult Mode. - * 8: mod addition. 9. mod substraction. 10: mod multiplication. 11: mod division. + * 8: mod addition. 9. mod subtraction. 10: mod multiplication. 11: mod division. */ #define ECC_MULT_WORK_MODE 0x0000000FU #define ECC_MULT_WORK_MODE_M (ECC_MULT_WORK_MODE_V << ECC_MULT_WORK_MODE_S) diff --git a/components/soc/esp32p4/include/soc/ecc_mult_struct.h b/components/soc/esp32p4/register/soc/ecc_mult_struct.h similarity index 96% rename from components/soc/esp32p4/include/soc/ecc_mult_struct.h rename to components/soc/esp32p4/register/soc/ecc_mult_struct.h index 5754a9e3cdd..d868fcc8f1f 100644 --- a/components/soc/esp32p4/include/soc/ecc_mult_struct.h +++ b/components/soc/esp32p4/register/soc/ecc_mult_struct.h @@ -77,7 +77,7 @@ typedef union { typedef union { struct { /** start : R/W/SC; bitpos: [0]; default: 0; - * Write 1 to start caculation of ECC Accelerator. This bit will be self-cleared after + * Write 1 to start calculation of ECC Accelerator. This bit will be self-cleared after * the caculatrion is done. */ uint32_t start:1; @@ -98,7 +98,7 @@ typedef union { * The work mode bits of ECC Accelerator. 0: Point Mult Mode. 1: Reserved. 2: Point * verification mode. 3: Point Verif+mult mode. 4: Jacobian Point Mult Mode. 5: Point * Add Mode. 6: Jacobian Point Verification Mode. 7: Point Verif + Jacobian Mult Mode. - * 8: mod addition. 9. mod substraction. 10: mod multiplication. 11: mod division. + * 8: mod addition. 9. mod subtraction. 10: mod multiplication. 11: mod division. */ uint32_t work_mode:4; /** security_mode : R/W; bitpos: [8]; default: 0; diff --git a/components/soc/esp32p4/include/soc/ecdsa_reg.h b/components/soc/esp32p4/register/soc/ecdsa_reg.h similarity index 98% rename from components/soc/esp32p4/include/soc/ecdsa_reg.h rename to components/soc/esp32p4/register/soc/ecdsa_reg.h index 6e09925e090..b5cc4f696af 100644 --- a/components/soc/esp32p4/include/soc/ecdsa_reg.h +++ b/components/soc/esp32p4/register/soc/ecdsa_reg.h @@ -155,7 +155,7 @@ extern "C" { */ #define ECDSA_START_REG (DR_REG_ECDSA_BASE + 0x1c) /** ECDSA_START : WT; bitpos: [0]; default: 0; - * Write 1 to start caculation of ECDSA Accelerator. This bit will be self-cleared + * Write 1 to start calculation of ECDSA Accelerator. This bit will be self-cleared * after configuration. */ #define ECDSA_START (BIT(0)) @@ -243,7 +243,7 @@ extern "C" { */ #define ECDSA_SHA_START_REG (DR_REG_ECDSA_BASE + 0x210) /** ECDSA_SHA_START : WT; bitpos: [0]; default: 0; - * Write 1 to start the first caculation of SHA Calculator in ECDSA Accelerator. This + * Write 1 to start the first calculation of SHA Calculator in ECDSA Accelerator. This * bit will be self-cleared after configuration. */ #define ECDSA_SHA_START (BIT(0)) @@ -256,7 +256,7 @@ extern "C" { */ #define ECDSA_SHA_CONTINUE_REG (DR_REG_ECDSA_BASE + 0x214) /** ECDSA_SHA_CONTINUE : WT; bitpos: [0]; default: 0; - * Write 1 to start the latter caculation of SHA Calculator in ECDSA Accelerator. This + * Write 1 to start the latter calculation of SHA Calculator in ECDSA Accelerator. This * bit will be self-cleared after configuration. */ #define ECDSA_SHA_CONTINUE (BIT(0)) diff --git a/components/soc/esp32p4/include/soc/ecdsa_struct.h b/components/soc/esp32p4/register/soc/ecdsa_struct.h similarity index 97% rename from components/soc/esp32p4/include/soc/ecdsa_struct.h rename to components/soc/esp32p4/register/soc/ecdsa_struct.h index 1d39f1ad04d..67e226f86d5 100644 --- a/components/soc/esp32p4/include/soc/ecdsa_struct.h +++ b/components/soc/esp32p4/register/soc/ecdsa_struct.h @@ -57,7 +57,7 @@ typedef union { typedef union { struct { /** start : WT; bitpos: [0]; default: 0; - * Write 1 to start caculation of ECDSA Accelerator. This bit will be self-cleared + * Write 1 to start calculation of ECDSA Accelerator. This bit will be self-cleared * after configuration. */ uint32_t start:1; @@ -228,7 +228,7 @@ typedef union { typedef union { struct { /** sha_start : WT; bitpos: [0]; default: 0; - * Write 1 to start the first caculation of SHA Calculator in ECDSA Accelerator. This + * Write 1 to start the first calculation of SHA Calculator in ECDSA Accelerator. This * bit will be self-cleared after configuration. */ uint32_t sha_start:1; @@ -243,7 +243,7 @@ typedef union { typedef union { struct { /** sha_continue : WT; bitpos: [0]; default: 0; - * Write 1 to start the latter caculation of SHA Calculator in ECDSA Accelerator. This + * Write 1 to start the latter calculation of SHA Calculator in ECDSA Accelerator. This * bit will be self-cleared after configuration. */ uint32_t sha_continue:1; diff --git a/components/soc/esp32p4/include/soc/efuse_reg.h b/components/soc/esp32p4/register/soc/efuse_reg.h similarity index 99% rename from components/soc/esp32p4/include/soc/efuse_reg.h rename to components/soc/esp32p4/register/soc/efuse_reg.h index 310bdaa73f6..f26a3c342e8 100644 --- a/components/soc/esp32p4/include/soc/efuse_reg.h +++ b/components/soc/esp32p4/register/soc/efuse_reg.h @@ -7,7 +7,7 @@ #include #include "soc/soc.h" -#include "efuse_defs.h" +#include "soc/efuse_defs.h" #ifdef __cplusplus extern "C" { #endif diff --git a/components/soc/esp32p4/include/soc/efuse_struct.h b/components/soc/esp32p4/register/soc/efuse_struct.h similarity index 100% rename from components/soc/esp32p4/include/soc/efuse_struct.h rename to components/soc/esp32p4/register/soc/efuse_struct.h diff --git a/components/soc/esp32p4/include/soc/emac_dma_struct.h b/components/soc/esp32p4/register/soc/emac_dma_struct.h similarity index 100% rename from components/soc/esp32p4/include/soc/emac_dma_struct.h rename to components/soc/esp32p4/register/soc/emac_dma_struct.h diff --git a/components/soc/esp32p4/include/soc/emac_mac_struct.h b/components/soc/esp32p4/register/soc/emac_mac_struct.h similarity index 100% rename from components/soc/esp32p4/include/soc/emac_mac_struct.h rename to components/soc/esp32p4/register/soc/emac_mac_struct.h diff --git a/components/soc/esp32p4/include/soc/gpio_ext_reg.h b/components/soc/esp32p4/register/soc/gpio_ext_reg.h similarity index 100% rename from components/soc/esp32p4/include/soc/gpio_ext_reg.h rename to components/soc/esp32p4/register/soc/gpio_ext_reg.h diff --git a/components/soc/esp32p4/include/soc/gpio_ext_struct.h b/components/soc/esp32p4/register/soc/gpio_ext_struct.h similarity index 100% rename from components/soc/esp32p4/include/soc/gpio_ext_struct.h rename to components/soc/esp32p4/register/soc/gpio_ext_struct.h diff --git a/components/soc/esp32p4/include/soc/gpio_reg.h b/components/soc/esp32p4/register/soc/gpio_reg.h similarity index 99% rename from components/soc/esp32p4/include/soc/gpio_reg.h rename to components/soc/esp32p4/register/soc/gpio_reg.h index 014c3753940..06b16129929 100644 --- a/components/soc/esp32p4/include/soc/gpio_reg.h +++ b/components/soc/esp32p4/register/soc/gpio_reg.h @@ -12151,11 +12151,11 @@ extern "C" { #define GPIO_SEND_SEQ_S 0 /** GPIO_RECIVE_SEQ_REG register - * High speed sdio pad bist recive sequence + * High speed sdio pad bist receive sequence */ #define GPIO_RECIVE_SEQ_REG (DR_REG_GPIO_BASE + 0x71c) /** GPIO_RECIVE_SEQ : RO; bitpos: [31:0]; default: 0; - * High speed sdio pad bist recive sequence + * High speed sdio pad bist receive sequence */ #define GPIO_RECIVE_SEQ 0xFFFFFFFFU #define GPIO_RECIVE_SEQ_M (GPIO_RECIVE_SEQ_V << GPIO_RECIVE_SEQ_S) diff --git a/components/soc/esp32p4/include/soc/gpio_struct.h b/components/soc/esp32p4/register/soc/gpio_struct.h similarity index 99% rename from components/soc/esp32p4/include/soc/gpio_struct.h rename to components/soc/esp32p4/register/soc/gpio_struct.h index 052c0b9a6db..5a9cab91712 100644 --- a/components/soc/esp32p4/include/soc/gpio_struct.h +++ b/components/soc/esp32p4/register/soc/gpio_struct.h @@ -580,12 +580,12 @@ typedef union { } gpio_send_seq_reg_t; /** Type of recive_seq register - * High speed sdio pad bist recive sequence + * High speed sdio pad bist receive sequence */ typedef union { struct { /** recive_seq : RO; bitpos: [31:0]; default: 0; - * High speed sdio pad bist recive sequence + * High speed sdio pad bist receive sequence */ uint32_t recive_seq:32; }; diff --git a/components/soc/esp32p4/include/soc/h264_dma_reg.h b/components/soc/esp32p4/register/soc/h264_dma_reg.h similarity index 100% rename from components/soc/esp32p4/include/soc/h264_dma_reg.h rename to components/soc/esp32p4/register/soc/h264_dma_reg.h diff --git a/components/soc/esp32p4/include/soc/h264_dma_struct.h b/components/soc/esp32p4/register/soc/h264_dma_struct.h similarity index 100% rename from components/soc/esp32p4/include/soc/h264_dma_struct.h rename to components/soc/esp32p4/register/soc/h264_dma_struct.h diff --git a/components/soc/esp32p4/include/soc/h264_reg.h b/components/soc/esp32p4/register/soc/h264_reg.h similarity index 100% rename from components/soc/esp32p4/include/soc/h264_reg.h rename to components/soc/esp32p4/register/soc/h264_reg.h diff --git a/components/soc/esp32p4/include/soc/h264_struct.h b/components/soc/esp32p4/register/soc/h264_struct.h similarity index 100% rename from components/soc/esp32p4/include/soc/h264_struct.h rename to components/soc/esp32p4/register/soc/h264_struct.h diff --git a/components/soc/esp32p4/include/soc/hmac_reg.h b/components/soc/esp32p4/register/soc/hmac_reg.h similarity index 100% rename from components/soc/esp32p4/include/soc/hmac_reg.h rename to components/soc/esp32p4/register/soc/hmac_reg.h diff --git a/components/soc/esp32p4/include/soc/hmac_struct.h b/components/soc/esp32p4/register/soc/hmac_struct.h similarity index 100% rename from components/soc/esp32p4/include/soc/hmac_struct.h rename to components/soc/esp32p4/register/soc/hmac_struct.h diff --git a/components/soc/esp32p4/include/soc/hp2lp_peri_pms_reg.h b/components/soc/esp32p4/register/soc/hp2lp_peri_pms_reg.h similarity index 100% rename from components/soc/esp32p4/include/soc/hp2lp_peri_pms_reg.h rename to components/soc/esp32p4/register/soc/hp2lp_peri_pms_reg.h diff --git a/components/soc/esp32p4/include/soc/hp2lp_peri_pms_struct.h b/components/soc/esp32p4/register/soc/hp2lp_peri_pms_struct.h similarity index 100% rename from components/soc/esp32p4/include/soc/hp2lp_peri_pms_struct.h rename to components/soc/esp32p4/register/soc/hp2lp_peri_pms_struct.h diff --git a/components/soc/esp32p4/include/soc/hp_peri_pms_reg.h b/components/soc/esp32p4/register/soc/hp_peri_pms_reg.h similarity index 100% rename from components/soc/esp32p4/include/soc/hp_peri_pms_reg.h rename to components/soc/esp32p4/register/soc/hp_peri_pms_reg.h diff --git a/components/soc/esp32p4/include/soc/hp_peri_pms_struct.h b/components/soc/esp32p4/register/soc/hp_peri_pms_struct.h similarity index 100% rename from components/soc/esp32p4/include/soc/hp_peri_pms_struct.h rename to components/soc/esp32p4/register/soc/hp_peri_pms_struct.h diff --git a/components/soc/esp32p4/include/soc/hp_sys_clkrst_reg.h b/components/soc/esp32p4/register/soc/hp_sys_clkrst_reg.h similarity index 100% rename from components/soc/esp32p4/include/soc/hp_sys_clkrst_reg.h rename to components/soc/esp32p4/register/soc/hp_sys_clkrst_reg.h diff --git a/components/soc/esp32p4/include/soc/hp_sys_clkrst_struct.h b/components/soc/esp32p4/register/soc/hp_sys_clkrst_struct.h similarity index 100% rename from components/soc/esp32p4/include/soc/hp_sys_clkrst_struct.h rename to components/soc/esp32p4/register/soc/hp_sys_clkrst_struct.h diff --git a/components/soc/esp32p4/include/soc/hp_system_reg.h b/components/soc/esp32p4/register/soc/hp_system_reg.h similarity index 99% rename from components/soc/esp32p4/include/soc/hp_system_reg.h rename to components/soc/esp32p4/register/soc/hp_system_reg.h index ec9b55a793a..e5d5a228e62 100644 --- a/components/soc/esp32p4/include/soc/hp_system_reg.h +++ b/components/soc/esp32p4/register/soc/hp_system_reg.h @@ -39,7 +39,7 @@ extern "C" { */ #define HP_SYSTEM_CPU_INT_FROM_CPU_0_REG (DR_REG_HP_SYS_BASE + 0x10) /** HP_SYSTEM_CPU_INT_FROM_CPU_0 : R/W; bitpos: [0]; default: 0; - * set 1 will triger a interrupt + * set 1 will trigger a interrupt */ #define HP_SYSTEM_CPU_INT_FROM_CPU_0 (BIT(0)) #define HP_SYSTEM_CPU_INT_FROM_CPU_0_M (HP_SYSTEM_CPU_INT_FROM_CPU_0_V << HP_SYSTEM_CPU_INT_FROM_CPU_0_S) @@ -51,7 +51,7 @@ extern "C" { */ #define HP_SYSTEM_CPU_INT_FROM_CPU_1_REG (DR_REG_HP_SYS_BASE + 0x14) /** HP_SYSTEM_CPU_INT_FROM_CPU_1 : R/W; bitpos: [0]; default: 0; - * set 1 will triger a interrupt + * set 1 will trigger a interrupt */ #define HP_SYSTEM_CPU_INT_FROM_CPU_1 (BIT(0)) #define HP_SYSTEM_CPU_INT_FROM_CPU_1_M (HP_SYSTEM_CPU_INT_FROM_CPU_1_V << HP_SYSTEM_CPU_INT_FROM_CPU_1_S) @@ -63,7 +63,7 @@ extern "C" { */ #define HP_SYSTEM_CPU_INT_FROM_CPU_2_REG (DR_REG_HP_SYS_BASE + 0x18) /** HP_SYSTEM_CPU_INT_FROM_CPU_2 : R/W; bitpos: [0]; default: 0; - * set 1 will triger a interrupt + * set 1 will trigger a interrupt */ #define HP_SYSTEM_CPU_INT_FROM_CPU_2 (BIT(0)) #define HP_SYSTEM_CPU_INT_FROM_CPU_2_M (HP_SYSTEM_CPU_INT_FROM_CPU_2_V << HP_SYSTEM_CPU_INT_FROM_CPU_2_S) @@ -75,7 +75,7 @@ extern "C" { */ #define HP_SYSTEM_CPU_INT_FROM_CPU_3_REG (DR_REG_HP_SYS_BASE + 0x1c) /** HP_SYSTEM_CPU_INT_FROM_CPU_3 : R/W; bitpos: [0]; default: 0; - * set 1 will triger a interrupt + * set 1 will trigger a interrupt */ #define HP_SYSTEM_CPU_INT_FROM_CPU_3 (BIT(0)) #define HP_SYSTEM_CPU_INT_FROM_CPU_3_M (HP_SYSTEM_CPU_INT_FROM_CPU_3_V << HP_SYSTEM_CPU_INT_FROM_CPU_3_S) @@ -87,7 +87,7 @@ extern "C" { */ #define HP_SYSTEM_CACHE_CLK_CONFIG_REG (DR_REG_HP_SYS_BASE + 0x20) /** HP_SYSTEM_REG_L2_CACHE_CLK_ON : R/W; bitpos: [0]; default: 1; - * l2 cahce clk enable + * l2 cache clk enable */ #define HP_SYSTEM_REG_L2_CACHE_CLK_ON (BIT(0)) #define HP_SYSTEM_REG_L2_CACHE_CLK_ON_M (HP_SYSTEM_REG_L2_CACHE_CLK_ON_V << HP_SYSTEM_REG_L2_CACHE_CLK_ON_S) @@ -269,7 +269,7 @@ extern "C" { */ #define HP_SYSTEM_PROBEA_CTRL_REG (DR_REG_HP_SYS_BASE + 0x50) /** HP_SYSTEM_REG_PROBE_A_MOD_SEL : R/W; bitpos: [15:0]; default: 0; - * Tihs field is used to selec probe_group from probe_group0 to probe_group15 for + * This field is used to selec probe_group from probe_group0 to probe_group15 for * module's probe_out[31:0] in a mode */ #define HP_SYSTEM_REG_PROBE_A_MOD_SEL 0x0000FFFFU @@ -277,21 +277,21 @@ extern "C" { #define HP_SYSTEM_REG_PROBE_A_MOD_SEL_V 0x0000FFFFU #define HP_SYSTEM_REG_PROBE_A_MOD_SEL_S 0 /** HP_SYSTEM_REG_PROBE_A_TOP_SEL : R/W; bitpos: [23:16]; default: 0; - * Tihs field is used to selec module's probe_out[31:0] as probe out in a mode + * This field is used to selec module's probe_out[31:0] as probe out in a mode */ #define HP_SYSTEM_REG_PROBE_A_TOP_SEL 0x000000FFU #define HP_SYSTEM_REG_PROBE_A_TOP_SEL_M (HP_SYSTEM_REG_PROBE_A_TOP_SEL_V << HP_SYSTEM_REG_PROBE_A_TOP_SEL_S) #define HP_SYSTEM_REG_PROBE_A_TOP_SEL_V 0x000000FFU #define HP_SYSTEM_REG_PROBE_A_TOP_SEL_S 16 /** HP_SYSTEM_REG_PROBE_L_SEL : R/W; bitpos: [25:24]; default: 0; - * Tihs field is used to selec probe_out[31:16] + * This field is used to selec probe_out[31:16] */ #define HP_SYSTEM_REG_PROBE_L_SEL 0x00000003U #define HP_SYSTEM_REG_PROBE_L_SEL_M (HP_SYSTEM_REG_PROBE_L_SEL_V << HP_SYSTEM_REG_PROBE_L_SEL_S) #define HP_SYSTEM_REG_PROBE_L_SEL_V 0x00000003U #define HP_SYSTEM_REG_PROBE_L_SEL_S 24 /** HP_SYSTEM_REG_PROBE_H_SEL : R/W; bitpos: [27:26]; default: 0; - * Tihs field is used to selec probe_out[31:16] + * This field is used to selec probe_out[31:16] */ #define HP_SYSTEM_REG_PROBE_H_SEL 0x00000003U #define HP_SYSTEM_REG_PROBE_H_SEL_M (HP_SYSTEM_REG_PROBE_H_SEL_V << HP_SYSTEM_REG_PROBE_H_SEL_S) @@ -310,7 +310,7 @@ extern "C" { */ #define HP_SYSTEM_PROBEB_CTRL_REG (DR_REG_HP_SYS_BASE + 0x54) /** HP_SYSTEM_REG_PROBE_B_MOD_SEL : R/W; bitpos: [15:0]; default: 0; - * Tihs field is used to selec probe_group from probe_group0 to probe_group15 for + * This field is used to selec probe_group from probe_group0 to probe_group15 for * module's probe_out[31:0] in b mode. */ #define HP_SYSTEM_REG_PROBE_B_MOD_SEL 0x0000FFFFU @@ -318,7 +318,7 @@ extern "C" { #define HP_SYSTEM_REG_PROBE_B_MOD_SEL_V 0x0000FFFFU #define HP_SYSTEM_REG_PROBE_B_MOD_SEL_S 0 /** HP_SYSTEM_REG_PROBE_B_TOP_SEL : R/W; bitpos: [23:16]; default: 0; - * Tihs field is used to select module's probe_out[31:0] as probe_out in b mode + * This field is used to select module's probe_out[31:0] as probe_out in b mode */ #define HP_SYSTEM_REG_PROBE_B_TOP_SEL 0x000000FFU #define HP_SYSTEM_REG_PROBE_B_TOP_SEL_M (HP_SYSTEM_REG_PROBE_B_TOP_SEL_V << HP_SYSTEM_REG_PROBE_B_TOP_SEL_S) @@ -1069,7 +1069,7 @@ extern "C" { */ #define HP_SYSTEM_BITSCRAMBLER_PERI_SEL_REG (DR_REG_HP_SYS_BASE + 0x140) /** HP_SYSTEM_BITSCRAMBLER_PERI_RX_SEL : R/W; bitpos: [3:0]; default: 15; - * Set this field to sel peri with DMA RX interface to connec with bitscrambler: 4'h0 + * Set this field to sel peri with DMA RX interface to connect with bitscrambler: 4'h0 * : lcd_cam, 4'h1: gpspi2, 4'h2: gpspi3, 4'h3: parl_io, 4'h4: aes, 4'h5: sha, 4'h6: * adc, 4'h7: i2s0, 4'h8: i2s1, 4'h9: i2s2, 4'ha: i3c_mst, 4'hb: uhci0, 4'hc: RMT, * else : none @@ -1079,7 +1079,7 @@ extern "C" { #define HP_SYSTEM_BITSCRAMBLER_PERI_RX_SEL_V 0x0000000FU #define HP_SYSTEM_BITSCRAMBLER_PERI_RX_SEL_S 0 /** HP_SYSTEM_BITSCRAMBLER_PERI_TX_SEL : R/W; bitpos: [7:4]; default: 15; - * Set this field to sel peri with DMA TX interface to connec with bitscrambler: 4'h0 + * Set this field to sel peri with DMA TX interface to connect with bitscrambler: 4'h0 * : lcd_cam, 4'h1: gpspi2, 4'h2: gpspi3, 4'h3: parl_io, 4'h4: aes, 4'h5: sha, 4'h6: * adc, 4'h7: i2s0, 4'h8: i2s1, 4'h9: i2s2, 4'ha: i3c_mst, 4'hb: uhci0, 4'hc: RMT, * else : none diff --git a/components/soc/esp32p4/include/soc/hp_system_struct.h b/components/soc/esp32p4/register/soc/hp_system_struct.h similarity index 98% rename from components/soc/esp32p4/include/soc/hp_system_struct.h rename to components/soc/esp32p4/register/soc/hp_system_struct.h index 628ef31ef4f..4e3d23f78ab 100644 --- a/components/soc/esp32p4/include/soc/hp_system_struct.h +++ b/components/soc/esp32p4/register/soc/hp_system_struct.h @@ -48,7 +48,7 @@ typedef union { typedef union { struct { /** cpu_int_from_cpu_0 : R/W; bitpos: [0]; default: 0; - * set 1 will triger a interrupt + * set 1 will trigger a interrupt */ uint32_t cpu_int_from_cpu_0:1; uint32_t reserved_1:31; @@ -64,7 +64,7 @@ typedef union { typedef union { struct { /** cpu_int_from_cpu_1 : R/W; bitpos: [0]; default: 0; - * set 1 will triger a interrupt + * set 1 will trigger a interrupt */ uint32_t cpu_int_from_cpu_1:1; uint32_t reserved_1:31; @@ -80,7 +80,7 @@ typedef union { typedef union { struct { /** cpu_int_from_cpu_2 : R/W; bitpos: [0]; default: 0; - * set 1 will triger a interrupt + * set 1 will trigger a interrupt */ uint32_t cpu_int_from_cpu_2:1; uint32_t reserved_1:31; @@ -96,7 +96,7 @@ typedef union { typedef union { struct { /** cpu_int_from_cpu_3 : R/W; bitpos: [0]; default: 0; - * set 1 will triger a interrupt + * set 1 will trigger a interrupt */ uint32_t cpu_int_from_cpu_3:1; uint32_t reserved_1:31; @@ -112,7 +112,7 @@ typedef union { typedef union { struct { /** reg_l2_cache_clk_on : R/W; bitpos: [0]; default: 1; - * l2 cahce clk enable + * l2 cache clk enable */ uint32_t reg_l2_cache_clk_on:1; /** reg_l1_d_cache_clk_on : R/W; bitpos: [1]; default: 1; @@ -283,20 +283,20 @@ typedef union { typedef union { struct { /** reg_probe_a_mod_sel : R/W; bitpos: [15:0]; default: 0; - * Tihs field is used to selec probe_group from probe_group0 to probe_group15 for + * This field is used to selec probe_group from probe_group0 to probe_group15 for * module's probe_out[31:0] in a mode */ uint32_t reg_probe_a_mod_sel:16; /** reg_probe_a_top_sel : R/W; bitpos: [23:16]; default: 0; - * Tihs field is used to selec module's probe_out[31:0] as probe out in a mode + * This field is used to selec module's probe_out[31:0] as probe out in a mode */ uint32_t reg_probe_a_top_sel:8; /** reg_probe_l_sel : R/W; bitpos: [25:24]; default: 0; - * Tihs field is used to selec probe_out[31:16] + * This field is used to selec probe_out[31:16] */ uint32_t reg_probe_l_sel:2; /** reg_probe_h_sel : R/W; bitpos: [27:26]; default: 0; - * Tihs field is used to selec probe_out[31:16] + * This field is used to selec probe_out[31:16] */ uint32_t reg_probe_h_sel:2; /** reg_probe_global_en : R/W; bitpos: [28]; default: 0; @@ -316,12 +316,12 @@ typedef union { typedef union { struct { /** reg_probe_b_mod_sel : R/W; bitpos: [15:0]; default: 0; - * Tihs field is used to selec probe_group from probe_group0 to probe_group15 for + * This field is used to selec probe_group from probe_group0 to probe_group15 for * module's probe_out[31:0] in b mode. */ uint32_t reg_probe_b_mod_sel:16; /** reg_probe_b_top_sel : R/W; bitpos: [23:16]; default: 0; - * Tihs field is used to select module's probe_out[31:0] as probe_out in b mode + * This field is used to select module's probe_out[31:0] as probe_out in b mode */ uint32_t reg_probe_b_top_sel:8; /** reg_probe_b_en : R/W; bitpos: [24]; default: 0; @@ -834,7 +834,7 @@ typedef union { } hp_system_tcm_rdn_eco_high_reg_t; -/** Group: HP GPIO DED HOLD CTRL REG */ +/** Group: HP GPIO DEAD HOLD CTRL REG */ /** Type of gpio_ded_hold_ctrl register * NA */ @@ -1021,14 +1021,14 @@ typedef union { typedef union { struct { /** bitscrambler_peri_rx_sel : R/W; bitpos: [3:0]; default: 15; - * Set this field to sel peri with DMA RX interface to connec with bitscrambler: 4'h0 + * Set this field to sel peri with DMA RX interface to connect with bitscrambler: 4'h0 * : lcd_cam, 4'h1: gpspi2, 4'h2: gpspi3, 4'h3: parl_io, 4'h4: aes, 4'h5: sha, 4'h6: * adc, 4'h7: i2s0, 4'h8: i2s1, 4'h9: i2s2, 4'ha: i3c_mst, 4'hb: uhci0, 4'hc: RMT, * else : none */ uint32_t bitscrambler_peri_rx_sel:4; /** bitscrambler_peri_tx_sel : R/W; bitpos: [7:4]; default: 15; - * Set this field to sel peri with DMA TX interface to connec with bitscrambler: 4'h0 + * Set this field to sel peri with DMA TX interface to connect with bitscrambler: 4'h0 * : lcd_cam, 4'h1: gpspi2, 4'h2: gpspi3, 4'h3: parl_io, 4'h4: aes, 4'h5: sha, 4'h6: * adc, 4'h7: i2s0, 4'h8: i2s1, 4'h9: i2s2, 4'ha: i3c_mst, 4'hb: uhci0, 4'hc: RMT, * else : none diff --git a/components/soc/esp32p4/include/soc/huk_reg.h b/components/soc/esp32p4/register/soc/huk_reg.h similarity index 100% rename from components/soc/esp32p4/include/soc/huk_reg.h rename to components/soc/esp32p4/register/soc/huk_reg.h diff --git a/components/soc/esp32p4/include/soc/huk_struct.h b/components/soc/esp32p4/register/soc/huk_struct.h similarity index 100% rename from components/soc/esp32p4/include/soc/huk_struct.h rename to components/soc/esp32p4/register/soc/huk_struct.h diff --git a/components/soc/esp32p4/include/soc/i2c_ana_mst_reg.h b/components/soc/esp32p4/register/soc/i2c_ana_mst_reg.h similarity index 100% rename from components/soc/esp32p4/include/soc/i2c_ana_mst_reg.h rename to components/soc/esp32p4/register/soc/i2c_ana_mst_reg.h diff --git a/components/soc/esp32p4/include/soc/i2c_ana_mst_struct.h b/components/soc/esp32p4/register/soc/i2c_ana_mst_struct.h similarity index 100% rename from components/soc/esp32p4/include/soc/i2c_ana_mst_struct.h rename to components/soc/esp32p4/register/soc/i2c_ana_mst_struct.h diff --git a/components/soc/esp32p4/include/soc/i2c_reg.h b/components/soc/esp32p4/register/soc/i2c_reg.h similarity index 100% rename from components/soc/esp32p4/include/soc/i2c_reg.h rename to components/soc/esp32p4/register/soc/i2c_reg.h diff --git a/components/soc/esp32p4/include/soc/i2c_struct.h b/components/soc/esp32p4/register/soc/i2c_struct.h similarity index 100% rename from components/soc/esp32p4/include/soc/i2c_struct.h rename to components/soc/esp32p4/register/soc/i2c_struct.h diff --git a/components/soc/esp32p4/include/soc/i2s_reg.h b/components/soc/esp32p4/register/soc/i2s_reg.h similarity index 99% rename from components/soc/esp32p4/include/soc/i2s_reg.h rename to components/soc/esp32p4/register/soc/i2s_reg.h index cf9267487d1..88ada789e78 100644 --- a/components/soc/esp32p4/include/soc/i2s_reg.h +++ b/components/soc/esp32p4/register/soc/i2s_reg.h @@ -320,7 +320,7 @@ extern "C" { #define I2S_TX_SLAVE_MOD_V 0x00000001U #define I2S_TX_SLAVE_MOD_S 3 /** I2S_TX_STOP_EN : R/W; bitpos: [4]; default: 1; - * Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy + * Set this bit to stop disable output BCK signal and WS signal when tx FIFO is empty */ #define I2S_TX_STOP_EN (BIT(4)) #define I2S_TX_STOP_EN_M (I2S_TX_STOP_EN_V << I2S_TX_STOP_EN_S) diff --git a/components/soc/esp32p4/include/soc/i2s_struct.h b/components/soc/esp32p4/register/soc/i2s_struct.h similarity index 99% rename from components/soc/esp32p4/include/soc/i2s_struct.h rename to components/soc/esp32p4/register/soc/i2s_struct.h index 6e05f6a2eb8..191b9dc6a1b 100644 --- a/components/soc/esp32p4/include/soc/i2s_struct.h +++ b/components/soc/esp32p4/register/soc/i2s_struct.h @@ -496,7 +496,7 @@ typedef union { */ uint32_t tx_slave_mod:1; /** tx_stop_en : R/W; bitpos: [4]; default: 1; - * Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy + * Set this bit to stop disable output BCK signal and WS signal when tx FIFO is empty */ uint32_t tx_stop_en:1; /** tx_chan_equal : R/W; bitpos: [5]; default: 0; diff --git a/components/soc/esp32p4/include/soc/i3c_mst_mem_reg.h b/components/soc/esp32p4/register/soc/i3c_mst_mem_reg.h similarity index 100% rename from components/soc/esp32p4/include/soc/i3c_mst_mem_reg.h rename to components/soc/esp32p4/register/soc/i3c_mst_mem_reg.h diff --git a/components/soc/esp32p4/include/soc/i3c_mst_mem_struct.h b/components/soc/esp32p4/register/soc/i3c_mst_mem_struct.h similarity index 100% rename from components/soc/esp32p4/include/soc/i3c_mst_mem_struct.h rename to components/soc/esp32p4/register/soc/i3c_mst_mem_struct.h diff --git a/components/soc/esp32p4/include/soc/i3c_mst_reg.h b/components/soc/esp32p4/register/soc/i3c_mst_reg.h similarity index 100% rename from components/soc/esp32p4/include/soc/i3c_mst_reg.h rename to components/soc/esp32p4/register/soc/i3c_mst_reg.h diff --git a/components/soc/esp32p4/include/soc/i3c_mst_struct.h b/components/soc/esp32p4/register/soc/i3c_mst_struct.h similarity index 100% rename from components/soc/esp32p4/include/soc/i3c_mst_struct.h rename to components/soc/esp32p4/register/soc/i3c_mst_struct.h diff --git a/components/soc/esp32p4/include/soc/i3c_slv_reg.h b/components/soc/esp32p4/register/soc/i3c_slv_reg.h similarity index 99% rename from components/soc/esp32p4/include/soc/i3c_slv_reg.h rename to components/soc/esp32p4/register/soc/i3c_slv_reg.h index a5684d88e0e..335ec44fc20 100644 --- a/components/soc/esp32p4/include/soc/i3c_slv_reg.h +++ b/components/soc/esp32p4/register/soc/i3c_slv_reg.h @@ -103,7 +103,7 @@ extern "C" { #define I3C_SLV_STNOTSTOP_V 0x00000001U #define I3C_SLV_STNOTSTOP_S 0 /** I3C_SLV_STMSG : RO; bitpos: [1]; default: 0; - * Is 1 if this bus Slave is listening to the bus traffic or repsonding, If + * Is 1 if this bus Slave is listening to the bus traffic or responding, If * STNOSTOP=1, then this will be 0 when a non-matching address seen until next * respeated START it STOP. */ diff --git a/components/soc/esp32p4/include/soc/i3c_slv_struct.h b/components/soc/esp32p4/register/soc/i3c_slv_struct.h similarity index 99% rename from components/soc/esp32p4/include/soc/i3c_slv_struct.h rename to components/soc/esp32p4/register/soc/i3c_slv_struct.h index 125ca7d6277..7df80af8942 100644 --- a/components/soc/esp32p4/include/soc/i3c_slv_struct.h +++ b/components/soc/esp32p4/register/soc/i3c_slv_struct.h @@ -83,7 +83,7 @@ typedef union { */ uint32_t stnotstop:1; /** stmsg : RO; bitpos: [1]; default: 0; - * Is 1 if this bus Slave is listening to the bus traffic or repsonding, If + * Is 1 if this bus Slave is listening to the bus traffic or responding, If * STNOSTOP=1, then this will be 0 when a non-matching address seen until next * respeated START it STOP. */ @@ -459,10 +459,10 @@ typedef union { */ typedef union { struct { - /** capablities : RO; bitpos: [31:0]; default: 2081684508; + /** capabilities : RO; bitpos: [31:0]; default: 2081684508; * NA */ - uint32_t capablities:32; + uint32_t capabilities:32; }; uint32_t val; } i3c_slv_capabilities_reg_t; diff --git a/components/soc/esp32p4/include/soc/icm_sys_qos_reg.h b/components/soc/esp32p4/register/soc/icm_sys_qos_reg.h similarity index 100% rename from components/soc/esp32p4/include/soc/icm_sys_qos_reg.h rename to components/soc/esp32p4/register/soc/icm_sys_qos_reg.h diff --git a/components/soc/esp32p4/include/soc/icm_sys_qos_struct.h b/components/soc/esp32p4/register/soc/icm_sys_qos_struct.h similarity index 100% rename from components/soc/esp32p4/include/soc/icm_sys_qos_struct.h rename to components/soc/esp32p4/register/soc/icm_sys_qos_struct.h diff --git a/components/soc/esp32p4/include/soc/icm_sys_reg.h b/components/soc/esp32p4/register/soc/icm_sys_reg.h similarity index 100% rename from components/soc/esp32p4/include/soc/icm_sys_reg.h rename to components/soc/esp32p4/register/soc/icm_sys_reg.h diff --git a/components/soc/esp32p4/include/soc/icm_sys_struct.h b/components/soc/esp32p4/register/soc/icm_sys_struct.h similarity index 100% rename from components/soc/esp32p4/include/soc/icm_sys_struct.h rename to components/soc/esp32p4/register/soc/icm_sys_struct.h diff --git a/components/soc/esp32p4/include/soc/interrupt_core0_reg.h b/components/soc/esp32p4/register/soc/interrupt_core0_reg.h similarity index 100% rename from components/soc/esp32p4/include/soc/interrupt_core0_reg.h rename to components/soc/esp32p4/register/soc/interrupt_core0_reg.h diff --git a/components/soc/esp32p4/include/soc/interrupt_core0_struct.h b/components/soc/esp32p4/register/soc/interrupt_core0_struct.h similarity index 100% rename from components/soc/esp32p4/include/soc/interrupt_core0_struct.h rename to components/soc/esp32p4/register/soc/interrupt_core0_struct.h diff --git a/components/soc/esp32p4/include/soc/interrupt_core1_reg.h b/components/soc/esp32p4/register/soc/interrupt_core1_reg.h similarity index 100% rename from components/soc/esp32p4/include/soc/interrupt_core1_reg.h rename to components/soc/esp32p4/register/soc/interrupt_core1_reg.h diff --git a/components/soc/esp32p4/include/soc/interrupt_core1_struct.h b/components/soc/esp32p4/register/soc/interrupt_core1_struct.h similarity index 100% rename from components/soc/esp32p4/include/soc/interrupt_core1_struct.h rename to components/soc/esp32p4/register/soc/interrupt_core1_struct.h diff --git a/components/soc/esp32p4/include/soc/io_mux_reg.h b/components/soc/esp32p4/register/soc/io_mux_reg.h similarity index 99% rename from components/soc/esp32p4/include/soc/io_mux_reg.h rename to components/soc/esp32p4/register/soc/io_mux_reg.h index 02440af9030..d7eba33c2cf 100644 --- a/components/soc/esp32p4/include/soc/io_mux_reg.h +++ b/components/soc/esp32p4/register/soc/io_mux_reg.h @@ -5,7 +5,7 @@ */ #pragma once -#include "soc.h" +#include "soc/soc.h" /* The following are the bit fields for PERIPHS_IO_MUX_x_U registers */ /* Output enable in sleep mode */ diff --git a/components/soc/esp32p4/include/soc/io_mux_struct.h b/components/soc/esp32p4/register/soc/io_mux_struct.h similarity index 100% rename from components/soc/esp32p4/include/soc/io_mux_struct.h rename to components/soc/esp32p4/register/soc/io_mux_struct.h diff --git a/components/soc/esp32p4/include/soc/iomux_mspi_pin_reg.h b/components/soc/esp32p4/register/soc/iomux_mspi_pin_reg.h similarity index 100% rename from components/soc/esp32p4/include/soc/iomux_mspi_pin_reg.h rename to components/soc/esp32p4/register/soc/iomux_mspi_pin_reg.h diff --git a/components/soc/esp32p4/include/soc/iomux_mspi_pin_struct.h b/components/soc/esp32p4/register/soc/iomux_mspi_pin_struct.h similarity index 100% rename from components/soc/esp32p4/include/soc/iomux_mspi_pin_struct.h rename to components/soc/esp32p4/register/soc/iomux_mspi_pin_struct.h diff --git a/components/soc/esp32p4/include/soc/isp_reg.h b/components/soc/esp32p4/register/soc/isp_reg.h similarity index 99% rename from components/soc/esp32p4/include/soc/isp_reg.h rename to components/soc/esp32p4/register/soc/isp_reg.h index 13749f014c8..c1c42d64aaf 100644 --- a/components/soc/esp32p4/include/soc/isp_reg.h +++ b/components/soc/esp32p4/register/soc/isp_reg.h @@ -521,56 +521,56 @@ extern "C" { */ #define ISP_BF_GAU0_REG (DR_REG_ISP_BASE + 0x30) /** ISP_GAU_TEMPLATE21 : R/W; bitpos: [3:0]; default: 15; - * this field configures index 21 of gausian template + * this field configures index 21 of gaussian template */ #define ISP_GAU_TEMPLATE21 0x0000000FU #define ISP_GAU_TEMPLATE21_M (ISP_GAU_TEMPLATE21_V << ISP_GAU_TEMPLATE21_S) #define ISP_GAU_TEMPLATE21_V 0x0000000FU #define ISP_GAU_TEMPLATE21_S 0 /** ISP_GAU_TEMPLATE20 : R/W; bitpos: [7:4]; default: 15; - * this field configures index 20 of gausian template + * this field configures index 20 of gaussian template */ #define ISP_GAU_TEMPLATE20 0x0000000FU #define ISP_GAU_TEMPLATE20_M (ISP_GAU_TEMPLATE20_V << ISP_GAU_TEMPLATE20_S) #define ISP_GAU_TEMPLATE20_V 0x0000000FU #define ISP_GAU_TEMPLATE20_S 4 /** ISP_GAU_TEMPLATE12 : R/W; bitpos: [11:8]; default: 15; - * this field configures index 12 of gausian template + * this field configures index 12 of gaussian template */ #define ISP_GAU_TEMPLATE12 0x0000000FU #define ISP_GAU_TEMPLATE12_M (ISP_GAU_TEMPLATE12_V << ISP_GAU_TEMPLATE12_S) #define ISP_GAU_TEMPLATE12_V 0x0000000FU #define ISP_GAU_TEMPLATE12_S 8 /** ISP_GAU_TEMPLATE11 : R/W; bitpos: [15:12]; default: 15; - * this field configures index 11 of gausian template + * this field configures index 11 of gaussian template */ #define ISP_GAU_TEMPLATE11 0x0000000FU #define ISP_GAU_TEMPLATE11_M (ISP_GAU_TEMPLATE11_V << ISP_GAU_TEMPLATE11_S) #define ISP_GAU_TEMPLATE11_V 0x0000000FU #define ISP_GAU_TEMPLATE11_S 12 /** ISP_GAU_TEMPLATE10 : R/W; bitpos: [19:16]; default: 15; - * this field configures index 10 of gausian template + * this field configures index 10 of gaussian template */ #define ISP_GAU_TEMPLATE10 0x0000000FU #define ISP_GAU_TEMPLATE10_M (ISP_GAU_TEMPLATE10_V << ISP_GAU_TEMPLATE10_S) #define ISP_GAU_TEMPLATE10_V 0x0000000FU #define ISP_GAU_TEMPLATE10_S 16 /** ISP_GAU_TEMPLATE02 : R/W; bitpos: [23:20]; default: 15; - * this field configures index 02 of gausian template + * this field configures index 02 of gaussian template */ #define ISP_GAU_TEMPLATE02 0x0000000FU #define ISP_GAU_TEMPLATE02_M (ISP_GAU_TEMPLATE02_V << ISP_GAU_TEMPLATE02_S) #define ISP_GAU_TEMPLATE02_V 0x0000000FU #define ISP_GAU_TEMPLATE02_S 20 /** ISP_GAU_TEMPLATE01 : R/W; bitpos: [27:24]; default: 15; - * this field configures index 01 of gausian template + * this field configures index 01 of gaussian template */ #define ISP_GAU_TEMPLATE01 0x0000000FU #define ISP_GAU_TEMPLATE01_M (ISP_GAU_TEMPLATE01_V << ISP_GAU_TEMPLATE01_S) #define ISP_GAU_TEMPLATE01_V 0x0000000FU #define ISP_GAU_TEMPLATE01_S 24 /** ISP_GAU_TEMPLATE00 : R/W; bitpos: [31:28]; default: 15; - * this field configures index 00 of gausian template + * this field configures index 00 of gaussian template */ #define ISP_GAU_TEMPLATE00 0x0000000FU #define ISP_GAU_TEMPLATE00_M (ISP_GAU_TEMPLATE00_V << ISP_GAU_TEMPLATE00_S) @@ -582,7 +582,7 @@ extern "C" { */ #define ISP_BF_GAU1_REG (DR_REG_ISP_BASE + 0x34) /** ISP_GAU_TEMPLATE22 : R/W; bitpos: [3:0]; default: 15; - * this field configures index 22 of gausian template + * this field configures index 22 of gaussian template */ #define ISP_GAU_TEMPLATE22 0x0000000FU #define ISP_GAU_TEMPLATE22_M (ISP_GAU_TEMPLATE22_V << ISP_GAU_TEMPLATE22_S) @@ -2584,7 +2584,7 @@ extern "C" { #define ISP_AE_MONITOR_TH_V 0x000000FFU #define ISP_AE_MONITOR_TH_S 8 /** ISP_AE_MONITOR_PERIOD : R/W; bitpos: [21:16]; default: 0; - * this field cnfigures ae monitor frame period + * this field configures ae monitor frame period */ #define ISP_AE_MONITOR_PERIOD 0x0000003FU #define ISP_AE_MONITOR_PERIOD_M (ISP_AE_MONITOR_PERIOD_V << ISP_AE_MONITOR_PERIOD_S) @@ -3030,7 +3030,7 @@ extern "C" { */ #define ISP_DMA_CNTL_REG (DR_REG_ISP_BASE + 0x10c) /** ISP_DMA_EN : WT; bitpos: [0]; default: 0; - * write 1 to triger dma to get 1 frame + * write 1 to trigger dma to get 1 frame */ #define ISP_DMA_EN (BIT(0)) #define ISP_DMA_EN_M (ISP_DMA_EN_V << ISP_DMA_EN_S) @@ -3090,7 +3090,7 @@ extern "C" { */ #define ISP_CAM_CNTL_REG (DR_REG_ISP_BASE + 0x114) /** ISP_CAM_EN : R/W; bitpos: [0]; default: 0; - * write 1 to start recive camera data, write 0 to disable + * write 1 to start receive camera data, write 0 to disable */ #define ISP_CAM_EN (BIT(0)) #define ISP_CAM_EN_M (ISP_CAM_EN_V << ISP_CAM_EN_S) @@ -3111,7 +3111,7 @@ extern "C" { #define ISP_CAM_RESET_V 0x00000001U #define ISP_CAM_RESET_S 2 /** ISP_CAM_CLK_INV : R/W; bitpos: [3]; default: 0; - * this bit configures the invertion of cam clk from pad. 0: not invert cam clk, 1: + * this bit configures the inversion of cam clk from pad. 0: not invert cam clk, 1: * invert cam clk */ #define ISP_CAM_CLK_INV (BIT(3)) @@ -3487,7 +3487,7 @@ extern "C" { */ #define ISP_AWB_MODE_REG (DR_REG_ISP_BASE + 0x164) /** ISP_AWB_MODE : R/W; bitpos: [1:0]; default: 3; - * this field configures awb algo sel. 00: none sellected. 01: sel algo0. 10: sel + * this field configures awb algo sel. 00: none selected. 01: sel algo0. 10: sel * algo1. 11: sel both algo0 and algo1 */ #define ISP_AWB_MODE 0x00000003U diff --git a/components/soc/esp32p4/include/soc/isp_struct.h b/components/soc/esp32p4/register/soc/isp_struct.h similarity index 100% rename from components/soc/esp32p4/include/soc/isp_struct.h rename to components/soc/esp32p4/register/soc/isp_struct.h diff --git a/components/soc/esp32p4/include/soc/jpeg_reg.h b/components/soc/esp32p4/register/soc/jpeg_reg.h similarity index 100% rename from components/soc/esp32p4/include/soc/jpeg_reg.h rename to components/soc/esp32p4/register/soc/jpeg_reg.h diff --git a/components/soc/esp32p4/include/soc/jpeg_struct.h b/components/soc/esp32p4/register/soc/jpeg_struct.h similarity index 100% rename from components/soc/esp32p4/include/soc/jpeg_struct.h rename to components/soc/esp32p4/register/soc/jpeg_struct.h diff --git a/components/soc/esp32p4/include/soc/keymng_reg.h b/components/soc/esp32p4/register/soc/keymng_reg.h similarity index 100% rename from components/soc/esp32p4/include/soc/keymng_reg.h rename to components/soc/esp32p4/register/soc/keymng_reg.h diff --git a/components/soc/esp32p4/include/soc/keymng_struct.h b/components/soc/esp32p4/register/soc/keymng_struct.h similarity index 100% rename from components/soc/esp32p4/include/soc/keymng_struct.h rename to components/soc/esp32p4/register/soc/keymng_struct.h diff --git a/components/soc/esp32p4/include/soc/l2mem_monitor_reg.h b/components/soc/esp32p4/register/soc/l2mem_monitor_reg.h similarity index 100% rename from components/soc/esp32p4/include/soc/l2mem_monitor_reg.h rename to components/soc/esp32p4/register/soc/l2mem_monitor_reg.h diff --git a/components/soc/esp32p4/include/soc/l2mem_monitor_struct.h b/components/soc/esp32p4/register/soc/l2mem_monitor_struct.h similarity index 98% rename from components/soc/esp32p4/include/soc/l2mem_monitor_struct.h rename to components/soc/esp32p4/register/soc/l2mem_monitor_struct.h index c88691215af..e3e1abf3761 100644 --- a/components/soc/esp32p4/include/soc/l2mem_monitor_struct.h +++ b/components/soc/esp32p4/register/soc/l2mem_monitor_struct.h @@ -12,7 +12,7 @@ extern "C" { /** Group: configuration registers */ /** Type of log_setting register - * log config regsiter + * log config register */ typedef union { struct { @@ -43,7 +43,7 @@ typedef union { } mem_monitor_log_setting_reg_t; /** Type of log_setting1 register - * log config regsiter + * log config register */ typedef union { struct { @@ -61,7 +61,7 @@ typedef union { } mem_monitor_log_setting1_reg_t; /** Type of log_check_data register - * check data regsiter + * check data register */ typedef union { struct { @@ -89,7 +89,7 @@ typedef union { } mem_monitor_log_data_mask_reg_t; /** Type of log_min register - * log boundary regsiter + * log boundary register */ typedef union { struct { @@ -102,7 +102,7 @@ typedef union { } mem_monitor_log_min_reg_t; /** Type of log_max register - * log boundary regsiter + * log boundary register */ typedef union { struct { diff --git a/components/soc/esp32p4/include/soc/lcd_cam_reg.h b/components/soc/esp32p4/register/soc/lcd_cam_reg.h similarity index 100% rename from components/soc/esp32p4/include/soc/lcd_cam_reg.h rename to components/soc/esp32p4/register/soc/lcd_cam_reg.h diff --git a/components/soc/esp32p4/include/soc/lcd_cam_struct.h b/components/soc/esp32p4/register/soc/lcd_cam_struct.h similarity index 100% rename from components/soc/esp32p4/include/soc/lcd_cam_struct.h rename to components/soc/esp32p4/register/soc/lcd_cam_struct.h diff --git a/components/soc/esp32p4/include/soc/ledc_reg.h b/components/soc/esp32p4/register/soc/ledc_reg.h similarity index 100% rename from components/soc/esp32p4/include/soc/ledc_reg.h rename to components/soc/esp32p4/register/soc/ledc_reg.h diff --git a/components/soc/esp32p4/include/soc/ledc_struct.h b/components/soc/esp32p4/register/soc/ledc_struct.h similarity index 100% rename from components/soc/esp32p4/include/soc/ledc_struct.h rename to components/soc/esp32p4/register/soc/ledc_struct.h diff --git a/components/soc/esp32p4/include/soc/lp2hp_peri_pms_reg.h b/components/soc/esp32p4/register/soc/lp2hp_peri_pms_reg.h similarity index 100% rename from components/soc/esp32p4/include/soc/lp2hp_peri_pms_reg.h rename to components/soc/esp32p4/register/soc/lp2hp_peri_pms_reg.h diff --git a/components/soc/esp32p4/include/soc/lp2hp_peri_pms_struct.h b/components/soc/esp32p4/register/soc/lp2hp_peri_pms_struct.h similarity index 100% rename from components/soc/esp32p4/include/soc/lp2hp_peri_pms_struct.h rename to components/soc/esp32p4/register/soc/lp2hp_peri_pms_struct.h diff --git a/components/soc/esp32p4/include/soc/lp_adc_reg.h b/components/soc/esp32p4/register/soc/lp_adc_reg.h similarity index 100% rename from components/soc/esp32p4/include/soc/lp_adc_reg.h rename to components/soc/esp32p4/register/soc/lp_adc_reg.h diff --git a/components/soc/esp32p4/include/soc/lp_adc_struct.h b/components/soc/esp32p4/register/soc/lp_adc_struct.h similarity index 100% rename from components/soc/esp32p4/include/soc/lp_adc_struct.h rename to components/soc/esp32p4/register/soc/lp_adc_struct.h diff --git a/components/soc/esp32p4/include/soc/lp_analog_peri_reg.h b/components/soc/esp32p4/register/soc/lp_analog_peri_reg.h similarity index 100% rename from components/soc/esp32p4/include/soc/lp_analog_peri_reg.h rename to components/soc/esp32p4/register/soc/lp_analog_peri_reg.h diff --git a/components/soc/esp32p4/include/soc/lp_analog_peri_struct.h b/components/soc/esp32p4/register/soc/lp_analog_peri_struct.h similarity index 100% rename from components/soc/esp32p4/include/soc/lp_analog_peri_struct.h rename to components/soc/esp32p4/register/soc/lp_analog_peri_struct.h diff --git a/components/soc/esp32p4/include/soc/lp_clkrst_reg.h b/components/soc/esp32p4/register/soc/lp_clkrst_reg.h similarity index 99% rename from components/soc/esp32p4/include/soc/lp_clkrst_reg.h rename to components/soc/esp32p4/register/soc/lp_clkrst_reg.h index de3f17820c1..a771250be62 100644 --- a/components/soc/esp32p4/include/soc/lp_clkrst_reg.h +++ b/components/soc/esp32p4/register/soc/lp_clkrst_reg.h @@ -829,7 +829,7 @@ extern "C" { #define LP_CLKRST_HP_FOSC_20M_CLK_EN_V 0x00000001U #define LP_CLKRST_HP_FOSC_20M_CLK_EN_S 24 /** LP_CLKRST_HP_XTAL_40M_CLK_EN : R/W; bitpos: [25]; default: 1; - * XTAL 40M Clock Enalbe. + * XTAL 40M Clock Enable. */ #define LP_CLKRST_HP_XTAL_40M_CLK_EN (BIT(25)) #define LP_CLKRST_HP_XTAL_40M_CLK_EN_M (LP_CLKRST_HP_XTAL_40M_CLK_EN_V << LP_CLKRST_HP_XTAL_40M_CLK_EN_S) diff --git a/components/soc/esp32p4/include/soc/lp_clkrst_struct.h b/components/soc/esp32p4/register/soc/lp_clkrst_struct.h similarity index 99% rename from components/soc/esp32p4/include/soc/lp_clkrst_struct.h rename to components/soc/esp32p4/register/soc/lp_clkrst_struct.h index 2e2246001f4..b21775966a1 100644 --- a/components/soc/esp32p4/include/soc/lp_clkrst_struct.h +++ b/components/soc/esp32p4/register/soc/lp_clkrst_struct.h @@ -611,7 +611,7 @@ typedef union { */ uint32_t hp_fosc_20m_clk_en:1; /** hp_xtal_40m_clk_en : R/W; bitpos: [25]; default: 1; - * XTAL 40M Clock Enalbe. + * XTAL 40M Clock Enable. */ uint32_t hp_xtal_40m_clk_en:1; /** hp_cpll_400m_clk_en : R/W; bitpos: [26]; default: 1; diff --git a/components/soc/esp32p4/include/soc/lp_gpio_reg.h b/components/soc/esp32p4/register/soc/lp_gpio_reg.h similarity index 100% rename from components/soc/esp32p4/include/soc/lp_gpio_reg.h rename to components/soc/esp32p4/register/soc/lp_gpio_reg.h diff --git a/components/soc/esp32p4/include/soc/lp_gpio_struct.h b/components/soc/esp32p4/register/soc/lp_gpio_struct.h similarity index 100% rename from components/soc/esp32p4/include/soc/lp_gpio_struct.h rename to components/soc/esp32p4/register/soc/lp_gpio_struct.h diff --git a/components/soc/esp32p4/include/soc/lp_i2c_reg.h b/components/soc/esp32p4/register/soc/lp_i2c_reg.h similarity index 100% rename from components/soc/esp32p4/include/soc/lp_i2c_reg.h rename to components/soc/esp32p4/register/soc/lp_i2c_reg.h diff --git a/components/soc/esp32p4/include/soc/lp_i2c_struct.h b/components/soc/esp32p4/register/soc/lp_i2c_struct.h similarity index 100% rename from components/soc/esp32p4/include/soc/lp_i2c_struct.h rename to components/soc/esp32p4/register/soc/lp_i2c_struct.h diff --git a/components/soc/esp32p4/include/soc/lp_i2s_reg.h b/components/soc/esp32p4/register/soc/lp_i2s_reg.h similarity index 100% rename from components/soc/esp32p4/include/soc/lp_i2s_reg.h rename to components/soc/esp32p4/register/soc/lp_i2s_reg.h diff --git a/components/soc/esp32p4/include/soc/lp_i2s_struct.h b/components/soc/esp32p4/register/soc/lp_i2s_struct.h similarity index 100% rename from components/soc/esp32p4/include/soc/lp_i2s_struct.h rename to components/soc/esp32p4/register/soc/lp_i2s_struct.h diff --git a/components/soc/esp32p4/include/soc/lp_intr_reg.h b/components/soc/esp32p4/register/soc/lp_intr_reg.h similarity index 100% rename from components/soc/esp32p4/include/soc/lp_intr_reg.h rename to components/soc/esp32p4/register/soc/lp_intr_reg.h diff --git a/components/soc/esp32p4/include/soc/lp_intr_struct.h b/components/soc/esp32p4/register/soc/lp_intr_struct.h similarity index 100% rename from components/soc/esp32p4/include/soc/lp_intr_struct.h rename to components/soc/esp32p4/register/soc/lp_intr_struct.h diff --git a/components/soc/esp32p4/include/soc/lp_iomux_reg.h b/components/soc/esp32p4/register/soc/lp_iomux_reg.h similarity index 100% rename from components/soc/esp32p4/include/soc/lp_iomux_reg.h rename to components/soc/esp32p4/register/soc/lp_iomux_reg.h diff --git a/components/soc/esp32p4/include/soc/lp_iomux_struct.h b/components/soc/esp32p4/register/soc/lp_iomux_struct.h similarity index 100% rename from components/soc/esp32p4/include/soc/lp_iomux_struct.h rename to components/soc/esp32p4/register/soc/lp_iomux_struct.h diff --git a/components/soc/esp32p4/include/soc/lp_mailbox_reg.h b/components/soc/esp32p4/register/soc/lp_mailbox_reg.h similarity index 100% rename from components/soc/esp32p4/include/soc/lp_mailbox_reg.h rename to components/soc/esp32p4/register/soc/lp_mailbox_reg.h diff --git a/components/soc/esp32p4/include/soc/lp_mailbox_struct.h b/components/soc/esp32p4/register/soc/lp_mailbox_struct.h similarity index 100% rename from components/soc/esp32p4/include/soc/lp_mailbox_struct.h rename to components/soc/esp32p4/register/soc/lp_mailbox_struct.h diff --git a/components/soc/esp32p4/include/soc/lp_peri_pms_reg.h b/components/soc/esp32p4/register/soc/lp_peri_pms_reg.h similarity index 100% rename from components/soc/esp32p4/include/soc/lp_peri_pms_reg.h rename to components/soc/esp32p4/register/soc/lp_peri_pms_reg.h diff --git a/components/soc/esp32p4/include/soc/lp_peri_pms_struct.h b/components/soc/esp32p4/register/soc/lp_peri_pms_struct.h similarity index 100% rename from components/soc/esp32p4/include/soc/lp_peri_pms_struct.h rename to components/soc/esp32p4/register/soc/lp_peri_pms_struct.h diff --git a/components/soc/esp32p4/include/soc/lp_spi_reg.h b/components/soc/esp32p4/register/soc/lp_spi_reg.h similarity index 99% rename from components/soc/esp32p4/include/soc/lp_spi_reg.h rename to components/soc/esp32p4/register/soc/lp_spi_reg.h index c00998b2b82..5892adfe42c 100644 --- a/components/soc/esp32p4/include/soc/lp_spi_reg.h +++ b/components/soc/esp32p4/register/soc/lp_spi_reg.h @@ -126,7 +126,7 @@ extern "C" { #define LP_REG_CLKDIV_PRE_V 0x0000000FU #define LP_REG_CLKDIV_PRE_S 18 /** LP_REG_CLK_EQU_SYSCLK : R/W; bitpos: [31]; default: 1; - * In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system + * In the master mode 1: spi_clk is equal to system 0: spi_clk is divided from system * clock. Can be configured in CONF state. */ #define LP_REG_CLK_EQU_SYSCLK (BIT(31)) @@ -1208,7 +1208,7 @@ extern "C" { /** LP_REG_CLK_MODE : R/W; bitpos: [1:0]; default: 0; * SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed * one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: - * SPI clock is alwasy on. Can be configured in CONF state. + * SPI clock is always on. Can be configured in CONF state. */ #define LP_REG_CLK_MODE 0x00000003U #define LP_REG_CLK_MODE_M (LP_REG_CLK_MODE_V << LP_REG_CLK_MODE_S) diff --git a/components/soc/esp32p4/include/soc/lp_spi_struct.h b/components/soc/esp32p4/register/soc/lp_spi_struct.h similarity index 100% rename from components/soc/esp32p4/include/soc/lp_spi_struct.h rename to components/soc/esp32p4/register/soc/lp_spi_struct.h diff --git a/components/soc/esp32p4/include/soc/lp_system_reg.h b/components/soc/esp32p4/register/soc/lp_system_reg.h similarity index 100% rename from components/soc/esp32p4/include/soc/lp_system_reg.h rename to components/soc/esp32p4/register/soc/lp_system_reg.h diff --git a/components/soc/esp32p4/include/soc/lp_system_struct.h b/components/soc/esp32p4/register/soc/lp_system_struct.h similarity index 100% rename from components/soc/esp32p4/include/soc/lp_system_struct.h rename to components/soc/esp32p4/register/soc/lp_system_struct.h diff --git a/components/soc/esp32p4/include/soc/lp_timer_reg.h b/components/soc/esp32p4/register/soc/lp_timer_reg.h similarity index 100% rename from components/soc/esp32p4/include/soc/lp_timer_reg.h rename to components/soc/esp32p4/register/soc/lp_timer_reg.h diff --git a/components/soc/esp32p4/include/soc/lp_timer_struct.h b/components/soc/esp32p4/register/soc/lp_timer_struct.h similarity index 100% rename from components/soc/esp32p4/include/soc/lp_timer_struct.h rename to components/soc/esp32p4/register/soc/lp_timer_struct.h diff --git a/components/soc/esp32p4/include/soc/lp_uart_reg.h b/components/soc/esp32p4/register/soc/lp_uart_reg.h similarity index 99% rename from components/soc/esp32p4/include/soc/lp_uart_reg.h rename to components/soc/esp32p4/register/soc/lp_uart_reg.h index 0a5ba491f40..d488866f781 100644 --- a/components/soc/esp32p4/include/soc/lp_uart_reg.h +++ b/components/soc/esp32p4/register/soc/lp_uart_reg.h @@ -100,7 +100,7 @@ extern "C" { #define LP_UART_RXFIFO_TOUT_INT_RAW_V 0x00000001U #define LP_UART_RXFIFO_TOUT_INT_RAW_S 8 /** LP_UART_SW_XON_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; - * This interrupt raw bit turns to high level when receiver recevies Xon char when + * This interrupt raw bit turns to high level when receiver receives Xon char when * uart_sw_flow_con_en is set to 1. */ #define LP_UART_SW_XON_INT_RAW (BIT(9)) @@ -261,7 +261,7 @@ extern "C" { #define LP_UART_TX_BRK_DONE_INT_ST_V 0x00000001U #define LP_UART_TX_BRK_DONE_INT_ST_S 12 /** LP_UART_TX_BRK_IDLE_DONE_INT_ST : RO; bitpos: [13]; default: 0; - * This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena + * This is the status bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena * is set to 1. */ #define LP_UART_TX_BRK_IDLE_DONE_INT_ST (BIT(13)) @@ -671,7 +671,7 @@ extern "C" { #define LP_UART_STOP_BIT_NUM_V 0x00000003U #define LP_UART_STOP_BIT_NUM_S 4 /** LP_UART_TXD_BRK : R/W; bitpos: [6]; default: 0; - * Set this bit to enbale transmitter to send NULL when the process of sending data + * Set this bit to enable transmitter to send NULL when the process of sending data * is done. */ #define LP_UART_TXD_BRK (BIT(6)) @@ -1151,7 +1151,7 @@ extern "C" { */ #define LP_UART_TOUT_CONF_SYNC_REG (DR_REG_LP_UART_BASE + 0x64) /** LP_UART_RX_TOUT_EN : R/W; bitpos: [0]; default: 0; - * This is the enble bit for uart receiver's timeout function. + * This is the enable bit for uart receiver's timeout function. */ #define LP_UART_RX_TOUT_EN (BIT(0)) #define LP_UART_RX_TOUT_EN_M (LP_UART_RX_TOUT_EN_V << LP_UART_RX_TOUT_EN_S) diff --git a/components/soc/esp32p4/include/soc/lp_uart_struct.h b/components/soc/esp32p4/register/soc/lp_uart_struct.h similarity index 99% rename from components/soc/esp32p4/include/soc/lp_uart_struct.h rename to components/soc/esp32p4/register/soc/lp_uart_struct.h index 5bd4d605c0b..d86d6a0d91d 100644 --- a/components/soc/esp32p4/include/soc/lp_uart_struct.h +++ b/components/soc/esp32p4/register/soc/lp_uart_struct.h @@ -50,7 +50,7 @@ typedef union { typedef union { struct { /** rx_tout_en : R/W; bitpos: [0]; default: 0; - * This is the enble bit for uart receiver's timeout function. + * This is the enable bit for uart receiver's timeout function. */ uint32_t rx_tout_en:1; /** rx_tout_flow_dis : R/W; bitpos: [1]; default: 0; @@ -121,7 +121,7 @@ typedef union { */ uint32_t rxfifo_tout_int_raw:1; /** sw_xon_int_raw : R/WTC/SS; bitpos: [9]; default: 0; - * This interrupt raw bit turns to high level when receiver recevies Xon char when + * This interrupt raw bit turns to high level when receiver receives Xon char when * uart_sw_flow_con_en is set to 1. */ uint32_t sw_xon_int_raw:1; @@ -225,7 +225,7 @@ typedef union { */ uint32_t tx_brk_done_int_st:1; /** tx_brk_idle_done_int_st : RO; bitpos: [13]; default: 0; - * This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena + * This is the status bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena * is set to 1. */ uint32_t tx_brk_idle_done_int_st:1; @@ -467,7 +467,7 @@ typedef union { */ uint32_t stop_bit_num:2; /** txd_brk : R/W; bitpos: [6]; default: 0; - * Set this bit to enbale transmitter to send NULL when the process of sending data + * Set this bit to enable transmitter to send NULL when the process of sending data * is done. */ uint32_t txd_brk:1; diff --git a/components/soc/esp32p4/include/soc/lp_wdt_reg.h b/components/soc/esp32p4/register/soc/lp_wdt_reg.h similarity index 100% rename from components/soc/esp32p4/include/soc/lp_wdt_reg.h rename to components/soc/esp32p4/register/soc/lp_wdt_reg.h diff --git a/components/soc/esp32p4/include/soc/lp_wdt_struct.h b/components/soc/esp32p4/register/soc/lp_wdt_struct.h similarity index 100% rename from components/soc/esp32p4/include/soc/lp_wdt_struct.h rename to components/soc/esp32p4/register/soc/lp_wdt_struct.h diff --git a/components/soc/esp32p4/include/soc/lpperi_reg.h b/components/soc/esp32p4/register/soc/lpperi_reg.h similarity index 100% rename from components/soc/esp32p4/include/soc/lpperi_reg.h rename to components/soc/esp32p4/register/soc/lpperi_reg.h diff --git a/components/soc/esp32p4/include/soc/lpperi_struct.h b/components/soc/esp32p4/register/soc/lpperi_struct.h similarity index 100% rename from components/soc/esp32p4/include/soc/lpperi_struct.h rename to components/soc/esp32p4/register/soc/lpperi_struct.h diff --git a/components/soc/esp32p4/include/soc/mcpwm_reg.h b/components/soc/esp32p4/register/soc/mcpwm_reg.h similarity index 99% rename from components/soc/esp32p4/include/soc/mcpwm_reg.h rename to components/soc/esp32p4/register/soc/mcpwm_reg.h index e526c38e605..8534b7f3345 100644 --- a/components/soc/esp32p4/include/soc/mcpwm_reg.h +++ b/components/soc/esp32p4/register/soc/mcpwm_reg.h @@ -2764,7 +2764,7 @@ extern "C" { #define MCPWM_CAP0_MODE_V 0x00000003U #define MCPWM_CAP0_MODE_S 1 /** MCPWM_CAP0_PRESCALE : R/W; bitpos: [10:3]; default: 0; - * Configures prescale value on possitive edge of CAP0. Prescale value = + * Configures prescale value on positive edge of CAP0. Prescale value = * PWM_CAP0_PRESCALE + 1 */ #define MCPWM_CAP0_PRESCALE 0x000000FFU @@ -2809,7 +2809,7 @@ extern "C" { #define MCPWM_CAP0_MODE_V 0x00000003U #define MCPWM_CAP0_MODE_S 1 /** MCPWM_CAP0_PRESCALE : R/W; bitpos: [10:3]; default: 0; - * Configures prescale value on possitive edge of CAP1. Prescale value = + * Configures prescale value on positive edge of CAP1. Prescale value = * PWM_CAP1_PRESCALE + 1 */ #define MCPWM_CAP0_PRESCALE 0x000000FFU @@ -2854,7 +2854,7 @@ extern "C" { #define MCPWM_CAP0_MODE_V 0x00000003U #define MCPWM_CAP0_MODE_S 1 /** MCPWM_CAP0_PRESCALE : R/W; bitpos: [10:3]; default: 0; - * Configures prescale value on possitive edge of CAP2. Prescale value = + * Configures prescale value on positive edge of CAP2. Prescale value = * PWM_CAP2_PRESCALE + 1 */ #define MCPWM_CAP0_PRESCALE 0x000000FFU diff --git a/components/soc/esp32p4/include/soc/mcpwm_struct.h b/components/soc/esp32p4/register/soc/mcpwm_struct.h similarity index 99% rename from components/soc/esp32p4/include/soc/mcpwm_struct.h rename to components/soc/esp32p4/register/soc/mcpwm_struct.h index 2b72d044e1a..71a4864a9c3 100644 --- a/components/soc/esp32p4/include/soc/mcpwm_struct.h +++ b/components/soc/esp32p4/register/soc/mcpwm_struct.h @@ -780,7 +780,7 @@ typedef union { */ uint32_t capn_mode:2; /** capn_prescale : R/W; bitpos: [10:3]; default: 0; - * Configures prescale value on possitive edge of CAPn. Prescale value = + * Configures prescale value on positive edge of CAPn. Prescale value = * PWM_CAPn_PRESCALE + 1 */ uint32_t capn_prescale:8; diff --git a/components/soc/esp32p4/include/soc/mipi_csi_bridge_reg.h b/components/soc/esp32p4/register/soc/mipi_csi_bridge_reg.h similarity index 100% rename from components/soc/esp32p4/include/soc/mipi_csi_bridge_reg.h rename to components/soc/esp32p4/register/soc/mipi_csi_bridge_reg.h diff --git a/components/soc/esp32p4/include/soc/mipi_csi_bridge_struct.h b/components/soc/esp32p4/register/soc/mipi_csi_bridge_struct.h similarity index 100% rename from components/soc/esp32p4/include/soc/mipi_csi_bridge_struct.h rename to components/soc/esp32p4/register/soc/mipi_csi_bridge_struct.h diff --git a/components/soc/esp32p4/include/soc/mipi_csi_host_reg.h b/components/soc/esp32p4/register/soc/mipi_csi_host_reg.h similarity index 100% rename from components/soc/esp32p4/include/soc/mipi_csi_host_reg.h rename to components/soc/esp32p4/register/soc/mipi_csi_host_reg.h diff --git a/components/soc/esp32p4/include/soc/mipi_csi_host_struct.h b/components/soc/esp32p4/register/soc/mipi_csi_host_struct.h similarity index 100% rename from components/soc/esp32p4/include/soc/mipi_csi_host_struct.h rename to components/soc/esp32p4/register/soc/mipi_csi_host_struct.h diff --git a/components/soc/esp32p4/include/soc/mipi_dsi_bridge_reg.h b/components/soc/esp32p4/register/soc/mipi_dsi_bridge_reg.h similarity index 100% rename from components/soc/esp32p4/include/soc/mipi_dsi_bridge_reg.h rename to components/soc/esp32p4/register/soc/mipi_dsi_bridge_reg.h diff --git a/components/soc/esp32p4/include/soc/mipi_dsi_bridge_struct.h b/components/soc/esp32p4/register/soc/mipi_dsi_bridge_struct.h similarity index 100% rename from components/soc/esp32p4/include/soc/mipi_dsi_bridge_struct.h rename to components/soc/esp32p4/register/soc/mipi_dsi_bridge_struct.h diff --git a/components/soc/esp32p4/include/soc/mipi_dsi_host_reg.h b/components/soc/esp32p4/register/soc/mipi_dsi_host_reg.h similarity index 100% rename from components/soc/esp32p4/include/soc/mipi_dsi_host_reg.h rename to components/soc/esp32p4/register/soc/mipi_dsi_host_reg.h diff --git a/components/soc/esp32p4/include/soc/mipi_dsi_host_struct.h b/components/soc/esp32p4/register/soc/mipi_dsi_host_struct.h similarity index 100% rename from components/soc/esp32p4/include/soc/mipi_dsi_host_struct.h rename to components/soc/esp32p4/register/soc/mipi_dsi_host_struct.h diff --git a/components/soc/esp32p4/include/soc/parl_io_reg.h b/components/soc/esp32p4/register/soc/parl_io_reg.h similarity index 98% rename from components/soc/esp32p4/include/soc/parl_io_reg.h rename to components/soc/esp32p4/register/soc/parl_io_reg.h index 74a528017d9..812470334d8 100644 --- a/components/soc/esp32p4/include/soc/parl_io_reg.h +++ b/components/soc/esp32p4/register/soc/parl_io_reg.h @@ -260,7 +260,7 @@ extern "C" { #define PARL_IO_TX_READY_S 31 /** PARL_IO_INT_ENA_REG register - * Parallel IO interrupt enable singal configuration register. + * Parallel IO interrupt enable signal configuration register. */ #define PARL_IO_INT_ENA_REG (DR_REG_PARL_IO_BASE + 0x28) /** PARL_IO_TX_FIFO_REMPTY_INT_ENA : R/W; bitpos: [0]; default: 0; @@ -286,7 +286,7 @@ extern "C" { #define PARL_IO_TX_EOF_INT_ENA_S 2 /** PARL_IO_INT_RAW_REG register - * Parallel IO interrupt raw singal status register. + * Parallel IO interrupt raw signal status register. */ #define PARL_IO_INT_RAW_REG (DR_REG_PARL_IO_BASE + 0x2c) /** PARL_IO_TX_FIFO_REMPTY_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; @@ -312,7 +312,7 @@ extern "C" { #define PARL_IO_TX_EOF_INT_RAW_S 2 /** PARL_IO_INT_ST_REG register - * Parallel IO interrupt singal status register. + * Parallel IO interrupt signal status register. */ #define PARL_IO_INT_ST_REG (DR_REG_PARL_IO_BASE + 0x30) /** PARL_IO_TX_FIFO_REMPTY_INT_ST : RO; bitpos: [0]; default: 0; @@ -338,7 +338,7 @@ extern "C" { #define PARL_IO_TX_EOF_INT_ST_S 2 /** PARL_IO_INT_CLR_REG register - * Parallel IO interrupt clear singal configuration register. + * Parallel IO interrupt clear signal configuration register. */ #define PARL_IO_INT_CLR_REG (DR_REG_PARL_IO_BASE + 0x34) /** PARL_IO_TX_FIFO_REMPTY_INT_CLR : WT; bitpos: [0]; default: 0; diff --git a/components/soc/esp32p4/include/soc/parl_io_struct.h b/components/soc/esp32p4/register/soc/parl_io_struct.h similarity index 98% rename from components/soc/esp32p4/include/soc/parl_io_struct.h rename to components/soc/esp32p4/register/soc/parl_io_struct.h index aea2cb383b8..7304e7be2c5 100644 --- a/components/soc/esp32p4/include/soc/parl_io_struct.h +++ b/components/soc/esp32p4/register/soc/parl_io_struct.h @@ -256,7 +256,7 @@ typedef union { /** Group: PARL_IO Interrupt Configuration and Status */ /** Type of int_ena register - * Parallel IO interrupt enable singal configuration register. + * Parallel IO interrupt enable signal configuration register. */ typedef union { struct { @@ -278,7 +278,7 @@ typedef union { } parl_io_int_ena_reg_t; /** Type of int_raw register - * Parallel IO interrupt raw singal status register. + * Parallel IO interrupt raw signal status register. */ typedef union { struct { @@ -300,7 +300,7 @@ typedef union { } parl_io_int_raw_reg_t; /** Type of int_st register - * Parallel IO interrupt singal status register. + * Parallel IO interrupt signal status register. */ typedef union { struct { @@ -322,7 +322,7 @@ typedef union { } parl_io_int_st_reg_t; /** Type of int_clr register - * Parallel IO interrupt clear singal configuration register. + * Parallel IO interrupt clear signal configuration register. */ typedef union { struct { diff --git a/components/soc/esp32p4/include/soc/pau_reg.h b/components/soc/esp32p4/register/soc/pau_reg.h similarity index 100% rename from components/soc/esp32p4/include/soc/pau_reg.h rename to components/soc/esp32p4/register/soc/pau_reg.h diff --git a/components/soc/esp32p4/include/soc/pau_struct.h b/components/soc/esp32p4/register/soc/pau_struct.h similarity index 100% rename from components/soc/esp32p4/include/soc/pau_struct.h rename to components/soc/esp32p4/register/soc/pau_struct.h diff --git a/components/soc/esp32p4/include/soc/pcnt_reg.h b/components/soc/esp32p4/register/soc/pcnt_reg.h similarity index 100% rename from components/soc/esp32p4/include/soc/pcnt_reg.h rename to components/soc/esp32p4/register/soc/pcnt_reg.h diff --git a/components/soc/esp32p4/include/soc/pcnt_struct.h b/components/soc/esp32p4/register/soc/pcnt_struct.h similarity index 100% rename from components/soc/esp32p4/include/soc/pcnt_struct.h rename to components/soc/esp32p4/register/soc/pcnt_struct.h diff --git a/components/soc/esp32p4/include/soc/pmu_reg.h b/components/soc/esp32p4/register/soc/pmu_reg.h similarity index 100% rename from components/soc/esp32p4/include/soc/pmu_reg.h rename to components/soc/esp32p4/register/soc/pmu_reg.h diff --git a/components/soc/esp32p4/include/soc/pmu_struct.h b/components/soc/esp32p4/register/soc/pmu_struct.h similarity index 100% rename from components/soc/esp32p4/include/soc/pmu_struct.h rename to components/soc/esp32p4/register/soc/pmu_struct.h diff --git a/components/soc/esp32p4/include/soc/ppa_reg.h b/components/soc/esp32p4/register/soc/ppa_reg.h similarity index 99% rename from components/soc/esp32p4/include/soc/ppa_reg.h rename to components/soc/esp32p4/register/soc/ppa_reg.h index 2b17794d771..a7a64aa44fb 100644 --- a/components/soc/esp32p4/include/soc/ppa_reg.h +++ b/components/soc/esp32p4/register/soc/ppa_reg.h @@ -645,21 +645,21 @@ extern "C" { */ #define PPA_CK_DEFAULT_REG (DR_REG_PPA_BASE + 0x60) /** PPA_COLORKEY_DEFAULT_B : R/W; bitpos: [7:0]; default: 0; - * default B channle value of color key + * default B channel value of color key */ #define PPA_COLORKEY_DEFAULT_B 0x000000FFU #define PPA_COLORKEY_DEFAULT_B_M (PPA_COLORKEY_DEFAULT_B_V << PPA_COLORKEY_DEFAULT_B_S) #define PPA_COLORKEY_DEFAULT_B_V 0x000000FFU #define PPA_COLORKEY_DEFAULT_B_S 0 /** PPA_COLORKEY_DEFAULT_G : R/W; bitpos: [15:8]; default: 0; - * default G channle value of color key + * default G channel value of color key */ #define PPA_COLORKEY_DEFAULT_G 0x000000FFU #define PPA_COLORKEY_DEFAULT_G_M (PPA_COLORKEY_DEFAULT_G_V << PPA_COLORKEY_DEFAULT_G_S) #define PPA_COLORKEY_DEFAULT_G_V 0x000000FFU #define PPA_COLORKEY_DEFAULT_G_S 8 /** PPA_COLORKEY_DEFAULT_R : R/W; bitpos: [23:16]; default: 0; - * default R channle value of color key + * default R channel value of color key */ #define PPA_COLORKEY_DEFAULT_R 0x000000FFU #define PPA_COLORKEY_DEFAULT_R_M (PPA_COLORKEY_DEFAULT_R_V << PPA_COLORKEY_DEFAULT_R_S) diff --git a/components/soc/esp32p4/include/soc/ppa_struct.h b/components/soc/esp32p4/register/soc/ppa_struct.h similarity index 99% rename from components/soc/esp32p4/include/soc/ppa_struct.h rename to components/soc/esp32p4/register/soc/ppa_struct.h index 5aa064b9014..abcc3dc0a7d 100644 --- a/components/soc/esp32p4/include/soc/ppa_struct.h +++ b/components/soc/esp32p4/register/soc/ppa_struct.h @@ -446,15 +446,15 @@ typedef union { typedef union { struct { /** colorkey_default_b : R/W; bitpos: [7:0]; default: 0; - * default B channle value of color key + * default B channel value of color key */ uint32_t colorkey_default_b:8; /** colorkey_default_g : R/W; bitpos: [15:8]; default: 0; - * default G channle value of color key + * default G channel value of color key */ uint32_t colorkey_default_g:8; /** colorkey_default_r : R/W; bitpos: [23:16]; default: 0; - * default R channle value of color key + * default R channel value of color key */ uint32_t colorkey_default_r:8; /** colorkey_fg_bg_reverse : R/W; bitpos: [24]; default: 0; diff --git a/components/soc/esp32p4/include/soc/pvt_reg.h b/components/soc/esp32p4/register/soc/pvt_reg.h similarity index 100% rename from components/soc/esp32p4/include/soc/pvt_reg.h rename to components/soc/esp32p4/register/soc/pvt_reg.h diff --git a/components/soc/esp32p4/include/soc/pvt_struct.h b/components/soc/esp32p4/register/soc/pvt_struct.h similarity index 100% rename from components/soc/esp32p4/include/soc/pvt_struct.h rename to components/soc/esp32p4/register/soc/pvt_struct.h diff --git a/components/soc/esp32p4/include/soc/reg_base.h b/components/soc/esp32p4/register/soc/reg_base.h similarity index 100% rename from components/soc/esp32p4/include/soc/reg_base.h rename to components/soc/esp32p4/register/soc/reg_base.h diff --git a/components/soc/esp32p4/include/soc/rmt_reg.h b/components/soc/esp32p4/register/soc/rmt_reg.h similarity index 100% rename from components/soc/esp32p4/include/soc/rmt_reg.h rename to components/soc/esp32p4/register/soc/rmt_reg.h diff --git a/components/soc/esp32p4/include/soc/rmt_struct.h b/components/soc/esp32p4/register/soc/rmt_struct.h similarity index 100% rename from components/soc/esp32p4/include/soc/rmt_struct.h rename to components/soc/esp32p4/register/soc/rmt_struct.h diff --git a/components/soc/esp32p4/include/soc/rsa_reg.h b/components/soc/esp32p4/register/soc/rsa_reg.h similarity index 100% rename from components/soc/esp32p4/include/soc/rsa_reg.h rename to components/soc/esp32p4/register/soc/rsa_reg.h diff --git a/components/soc/esp32p4/include/soc/rsa_struct.h b/components/soc/esp32p4/register/soc/rsa_struct.h similarity index 100% rename from components/soc/esp32p4/include/soc/rsa_struct.h rename to components/soc/esp32p4/register/soc/rsa_struct.h diff --git a/components/soc/esp32p4/include/soc/rtclockcali_reg.h b/components/soc/esp32p4/register/soc/rtclockcali_reg.h similarity index 98% rename from components/soc/esp32p4/include/soc/rtclockcali_reg.h rename to components/soc/esp32p4/register/soc/rtclockcali_reg.h index 329ef154c4d..d9794fe943b 100644 --- a/components/soc/esp32p4/include/soc/rtclockcali_reg.h +++ b/components/soc/esp32p4/register/soc/rtclockcali_reg.h @@ -267,21 +267,21 @@ extern "C" { #define RTCLOCKCALI_DREQ_UPDATE_V 0x00000001U #define RTCLOCKCALI_DREQ_UPDATE_S 0 /** RTCLOCKCALI_DREQ_INIT_32K : WT; bitpos: [2]; default: 0; - * Initialize the vaule of 32K OSC dfreq setting. + * Initialize the value of 32K OSC dfreq setting. */ #define RTCLOCKCALI_DREQ_INIT_32K (BIT(2)) #define RTCLOCKCALI_DREQ_INIT_32K_M (RTCLOCKCALI_DREQ_INIT_32K_V << RTCLOCKCALI_DREQ_INIT_32K_S) #define RTCLOCKCALI_DREQ_INIT_32K_V 0x00000001U #define RTCLOCKCALI_DREQ_INIT_32K_S 2 /** RTCLOCKCALI_DREQ_INIT_FOSC : WT; bitpos: [3]; default: 0; - * Initialize the vaule of FOSC dfreq setting. + * Initialize the value of FOSC dfreq setting. */ #define RTCLOCKCALI_DREQ_INIT_FOSC (BIT(3)) #define RTCLOCKCALI_DREQ_INIT_FOSC_M (RTCLOCKCALI_DREQ_INIT_FOSC_V << RTCLOCKCALI_DREQ_INIT_FOSC_S) #define RTCLOCKCALI_DREQ_INIT_FOSC_V 0x00000001U #define RTCLOCKCALI_DREQ_INIT_FOSC_S 3 /** RTCLOCKCALI_DREQ_INIT_SOSC : WT; bitpos: [4]; default: 0; - * Initialize the vaule of SOSC dfreq setting. + * Initialize the value of SOSC dfreq setting. */ #define RTCLOCKCALI_DREQ_INIT_SOSC (BIT(4)) #define RTCLOCKCALI_DREQ_INIT_SOSC_M (RTCLOCKCALI_DREQ_INIT_SOSC_V << RTCLOCKCALI_DREQ_INIT_SOSC_S) @@ -312,21 +312,21 @@ extern "C" { #define RTCLOCKCALI_SOSC_DFREQ_SEL_V 0x00000001U #define RTCLOCKCALI_SOSC_DFREQ_SEL_S 7 /** RTCLOCKCALI_FINE_STEP : R/W; bitpos: [15:8]; default: 1; - * Frequncy fine step. + * Frequency fine step. */ #define RTCLOCKCALI_FINE_STEP 0x000000FFU #define RTCLOCKCALI_FINE_STEP_M (RTCLOCKCALI_FINE_STEP_V << RTCLOCKCALI_FINE_STEP_S) #define RTCLOCKCALI_FINE_STEP_V 0x000000FFU #define RTCLOCKCALI_FINE_STEP_S 8 /** RTCLOCKCALI_COARSE_STEP_FAST : R/W; bitpos: [23:16]; default: 8; - * Frequncy coarse step,use to decrease calibration time. + * Frequency coarse step,use to decrease calibration time. */ #define RTCLOCKCALI_COARSE_STEP_FAST 0x000000FFU #define RTCLOCKCALI_COARSE_STEP_FAST_M (RTCLOCKCALI_COARSE_STEP_FAST_V << RTCLOCKCALI_COARSE_STEP_FAST_S) #define RTCLOCKCALI_COARSE_STEP_FAST_V 0x000000FFU #define RTCLOCKCALI_COARSE_STEP_FAST_S 16 /** RTCLOCKCALI_COARSE_STEP_SLOW : R/W; bitpos: [31:24]; default: 8; - * Frequncy coarse step,use to decrease calibration time. + * Frequency coarse step,use to decrease calibration time. */ #define RTCLOCKCALI_COARSE_STEP_SLOW 0x000000FFU #define RTCLOCKCALI_COARSE_STEP_SLOW_M (RTCLOCKCALI_COARSE_STEP_SLOW_V << RTCLOCKCALI_COARSE_STEP_SLOW_S) @@ -409,14 +409,14 @@ extern "C" { */ #define RTCLOCKCALI_INT_RAW_REG (DR_REG_RTCLOCKCALI_BASE + 0x38) /** RTCLOCKCALI_XTAL_TIMEOUT_INT_RAW : R/WTC/SS; bitpos: [29]; default: 0; - * Indicate the xtal timeout once happend . + * Indicate the xtal timeout once happened . */ #define RTCLOCKCALI_XTAL_TIMEOUT_INT_RAW (BIT(29)) #define RTCLOCKCALI_XTAL_TIMEOUT_INT_RAW_M (RTCLOCKCALI_XTAL_TIMEOUT_INT_RAW_V << RTCLOCKCALI_XTAL_TIMEOUT_INT_RAW_S) #define RTCLOCKCALI_XTAL_TIMEOUT_INT_RAW_V 0x00000001U #define RTCLOCKCALI_XTAL_TIMEOUT_INT_RAW_S 29 /** RTCLOCKCALI_CALI_TIMEOUT_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0; - * Indicate the calibration timeout once happend . + * Indicate the calibration timeout once happened . */ #define RTCLOCKCALI_CALI_TIMEOUT_INT_RAW (BIT(30)) #define RTCLOCKCALI_CALI_TIMEOUT_INT_RAW_M (RTCLOCKCALI_CALI_TIMEOUT_INT_RAW_V << RTCLOCKCALI_CALI_TIMEOUT_INT_RAW_S) diff --git a/components/soc/esp32p4/include/soc/rtclockcali_struct.h b/components/soc/esp32p4/register/soc/rtclockcali_struct.h similarity index 97% rename from components/soc/esp32p4/include/soc/rtclockcali_struct.h rename to components/soc/esp32p4/register/soc/rtclockcali_struct.h index 358ab21fc80..3898c762938 100644 --- a/components/soc/esp32p4/include/soc/rtclockcali_struct.h +++ b/components/soc/esp32p4/register/soc/rtclockcali_struct.h @@ -107,15 +107,15 @@ typedef union { uint32_t dreq_update:1; uint32_t reserved_1:1; /** dreq_init_32k : WT; bitpos: [2]; default: 0; - * Initialize the vaule of 32K OSC dfreq setting. + * Initialize the value of 32K OSC dfreq setting. */ uint32_t dreq_init_32k:1; /** dreq_init_fosc : WT; bitpos: [3]; default: 0; - * Initialize the vaule of FOSC dfreq setting. + * Initialize the value of FOSC dfreq setting. */ uint32_t dreq_init_fosc:1; /** dreq_init_sosc : WT; bitpos: [4]; default: 0; - * Initialize the vaule of SOSC dfreq setting. + * Initialize the value of SOSC dfreq setting. */ uint32_t dreq_init_sosc:1; /** rc32k_dfreq_sel : R/W; bitpos: [5]; default: 0; @@ -134,15 +134,15 @@ typedef union { */ uint32_t sosc_dfreq_sel:1; /** fine_step : R/W; bitpos: [15:8]; default: 1; - * Frequncy fine step. + * Frequency fine step. */ uint32_t fine_step:8; /** coarse_step_fast : R/W; bitpos: [23:16]; default: 8; - * Frequncy coarse step,use to decrease calibration time. + * Frequency coarse step,use to decrease calibration time. */ uint32_t coarse_step_fast:8; /** coarse_step_slow : R/W; bitpos: [31:24]; default: 8; - * Frequncy coarse step,use to decrease calibration time. + * Frequency coarse step,use to decrease calibration time. */ uint32_t coarse_step_slow:8; }; @@ -218,11 +218,11 @@ typedef union { struct { uint32_t reserved_0:29; /** xtal_timeout_int_raw : R/WTC/SS; bitpos: [29]; default: 0; - * Indicate the xtal timeout once happend . + * Indicate the xtal timeout once happened . */ uint32_t xtal_timeout_int_raw:1; /** cali_timeout_int_raw : R/WTC/SS; bitpos: [30]; default: 0; - * Indicate the calibration timeout once happend . + * Indicate the calibration timeout once happened . */ uint32_t cali_timeout_int_raw:1; /** cali_done_int_raw : R/WTC/SS; bitpos: [31]; default: 0; diff --git a/components/soc/esp32p4/include/soc/sdmmc_reg.h b/components/soc/esp32p4/register/soc/sdmmc_reg.h similarity index 99% rename from components/soc/esp32p4/include/soc/sdmmc_reg.h rename to components/soc/esp32p4/register/soc/sdmmc_reg.h index f8ba68d49fe..536a95e4ef9 100644 --- a/components/soc/esp32p4/include/soc/sdmmc_reg.h +++ b/components/soc/esp32p4/register/soc/sdmmc_reg.h @@ -893,7 +893,7 @@ extern "C" { #define SDHOST_BUS_TYPE_REG_V 0x00000001U #define SDHOST_BUS_TYPE_REG_S 6 /** SDHOST_DATA_WIDTH_REG : RO; bitpos: [9:7]; default: 1; - * Regisger data widht is 32. + * Regisger data width is 32. */ #define SDHOST_DATA_WIDTH_REG 0x00000007U #define SDHOST_DATA_WIDTH_REG_M (SDHOST_DATA_WIDTH_REG_V << SDHOST_DATA_WIDTH_REG_S) @@ -907,7 +907,7 @@ extern "C" { #define SDHOST_ADDR_WIDTH_REG_V 0x0000003FU #define SDHOST_ADDR_WIDTH_REG_S 10 /** SDHOST_DMA_WIDTH_REG : RO; bitpos: [20:18]; default: 1; - * DMA data witdth is 32. + * DMA data width is 32. */ #define SDHOST_DMA_WIDTH_REG 0x00000007U #define SDHOST_DMA_WIDTH_REG_M (SDHOST_DMA_WIDTH_REG_V << SDHOST_DMA_WIDTH_REG_S) @@ -921,7 +921,7 @@ extern "C" { #define SDHOST_RAM_INDISE_REG_V 0x00000001U #define SDHOST_RAM_INDISE_REG_S 21 /** SDHOST_HOLD_REG : RO; bitpos: [22]; default: 1; - * Have a hold regiser in data path . + * Have a hold register in data path . */ #define SDHOST_HOLD_REG (BIT(22)) #define SDHOST_HOLD_REG_M (SDHOST_HOLD_REG_V << SDHOST_HOLD_REG_S) @@ -940,9 +940,9 @@ extern "C" { */ #define SDHOST_UHS_REG (DR_REG_SDHOST_BASE + 0x74) /** SDHOST_DDR_REG : R/W; bitpos: [17:16]; default: 0; - * DDR mode selecton,1 bit for each card. - * 0-Non-DDR mdoe. - * 1-DDR mdoe. + * DDR mode selection,1 bit for each card. + * 0-Non-DDR mode. + * 1-DDR mode. */ #define SDHOST_DDR_REG 0x00000003U #define SDHOST_DDR_REG_M (SDHOST_DDR_REG_V << SDHOST_DDR_REG_S) diff --git a/components/soc/esp32p4/include/soc/sdmmc_struct.h b/components/soc/esp32p4/register/soc/sdmmc_struct.h similarity index 99% rename from components/soc/esp32p4/include/soc/sdmmc_struct.h rename to components/soc/esp32p4/register/soc/sdmmc_struct.h index f9b5a5ed77b..10318d6c9c7 100644 --- a/components/soc/esp32p4/include/soc/sdmmc_struct.h +++ b/components/soc/esp32p4/register/soc/sdmmc_struct.h @@ -870,7 +870,7 @@ typedef union { */ uint32_t bus_type_reg:1; /** data_width_reg : RO; bitpos: [9:7]; default: 1; - * Regisger data widht is 32. + * Regisger data width is 32. */ uint32_t data_width_reg:3; /** addr_width_reg : RO; bitpos: [15:10]; default: 19; @@ -879,7 +879,7 @@ typedef union { uint32_t addr_width_reg:6; uint32_t reserved_16:2; /** dma_width_reg : RO; bitpos: [20:18]; default: 1; - * DMA data witdth is 32. + * DMA data width is 32. */ uint32_t dma_width_reg:3; /** ram_indise_reg : RO; bitpos: [21]; default: 0; @@ -887,7 +887,7 @@ typedef union { */ uint32_t ram_indise_reg:1; /** hold_reg : RO; bitpos: [22]; default: 1; - * Have a hold regiser in data path . + * Have a hold register in data path . */ uint32_t hold_reg:1; uint32_t reserved_23:1; @@ -909,9 +909,9 @@ typedef union { struct { uint32_t reserved_0:16; /** ddr : R/W; bitpos: [17:16]; default: 0; - * DDR mode selecton,1 bit for each card. - * 0-Non-DDR mdoe. - * 1-DDR mdoe. + * DDR mode selection,1 bit for each card. + * 0-Non-DDR mode. + * 1-DDR mode. */ uint32_t ddr:2; uint32_t reserved_18:14; diff --git a/components/soc/esp32p4/include/soc/sha_reg.h b/components/soc/esp32p4/register/soc/sha_reg.h similarity index 98% rename from components/soc/esp32p4/include/soc/sha_reg.h rename to components/soc/esp32p4/register/soc/sha_reg.h index 888da914b30..40f4d53dfb0 100644 --- a/components/soc/esp32p4/include/soc/sha_reg.h +++ b/components/soc/esp32p4/register/soc/sha_reg.h @@ -156,7 +156,7 @@ extern "C" { #define SHA_DATE_S 0 /** SHA_H_MEM register - * Sha H memory which contains intermediate hash or finial hash. + * Sha H memory which contains intermediate hash or final hash. */ #define SHA_H_MEM (DR_REG_SHA_BASE + 0x40) #define SHA_H_MEM_SIZE_BYTES 64 diff --git a/components/soc/esp32p4/include/soc/sha_struct.h b/components/soc/esp32p4/register/soc/sha_struct.h similarity index 100% rename from components/soc/esp32p4/include/soc/sha_struct.h rename to components/soc/esp32p4/register/soc/sha_struct.h diff --git a/components/soc/esp32p4/include/soc/soc_etm_reg.h b/components/soc/esp32p4/register/soc/soc_etm_reg.h similarity index 100% rename from components/soc/esp32p4/include/soc/soc_etm_reg.h rename to components/soc/esp32p4/register/soc/soc_etm_reg.h diff --git a/components/soc/esp32p4/include/soc/soc_etm_struct.h b/components/soc/esp32p4/register/soc/soc_etm_struct.h similarity index 100% rename from components/soc/esp32p4/include/soc/soc_etm_struct.h rename to components/soc/esp32p4/register/soc/soc_etm_struct.h diff --git a/components/soc/esp32p4/include/soc/spi1_mem_c_reg.h b/components/soc/esp32p4/register/soc/spi1_mem_c_reg.h similarity index 99% rename from components/soc/esp32p4/include/soc/spi1_mem_c_reg.h rename to components/soc/esp32p4/register/soc/spi1_mem_c_reg.h index e3bfc692140..eab9fa8a7e3 100644 --- a/components/soc/esp32p4/include/soc/spi1_mem_c_reg.h +++ b/components/soc/esp32p4/register/soc/spi1_mem_c_reg.h @@ -321,7 +321,7 @@ extern "C" { /** SPI1_MEM_C_CLK_MODE : R/W; bitpos: [1:0]; default: 0; * SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed * one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: - * SPI clock is alwasy on. + * SPI clock is always on. */ #define SPI1_MEM_C_CLK_MODE 0x00000003U #define SPI1_MEM_C_CLK_MODE_M (SPI1_MEM_C_CLK_MODE_V << SPI1_MEM_C_CLK_MODE_S) @@ -1268,7 +1268,7 @@ extern "C" { #define SPI1_MEM_C_MST_ST_END_INT_RAW_S 4 /** SPI1_MEM_C_BROWN_OUT_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; * The raw bit for SPI1_MEM_C_BROWN_OUT_INT interrupt. 1: Triggered condition is that - * chip is loosing power and RTC module sends out brown out close flash request to + * chip is losing power and RTC module sends out brown out close flash request to * SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered * and MSPI returns to idle state. 0: Others. */ diff --git a/components/soc/esp32p4/include/soc/spi1_mem_c_struct.h b/components/soc/esp32p4/register/soc/spi1_mem_c_struct.h similarity index 99% rename from components/soc/esp32p4/include/soc/spi1_mem_c_struct.h rename to components/soc/esp32p4/register/soc/spi1_mem_c_struct.h index b78578c0825..6b08445b576 100644 --- a/components/soc/esp32p4/include/soc/spi1_mem_c_struct.h +++ b/components/soc/esp32p4/register/soc/spi1_mem_c_struct.h @@ -334,7 +334,7 @@ typedef union { /** clk_mode : R/W; bitpos: [1:0]; default: 0; * SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed * one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: - * SPI clock is alwasy on. + * SPI clock is always on. */ uint32_t clk_mode:2; /** cs_hold_dly_res : R/W; bitpos: [11:2]; default: 1023; @@ -912,7 +912,7 @@ typedef union { uint32_t reserved_5:5; /** brown_out_int_raw : R/WTC/SS; bitpos: [10]; default: 0; * The raw bit for SPI1_MEM_C_BROWN_OUT_INT interrupt. 1: Triggered condition is that - * chip is loosing power and RTC module sends out brown out close flash request to + * chip is losing power and RTC module sends out brown out close flash request to * SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered * and MSPI returns to idle state. 0: Others. */ diff --git a/components/soc/esp32p4/include/soc/spi1_mem_s_reg.h b/components/soc/esp32p4/register/soc/spi1_mem_s_reg.h similarity index 99% rename from components/soc/esp32p4/include/soc/spi1_mem_s_reg.h rename to components/soc/esp32p4/register/soc/spi1_mem_s_reg.h index 8aa91923ec7..9bc4517be9a 100644 --- a/components/soc/esp32p4/include/soc/spi1_mem_s_reg.h +++ b/components/soc/esp32p4/register/soc/spi1_mem_s_reg.h @@ -321,7 +321,7 @@ extern "C" { /** SPI1_MEM_S_CLK_MODE : R/W; bitpos: [1:0]; default: 0; * SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed * one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: - * SPI clock is alwasy on. + * SPI clock is always on. */ #define SPI1_MEM_S_CLK_MODE 0x00000003U #define SPI1_MEM_S_CLK_MODE_M (SPI1_MEM_S_CLK_MODE_V << SPI1_MEM_S_CLK_MODE_S) @@ -1268,7 +1268,7 @@ extern "C" { #define SPI1_MEM_S_MST_ST_END_INT_RAW_S 4 /** SPI1_MEM_S_BROWN_OUT_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; * The raw bit for SPI1_MEM_S_BROWN_OUT_INT interrupt. 1: Triggered condition is that - * chip is loosing power and RTC module sends out brown out close flash request to + * chip is losing power and RTC module sends out brown out close flash request to * SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered * and MSPI returns to idle state. 0: Others. */ diff --git a/components/soc/esp32p4/include/soc/spi1_mem_s_struct.h b/components/soc/esp32p4/register/soc/spi1_mem_s_struct.h similarity index 99% rename from components/soc/esp32p4/include/soc/spi1_mem_s_struct.h rename to components/soc/esp32p4/register/soc/spi1_mem_s_struct.h index c2bb46eb9d2..5cbe96076ba 100644 --- a/components/soc/esp32p4/include/soc/spi1_mem_s_struct.h +++ b/components/soc/esp32p4/register/soc/spi1_mem_s_struct.h @@ -334,7 +334,7 @@ typedef union { /** clk_mode : R/W; bitpos: [1:0]; default: 0; * SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed * one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: - * SPI clock is alwasy on. + * SPI clock is always on. */ uint32_t clk_mode:2; /** cs_hold_dly_res : R/W; bitpos: [11:2]; default: 1023; @@ -1123,7 +1123,7 @@ typedef union { uint32_t reserved_5:5; /** brown_out_int_raw : R/WTC/SS; bitpos: [10]; default: 0; * The raw bit for SPI1_MEM_S_BROWN_OUT_INT interrupt. 1: Triggered condition is that - * chip is loosing power and RTC module sends out brown out close flash request to + * chip is losing power and RTC module sends out brown out close flash request to * SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered * and MSPI returns to idle state. 0: Others. */ diff --git a/components/soc/esp32p4/include/soc/spi_mem_c_reg.h b/components/soc/esp32p4/register/soc/spi_mem_c_reg.h similarity index 99% rename from components/soc/esp32p4/include/soc/spi_mem_c_reg.h rename to components/soc/esp32p4/register/soc/spi_mem_c_reg.h index 89ff7ae9489..4b5c8c54e52 100644 --- a/components/soc/esp32p4/include/soc/spi_mem_c_reg.h +++ b/components/soc/esp32p4/register/soc/spi_mem_c_reg.h @@ -199,7 +199,7 @@ extern "C" { /** SPI_MEM_C_CLK_MODE : R/W; bitpos: [1:0]; default: 0; * SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed * one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: - * SPI clock is alwasy on. + * SPI clock is always on. */ #define SPI_MEM_C_CLK_MODE 0x00000003U #define SPI_MEM_C_CLK_MODE_M (SPI_MEM_C_CLK_MODE_V << SPI_MEM_C_CLK_MODE_S) @@ -2694,7 +2694,7 @@ extern "C" { */ #define SPI_MEM_C_DPA_CTRL_REG (DR_REG_FLASH_SPI0_BASE + 0x388) /** SPI_MEM_C_CRYPT_SECURITY_LEVEL : R/W; bitpos: [2:0]; default: 7; - * Set the security level of spi mem cryption. 0: Shut off cryption DPA funtion. 1-7: + * Set the security level of spi mem cryption. 0: Shut off cryption DPA function. 1-7: * The bigger the number is, the more secure the cryption is. (Note that the * performance of cryption will decrease together with this number increasing) */ diff --git a/components/soc/esp32p4/include/soc/spi_mem_c_struct.h b/components/soc/esp32p4/register/soc/spi_mem_c_struct.h similarity index 99% rename from components/soc/esp32p4/include/soc/spi_mem_c_struct.h rename to components/soc/esp32p4/register/soc/spi_mem_c_struct.h index c694be7e0a3..61abcf05911 100644 --- a/components/soc/esp32p4/include/soc/spi_mem_c_struct.h +++ b/components/soc/esp32p4/register/soc/spi_mem_c_struct.h @@ -167,7 +167,7 @@ typedef union { /** clk_mode : R/W; bitpos: [1:0]; default: 0; * SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed * one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: - * SPI clock is alwasy on. + * SPI clock is always on. */ uint32_t clk_mode:2; uint32_t reserved_2:19; @@ -1908,7 +1908,7 @@ typedef union { typedef union { struct { /** crypt_security_level : R/W; bitpos: [2:0]; default: 7; - * Set the security level of spi mem cryption. 0: Shut off cryption DPA funtion. 1-7: + * Set the security level of spi mem cryption. 0: Shut off cryption DPA function. 1-7: * The bigger the number is, the more secure the cryption is. (Note that the * performance of cryption will decrease together with this number increasing) */ diff --git a/components/soc/esp32p4/include/soc/spi_mem_s_reg.h b/components/soc/esp32p4/register/soc/spi_mem_s_reg.h similarity index 99% rename from components/soc/esp32p4/include/soc/spi_mem_s_reg.h rename to components/soc/esp32p4/register/soc/spi_mem_s_reg.h index 4e81aa49b4f..ec83145c771 100644 --- a/components/soc/esp32p4/include/soc/spi_mem_s_reg.h +++ b/components/soc/esp32p4/register/soc/spi_mem_s_reg.h @@ -199,7 +199,7 @@ extern "C" { /** SPI_MEM_S_CLK_MODE : R/W; bitpos: [1:0]; default: 0; * SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed * one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: - * SPI clock is alwasy on. + * SPI clock is always on. */ #define SPI_MEM_S_CLK_MODE 0x00000003U #define SPI_MEM_S_CLK_MODE_M (SPI_MEM_S_CLK_MODE_V << SPI_MEM_S_CLK_MODE_S) @@ -945,7 +945,7 @@ extern "C" { #define SPI_MEM_S_SCLKCNT_N_V 0x000000FFU #define SPI_MEM_S_SCLKCNT_N_S 16 /** SPI_MEM_S_SCLK_EQU_SYSCLK : R/W; bitpos: [31]; default: 0; - * For SPI0 external RAM interface, 1: spi_mem_clk is eqaul to system 0: spi_mem_clk + * For SPI0 external RAM interface, 1: spi_mem_clk is equal to system 0: spi_mem_clk * is divided from system clock. */ #define SPI_MEM_S_SCLK_EQU_SYSCLK (BIT(31)) @@ -3461,7 +3461,7 @@ extern "C" { */ #define SPI_MEM_S_DPA_CTRL_REG (DR_REG_PSRAM_MSPI0_BASE + 0x388) /** SPI_MEM_S_CRYPT_SECURITY_LEVEL : R/W; bitpos: [2:0]; default: 7; - * Set the security level of spi mem cryption. 0: Shut off cryption DPA funtion. 1-7: + * Set the security level of spi mem cryption. 0: Shut off cryption DPA function. 1-7: * The bigger the number is, the more secure the cryption is. (Note that the * performance of cryption will decrease together with this number increasing) */ diff --git a/components/soc/esp32p4/include/soc/spi_mem_s_struct.h b/components/soc/esp32p4/register/soc/spi_mem_s_struct.h similarity index 99% rename from components/soc/esp32p4/include/soc/spi_mem_s_struct.h rename to components/soc/esp32p4/register/soc/spi_mem_s_struct.h index 691b30c6d7d..4948325c47c 100644 --- a/components/soc/esp32p4/include/soc/spi_mem_s_struct.h +++ b/components/soc/esp32p4/register/soc/spi_mem_s_struct.h @@ -167,7 +167,7 @@ typedef union { /** mem_clk_mode : R/W; bitpos: [1:0]; default: 0; * SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed * one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: - * SPI clock is alwasy on. + * SPI clock is always on. */ uint32_t mem_clk_mode:2; uint32_t reserved_2:19; @@ -504,7 +504,7 @@ typedef union { uint32_t mem_sclkcnt_n:8; uint32_t reserved_24:7; /** mem_sclk_equ_sysclk : R/W; bitpos: [31]; default: 0; - * For SPI0 external RAM interface, 1: spi_mem_s_clk is eqaul to system 0: spi_mem_s_clk + * For SPI0 external RAM interface, 1: spi_mem_s_clk is equal to system 0: spi_mem_s_clk * is divided from system clock. */ uint32_t mem_sclk_equ_sysclk:1; @@ -2446,7 +2446,7 @@ typedef union { typedef union { struct { /** crypt_security_level : R/W; bitpos: [2:0]; default: 7; - * Set the security level of spi mem cryption. 0: Shut off cryption DPA funtion. 1-7: + * Set the security level of spi mem cryption. 0: Shut off cryption DPA function. 1-7: * The bigger the number is, the more secure the cryption is. (Note that the * performance of cryption will decrease together with this number increasing) */ diff --git a/components/soc/esp32p4/include/soc/spi_reg.h b/components/soc/esp32p4/register/soc/spi_reg.h similarity index 99% rename from components/soc/esp32p4/include/soc/spi_reg.h rename to components/soc/esp32p4/register/soc/spi_reg.h index 61a1858b096..ffce14740ee 100644 --- a/components/soc/esp32p4/include/soc/spi_reg.h +++ b/components/soc/esp32p4/register/soc/spi_reg.h @@ -225,7 +225,7 @@ extern "C" { #define SPI_CLKDIV_PRE_V 0x0000000FU #define SPI_CLKDIV_PRE_S 18 /** SPI_CLK_EQU_SYSCLK : R/W; bitpos: [31]; default: 1; - * In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system + * In the master mode 1: spi_clk is equal to system 0: spi_clk is divided from system * clock. Can be configured in CONF state. */ #define SPI_CLK_EQU_SYSCLK (BIT(31)) @@ -1978,7 +1978,7 @@ extern "C" { /** SPI_CLK_MODE : R/W; bitpos: [1:0]; default: 0; * SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed * one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: - * SPI clock is alwasy on. Can be configured in CONF state. + * SPI clock is always on. Can be configured in CONF state. */ #define SPI_CLK_MODE 0x00000003U #define SPI_CLK_MODE_M (SPI_CLK_MODE_V << SPI_CLK_MODE_S) diff --git a/components/soc/esp32p4/include/soc/spi_struct.h b/components/soc/esp32p4/register/soc/spi_struct.h similarity index 99% rename from components/soc/esp32p4/include/soc/spi_struct.h rename to components/soc/esp32p4/register/soc/spi_struct.h index 66929cd3a07..8d004e60e1d 100644 --- a/components/soc/esp32p4/include/soc/spi_struct.h +++ b/components/soc/esp32p4/register/soc/spi_struct.h @@ -511,7 +511,7 @@ typedef union { /** clk_mode : R/W; bitpos: [1:0]; default: 0; * SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed * one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: - * SPI clock is alwasy on. Can be configured in CONF state. + * SPI clock is always on. Can be configured in CONF state. */ uint32_t clk_mode:2; /** clk_mode_13 : R/W; bitpos: [2]; default: 0; @@ -629,7 +629,7 @@ typedef union { uint32_t clkdiv_pre:4; uint32_t reserved_22:9; /** clk_equ_sysclk : R/W; bitpos: [31]; default: 1; - * In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system + * In the master mode 1: spi_clk is equal to system 0: spi_clk is divided from system * clock. Can be configured in CONF state. */ uint32_t clk_equ_sysclk:1; diff --git a/components/soc/esp32p4/include/soc/systimer_reg.h b/components/soc/esp32p4/register/soc/systimer_reg.h similarity index 100% rename from components/soc/esp32p4/include/soc/systimer_reg.h rename to components/soc/esp32p4/register/soc/systimer_reg.h diff --git a/components/soc/esp32p4/include/soc/systimer_struct.h b/components/soc/esp32p4/register/soc/systimer_struct.h similarity index 100% rename from components/soc/esp32p4/include/soc/systimer_struct.h rename to components/soc/esp32p4/register/soc/systimer_struct.h diff --git a/components/soc/esp32p4/include/soc/tcm_monitor_reg.h b/components/soc/esp32p4/register/soc/tcm_monitor_reg.h similarity index 98% rename from components/soc/esp32p4/include/soc/tcm_monitor_reg.h rename to components/soc/esp32p4/register/soc/tcm_monitor_reg.h index d89fc3009cc..f04f761def9 100644 --- a/components/soc/esp32p4/include/soc/tcm_monitor_reg.h +++ b/components/soc/esp32p4/register/soc/tcm_monitor_reg.h @@ -12,7 +12,7 @@ extern "C" { #endif /** MEM_MONITOR_LOG_SETTING_REG register - * log config regsiter + * log config register */ #define MEM_MONITOR_LOG_SETTING_REG (DR_REG_MEM_MONITOR_BASE + 0x0) /** MEM_MONITOR_LOG_MODE : R/W; bitpos: [3:0]; default: 0; @@ -53,7 +53,7 @@ extern "C" { #define MEM_MONITOR_LOG_DMA_1_ENA_S 24 /** MEM_MONITOR_LOG_SETTING1_REG register - * log config regsiter + * log config register */ #define MEM_MONITOR_LOG_SETTING1_REG (DR_REG_MEM_MONITOR_BASE + 0x4) /** MEM_MONITOR_LOG_DMA_2_ENA : R/W; bitpos: [7:0]; default: 0; @@ -72,7 +72,7 @@ extern "C" { #define MEM_MONITOR_LOG_DMA_3_ENA_S 8 /** MEM_MONITOR_LOG_CHECK_DATA_REG register - * check data regsiter + * check data register */ #define MEM_MONITOR_LOG_CHECK_DATA_REG (DR_REG_MEM_MONITOR_BASE + 0x8) /** MEM_MONITOR_LOG_CHECK_DATA : R/W; bitpos: [31:0]; default: 0; @@ -97,7 +97,7 @@ extern "C" { #define MEM_MONITOR_LOG_DATA_MASK_S 0 /** MEM_MONITOR_LOG_MIN_REG register - * log boundary regsiter + * log boundary register */ #define MEM_MONITOR_LOG_MIN_REG (DR_REG_MEM_MONITOR_BASE + 0x10) /** MEM_MONITOR_LOG_MIN : R/W; bitpos: [31:0]; default: 0; @@ -109,7 +109,7 @@ extern "C" { #define MEM_MONITOR_LOG_MIN_S 0 /** MEM_MONITOR_LOG_MAX_REG register - * log boundary regsiter + * log boundary register */ #define MEM_MONITOR_LOG_MAX_REG (DR_REG_MEM_MONITOR_BASE + 0x14) /** MEM_MONITOR_LOG_MAX : R/W; bitpos: [31:0]; default: 0; diff --git a/components/soc/esp32p4/include/soc/tcm_monitor_struct.h b/components/soc/esp32p4/register/soc/tcm_monitor_struct.h similarity index 98% rename from components/soc/esp32p4/include/soc/tcm_monitor_struct.h rename to components/soc/esp32p4/register/soc/tcm_monitor_struct.h index c88691215af..e3e1abf3761 100644 --- a/components/soc/esp32p4/include/soc/tcm_monitor_struct.h +++ b/components/soc/esp32p4/register/soc/tcm_monitor_struct.h @@ -12,7 +12,7 @@ extern "C" { /** Group: configuration registers */ /** Type of log_setting register - * log config regsiter + * log config register */ typedef union { struct { @@ -43,7 +43,7 @@ typedef union { } mem_monitor_log_setting_reg_t; /** Type of log_setting1 register - * log config regsiter + * log config register */ typedef union { struct { @@ -61,7 +61,7 @@ typedef union { } mem_monitor_log_setting1_reg_t; /** Type of log_check_data register - * check data regsiter + * check data register */ typedef union { struct { @@ -89,7 +89,7 @@ typedef union { } mem_monitor_log_data_mask_reg_t; /** Type of log_min register - * log boundary regsiter + * log boundary register */ typedef union { struct { @@ -102,7 +102,7 @@ typedef union { } mem_monitor_log_min_reg_t; /** Type of log_max register - * log boundary regsiter + * log boundary register */ typedef union { struct { diff --git a/components/soc/esp32p4/include/soc/timer_group_reg.h b/components/soc/esp32p4/register/soc/timer_group_reg.h similarity index 100% rename from components/soc/esp32p4/include/soc/timer_group_reg.h rename to components/soc/esp32p4/register/soc/timer_group_reg.h diff --git a/components/soc/esp32p4/include/soc/timer_group_struct.h b/components/soc/esp32p4/register/soc/timer_group_struct.h similarity index 100% rename from components/soc/esp32p4/include/soc/timer_group_struct.h rename to components/soc/esp32p4/register/soc/timer_group_struct.h diff --git a/components/soc/esp32p4/include/soc/touch_reg.h b/components/soc/esp32p4/register/soc/touch_reg.h similarity index 100% rename from components/soc/esp32p4/include/soc/touch_reg.h rename to components/soc/esp32p4/register/soc/touch_reg.h diff --git a/components/soc/esp32p4/include/soc/touch_struct.h b/components/soc/esp32p4/register/soc/touch_struct.h similarity index 100% rename from components/soc/esp32p4/include/soc/touch_struct.h rename to components/soc/esp32p4/register/soc/touch_struct.h diff --git a/components/soc/esp32p4/include/soc/trace_reg.h b/components/soc/esp32p4/register/soc/trace_reg.h similarity index 100% rename from components/soc/esp32p4/include/soc/trace_reg.h rename to components/soc/esp32p4/register/soc/trace_reg.h diff --git a/components/soc/esp32p4/include/soc/trace_struct.h b/components/soc/esp32p4/register/soc/trace_struct.h similarity index 100% rename from components/soc/esp32p4/include/soc/trace_struct.h rename to components/soc/esp32p4/register/soc/trace_struct.h diff --git a/components/soc/esp32p4/include/soc/tsens_reg.h b/components/soc/esp32p4/register/soc/tsens_reg.h similarity index 100% rename from components/soc/esp32p4/include/soc/tsens_reg.h rename to components/soc/esp32p4/register/soc/tsens_reg.h diff --git a/components/soc/esp32p4/include/soc/tsens_struct.h b/components/soc/esp32p4/register/soc/tsens_struct.h similarity index 100% rename from components/soc/esp32p4/include/soc/tsens_struct.h rename to components/soc/esp32p4/register/soc/tsens_struct.h diff --git a/components/soc/esp32p4/include/soc/twai_reg.h b/components/soc/esp32p4/register/soc/twai_reg.h similarity index 100% rename from components/soc/esp32p4/include/soc/twai_reg.h rename to components/soc/esp32p4/register/soc/twai_reg.h diff --git a/components/soc/esp32p4/include/soc/twai_struct.h b/components/soc/esp32p4/register/soc/twai_struct.h similarity index 100% rename from components/soc/esp32p4/include/soc/twai_struct.h rename to components/soc/esp32p4/register/soc/twai_struct.h diff --git a/components/soc/esp32p4/include/soc/uart_reg.h b/components/soc/esp32p4/register/soc/uart_reg.h similarity index 99% rename from components/soc/esp32p4/include/soc/uart_reg.h rename to components/soc/esp32p4/register/soc/uart_reg.h index fc3c662721e..014f8eaed29 100644 --- a/components/soc/esp32p4/include/soc/uart_reg.h +++ b/components/soc/esp32p4/register/soc/uart_reg.h @@ -100,7 +100,7 @@ extern "C" { #define UART_RXFIFO_TOUT_INT_RAW_V 0x00000001U #define UART_RXFIFO_TOUT_INT_RAW_S 8 /** UART_SW_XON_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; - * This interrupt raw bit turns to high level when receiver recevies Xon char when + * This interrupt raw bit turns to high level when receiver receives Xon char when * uart_sw_flow_con_en is set to 1. */ #define UART_SW_XON_INT_RAW (BIT(9)) @@ -285,7 +285,7 @@ extern "C" { #define UART_TX_BRK_DONE_INT_ST_V 0x00000001U #define UART_TX_BRK_DONE_INT_ST_S 12 /** UART_TX_BRK_IDLE_DONE_INT_ST : RO; bitpos: [13]; default: 0; - * This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena + * This is the status bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena * is set to 1. */ #define UART_TX_BRK_IDLE_DONE_INT_ST (BIT(13)) @@ -760,7 +760,7 @@ extern "C" { #define UART_STOP_BIT_NUM_V 0x00000003U #define UART_STOP_BIT_NUM_S 4 /** UART_TXD_BRK : R/W; bitpos: [6]; default: 0; - * Set this bit to enbale transmitter to send NULL when the process of sending data + * Set this bit to enable transmitter to send NULL when the process of sending data * is done. */ #define UART_TXD_BRK (BIT(6)) @@ -1326,7 +1326,7 @@ extern "C" { */ #define UART_TOUT_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x64) /** UART_RX_TOUT_EN : R/W; bitpos: [0]; default: 0; - * This is the enble bit for uart receiver's timeout function. + * This is the enable bit for uart receiver's timeout function. */ #define UART_RX_TOUT_EN (BIT(0)) #define UART_RX_TOUT_EN_M (UART_RX_TOUT_EN_V << UART_RX_TOUT_EN_S) @@ -1450,7 +1450,7 @@ extern "C" { */ #define UART_HIGHPULSE_REG(i) (REG_UART_BASE(i) + 0x80) /** UART_HIGHPULSE_MIN_CNT : RO; bitpos: [11:0]; default: 4095; - * This register stores the value of the maxinum duration time for the high level + * This register stores the value of the maximum duration time for the high level * pulse. It is used in baud rate-detect process. */ #define UART_HIGHPULSE_MIN_CNT 0x00000FFFU diff --git a/components/soc/esp32p4/include/soc/uart_struct.h b/components/soc/esp32p4/register/soc/uart_struct.h similarity index 99% rename from components/soc/esp32p4/include/soc/uart_struct.h rename to components/soc/esp32p4/register/soc/uart_struct.h index b23e6db9305..b750ef943af 100644 --- a/components/soc/esp32p4/include/soc/uart_struct.h +++ b/components/soc/esp32p4/register/soc/uart_struct.h @@ -49,7 +49,7 @@ typedef union { typedef union { struct { /** rx_tout_en : R/W; bitpos: [0]; default: 0; - * This is the enble bit for uart receiver's timeout function. + * This is the enable bit for uart receiver's timeout function. */ uint32_t rx_tout_en:1; /** rx_tout_flow_dis : R/W; bitpos: [1]; default: 0; @@ -120,7 +120,7 @@ typedef union { */ uint32_t rxfifo_tout_int_raw:1; /** sw_xon_int_raw : R/WTC/SS; bitpos: [9]; default: 0; - * This interrupt raw bit turns to high level when receiver recevies Xon char when + * This interrupt raw bit turns to high level when receiver receives Xon char when * uart_sw_flow_con_en is set to 1. */ uint32_t sw_xon_int_raw:1; @@ -238,7 +238,7 @@ typedef union { */ uint32_t tx_brk_done_int_st:1; /** tx_brk_idle_done_int_st : RO; bitpos: [13]; default: 0; - * This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena + * This is the status bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena * is set to 1. */ uint32_t tx_brk_idle_done_int_st:1; @@ -515,7 +515,7 @@ typedef union { */ uint32_t stop_bit_num:2; /** txd_brk : R/W; bitpos: [6]; default: 0; - * Set this bit to enbale transmitter to send NULL when the process of sending data + * Set this bit to enable transmitter to send NULL when the process of sending data * is done. */ uint32_t txd_brk:1; @@ -1160,7 +1160,7 @@ typedef union { typedef union { struct { /** highpulse_min_cnt : RO; bitpos: [11:0]; default: 4095; - * This register stores the value of the maxinum duration time for the high level + * This register stores the value of the maximum duration time for the high level * pulse. It is used in baud rate-detect process. */ uint32_t highpulse_min_cnt:12; diff --git a/components/soc/esp32p4/include/soc/uhci_reg.h b/components/soc/esp32p4/register/soc/uhci_reg.h similarity index 100% rename from components/soc/esp32p4/include/soc/uhci_reg.h rename to components/soc/esp32p4/register/soc/uhci_reg.h diff --git a/components/soc/esp32p4/include/soc/uhci_struct.h b/components/soc/esp32p4/register/soc/uhci_struct.h similarity index 100% rename from components/soc/esp32p4/include/soc/uhci_struct.h rename to components/soc/esp32p4/register/soc/uhci_struct.h diff --git a/components/soc/esp32p4/include/soc/usb_serial_jtag_reg.h b/components/soc/esp32p4/register/soc/usb_serial_jtag_reg.h similarity index 99% rename from components/soc/esp32p4/include/soc/usb_serial_jtag_reg.h rename to components/soc/esp32p4/register/soc/usb_serial_jtag_reg.h index 478c734ea80..6de18f3a76f 100644 --- a/components/soc/esp32p4/include/soc/usb_serial_jtag_reg.h +++ b/components/soc/esp32p4/register/soc/usb_serial_jtag_reg.h @@ -1140,7 +1140,7 @@ extern "C" { #define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_V 0x00000001U #define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_S 3 /** USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY : RO; bitpos: [4]; default: 1; - * CDC_ACM OUTOUT async FIFO empty signal in read clock domain. + * CDC_ACM OUTPUT async FIFO empty signal in read clock domain. */ #define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY (BIT(4)) #define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_M (USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_V << USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_S) diff --git a/components/soc/esp32p4/include/soc/usb_serial_jtag_struct.h b/components/soc/esp32p4/register/soc/usb_serial_jtag_struct.h similarity index 100% rename from components/soc/esp32p4/include/soc/usb_serial_jtag_struct.h rename to components/soc/esp32p4/register/soc/usb_serial_jtag_struct.h diff --git a/components/soc/esp32p4/include/soc/usb_wrap_reg.h b/components/soc/esp32p4/register/soc/usb_wrap_reg.h similarity index 100% rename from components/soc/esp32p4/include/soc/usb_wrap_reg.h rename to components/soc/esp32p4/register/soc/usb_wrap_reg.h diff --git a/components/soc/esp32p4/include/soc/usb_wrap_struct.h b/components/soc/esp32p4/register/soc/usb_wrap_struct.h similarity index 100% rename from components/soc/esp32p4/include/soc/usb_wrap_struct.h rename to components/soc/esp32p4/register/soc/usb_wrap_struct.h From f0c34575d147263aee9164f4274a55e4bfba6251 Mon Sep 17 00:00:00 2001 From: laokaiyao Date: Fri, 6 Sep 2024 17:22:19 +0800 Subject: [PATCH 118/472] refactor(soc): sort esp32c6 soc headers --- .../soc/esp32c6/include/soc/dport_access.h | 1 - components/soc/esp32c6/include/soc/soc.h | 2 +- .../soc/esp32c6/include/soc/system_reg.h | 2 +- components/soc/esp32c6/register/soc/.gitkeep | 0 .../{include => register}/soc/aes_reg.h | 0 .../{include => register}/soc/aes_struct.h | 0 .../soc/apb_saradc_reg.h | 0 .../soc/apb_saradc_struct.h | 0 .../soc/assist_debug_reg.h | 12 +- .../soc/assist_debug_struct.h | 18 +- .../{include => register}/soc/clint_reg.h | 0 .../{include => register}/soc/ds_reg.h | 0 .../{include => register}/soc/ds_struct.h | 0 .../{include => register}/soc/ecc_mult_reg.h | 2 +- .../soc/ecc_mult_struct.h | 2 +- .../{include => register}/soc/efuse_reg.h | 8 +- .../{include => register}/soc/efuse_struct.h | 6 +- .../{include => register}/soc/extmem_reg.h | 36 +-- .../{include => register}/soc/extmem_struct.h | 8 +- .../{include => register}/soc/gdma_reg.h | 0 .../{include => register}/soc/gdma_struct.h | 0 .../{include => register}/soc/gpio_ext_reg.h | 0 .../soc/gpio_ext_struct.h | 0 .../{include => register}/soc/gpio_reg.h | 0 .../{include => register}/soc/gpio_struct.h | 0 .../soc/hardware_lock_reg.h | 10 +- .../soc/hardware_lock_struct.h | 10 +- .../{include => register}/soc/hinf_reg.h | 0 .../{include => register}/soc/hinf_struct.h | 0 .../{include => register}/soc/hmac_reg.h | 0 .../{include => register}/soc/hmac_struct.h | 0 .../{include => register}/soc/host_reg.h | 0 .../{include => register}/soc/host_struct.h | 0 .../{include => register}/soc/hp_apm_reg.h | 0 .../{include => register}/soc/hp_apm_struct.h | 0 .../{include => register}/soc/hp_system_reg.h | 2 +- .../soc/hp_system_struct.h | 2 +- .../soc/i2c_ana_mst_reg.h | 0 .../{include => register}/soc/i2c_reg.h | 0 .../{include => register}/soc/i2c_struct.h | 0 .../{include => register}/soc/i2s_reg.h | 2 +- .../{include => register}/soc/i2s_struct.h | 2 +- .../soc/ieee802154_reg.h | 0 .../soc/ieee802154_struct.h | 0 .../soc/interrupt_matrix_reg.h | 0 .../soc/interrupt_matrix_struct.h | 0 .../{include => register}/soc/intpri_reg.h | 0 .../{include => register}/soc/intpri_struct.h | 0 .../{include => register}/soc/io_mux_reg.h | 2 +- .../{include => register}/soc/ledc_reg.h | 0 .../{include => register}/soc/ledc_struct.h | 0 .../soc/lp_analog_peri_reg.h | 0 .../soc/lp_analog_peri_struct.h | 0 .../{include => register}/soc/lp_aon_reg.h | 0 .../{include => register}/soc/lp_aon_struct.h | 0 .../{include => register}/soc/lp_apm0_reg.h | 0 .../soc/lp_apm0_struct.h | 0 .../{include => register}/soc/lp_apm_reg.h | 0 .../{include => register}/soc/lp_apm_struct.h | 0 .../{include => register}/soc/lp_clkrst_reg.h | 0 .../soc/lp_clkrst_struct.h | 0 .../soc/lp_i2c_ana_mst_reg.h | 0 .../soc/lp_i2c_ana_mst_struct.h | 0 .../{include => register}/soc/lp_i2c_reg.h | 0 .../{include => register}/soc/lp_i2c_struct.h | 0 .../{include => register}/soc/lp_io_reg.h | 0 .../{include => register}/soc/lp_io_struct.h | 0 .../{include => register}/soc/lp_tee_reg.h | 0 .../{include => register}/soc/lp_tee_struct.h | 0 .../{include => register}/soc/lp_timer_reg.h | 0 .../soc/lp_timer_struct.h | 0 .../{include => register}/soc/lp_uart_reg.h | 8 +- .../soc/lp_uart_struct.h | 10 +- .../{include => register}/soc/lp_wdt_reg.h | 0 .../{include => register}/soc/lp_wdt_struct.h | 0 .../{include => register}/soc/lpperi_reg.h | 0 .../{include => register}/soc/lpperi_struct.h | 0 .../{include => register}/soc/mcpwm_reg.h | 12 +- .../{include => register}/soc/mcpwm_struct.h | 4 +- .../soc/mem_monitor_reg.h | 8 +- .../soc/mem_monitor_struct.h | 8 +- .../{include => register}/soc/otp_debug_reg.h | 260 ++++++++--------- .../soc/otp_debug_struct.h | 262 +++++++++--------- .../{include => register}/soc/parl_io_reg.h | 10 +- .../soc/parl_io_struct.h | 10 +- .../{include => register}/soc/pau_reg.h | 0 .../{include => register}/soc/pau_struct.h | 0 .../{include => register}/soc/pcnt_reg.h | 0 .../{include => register}/soc/pcnt_struct.h | 0 .../{include => register}/soc/pcr_reg.h | 54 ++-- .../{include => register}/soc/pcr_struct.h | 54 ++-- .../{include => register}/soc/plic_reg.h | 0 .../{include => register}/soc/pmu_reg.h | 0 .../{include => register}/soc/pmu_struct.h | 2 +- .../{include => register}/soc/reg_base.h | 0 .../{include => register}/soc/rmt_reg.h | 0 .../{include => register}/soc/rmt_struct.h | 0 .../{include => register}/soc/rsa_reg.h | 0 .../{include => register}/soc/rsa_struct.h | 0 .../{include => register}/soc/sha_reg.h | 2 +- .../{include => register}/soc/sha_struct.h | 0 .../{include => register}/soc/slc_reg.h | 0 .../{include => register}/soc/slc_struct.h | 0 .../{include => register}/soc/soc_etm_reg.h | 0 .../soc/soc_etm_struct.h | 0 .../{include => register}/soc/spi_mem_reg.h | 52 ++-- .../soc/spi_mem_struct.h | 8 +- .../{include => register}/soc/spi_reg.h | 4 +- .../{include => register}/soc/spi_struct.h | 4 +- .../{include => register}/soc/systimer_reg.h | 0 .../soc/systimer_struct.h | 0 .../{include => register}/soc/tee_reg.h | 0 .../{include => register}/soc/tee_struct.h | 0 .../soc/timer_group_reg.h | 0 .../soc/timer_group_struct.h | 0 .../{include => register}/soc/trace_reg.h | 2 +- .../{include => register}/soc/trace_struct.h | 2 +- .../{include => register}/soc/twai_reg.h | 0 .../{include => register}/soc/twai_struct.h | 0 .../{include => register}/soc/uart_reg.h | 10 +- .../{include => register}/soc/uart_struct.h | 10 +- .../{include => register}/soc/uhci_reg.h | 0 .../{include => register}/soc/uhci_struct.h | 0 .../soc/usb_serial_jtag_reg.h | 2 +- .../soc/usb_serial_jtag_struct.h | 0 .../{include => register}/soc/xts_aes_reg.h | 6 +- 126 files changed, 465 insertions(+), 466 deletions(-) delete mode 100644 components/soc/esp32c6/register/soc/.gitkeep rename components/soc/esp32c6/{include => register}/soc/aes_reg.h (100%) rename components/soc/esp32c6/{include => register}/soc/aes_struct.h (100%) rename components/soc/esp32c6/{include => register}/soc/apb_saradc_reg.h (100%) rename components/soc/esp32c6/{include => register}/soc/apb_saradc_struct.h (100%) rename components/soc/esp32c6/{include => register}/soc/assist_debug_reg.h (99%) rename components/soc/esp32c6/{include => register}/soc/assist_debug_struct.h (98%) rename components/soc/esp32c6/{include => register}/soc/clint_reg.h (100%) rename components/soc/esp32c6/{include => register}/soc/ds_reg.h (100%) rename components/soc/esp32c6/{include => register}/soc/ds_struct.h (100%) rename components/soc/esp32c6/{include => register}/soc/ecc_mult_reg.h (98%) rename components/soc/esp32c6/{include => register}/soc/ecc_mult_struct.h (97%) rename components/soc/esp32c6/{include => register}/soc/efuse_reg.h (99%) rename components/soc/esp32c6/{include => register}/soc/efuse_struct.h (99%) rename components/soc/esp32c6/{include => register}/soc/extmem_reg.h (98%) rename components/soc/esp32c6/{include => register}/soc/extmem_struct.h (99%) rename components/soc/esp32c6/{include => register}/soc/gdma_reg.h (100%) rename components/soc/esp32c6/{include => register}/soc/gdma_struct.h (100%) rename components/soc/esp32c6/{include => register}/soc/gpio_ext_reg.h (100%) rename components/soc/esp32c6/{include => register}/soc/gpio_ext_struct.h (100%) rename components/soc/esp32c6/{include => register}/soc/gpio_reg.h (100%) rename components/soc/esp32c6/{include => register}/soc/gpio_struct.h (100%) rename components/soc/esp32c6/{include => register}/soc/hardware_lock_reg.h (93%) rename components/soc/esp32c6/{include => register}/soc/hardware_lock_struct.h (92%) rename components/soc/esp32c6/{include => register}/soc/hinf_reg.h (100%) rename components/soc/esp32c6/{include => register}/soc/hinf_struct.h (100%) rename components/soc/esp32c6/{include => register}/soc/hmac_reg.h (100%) rename components/soc/esp32c6/{include => register}/soc/hmac_struct.h (100%) rename components/soc/esp32c6/{include => register}/soc/host_reg.h (100%) rename components/soc/esp32c6/{include => register}/soc/host_struct.h (100%) rename components/soc/esp32c6/{include => register}/soc/hp_apm_reg.h (100%) rename components/soc/esp32c6/{include => register}/soc/hp_apm_struct.h (100%) rename components/soc/esp32c6/{include => register}/soc/hp_system_reg.h (99%) rename components/soc/esp32c6/{include => register}/soc/hp_system_struct.h (99%) rename components/soc/esp32c6/{include => register}/soc/i2c_ana_mst_reg.h (100%) rename components/soc/esp32c6/{include => register}/soc/i2c_reg.h (100%) rename components/soc/esp32c6/{include => register}/soc/i2c_struct.h (100%) rename components/soc/esp32c6/{include => register}/soc/i2s_reg.h (99%) rename components/soc/esp32c6/{include => register}/soc/i2s_struct.h (99%) rename components/soc/esp32c6/{include => register}/soc/ieee802154_reg.h (100%) rename components/soc/esp32c6/{include => register}/soc/ieee802154_struct.h (100%) rename components/soc/esp32c6/{include => register}/soc/interrupt_matrix_reg.h (100%) rename components/soc/esp32c6/{include => register}/soc/interrupt_matrix_struct.h (100%) rename components/soc/esp32c6/{include => register}/soc/intpri_reg.h (100%) rename components/soc/esp32c6/{include => register}/soc/intpri_struct.h (100%) rename components/soc/esp32c6/{include => register}/soc/io_mux_reg.h (99%) rename components/soc/esp32c6/{include => register}/soc/ledc_reg.h (100%) rename components/soc/esp32c6/{include => register}/soc/ledc_struct.h (100%) rename components/soc/esp32c6/{include => register}/soc/lp_analog_peri_reg.h (100%) rename components/soc/esp32c6/{include => register}/soc/lp_analog_peri_struct.h (100%) rename components/soc/esp32c6/{include => register}/soc/lp_aon_reg.h (100%) rename components/soc/esp32c6/{include => register}/soc/lp_aon_struct.h (100%) rename components/soc/esp32c6/{include => register}/soc/lp_apm0_reg.h (100%) rename components/soc/esp32c6/{include => register}/soc/lp_apm0_struct.h (100%) rename components/soc/esp32c6/{include => register}/soc/lp_apm_reg.h (100%) rename components/soc/esp32c6/{include => register}/soc/lp_apm_struct.h (100%) rename components/soc/esp32c6/{include => register}/soc/lp_clkrst_reg.h (100%) rename components/soc/esp32c6/{include => register}/soc/lp_clkrst_struct.h (100%) rename components/soc/esp32c6/{include => register}/soc/lp_i2c_ana_mst_reg.h (100%) rename components/soc/esp32c6/{include => register}/soc/lp_i2c_ana_mst_struct.h (100%) rename components/soc/esp32c6/{include => register}/soc/lp_i2c_reg.h (100%) rename components/soc/esp32c6/{include => register}/soc/lp_i2c_struct.h (100%) rename components/soc/esp32c6/{include => register}/soc/lp_io_reg.h (100%) rename components/soc/esp32c6/{include => register}/soc/lp_io_struct.h (100%) rename components/soc/esp32c6/{include => register}/soc/lp_tee_reg.h (100%) rename components/soc/esp32c6/{include => register}/soc/lp_tee_struct.h (100%) rename components/soc/esp32c6/{include => register}/soc/lp_timer_reg.h (100%) rename components/soc/esp32c6/{include => register}/soc/lp_timer_struct.h (100%) rename components/soc/esp32c6/{include => register}/soc/lp_uart_reg.h (99%) rename components/soc/esp32c6/{include => register}/soc/lp_uart_struct.h (99%) rename components/soc/esp32c6/{include => register}/soc/lp_wdt_reg.h (100%) rename components/soc/esp32c6/{include => register}/soc/lp_wdt_struct.h (100%) rename components/soc/esp32c6/{include => register}/soc/lpperi_reg.h (100%) rename components/soc/esp32c6/{include => register}/soc/lpperi_struct.h (100%) rename components/soc/esp32c6/{include => register}/soc/mcpwm_reg.h (99%) rename components/soc/esp32c6/{include => register}/soc/mcpwm_struct.h (99%) rename components/soc/esp32c6/{include => register}/soc/mem_monitor_reg.h (98%) rename components/soc/esp32c6/{include => register}/soc/mem_monitor_struct.h (98%) rename components/soc/esp32c6/{include => register}/soc/otp_debug_reg.h (91%) rename components/soc/esp32c6/{include => register}/soc/otp_debug_struct.h (89%) rename components/soc/esp32c6/{include => register}/soc/parl_io_reg.h (98%) rename components/soc/esp32c6/{include => register}/soc/parl_io_struct.h (97%) rename components/soc/esp32c6/{include => register}/soc/pau_reg.h (100%) rename components/soc/esp32c6/{include => register}/soc/pau_struct.h (100%) rename components/soc/esp32c6/{include => register}/soc/pcnt_reg.h (100%) rename components/soc/esp32c6/{include => register}/soc/pcnt_struct.h (100%) rename components/soc/esp32c6/{include => register}/soc/pcr_reg.h (98%) rename components/soc/esp32c6/{include => register}/soc/pcr_struct.h (97%) rename components/soc/esp32c6/{include => register}/soc/plic_reg.h (100%) rename components/soc/esp32c6/{include => register}/soc/pmu_reg.h (100%) rename components/soc/esp32c6/{include => register}/soc/pmu_struct.h (99%) rename components/soc/esp32c6/{include => register}/soc/reg_base.h (100%) rename components/soc/esp32c6/{include => register}/soc/rmt_reg.h (100%) rename components/soc/esp32c6/{include => register}/soc/rmt_struct.h (100%) rename components/soc/esp32c6/{include => register}/soc/rsa_reg.h (100%) rename components/soc/esp32c6/{include => register}/soc/rsa_struct.h (100%) rename components/soc/esp32c6/{include => register}/soc/sha_reg.h (98%) rename components/soc/esp32c6/{include => register}/soc/sha_struct.h (100%) rename components/soc/esp32c6/{include => register}/soc/slc_reg.h (100%) rename components/soc/esp32c6/{include => register}/soc/slc_struct.h (100%) rename components/soc/esp32c6/{include => register}/soc/soc_etm_reg.h (100%) rename components/soc/esp32c6/{include => register}/soc/soc_etm_struct.h (100%) rename components/soc/esp32c6/{include => register}/soc/spi_mem_reg.h (99%) rename components/soc/esp32c6/{include => register}/soc/spi_mem_struct.h (99%) rename components/soc/esp32c6/{include => register}/soc/spi_reg.h (99%) rename components/soc/esp32c6/{include => register}/soc/spi_struct.h (99%) rename components/soc/esp32c6/{include => register}/soc/systimer_reg.h (100%) rename components/soc/esp32c6/{include => register}/soc/systimer_struct.h (100%) rename components/soc/esp32c6/{include => register}/soc/tee_reg.h (100%) rename components/soc/esp32c6/{include => register}/soc/tee_struct.h (100%) rename components/soc/esp32c6/{include => register}/soc/timer_group_reg.h (100%) rename components/soc/esp32c6/{include => register}/soc/timer_group_struct.h (100%) rename components/soc/esp32c6/{include => register}/soc/trace_reg.h (99%) rename components/soc/esp32c6/{include => register}/soc/trace_struct.h (99%) rename components/soc/esp32c6/{include => register}/soc/twai_reg.h (100%) rename components/soc/esp32c6/{include => register}/soc/twai_struct.h (100%) rename components/soc/esp32c6/{include => register}/soc/uart_reg.h (99%) rename components/soc/esp32c6/{include => register}/soc/uart_struct.h (99%) rename components/soc/esp32c6/{include => register}/soc/uhci_reg.h (100%) rename components/soc/esp32c6/{include => register}/soc/uhci_struct.h (100%) rename components/soc/esp32c6/{include => register}/soc/usb_serial_jtag_reg.h (99%) rename components/soc/esp32c6/{include => register}/soc/usb_serial_jtag_struct.h (100%) rename components/soc/esp32c6/{include => register}/soc/xts_aes_reg.h (98%) diff --git a/components/soc/esp32c6/include/soc/dport_access.h b/components/soc/esp32c6/include/soc/dport_access.h index 000b58c36a1..54eb8a0a352 100644 --- a/components/soc/esp32c6/include/soc/dport_access.h +++ b/components/soc/esp32c6/include/soc/dport_access.h @@ -9,7 +9,6 @@ #include #include "soc.h" -#include "uart_reg.h" #ifdef __cplusplus extern "C" { diff --git a/components/soc/esp32c6/include/soc/soc.h b/components/soc/esp32c6/include/soc/soc.h index 6778a1764bc..afd44da86c4 100644 --- a/components/soc/esp32c6/include/soc/soc.h +++ b/components/soc/esp32c6/include/soc/soc.h @@ -12,7 +12,7 @@ #endif #include "esp_bit_defs.h" -#include "reg_base.h" +#include "soc/reg_base.h" #define PRO_CPU_NUM (0) diff --git a/components/soc/esp32c6/include/soc/system_reg.h b/components/soc/esp32c6/include/soc/system_reg.h index 4ed6ac2ac25..17cf94805ed 100644 --- a/components/soc/esp32c6/include/soc/system_reg.h +++ b/components/soc/esp32c6/include/soc/system_reg.h @@ -7,6 +7,6 @@ #include "soc/hp_system_reg.h" // TODO: IDF-5720 -#include "intpri_reg.h" +#include "soc/intpri_reg.h" #define SYSTEM_CPU_INTR_FROM_CPU_0_REG INTPRI_CPU_INTR_FROM_CPU_0_REG #define SYSTEM_CPU_INTR_FROM_CPU_0 INTPRI_CPU_INTR_FROM_CPU_0 diff --git a/components/soc/esp32c6/register/soc/.gitkeep b/components/soc/esp32c6/register/soc/.gitkeep deleted file mode 100644 index e69de29bb2d..00000000000 diff --git a/components/soc/esp32c6/include/soc/aes_reg.h b/components/soc/esp32c6/register/soc/aes_reg.h similarity index 100% rename from components/soc/esp32c6/include/soc/aes_reg.h rename to components/soc/esp32c6/register/soc/aes_reg.h diff --git a/components/soc/esp32c6/include/soc/aes_struct.h b/components/soc/esp32c6/register/soc/aes_struct.h similarity index 100% rename from components/soc/esp32c6/include/soc/aes_struct.h rename to components/soc/esp32c6/register/soc/aes_struct.h diff --git a/components/soc/esp32c6/include/soc/apb_saradc_reg.h b/components/soc/esp32c6/register/soc/apb_saradc_reg.h similarity index 100% rename from components/soc/esp32c6/include/soc/apb_saradc_reg.h rename to components/soc/esp32c6/register/soc/apb_saradc_reg.h diff --git a/components/soc/esp32c6/include/soc/apb_saradc_struct.h b/components/soc/esp32c6/register/soc/apb_saradc_struct.h similarity index 100% rename from components/soc/esp32c6/include/soc/apb_saradc_struct.h rename to components/soc/esp32c6/register/soc/apb_saradc_struct.h diff --git a/components/soc/esp32c6/include/soc/assist_debug_reg.h b/components/soc/esp32c6/register/soc/assist_debug_reg.h similarity index 99% rename from components/soc/esp32c6/include/soc/assist_debug_reg.h rename to components/soc/esp32c6/register/soc/assist_debug_reg.h index 8e0426dc6f5..d2b947d9466 100644 --- a/components/soc/esp32c6/include/soc/assist_debug_reg.h +++ b/components/soc/esp32c6/register/soc/assist_debug_reg.h @@ -92,7 +92,7 @@ extern "C" { #define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_V 0x00000001U #define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_S 10 /** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA : R/W; bitpos: [11]; default: 0; - * DBUS busy monitor enbale + * DBUS busy monitor enable */ #define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA (BIT(11)) #define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_M (ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_V << ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_S) @@ -270,7 +270,7 @@ extern "C" { #define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_V 0x00000001U #define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_S 10 /** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS : R/W; bitpos: [11]; default: 0; - * DBUS busy monitor interrupt enbale + * DBUS busy monitor interrupt enable */ #define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS (BIT(11)) #define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_M (ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_V << ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_S) @@ -491,7 +491,7 @@ extern "C" { */ #define ASSIST_DEBUG_CORE_0_SP_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x38) /** ASSIST_DEBUG_CORE_0_SP_MIN : R/W; bitpos: [31:0]; default: 0; - * core0 sp region configuration regsiter + * core0 sp region configuration register */ #define ASSIST_DEBUG_CORE_0_SP_MIN 0xFFFFFFFFU #define ASSIST_DEBUG_CORE_0_SP_MIN_M (ASSIST_DEBUG_CORE_0_SP_MIN_V << ASSIST_DEBUG_CORE_0_SP_MIN_S) @@ -515,7 +515,7 @@ extern "C" { */ #define ASSIST_DEBUG_CORE_0_SP_PC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x40) /** ASSIST_DEBUG_CORE_0_SP_PC : RO; bitpos: [31:0]; default: 0; - * This regsiter stores the PC when trigger stack monitor. + * This register stores the PC when trigger stack monitor. */ #define ASSIST_DEBUG_CORE_0_SP_PC 0xFFFFFFFFU #define ASSIST_DEBUG_CORE_0_SP_PC_M (ASSIST_DEBUG_CORE_0_SP_PC_V << ASSIST_DEBUG_CORE_0_SP_PC_S) @@ -542,7 +542,7 @@ extern "C" { #define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_S 1 /** ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG register - * record status regsiter + * record status register */ #define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x48) /** ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC : RO; bitpos: [31:0]; default: 0; @@ -554,7 +554,7 @@ extern "C" { #define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_S 0 /** ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG register - * record status regsiter + * record status register */ #define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG (DR_REG_ASSIST_DEBUG_BASE + 0x4c) /** ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP : RO; bitpos: [31:0]; default: 0; diff --git a/components/soc/esp32c6/include/soc/assist_debug_struct.h b/components/soc/esp32c6/register/soc/assist_debug_struct.h similarity index 98% rename from components/soc/esp32c6/include/soc/assist_debug_struct.h rename to components/soc/esp32c6/register/soc/assist_debug_struct.h index 24c28c33efa..9838880bc8c 100644 --- a/components/soc/esp32c6/include/soc/assist_debug_struct.h +++ b/components/soc/esp32c6/register/soc/assist_debug_struct.h @@ -61,7 +61,7 @@ typedef union { */ uint32_t core_0_iram0_exception_monitor_ena:1; /** core_0_dram0_exception_monitor_ena : R/W; bitpos: [11]; default: 0; - * DBUS busy monitor enbale + * DBUS busy monitor enable */ uint32_t core_0_dram0_exception_monitor_ena:1; uint32_t reserved_12:20; @@ -205,7 +205,7 @@ typedef union { typedef union { struct { /** core_0_sp_min : R/W; bitpos: [31:0]; default: 0; - * core0 sp region configuration regsiter + * core0 sp region configuration register */ uint32_t core_0_sp_min:32; }; @@ -231,7 +231,7 @@ typedef union { typedef union { struct { /** core_0_sp_pc : RO; bitpos: [31:0]; default: 0; - * This regsiter stores the PC when trigger stack monitor. + * This register stores the PC when trigger stack monitor. */ uint32_t core_0_sp_pc:32; }; @@ -348,7 +348,7 @@ typedef union { */ uint32_t core_0_iram0_exception_monitor_rls:1; /** core_0_dram0_exception_monitor_rls : R/W; bitpos: [11]; default: 0; - * DBUS busy monitor interrupt enbale + * DBUS busy monitor interrupt enable */ uint32_t core_0_dram0_exception_monitor_rls:1; uint32_t reserved_12:20; @@ -415,7 +415,7 @@ typedef union { } assist_debug_core_0_intr_clr_reg_t; -/** Group: pc reording configuration register */ +/** Group: pc recording configuration register */ /** Type of core_0_rcd_en register * record enable configuration register */ @@ -435,9 +435,9 @@ typedef union { } assist_debug_core_0_rcd_en_reg_t; -/** Group: pc reording status register */ +/** Group: pc recording status register */ /** Type of core_0_rcd_pdebugpc register - * record status regsiter + * record status register */ typedef union { struct { @@ -450,7 +450,7 @@ typedef union { } assist_debug_core_0_rcd_pdebugpc_reg_t; /** Type of core_0_rcd_pdebugsp register - * record status regsiter + * record status register */ typedef union { struct { @@ -463,7 +463,7 @@ typedef union { } assist_debug_core_0_rcd_pdebugsp_reg_t; -/** Group: exception monitor regsiter */ +/** Group: exception monitor register */ /** Type of core_0_iram0_exception_monitor_0 register * exception monitor status register0 */ diff --git a/components/soc/esp32c6/include/soc/clint_reg.h b/components/soc/esp32c6/register/soc/clint_reg.h similarity index 100% rename from components/soc/esp32c6/include/soc/clint_reg.h rename to components/soc/esp32c6/register/soc/clint_reg.h diff --git a/components/soc/esp32c6/include/soc/ds_reg.h b/components/soc/esp32c6/register/soc/ds_reg.h similarity index 100% rename from components/soc/esp32c6/include/soc/ds_reg.h rename to components/soc/esp32c6/register/soc/ds_reg.h diff --git a/components/soc/esp32c6/include/soc/ds_struct.h b/components/soc/esp32c6/register/soc/ds_struct.h similarity index 100% rename from components/soc/esp32c6/include/soc/ds_struct.h rename to components/soc/esp32c6/register/soc/ds_struct.h diff --git a/components/soc/esp32c6/include/soc/ecc_mult_reg.h b/components/soc/esp32c6/register/soc/ecc_mult_reg.h similarity index 98% rename from components/soc/esp32c6/include/soc/ecc_mult_reg.h rename to components/soc/esp32c6/register/soc/ecc_mult_reg.h index dca2cc1206a..00846e8ed63 100644 --- a/components/soc/esp32c6/include/soc/ecc_mult_reg.h +++ b/components/soc/esp32c6/register/soc/ecc_mult_reg.h @@ -64,7 +64,7 @@ extern "C" { */ #define ECC_MULT_CONF_REG (DR_REG_ECC_MULT_BASE + 0x1c) /** ECC_MULT_START : R/W/SC; bitpos: [0]; default: 0; - * Write 1 to start caculation of ECC Accelerator. This bit will be self-cleared after + * Write 1 to start calculation of ECC Accelerator. This bit will be self-cleared after * the caculatrion is done. */ #define ECC_MULT_START (BIT(0)) diff --git a/components/soc/esp32c6/include/soc/ecc_mult_struct.h b/components/soc/esp32c6/register/soc/ecc_mult_struct.h similarity index 97% rename from components/soc/esp32c6/include/soc/ecc_mult_struct.h rename to components/soc/esp32c6/register/soc/ecc_mult_struct.h index c120fb068de..89665324365 100644 --- a/components/soc/esp32c6/include/soc/ecc_mult_struct.h +++ b/components/soc/esp32c6/register/soc/ecc_mult_struct.h @@ -77,7 +77,7 @@ typedef union { typedef union { struct { /** start : R/W/SC; bitpos: [0]; default: 0; - * Write 1 to start caculation of ECC Accelerator. This bit will be self-cleared after + * Write 1 to start calculation of ECC Accelerator. This bit will be self-cleared after * the caculatrion is done. */ uint32_t start:1; diff --git a/components/soc/esp32c6/include/soc/efuse_reg.h b/components/soc/esp32c6/register/soc/efuse_reg.h similarity index 99% rename from components/soc/esp32c6/include/soc/efuse_reg.h rename to components/soc/esp32c6/register/soc/efuse_reg.h index 882041ac413..b91b0b0ff0e 100644 --- a/components/soc/esp32c6/include/soc/efuse_reg.h +++ b/components/soc/esp32c6/register/soc/efuse_reg.h @@ -7,7 +7,7 @@ #include #include "soc/soc.h" -#include "efuse_defs.h" +#include "soc/efuse_defs.h" #ifdef __cplusplus extern "C" { #endif @@ -264,14 +264,14 @@ extern "C" { #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V 0x00000001U #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S 20 /** EFUSE_USB_DREFH : RO; bitpos: [22:21]; default: 0; - * Represents the single-end input threhold vrefh, 1.76 V to 2 V with step of 80 mV. + * Represents the single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV. */ #define EFUSE_USB_DREFH 0x00000003U #define EFUSE_USB_DREFH_M (EFUSE_USB_DREFH_V << EFUSE_USB_DREFH_S) #define EFUSE_USB_DREFH_V 0x00000003U #define EFUSE_USB_DREFH_S 21 /** EFUSE_USB_DREFL : RO; bitpos: [24:23]; default: 0; - * Represents the single-end input threhold vrefl, 1.76 V to 2 V with step of 80 mV. + * Represents the single-end input threshold vrefl, 1.76 V to 2 V with step of 80 mV. */ #define EFUSE_USB_DREFL 0x00000003U #define EFUSE_USB_DREFL_M (EFUSE_USB_DREFL_V << EFUSE_USB_DREFL_S) @@ -2390,7 +2390,7 @@ extern "C" { #define EFUSE_CLK_EN_S 16 /** EFUSE_CONF_REG register - * eFuse operation mode configuraiton register + * eFuse operation mode configuration register */ #define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x1cc) /** EFUSE_OP_CODE : R/W; bitpos: [15:0]; default: 0; diff --git a/components/soc/esp32c6/include/soc/efuse_struct.h b/components/soc/esp32c6/register/soc/efuse_struct.h similarity index 99% rename from components/soc/esp32c6/include/soc/efuse_struct.h rename to components/soc/esp32c6/register/soc/efuse_struct.h index e6971b4d583..c92f02208c4 100644 --- a/components/soc/esp32c6/include/soc/efuse_struct.h +++ b/components/soc/esp32c6/register/soc/efuse_struct.h @@ -239,11 +239,11 @@ typedef union { */ uint32_t dis_download_manual_encrypt:1; /** usb_drefh : RO; bitpos: [22:21]; default: 0; - * Represents the single-end input threhold vrefh, 1.76 V to 2 V with step of 80 mV. + * Represents the single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV. */ uint32_t usb_drefh:2; /** usb_drefl : RO; bitpos: [24:23]; default: 0; - * Represents the single-end input threhold vrefl, 1.76 V to 2 V with step of 80 mV. + * Represents the single-end input threshold vrefl, 1.76 V to 2 V with step of 80 mV. */ uint32_t usb_drefl:2; /** usb_exchg_pins : RO; bitpos: [25]; default: 0; @@ -2024,7 +2024,7 @@ typedef union { } efuse_clk_reg_t; /** Type of conf register - * eFuse operation mode configuraiton register + * eFuse operation mode configuration register */ typedef union { struct { diff --git a/components/soc/esp32c6/include/soc/extmem_reg.h b/components/soc/esp32c6/register/soc/extmem_reg.h similarity index 98% rename from components/soc/esp32c6/include/soc/extmem_reg.h rename to components/soc/esp32c6/register/soc/extmem_reg.h index a9cb6935862..08a9daf433c 100644 --- a/components/soc/esp32c6/include/soc/extmem_reg.h +++ b/components/soc/esp32c6/register/soc/extmem_reg.h @@ -243,8 +243,8 @@ ould be used together with CACHE_LOCK_ADDR_REG.*/ #define EXTMEM_L1_CACHE_SYNC_DONE_S 4 /* EXTMEM_L1_CACHE_WRITEBACK_INVALIDATE_ENA : R/W/SC ;bitpos:[3] ;default: 1'h0 ; */ /*description: The bit is used to enable writeback-invalidate operation. It will be cleared by -hardware after writeback-invalidate operation done. Note that this bit and the o -ther sync-bits (invalidate_ena, clean_ena, writeback_ena) are mutually exclusive +hardware after writeback-invalidate operation done. Note that this bit and the +other sync-bits (invalidate_ena, clean_ena, writeback_ena) are mutually exclusive , that is, those bits can not be set to 1 at the same time..*/ #define EXTMEM_L1_CACHE_WRITEBACK_INVALIDATE_ENA (BIT(3)) #define EXTMEM_L1_CACHE_WRITEBACK_INVALIDATE_ENA_M (BIT(3)) @@ -262,16 +262,16 @@ those bits can not be set to 1 at the same time..*/ /* EXTMEM_L1_CACHE_CLEAN_ENA : R/W/SC ;bitpos:[1] ;default: 1'h0 ; */ /*description: The bit is used to enable clean operation. It will be cleared by hardware after clean operation done. Note that this bit and the other sync-bits (invalidate_ena -, writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is, thos -e bits can not be set to 1 at the same time..*/ +, writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is, those +bits can not be set to 1 at the same time..*/ #define EXTMEM_L1_CACHE_CLEAN_ENA (BIT(1)) #define EXTMEM_L1_CACHE_CLEAN_ENA_M (BIT(1)) #define EXTMEM_L1_CACHE_CLEAN_ENA_V 0x1 #define EXTMEM_L1_CACHE_CLEAN_ENA_S 1 /* EXTMEM_L1_CACHE_INVALIDATE_ENA : R/W/SC ;bitpos:[0] ;default: 1'h1 ; */ /*description: The bit is used to enable invalidate operation. It will be cleared by hardware a -fter invalidate operation done. Note that this bit and the other sync-bits (clea -n_ena, writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is, +after invalidate operation done. Note that this bit and the other sync-bits (clean_ena, +writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is, those bits can not be set to 1 at the same time..*/ #define EXTMEM_L1_CACHE_INVALIDATE_ENA (BIT(0)) #define EXTMEM_L1_CACHE_INVALIDATE_ENA_M (BIT(0)) @@ -452,15 +452,15 @@ SCT1_ADDR and L1_CACHE_AUTOLOAD_SCT1_ENA..*/ #define EXTMEM_L1_CACHE_ACS_CNT_INT_CLR_REG (DR_REG_EXTMEM_BASE + 0x15C) /* EXTMEM_L1_DBUS_OVF_INT_CLR : WT ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The bit is used to clear counters overflow interrupt and counters in L1-DCache d -ue to bus1 accesses L1-DCache..*/ +/*description: The bit is used to clear counters overflow interrupt and counters in L1-DCache due +to bus1 accesses L1-DCache..*/ #define EXTMEM_L1_DBUS_OVF_INT_CLR (BIT(5)) #define EXTMEM_L1_DBUS_OVF_INT_CLR_M (BIT(5)) #define EXTMEM_L1_DBUS_OVF_INT_CLR_V 0x1 #define EXTMEM_L1_DBUS_OVF_INT_CLR_S 5 /* EXTMEM_L1_IBUS_OVF_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The bit is used to clear counters overflow interrupt and counters in L1-DCache d -ue to bus0 accesses L1-DCache..*/ +/*description: The bit is used to clear counters overflow interrupt and counters in L1-DCache due +to bus0 accesses L1-DCache..*/ #define EXTMEM_L1_IBUS_OVF_INT_CLR (BIT(4)) #define EXTMEM_L1_IBUS_OVF_INT_CLR_M (BIT(4)) #define EXTMEM_L1_IBUS_OVF_INT_CLR_V 0x1 @@ -526,8 +526,8 @@ o cpu accesses L1-DCache..*/ #define EXTMEM_L1_CACHE_ACS_FAIL_INT_ST_REG (DR_REG_EXTMEM_BASE + 0x174) /* EXTMEM_L1_CACHE_FAIL_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The bit indicates the interrupt status of access fail that occurs in L1-DCache d -ue to cpu accesses L1-DCache..*/ +/*description: The bit indicates the interrupt status of access fail that occurs in L1-DCache due +to cpu accesses L1-DCache..*/ #define EXTMEM_L1_CACHE_FAIL_INT_ST (BIT(4)) #define EXTMEM_L1_CACHE_FAIL_INT_ST_M (BIT(4)) #define EXTMEM_L1_CACHE_FAIL_INT_ST_V 0x1 @@ -740,7 +740,7 @@ ror occurs..*/ #define EXTMEM_L1_CACHE_SYNC_ERR_INT_ST_V 0x1 #define EXTMEM_L1_CACHE_SYNC_ERR_INT_ST_S 13 /* EXTMEM_L1_CACHE_PLD_ERR_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: The bit indicates the status of the interrupt of L1-Cache preload-operation erro +/*description: The bit indicates the status of the interrupt of L1-Cache preload-operation error r..*/ #define EXTMEM_L1_CACHE_PLD_ERR_INT_ST (BIT(11)) #define EXTMEM_L1_CACHE_PLD_ERR_INT_ST_M (BIT(11)) @@ -778,7 +778,7 @@ load-operation is done..*/ #define EXTMEM_L1_CACHE_SYNC_RST_CTRL_REG (DR_REG_EXTMEM_BASE + 0x238) /* EXTMEM_L1_CACHE_SYNC_RST : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: set this bit to reset sync-logic inside L1-Cache. Recommend that this should onl +/*description: set this bit to reset sync-logic inside L1-Cache. Recommend that this should only y be used to initialize sync-logic when some fatal error of sync-logic occurs..*/ #define EXTMEM_L1_CACHE_SYNC_RST (BIT(4)) #define EXTMEM_L1_CACHE_SYNC_RST_M (BIT(4)) @@ -808,7 +808,7 @@ rks in L1-Cache..*/ #define EXTMEM_L1_UNALLOCATE_BUFFER_CLEAR_REG (DR_REG_EXTMEM_BASE + 0x244) /* EXTMEM_L1_CACHE_UNALLOC_CLR : R/W ;bitpos:[4] ;default: 1'b0 ; */ /*description: The bit is used to clear the unallocate request buffer of l1 cache where the una -llocate request is responsed but not completed..*/ +llocate request is responded but not completed..*/ #define EXTMEM_L1_CACHE_UNALLOC_CLR (BIT(4)) #define EXTMEM_L1_CACHE_UNALLOC_CLR_M (BIT(4)) #define EXTMEM_L1_CACHE_UNALLOC_CLR_V 0x1 @@ -823,7 +823,7 @@ th the others fields inside this register..*/ #define EXTMEM_L1_CACHE_MEM_OBJECT_V 0x1 #define EXTMEM_L1_CACHE_MEM_OBJECT_S 10 /* EXTMEM_L1_CACHE_TAG_OBJECT : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: Set this bit to set L1-Cache tag memory as object. This bit should be onehot wit +/*description: Set this bit to set L1-Cache tag memory as object. This bit should be onehot with h the others fields inside this register..*/ #define EXTMEM_L1_CACHE_TAG_OBJECT (BIT(4)) #define EXTMEM_L1_CACHE_TAG_OBJECT_M (BIT(4)) @@ -841,8 +841,8 @@ h the others fields inside this register..*/ #define EXTMEM_L1_CACHE_VADDR_REG (DR_REG_EXTMEM_BASE + 0x250) /* EXTMEM_L1_CACHE_VADDR : R/W ;bitpos:[31:0] ;default: 32'h40000000 ; */ -/*description: Those bits stores the virtual address which will decide where inside the specifi -ed tag memory object will be accessed..*/ +/*description: Those bits stores the virtual address which will decide where inside the specified +tag memory object will be accessed..*/ #define EXTMEM_L1_CACHE_VADDR 0xFFFFFFFF #define EXTMEM_L1_CACHE_VADDR_M ((EXTMEM_L1_CACHE_VADDR_V)<<(EXTMEM_L1_CACHE_VADDR_S)) #define EXTMEM_L1_CACHE_VADDR_V 0xFFFFFFFF diff --git a/components/soc/esp32c6/include/soc/extmem_struct.h b/components/soc/esp32c6/register/soc/extmem_struct.h similarity index 99% rename from components/soc/esp32c6/include/soc/extmem_struct.h rename to components/soc/esp32c6/register/soc/extmem_struct.h index d309e09235e..d43c5fcee3d 100644 --- a/components/soc/esp32c6/include/soc/extmem_struct.h +++ b/components/soc/esp32c6/register/soc/extmem_struct.h @@ -5115,12 +5115,12 @@ typedef union { struct { /** l1_icache0_unalloc_clr : HRO; bitpos: [0]; default: 0; * The bit is used to clear the unallocate request buffer of l1 icache0 where the - * unallocate request is responsed but not completed. + * unallocate request is responded but not completed. */ uint32_t l1_icache0_unalloc_clr:1; /** l1_icache1_unalloc_clr : HRO; bitpos: [1]; default: 0; * The bit is used to clear the unallocate request buffer of l1 icache1 where the - * unallocate request is responsed but not completed. + * unallocate request is responded but not completed. */ uint32_t l1_icache1_unalloc_clr:1; /** l1_icache2_unalloc_clr : HRO; bitpos: [2]; default: 0; @@ -5133,7 +5133,7 @@ typedef union { uint32_t l1_icache3_unalloc_clr:1; /** l1_cache_unalloc_clr : R/W; bitpos: [4]; default: 0; * The bit is used to clear the unallocate request buffer of l1 cache where the - * unallocate request is responsed but not completed. + * unallocate request is responded but not completed. */ uint32_t l1_cache_unalloc_clr:1; uint32_t reserved_5:27; @@ -5149,7 +5149,7 @@ typedef union { uint32_t reserved_0:5; /** l2_cache_unalloc_clr : HRO; bitpos: [5]; default: 0; * The bit is used to clear the unallocate request buffer of l2 icache where the - * unallocate request is responsed but not completed. + * unallocate request is responded but not completed. */ uint32_t l2_cache_unalloc_clr:1; uint32_t reserved_6:26; diff --git a/components/soc/esp32c6/include/soc/gdma_reg.h b/components/soc/esp32c6/register/soc/gdma_reg.h similarity index 100% rename from components/soc/esp32c6/include/soc/gdma_reg.h rename to components/soc/esp32c6/register/soc/gdma_reg.h diff --git a/components/soc/esp32c6/include/soc/gdma_struct.h b/components/soc/esp32c6/register/soc/gdma_struct.h similarity index 100% rename from components/soc/esp32c6/include/soc/gdma_struct.h rename to components/soc/esp32c6/register/soc/gdma_struct.h diff --git a/components/soc/esp32c6/include/soc/gpio_ext_reg.h b/components/soc/esp32c6/register/soc/gpio_ext_reg.h similarity index 100% rename from components/soc/esp32c6/include/soc/gpio_ext_reg.h rename to components/soc/esp32c6/register/soc/gpio_ext_reg.h diff --git a/components/soc/esp32c6/include/soc/gpio_ext_struct.h b/components/soc/esp32c6/register/soc/gpio_ext_struct.h similarity index 100% rename from components/soc/esp32c6/include/soc/gpio_ext_struct.h rename to components/soc/esp32c6/register/soc/gpio_ext_struct.h diff --git a/components/soc/esp32c6/include/soc/gpio_reg.h b/components/soc/esp32c6/register/soc/gpio_reg.h similarity index 100% rename from components/soc/esp32c6/include/soc/gpio_reg.h rename to components/soc/esp32c6/register/soc/gpio_reg.h diff --git a/components/soc/esp32c6/include/soc/gpio_struct.h b/components/soc/esp32c6/register/soc/gpio_struct.h similarity index 100% rename from components/soc/esp32c6/include/soc/gpio_struct.h rename to components/soc/esp32c6/register/soc/gpio_struct.h diff --git a/components/soc/esp32c6/include/soc/hardware_lock_reg.h b/components/soc/esp32c6/register/soc/hardware_lock_reg.h similarity index 93% rename from components/soc/esp32c6/include/soc/hardware_lock_reg.h rename to components/soc/esp32c6/register/soc/hardware_lock_reg.h index a9fbfb8cb06..a80313138c4 100644 --- a/components/soc/esp32c6/include/soc/hardware_lock_reg.h +++ b/components/soc/esp32c6/register/soc/hardware_lock_reg.h @@ -12,7 +12,7 @@ extern "C" { #endif /** ATOMIC_ADDR_LOCK_REG register - * hardware lock regsiter + * hardware lock register */ #define ATOMIC_ADDR_LOCK_REG (DR_REG_ATOMIC_BASE + 0x0) /** ATOMIC_LOCK : R/W; bitpos: [1:0]; default: 0; @@ -24,7 +24,7 @@ extern "C" { #define ATOMIC_LOCK_S 0 /** ATOMIC_LR_ADDR_REG register - * gloable lr address regsiter + * gloable lr address register */ #define ATOMIC_LR_ADDR_REG (DR_REG_ATOMIC_BASE + 0x4) /** ATOMIC_GLOABLE_LR_ADDR : R/W; bitpos: [31:0]; default: 0; @@ -36,7 +36,7 @@ extern "C" { #define ATOMIC_GLOABLE_LR_ADDR_S 0 /** ATOMIC_LR_VALUE_REG register - * gloable lr value regsiter + * gloable lr value register */ #define ATOMIC_LR_VALUE_REG (DR_REG_ATOMIC_BASE + 0x8) /** ATOMIC_GLOABLE_LR_VALUE : R/W; bitpos: [31:0]; default: 0; @@ -48,11 +48,11 @@ extern "C" { #define ATOMIC_GLOABLE_LR_VALUE_S 0 /** ATOMIC_LOCK_STATUS_REG register - * lock status regsiter + * lock status register */ #define ATOMIC_LOCK_STATUS_REG (DR_REG_ATOMIC_BASE + 0xc) /** ATOMIC_LOCK_STATUS : RO; bitpos: [1:0]; default: 0; - * read hareware lock status for debug + * read hardware lock status for debug */ #define ATOMIC_LOCK_STATUS 0x00000003U #define ATOMIC_LOCK_STATUS_M (ATOMIC_LOCK_STATUS_V << ATOMIC_LOCK_STATUS_S) diff --git a/components/soc/esp32c6/include/soc/hardware_lock_struct.h b/components/soc/esp32c6/register/soc/hardware_lock_struct.h similarity index 92% rename from components/soc/esp32c6/include/soc/hardware_lock_struct.h rename to components/soc/esp32c6/register/soc/hardware_lock_struct.h index 0430212e50d..cbea0bebea0 100644 --- a/components/soc/esp32c6/include/soc/hardware_lock_struct.h +++ b/components/soc/esp32c6/register/soc/hardware_lock_struct.h @@ -12,7 +12,7 @@ extern "C" { /** Group: configuration registers */ /** Type of addr_lock register - * hardware lock regsiter + * hardware lock register */ typedef union { struct { @@ -26,7 +26,7 @@ typedef union { } atomic_addr_lock_reg_t; /** Type of lr_addr register - * gloable lr address regsiter + * gloable lr address register */ typedef union { struct { @@ -39,7 +39,7 @@ typedef union { } atomic_lr_addr_reg_t; /** Type of lr_value register - * gloable lr value regsiter + * gloable lr value register */ typedef union { struct { @@ -52,12 +52,12 @@ typedef union { } atomic_lr_value_reg_t; /** Type of lock_status register - * lock status regsiter + * lock status register */ typedef union { struct { /** lock_status : RO; bitpos: [1:0]; default: 0; - * read hareware lock status for debug + * read hardware lock status for debug */ uint32_t lock_status:2; uint32_t reserved_2:30; diff --git a/components/soc/esp32c6/include/soc/hinf_reg.h b/components/soc/esp32c6/register/soc/hinf_reg.h similarity index 100% rename from components/soc/esp32c6/include/soc/hinf_reg.h rename to components/soc/esp32c6/register/soc/hinf_reg.h diff --git a/components/soc/esp32c6/include/soc/hinf_struct.h b/components/soc/esp32c6/register/soc/hinf_struct.h similarity index 100% rename from components/soc/esp32c6/include/soc/hinf_struct.h rename to components/soc/esp32c6/register/soc/hinf_struct.h diff --git a/components/soc/esp32c6/include/soc/hmac_reg.h b/components/soc/esp32c6/register/soc/hmac_reg.h similarity index 100% rename from components/soc/esp32c6/include/soc/hmac_reg.h rename to components/soc/esp32c6/register/soc/hmac_reg.h diff --git a/components/soc/esp32c6/include/soc/hmac_struct.h b/components/soc/esp32c6/register/soc/hmac_struct.h similarity index 100% rename from components/soc/esp32c6/include/soc/hmac_struct.h rename to components/soc/esp32c6/register/soc/hmac_struct.h diff --git a/components/soc/esp32c6/include/soc/host_reg.h b/components/soc/esp32c6/register/soc/host_reg.h similarity index 100% rename from components/soc/esp32c6/include/soc/host_reg.h rename to components/soc/esp32c6/register/soc/host_reg.h diff --git a/components/soc/esp32c6/include/soc/host_struct.h b/components/soc/esp32c6/register/soc/host_struct.h similarity index 100% rename from components/soc/esp32c6/include/soc/host_struct.h rename to components/soc/esp32c6/register/soc/host_struct.h diff --git a/components/soc/esp32c6/include/soc/hp_apm_reg.h b/components/soc/esp32c6/register/soc/hp_apm_reg.h similarity index 100% rename from components/soc/esp32c6/include/soc/hp_apm_reg.h rename to components/soc/esp32c6/register/soc/hp_apm_reg.h diff --git a/components/soc/esp32c6/include/soc/hp_apm_struct.h b/components/soc/esp32c6/register/soc/hp_apm_struct.h similarity index 100% rename from components/soc/esp32c6/include/soc/hp_apm_struct.h rename to components/soc/esp32c6/register/soc/hp_apm_struct.h diff --git a/components/soc/esp32c6/include/soc/hp_system_reg.h b/components/soc/esp32c6/register/soc/hp_system_reg.h similarity index 99% rename from components/soc/esp32c6/include/soc/hp_system_reg.h rename to components/soc/esp32c6/register/soc/hp_system_reg.h index 898d0fb0e59..f32f280f237 100644 --- a/components/soc/esp32c6/include/soc/hp_system_reg.h +++ b/components/soc/esp32c6/register/soc/hp_system_reg.h @@ -78,7 +78,7 @@ extern "C" { * 0: anti-DPA disable. 1~3: anti-DPA enable with different security level. The larger * the number, the stronger the ability to resist DPA attacks and the higher the * security level, but it will increase the computational overhead of the hardware - * crypto-accelerators. Only avaliable if HP_SYSTEM_SEC_DPA_CFG_SEL is 0. + * crypto-accelerators. Only available if HP_SYSTEM_SEC_DPA_CFG_SEL is 0. */ #define HP_SYSTEM_SEC_DPA_LEVEL 0x00000003U #define HP_SYSTEM_SEC_DPA_LEVEL_M (HP_SYSTEM_SEC_DPA_LEVEL_V << HP_SYSTEM_SEC_DPA_LEVEL_S) diff --git a/components/soc/esp32c6/include/soc/hp_system_struct.h b/components/soc/esp32c6/register/soc/hp_system_struct.h similarity index 99% rename from components/soc/esp32c6/include/soc/hp_system_struct.h rename to components/soc/esp32c6/register/soc/hp_system_struct.h index b174aa4290a..20b8eac2f88 100644 --- a/components/soc/esp32c6/include/soc/hp_system_struct.h +++ b/components/soc/esp32c6/register/soc/hp_system_struct.h @@ -70,7 +70,7 @@ typedef union { * 0: anti-DPA disable. 1~3: anti-DPA enable with different security level. The larger * the number, the stronger the ability to resist DPA attacks and the higher the * security level, but it will increase the computational overhead of the hardware - * crypto-accelerators. Only avaliable if HP_SYSTEM_SEC_DPA_CFG_SEL is 0. + * crypto-accelerators. Only available if HP_SYSTEM_SEC_DPA_CFG_SEL is 0. */ uint32_t sec_dpa_level:2; /** sec_dpa_cfg_sel : R/W; bitpos: [2]; default: 0; diff --git a/components/soc/esp32c6/include/soc/i2c_ana_mst_reg.h b/components/soc/esp32c6/register/soc/i2c_ana_mst_reg.h similarity index 100% rename from components/soc/esp32c6/include/soc/i2c_ana_mst_reg.h rename to components/soc/esp32c6/register/soc/i2c_ana_mst_reg.h diff --git a/components/soc/esp32c6/include/soc/i2c_reg.h b/components/soc/esp32c6/register/soc/i2c_reg.h similarity index 100% rename from components/soc/esp32c6/include/soc/i2c_reg.h rename to components/soc/esp32c6/register/soc/i2c_reg.h diff --git a/components/soc/esp32c6/include/soc/i2c_struct.h b/components/soc/esp32c6/register/soc/i2c_struct.h similarity index 100% rename from components/soc/esp32c6/include/soc/i2c_struct.h rename to components/soc/esp32c6/register/soc/i2c_struct.h diff --git a/components/soc/esp32c6/include/soc/i2s_reg.h b/components/soc/esp32c6/register/soc/i2s_reg.h similarity index 99% rename from components/soc/esp32c6/include/soc/i2s_reg.h rename to components/soc/esp32c6/register/soc/i2s_reg.h index 89fd5eb8444..4f259c1131c 100644 --- a/components/soc/esp32c6/include/soc/i2s_reg.h +++ b/components/soc/esp32c6/register/soc/i2s_reg.h @@ -361,7 +361,7 @@ extern "C" { #define I2S_TX_PCM_BYPASS_V 0x00000001U #define I2S_TX_PCM_BYPASS_S 12 /** I2S_TX_STOP_EN : R/W; bitpos: [13]; default: 1; - * Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy + * Set this bit to stop disable output BCK signal and WS signal when tx FIFO is empty */ #define I2S_TX_STOP_EN (BIT(13)) #define I2S_TX_STOP_EN_M (I2S_TX_STOP_EN_V << I2S_TX_STOP_EN_S) diff --git a/components/soc/esp32c6/include/soc/i2s_struct.h b/components/soc/esp32c6/register/soc/i2s_struct.h similarity index 99% rename from components/soc/esp32c6/include/soc/i2s_struct.h rename to components/soc/esp32c6/register/soc/i2s_struct.h index f7b7f069ad9..b7629e4c989 100644 --- a/components/soc/esp32c6/include/soc/i2s_struct.h +++ b/components/soc/esp32c6/register/soc/i2s_struct.h @@ -494,7 +494,7 @@ typedef union { */ uint32_t tx_pcm_bypass:1; /** tx_stop_en : R/W; bitpos: [13]; default: 1; - * Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy + * Set this bit to stop disable output BCK signal and WS signal when tx FIFO is empty */ uint32_t tx_stop_en:1; uint32_t reserved_14:1; diff --git a/components/soc/esp32c6/include/soc/ieee802154_reg.h b/components/soc/esp32c6/register/soc/ieee802154_reg.h similarity index 100% rename from components/soc/esp32c6/include/soc/ieee802154_reg.h rename to components/soc/esp32c6/register/soc/ieee802154_reg.h diff --git a/components/soc/esp32c6/include/soc/ieee802154_struct.h b/components/soc/esp32c6/register/soc/ieee802154_struct.h similarity index 100% rename from components/soc/esp32c6/include/soc/ieee802154_struct.h rename to components/soc/esp32c6/register/soc/ieee802154_struct.h diff --git a/components/soc/esp32c6/include/soc/interrupt_matrix_reg.h b/components/soc/esp32c6/register/soc/interrupt_matrix_reg.h similarity index 100% rename from components/soc/esp32c6/include/soc/interrupt_matrix_reg.h rename to components/soc/esp32c6/register/soc/interrupt_matrix_reg.h diff --git a/components/soc/esp32c6/include/soc/interrupt_matrix_struct.h b/components/soc/esp32c6/register/soc/interrupt_matrix_struct.h similarity index 100% rename from components/soc/esp32c6/include/soc/interrupt_matrix_struct.h rename to components/soc/esp32c6/register/soc/interrupt_matrix_struct.h diff --git a/components/soc/esp32c6/include/soc/intpri_reg.h b/components/soc/esp32c6/register/soc/intpri_reg.h similarity index 100% rename from components/soc/esp32c6/include/soc/intpri_reg.h rename to components/soc/esp32c6/register/soc/intpri_reg.h diff --git a/components/soc/esp32c6/include/soc/intpri_struct.h b/components/soc/esp32c6/register/soc/intpri_struct.h similarity index 100% rename from components/soc/esp32c6/include/soc/intpri_struct.h rename to components/soc/esp32c6/register/soc/intpri_struct.h diff --git a/components/soc/esp32c6/include/soc/io_mux_reg.h b/components/soc/esp32c6/register/soc/io_mux_reg.h similarity index 99% rename from components/soc/esp32c6/include/soc/io_mux_reg.h rename to components/soc/esp32c6/register/soc/io_mux_reg.h index 698a2b5785b..0adf0203ef1 100644 --- a/components/soc/esp32c6/include/soc/io_mux_reg.h +++ b/components/soc/esp32c6/register/soc/io_mux_reg.h @@ -5,7 +5,7 @@ */ #pragma once -#include "soc.h" +#include "soc/soc.h" /* The following are the bit fields for PERIPHS_IO_MUX_x_U registers */ /* Output enable in sleep mode */ diff --git a/components/soc/esp32c6/include/soc/ledc_reg.h b/components/soc/esp32c6/register/soc/ledc_reg.h similarity index 100% rename from components/soc/esp32c6/include/soc/ledc_reg.h rename to components/soc/esp32c6/register/soc/ledc_reg.h diff --git a/components/soc/esp32c6/include/soc/ledc_struct.h b/components/soc/esp32c6/register/soc/ledc_struct.h similarity index 100% rename from components/soc/esp32c6/include/soc/ledc_struct.h rename to components/soc/esp32c6/register/soc/ledc_struct.h diff --git a/components/soc/esp32c6/include/soc/lp_analog_peri_reg.h b/components/soc/esp32c6/register/soc/lp_analog_peri_reg.h similarity index 100% rename from components/soc/esp32c6/include/soc/lp_analog_peri_reg.h rename to components/soc/esp32c6/register/soc/lp_analog_peri_reg.h diff --git a/components/soc/esp32c6/include/soc/lp_analog_peri_struct.h b/components/soc/esp32c6/register/soc/lp_analog_peri_struct.h similarity index 100% rename from components/soc/esp32c6/include/soc/lp_analog_peri_struct.h rename to components/soc/esp32c6/register/soc/lp_analog_peri_struct.h diff --git a/components/soc/esp32c6/include/soc/lp_aon_reg.h b/components/soc/esp32c6/register/soc/lp_aon_reg.h similarity index 100% rename from components/soc/esp32c6/include/soc/lp_aon_reg.h rename to components/soc/esp32c6/register/soc/lp_aon_reg.h diff --git a/components/soc/esp32c6/include/soc/lp_aon_struct.h b/components/soc/esp32c6/register/soc/lp_aon_struct.h similarity index 100% rename from components/soc/esp32c6/include/soc/lp_aon_struct.h rename to components/soc/esp32c6/register/soc/lp_aon_struct.h diff --git a/components/soc/esp32c6/include/soc/lp_apm0_reg.h b/components/soc/esp32c6/register/soc/lp_apm0_reg.h similarity index 100% rename from components/soc/esp32c6/include/soc/lp_apm0_reg.h rename to components/soc/esp32c6/register/soc/lp_apm0_reg.h diff --git a/components/soc/esp32c6/include/soc/lp_apm0_struct.h b/components/soc/esp32c6/register/soc/lp_apm0_struct.h similarity index 100% rename from components/soc/esp32c6/include/soc/lp_apm0_struct.h rename to components/soc/esp32c6/register/soc/lp_apm0_struct.h diff --git a/components/soc/esp32c6/include/soc/lp_apm_reg.h b/components/soc/esp32c6/register/soc/lp_apm_reg.h similarity index 100% rename from components/soc/esp32c6/include/soc/lp_apm_reg.h rename to components/soc/esp32c6/register/soc/lp_apm_reg.h diff --git a/components/soc/esp32c6/include/soc/lp_apm_struct.h b/components/soc/esp32c6/register/soc/lp_apm_struct.h similarity index 100% rename from components/soc/esp32c6/include/soc/lp_apm_struct.h rename to components/soc/esp32c6/register/soc/lp_apm_struct.h diff --git a/components/soc/esp32c6/include/soc/lp_clkrst_reg.h b/components/soc/esp32c6/register/soc/lp_clkrst_reg.h similarity index 100% rename from components/soc/esp32c6/include/soc/lp_clkrst_reg.h rename to components/soc/esp32c6/register/soc/lp_clkrst_reg.h diff --git a/components/soc/esp32c6/include/soc/lp_clkrst_struct.h b/components/soc/esp32c6/register/soc/lp_clkrst_struct.h similarity index 100% rename from components/soc/esp32c6/include/soc/lp_clkrst_struct.h rename to components/soc/esp32c6/register/soc/lp_clkrst_struct.h diff --git a/components/soc/esp32c6/include/soc/lp_i2c_ana_mst_reg.h b/components/soc/esp32c6/register/soc/lp_i2c_ana_mst_reg.h similarity index 100% rename from components/soc/esp32c6/include/soc/lp_i2c_ana_mst_reg.h rename to components/soc/esp32c6/register/soc/lp_i2c_ana_mst_reg.h diff --git a/components/soc/esp32c6/include/soc/lp_i2c_ana_mst_struct.h b/components/soc/esp32c6/register/soc/lp_i2c_ana_mst_struct.h similarity index 100% rename from components/soc/esp32c6/include/soc/lp_i2c_ana_mst_struct.h rename to components/soc/esp32c6/register/soc/lp_i2c_ana_mst_struct.h diff --git a/components/soc/esp32c6/include/soc/lp_i2c_reg.h b/components/soc/esp32c6/register/soc/lp_i2c_reg.h similarity index 100% rename from components/soc/esp32c6/include/soc/lp_i2c_reg.h rename to components/soc/esp32c6/register/soc/lp_i2c_reg.h diff --git a/components/soc/esp32c6/include/soc/lp_i2c_struct.h b/components/soc/esp32c6/register/soc/lp_i2c_struct.h similarity index 100% rename from components/soc/esp32c6/include/soc/lp_i2c_struct.h rename to components/soc/esp32c6/register/soc/lp_i2c_struct.h diff --git a/components/soc/esp32c6/include/soc/lp_io_reg.h b/components/soc/esp32c6/register/soc/lp_io_reg.h similarity index 100% rename from components/soc/esp32c6/include/soc/lp_io_reg.h rename to components/soc/esp32c6/register/soc/lp_io_reg.h diff --git a/components/soc/esp32c6/include/soc/lp_io_struct.h b/components/soc/esp32c6/register/soc/lp_io_struct.h similarity index 100% rename from components/soc/esp32c6/include/soc/lp_io_struct.h rename to components/soc/esp32c6/register/soc/lp_io_struct.h diff --git a/components/soc/esp32c6/include/soc/lp_tee_reg.h b/components/soc/esp32c6/register/soc/lp_tee_reg.h similarity index 100% rename from components/soc/esp32c6/include/soc/lp_tee_reg.h rename to components/soc/esp32c6/register/soc/lp_tee_reg.h diff --git a/components/soc/esp32c6/include/soc/lp_tee_struct.h b/components/soc/esp32c6/register/soc/lp_tee_struct.h similarity index 100% rename from components/soc/esp32c6/include/soc/lp_tee_struct.h rename to components/soc/esp32c6/register/soc/lp_tee_struct.h diff --git a/components/soc/esp32c6/include/soc/lp_timer_reg.h b/components/soc/esp32c6/register/soc/lp_timer_reg.h similarity index 100% rename from components/soc/esp32c6/include/soc/lp_timer_reg.h rename to components/soc/esp32c6/register/soc/lp_timer_reg.h diff --git a/components/soc/esp32c6/include/soc/lp_timer_struct.h b/components/soc/esp32c6/register/soc/lp_timer_struct.h similarity index 100% rename from components/soc/esp32c6/include/soc/lp_timer_struct.h rename to components/soc/esp32c6/register/soc/lp_timer_struct.h diff --git a/components/soc/esp32c6/include/soc/lp_uart_reg.h b/components/soc/esp32c6/register/soc/lp_uart_reg.h similarity index 99% rename from components/soc/esp32c6/include/soc/lp_uart_reg.h rename to components/soc/esp32c6/register/soc/lp_uart_reg.h index b67fa1b59e8..017abf55f8e 100644 --- a/components/soc/esp32c6/include/soc/lp_uart_reg.h +++ b/components/soc/esp32c6/register/soc/lp_uart_reg.h @@ -100,7 +100,7 @@ extern "C" { #define LP_UART_RXFIFO_TOUT_INT_RAW_V 0x00000001U #define LP_UART_RXFIFO_TOUT_INT_RAW_S 8 /** LP_UART_SW_XON_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; - * This interrupt raw bit turns to high level when receiver recevies Xon char when + * This interrupt raw bit turns to high level when receiver receives Xon char when * uart_sw_flow_con_en is set to 1. */ #define LP_UART_SW_XON_INT_RAW (BIT(9)) @@ -261,7 +261,7 @@ extern "C" { #define LP_UART_TX_BRK_DONE_INT_ST_V 0x00000001U #define LP_UART_TX_BRK_DONE_INT_ST_S 12 /** LP_UART_TX_BRK_IDLE_DONE_INT_ST : RO; bitpos: [13]; default: 0; - * This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena + * This is the status bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena * is set to 1. */ #define LP_UART_TX_BRK_IDLE_DONE_INT_ST (BIT(13)) @@ -671,7 +671,7 @@ extern "C" { #define LP_UART_STOP_BIT_NUM_V 0x00000003U #define LP_UART_STOP_BIT_NUM_S 4 /** LP_UART_TXD_BRK : R/W; bitpos: [6]; default: 0; - * Set this bit to enbale transmitter to send NULL when the process of sending data + * Set this bit to enable transmitter to send NULL when the process of sending data * is done. */ #define LP_UART_TXD_BRK (BIT(6)) @@ -1151,7 +1151,7 @@ extern "C" { */ #define LP_UART_TOUT_CONF_SYNC_REG (DR_REG_LP_UART_BASE + 0x64) /** LP_UART_RX_TOUT_EN : R/W; bitpos: [0]; default: 0; - * This is the enble bit for uart receiver's timeout function. + * This is the enable bit for uart receiver's timeout function. */ #define LP_UART_RX_TOUT_EN (BIT(0)) #define LP_UART_RX_TOUT_EN_M (LP_UART_RX_TOUT_EN_V << LP_UART_RX_TOUT_EN_S) diff --git a/components/soc/esp32c6/include/soc/lp_uart_struct.h b/components/soc/esp32c6/register/soc/lp_uart_struct.h similarity index 99% rename from components/soc/esp32c6/include/soc/lp_uart_struct.h rename to components/soc/esp32c6/register/soc/lp_uart_struct.h index 122c7d920a9..bc9993276f3 100644 --- a/components/soc/esp32c6/include/soc/lp_uart_struct.h +++ b/components/soc/esp32c6/register/soc/lp_uart_struct.h @@ -49,7 +49,7 @@ typedef union { typedef union { struct { /** rx_tout_en : R/W; bitpos: [0]; default: 0; - * This is the enble bit for uart receiver's timeout function. + * This is the enable bit for uart receiver's timeout function. */ uint32_t rx_tout_en:1; /** rx_tout_flow_dis : R/W; bitpos: [1]; default: 0; @@ -120,7 +120,7 @@ typedef union { */ uint32_t rxfifo_tout:1; /** sw_xon : R/WTC/SS; bitpos: [9]; default: 0; - * This interrupt raw bit turns to high level when receiver recevies Xon char when + * This interrupt raw bit turns to high level when receiver receives Xon char when * uart_sw_flow_con_en is set to 1. */ uint32_t sw_xon:1; @@ -224,7 +224,7 @@ typedef union { */ uint32_t tx_brk_done:1; /** tx_brk_idle_done : RO; bitpos: [13]; default: 0; - * This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena + * This is the status bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena * is set to 1. */ uint32_t tx_brk_idle_done:1; @@ -466,7 +466,7 @@ typedef union { */ uint32_t stop_bit_num:2; /** txd_brk : R/W; bitpos: [6]; default: 0; - * Set this bit to enbale transmitter to send NULL when the process of sending data + * Set this bit to enable transmitter to send NULL when the process of sending data * is done. */ uint32_t txd_brk:1; @@ -1115,7 +1115,7 @@ typedef struct lp_uart_dev_t { volatile lp_uart_id_reg_t id; } lp_uart_dev_t; -// We map the LP_UART instance to the uart_dev_t struct for convinience of using the same HAL/LL. See soc/uart_struct.h +// We map the LP_UART instance to the uart_dev_t struct for convenience of using the same HAL/LL. See soc/uart_struct.h // extern lp_uart_dev_t LP_UART; #ifndef __cplusplus diff --git a/components/soc/esp32c6/include/soc/lp_wdt_reg.h b/components/soc/esp32c6/register/soc/lp_wdt_reg.h similarity index 100% rename from components/soc/esp32c6/include/soc/lp_wdt_reg.h rename to components/soc/esp32c6/register/soc/lp_wdt_reg.h diff --git a/components/soc/esp32c6/include/soc/lp_wdt_struct.h b/components/soc/esp32c6/register/soc/lp_wdt_struct.h similarity index 100% rename from components/soc/esp32c6/include/soc/lp_wdt_struct.h rename to components/soc/esp32c6/register/soc/lp_wdt_struct.h diff --git a/components/soc/esp32c6/include/soc/lpperi_reg.h b/components/soc/esp32c6/register/soc/lpperi_reg.h similarity index 100% rename from components/soc/esp32c6/include/soc/lpperi_reg.h rename to components/soc/esp32c6/register/soc/lpperi_reg.h diff --git a/components/soc/esp32c6/include/soc/lpperi_struct.h b/components/soc/esp32c6/register/soc/lpperi_struct.h similarity index 100% rename from components/soc/esp32c6/include/soc/lpperi_struct.h rename to components/soc/esp32c6/register/soc/lpperi_struct.h diff --git a/components/soc/esp32c6/include/soc/mcpwm_reg.h b/components/soc/esp32c6/register/soc/mcpwm_reg.h similarity index 99% rename from components/soc/esp32c6/include/soc/mcpwm_reg.h rename to components/soc/esp32c6/register/soc/mcpwm_reg.h index 4eacabbc9c5..4de6f5b9f7f 100644 --- a/components/soc/esp32c6/include/soc/mcpwm_reg.h +++ b/components/soc/esp32c6/register/soc/mcpwm_reg.h @@ -894,7 +894,7 @@ extern "C" { #define MCPWM_DB0_RED_S 0 /** MCPWM_CARRIER0_CFG_REG register - * Carrier enable and configuratoin + * Carrier enable and configuration */ #define MCPWM_CARRIER0_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x64) /** MCPWM_CHOPPER0_EN : R/W; bitpos: [0]; default: 0; @@ -1575,7 +1575,7 @@ extern "C" { #define MCPWM_DB1_RED_S 0 /** MCPWM_CARRIER1_CFG_REG register - * Carrier enable and configuratoin + * Carrier enable and configuration */ #define MCPWM_CARRIER1_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x9c) /** MCPWM_CHOPPER1_EN : R/W; bitpos: [0]; default: 0; @@ -2256,7 +2256,7 @@ extern "C" { #define MCPWM_DB2_RED_S 0 /** MCPWM_CARRIER2_CFG_REG register - * Carrier enable and configuratoin + * Carrier enable and configuration */ #define MCPWM_CARRIER2_CFG_REG(i) (REG_MCPWM_BASE(i) + 0xd4) /** MCPWM_CHOPPER2_EN : R/W; bitpos: [0]; default: 0; @@ -2621,7 +2621,7 @@ extern "C" { #define MCPWM_CAP0_MODE_V 0x00000003U #define MCPWM_CAP0_MODE_S 1 /** MCPWM_CAP0_PRESCALE : R/W; bitpos: [10:3]; default: 0; - * Value of prescaling on possitive edge of CAP0. Prescale value = PWM_CAP0_PRESCALE + + * Value of prescaling on positive edge of CAP0. Prescale value = PWM_CAP0_PRESCALE + * 1 */ #define MCPWM_CAP0_PRESCALE 0x000000FFU @@ -2664,7 +2664,7 @@ extern "C" { #define MCPWM_CAP1_MODE_V 0x00000003U #define MCPWM_CAP1_MODE_S 1 /** MCPWM_CAP1_PRESCALE : R/W; bitpos: [10:3]; default: 0; - * Value of prescaling on possitive edge of CAP1. Prescale value = PWM_CAP1_PRESCALE + + * Value of prescaling on positive edge of CAP1. Prescale value = PWM_CAP1_PRESCALE + * 1 */ #define MCPWM_CAP1_PRESCALE 0x000000FFU @@ -2707,7 +2707,7 @@ extern "C" { #define MCPWM_CAP2_MODE_V 0x00000003U #define MCPWM_CAP2_MODE_S 1 /** MCPWM_CAP2_PRESCALE : R/W; bitpos: [10:3]; default: 0; - * Value of prescaling on possitive edge of CAP2. Prescale value = PWM_CAP2_PRESCALE + + * Value of prescaling on positive edge of CAP2. Prescale value = PWM_CAP2_PRESCALE + * 1 */ #define MCPWM_CAP2_PRESCALE 0x000000FFU diff --git a/components/soc/esp32c6/include/soc/mcpwm_struct.h b/components/soc/esp32c6/register/soc/mcpwm_struct.h similarity index 99% rename from components/soc/esp32c6/include/soc/mcpwm_struct.h rename to components/soc/esp32c6/register/soc/mcpwm_struct.h index 1a91a623f6b..5fe75f3c99e 100644 --- a/components/soc/esp32c6/include/soc/mcpwm_struct.h +++ b/components/soc/esp32c6/register/soc/mcpwm_struct.h @@ -462,7 +462,7 @@ typedef union { } mcpwm_dt_red_cfg_reg_t; /** Type of carrier_cfg register - * Carrier enable and configuratoin + * Carrier enable and configuration */ typedef union { struct { @@ -734,7 +734,7 @@ typedef union { */ uint32_t capn_mode:2; /** capn_prescale : R/W; bitpos: [10:3]; default: 0; - * Value of prescaling on possitive edge of CAPn. Prescale value = PWM_CAP0_PRESCALE + + * Value of prescaling on positive edge of CAPn. Prescale value = PWM_CAP0_PRESCALE + * 1 */ uint32_t capn_prescale:8; diff --git a/components/soc/esp32c6/include/soc/mem_monitor_reg.h b/components/soc/esp32c6/register/soc/mem_monitor_reg.h similarity index 98% rename from components/soc/esp32c6/include/soc/mem_monitor_reg.h rename to components/soc/esp32c6/register/soc/mem_monitor_reg.h index fccde61ad72..b75a52af212 100644 --- a/components/soc/esp32c6/include/soc/mem_monitor_reg.h +++ b/components/soc/esp32c6/register/soc/mem_monitor_reg.h @@ -12,7 +12,7 @@ extern "C" { #endif /** MEM_MONITOR_LOG_SETTING_REG register - * log config regsiter + * log config register */ #define MEM_MONITOR_LOG_SETTING_REG (DR_REG_MEM_MONITOR_BASE + 0x0) /** MEM_MONITOR_LOG_ENA : R/W; bitpos: [2:0]; default: 0; @@ -39,7 +39,7 @@ extern "C" { #define MEM_MONITOR_LOG_MEM_LOOP_ENABLE_S 7 /** MEM_MONITOR_LOG_CHECK_DATA_REG register - * check data regsiter + * check data register */ #define MEM_MONITOR_LOG_CHECK_DATA_REG (DR_REG_MEM_MONITOR_BASE + 0x4) /** MEM_MONITOR_LOG_CHECK_DATA : R/W; bitpos: [31:0]; default: 0; @@ -64,7 +64,7 @@ extern "C" { #define MEM_MONITOR_LOG_DATA_MASK_S 0 /** MEM_MONITOR_LOG_MIN_REG register - * log boundary regsiter + * log boundary register */ #define MEM_MONITOR_LOG_MIN_REG (DR_REG_MEM_MONITOR_BASE + 0xc) /** MEM_MONITOR_LOG_MIN : R/W; bitpos: [31:0]; default: 0; @@ -76,7 +76,7 @@ extern "C" { #define MEM_MONITOR_LOG_MIN_S 0 /** MEM_MONITOR_LOG_MAX_REG register - * log boundary regsiter + * log boundary register */ #define MEM_MONITOR_LOG_MAX_REG (DR_REG_MEM_MONITOR_BASE + 0x10) /** MEM_MONITOR_LOG_MAX : R/W; bitpos: [31:0]; default: 0; diff --git a/components/soc/esp32c6/include/soc/mem_monitor_struct.h b/components/soc/esp32c6/register/soc/mem_monitor_struct.h similarity index 98% rename from components/soc/esp32c6/include/soc/mem_monitor_struct.h rename to components/soc/esp32c6/register/soc/mem_monitor_struct.h index 6fd735edf54..862959b9494 100644 --- a/components/soc/esp32c6/include/soc/mem_monitor_struct.h +++ b/components/soc/esp32c6/register/soc/mem_monitor_struct.h @@ -12,7 +12,7 @@ extern "C" { /** Group: configuration registers */ /** Type of log_setting register - * log config regsiter + * log config register */ typedef union { struct { @@ -35,7 +35,7 @@ typedef union { } mem_monitor_log_setting_reg_t; /** Type of log_check_data register - * check data regsiter + * check data register */ typedef union { struct { @@ -63,7 +63,7 @@ typedef union { } mem_monitor_log_data_mask_reg_t; /** Type of log_min register - * log boundary regsiter + * log boundary register */ typedef union { struct { @@ -76,7 +76,7 @@ typedef union { } mem_monitor_log_min_reg_t; /** Type of log_max register - * log boundary regsiter + * log boundary register */ typedef union { struct { diff --git a/components/soc/esp32c6/include/soc/otp_debug_reg.h b/components/soc/esp32c6/register/soc/otp_debug_reg.h similarity index 91% rename from components/soc/esp32c6/include/soc/otp_debug_reg.h rename to components/soc/esp32c6/register/soc/otp_debug_reg.h index 6d0e84c69f1..49d1754d4f5 100644 --- a/components/soc/esp32c6/include/soc/otp_debug_reg.h +++ b/components/soc/esp32c6/register/soc/otp_debug_reg.h @@ -12,7 +12,7 @@ extern "C" { #endif /** OTP_DEBUG_WR_DIS_REG register - * Otp debuger block0 data register1. + * Otp debugger block0 data register1. */ #define OTP_DEBUG_WR_DIS_REG (DR_REG_OTP_DEBUG_BASE + 0x0) /** OTP_DEBUG_BLOCK0_WR_DIS : RO; bitpos: [31:0]; default: 0; @@ -24,7 +24,7 @@ extern "C" { #define OTP_DEBUG_BLOCK0_WR_DIS_S 0 /** OTP_DEBUG_BLK0_BACKUP1_W1_REG register - * Otp debuger block0 data register2. + * Otp debugger block0 data register2. */ #define OTP_DEBUG_BLK0_BACKUP1_W1_REG (DR_REG_OTP_DEBUG_BASE + 0x4) /** OTP_DEBUG_BLOCK0_BACKUP1_W1 : RO; bitpos: [31:0]; default: 0; @@ -36,7 +36,7 @@ extern "C" { #define OTP_DEBUG_BLOCK0_BACKUP1_W1_S 0 /** OTP_DEBUG_BLK0_BACKUP1_W2_REG register - * Otp debuger block0 data register3. + * Otp debugger block0 data register3. */ #define OTP_DEBUG_BLK0_BACKUP1_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x8) /** OTP_DEBUG_BLOCK0_BACKUP1_W2 : RO; bitpos: [31:0]; default: 0; @@ -48,7 +48,7 @@ extern "C" { #define OTP_DEBUG_BLOCK0_BACKUP1_W2_S 0 /** OTP_DEBUG_BLK0_BACKUP1_W3_REG register - * Otp debuger block0 data register4. + * Otp debugger block0 data register4. */ #define OTP_DEBUG_BLK0_BACKUP1_W3_REG (DR_REG_OTP_DEBUG_BASE + 0xc) /** OTP_DEBUG_BLOCK0_BACKUP1_W3 : RO; bitpos: [31:0]; default: 0; @@ -60,7 +60,7 @@ extern "C" { #define OTP_DEBUG_BLOCK0_BACKUP1_W3_S 0 /** OTP_DEBUG_BLK0_BACKUP1_W4_REG register - * Otp debuger block0 data register5. + * Otp debugger block0 data register5. */ #define OTP_DEBUG_BLK0_BACKUP1_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x10) /** OTP_DEBUG_BLOCK0_BACKUP1_W4 : RO; bitpos: [31:0]; default: 0; @@ -72,7 +72,7 @@ extern "C" { #define OTP_DEBUG_BLOCK0_BACKUP1_W4_S 0 /** OTP_DEBUG_BLK0_BACKUP1_W5_REG register - * Otp debuger block0 data register6. + * Otp debugger block0 data register6. */ #define OTP_DEBUG_BLK0_BACKUP1_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x14) /** OTP_DEBUG_BLOCK0_BACKUP1_W5 : RO; bitpos: [31:0]; default: 0; @@ -84,7 +84,7 @@ extern "C" { #define OTP_DEBUG_BLOCK0_BACKUP1_W5_S 0 /** OTP_DEBUG_BLK0_BACKUP2_W1_REG register - * Otp debuger block0 data register7. + * Otp debugger block0 data register7. */ #define OTP_DEBUG_BLK0_BACKUP2_W1_REG (DR_REG_OTP_DEBUG_BASE + 0x18) /** OTP_DEBUG_BLOCK0_BACKUP2_W1 : RO; bitpos: [31:0]; default: 0; @@ -96,7 +96,7 @@ extern "C" { #define OTP_DEBUG_BLOCK0_BACKUP2_W1_S 0 /** OTP_DEBUG_BLK0_BACKUP2_W2_REG register - * Otp debuger block0 data register8. + * Otp debugger block0 data register8. */ #define OTP_DEBUG_BLK0_BACKUP2_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x1c) /** OTP_DEBUG_BLOCK0_BACKUP2_W2 : RO; bitpos: [31:0]; default: 0; @@ -108,7 +108,7 @@ extern "C" { #define OTP_DEBUG_BLOCK0_BACKUP2_W2_S 0 /** OTP_DEBUG_BLK0_BACKUP2_W3_REG register - * Otp debuger block0 data register9. + * Otp debugger block0 data register9. */ #define OTP_DEBUG_BLK0_BACKUP2_W3_REG (DR_REG_OTP_DEBUG_BASE + 0x20) /** OTP_DEBUG_BLOCK0_BACKUP2_W3 : RO; bitpos: [31:0]; default: 0; @@ -120,7 +120,7 @@ extern "C" { #define OTP_DEBUG_BLOCK0_BACKUP2_W3_S 0 /** OTP_DEBUG_BLK0_BACKUP2_W4_REG register - * Otp debuger block0 data register10. + * Otp debugger block0 data register10. */ #define OTP_DEBUG_BLK0_BACKUP2_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x24) /** OTP_DEBUG_BLOCK0_BACKUP2_W4 : RO; bitpos: [31:0]; default: 0; @@ -132,7 +132,7 @@ extern "C" { #define OTP_DEBUG_BLOCK0_BACKUP2_W4_S 0 /** OTP_DEBUG_BLK0_BACKUP2_W5_REG register - * Otp debuger block0 data register11. + * Otp debugger block0 data register11. */ #define OTP_DEBUG_BLK0_BACKUP2_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x28) /** OTP_DEBUG_BLOCK0_BACKUP2_W5 : RO; bitpos: [31:0]; default: 0; @@ -144,7 +144,7 @@ extern "C" { #define OTP_DEBUG_BLOCK0_BACKUP2_W5_S 0 /** OTP_DEBUG_BLK0_BACKUP3_W1_REG register - * Otp debuger block0 data register12. + * Otp debugger block0 data register12. */ #define OTP_DEBUG_BLK0_BACKUP3_W1_REG (DR_REG_OTP_DEBUG_BASE + 0x2c) /** OTP_DEBUG_BLOCK0_BACKUP3_W1 : RO; bitpos: [31:0]; default: 0; @@ -156,7 +156,7 @@ extern "C" { #define OTP_DEBUG_BLOCK0_BACKUP3_W1_S 0 /** OTP_DEBUG_BLK0_BACKUP3_W2_REG register - * Otp debuger block0 data register13. + * Otp debugger block0 data register13. */ #define OTP_DEBUG_BLK0_BACKUP3_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x30) /** OTP_DEBUG_BLOCK0_BACKUP3_W2 : RO; bitpos: [31:0]; default: 0; @@ -168,7 +168,7 @@ extern "C" { #define OTP_DEBUG_BLOCK0_BACKUP3_W2_S 0 /** OTP_DEBUG_BLK0_BACKUP3_W3_REG register - * Otp debuger block0 data register14. + * Otp debugger block0 data register14. */ #define OTP_DEBUG_BLK0_BACKUP3_W3_REG (DR_REG_OTP_DEBUG_BASE + 0x34) /** OTP_DEBUG_BLOCK0_BACKUP3_W3 : RO; bitpos: [31:0]; default: 0; @@ -180,7 +180,7 @@ extern "C" { #define OTP_DEBUG_BLOCK0_BACKUP3_W3_S 0 /** OTP_DEBUG_BLK0_BACKUP3_W4_REG register - * Otp debuger block0 data register15. + * Otp debugger block0 data register15. */ #define OTP_DEBUG_BLK0_BACKUP3_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x38) /** OTP_DEBUG_BLOCK0_BACKUP3_W4 : RO; bitpos: [31:0]; default: 0; @@ -192,7 +192,7 @@ extern "C" { #define OTP_DEBUG_BLOCK0_BACKUP3_W4_S 0 /** OTP_DEBUG_BLK0_BACKUP3_W5_REG register - * Otp debuger block0 data register16. + * Otp debugger block0 data register16. */ #define OTP_DEBUG_BLK0_BACKUP3_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x3c) /** OTP_DEBUG_BLOCK0_BACKUP3_W5 : RO; bitpos: [31:0]; default: 0; @@ -204,7 +204,7 @@ extern "C" { #define OTP_DEBUG_BLOCK0_BACKUP3_W5_S 0 /** OTP_DEBUG_BLK0_BACKUP4_W1_REG register - * Otp debuger block0 data register17. + * Otp debugger block0 data register17. */ #define OTP_DEBUG_BLK0_BACKUP4_W1_REG (DR_REG_OTP_DEBUG_BASE + 0x40) /** OTP_DEBUG_BLOCK0_BACKUP4_W1 : RO; bitpos: [31:0]; default: 0; @@ -216,7 +216,7 @@ extern "C" { #define OTP_DEBUG_BLOCK0_BACKUP4_W1_S 0 /** OTP_DEBUG_BLK0_BACKUP4_W2_REG register - * Otp debuger block0 data register18. + * Otp debugger block0 data register18. */ #define OTP_DEBUG_BLK0_BACKUP4_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x44) /** OTP_DEBUG_BLOCK0_BACKUP4_W2 : RO; bitpos: [31:0]; default: 0; @@ -228,7 +228,7 @@ extern "C" { #define OTP_DEBUG_BLOCK0_BACKUP4_W2_S 0 /** OTP_DEBUG_BLK0_BACKUP4_W3_REG register - * Otp debuger block0 data register19. + * Otp debugger block0 data register19. */ #define OTP_DEBUG_BLK0_BACKUP4_W3_REG (DR_REG_OTP_DEBUG_BASE + 0x48) /** OTP_DEBUG_BLOCK0_BACKUP4_W3 : RO; bitpos: [31:0]; default: 0; @@ -240,7 +240,7 @@ extern "C" { #define OTP_DEBUG_BLOCK0_BACKUP4_W3_S 0 /** OTP_DEBUG_BLK0_BACKUP4_W4_REG register - * Otp debuger block0 data register20. + * Otp debugger block0 data register20. */ #define OTP_DEBUG_BLK0_BACKUP4_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x4c) /** OTP_DEBUG_BLOCK0_BACKUP4_W4 : RO; bitpos: [31:0]; default: 0; @@ -252,7 +252,7 @@ extern "C" { #define OTP_DEBUG_BLOCK0_BACKUP4_W4_S 0 /** OTP_DEBUG_BLK0_BACKUP4_W5_REG register - * Otp debuger block0 data register21. + * Otp debugger block0 data register21. */ #define OTP_DEBUG_BLK0_BACKUP4_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x50) /** OTP_DEBUG_BLOCK0_BACKUP4_W5 : RO; bitpos: [31:0]; default: 0; @@ -264,7 +264,7 @@ extern "C" { #define OTP_DEBUG_BLOCK0_BACKUP4_W5_S 0 /** OTP_DEBUG_BLK1_W1_REG register - * Otp debuger block1 data register1. + * Otp debugger block1 data register1. */ #define OTP_DEBUG_BLK1_W1_REG (DR_REG_OTP_DEBUG_BASE + 0x54) /** OTP_DEBUG_BLOCK1_W1 : RO; bitpos: [31:0]; default: 0; @@ -276,7 +276,7 @@ extern "C" { #define OTP_DEBUG_BLOCK1_W1_S 0 /** OTP_DEBUG_BLK1_W2_REG register - * Otp debuger block1 data register2. + * Otp debugger block1 data register2. */ #define OTP_DEBUG_BLK1_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x58) /** OTP_DEBUG_BLOCK1_W2 : RO; bitpos: [31:0]; default: 0; @@ -288,7 +288,7 @@ extern "C" { #define OTP_DEBUG_BLOCK1_W2_S 0 /** OTP_DEBUG_BLK1_W3_REG register - * Otp debuger block1 data register3. + * Otp debugger block1 data register3. */ #define OTP_DEBUG_BLK1_W3_REG (DR_REG_OTP_DEBUG_BASE + 0x5c) /** OTP_DEBUG_BLOCK1_W3 : RO; bitpos: [31:0]; default: 0; @@ -300,7 +300,7 @@ extern "C" { #define OTP_DEBUG_BLOCK1_W3_S 0 /** OTP_DEBUG_BLK1_W4_REG register - * Otp debuger block1 data register4. + * Otp debugger block1 data register4. */ #define OTP_DEBUG_BLK1_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x60) /** OTP_DEBUG_BLOCK1_W4 : RO; bitpos: [31:0]; default: 0; @@ -312,7 +312,7 @@ extern "C" { #define OTP_DEBUG_BLOCK1_W4_S 0 /** OTP_DEBUG_BLK1_W5_REG register - * Otp debuger block1 data register5. + * Otp debugger block1 data register5. */ #define OTP_DEBUG_BLK1_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x64) /** OTP_DEBUG_BLOCK1_W5 : RO; bitpos: [31:0]; default: 0; @@ -324,7 +324,7 @@ extern "C" { #define OTP_DEBUG_BLOCK1_W5_S 0 /** OTP_DEBUG_BLK1_W6_REG register - * Otp debuger block1 data register6. + * Otp debugger block1 data register6. */ #define OTP_DEBUG_BLK1_W6_REG (DR_REG_OTP_DEBUG_BASE + 0x68) /** OTP_DEBUG_BLOCK1_W6 : RO; bitpos: [31:0]; default: 0; @@ -336,7 +336,7 @@ extern "C" { #define OTP_DEBUG_BLOCK1_W6_S 0 /** OTP_DEBUG_BLK1_W7_REG register - * Otp debuger block1 data register7. + * Otp debugger block1 data register7. */ #define OTP_DEBUG_BLK1_W7_REG (DR_REG_OTP_DEBUG_BASE + 0x6c) /** OTP_DEBUG_BLOCK1_W7 : RO; bitpos: [31:0]; default: 0; @@ -348,7 +348,7 @@ extern "C" { #define OTP_DEBUG_BLOCK1_W7_S 0 /** OTP_DEBUG_BLK1_W8_REG register - * Otp debuger block1 data register8. + * Otp debugger block1 data register8. */ #define OTP_DEBUG_BLK1_W8_REG (DR_REG_OTP_DEBUG_BASE + 0x70) /** OTP_DEBUG_BLOCK1_W8 : RO; bitpos: [31:0]; default: 0; @@ -360,7 +360,7 @@ extern "C" { #define OTP_DEBUG_BLOCK1_W8_S 0 /** OTP_DEBUG_BLK1_W9_REG register - * Otp debuger block1 data register9. + * Otp debugger block1 data register9. */ #define OTP_DEBUG_BLK1_W9_REG (DR_REG_OTP_DEBUG_BASE + 0x74) /** OTP_DEBUG_BLOCK1_W9 : RO; bitpos: [31:0]; default: 0; @@ -372,7 +372,7 @@ extern "C" { #define OTP_DEBUG_BLOCK1_W9_S 0 /** OTP_DEBUG_BLK2_W1_REG register - * Otp debuger block2 data register1. + * Otp debugger block2 data register1. */ #define OTP_DEBUG_BLK2_W1_REG (DR_REG_OTP_DEBUG_BASE + 0x78) /** OTP_DEBUG_BLOCK2_W1 : RO; bitpos: [31:0]; default: 0; @@ -384,7 +384,7 @@ extern "C" { #define OTP_DEBUG_BLOCK2_W1_S 0 /** OTP_DEBUG_BLK2_W2_REG register - * Otp debuger block2 data register2. + * Otp debugger block2 data register2. */ #define OTP_DEBUG_BLK2_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x7c) /** OTP_DEBUG_BLOCK2_W2 : RO; bitpos: [31:0]; default: 0; @@ -396,7 +396,7 @@ extern "C" { #define OTP_DEBUG_BLOCK2_W2_S 0 /** OTP_DEBUG_BLK2_W3_REG register - * Otp debuger block2 data register3. + * Otp debugger block2 data register3. */ #define OTP_DEBUG_BLK2_W3_REG (DR_REG_OTP_DEBUG_BASE + 0x80) /** OTP_DEBUG_BLOCK2_W3 : RO; bitpos: [31:0]; default: 0; @@ -408,7 +408,7 @@ extern "C" { #define OTP_DEBUG_BLOCK2_W3_S 0 /** OTP_DEBUG_BLK2_W4_REG register - * Otp debuger block2 data register4. + * Otp debugger block2 data register4. */ #define OTP_DEBUG_BLK2_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x84) /** OTP_DEBUG_BLOCK2_W4 : RO; bitpos: [31:0]; default: 0; @@ -420,7 +420,7 @@ extern "C" { #define OTP_DEBUG_BLOCK2_W4_S 0 /** OTP_DEBUG_BLK2_W5_REG register - * Otp debuger block2 data register5. + * Otp debugger block2 data register5. */ #define OTP_DEBUG_BLK2_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x88) /** OTP_DEBUG_BLOCK2_W5 : RO; bitpos: [31:0]; default: 0; @@ -432,7 +432,7 @@ extern "C" { #define OTP_DEBUG_BLOCK2_W5_S 0 /** OTP_DEBUG_BLK2_W6_REG register - * Otp debuger block2 data register6. + * Otp debugger block2 data register6. */ #define OTP_DEBUG_BLK2_W6_REG (DR_REG_OTP_DEBUG_BASE + 0x8c) /** OTP_DEBUG_BLOCK2_W6 : RO; bitpos: [31:0]; default: 0; @@ -444,7 +444,7 @@ extern "C" { #define OTP_DEBUG_BLOCK2_W6_S 0 /** OTP_DEBUG_BLK2_W7_REG register - * Otp debuger block2 data register7. + * Otp debugger block2 data register7. */ #define OTP_DEBUG_BLK2_W7_REG (DR_REG_OTP_DEBUG_BASE + 0x90) /** OTP_DEBUG_BLOCK2_W7 : RO; bitpos: [31:0]; default: 0; @@ -456,7 +456,7 @@ extern "C" { #define OTP_DEBUG_BLOCK2_W7_S 0 /** OTP_DEBUG_BLK2_W8_REG register - * Otp debuger block2 data register8. + * Otp debugger block2 data register8. */ #define OTP_DEBUG_BLK2_W8_REG (DR_REG_OTP_DEBUG_BASE + 0x94) /** OTP_DEBUG_BLOCK2_W8 : RO; bitpos: [31:0]; default: 0; @@ -468,7 +468,7 @@ extern "C" { #define OTP_DEBUG_BLOCK2_W8_S 0 /** OTP_DEBUG_BLK2_W9_REG register - * Otp debuger block2 data register9. + * Otp debugger block2 data register9. */ #define OTP_DEBUG_BLK2_W9_REG (DR_REG_OTP_DEBUG_BASE + 0x98) /** OTP_DEBUG_BLOCK2_W9 : RO; bitpos: [31:0]; default: 0; @@ -480,7 +480,7 @@ extern "C" { #define OTP_DEBUG_BLOCK2_W9_S 0 /** OTP_DEBUG_BLK2_W10_REG register - * Otp debuger block2 data register10. + * Otp debugger block2 data register10. */ #define OTP_DEBUG_BLK2_W10_REG (DR_REG_OTP_DEBUG_BASE + 0x9c) /** OTP_DEBUG_BLOCK2_W10 : RO; bitpos: [31:0]; default: 0; @@ -492,7 +492,7 @@ extern "C" { #define OTP_DEBUG_BLOCK2_W10_S 0 /** OTP_DEBUG_BLK2_W11_REG register - * Otp debuger block2 data register11. + * Otp debugger block2 data register11. */ #define OTP_DEBUG_BLK2_W11_REG (DR_REG_OTP_DEBUG_BASE + 0xa0) /** OTP_DEBUG_BLOCK2_W11 : RO; bitpos: [31:0]; default: 0; @@ -504,7 +504,7 @@ extern "C" { #define OTP_DEBUG_BLOCK2_W11_S 0 /** OTP_DEBUG_BLK3_W1_REG register - * Otp debuger block3 data register1. + * Otp debugger block3 data register1. */ #define OTP_DEBUG_BLK3_W1_REG (DR_REG_OTP_DEBUG_BASE + 0xa4) /** OTP_DEBUG_BLOCK3_W1 : RO; bitpos: [31:0]; default: 0; @@ -516,7 +516,7 @@ extern "C" { #define OTP_DEBUG_BLOCK3_W1_S 0 /** OTP_DEBUG_BLK3_W2_REG register - * Otp debuger block3 data register2. + * Otp debugger block3 data register2. */ #define OTP_DEBUG_BLK3_W2_REG (DR_REG_OTP_DEBUG_BASE + 0xa8) /** OTP_DEBUG_BLOCK3_W2 : RO; bitpos: [31:0]; default: 0; @@ -528,7 +528,7 @@ extern "C" { #define OTP_DEBUG_BLOCK3_W2_S 0 /** OTP_DEBUG_BLK3_W3_REG register - * Otp debuger block3 data register3. + * Otp debugger block3 data register3. */ #define OTP_DEBUG_BLK3_W3_REG (DR_REG_OTP_DEBUG_BASE + 0xac) /** OTP_DEBUG_BLOCK3_W3 : RO; bitpos: [31:0]; default: 0; @@ -540,7 +540,7 @@ extern "C" { #define OTP_DEBUG_BLOCK3_W3_S 0 /** OTP_DEBUG_BLK3_W4_REG register - * Otp debuger block3 data register4. + * Otp debugger block3 data register4. */ #define OTP_DEBUG_BLK3_W4_REG (DR_REG_OTP_DEBUG_BASE + 0xb0) /** OTP_DEBUG_BLOCK3_W4 : RO; bitpos: [31:0]; default: 0; @@ -552,7 +552,7 @@ extern "C" { #define OTP_DEBUG_BLOCK3_W4_S 0 /** OTP_DEBUG_BLK3_W5_REG register - * Otp debuger block3 data register5. + * Otp debugger block3 data register5. */ #define OTP_DEBUG_BLK3_W5_REG (DR_REG_OTP_DEBUG_BASE + 0xb4) /** OTP_DEBUG_BLOCK3_W5 : RO; bitpos: [31:0]; default: 0; @@ -564,7 +564,7 @@ extern "C" { #define OTP_DEBUG_BLOCK3_W5_S 0 /** OTP_DEBUG_BLK3_W6_REG register - * Otp debuger block3 data register6. + * Otp debugger block3 data register6. */ #define OTP_DEBUG_BLK3_W6_REG (DR_REG_OTP_DEBUG_BASE + 0xb8) /** OTP_DEBUG_BLOCK3_W6 : RO; bitpos: [31:0]; default: 0; @@ -576,7 +576,7 @@ extern "C" { #define OTP_DEBUG_BLOCK3_W6_S 0 /** OTP_DEBUG_BLK3_W7_REG register - * Otp debuger block3 data register7. + * Otp debugger block3 data register7. */ #define OTP_DEBUG_BLK3_W7_REG (DR_REG_OTP_DEBUG_BASE + 0xbc) /** OTP_DEBUG_BLOCK3_W7 : RO; bitpos: [31:0]; default: 0; @@ -588,7 +588,7 @@ extern "C" { #define OTP_DEBUG_BLOCK3_W7_S 0 /** OTP_DEBUG_BLK3_W8_REG register - * Otp debuger block3 data register8. + * Otp debugger block3 data register8. */ #define OTP_DEBUG_BLK3_W8_REG (DR_REG_OTP_DEBUG_BASE + 0xc0) /** OTP_DEBUG_BLOCK3_W8 : RO; bitpos: [31:0]; default: 0; @@ -600,7 +600,7 @@ extern "C" { #define OTP_DEBUG_BLOCK3_W8_S 0 /** OTP_DEBUG_BLK3_W9_REG register - * Otp debuger block3 data register9. + * Otp debugger block3 data register9. */ #define OTP_DEBUG_BLK3_W9_REG (DR_REG_OTP_DEBUG_BASE + 0xc4) /** OTP_DEBUG_BLOCK3_W9 : RO; bitpos: [31:0]; default: 0; @@ -612,7 +612,7 @@ extern "C" { #define OTP_DEBUG_BLOCK3_W9_S 0 /** OTP_DEBUG_BLK3_W10_REG register - * Otp debuger block3 data register10. + * Otp debugger block3 data register10. */ #define OTP_DEBUG_BLK3_W10_REG (DR_REG_OTP_DEBUG_BASE + 0xc8) /** OTP_DEBUG_BLOCK3_W10 : RO; bitpos: [31:0]; default: 0; @@ -624,7 +624,7 @@ extern "C" { #define OTP_DEBUG_BLOCK3_W10_S 0 /** OTP_DEBUG_BLK3_W11_REG register - * Otp debuger block3 data register11. + * Otp debugger block3 data register11. */ #define OTP_DEBUG_BLK3_W11_REG (DR_REG_OTP_DEBUG_BASE + 0xcc) /** OTP_DEBUG_BLOCK3_W11 : RO; bitpos: [31:0]; default: 0; @@ -636,7 +636,7 @@ extern "C" { #define OTP_DEBUG_BLOCK3_W11_S 0 /** OTP_DEBUG_BLK4_W1_REG register - * Otp debuger block4 data register1. + * Otp debugger block4 data register1. */ #define OTP_DEBUG_BLK4_W1_REG (DR_REG_OTP_DEBUG_BASE + 0xd0) /** OTP_DEBUG_BLOCK4_W1 : RO; bitpos: [31:0]; default: 0; @@ -648,7 +648,7 @@ extern "C" { #define OTP_DEBUG_BLOCK4_W1_S 0 /** OTP_DEBUG_BLK4_W2_REG register - * Otp debuger block4 data register2. + * Otp debugger block4 data register2. */ #define OTP_DEBUG_BLK4_W2_REG (DR_REG_OTP_DEBUG_BASE + 0xd4) /** OTP_DEBUG_BLOCK4_W2 : RO; bitpos: [31:0]; default: 0; @@ -660,7 +660,7 @@ extern "C" { #define OTP_DEBUG_BLOCK4_W2_S 0 /** OTP_DEBUG_BLK4_W3_REG register - * Otp debuger block4 data register3. + * Otp debugger block4 data register3. */ #define OTP_DEBUG_BLK4_W3_REG (DR_REG_OTP_DEBUG_BASE + 0xd8) /** OTP_DEBUG_BLOCK4_W3 : RO; bitpos: [31:0]; default: 0; @@ -672,7 +672,7 @@ extern "C" { #define OTP_DEBUG_BLOCK4_W3_S 0 /** OTP_DEBUG_BLK4_W4_REG register - * Otp debuger block4 data register4. + * Otp debugger block4 data register4. */ #define OTP_DEBUG_BLK4_W4_REG (DR_REG_OTP_DEBUG_BASE + 0xdc) /** OTP_DEBUG_BLOCK4_W4 : RO; bitpos: [31:0]; default: 0; @@ -684,7 +684,7 @@ extern "C" { #define OTP_DEBUG_BLOCK4_W4_S 0 /** OTP_DEBUG_BLK4_W5_REG register - * Otp debuger block4 data register5. + * Otp debugger block4 data register5. */ #define OTP_DEBUG_BLK4_W5_REG (DR_REG_OTP_DEBUG_BASE + 0xe0) /** OTP_DEBUG_BLOCK4_W5 : RO; bitpos: [31:0]; default: 0; @@ -696,7 +696,7 @@ extern "C" { #define OTP_DEBUG_BLOCK4_W5_S 0 /** OTP_DEBUG_BLK4_W6_REG register - * Otp debuger block4 data register6. + * Otp debugger block4 data register6. */ #define OTP_DEBUG_BLK4_W6_REG (DR_REG_OTP_DEBUG_BASE + 0xe4) /** OTP_DEBUG_BLOCK4_W6 : RO; bitpos: [31:0]; default: 0; @@ -708,7 +708,7 @@ extern "C" { #define OTP_DEBUG_BLOCK4_W6_S 0 /** OTP_DEBUG_BLK4_W7_REG register - * Otp debuger block4 data register7. + * Otp debugger block4 data register7. */ #define OTP_DEBUG_BLK4_W7_REG (DR_REG_OTP_DEBUG_BASE + 0xe8) /** OTP_DEBUG_BLOCK4_W7 : RO; bitpos: [31:0]; default: 0; @@ -720,7 +720,7 @@ extern "C" { #define OTP_DEBUG_BLOCK4_W7_S 0 /** OTP_DEBUG_BLK4_W8_REG register - * Otp debuger block4 data register8. + * Otp debugger block4 data register8. */ #define OTP_DEBUG_BLK4_W8_REG (DR_REG_OTP_DEBUG_BASE + 0xec) /** OTP_DEBUG_BLOCK4_W8 : RO; bitpos: [31:0]; default: 0; @@ -732,7 +732,7 @@ extern "C" { #define OTP_DEBUG_BLOCK4_W8_S 0 /** OTP_DEBUG_BLK4_W9_REG register - * Otp debuger block4 data register9. + * Otp debugger block4 data register9. */ #define OTP_DEBUG_BLK4_W9_REG (DR_REG_OTP_DEBUG_BASE + 0xf0) /** OTP_DEBUG_BLOCK4_W9 : RO; bitpos: [31:0]; default: 0; @@ -744,7 +744,7 @@ extern "C" { #define OTP_DEBUG_BLOCK4_W9_S 0 /** OTP_DEBUG_BLK4_W10_REG register - * Otp debuger block4 data registe10. + * Otp debugger block4 data registe10. */ #define OTP_DEBUG_BLK4_W10_REG (DR_REG_OTP_DEBUG_BASE + 0xf4) /** OTP_DEBUG_BLOCK4_W10 : RO; bitpos: [31:0]; default: 0; @@ -756,7 +756,7 @@ extern "C" { #define OTP_DEBUG_BLOCK4_W10_S 0 /** OTP_DEBUG_BLK4_W11_REG register - * Otp debuger block4 data register11. + * Otp debugger block4 data register11. */ #define OTP_DEBUG_BLK4_W11_REG (DR_REG_OTP_DEBUG_BASE + 0xf8) /** OTP_DEBUG_BLOCK4_W11 : RO; bitpos: [31:0]; default: 0; @@ -768,7 +768,7 @@ extern "C" { #define OTP_DEBUG_BLOCK4_W11_S 0 /** OTP_DEBUG_BLK5_W1_REG register - * Otp debuger block5 data register1. + * Otp debugger block5 data register1. */ #define OTP_DEBUG_BLK5_W1_REG (DR_REG_OTP_DEBUG_BASE + 0xfc) /** OTP_DEBUG_BLOCK5_W1 : RO; bitpos: [31:0]; default: 0; @@ -780,7 +780,7 @@ extern "C" { #define OTP_DEBUG_BLOCK5_W1_S 0 /** OTP_DEBUG_BLK5_W2_REG register - * Otp debuger block5 data register2. + * Otp debugger block5 data register2. */ #define OTP_DEBUG_BLK5_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x100) /** OTP_DEBUG_BLOCK5_W2 : RO; bitpos: [31:0]; default: 0; @@ -792,7 +792,7 @@ extern "C" { #define OTP_DEBUG_BLOCK5_W2_S 0 /** OTP_DEBUG_BLK5_W3_REG register - * Otp debuger block5 data register3. + * Otp debugger block5 data register3. */ #define OTP_DEBUG_BLK5_W3_REG (DR_REG_OTP_DEBUG_BASE + 0x104) /** OTP_DEBUG_BLOCK5_W3 : RO; bitpos: [31:0]; default: 0; @@ -804,7 +804,7 @@ extern "C" { #define OTP_DEBUG_BLOCK5_W3_S 0 /** OTP_DEBUG_BLK5_W4_REG register - * Otp debuger block5 data register4. + * Otp debugger block5 data register4. */ #define OTP_DEBUG_BLK5_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x108) /** OTP_DEBUG_BLOCK5_W4 : RO; bitpos: [31:0]; default: 0; @@ -816,7 +816,7 @@ extern "C" { #define OTP_DEBUG_BLOCK5_W4_S 0 /** OTP_DEBUG_BLK5_W5_REG register - * Otp debuger block5 data register5. + * Otp debugger block5 data register5. */ #define OTP_DEBUG_BLK5_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x10c) /** OTP_DEBUG_BLOCK5_W5 : RO; bitpos: [31:0]; default: 0; @@ -828,7 +828,7 @@ extern "C" { #define OTP_DEBUG_BLOCK5_W5_S 0 /** OTP_DEBUG_BLK5_W6_REG register - * Otp debuger block5 data register6. + * Otp debugger block5 data register6. */ #define OTP_DEBUG_BLK5_W6_REG (DR_REG_OTP_DEBUG_BASE + 0x110) /** OTP_DEBUG_BLOCK5_W6 : RO; bitpos: [31:0]; default: 0; @@ -840,7 +840,7 @@ extern "C" { #define OTP_DEBUG_BLOCK5_W6_S 0 /** OTP_DEBUG_BLK5_W7_REG register - * Otp debuger block5 data register7. + * Otp debugger block5 data register7. */ #define OTP_DEBUG_BLK5_W7_REG (DR_REG_OTP_DEBUG_BASE + 0x114) /** OTP_DEBUG_BLOCK5_W7 : RO; bitpos: [31:0]; default: 0; @@ -852,7 +852,7 @@ extern "C" { #define OTP_DEBUG_BLOCK5_W7_S 0 /** OTP_DEBUG_BLK5_W8_REG register - * Otp debuger block5 data register8. + * Otp debugger block5 data register8. */ #define OTP_DEBUG_BLK5_W8_REG (DR_REG_OTP_DEBUG_BASE + 0x118) /** OTP_DEBUG_BLOCK5_W8 : RO; bitpos: [31:0]; default: 0; @@ -864,7 +864,7 @@ extern "C" { #define OTP_DEBUG_BLOCK5_W8_S 0 /** OTP_DEBUG_BLK5_W9_REG register - * Otp debuger block5 data register9. + * Otp debugger block5 data register9. */ #define OTP_DEBUG_BLK5_W9_REG (DR_REG_OTP_DEBUG_BASE + 0x11c) /** OTP_DEBUG_BLOCK5_W9 : RO; bitpos: [31:0]; default: 0; @@ -876,7 +876,7 @@ extern "C" { #define OTP_DEBUG_BLOCK5_W9_S 0 /** OTP_DEBUG_BLK5_W10_REG register - * Otp debuger block5 data register10. + * Otp debugger block5 data register10. */ #define OTP_DEBUG_BLK5_W10_REG (DR_REG_OTP_DEBUG_BASE + 0x120) /** OTP_DEBUG_BLOCK5_W10 : RO; bitpos: [31:0]; default: 0; @@ -888,7 +888,7 @@ extern "C" { #define OTP_DEBUG_BLOCK5_W10_S 0 /** OTP_DEBUG_BLK5_W11_REG register - * Otp debuger block5 data register11. + * Otp debugger block5 data register11. */ #define OTP_DEBUG_BLK5_W11_REG (DR_REG_OTP_DEBUG_BASE + 0x124) /** OTP_DEBUG_BLOCK5_W11 : RO; bitpos: [31:0]; default: 0; @@ -900,7 +900,7 @@ extern "C" { #define OTP_DEBUG_BLOCK5_W11_S 0 /** OTP_DEBUG_BLK6_W1_REG register - * Otp debuger block6 data register1. + * Otp debugger block6 data register1. */ #define OTP_DEBUG_BLK6_W1_REG (DR_REG_OTP_DEBUG_BASE + 0x128) /** OTP_DEBUG_BLOCK6_W1 : RO; bitpos: [31:0]; default: 0; @@ -912,7 +912,7 @@ extern "C" { #define OTP_DEBUG_BLOCK6_W1_S 0 /** OTP_DEBUG_BLK6_W2_REG register - * Otp debuger block6 data register2. + * Otp debugger block6 data register2. */ #define OTP_DEBUG_BLK6_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x12c) /** OTP_DEBUG_BLOCK6_W2 : RO; bitpos: [31:0]; default: 0; @@ -924,7 +924,7 @@ extern "C" { #define OTP_DEBUG_BLOCK6_W2_S 0 /** OTP_DEBUG_BLK6_W3_REG register - * Otp debuger block6 data register3. + * Otp debugger block6 data register3. */ #define OTP_DEBUG_BLK6_W3_REG (DR_REG_OTP_DEBUG_BASE + 0x130) /** OTP_DEBUG_BLOCK6_W3 : RO; bitpos: [31:0]; default: 0; @@ -936,7 +936,7 @@ extern "C" { #define OTP_DEBUG_BLOCK6_W3_S 0 /** OTP_DEBUG_BLK6_W4_REG register - * Otp debuger block6 data register4. + * Otp debugger block6 data register4. */ #define OTP_DEBUG_BLK6_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x134) /** OTP_DEBUG_BLOCK6_W4 : RO; bitpos: [31:0]; default: 0; @@ -948,7 +948,7 @@ extern "C" { #define OTP_DEBUG_BLOCK6_W4_S 0 /** OTP_DEBUG_BLK6_W5_REG register - * Otp debuger block6 data register5. + * Otp debugger block6 data register5. */ #define OTP_DEBUG_BLK6_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x138) /** OTP_DEBUG_BLOCK6_W5 : RO; bitpos: [31:0]; default: 0; @@ -960,7 +960,7 @@ extern "C" { #define OTP_DEBUG_BLOCK6_W5_S 0 /** OTP_DEBUG_BLK6_W6_REG register - * Otp debuger block6 data register6. + * Otp debugger block6 data register6. */ #define OTP_DEBUG_BLK6_W6_REG (DR_REG_OTP_DEBUG_BASE + 0x13c) /** OTP_DEBUG_BLOCK6_W6 : RO; bitpos: [31:0]; default: 0; @@ -972,7 +972,7 @@ extern "C" { #define OTP_DEBUG_BLOCK6_W6_S 0 /** OTP_DEBUG_BLK6_W7_REG register - * Otp debuger block6 data register7. + * Otp debugger block6 data register7. */ #define OTP_DEBUG_BLK6_W7_REG (DR_REG_OTP_DEBUG_BASE + 0x140) /** OTP_DEBUG_BLOCK6_W7 : RO; bitpos: [31:0]; default: 0; @@ -984,7 +984,7 @@ extern "C" { #define OTP_DEBUG_BLOCK6_W7_S 0 /** OTP_DEBUG_BLK6_W8_REG register - * Otp debuger block6 data register8. + * Otp debugger block6 data register8. */ #define OTP_DEBUG_BLK6_W8_REG (DR_REG_OTP_DEBUG_BASE + 0x144) /** OTP_DEBUG_BLOCK6_W8 : RO; bitpos: [31:0]; default: 0; @@ -996,7 +996,7 @@ extern "C" { #define OTP_DEBUG_BLOCK6_W8_S 0 /** OTP_DEBUG_BLK6_W9_REG register - * Otp debuger block6 data register9. + * Otp debugger block6 data register9. */ #define OTP_DEBUG_BLK6_W9_REG (DR_REG_OTP_DEBUG_BASE + 0x148) /** OTP_DEBUG_BLOCK6_W9 : RO; bitpos: [31:0]; default: 0; @@ -1008,7 +1008,7 @@ extern "C" { #define OTP_DEBUG_BLOCK6_W9_S 0 /** OTP_DEBUG_BLK6_W10_REG register - * Otp debuger block6 data register10. + * Otp debugger block6 data register10. */ #define OTP_DEBUG_BLK6_W10_REG (DR_REG_OTP_DEBUG_BASE + 0x14c) /** OTP_DEBUG_BLOCK6_W10 : RO; bitpos: [31:0]; default: 0; @@ -1020,7 +1020,7 @@ extern "C" { #define OTP_DEBUG_BLOCK6_W10_S 0 /** OTP_DEBUG_BLK6_W11_REG register - * Otp debuger block6 data register11. + * Otp debugger block6 data register11. */ #define OTP_DEBUG_BLK6_W11_REG (DR_REG_OTP_DEBUG_BASE + 0x150) /** OTP_DEBUG_BLOCK6_W11 : RO; bitpos: [31:0]; default: 0; @@ -1032,7 +1032,7 @@ extern "C" { #define OTP_DEBUG_BLOCK6_W11_S 0 /** OTP_DEBUG_BLK7_W1_REG register - * Otp debuger block7 data register1. + * Otp debugger block7 data register1. */ #define OTP_DEBUG_BLK7_W1_REG (DR_REG_OTP_DEBUG_BASE + 0x154) /** OTP_DEBUG_BLOCK7_W1 : RO; bitpos: [31:0]; default: 0; @@ -1044,7 +1044,7 @@ extern "C" { #define OTP_DEBUG_BLOCK7_W1_S 0 /** OTP_DEBUG_BLK7_W2_REG register - * Otp debuger block7 data register2. + * Otp debugger block7 data register2. */ #define OTP_DEBUG_BLK7_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x158) /** OTP_DEBUG_BLOCK7_W2 : RO; bitpos: [31:0]; default: 0; @@ -1056,7 +1056,7 @@ extern "C" { #define OTP_DEBUG_BLOCK7_W2_S 0 /** OTP_DEBUG_BLK7_W3_REG register - * Otp debuger block7 data register3. + * Otp debugger block7 data register3. */ #define OTP_DEBUG_BLK7_W3_REG (DR_REG_OTP_DEBUG_BASE + 0x15c) /** OTP_DEBUG_BLOCK7_W3 : RO; bitpos: [31:0]; default: 0; @@ -1068,7 +1068,7 @@ extern "C" { #define OTP_DEBUG_BLOCK7_W3_S 0 /** OTP_DEBUG_BLK7_W4_REG register - * Otp debuger block7 data register4. + * Otp debugger block7 data register4. */ #define OTP_DEBUG_BLK7_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x160) /** OTP_DEBUG_BLOCK7_W4 : RO; bitpos: [31:0]; default: 0; @@ -1080,7 +1080,7 @@ extern "C" { #define OTP_DEBUG_BLOCK7_W4_S 0 /** OTP_DEBUG_BLK7_W5_REG register - * Otp debuger block7 data register5. + * Otp debugger block7 data register5. */ #define OTP_DEBUG_BLK7_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x164) /** OTP_DEBUG_BLOCK7_W5 : RO; bitpos: [31:0]; default: 0; @@ -1092,7 +1092,7 @@ extern "C" { #define OTP_DEBUG_BLOCK7_W5_S 0 /** OTP_DEBUG_BLK7_W6_REG register - * Otp debuger block7 data register6. + * Otp debugger block7 data register6. */ #define OTP_DEBUG_BLK7_W6_REG (DR_REG_OTP_DEBUG_BASE + 0x168) /** OTP_DEBUG_BLOCK7_W6 : RO; bitpos: [31:0]; default: 0; @@ -1104,7 +1104,7 @@ extern "C" { #define OTP_DEBUG_BLOCK7_W6_S 0 /** OTP_DEBUG_BLK7_W7_REG register - * Otp debuger block7 data register7. + * Otp debugger block7 data register7. */ #define OTP_DEBUG_BLK7_W7_REG (DR_REG_OTP_DEBUG_BASE + 0x16c) /** OTP_DEBUG_BLOCK7_W7 : RO; bitpos: [31:0]; default: 0; @@ -1116,7 +1116,7 @@ extern "C" { #define OTP_DEBUG_BLOCK7_W7_S 0 /** OTP_DEBUG_BLK7_W8_REG register - * Otp debuger block7 data register8. + * Otp debugger block7 data register8. */ #define OTP_DEBUG_BLK7_W8_REG (DR_REG_OTP_DEBUG_BASE + 0x170) /** OTP_DEBUG_BLOCK7_W8 : RO; bitpos: [31:0]; default: 0; @@ -1128,7 +1128,7 @@ extern "C" { #define OTP_DEBUG_BLOCK7_W8_S 0 /** OTP_DEBUG_BLK7_W9_REG register - * Otp debuger block7 data register9. + * Otp debugger block7 data register9. */ #define OTP_DEBUG_BLK7_W9_REG (DR_REG_OTP_DEBUG_BASE + 0x174) /** OTP_DEBUG_BLOCK7_W9 : RO; bitpos: [31:0]; default: 0; @@ -1140,7 +1140,7 @@ extern "C" { #define OTP_DEBUG_BLOCK7_W9_S 0 /** OTP_DEBUG_BLK7_W10_REG register - * Otp debuger block7 data register10. + * Otp debugger block7 data register10. */ #define OTP_DEBUG_BLK7_W10_REG (DR_REG_OTP_DEBUG_BASE + 0x178) /** OTP_DEBUG_BLOCK7_W10 : RO; bitpos: [31:0]; default: 0; @@ -1152,7 +1152,7 @@ extern "C" { #define OTP_DEBUG_BLOCK7_W10_S 0 /** OTP_DEBUG_BLK7_W11_REG register - * Otp debuger block7 data register11. + * Otp debugger block7 data register11. */ #define OTP_DEBUG_BLK7_W11_REG (DR_REG_OTP_DEBUG_BASE + 0x17c) /** OTP_DEBUG_BLOCK7_W11 : RO; bitpos: [31:0]; default: 0; @@ -1164,7 +1164,7 @@ extern "C" { #define OTP_DEBUG_BLOCK7_W11_S 0 /** OTP_DEBUG_BLK8_W1_REG register - * Otp debuger block8 data register1. + * Otp debugger block8 data register1. */ #define OTP_DEBUG_BLK8_W1_REG (DR_REG_OTP_DEBUG_BASE + 0x180) /** OTP_DEBUG_BLOCK8_W1 : RO; bitpos: [31:0]; default: 0; @@ -1176,7 +1176,7 @@ extern "C" { #define OTP_DEBUG_BLOCK8_W1_S 0 /** OTP_DEBUG_BLK8_W2_REG register - * Otp debuger block8 data register2. + * Otp debugger block8 data register2. */ #define OTP_DEBUG_BLK8_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x184) /** OTP_DEBUG_BLOCK8_W2 : RO; bitpos: [31:0]; default: 0; @@ -1188,7 +1188,7 @@ extern "C" { #define OTP_DEBUG_BLOCK8_W2_S 0 /** OTP_DEBUG_BLK8_W3_REG register - * Otp debuger block8 data register3. + * Otp debugger block8 data register3. */ #define OTP_DEBUG_BLK8_W3_REG (DR_REG_OTP_DEBUG_BASE + 0x188) /** OTP_DEBUG_BLOCK8_W3 : RO; bitpos: [31:0]; default: 0; @@ -1200,7 +1200,7 @@ extern "C" { #define OTP_DEBUG_BLOCK8_W3_S 0 /** OTP_DEBUG_BLK8_W4_REG register - * Otp debuger block8 data register4. + * Otp debugger block8 data register4. */ #define OTP_DEBUG_BLK8_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x18c) /** OTP_DEBUG_BLOCK8_W4 : RO; bitpos: [31:0]; default: 0; @@ -1212,7 +1212,7 @@ extern "C" { #define OTP_DEBUG_BLOCK8_W4_S 0 /** OTP_DEBUG_BLK8_W5_REG register - * Otp debuger block8 data register5. + * Otp debugger block8 data register5. */ #define OTP_DEBUG_BLK8_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x190) /** OTP_DEBUG_BLOCK8_W5 : RO; bitpos: [31:0]; default: 0; @@ -1224,7 +1224,7 @@ extern "C" { #define OTP_DEBUG_BLOCK8_W5_S 0 /** OTP_DEBUG_BLK8_W6_REG register - * Otp debuger block8 data register6. + * Otp debugger block8 data register6. */ #define OTP_DEBUG_BLK8_W6_REG (DR_REG_OTP_DEBUG_BASE + 0x194) /** OTP_DEBUG_BLOCK8_W6 : RO; bitpos: [31:0]; default: 0; @@ -1236,7 +1236,7 @@ extern "C" { #define OTP_DEBUG_BLOCK8_W6_S 0 /** OTP_DEBUG_BLK8_W7_REG register - * Otp debuger block8 data register7. + * Otp debugger block8 data register7. */ #define OTP_DEBUG_BLK8_W7_REG (DR_REG_OTP_DEBUG_BASE + 0x198) /** OTP_DEBUG_BLOCK8_W7 : RO; bitpos: [31:0]; default: 0; @@ -1248,7 +1248,7 @@ extern "C" { #define OTP_DEBUG_BLOCK8_W7_S 0 /** OTP_DEBUG_BLK8_W8_REG register - * Otp debuger block8 data register8. + * Otp debugger block8 data register8. */ #define OTP_DEBUG_BLK8_W8_REG (DR_REG_OTP_DEBUG_BASE + 0x19c) /** OTP_DEBUG_BLOCK8_W8 : RO; bitpos: [31:0]; default: 0; @@ -1260,7 +1260,7 @@ extern "C" { #define OTP_DEBUG_BLOCK8_W8_S 0 /** OTP_DEBUG_BLK8_W9_REG register - * Otp debuger block8 data register9. + * Otp debugger block8 data register9. */ #define OTP_DEBUG_BLK8_W9_REG (DR_REG_OTP_DEBUG_BASE + 0x1a0) /** OTP_DEBUG_BLOCK8_W9 : RO; bitpos: [31:0]; default: 0; @@ -1272,7 +1272,7 @@ extern "C" { #define OTP_DEBUG_BLOCK8_W9_S 0 /** OTP_DEBUG_BLK8_W10_REG register - * Otp debuger block8 data register10. + * Otp debugger block8 data register10. */ #define OTP_DEBUG_BLK8_W10_REG (DR_REG_OTP_DEBUG_BASE + 0x1a4) /** OTP_DEBUG_BLOCK8_W10 : RO; bitpos: [31:0]; default: 0; @@ -1284,7 +1284,7 @@ extern "C" { #define OTP_DEBUG_BLOCK8_W10_S 0 /** OTP_DEBUG_BLK8_W11_REG register - * Otp debuger block8 data register11. + * Otp debugger block8 data register11. */ #define OTP_DEBUG_BLK8_W11_REG (DR_REG_OTP_DEBUG_BASE + 0x1a8) /** OTP_DEBUG_BLOCK8_W11 : RO; bitpos: [31:0]; default: 0; @@ -1296,7 +1296,7 @@ extern "C" { #define OTP_DEBUG_BLOCK8_W11_S 0 /** OTP_DEBUG_BLK9_W1_REG register - * Otp debuger block9 data register1. + * Otp debugger block9 data register1. */ #define OTP_DEBUG_BLK9_W1_REG (DR_REG_OTP_DEBUG_BASE + 0x1ac) /** OTP_DEBUG_BLOCK9_W1 : RO; bitpos: [31:0]; default: 0; @@ -1308,7 +1308,7 @@ extern "C" { #define OTP_DEBUG_BLOCK9_W1_S 0 /** OTP_DEBUG_BLK9_W2_REG register - * Otp debuger block9 data register2. + * Otp debugger block9 data register2. */ #define OTP_DEBUG_BLK9_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x1b0) /** OTP_DEBUG_BLOCK9_W2 : RO; bitpos: [31:0]; default: 0; @@ -1320,7 +1320,7 @@ extern "C" { #define OTP_DEBUG_BLOCK9_W2_S 0 /** OTP_DEBUG_BLK9_W3_REG register - * Otp debuger block9 data register3. + * Otp debugger block9 data register3. */ #define OTP_DEBUG_BLK9_W3_REG (DR_REG_OTP_DEBUG_BASE + 0x1b4) /** OTP_DEBUG_BLOCK9_W3 : RO; bitpos: [31:0]; default: 0; @@ -1332,7 +1332,7 @@ extern "C" { #define OTP_DEBUG_BLOCK9_W3_S 0 /** OTP_DEBUG_BLK9_W4_REG register - * Otp debuger block9 data register4. + * Otp debugger block9 data register4. */ #define OTP_DEBUG_BLK9_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x1b8) /** OTP_DEBUG_BLOCK9_W4 : RO; bitpos: [31:0]; default: 0; @@ -1344,7 +1344,7 @@ extern "C" { #define OTP_DEBUG_BLOCK9_W4_S 0 /** OTP_DEBUG_BLK9_W5_REG register - * Otp debuger block9 data register5. + * Otp debugger block9 data register5. */ #define OTP_DEBUG_BLK9_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x1bc) /** OTP_DEBUG_BLOCK9_W5 : RO; bitpos: [31:0]; default: 0; @@ -1356,7 +1356,7 @@ extern "C" { #define OTP_DEBUG_BLOCK9_W5_S 0 /** OTP_DEBUG_BLK9_W6_REG register - * Otp debuger block9 data register6. + * Otp debugger block9 data register6. */ #define OTP_DEBUG_BLK9_W6_REG (DR_REG_OTP_DEBUG_BASE + 0x1c0) /** OTP_DEBUG_BLOCK9_W6 : RO; bitpos: [31:0]; default: 0; @@ -1368,7 +1368,7 @@ extern "C" { #define OTP_DEBUG_BLOCK9_W6_S 0 /** OTP_DEBUG_BLK9_W7_REG register - * Otp debuger block9 data register7. + * Otp debugger block9 data register7. */ #define OTP_DEBUG_BLK9_W7_REG (DR_REG_OTP_DEBUG_BASE + 0x1c4) /** OTP_DEBUG_BLOCK9_W7 : RO; bitpos: [31:0]; default: 0; @@ -1380,7 +1380,7 @@ extern "C" { #define OTP_DEBUG_BLOCK9_W7_S 0 /** OTP_DEBUG_BLK9_W8_REG register - * Otp debuger block9 data register8. + * Otp debugger block9 data register8. */ #define OTP_DEBUG_BLK9_W8_REG (DR_REG_OTP_DEBUG_BASE + 0x1c8) /** OTP_DEBUG_BLOCK9_W8 : RO; bitpos: [31:0]; default: 0; @@ -1392,7 +1392,7 @@ extern "C" { #define OTP_DEBUG_BLOCK9_W8_S 0 /** OTP_DEBUG_BLK9_W9_REG register - * Otp debuger block9 data register9. + * Otp debugger block9 data register9. */ #define OTP_DEBUG_BLK9_W9_REG (DR_REG_OTP_DEBUG_BASE + 0x1cc) /** OTP_DEBUG_BLOCK9_W9 : RO; bitpos: [31:0]; default: 0; @@ -1404,7 +1404,7 @@ extern "C" { #define OTP_DEBUG_BLOCK9_W9_S 0 /** OTP_DEBUG_BLK9_W10_REG register - * Otp debuger block9 data register10. + * Otp debugger block9 data register10. */ #define OTP_DEBUG_BLK9_W10_REG (DR_REG_OTP_DEBUG_BASE + 0x1d0) /** OTP_DEBUG_BLOCK9_W10 : RO; bitpos: [31:0]; default: 0; @@ -1416,7 +1416,7 @@ extern "C" { #define OTP_DEBUG_BLOCK9_W10_S 0 /** OTP_DEBUG_BLK9_W11_REG register - * Otp debuger block9 data register11. + * Otp debugger block9 data register11. */ #define OTP_DEBUG_BLK9_W11_REG (DR_REG_OTP_DEBUG_BASE + 0x1d4) /** OTP_DEBUG_BLOCK9_W11 : RO; bitpos: [31:0]; default: 0; @@ -1428,7 +1428,7 @@ extern "C" { #define OTP_DEBUG_BLOCK9_W11_S 0 /** OTP_DEBUG_BLK10_W1_REG register - * Otp debuger block10 data register1. + * Otp debugger block10 data register1. */ #define OTP_DEBUG_BLK10_W1_REG (DR_REG_OTP_DEBUG_BASE + 0x1d8) /** OTP_DEBUG_BLOCK10_W1 : RO; bitpos: [31:0]; default: 0; @@ -1440,7 +1440,7 @@ extern "C" { #define OTP_DEBUG_BLOCK10_W1_S 0 /** OTP_DEBUG_BLK10_W2_REG register - * Otp debuger block10 data register2. + * Otp debugger block10 data register2. */ #define OTP_DEBUG_BLK10_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x1dc) /** OTP_DEBUG_BLOCK10_W2 : RO; bitpos: [31:0]; default: 0; @@ -1452,7 +1452,7 @@ extern "C" { #define OTP_DEBUG_BLOCK10_W2_S 0 /** OTP_DEBUG_BLK10_W3_REG register - * Otp debuger block10 data register3. + * Otp debugger block10 data register3. */ #define OTP_DEBUG_BLK10_W3_REG (DR_REG_OTP_DEBUG_BASE + 0x1e0) /** OTP_DEBUG_BLOCK10_W3 : RO; bitpos: [31:0]; default: 0; @@ -1464,7 +1464,7 @@ extern "C" { #define OTP_DEBUG_BLOCK10_W3_S 0 /** OTP_DEBUG_BLK10_W4_REG register - * Otp debuger block10 data register4. + * Otp debugger block10 data register4. */ #define OTP_DEBUG_BLK10_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x1e4) /** OTP_DEBUG_BLOCK10_W4 : RO; bitpos: [31:0]; default: 0; @@ -1476,7 +1476,7 @@ extern "C" { #define OTP_DEBUG_BLOCK10_W4_S 0 /** OTP_DEBUG_BLK10_W5_REG register - * Otp debuger block10 data register5. + * Otp debugger block10 data register5. */ #define OTP_DEBUG_BLK10_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x1e8) /** OTP_DEBUG_BLOCK10_W5 : RO; bitpos: [31:0]; default: 0; @@ -1488,7 +1488,7 @@ extern "C" { #define OTP_DEBUG_BLOCK10_W5_S 0 /** OTP_DEBUG_BLK10_W6_REG register - * Otp debuger block10 data register6. + * Otp debugger block10 data register6. */ #define OTP_DEBUG_BLK10_W6_REG (DR_REG_OTP_DEBUG_BASE + 0x1ec) /** OTP_DEBUG_BLOCK10_W6 : RO; bitpos: [31:0]; default: 0; @@ -1500,7 +1500,7 @@ extern "C" { #define OTP_DEBUG_BLOCK10_W6_S 0 /** OTP_DEBUG_BLK10_W7_REG register - * Otp debuger block10 data register7. + * Otp debugger block10 data register7. */ #define OTP_DEBUG_BLK10_W7_REG (DR_REG_OTP_DEBUG_BASE + 0x1f0) /** OTP_DEBUG_BLOCK10_W7 : RO; bitpos: [31:0]; default: 0; @@ -1512,7 +1512,7 @@ extern "C" { #define OTP_DEBUG_BLOCK10_W7_S 0 /** OTP_DEBUG_BLK10_W8_REG register - * Otp debuger block10 data register8. + * Otp debugger block10 data register8. */ #define OTP_DEBUG_BLK10_W8_REG (DR_REG_OTP_DEBUG_BASE + 0x1f4) /** OTP_DEBUG_BLOCK10_W8 : RO; bitpos: [31:0]; default: 0; @@ -1524,7 +1524,7 @@ extern "C" { #define OTP_DEBUG_BLOCK10_W8_S 0 /** OTP_DEBUG_BLK10_W9_REG register - * Otp debuger block10 data register9. + * Otp debugger block10 data register9. */ #define OTP_DEBUG_BLK10_W9_REG (DR_REG_OTP_DEBUG_BASE + 0x1f8) /** OTP_DEBUG_BLOCK10_W9 : RO; bitpos: [31:0]; default: 0; @@ -1536,7 +1536,7 @@ extern "C" { #define OTP_DEBUG_BLOCK10_W9_S 0 /** OTP_DEBUG_BLK10_W10_REG register - * Otp debuger block10 data register10. + * Otp debugger block10 data register10. */ #define OTP_DEBUG_BLK10_W10_REG (DR_REG_OTP_DEBUG_BASE + 0x1fc) /** OTP_DEBUG_BLOCK19_W10 : RO; bitpos: [31:0]; default: 0; @@ -1548,7 +1548,7 @@ extern "C" { #define OTP_DEBUG_BLOCK19_W10_S 0 /** OTP_DEBUG_BLK10_W11_REG register - * Otp debuger block10 data register11. + * Otp debugger block10 data register11. */ #define OTP_DEBUG_BLK10_W11_REG (DR_REG_OTP_DEBUG_BASE + 0x200) /** OTP_DEBUG_BLOCK10_W11 : RO; bitpos: [31:0]; default: 0; @@ -1560,7 +1560,7 @@ extern "C" { #define OTP_DEBUG_BLOCK10_W11_S 0 /** OTP_DEBUG_CLK_REG register - * Otp debuger clk_en configuration register. + * Otp debugger clk_en configuration register. */ #define OTP_DEBUG_CLK_REG (DR_REG_OTP_DEBUG_BASE + 0x204) /** OTP_DEBUG_CLK_EN : R/W; bitpos: [0]; default: 0; diff --git a/components/soc/esp32c6/include/soc/otp_debug_struct.h b/components/soc/esp32c6/register/soc/otp_debug_struct.h similarity index 89% rename from components/soc/esp32c6/include/soc/otp_debug_struct.h rename to components/soc/esp32c6/register/soc/otp_debug_struct.h index 5b0737475f7..8ed1fe28029 100644 --- a/components/soc/esp32c6/include/soc/otp_debug_struct.h +++ b/components/soc/esp32c6/register/soc/otp_debug_struct.h @@ -12,7 +12,7 @@ extern "C" { /** Group: OTP_DEBUG Block0 Write Disable Data */ /** Type of wr_dis register - * Otp debuger block0 data register1. + * Otp debugger block0 data register1. */ typedef union { struct { @@ -27,7 +27,7 @@ typedef union { /** Group: OTP_DEBUG Block0 Backup1 Word1 Data */ /** Type of blk0_backup1_w1 register - * Otp debuger block0 data register2. + * Otp debugger block0 data register2. */ typedef union { struct { @@ -42,7 +42,7 @@ typedef union { /** Group: OTP_DEBUG Block0 Backup1 Word2 Data */ /** Type of blk0_backup1_w2 register - * Otp debuger block0 data register3. + * Otp debugger block0 data register3. */ typedef union { struct { @@ -57,7 +57,7 @@ typedef union { /** Group: OTP_DEBUG Block0 Backup1 Word3 Data */ /** Type of blk0_backup1_w3 register - * Otp debuger block0 data register4. + * Otp debugger block0 data register4. */ typedef union { struct { @@ -72,7 +72,7 @@ typedef union { /** Group: OTP_DEBUG Block0 Backup1 Word4 Data */ /** Type of blk0_backup1_w4 register - * Otp debuger block0 data register5. + * Otp debugger block0 data register5. */ typedef union { struct { @@ -87,7 +87,7 @@ typedef union { /** Group: OTP_DEBUG Block0 Backup1 Word5 Data */ /** Type of blk0_backup1_w5 register - * Otp debuger block0 data register6. + * Otp debugger block0 data register6. */ typedef union { struct { @@ -102,7 +102,7 @@ typedef union { /** Group: OTP_DEBUG Block0 Backup2 Word1 Data */ /** Type of blk0_backup2_w1 register - * Otp debuger block0 data register7. + * Otp debugger block0 data register7. */ typedef union { struct { @@ -117,7 +117,7 @@ typedef union { /** Group: OTP_DEBUG Block0 Backup2 Word2 Data */ /** Type of blk0_backup2_w2 register - * Otp debuger block0 data register8. + * Otp debugger block0 data register8. */ typedef union { struct { @@ -132,7 +132,7 @@ typedef union { /** Group: OTP_DEBUG Block0 Backup2 Word3 Data */ /** Type of blk0_backup2_w3 register - * Otp debuger block0 data register9. + * Otp debugger block0 data register9. */ typedef union { struct { @@ -147,7 +147,7 @@ typedef union { /** Group: OTP_DEBUG Block0 Backup2 Word4 Data */ /** Type of blk0_backup2_w4 register - * Otp debuger block0 data register10. + * Otp debugger block0 data register10. */ typedef union { struct { @@ -162,7 +162,7 @@ typedef union { /** Group: OTP_DEBUG Block0 Backup2 Word5 Data */ /** Type of blk0_backup2_w5 register - * Otp debuger block0 data register11. + * Otp debugger block0 data register11. */ typedef union { struct { @@ -177,7 +177,7 @@ typedef union { /** Group: OTP_DEBUG Block0 Backup3 Word1 Data */ /** Type of blk0_backup3_w1 register - * Otp debuger block0 data register12. + * Otp debugger block0 data register12. */ typedef union { struct { @@ -192,7 +192,7 @@ typedef union { /** Group: OTP_DEBUG Block0 Backup3 Word2 Data */ /** Type of blk0_backup3_w2 register - * Otp debuger block0 data register13. + * Otp debugger block0 data register13. */ typedef union { struct { @@ -207,7 +207,7 @@ typedef union { /** Group: OTP_DEBUG Block0 Backup3 Word3 Data */ /** Type of blk0_backup3_w3 register - * Otp debuger block0 data register14. + * Otp debugger block0 data register14. */ typedef union { struct { @@ -222,7 +222,7 @@ typedef union { /** Group: OTP_DEBUG Block0 Backup3 Word4 Data */ /** Type of blk0_backup3_w4 register - * Otp debuger block0 data register15. + * Otp debugger block0 data register15. */ typedef union { struct { @@ -237,7 +237,7 @@ typedef union { /** Group: OTP_DEBUG Block0 Backup3 Word5 Data */ /** Type of blk0_backup3_w5 register - * Otp debuger block0 data register16. + * Otp debugger block0 data register16. */ typedef union { struct { @@ -252,7 +252,7 @@ typedef union { /** Group: OTP_DEBUG Block0 Backup4 Word1 Data */ /** Type of blk0_backup4_w1 register - * Otp debuger block0 data register17. + * Otp debugger block0 data register17. */ typedef union { struct { @@ -267,7 +267,7 @@ typedef union { /** Group: OTP_DEBUG Block0 Backup4 Word2 Data */ /** Type of blk0_backup4_w2 register - * Otp debuger block0 data register18. + * Otp debugger block0 data register18. */ typedef union { struct { @@ -282,7 +282,7 @@ typedef union { /** Group: OTP_DEBUG Block0 Backup4 Word3 Data */ /** Type of blk0_backup4_w3 register - * Otp debuger block0 data register19. + * Otp debugger block0 data register19. */ typedef union { struct { @@ -297,7 +297,7 @@ typedef union { /** Group: OTP_DEBUG Block0 Backup4 Word4 Data */ /** Type of blk0_backup4_w4 register - * Otp debuger block0 data register20. + * Otp debugger block0 data register20. */ typedef union { struct { @@ -312,7 +312,7 @@ typedef union { /** Group: OTP_DEBUG Block0 Backup4 Word5 Data */ /** Type of blk0_backup4_w5 register - * Otp debuger block0 data register21. + * Otp debugger block0 data register21. */ typedef union { struct { @@ -327,7 +327,7 @@ typedef union { /** Group: OTP_DEBUG Block1 Word1 Data */ /** Type of blk1_w1 register - * Otp debuger block1 data register1. + * Otp debugger block1 data register1. */ typedef union { struct { @@ -342,7 +342,7 @@ typedef union { /** Group: OTP_DEBUG Block1 Word2 Data */ /** Type of blk1_w2 register - * Otp debuger block1 data register2. + * Otp debugger block1 data register2. */ typedef union { struct { @@ -357,7 +357,7 @@ typedef union { /** Group: OTP_DEBUG Block1 Word3 Data */ /** Type of blk1_w3 register - * Otp debuger block1 data register3. + * Otp debugger block1 data register3. */ typedef union { struct { @@ -372,7 +372,7 @@ typedef union { /** Group: OTP_DEBUG Block1 Word4 Data */ /** Type of blk1_w4 register - * Otp debuger block1 data register4. + * Otp debugger block1 data register4. */ typedef union { struct { @@ -387,7 +387,7 @@ typedef union { /** Group: OTP_DEBUG Block1 Word5 Data */ /** Type of blk1_w5 register - * Otp debuger block1 data register5. + * Otp debugger block1 data register5. */ typedef union { struct { @@ -402,7 +402,7 @@ typedef union { /** Group: OTP_DEBUG Block1 Word6 Data */ /** Type of blk1_w6 register - * Otp debuger block1 data register6. + * Otp debugger block1 data register6. */ typedef union { struct { @@ -417,7 +417,7 @@ typedef union { /** Group: OTP_DEBUG Block1 Word7 Data */ /** Type of blk1_w7 register - * Otp debuger block1 data register7. + * Otp debugger block1 data register7. */ typedef union { struct { @@ -432,7 +432,7 @@ typedef union { /** Group: OTP_DEBUG Block1 Word8 Data */ /** Type of blk1_w8 register - * Otp debuger block1 data register8. + * Otp debugger block1 data register8. */ typedef union { struct { @@ -447,7 +447,7 @@ typedef union { /** Group: OTP_DEBUG Block1 Word9 Data */ /** Type of blk1_w9 register - * Otp debuger block1 data register9. + * Otp debugger block1 data register9. */ typedef union { struct { @@ -462,7 +462,7 @@ typedef union { /** Group: OTP_DEBUG Block2 Word1 Data */ /** Type of blk2_w1 register - * Otp debuger block2 data register1. + * Otp debugger block2 data register1. */ typedef union { struct { @@ -477,7 +477,7 @@ typedef union { /** Group: OTP_DEBUG Block2 Word2 Data */ /** Type of blk2_w2 register - * Otp debuger block2 data register2. + * Otp debugger block2 data register2. */ typedef union { struct { @@ -492,7 +492,7 @@ typedef union { /** Group: OTP_DEBUG Block2 Word3 Data */ /** Type of blk2_w3 register - * Otp debuger block2 data register3. + * Otp debugger block2 data register3. */ typedef union { struct { @@ -507,7 +507,7 @@ typedef union { /** Group: OTP_DEBUG Block2 Word4 Data */ /** Type of blk2_w4 register - * Otp debuger block2 data register4. + * Otp debugger block2 data register4. */ typedef union { struct { @@ -522,7 +522,7 @@ typedef union { /** Group: OTP_DEBUG Block2 Word5 Data */ /** Type of blk2_w5 register - * Otp debuger block2 data register5. + * Otp debugger block2 data register5. */ typedef union { struct { @@ -537,7 +537,7 @@ typedef union { /** Group: OTP_DEBUG Block2 Word6 Data */ /** Type of blk2_w6 register - * Otp debuger block2 data register6. + * Otp debugger block2 data register6. */ typedef union { struct { @@ -552,7 +552,7 @@ typedef union { /** Group: OTP_DEBUG Block2 Word7 Data */ /** Type of blk2_w7 register - * Otp debuger block2 data register7. + * Otp debugger block2 data register7. */ typedef union { struct { @@ -567,7 +567,7 @@ typedef union { /** Group: OTP_DEBUG Block2 Word8 Data */ /** Type of blk2_w8 register - * Otp debuger block2 data register8. + * Otp debugger block2 data register8. */ typedef union { struct { @@ -582,7 +582,7 @@ typedef union { /** Group: OTP_DEBUG Block2 Word9 Data */ /** Type of blk2_w9 register - * Otp debuger block2 data register9. + * Otp debugger block2 data register9. */ typedef union { struct { @@ -597,7 +597,7 @@ typedef union { /** Group: OTP_DEBUG Block2 Word10 Data */ /** Type of blk2_w10 register - * Otp debuger block2 data register10. + * Otp debugger block2 data register10. */ typedef union { struct { @@ -612,7 +612,7 @@ typedef union { /** Group: OTP_DEBUG Block2 Word11 Data */ /** Type of blk2_w11 register - * Otp debuger block2 data register11. + * Otp debugger block2 data register11. */ typedef union { struct { @@ -625,7 +625,7 @@ typedef union { } otp_debug_blk2_w11_reg_t; /** Type of blk10_w11 register - * Otp debuger block10 data register11. + * Otp debugger block10 data register11. */ typedef union { struct { @@ -640,7 +640,7 @@ typedef union { /** Group: OTP_DEBUG Block3 Word1 Data */ /** Type of blk3_w1 register - * Otp debuger block3 data register1. + * Otp debugger block3 data register1. */ typedef union { struct { @@ -655,7 +655,7 @@ typedef union { /** Group: OTP_DEBUG Block3 Word2 Data */ /** Type of blk3_w2 register - * Otp debuger block3 data register2. + * Otp debugger block3 data register2. */ typedef union { struct { @@ -670,7 +670,7 @@ typedef union { /** Group: OTP_DEBUG Block3 Word3 Data */ /** Type of blk3_w3 register - * Otp debuger block3 data register3. + * Otp debugger block3 data register3. */ typedef union { struct { @@ -685,7 +685,7 @@ typedef union { /** Group: OTP_DEBUG Block3 Word4 Data */ /** Type of blk3_w4 register - * Otp debuger block3 data register4. + * Otp debugger block3 data register4. */ typedef union { struct { @@ -700,7 +700,7 @@ typedef union { /** Group: OTP_DEBUG Block3 Word5 Data */ /** Type of blk3_w5 register - * Otp debuger block3 data register5. + * Otp debugger block3 data register5. */ typedef union { struct { @@ -715,7 +715,7 @@ typedef union { /** Group: OTP_DEBUG Block3 Word6 Data */ /** Type of blk3_w6 register - * Otp debuger block3 data register6. + * Otp debugger block3 data register6. */ typedef union { struct { @@ -730,7 +730,7 @@ typedef union { /** Group: OTP_DEBUG Block3 Word7 Data */ /** Type of blk3_w7 register - * Otp debuger block3 data register7. + * Otp debugger block3 data register7. */ typedef union { struct { @@ -745,7 +745,7 @@ typedef union { /** Group: OTP_DEBUG Block3 Word8 Data */ /** Type of blk3_w8 register - * Otp debuger block3 data register8. + * Otp debugger block3 data register8. */ typedef union { struct { @@ -760,7 +760,7 @@ typedef union { /** Group: OTP_DEBUG Block3 Word9 Data */ /** Type of blk3_w9 register - * Otp debuger block3 data register9. + * Otp debugger block3 data register9. */ typedef union { struct { @@ -775,7 +775,7 @@ typedef union { /** Group: OTP_DEBUG Block3 Word10 Data */ /** Type of blk3_w10 register - * Otp debuger block3 data register10. + * Otp debugger block3 data register10. */ typedef union { struct { @@ -790,7 +790,7 @@ typedef union { /** Group: OTP_DEBUG Block3 Word11 Data */ /** Type of blk3_w11 register - * Otp debuger block3 data register11. + * Otp debugger block3 data register11. */ typedef union { struct { @@ -805,7 +805,7 @@ typedef union { /** Group: OTP_DEBUG Block4 Word1 Data */ /** Type of blk4_w1 register - * Otp debuger block4 data register1. + * Otp debugger block4 data register1. */ typedef union { struct { @@ -820,7 +820,7 @@ typedef union { /** Group: OTP_DEBUG Block4 Word2 Data */ /** Type of blk4_w2 register - * Otp debuger block4 data register2. + * Otp debugger block4 data register2. */ typedef union { struct { @@ -835,7 +835,7 @@ typedef union { /** Group: OTP_DEBUG Block4 Word3 Data */ /** Type of blk4_w3 register - * Otp debuger block4 data register3. + * Otp debugger block4 data register3. */ typedef union { struct { @@ -850,7 +850,7 @@ typedef union { /** Group: OTP_DEBUG Block4 Word4 Data */ /** Type of blk4_w4 register - * Otp debuger block4 data register4. + * Otp debugger block4 data register4. */ typedef union { struct { @@ -865,7 +865,7 @@ typedef union { /** Group: OTP_DEBUG Block4 Word5 Data */ /** Type of blk4_w5 register - * Otp debuger block4 data register5. + * Otp debugger block4 data register5. */ typedef union { struct { @@ -880,7 +880,7 @@ typedef union { /** Group: OTP_DEBUG Block4 Word6 Data */ /** Type of blk4_w6 register - * Otp debuger block4 data register6. + * Otp debugger block4 data register6. */ typedef union { struct { @@ -895,7 +895,7 @@ typedef union { /** Group: OTP_DEBUG Block4 Word7 Data */ /** Type of blk4_w7 register - * Otp debuger block4 data register7. + * Otp debugger block4 data register7. */ typedef union { struct { @@ -910,7 +910,7 @@ typedef union { /** Group: OTP_DEBUG Block4 Word8 Data */ /** Type of blk4_w8 register - * Otp debuger block4 data register8. + * Otp debugger block4 data register8. */ typedef union { struct { @@ -925,7 +925,7 @@ typedef union { /** Group: OTP_DEBUG Block4 Word9 Data */ /** Type of blk4_w9 register - * Otp debuger block4 data register9. + * Otp debugger block4 data register9. */ typedef union { struct { @@ -940,7 +940,7 @@ typedef union { /** Group: OTP_DEBUG Block4 Word10 Data */ /** Type of blk4_w10 register - * Otp debuger block4 data registe10. + * Otp debugger block4 data registe10. */ typedef union { struct { @@ -955,7 +955,7 @@ typedef union { /** Group: OTP_DEBUG Block4 Word11 Data */ /** Type of blk4_w11 register - * Otp debuger block4 data register11. + * Otp debugger block4 data register11. */ typedef union { struct { @@ -970,7 +970,7 @@ typedef union { /** Group: OTP_DEBUG Block5 Word1 Data */ /** Type of blk5_w1 register - * Otp debuger block5 data register1. + * Otp debugger block5 data register1. */ typedef union { struct { @@ -985,7 +985,7 @@ typedef union { /** Group: OTP_DEBUG Block5 Word2 Data */ /** Type of blk5_w2 register - * Otp debuger block5 data register2. + * Otp debugger block5 data register2. */ typedef union { struct { @@ -1000,7 +1000,7 @@ typedef union { /** Group: OTP_DEBUG Block5 Word3 Data */ /** Type of blk5_w3 register - * Otp debuger block5 data register3. + * Otp debugger block5 data register3. */ typedef union { struct { @@ -1015,7 +1015,7 @@ typedef union { /** Group: OTP_DEBUG Block5 Word4 Data */ /** Type of blk5_w4 register - * Otp debuger block5 data register4. + * Otp debugger block5 data register4. */ typedef union { struct { @@ -1030,7 +1030,7 @@ typedef union { /** Group: OTP_DEBUG Block5 Word5 Data */ /** Type of blk5_w5 register - * Otp debuger block5 data register5. + * Otp debugger block5 data register5. */ typedef union { struct { @@ -1045,7 +1045,7 @@ typedef union { /** Group: OTP_DEBUG Block5 Word6 Data */ /** Type of blk5_w6 register - * Otp debuger block5 data register6. + * Otp debugger block5 data register6. */ typedef union { struct { @@ -1060,7 +1060,7 @@ typedef union { /** Group: OTP_DEBUG Block5 Word7 Data */ /** Type of blk5_w7 register - * Otp debuger block5 data register7. + * Otp debugger block5 data register7. */ typedef union { struct { @@ -1075,7 +1075,7 @@ typedef union { /** Group: OTP_DEBUG Block5 Word8 Data */ /** Type of blk5_w8 register - * Otp debuger block5 data register8. + * Otp debugger block5 data register8. */ typedef union { struct { @@ -1090,7 +1090,7 @@ typedef union { /** Group: OTP_DEBUG Block5 Word9 Data */ /** Type of blk5_w9 register - * Otp debuger block5 data register9. + * Otp debugger block5 data register9. */ typedef union { struct { @@ -1105,7 +1105,7 @@ typedef union { /** Group: OTP_DEBUG Block5 Word10 Data */ /** Type of blk5_w10 register - * Otp debuger block5 data register10. + * Otp debugger block5 data register10. */ typedef union { struct { @@ -1120,7 +1120,7 @@ typedef union { /** Group: OTP_DEBUG Block5 Word11 Data */ /** Type of blk5_w11 register - * Otp debuger block5 data register11. + * Otp debugger block5 data register11. */ typedef union { struct { @@ -1135,7 +1135,7 @@ typedef union { /** Group: OTP_DEBUG Block6 Word1 Data */ /** Type of blk6_w1 register - * Otp debuger block6 data register1. + * Otp debugger block6 data register1. */ typedef union { struct { @@ -1150,7 +1150,7 @@ typedef union { /** Group: OTP_DEBUG Block6 Word2 Data */ /** Type of blk6_w2 register - * Otp debuger block6 data register2. + * Otp debugger block6 data register2. */ typedef union { struct { @@ -1165,7 +1165,7 @@ typedef union { /** Group: OTP_DEBUG Block6 Word3 Data */ /** Type of blk6_w3 register - * Otp debuger block6 data register3. + * Otp debugger block6 data register3. */ typedef union { struct { @@ -1180,7 +1180,7 @@ typedef union { /** Group: OTP_DEBUG Block6 Word4 Data */ /** Type of blk6_w4 register - * Otp debuger block6 data register4. + * Otp debugger block6 data register4. */ typedef union { struct { @@ -1195,7 +1195,7 @@ typedef union { /** Group: OTP_DEBUG Block6 Word5 Data */ /** Type of blk6_w5 register - * Otp debuger block6 data register5. + * Otp debugger block6 data register5. */ typedef union { struct { @@ -1210,7 +1210,7 @@ typedef union { /** Group: OTP_DEBUG Block6 Word6 Data */ /** Type of blk6_w6 register - * Otp debuger block6 data register6. + * Otp debugger block6 data register6. */ typedef union { struct { @@ -1225,7 +1225,7 @@ typedef union { /** Group: OTP_DEBUG Block6 Word7 Data */ /** Type of blk6_w7 register - * Otp debuger block6 data register7. + * Otp debugger block6 data register7. */ typedef union { struct { @@ -1240,7 +1240,7 @@ typedef union { /** Group: OTP_DEBUG Block6 Word8 Data */ /** Type of blk6_w8 register - * Otp debuger block6 data register8. + * Otp debugger block6 data register8. */ typedef union { struct { @@ -1255,7 +1255,7 @@ typedef union { /** Group: OTP_DEBUG Block6 Word9 Data */ /** Type of blk6_w9 register - * Otp debuger block6 data register9. + * Otp debugger block6 data register9. */ typedef union { struct { @@ -1270,7 +1270,7 @@ typedef union { /** Group: OTP_DEBUG Block6 Word10 Data */ /** Type of blk6_w10 register - * Otp debuger block6 data register10. + * Otp debugger block6 data register10. */ typedef union { struct { @@ -1285,7 +1285,7 @@ typedef union { /** Group: OTP_DEBUG Block6 Word11 Data */ /** Type of blk6_w11 register - * Otp debuger block6 data register11. + * Otp debugger block6 data register11. */ typedef union { struct { @@ -1300,7 +1300,7 @@ typedef union { /** Group: OTP_DEBUG Block7 Word1 Data */ /** Type of blk7_w1 register - * Otp debuger block7 data register1. + * Otp debugger block7 data register1. */ typedef union { struct { @@ -1315,7 +1315,7 @@ typedef union { /** Group: OTP_DEBUG Block7 Word2 Data */ /** Type of blk7_w2 register - * Otp debuger block7 data register2. + * Otp debugger block7 data register2. */ typedef union { struct { @@ -1330,7 +1330,7 @@ typedef union { /** Group: OTP_DEBUG Block7 Word3 Data */ /** Type of blk7_w3 register - * Otp debuger block7 data register3. + * Otp debugger block7 data register3. */ typedef union { struct { @@ -1345,7 +1345,7 @@ typedef union { /** Group: OTP_DEBUG Block7 Word4 Data */ /** Type of blk7_w4 register - * Otp debuger block7 data register4. + * Otp debugger block7 data register4. */ typedef union { struct { @@ -1360,7 +1360,7 @@ typedef union { /** Group: OTP_DEBUG Block7 Word5 Data */ /** Type of blk7_w5 register - * Otp debuger block7 data register5. + * Otp debugger block7 data register5. */ typedef union { struct { @@ -1375,7 +1375,7 @@ typedef union { /** Group: OTP_DEBUG Block7 Word6 Data */ /** Type of blk7_w6 register - * Otp debuger block7 data register6. + * Otp debugger block7 data register6. */ typedef union { struct { @@ -1390,7 +1390,7 @@ typedef union { /** Group: OTP_DEBUG Block7 Word7 Data */ /** Type of blk7_w7 register - * Otp debuger block7 data register7. + * Otp debugger block7 data register7. */ typedef union { struct { @@ -1405,7 +1405,7 @@ typedef union { /** Group: OTP_DEBUG Block7 Word8 Data */ /** Type of blk7_w8 register - * Otp debuger block7 data register8. + * Otp debugger block7 data register8. */ typedef union { struct { @@ -1420,7 +1420,7 @@ typedef union { /** Group: OTP_DEBUG Block7 Word9 Data */ /** Type of blk7_w9 register - * Otp debuger block7 data register9. + * Otp debugger block7 data register9. */ typedef union { struct { @@ -1435,7 +1435,7 @@ typedef union { /** Group: OTP_DEBUG Block7 Word10 Data */ /** Type of blk7_w10 register - * Otp debuger block7 data register10. + * Otp debugger block7 data register10. */ typedef union { struct { @@ -1450,7 +1450,7 @@ typedef union { /** Group: OTP_DEBUG Block7 Word11 Data */ /** Type of blk7_w11 register - * Otp debuger block7 data register11. + * Otp debugger block7 data register11. */ typedef union { struct { @@ -1465,7 +1465,7 @@ typedef union { /** Group: OTP_DEBUG Block8 Word1 Data */ /** Type of blk8_w1 register - * Otp debuger block8 data register1. + * Otp debugger block8 data register1. */ typedef union { struct { @@ -1480,7 +1480,7 @@ typedef union { /** Group: OTP_DEBUG Block8 Word2 Data */ /** Type of blk8_w2 register - * Otp debuger block8 data register2. + * Otp debugger block8 data register2. */ typedef union { struct { @@ -1495,7 +1495,7 @@ typedef union { /** Group: OTP_DEBUG Block8 Word3 Data */ /** Type of blk8_w3 register - * Otp debuger block8 data register3. + * Otp debugger block8 data register3. */ typedef union { struct { @@ -1510,7 +1510,7 @@ typedef union { /** Group: OTP_DEBUG Block8 Word4 Data */ /** Type of blk8_w4 register - * Otp debuger block8 data register4. + * Otp debugger block8 data register4. */ typedef union { struct { @@ -1525,7 +1525,7 @@ typedef union { /** Group: OTP_DEBUG Block8 Word5 Data */ /** Type of blk8_w5 register - * Otp debuger block8 data register5. + * Otp debugger block8 data register5. */ typedef union { struct { @@ -1540,7 +1540,7 @@ typedef union { /** Group: OTP_DEBUG Block8 Word6 Data */ /** Type of blk8_w6 register - * Otp debuger block8 data register6. + * Otp debugger block8 data register6. */ typedef union { struct { @@ -1555,7 +1555,7 @@ typedef union { /** Group: OTP_DEBUG Block8 Word7 Data */ /** Type of blk8_w7 register - * Otp debuger block8 data register7. + * Otp debugger block8 data register7. */ typedef union { struct { @@ -1570,7 +1570,7 @@ typedef union { /** Group: OTP_DEBUG Block8 Word8 Data */ /** Type of blk8_w8 register - * Otp debuger block8 data register8. + * Otp debugger block8 data register8. */ typedef union { struct { @@ -1585,7 +1585,7 @@ typedef union { /** Group: OTP_DEBUG Block8 Word9 Data */ /** Type of blk8_w9 register - * Otp debuger block8 data register9. + * Otp debugger block8 data register9. */ typedef union { struct { @@ -1600,7 +1600,7 @@ typedef union { /** Group: OTP_DEBUG Block8 Word10 Data */ /** Type of blk8_w10 register - * Otp debuger block8 data register10. + * Otp debugger block8 data register10. */ typedef union { struct { @@ -1615,7 +1615,7 @@ typedef union { /** Group: OTP_DEBUG Block8 Word11 Data */ /** Type of blk8_w11 register - * Otp debuger block8 data register11. + * Otp debugger block8 data register11. */ typedef union { struct { @@ -1630,7 +1630,7 @@ typedef union { /** Group: OTP_DEBUG Block9 Word1 Data */ /** Type of blk9_w1 register - * Otp debuger block9 data register1. + * Otp debugger block9 data register1. */ typedef union { struct { @@ -1645,7 +1645,7 @@ typedef union { /** Group: OTP_DEBUG Block9 Word2 Data */ /** Type of blk9_w2 register - * Otp debuger block9 data register2. + * Otp debugger block9 data register2. */ typedef union { struct { @@ -1660,7 +1660,7 @@ typedef union { /** Group: OTP_DEBUG Block9 Word3 Data */ /** Type of blk9_w3 register - * Otp debuger block9 data register3. + * Otp debugger block9 data register3. */ typedef union { struct { @@ -1675,7 +1675,7 @@ typedef union { /** Group: OTP_DEBUG Block9 Word4 Data */ /** Type of blk9_w4 register - * Otp debuger block9 data register4. + * Otp debugger block9 data register4. */ typedef union { struct { @@ -1690,7 +1690,7 @@ typedef union { /** Group: OTP_DEBUG Block9 Word5 Data */ /** Type of blk9_w5 register - * Otp debuger block9 data register5. + * Otp debugger block9 data register5. */ typedef union { struct { @@ -1705,7 +1705,7 @@ typedef union { /** Group: OTP_DEBUG Block9 Word6 Data */ /** Type of blk9_w6 register - * Otp debuger block9 data register6. + * Otp debugger block9 data register6. */ typedef union { struct { @@ -1720,7 +1720,7 @@ typedef union { /** Group: OTP_DEBUG Block9 Word7 Data */ /** Type of blk9_w7 register - * Otp debuger block9 data register7. + * Otp debugger block9 data register7. */ typedef union { struct { @@ -1735,7 +1735,7 @@ typedef union { /** Group: OTP_DEBUG Block9 Word8 Data */ /** Type of blk9_w8 register - * Otp debuger block9 data register8. + * Otp debugger block9 data register8. */ typedef union { struct { @@ -1750,7 +1750,7 @@ typedef union { /** Group: OTP_DEBUG Block9 Word9 Data */ /** Type of blk9_w9 register - * Otp debuger block9 data register9. + * Otp debugger block9 data register9. */ typedef union { struct { @@ -1765,7 +1765,7 @@ typedef union { /** Group: OTP_DEBUG Block9 Word10 Data */ /** Type of blk9_w10 register - * Otp debuger block9 data register10. + * Otp debugger block9 data register10. */ typedef union { struct { @@ -1780,7 +1780,7 @@ typedef union { /** Group: OTP_DEBUG Block9 Word11 Data */ /** Type of blk9_w11 register - * Otp debuger block9 data register11. + * Otp debugger block9 data register11. */ typedef union { struct { @@ -1795,7 +1795,7 @@ typedef union { /** Group: OTP_DEBUG Block10 Word1 Data */ /** Type of blk10_w1 register - * Otp debuger block10 data register1. + * Otp debugger block10 data register1. */ typedef union { struct { @@ -1810,7 +1810,7 @@ typedef union { /** Group: OTP_DEBUG Block10 Word2 Data */ /** Type of blk10_w2 register - * Otp debuger block10 data register2. + * Otp debugger block10 data register2. */ typedef union { struct { @@ -1825,7 +1825,7 @@ typedef union { /** Group: OTP_DEBUG Block10 Word3 Data */ /** Type of blk10_w3 register - * Otp debuger block10 data register3. + * Otp debugger block10 data register3. */ typedef union { struct { @@ -1840,7 +1840,7 @@ typedef union { /** Group: OTP_DEBUG Block10 Word4 Data */ /** Type of blk10_w4 register - * Otp debuger block10 data register4. + * Otp debugger block10 data register4. */ typedef union { struct { @@ -1855,7 +1855,7 @@ typedef union { /** Group: OTP_DEBUG Block10 Word5 Data */ /** Type of blk10_w5 register - * Otp debuger block10 data register5. + * Otp debugger block10 data register5. */ typedef union { struct { @@ -1870,7 +1870,7 @@ typedef union { /** Group: OTP_DEBUG Block10 Word6 Data */ /** Type of blk10_w6 register - * Otp debuger block10 data register6. + * Otp debugger block10 data register6. */ typedef union { struct { @@ -1885,7 +1885,7 @@ typedef union { /** Group: OTP_DEBUG Block10 Word7 Data */ /** Type of blk10_w7 register - * Otp debuger block10 data register7. + * Otp debugger block10 data register7. */ typedef union { struct { @@ -1900,7 +1900,7 @@ typedef union { /** Group: OTP_DEBUG Block10 Word8 Data */ /** Type of blk10_w8 register - * Otp debuger block10 data register8. + * Otp debugger block10 data register8. */ typedef union { struct { @@ -1915,7 +1915,7 @@ typedef union { /** Group: OTP_DEBUG Block10 Word9 Data */ /** Type of blk10_w9 register - * Otp debuger block10 data register9. + * Otp debugger block10 data register9. */ typedef union { struct { @@ -1930,7 +1930,7 @@ typedef union { /** Group: OTP_DEBUG Block10 Word10 Data */ /** Type of blk10_w10 register - * Otp debuger block10 data register10. + * Otp debugger block10 data register10. */ typedef union { struct { @@ -1945,7 +1945,7 @@ typedef union { /** Group: OTP_DEBUG Clock_en Configuration Register */ /** Type of clk register - * Otp debuger clk_en configuration register. + * Otp debugger clk_en configuration register. */ typedef union { struct { @@ -1959,7 +1959,7 @@ typedef union { } otp_debug_clk_reg_t; -/** Group: OTP_DEBUG Apb2otp Enable Singal */ +/** Group: OTP_DEBUG Apb2otp Enable Signal */ /** Type of apb2otp_en register * Otp_debuger apb2otp enable configuration register. */ diff --git a/components/soc/esp32c6/include/soc/parl_io_reg.h b/components/soc/esp32c6/register/soc/parl_io_reg.h similarity index 98% rename from components/soc/esp32c6/include/soc/parl_io_reg.h rename to components/soc/esp32c6/register/soc/parl_io_reg.h index 7377e9788b3..191656298c4 100644 --- a/components/soc/esp32c6/include/soc/parl_io_reg.h +++ b/components/soc/esp32c6/register/soc/parl_io_reg.h @@ -31,7 +31,7 @@ extern "C" { #define PARL_IO_RX_START_V 0x00000001U #define PARL_IO_RX_START_S 1 /** PARL_IO_RX_DATA_BYTELEN : R/W; bitpos: [17:2]; default: 0; - * Configures rx receieved data byte length. + * Configures rx received data byte length. */ #define PARL_IO_RX_DATA_BYTELEN 0x0000FFFFU #define PARL_IO_RX_DATA_BYTELEN_M (PARL_IO_RX_DATA_BYTELEN_V << PARL_IO_RX_DATA_BYTELEN_S) @@ -251,7 +251,7 @@ extern "C" { #define PARL_IO_TX_READY_S 31 /** PARL_IO_INT_ENA_REG register - * Parallel IO interrupt enable singal configuration register. + * Parallel IO interrupt enable signal configuration register. */ #define PARL_IO_INT_ENA_REG (DR_REG_PARL_IO_BASE + 0x14) /** PARL_IO_TX_FIFO_REMPTY_INT_ENA : R/W; bitpos: [0]; default: 0; @@ -277,7 +277,7 @@ extern "C" { #define PARL_IO_TX_EOF_INT_ENA_S 2 /** PARL_IO_INT_RAW_REG register - * Parallel IO interrupt raw singal status register. + * Parallel IO interrupt raw signal status register. */ #define PARL_IO_INT_RAW_REG (DR_REG_PARL_IO_BASE + 0x18) /** PARL_IO_TX_FIFO_REMPTY_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; @@ -303,7 +303,7 @@ extern "C" { #define PARL_IO_TX_EOF_INT_RAW_S 2 /** PARL_IO_INT_ST_REG register - * Parallel IO interrupt singal status register. + * Parallel IO interrupt signal status register. */ #define PARL_IO_INT_ST_REG (DR_REG_PARL_IO_BASE + 0x1c) /** PARL_IO_TX_FIFO_REMPTY_INT_ST : RO; bitpos: [0]; default: 0; @@ -329,7 +329,7 @@ extern "C" { #define PARL_IO_TX_EOF_INT_ST_S 2 /** PARL_IO_INT_CLR_REG register - * Parallel IO interrupt clear singal configuration register. + * Parallel IO interrupt clear signal configuration register. */ #define PARL_IO_INT_CLR_REG (DR_REG_PARL_IO_BASE + 0x20) /** PARL_IO_TX_FIFO_REMPTY_INT_CLR : WT; bitpos: [0]; default: 0; diff --git a/components/soc/esp32c6/include/soc/parl_io_struct.h b/components/soc/esp32c6/register/soc/parl_io_struct.h similarity index 97% rename from components/soc/esp32c6/include/soc/parl_io_struct.h rename to components/soc/esp32c6/register/soc/parl_io_struct.h index 816a7de3ef1..e0000ebc56b 100644 --- a/components/soc/esp32c6/include/soc/parl_io_struct.h +++ b/components/soc/esp32c6/register/soc/parl_io_struct.h @@ -26,7 +26,7 @@ typedef union { */ uint32_t rx_start:1; /** rx_data_bytelen : R/W; bitpos: [17:2]; default: 0; - * Configures rx receieved data byte length. + * Configures rx received data byte length. */ uint32_t rx_data_bytelen:16; /** rx_sw_en : R/W; bitpos: [18]; default: 0; @@ -213,7 +213,7 @@ typedef union { /** Group: PARL_IO Interrupt Configuration and Status */ /** Type of int_ena register - * Parallel IO interrupt enable singal configuration register. + * Parallel IO interrupt enable signal configuration register. */ typedef union { struct { @@ -235,7 +235,7 @@ typedef union { } parl_io_int_ena_reg_t; /** Type of int_raw register - * Parallel IO interrupt raw singal status register. + * Parallel IO interrupt raw signal status register. */ typedef union { struct { @@ -257,7 +257,7 @@ typedef union { } parl_io_int_raw_reg_t; /** Type of int_st register - * Parallel IO interrupt singal status register. + * Parallel IO interrupt signal status register. */ typedef union { struct { @@ -279,7 +279,7 @@ typedef union { } parl_io_int_st_reg_t; /** Type of int_clr register - * Parallel IO interrupt clear singal configuration register. + * Parallel IO interrupt clear signal configuration register. */ typedef union { struct { diff --git a/components/soc/esp32c6/include/soc/pau_reg.h b/components/soc/esp32c6/register/soc/pau_reg.h similarity index 100% rename from components/soc/esp32c6/include/soc/pau_reg.h rename to components/soc/esp32c6/register/soc/pau_reg.h diff --git a/components/soc/esp32c6/include/soc/pau_struct.h b/components/soc/esp32c6/register/soc/pau_struct.h similarity index 100% rename from components/soc/esp32c6/include/soc/pau_struct.h rename to components/soc/esp32c6/register/soc/pau_struct.h diff --git a/components/soc/esp32c6/include/soc/pcnt_reg.h b/components/soc/esp32c6/register/soc/pcnt_reg.h similarity index 100% rename from components/soc/esp32c6/include/soc/pcnt_reg.h rename to components/soc/esp32c6/register/soc/pcnt_reg.h diff --git a/components/soc/esp32c6/include/soc/pcnt_struct.h b/components/soc/esp32c6/register/soc/pcnt_struct.h similarity index 100% rename from components/soc/esp32c6/include/soc/pcnt_struct.h rename to components/soc/esp32c6/register/soc/pcnt_struct.h diff --git a/components/soc/esp32c6/include/soc/pcr_reg.h b/components/soc/esp32c6/register/soc/pcr_reg.h similarity index 98% rename from components/soc/esp32c6/include/soc/pcr_reg.h rename to components/soc/esp32c6/register/soc/pcr_reg.h index 35a77baaab4..466b25f0201 100644 --- a/components/soc/esp32c6/include/soc/pcr_reg.h +++ b/components/soc/esp32c6/register/soc/pcr_reg.h @@ -201,7 +201,7 @@ extern "C" { #define PCR_MSPI_CLK_CONF_REG (DR_REG_PCR_BASE + 0x1c) /** PCR_MSPI_FAST_LS_DIV_NUM : R/W; bitpos: [7:0]; default: 0; * Set as one within (0,1,2) to generate div1(default)/div2/div4 of low-speed - * clock-source to drive clk_mspi_fast. Only avaiable whe the clck-source is a + * clock-source to drive clk_mspi_fast. Only available when the clck-source is a * low-speed clock-source such as XTAL/FOSC. */ #define PCR_MSPI_FAST_LS_DIV_NUM 0x000000FFU @@ -210,7 +210,7 @@ extern "C" { #define PCR_MSPI_FAST_LS_DIV_NUM_S 0 /** PCR_MSPI_FAST_HS_DIV_NUM : R/W; bitpos: [15:8]; default: 3; * Set as one within (3,4,5) to generate div4(default)/div5/div6 of high-speed - * clock-source to drive clk_mspi_fast. Only avaiable whe the clck-source is a + * clock-source to drive clk_mspi_fast. Only available when the clck-source is a * high-speed clock-source such as SPLL. */ #define PCR_MSPI_FAST_HS_DIV_NUM 0x000000FFU @@ -1163,7 +1163,7 @@ extern "C" { #define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_V 0x0000000FU #define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_S 0 /** PCR_PVT_MONITOR_FUNC_CLK_SEL : R/W; bitpos: [20]; default: 0; - * set this field to select clock-source. 0: XTAL, 1(default): 160MHz drived by SPLL + * set this field to select clock-source. 0: XTAL, 1(default): 160MHz driven by SPLL * divided by 3. */ #define PCR_PVT_MONITOR_FUNC_CLK_SEL (BIT(20)) @@ -1666,8 +1666,8 @@ extern "C" { */ #define PCR_CPU_FREQ_CONF_REG (DR_REG_PCR_BASE + 0x118) /** PCR_CPU_LS_DIV_NUM : R/W; bitpos: [7:0]; default: 0; - * Set as one within (0,1,3) to generate clk_cpu drived by clk_hproot. The clk_cpu is - * div1(default)/div2/div4 of clk_hproot. This field is only avaliable for low-speed + * Set as one within (0,1,3) to generate clk_cpu driven by clk_hproot. The clk_cpu is + * div1(default)/div2/div4 of clk_hproot. This field is only available for low-speed * clock-source such as XTAL/FOSC, and should be used together with PCR_AHB_LS_DIV_NUM. */ #define PCR_CPU_LS_DIV_NUM 0x000000FFU @@ -1675,8 +1675,8 @@ extern "C" { #define PCR_CPU_LS_DIV_NUM_V 0x000000FFU #define PCR_CPU_LS_DIV_NUM_S 0 /** PCR_CPU_HS_DIV_NUM : R/W; bitpos: [15:8]; default: 0; - * Set as one within (0,1,3) to generate clk_cpu drived by clk_hproot. The clk_cpu is - * div1(default)/div2/div4 of clk_hproot. This field is only avaliable for high-speed + * Set as one within (0,1,3) to generate clk_cpu driven by clk_hproot. The clk_cpu is + * div1(default)/div2/div4 of clk_hproot. This field is only available for high-speed * clock-source such as SPLL, and should be used together with PCR_AHB_HS_DIV_NUM. */ #define PCR_CPU_HS_DIV_NUM 0x000000FFU @@ -1685,7 +1685,7 @@ extern "C" { #define PCR_CPU_HS_DIV_NUM_S 8 /** PCR_CPU_HS_120M_FORCE : R/W; bitpos: [16]; default: 0; * Given that PCR_CPU_HS_DIV_NUM is 0, set this field as 1 to force clk_cpu at 120MHz. - * Only avaliable when PCR_CPU_HS_DIV_NUM is 0 and clk_cpu is driven by SPLL. + * Only available when PCR_CPU_HS_DIV_NUM is 0 and clk_cpu is driven by SPLL. */ #define PCR_CPU_HS_120M_FORCE (BIT(16)) #define PCR_CPU_HS_120M_FORCE_M (PCR_CPU_HS_120M_FORCE_V << PCR_CPU_HS_120M_FORCE_S) @@ -1697,8 +1697,8 @@ extern "C" { */ #define PCR_AHB_FREQ_CONF_REG (DR_REG_PCR_BASE + 0x11c) /** PCR_AHB_LS_DIV_NUM : R/W; bitpos: [7:0]; default: 0; - * Set as one within (0,1,3,7) to generate clk_ahb drived by clk_hproot. The clk_ahb - * is div1(default)/div2/div4/div8 of clk_hproot. This field is only avaliable for + * Set as one within (0,1,3,7) to generate clk_ahb driven by clk_hproot. The clk_ahb + * is div1(default)/div2/div4/div8 of clk_hproot. This field is only available for * low-speed clock-source such as XTAL/FOSC, and should be used together with * PCR_CPU_LS_DIV_NUM. */ @@ -1707,8 +1707,8 @@ extern "C" { #define PCR_AHB_LS_DIV_NUM_V 0x000000FFU #define PCR_AHB_LS_DIV_NUM_S 0 /** PCR_AHB_HS_DIV_NUM : R/W; bitpos: [15:8]; default: 3; - * Set as one within (3,7,15) to generate clk_ahb drived by clk_hproot. The clk_ahb is - * div4(default)/div8/div16 of clk_hproot. This field is only avaliable for high-speed + * Set as one within (3,7,15) to generate clk_ahb driven by clk_hproot. The clk_ahb is + * div4(default)/div8/div16 of clk_hproot. This field is only available for high-speed * clock-source such as SPLL, and should be used together with PCR_CPU_HS_DIV_NUM. */ #define PCR_AHB_HS_DIV_NUM 0x000000FFU @@ -1734,7 +1734,7 @@ extern "C" { #define PCR_APB_DECREASE_DIV_NUM_V 0x000000FFU #define PCR_APB_DECREASE_DIV_NUM_S 0 /** PCR_APB_DIV_NUM : R/W; bitpos: [15:8]; default: 0; - * Set as one within (0,1,3) to generate clk_apb drived by clk_ahb. The clk_apb is + * Set as one within (0,1,3) to generate clk_apb driven by clk_ahb. The clk_apb is * div1(default)/div2/div4 of clk_ahb. */ #define PCR_APB_DIV_NUM 0x000000FFU @@ -1766,56 +1766,56 @@ extern "C" { */ #define PCR_PLL_DIV_CLK_EN_REG (DR_REG_PCR_BASE + 0x128) /** PCR_PLL_240M_CLK_EN : R/W; bitpos: [0]; default: 1; - * This field is used to open 240 MHz clock (div2 of SPLL) drived from SPLL. 0: close, - * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + * This field is used to open 240 MHz clock (div2 of SPLL) driven from SPLL. 0: close, + * 1: open(default). Only available when high-speed clock-source SPLL is active. */ #define PCR_PLL_240M_CLK_EN (BIT(0)) #define PCR_PLL_240M_CLK_EN_M (PCR_PLL_240M_CLK_EN_V << PCR_PLL_240M_CLK_EN_S) #define PCR_PLL_240M_CLK_EN_V 0x00000001U #define PCR_PLL_240M_CLK_EN_S 0 /** PCR_PLL_160M_CLK_EN : R/W; bitpos: [1]; default: 1; - * This field is used to open 160 MHz clock (div3 of SPLL) drived from SPLL. 0: close, - * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + * This field is used to open 160 MHz clock (div3 of SPLL) driven from SPLL. 0: close, + * 1: open(default). Only available when high-speed clock-source SPLL is active. */ #define PCR_PLL_160M_CLK_EN (BIT(1)) #define PCR_PLL_160M_CLK_EN_M (PCR_PLL_160M_CLK_EN_V << PCR_PLL_160M_CLK_EN_S) #define PCR_PLL_160M_CLK_EN_V 0x00000001U #define PCR_PLL_160M_CLK_EN_S 1 /** PCR_PLL_120M_CLK_EN : R/W; bitpos: [2]; default: 1; - * This field is used to open 120 MHz clock (div4 of SPLL) drived from SPLL. 0: close, - * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + * This field is used to open 120 MHz clock (div4 of SPLL) driven from SPLL. 0: close, + * 1: open(default). Only available when high-speed clock-source SPLL is active. */ #define PCR_PLL_120M_CLK_EN (BIT(2)) #define PCR_PLL_120M_CLK_EN_M (PCR_PLL_120M_CLK_EN_V << PCR_PLL_120M_CLK_EN_S) #define PCR_PLL_120M_CLK_EN_V 0x00000001U #define PCR_PLL_120M_CLK_EN_S 2 /** PCR_PLL_80M_CLK_EN : R/W; bitpos: [3]; default: 1; - * This field is used to open 80 MHz clock (div6 of SPLL) drived from SPLL. 0: close, - * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + * This field is used to open 80 MHz clock (div6 of SPLL) driven from SPLL. 0: close, + * 1: open(default). Only available when high-speed clock-source SPLL is active. */ #define PCR_PLL_80M_CLK_EN (BIT(3)) #define PCR_PLL_80M_CLK_EN_M (PCR_PLL_80M_CLK_EN_V << PCR_PLL_80M_CLK_EN_S) #define PCR_PLL_80M_CLK_EN_V 0x00000001U #define PCR_PLL_80M_CLK_EN_S 3 /** PCR_PLL_48M_CLK_EN : R/W; bitpos: [4]; default: 1; - * This field is used to open 48 MHz clock (div10 of SPLL) drived from SPLL. 0: close, - * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + * This field is used to open 48 MHz clock (div10 of SPLL) driven from SPLL. 0: close, + * 1: open(default). Only available when high-speed clock-source SPLL is active. */ #define PCR_PLL_48M_CLK_EN (BIT(4)) #define PCR_PLL_48M_CLK_EN_M (PCR_PLL_48M_CLK_EN_V << PCR_PLL_48M_CLK_EN_S) #define PCR_PLL_48M_CLK_EN_V 0x00000001U #define PCR_PLL_48M_CLK_EN_S 4 /** PCR_PLL_40M_CLK_EN : R/W; bitpos: [5]; default: 1; - * This field is used to open 40 MHz clock (div12 of SPLL) drived from SPLL. 0: close, - * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + * This field is used to open 40 MHz clock (div12 of SPLL) driven from SPLL. 0: close, + * 1: open(default). Only available when high-speed clock-source SPLL is active. */ #define PCR_PLL_40M_CLK_EN (BIT(5)) #define PCR_PLL_40M_CLK_EN_M (PCR_PLL_40M_CLK_EN_V << PCR_PLL_40M_CLK_EN_S) #define PCR_PLL_40M_CLK_EN_V 0x00000001U #define PCR_PLL_40M_CLK_EN_S 5 /** PCR_PLL_20M_CLK_EN : R/W; bitpos: [6]; default: 1; - * This field is used to open 20 MHz clock (div24 of SPLL) drived from SPLL. 0: close, - * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + * This field is used to open 20 MHz clock (div24 of SPLL) driven from SPLL. 0: close, + * 1: open(default). Only available when high-speed clock-source SPLL is active. */ #define PCR_PLL_20M_CLK_EN (BIT(6)) #define PCR_PLL_20M_CLK_EN_M (PCR_PLL_20M_CLK_EN_V << PCR_PLL_20M_CLK_EN_S) diff --git a/components/soc/esp32c6/include/soc/pcr_struct.h b/components/soc/esp32c6/register/soc/pcr_struct.h similarity index 97% rename from components/soc/esp32c6/include/soc/pcr_struct.h rename to components/soc/esp32c6/register/soc/pcr_struct.h index f31e632d865..ee74db8ff14 100644 --- a/components/soc/esp32c6/include/soc/pcr_struct.h +++ b/components/soc/esp32c6/register/soc/pcr_struct.h @@ -176,13 +176,13 @@ typedef union { struct { /** mspi_fast_ls_div_num : R/W; bitpos: [7:0]; default: 0; * Set as one within (0,1,2) to generate div1(default)/div2/div4 of low-speed - * clock-source to drive clk_mspi_fast. Only avaiable whe the clck-source is a + * clock-source to drive clk_mspi_fast. Only available when the clck-source is a * low-speed clock-source such as XTAL/FOSC. */ uint32_t mspi_fast_ls_div_num:8; /** mspi_fast_hs_div_num : R/W; bitpos: [15:8]; default: 3; * Set as one within (3,4,5) to generate div4(default)/div5/div6 of high-speed - * clock-source to drive clk_mspi_fast. Only avaiable whe the clck-source is a + * clock-source to drive clk_mspi_fast. Only available when the clck-source is a * high-speed clock-source such as SPLL. */ uint32_t mspi_fast_hs_div_num:8; @@ -1033,7 +1033,7 @@ typedef union { uint32_t pvt_monitor_func_clk_div_num:4; uint32_t reserved_4:16; /** pvt_monitor_func_clk_sel : R/W; bitpos: [20]; default: 0; - * set this field to select clock-source. 0: XTAL, 1(default): 160MHz drived by SPLL + * set this field to select clock-source. 0: XTAL, 1(default): 160MHz driven by SPLL * divided by 3. */ uint32_t pvt_monitor_func_clk_sel:1; @@ -1499,20 +1499,20 @@ typedef union { typedef union { struct { /** cpu_ls_div_num : R/W; bitpos: [7:0]; default: 0; - * Set as one within (0,1,3) to generate clk_cpu drived by clk_hproot. The clk_cpu is - * div1(default)/div2/div4 of clk_hproot. This field is only avaliable for low-speed + * Set as one within (0,1,3) to generate clk_cpu driven by clk_hproot. The clk_cpu is + * div1(default)/div2/div4 of clk_hproot. This field is only available for low-speed * clock-source such as XTAL/FOSC, and should be used together with PCR_AHB_LS_DIV_NUM. */ uint32_t cpu_ls_div_num:8; /** cpu_hs_div_num : R/W; bitpos: [15:8]; default: 0; - * Set as one within (0,1,3) to generate clk_cpu drived by clk_hproot. The clk_cpu is - * div1(default)/div2/div4 of clk_hproot. This field is only avaliable for high-speed + * Set as one within (0,1,3) to generate clk_cpu driven by clk_hproot. The clk_cpu is + * div1(default)/div2/div4 of clk_hproot. This field is only available for high-speed * clock-source such as SPLL, and should be used together with PCR_AHB_HS_DIV_NUM. */ uint32_t cpu_hs_div_num:8; /** cpu_hs_120m_force : R/W; bitpos: [16]; default: 0; * Given that PCR_CPU_HS_DIV_NUM is 0, set this field as 1 to force clk_cpu at 120MHz. - * Only avaliable when PCR_CPU_HS_DIV_NUM is 0 and clk_cpu is driven by SPLL. + * Only available when PCR_CPU_HS_DIV_NUM is 0 and clk_cpu is driven by SPLL. */ uint32_t cpu_hs_120m_force:1; uint32_t reserved_17:15; @@ -1526,15 +1526,15 @@ typedef union { typedef union { struct { /** ahb_ls_div_num : R/W; bitpos: [7:0]; default: 0; - * Set as one within (0,1,3,7) to generate clk_ahb drived by clk_hproot. The clk_ahb - * is div1(default)/div2/div4/div8 of clk_hproot. This field is only avaliable for + * Set as one within (0,1,3,7) to generate clk_ahb driven by clk_hproot. The clk_ahb + * is div1(default)/div2/div4/div8 of clk_hproot. This field is only available for * low-speed clock-source such as XTAL/FOSC, and should be used together with * PCR_CPU_LS_DIV_NUM. */ uint32_t ahb_ls_div_num:8; /** ahb_hs_div_num : R/W; bitpos: [15:8]; default: 3; - * Set as one within (3,7,15) to generate clk_ahb drived by clk_hproot. The clk_ahb is - * div4(default)/div8/div16 of clk_hproot. This field is only avaliable for high-speed + * Set as one within (3,7,15) to generate clk_ahb driven by clk_hproot. The clk_ahb is + * div4(default)/div8/div16 of clk_hproot. This field is only available for high-speed * clock-source such as SPLL, and should be used together with PCR_CPU_HS_DIV_NUM. */ uint32_t ahb_hs_div_num:8; @@ -1559,7 +1559,7 @@ typedef union { */ uint32_t apb_decrease_div_num:8; /** apb_div_num : R/W; bitpos: [15:8]; default: 0; - * Set as one within (0,1,3) to generate clk_apb drived by clk_ahb. The clk_apb is + * Set as one within (0,1,3) to generate clk_apb driven by clk_ahb. The clk_apb is * div1(default)/div2/div4 of clk_ahb. */ uint32_t apb_div_num:8; @@ -1574,38 +1574,38 @@ typedef union { typedef union { struct { /** pll_240m_clk_en : R/W; bitpos: [0]; default: 1; - * This field is used to open 240 MHz clock (div2 of SPLL) drived from SPLL. 0: close, - * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + * This field is used to open 240 MHz clock (div2 of SPLL) driven from SPLL. 0: close, + * 1: open(default). Only available when high-speed clock-source SPLL is active. */ uint32_t pll_240m_clk_en:1; /** pll_160m_clk_en : R/W; bitpos: [1]; default: 1; - * This field is used to open 160 MHz clock (div3 of SPLL) drived from SPLL. 0: close, - * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + * This field is used to open 160 MHz clock (div3 of SPLL) driven from SPLL. 0: close, + * 1: open(default). Only available when high-speed clock-source SPLL is active. */ uint32_t pll_160m_clk_en:1; /** pll_120m_clk_en : R/W; bitpos: [2]; default: 1; - * This field is used to open 120 MHz clock (div4 of SPLL) drived from SPLL. 0: close, - * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + * This field is used to open 120 MHz clock (div4 of SPLL) driven from SPLL. 0: close, + * 1: open(default). Only available when high-speed clock-source SPLL is active. */ uint32_t pll_120m_clk_en:1; /** pll_80m_clk_en : R/W; bitpos: [3]; default: 1; - * This field is used to open 80 MHz clock (div6 of SPLL) drived from SPLL. 0: close, - * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + * This field is used to open 80 MHz clock (div6 of SPLL) driven from SPLL. 0: close, + * 1: open(default). Only available when high-speed clock-source SPLL is active. */ uint32_t pll_80m_clk_en:1; /** pll_48m_clk_en : R/W; bitpos: [4]; default: 1; - * This field is used to open 48 MHz clock (div10 of SPLL) drived from SPLL. 0: close, - * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + * This field is used to open 48 MHz clock (div10 of SPLL) driven from SPLL. 0: close, + * 1: open(default). Only available when high-speed clock-source SPLL is active. */ uint32_t pll_48m_clk_en:1; /** pll_40m_clk_en : R/W; bitpos: [5]; default: 1; - * This field is used to open 40 MHz clock (div12 of SPLL) drived from SPLL. 0: close, - * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + * This field is used to open 40 MHz clock (div12 of SPLL) driven from SPLL. 0: close, + * 1: open(default). Only available when high-speed clock-source SPLL is active. */ uint32_t pll_40m_clk_en:1; /** pll_20m_clk_en : R/W; bitpos: [6]; default: 1; - * This field is used to open 20 MHz clock (div24 of SPLL) drived from SPLL. 0: close, - * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + * This field is used to open 20 MHz clock (div24 of SPLL) driven from SPLL. 0: close, + * 1: open(default). Only available when high-speed clock-source SPLL is active. */ uint32_t pll_20m_clk_en:1; uint32_t reserved_7:25; diff --git a/components/soc/esp32c6/include/soc/plic_reg.h b/components/soc/esp32c6/register/soc/plic_reg.h similarity index 100% rename from components/soc/esp32c6/include/soc/plic_reg.h rename to components/soc/esp32c6/register/soc/plic_reg.h diff --git a/components/soc/esp32c6/include/soc/pmu_reg.h b/components/soc/esp32c6/register/soc/pmu_reg.h similarity index 100% rename from components/soc/esp32c6/include/soc/pmu_reg.h rename to components/soc/esp32c6/register/soc/pmu_reg.h diff --git a/components/soc/esp32c6/include/soc/pmu_struct.h b/components/soc/esp32c6/register/soc/pmu_struct.h similarity index 99% rename from components/soc/esp32c6/include/soc/pmu_struct.h rename to components/soc/esp32c6/register/soc/pmu_struct.h index 5d063118955..db545cfbc58 100644 --- a/components/soc/esp32c6/include/soc/pmu_struct.h +++ b/components/soc/esp32c6/register/soc/pmu_struct.h @@ -11,7 +11,7 @@ extern "C" { #endif -#include "soc.h" +#include "soc/soc.h" #include "soc/pmu_reg.h" typedef union { diff --git a/components/soc/esp32c6/include/soc/reg_base.h b/components/soc/esp32c6/register/soc/reg_base.h similarity index 100% rename from components/soc/esp32c6/include/soc/reg_base.h rename to components/soc/esp32c6/register/soc/reg_base.h diff --git a/components/soc/esp32c6/include/soc/rmt_reg.h b/components/soc/esp32c6/register/soc/rmt_reg.h similarity index 100% rename from components/soc/esp32c6/include/soc/rmt_reg.h rename to components/soc/esp32c6/register/soc/rmt_reg.h diff --git a/components/soc/esp32c6/include/soc/rmt_struct.h b/components/soc/esp32c6/register/soc/rmt_struct.h similarity index 100% rename from components/soc/esp32c6/include/soc/rmt_struct.h rename to components/soc/esp32c6/register/soc/rmt_struct.h diff --git a/components/soc/esp32c6/include/soc/rsa_reg.h b/components/soc/esp32c6/register/soc/rsa_reg.h similarity index 100% rename from components/soc/esp32c6/include/soc/rsa_reg.h rename to components/soc/esp32c6/register/soc/rsa_reg.h diff --git a/components/soc/esp32c6/include/soc/rsa_struct.h b/components/soc/esp32c6/register/soc/rsa_struct.h similarity index 100% rename from components/soc/esp32c6/include/soc/rsa_struct.h rename to components/soc/esp32c6/register/soc/rsa_struct.h diff --git a/components/soc/esp32c6/include/soc/sha_reg.h b/components/soc/esp32c6/register/soc/sha_reg.h similarity index 98% rename from components/soc/esp32c6/include/soc/sha_reg.h rename to components/soc/esp32c6/register/soc/sha_reg.h index 265f510472a..46955176e5a 100644 --- a/components/soc/esp32c6/include/soc/sha_reg.h +++ b/components/soc/esp32c6/register/soc/sha_reg.h @@ -156,7 +156,7 @@ extern "C" { #define SHA_DATE_S 0 /** SHA_H_MEM register - * Sha H memory which contains intermediate hash or finial hash. + * Sha H memory which contains intermediate hash or final hash. */ #define SHA_H_MEM (DR_REG_SHA_BASE + 0x40) #define SHA_H_MEM_SIZE_BYTES 64 diff --git a/components/soc/esp32c6/include/soc/sha_struct.h b/components/soc/esp32c6/register/soc/sha_struct.h similarity index 100% rename from components/soc/esp32c6/include/soc/sha_struct.h rename to components/soc/esp32c6/register/soc/sha_struct.h diff --git a/components/soc/esp32c6/include/soc/slc_reg.h b/components/soc/esp32c6/register/soc/slc_reg.h similarity index 100% rename from components/soc/esp32c6/include/soc/slc_reg.h rename to components/soc/esp32c6/register/soc/slc_reg.h diff --git a/components/soc/esp32c6/include/soc/slc_struct.h b/components/soc/esp32c6/register/soc/slc_struct.h similarity index 100% rename from components/soc/esp32c6/include/soc/slc_struct.h rename to components/soc/esp32c6/register/soc/slc_struct.h diff --git a/components/soc/esp32c6/include/soc/soc_etm_reg.h b/components/soc/esp32c6/register/soc/soc_etm_reg.h similarity index 100% rename from components/soc/esp32c6/include/soc/soc_etm_reg.h rename to components/soc/esp32c6/register/soc/soc_etm_reg.h diff --git a/components/soc/esp32c6/include/soc/soc_etm_struct.h b/components/soc/esp32c6/register/soc/soc_etm_struct.h similarity index 100% rename from components/soc/esp32c6/include/soc/soc_etm_struct.h rename to components/soc/esp32c6/register/soc/soc_etm_struct.h diff --git a/components/soc/esp32c6/include/soc/spi_mem_reg.h b/components/soc/esp32c6/register/soc/spi_mem_reg.h similarity index 99% rename from components/soc/esp32c6/include/soc/spi_mem_reg.h rename to components/soc/esp32c6/register/soc/spi_mem_reg.h index 81a136b8703..56ada6dc461 100644 --- a/components/soc/esp32c6/include/soc/spi_mem_reg.h +++ b/components/soc/esp32c6/register/soc/spi_mem_reg.h @@ -98,8 +98,8 @@ he bit will be cleared once the operation done.1: enable 0: disable..*/ #define SPI_MEM_FLASH_DP_S 21 /* SPI_MEM_FLASH_RES : R/W/SC ;bitpos:[20] ;default: 1'b0 ; */ /*description: This bit combined with reg_resandres bit releases Flash from the power-down stat -e or high performance mode and obtains the devices ID. The bit will be cleared o -nce the operation done.1: enable 0: disable..*/ +e or high performance mode and obtains the devices ID. The bit will be cleared once + the operation done.1: enable 0: disable..*/ #define SPI_MEM_FLASH_RES (BIT(20)) #define SPI_MEM_FLASH_RES_M (BIT(20)) #define SPI_MEM_FLASH_RES_V 0x1 @@ -128,9 +128,9 @@ peration done.1: enable 0: disable..*/ #define SPI_MEM_FLASH_PE_V 0x1 #define SPI_MEM_FLASH_PE_S 17 /* SPI_MEM_SLV_ST : RO ;bitpos:[7:4] ;default: 4'b0 ; */ -/*description: The current status of SPI0 slave FSM: mspi_st. 0: idle state, 1: preparation sta -te, 2: send command state, 3: send address state, 4: wait state, 5: read data st -ate, 6:write data state, 7: done state, 8: read data end state..*/ +/*description: The current status of SPI0 slave FSM: mspi_st. 0: idle state, 1: preparation state, +2: send command state, 3: send address state, 4: wait state, 5: read data state +, 6:write data state, 7: done state, 8: read data end state..*/ #define SPI_MEM_SLV_ST 0x0000000F #define SPI_MEM_SLV_ST_M ((SPI_MEM_SLV_ST_V)<<(SPI_MEM_SLV_ST_S)) #define SPI_MEM_SLV_ST_V 0xF @@ -162,7 +162,7 @@ lways 1. 0: Others..*/ #define SPI_MEM_DATA_IE_ALWAYS_ON_V 0x1 #define SPI_MEM_DATA_IE_ALWAYS_ON_S 31 /* SPI_MEM_DQS_IE_ALWAYS_ON : HRO ;bitpos:[30] ;default: 1'b0 ; */ -/*description: When accesses to flash, 1: the IE signals of pads connected to SPI_DQS are alway +/*description: When accesses to flash, 1: the IE signals of pads connected to SPI_DQS are always s 1. 0: Others..*/ #define SPI_MEM_DQS_IE_ALWAYS_ON (BIT(30)) #define SPI_MEM_DQS_IE_ALWAYS_ON_M (BIT(30)) @@ -234,14 +234,14 @@ UT and SPI_MEM_FREAD_DOUT. 1: enable 0: disable..*/ #define SPI_MEM_FASTRD_MODE_V 0x1 #define SPI_MEM_FASTRD_MODE_S 13 /* SPI_MEM_TX_CRC_EN : HRO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disabl +/*description: For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disable e.*/ #define SPI_MEM_TX_CRC_EN (BIT(11)) #define SPI_MEM_TX_CRC_EN_M (BIT(11)) #define SPI_MEM_TX_CRC_EN_V 0x1 #define SPI_MEM_TX_CRC_EN_S 11 /* SPI_MEM_FCS_CRC_EN : HRO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: For SPI1, initialize crc32 module before writing encrypted data to flash. Activ +/*description: For SPI1, initialize crc32 module before writing encrypted data to flash. Active e low..*/ #define SPI_MEM_FCS_CRC_EN (BIT(10)) #define SPI_MEM_FCS_CRC_EN_M (BIT(10)) @@ -397,7 +397,7 @@ y the real AXI read data back. 0: When ARSIZE 0~1, MSPI reply SLV_ERR..*/ /* SPI_MEM_CLK_MODE : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ /*description: SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delaye d one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inacti -ve 3: SPI clock is alwasy on..*/ +ve 3: SPI clock is always on..*/ #define SPI_MEM_CLK_MODE 0x00000003 #define SPI_MEM_CLK_MODE_M ((SPI_MEM_CLK_MODE_V)<<(SPI_MEM_CLK_MODE_S)) #define SPI_MEM_CLK_MODE_V 0x3 @@ -427,8 +427,8 @@ whether there is an ECC region or not..*/ #define SPI_MEM_SPLIT_TRANS_EN_V 0x1 #define SPI_MEM_SPLIT_TRANS_EN_S 24 /* SPI_MEM_ECC_16TO18_BYTE_EN : HRO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode whe -n accesses flash..*/ +/*description: Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when + accesses flash..*/ #define SPI_MEM_ECC_16TO18_BYTE_EN (BIT(14)) #define SPI_MEM_ECC_16TO18_BYTE_EN_M (BIT(14)) #define SPI_MEM_ECC_16TO18_BYTE_EN_V 0x1 @@ -808,8 +808,8 @@ he register value shall be (bit_num-1)..*/ #define SPI_MEM_SRAM_RDUMMY_CYCLELEN_V 0x3F #define SPI_MEM_SRAM_RDUMMY_CYCLELEN_S 6 /* SPI_MEM_CACHE_SRAM_USR_RCMD : HRO ;bitpos:[5] ;default: 1'b1 ; */ -/*description: For SPI0, In the external RAM mode cache read external RAM for user define comma -nd..*/ +/*description: For SPI0, In the external RAM mode cache read external RAM for user define command +..*/ #define SPI_MEM_CACHE_SRAM_USR_RCMD (BIT(5)) #define SPI_MEM_CACHE_SRAM_USR_RCMD_M (BIT(5)) #define SPI_MEM_CACHE_SRAM_USR_RCMD_V 0x1 @@ -1016,7 +1016,7 @@ e for sram..*/ #define SPI_MEM_SRAM_CLK_REG(i) (REG_SPI_MEM_BASE(i) + 0x50) /* SPI_MEM_SCLK_EQU_SYSCLK : HRO ;bitpos:[31] ;default: 1'b0 ; */ -/*description: For SPI0 external RAM interface, 1: spi_mem_clk is eqaul to system 0: spi_mem_c +/*description: For SPI0 external RAM interface, 1: spi_mem_clk is equal to system 0: spi_mem_c lk is divided from system clock..*/ #define SPI_MEM_SCLK_EQU_SYSCLK (BIT(31)) #define SPI_MEM_SCLK_EQU_SYSCLK_M (BIT(31)) @@ -1274,7 +1274,7 @@ out, status_in[15:0] is valid when two bytes of data are read out), SUS/SUS1/SUS #define SPI_MEM_FLASH_PES_EN_S 5 /* SPI_MEM_PES_PER_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */ /*description: Set this bit to enable PES end triggers PER transfer option. If this bit is 0, a -pplication should send PER after PES is done..*/ +application should send PER after PES is done..*/ #define SPI_MEM_PES_PER_EN (BIT(4)) #define SPI_MEM_PES_PER_EN_M (BIT(4)) #define SPI_MEM_PES_PER_EN_V 0x1 @@ -1296,8 +1296,8 @@ resume command is sent..*/ #define SPI_MEM_FLASH_PER_WAIT_EN_V 0x1 #define SPI_MEM_FLASH_PER_WAIT_EN_S 2 /* SPI_MEM_FLASH_PES : R/W/SC ;bitpos:[1] ;default: 1'b0 ; */ -/*description: program erase suspend bit, program erase suspend operation will be triggered whe -n the bit is set. The bit will be cleared once the operation done.1: enable 0: d +/*description: program erase suspend bit, program erase suspend operation will be triggered when +the bit is set. The bit will be cleared once the operation done.1: enable 0: d isable..*/ #define SPI_MEM_FLASH_PES (BIT(1)) #define SPI_MEM_FLASH_PES_M (BIT(1)) @@ -1541,7 +1541,7 @@ mmand is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles #define SPI_MEM_INT_RAW_REG(i) (REG_SPI_MEM_BASE(i) + 0xC8) /* SPI_MEM_BROWN_OUT_INT_RAW : R/WTC/SS ;bitpos:[10] ;default: 1'b0 ; */ /*description: The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that -chip is loosing power and RTC module sends out brown out close flash request to +chip is losing power and RTC module sends out brown out close flash request to SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered and MSPI returns to idle state. 0: Others..*/ #define SPI_MEM_BROWN_OUT_INT_RAW (BIT(10)) @@ -1584,9 +1584,9 @@ et and SPI_SMEM_ECC_ERR_INT_EN is cleared, this bit is triggered when the error his bit is triggered when the error times of SPI0/1 ECC read external RAM are eq ual or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and SP I_SMEM_ECC_ERR_INT_EN are set, this bit is triggered when the total error times -of SPI0/1 ECC read external RAM and flash are equal or bigger than SPI_MEM_ECC_E -RR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and SPI_SMEM_ECC_ERR_INT_EN are cleare -d, this bit will not be triggered..*/ +of SPI0/1 ECC read external RAM and flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. +When SPI_FMEM_ECC_ERR_INT_EN and SPI_SMEM_ECC_ERR_INT_EN are cleared, +this bit will not be triggered..*/ #define SPI_MEM_ECC_ERR_INT_RAW (BIT(5)) #define SPI_MEM_ECC_ERR_INT_RAW_M (BIT(5)) #define SPI_MEM_ECC_ERR_INT_RAW_V 0x1 @@ -2376,8 +2376,8 @@ and RDATA_AFIFO are empty and spi0_mst_st is IDLE..*/ #define SPI_MEM_ALL_FIFO_EMPTY_V 0x1 #define SPI_MEM_ALL_FIFO_EMPTY_S 26 /* SPI_MEM_AXI_ERR_ADDR : R/SS/WTC ;bitpos:[25:0] ;default: 26'h0 ; */ -/*description: This bits show the first AXI write/read invalid error or AXI write flash error a -ddress. It is cleared by when SPI_MEM_AXI_WADDR_ERR_INT_CLR, SPI_MEM_AXI_WR_FLAS +/*description: This bits show the first AXI write/read invalid error or AXI write flash error +address. It is cleared by when SPI_MEM_AXI_WADDR_ERR_INT_CLR, SPI_MEM_AXI_WR_FLAS H_ERR_IN_CLR or SPI_MEM_AXI_RADDR_ERR_IN_CLR bit is set..*/ #define SPI_MEM_AXI_ERR_ADDR 0x03FFFFFF #define SPI_MEM_AXI_ERR_ADDR_M ((SPI_MEM_AXI_ERR_ADDR_V)<<(SPI_MEM_AXI_ERR_ADDR_S)) @@ -2684,7 +2684,7 @@ ations..*/ #define SPI_MEM_SMEM_TIMING_CALI_V 0x1 #define SPI_MEM_SMEM_TIMING_CALI_S 1 /* SPI_MEM_SMEM_TIMING_CLK_ENA : HRO ;bitpos:[0] ;default: 1'b1 ; */ -/*description: For sram, the bit is used to enable timing adjust clock for all reading operatio +/*description: For sram, the bit is used to enable timing adjust clock for all reading operation ns..*/ #define SPI_MEM_SMEM_TIMING_CLK_ENA (BIT(0)) #define SPI_MEM_SMEM_TIMING_CLK_ENA_M (BIT(0)) @@ -2942,8 +2942,8 @@ SPI core clock cycles..*/ #define SPI_MEM_SMEM_CS_HOLD_DELAY_V 0x3F #define SPI_MEM_SMEM_CS_HOLD_DELAY_S 25 /* SPI_MEM_SMEM_ECC_16TO18_BYTE_EN : HRO ;bitpos:[16] ;default: 1'b0 ; */ -/*description: Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode whe -n accesses external RAM..*/ +/*description: Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when +accesses external RAM..*/ #define SPI_MEM_SMEM_ECC_16TO18_BYTE_EN (BIT(16)) #define SPI_MEM_SMEM_ECC_16TO18_BYTE_EN_M (BIT(16)) #define SPI_MEM_SMEM_ECC_16TO18_BYTE_EN_V 0x1 diff --git a/components/soc/esp32c6/include/soc/spi_mem_struct.h b/components/soc/esp32c6/register/soc/spi_mem_struct.h similarity index 99% rename from components/soc/esp32c6/include/soc/spi_mem_struct.h rename to components/soc/esp32c6/register/soc/spi_mem_struct.h index 9e2f7c1d3ba..74588ee0277 100644 --- a/components/soc/esp32c6/include/soc/spi_mem_struct.h +++ b/components/soc/esp32c6/register/soc/spi_mem_struct.h @@ -69,7 +69,7 @@ typedef volatile struct spi_mem_dev_s { } ctrl; union { struct { - uint32_t clk_mode : 2; /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on.*/ + uint32_t clk_mode : 2; /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is always on.*/ uint32_t cs_hold_dly_res : 10; /*After RES/DP/HPM command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 512) SPI_CLK cycles.*/ uint32_t reserved2 : 9; /*reserved*/ uint32_t reg_ar_size0_1_support_en : 1; /*1: MSPI supports ARSIZE 0~3. When ARSIZE =0~2, MSPI read address is 4*n and reply the real AXI read data back. 0: When ARSIZE 0~1, MSPI reply SLV_ERR.*/ @@ -271,7 +271,7 @@ typedef volatile struct spi_mem_dev_s { uint32_t sclkcnt_h : 8; /*For SPI0 external RAM interface, it must be floor((spi_mem_clkcnt_N+1)/2-1).*/ uint32_t sclkcnt_n : 8; /*For SPI0 external RAM interface, it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)*/ uint32_t reserved24 : 7; /*reserved*/ - uint32_t sclk_equ_sysclk : 1; /*For SPI0 external RAM interface, 1: spi_mem_clk is eqaul to system 0: spi_mem_clk is divided from system clock.*/ + uint32_t sclk_equ_sysclk : 1; /*For SPI0 external RAM interface, 1: spi_mem_clk is equal to system 0: spi_mem_clk is divided from system clock.*/ }; uint32_t val; } sram_clk; @@ -388,7 +388,7 @@ typedef volatile struct spi_mem_dev_s { uint32_t axi_raddr_err : 1; /*The raw bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read address is invalid by compared to MMU configuration. 0: Others.*/ uint32_t axi_wr_flash_err : 1; /*The raw bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI write flash request is received. 0: Others.*/ uint32_t axi_waddr_err : 1; /*The raw bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write address is invalid by compared to MMU configuration. 0: Others.*/ - uint32_t brown_out : 1; /*The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that chip is loosing power and RTC module sends out brown out close flash request to SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered and MSPI returns to idle state. 0: Others.*/ + uint32_t brown_out : 1; /*The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that chip is losing power and RTC module sends out brown out close flash request to SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered and MSPI returns to idle state. 0: Others.*/ uint32_t reserved11 : 21; /*reserved*/ }; uint32_t val; @@ -1025,7 +1025,7 @@ typedef volatile struct spi_mem_dev_s { } mmu_power_ctrl; union { struct { - uint32_t reg_crypt_security_level : 3; /*Set the security level of spi mem cryption. 0: Shut off cryption DPA funtion. 1-7: The bigger the number is, the more secure the cryption is. (Note that the performance of cryption will decrease together with this number increasing)*/ + uint32_t reg_crypt_security_level : 3; /*Set the security level of spi mem cryption. 0: Shut off cryption DPA function. 1-7: The bigger the number is, the more secure the cryption is. (Note that the performance of cryption will decrease together with this number increasing)*/ uint32_t reg_crypt_calc_d_dpa_en : 1; /*Only available when SPI_CRYPT_SECURITY_LEVEL is not 0. 1: Enable DPA in the calculation that using key 1 or key 2. 0: Enable DPA only in the calculation that using key 1.*/ uint32_t reg_crypt_dpa_selectister : 1; /*1: MSPI XTS DPA clock gate is controlled by SPI_CRYPT_CALC_D_DPA_EN and SPI_CRYPT_SECURITY_LEVEL. 0: Controlled by efuse bits.*/ uint32_t reserved5 : 27; /*reserved*/ diff --git a/components/soc/esp32c6/include/soc/spi_reg.h b/components/soc/esp32c6/register/soc/spi_reg.h similarity index 99% rename from components/soc/esp32c6/include/soc/spi_reg.h rename to components/soc/esp32c6/register/soc/spi_reg.h index 544b54abd1f..8da5868eaac 100644 --- a/components/soc/esp32c6/include/soc/spi_reg.h +++ b/components/soc/esp32c6/register/soc/spi_reg.h @@ -221,7 +221,7 @@ extern "C" { #define SPI_CLKDIV_PRE_V 0x0000000FU #define SPI_CLKDIV_PRE_S 18 /** SPI_CLK_EQU_SYSCLK : R/W; bitpos: [31]; default: 1; - * In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system + * In the master mode 1: spi_clk is equal to system 0: spi_clk is divided from system * clock. Can be configured in CONF state. */ #define SPI_CLK_EQU_SYSCLK (BIT(31)) @@ -1944,7 +1944,7 @@ extern "C" { /** SPI_CLK_MODE : R/W; bitpos: [1:0]; default: 0; * SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed * one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: - * SPI clock is alwasy on. Can be configured in CONF state. + * SPI clock is always on. Can be configured in CONF state. */ #define SPI_CLK_MODE 0x00000003U #define SPI_CLK_MODE_M (SPI_CLK_MODE_V << SPI_CLK_MODE_S) diff --git a/components/soc/esp32c6/include/soc/spi_struct.h b/components/soc/esp32c6/register/soc/spi_struct.h similarity index 99% rename from components/soc/esp32c6/include/soc/spi_struct.h rename to components/soc/esp32c6/register/soc/spi_struct.h index 14b6be86c14..52076bb16c8 100644 --- a/components/soc/esp32c6/include/soc/spi_struct.h +++ b/components/soc/esp32c6/register/soc/spi_struct.h @@ -511,7 +511,7 @@ typedef union { /** clk_mode : R/W; bitpos: [1:0]; default: 0; * SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed * one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: - * SPI clock is alwasy on. Can be configured in CONF state. + * SPI clock is always on. Can be configured in CONF state. */ uint32_t clk_mode:2; /** clk_mode_13 : R/W; bitpos: [2]; default: 0; @@ -624,7 +624,7 @@ typedef union { uint32_t clkdiv_pre:4; uint32_t reserved_22:9; /** clk_equ_sysclk : R/W; bitpos: [31]; default: 1; - * In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system + * In the master mode 1: spi_clk is equal to system 0: spi_clk is divided from system * clock. Can be configured in CONF state. */ uint32_t clk_equ_sysclk:1; diff --git a/components/soc/esp32c6/include/soc/systimer_reg.h b/components/soc/esp32c6/register/soc/systimer_reg.h similarity index 100% rename from components/soc/esp32c6/include/soc/systimer_reg.h rename to components/soc/esp32c6/register/soc/systimer_reg.h diff --git a/components/soc/esp32c6/include/soc/systimer_struct.h b/components/soc/esp32c6/register/soc/systimer_struct.h similarity index 100% rename from components/soc/esp32c6/include/soc/systimer_struct.h rename to components/soc/esp32c6/register/soc/systimer_struct.h diff --git a/components/soc/esp32c6/include/soc/tee_reg.h b/components/soc/esp32c6/register/soc/tee_reg.h similarity index 100% rename from components/soc/esp32c6/include/soc/tee_reg.h rename to components/soc/esp32c6/register/soc/tee_reg.h diff --git a/components/soc/esp32c6/include/soc/tee_struct.h b/components/soc/esp32c6/register/soc/tee_struct.h similarity index 100% rename from components/soc/esp32c6/include/soc/tee_struct.h rename to components/soc/esp32c6/register/soc/tee_struct.h diff --git a/components/soc/esp32c6/include/soc/timer_group_reg.h b/components/soc/esp32c6/register/soc/timer_group_reg.h similarity index 100% rename from components/soc/esp32c6/include/soc/timer_group_reg.h rename to components/soc/esp32c6/register/soc/timer_group_reg.h diff --git a/components/soc/esp32c6/include/soc/timer_group_struct.h b/components/soc/esp32c6/register/soc/timer_group_struct.h similarity index 100% rename from components/soc/esp32c6/include/soc/timer_group_struct.h rename to components/soc/esp32c6/register/soc/timer_group_struct.h diff --git a/components/soc/esp32c6/include/soc/trace_reg.h b/components/soc/esp32c6/register/soc/trace_reg.h similarity index 99% rename from components/soc/esp32c6/include/soc/trace_reg.h rename to components/soc/esp32c6/register/soc/trace_reg.h index a5c3eda9dc7..b363fbd1f8e 100644 --- a/components/soc/esp32c6/include/soc/trace_reg.h +++ b/components/soc/esp32c6/register/soc/trace_reg.h @@ -154,7 +154,7 @@ extern "C" { #define TRACE_TRIGGER_OFF_V 0x00000001U #define TRACE_TRIGGER_OFF_S 1 /** TRACE_MEM_LOOP : R/W; bitpos: [2]; default: 1; - * if this reg is 1, trace will loop wrtie trace_mem. If is 0, when mem_current_addr + * if this reg is 1, trace will loop write trace_mem. If is 0, when mem_current_addr * at mem_end_addr, it will stop at the mem_end_addr */ #define TRACE_MEM_LOOP (BIT(2)) diff --git a/components/soc/esp32c6/include/soc/trace_struct.h b/components/soc/esp32c6/register/soc/trace_struct.h similarity index 99% rename from components/soc/esp32c6/include/soc/trace_struct.h rename to components/soc/esp32c6/register/soc/trace_struct.h index 3b8330b6b0e..e5bb04d46d5 100644 --- a/components/soc/esp32c6/include/soc/trace_struct.h +++ b/components/soc/esp32c6/register/soc/trace_struct.h @@ -156,7 +156,7 @@ typedef union { */ uint32_t trigger_off:1; /** mem_loop : R/W; bitpos: [2]; default: 1; - * if this reg is 1, trace will loop wrtie trace_mem. If is 0, when mem_current_addr + * if this reg is 1, trace will loop write trace_mem. If is 0, when mem_current_addr * at mem_end_addr, it will stop at the mem_end_addr */ uint32_t mem_loop:1; diff --git a/components/soc/esp32c6/include/soc/twai_reg.h b/components/soc/esp32c6/register/soc/twai_reg.h similarity index 100% rename from components/soc/esp32c6/include/soc/twai_reg.h rename to components/soc/esp32c6/register/soc/twai_reg.h diff --git a/components/soc/esp32c6/include/soc/twai_struct.h b/components/soc/esp32c6/register/soc/twai_struct.h similarity index 100% rename from components/soc/esp32c6/include/soc/twai_struct.h rename to components/soc/esp32c6/register/soc/twai_struct.h diff --git a/components/soc/esp32c6/include/soc/uart_reg.h b/components/soc/esp32c6/register/soc/uart_reg.h similarity index 99% rename from components/soc/esp32c6/include/soc/uart_reg.h rename to components/soc/esp32c6/register/soc/uart_reg.h index abac8d92b19..d85004fcc1d 100644 --- a/components/soc/esp32c6/include/soc/uart_reg.h +++ b/components/soc/esp32c6/register/soc/uart_reg.h @@ -100,7 +100,7 @@ extern "C" { #define UART_RXFIFO_TOUT_INT_RAW_V 0x00000001U #define UART_RXFIFO_TOUT_INT_RAW_S 8 /** UART_SW_XON_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; - * This interrupt raw bit turns to high level when receiver recevies Xon char when + * This interrupt raw bit turns to high level when receiver receives Xon char when * uart_sw_flow_con_en is set to 1. */ #define UART_SW_XON_INT_RAW (BIT(9)) @@ -285,7 +285,7 @@ extern "C" { #define UART_TX_BRK_DONE_INT_ST_V 0x00000001U #define UART_TX_BRK_DONE_INT_ST_S 12 /** UART_TX_BRK_IDLE_DONE_INT_ST : RO; bitpos: [13]; default: 0; - * This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena + * This is the status bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena * is set to 1. */ #define UART_TX_BRK_IDLE_DONE_INT_ST (BIT(13)) @@ -760,7 +760,7 @@ extern "C" { #define UART_STOP_BIT_NUM_V 0x00000003U #define UART_STOP_BIT_NUM_S 4 /** UART_TXD_BRK : R/W; bitpos: [6]; default: 0; - * Set this bit to enbale transmitter to send NULL when the process of sending data + * Set this bit to enable transmitter to send NULL when the process of sending data * is done. */ #define UART_TXD_BRK (BIT(6)) @@ -1326,7 +1326,7 @@ extern "C" { */ #define UART_TOUT_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x64) /** UART_RX_TOUT_EN : R/W; bitpos: [0]; default: 0; - * This is the enble bit for uart receiver's timeout function. + * This is the enable bit for uart receiver's timeout function. */ #define UART_RX_TOUT_EN (BIT(0)) #define UART_RX_TOUT_EN_M (UART_RX_TOUT_EN_V << UART_RX_TOUT_EN_S) @@ -1450,7 +1450,7 @@ extern "C" { */ #define UART_HIGHPULSE_REG(i) (REG_UART_BASE(i) + 0x80) /** UART_HIGHPULSE_MIN_CNT : RO; bitpos: [11:0]; default: 4095; - * This register stores the value of the maxinum duration time for the high level + * This register stores the value of the maximum duration time for the high level * pulse. It is used in baud rate-detect process. */ #define UART_HIGHPULSE_MIN_CNT 0x00000FFFU diff --git a/components/soc/esp32c6/include/soc/uart_struct.h b/components/soc/esp32c6/register/soc/uart_struct.h similarity index 99% rename from components/soc/esp32c6/include/soc/uart_struct.h rename to components/soc/esp32c6/register/soc/uart_struct.h index 674af37135c..05d3b740d1f 100644 --- a/components/soc/esp32c6/include/soc/uart_struct.h +++ b/components/soc/esp32c6/register/soc/uart_struct.h @@ -49,7 +49,7 @@ typedef union { typedef union { struct { /** rx_tout_en : R/W; bitpos: [0]; default: 0; - * This is the enble bit for uart receiver's timeout function. + * This is the enable bit for uart receiver's timeout function. */ uint32_t rx_tout_en:1; /** rx_tout_flow_dis : R/W; bitpos: [1]; default: 0; @@ -120,7 +120,7 @@ typedef union { */ uint32_t rxfifo_tout:1; /** sw_xon : R/WTC/SS; bitpos: [9]; default: 0; - * This interrupt raw bit turns to high level when receiver recevies Xon char when + * This interrupt raw bit turns to high level when receiver receives Xon char when * uart_sw_flow_con_en is set to 1. */ uint32_t sw_xon:1; @@ -238,7 +238,7 @@ typedef union { */ uint32_t tx_brk_done:1; /** tx_brk_idle_done : RO; bitpos: [13]; default: 0; - * This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena + * This is the status bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena * is set to 1. */ uint32_t tx_brk_idle_done:1; @@ -515,7 +515,7 @@ typedef union { */ uint32_t stop_bit_num:2; /** txd_brk : R/W; bitpos: [6]; default: 0; - * Set this bit to enbale transmitter to send NULL when the process of sending data + * Set this bit to enable transmitter to send NULL when the process of sending data * is done. */ uint32_t txd_brk:1; @@ -1170,7 +1170,7 @@ typedef union { typedef union { struct { /** highpulse_min_cnt : RO; bitpos: [11:0]; default: 4095; - * This register stores the value of the maxinum duration time for the high level + * This register stores the value of the maximum duration time for the high level * pulse. It is used in baud rate-detect process. */ uint32_t highpulse_min_cnt:12; diff --git a/components/soc/esp32c6/include/soc/uhci_reg.h b/components/soc/esp32c6/register/soc/uhci_reg.h similarity index 100% rename from components/soc/esp32c6/include/soc/uhci_reg.h rename to components/soc/esp32c6/register/soc/uhci_reg.h diff --git a/components/soc/esp32c6/include/soc/uhci_struct.h b/components/soc/esp32c6/register/soc/uhci_struct.h similarity index 100% rename from components/soc/esp32c6/include/soc/uhci_struct.h rename to components/soc/esp32c6/register/soc/uhci_struct.h diff --git a/components/soc/esp32c6/include/soc/usb_serial_jtag_reg.h b/components/soc/esp32c6/register/soc/usb_serial_jtag_reg.h similarity index 99% rename from components/soc/esp32c6/include/soc/usb_serial_jtag_reg.h rename to components/soc/esp32c6/register/soc/usb_serial_jtag_reg.h index eb4b8a1e039..e188eea9111 100644 --- a/components/soc/esp32c6/include/soc/usb_serial_jtag_reg.h +++ b/components/soc/esp32c6/register/soc/usb_serial_jtag_reg.h @@ -1144,7 +1144,7 @@ extern "C" { #define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_V 0x00000001U #define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_S 3 /** USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY : RO; bitpos: [4]; default: 1; - * CDC_ACM OUTOUT async FIFO empty signal in read clock domain. + * CDC_ACM OUTPUT async FIFO empty signal in read clock domain. */ #define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY (BIT(4)) #define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_M (USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_V << USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_S) diff --git a/components/soc/esp32c6/include/soc/usb_serial_jtag_struct.h b/components/soc/esp32c6/register/soc/usb_serial_jtag_struct.h similarity index 100% rename from components/soc/esp32c6/include/soc/usb_serial_jtag_struct.h rename to components/soc/esp32c6/register/soc/usb_serial_jtag_struct.h diff --git a/components/soc/esp32c6/include/soc/xts_aes_reg.h b/components/soc/esp32c6/register/soc/xts_aes_reg.h similarity index 98% rename from components/soc/esp32c6/include/soc/xts_aes_reg.h rename to components/soc/esp32c6/register/soc/xts_aes_reg.h index 5d7d7e0b818..6e7cba263a7 100644 --- a/components/soc/esp32c6/include/soc/xts_aes_reg.h +++ b/components/soc/esp32c6/register/soc/xts_aes_reg.h @@ -32,7 +32,7 @@ s. Please do not use this field..*/ #define XTS_AES_DESTINATION_REG(i) (REG_SPI_MEM_BASE(i) + 0x344) /* XTS_AES_DESTINATION : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: This bit stores the destination parameter which will be used in manual encryptio +/*description: This bit stores the destination parameter which will be used in manual encryption n calculation. 0: flash(default), 1: psram(reserved). Only default value can be used..*/ #define XTS_AES_DESTINATION (BIT(0)) @@ -54,7 +54,7 @@ size parameter..*/ /* XTS_AES_TRIGGER : WT ;bitpos:[0] ;default: 1'b0 ; */ /*description: Set this bit to trigger the process of manual encryption calculation. This actio n should only be asserted when manual encryption status is 0. After this action, - manual encryption status becomes 1. After calculation is done, manual encryptio + manual encryption status becomes 1. After calculation is done, manual encryption n status becomes 2..*/ #define XTS_AES_TRIGGER (BIT(0)) #define XTS_AES_TRIGGER_M (BIT(0)) @@ -115,7 +115,7 @@ ing key 1..*/ #define XTS_AES_CRYPT_CALC_D_DPA_EN_V 0x1 #define XTS_AES_CRYPT_CALC_D_DPA_EN_S 3 /* XTS_AES_CRYPT_SECURITY_LEVEL : R/W ;bitpos:[2:0] ;default: 3'd7 ; */ -/*description: Set the security level of spi mem cryption. 0: Shut off cryption DPA funtion. 1- +/*description: Set the security level of spi mem cryption. 0: Shut off cryption DPA function. 1- 7: The bigger the number is, the more secure the cryption is. (Note that the per formance of cryption will decrease together with this number increasing).*/ #define XTS_AES_CRYPT_SECURITY_LEVEL 0x00000007 From 82f4add36def32ec9d504ff6104e05dd3dd051c9 Mon Sep 17 00:00:00 2001 From: laokaiyao Date: Fri, 6 Sep 2024 18:29:15 +0800 Subject: [PATCH 119/472] refactor(soc): sort esp32c5 soc headers --- components/soc/esp32c5/include/soc/soc.h | 2 +- components/soc/esp32c5/include/soc/system_reg.h | 2 +- components/soc/esp32c5/register/soc/.gitkeep | 0 components/soc/esp32c5/{include => register}/soc/aes_reg.h | 0 components/soc/esp32c5/{include => register}/soc/aes_struct.h | 0 components/soc/esp32c5/{include => register}/soc/ahb_dma_reg.h | 0 .../soc/esp32c5/{include => register}/soc/ahb_dma_struct.h | 0 .../soc/esp32c5/{include => register}/soc/apb_saradc_reg.h | 0 .../soc/esp32c5/{include => register}/soc/apb_saradc_struct.h | 0 .../soc/esp32c5/{include => register}/soc/assist_debug_reg.h | 0 .../soc/esp32c5/{include => register}/soc/assist_debug_struct.h | 0 .../soc/esp32c5/{include => register}/soc/bitscrambler_reg.h | 0 .../soc/esp32c5/{include => register}/soc/bitscrambler_struct.h | 0 components/soc/esp32c5/{include => register}/soc/cache_reg.h | 0 components/soc/esp32c5/{include => register}/soc/cache_struct.h | 0 components/soc/esp32c5/{include => register}/soc/ds_reg.h | 0 components/soc/esp32c5/{include => register}/soc/ds_struct.h | 0 components/soc/esp32c5/{include => register}/soc/ecc_mult_reg.h | 0 .../soc/esp32c5/{include => register}/soc/ecc_mult_struct.h | 0 components/soc/esp32c5/{include => register}/soc/ecdsa_reg.h | 0 components/soc/esp32c5/{include => register}/soc/ecdsa_struct.h | 0 components/soc/esp32c5/{include => register}/soc/efuse_reg.h | 0 components/soc/esp32c5/{include => register}/soc/efuse_struct.h | 0 components/soc/esp32c5/{include => register}/soc/gpio_reg.h | 0 components/soc/esp32c5/{include => register}/soc/gpio_struct.h | 0 components/soc/esp32c5/{include => register}/soc/hmac_reg.h | 0 components/soc/esp32c5/{include => register}/soc/hmac_struct.h | 0 components/soc/esp32c5/{include => register}/soc/hp_apm_reg.h | 0 .../soc/esp32c5/{include => register}/soc/hp_apm_struct.h | 0 .../soc/esp32c5/{include => register}/soc/hp_system_reg.h | 0 .../soc/esp32c5/{include => register}/soc/hp_system_struct.h | 0 components/soc/esp32c5/{include => register}/soc/huk_reg.h | 0 components/soc/esp32c5/{include => register}/soc/huk_struct.h | 0 .../soc/esp32c5/{include => register}/soc/i2c_ana_mst_reg.h | 0 components/soc/esp32c5/{include => register}/soc/i2c_reg.h | 0 components/soc/esp32c5/{include => register}/soc/i2c_struct.h | 0 components/soc/esp32c5/{include => register}/soc/i2s_reg.h | 0 components/soc/esp32c5/{include => register}/soc/i2s_struct.h | 0 .../soc/esp32c5/{include => register}/soc/ieee802154_reg.h | 0 .../soc/esp32c5/{include => register}/soc/ieee802154_struct.h | 0 .../esp32c5/{include => register}/soc/interrupt_matrix_reg.h | 0 .../esp32c5/{include => register}/soc/interrupt_matrix_struct.h | 0 components/soc/esp32c5/{include => register}/soc/intpri_reg.h | 0 .../soc/esp32c5/{include => register}/soc/intpri_struct.h | 0 components/soc/esp32c5/{include => register}/soc/io_mux_reg.h | 0 .../soc/esp32c5/{include => register}/soc/io_mux_struct.h | 0 components/soc/esp32c5/{include => register}/soc/keymng_reg.h | 0 .../soc/esp32c5/{include => register}/soc/keymng_struct.h | 0 components/soc/esp32c5/{include => register}/soc/ledc_reg.h | 0 components/soc/esp32c5/{include => register}/soc/ledc_struct.h | 0 .../soc/esp32c5/{include => register}/soc/lp_analog_peri_reg.h | 0 .../esp32c5/{include => register}/soc/lp_analog_peri_struct.h | 0 components/soc/esp32c5/{include => register}/soc/lp_aon_reg.h | 0 .../soc/esp32c5/{include => register}/soc/lp_aon_struct.h | 0 components/soc/esp32c5/{include => register}/soc/lp_apm0_reg.h | 0 .../soc/esp32c5/{include => register}/soc/lp_apm0_struct.h | 0 components/soc/esp32c5/{include => register}/soc/lp_apm_reg.h | 0 .../soc/esp32c5/{include => register}/soc/lp_apm_struct.h | 0 .../soc/esp32c5/{include => register}/soc/lp_clkrst_reg.h | 0 .../soc/esp32c5/{include => register}/soc/lp_clkrst_struct.h | 0 components/soc/esp32c5/{include => register}/soc/lp_gpio_reg.h | 0 .../soc/esp32c5/{include => register}/soc/lp_gpio_struct.h | 0 .../soc/esp32c5/{include => register}/soc/lp_i2c_ana_mst_reg.h | 0 .../esp32c5/{include => register}/soc/lp_i2c_ana_mst_struct.h | 0 components/soc/esp32c5/{include => register}/soc/lp_i2c_reg.h | 0 .../soc/esp32c5/{include => register}/soc/lp_i2c_struct.h | 0 components/soc/esp32c5/{include => register}/soc/lp_iomux_reg.h | 0 .../soc/esp32c5/{include => register}/soc/lp_iomux_struct.h | 0 components/soc/esp32c5/{include => register}/soc/lp_tee_reg.h | 0 .../soc/esp32c5/{include => register}/soc/lp_tee_struct.h | 0 components/soc/esp32c5/{include => register}/soc/lp_timer_reg.h | 0 .../soc/esp32c5/{include => register}/soc/lp_timer_struct.h | 0 components/soc/esp32c5/{include => register}/soc/lp_uart_reg.h | 0 .../soc/esp32c5/{include => register}/soc/lp_uart_struct.h | 0 components/soc/esp32c5/{include => register}/soc/lp_wdt_reg.h | 0 .../soc/esp32c5/{include => register}/soc/lp_wdt_struct.h | 0 components/soc/esp32c5/{include => register}/soc/lpperi_reg.h | 0 .../soc/esp32c5/{include => register}/soc/lpperi_struct.h | 0 components/soc/esp32c5/{include => register}/soc/mcpwm_reg.h | 0 components/soc/esp32c5/{include => register}/soc/mcpwm_struct.h | 0 .../soc/esp32c5/{include => register}/soc/mem_monitor_reg.h | 0 .../soc/esp32c5/{include => register}/soc/mem_monitor_struct.h | 0 components/soc/esp32c5/{include => register}/soc/parl_io_reg.h | 0 .../soc/esp32c5/{include => register}/soc/parl_io_struct.h | 0 components/soc/esp32c5/{include => register}/soc/pau_reg.h | 0 components/soc/esp32c5/{include => register}/soc/pau_struct.h | 0 components/soc/esp32c5/{include => register}/soc/pcnt_reg.h | 0 components/soc/esp32c5/{include => register}/soc/pcnt_struct.h | 0 components/soc/esp32c5/{include => register}/soc/pcr_reg.h | 0 components/soc/esp32c5/{include => register}/soc/pcr_struct.h | 0 components/soc/esp32c5/{include => register}/soc/pmu_reg.h | 0 components/soc/esp32c5/{include => register}/soc/pmu_struct.h | 2 +- components/soc/esp32c5/{include => register}/soc/pvt_reg.h | 0 components/soc/esp32c5/{include => register}/soc/pvt_struct.h | 0 components/soc/esp32c5/{include => register}/soc/reg_base.h | 0 components/soc/esp32c5/{include => register}/soc/rmt_reg.h | 0 components/soc/esp32c5/{include => register}/soc/rmt_struct.h | 0 components/soc/esp32c5/{include => register}/soc/rsa_reg.h | 0 components/soc/esp32c5/{include => register}/soc/rsa_struct.h | 0 components/soc/esp32c5/{include => register}/soc/sha_reg.h | 0 components/soc/esp32c5/{include => register}/soc/sha_struct.h | 0 components/soc/esp32c5/{include => register}/soc/soc_etm_reg.h | 0 .../soc/esp32c5/{include => register}/soc/soc_etm_struct.h | 0 components/soc/esp32c5/{include => register}/soc/spi1_mem_reg.h | 0 .../soc/esp32c5/{include => register}/soc/spi1_mem_struct.h | 0 .../soc/esp32c5/{include => register}/soc/spi_mem_c_reg.h | 0 .../soc/esp32c5/{include => register}/soc/spi_mem_c_struct.h | 0 components/soc/esp32c5/{include => register}/soc/spi_reg.h | 0 components/soc/esp32c5/{include => register}/soc/spi_struct.h | 0 components/soc/esp32c5/{include => register}/soc/systimer_reg.h | 0 .../soc/esp32c5/{include => register}/soc/systimer_struct.h | 0 components/soc/esp32c5/{include => register}/soc/tee_reg.h | 0 components/soc/esp32c5/{include => register}/soc/tee_struct.h | 0 .../soc/esp32c5/{include => register}/soc/timer_group_reg.h | 0 .../soc/esp32c5/{include => register}/soc/timer_group_struct.h | 0 components/soc/esp32c5/{include => register}/soc/trace_reg.h | 0 components/soc/esp32c5/{include => register}/soc/trace_struct.h | 0 components/soc/esp32c5/{include => register}/soc/twaifd_reg.h | 0 .../soc/esp32c5/{include => register}/soc/twaifd_struct.h | 0 components/soc/esp32c5/{include => register}/soc/uart_reg.h | 0 components/soc/esp32c5/{include => register}/soc/uart_struct.h | 0 components/soc/esp32c5/{include => register}/soc/uhci_reg.h | 0 components/soc/esp32c5/{include => register}/soc/uhci_struct.h | 0 .../soc/esp32c5/{include => register}/soc/usb_serial_jtag_reg.h | 0 .../esp32c5/{include => register}/soc/usb_serial_jtag_struct.h | 0 125 files changed, 3 insertions(+), 3 deletions(-) delete mode 100644 components/soc/esp32c5/register/soc/.gitkeep rename components/soc/esp32c5/{include => register}/soc/aes_reg.h (100%) rename components/soc/esp32c5/{include => register}/soc/aes_struct.h (100%) rename components/soc/esp32c5/{include => register}/soc/ahb_dma_reg.h (100%) rename components/soc/esp32c5/{include => register}/soc/ahb_dma_struct.h (100%) rename components/soc/esp32c5/{include => register}/soc/apb_saradc_reg.h (100%) rename components/soc/esp32c5/{include => register}/soc/apb_saradc_struct.h (100%) rename components/soc/esp32c5/{include => register}/soc/assist_debug_reg.h (100%) rename components/soc/esp32c5/{include => register}/soc/assist_debug_struct.h (100%) rename components/soc/esp32c5/{include => register}/soc/bitscrambler_reg.h (100%) rename components/soc/esp32c5/{include => register}/soc/bitscrambler_struct.h (100%) rename components/soc/esp32c5/{include => register}/soc/cache_reg.h (100%) rename components/soc/esp32c5/{include => register}/soc/cache_struct.h (100%) rename components/soc/esp32c5/{include => register}/soc/ds_reg.h (100%) rename components/soc/esp32c5/{include => register}/soc/ds_struct.h (100%) rename components/soc/esp32c5/{include => register}/soc/ecc_mult_reg.h (100%) rename components/soc/esp32c5/{include => register}/soc/ecc_mult_struct.h (100%) rename components/soc/esp32c5/{include => register}/soc/ecdsa_reg.h (100%) rename components/soc/esp32c5/{include => register}/soc/ecdsa_struct.h (100%) rename components/soc/esp32c5/{include => register}/soc/efuse_reg.h (100%) rename components/soc/esp32c5/{include => register}/soc/efuse_struct.h (100%) rename components/soc/esp32c5/{include => register}/soc/gpio_reg.h (100%) rename components/soc/esp32c5/{include => register}/soc/gpio_struct.h (100%) rename components/soc/esp32c5/{include => register}/soc/hmac_reg.h (100%) rename components/soc/esp32c5/{include => register}/soc/hmac_struct.h (100%) rename components/soc/esp32c5/{include => register}/soc/hp_apm_reg.h (100%) rename components/soc/esp32c5/{include => register}/soc/hp_apm_struct.h (100%) rename components/soc/esp32c5/{include => register}/soc/hp_system_reg.h (100%) rename components/soc/esp32c5/{include => register}/soc/hp_system_struct.h (100%) rename components/soc/esp32c5/{include => register}/soc/huk_reg.h (100%) rename components/soc/esp32c5/{include => register}/soc/huk_struct.h (100%) rename components/soc/esp32c5/{include => register}/soc/i2c_ana_mst_reg.h (100%) rename components/soc/esp32c5/{include => register}/soc/i2c_reg.h (100%) rename components/soc/esp32c5/{include => register}/soc/i2c_struct.h (100%) rename components/soc/esp32c5/{include => register}/soc/i2s_reg.h (100%) rename components/soc/esp32c5/{include => register}/soc/i2s_struct.h (100%) rename components/soc/esp32c5/{include => register}/soc/ieee802154_reg.h (100%) rename components/soc/esp32c5/{include => register}/soc/ieee802154_struct.h (100%) rename components/soc/esp32c5/{include => register}/soc/interrupt_matrix_reg.h (100%) rename components/soc/esp32c5/{include => register}/soc/interrupt_matrix_struct.h (100%) rename components/soc/esp32c5/{include => register}/soc/intpri_reg.h (100%) rename components/soc/esp32c5/{include => register}/soc/intpri_struct.h (100%) rename components/soc/esp32c5/{include => register}/soc/io_mux_reg.h (100%) rename components/soc/esp32c5/{include => register}/soc/io_mux_struct.h (100%) rename components/soc/esp32c5/{include => register}/soc/keymng_reg.h (100%) rename components/soc/esp32c5/{include => register}/soc/keymng_struct.h (100%) rename components/soc/esp32c5/{include => register}/soc/ledc_reg.h (100%) rename components/soc/esp32c5/{include => register}/soc/ledc_struct.h (100%) rename components/soc/esp32c5/{include => register}/soc/lp_analog_peri_reg.h (100%) rename components/soc/esp32c5/{include => register}/soc/lp_analog_peri_struct.h (100%) rename components/soc/esp32c5/{include => register}/soc/lp_aon_reg.h (100%) rename components/soc/esp32c5/{include => register}/soc/lp_aon_struct.h (100%) rename components/soc/esp32c5/{include => register}/soc/lp_apm0_reg.h (100%) rename components/soc/esp32c5/{include => register}/soc/lp_apm0_struct.h (100%) rename components/soc/esp32c5/{include => register}/soc/lp_apm_reg.h (100%) rename components/soc/esp32c5/{include => register}/soc/lp_apm_struct.h (100%) rename components/soc/esp32c5/{include => register}/soc/lp_clkrst_reg.h (100%) rename components/soc/esp32c5/{include => register}/soc/lp_clkrst_struct.h (100%) rename components/soc/esp32c5/{include => register}/soc/lp_gpio_reg.h (100%) rename components/soc/esp32c5/{include => register}/soc/lp_gpio_struct.h (100%) rename components/soc/esp32c5/{include => register}/soc/lp_i2c_ana_mst_reg.h (100%) rename components/soc/esp32c5/{include => register}/soc/lp_i2c_ana_mst_struct.h (100%) rename components/soc/esp32c5/{include => register}/soc/lp_i2c_reg.h (100%) rename components/soc/esp32c5/{include => register}/soc/lp_i2c_struct.h (100%) rename components/soc/esp32c5/{include => register}/soc/lp_iomux_reg.h (100%) rename components/soc/esp32c5/{include => register}/soc/lp_iomux_struct.h (100%) rename components/soc/esp32c5/{include => register}/soc/lp_tee_reg.h (100%) rename components/soc/esp32c5/{include => register}/soc/lp_tee_struct.h (100%) rename components/soc/esp32c5/{include => register}/soc/lp_timer_reg.h (100%) rename components/soc/esp32c5/{include => register}/soc/lp_timer_struct.h (100%) rename components/soc/esp32c5/{include => register}/soc/lp_uart_reg.h (100%) rename components/soc/esp32c5/{include => register}/soc/lp_uart_struct.h (100%) rename components/soc/esp32c5/{include => register}/soc/lp_wdt_reg.h (100%) rename components/soc/esp32c5/{include => register}/soc/lp_wdt_struct.h (100%) rename components/soc/esp32c5/{include => register}/soc/lpperi_reg.h (100%) rename components/soc/esp32c5/{include => register}/soc/lpperi_struct.h (100%) rename components/soc/esp32c5/{include => register}/soc/mcpwm_reg.h (100%) rename components/soc/esp32c5/{include => register}/soc/mcpwm_struct.h (100%) rename components/soc/esp32c5/{include => register}/soc/mem_monitor_reg.h (100%) rename components/soc/esp32c5/{include => register}/soc/mem_monitor_struct.h (100%) rename components/soc/esp32c5/{include => register}/soc/parl_io_reg.h (100%) rename components/soc/esp32c5/{include => register}/soc/parl_io_struct.h (100%) rename components/soc/esp32c5/{include => register}/soc/pau_reg.h (100%) rename components/soc/esp32c5/{include => register}/soc/pau_struct.h (100%) rename components/soc/esp32c5/{include => register}/soc/pcnt_reg.h (100%) rename components/soc/esp32c5/{include => register}/soc/pcnt_struct.h (100%) rename components/soc/esp32c5/{include => register}/soc/pcr_reg.h (100%) rename components/soc/esp32c5/{include => register}/soc/pcr_struct.h (100%) rename components/soc/esp32c5/{include => register}/soc/pmu_reg.h (100%) rename components/soc/esp32c5/{include => register}/soc/pmu_struct.h (99%) rename components/soc/esp32c5/{include => register}/soc/pvt_reg.h (100%) rename components/soc/esp32c5/{include => register}/soc/pvt_struct.h (100%) rename components/soc/esp32c5/{include => register}/soc/reg_base.h (100%) rename components/soc/esp32c5/{include => register}/soc/rmt_reg.h (100%) rename components/soc/esp32c5/{include => register}/soc/rmt_struct.h (100%) rename components/soc/esp32c5/{include => register}/soc/rsa_reg.h (100%) rename components/soc/esp32c5/{include => register}/soc/rsa_struct.h (100%) rename components/soc/esp32c5/{include => register}/soc/sha_reg.h (100%) rename components/soc/esp32c5/{include => register}/soc/sha_struct.h (100%) rename components/soc/esp32c5/{include => register}/soc/soc_etm_reg.h (100%) rename components/soc/esp32c5/{include => register}/soc/soc_etm_struct.h (100%) rename components/soc/esp32c5/{include => register}/soc/spi1_mem_reg.h (100%) rename components/soc/esp32c5/{include => register}/soc/spi1_mem_struct.h (100%) rename components/soc/esp32c5/{include => register}/soc/spi_mem_c_reg.h (100%) rename components/soc/esp32c5/{include => register}/soc/spi_mem_c_struct.h (100%) rename components/soc/esp32c5/{include => register}/soc/spi_reg.h (100%) rename components/soc/esp32c5/{include => register}/soc/spi_struct.h (100%) rename components/soc/esp32c5/{include => register}/soc/systimer_reg.h (100%) rename components/soc/esp32c5/{include => register}/soc/systimer_struct.h (100%) rename components/soc/esp32c5/{include => register}/soc/tee_reg.h (100%) rename components/soc/esp32c5/{include => register}/soc/tee_struct.h (100%) rename components/soc/esp32c5/{include => register}/soc/timer_group_reg.h (100%) rename components/soc/esp32c5/{include => register}/soc/timer_group_struct.h (100%) rename components/soc/esp32c5/{include => register}/soc/trace_reg.h (100%) rename components/soc/esp32c5/{include => register}/soc/trace_struct.h (100%) rename components/soc/esp32c5/{include => register}/soc/twaifd_reg.h (100%) rename components/soc/esp32c5/{include => register}/soc/twaifd_struct.h (100%) rename components/soc/esp32c5/{include => register}/soc/uart_reg.h (100%) rename components/soc/esp32c5/{include => register}/soc/uart_struct.h (100%) rename components/soc/esp32c5/{include => register}/soc/uhci_reg.h (100%) rename components/soc/esp32c5/{include => register}/soc/uhci_struct.h (100%) rename components/soc/esp32c5/{include => register}/soc/usb_serial_jtag_reg.h (100%) rename components/soc/esp32c5/{include => register}/soc/usb_serial_jtag_struct.h (100%) diff --git a/components/soc/esp32c5/include/soc/soc.h b/components/soc/esp32c5/include/soc/soc.h index 7134121e4b5..d03396f3c68 100644 --- a/components/soc/esp32c5/include/soc/soc.h +++ b/components/soc/esp32c5/include/soc/soc.h @@ -12,7 +12,7 @@ #endif #include "esp_bit_defs.h" -#include "reg_base.h" +#include "soc/reg_base.h" #define PRO_CPU_NUM (0) diff --git a/components/soc/esp32c5/include/soc/system_reg.h b/components/soc/esp32c5/include/soc/system_reg.h index 06daf447132..939bf695f0b 100644 --- a/components/soc/esp32c5/include/soc/system_reg.h +++ b/components/soc/esp32c5/include/soc/system_reg.h @@ -7,6 +7,6 @@ #include "soc/hp_system_reg.h" // TODO: IDF-5720 -#include "intpri_reg.h" +#include "soc/intpri_reg.h" #define SYSTEM_CPU_INTR_FROM_CPU_0_REG INTPRI_CPU_INTR_FROM_CPU_0_REG #define SYSTEM_CPU_INTR_FROM_CPU_0 INTPRI_CPU_INTR_FROM_CPU_0 diff --git a/components/soc/esp32c5/register/soc/.gitkeep b/components/soc/esp32c5/register/soc/.gitkeep deleted file mode 100644 index e69de29bb2d..00000000000 diff --git a/components/soc/esp32c5/include/soc/aes_reg.h b/components/soc/esp32c5/register/soc/aes_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/aes_reg.h rename to components/soc/esp32c5/register/soc/aes_reg.h diff --git a/components/soc/esp32c5/include/soc/aes_struct.h b/components/soc/esp32c5/register/soc/aes_struct.h similarity index 100% rename from components/soc/esp32c5/include/soc/aes_struct.h rename to components/soc/esp32c5/register/soc/aes_struct.h diff --git a/components/soc/esp32c5/include/soc/ahb_dma_reg.h b/components/soc/esp32c5/register/soc/ahb_dma_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/ahb_dma_reg.h rename to components/soc/esp32c5/register/soc/ahb_dma_reg.h diff --git a/components/soc/esp32c5/include/soc/ahb_dma_struct.h b/components/soc/esp32c5/register/soc/ahb_dma_struct.h similarity index 100% rename from components/soc/esp32c5/include/soc/ahb_dma_struct.h rename to components/soc/esp32c5/register/soc/ahb_dma_struct.h diff --git a/components/soc/esp32c5/include/soc/apb_saradc_reg.h b/components/soc/esp32c5/register/soc/apb_saradc_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/apb_saradc_reg.h rename to components/soc/esp32c5/register/soc/apb_saradc_reg.h diff --git a/components/soc/esp32c5/include/soc/apb_saradc_struct.h b/components/soc/esp32c5/register/soc/apb_saradc_struct.h similarity index 100% rename from components/soc/esp32c5/include/soc/apb_saradc_struct.h rename to components/soc/esp32c5/register/soc/apb_saradc_struct.h diff --git a/components/soc/esp32c5/include/soc/assist_debug_reg.h b/components/soc/esp32c5/register/soc/assist_debug_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/assist_debug_reg.h rename to components/soc/esp32c5/register/soc/assist_debug_reg.h diff --git a/components/soc/esp32c5/include/soc/assist_debug_struct.h b/components/soc/esp32c5/register/soc/assist_debug_struct.h similarity index 100% rename from components/soc/esp32c5/include/soc/assist_debug_struct.h rename to components/soc/esp32c5/register/soc/assist_debug_struct.h diff --git a/components/soc/esp32c5/include/soc/bitscrambler_reg.h b/components/soc/esp32c5/register/soc/bitscrambler_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/bitscrambler_reg.h rename to components/soc/esp32c5/register/soc/bitscrambler_reg.h diff --git a/components/soc/esp32c5/include/soc/bitscrambler_struct.h b/components/soc/esp32c5/register/soc/bitscrambler_struct.h similarity index 100% rename from components/soc/esp32c5/include/soc/bitscrambler_struct.h rename to components/soc/esp32c5/register/soc/bitscrambler_struct.h diff --git a/components/soc/esp32c5/include/soc/cache_reg.h b/components/soc/esp32c5/register/soc/cache_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/cache_reg.h rename to components/soc/esp32c5/register/soc/cache_reg.h diff --git a/components/soc/esp32c5/include/soc/cache_struct.h b/components/soc/esp32c5/register/soc/cache_struct.h similarity index 100% rename from components/soc/esp32c5/include/soc/cache_struct.h rename to components/soc/esp32c5/register/soc/cache_struct.h diff --git a/components/soc/esp32c5/include/soc/ds_reg.h b/components/soc/esp32c5/register/soc/ds_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/ds_reg.h rename to components/soc/esp32c5/register/soc/ds_reg.h diff --git a/components/soc/esp32c5/include/soc/ds_struct.h b/components/soc/esp32c5/register/soc/ds_struct.h similarity index 100% rename from components/soc/esp32c5/include/soc/ds_struct.h rename to components/soc/esp32c5/register/soc/ds_struct.h diff --git a/components/soc/esp32c5/include/soc/ecc_mult_reg.h b/components/soc/esp32c5/register/soc/ecc_mult_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/ecc_mult_reg.h rename to components/soc/esp32c5/register/soc/ecc_mult_reg.h diff --git a/components/soc/esp32c5/include/soc/ecc_mult_struct.h b/components/soc/esp32c5/register/soc/ecc_mult_struct.h similarity index 100% rename from components/soc/esp32c5/include/soc/ecc_mult_struct.h rename to components/soc/esp32c5/register/soc/ecc_mult_struct.h diff --git a/components/soc/esp32c5/include/soc/ecdsa_reg.h b/components/soc/esp32c5/register/soc/ecdsa_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/ecdsa_reg.h rename to components/soc/esp32c5/register/soc/ecdsa_reg.h diff --git a/components/soc/esp32c5/include/soc/ecdsa_struct.h b/components/soc/esp32c5/register/soc/ecdsa_struct.h similarity index 100% rename from components/soc/esp32c5/include/soc/ecdsa_struct.h rename to components/soc/esp32c5/register/soc/ecdsa_struct.h diff --git a/components/soc/esp32c5/include/soc/efuse_reg.h b/components/soc/esp32c5/register/soc/efuse_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/efuse_reg.h rename to components/soc/esp32c5/register/soc/efuse_reg.h diff --git a/components/soc/esp32c5/include/soc/efuse_struct.h b/components/soc/esp32c5/register/soc/efuse_struct.h similarity index 100% rename from components/soc/esp32c5/include/soc/efuse_struct.h rename to components/soc/esp32c5/register/soc/efuse_struct.h diff --git a/components/soc/esp32c5/include/soc/gpio_reg.h b/components/soc/esp32c5/register/soc/gpio_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/gpio_reg.h rename to components/soc/esp32c5/register/soc/gpio_reg.h diff --git a/components/soc/esp32c5/include/soc/gpio_struct.h b/components/soc/esp32c5/register/soc/gpio_struct.h similarity index 100% rename from components/soc/esp32c5/include/soc/gpio_struct.h rename to components/soc/esp32c5/register/soc/gpio_struct.h diff --git a/components/soc/esp32c5/include/soc/hmac_reg.h b/components/soc/esp32c5/register/soc/hmac_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/hmac_reg.h rename to components/soc/esp32c5/register/soc/hmac_reg.h diff --git a/components/soc/esp32c5/include/soc/hmac_struct.h b/components/soc/esp32c5/register/soc/hmac_struct.h similarity index 100% rename from components/soc/esp32c5/include/soc/hmac_struct.h rename to components/soc/esp32c5/register/soc/hmac_struct.h diff --git a/components/soc/esp32c5/include/soc/hp_apm_reg.h b/components/soc/esp32c5/register/soc/hp_apm_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/hp_apm_reg.h rename to components/soc/esp32c5/register/soc/hp_apm_reg.h diff --git a/components/soc/esp32c5/include/soc/hp_apm_struct.h b/components/soc/esp32c5/register/soc/hp_apm_struct.h similarity index 100% rename from components/soc/esp32c5/include/soc/hp_apm_struct.h rename to components/soc/esp32c5/register/soc/hp_apm_struct.h diff --git a/components/soc/esp32c5/include/soc/hp_system_reg.h b/components/soc/esp32c5/register/soc/hp_system_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/hp_system_reg.h rename to components/soc/esp32c5/register/soc/hp_system_reg.h diff --git a/components/soc/esp32c5/include/soc/hp_system_struct.h b/components/soc/esp32c5/register/soc/hp_system_struct.h similarity index 100% rename from components/soc/esp32c5/include/soc/hp_system_struct.h rename to components/soc/esp32c5/register/soc/hp_system_struct.h diff --git a/components/soc/esp32c5/include/soc/huk_reg.h b/components/soc/esp32c5/register/soc/huk_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/huk_reg.h rename to components/soc/esp32c5/register/soc/huk_reg.h diff --git a/components/soc/esp32c5/include/soc/huk_struct.h b/components/soc/esp32c5/register/soc/huk_struct.h similarity index 100% rename from components/soc/esp32c5/include/soc/huk_struct.h rename to components/soc/esp32c5/register/soc/huk_struct.h diff --git a/components/soc/esp32c5/include/soc/i2c_ana_mst_reg.h b/components/soc/esp32c5/register/soc/i2c_ana_mst_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/i2c_ana_mst_reg.h rename to components/soc/esp32c5/register/soc/i2c_ana_mst_reg.h diff --git a/components/soc/esp32c5/include/soc/i2c_reg.h b/components/soc/esp32c5/register/soc/i2c_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/i2c_reg.h rename to components/soc/esp32c5/register/soc/i2c_reg.h diff --git a/components/soc/esp32c5/include/soc/i2c_struct.h b/components/soc/esp32c5/register/soc/i2c_struct.h similarity index 100% rename from components/soc/esp32c5/include/soc/i2c_struct.h rename to components/soc/esp32c5/register/soc/i2c_struct.h diff --git a/components/soc/esp32c5/include/soc/i2s_reg.h b/components/soc/esp32c5/register/soc/i2s_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/i2s_reg.h rename to components/soc/esp32c5/register/soc/i2s_reg.h diff --git a/components/soc/esp32c5/include/soc/i2s_struct.h b/components/soc/esp32c5/register/soc/i2s_struct.h similarity index 100% rename from components/soc/esp32c5/include/soc/i2s_struct.h rename to components/soc/esp32c5/register/soc/i2s_struct.h diff --git a/components/soc/esp32c5/include/soc/ieee802154_reg.h b/components/soc/esp32c5/register/soc/ieee802154_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/ieee802154_reg.h rename to components/soc/esp32c5/register/soc/ieee802154_reg.h diff --git a/components/soc/esp32c5/include/soc/ieee802154_struct.h b/components/soc/esp32c5/register/soc/ieee802154_struct.h similarity index 100% rename from components/soc/esp32c5/include/soc/ieee802154_struct.h rename to components/soc/esp32c5/register/soc/ieee802154_struct.h diff --git a/components/soc/esp32c5/include/soc/interrupt_matrix_reg.h b/components/soc/esp32c5/register/soc/interrupt_matrix_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/interrupt_matrix_reg.h rename to components/soc/esp32c5/register/soc/interrupt_matrix_reg.h diff --git a/components/soc/esp32c5/include/soc/interrupt_matrix_struct.h b/components/soc/esp32c5/register/soc/interrupt_matrix_struct.h similarity index 100% rename from components/soc/esp32c5/include/soc/interrupt_matrix_struct.h rename to components/soc/esp32c5/register/soc/interrupt_matrix_struct.h diff --git a/components/soc/esp32c5/include/soc/intpri_reg.h b/components/soc/esp32c5/register/soc/intpri_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/intpri_reg.h rename to components/soc/esp32c5/register/soc/intpri_reg.h diff --git a/components/soc/esp32c5/include/soc/intpri_struct.h b/components/soc/esp32c5/register/soc/intpri_struct.h similarity index 100% rename from components/soc/esp32c5/include/soc/intpri_struct.h rename to components/soc/esp32c5/register/soc/intpri_struct.h diff --git a/components/soc/esp32c5/include/soc/io_mux_reg.h b/components/soc/esp32c5/register/soc/io_mux_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/io_mux_reg.h rename to components/soc/esp32c5/register/soc/io_mux_reg.h diff --git a/components/soc/esp32c5/include/soc/io_mux_struct.h b/components/soc/esp32c5/register/soc/io_mux_struct.h similarity index 100% rename from components/soc/esp32c5/include/soc/io_mux_struct.h rename to components/soc/esp32c5/register/soc/io_mux_struct.h diff --git a/components/soc/esp32c5/include/soc/keymng_reg.h b/components/soc/esp32c5/register/soc/keymng_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/keymng_reg.h rename to components/soc/esp32c5/register/soc/keymng_reg.h diff --git a/components/soc/esp32c5/include/soc/keymng_struct.h b/components/soc/esp32c5/register/soc/keymng_struct.h similarity index 100% rename from components/soc/esp32c5/include/soc/keymng_struct.h rename to components/soc/esp32c5/register/soc/keymng_struct.h diff --git a/components/soc/esp32c5/include/soc/ledc_reg.h b/components/soc/esp32c5/register/soc/ledc_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/ledc_reg.h rename to components/soc/esp32c5/register/soc/ledc_reg.h diff --git a/components/soc/esp32c5/include/soc/ledc_struct.h b/components/soc/esp32c5/register/soc/ledc_struct.h similarity index 100% rename from components/soc/esp32c5/include/soc/ledc_struct.h rename to components/soc/esp32c5/register/soc/ledc_struct.h diff --git a/components/soc/esp32c5/include/soc/lp_analog_peri_reg.h b/components/soc/esp32c5/register/soc/lp_analog_peri_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/lp_analog_peri_reg.h rename to components/soc/esp32c5/register/soc/lp_analog_peri_reg.h diff --git a/components/soc/esp32c5/include/soc/lp_analog_peri_struct.h b/components/soc/esp32c5/register/soc/lp_analog_peri_struct.h similarity index 100% rename from components/soc/esp32c5/include/soc/lp_analog_peri_struct.h rename to components/soc/esp32c5/register/soc/lp_analog_peri_struct.h diff --git a/components/soc/esp32c5/include/soc/lp_aon_reg.h b/components/soc/esp32c5/register/soc/lp_aon_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/lp_aon_reg.h rename to components/soc/esp32c5/register/soc/lp_aon_reg.h diff --git a/components/soc/esp32c5/include/soc/lp_aon_struct.h b/components/soc/esp32c5/register/soc/lp_aon_struct.h similarity index 100% rename from components/soc/esp32c5/include/soc/lp_aon_struct.h rename to components/soc/esp32c5/register/soc/lp_aon_struct.h diff --git a/components/soc/esp32c5/include/soc/lp_apm0_reg.h b/components/soc/esp32c5/register/soc/lp_apm0_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/lp_apm0_reg.h rename to components/soc/esp32c5/register/soc/lp_apm0_reg.h diff --git a/components/soc/esp32c5/include/soc/lp_apm0_struct.h b/components/soc/esp32c5/register/soc/lp_apm0_struct.h similarity index 100% rename from components/soc/esp32c5/include/soc/lp_apm0_struct.h rename to components/soc/esp32c5/register/soc/lp_apm0_struct.h diff --git a/components/soc/esp32c5/include/soc/lp_apm_reg.h b/components/soc/esp32c5/register/soc/lp_apm_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/lp_apm_reg.h rename to components/soc/esp32c5/register/soc/lp_apm_reg.h diff --git a/components/soc/esp32c5/include/soc/lp_apm_struct.h b/components/soc/esp32c5/register/soc/lp_apm_struct.h similarity index 100% rename from components/soc/esp32c5/include/soc/lp_apm_struct.h rename to components/soc/esp32c5/register/soc/lp_apm_struct.h diff --git a/components/soc/esp32c5/include/soc/lp_clkrst_reg.h b/components/soc/esp32c5/register/soc/lp_clkrst_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/lp_clkrst_reg.h rename to components/soc/esp32c5/register/soc/lp_clkrst_reg.h diff --git a/components/soc/esp32c5/include/soc/lp_clkrst_struct.h b/components/soc/esp32c5/register/soc/lp_clkrst_struct.h similarity index 100% rename from components/soc/esp32c5/include/soc/lp_clkrst_struct.h rename to components/soc/esp32c5/register/soc/lp_clkrst_struct.h diff --git a/components/soc/esp32c5/include/soc/lp_gpio_reg.h b/components/soc/esp32c5/register/soc/lp_gpio_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/lp_gpio_reg.h rename to components/soc/esp32c5/register/soc/lp_gpio_reg.h diff --git a/components/soc/esp32c5/include/soc/lp_gpio_struct.h b/components/soc/esp32c5/register/soc/lp_gpio_struct.h similarity index 100% rename from components/soc/esp32c5/include/soc/lp_gpio_struct.h rename to components/soc/esp32c5/register/soc/lp_gpio_struct.h diff --git a/components/soc/esp32c5/include/soc/lp_i2c_ana_mst_reg.h b/components/soc/esp32c5/register/soc/lp_i2c_ana_mst_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/lp_i2c_ana_mst_reg.h rename to components/soc/esp32c5/register/soc/lp_i2c_ana_mst_reg.h diff --git a/components/soc/esp32c5/include/soc/lp_i2c_ana_mst_struct.h b/components/soc/esp32c5/register/soc/lp_i2c_ana_mst_struct.h similarity index 100% rename from components/soc/esp32c5/include/soc/lp_i2c_ana_mst_struct.h rename to components/soc/esp32c5/register/soc/lp_i2c_ana_mst_struct.h diff --git a/components/soc/esp32c5/include/soc/lp_i2c_reg.h b/components/soc/esp32c5/register/soc/lp_i2c_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/lp_i2c_reg.h rename to components/soc/esp32c5/register/soc/lp_i2c_reg.h diff --git a/components/soc/esp32c5/include/soc/lp_i2c_struct.h b/components/soc/esp32c5/register/soc/lp_i2c_struct.h similarity index 100% rename from components/soc/esp32c5/include/soc/lp_i2c_struct.h rename to components/soc/esp32c5/register/soc/lp_i2c_struct.h diff --git a/components/soc/esp32c5/include/soc/lp_iomux_reg.h b/components/soc/esp32c5/register/soc/lp_iomux_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/lp_iomux_reg.h rename to components/soc/esp32c5/register/soc/lp_iomux_reg.h diff --git a/components/soc/esp32c5/include/soc/lp_iomux_struct.h b/components/soc/esp32c5/register/soc/lp_iomux_struct.h similarity index 100% rename from components/soc/esp32c5/include/soc/lp_iomux_struct.h rename to components/soc/esp32c5/register/soc/lp_iomux_struct.h diff --git a/components/soc/esp32c5/include/soc/lp_tee_reg.h b/components/soc/esp32c5/register/soc/lp_tee_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/lp_tee_reg.h rename to components/soc/esp32c5/register/soc/lp_tee_reg.h diff --git a/components/soc/esp32c5/include/soc/lp_tee_struct.h b/components/soc/esp32c5/register/soc/lp_tee_struct.h similarity index 100% rename from components/soc/esp32c5/include/soc/lp_tee_struct.h rename to components/soc/esp32c5/register/soc/lp_tee_struct.h diff --git a/components/soc/esp32c5/include/soc/lp_timer_reg.h b/components/soc/esp32c5/register/soc/lp_timer_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/lp_timer_reg.h rename to components/soc/esp32c5/register/soc/lp_timer_reg.h diff --git a/components/soc/esp32c5/include/soc/lp_timer_struct.h b/components/soc/esp32c5/register/soc/lp_timer_struct.h similarity index 100% rename from components/soc/esp32c5/include/soc/lp_timer_struct.h rename to components/soc/esp32c5/register/soc/lp_timer_struct.h diff --git a/components/soc/esp32c5/include/soc/lp_uart_reg.h b/components/soc/esp32c5/register/soc/lp_uart_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/lp_uart_reg.h rename to components/soc/esp32c5/register/soc/lp_uart_reg.h diff --git a/components/soc/esp32c5/include/soc/lp_uart_struct.h b/components/soc/esp32c5/register/soc/lp_uart_struct.h similarity index 100% rename from components/soc/esp32c5/include/soc/lp_uart_struct.h rename to components/soc/esp32c5/register/soc/lp_uart_struct.h diff --git a/components/soc/esp32c5/include/soc/lp_wdt_reg.h b/components/soc/esp32c5/register/soc/lp_wdt_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/lp_wdt_reg.h rename to components/soc/esp32c5/register/soc/lp_wdt_reg.h diff --git a/components/soc/esp32c5/include/soc/lp_wdt_struct.h b/components/soc/esp32c5/register/soc/lp_wdt_struct.h similarity index 100% rename from components/soc/esp32c5/include/soc/lp_wdt_struct.h rename to components/soc/esp32c5/register/soc/lp_wdt_struct.h diff --git a/components/soc/esp32c5/include/soc/lpperi_reg.h b/components/soc/esp32c5/register/soc/lpperi_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/lpperi_reg.h rename to components/soc/esp32c5/register/soc/lpperi_reg.h diff --git a/components/soc/esp32c5/include/soc/lpperi_struct.h b/components/soc/esp32c5/register/soc/lpperi_struct.h similarity index 100% rename from components/soc/esp32c5/include/soc/lpperi_struct.h rename to components/soc/esp32c5/register/soc/lpperi_struct.h diff --git a/components/soc/esp32c5/include/soc/mcpwm_reg.h b/components/soc/esp32c5/register/soc/mcpwm_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/mcpwm_reg.h rename to components/soc/esp32c5/register/soc/mcpwm_reg.h diff --git a/components/soc/esp32c5/include/soc/mcpwm_struct.h b/components/soc/esp32c5/register/soc/mcpwm_struct.h similarity index 100% rename from components/soc/esp32c5/include/soc/mcpwm_struct.h rename to components/soc/esp32c5/register/soc/mcpwm_struct.h diff --git a/components/soc/esp32c5/include/soc/mem_monitor_reg.h b/components/soc/esp32c5/register/soc/mem_monitor_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/mem_monitor_reg.h rename to components/soc/esp32c5/register/soc/mem_monitor_reg.h diff --git a/components/soc/esp32c5/include/soc/mem_monitor_struct.h b/components/soc/esp32c5/register/soc/mem_monitor_struct.h similarity index 100% rename from components/soc/esp32c5/include/soc/mem_monitor_struct.h rename to components/soc/esp32c5/register/soc/mem_monitor_struct.h diff --git a/components/soc/esp32c5/include/soc/parl_io_reg.h b/components/soc/esp32c5/register/soc/parl_io_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/parl_io_reg.h rename to components/soc/esp32c5/register/soc/parl_io_reg.h diff --git a/components/soc/esp32c5/include/soc/parl_io_struct.h b/components/soc/esp32c5/register/soc/parl_io_struct.h similarity index 100% rename from components/soc/esp32c5/include/soc/parl_io_struct.h rename to components/soc/esp32c5/register/soc/parl_io_struct.h diff --git a/components/soc/esp32c5/include/soc/pau_reg.h b/components/soc/esp32c5/register/soc/pau_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/pau_reg.h rename to components/soc/esp32c5/register/soc/pau_reg.h diff --git a/components/soc/esp32c5/include/soc/pau_struct.h b/components/soc/esp32c5/register/soc/pau_struct.h similarity index 100% rename from components/soc/esp32c5/include/soc/pau_struct.h rename to components/soc/esp32c5/register/soc/pau_struct.h diff --git a/components/soc/esp32c5/include/soc/pcnt_reg.h b/components/soc/esp32c5/register/soc/pcnt_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/pcnt_reg.h rename to components/soc/esp32c5/register/soc/pcnt_reg.h diff --git a/components/soc/esp32c5/include/soc/pcnt_struct.h b/components/soc/esp32c5/register/soc/pcnt_struct.h similarity index 100% rename from components/soc/esp32c5/include/soc/pcnt_struct.h rename to components/soc/esp32c5/register/soc/pcnt_struct.h diff --git a/components/soc/esp32c5/include/soc/pcr_reg.h b/components/soc/esp32c5/register/soc/pcr_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/pcr_reg.h rename to components/soc/esp32c5/register/soc/pcr_reg.h diff --git a/components/soc/esp32c5/include/soc/pcr_struct.h b/components/soc/esp32c5/register/soc/pcr_struct.h similarity index 100% rename from components/soc/esp32c5/include/soc/pcr_struct.h rename to components/soc/esp32c5/register/soc/pcr_struct.h diff --git a/components/soc/esp32c5/include/soc/pmu_reg.h b/components/soc/esp32c5/register/soc/pmu_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/pmu_reg.h rename to components/soc/esp32c5/register/soc/pmu_reg.h diff --git a/components/soc/esp32c5/include/soc/pmu_struct.h b/components/soc/esp32c5/register/soc/pmu_struct.h similarity index 99% rename from components/soc/esp32c5/include/soc/pmu_struct.h rename to components/soc/esp32c5/register/soc/pmu_struct.h index 67f6269fc32..ad7fc03d016 100644 --- a/components/soc/esp32c5/include/soc/pmu_struct.h +++ b/components/soc/esp32c5/register/soc/pmu_struct.h @@ -11,7 +11,7 @@ extern "C" { #endif -#include "soc.h" +#include "soc/soc.h" #include "soc/pmu_reg.h" typedef union { diff --git a/components/soc/esp32c5/include/soc/pvt_reg.h b/components/soc/esp32c5/register/soc/pvt_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/pvt_reg.h rename to components/soc/esp32c5/register/soc/pvt_reg.h diff --git a/components/soc/esp32c5/include/soc/pvt_struct.h b/components/soc/esp32c5/register/soc/pvt_struct.h similarity index 100% rename from components/soc/esp32c5/include/soc/pvt_struct.h rename to components/soc/esp32c5/register/soc/pvt_struct.h diff --git a/components/soc/esp32c5/include/soc/reg_base.h b/components/soc/esp32c5/register/soc/reg_base.h similarity index 100% rename from components/soc/esp32c5/include/soc/reg_base.h rename to components/soc/esp32c5/register/soc/reg_base.h diff --git a/components/soc/esp32c5/include/soc/rmt_reg.h b/components/soc/esp32c5/register/soc/rmt_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/rmt_reg.h rename to components/soc/esp32c5/register/soc/rmt_reg.h diff --git a/components/soc/esp32c5/include/soc/rmt_struct.h b/components/soc/esp32c5/register/soc/rmt_struct.h similarity index 100% rename from components/soc/esp32c5/include/soc/rmt_struct.h rename to components/soc/esp32c5/register/soc/rmt_struct.h diff --git a/components/soc/esp32c5/include/soc/rsa_reg.h b/components/soc/esp32c5/register/soc/rsa_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/rsa_reg.h rename to components/soc/esp32c5/register/soc/rsa_reg.h diff --git a/components/soc/esp32c5/include/soc/rsa_struct.h b/components/soc/esp32c5/register/soc/rsa_struct.h similarity index 100% rename from components/soc/esp32c5/include/soc/rsa_struct.h rename to components/soc/esp32c5/register/soc/rsa_struct.h diff --git a/components/soc/esp32c5/include/soc/sha_reg.h b/components/soc/esp32c5/register/soc/sha_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/sha_reg.h rename to components/soc/esp32c5/register/soc/sha_reg.h diff --git a/components/soc/esp32c5/include/soc/sha_struct.h b/components/soc/esp32c5/register/soc/sha_struct.h similarity index 100% rename from components/soc/esp32c5/include/soc/sha_struct.h rename to components/soc/esp32c5/register/soc/sha_struct.h diff --git a/components/soc/esp32c5/include/soc/soc_etm_reg.h b/components/soc/esp32c5/register/soc/soc_etm_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/soc_etm_reg.h rename to components/soc/esp32c5/register/soc/soc_etm_reg.h diff --git a/components/soc/esp32c5/include/soc/soc_etm_struct.h b/components/soc/esp32c5/register/soc/soc_etm_struct.h similarity index 100% rename from components/soc/esp32c5/include/soc/soc_etm_struct.h rename to components/soc/esp32c5/register/soc/soc_etm_struct.h diff --git a/components/soc/esp32c5/include/soc/spi1_mem_reg.h b/components/soc/esp32c5/register/soc/spi1_mem_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/spi1_mem_reg.h rename to components/soc/esp32c5/register/soc/spi1_mem_reg.h diff --git a/components/soc/esp32c5/include/soc/spi1_mem_struct.h b/components/soc/esp32c5/register/soc/spi1_mem_struct.h similarity index 100% rename from components/soc/esp32c5/include/soc/spi1_mem_struct.h rename to components/soc/esp32c5/register/soc/spi1_mem_struct.h diff --git a/components/soc/esp32c5/include/soc/spi_mem_c_reg.h b/components/soc/esp32c5/register/soc/spi_mem_c_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/spi_mem_c_reg.h rename to components/soc/esp32c5/register/soc/spi_mem_c_reg.h diff --git a/components/soc/esp32c5/include/soc/spi_mem_c_struct.h b/components/soc/esp32c5/register/soc/spi_mem_c_struct.h similarity index 100% rename from components/soc/esp32c5/include/soc/spi_mem_c_struct.h rename to components/soc/esp32c5/register/soc/spi_mem_c_struct.h diff --git a/components/soc/esp32c5/include/soc/spi_reg.h b/components/soc/esp32c5/register/soc/spi_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/spi_reg.h rename to components/soc/esp32c5/register/soc/spi_reg.h diff --git a/components/soc/esp32c5/include/soc/spi_struct.h b/components/soc/esp32c5/register/soc/spi_struct.h similarity index 100% rename from components/soc/esp32c5/include/soc/spi_struct.h rename to components/soc/esp32c5/register/soc/spi_struct.h diff --git a/components/soc/esp32c5/include/soc/systimer_reg.h b/components/soc/esp32c5/register/soc/systimer_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/systimer_reg.h rename to components/soc/esp32c5/register/soc/systimer_reg.h diff --git a/components/soc/esp32c5/include/soc/systimer_struct.h b/components/soc/esp32c5/register/soc/systimer_struct.h similarity index 100% rename from components/soc/esp32c5/include/soc/systimer_struct.h rename to components/soc/esp32c5/register/soc/systimer_struct.h diff --git a/components/soc/esp32c5/include/soc/tee_reg.h b/components/soc/esp32c5/register/soc/tee_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/tee_reg.h rename to components/soc/esp32c5/register/soc/tee_reg.h diff --git a/components/soc/esp32c5/include/soc/tee_struct.h b/components/soc/esp32c5/register/soc/tee_struct.h similarity index 100% rename from components/soc/esp32c5/include/soc/tee_struct.h rename to components/soc/esp32c5/register/soc/tee_struct.h diff --git a/components/soc/esp32c5/include/soc/timer_group_reg.h b/components/soc/esp32c5/register/soc/timer_group_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/timer_group_reg.h rename to components/soc/esp32c5/register/soc/timer_group_reg.h diff --git a/components/soc/esp32c5/include/soc/timer_group_struct.h b/components/soc/esp32c5/register/soc/timer_group_struct.h similarity index 100% rename from components/soc/esp32c5/include/soc/timer_group_struct.h rename to components/soc/esp32c5/register/soc/timer_group_struct.h diff --git a/components/soc/esp32c5/include/soc/trace_reg.h b/components/soc/esp32c5/register/soc/trace_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/trace_reg.h rename to components/soc/esp32c5/register/soc/trace_reg.h diff --git a/components/soc/esp32c5/include/soc/trace_struct.h b/components/soc/esp32c5/register/soc/trace_struct.h similarity index 100% rename from components/soc/esp32c5/include/soc/trace_struct.h rename to components/soc/esp32c5/register/soc/trace_struct.h diff --git a/components/soc/esp32c5/include/soc/twaifd_reg.h b/components/soc/esp32c5/register/soc/twaifd_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/twaifd_reg.h rename to components/soc/esp32c5/register/soc/twaifd_reg.h diff --git a/components/soc/esp32c5/include/soc/twaifd_struct.h b/components/soc/esp32c5/register/soc/twaifd_struct.h similarity index 100% rename from components/soc/esp32c5/include/soc/twaifd_struct.h rename to components/soc/esp32c5/register/soc/twaifd_struct.h diff --git a/components/soc/esp32c5/include/soc/uart_reg.h b/components/soc/esp32c5/register/soc/uart_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/uart_reg.h rename to components/soc/esp32c5/register/soc/uart_reg.h diff --git a/components/soc/esp32c5/include/soc/uart_struct.h b/components/soc/esp32c5/register/soc/uart_struct.h similarity index 100% rename from components/soc/esp32c5/include/soc/uart_struct.h rename to components/soc/esp32c5/register/soc/uart_struct.h diff --git a/components/soc/esp32c5/include/soc/uhci_reg.h b/components/soc/esp32c5/register/soc/uhci_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/uhci_reg.h rename to components/soc/esp32c5/register/soc/uhci_reg.h diff --git a/components/soc/esp32c5/include/soc/uhci_struct.h b/components/soc/esp32c5/register/soc/uhci_struct.h similarity index 100% rename from components/soc/esp32c5/include/soc/uhci_struct.h rename to components/soc/esp32c5/register/soc/uhci_struct.h diff --git a/components/soc/esp32c5/include/soc/usb_serial_jtag_reg.h b/components/soc/esp32c5/register/soc/usb_serial_jtag_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/usb_serial_jtag_reg.h rename to components/soc/esp32c5/register/soc/usb_serial_jtag_reg.h diff --git a/components/soc/esp32c5/include/soc/usb_serial_jtag_struct.h b/components/soc/esp32c5/register/soc/usb_serial_jtag_struct.h similarity index 100% rename from components/soc/esp32c5/include/soc/usb_serial_jtag_struct.h rename to components/soc/esp32c5/register/soc/usb_serial_jtag_struct.h From cb097aeb54564834732c8db267d8edb5ec758214 Mon Sep 17 00:00:00 2001 From: Chen Jichang Date: Wed, 9 Oct 2024 15:37:05 +0800 Subject: [PATCH 120/472] refactor(mcpwm): refactor gpio mode config in mcpwm Deprecate io_loop_back flag. Use capture timer to test generator and dead time. --- .../include/driver/mcpwm_cap.h | 3 +- components/esp_driver_mcpwm/src/mcpwm_cap.c | 34 +- components/esp_driver_mcpwm/src/mcpwm_fault.c | 32 +- components/esp_driver_mcpwm/src/mcpwm_gen.c | 28 +- .../esp_driver_mcpwm/src/mcpwm_private.h | 3 - components/esp_driver_mcpwm/src/mcpwm_sync.c | 31 +- .../test_apps/mcpwm/main/test_mcpwm_cap.c | 13 +- .../test_apps/mcpwm/main/test_mcpwm_fault.c | 13 +- .../test_apps/mcpwm/main/test_mcpwm_gen.c | 325 ++++++++++++++++-- .../test_apps/mcpwm/main/test_mcpwm_iram.c | 11 +- .../test_apps/mcpwm/main/test_mcpwm_oper.c | 45 ++- .../test_apps/mcpwm/main/test_mcpwm_sync.c | 12 +- docs/en/api-reference/peripherals/mcpwm.rst | 6 - .../zh_CN/api-reference/peripherals/mcpwm.rst | 6 - 14 files changed, 442 insertions(+), 120 deletions(-) diff --git a/components/esp_driver_mcpwm/include/driver/mcpwm_cap.h b/components/esp_driver_mcpwm/include/driver/mcpwm_cap.h index 6e280860876..601454b82a4 100644 --- a/components/esp_driver_mcpwm/include/driver/mcpwm_cap.h +++ b/components/esp_driver_mcpwm/include/driver/mcpwm_cap.h @@ -145,8 +145,7 @@ typedef struct { uint32_t pull_down: 1; /*!< Whether to pull down internally */ uint32_t invert_cap_signal: 1; /*!< Invert the input capture signal */ uint32_t io_loop_back: 1; /*!< For debug/test, the signal output from the GPIO will be fed to the input path as well */ - uint32_t keep_io_conf_at_exit: 1; /*!< For debug/test, whether to keep the GPIO configuration when capture channel is deleted. - By default, driver will reset the GPIO pin at exit. */ + uint32_t keep_io_conf_at_exit: 1 __attribute__((deprecated)); /*!< Deprecated. Driver won't change the GPIO configuration in deinilization. */ } flags; /*!< Extra configuration flags for capture channel */ } mcpwm_capture_channel_config_t; diff --git a/components/esp_driver_mcpwm/src/mcpwm_cap.c b/components/esp_driver_mcpwm/src/mcpwm_cap.c index 0baf6b090cb..c80eedd6817 100644 --- a/components/esp_driver_mcpwm/src/mcpwm_cap.c +++ b/components/esp_driver_mcpwm/src/mcpwm_cap.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -24,9 +24,11 @@ #include "soc/soc_caps.h" #include "soc/mcpwm_periph.h" #include "hal/mcpwm_ll.h" +#include "hal/gpio_hal.h" #include "driver/mcpwm_cap.h" #include "driver/gpio.h" #include "mcpwm_private.h" +#include "esp_private/gpio.h" static const char *TAG = "mcpwm"; @@ -289,20 +291,25 @@ esp_err_t mcpwm_new_capture_channel(mcpwm_cap_timer_handle_t cap_timer, const mc if (config->gpio_num >= 0) { // GPIO configuration - gpio_config_t gpio_conf = { - .intr_type = GPIO_INTR_DISABLE, - .mode = GPIO_MODE_INPUT | (config->flags.io_loop_back ? GPIO_MODE_OUTPUT : 0), // also enable the output path if `io_loop_back` is enabled - .pin_bit_mask = (1ULL << config->gpio_num), - .pull_down_en = config->flags.pull_down, - .pull_up_en = config->flags.pull_up, - }; - ESP_GOTO_ON_ERROR(gpio_config(&gpio_conf), err, TAG, "config capture GPIO failed"); + gpio_func_sel(config->gpio_num, PIN_FUNC_GPIO); + gpio_input_enable(config->gpio_num); esp_rom_gpio_connect_in_signal(config->gpio_num, mcpwm_periph_signals.groups[group->group_id].captures[cap_chan_id].cap_sig, 0); + if (config->flags.pull_down) { + gpio_pulldown_en(config->gpio_num); + } + if (config->flags.pull_up) { + gpio_pullup_en(config->gpio_num); + } + + // deprecated, to be removed in in esp-idf v6.0 + if (config->flags.io_loop_back) { + gpio_ll_output_enable(&GPIO, config->gpio_num); + } } cap_chan->gpio_num = config->gpio_num; cap_chan->fsm = MCPWM_CAP_CHAN_FSM_INIT; - cap_chan->flags.reset_io_at_exit = !config->flags.keep_io_conf_at_exit && config->gpio_num >= 0; + *ret_cap_channel = cap_chan; ESP_LOGD(TAG, "new capture channel (%d,%d) at %p", group->group_id, cap_chan_id, cap_chan); return ESP_OK; @@ -323,15 +330,16 @@ esp_err_t mcpwm_del_capture_channel(mcpwm_cap_channel_handle_t cap_channel) int cap_chan_id = cap_channel->cap_chan_id; ESP_LOGD(TAG, "del capture channel (%d,%d)", group->group_id, cap_channel->cap_chan_id); - if (cap_channel->flags.reset_io_at_exit) { - gpio_reset_pin(cap_channel->gpio_num); - } portENTER_CRITICAL(&group->spinlock); mcpwm_ll_intr_enable(hal->dev, MCPWM_LL_EVENT_CAPTURE(cap_chan_id), false); mcpwm_ll_intr_clear_status(hal->dev, MCPWM_LL_EVENT_CAPTURE(cap_chan_id)); portEXIT_CRITICAL(&group->spinlock); + // disconnect signal from the GPIO pin + esp_rom_gpio_connect_in_signal(GPIO_MATRIX_CONST_ZERO_INPUT, + mcpwm_periph_signals.groups[group->group_id].captures[cap_chan_id].cap_sig, 0); + // recycle memory resource ESP_RETURN_ON_ERROR(mcpwm_capture_channel_destroy(cap_channel), TAG, "destroy capture channel failed"); return ESP_OK; diff --git a/components/esp_driver_mcpwm/src/mcpwm_fault.c b/components/esp_driver_mcpwm/src/mcpwm_fault.c index b2539e2048f..d1ccde6912d 100644 --- a/components/esp_driver_mcpwm/src/mcpwm_fault.c +++ b/components/esp_driver_mcpwm/src/mcpwm_fault.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -22,9 +22,11 @@ #include "soc/soc_caps.h" #include "soc/mcpwm_periph.h" #include "hal/mcpwm_ll.h" +#include "hal/gpio_hal.h" #include "driver/mcpwm_fault.h" #include "driver/gpio.h" #include "mcpwm_private.h" +#include "esp_private/gpio.h" static const char *TAG = "mcpwm"; @@ -112,16 +114,22 @@ esp_err_t mcpwm_new_gpio_fault(const mcpwm_gpio_fault_config_t *config, mcpwm_fa ESP_GOTO_ON_ERROR(mcpwm_check_intr_priority(group, config->intr_priority), err, TAG, "set group interrupt priority failed"); // GPIO configuration - gpio_config_t gpio_conf = { - .intr_type = GPIO_INTR_DISABLE, - .mode = GPIO_MODE_INPUT | (config->flags.io_loop_back ? GPIO_MODE_OUTPUT : 0), // also enable the output path if `io_loop_back` is enabled - .pin_bit_mask = (1ULL << config->gpio_num), - .pull_down_en = config->flags.pull_down, - .pull_up_en = config->flags.pull_up, - }; - ESP_GOTO_ON_ERROR(gpio_config(&gpio_conf), err, TAG, "config fault GPIO failed"); + gpio_func_sel(config->gpio_num, PIN_FUNC_GPIO); + gpio_input_enable(config->gpio_num); esp_rom_gpio_connect_in_signal(config->gpio_num, mcpwm_periph_signals.groups[group_id].gpio_faults[fault_id].fault_sig, 0); + if (config->flags.pull_down) { + gpio_pulldown_en(config->gpio_num); + } + if (config->flags.pull_up) { + gpio_pullup_en(config->gpio_num); + } + + // deprecated, to be removed in in esp-idf v6.0 + if (config->flags.io_loop_back) { + gpio_ll_output_enable(&GPIO, config->gpio_num); + } + // set fault detection polarity // different gpio faults share the same config register, using a group level spin lock portENTER_CRITICAL(&group->spinlock); @@ -151,10 +159,10 @@ static esp_err_t mcpwm_del_gpio_fault(mcpwm_fault_handle_t fault) mcpwm_gpio_fault_t *gpio_fault = __containerof(fault, mcpwm_gpio_fault_t, base); mcpwm_group_t *group = fault->group; mcpwm_hal_context_t *hal = &group->hal; + int group_id = group->group_id; int fault_id = gpio_fault->fault_id; ESP_LOGD(TAG, "del GPIO fault (%d,%d)", group->group_id, fault_id); - gpio_reset_pin(gpio_fault->gpio_num); portENTER_CRITICAL(&group->spinlock); mcpwm_ll_intr_enable(hal->dev, MCPWM_LL_EVENT_FAULT_MASK(fault_id), false); @@ -164,6 +172,10 @@ static esp_err_t mcpwm_del_gpio_fault(mcpwm_fault_handle_t fault) // disable fault detection mcpwm_ll_fault_enable_detection(hal->dev, fault_id, false); + // disconnect signal from the GPIO pin + esp_rom_gpio_connect_in_signal(GPIO_MATRIX_CONST_ZERO_INPUT, + mcpwm_periph_signals.groups[group_id].gpio_faults[fault_id].fault_sig, 0); + // recycle memory resource ESP_RETURN_ON_ERROR(mcpwm_gpio_fault_destroy(gpio_fault), TAG, "destroy GPIO fault failed"); return ESP_OK; diff --git a/components/esp_driver_mcpwm/src/mcpwm_gen.c b/components/esp_driver_mcpwm/src/mcpwm_gen.c index 0851f744c61..2c145e8bea4 100644 --- a/components/esp_driver_mcpwm/src/mcpwm_gen.c +++ b/components/esp_driver_mcpwm/src/mcpwm_gen.c @@ -21,10 +21,12 @@ #include "soc/soc_caps.h" #include "soc/mcpwm_periph.h" #include "hal/mcpwm_ll.h" +#include "hal/gpio_hal.h" #include "driver/gpio.h" #include "driver/mcpwm_gen.h" #include "mcpwm_private.h" #include "esp_private/esp_gpio_reserve.h" +#include "esp_private/gpio.h" static const char *TAG = "mcpwm"; @@ -84,27 +86,29 @@ esp_err_t mcpwm_new_generator(mcpwm_oper_handle_t oper, const mcpwm_generator_co // reset generator mcpwm_hal_generator_reset(hal, oper_id, gen_id); - // GPIO configuration gen->gen_gpio_num = -1; // gpio not initialized yet - gpio_config_t gpio_conf = { - .intr_type = GPIO_INTR_DISABLE, - // also enable the input path if `io_loop_back` is enabled - .mode = (config->flags.io_od_mode ? GPIO_MODE_OUTPUT_OD : GPIO_MODE_OUTPUT) | (config->flags.io_loop_back ? GPIO_MODE_INPUT : 0), - .pin_bit_mask = (1ULL << config->gen_gpio_num), - .pull_down_en = config->flags.pull_down, - .pull_up_en = config->flags.pull_up, - }; - ESP_GOTO_ON_ERROR(gpio_config(&gpio_conf), err, TAG, "config gen GPIO failed"); // reserve the GPIO output path, because we don't expect another peripheral to signal to the same GPIO uint64_t old_gpio_rsv_mask = esp_gpio_reserve(BIT64(config->gen_gpio_num)); // check if the GPIO is already used by others if (old_gpio_rsv_mask & BIT64(config->gen_gpio_num)) { ESP_LOGW(TAG, "GPIO %d is not usable, maybe conflict with others", config->gen_gpio_num); } + + // GPIO Matrix/MUX configuration + gpio_func_sel(config->gen_gpio_num, PIN_FUNC_GPIO); + // connect the signal to the GPIO by matrix, it will also enable the output path properly esp_rom_gpio_connect_out_signal(config->gen_gpio_num, mcpwm_periph_signals.groups[group->group_id].operators[oper_id].generators[gen_id].pwm_sig, config->flags.invert_pwm, 0); + // deprecated, to be removed in in esp-idf v6.0 + if (config->flags.io_loop_back) { + gpio_ll_input_enable(&GPIO, config->gen_gpio_num); + } + if (config->flags.io_od_mode) { + gpio_ll_od_enable(&GPIO, config->gen_gpio_num); + } + // fill in other generator members gen->gen_gpio_num = config->gen_gpio_num; gen->spinlock = (portMUX_TYPE)portMUX_INITIALIZER_UNLOCKED; @@ -126,9 +130,9 @@ esp_err_t mcpwm_del_generator(mcpwm_gen_handle_t gen) mcpwm_group_t *group = oper->group; ESP_LOGD(TAG, "del generator (%d,%d,%d)", group->group_id, oper->oper_id, gen->gen_id); - // reset GPIO + // disable GPIO output if (gen->gen_gpio_num >= 0) { - gpio_reset_pin(gen->gen_gpio_num); + gpio_output_disable(gen->gen_gpio_num); esp_gpio_revoke(BIT64(gen->gen_gpio_num)); } // recycle memory resource diff --git a/components/esp_driver_mcpwm/src/mcpwm_private.h b/components/esp_driver_mcpwm/src/mcpwm_private.h index cc3e2fcd490..e299d3dd80b 100644 --- a/components/esp_driver_mcpwm/src/mcpwm_private.h +++ b/components/esp_driver_mcpwm/src/mcpwm_private.h @@ -250,9 +250,6 @@ struct mcpwm_cap_channel_t { intr_handle_t intr; // Interrupt handle mcpwm_capture_event_cb_t on_cap; // Callback function which would be invoked in capture interrupt routine void *user_data; // user data which would be passed to the capture callback - struct { - uint32_t reset_io_at_exit: 1; // Whether to reset the GPIO configuration when capture channel is deleted - } flags; }; mcpwm_group_t *mcpwm_acquire_group_handle(int group_id); diff --git a/components/esp_driver_mcpwm/src/mcpwm_sync.c b/components/esp_driver_mcpwm/src/mcpwm_sync.c index dede456adc3..3fe84b5fb26 100644 --- a/components/esp_driver_mcpwm/src/mcpwm_sync.c +++ b/components/esp_driver_mcpwm/src/mcpwm_sync.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -22,9 +22,11 @@ #include "soc/soc_caps.h" #include "soc/mcpwm_periph.h" #include "hal/mcpwm_ll.h" +#include "hal/gpio_hal.h" #include "driver/mcpwm_sync.h" #include "driver/gpio.h" #include "mcpwm_private.h" +#include "esp_private/gpio.h" static const char *TAG = "mcpwm"; @@ -192,16 +194,23 @@ esp_err_t mcpwm_new_gpio_sync_src(const mcpwm_gpio_sync_src_config_t *config, mc int sync_id = gpio_sync_src->sync_id; // GPIO configuration - gpio_config_t gpio_conf = { - .intr_type = GPIO_INTR_DISABLE, - .mode = GPIO_MODE_INPUT | (config->flags.io_loop_back ? GPIO_MODE_OUTPUT : 0), // also enable the output path if `io_loop_back` is enabled - .pin_bit_mask = (1ULL << config->gpio_num), - .pull_down_en = config->flags.pull_down, - .pull_up_en = config->flags.pull_up, - }; - ESP_GOTO_ON_ERROR(gpio_config(&gpio_conf), err, TAG, "config sync GPIO failed"); + gpio_func_sel(config->gpio_num, PIN_FUNC_GPIO); + gpio_input_enable(config->gpio_num); + esp_rom_gpio_connect_in_signal(config->gpio_num, mcpwm_periph_signals.groups[group_id].gpio_synchros[sync_id].sync_sig, 0); + if (config->flags.pull_down) { + gpio_pulldown_en(config->gpio_num); + } + if (config->flags.pull_up) { + gpio_pullup_en(config->gpio_num); + } + + // deprecated, to be removed in in esp-idf v6.0 + if (config->flags.io_loop_back) { + gpio_ll_output_enable(&GPIO, config->gpio_num); + } + // different ext sync share the same config register, using a group level spin lock portENTER_CRITICAL(&group->spinlock); mcpwm_ll_invert_gpio_sync_input(group->hal.dev, sync_id, config->flags.active_neg); @@ -226,9 +235,11 @@ static esp_err_t mcpwm_del_gpio_sync_src(mcpwm_sync_t *sync_src) { mcpwm_gpio_sync_src_t *gpio_sync_src = __containerof(sync_src, mcpwm_gpio_sync_src_t, base); mcpwm_group_t *group = sync_src->group; + int group_id = group->group_id; + int sync_id = gpio_sync_src->sync_id; ESP_LOGD(TAG, "del gpio sync_src (%d,%d)", group->group_id, gpio_sync_src->sync_id); - gpio_reset_pin(gpio_sync_src->gpio_num); + esp_rom_gpio_connect_in_signal(GPIO_MATRIX_CONST_ZERO_INPUT, mcpwm_periph_signals.groups[group_id].gpio_synchros[sync_id].sync_sig, 0); // recycle memory resource ESP_RETURN_ON_ERROR(mcpwm_gpio_sync_src_destroy(gpio_sync_src), TAG, "destroy GPIO sync_src failed"); diff --git a/components/esp_driver_mcpwm/test_apps/mcpwm/main/test_mcpwm_cap.c b/components/esp_driver_mcpwm/test_apps/mcpwm/main/test_mcpwm_cap.c index 228d0648cf7..8c01654f4f8 100644 --- a/components/esp_driver_mcpwm/test_apps/mcpwm/main/test_mcpwm_cap.c +++ b/components/esp_driver_mcpwm/test_apps/mcpwm/main/test_mcpwm_cap.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -71,6 +71,14 @@ static bool test_capture_callback(mcpwm_cap_channel_handle_t cap_channel, const TEST_CASE("mcpwm_capture_ext_gpio", "[mcpwm]") { + printf("init a gpio to simulate the external capture signal\r\n"); + const int cap_gpio = TEST_CAP_GPIO; + gpio_config_t ext_gpio_conf = { + .mode = GPIO_MODE_OUTPUT, + .pin_bit_mask = BIT(cap_gpio), + }; + TEST_ESP_OK(gpio_config(&ext_gpio_conf)); + printf("install mcpwm capture timer\r\n"); mcpwm_cap_timer_handle_t cap_timer = NULL; mcpwm_capture_timer_config_t cap_timer_config = { @@ -80,7 +88,6 @@ TEST_CASE("mcpwm_capture_ext_gpio", "[mcpwm]") }; TEST_ESP_OK(mcpwm_new_capture_timer(&cap_timer_config, &cap_timer)); - const int cap_gpio = TEST_CAP_GPIO; // put the GPIO into a preset state gpio_set_level(cap_gpio, 0); @@ -91,7 +98,6 @@ TEST_CASE("mcpwm_capture_ext_gpio", "[mcpwm]") .prescale = 1, .flags.pos_edge = true, .flags.neg_edge = true, - .flags.io_loop_back = true, // so we can use GPIO functions to simulate the external capture signal .flags.pull_up = true, }; TEST_ESP_OK(mcpwm_new_capture_channel(cap_timer, &cap_chan_config, &pps_channel)); @@ -127,6 +133,7 @@ TEST_CASE("mcpwm_capture_ext_gpio", "[mcpwm]") TEST_ESP_OK(mcpwm_del_capture_channel(pps_channel)); TEST_ESP_OK(mcpwm_capture_timer_disable(cap_timer)); TEST_ESP_OK(mcpwm_del_capture_timer(cap_timer)); + TEST_ESP_OK(gpio_reset_pin(cap_gpio)); } typedef struct { diff --git a/components/esp_driver_mcpwm/test_apps/mcpwm/main/test_mcpwm_fault.c b/components/esp_driver_mcpwm/test_apps/mcpwm/main/test_mcpwm_fault.c index 38a852c06f8..2dc14b34d39 100644 --- a/components/esp_driver_mcpwm/test_apps/mcpwm/main/test_mcpwm_fault.c +++ b/components/esp_driver_mcpwm/test_apps/mcpwm/main/test_mcpwm_fault.c @@ -58,15 +58,21 @@ static bool IRAM_ATTR test_fault_exit_callback(mcpwm_fault_handle_t detector, co TEST_CASE("mcpwm_gpio_fault_event_callbacks", "[mcpwm]") { - printf("create gpio fault\r\n"); + printf("init a gpio to simulate the fault signal\r\n"); const int fault_gpio = TEST_FAULT_GPIO; + gpio_config_t fault_gpio_conf = { + .mode = GPIO_MODE_OUTPUT, + .pin_bit_mask = BIT(fault_gpio), + }; + TEST_ESP_OK(gpio_config(&fault_gpio_conf)); + + printf("create gpio fault\r\n"); mcpwm_fault_handle_t fault = NULL; mcpwm_gpio_fault_config_t gpio_fault_config = { .group_id = 0, .gpio_num = fault_gpio, .flags.active_level = true, // active on high level .flags.pull_down = true, - .flags.io_loop_back = true, // for debug, so that we can use gpio_set_level to mimic a fault source }; TEST_ESP_OK(mcpwm_new_gpio_fault(&gpio_fault_config, &fault)); @@ -80,7 +86,7 @@ TEST_CASE("mcpwm_gpio_fault_event_callbacks", "[mcpwm]") }; TaskHandle_t task_to_notify = xTaskGetCurrentTaskHandle(); TEST_ESP_OK(mcpwm_fault_register_event_callbacks(fault, &cbs, task_to_notify)); - TEST_ASSERT_EQUAL(0, ulTaskNotifyTake(pdTRUE, pdMS_TO_TICKS(1000))); + TEST_ASSERT_EQUAL(0, ulTaskNotifyTake(pdTRUE, pdMS_TO_TICKS(100))); printf("trigget a fault event\r\n"); gpio_set_level(fault_gpio, 1); @@ -91,4 +97,5 @@ TEST_CASE("mcpwm_gpio_fault_event_callbacks", "[mcpwm]") TEST_ASSERT_NOT_EQUAL(0, ulTaskNotifyTake(pdTRUE, pdMS_TO_TICKS(10))); TEST_ESP_OK(mcpwm_del_fault(fault)); + TEST_ESP_OK(gpio_reset_pin(fault_gpio)); } diff --git a/components/esp_driver_mcpwm/test_apps/mcpwm/main/test_mcpwm_gen.c b/components/esp_driver_mcpwm/test_apps/mcpwm/main/test_mcpwm_gen.c index a00bed33090..1182f74e7df 100644 --- a/components/esp_driver_mcpwm/test_apps/mcpwm/main/test_mcpwm_gen.c +++ b/components/esp_driver_mcpwm/test_apps/mcpwm/main/test_mcpwm_gen.c @@ -7,6 +7,7 @@ #include "freertos/task.h" #include "unity.h" #include "soc/soc_caps.h" +#include "driver/mcpwm_cap.h" #include "driver/mcpwm_timer.h" #include "driver/mcpwm_oper.h" #include "driver/mcpwm_cmpr.h" @@ -15,6 +16,7 @@ #include "driver/mcpwm_sync.h" #include "driver/gpio.h" #include "test_mcpwm_utils.h" +#include "esp_clk_tree.h" TEST_CASE("mcpwm_generator_install_uninstall", "[mcpwm]") { @@ -46,6 +48,14 @@ TEST_CASE("mcpwm_generator_install_uninstall", "[mcpwm]") TEST_CASE("mcpwm_generator_force_level_hold_on", "[mcpwm]") { + const int gen_gpio = TEST_PWMA_GPIO; + printf("init a gpio to read generator output\r\n"); + gpio_config_t gen_gpio_conf = { + .mode = GPIO_MODE_INPUT, + .pin_bit_mask = BIT(gen_gpio), + }; + TEST_ESP_OK(gpio_config(&gen_gpio_conf)); + // The operator can even work without the timer printf("create operator and generator\r\n"); mcpwm_oper_handle_t oper = NULL; @@ -55,10 +65,8 @@ TEST_CASE("mcpwm_generator_force_level_hold_on", "[mcpwm]") TEST_ESP_OK(mcpwm_new_operator(&operator_config, &oper)); mcpwm_gen_handle_t generator = NULL; - const int gen_gpio = TEST_PWMA_GPIO; mcpwm_generator_config_t generator_config = { .gen_gpio_num = gen_gpio, - .flags.io_loop_back = true, // loop back for test }; TEST_ESP_OK(mcpwm_new_generator(oper, &generator_config, &generator)); @@ -78,12 +86,22 @@ TEST_CASE("mcpwm_generator_force_level_hold_on", "[mcpwm]") printf("delete generator and operator\r\n"); TEST_ESP_OK(mcpwm_del_generator(generator)); TEST_ESP_OK(mcpwm_del_operator(oper)); + TEST_ESP_OK(gpio_reset_pin(gen_gpio)); } // mcpwm_generator_set_force_level acts before the dead time module // so the value output on the generator is a combined result TEST_CASE("mcpwm_force_level_and_dead_time", "[mcpwm]") { + const int gen_a_gpio = TEST_PWMA_GPIO; + const int gen_b_gpio = TEST_PWMB_GPIO; + printf("init gpios to read generator output\r\n"); + gpio_config_t gen_gpio_conf = { + .mode = GPIO_MODE_INPUT, + .pin_bit_mask = BIT(gen_a_gpio) | BIT(gen_b_gpio), + }; + TEST_ESP_OK(gpio_config(&gen_gpio_conf)); + printf("create operator and generators\r\n"); mcpwm_oper_handle_t oper = NULL; mcpwm_operator_config_t operator_config = { @@ -93,11 +111,8 @@ TEST_CASE("mcpwm_force_level_and_dead_time", "[mcpwm]") mcpwm_gen_handle_t gen_a = NULL; mcpwm_gen_handle_t gen_b = NULL; - const int gen_a_gpio = TEST_PWMA_GPIO; - const int gen_b_gpio = TEST_PWMB_GPIO; mcpwm_generator_config_t generator_config = { .gen_gpio_num = gen_a_gpio, - .flags.io_loop_back = true, // loop back for test }; TEST_ESP_OK(mcpwm_new_generator(oper, &generator_config, &gen_a)); generator_config.gen_gpio_num = gen_b_gpio; @@ -128,10 +143,20 @@ TEST_CASE("mcpwm_force_level_and_dead_time", "[mcpwm]") TEST_ESP_OK(mcpwm_del_generator(gen_a)); TEST_ESP_OK(mcpwm_del_generator(gen_b)); TEST_ESP_OK(mcpwm_del_operator(oper)); + TEST_ESP_OK(gpio_reset_pin(gen_a_gpio)); + TEST_ESP_OK(gpio_reset_pin(gen_b_gpio)); } TEST_CASE("mcpwm_generator_force_level_recovery", "[mcpwm]") { + const int gen_gpio = TEST_PWMA_GPIO; + printf("init a gpio to read generator output\r\n"); + gpio_config_t gen_gpio_conf = { + .mode = GPIO_MODE_INPUT, + .pin_bit_mask = BIT(gen_gpio), + }; + TEST_ESP_OK(gpio_config(&gen_gpio_conf)); + printf("create mcpwm timer\r\n"); mcpwm_timer_config_t timer_config = { .group_id = 0, @@ -155,10 +180,8 @@ TEST_CASE("mcpwm_generator_force_level_recovery", "[mcpwm]") printf("create generator\r\n"); mcpwm_gen_handle_t generator = NULL; - const int gen_gpio = TEST_PWMA_GPIO; mcpwm_generator_config_t generator_config = { .gen_gpio_num = gen_gpio, - .flags.io_loop_back = true, // loop back for test }; TEST_ESP_OK(mcpwm_new_generator(oper, &generator_config, &generator)); @@ -195,11 +218,19 @@ TEST_CASE("mcpwm_generator_force_level_recovery", "[mcpwm]") TEST_ESP_OK(mcpwm_del_generator(generator)); TEST_ESP_OK(mcpwm_del_operator(oper)); TEST_ESP_OK(mcpwm_del_timer(timer)); + TEST_ESP_OK(gpio_reset_pin(gen_gpio)); } TEST_CASE("mcpwm_generator_action_on_timer_event", "[mcpwm]") { const int generator_gpio = TEST_PWMA_GPIO; + printf("init a gpio to read generator output\r\n"); + gpio_config_t gen_gpio_conf = { + .mode = GPIO_MODE_INPUT, + .pin_bit_mask = BIT(generator_gpio), + }; + TEST_ESP_OK(gpio_config(&gen_gpio_conf)); + printf("create timer and operator\r\n"); mcpwm_timer_config_t timer_config = { .group_id = 0, @@ -224,7 +255,6 @@ TEST_CASE("mcpwm_generator_action_on_timer_event", "[mcpwm]") printf("create generator\r\n"); mcpwm_generator_config_t gen_config = { .gen_gpio_num = generator_gpio, - .flags.io_loop_back = 1, // so that we can read the GPIO value by GPIO driver }; mcpwm_gen_handle_t gen = NULL; TEST_ESP_OK(mcpwm_new_generator(oper, &gen_config, &gen)); @@ -258,12 +288,26 @@ TEST_CASE("mcpwm_generator_action_on_timer_event", "[mcpwm]") TEST_ESP_OK(mcpwm_del_generator(gen)); TEST_ESP_OK(mcpwm_del_operator(oper)); TEST_ESP_OK(mcpwm_del_timer(timer)); + TEST_ESP_OK(gpio_reset_pin(generator_gpio)); +} + +TEST_MCPWM_CALLBACK_ATTR +static bool test_capture_callback(mcpwm_cap_channel_handle_t cap_channel, const mcpwm_capture_event_data_t *edata, void *user_data) +{ + uint32_t *cap_value = (uint32_t *)user_data; + if (edata->cap_edge == MCPWM_CAP_EDGE_NEG) { + cap_value[1] = edata->cap_value; + } else { + cap_value[0] = edata->cap_value; + } + return false; } typedef void (*set_gen_actions_cb_t)(mcpwm_gen_handle_t gena, mcpwm_gen_handle_t genb, mcpwm_cmpr_handle_t cmpa, mcpwm_cmpr_handle_t cmpb); static void mcpwm_gen_action_test_template(uint32_t timer_resolution, uint32_t period, mcpwm_timer_count_mode_t count_mode, - uint32_t cmpa, uint32_t cmpb, int gpioa, int gpiob, set_gen_actions_cb_t set_generator_actions) + uint32_t cmpa, uint32_t cmpb, int gpioa, int gpiob, set_gen_actions_cb_t set_generator_actions, + uint32_t *ret_capa, uint32_t *ret_capb) { mcpwm_timer_config_t timer_config = { .group_id = 0, @@ -305,10 +349,72 @@ static void mcpwm_gen_action_test_template(uint32_t timer_resolution, uint32_t p set_generator_actions(generator_a, generator_b, comparator_a, comparator_b); + // install mcpwm capture timer + mcpwm_cap_timer_handle_t cap_timer = NULL; + uint32_t clk_src_freq_hz; + esp_clk_tree_src_get_freq_hz(MCPWM_CAPTURE_CLK_SRC_DEFAULT, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_freq_hz); + mcpwm_capture_timer_config_t cap_timer_config = { + .clk_src = MCPWM_CAPTURE_CLK_SRC_DEFAULT, + .group_id = 0, + .resolution_hz = clk_src_freq_hz / 2, + }; + TEST_ESP_OK(mcpwm_new_capture_timer(&cap_timer_config, &cap_timer)); + + // install mcpwm capture channel + mcpwm_cap_channel_handle_t cap_channel_a; + mcpwm_cap_channel_handle_t cap_channel_b; + mcpwm_capture_channel_config_t cap_chan_config = { + .gpio_num = gpioa, + .prescale = 1, + .flags.pos_edge = true, + .flags.neg_edge = true, + }; + TEST_ESP_OK(mcpwm_new_capture_channel(cap_timer, &cap_chan_config, &cap_channel_a)); + cap_chan_config.gpio_num = gpiob; + TEST_ESP_OK(mcpwm_new_capture_channel(cap_timer, &cap_chan_config, &cap_channel_b)); + + // install callback for capture channel + mcpwm_capture_event_callbacks_t cbs = { + .on_cap = test_capture_callback, + }; + uint32_t cap_value_a[2] = {0}; + uint32_t cap_value_b[2] = {0}; + TEST_ESP_OK(mcpwm_capture_channel_register_event_callbacks(cap_channel_a, &cbs, cap_value_a)); + TEST_ESP_OK(mcpwm_capture_channel_register_event_callbacks(cap_channel_b, &cbs, cap_value_b)); + + // enable capture channel and timer + TEST_ESP_OK(mcpwm_capture_channel_enable(cap_channel_a)); + TEST_ESP_OK(mcpwm_capture_channel_enable(cap_channel_b)); + TEST_ESP_OK(mcpwm_capture_timer_enable(cap_timer)); + + // start timer and capture timer TEST_ESP_OK(mcpwm_timer_start_stop(timer, MCPWM_TIMER_START_NO_STOP)); + TEST_ESP_OK(mcpwm_capture_timer_start(cap_timer)); vTaskDelay(pdMS_TO_TICKS(100)); TEST_ESP_OK(mcpwm_timer_start_stop(timer, MCPWM_TIMER_STOP_EMPTY)); vTaskDelay(pdMS_TO_TICKS(10)); + TEST_ESP_OK(mcpwm_capture_timer_stop(cap_timer)); + + // calculate the actual capture time + uint32_t clk_src_res; + TEST_ESP_OK(mcpwm_capture_timer_get_resolution(cap_timer, &clk_src_res)); + clk_src_res /= 1000; // convert to kHz + + if (cap_value_a[1] > cap_value_a[0]) { + // generator end with low level, calculate the high level time + *ret_capa = (cap_value_a[1] - cap_value_a[0]) * 1000 / clk_src_res; + } else { + // generator end with high level, calculate the low level time + *ret_capa = (cap_value_a[0] - cap_value_a[1]) * 1000 / clk_src_res; + } + + if (cap_value_b[1] > cap_value_b[0]) { + // generator end with low level, calculate the high level time + *ret_capb = (cap_value_b[1] - cap_value_b[0]) * 1000 / clk_src_res; + } else { + // generator end with high level, calculate the low level time + *ret_capb = (cap_value_b[0] - cap_value_b[1]) * 1000 / clk_src_res; + } TEST_ESP_OK(mcpwm_timer_disable(timer)); TEST_ESP_OK(mcpwm_del_generator(generator_a)); @@ -317,6 +423,12 @@ static void mcpwm_gen_action_test_template(uint32_t timer_resolution, uint32_t p TEST_ESP_OK(mcpwm_del_comparator(comparator_b)); TEST_ESP_OK(mcpwm_del_operator(oper)); TEST_ESP_OK(mcpwm_del_timer(timer)); + TEST_ESP_OK(mcpwm_capture_channel_disable(cap_channel_a)); + TEST_ESP_OK(mcpwm_del_capture_channel(cap_channel_a)); + TEST_ESP_OK(mcpwm_capture_channel_disable(cap_channel_b)); + TEST_ESP_OK(mcpwm_del_capture_channel(cap_channel_b)); + TEST_ESP_OK(mcpwm_capture_timer_disable(cap_timer)); + TEST_ESP_OK(mcpwm_del_capture_timer(cap_timer)); } static void single_edge_active_high(mcpwm_gen_handle_t gena, mcpwm_gen_handle_t genb, mcpwm_cmpr_handle_t cmpa, mcpwm_cmpr_handle_t cmpb) @@ -392,41 +504,55 @@ static void dual_edge_complementary(mcpwm_gen_handle_t gena, mcpwm_gen_handle_t TEST_CASE("mcpwm_generator_action_on_compare_event", "[mcpwm]") { + uint32_t capa, capb; printf("[Asymmetric, SingleEdge, ActiveHigh]\r\n"); // PWMA: high = [1->350], low = [351->499,0] // PWMB: high = [1->200], low = [201->499,0] - mcpwm_gen_action_test_template(1000000, 500, MCPWM_TIMER_COUNT_MODE_UP, 350, 200, TEST_PWMA_GPIO, TEST_PWMB_GPIO, single_edge_active_high); + mcpwm_gen_action_test_template(1000000, 500, MCPWM_TIMER_COUNT_MODE_UP, 350, 200, TEST_PWMA_GPIO, TEST_PWMB_GPIO, single_edge_active_high, &capa, &capb); + TEST_ASSERT_UINT_WITHIN(2, 150, capa); + TEST_ASSERT_UINT_WITHIN(2, 300, capb); printf("[Asymmetric, SingleEdge, ActiveLow]\r\n"); // PWMA: low = [0->300], high = [301->499] // PWMB: low = [0->150], high = [151->499] - mcpwm_gen_action_test_template(1000000, 500, MCPWM_TIMER_COUNT_MODE_UP, 300, 150, TEST_PWMA_GPIO, TEST_PWMB_GPIO, single_edge_active_low); + mcpwm_gen_action_test_template(1000000, 500, MCPWM_TIMER_COUNT_MODE_UP, 300, 150, TEST_PWMA_GPIO, TEST_PWMB_GPIO, single_edge_active_low, &capa, &capb); + TEST_ASSERT_UINT_WITHIN(2, 200, capa); + TEST_ASSERT_UINT_WITHIN(2, 350, capb); printf("[Asymmetric, PulsePlacement]\r\n"); // PWMA: low = [0->200], high = [201->400], low = [401->599] // PWMB: high = [0->599], low = [0->599] - mcpwm_gen_action_test_template(1000000, 600, MCPWM_TIMER_COUNT_MODE_UP, 200, 400, TEST_PWMA_GPIO, TEST_PWMB_GPIO, pulse_placement); + mcpwm_gen_action_test_template(1000000, 600, MCPWM_TIMER_COUNT_MODE_UP, 200, 400, TEST_PWMA_GPIO, TEST_PWMB_GPIO, pulse_placement, &capa, &capb); + TEST_ASSERT_UINT_WITHIN(2, 200, capa); + TEST_ASSERT_UINT_WITHIN(2, 600, capb); printf("[Asymmetric, DualEdge, ActiveLow]\r\n"); // PWMA: low = [0->250], high = [251->599, 600->450], low = [451->1] // PWMB: low = [0->599], low = [600->1] - mcpwm_gen_action_test_template(1000000, 1200, MCPWM_TIMER_COUNT_MODE_UP_DOWN, 250, 450, TEST_PWMA_GPIO, TEST_PWMB_GPIO, dual_edge_active_low_asym); + mcpwm_gen_action_test_template(1000000, 1200, MCPWM_TIMER_COUNT_MODE_UP_DOWN, 250, 450, TEST_PWMA_GPIO, TEST_PWMB_GPIO, dual_edge_active_low_asym, &capa, &capb); + TEST_ASSERT_UINT_WITHIN(2, 500, capa); + TEST_ASSERT_UINT_WITHIN(2, 600, capb); printf("[Symmetric, DualEdge, ActiveLow]\r\n"); // PWMA: low = [0->400], high = [401->599, 600->400], low = [399->1] // PWMB: low = [0->500], high = [501->599, 600->500], low = [499->1] - mcpwm_gen_action_test_template(1000000, 1200, MCPWM_TIMER_COUNT_MODE_UP_DOWN, 400, 500, TEST_PWMA_GPIO, TEST_PWMB_GPIO, dual_edge_active_low_sym); + mcpwm_gen_action_test_template(1000000, 1200, MCPWM_TIMER_COUNT_MODE_UP_DOWN, 400, 500, TEST_PWMA_GPIO, TEST_PWMB_GPIO, dual_edge_active_low_sym, &capa, &capb); + TEST_ASSERT_UINT_WITHIN(2, 400, capa); + TEST_ASSERT_UINT_WITHIN(2, 200, capb); printf("[Symmetric, DualEdge, Complementary]\r\n"); // PWMA: low = [0->350], high = [351->599, 600->350], low = [349->1] // PWMB: low = [0->400], high = [401->599, 600->400], low = [399->1] - mcpwm_gen_action_test_template(1000000, 1200, MCPWM_TIMER_COUNT_MODE_UP_DOWN, 350, 400, TEST_PWMA_GPIO, TEST_PWMB_GPIO, dual_edge_complementary); + mcpwm_gen_action_test_template(1000000, 1200, MCPWM_TIMER_COUNT_MODE_UP_DOWN, 350, 400, TEST_PWMA_GPIO, TEST_PWMB_GPIO, dual_edge_complementary, &capa, &capb); + TEST_ASSERT_UINT_WITHIN(2, 500, capa); + TEST_ASSERT_UINT_WITHIN(2, 400, capb); } typedef void (*set_dead_time_cb_t)(mcpwm_gen_handle_t gena, mcpwm_gen_handle_t genb); static void mcpwm_deadtime_test_template(uint32_t timer_resolution, uint32_t period, uint32_t cmpa, uint32_t cmpb, int gpioa, int gpiob, - set_gen_actions_cb_t set_generator_actions, set_dead_time_cb_t set_dead_time) + set_gen_actions_cb_t set_generator_actions, set_dead_time_cb_t set_dead_time, + uint32_t ret_capa[2], uint32_t ret_capb[2]) { mcpwm_timer_config_t timer_config = { .group_id = 0, @@ -469,10 +595,61 @@ static void mcpwm_deadtime_test_template(uint32_t timer_resolution, uint32_t per set_generator_actions(generator_a, generator_b, comparator_a, comparator_b); set_dead_time(generator_a, generator_b); + // install mcpwm capture timer + mcpwm_cap_timer_handle_t cap_timer = NULL; + uint32_t clk_src_freq_hz; + esp_clk_tree_src_get_freq_hz(MCPWM_CAPTURE_CLK_SRC_DEFAULT, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_freq_hz); + mcpwm_capture_timer_config_t cap_timer_config = { + .clk_src = MCPWM_CAPTURE_CLK_SRC_DEFAULT, + .group_id = 0, + .resolution_hz = clk_src_freq_hz / 2, + }; + TEST_ESP_OK(mcpwm_new_capture_timer(&cap_timer_config, &cap_timer)); + + // install mcpwm capture channel + mcpwm_cap_channel_handle_t cap_channel_a; + mcpwm_cap_channel_handle_t cap_channel_b; + mcpwm_capture_channel_config_t cap_chan_config = { + .gpio_num = gpioa, + .prescale = 1, + .flags.pos_edge = true, + .flags.neg_edge = true, + }; + TEST_ESP_OK(mcpwm_new_capture_channel(cap_timer, &cap_chan_config, &cap_channel_a)); + cap_chan_config.gpio_num = gpiob; + TEST_ESP_OK(mcpwm_new_capture_channel(cap_timer, &cap_chan_config, &cap_channel_b)); + + // install callback for capture channel + mcpwm_capture_event_callbacks_t cbs = { + .on_cap = test_capture_callback, + }; + uint32_t cap_value_a[2] = {0}; + uint32_t cap_value_b[2] = {0}; + TEST_ESP_OK(mcpwm_capture_channel_register_event_callbacks(cap_channel_a, &cbs, cap_value_a)); + TEST_ESP_OK(mcpwm_capture_channel_register_event_callbacks(cap_channel_b, &cbs, cap_value_b)); + + // enable capture channel and timer + TEST_ESP_OK(mcpwm_capture_channel_enable(cap_channel_a)); + TEST_ESP_OK(mcpwm_capture_channel_enable(cap_channel_b)); + TEST_ESP_OK(mcpwm_capture_timer_enable(cap_timer)); + + // start timer and capture timer TEST_ESP_OK(mcpwm_timer_start_stop(timer, MCPWM_TIMER_START_NO_STOP)); + TEST_ESP_OK(mcpwm_capture_timer_start(cap_timer)); vTaskDelay(pdMS_TO_TICKS(100)); - TEST_ESP_OK(mcpwm_timer_start_stop(timer, MCPWM_TIMER_STOP_EMPTY)); + TEST_ESP_OK(mcpwm_timer_start_stop(timer, MCPWM_TIMER_STOP_FULL)); vTaskDelay(pdMS_TO_TICKS(10)); + TEST_ESP_OK(mcpwm_capture_timer_stop(cap_timer)); + + // calculate the actual capture time + uint32_t clk_src_res; + TEST_ESP_OK(mcpwm_capture_timer_get_resolution(cap_timer, &clk_src_res)); + clk_src_res /= 1000; // convert to kHz + + ret_capa[0] = cap_value_a[0] * 1000 / clk_src_res; + ret_capa[1] = cap_value_a[1] * 1000 / clk_src_res; + ret_capb[0] = cap_value_b[0] * 1000 / clk_src_res; + ret_capb[1] = cap_value_b[1] * 1000 / clk_src_res; TEST_ESP_OK(mcpwm_timer_disable(timer)); TEST_ESP_OK(mcpwm_del_generator(generator_a)); @@ -481,6 +658,12 @@ static void mcpwm_deadtime_test_template(uint32_t timer_resolution, uint32_t per TEST_ESP_OK(mcpwm_del_comparator(comparator_b)); TEST_ESP_OK(mcpwm_del_operator(oper)); TEST_ESP_OK(mcpwm_del_timer(timer)); + TEST_ESP_OK(mcpwm_capture_channel_disable(cap_channel_a)); + TEST_ESP_OK(mcpwm_del_capture_channel(cap_channel_a)); + TEST_ESP_OK(mcpwm_capture_channel_disable(cap_channel_b)); + TEST_ESP_OK(mcpwm_del_capture_channel(cap_channel_b)); + TEST_ESP_OK(mcpwm_capture_timer_disable(cap_timer)); + TEST_ESP_OK(mcpwm_del_capture_timer(cap_timer)); } static void ahc_set_generator_actions(mcpwm_gen_handle_t gena, mcpwm_gen_handle_t genb, mcpwm_cmpr_handle_t cmpa, mcpwm_cmpr_handle_t cmpb) @@ -663,34 +846,58 @@ static void invalid_reda_redb_set_dead_time(mcpwm_gen_handle_t gena, mcpwm_gen_h TEST_CASE("mcpwm_generator_deadtime_classical_configuration", "[mcpwm]") { + uint32_t capa[2], capb[2]; printf("Active High Complementary\r\n"); - mcpwm_deadtime_test_template(1000000, 600, 200, 400, TEST_PWMA_GPIO, TEST_PWMB_GPIO, ahc_set_generator_actions, ahc_set_dead_time); + mcpwm_deadtime_test_template(1000000, 600, 200, 400, TEST_PWMA_GPIO, TEST_PWMB_GPIO, ahc_set_generator_actions, ahc_set_dead_time, capa, capb); + TEST_ASSERT_UINT_WITHIN(2, 50, capa[0] - capb[1]); + TEST_ASSERT_UINT_WITHIN(2, 100, capb[0] - capa[1]); printf("Active Low Complementary\r\n"); - mcpwm_deadtime_test_template(1000000, 600, 200, 400, TEST_PWMA_GPIO, TEST_PWMB_GPIO, alc_set_generator_actions, alc_set_dead_time); + mcpwm_deadtime_test_template(1000000, 600, 200, 400, TEST_PWMA_GPIO, TEST_PWMB_GPIO, alc_set_generator_actions, alc_set_dead_time, capa, capb); + TEST_ASSERT_UINT_WITHIN(2, 50, capa[1] - capb[0]); + TEST_ASSERT_UINT_WITHIN(2, 100, capb[1] - capa[0]); printf("Active High\r\n"); - mcpwm_deadtime_test_template(1000000, 600, 200, 400, TEST_PWMA_GPIO, TEST_PWMB_GPIO, ah_set_generator_actions, ah_set_dead_time); + mcpwm_deadtime_test_template(1000000, 600, 200, 400, TEST_PWMA_GPIO, TEST_PWMB_GPIO, ah_set_generator_actions, ah_set_dead_time, capa, capb); + TEST_ASSERT_UINT_WITHIN(2, 50, capa[0] - capb[0]); + TEST_ASSERT_UINT_WITHIN(2, 100, capb[1] - capa[1]); printf("Active Low\r\n"); - mcpwm_deadtime_test_template(1000000, 600, 200, 400, TEST_PWMA_GPIO, TEST_PWMB_GPIO, al_set_generator_actions, al_set_dead_time); + mcpwm_deadtime_test_template(1000000, 600, 200, 400, TEST_PWMA_GPIO, TEST_PWMB_GPIO, al_set_generator_actions, al_set_dead_time, capa, capb); + TEST_ASSERT_UINT_WITHIN(2, 50, capa[1] - capb[1]); + TEST_ASSERT_UINT_WITHIN(2, 100, capb[0] - capa[0]); printf("RED on A, Bypass B\r\n"); - mcpwm_deadtime_test_template(1000000, 500, 350, 350, TEST_PWMA_GPIO, TEST_PWMB_GPIO, reda_only_set_generator_actions, reda_only_set_dead_time); + mcpwm_deadtime_test_template(1000000, 500, 350, 350, TEST_PWMA_GPIO, TEST_PWMB_GPIO, reda_only_set_generator_actions, reda_only_set_dead_time, capa, capb); + TEST_ASSERT_UINT_WITHIN(2, 50, capa[0] - capb[0]); + TEST_ASSERT_UINT_WITHIN(2, 0, capb[1] - capa[1]); printf("Bypass A, FED on B\r\n"); - mcpwm_deadtime_test_template(1000000, 500, 350, 350, TEST_PWMA_GPIO, TEST_PWMB_GPIO, fedb_only_set_generator_actions, fedb_only_set_dead_time); + mcpwm_deadtime_test_template(1000000, 500, 350, 350, TEST_PWMA_GPIO, TEST_PWMB_GPIO, fedb_only_set_generator_actions, fedb_only_set_dead_time, capa, capb); + TEST_ASSERT_UINT_WITHIN(2, 50, capb[1] - capa[1]); + TEST_ASSERT_UINT_WITHIN(2, 0, capb[0] - capa[0]); printf("Bypass A, RED + FED on B\r\n"); - mcpwm_deadtime_test_template(1000000, 500, 350, 350, TEST_PWMA_GPIO, TEST_PWMB_GPIO, redfedb_only_set_generator_actions, redfedb_only_set_dead_time); + mcpwm_deadtime_test_template(1000000, 500, 350, 350, TEST_PWMA_GPIO, TEST_PWMB_GPIO, redfedb_only_set_generator_actions, redfedb_only_set_dead_time, capa, capb); + TEST_ASSERT_UINT_WITHIN(2, 50, capb[0] - capa[0]); + TEST_ASSERT_UINT_WITHIN(2, 50, capb[1] - capa[1]); printf("Can't apply one delay module to multiple generators\r\n"); - mcpwm_deadtime_test_template(1000000, 500, 350, 350, TEST_PWMA_GPIO, TEST_PWMB_GPIO, redfedb_only_set_generator_actions, invalid_reda_redb_set_dead_time); + mcpwm_deadtime_test_template(1000000, 500, 350, 350, TEST_PWMA_GPIO, TEST_PWMB_GPIO, redfedb_only_set_generator_actions, invalid_reda_redb_set_dead_time, capa, capb); + TEST_ASSERT_UINT_WITHIN(2, 0, capa[0] - capb[0]); + TEST_ASSERT_UINT_WITHIN(2, 0, capa[1] - capb[1]); } TEST_CASE("mcpwm_duty_empty_full", "[mcpwm]") { const int gen_gpio_num = TEST_PWMA_GPIO; + printf("init a gpio to read generator output\r\n"); + gpio_config_t gen_gpio_conf = { + .mode = GPIO_MODE_INPUT, + .pin_bit_mask = BIT(gen_gpio_num), + }; + TEST_ESP_OK(gpio_config(&gen_gpio_conf)); + mcpwm_timer_handle_t timer; mcpwm_oper_handle_t oper; mcpwm_cmpr_handle_t comparator; @@ -722,7 +929,6 @@ TEST_CASE("mcpwm_duty_empty_full", "[mcpwm]") printf("install MCPWM generator\r\n"); mcpwm_generator_config_t gen_config = { .gen_gpio_num = gen_gpio_num, - .flags.io_loop_back = true, // we want to read the output level as well }; TEST_ESP_OK(mcpwm_new_generator(oper, &gen_config, &gen)); @@ -763,12 +969,30 @@ TEST_CASE("mcpwm_duty_empty_full", "[mcpwm]") TEST_ESP_OK(mcpwm_del_comparator(comparator)); TEST_ESP_OK(mcpwm_del_operator(oper)); TEST_ESP_OK(mcpwm_del_timer(timer)); + TEST_ESP_OK(gpio_reset_pin(gen_gpio_num)); } TEST_CASE("mcpwm_generator_action_on_fault_trigger_event", "[mcpwm]") { const int generator_gpio = TEST_PWMA_GPIO; const int fault_gpio_num[3] = {TEST_FAULT_GPIO0, TEST_FAULT_GPIO1, TEST_FAULT_GPIO2}; + + printf("init a gpio to read generator output and simulate fault signal\r\n"); + gpio_config_t generator_gpio_conf = { + .mode = GPIO_MODE_INPUT, + .pin_bit_mask = BIT(generator_gpio), + }; + TEST_ESP_OK(gpio_config(&generator_gpio_conf)); + + gpio_config_t fault_gpio_conf = { + .mode = GPIO_MODE_OUTPUT, + .pin_bit_mask = 0, + }; + for (int i = 0; i < 3; i++) { + fault_gpio_conf.pin_bit_mask |= BIT(fault_gpio_num[i]); + } + TEST_ESP_OK(gpio_config(&fault_gpio_conf)); + printf("create timer and operator\r\n"); mcpwm_timer_config_t timer_config = { .group_id = 0, @@ -796,7 +1020,6 @@ TEST_CASE("mcpwm_generator_action_on_fault_trigger_event", "[mcpwm]") .flags.active_level = 1, .flags.pull_down = 1, .flags.pull_up = 0, - .flags.io_loop_back = 1, // so that we can write the GPIO value by GPIO driver }; for (int i = 0 ; i < 3; i++) { gpio_trigger_config.gpio_num = fault_gpio_num[i]; @@ -806,7 +1029,6 @@ TEST_CASE("mcpwm_generator_action_on_fault_trigger_event", "[mcpwm]") printf("create generator\r\n"); mcpwm_generator_config_t gen_config = { .gen_gpio_num = generator_gpio, - .flags.io_loop_back = 1, // so that we can read the GPIO value by GPIO driver }; mcpwm_gen_handle_t gen = NULL; TEST_ESP_OK(mcpwm_new_generator(oper, &gen_config, &gen)); @@ -839,11 +1061,22 @@ TEST_CASE("mcpwm_generator_action_on_fault_trigger_event", "[mcpwm]") TEST_ESP_OK(mcpwm_del_generator(gen)); TEST_ESP_OK(mcpwm_del_operator(oper)); TEST_ESP_OK(mcpwm_del_timer(timer)); + TEST_ESP_OK(gpio_reset_pin(generator_gpio)); + for (int i = 0; i < 3; i++) { + TEST_ESP_OK(gpio_reset_pin(fault_gpio_num[i])); + } } TEST_CASE("mcpwm_generator_action_on_soft_sync_trigger_event", "[mcpwm]") { const int generator_gpio = TEST_PWMA_GPIO; + printf("init a gpio to read generator output\r\n"); + gpio_config_t generator_gpio_conf = { + .mode = GPIO_MODE_INPUT, + .pin_bit_mask = BIT(generator_gpio), + }; + TEST_ESP_OK(gpio_config(&generator_gpio_conf)); + printf("create timer and operator\r\n"); mcpwm_timer_config_t timer_config = { .group_id = 0, @@ -879,7 +1112,6 @@ TEST_CASE("mcpwm_generator_action_on_soft_sync_trigger_event", "[mcpwm]") printf("create generator\r\n"); mcpwm_generator_config_t gen_config = { .gen_gpio_num = generator_gpio, - .flags.io_loop_back = 1, // so that we can read the GPIO value by GPIO driver }; mcpwm_gen_handle_t gen = NULL; TEST_ESP_OK(mcpwm_new_generator(oper, &gen_config, &gen)); @@ -905,11 +1137,19 @@ TEST_CASE("mcpwm_generator_action_on_soft_sync_trigger_event", "[mcpwm]") TEST_ESP_OK(mcpwm_del_generator(gen)); TEST_ESP_OK(mcpwm_del_operator(oper)); TEST_ESP_OK(mcpwm_del_timer(timer)); + TEST_ESP_OK(gpio_reset_pin(generator_gpio)); } TEST_CASE("mcpwm_generator_action_on_timer_sync_trigger_event", "[mcpwm]") { const int generator_gpio = TEST_PWMA_GPIO; + printf("init a gpio to read generator output\r\n"); + gpio_config_t generator_gpio_conf = { + .mode = GPIO_MODE_INPUT, + .pin_bit_mask = BIT(generator_gpio), + }; + TEST_ESP_OK(gpio_config(&generator_gpio_conf)); + printf("create timer and operator\r\n"); mcpwm_timer_config_t timer_config = { .group_id = 0, @@ -948,7 +1188,6 @@ TEST_CASE("mcpwm_generator_action_on_timer_sync_trigger_event", "[mcpwm]") printf("create generator\r\n"); mcpwm_generator_config_t gen_config = { .gen_gpio_num = generator_gpio, - .flags.io_loop_back = 1, // so that we can read the GPIO value by GPIO driver }; mcpwm_gen_handle_t gen = NULL; TEST_ESP_OK(mcpwm_new_generator(oper, &gen_config, &gen)); @@ -970,11 +1209,25 @@ TEST_CASE("mcpwm_generator_action_on_timer_sync_trigger_event", "[mcpwm]") TEST_ESP_OK(mcpwm_del_generator(gen)); TEST_ESP_OK(mcpwm_del_operator(oper)); TEST_ESP_OK(mcpwm_del_timer(timer)); + TEST_ESP_OK(gpio_reset_pin(generator_gpio)); } TEST_CASE("mcpwm_generator_action_on_gpio_sync_trigger_event", "[mcpwm]") { const int generator_gpio = TEST_PWMA_GPIO; + const int sync_gpio = TEST_SYNC_GPIO; + printf("init a gpio to read generator output and simulate sync signal\r\n"); + gpio_config_t generator_gpio_conf = { + .mode = GPIO_MODE_INPUT, + .pin_bit_mask = BIT(generator_gpio), + }; + TEST_ESP_OK(gpio_config(&generator_gpio_conf)); + gpio_config_t sync_gpio_conf = { + .mode = GPIO_MODE_OUTPUT, + .pin_bit_mask = BIT(sync_gpio), + }; + TEST_ESP_OK(gpio_config(&sync_gpio_conf)); + printf("create timer and operator\r\n"); mcpwm_timer_config_t timer_config = { .group_id = 0, @@ -999,14 +1252,13 @@ TEST_CASE("mcpwm_generator_action_on_gpio_sync_trigger_event", "[mcpwm]") mcpwm_sync_handle_t gpio_sync = NULL; mcpwm_gpio_sync_src_config_t gpio_sync_config = { .group_id = 0, - .gpio_num = TEST_SYNC_GPIO, - .flags.io_loop_back = true, // so that we can use gpio driver to simulate the sync signal + .gpio_num = sync_gpio, .flags.pull_down = true, // internally pull down }; TEST_ESP_OK(mcpwm_new_gpio_sync_src(&gpio_sync_config, &gpio_sync)); // put the GPIO into initial state - gpio_set_level(gpio_sync_config.gpio_num, 0); + gpio_set_level(sync_gpio, 0); mcpwm_timer_sync_phase_config_t sync_phase_config = { .count_value = 0, @@ -1018,7 +1270,6 @@ TEST_CASE("mcpwm_generator_action_on_gpio_sync_trigger_event", "[mcpwm]") printf("create generator\r\n"); mcpwm_generator_config_t gen_config = { .gen_gpio_num = generator_gpio, - .flags.io_loop_back = 1, // so that we can read the GPIO value by GPIO driver }; mcpwm_gen_handle_t gen = NULL; TEST_ESP_OK(mcpwm_new_generator(oper, &gen_config, &gen)); @@ -1028,8 +1279,8 @@ TEST_CASE("mcpwm_generator_action_on_gpio_sync_trigger_event", "[mcpwm]") MCPWM_GEN_SYNC_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, gpio_sync, MCPWM_GEN_ACTION_HIGH))); TEST_ASSERT_EQUAL(0, gpio_get_level(generator_gpio)); - gpio_set_level(gpio_sync_config.gpio_num, 1); - gpio_set_level(gpio_sync_config.gpio_num, 0); + gpio_set_level(sync_gpio, 1); + gpio_set_level(sync_gpio, 0); TEST_ASSERT_EQUAL(1, gpio_get_level(generator_gpio)); vTaskDelay(pdMS_TO_TICKS(10)); @@ -1038,4 +1289,6 @@ TEST_CASE("mcpwm_generator_action_on_gpio_sync_trigger_event", "[mcpwm]") TEST_ESP_OK(mcpwm_del_generator(gen)); TEST_ESP_OK(mcpwm_del_operator(oper)); TEST_ESP_OK(mcpwm_del_timer(timer)); + TEST_ESP_OK(gpio_reset_pin(generator_gpio)); + TEST_ESP_OK(gpio_reset_pin(sync_gpio)); } diff --git a/components/esp_driver_mcpwm/test_apps/mcpwm/main/test_mcpwm_iram.c b/components/esp_driver_mcpwm/test_apps/mcpwm/main/test_mcpwm_iram.c index fa53482c569..24744463bab 100644 --- a/components/esp_driver_mcpwm/test_apps/mcpwm/main/test_mcpwm_iram.c +++ b/components/esp_driver_mcpwm/test_apps/mcpwm/main/test_mcpwm_iram.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -46,6 +46,13 @@ TEST_CASE("mcpwm_capture_iram_safe", "[mcpwm]") TEST_ESP_OK(mcpwm_new_capture_timer(&cap_timer_config, &cap_timer)); const int cap_gpio = TEST_CAP_GPIO; + printf("init a gpio to simulate the external capture signal\r\n"); + gpio_config_t cap_gpio_conf = { + .mode = GPIO_MODE_OUTPUT, + .pin_bit_mask = BIT(cap_gpio), + }; + TEST_ESP_OK(gpio_config(&cap_gpio_conf)); + // put the GPIO into a preset state gpio_set_level(cap_gpio, 0); @@ -56,7 +63,6 @@ TEST_CASE("mcpwm_capture_iram_safe", "[mcpwm]") .prescale = 1, .flags.pos_edge = true, .flags.neg_edge = true, - .flags.io_loop_back = true, // so we can use GPIO functions to simulate the external capture signal .flags.pull_up = true, }; TEST_ESP_OK(mcpwm_new_capture_channel(cap_timer, &cap_chan_config, &pps_channel)); @@ -89,6 +95,7 @@ TEST_CASE("mcpwm_capture_iram_safe", "[mcpwm]") TEST_ESP_OK(mcpwm_del_capture_channel(pps_channel)); TEST_ESP_OK(mcpwm_capture_timer_disable(cap_timer)); TEST_ESP_OK(mcpwm_del_capture_timer(cap_timer)); + TEST_ESP_OK(gpio_reset_pin(cap_gpio)); } static bool IRAM_ATTR test_compare_on_reach(mcpwm_cmpr_handle_t cmpr, const mcpwm_compare_event_data_t *ev_data, void *user_data) diff --git a/components/esp_driver_mcpwm/test_apps/mcpwm/main/test_mcpwm_oper.c b/components/esp_driver_mcpwm/test_apps/mcpwm/main/test_mcpwm_oper.c index 76f977a268c..ce2523d7fbe 100644 --- a/components/esp_driver_mcpwm/test_apps/mcpwm/main/test_mcpwm_oper.c +++ b/components/esp_driver_mcpwm/test_apps/mcpwm/main/test_mcpwm_oper.c @@ -121,6 +121,22 @@ static bool IRAM_ATTR test_ost_brake_on_gpio_fault_callback(mcpwm_oper_handle_t TEST_CASE("mcpwm_operator_brake_on_gpio_fault", "[mcpwm]") { + const int cbc_fault_gpio = TEST_FAULT_GPIO1; + const int ost_fault_gpio = TEST_FAULT_GPIO2; + const int gen_a_gpio = TEST_PWMA_GPIO; + const int gen_b_gpio = TEST_PWMB_GPIO; + printf("init gpios to read generator output and simulate fault signal\r\n"); + gpio_config_t fault_gpio_conf = { + .mode = GPIO_MODE_OUTPUT, + .pin_bit_mask = BIT(cbc_fault_gpio) | BIT(ost_fault_gpio), + }; + TEST_ESP_OK(gpio_config(&fault_gpio_conf)); + gpio_config_t gen_gpio_conf = { + .mode = GPIO_MODE_INPUT, + .pin_bit_mask = BIT(gen_a_gpio) | BIT(gen_b_gpio), + }; + TEST_ESP_OK(gpio_config(&gen_gpio_conf)); + printf("install timer\r\n"); mcpwm_timer_config_t timer_config = { .clk_src = MCPWM_TIMER_CLK_SRC_DEFAULT, @@ -151,13 +167,10 @@ TEST_CASE("mcpwm_operator_brake_on_gpio_fault", "[mcpwm]") mcpwm_gpio_fault_config_t gpio_fault_config = { .group_id = 0, .flags.active_level = 1, - .flags.io_loop_back = true, .flags.pull_down = true, }; mcpwm_fault_handle_t gpio_cbc_fault = NULL; mcpwm_fault_handle_t gpio_ost_fault = NULL; - const int cbc_fault_gpio = TEST_FAULT_GPIO1; - const int ost_fault_gpio = TEST_FAULT_GPIO2; gpio_fault_config.gpio_num = cbc_fault_gpio; TEST_ESP_OK(mcpwm_new_gpio_fault(&gpio_fault_config, &gpio_cbc_fault)); @@ -180,14 +193,12 @@ TEST_CASE("mcpwm_operator_brake_on_gpio_fault", "[mcpwm]") TEST_ESP_OK(mcpwm_operator_set_brake_on_fault(oper, &brake_config)); printf("create generators\r\n"); - const int gen_a_gpio = TEST_PWMA_GPIO; - const int gen_b_gpio = TEST_PWMB_GPIO; + mcpwm_gen_handle_t gen_a = NULL; mcpwm_gen_handle_t gen_b = NULL; mcpwm_generator_config_t generator_config = { - .flags.io_loop_back = true, + .gen_gpio_num = gen_a_gpio, }; - generator_config.gen_gpio_num = gen_a_gpio; TEST_ESP_OK(mcpwm_new_generator(oper, &generator_config, &gen_a)); generator_config.gen_gpio_num = gen_b_gpio; TEST_ESP_OK(mcpwm_new_generator(oper, &generator_config, &gen_b)); @@ -249,10 +260,23 @@ TEST_CASE("mcpwm_operator_brake_on_gpio_fault", "[mcpwm]") TEST_ESP_OK(mcpwm_del_generator(gen_b)); TEST_ESP_OK(mcpwm_del_operator(oper)); TEST_ESP_OK(mcpwm_del_timer(timer)); + TEST_ESP_OK(gpio_reset_pin(cbc_fault_gpio)); + TEST_ESP_OK(gpio_reset_pin(ost_fault_gpio)); + TEST_ESP_OK(gpio_reset_pin(gen_a_gpio)); + TEST_ESP_OK(gpio_reset_pin(gen_b_gpio)); } TEST_CASE("mcpwm_operator_brake_on_soft_fault", "[mcpwm]") { + const int gen_a_gpio = TEST_PWMA_GPIO; + const int gen_b_gpio = TEST_PWMB_GPIO; + printf("init gpios to read generator output\r\n"); + gpio_config_t gen_gpio_conf = { + .mode = GPIO_MODE_INPUT, + .pin_bit_mask = BIT(gen_a_gpio) | BIT(gen_b_gpio), + }; + TEST_ESP_OK(gpio_config(&gen_gpio_conf)); + printf("install timer\r\n"); mcpwm_timer_config_t timer_config = { .clk_src = MCPWM_TIMER_CLK_SRC_DEFAULT, @@ -286,14 +310,11 @@ TEST_CASE("mcpwm_operator_brake_on_soft_fault", "[mcpwm]") TEST_ESP_OK(mcpwm_operator_set_brake_on_fault(oper, &brake_config)); printf("create generators\r\n"); - const int gen_a_gpio = TEST_PWMA_GPIO; - const int gen_b_gpio = TEST_PWMB_GPIO; mcpwm_gen_handle_t gen_a = NULL; mcpwm_gen_handle_t gen_b = NULL; mcpwm_generator_config_t generator_config = { - .flags.io_loop_back = true, + .gen_gpio_num = gen_a_gpio, }; - generator_config.gen_gpio_num = gen_a_gpio; TEST_ESP_OK(mcpwm_new_generator(oper, &generator_config, &gen_a)); generator_config.gen_gpio_num = gen_b_gpio; TEST_ESP_OK(mcpwm_new_generator(oper, &generator_config, &gen_b)); @@ -360,4 +381,6 @@ TEST_CASE("mcpwm_operator_brake_on_soft_fault", "[mcpwm]") TEST_ESP_OK(mcpwm_del_generator(gen_b)); TEST_ESP_OK(mcpwm_del_operator(oper)); TEST_ESP_OK(mcpwm_del_timer(timer)); + TEST_ESP_OK(gpio_reset_pin(gen_a_gpio)); + TEST_ESP_OK(gpio_reset_pin(gen_b_gpio)); } diff --git a/components/esp_driver_mcpwm/test_apps/mcpwm/main/test_mcpwm_sync.c b/components/esp_driver_mcpwm/test_apps/mcpwm/main/test_mcpwm_sync.c index 7fb5328cfad..d8bc8e4aaf7 100644 --- a/components/esp_driver_mcpwm/test_apps/mcpwm/main/test_mcpwm_sync.c +++ b/components/esp_driver_mcpwm/test_apps/mcpwm/main/test_mcpwm_sync.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -106,6 +106,13 @@ TEST_CASE("mcpwm_gpio_sync_timer_phase_lock", "[mcpwm]") // | // v // timer0-->timer1-->timer2 + const int gpio_num = TEST_SYNC_GPIO; + gpio_config_t sync_gpio_conf = { + .mode = GPIO_MODE_OUTPUT, + .pin_bit_mask = BIT(gpio_num), + }; + TEST_ESP_OK(gpio_config(&sync_gpio_conf)); + mcpwm_timer_config_t timer_config = { .clk_src = MCPWM_TIMER_CLK_SRC_DEFAULT, .group_id = 0, @@ -127,11 +134,9 @@ TEST_CASE("mcpwm_gpio_sync_timer_phase_lock", "[mcpwm]") .direction = MCPWM_TIMER_DIRECTION_UP, }; mcpwm_sync_handle_t gpio_sync_src; - const int gpio_num = TEST_SYNC_GPIO; mcpwm_gpio_sync_src_config_t gpio_sync_config = { .group_id = 0, .gpio_num = gpio_num, - .flags.io_loop_back = true, // so that we can use gpio driver to simulate the sync signal .flags.pull_down = true, // internally pull down }; TEST_ESP_OK(mcpwm_new_gpio_sync_src(&gpio_sync_config, &gpio_sync_src)); @@ -154,6 +159,7 @@ TEST_CASE("mcpwm_gpio_sync_timer_phase_lock", "[mcpwm]") TEST_ESP_OK(mcpwm_del_sync_src(sync_srcs[i])); TEST_ESP_OK(mcpwm_del_timer(timers[i])); } + TEST_ESP_OK(gpio_reset_pin(gpio_num)); } TEST_CASE("mcpwm_timer_sync_timer_phase_lock", "[mcpwm]") diff --git a/docs/en/api-reference/peripherals/mcpwm.rst b/docs/en/api-reference/peripherals/mcpwm.rst index 3a6de1476e0..a7d1ae5ba42 100644 --- a/docs/en/api-reference/peripherals/mcpwm.rst +++ b/docs/en/api-reference/peripherals/mcpwm.rst @@ -122,8 +122,6 @@ You can allocate a MCPWM generator object by calling the :cpp:func:`mcpwm_new_ge - :cpp:member:`mcpwm_generator_config_t::gen_gpio_num` sets the GPIO number used by the generator. - :cpp:member:`mcpwm_generator_config_t::invert_pwm` sets whether to invert the PWM signal. -- :cpp:member:`mcpwm_generator_config_t::io_loop_back` sets whether to enable the Loop-back mode. It is for debugging purposes only. It enables both the GPIO's input and output ability through the GPIO matrix peripheral. -- :cpp:member:`mcpwm_generator_config_t::io_od_mode` configures the PWM GPIO as open-drain output. - :cpp:member:`mcpwm_generator_config_t::pull_up` and :cpp:member:`mcpwm_generator_config_t::pull_down` controls whether to enable the internal pull-up and pull-down resistors accordingly. The :cpp:func:`mcpwm_new_generator` will return a pointer to the allocated generator object if the allocation succeeds. Otherwise, it will return an error code. Specifically, when there are no more free generators in the MCPWM operator, this function will return the :c:macro:`ESP_ERR_NOT_FOUND` error. [1]_ @@ -142,7 +140,6 @@ To allocate a GPIO fault object, you can call the :cpp:func:`mcpwm_new_gpio_faul - :cpp:member:`mcpwm_gpio_fault_config_t::gpio_num` sets the GPIO number used by the fault. - :cpp:member:`mcpwm_gpio_fault_config_t::active_level` sets the active level of the fault signal. - :cpp:member:`mcpwm_gpio_fault_config_t::pull_up` and :cpp:member:`mcpwm_gpio_fault_config_t::pull_down` set whether to pull up and/or pull down the GPIO internally. -- :cpp:member:`mcpwm_gpio_fault_config_t::io_loop_back` sets whether to enable the loopback mode. It is for debugging purposes only. It enables both the GPIO's input and output ability through the GPIO matrix peripheral. The :cpp:func:`mcpwm_new_gpio_fault` will return a pointer to the allocated fault object if the allocation succeeds. Otherwise, it will return an error code. Specifically, when there are no more free GPIO faults in the MCPWM group, this function will return the :c:macro:`ESP_ERR_NOT_FOUND` error. [1]_ @@ -163,7 +160,6 @@ To allocate a GPIO sync source, you can call the :cpp:func:`mcpwm_new_gpio_sync_ - :cpp:member:`mcpwm_gpio_sync_src_config_t::gpio_num` sets the GPIO number used by the sync source. - :cpp:member:`mcpwm_gpio_sync_src_config_t::active_neg` sets whether the sync signal is active on falling edges. - :cpp:member:`mcpwm_gpio_sync_src_config_t::pull_up` and :cpp:member:`mcpwm_gpio_sync_src_config_t::pull_down` set whether to pull up and/or pull down the GPIO internally. -- :cpp:member:`mcpwm_gpio_sync_src_config_t::io_loop_back` sets whether to enable the Loop-back mode. It is for debugging purposes only. It enables both the GPIO's input and output ability through the GPIO matrix peripheral. The :cpp:func:`mcpwm_new_gpio_sync_src` will return a pointer to the allocated sync source object if the allocation succeeds. Otherwise, it will return an error code. Specifically, when there are no more free GPIO sync sources in the MCPWM group, this function will return the :c:macro:`ESP_ERR_NOT_FOUND` error. [1]_ @@ -207,8 +203,6 @@ Next, to allocate a capture channel, you can call the :cpp:func:`mcpwm_new_captu - :cpp:member:`mcpwm_capture_channel_config_t::extra_capture_channel_flags::pos_edge` and :cpp:member:`mcpwm_capture_channel_config_t::extra_capture_channel_flags::neg_edge` set whether to capture on the positive and/or falling edge of the input signal. - :cpp:member:`mcpwm_capture_channel_config_t::extra_capture_channel_flags::pull_up` and :cpp:member:`mcpwm_capture_channel_config_t::extra_capture_channel_flags::pull_down` set whether to pull up and/or pull down the GPIO internally. - :cpp:member:`mcpwm_capture_channel_config_t::extra_capture_channel_flags::invert_cap_signal` sets whether to invert the capture signal. -- :cpp:member:`mcpwm_capture_channel_config_t::extra_capture_channel_flags::io_loop_back` sets whether to enable the Loop-back mode. It is for debugging purposes only. It enables both the GPIO's input and output ability through the GPIO matrix peripheral. -- :cpp:member:`mcpwm_capture_channel_config_t::extra_capture_channel_flags::keep_io_conf_at_exit` sets whether to keep the GPIO configuration when the capture channel is deleted. The :cpp:func:`mcpwm_new_capture_channel` will return a pointer to the allocated capture channel object if the allocation succeeds. Otherwise, it will return an error code. Specifically, when there is no free capture channel left in the capture timer, this function will return the :c:macro:`ESP_ERR_NOT_FOUND` error. diff --git a/docs/zh_CN/api-reference/peripherals/mcpwm.rst b/docs/zh_CN/api-reference/peripherals/mcpwm.rst index f90ba9cd429..9aaaa22bb46 100644 --- a/docs/zh_CN/api-reference/peripherals/mcpwm.rst +++ b/docs/zh_CN/api-reference/peripherals/mcpwm.rst @@ -122,8 +122,6 @@ MCPWM 生成器 - :cpp:member:`mcpwm_generator_config_t::gen_gpio_num` 设置生成器使用的 GPIO 编号。 - :cpp:member:`mcpwm_generator_config_t::invert_pwm` 设置是否反相 PWM 信号。 -- :cpp:member:`mcpwm_generator_config_t::io_loop_back` 设置是否启用回环模式。该模式仅用于调试，使用 GPIO 交换矩阵外设同时启用 GPIO 输入和输出。 -- :cpp:member:`mcpwm_generator_config_t::io_od_mode` 设置是否启用漏极开路输出。 - :cpp:member:`mcpwm_generator_config_t::pull_up` 和 :cpp:member:`mcpwm_generator_config_t::pull_down` 用来设置是否启用内部上下拉电阻。 分配成功后，:cpp:func:`mcpwm_new_generator` 将返回一个指向已分配生成器的指针。否则，函数将返回错误代码。具体来说，当 MCPWM 操作器中没有空闲生成器时，将返回 :c:macro:`ESP_ERR_NOT_FOUND` 错误。[1]_ @@ -142,7 +140,6 @@ MCPWM 故障分为两种类型：来自 GPIO 的故障信号和软件故障。 - :cpp:member:`mcpwm_gpio_fault_config_t::gpio_num` 设置故障所使用的 GPIO 编号。 - :cpp:member:`mcpwm_gpio_fault_config_t::active_level` 设置故障信号的有效电平。 - :cpp:member:`mcpwm_gpio_fault_config_t::pull_up` 和 :cpp:member:`mcpwm_gpio_fault_config_t::pull_down` 设置是否在内部拉高和/或拉低 GPIO。 -- :cpp:member:`mcpwm_gpio_fault_config_t::io_loop_back` 设置是否启用回环模式。该模式仅用于调试，使用 GPIO 交换矩阵外设同时启用 GPIO 输入和输出。 分配成功后，:cpp:func:`mcpwm_new_gpio_fault` 将返回一个指向已分配故障的指针。否则，函数将返回错误代码。具体来说，当指定 MCPWM 组中没有空闲 GPIO 故障时，将返回 :c:macro:`ESP_ERR_NOT_FOUND` 错误。[1]_ @@ -163,7 +160,6 @@ MCPWM 同步源 - :cpp:member:`mcpwm_gpio_sync_src_config_t::gpio_num` 设置同步源使用的 GPIO 编号。 - :cpp:member:`mcpwm_gpio_sync_src_config_t::active_neg` 设置同步信号在下降沿是否有效。 - :cpp:member:`mcpwm_gpio_sync_src_config_t::pull_up` 和 :cpp:member:`mcpwm_gpio_sync_src_config_t::pull_down` 设置是否在内部拉高和/或拉低 GPIO。 -- :cpp:member:`mcpwm_gpio_sync_src_config_t::io_loop_back` 设置是否启用回环模式。该模式仅用于调试，使用 GPIO 交换矩阵外设同时启用 GPIO 输入和输出。 分配成功后，:cpp:func:`mcpwm_new_gpio_sync_src` 将返回一个指向已分配同步源的指针。否则，函数将返回错误代码。具体来说，当 MCPWM 组中没有空闲 GPIO 时钟源时，将返回 :c:macro:`ESP_ERR_NOT_FOUND` 错误。[1]_ @@ -207,8 +203,6 @@ MCPWM 组有一个专用定时器，用于捕获特定事件发生时的时间 - :cpp:member:`mcpwm_capture_channel_config_t::extra_capture_channel_flags::pos_edge` 和 :cpp:member:`mcpwm_capture_channel_config_t::extra_capture_channel_flags::neg_edge` 设置是否在输入信号的上升沿和/或下降沿捕获时间戳。 - :cpp:member:`mcpwm_capture_channel_config_t::extra_capture_channel_flags::pull_up` 和 :cpp:member:`mcpwm_capture_channel_config_t::extra_capture_channel_flags::pull_down` 设置是否在内部拉高和/或拉低 GPIO。 - :cpp:member:`mcpwm_capture_channel_config_t::extra_capture_channel_flags::invert_cap_signal` 设置是否取反捕获信号。 -- :cpp:member:`mcpwm_capture_channel_config_t::extra_capture_channel_flags::io_loop_back` 设置是否启用回环模式。该模式仅用于调试，使用 GPIO 交换矩阵外设同时启用 GPIO 输入和输出。 -- :cpp:member:`mcpwm_capture_channel_config_t::extra_capture_channel_flags::keep_io_conf_at_exit` 设置是否在删除通道时保留 GPIO 的相关配置。 分配成功后，:cpp:func:`mcpwm_new_capture_channel` 将返回一个指向已分配捕获通道的指针。否则，函数将返回错误代码。具体来说，当捕获定时器中没有空闲捕获通道时，将返回 :c:macro:`ESP_ERR_NOT_FOUND` 错误。 From 1193e26c88e37cfd05cce2f20225b03aff49eee2 Mon Sep 17 00:00:00 2001 From: morris Date: Tue, 27 Aug 2024 17:45:05 +0800 Subject: [PATCH 121/472] feat(gdma): added function to concat two link lists --- components/esp_hw_support/dma/gdma_link.c | 13 +++++++-- .../dma/include/esp_private/gdma_link.h | 27 ++++++++++++++++--- 2 files changed, 35 insertions(+), 5 deletions(-) diff --git a/components/esp_hw_support/dma/gdma_link.c b/components/esp_hw_support/dma/gdma_link.c index d13b62e64d2..ae9d70326f5 100644 --- a/components/esp_hw_support/dma/gdma_link.c +++ b/components/esp_hw_support/dma/gdma_link.c @@ -227,11 +227,20 @@ uintptr_t gdma_link_get_head_addr(gdma_link_list_handle_t list) return (uintptr_t)(list->items); } +esp_err_t gdma_link_concat(gdma_link_list_handle_t first_link, int first_link_item_index, gdma_link_list_handle_t second_link, int second_link_item_index) +{ + ESP_RETURN_ON_FALSE(first_link && second_link, ESP_ERR_INVALID_ARG, TAG, "invalid argument"); + gdma_link_list_item_t *lli_nc = NULL; + lli_nc = (gdma_link_list_item_t *)(first_link->items_nc + (first_link->num_items + first_link_item_index) % first_link->num_items * first_link->item_size); + lli_nc->next = (gdma_link_list_item_t *)(second_link->items + (second_link->num_items + second_link_item_index) % second_link->num_items * second_link->item_size); + return ESP_OK; +} + esp_err_t gdma_link_set_owner(gdma_link_list_handle_t list, int item_index, gdma_lli_owner_t owner) { ESP_RETURN_ON_FALSE_ISR(list, ESP_ERR_INVALID_ARG, TAG, "invalid argument"); ESP_RETURN_ON_FALSE_ISR(item_index < list->num_items, ESP_ERR_INVALID_ARG, TAG, "invalid item index"); - gdma_link_list_item_t *lli = (gdma_link_list_item_t *)(list->items_nc + item_index * list->item_size); + gdma_link_list_item_t *lli = (gdma_link_list_item_t *)(list->items_nc + (list->num_items + item_index) % list->num_items * list->item_size); lli->dw0.owner = owner; return ESP_OK; } @@ -240,7 +249,7 @@ esp_err_t gdma_link_get_owner(gdma_link_list_handle_t list, int item_index, gdma { ESP_RETURN_ON_FALSE_ISR(list && owner, ESP_ERR_INVALID_ARG, TAG, "invalid argument"); ESP_RETURN_ON_FALSE_ISR(item_index < list->num_items, ESP_ERR_INVALID_ARG, TAG, "invalid item index"); - gdma_link_list_item_t *lli = (gdma_link_list_item_t *)(list->items_nc + item_index * list->item_size); + gdma_link_list_item_t *lli = (gdma_link_list_item_t *)(list->items_nc + (list->num_items + item_index) % list->num_items * list->item_size); *owner = lli->dw0.owner; return ESP_OK; } diff --git a/components/esp_hw_support/dma/include/esp_private/gdma_link.h b/components/esp_hw_support/dma/include/esp_private/gdma_link.h index 94a13651c4e..61dd0beba62 100644 --- a/components/esp_hw_support/dma/include/esp_private/gdma_link.h +++ b/components/esp_hw_support/dma/include/esp_private/gdma_link.h @@ -71,7 +71,7 @@ typedef struct { uint32_t mark_final: 1; /*!< Whether to terminate the DMA link list at this item. Note, DMA engine will stop at this item and trigger an interrupt. If `mark_final` is not set, this list item will point to the next item, and - wrap around to the head item if it's the one in the list. */ + wrap around to the head item if it's the last one in the list. */ } flags; //!< Flags for buffer mount configurations } gdma_buffer_mount_config_t; @@ -105,6 +105,27 @@ esp_err_t gdma_link_mount_buffers(gdma_link_list_handle_t list, uint32_t start_i */ uintptr_t gdma_link_get_head_addr(gdma_link_list_handle_t list); +/** + * @brief Concatenate two link lists as follows: + * + * Link A: A1 --> A2 --> A3 --> A4 + * | item_index + * +-----+ + * | + * v item_index + * Link B: B1 --> B2 --> B3 --> B4 + * + * @param[in] first_link First link list handle, allocated by `gdma_new_link_list` + * @param[in] first_link_item_index Index of the item in the first link list (-1 means the last item) + * @param[in] second_link Second link list handle, allocated by `gdma_new_link_list` + * @param[in] second_link_item_index Index of the item in the second link list (-1 means the last item) + * @return + * - ESP_OK: Concatenate the link lists successfully + * - ESP_ERR_INVALID_ARG: Concatenate the link lists failed because of invalid argument + * - ESP_FAIL: Concatenate the link lists failed because of other error + */ +esp_err_t gdma_link_concat(gdma_link_list_handle_t first_link, int first_link_item_index, gdma_link_list_handle_t second_link, int second_link_item_index); + /** * @brief GDMA link list item owner */ @@ -117,7 +138,7 @@ typedef enum { * @brief Set the ownership for a DMA link list item * * @param[in] list Link list handle, allocated by `gdma_new_link_list` - * @param[in] item_index Index of the link list item + * @param[in] item_index Index of the link list item (-1 means the last item) * @param[in] owner Ownership * @return * - ESP_OK: Set the ownership successfully @@ -130,7 +151,7 @@ esp_err_t gdma_link_set_owner(gdma_link_list_handle_t list, int item_index, gdma * @brief Get the ownership of a DMA link list item * * @param[in] list Link list handle, allocated by `gdma_new_link_list` - * @param[in] item_index Index of the link list item + * @param[in] item_index Index of the link list item (-1 means the last item) * @param[out] owner Ownership * @return * - ESP_OK: Get the ownership successfully From dd82222dd984485cf306a29986060094b1cd10c8 Mon Sep 17 00:00:00 2001 From: morris Date: Mon, 23 Sep 2024 23:28:00 +0800 Subject: [PATCH 122/472] feat(rgb_lcd): use gdma_link driver --- components/esp_lcd/linker.lf | 1 + .../esp_lcd/priv_include/esp_lcd_common.h | 11 +- components/esp_lcd/rgb/esp_lcd_panel_rgb.c | 333 ++++++++++-------- components/esp_lcd/src/esp_lcd_common.c | 26 -- .../test_apps/rgb_lcd/main/test_rgb_board.h | 4 +- 5 files changed, 199 insertions(+), 176 deletions(-) diff --git a/components/esp_lcd/linker.lf b/components/esp_lcd/linker.lf index 513429d536e..123a258a922 100644 --- a/components/esp_lcd/linker.lf +++ b/components/esp_lcd/linker.lf @@ -4,6 +4,7 @@ entries: if LCD_RGB_ISR_IRAM_SAFE = y: gdma: gdma_reset (noflash) gdma: gdma_start (noflash) + gdma_link: gdma_link_get_head_addr (noflash) [mapping:esp_lcd_hal] archive: libhal.a diff --git a/components/esp_lcd/priv_include/esp_lcd_common.h b/components/esp_lcd/priv_include/esp_lcd_common.h index b57d37a787c..64546727ef3 100644 --- a/components/esp_lcd/priv_include/esp_lcd_common.h +++ b/components/esp_lcd/priv_include/esp_lcd_common.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -60,15 +60,6 @@ int lcd_com_register_device(lcd_com_device_type_t device_type, void *device_obj) void lcd_com_remove_device(lcd_com_device_type_t device_type, int member_id); #endif // SOC_LCDCAM_SUPPORTED -/** - * @brief Mount data to DMA descriptors - * - * @param desc_head Point to the head of DMA descriptor chain - * @param buffer Data buffer - * @param len Size of the data buffer, in bytes - */ -void lcd_com_mount_dma_data(dma_descriptor_t *desc_head, const void *buffer, size_t len); - /** * @brief Reverse the bytes in the buffer * diff --git a/components/esp_lcd/rgb/esp_lcd_panel_rgb.c b/components/esp_lcd/rgb/esp_lcd_panel_rgb.c index f105ddf7cc4..92e0e204f8d 100644 --- a/components/esp_lcd/rgb/esp_lcd_panel_rgb.c +++ b/components/esp_lcd/rgb/esp_lcd_panel_rgb.c @@ -17,7 +17,6 @@ #endif #include "freertos/FreeRTOS.h" #include "freertos/task.h" -#include "freertos/semphr.h" #include "esp_attr.h" #include "esp_check.h" #include "esp_pm.h" @@ -28,14 +27,16 @@ #include "soc/soc_caps.h" #include "esp_clk_tree.h" #include "hal/dma_types.h" -#include "esp_private/gdma.h" #include "driver/gpio.h" #include "esp_bit_defs.h" #include "esp_private/esp_clk_tree_common.h" +#include "esp_private/gdma.h" +#include "esp_private/gdma_link.h" #include "esp_private/periph_ctrl.h" #include "esp_private/gpio.h" #include "esp_psram.h" #include "esp_lcd_common.h" +#include "esp_cache.h" #include "esp_memory_utils.h" #include "soc/lcd_periph.h" #include "soc/io_mux_reg.h" @@ -43,18 +44,27 @@ #include "hal/lcd_ll.h" #include "hal/cache_hal.h" #include "hal/cache_ll.h" -#include "rom/cache.h" -#include "esp_cache.h" #if CONFIG_LCD_RGB_ISR_IRAM_SAFE #define LCD_RGB_INTR_ALLOC_FLAGS (ESP_INTR_FLAG_IRAM | ESP_INTR_FLAG_INTRDISABLED) +#define LCD_RGB_MEM_ALLOC_CAPS (MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT) #else #define LCD_RGB_INTR_ALLOC_FLAGS ESP_INTR_FLAG_INTRDISABLED +#define LCD_RGB_MEM_ALLOC_CAPS MALLOC_CAP_DEFAULT +#endif + +#if defined(SOC_GDMA_TRIG_PERIPH_LCD0_BUS) && (SOC_GDMA_TRIG_PERIPH_LCD0_BUS == SOC_GDMA_BUS_AHB) +#define LCD_GDMA_NEW_CHANNEL gdma_new_ahb_channel +#define LCD_GDMA_DESCRIPTOR_ALIGN 4 +#elif defined(SOC_GDMA_TRIG_PERIPH_LCD0_BUS) && (SOC_GDMA_TRIG_PERIPH_LCD0_BUS == SOC_GDMA_BUS_AXI) +#define LCD_GDMA_NEW_CHANNEL gdma_new_axi_channel +#define LCD_GDMA_DESCRIPTOR_ALIGN 8 +#else +#error "Unsupported GDMA bus type for RGB LCD" #endif #define RGB_LCD_PANEL_MAX_FB_NUM 3 // maximum supported frame buffer number #define RGB_LCD_PANEL_BOUNCE_BUF_NUM 2 // bounce buffer number -#define RGB_LCD_PANEL_DMA_LINKS_REPLICA MAX(RGB_LCD_PANEL_MAX_FB_NUM, RGB_LCD_PANEL_BOUNCE_BUF_NUM) #define RGB_PANEL_SWAP_XY 0 #define RGB_PANEL_MIRROR_Y 1 @@ -80,8 +90,8 @@ static esp_err_t rgb_panel_swap_xy(esp_lcd_panel_t *panel, bool swap_axes); static esp_err_t rgb_panel_set_gap(esp_lcd_panel_t *panel, int x_gap, int y_gap); static esp_err_t rgb_panel_disp_on_off(esp_lcd_panel_t *panel, bool off); static esp_err_t lcd_rgb_panel_select_clock_src(esp_rgb_panel_t *panel, lcd_clock_source_t clk_src); -static esp_err_t lcd_rgb_create_dma_channel(esp_rgb_panel_t *panel); -static void lcd_rgb_panel_init_trans_link(esp_rgb_panel_t *panel); +static esp_err_t lcd_rgb_create_dma_channel(esp_rgb_panel_t *rgb_panel); +static esp_err_t lcd_rgb_panel_init_trans_link(esp_rgb_panel_t *rgb_panel); static esp_err_t lcd_rgb_panel_configure_gpio(esp_rgb_panel_t *panel, const esp_lcd_rgb_panel_config_t *panel_config); static void lcd_rgb_panel_start_transmission(esp_rgb_panel_t *rgb_panel); static void rgb_lcd_default_isr_handler(void *args); @@ -99,19 +109,24 @@ struct esp_rgb_panel_t { intr_handle_t intr; // LCD peripheral interrupt handle esp_pm_lock_handle_t pm_lock; // Power management lock size_t num_dma_nodes; // Number of DMA descriptors that used to carry the frame buffer + gdma_channel_handle_t dma_chan; // DMA channel handle + gdma_link_list_handle_t dma_fb_links[RGB_LCD_PANEL_MAX_FB_NUM]; // DMA link lists for multiple frame buffers + gdma_link_list_handle_t dma_bb_link; // DMA link list for bounce buffer + gdma_link_list_handle_t dma_restart_link; // DMA link list for restarting the DMA uint8_t *fbs[RGB_LCD_PANEL_MAX_FB_NUM]; // Frame buffers + uint8_t *bounce_buffer[RGB_LCD_PANEL_BOUNCE_BUF_NUM]; // Pointer to the bounce buffers + size_t fb_size; // Size of frame buffer, in bytes + size_t bb_size; // Size of the bounce buffer, in bytes. If not-zero, the driver uses two bounce buffers allocated from internal memory uint8_t cur_fb_index; // Current frame buffer index uint8_t bb_fb_index; // Current frame buffer index which used by bounce buffer - size_t fb_size; // Size of frame buffer, in bytes + size_t int_mem_align; // DMA buffer alignment for internal memory + size_t ext_mem_align; // DMA buffer alignment for external memory int data_gpio_nums[SOC_LCD_RGB_DATA_WIDTH]; // GPIOs used for data lines, we keep these GPIOs for action like "invert_color" uint32_t src_clk_hz; // Peripheral source clock resolution esp_lcd_rgb_timing_t timings; // RGB timing parameters (e.g. pclk, sync pulse, porch width) - size_t bb_size; // Size of the bounce buffer, in bytes. If not-zero, the driver uses two bounce buffers allocated from internal memory int bounce_pos_px; // Position in whatever source material is used for the bounce buffer, in pixels - uint8_t *bounce_buffer[RGB_LCD_PANEL_BOUNCE_BUF_NUM]; // Pointer to the bounce buffers size_t bb_eof_count; // record the number we received the DMA EOF event, compare with `expect_eof_count` in the VSYNC_END ISR size_t expect_eof_count; // record the number of DMA EOF event we expected to receive - gdma_channel_handle_t dma_chan; // DMA channel handle esp_lcd_rgb_panel_vsync_cb_t on_vsync; // VSYNC event callback esp_lcd_rgb_panel_bounce_buf_fill_cb_t on_bounce_empty; // callback used to fill a bounce buffer rather than copying from the frame buffer esp_lcd_rgb_panel_bounce_buf_finish_cb_t on_bounce_frame_finish; // callback used to notify when the bounce buffer finish copying the entire frame @@ -128,66 +143,55 @@ struct esp_rgb_panel_t { uint32_t need_update_pclk: 1; // Whether to update the PCLK before start a new transaction uint32_t need_restart: 1; // Whether to restart the LCD controller and the DMA uint32_t bb_invalidate_cache: 1; // Whether to do cache invalidation in bounce buffer mode + uint32_t fb_behind_cache: 1; // Whether the frame buffer is behind the cache + uint32_t bb_behind_cache: 1; // Whether the bounce buffer is behind the cache } flags; - dma_descriptor_t *dma_links[RGB_LCD_PANEL_DMA_LINKS_REPLICA]; // fbs[0] <-> dma_links[0], fbs[1] <-> dma_links[1], etc - dma_descriptor_t dma_restart_node; // DMA descriptor used to restart the transfer - dma_descriptor_t dma_nodes[]; // DMA descriptors pool }; -static esp_err_t lcd_rgb_panel_alloc_frame_buffers(const esp_lcd_rgb_panel_config_t *rgb_panel_config, esp_rgb_panel_t *rgb_panel) +static esp_err_t lcd_rgb_panel_alloc_frame_buffers(esp_rgb_panel_t *rgb_panel) { - bool fb_in_psram = false; - size_t ext_mem_align = 0; - size_t int_mem_align = 0; - gdma_get_alignment_constraints(rgb_panel->dma_chan, &int_mem_align, &ext_mem_align); + bool fb_in_psram = rgb_panel->flags.fb_in_psram; - // also take the cache line size into account when allocating the frame buffer - uint32_t ext_mem_cache_line_size = cache_hal_get_cache_line_size(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_DATA); + // read the cache line size of internal and external memory, we use this information to check if the allocated memory is behind the cache uint32_t int_mem_cache_line_size = cache_hal_get_cache_line_size(CACHE_LL_LEVEL_INT_MEM, CACHE_TYPE_DATA); - // The buffer must be aligned to the cache line size - if (ext_mem_cache_line_size) { - ext_mem_align = MAX(ext_mem_align, ext_mem_cache_line_size); - } - if (int_mem_cache_line_size) { - int_mem_align = MAX(int_mem_align, int_mem_cache_line_size); - } + uint32_t ext_mem_cache_line_size = cache_hal_get_cache_line_size(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_DATA); // alloc frame buffer - if (rgb_panel->num_fbs > 0) { - // fb_in_psram is only an option, if there's no PSRAM on board, we fallback to alloc from SRAM - if (rgb_panel_config->flags.fb_in_psram) { -#if CONFIG_SPIRAM_USE_MALLOC || CONFIG_SPIRAM_USE_CAPS_ALLOC - if (esp_psram_is_initialized()) { - fb_in_psram = true; - } -#endif + for (int i = 0; i < rgb_panel->num_fbs; i++) { + if (fb_in_psram) { + // the allocated buffer is also aligned to the cache line size + rgb_panel->fbs[i] = heap_caps_aligned_calloc(rgb_panel->ext_mem_align, 1, rgb_panel->fb_size, + MALLOC_CAP_SPIRAM | MALLOC_CAP_DMA | MALLOC_CAP_8BIT); + ESP_RETURN_ON_FALSE(rgb_panel->fbs[i], ESP_ERR_NO_MEM, TAG, "no mem for frame buffer"); + rgb_panel->flags.fb_behind_cache = ext_mem_cache_line_size > 0; + } else { + rgb_panel->fbs[i] = heap_caps_aligned_calloc(rgb_panel->int_mem_align, 1, rgb_panel->fb_size, + MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_8BIT); + ESP_RETURN_ON_FALSE(rgb_panel->fbs[i], ESP_ERR_NO_MEM, TAG, "no mem for frame buffer"); + rgb_panel->flags.fb_behind_cache = int_mem_cache_line_size > 0; } - for (int i = 0; i < rgb_panel->num_fbs; i++) { - if (fb_in_psram) { - // the low level malloc function will help check the validation of alignment - rgb_panel->fbs[i] = heap_caps_aligned_calloc(ext_mem_align, 1, rgb_panel->fb_size, MALLOC_CAP_SPIRAM | MALLOC_CAP_8BIT); - ESP_RETURN_ON_FALSE(rgb_panel->fbs[i], ESP_ERR_NO_MEM, TAG, "no mem for frame buffer"); - // calloc not only allocates but also zero's the buffer. We have to make sure this is - // properly committed to the PSRAM, otherwise all sorts of visual corruption will happen. - ESP_RETURN_ON_ERROR(esp_cache_msync(rgb_panel->fbs[i], rgb_panel->fb_size, ESP_CACHE_MSYNC_FLAG_DIR_C2M), TAG, "cache write back failed"); - } else { - rgb_panel->fbs[i] = heap_caps_aligned_calloc(int_mem_align, 1, rgb_panel->fb_size, MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA); - ESP_RETURN_ON_FALSE(rgb_panel->fbs[i], ESP_ERR_NO_MEM, TAG, "no mem for frame buffer"); - } + // flush data from cache to the physical memory + if (rgb_panel->flags.fb_behind_cache) { + esp_cache_msync(rgb_panel->fbs[i], rgb_panel->fb_size, ESP_CACHE_MSYNC_FLAG_DIR_C2M | ESP_CACHE_MSYNC_FLAG_UNALIGNED); } } // alloc bounce buffer if (rgb_panel->bb_size) { for (int i = 0; i < RGB_LCD_PANEL_BOUNCE_BUF_NUM; i++) { - // bounce buffer must come from SRAM - rgb_panel->bounce_buffer[i] = heap_caps_aligned_calloc(int_mem_align, 1, rgb_panel->bb_size, MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA); + // bounce buffer must be allocated from internal memory for performance + rgb_panel->bounce_buffer[i] = heap_caps_aligned_calloc(rgb_panel->int_mem_align, 1, rgb_panel->bb_size, + MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_8BIT); ESP_RETURN_ON_FALSE(rgb_panel->bounce_buffer[i], ESP_ERR_NO_MEM, TAG, "no mem for bounce buffer"); + if (int_mem_cache_line_size > 0) { + // flush data from cache to the physical memory + esp_cache_msync(rgb_panel->bounce_buffer[i], rgb_panel->bb_size, ESP_CACHE_MSYNC_FLAG_DIR_C2M | ESP_CACHE_MSYNC_FLAG_UNALIGNED); + rgb_panel->flags.bb_behind_cache = true; + } } } rgb_panel->cur_fb_index = 0; rgb_panel->bb_fb_index = 0; - rgb_panel->flags.fb_in_psram = fb_in_psram; return ESP_OK; } @@ -205,20 +209,28 @@ static esp_err_t lcd_rgb_panel_destroy(esp_rgb_panel_t *rgb_panel) } lcd_com_remove_device(LCD_COM_DEVICE_TYPE_RGB, rgb_panel->panel_id); } - for (size_t i = 0; i < rgb_panel->num_fbs; i++) { + if (rgb_panel->dma_chan) { + gdma_disconnect(rgb_panel->dma_chan); + gdma_del_channel(rgb_panel->dma_chan); + } + for (size_t i = 0; i < RGB_LCD_PANEL_MAX_FB_NUM; i++) { if (rgb_panel->fbs[i]) { free(rgb_panel->fbs[i]); } + if (rgb_panel->dma_fb_links[i]) { + gdma_del_link_list(rgb_panel->dma_fb_links[i]); + } } - if (rgb_panel->bounce_buffer[0]) { - free(rgb_panel->bounce_buffer[0]); + for (int i = 0; i < RGB_LCD_PANEL_BOUNCE_BUF_NUM; i++) { + if (rgb_panel->bounce_buffer[i]) { + free(rgb_panel->bounce_buffer[i]); + } } - if (rgb_panel->bounce_buffer[1]) { - free(rgb_panel->bounce_buffer[1]); + if (rgb_panel->dma_bb_link) { + gdma_del_link_list(rgb_panel->dma_bb_link); } - if (rgb_panel->dma_chan) { - gdma_disconnect(rgb_panel->dma_chan); - gdma_del_channel(rgb_panel->dma_chan); + if (rgb_panel->dma_restart_link) { + gdma_del_link_list(rgb_panel->dma_restart_link); } if (rgb_panel->intr) { esp_intr_free(rgb_panel->intr); @@ -240,7 +252,7 @@ esp_err_t esp_lcd_new_rgb_panel(const esp_lcd_rgb_panel_config_t *rgb_panel_conf esp_rgb_panel_t *rgb_panel = NULL; ESP_RETURN_ON_FALSE(rgb_panel_config && ret_panel, ESP_ERR_INVALID_ARG, TAG, "invalid parameter"); size_t data_width = rgb_panel_config->data_width; - ESP_RETURN_ON_FALSE((data_width >= 8) && (data_width <= SOC_LCD_RGB_DATA_WIDTH) && ((data_width & (data_width - 1)) == 0), ESP_ERR_INVALID_ARG, + ESP_RETURN_ON_FALSE((data_width > 0) && (data_width <= SOC_LCDCAM_RGB_DATA_WIDTH) && ((data_width % 8) == 0), ESP_ERR_INVALID_ARG, TAG, "unsupported data width %d", data_width); ESP_RETURN_ON_FALSE(!(rgb_panel_config->flags.double_fb && rgb_panel_config->flags.no_fb), ESP_ERR_INVALID_ARG, TAG, "double_fb conflicts with no_fb"); @@ -283,25 +295,16 @@ esp_err_t esp_lcd_new_rgb_panel(const esp_lcd_rgb_panel_config_t *rgb_panel_conf // calculate the number of DMA descriptors size_t num_dma_nodes = 0; - if (bb_size) { - // in bounce buffer mode, DMA is used to convey the bounce buffer, not the frame buffer. - // frame buffer is copied to bounce buffer by CPU - num_dma_nodes = (bb_size + DMA_DESCRIPTOR_BUFFER_MAX_SIZE - 1) / DMA_DESCRIPTOR_BUFFER_MAX_SIZE; - } else { - // Not bounce buffer mode, DMA descriptors need to fit the entire frame buffer - num_dma_nodes = (fb_size + DMA_DESCRIPTOR_BUFFER_MAX_SIZE - 1) / DMA_DESCRIPTOR_BUFFER_MAX_SIZE; - } - - // DMA descriptors must be placed in internal SRAM (requested by DMA) - rgb_panel = heap_caps_calloc(1, sizeof(esp_rgb_panel_t) + num_dma_nodes * sizeof(dma_descriptor_t) * RGB_LCD_PANEL_DMA_LINKS_REPLICA, - MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL); + // allocate memory for rgb panel + rgb_panel = heap_caps_calloc(1, sizeof(esp_rgb_panel_t), LCD_RGB_MEM_ALLOC_CAPS); ESP_GOTO_ON_FALSE(rgb_panel, ESP_ERR_NO_MEM, err, TAG, "no mem for rgb panel"); + rgb_panel->panel_id = -1; rgb_panel->num_dma_nodes = num_dma_nodes; rgb_panel->num_fbs = num_fbs; rgb_panel->fb_size = fb_size; rgb_panel->bb_size = bb_size; + rgb_panel->fb_bits_per_pixel = fb_bits_per_pixel; rgb_panel->expect_eof_count = expect_bb_eof_count; - rgb_panel->panel_id = -1; // register to platform int panel_id = lcd_com_register_device(LCD_COM_DEVICE_TYPE_RGB, rgb_panel); ESP_GOTO_ON_FALSE(panel_id >= 0, ESP_ERR_NOT_FOUND, err, TAG, "no free rgb panel slot"); @@ -343,13 +346,13 @@ esp_err_t esp_lcd_new_rgb_panel(const esp_lcd_rgb_panel_config_t *rgb_panel_conf // install DMA service rgb_panel->flags.stream_mode = !rgb_panel_config->flags.refresh_on_demand; - rgb_panel->fb_bits_per_pixel = fb_bits_per_pixel; rgb_panel->dma_burst_size = rgb_panel_config->dma_burst_size ? rgb_panel_config->dma_burst_size : 64; + rgb_panel->flags.fb_in_psram = rgb_panel_config->flags.fb_in_psram; ESP_GOTO_ON_ERROR(lcd_rgb_create_dma_channel(rgb_panel), err, TAG, "install DMA failed"); // allocate frame buffers + bounce buffers - ESP_GOTO_ON_ERROR(lcd_rgb_panel_alloc_frame_buffers(rgb_panel_config, rgb_panel), err, TAG, "alloc frame buffers failed"); + ESP_GOTO_ON_ERROR(lcd_rgb_panel_alloc_frame_buffers(rgb_panel), err, TAG, "alloc frame buffers failed"); // initialize DMA descriptor link - lcd_rgb_panel_init_trans_link(rgb_panel); + ESP_GOTO_ON_ERROR(lcd_rgb_panel_init_trans_link(rgb_panel), err, TAG, "init DMA link failed"); // configure GPIO ret = lcd_rgb_panel_configure_gpio(rgb_panel, rgb_panel_config); @@ -786,13 +789,14 @@ static esp_err_t rgb_panel_draw_bitmap(esp_lcd_panel_t *panel, int x_start, int if (!rgb_panel->bb_size) { if (rgb_panel->flags.stream_mode) { - // the DMA will convey the new frame buffer next time - for (int i = 0; i < RGB_LCD_PANEL_DMA_LINKS_REPLICA; i++) { - rgb_panel->dma_nodes[rgb_panel->num_dma_nodes * (i + 1) - 1].next = rgb_panel->dma_links[rgb_panel->cur_fb_index]; + for (int i = 0; i < rgb_panel->num_fbs; i++) { + // Note, because of DMA prefetch, there's possibility that the old frame buffer might be sent out again + // it's hard to know the time when the new frame buffer starts + gdma_link_concat(rgb_panel->dma_fb_links[i], -1, rgb_panel->dma_fb_links[rgb_panel->cur_fb_index], 0); } + } } - return ESP_OK; } @@ -959,95 +963,144 @@ static IRAM_ATTR bool lcd_rgb_panel_fill_bounce_buffer(esp_rgb_panel_t *panel, u static IRAM_ATTR bool lcd_rgb_panel_eof_handler(gdma_channel_handle_t dma_chan, gdma_event_data_t *event_data, void *user_data) { esp_rgb_panel_t *panel = (esp_rgb_panel_t *)user_data; - dma_descriptor_t *desc = (dma_descriptor_t *)event_data->tx_eof_desc_addr; // Figure out which bounce buffer to write to. - // Note: what we receive is the *last* descriptor of this bounce buffer. - int bb = (desc == &panel->dma_nodes[panel->num_dma_nodes - 1]) ? 0 : 1; portENTER_CRITICAL_ISR(&panel->spinlock); + int bb = panel->bb_eof_count % RGB_LCD_PANEL_BOUNCE_BUF_NUM; panel->bb_eof_count++; portEXIT_CRITICAL_ISR(&panel->spinlock); return lcd_rgb_panel_fill_bounce_buffer(panel, panel->bounce_buffer[bb]); } -static esp_err_t lcd_rgb_create_dma_channel(esp_rgb_panel_t *panel) +static esp_err_t lcd_rgb_create_dma_channel(esp_rgb_panel_t *rgb_panel) { // alloc DMA channel and connect to LCD peripheral gdma_channel_alloc_config_t dma_chan_config = { .direction = GDMA_CHANNEL_DIRECTION_TX, }; -#if SOC_GDMA_TRIG_PERIPH_LCD0_BUS == SOC_GDMA_BUS_AHB - ESP_RETURN_ON_ERROR(gdma_new_ahb_channel(&dma_chan_config, &panel->dma_chan), TAG, "alloc DMA channel failed"); -#elif SOC_GDMA_TRIG_PERIPH_LCD0_BUS == SOC_GDMA_BUS_AXI - ESP_RETURN_ON_ERROR(gdma_new_axi_channel(&dma_chan_config, &panel->dma_chan), TAG, "alloc DMA channel failed"); -#endif - gdma_connect(panel->dma_chan, GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_LCD, 0)); + ESP_RETURN_ON_ERROR(LCD_GDMA_NEW_CHANNEL(&dma_chan_config, &rgb_panel->dma_chan), TAG, "alloc DMA channel failed"); + gdma_connect(rgb_panel->dma_chan, GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_LCD, 0)); + + // configure DMA strategy + gdma_strategy_config_t dma_strategy = { + .eof_till_data_popped = false, + }; + gdma_apply_strategy(rgb_panel->dma_chan, &dma_strategy); - // configure DMA transfer parameters + // configure DMA transfer gdma_transfer_config_t trans_cfg = { - .max_data_burst_size = panel->dma_burst_size, - .access_ext_mem = true, // frame buffer was allocated from external memory + .max_data_burst_size = rgb_panel->dma_burst_size, + .access_ext_mem = rgb_panel->flags.fb_in_psram, }; - ESP_RETURN_ON_ERROR(gdma_config_transfer(panel->dma_chan, &trans_cfg), TAG, "config DMA transfer failed"); + ESP_RETURN_ON_ERROR(gdma_config_transfer(rgb_panel->dma_chan, &trans_cfg), TAG, "config DMA transfer failed"); + // get the memory alignment required by the DMA + gdma_get_alignment_constraints(rgb_panel->dma_chan, &rgb_panel->int_mem_align, &rgb_panel->ext_mem_align); // we need to refill the bounce buffer in the DMA EOF interrupt, so only register the callback for bounce buffer mode - if (panel->bb_size) { + if (rgb_panel->bb_size) { gdma_tx_event_callbacks_t cbs = { .on_trans_eof = lcd_rgb_panel_eof_handler, }; - gdma_register_tx_event_callbacks(panel->dma_chan, &cbs, panel); + gdma_register_tx_event_callbacks(rgb_panel->dma_chan, &cbs, rgb_panel); } return ESP_OK; } -// If we restart GDMA, many pixels already have been transferred to the LCD peripheral. -// Looks like that has 16 pixels of FIFO plus one holding register. +// If we restart GDMA, the data sent to the LCD peripheral needs to start LCD_FIFO_PRESERVE_SIZE_PX pixels after the FB start +// so we use a dedicated DMA link (called restart link) to restart the transaction #define LCD_FIFO_PRESERVE_SIZE_PX (LCD_LL_FIFO_DEPTH + 1) -static void lcd_rgb_panel_init_trans_link(esp_rgb_panel_t *panel) +static esp_err_t lcd_rgb_panel_init_trans_link(esp_rgb_panel_t *rgb_panel) { - for (int i = 0; i < RGB_LCD_PANEL_DMA_LINKS_REPLICA; i++) { - panel->dma_links[i] = &panel->dma_nodes[panel->num_dma_nodes * i]; - } - // chain DMA descriptors - for (int i = 0; i < panel->num_dma_nodes * RGB_LCD_PANEL_DMA_LINKS_REPLICA; i++) { - panel->dma_nodes[i].dw0.owner = DMA_DESCRIPTOR_BUFFER_OWNER_CPU; - panel->dma_nodes[i].next = &panel->dma_nodes[i + 1]; - } - - if (panel->bb_size) { - // loop end back to start - panel->dma_nodes[panel->num_dma_nodes * RGB_LCD_PANEL_BOUNCE_BUF_NUM - 1].next = &panel->dma_nodes[0]; - // mount the bounce buffers to the DMA descriptors - lcd_com_mount_dma_data(panel->dma_links[0], panel->bounce_buffer[0], panel->bb_size); - lcd_com_mount_dma_data(panel->dma_links[1], panel->bounce_buffer[1], panel->bb_size); - } else { - if (panel->flags.stream_mode) { - // circle DMA descriptors chain for each frame buffer - for (int i = 0; i < RGB_LCD_PANEL_DMA_LINKS_REPLICA; i++) { - panel->dma_nodes[panel->num_dma_nodes * (i + 1) - 1].next = &panel->dma_nodes[panel->num_dma_nodes * i]; - } - } else { - // one-off DMA descriptors chain - for (int i = 0; i < RGB_LCD_PANEL_DMA_LINKS_REPLICA; i++) { - panel->dma_nodes[panel->num_dma_nodes * (i + 1) - 1].next = NULL; + // the restart link shares the same buffer with the frame/bounce buffer but start from a different offset + int restart_skip_bytes = LCD_FIFO_PRESERVE_SIZE_PX * (rgb_panel->fb_bits_per_pixel / 8); + if (rgb_panel->bb_size) { + // DMA is used to convey the bounce buffer + size_t num_dma_nodes_per_bounce_buffer = (rgb_panel->bb_size + LCD_DMA_DESCRIPTOR_BUFFER_MAX_SIZE - 1) / LCD_DMA_DESCRIPTOR_BUFFER_MAX_SIZE; + gdma_link_list_config_t link_cfg = { + .buffer_alignment = rgb_panel->int_mem_align, + .item_alignment = LCD_GDMA_DESCRIPTOR_ALIGN, + .num_items = num_dma_nodes_per_bounce_buffer * RGB_LCD_PANEL_BOUNCE_BUF_NUM, + .flags = { + .check_owner = true, } + }; + ESP_RETURN_ON_ERROR(gdma_new_link_list(&link_cfg, &rgb_panel->dma_bb_link), TAG, "create bounce buffer DMA link failed"); + // mount bounce buffers to the DMA link list + gdma_buffer_mount_config_t mount_cfgs[RGB_LCD_PANEL_BOUNCE_BUF_NUM] = {0}; + for (int i = 0; i < RGB_LCD_PANEL_BOUNCE_BUF_NUM; i++) { + mount_cfgs[i].buffer = rgb_panel->bounce_buffer[i]; + mount_cfgs[i].length = rgb_panel->bb_size; + mount_cfgs[i].flags.mark_eof = true; // we use the DMA EOF interrupt to copy the frame buffer (partially) to the bounce buffer } - // mount the frame buffer to the DMA descriptors - for (size_t i = 0; i < panel->num_fbs; i++) { - lcd_com_mount_dma_data(panel->dma_links[i], panel->fbs[i], panel->fb_size); + ESP_RETURN_ON_ERROR(gdma_link_mount_buffers(rgb_panel->dma_bb_link, 0, mount_cfgs, RGB_LCD_PANEL_BOUNCE_BUF_NUM, NULL), + TAG, "mount DMA bounce buffers failed"); + // create restart link + gdma_link_list_config_t restart_link_cfg = { + .buffer_alignment = rgb_panel->int_mem_align, + .item_alignment = LCD_GDMA_DESCRIPTOR_ALIGN, + .num_items = 1, // the restart link only contains one node + .flags = { + .check_owner = true, + } + }; + ESP_RETURN_ON_ERROR(gdma_new_link_list(&restart_link_cfg, &rgb_panel->dma_restart_link), TAG, "create DMA restart link list failed"); + gdma_buffer_mount_config_t restart_buffer_mount_cfg = { + .buffer = rgb_panel->bounce_buffer[0] + restart_skip_bytes, + .length = MIN(LCD_DMA_DESCRIPTOR_BUFFER_MAX_SIZE, rgb_panel->bb_size) - restart_skip_bytes, + }; + ESP_RETURN_ON_ERROR(gdma_link_mount_buffers(rgb_panel->dma_restart_link, 0, &restart_buffer_mount_cfg, 1, NULL), + TAG, "mount DMA restart buffer failed"); + + // Magic here: we use the restart link to restart the bounce buffer link list, so concat them + gdma_link_concat(rgb_panel->dma_restart_link, 0, rgb_panel->dma_bb_link, 1); + } else { + // DMA is used to convey the frame buffer + size_t num_dma_nodes = (rgb_panel->fb_size + LCD_DMA_DESCRIPTOR_BUFFER_MAX_SIZE - 1) / LCD_DMA_DESCRIPTOR_BUFFER_MAX_SIZE; + gdma_link_list_config_t link_cfg = { + .buffer_alignment = rgb_panel->flags.fb_in_psram ? rgb_panel->ext_mem_align : rgb_panel->int_mem_align, + .item_alignment = LCD_GDMA_DESCRIPTOR_ALIGN, + .num_items = num_dma_nodes, + .flags = { + .check_owner = true, + }, + }; + gdma_buffer_mount_config_t mount_cfg = { + .length = rgb_panel->fb_size, + .flags = { + .mark_final = rgb_panel->flags.stream_mode ? false : true, + .mark_eof = true, + }, + }; + for (size_t i = 0; i < rgb_panel->num_fbs; i++) { + ESP_RETURN_ON_ERROR(gdma_new_link_list(&link_cfg, &rgb_panel->dma_fb_links[i]), TAG, "create frame buffer DMA link failed"); + // mount bounce buffers to the DMA link list + mount_cfg.buffer = rgb_panel->fbs[i]; + ESP_RETURN_ON_ERROR(gdma_link_mount_buffers(rgb_panel->dma_fb_links[i], 0, &mount_cfg, 1, NULL), + TAG, "mount DMA frame buffer failed"); } + // create restart link + gdma_link_list_config_t restart_link_cfg = { + .buffer_alignment = rgb_panel->flags.fb_in_psram ? rgb_panel->ext_mem_align : rgb_panel->int_mem_align, + .item_alignment = LCD_GDMA_DESCRIPTOR_ALIGN, + .num_items = 1, // the restart link only contains one node + .flags = { + .check_owner = true, + } + }; + ESP_RETURN_ON_ERROR(gdma_new_link_list(&restart_link_cfg, &rgb_panel->dma_restart_link), TAG, "create DMA restart link list failed"); + gdma_buffer_mount_config_t restart_buffer_mount_cfg = { + .buffer = rgb_panel->fbs[0] + restart_skip_bytes, + .length = MIN(LCD_DMA_DESCRIPTOR_BUFFER_MAX_SIZE, rgb_panel->fb_size) - restart_skip_bytes, + }; + ESP_RETURN_ON_ERROR(gdma_link_mount_buffers(rgb_panel->dma_restart_link, 0, &restart_buffer_mount_cfg, 1, NULL), + TAG, "mount DMA restart buffer failed"); + + // Magic here: we use the restart link to restart the frame buffer link list, so concat them + gdma_link_concat(rgb_panel->dma_restart_link, 0, rgb_panel->dma_fb_links[0], 1); } - // On restart, the data sent to the LCD peripheral needs to start LCD_FIFO_PRESERVE_SIZE_PX pixels after the FB start - // so we use a dedicated DMA node to restart the DMA transaction - // see also `lcd_rgb_panel_try_restart_transmission` - memcpy(&panel->dma_restart_node, &panel->dma_nodes[0], sizeof(panel->dma_restart_node)); - int restart_skip_bytes = LCD_FIFO_PRESERVE_SIZE_PX * (panel->fb_bits_per_pixel / 8); - uint8_t *p = (uint8_t *)panel->dma_restart_node.buffer; - panel->dma_restart_node.buffer = &p[restart_skip_bytes]; - panel->dma_restart_node.dw0.length -= restart_skip_bytes; - panel->dma_restart_node.dw0.size -= restart_skip_bytes; + return ESP_OK; } // reset the GDMA channel every VBlank to stop permanent desyncs from happening. @@ -1093,7 +1146,7 @@ static IRAM_ATTR void lcd_rgb_panel_try_restart_transmission(esp_rgb_panel_t *pa gdma_reset(panel->dma_chan); // restart the DMA by a special DMA node - gdma_start(panel->dma_chan, (intptr_t)&panel->dma_restart_node); + gdma_start(panel->dma_chan, gdma_link_get_head_addr(panel->dma_restart_link)); if (panel->bb_size) { // Fill 2nd bounce buffer while 1st is being sent out, if needed. @@ -1119,7 +1172,11 @@ static void lcd_rgb_panel_start_transmission(esp_rgb_panel_t *rgb_panel) } // the start of DMA should be prior to the start of LCD engine - gdma_start(rgb_panel->dma_chan, (intptr_t)rgb_panel->dma_links[rgb_panel->cur_fb_index]); + if (rgb_panel->bb_size) { + gdma_start(rgb_panel->dma_chan, gdma_link_get_head_addr(rgb_panel->dma_bb_link)); + } else { + gdma_start(rgb_panel->dma_chan, gdma_link_get_head_addr(rgb_panel->dma_fb_links[rgb_panel->cur_fb_index])); + } // delay 1us is sufficient for DMA to pass data to LCD FIFO // in fact, this is only needed when LCD pixel clock is set too high esp_rom_delay_us(1); diff --git a/components/esp_lcd/src/esp_lcd_common.c b/components/esp_lcd/src/esp_lcd_common.c index 07ee21a98e2..7b739188bba 100644 --- a/components/esp_lcd/src/esp_lcd_common.c +++ b/components/esp_lcd/src/esp_lcd_common.c @@ -78,29 +78,3 @@ void lcd_com_remove_device(lcd_com_device_type_t device_type, int member_id) } } #endif // SOC_LCDCAM_SUPPORTED - -void lcd_com_mount_dma_data(dma_descriptor_t *desc_head, const void *buffer, size_t len) -{ - size_t prepared_length = 0; - uint8_t *data = (uint8_t *)buffer; - dma_descriptor_t *desc = desc_head; - while (len > DMA_DESCRIPTOR_BUFFER_MAX_SIZE) { - desc->dw0.suc_eof = 0; // not the end of the transaction - desc->dw0.size = DMA_DESCRIPTOR_BUFFER_MAX_SIZE; - desc->dw0.length = DMA_DESCRIPTOR_BUFFER_MAX_SIZE; - desc->dw0.owner = DMA_DESCRIPTOR_BUFFER_OWNER_DMA; - desc->buffer = &data[prepared_length]; - desc = desc->next; // move to next descriptor - prepared_length += DMA_DESCRIPTOR_BUFFER_MAX_SIZE; - len -= DMA_DESCRIPTOR_BUFFER_MAX_SIZE; - } - if (len) { - desc->dw0.suc_eof = 1; // end of the transaction - desc->dw0.size = len; - desc->dw0.length = len; - desc->dw0.owner = DMA_DESCRIPTOR_BUFFER_OWNER_DMA; - desc->buffer = &data[prepared_length]; - desc = desc->next; // move to next descriptor - prepared_length += len; - } -} diff --git a/components/esp_lcd/test_apps/rgb_lcd/main/test_rgb_board.h b/components/esp_lcd/test_apps/rgb_lcd/main/test_rgb_board.h index 180c519e561..4aad495537c 100644 --- a/components/esp_lcd/test_apps/rgb_lcd/main/test_rgb_board.h +++ b/components/esp_lcd/test_apps/rgb_lcd/main/test_rgb_board.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -34,7 +34,7 @@ extern "C" { #define TEST_LCD_DATA15_GPIO 40 // R4 #define TEST_LCD_DISP_EN_GPIO -1 -#define TEST_LCD_PIXEL_CLOCK_HZ (10 * 1000 * 1000) +#define TEST_LCD_PIXEL_CLOCK_HZ (18 * 1000 * 1000) #ifdef __cplusplus } From d792f7d86de9cdcaa014e240f9dc6544aa18bf07 Mon Sep 17 00:00:00 2001 From: Zhang Shuxian Date: Tue, 8 Oct 2024 14:34:36 +0800 Subject: [PATCH 123/472] docs: Update CN translation for esp_eth.rst --- docs/en/api-reference/network/esp_eth.rst | 2 +- docs/zh_CN/api-reference/network/esp_eth.rst | 20 +++++++++++++++----- 2 files changed, 16 insertions(+), 6 deletions(-) diff --git a/docs/en/api-reference/network/esp_eth.rst b/docs/en/api-reference/network/esp_eth.rst index ced34bb9822..0b1ee221755 100644 --- a/docs/en/api-reference/network/esp_eth.rst +++ b/docs/en/api-reference/network/esp_eth.rst @@ -293,7 +293,7 @@ The Ethernet driver is implemented in an Object-Oriented style. Any operation on eth_mac_config_t mac_config = ETH_MAC_DEFAULT_CONFIG(); // apply default common MAC configuration eth_esp32_emac_config_t esp32_emac_config = ETH_ESP32_EMAC_DEFAULT_CONFIG(); // apply default vendor-specific MAC configuration esp32_emac_config.smi_gpio.mdc_num = CONFIG_EXAMPLE_ETH_MDC_GPIO; // alter the GPIO used for MDC signal - esp32_emac_config.smi_gpio.mdio_num = CONFIG_EXAMPLE_ETH_MDIO_GPIO; // alter the GPIO used for MDIO signa + esp32_emac_config.smi_gpio.mdio_num = CONFIG_EXAMPLE_ETH_MDIO_GPIO; // alter the GPIO used for MDIO signal esp_eth_mac_t *mac = esp_eth_mac_new_esp32(&esp32_emac_config, &mac_config); // create MAC instance eth_phy_config_t phy_config = ETH_PHY_DEFAULT_CONFIG(); // apply default PHY configuration diff --git a/docs/zh_CN/api-reference/network/esp_eth.rst b/docs/zh_CN/api-reference/network/esp_eth.rst index d4acdfb6d13..96ffa63b23c 100644 --- a/docs/zh_CN/api-reference/network/esp_eth.rst +++ b/docs/zh_CN/api-reference/network/esp_eth.rst @@ -269,6 +269,10 @@ PHY 的相关配置可以在 :cpp:class:`eth_phy_config_t` 中找到，具体包 * :cpp:member:`eth_phy_config_t::reset_gpio_num`：如果开发板同时将 PHY 复位管脚连接至了任意 GPIO 管脚，请使用该字段进行配置。否则，配置为 ``-1``。 + * :cpp:member:`eth_phy_config_t::hw_reset_assert_time_us`：PHY 复位引脚被置为有效状态的时间（以微秒为单位）。将该值配置为 ``0``，即可使用芯片默认的复位时长。 + + * :cpp:member:`eth_phy_config_t::post_hw_reset_delay_ms`：PHY 硬件复位完成后的等待时间（以毫秒为单位）。将该值配置为 ``0``，即可使用芯片默认的等待时长，配置为 ``-1``，表示执行 PHY 硬件复位后不等待。 + ESP-IDF 在宏 :c:macro:`ETH_MAC_DEFAULT_CONFIG` 和 :c:macro:`ETH_PHY_DEFAULT_CONFIG` 中为 MAC 和 PHY 提供了默认配置。 @@ -288,19 +292,23 @@ ESP-IDF 在宏 :c:macro:`ETH_MAC_DEFAULT_CONFIG` 和 :c:macro:`ETH_PHY_DEFAULT_C eth_mac_config_t mac_config = ETH_MAC_DEFAULT_CONFIG(); // 应用默认的通用 MAC 配置 eth_esp32_emac_config_t esp32_emac_config = ETH_ESP32_EMAC_DEFAULT_CONFIG(); // 应用默认的供应商特定 MAC 配置 - esp32_emac_config.smi_mdc_gpio_num = CONFIG_EXAMPLE_ETH_MDC_GPIO; // 更改用于 MDC 信号的 GPIO - esp32_emac_config.smi_mdio_gpio_num = CONFIG_EXAMPLE_ETH_MDIO_GPIO; // 更改用于 MDIO 信号的 GPIO + esp32_emac_config.smi_gpio.mdc_num = CONFIG_EXAMPLE_ETH_MDC_GPIO; // 更改用于 MDC 信号的 GPIO + esp32_emac_config.smi_gpio.mdio_num = CONFIG_EXAMPLE_ETH_MDIO_GPIO; // 更改用于 MDIO 信号的 GPIO esp_eth_mac_t *mac = esp_eth_mac_new_esp32(&esp32_emac_config, &mac_config); // 创建 MAC 实例 eth_phy_config_t phy_config = ETH_PHY_DEFAULT_CONFIG(); // 应用默认的 PHY 配置 phy_config.phy_addr = CONFIG_EXAMPLE_ETH_PHY_ADDR; // 根据开发板设计更改 PHY 地址 phy_config.reset_gpio_num = CONFIG_EXAMPLE_ETH_PHY_RST_GPIO; // 更改用于 PHY 复位的 GPIO - esp_eth_phy_t *phy = esp_eth_phy_new_ip101(&phy_config); // 创建 PHY 实例 - // ESP-IDF 为数种以太网 PHY 芯片驱动提供官方支持 + esp_eth_phy_t *phy = esp_eth_phy_new_generic(&phy_config); // 创建通用 PHY 实例 + // ESP-IDF 为数种特定以太网 PHY 芯片驱动提供官方支持 + // esp_eth_phy_t *phy = esp_eth_phy_new_ip101(&phy_config); // esp_eth_phy_t *phy = esp_eth_phy_new_rtl8201(&phy_config); // esp_eth_phy_t *phy = esp_eth_phy_new_lan8720(&phy_config); // esp_eth_phy_t *phy = esp_eth_phy_new_dp83848(&phy_config); + .. note:: + 使用 :cpp:func:`esp_eth_phy_new_generic` 创建新的 PHY 实例时，可以使用任何符合 IEEE 802.3 标准的以太网 PHY 芯片。然而，尽管 PHY 芯片符合 IEEE 802.3 标准，能提供基本功能，但某些特定的功能可能无法完全实现。例如，某些以太网 PHY 芯片可能需要配置特定的速度模式才能启用环回功能。遇到这种情况，需要配置 PHY 驱动程序以满足特定芯片需求，请使用 ESP-IDF 官方支持的 PHY 芯片驱动程序，或参阅 :ref:`Custom PHY Driver ` 小节以创建新的自定义驱动程序。 + 可选的运行时 MAC 时钟配置 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -557,10 +565,12 @@ ESP-IDF 在宏 :c:macro:`ETH_DEFAULT_CONFIG` 中为安装驱动程序提供了 进阶操作 --------------- +.. _custom-phy-driver: + 自定义 PHY 驱动程序 ^^^^^^^^^^^^^^^^^^^^^^^^^ -市面上有多家 PHY 芯片制造商提供各种类型的芯片。ESP-IDF 现已支持数种 PHY 芯片，但是由于价格、功能、库存等原因，有时用户还是无法找到一款能满足其实际需求的芯片。 +市面上有多家 PHY 芯片制造商提供各种类型的芯片。ESP-IDF 现已支持 ``通用 PHY`` 和数种特定的 PHY 芯片，但是由于价格、功能、库存等原因，有时用户还是无法找到一款能满足其实际需求的芯片。 好在 IEEE 802.3 在其 22.2.4 管理功能部分对 EMAC 和 PHY 之间的管理接口进行了标准化。该部分定义了所谓的 ”MII 管理接口”规范，用于控制 PHY 和收集 PHY 的状态，还定义了一组管理寄存器来控制芯片行为、链接属性、自动协商配置等。在 ESP-IDF 中，这项基本的管理功能是由 :component_file:`esp_eth/src/phy/esp_eth_phy_802_3.c` 实现的，这也大大降低了创建新的自定义 PHY 芯片驱动的难度。 From 03d76006b853b3711c07d757b841296402c9b2eb Mon Sep 17 00:00:00 2001 From: Sudeep Mohanty Date: Fri, 11 Oct 2024 11:49:50 +0200 Subject: [PATCH 124/472] fix(freertos): Fixed SMP race condition in stream_buffers.c This commit fixes a race condition in dual-core SMP mode where in the xStreamBufferReceive() makes the xTaskWaitingToReceive NULL but it may have already been evaluated to not be NULL by xStreamBufferSend() running on another core and eventually leading to a crash in tasks.c. --- .../freertos/FreeRTOS-Kernel/idf_changes.md | 2 ++ .../freertos/FreeRTOS-Kernel/stream_buffer.c | 18 +++++++++++++++--- 2 files changed, 17 insertions(+), 3 deletions(-) diff --git a/components/freertos/FreeRTOS-Kernel/idf_changes.md b/components/freertos/FreeRTOS-Kernel/idf_changes.md index a3ef8454601..83bee684332 100644 --- a/components/freertos/FreeRTOS-Kernel/idf_changes.md +++ b/components/freertos/FreeRTOS-Kernel/idf_changes.md @@ -123,6 +123,8 @@ The following functions were modified to accommodate SMP behavior: - In SMP, the function now disables interrupts to ensure that the calling task does not switch cores while checking its own copy of `uxSchedulerSuspended`. - `prvAddCurrentTaskToDelayedList()` - Added extra check to see if current blocking task has already been deleted by the other core. +- `xStreamBufferReceive()` + - Added a critical section for setting `xTaskWaitingToReceive` to `NULL` so that the write is SMP safe. ### Critical Section Changes diff --git a/components/freertos/FreeRTOS-Kernel/stream_buffer.c b/components/freertos/FreeRTOS-Kernel/stream_buffer.c index 50c2fb13cae..988eb3f5f7f 100644 --- a/components/freertos/FreeRTOS-Kernel/stream_buffer.c +++ b/components/freertos/FreeRTOS-Kernel/stream_buffer.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: MIT * - * SPDX-FileContributor: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileContributor: 2023-2024 Espressif Systems (Shanghai) CO LTD * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -977,7 +977,19 @@ size_t xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, /* Wait for data to be available. */ traceBLOCKING_ON_STREAM_BUFFER_RECEIVE( xStreamBuffer ); ( void ) xTaskNotifyWait( ( uint32_t ) 0, ( uint32_t ) 0, NULL, xTicksToWait ); - pxStreamBuffer->xTaskWaitingToReceive = NULL; + + /* In SMP mode, the task may have been woken and scheduled on + * another core. Hence, we must clear the xTaskWaitingToReceive + * handle in a critical section. */ + #if ( configNUMBER_OF_CORES > 1 ) + taskENTER_CRITICAL( &( pxStreamBuffer->xStreamBufferLock ) ); + #endif /* configNUMBER_OF_CORES > 1 */ + { + pxStreamBuffer->xTaskWaitingToReceive = NULL; + } + #if ( configNUMBER_OF_CORES > 1 ) + taskEXIT_CRITICAL( &( pxStreamBuffer->xStreamBufferLock ) ); + #endif /* configNUMBER_OF_CORES > 1 */ /* Recheck the data available after blocking. */ xBytesAvailable = prvBytesInBuffer( pxStreamBuffer ); @@ -1421,7 +1433,7 @@ static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer, * result in confusion as to what is actually being observed. */ const BaseType_t xWriteValue = 0x55; configASSERT( memset( pucBuffer, ( int ) xWriteValue, xBufferSizeBytes ) == pucBuffer ); - (void)xWriteValue; + ( void ) xWriteValue; } /*lint !e529 !e438 xWriteValue is only used if configASSERT() is defined. */ #endif From e2241f1fc115a3d9279e2a9e6a3a5caa23dde1af Mon Sep 17 00:00:00 2001 From: Jin Cheng Date: Fri, 27 Sep 2024 16:03:34 +0800 Subject: [PATCH 125/472] fix(bt/controller): Fixed some controller bugs on ESP32 - Fixed access NULL in SCO frame end Closes https://jira.espressif.com:8443/browse/IDFGH-10796 - Added LAP checking for Periodic Inquiry - Removed an inproper assertion in SCO module - Fixed wrong logic in key exchange when LMP transaction collision occurred - Fixed the using of wrong error code in the transaction collision of role switch --- components/bt/controller/lib_esp32 | 2 +- components/esp_rom/esp32/ld/esp32.rom.ld | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/components/bt/controller/lib_esp32 b/components/bt/controller/lib_esp32 index 22a4e62193e..f5114d2a70e 160000 --- a/components/bt/controller/lib_esp32 +++ b/components/bt/controller/lib_esp32 @@ -1 +1 @@ -Subproject commit 22a4e62193eb8bf9c747c9ec826fece57b40c042 +Subproject commit f5114d2a70e33a352adc5a3ad5d44c8537aa13da diff --git a/components/esp_rom/esp32/ld/esp32.rom.ld b/components/esp_rom/esp32/ld/esp32.rom.ld index b47c3140b89..a24ff27f071 100644 --- a/components/esp_rom/esp32/ld/esp32.rom.ld +++ b/components/esp_rom/esp32/ld/esp32.rom.ld @@ -1368,6 +1368,7 @@ PROVIDE ( esp_rom_spiflash_config_clk = 0x40062bc8 ); PROVIDE ( g_rom_spiflash_chip = 0x3ffae270 ); PROVIDE ( SPI_write_enable = 0x40062320 ); PROVIDE ( hci_le_rd_rem_used_feats_cmd_handler = 0x400417b4 ); +PROVIDE ( hci_per_inq_mode_cmd_handler = 0x400519b0 ); PROVIDE ( llcp_length_req_handler = 0x40043808 ); PROVIDE ( llcp_unknown_rsp_handler = 0x40043ba8 ); PROVIDE ( llcp_channel_map_req_handler = 0x4004291c ); From fa8d73861b201a74b032085bfa7f0023a28226e8 Mon Sep 17 00:00:00 2001 From: laokaiyao Date: Fri, 6 Sep 2024 16:47:13 +0800 Subject: [PATCH 126/472] refactor(soc): sort esp32c2 soc headers --- .../soc/esp32c2/include/soc/dport_access.h | 3 +- .../soc/esp32c2/include/soc/interrupt_reg.h | 2 +- components/soc/esp32c2/include/soc/soc.h | 2 +- components/soc/esp32c2/register/soc/.gitkeep | 0 .../soc/apb_saradc_reg.h | 0 .../soc/apb_saradc_struct.h | 0 .../soc/assist_debug_reg.h | 22 +++++++-------- .../{include => register}/soc/ecc_mult_reg.h | 2 +- .../{include => register}/soc/efuse_reg.h | 4 +-- .../{include => register}/soc/efuse_struct.h | 2 +- .../{include => register}/soc/extmem_reg.h | 0 .../{include => register}/soc/gdma_reg.h | 0 .../{include => register}/soc/gdma_struct.h | 0 .../{include => register}/soc/gpio_reg.h | 0 .../{include => register}/soc/gpio_struct.h | 0 .../{include => register}/soc/i2c_reg.h | 0 .../{include => register}/soc/i2c_struct.h | 0 .../soc/interrupt_core0_reg.h | 0 .../{include => register}/soc/io_mux_reg.h | 2 +- .../{include => register}/soc/ledc_reg.h | 0 .../{include => register}/soc/ledc_struct.h | 0 .../soc/modem_clkrst_reg.h | 0 .../{include => register}/soc/reg_base.h | 2 +- .../{include => register}/soc/rtc_cntl_reg.h | 4 +-- .../soc/rtc_cntl_struct.h | 2 +- .../{include => register}/soc/sensitive_reg.h | 0 .../soc/sensitive_struct.h | 0 .../{include => register}/soc/spi_mem_reg.h | 28 +++++++++---------- .../soc/spi_mem_struct.h | 4 +-- .../{include => register}/soc/spi_reg.h | 16 +++++------ .../{include => register}/soc/spi_struct.h | 6 ++-- .../{include => register}/soc/syscon_reg.h | 2 +- .../{include => register}/soc/syscon_struct.h | 0 .../{include => register}/soc/system_reg.h | 0 .../{include => register}/soc/system_struct.h | 0 .../{include => register}/soc/systimer_reg.h | 0 .../soc/systimer_struct.h | 0 .../soc/timer_group_reg.h | 0 .../soc/timer_group_struct.h | 0 .../{include => register}/soc/uart_reg.h | 20 ++++++------- .../{include => register}/soc/uart_struct.h | 10 +++---- .../{include => register}/soc/xts_aes_reg.h | 2 +- 42 files changed, 67 insertions(+), 68 deletions(-) delete mode 100644 components/soc/esp32c2/register/soc/.gitkeep rename components/soc/esp32c2/{include => register}/soc/apb_saradc_reg.h (100%) rename components/soc/esp32c2/{include => register}/soc/apb_saradc_struct.h (100%) rename components/soc/esp32c2/{include => register}/soc/assist_debug_reg.h (95%) rename components/soc/esp32c2/{include => register}/soc/ecc_mult_reg.h (99%) rename components/soc/esp32c2/{include => register}/soc/efuse_reg.h (99%) rename components/soc/esp32c2/{include => register}/soc/efuse_struct.h (99%) rename components/soc/esp32c2/{include => register}/soc/extmem_reg.h (100%) rename components/soc/esp32c2/{include => register}/soc/gdma_reg.h (100%) rename components/soc/esp32c2/{include => register}/soc/gdma_struct.h (100%) rename components/soc/esp32c2/{include => register}/soc/gpio_reg.h (100%) rename components/soc/esp32c2/{include => register}/soc/gpio_struct.h (100%) rename components/soc/esp32c2/{include => register}/soc/i2c_reg.h (100%) rename components/soc/esp32c2/{include => register}/soc/i2c_struct.h (100%) rename components/soc/esp32c2/{include => register}/soc/interrupt_core0_reg.h (100%) rename components/soc/esp32c2/{include => register}/soc/io_mux_reg.h (99%) rename components/soc/esp32c2/{include => register}/soc/ledc_reg.h (100%) rename components/soc/esp32c2/{include => register}/soc/ledc_struct.h (100%) rename components/soc/esp32c2/{include => register}/soc/modem_clkrst_reg.h (100%) rename components/soc/esp32c2/{include => register}/soc/reg_base.h (97%) rename components/soc/esp32c2/{include => register}/soc/rtc_cntl_reg.h (99%) rename components/soc/esp32c2/{include => register}/soc/rtc_cntl_struct.h (99%) rename components/soc/esp32c2/{include => register}/soc/sensitive_reg.h (100%) rename components/soc/esp32c2/{include => register}/soc/sensitive_struct.h (100%) rename components/soc/esp32c2/{include => register}/soc/spi_mem_reg.h (99%) rename components/soc/esp32c2/{include => register}/soc/spi_mem_struct.h (99%) rename components/soc/esp32c2/{include => register}/soc/spi_reg.h (99%) rename components/soc/esp32c2/{include => register}/soc/spi_struct.h (99%) rename components/soc/esp32c2/{include => register}/soc/syscon_reg.h (99%) rename components/soc/esp32c2/{include => register}/soc/syscon_struct.h (100%) rename components/soc/esp32c2/{include => register}/soc/system_reg.h (100%) rename components/soc/esp32c2/{include => register}/soc/system_struct.h (100%) rename components/soc/esp32c2/{include => register}/soc/systimer_reg.h (100%) rename components/soc/esp32c2/{include => register}/soc/systimer_struct.h (100%) rename components/soc/esp32c2/{include => register}/soc/timer_group_reg.h (100%) rename components/soc/esp32c2/{include => register}/soc/timer_group_struct.h (100%) rename components/soc/esp32c2/{include => register}/soc/uart_reg.h (99%) rename components/soc/esp32c2/{include => register}/soc/uart_struct.h (98%) rename components/soc/esp32c2/{include => register}/soc/xts_aes_reg.h (98%) diff --git a/components/soc/esp32c2/include/soc/dport_access.h b/components/soc/esp32c2/include/soc/dport_access.h index 5a847ca4842..e499a791bdd 100644 --- a/components/soc/esp32c2/include/soc/dport_access.h +++ b/components/soc/esp32c2/include/soc/dport_access.h @@ -8,8 +8,7 @@ #define _DPORT_ACCESS_H_ #include -#include "soc.h" -#include "uart_reg.h" +#include "soc/soc.h" #ifdef __cplusplus extern "C" { diff --git a/components/soc/esp32c2/include/soc/interrupt_reg.h b/components/soc/esp32c2/include/soc/interrupt_reg.h index 749a2e92167..d02c2d5c20c 100644 --- a/components/soc/esp32c2/include/soc/interrupt_reg.h +++ b/components/soc/esp32c2/include/soc/interrupt_reg.h @@ -5,7 +5,7 @@ */ #pragma once -#include "interrupt_core0_reg.h" +#include "soc/interrupt_core0_reg.h" #define INTERRUPT_CURRENT_CORE_INT_THRESH_REG INTERRUPT_CORE0_CPU_INT_THRESH_REG #define INTERRUPT_PRIO_REG(n) (INTERRUPT_CORE0_CPU_INT_PRI_0_REG + (n)*4) diff --git a/components/soc/esp32c2/include/soc/soc.h b/components/soc/esp32c2/include/soc/soc.h index a57b15794ae..a24a2b197e6 100644 --- a/components/soc/esp32c2/include/soc/soc.h +++ b/components/soc/esp32c2/include/soc/soc.h @@ -12,7 +12,7 @@ #endif #include "esp_bit_defs.h" -#include "reg_base.h" +#include "soc/reg_base.h" #define PRO_CPU_NUM (0) diff --git a/components/soc/esp32c2/register/soc/.gitkeep b/components/soc/esp32c2/register/soc/.gitkeep deleted file mode 100644 index e69de29bb2d..00000000000 diff --git a/components/soc/esp32c2/include/soc/apb_saradc_reg.h b/components/soc/esp32c2/register/soc/apb_saradc_reg.h similarity index 100% rename from components/soc/esp32c2/include/soc/apb_saradc_reg.h rename to components/soc/esp32c2/register/soc/apb_saradc_reg.h diff --git a/components/soc/esp32c2/include/soc/apb_saradc_struct.h b/components/soc/esp32c2/register/soc/apb_saradc_struct.h similarity index 100% rename from components/soc/esp32c2/include/soc/apb_saradc_struct.h rename to components/soc/esp32c2/register/soc/apb_saradc_struct.h diff --git a/components/soc/esp32c2/include/soc/assist_debug_reg.h b/components/soc/esp32c2/register/soc/assist_debug_reg.h similarity index 95% rename from components/soc/esp32c2/include/soc/assist_debug_reg.h rename to components/soc/esp32c2/register/soc/assist_debug_reg.h index 2734f5e2984..bee2070557c 100644 --- a/components/soc/esp32c2/include/soc/assist_debug_reg.h +++ b/components/soc/esp32c2/register/soc/assist_debug_reg.h @@ -15,14 +15,14 @@ extern "C" { */ #define ASSIST_DEBUG_CORE_0_INTR_ENA_REG (DR_REG_ASSIST_DEBUG_BASE + 0x0) /** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA : R/W; bitpos: [0]; default: 0; - * enbale sp underlow monitor + * enable sp underflow monitor */ #define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA (BIT(0)) #define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_S) #define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_V 0x00000001U #define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_S 0 /** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA : R/W; bitpos: [1]; default: 0; - * enbale sp overflow monitor + * enable sp overflow monitor */ #define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA (BIT(1)) #define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_S) @@ -34,14 +34,14 @@ extern "C" { */ #define ASSIST_DEBUG_CORE_0_INTR_RAW_REG (DR_REG_ASSIST_DEBUG_BASE + 0x4) /** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW : RO; bitpos: [0]; default: 0; - * sp underlow monitor interrupt status register + * sp underflow monitor interrupt status register */ #define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW (BIT(0)) #define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_S) #define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_V 0x00000001U #define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_S 0 /** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW : RO; bitpos: [1]; default: 0; - * sp overflow monitor interupt status register + * sp overflow monitor interrupt status register */ #define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW (BIT(1)) #define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_S) @@ -53,14 +53,14 @@ extern "C" { */ #define ASSIST_DEBUG_CORE_0_INTR_RLS_REG (DR_REG_ASSIST_DEBUG_BASE + 0x8) /** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS : R/W; bitpos: [0]; default: 0; - * enbale sp underlow monitor interrupt + * enable sp underflow monitor interrupt */ #define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS (BIT(0)) #define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_S) #define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_V 0x00000001U #define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_S 0 /** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS : R/W; bitpos: [1]; default: 0; - * enbale sp overflow monitor interrupt + * enable sp overflow monitor interrupt */ #define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS (BIT(1)) #define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_S) @@ -72,7 +72,7 @@ extern "C" { */ #define ASSIST_DEBUG_CORE_0_INTR_CLR_REG (DR_REG_ASSIST_DEBUG_BASE + 0xc) /** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR : WT; bitpos: [0]; default: 0; - * clr sp underlow monitor interrupt + * clr sp underflow monitor interrupt */ #define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR (BIT(0)) #define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_S) @@ -91,7 +91,7 @@ extern "C" { */ #define ASSIST_DEBUG_CORE_0_SP_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x10) /** ASSIST_DEBUG_CORE_0_SP_MIN : R/W; bitpos: [31:0]; default: 0; - * core0 sp region configuration regsiter + * core0 sp region configuration register */ #define ASSIST_DEBUG_CORE_0_SP_MIN 0xFFFFFFFFU #define ASSIST_DEBUG_CORE_0_SP_MIN_M (ASSIST_DEBUG_CORE_0_SP_MIN_V << ASSIST_DEBUG_CORE_0_SP_MIN_S) @@ -115,7 +115,7 @@ extern "C" { */ #define ASSIST_DEBUG_CORE_0_SP_PC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x18) /** ASSIST_DEBUG_CORE_0_SP_PC : RO; bitpos: [31:0]; default: 0; - * This regsiter stores the PC when trigger stack monitor. + * This register stores the PC when trigger stack monitor. */ #define ASSIST_DEBUG_CORE_0_SP_PC 0xFFFFFFFFU #define ASSIST_DEBUG_CORE_0_SP_PC_M (ASSIST_DEBUG_CORE_0_SP_PC_V << ASSIST_DEBUG_CORE_0_SP_PC_S) @@ -142,7 +142,7 @@ extern "C" { #define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_S 1 /** ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG register - * record status regsiter + * record status register */ #define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x20) /** ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC : RO; bitpos: [31:0]; default: 0; @@ -154,7 +154,7 @@ extern "C" { #define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_S 0 /** ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG register - * record status regsiter + * record status register */ #define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG (DR_REG_ASSIST_DEBUG_BASE + 0x24) /** ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP : RO; bitpos: [31:0]; default: 0; diff --git a/components/soc/esp32c2/include/soc/ecc_mult_reg.h b/components/soc/esp32c2/register/soc/ecc_mult_reg.h similarity index 99% rename from components/soc/esp32c2/include/soc/ecc_mult_reg.h rename to components/soc/esp32c2/register/soc/ecc_mult_reg.h index 906a91b7af7..cb4bf5797b9 100644 --- a/components/soc/esp32c2/include/soc/ecc_mult_reg.h +++ b/components/soc/esp32c2/register/soc/ecc_mult_reg.h @@ -5,7 +5,7 @@ */ #pragma once -#include "soc.h" +#include "soc/soc.h" #ifdef __cplusplus extern "C" { diff --git a/components/soc/esp32c2/include/soc/efuse_reg.h b/components/soc/esp32c2/register/soc/efuse_reg.h similarity index 99% rename from components/soc/esp32c2/include/soc/efuse_reg.h rename to components/soc/esp32c2/register/soc/efuse_reg.h index 6f13f2a2bae..8471fef930a 100644 --- a/components/soc/esp32c2/include/soc/efuse_reg.h +++ b/components/soc/esp32c2/register/soc/efuse_reg.h @@ -7,7 +7,7 @@ #include #include "soc/soc.h" -#include "efuse_defs.h" +#include "soc/efuse_defs.h" #ifdef __cplusplus extern "C" { #endif @@ -896,7 +896,7 @@ extern "C" { #define EFUSE_CLK_EN_S 16 /** EFUSE_CONF_REG register - * eFuse operation mode configuraiton register + * eFuse operation mode configuration register */ #define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x8c) /** EFUSE_OP_CODE : R/W; bitpos: [15:0]; default: 0; diff --git a/components/soc/esp32c2/include/soc/efuse_struct.h b/components/soc/esp32c2/register/soc/efuse_struct.h similarity index 99% rename from components/soc/esp32c2/include/soc/efuse_struct.h rename to components/soc/esp32c2/register/soc/efuse_struct.h index c30ded3f9c9..fa1800be944 100644 --- a/components/soc/esp32c2/include/soc/efuse_struct.h +++ b/components/soc/esp32c2/register/soc/efuse_struct.h @@ -745,7 +745,7 @@ typedef union { } efuse_clk_reg_t; /** Type of conf register - * eFuse operation mode configuraiton register + * eFuse operation mode configuration register */ typedef union { struct { diff --git a/components/soc/esp32c2/include/soc/extmem_reg.h b/components/soc/esp32c2/register/soc/extmem_reg.h similarity index 100% rename from components/soc/esp32c2/include/soc/extmem_reg.h rename to components/soc/esp32c2/register/soc/extmem_reg.h diff --git a/components/soc/esp32c2/include/soc/gdma_reg.h b/components/soc/esp32c2/register/soc/gdma_reg.h similarity index 100% rename from components/soc/esp32c2/include/soc/gdma_reg.h rename to components/soc/esp32c2/register/soc/gdma_reg.h diff --git a/components/soc/esp32c2/include/soc/gdma_struct.h b/components/soc/esp32c2/register/soc/gdma_struct.h similarity index 100% rename from components/soc/esp32c2/include/soc/gdma_struct.h rename to components/soc/esp32c2/register/soc/gdma_struct.h diff --git a/components/soc/esp32c2/include/soc/gpio_reg.h b/components/soc/esp32c2/register/soc/gpio_reg.h similarity index 100% rename from components/soc/esp32c2/include/soc/gpio_reg.h rename to components/soc/esp32c2/register/soc/gpio_reg.h diff --git a/components/soc/esp32c2/include/soc/gpio_struct.h b/components/soc/esp32c2/register/soc/gpio_struct.h similarity index 100% rename from components/soc/esp32c2/include/soc/gpio_struct.h rename to components/soc/esp32c2/register/soc/gpio_struct.h diff --git a/components/soc/esp32c2/include/soc/i2c_reg.h b/components/soc/esp32c2/register/soc/i2c_reg.h similarity index 100% rename from components/soc/esp32c2/include/soc/i2c_reg.h rename to components/soc/esp32c2/register/soc/i2c_reg.h diff --git a/components/soc/esp32c2/include/soc/i2c_struct.h b/components/soc/esp32c2/register/soc/i2c_struct.h similarity index 100% rename from components/soc/esp32c2/include/soc/i2c_struct.h rename to components/soc/esp32c2/register/soc/i2c_struct.h diff --git a/components/soc/esp32c2/include/soc/interrupt_core0_reg.h b/components/soc/esp32c2/register/soc/interrupt_core0_reg.h similarity index 100% rename from components/soc/esp32c2/include/soc/interrupt_core0_reg.h rename to components/soc/esp32c2/register/soc/interrupt_core0_reg.h diff --git a/components/soc/esp32c2/include/soc/io_mux_reg.h b/components/soc/esp32c2/register/soc/io_mux_reg.h similarity index 99% rename from components/soc/esp32c2/include/soc/io_mux_reg.h rename to components/soc/esp32c2/register/soc/io_mux_reg.h index b54614e4778..7a59d046f7f 100644 --- a/components/soc/esp32c2/include/soc/io_mux_reg.h +++ b/components/soc/esp32c2/register/soc/io_mux_reg.h @@ -7,7 +7,7 @@ #define _SOC_IO_MUX_REG_H_ #pragma once -#include "soc.h" +#include "soc/soc.h" /* The following are the bit fields for PERIPHS_IO_MUX_x_U registers */ /* Output enable in sleep mode */ diff --git a/components/soc/esp32c2/include/soc/ledc_reg.h b/components/soc/esp32c2/register/soc/ledc_reg.h similarity index 100% rename from components/soc/esp32c2/include/soc/ledc_reg.h rename to components/soc/esp32c2/register/soc/ledc_reg.h diff --git a/components/soc/esp32c2/include/soc/ledc_struct.h b/components/soc/esp32c2/register/soc/ledc_struct.h similarity index 100% rename from components/soc/esp32c2/include/soc/ledc_struct.h rename to components/soc/esp32c2/register/soc/ledc_struct.h diff --git a/components/soc/esp32c2/include/soc/modem_clkrst_reg.h b/components/soc/esp32c2/register/soc/modem_clkrst_reg.h similarity index 100% rename from components/soc/esp32c2/include/soc/modem_clkrst_reg.h rename to components/soc/esp32c2/register/soc/modem_clkrst_reg.h diff --git a/components/soc/esp32c2/include/soc/reg_base.h b/components/soc/esp32c2/register/soc/reg_base.h similarity index 97% rename from components/soc/esp32c2/include/soc/reg_base.h rename to components/soc/esp32c2/register/soc/reg_base.h index b410fbb3f3d..34b56a9d95b 100644 --- a/components/soc/esp32c2/include/soc/reg_base.h +++ b/components/soc/esp32c2/register/soc/reg_base.h @@ -43,5 +43,5 @@ #define DR_REG_I2C_MST_BASE 0x6004E800 #define DR_REG_XTS_AES_BASE 0x600CC000 -/* For backward compatability with the older register name */ +/* For backward compatibility with the older register name */ #define DR_REG_AES_XTS_BASE DR_REG_XTS_AES_BASE diff --git a/components/soc/esp32c2/include/soc/rtc_cntl_reg.h b/components/soc/esp32c2/register/soc/rtc_cntl_reg.h similarity index 99% rename from components/soc/esp32c2/include/soc/rtc_cntl_reg.h rename to components/soc/esp32c2/register/soc/rtc_cntl_reg.h index e5ce9bff061..2a9a5659f7f 100644 --- a/components/soc/esp32c2/include/soc/rtc_cntl_reg.h +++ b/components/soc/esp32c2/register/soc/rtc_cntl_reg.h @@ -9,7 +9,7 @@ #ifdef __cplusplus extern "C" { #endif -#include "soc.h" +#include "soc/soc.h" #define RTC_CNTL_TIME0_REG RTC_CNTL_TIME_LOW0_REG #define RTC_CNTL_TIME1_REG RTC_CNTL_TIME_HIGH0_REG @@ -1144,7 +1144,7 @@ RO CPU.*/ #define RTC_CNTL_SWD_AUTO_FEED_EN_V 0x1 #define RTC_CNTL_SWD_AUTO_FEED_EN_S 31 /* RTC_CNTL_SWD_DISABLE : ;bitpos:[30] ;default: 1'b0 ; */ -/*description: disabel SWD.*/ +/*description: disable SWD.*/ #define RTC_CNTL_SWD_DISABLE (BIT(30)) #define RTC_CNTL_SWD_DISABLE_M (BIT(30)) #define RTC_CNTL_SWD_DISABLE_V 0x1 diff --git a/components/soc/esp32c2/include/soc/rtc_cntl_struct.h b/components/soc/esp32c2/register/soc/rtc_cntl_struct.h similarity index 99% rename from components/soc/esp32c2/include/soc/rtc_cntl_struct.h rename to components/soc/esp32c2/register/soc/rtc_cntl_struct.h index 89a7820dc27..5252040c3f0 100644 --- a/components/soc/esp32c2/include/soc/rtc_cntl_struct.h +++ b/components/soc/esp32c2/register/soc/rtc_cntl_struct.h @@ -399,7 +399,7 @@ typedef volatile struct rtc_cntl_dev_s{ uint32_t swd_signal_width : 10; /*adjust signal width send to swd*/ uint32_t swd_rst_flag_clr : 1; /*reset swd reset flag*/ uint32_t swd_feed : 1; /*Sw feed swd*/ - uint32_t swd_disable : 1; /*disabel SWD*/ + uint32_t swd_disable : 1; /*disable SWD*/ uint32_t swd_auto_feed_en : 1; /*automatically feed swd when int comes*/ }; uint32_t val; diff --git a/components/soc/esp32c2/include/soc/sensitive_reg.h b/components/soc/esp32c2/register/soc/sensitive_reg.h similarity index 100% rename from components/soc/esp32c2/include/soc/sensitive_reg.h rename to components/soc/esp32c2/register/soc/sensitive_reg.h diff --git a/components/soc/esp32c2/include/soc/sensitive_struct.h b/components/soc/esp32c2/register/soc/sensitive_struct.h similarity index 100% rename from components/soc/esp32c2/include/soc/sensitive_struct.h rename to components/soc/esp32c2/register/soc/sensitive_struct.h diff --git a/components/soc/esp32c2/include/soc/spi_mem_reg.h b/components/soc/esp32c2/register/soc/spi_mem_reg.h similarity index 99% rename from components/soc/esp32c2/include/soc/spi_mem_reg.h rename to components/soc/esp32c2/register/soc/spi_mem_reg.h index bd22f94efb1..8eeb65b014f 100644 --- a/components/soc/esp32c2/include/soc/spi_mem_reg.h +++ b/components/soc/esp32c2/register/soc/spi_mem_reg.h @@ -7,7 +7,7 @@ #define _SOC_SPI_MEM_REG_H_ -#include "soc.h" +#include "soc/soc.h" #ifdef __cplusplus extern "C" { #endif @@ -94,15 +94,15 @@ he bit will be cleared once the operation done.1: enable 0: disable..*/ #define SPI_MEM_FLASH_DP_S 21 /* SPI_MEM_FLASH_RES : R/W/SC ;bitpos:[20] ;default: 1'b0 ; */ /*description: This bit combined with reg_resandres bit releases Flash from the power-down stat -e or high performance mode and obtains the devices ID. The bit will be cleared o -nce the operation done.1: enable 0: disable..*/ +e or high performance mode and obtains the devices ID. The bit will be cleared once +the operation done.1: enable 0: disable..*/ #define SPI_MEM_FLASH_RES (BIT(20)) #define SPI_MEM_FLASH_RES_M (BIT(20)) #define SPI_MEM_FLASH_RES_V 0x1 #define SPI_MEM_FLASH_RES_S 20 /* SPI_MEM_FLASH_HPM : R/W/SC ;bitpos:[19] ;default: 1'b0 ; */ -/*description: Drive Flash into high performance mode. The bit will be cleared once the operat -ion done.1: enable 0: disable..*/ +/*description: Drive Flash into high performance mode. The bit will be cleared once the operation +done.1: enable 0: disable..*/ #define SPI_MEM_FLASH_HPM (BIT(19)) #define SPI_MEM_FLASH_HPM_M (BIT(19)) #define SPI_MEM_FLASH_HPM_V 0x1 @@ -123,8 +123,8 @@ peration done.1: enable 0: disable..*/ #define SPI_MEM_FLASH_PE_V 0x1 #define SPI_MEM_FLASH_PE_S 17 /* SPI_MEM_MSPI_ST : RO ;bitpos:[7:4] ;default: 4'b0 ; */ -/*description: The current status of SPI1 slave FSM: mspi_st. 0: idle state, 1: preparation sta -te, 2: send command state, 3: send address state, 4: wait state, 5: read data st +/*description: The current status of SPI1 slave FSM: mspi_st. 0: idle state, 1: preparation +state, 2: send command state, 3: send address state, 4: wait state, 5: read data st ate, 6:write data state, 7: done state, 8: read data end state..*/ #define SPI_MEM_MSPI_ST 0x0000000F #define SPI_MEM_MSPI_ST_M ((SPI_MEM_MSPI_ST_V)<<(SPI_MEM_MSPI_ST_S)) @@ -213,14 +213,14 @@ UT AND SPI_MEM_FREAD_DOUT. 1: enable 0: disable..*/ #define SPI_MEM_FASTRD_MODE_V 0x1 #define SPI_MEM_FASTRD_MODE_S 13 /* SPI_MEM_TX_CRC_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disabl +/*description: For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disable e.*/ #define SPI_MEM_TX_CRC_EN (BIT(11)) #define SPI_MEM_TX_CRC_EN_M (BIT(11)) #define SPI_MEM_TX_CRC_EN_V 0x1 #define SPI_MEM_TX_CRC_EN_S 11 /* SPI_MEM_FCS_CRC_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: For SPI1, initialize crc32 module before writing encrypted data to flash. Activ +/*description: For SPI1, initialize crc32 module before writing encrypted data to flash. Active e low..*/ #define SPI_MEM_FCS_CRC_EN (BIT(10)) #define SPI_MEM_FCS_CRC_EN_M (BIT(10)) @@ -262,7 +262,7 @@ e low..*/ /* SPI_MEM_CLK_MODE : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ /*description: SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delaye d one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inacti -ve 3: SPI clock is alwasy on..*/ +ve 3: SPI clock is always on..*/ #define SPI_MEM_CLK_MODE 0x00000003 #define SPI_MEM_CLK_MODE_M ((SPI_MEM_CLK_MODE_V)<<(SPI_MEM_CLK_MODE_S)) #define SPI_MEM_CLK_MODE_V 0x3 @@ -822,7 +822,7 @@ out, status_in[15:0] is valid when two bytes of data are read out), SUS/SUS1/SUS #define SPI_MEM_FLASH_PES_EN_S 5 /* SPI_MEM_PES_PER_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */ /*description: Set this bit to enable PES end triggers PER transfer option. If this bit is 0, a -pplication should send PER after PES is done..*/ +application should send PER after PES is done..*/ #define SPI_MEM_PES_PER_EN (BIT(4)) #define SPI_MEM_PES_PER_EN_M (BIT(4)) #define SPI_MEM_PES_PER_EN_V 0x1 @@ -844,8 +844,8 @@ resume command is sent..*/ #define SPI_MEM_FLASH_PER_WAIT_EN_V 0x1 #define SPI_MEM_FLASH_PER_WAIT_EN_S 2 /* SPI_MEM_FLASH_PES : R/W/SC ;bitpos:[1] ;default: 1'b0 ; */ -/*description: program erase suspend bit, program erase suspend operation will be triggered whe -n the bit is set. The bit will be cleared once the operation done.1: enable 0: d +/*description: program erase suspend bit, program erase suspend operation will be triggered when +the bit is set. The bit will be cleared once the operation done.1: enable 0: d isable..*/ #define SPI_MEM_FLASH_PES (BIT(1)) #define SPI_MEM_FLASH_PES_M (BIT(1)) @@ -1148,7 +1148,7 @@ ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/ #define SPI_MEM_INT_RAW_REG(i) (REG_SPI_MEM_BASE(i) + 0xC8) /* SPI_MEM_BROWN_OUT_INT_RAW : R/WTC/SS ;bitpos:[5] ;default: 1'b0 ; */ /*description: The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that -chip is loosing power and RTC module sends out brown out close flash request to +chip is losing power and RTC module sends out brown out close flash request to SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered and MSPI returns to idle state. 0: Others..*/ #define SPI_MEM_BROWN_OUT_INT_RAW (BIT(5)) diff --git a/components/soc/esp32c2/include/soc/spi_mem_struct.h b/components/soc/esp32c2/register/soc/spi_mem_struct.h similarity index 99% rename from components/soc/esp32c2/include/soc/spi_mem_struct.h rename to components/soc/esp32c2/register/soc/spi_mem_struct.h index c2cc1c5010a..230c292b4b2 100644 --- a/components/soc/esp32c2/include/soc/spi_mem_struct.h +++ b/components/soc/esp32c2/register/soc/spi_mem_struct.h @@ -64,7 +64,7 @@ typedef volatile struct spi_mem_dev_s{ } ctrl; union { struct { - uint32_t clk_mode : 2; /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on.*/ + uint32_t clk_mode : 2; /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is always on.*/ uint32_t cs_hold_dly_res : 10; /*After RES/DP/HPM command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 512) SPI_CLK cycles.*/ uint32_t reserved2 : 18; /*reserved*/ uint32_t rxfifo_rst : 1; /*SPI0 RX FIFO reset signal.*/ @@ -322,7 +322,7 @@ typedef volatile struct spi_mem_dev_s{ uint32_t wpe_end : 1; /*The raw bit for SPI_MEM_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE is sent and flash is already idle. 0: Others.*/ uint32_t slv_st_end : 1; /*The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st is changed from non idle state to idle state. It means that SPI_CS raises high. 0: Others*/ uint32_t mst_st_end : 1; /*The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st is changed from non idle state to idle state. 0: Others.*/ - uint32_t brown_out : 1; /*The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that chip is loosing power and RTC module sends out brown out close flash request to SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered and MSPI returns to idle state. 0: Others.*/ + uint32_t brown_out : 1; /*The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that chip is losing power and RTC module sends out brown out close flash request to SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered and MSPI returns to idle state. 0: Others.*/ uint32_t reserved6 : 26; /*reserved*/ }; uint32_t val; diff --git a/components/soc/esp32c2/include/soc/spi_reg.h b/components/soc/esp32c2/register/soc/spi_reg.h similarity index 99% rename from components/soc/esp32c2/include/soc/spi_reg.h rename to components/soc/esp32c2/register/soc/spi_reg.h index eaa92535e1e..29293c94699 100644 --- a/components/soc/esp32c2/include/soc/spi_reg.h +++ b/components/soc/esp32c2/register/soc/spi_reg.h @@ -159,7 +159,7 @@ e, the FSPI bus signals are output. Can be configured in CONF state..*/ #define SPI_CLOCK_REG(i) (REG_SPI_BASE(i) + 0xC) /* SPI_CLK_EQU_SYSCLK : R/W ;bitpos:[31] ;default: 1'b1 ; */ -/*description: In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from syst +/*description: In the master mode 1: spi_clk is equal to system 0: spi_clk is divided from syst em clock. Can be configured in CONF state..*/ #define SPI_CLK_EQU_SYSCLK (BIT(31)) #define SPI_CLK_EQU_SYSCLK_M (BIT(31)) @@ -196,15 +196,15 @@ e 0. Can be configured in CONF state..*/ #define SPI_USER_REG(i) (REG_SPI_BASE(i) + 0x10) /* SPI_USR_COMMAND : R/W ;bitpos:[31] ;default: 1'b1 ; */ -/*description: This bit enable the command phase of an operation. Can be configured in CONF sta -te..*/ +/*description: This bit enable the command phase of an operation. Can be configured in CONF +state..*/ #define SPI_USR_COMMAND (BIT(31)) #define SPI_USR_COMMAND_M (BIT(31)) #define SPI_USR_COMMAND_V 0x1 #define SPI_USR_COMMAND_S 31 /* SPI_USR_ADDR : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: This bit enable the address phase of an operation. Can be configured in CONF sta -te..*/ +/*description: This bit enable the address phase of an operation. Can be configured in CONF +state..*/ #define SPI_USR_ADDR (BIT(30)) #define SPI_USR_ADDR_M (BIT(30)) #define SPI_USR_ADDR_V 0x1 @@ -392,7 +392,7 @@ n be configured in CONF state..*/ #define SPI_USR_COMMAND_BITLEN_S 28 /* SPI_MST_REMPTY_ERR_END_EN : R/W ;bitpos:[27] ;default: 1'b1 ; */ /*description: 1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI m -aster FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty erro +aster FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error r is valid in GP-SPI master FD/HD-mode..*/ #define SPI_MST_REMPTY_ERR_END_EN (BIT(27)) #define SPI_MST_REMPTY_ERR_END_EN_M (BIT(27)) @@ -1113,7 +1113,7 @@ AFIFO read-empty error when SPI outputs data in master mode. 0: Others..*/ #define SPI_SLV_CMD_ERR_INT_RAW_V 0x1 #define SPI_SLV_CMD_ERR_INT_RAW_S 16 /* SPI_SLV_BUF_ADDR_ERR_INT_RAW : R/WTC/SS ;bitpos:[15] ;default: 1'b0 ; */ -/*description: The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data addres +/*description: The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address s of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is bigger than 63. 0: Others..*/ #define SPI_SLV_BUF_ADDR_ERR_INT_RAW (BIT(15)) @@ -1684,7 +1684,7 @@ dge 0: output data at tsck posedge.*/ /* SPI_CLK_MODE : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ /*description: SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delaye d one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inacti -ve 3: SPI clock is alwasy on. Can be configured in CONF state..*/ +ve 3: SPI clock is always on. Can be configured in CONF state..*/ #define SPI_CLK_MODE 0x00000003 #define SPI_CLK_MODE_M ((SPI_CLK_MODE_V)<<(SPI_CLK_MODE_S)) #define SPI_CLK_MODE_V 0x3 diff --git a/components/soc/esp32c2/include/soc/spi_struct.h b/components/soc/esp32c2/register/soc/spi_struct.h similarity index 99% rename from components/soc/esp32c2/include/soc/spi_struct.h rename to components/soc/esp32c2/register/soc/spi_struct.h index da359da8450..08920a09e6a 100644 --- a/components/soc/esp32c2/include/soc/spi_struct.h +++ b/components/soc/esp32c2/register/soc/spi_struct.h @@ -10,7 +10,7 @@ #ifdef __cplusplus extern "C" { #endif -#include "soc.h" +#include "soc/soc.h" typedef volatile struct spi_dev_s{ union { @@ -58,7 +58,7 @@ typedef volatile struct spi_dev_s{ uint32_t clkcnt_n : 6; /*In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state.*/ uint32_t clkdiv_pre : 4; /*In the master mode it is pre-divider of spi_clk. Can be configured in CONF state.*/ uint32_t reserved22 : 9; /*reserved*/ - uint32_t clk_equ_sysclk : 1; /*In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock. Can be configured in CONF state.*/ + uint32_t clk_equ_sysclk : 1; /*In the master mode 1: spi_clk is equal to system 0: spi_clk is divided from system clock. Can be configured in CONF state.*/ }; uint32_t val; } clock; @@ -366,7 +366,7 @@ typedef volatile struct spi_dev_s{ uint32_t reserved_dc; union { struct { - uint32_t clk_mode : 2; /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state.*/ + uint32_t clk_mode : 2; /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is always on. Can be configured in CONF state.*/ uint32_t clk_mode_13 : 1; /*{CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7]. 0: support spi clk mode 0 and 2, first edge output data B[1]/B[6].*/ uint32_t rsck_data_out : 1; /*It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge 0: output data at tsck posedge */ uint32_t reserved4 : 4; /*reserved*/ diff --git a/components/soc/esp32c2/include/soc/syscon_reg.h b/components/soc/esp32c2/register/soc/syscon_reg.h similarity index 99% rename from components/soc/esp32c2/include/soc/syscon_reg.h rename to components/soc/esp32c2/register/soc/syscon_reg.h index 9c4f8b5e610..fbbf7706bcb 100644 --- a/components/soc/esp32c2/include/soc/syscon_reg.h +++ b/components/soc/esp32c2/register/soc/syscon_reg.h @@ -10,7 +10,7 @@ #ifdef __cplusplus extern "C" { #endif -#include "soc.h" +#include "soc/soc.h" #define SYSCON_SYSCLK_CONF_REG (DR_REG_SYSCON_BASE + 0x0) /* SYSCON_RST_TICK_CNT : R/W ;bitpos:[12] ;default: 1'b0 ; */ diff --git a/components/soc/esp32c2/include/soc/syscon_struct.h b/components/soc/esp32c2/register/soc/syscon_struct.h similarity index 100% rename from components/soc/esp32c2/include/soc/syscon_struct.h rename to components/soc/esp32c2/register/soc/syscon_struct.h diff --git a/components/soc/esp32c2/include/soc/system_reg.h b/components/soc/esp32c2/register/soc/system_reg.h similarity index 100% rename from components/soc/esp32c2/include/soc/system_reg.h rename to components/soc/esp32c2/register/soc/system_reg.h diff --git a/components/soc/esp32c2/include/soc/system_struct.h b/components/soc/esp32c2/register/soc/system_struct.h similarity index 100% rename from components/soc/esp32c2/include/soc/system_struct.h rename to components/soc/esp32c2/register/soc/system_struct.h diff --git a/components/soc/esp32c2/include/soc/systimer_reg.h b/components/soc/esp32c2/register/soc/systimer_reg.h similarity index 100% rename from components/soc/esp32c2/include/soc/systimer_reg.h rename to components/soc/esp32c2/register/soc/systimer_reg.h diff --git a/components/soc/esp32c2/include/soc/systimer_struct.h b/components/soc/esp32c2/register/soc/systimer_struct.h similarity index 100% rename from components/soc/esp32c2/include/soc/systimer_struct.h rename to components/soc/esp32c2/register/soc/systimer_struct.h diff --git a/components/soc/esp32c2/include/soc/timer_group_reg.h b/components/soc/esp32c2/register/soc/timer_group_reg.h similarity index 100% rename from components/soc/esp32c2/include/soc/timer_group_reg.h rename to components/soc/esp32c2/register/soc/timer_group_reg.h diff --git a/components/soc/esp32c2/include/soc/timer_group_struct.h b/components/soc/esp32c2/register/soc/timer_group_struct.h similarity index 100% rename from components/soc/esp32c2/include/soc/timer_group_struct.h rename to components/soc/esp32c2/register/soc/timer_group_struct.h diff --git a/components/soc/esp32c2/include/soc/uart_reg.h b/components/soc/esp32c2/register/soc/uart_reg.h similarity index 99% rename from components/soc/esp32c2/include/soc/uart_reg.h rename to components/soc/esp32c2/register/soc/uart_reg.h index 0f105fa0b2f..70413882e77 100644 --- a/components/soc/esp32c2/include/soc/uart_reg.h +++ b/components/soc/esp32c2/register/soc/uart_reg.h @@ -10,7 +10,7 @@ #ifdef __cplusplus extern "C" { #endif -#include "soc.h" +#include "soc/soc.h" #define UART_FIFO_REG(i) (REG_UART_BASE(i) + 0x0) /* UART_RXFIFO_RD_BYTE : RO ;bitpos:[7:0] ;default: 8'b0 ; */ @@ -92,7 +92,7 @@ NULL characters, after all data in Tx-FIFO are sent..*/ #define UART_SW_XOFF_INT_RAW_V 0x1 #define UART_SW_XOFF_INT_RAW_S 10 /* UART_SW_XON_INT_RAW : R/WTC/SS ;bitpos:[9] ;default: 1'b0 ; */ -/*description: This interrupt raw bit turns to high level when receiver recevies Xon char when +/*description: This interrupt raw bit turns to high level when receiver receives Xon char when uart_sw_flow_con_en is set to 1..*/ #define UART_SW_XON_INT_RAW (BIT(9)) #define UART_SW_XON_INT_RAW_M (BIT(9)) @@ -205,7 +205,7 @@ t to 1..*/ #define UART_TX_DONE_INT_ST_V 0x1 #define UART_TX_DONE_INT_ST_S 14 /* UART_TX_BRK_IDLE_DONE_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_en +/*description: This is the status bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_en a is set to 1..*/ #define UART_TX_BRK_IDLE_DONE_INT_ST (BIT(13)) #define UART_TX_BRK_IDLE_DONE_INT_ST_M (BIT(13)) @@ -744,7 +744,7 @@ ansmitter's 11th bit to 0..*/ #define UART_IRDA_DPLX_V 0x1 #define UART_IRDA_DPLX_S 9 /* UART_TXD_BRK : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: Set this bit to enbale transmitter to send NULL when the process of sending dat +/*description: Set this bit to enable transmitter to send NULL when the process of sending dat a is done..*/ #define UART_TXD_BRK (BIT(8)) #define UART_TXD_BRK_M (BIT(8)) @@ -791,7 +791,7 @@ ware flow control..*/ #define UART_CONF1_REG(i) (REG_UART_BASE(i) + 0x24) /* UART_RX_TOUT_EN : R/W ;bitpos:[21] ;default: 1'b0 ; */ -/*description: This is the enble bit for uart receiver's timeout function..*/ +/*description: This is the enable bit for uart receiver's timeout function..*/ #define UART_RX_TOUT_EN (BIT(21)) #define UART_RX_TOUT_EN_M (BIT(21)) #define UART_RX_TOUT_EN_V 0x1 @@ -840,7 +840,7 @@ se. It is used in baud rate-detect process..*/ #define UART_HIGHPULSE_REG(i) (REG_UART_BASE(i) + 0x2C) /* UART_HIGHPULSE_MIN_CNT : RO ;bitpos:[11:0] ;default: 12'hfff ; */ -/*description: This register stores the value of the maxinum duration time for the high level +/*description: This register stores the value of the maximum duration time for the high level pulse. It is used in baud rate-detect process..*/ #define UART_HIGHPULSE_MIN_CNT 0x00000FFF #define UART_HIGHPULSE_MIN_CNT_M ((UART_HIGHPULSE_MIN_CNT_V)<<(UART_HIGHPULSE_MIN_CNT_S)) @@ -898,7 +898,7 @@ t process..*/ #define UART_SLEEP_CONF_REG(i) (REG_UART_BASE(i) + 0x38) /* UART_ACTIVE_THRESHOLD : R/W ;bitpos:[9:0] ;default: 10'hf0 ; */ /*description: The uart is activated from light sleeping mode when the input rxd edge changes m -ore times than this register value..*/ +or times than this register value..*/ #define UART_ACTIVE_THRESHOLD 0x000003FF #define UART_ACTIVE_THRESHOLD_M ((UART_ACTIVE_THRESHOLD_V)<<(UART_ACTIVE_THRESHOLD_S)) #define UART_ACTIVE_THRESHOLD_V 0x3FF @@ -951,8 +951,8 @@ of sending data is done. It is active when txd_brk is set to 1..*/ #define UART_TX_IDLE_NUM_V 0x3FF #define UART_TX_IDLE_NUM_S 10 /* UART_RX_IDLE_THRHD : R/W ;bitpos:[9:0] ;default: 10'h100 ; */ -/*description: It will produce frame end signal when receiver takes more time to receive one by -te data than this register value..*/ +/*description: It will produce frame end signal when receiver takes more time to receive one byte +data than this register value..*/ #define UART_RX_IDLE_THRHD 0x000003FF #define UART_RX_IDLE_THRHD_M ((UART_RX_IDLE_THRHD_V)<<(UART_RX_IDLE_THRHD_S)) #define UART_RX_IDLE_THRHD_V 0x3FF @@ -1066,7 +1066,7 @@ akes more time to receive one byte with rx_tout_en set to 1..*/ #define UART_RX_TOUT_THRHD_V 0x3FF #define UART_RX_TOUT_THRHD_S 16 /* UART_RX_FLOW_THRHD : R/W ;bitpos:[15:7] ;default: 9'h0 ; */ -/*description: This register is used to configure the maximum amount of data that can be receiv +/*description: This register is used to configure the maximum amount of data that can be receive ed when hardware flow control works..*/ #define UART_RX_FLOW_THRHD 0x000001FF #define UART_RX_FLOW_THRHD_M ((UART_RX_FLOW_THRHD_V)<<(UART_RX_FLOW_THRHD_S)) diff --git a/components/soc/esp32c2/include/soc/uart_struct.h b/components/soc/esp32c2/register/soc/uart_struct.h similarity index 98% rename from components/soc/esp32c2/include/soc/uart_struct.h rename to components/soc/esp32c2/register/soc/uart_struct.h index 64c4504e39d..8cc5bdbc876 100644 --- a/components/soc/esp32c2/include/soc/uart_struct.h +++ b/components/soc/esp32c2/register/soc/uart_struct.h @@ -29,7 +29,7 @@ typedef volatile struct uart_dev_s { uint32_t cts_chg : 1; /*This interrupt raw bit turns to high level when receiver detects the edge change of CTSn signal.*/ uint32_t brk_det : 1; /*This interrupt raw bit turns to high level when receiver detects a 0 after the stop bit.*/ uint32_t rxfifo_tout : 1; /*This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte.*/ - uint32_t sw_xon : 1; /*This interrupt raw bit turns to high level when receiver recevies Xon char when uart_sw_flow_con_en is set to 1.*/ + uint32_t sw_xon : 1; /*This interrupt raw bit turns to high level when receiver receives Xon char when uart_sw_flow_con_en is set to 1.*/ uint32_t sw_xoff : 1; /*This interrupt raw bit turns to high level when receiver receives Xoff char when uart_sw_flow_con_en is set to 1.*/ uint32_t glitch_det : 1; /*This interrupt raw bit turns to high level when receiver detects a glitch in the middle of a start bit.*/ uint32_t tx_brk_done : 1; /*This interrupt raw bit turns to high level when transmitter completes sending NULL characters, after all data in Tx-FIFO are sent.*/ @@ -59,7 +59,7 @@ typedef volatile struct uart_dev_s { uint32_t sw_xoff : 1; /*This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.*/ uint32_t glitch_det : 1; /*This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1.*/ uint32_t tx_brk_done : 1; /*This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1.*/ - uint32_t tx_brk_idle_done : 1; /*This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1.*/ + uint32_t tx_brk_idle_done : 1; /*This is the status bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1.*/ uint32_t tx_done : 1; /*This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.*/ uint32_t rs485_parity_err : 1; /*This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is set to 1.*/ uint32_t rs485_frm_err : 1; /*This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is set to 1.*/ @@ -162,7 +162,7 @@ typedef volatile struct uart_dev_s { uint32_t stop_bit_num : 2; /*This register is used to set the length of stop bit.*/ uint32_t sw_rts : 1; /*This register is used to configure the software rts signal which is used in software flow control.*/ uint32_t sw_dtr : 1; /*This register is used to configure the software dtr signal which is used in software flow control.*/ - uint32_t txd_brk : 1; /*Set this bit to enbale transmitter to send NULL when the process of sending data is done.*/ + uint32_t txd_brk : 1; /*Set this bit to enable transmitter to send NULL when the process of sending data is done.*/ uint32_t irda_dplx : 1; /*Set this bit to enable IrDA loopback mode.*/ uint32_t irda_tx_en : 1; /*This is the start enable bit for IrDA transmitter.*/ uint32_t irda_wctl : 1; /*1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA transmitter's 11th bit to 0.*/ @@ -194,7 +194,7 @@ typedef volatile struct uart_dev_s { uint32_t dis_rx_dat_ovf : 1; /*Disable UART Rx data overflow detect. */ uint32_t rx_tout_flow_dis : 1; /*Set this bit to stop accumulating idle_cnt when hardware flow control works.*/ uint32_t rx_flow_en : 1; /*This is the flow enable bit for UART receiver.*/ - uint32_t rx_tout_en : 1; /*This is the enble bit for uart receiver's timeout function.*/ + uint32_t rx_tout_en : 1; /*This is the enable bit for uart receiver's timeout function.*/ uint32_t reserved22 : 10; }; uint32_t val; @@ -208,7 +208,7 @@ typedef volatile struct uart_dev_s { } lowpulse; union { struct { - uint32_t min_cnt : 12; /*This register stores the value of the maxinum duration time for the high level pulse. It is used in baud rate-detect process.*/ + uint32_t min_cnt : 12; /*This register stores the value of the maximum duration time for the high level pulse. It is used in baud rate-detect process.*/ uint32_t reserved12 : 20; /*Reserved*/ }; uint32_t val; diff --git a/components/soc/esp32c2/include/soc/xts_aes_reg.h b/components/soc/esp32c2/register/soc/xts_aes_reg.h similarity index 98% rename from components/soc/esp32c2/include/soc/xts_aes_reg.h rename to components/soc/esp32c2/register/soc/xts_aes_reg.h index 9845d0b0582..6a6e64539c5 100644 --- a/components/soc/esp32c2/include/soc/xts_aes_reg.h +++ b/components/soc/esp32c2/register/soc/xts_aes_reg.h @@ -119,7 +119,7 @@ extern "C" { #define XTS_AES_DATE_V 0x3FFFFFFFU #define XTS_AES_DATE_S 0 -/* For backward compatability with the older register names */ +/* For backward compatibility with the older register names */ #define AES_XTS_PLAIN_BASE XTS_AES_PLAIN_MEM #define AES_XTS_SIZE_REG XTS_AES_LINESIZE_REG #define AES_XTS_DESTINATION_REG XTS_AES_DESTINATION_REG From 02a88eed4ecc19d91031e38901eb03de4ab681a3 Mon Sep 17 00:00:00 2001 From: xuxiao Date: Thu, 26 Sep 2024 15:21:58 +0800 Subject: [PATCH 127/472] fix(wifi): add bss color support for softap --- components/esp_rom/esp32c5/ld/esp32c5.rom.net80211.ld | 2 +- components/esp_rom/esp32c5/ld/esp32c5.rom.pp.ld | 4 ++-- .../esp_rom/esp32c61/ld/esp32c61.rom.net80211.ld | 2 +- components/esp_rom/esp32c61/ld/esp32c61.rom.pp.ld | 4 ++-- components/esp_wifi/include/esp_wifi_he.h | 10 +++++++--- components/esp_wifi/lib | 2 +- 6 files changed, 14 insertions(+), 10 deletions(-) diff --git a/components/esp_rom/esp32c5/ld/esp32c5.rom.net80211.ld b/components/esp_rom/esp32c5/ld/esp32c5.rom.net80211.ld index bd55f3bb3cb..1d87aafcb38 100644 --- a/components/esp_rom/esp32c5/ld/esp32c5.rom.net80211.ld +++ b/components/esp_rom/esp32c5/ld/esp32c5.rom.net80211.ld @@ -60,7 +60,7 @@ ieee80211_find_ext_elem = 0x40000bb0; ieee80211_find_ie = 0x40000bb4; ieee80211_find_ext_ie = 0x40000bb8; ieee80211_merge_mbssid_profile = 0x40000bbc; -ieee80211_encap_esfbuf_htc = 0x40000bc0; +/*ieee80211_encap_esfbuf_htc = 0x40000bc0;*/ /*wifi_get_macaddr = 0x40000bc4;*/ /*wifi_rf_phy_disable = 0x40000bc8;*/ /*wifi_rf_phy_enable = 0x40000bcc;*/ diff --git a/components/esp_rom/esp32c5/ld/esp32c5.rom.pp.ld b/components/esp_rom/esp32c5/ld/esp32c5.rom.pp.ld index 605063d1c68..7515b90cca3 100644 --- a/components/esp_rom/esp32c5/ld/esp32c5.rom.pp.ld +++ b/components/esp_rom/esp32c5/ld/esp32c5.rom.pp.ld @@ -27,14 +27,14 @@ esf_buf_recycle = 0x40000bfc; GetAccess = 0x40000c00; hal_mac_is_low_rate_enabled = 0x40000c04; hal_mac_tx_get_blockack = 0x40000c08; -hal_mac_tx_set_ppdu = 0x40000c0c; +/*hal_mac_tx_set_ppdu = 0x40000c0c;*/ hal_mac_tx_clr_mplen = 0x40000c10; hal_mac_get_txq_state = 0x40000c14; hal_mac_clr_txq_state = 0x40000c18; hal_mac_get_txq_complete = 0x40000c1c; /*hal_mac_deinit_twt_tx = 0x40000c20;*/ hal_mac_is_dma_enable = 0x40000c24; -hal_he_get_bss_color = 0x40000c28; +/*hal_he_get_bss_color = 0x40000c28;*/ hal_he_set_ersu = 0x40000c2c; hal_he_get_mplen_addr_start = 0x40000c30; hal_he_get_mplen_addr_end = 0x40000c34; diff --git a/components/esp_rom/esp32c61/ld/esp32c61.rom.net80211.ld b/components/esp_rom/esp32c61/ld/esp32c61.rom.net80211.ld index 82727daf241..230c560b3df 100644 --- a/components/esp_rom/esp32c61/ld/esp32c61.rom.net80211.ld +++ b/components/esp_rom/esp32c61/ld/esp32c61.rom.net80211.ld @@ -60,7 +60,7 @@ ieee80211_find_ext_elem = 0x40000b18; ieee80211_find_ie = 0x40000b1c; ieee80211_find_ext_ie = 0x40000b20; ieee80211_merge_mbssid_profile = 0x40000b24; -ieee80211_encap_esfbuf_htc = 0x40000b28; +/*ieee80211_encap_esfbuf_htc = 0x40000b28;*/ wifi_get_macaddr = 0x40000b2c; wifi_rf_phy_disable = 0x40000b30; wifi_rf_phy_enable = 0x40000b34; diff --git a/components/esp_rom/esp32c61/ld/esp32c61.rom.pp.ld b/components/esp_rom/esp32c61/ld/esp32c61.rom.pp.ld index 54f0a48c42b..cf1349b9ab2 100644 --- a/components/esp_rom/esp32c61/ld/esp32c61.rom.pp.ld +++ b/components/esp_rom/esp32c61/ld/esp32c61.rom.pp.ld @@ -27,14 +27,14 @@ esf_buf_recycle = 0x40000b64; GetAccess = 0x40000b68; hal_mac_is_low_rate_enabled = 0x40000b6c; hal_mac_tx_get_blockack = 0x40000b70; -hal_mac_tx_set_ppdu = 0x40000b74; +/*hal_mac_tx_set_ppdu = 0x40000b74;*/ hal_mac_tx_clr_mplen = 0x40000b78; hal_mac_get_txq_state = 0x40000b7c; hal_mac_clr_txq_state = 0x40000b80; hal_mac_get_txq_complete = 0x40000b84; hal_mac_deinit_twt_tx = 0x40000b88; hal_mac_is_dma_enable = 0x40000b8c; -hal_he_get_bss_color = 0x40000b90; +/*hal_he_get_bss_color = 0x40000b90;*/ hal_he_set_ersu = 0x40000b94; hal_he_get_mplen_addr_start = 0x40000b98; hal_he_get_mplen_addr_end = 0x40000b9c; diff --git a/components/esp_wifi/include/esp_wifi_he.h b/components/esp_wifi/include/esp_wifi_he.h index 99a3be564b2..619c7b3fa6c 100644 --- a/components/esp_wifi/include/esp_wifi_he.h +++ b/components/esp_wifi/include/esp_wifi_he.h @@ -9,6 +9,7 @@ #include #include #include "esp_err.h" +#include "esp_wifi_types.h" #include "esp_wifi_he_types.h" #ifdef __cplusplus @@ -219,15 +220,18 @@ esp_err_t esp_wifi_sta_twt_config(wifi_twt_config_t *config); /** * @brief Enable bss color collision detection. * - * @param[in] enable If true, when the station detects a BSS color collision, it will report the BSS color collision event to the access point (AP). + * @attention Currently, only STA BSS color collision detection is supported. + * + * @param ifx interface to be configured + * @param enable If true, when the STA detects a BSS color collision, it will report the BSS color collision event to the access point (AP). * * @return * - ESP_OK: succeed + * - ESP_ERR_WIFI_IF: Invalid interface * - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by esp_wifi_init * - ESP_ERR_WIFI_NOT_STARTED: WiFi is not started by esp_wifi_start - * - ESP_ERR_NOT_SUPPORTED: This API is not supported in AP mode yet */ -esp_err_t esp_wifi_sta_enable_bsscolor_collision_detection(bool enable); +esp_err_t esp_wifi_enable_bsscolor_collision_detection(wifi_interface_t ifx, bool enable); #ifdef __cplusplus } diff --git a/components/esp_wifi/lib b/components/esp_wifi/lib index 903d1e428f1..a93530033ae 160000 --- a/components/esp_wifi/lib +++ b/components/esp_wifi/lib @@ -1 +1 @@ -Subproject commit 903d1e428f1b08806070be4dc7a39118a4f7e417 +Subproject commit a93530033aece29f1622c9ca9161eb4770aea909 From 6fd834eb90a40d8eaa6697ed1d32f8d22fbed215 Mon Sep 17 00:00:00 2001 From: "C.S.M" Date: Fri, 11 Oct 2024 16:16:49 +0800 Subject: [PATCH 128/472] fix(i2c): Fix there is no define in retention bitmap --- components/soc/esp32p4/include/soc/retention_periph_defs.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/components/soc/esp32p4/include/soc/retention_periph_defs.h b/components/soc/esp32p4/include/soc/retention_periph_defs.h index ab603ed24a8..d7ca81d8049 100644 --- a/components/soc/esp32p4/include/soc/retention_periph_defs.h +++ b/components/soc/esp32p4/include/soc/retention_periph_defs.h @@ -81,6 +81,8 @@ typedef enum periph_retention_module_bitmap { SLEEP_RETENTION_MODULE_BM_I2S1 = BIT(SLEEP_RETENTION_MODULE_I2S1), SLEEP_RETENTION_MODULE_BM_I2S2 = BIT(SLEEP_RETENTION_MODULE_I2S2), SLEEP_RETENTION_MODULE_BM_ETM0 = BIT(SLEEP_RETENTION_MODULE_ETM0), + SLEEP_RETENTION_MODULE_BM_I2C0 = BIT(SLEEP_RETENTION_MODULE_I2C0), + SLEEP_RETENTION_MODULE_BM_I2C1 = BIT(SLEEP_RETENTION_MODULE_I2C1), SLEEP_RETENTION_MODULE_BM_ALL = (uint32_t)-1 } periph_retention_module_bitmap_t; @@ -106,6 +108,8 @@ typedef enum periph_retention_module_bitmap { | SLEEP_RETENTION_MODULE_BM_I2S1 \ | SLEEP_RETENTION_MODULE_BM_I2S2 \ | SLEEP_RETENTION_MODULE_BM_ETM0 \ + | SLEEP_RETENTION_MODULE_BM_I2C0 \ + | SLEEP_RETENTION_MODULE_BM_I2C1 \ ) #ifdef __cplusplus From d93a25d1fb2857af17e45e1ba175561b28db0599 Mon Sep 17 00:00:00 2001 From: morris Date: Thu, 10 Oct 2024 16:28:37 +0800 Subject: [PATCH 129/472] feat(etm): add driver support for esp32c61 --- .../esp32c61/ld/esp32c61.rom.systimer.ld | 5 +- components/esp_rom/patches/esp_rom_systimer.c | 4 +- .../main/test_systick_etm.c | 2 +- components/hal/esp32c5/include/hal/etm_ll.h | 1 - components/hal/esp32c6/include/hal/etm_ll.h | 1 - components/hal/esp32c61/include/hal/etm_ll.h | 117 +++++++++++++++ .../hal/esp32c61/include/hal/gpio_etm_ll.h | 136 ++++++++++++++++++ .../esp32c61/include/soc/Kconfig.soc_caps.in | 24 ++++ .../esp32c61/include/soc/gpio_ext_struct.h | 26 ++-- .../soc/esp32c61/include/soc/soc_caps.h | 12 +- .../soc/esp32c61/include/soc/soc_etm_struct.h | 106 +------------- .../soc/esp32c61/ld/esp32c61.peripherals.ld | 2 + docs/docs_not_updated/esp32c61.txt | 1 - .../gptimer_capture_hc_sr04/README.md | 4 +- .../pytest_gptimer_capture_example.py | 1 + 15 files changed, 317 insertions(+), 125 deletions(-) create mode 100644 components/hal/esp32c61/include/hal/etm_ll.h create mode 100644 components/hal/esp32c61/include/hal/gpio_etm_ll.h diff --git a/components/esp_rom/esp32c61/ld/esp32c61.rom.systimer.ld b/components/esp_rom/esp32c61/ld/esp32c61.rom.systimer.ld index 7be47b11105..9f260f5ecd4 100644 --- a/components/esp_rom/esp32c61/ld/esp32c61.rom.systimer.ld +++ b/components/esp_rom/esp32c61/ld/esp32c61.rom.systimer.ld @@ -9,8 +9,9 @@ ***************************************/ /* Functions */ -systimer_hal_init = 0x400003d0; -systimer_hal_deinit = 0x400003d4; +/* The following ROM functions are commented out because they're patched in the esp_rom_systimer.c */ +/* systimer_hal_init = 0x400003d0; */ +/* systimer_hal_deinit = 0x400003d4; */ systimer_hal_set_tick_rate_ops = 0x400003d8; systimer_hal_get_counter_value = 0x400003dc; systimer_hal_get_time = 0x400003e0; diff --git a/components/esp_rom/patches/esp_rom_systimer.c b/components/esp_rom/patches/esp_rom_systimer.c index 0b8b20e180d..7de32f09e6a 100644 --- a/components/esp_rom/patches/esp_rom_systimer.c +++ b/components/esp_rom/patches/esp_rom_systimer.c @@ -64,7 +64,7 @@ void systimer_hal_counter_value_advance(systimer_hal_context_t *hal, uint32_t co } #endif // CONFIG_IDF_TARGET_ESP32C2 && (CONFIG_ESP32C2_REV_MIN_FULL < 200) -#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C5 +#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C61 void systimer_hal_init(systimer_hal_context_t *hal) { hal->dev = &SYSTIMER; @@ -78,6 +78,6 @@ void systimer_hal_deinit(systimer_hal_context_t *hal) systimer_ll_enable_clock(hal->dev, false); hal->dev = NULL; } -#endif // CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4 +#endif // CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C61 #endif // CONFIG_HAL_SYSTIMER_USE_ROM_IMPL diff --git a/components/esp_system/test_apps/esp_system_unity_tests/main/test_systick_etm.c b/components/esp_system/test_apps/esp_system_unity_tests/main/test_systick_etm.c index d82cf13d625..58793d18249 100644 --- a/components/esp_system/test_apps/esp_system_unity_tests/main/test_systick_etm.c +++ b/components/esp_system/test_apps/esp_system_unity_tests/main/test_systick_etm.c @@ -51,7 +51,7 @@ TEST_CASE("rtos_systick_etm_event", "[etm]") TEST_ESP_OK(esp_etm_channel_enable(etm_channel_a)); - // should see a 500Hz square wave on the GPIO (if RTOS systick is set to 1000Hz) + // should see a 50Hz square wave on the GPIO (if RTOS systick is set to 100Hz) vTaskDelay(pdMS_TO_TICKS(1000)); // delete etm primitives diff --git a/components/hal/esp32c5/include/hal/etm_ll.h b/components/hal/esp32c5/include/hal/etm_ll.h index fa76af9f99b..ebed4861b56 100644 --- a/components/hal/esp32c5/include/hal/etm_ll.h +++ b/components/hal/esp32c5/include/hal/etm_ll.h @@ -11,7 +11,6 @@ #include #include "hal/assert.h" #include "hal/misc.h" -#include "hal/lp_aon_ll.h" #include "soc/soc_etm_struct.h" #include "soc/pcr_struct.h" diff --git a/components/hal/esp32c6/include/hal/etm_ll.h b/components/hal/esp32c6/include/hal/etm_ll.h index 9d7079619d0..e77bfeec5f9 100644 --- a/components/hal/esp32c6/include/hal/etm_ll.h +++ b/components/hal/esp32c6/include/hal/etm_ll.h @@ -11,7 +11,6 @@ #include #include "hal/assert.h" #include "hal/misc.h" -#include "hal/lp_aon_ll.h" #include "soc/soc_etm_struct.h" #include "soc/pcr_struct.h" diff --git a/components/hal/esp32c61/include/hal/etm_ll.h b/components/hal/esp32c61/include/hal/etm_ll.h new file mode 100644 index 00000000000..6708cd7f17e --- /dev/null +++ b/components/hal/esp32c61/include/hal/etm_ll.h @@ -0,0 +1,117 @@ +/* + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +// Note that most of the register operations in this layer are non-atomic operations. + +#pragma once + +#include +#include "hal/assert.h" +#include "hal/misc.h" +#include "soc/soc_etm_struct.h" +#include "soc/pcr_struct.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Enable the clock for ETM register + * + * @param group_id Group ID + * @param enable true to enable, false to disable + */ +static inline void etm_ll_enable_bus_clock(int group_id, bool enable) +{ + (void)group_id; + PCR.etm_conf.etm_clk_en = enable; +} + +/** + * @brief Reset the ETM register + * + * @param group_id Group ID + */ +static inline void etm_ll_reset_register(int group_id) +{ + (void)group_id; + PCR.etm_conf.etm_rst_en = 1; + PCR.etm_conf.etm_rst_en = 0; +} + +/** + * @brief Enable ETM channel + * + * @param hw ETM register base address + * @param chan Channel ID + */ +static inline void etm_ll_enable_channel(soc_etm_dev_t *hw, uint32_t chan) +{ + if (chan < 32) { + hw->ch_ena_ad0_set.val = 1 << chan; + } else { + hw->ch_ena_ad1_set.val = 1 << (chan - 32); + } +} + +/** + * @brief Disable ETM channel + * + * @param hw ETM register base address + * @param chan Channel ID + */ +static inline void etm_ll_disable_channel(soc_etm_dev_t *hw, uint32_t chan) +{ + if (chan < 32) { + hw->ch_ena_ad0_clr.val = 1 << chan; + } else { + hw->ch_ena_ad1_clr.val = 1 << (chan - 32); + } +} + +/** + * @brief Check whether the ETM channel is enabled or not + * + * @param hw ETM register base address + * @param chan Channel ID + * @return true if the channel is enabled, false otherwise + */ +static inline bool etm_ll_is_channel_enabled(soc_etm_dev_t *hw, uint32_t chan) +{ + if (chan < 32) { + return hw->ch_ena_ad0.val & (1 << chan); + } else { + return hw->ch_ena_ad1.val & (1 << (chan - 32)); + } +} + +/** + * @brief Set the input event for the ETM channel + * + * @param hw ETM register base address + * @param chan Channel ID + * @param event Event ID + */ +static inline void etm_ll_channel_set_event(soc_etm_dev_t *hw, uint32_t chan, uint32_t event) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->channel[chan].eid, chn_evt_id, event); +} + +/** + * @brief Set the output task for the ETM channel + * + * @param hw ETM register base address + * @param chan Channel ID + * @param task Task ID + */ +static inline void etm_ll_channel_set_task(soc_etm_dev_t *hw, uint32_t chan, uint32_t task) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->channel[chan].tid, chn_task_id, task); +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32c61/include/hal/gpio_etm_ll.h b/components/hal/esp32c61/include/hal/gpio_etm_ll.h new file mode 100644 index 00000000000..52a06e7fc3e --- /dev/null +++ b/components/hal/esp32c61/include/hal/gpio_etm_ll.h @@ -0,0 +1,136 @@ +/* + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +// Note that most of the register operations in this layer are non-atomic operations. + +#pragma once + +#include +#include "hal/assert.h" +#include "hal/misc.h" +#include "soc/gpio_ext_struct.h" +#include "soc/soc_etm_source.h" + +#define GPIO_LL_ETM_EVENT_ID_POS_EDGE(ch) (GPIO_EVT_CH0_RISE_EDGE + (ch)) +#define GPIO_LL_ETM_EVENT_ID_NEG_EDGE(ch) (GPIO_EVT_CH0_FALL_EDGE + (ch)) +#define GPIO_LL_ETM_EVENT_ID_ANY_EDGE(ch) (GPIO_EVT_CH0_ANY_EDGE + (ch)) + +#define GPIO_LL_ETM_TASK_ID_SET(ch) (GPIO_TASK_CH0_SET + (ch)) +#define GPIO_LL_ETM_TASK_ID_CLR(ch) (GPIO_TASK_CH0_CLEAR + (ch)) +#define GPIO_LL_ETM_TASK_ID_TOG(ch) (GPIO_TASK_CH0_TOGGLE + (ch)) + +#define GPIO_LL_ETM_EVENT_CHANNELS_PER_GROUP 8 +#define GPIO_LL_ETM_TASK_CHANNELS_PER_GROUP 8 + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Set which GPIO to be bound to the event channel + * + * @note Different channels can be bound to one GPIO + * + * @param dev Register base address + * @param chan GPIO ETM Event channel number + * @param gpio_num GPIO number + */ +static inline void gpio_ll_etm_event_channel_set_gpio(gpio_etm_dev_t *dev, uint32_t chan, uint32_t gpio_num) +{ + dev->etm_event_chn_cfg[chan].etm_chn_event_sel = gpio_num; +} + +/** + * @brief Whether to enable the event channel + * + * @param dev Register base address + * @param chan GPIO ETM Event channel number + * @param enable True to enable, false to disable + */ +static inline void gpio_ll_etm_enable_event_channel(gpio_etm_dev_t *dev, uint32_t chan, bool enable) +{ + dev->etm_event_chn_cfg[chan].etm_chn_event_en = enable; +} + +/** + * @brief Get which GPIO is bound to the event channel + * + * @param dev Register base address + * @param chan GPIO ETM Event channel number + * @return GPIO number + */ +static inline uint32_t gpio_ll_etm_event_channel_get_gpio(gpio_etm_dev_t *dev, uint32_t chan) +{ + return dev->etm_event_chn_cfg[chan].etm_chn_event_sel; +} + +/** + * @brief Set which GPIO to be bound to the task channel + * + * @note One channel can be bound to multiple different GPIOs + * + * @param dev Register base address + * @param chan GPIO ETM Task channel number + * @param gpio_num GPIO number + */ +static inline void gpio_ll_etm_gpio_set_task_channel(gpio_etm_dev_t *dev, uint32_t gpio_num, uint32_t chan) +{ + int g_p = gpio_num / 5; + int g_idx = gpio_num % 5; + uint32_t reg_val = dev->etm_task_pn_cfg[g_p].val; + reg_val &= ~(0x07 << (g_idx * 6)); + reg_val |= ((chan & 0x07) << (g_idx * 6)); + dev->etm_task_pn_cfg[g_p].val = reg_val; +} + +/** + * @brief Whether to enable the GPIO to be managed by the task channel + * + * @param dev Register base address + * @param gpio_num GPIO number + * @param enable True to enable, false to disable + */ +static inline void gpio_ll_etm_enable_task_gpio(gpio_etm_dev_t *dev, uint32_t gpio_num, bool enable) +{ + int g_p = gpio_num / 5; + int g_idx = gpio_num % 5; + uint32_t reg_val = dev->etm_task_pn_cfg[g_p].val; + reg_val &= ~(0x01 << (g_idx * 6 + 5)); + reg_val |= ((enable & 0x01) << (g_idx * 6 + 5)); + dev->etm_task_pn_cfg[g_p].val = reg_val; +} + +/** + * @brief Check whether a GPIO has been enabled and managed by a task channel + * + * @param dev Register base address + * @param gpio_num GPIO number + * @return True if enabled, false otherwise + */ +static inline bool gpio_ll_etm_is_task_gpio_enabled(gpio_etm_dev_t *dev, uint32_t gpio_num) +{ + int g_p = gpio_num / 5; + int g_idx = gpio_num % 5; + return dev->etm_task_pn_cfg[g_p].val & (0x01 << (g_idx * 6 + 5)); +} + +/** + * @brief Get the channel number that the GPIO is bound to + * + * @param dev Register base address + * @param gpio_num GPIO number + * @return GPIO ETM Task channel number + */ +static inline uint32_t gpio_ll_etm_gpio_get_task_channel(gpio_etm_dev_t *dev, uint32_t gpio_num) +{ + int g_p = gpio_num / 5; + int g_idx = gpio_num % 5; + return (dev->etm_task_pn_cfg[g_p].val >> (g_idx * 6)) & 0x07; +} + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in index 94aaaa03901..73a93f10d4c 100644 --- a/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in @@ -131,6 +131,10 @@ config SOC_REG_I2C_SUPPORTED bool default y +config SOC_ETM_SUPPORTED + bool + default y + config SOC_PAU_SUPPORTED bool default y @@ -267,6 +271,10 @@ config SOC_GDMA_PAIRS_PER_GROUP_MAX int default 2 +config SOC_GDMA_SUPPORT_ETM + bool + default y + config SOC_GDMA_SUPPORT_SLEEP_RETENTION bool default y @@ -279,6 +287,10 @@ config SOC_ETM_CHANNELS_PER_GROUP int default 50 +config SOC_ETM_SUPPORT_SLEEP_RETENTION + bool + default y + config SOC_GPIO_PORT int default 1 @@ -295,6 +307,10 @@ config SOC_GPIO_SUPPORT_PIN_HYS_FILTER bool default y +config SOC_GPIO_SUPPORT_ETM + bool + default y + config SOC_GPIO_SUPPORT_RTC_INDEPENDENT bool default y @@ -655,6 +671,10 @@ config SOC_SYSTIMER_ALARM_MISS_COMPENSATE bool default y +config SOC_SYSTIMER_SUPPORT_ETM + bool + default y + config SOC_LP_TIMER_BIT_WIDTH_LO int default 32 @@ -691,6 +711,10 @@ config SOC_TIMER_SUPPORT_SLEEP_RETENTION bool default y +config SOC_TIMER_SUPPORT_ETM + bool + default y + config SOC_MWDT_SUPPORT_SLEEP_RETENTION bool default y diff --git a/components/soc/esp32c61/include/soc/gpio_ext_struct.h b/components/soc/esp32c61/include/soc/gpio_ext_struct.h index f02a5fec8a1..1f7f58950e2 100644 --- a/components/soc/esp32c61/include/soc/gpio_ext_struct.h +++ b/components/soc/esp32c61/include/soc/gpio_ext_struct.h @@ -39,7 +39,7 @@ typedef union { */ uint32_t xpd_comp_0:1; /** mode_comp_0 : R/W; bitpos: [1]; default: 0; - * Configures the reference voltage for analog PAD voltage comparater.. \\ + * Configures the reference voltage for analog PAD voltage comparator.. \\ * 0: Reference voltage is the internal reference voltage, meanwhile GPIO8 PAD can be * used as a regular GPIO\\ * 1: Reference voltage is the voltage on the GPIO8 PAD\\ @@ -128,6 +128,15 @@ typedef union { uint32_t val; } gpio_ext_etm_event_chn_cfg_reg_t; +/** Type of etm_task_pn_cfg register + * GPIO selection register for ETM. + * This register is an abstraction of the following registers: + * gpio_ext_etm_task_p0_cfg_reg_t ~ gpio_ext_etm_task_p4_cfg_reg_t + */ +typedef union { + uint32_t val; +} gpio_ext_etm_task_pn_cfg_reg_t; + /** Type of etm_task_p0_cfg register * GPIO selection register 0 for ETM */ @@ -659,6 +668,11 @@ typedef union { uint32_t val; } gpio_ext_version_reg_t; +typedef struct gpio_etm_dev_t { + volatile gpio_ext_etm_event_chn_cfg_reg_t etm_event_chn_cfg[8]; + uint32_t reserved_138[8]; + volatile gpio_ext_etm_task_pn_cfg_reg_t etm_task_pn_cfg[5]; +} gpio_etm_dev_t; typedef struct { volatile gpio_ext_clock_gate_reg_t clock_gate; @@ -666,13 +680,7 @@ typedef struct { volatile gpio_ext_pad_comp_config_0_reg_t pad_comp_config_0; volatile gpio_ext_pad_comp_filter_0_reg_t pad_comp_filter_0; uint32_t reserved_060[46]; - volatile gpio_ext_etm_event_chn_cfg_reg_t etm_event_chn_cfg[8]; - uint32_t reserved_138[8]; - volatile gpio_ext_etm_task_p0_cfg_reg_t etm_task_p0_cfg; - volatile gpio_ext_etm_task_p1_cfg_reg_t etm_task_p1_cfg; - volatile gpio_ext_etm_task_p2_cfg_reg_t etm_task_p2_cfg; - volatile gpio_ext_etm_task_p3_cfg_reg_t etm_task_p3_cfg; - volatile gpio_ext_etm_task_p4_cfg_reg_t etm_task_p4_cfg; + volatile gpio_etm_dev_t etm; uint32_t reserved_16c[25]; volatile gpio_ext_int_raw_reg_t int_raw; volatile gpio_ext_int_st_reg_t int_st; @@ -683,6 +691,8 @@ typedef struct { volatile gpio_ext_version_reg_t version; } gpio_ext_dev_t; +extern gpio_etm_dev_t GPIO_ETM; +extern gpio_ext_dev_t GPIO_EXT; #ifndef __cplusplus _Static_assert(sizeof(gpio_ext_dev_t) == 0x200, "Invalid size of gpio_ext_dev_t structure"); diff --git a/components/soc/esp32c61/include/soc/soc_caps.h b/components/soc/esp32c61/include/soc/soc_caps.h index 5e70aafba19..3d0cb808671 100644 --- a/components/soc/esp32c61/include/soc/soc_caps.h +++ b/components/soc/esp32c61/include/soc/soc_caps.h @@ -56,7 +56,7 @@ // \#define SOC_RNG_SUPPORTED 1 //TODO: [ESP32C61] IDF-9236 #define SOC_MODEM_CLOCK_SUPPORTED 1 #define SOC_REG_I2C_SUPPORTED 1 -// \#define SOC_ETM_SUPPORTED 0 +#define SOC_ETM_SUPPORTED 1 // \#define SOC_SDIO_SLAVE_SUPPORTED 0 #define SOC_PAU_SUPPORTED 1 #define SOC_LIGHT_SLEEP_SUPPORTED 1 @@ -148,13 +148,13 @@ #define SOC_AHB_GDMA_VERSION 2U #define SOC_GDMA_NUM_GROUPS_MAX 1U #define SOC_GDMA_PAIRS_PER_GROUP_MAX 2 -// \#define SOC_GDMA_SUPPORT_ETM 1 // Support ETM submodule TODO: IDF-9964 +#define SOC_GDMA_SUPPORT_ETM 1 // Support ETM submodule #define SOC_GDMA_SUPPORT_SLEEP_RETENTION 1 /*-------------------------- ETM CAPS --------------------------------------*/ #define SOC_ETM_GROUPS 1U // Number of ETM groups #define SOC_ETM_CHANNELS_PER_GROUP 50 // Number of ETM channels in the group -// #define SOC_ETM_SUPPORT_SLEEP_RETENTION 1 // Support sleep retention +#define SOC_ETM_SUPPORT_SLEEP_RETENTION 1 // Support sleep retention /*-------------------------- GPIO CAPS ---------------------------------------*/ // ESP32-C61 has 1 GPIO peripheral @@ -164,7 +164,7 @@ #define SOC_GPIO_SUPPORT_PIN_HYS_FILTER 1 // GPIO peripheral has the ETM extension -// \#define SOC_GPIO_SUPPORT_ETM 1 //TODO: [ESP32C61] IDF-9318 +#define SOC_GPIO_SUPPORT_ETM 1 // Target has the full LP IO subsystem // On ESP32-C61, Digital IOs have their own registers to control pullup/down capability, independent of LP registers. @@ -340,7 +340,7 @@ #define SOC_SYSTIMER_SUPPORT_RC_FAST 1 // Systimer can use RC_FAST clock source #define SOC_SYSTIMER_INT_LEVEL 1 // Systimer peripheral uses level interrupt #define SOC_SYSTIMER_ALARM_MISS_COMPENSATE 1 // Systimer peripheral can generate interrupt immediately if t(target) > t(current) -// #define SOC_SYSTIMER_SUPPORT_ETM 1 // Systimer comparator can generate ETM event +#define SOC_SYSTIMER_SUPPORT_ETM 1 // Systimer comparator can generate ETM event /*-------------------------- LP_TIMER CAPS ----------------------------------*/ #define SOC_LP_TIMER_BIT_WIDTH_LO 32 // Bit width of lp_timer low part @@ -354,7 +354,7 @@ #define SOC_TIMER_GROUP_SUPPORT_XTAL (1) #define SOC_TIMER_GROUP_SUPPORT_RC_FAST (1) #define SOC_TIMER_SUPPORT_SLEEP_RETENTION (1) -// #define SOC_TIMER_SUPPORT_ETM (1) +#define SOC_TIMER_SUPPORT_ETM (1) /*--------------------------- WATCHDOG CAPS ---------------------------------------*/ // #define SOC_MWDT_SUPPORT_XTAL (1) diff --git a/components/soc/esp32c61/include/soc/soc_etm_struct.h b/components/soc/esp32c61/include/soc/soc_etm_struct.h index 464ab7f33e1..2cb80d7c280 100644 --- a/components/soc/esp32c61/include/soc/soc_etm_struct.h +++ b/components/soc/esp32c61/include/soc/soc_etm_struct.h @@ -3161,113 +3161,17 @@ typedef union { } soc_etm_date_reg_t; -typedef struct { +typedef struct soc_etm_dev_t { volatile soc_etm_ch_ena_ad0_reg_t ch_ena_ad0; volatile soc_etm_ch_ena_ad0_set_reg_t ch_ena_ad0_set; volatile soc_etm_ch_ena_ad0_clr_reg_t ch_ena_ad0_clr; volatile soc_etm_ch_ena_ad1_reg_t ch_ena_ad1; volatile soc_etm_ch_ena_ad1_set_reg_t ch_ena_ad1_set; volatile soc_etm_ch_ena_ad1_clr_reg_t ch_ena_ad1_clr; - volatile soc_etm_chn_evt_id_reg_t ch0_evt_id; - volatile soc_etm_chn_task_id_reg_t ch0_task_id; - volatile soc_etm_chn_evt_id_reg_t ch1_evt_id; - volatile soc_etm_chn_task_id_reg_t ch1_task_id; - volatile soc_etm_chn_evt_id_reg_t ch2_evt_id; - volatile soc_etm_chn_task_id_reg_t ch2_task_id; - volatile soc_etm_chn_evt_id_reg_t ch3_evt_id; - volatile soc_etm_chn_task_id_reg_t ch3_task_id; - volatile soc_etm_chn_evt_id_reg_t ch4_evt_id; - volatile soc_etm_chn_task_id_reg_t ch4_task_id; - volatile soc_etm_chn_evt_id_reg_t ch5_evt_id; - volatile soc_etm_chn_task_id_reg_t ch5_task_id; - volatile soc_etm_chn_evt_id_reg_t ch6_evt_id; - volatile soc_etm_chn_task_id_reg_t ch6_task_id; - volatile soc_etm_chn_evt_id_reg_t ch7_evt_id; - volatile soc_etm_chn_task_id_reg_t ch7_task_id; - volatile soc_etm_chn_evt_id_reg_t ch8_evt_id; - volatile soc_etm_chn_task_id_reg_t ch8_task_id; - volatile soc_etm_chn_evt_id_reg_t ch9_evt_id; - volatile soc_etm_chn_task_id_reg_t ch9_task_id; - volatile soc_etm_chn_evt_id_reg_t ch10_evt_id; - volatile soc_etm_chn_task_id_reg_t ch10_task_id; - volatile soc_etm_chn_evt_id_reg_t ch11_evt_id; - volatile soc_etm_chn_task_id_reg_t ch11_task_id; - volatile soc_etm_chn_evt_id_reg_t ch12_evt_id; - volatile soc_etm_chn_task_id_reg_t ch12_task_id; - volatile soc_etm_chn_evt_id_reg_t ch13_evt_id; - volatile soc_etm_chn_task_id_reg_t ch13_task_id; - volatile soc_etm_chn_evt_id_reg_t ch14_evt_id; - volatile soc_etm_chn_task_id_reg_t ch14_task_id; - volatile soc_etm_chn_evt_id_reg_t ch15_evt_id; - volatile soc_etm_chn_task_id_reg_t ch15_task_id; - volatile soc_etm_chn_evt_id_reg_t ch16_evt_id; - volatile soc_etm_chn_task_id_reg_t ch16_task_id; - volatile soc_etm_chn_evt_id_reg_t ch17_evt_id; - volatile soc_etm_chn_task_id_reg_t ch17_task_id; - volatile soc_etm_chn_evt_id_reg_t ch18_evt_id; - volatile soc_etm_chn_task_id_reg_t ch18_task_id; - volatile soc_etm_chn_evt_id_reg_t ch19_evt_id; - volatile soc_etm_chn_task_id_reg_t ch19_task_id; - volatile soc_etm_chn_evt_id_reg_t ch20_evt_id; - volatile soc_etm_chn_task_id_reg_t ch20_task_id; - volatile soc_etm_chn_evt_id_reg_t ch21_evt_id; - volatile soc_etm_chn_task_id_reg_t ch21_task_id; - volatile soc_etm_chn_evt_id_reg_t ch22_evt_id; - volatile soc_etm_chn_task_id_reg_t ch22_task_id; - volatile soc_etm_chn_evt_id_reg_t ch23_evt_id; - volatile soc_etm_chn_task_id_reg_t ch23_task_id; - volatile soc_etm_chn_evt_id_reg_t ch24_evt_id; - volatile soc_etm_chn_task_id_reg_t ch24_task_id; - volatile soc_etm_chn_evt_id_reg_t ch25_evt_id; - volatile soc_etm_chn_task_id_reg_t ch25_task_id; - volatile soc_etm_chn_evt_id_reg_t ch26_evt_id; - volatile soc_etm_chn_task_id_reg_t ch26_task_id; - volatile soc_etm_chn_evt_id_reg_t ch27_evt_id; - volatile soc_etm_chn_task_id_reg_t ch27_task_id; - volatile soc_etm_chn_evt_id_reg_t ch28_evt_id; - volatile soc_etm_chn_task_id_reg_t ch28_task_id; - volatile soc_etm_chn_evt_id_reg_t ch29_evt_id; - volatile soc_etm_chn_task_id_reg_t ch29_task_id; - volatile soc_etm_chn_evt_id_reg_t ch30_evt_id; - volatile soc_etm_chn_task_id_reg_t ch30_task_id; - volatile soc_etm_chn_evt_id_reg_t ch31_evt_id; - volatile soc_etm_chn_task_id_reg_t ch31_task_id; - volatile soc_etm_chn_evt_id_reg_t ch32_evt_id; - volatile soc_etm_chn_task_id_reg_t ch32_task_id; - volatile soc_etm_chn_evt_id_reg_t ch33_evt_id; - volatile soc_etm_chn_task_id_reg_t ch33_task_id; - volatile soc_etm_chn_evt_id_reg_t ch34_evt_id; - volatile soc_etm_chn_task_id_reg_t ch34_task_id; - volatile soc_etm_chn_evt_id_reg_t ch35_evt_id; - volatile soc_etm_chn_task_id_reg_t ch35_task_id; - volatile soc_etm_chn_evt_id_reg_t ch36_evt_id; - volatile soc_etm_chn_task_id_reg_t ch36_task_id; - volatile soc_etm_chn_evt_id_reg_t ch37_evt_id; - volatile soc_etm_chn_task_id_reg_t ch37_task_id; - volatile soc_etm_chn_evt_id_reg_t ch38_evt_id; - volatile soc_etm_chn_task_id_reg_t ch38_task_id; - volatile soc_etm_chn_evt_id_reg_t ch39_evt_id; - volatile soc_etm_chn_task_id_reg_t ch39_task_id; - volatile soc_etm_chn_evt_id_reg_t ch40_evt_id; - volatile soc_etm_chn_task_id_reg_t ch40_task_id; - volatile soc_etm_chn_evt_id_reg_t ch41_evt_id; - volatile soc_etm_chn_task_id_reg_t ch41_task_id; - volatile soc_etm_chn_evt_id_reg_t ch42_evt_id; - volatile soc_etm_chn_task_id_reg_t ch42_task_id; - volatile soc_etm_chn_evt_id_reg_t ch43_evt_id; - volatile soc_etm_chn_task_id_reg_t ch43_task_id; - volatile soc_etm_chn_evt_id_reg_t ch44_evt_id; - volatile soc_etm_chn_task_id_reg_t ch44_task_id; - volatile soc_etm_chn_evt_id_reg_t ch45_evt_id; - volatile soc_etm_chn_task_id_reg_t ch45_task_id; - volatile soc_etm_chn_evt_id_reg_t ch46_evt_id; - volatile soc_etm_chn_task_id_reg_t ch46_task_id; - volatile soc_etm_chn_evt_id_reg_t ch47_evt_id; - volatile soc_etm_chn_task_id_reg_t ch47_task_id; - volatile soc_etm_chn_evt_id_reg_t ch48_evt_id; - volatile soc_etm_chn_task_id_reg_t ch48_task_id; - volatile soc_etm_chn_evt_id_reg_t ch49_evt_id; - volatile soc_etm_chn_task_id_reg_t ch49_task_id; + volatile struct { + soc_etm_chn_evt_id_reg_t eid; + soc_etm_chn_task_id_reg_t tid; + } channel[50]; volatile soc_etm_evt_st0_reg_t evt_st0; volatile soc_etm_evt_st0_clr_reg_t evt_st0_clr; volatile soc_etm_evt_st1_reg_t evt_st1; diff --git a/components/soc/esp32c61/ld/esp32c61.peripherals.ld b/components/soc/esp32c61/ld/esp32c61.peripherals.ld index 6d5ca8d8c3b..f0741f33cc4 100644 --- a/components/soc/esp32c61/ld/esp32c61.peripherals.ld +++ b/components/soc/esp32c61/ld/esp32c61.peripherals.ld @@ -29,6 +29,8 @@ PROVIDE ( ECC = 0x6008B000 ); PROVIDE ( ECDSA = 0x6008E000 ); PROVIDE ( IO_MUX = 0x60090000 ); PROVIDE ( GPIO = 0x60091000 ); +PROVIDE ( GPIO_EXT = 0x60091e00 ); +PROVIDE ( GPIO_ETM = 0x60091f18 ); PROVIDE ( TCM_MEM_MONITOR = 0x60092000 ); PROVIDE ( PAU = 0x60093000 ); PROVIDE ( HP_SYSTEM = 0x60095000 ); diff --git a/docs/docs_not_updated/esp32c61.txt b/docs/docs_not_updated/esp32c61.txt index 7dfeaed03e7..a6622d64a31 100644 --- a/docs/docs_not_updated/esp32c61.txt +++ b/docs/docs_not_updated/esp32c61.txt @@ -54,7 +54,6 @@ api-reference/peripherals/usb_host/usb_host_notes_design.rst api-reference/peripherals/usb_device.rst api-reference/peripherals/sdspi_host.rst api-reference/peripherals/dac.rst -api-reference/peripherals/etm.rst api-reference/peripherals/i2s.rst api-reference/peripherals/touch_element.rst api-reference/peripherals/ppa.rst diff --git a/examples/peripherals/timer_group/gptimer_capture_hc_sr04/README.md b/examples/peripherals/timer_group/gptimer_capture_hc_sr04/README.md index 26ed2f38b78..4843828bc25 100644 --- a/examples/peripherals/timer_group/gptimer_capture_hc_sr04/README.md +++ b/examples/peripherals/timer_group/gptimer_capture_hc_sr04/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | -| ----------------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | +| ----------------- | -------- | -------- | --------- | -------- | -------- | # HC-SR04 Example based on GPTimer Capture and ETM diff --git a/examples/peripherals/timer_group/gptimer_capture_hc_sr04/pytest_gptimer_capture_example.py b/examples/peripherals/timer_group/gptimer_capture_hc_sr04/pytest_gptimer_capture_example.py index 0c668e45bb1..2756fe0fa29 100644 --- a/examples/peripherals/timer_group/gptimer_capture_hc_sr04/pytest_gptimer_capture_example.py +++ b/examples/peripherals/timer_group/gptimer_capture_hc_sr04/pytest_gptimer_capture_example.py @@ -6,6 +6,7 @@ @pytest.mark.esp32c5 @pytest.mark.esp32c6 +@pytest.mark.esp32c61 @pytest.mark.esp32h2 @pytest.mark.esp32p4 @pytest.mark.generic From cfdaf3b379317671147b47e92707e17150de444b Mon Sep 17 00:00:00 2001 From: Chen Jichang Date: Fri, 11 Oct 2024 17:25:52 +0800 Subject: [PATCH 130/472] feat(parlio): refactor gpio mode config in parlio --- .../include/driver/parlio_rx.h | 3 +- components/esp_driver_parlio/src/parlio_rx.c | 56 ++++++++++--------- components/esp_driver_parlio/src/parlio_tx.c | 51 ++++++++++------- .../test_apps/parlio/main/test_parlio_rx.c | 9 ++- .../test_apps/parlio/main/test_parlio_tx.c | 18 +++++- .../esp_probe/hw_impl/esp_probe_impl_parlio.c | 2 - 6 files changed, 86 insertions(+), 53 deletions(-) diff --git a/components/esp_driver_parlio/include/driver/parlio_rx.h b/components/esp_driver_parlio/include/driver/parlio_rx.h index 400b10beabe..3a450bd3fdc 100644 --- a/components/esp_driver_parlio/include/driver/parlio_rx.h +++ b/components/esp_driver_parlio/include/driver/parlio_rx.h @@ -40,8 +40,7 @@ typedef struct { the output clock will be controlled by the valid gpio, i.e. high level of valid gpio to enable the clock output, low to disable */ uint32_t io_loop_back: 1; /*!< For debug/test, the signal output from the GPIO will be fed to the input path as well */ - uint32_t io_no_init: 1; /*!< Set to skip initializing the GPIO, but only attach the pralio rx signals to those GPIOs via IO Matrix. - So that the signals that have attached to those GPIO won't be overwritten. Mainly used for self communication or self monitoring */ + uint32_t io_no_init: 1 __attribute__((deprecated)); /*!< Deprecated. Driver won't change the GPIO configuration in inilization. */ } flags; /*!< RX driver flags */ } parlio_rx_unit_config_t; diff --git a/components/esp_driver_parlio/src/parlio_rx.c b/components/esp_driver_parlio/src/parlio_rx.c index 411ed2aea0d..12a9150b1a7 100644 --- a/components/esp_driver_parlio/src/parlio_rx.c +++ b/components/esp_driver_parlio/src/parlio_rx.c @@ -25,7 +25,6 @@ #include "soc/parlio_periph.h" #include "soc/soc_caps.h" #include "hal/parlio_ll.h" -#include "hal/gpio_hal.h" #include "hal/dma_types.h" #include "hal/hal_utils.h" #include "driver/gpio.h" @@ -252,24 +251,19 @@ static esp_err_t s_parlio_rx_unit_set_gpio(parlio_rx_unit_handle_t rx_unit, cons { int group_id = rx_unit->base.group->group_id; int unit_id = rx_unit->base.unit_id; - /* Default GPIO configuration */ - gpio_config_t gpio_conf = { - .intr_type = GPIO_INTR_DISABLE, - .pull_down_en = false, - .pull_up_en = true, - }; /* When the source clock comes from external, enable the gpio input direction and connect to the clock input signal */ if (config->clk_src == PARLIO_CLK_SRC_EXTERNAL) { ESP_RETURN_ON_FALSE(config->clk_in_gpio_num >= 0, ESP_ERR_INVALID_ARG, TAG, "clk_in_gpio_num must be set while the clock input from external"); /* Connect the clock in signal to the GPIO matrix if it is set */ - if (!config->flags.io_no_init) { - gpio_conf.mode = config->flags.io_loop_back ? GPIO_MODE_INPUT_OUTPUT : GPIO_MODE_INPUT; - gpio_conf.pin_bit_mask = BIT64(config->clk_in_gpio_num); - ESP_RETURN_ON_ERROR(gpio_config(&gpio_conf), TAG, "config clk in GPIO failed"); - } else { - gpio_ll_input_enable(&GPIO, config->clk_in_gpio_num); + gpio_func_sel(config->clk_in_gpio_num, PIN_FUNC_GPIO); + gpio_input_enable(config->clk_in_gpio_num); + + // deprecated, to be removed in in esp-idf v6.0 + if (config->flags.io_loop_back) { + gpio_output_enable(config->clk_in_gpio_num); } + esp_rom_gpio_connect_in_signal(config->clk_in_gpio_num, parlio_periph_signals.groups[group_id].rx_units[unit_id].clk_in_sig, false); } @@ -277,9 +271,14 @@ static esp_err_t s_parlio_rx_unit_set_gpio(parlio_rx_unit_handle_t rx_unit, cons * enable the gpio output direction and connect to the clock output signal */ if (config->clk_out_gpio_num >= 0) { #if SOC_PARLIO_RX_CLK_SUPPORT_OUTPUT - gpio_conf.mode = config->flags.io_loop_back ? GPIO_MODE_INPUT_OUTPUT : GPIO_MODE_OUTPUT; - gpio_conf.pin_bit_mask = BIT64(config->clk_out_gpio_num); - ESP_RETURN_ON_ERROR(gpio_config(&gpio_conf), TAG, "config clk out GPIO failed"); + gpio_func_sel(config->clk_out_gpio_num, PIN_FUNC_GPIO); + + // deprecated, to be removed in in esp-idf v6.0 + if (config->flags.io_loop_back) { + gpio_input_enable(config->clk_out_gpio_num); + } + + // connect the signal to the GPIO by matrix, it will also enable the output path properly esp_rom_gpio_connect_out_signal(config->clk_out_gpio_num, parlio_periph_signals.groups[group_id].rx_units[unit_id].clk_out_sig, false, false); #else @@ -287,15 +286,16 @@ static esp_err_t s_parlio_rx_unit_set_gpio(parlio_rx_unit_handle_t rx_unit, cons #endif // SOC_PARLIO_RX_CLK_SUPPORT_OUTPUT } - gpio_conf.mode = config->flags.io_loop_back ? GPIO_MODE_INPUT_OUTPUT : GPIO_MODE_INPUT; /* Initialize the valid GPIO as input */ if (config->valid_gpio_num >= 0) { - if (!config->flags.io_no_init) { - gpio_conf.pin_bit_mask = BIT64(config->valid_gpio_num); - ESP_RETURN_ON_ERROR(gpio_config(&gpio_conf), TAG, "config data GPIO failed"); - } else { - gpio_ll_input_enable(&GPIO, config->valid_gpio_num); + gpio_func_sel(config->valid_gpio_num, PIN_FUNC_GPIO); + gpio_input_enable(config->valid_gpio_num); + + // deprecated, to be removed in in esp-idf v6.0 + if (config->flags.io_loop_back) { + gpio_output_enable(config->valid_gpio_num); } + /* Not connect the signal here, the signal is lazy connected until the delimiter takes effect */ } @@ -303,12 +303,14 @@ static esp_err_t s_parlio_rx_unit_set_gpio(parlio_rx_unit_handle_t rx_unit, cons for (int i = 0; i < config->data_width; i++) { /* Loop the data_gpio_nums to connect data and valid signals via GPIO matrix */ if (config->data_gpio_nums[i] >= 0) { - if (!config->flags.io_no_init) { - gpio_conf.pin_bit_mask = BIT64(config->data_gpio_nums[i]); - ESP_RETURN_ON_ERROR(gpio_config(&gpio_conf), TAG, "config data GPIO failed"); - } else { - gpio_ll_input_enable(&GPIO, config->data_gpio_nums[i]); + gpio_func_sel(config->data_gpio_nums[i], PIN_FUNC_GPIO); + gpio_input_enable(config->data_gpio_nums[i]); + + // deprecated, to be removed in in esp-idf v6.0 + if (config->flags.io_loop_back) { + gpio_output_enable(config->data_gpio_nums[i]); } + esp_rom_gpio_connect_in_signal(config->data_gpio_nums[i], parlio_periph_signals.groups[group_id].rx_units[unit_id].data_sigs[i], false); } else { diff --git a/components/esp_driver_parlio/src/parlio_tx.c b/components/esp_driver_parlio/src/parlio_tx.c index dcf073ed264..e8ebaf86520 100644 --- a/components/esp_driver_parlio/src/parlio_tx.c +++ b/components/esp_driver_parlio/src/parlio_tx.c @@ -138,46 +138,59 @@ static esp_err_t parlio_tx_unit_configure_gpio(parlio_tx_unit_t *tx_unit, const { int group_id = tx_unit->base.group->group_id; int unit_id = tx_unit->base.unit_id; - gpio_config_t gpio_conf = { - .intr_type = GPIO_INTR_DISABLE, - .mode = config->flags.io_loop_back ? GPIO_MODE_INPUT_OUTPUT : GPIO_MODE_OUTPUT, - .pull_down_en = false, - .pull_up_en = true, - }; // connect peripheral signals via GPIO matrix for (size_t i = 0; i < config->data_width; i++) { if (config->data_gpio_nums[i] >= 0) { - gpio_conf.pin_bit_mask = BIT64(config->data_gpio_nums[i]); - ESP_RETURN_ON_ERROR(gpio_config(&gpio_conf), TAG, "config data GPIO failed"); + gpio_func_sel(config->data_gpio_nums[i], PIN_FUNC_GPIO); + + // deprecated, to be removed in in esp-idf v6.0 + if (config->flags.io_loop_back) { + gpio_input_enable(config->data_gpio_nums[i]); + } + + // connect the signal to the GPIO by matrix, it will also enable the output path properly esp_rom_gpio_connect_out_signal(config->data_gpio_nums[i], parlio_periph_signals.groups[group_id].tx_units[unit_id].data_sigs[i], false, false); - gpio_func_sel(config->data_gpio_nums[i], PIN_FUNC_GPIO); } } // Note: the valid signal will override TXD[PARLIO_LL_TX_DATA_LINE_AS_VALID_SIG] if (config->valid_gpio_num >= 0) { - gpio_conf.pin_bit_mask = BIT64(config->valid_gpio_num); - ESP_RETURN_ON_ERROR(gpio_config(&gpio_conf), TAG, "config valid GPIO failed"); + gpio_func_sel(config->valid_gpio_num, PIN_FUNC_GPIO); + + // deprecated, to be removed in in esp-idf v6.0 + if (config->flags.io_loop_back) { + gpio_input_enable(config->valid_gpio_num); + } + + // connect the signal to the GPIO by matrix, it will also enable the output path properly esp_rom_gpio_connect_out_signal(config->valid_gpio_num, parlio_periph_signals.groups[group_id].tx_units[unit_id].data_sigs[PARLIO_LL_TX_DATA_LINE_AS_VALID_SIG], false, false); - gpio_func_sel(config->valid_gpio_num, PIN_FUNC_GPIO); } if (config->clk_out_gpio_num >= 0) { - gpio_conf.pin_bit_mask = BIT64(config->clk_out_gpio_num); - ESP_RETURN_ON_ERROR(gpio_config(&gpio_conf), TAG, "config clk out GPIO failed"); + gpio_func_sel(config->clk_out_gpio_num, PIN_FUNC_GPIO); + + // deprecated, to be removed in in esp-idf v6.0 + if (config->flags.io_loop_back) { + gpio_input_enable(config->clk_out_gpio_num); + } + + // connect the signal to the GPIO by matrix, it will also enable the output path properly esp_rom_gpio_connect_out_signal(config->clk_out_gpio_num, parlio_periph_signals.groups[group_id].tx_units[unit_id].clk_out_sig, false, false); - gpio_func_sel(config->clk_out_gpio_num, PIN_FUNC_GPIO); } if (config->clk_in_gpio_num >= 0) { - gpio_conf.mode = config->flags.io_loop_back ? GPIO_MODE_INPUT_OUTPUT : GPIO_MODE_INPUT; - gpio_conf.pin_bit_mask = BIT64(config->clk_in_gpio_num); - ESP_RETURN_ON_ERROR(gpio_config(&gpio_conf), TAG, "config clk in GPIO failed"); + gpio_func_sel(config->clk_in_gpio_num, PIN_FUNC_GPIO); + gpio_input_enable(config->clk_in_gpio_num); + + // deprecated, to be removed in in esp-idf v6.0 + if (config->flags.io_loop_back) { + gpio_output_enable(config->clk_in_gpio_num); + } + esp_rom_gpio_connect_in_signal(config->clk_in_gpio_num, parlio_periph_signals.groups[group_id].tx_units[unit_id].clk_in_sig, false); - gpio_func_sel(config->clk_in_gpio_num, PIN_FUNC_GPIO); } return ESP_OK; } diff --git a/components/esp_driver_parlio/test_apps/parlio/main/test_parlio_rx.c b/components/esp_driver_parlio/test_apps/parlio/main/test_parlio_rx.c index cf5f0befcb2..d9d84cf0053 100644 --- a/components/esp_driver_parlio/test_apps/parlio/main/test_parlio_rx.c +++ b/components/esp_driver_parlio/test_apps/parlio/main/test_parlio_rx.c @@ -52,7 +52,6 @@ }, \ .flags = { \ .clk_gate_en = false, \ - .io_loop_back = true, \ } \ } @@ -528,6 +527,13 @@ TEST_CASE("parallel_rx_unit_receive_transaction_test", "[parlio_rx]") TEST_CASE("parallel_rx_unit_receive_timeout_test", "[parlio_rx]") { + printf("init a gpio to simulate valid signal\r\n"); + gpio_config_t test_gpio_conf = { + .mode = GPIO_MODE_OUTPUT, + .pin_bit_mask = BIT64(TEST_VALID_GPIO), + }; + TEST_ESP_OK(gpio_config(&test_gpio_conf)); + parlio_rx_unit_handle_t rx_unit = NULL; parlio_rx_delimiter_handle_t timeout_deli = NULL; @@ -583,5 +589,6 @@ TEST_CASE("parallel_rx_unit_receive_timeout_test", "[parlio_rx]") TEST_ESP_OK(parlio_rx_unit_disable(rx_unit)); TEST_ESP_OK(parlio_del_rx_delimiter(timeout_deli)); TEST_ESP_OK(parlio_del_rx_unit(rx_unit)); + TEST_ESP_OK(gpio_reset_pin(TEST_VALID_GPIO)); free(payload); } diff --git a/components/esp_driver_parlio/test_apps/parlio/main/test_parlio_tx.c b/components/esp_driver_parlio/test_apps/parlio/main/test_parlio_tx.c index a1fd71d8883..a556c8a407a 100644 --- a/components/esp_driver_parlio/test_apps/parlio/main/test_parlio_tx.c +++ b/components/esp_driver_parlio/test_apps/parlio/main/test_parlio_tx.c @@ -178,6 +178,13 @@ TEST_CASE("parallel_tx_unit_enable_disable", "[parlio_tx]") TEST_CASE("parallel_tx_unit_idle_value", "[parlio_tx]") { + printf("init a gpio to read parlio_tx output\r\n"); + gpio_config_t test_gpio_conf = { + .mode = GPIO_MODE_INPUT, + .pin_bit_mask = BIT64(TEST_DATA0_GPIO), + }; + TEST_ESP_OK(gpio_config(&test_gpio_conf)); + printf("install parlio tx unit\r\n"); parlio_tx_unit_handle_t tx_unit = NULL; parlio_tx_unit_config_t config = { @@ -201,7 +208,6 @@ TEST_CASE("parallel_tx_unit_idle_value", "[parlio_tx]") .max_transfer_size = 64, .bit_pack_order = PARLIO_BIT_PACK_ORDER_LSB, .sample_edge = PARLIO_SAMPLE_EDGE_POS, - .flags.io_loop_back = 1, // enable loop back by GPIO matrix, so that we can read the level of the data line by gpio driver }; TEST_ESP_OK(parlio_new_tx_unit(&config, &tx_unit)); TEST_ESP_OK(parlio_tx_unit_enable(tx_unit)); @@ -224,11 +230,19 @@ TEST_CASE("parallel_tx_unit_idle_value", "[parlio_tx]") TEST_ESP_OK(parlio_tx_unit_disable(tx_unit)); TEST_ESP_OK(parlio_del_tx_unit(tx_unit)); + TEST_ESP_OK(gpio_reset_pin(TEST_DATA0_GPIO)); } #if SOC_PARLIO_TX_CLK_SUPPORT_GATING TEST_CASE("parallel_tx_clock_gating", "[paralio_tx]") { + printf("init a gpio to read parlio_tx clk output\r\n"); + gpio_config_t test_gpio_conf = { + .mode = GPIO_MODE_INPUT, + .pin_bit_mask = BIT64(TEST_CLK_GPIO), + }; + TEST_ESP_OK(gpio_config(&test_gpio_conf)); + printf("install parlio tx unit\r\n"); parlio_tx_unit_handle_t tx_unit = NULL; parlio_tx_unit_config_t config = { @@ -247,7 +261,6 @@ TEST_CASE("parallel_tx_clock_gating", "[paralio_tx]") .bit_pack_order = PARLIO_BIT_PACK_ORDER_MSB, .sample_edge = PARLIO_SAMPLE_EDGE_POS, .flags.clk_gate_en = true, // enable clock gating, controlled by the level of TEST_DATA7_GPIO - .flags.io_loop_back = true, // for reading the level of the clock line in IDLE state }; TEST_ESP_OK(parlio_new_tx_unit(&config, &tx_unit)); TEST_ESP_OK(parlio_tx_unit_enable(tx_unit)); @@ -272,5 +285,6 @@ TEST_CASE("parallel_tx_clock_gating", "[paralio_tx]") TEST_ESP_OK(parlio_tx_unit_disable(tx_unit)); TEST_ESP_OK(parlio_del_tx_unit(tx_unit)); + TEST_ESP_OK(gpio_reset_pin(TEST_CLK_GPIO)); } #endif // SOC_PARLIO_TX_CLK_SUPPORT_GATING diff --git a/examples/peripherals/parlio/parlio_rx/logic_analyzer/components/esp_probe/hw_impl/esp_probe_impl_parlio.c b/examples/peripherals/parlio/parlio_rx/logic_analyzer/components/esp_probe/hw_impl/esp_probe_impl_parlio.c index 41de582782c..6ad6b4d238c 100644 --- a/examples/peripherals/parlio/parlio_rx/logic_analyzer/components/esp_probe/hw_impl/esp_probe_impl_parlio.c +++ b/examples/peripherals/parlio/parlio_rx/logic_analyzer/components/esp_probe/hw_impl/esp_probe_impl_parlio.c @@ -82,8 +82,6 @@ esp_err_t esp_probe_priv_init_hardware(esp_probe_handle_t handle, esp_probe_conf .valid_gpio_num = GPIO_NUM_NC, // Does not need valid gpio, all data gpio are used as sampling channel .flags = { .clk_gate_en = false, - .io_loop_back = true, - .io_no_init = true, } }; memcpy(parlio_rx_cfg.data_gpio_nums, config->probe_gpio, PARLIO_RX_UNIT_MAX_DATA_WIDTH * sizeof(gpio_num_t)); From c2d1f7a48c29e97dc5e3f0fea45b143ae63f6aa4 Mon Sep 17 00:00:00 2001 From: "C.S.M" Date: Sat, 12 Oct 2024 15:08:24 +0800 Subject: [PATCH 131/472] feat(esp32p4): Introduce p4 eco2 configuration --- .../port/soc/esp32p4/Kconfig.system | 27 ++++++++++++++++--- 1 file changed, 23 insertions(+), 4 deletions(-) diff --git a/components/esp_system/port/soc/esp32p4/Kconfig.system b/components/esp_system/port/soc/esp32p4/Kconfig.system index 5ffec7fe769..2e1d235b687 100644 --- a/components/esp_system/port/soc/esp32p4/Kconfig.system +++ b/components/esp_system/port/soc/esp32p4/Kconfig.system @@ -10,7 +10,7 @@ menu "Brownout Detector" choice ESP_BROWNOUT_DET_LVL_SEL prompt "Brownout voltage level" - depends on ESP_BROWNOUT_DET + depends on ESP_BROWNOUT_DET && (ESP32P4_REV_MIN_FULL <= 1) default ESP_BROWNOUT_DET_LVL_SEL_7 help The brownout detector will reset the chip when the supply voltage is approximately @@ -33,13 +33,32 @@ menu "Brownout Detector" bool "3.27V" endchoice + choice ESP_BROWNOUT_DET_LVL_SEL_V2 + prompt "Brownout voltage level" + default ESP_BROWNOUT_DET_LVL_SEL_7_V2 + depends on ESP_BROWNOUT_DET && (ESP32P4_REV_MIN_FULL >= 100) + help + The brownout detector will reset the chip when the supply voltage is approximately + below this level. Note that there may be some variation of brownout voltage level + between each chip. + + #The voltage levels here are estimates, more work needs to be done to figure out the exact voltages + #of the brownout threshold levels. + config ESP_BROWNOUT_DET_LVL_SEL_7_V2 + bool "2.6V" + config ESP_BROWNOUT_DET_LVL_SEL_6_V2 + bool "2.52V" + config ESP_BROWNOUT_DET_LVL_SEL_5_V2 + bool "2.42V" + endchoice + config ESP_BROWNOUT_DET_LVL int default 2 if ESP_BROWNOUT_DET_LVL_SEL_2 default 3 if ESP_BROWNOUT_DET_LVL_SEL_3 default 4 if ESP_BROWNOUT_DET_LVL_SEL_4 - default 5 if ESP_BROWNOUT_DET_LVL_SEL_5 - default 6 if ESP_BROWNOUT_DET_LVL_SEL_6 - default 7 if ESP_BROWNOUT_DET_LVL_SEL_7 + default 5 if ESP_BROWNOUT_DET_LVL_SEL_5 || ESP_BROWNOUT_DET_LVL_SEL_5_V2 + default 6 if ESP_BROWNOUT_DET_LVL_SEL_6 || ESP_BROWNOUT_DET_LVL_SEL_6_V2 + default 7 if ESP_BROWNOUT_DET_LVL_SEL_7 || ESP_BROWNOUT_DET_LVL_SEL_7_V2 endmenu From b148fb507e8f3fb30bc5806208ac07ff0a63645c Mon Sep 17 00:00:00 2001 From: zwx Date: Thu, 26 Sep 2024 12:15:58 +0800 Subject: [PATCH 132/472] fix(802154): pass hardware abort reason into processing function --- .../ieee802154/driver/esp_ieee802154_dev.c | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) diff --git a/components/ieee802154/driver/esp_ieee802154_dev.c b/components/ieee802154/driver/esp_ieee802154_dev.c index 5376f192411..6f8fdc2b61a 100644 --- a/components/ieee802154/driver/esp_ieee802154_dev.c +++ b/components/ieee802154/driver/esp_ieee802154_dev.c @@ -469,11 +469,10 @@ static IRAM_ATTR void isr_handle_ack_rx_done(void) NEEDS_NEXT_OPT(true); } -static IRAM_ATTR void isr_handle_rx_phase_rx_abort(void) +static IRAM_ATTR void isr_handle_rx_phase_rx_abort(ieee802154_ll_rx_abort_reason_t rx_abort_reason) { event_end_process(); uint32_t rx_status = ieee802154_ll_get_rx_status(); - ieee802154_ll_rx_abort_reason_t rx_abort_reason = ieee802154_ll_get_rx_abort_reason(); switch (rx_abort_reason) { case IEEE802154_RX_ABORT_BY_RX_STOP: case IEEE802154_RX_ABORT_BY_TX_ACK_STOP: @@ -508,13 +507,12 @@ static IRAM_ATTR void isr_handle_rx_phase_rx_abort(void) NEEDS_NEXT_OPT(true); } -static IRAM_ATTR void isr_handle_tx_ack_phase_rx_abort(void) +static IRAM_ATTR void isr_handle_tx_ack_phase_rx_abort(ieee802154_ll_rx_abort_reason_t rx_abort_reason) { event_end_process(); #if CONFIG_IEEE802154_TEST uint32_t rx_status = ieee802154_ll_get_rx_status(); #endif - ieee802154_ll_rx_abort_reason_t rx_abort_reason = ieee802154_ll_get_rx_abort_reason(); switch (rx_abort_reason) { case IEEE802154_RX_ABORT_BY_RX_STOP: case IEEE802154_RX_ABORT_BY_TX_ACK_STOP: @@ -553,10 +551,9 @@ static IRAM_ATTR void isr_handle_tx_ack_phase_rx_abort(void) NEEDS_NEXT_OPT(true); } -static IRAM_ATTR void isr_handle_tx_abort(void) +static IRAM_ATTR void isr_handle_tx_abort(ieee802154_ll_tx_abort_reason_t tx_abort_reason) { event_end_process(); - ieee802154_ll_tx_abort_reason_t tx_abort_reason = ieee802154_ll_get_tx_abort_reason(); switch (tx_abort_reason) { case IEEE802154_TX_ABORT_BY_RX_ACK_STOP: case IEEE802154_TX_ABORT_BY_TX_STOP: @@ -636,6 +633,8 @@ static void ieee802154_isr(void *arg) { ieee802154_enter_critical(); ieee802154_ll_events events = ieee802154_ll_get_events(); + ieee802154_ll_rx_abort_reason_t rx_abort_reason = ieee802154_ll_get_rx_abort_reason(); + ieee802154_ll_tx_abort_reason_t tx_abort_reason = ieee802154_ll_get_tx_abort_reason(); IEEE802154_PROBE(events); @@ -643,7 +642,7 @@ static void ieee802154_isr(void *arg) if (events & IEEE802154_EVENT_RX_ABORT) { // First phase rx abort process, will clear RX_ABORT event in second. - isr_handle_rx_phase_rx_abort(); + isr_handle_rx_phase_rx_abort(rx_abort_reason); } if (events & IEEE802154_EVENT_RX_SFD_DONE) { @@ -701,12 +700,12 @@ static void ieee802154_isr(void *arg) if (events & IEEE802154_EVENT_RX_ABORT) { // Second phase rx abort process, clears RX_ABORT event. - isr_handle_tx_ack_phase_rx_abort(); + isr_handle_tx_ack_phase_rx_abort(rx_abort_reason); events &= (uint16_t)(~IEEE802154_EVENT_RX_ABORT); } if (events & IEEE802154_EVENT_TX_ABORT) { - isr_handle_tx_abort(); + isr_handle_tx_abort(tx_abort_reason); events &= (uint16_t)(~IEEE802154_EVENT_TX_ABORT); } From a0ae573357a99e07a0214d32bf0180fc1f2a1acf Mon Sep 17 00:00:00 2001 From: Xu Si Yu Date: Wed, 17 Jul 2024 12:27:56 +0800 Subject: [PATCH 133/472] feat(openthread): support trel feature --- components/openthread/CMakeLists.txt | 18 +- components/openthread/Kconfig | 20 +- .../openthread/include/esp_openthread_trel.h | 38 ++ .../openthread/include/esp_openthread_types.h | 1 + .../openthread-core-esp32x-ftd-config.h | 30 +- .../src/port/esp_openthread_radio.c | 2 +- .../src/port/esp_openthread_radio_spinel.cpp | 1 - .../openthread/src/port/esp_openthread_trel.c | 374 ++++++++++++++++++ .../src/port/esp_spi_spinel_interface.cpp | 2 +- examples/openthread/.build-test-rules.yml | 5 + examples/openthread/ot_trel/CMakeLists.txt | 6 + examples/openthread/ot_trel/README.md | 132 +++++++ .../openthread/ot_trel/main/CMakeLists.txt | 2 + .../openthread/ot_trel/main/Kconfig.projbuild | 9 + .../openthread/ot_trel/main/esp_ot_config.h | 58 +++ .../openthread/ot_trel/main/esp_ot_trel.c | 141 +++++++ .../openthread/ot_trel/main/idf_component.yml | 11 + examples/openthread/ot_trel/partitions.csv | 5 + .../openthread/ot_trel/sdkconfig.defaults | 42 ++ 19 files changed, 883 insertions(+), 14 deletions(-) create mode 100644 components/openthread/include/esp_openthread_trel.h create mode 100644 components/openthread/src/port/esp_openthread_trel.c create mode 100644 examples/openthread/ot_trel/CMakeLists.txt create mode 100644 examples/openthread/ot_trel/README.md create mode 100644 examples/openthread/ot_trel/main/CMakeLists.txt create mode 100644 examples/openthread/ot_trel/main/Kconfig.projbuild create mode 100644 examples/openthread/ot_trel/main/esp_ot_config.h create mode 100644 examples/openthread/ot_trel/main/esp_ot_trel.c create mode 100644 examples/openthread/ot_trel/main/idf_component.yml create mode 100644 examples/openthread/ot_trel/partitions.csv create mode 100644 examples/openthread/ot_trel/sdkconfig.defaults diff --git a/components/openthread/CMakeLists.txt b/components/openthread/CMakeLists.txt index 51b66bb4489..0b555bbf04e 100644 --- a/components/openthread/CMakeLists.txt +++ b/components/openthread/CMakeLists.txt @@ -15,7 +15,6 @@ if(CONFIG_OPENTHREAD_ENABLED) set(private_include_dirs "openthread/examples/platforms" - "openthread/include/openthread" "openthread/src" "openthread/src/core" "openthread/src/lib" @@ -140,6 +139,19 @@ if(CONFIG_OPENTHREAD_ENABLED) list(APPEND exclude_srcs "src/port/esp_openthread_radio.c" "src/port/esp_openthread_sleep.c") + elseif(CONFIG_OPENTHREAD_RADIO_154_NONE) + list(APPEND exclude_srcs + "src/port/esp_openthread_radio_spinel.cpp" + "src/port/esp_spi_spinel_interface.cpp" + "src/port/esp_uart_spinel_interface.cpp" + "src/port/esp_openthread_radio.c" + "src/port/esp_openthread_sleep.c" + ) + endif() + + if(NOT CONFIG_OPENTHREAD_RADIO_TREL) + list(APPEND exclude_srcs + "src/port/esp_openthread_trel.c") endif() if(CONFIG_OPENTHREAD_BORDER_ROUTER) @@ -259,6 +271,10 @@ idf_component_register(SRC_DIRS "${src_dirs}" PRIV_REQUIRES console esp_event esp_partition esp_timer ieee802154 mbedtls nvs_flash) +if(CONFIG_OPENTHREAD_RADIO_TREL) +idf_component_optional_requires(PRIVATE espressif__mdns) +endif() + if(CONFIG_OPENTHREAD_ENABLED OR CONFIG_OPENTHREAD_SPINEL_ONLY) if(CONFIG_OPENTHREAD_RADIO) set(CONFIG_FILE_TYPE "radio") diff --git a/components/openthread/Kconfig b/components/openthread/Kconfig index 160084fbcb7..9ae0a6c63b9 100644 --- a/components/openthread/Kconfig +++ b/components/openthread/Kconfig @@ -101,7 +101,7 @@ menu "OpenThread" default 5 if OPENTHREAD_LOG_LEVEL_DEBG choice OPENTHREAD_RADIO_TYPE - prompt "Config the Thread radio type" + prompt "Config the Thread radio type with 15.4 link" depends on OPENTHREAD_ENABLED default OPENTHREAD_RADIO_NATIVE if SOC_IEEE802154_SUPPORTED default OPENTHREAD_RADIO_SPINEL_UART @@ -124,8 +124,26 @@ menu "OpenThread" help Select this to connect to a Radio Co-Processor via SPI. + config OPENTHREAD_RADIO_154_NONE + bool "Disable the Thread radio based on 15.4 link" + help + Select this to disable the Thread radio based on 15.4 link. endchoice + config OPENTHREAD_RADIO_TREL + bool "Enable Thread Radio Encapsulation Link (TREL)" + depends on SOC_WIFI_SUPPORTED + default n + help + Select this option to enable Thread Radio Encapsulation Link. + + config OPENTHREAD_TREL_PORT + int "The port of openthread trel service" + depends on OPENTHREAD_RADIO_TREL + default 12390 + help + Configure the port number of TREL service. + choice OPENTHREAD_DEVICE_TYPE prompt "Config the Thread device type" depends on OPENTHREAD_ENABLED diff --git a/components/openthread/include/esp_openthread_trel.h b/components/openthread/include/esp_openthread_trel.h new file mode 100644 index 00000000000..c2dc8c58b47 --- /dev/null +++ b/components/openthread/include/esp_openthread_trel.h @@ -0,0 +1,38 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include "sdkconfig.h" +#include "esp_netif.h" +#include "esp_netif_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Sets the interface used for trel feature. + * + * @note This function must be called after connect to wifi/ethernet + * + * @param[in] trel_netif The network interface (WiFi or ethernet) + * + */ +void esp_openthread_set_trel_netif(esp_netif_t *trel_netif); + +/** + * @brief Gets the trel interface of OpenThread device. + * + * @return + * The trel interface or NULL if trel not initialized. + * + */ +esp_netif_t *esp_openthread_get_trel_netif(void); + +#ifdef __cplusplus +} +#endif diff --git a/components/openthread/include/esp_openthread_types.h b/components/openthread/include/esp_openthread_types.h index 03095940194..e046c4606f3 100644 --- a/components/openthread/include/esp_openthread_types.h +++ b/components/openthread/include/esp_openthread_types.h @@ -117,6 +117,7 @@ typedef enum { RADIO_MODE_NATIVE = 0x0, /*!< Use the native 15.4 radio */ RADIO_MODE_UART_RCP, /*!< UART connection to a 15.4 capable radio co-processor (RCP) */ RADIO_MODE_SPI_RCP, /*!< SPI connection to a 15.4 capable radio co-processor (RCP) */ + RADIO_MODE_TREL, /*!< Use the Thread Radio Encapsulation Link (TREL) */ RADIO_MODE_MAX, /*!< Using for parameter check */ } esp_openthread_radio_mode_t; diff --git a/components/openthread/private_include/openthread-core-esp32x-ftd-config.h b/components/openthread/private_include/openthread-core-esp32x-ftd-config.h index aa8882f2341..0cd3542a914 100644 --- a/components/openthread/private_include/openthread-core-esp32x-ftd-config.h +++ b/components/openthread/private_include/openthread-core-esp32x-ftd-config.h @@ -203,28 +203,40 @@ #define OPENTHREAD_CONFIG_DNSSD_SERVER_ENABLE 1 #endif +/** + * @def OPENTHREAD_CONFIG_BACKBONE_ROUTER_ENABLE + * + * Define to 1 to enable Backbone Router support. + * + */ +#ifndef OPENTHREAD_CONFIG_BACKBONE_ROUTER_ENABLE +#define OPENTHREAD_CONFIG_BACKBONE_ROUTER_ENABLE 1 +#endif + +#endif // CONFIG_OPENTHREAD_BORDER_ROUTER + /** * @def OPENTHREAD_CONFIG_RADIO_LINK_TREL_ENABLE * * Set to 1 to enable support for Thread Radio Encapsulation Link (TREL). * */ -#ifndef OPENTHREAD_CONFIG_RADIO_LINK_TREL_ENABLE -#define OPENTHREAD_CONFIG_RADIO_LINK_TREL_ENABLE 0 -#endif +#if CONFIG_OPENTHREAD_RADIO_TREL +#define OPENTHREAD_CONFIG_RADIO_LINK_TREL_ENABLE 1 +#endif // CONFIG_OPENTHREAD_RADIO_TREL /** - * @def OPENTHREAD_CONFIG_BACKBONE_ROUTER_ENABLE + * @def OPENTHREAD_CONFIG_RADIO_LINK_IEEE_802_15_4_ENABLE * - * Define to 1 to enable Backbone Router support. + * Set to 1 to enable support for IEEE802.15.4 radio link. * */ -#ifndef OPENTHREAD_CONFIG_BACKBONE_ROUTER_ENABLE -#define OPENTHREAD_CONFIG_BACKBONE_ROUTER_ENABLE 1 +#if CONFIG_OPENTHREAD_RADIO_NATIVE || CONFIG_OPENTHREAD_RADIO_SPINEL_UART || CONFIG_OPENTHREAD_RADIO_SPINEL_SPI +#define OPENTHREAD_CONFIG_RADIO_LINK_IEEE_802_15_4_ENABLE 1 +#else +#define OPENTHREAD_CONFIG_RADIO_LINK_IEEE_802_15_4_ENABLE 0 #endif -#endif // CONFIG_OPENTHREAD_BORDER_ROUTER - #if !CONFIG_OPENTHREAD_RADIO_NATIVE /** * @def OPENTHREAD_SPINEL_CONFIG_RCP_RESTORATION_MAX_COUNT diff --git a/components/openthread/src/port/esp_openthread_radio.c b/components/openthread/src/port/esp_openthread_radio.c index 4276809c528..aac760c260d 100644 --- a/components/openthread/src/port/esp_openthread_radio.c +++ b/components/openthread/src/port/esp_openthread_radio.c @@ -7,7 +7,7 @@ #include #include "esp_openthread_radio.h" -#include "error.h" +#include "openthread/error.h" #include "esp_err.h" #include "sdkconfig.h" #include "esp_check.h" diff --git a/components/openthread/src/port/esp_openthread_radio_spinel.cpp b/components/openthread/src/port/esp_openthread_radio_spinel.cpp index 3d566b05e9a..b851c5608b5 100644 --- a/components/openthread/src/port/esp_openthread_radio_spinel.cpp +++ b/components/openthread/src/port/esp_openthread_radio_spinel.cpp @@ -6,7 +6,6 @@ #include "esp_openthread_radio.h" -#include "link_raw.h" #include "sdkconfig.h" #include "esp_check.h" #include "esp_err.h" diff --git a/components/openthread/src/port/esp_openthread_trel.c b/components/openthread/src/port/esp_openthread_trel.c new file mode 100644 index 00000000000..69c43f00ec7 --- /dev/null +++ b/components/openthread/src/port/esp_openthread_trel.c @@ -0,0 +1,374 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "esp_err.h" +#include "esp_netif_types.h" +#include "lwip/ip6_addr.h" +#include "sdkconfig.h" +#include "common/code_utils.hpp" +#include "openthread/error.h" +#include "esp_check.h" +#include "esp_event.h" +#include "esp_log.h" +#include "esp_netif.h" +#include "mdns.h" +#include "esp_netif_ip_addr.h" +#include "esp_openthread.h" +#include "esp_openthread_common_macro.h" +#include "esp_openthread_lock.h" +#include "esp_openthread_radio.h" +#include "esp_openthread_task_queue.h" +#include "esp_openthread_trel.h" +#include "lwip/pbuf.h" +#include "lwip/tcpip.h" +#include "lwip/udp.h" +#include "openthread/trel.h" +#include "openthread/platform/diag.h" + +#if CONFIG_OPENTHREAD_BORDER_ROUTER +#include "esp_openthread_border_router.h" +#endif + +static esp_netif_t *s_trel_netif = NULL; +static otPlatTrelCounters s_trel_counters; + +#define TREL_MDNS_TYPE "_trel" +#define TREL_MDNS_PROTO "_udp" + +typedef struct { + uint16_t port; + struct udp_pcb *trel_pcb; +} ot_trel_t; + +typedef struct { + struct pbuf *p; +} ot_trel_recv_task_t; + +typedef struct { + struct udp_pcb *pcb; + const uint8_t *payload; + uint16_t length; + ip_addr_t peer_addr; + uint16_t peer_port; +} ot_trel_send_task_t; + +static ot_trel_t s_ot_trel = {CONFIG_OPENTHREAD_TREL_PORT, NULL}; +static bool s_is_service_registered = false; + +static void trel_browse_notifier(mdns_result_t *result) +{ + while (result) { + + if (result->addr->addr.type == IPADDR_TYPE_V6) { + otPlatTrelPeerInfo info; + uint8_t trel_txt[1024] = {0}; + uint16_t trel_txt_len = 0; + size_t index = 0; + while (index < result->txt_count) { + trel_txt[trel_txt_len++] = strlen(result->txt[index].key) + result->txt_value_len[index] + 1; + memcpy((trel_txt + trel_txt_len), (void *)result->txt[index].key, strlen(result->txt[index].key)); + trel_txt_len += (strlen(result->txt[index].key)); + trel_txt[trel_txt_len++] = '='; + memcpy((trel_txt + trel_txt_len), (void *)result->txt[index].value, result->txt_value_len[index]); + trel_txt_len += result->txt_value_len[index]; + index++; + } + + info.mTxtData = trel_txt; + info.mTxtLength = trel_txt_len; + info.mSockAddr.mPort = result->port; + + memcpy(info.mSockAddr.mAddress.mFields.m32, result->addr->addr.u_addr.ip6.addr, OT_IP6_ADDRESS_SIZE); + + info.mRemoved = (result->ttl == 0); + ESP_LOGI(OT_PLAT_LOG_TAG, "Found TREL peer: address: %s, port:%d", ip6addr_ntoa(((ip6_addr_t*)(&result->addr->addr.u_addr.ip6))), info.mSockAddr.mPort); + + esp_openthread_task_switching_lock_acquire(portMAX_DELAY); + otPlatTrelHandleDiscoveredPeerInfo(esp_openthread_get_instance(), &info); + esp_openthread_task_switching_lock_release(); + } + + result = result->next; + } +} + +static void trel_recv_task(void *ctx) +{ + struct pbuf *recv_buf = (struct pbuf *)ctx; + uint8_t *data_buf = (uint8_t *)recv_buf->payload; + uint8_t *data_buf_to_free = NULL; + uint16_t length = recv_buf->len; + + if (recv_buf->next != NULL) { + data_buf = (uint8_t *)malloc(recv_buf->tot_len); + if (data_buf != NULL) { + length = recv_buf->tot_len; + data_buf_to_free = data_buf; + pbuf_copy_partial(recv_buf, data_buf, recv_buf->tot_len, 0); + } else { + ESP_LOGE(OT_PLAT_LOG_TAG, "Failed to allocate data buf when receiving Thread TREL message"); + ExitNow(); + } + } + otPlatTrelHandleReceived(esp_openthread_get_instance(), data_buf, length); + +exit: + if (data_buf_to_free) { + free(data_buf_to_free); + } + pbuf_free(recv_buf); +} + +static void handle_trel_udp_recv(void *ctx, struct udp_pcb *pcb, struct pbuf *p, const ip_addr_t *addr, uint16_t port) +{ + ESP_LOGD(OT_PLAT_LOG_TAG, "Receive from %s:%d", ip6addr_ntoa(&(addr->u_addr.ip6)), port); + + if (esp_openthread_task_queue_post(trel_recv_task, p) != ESP_OK) { + ESP_LOGE(OT_PLAT_LOG_TAG, "Failed to receive OpenThread TREL message"); + } +} + +static esp_err_t ot_new_trel(void *ctx) +{ + ot_trel_t *task = (ot_trel_t *)ctx; + + task->trel_pcb = udp_new(); + ESP_RETURN_ON_FALSE(task->trel_pcb != NULL, ESP_ERR_NO_MEM, OT_PLAT_LOG_TAG, "Failed to create a new UDP pcb"); + udp_bind(task->trel_pcb, IP6_ADDR_ANY, task->port); + udp_bind_netif(task->trel_pcb, netif_get_by_index(esp_netif_get_netif_impl_index(s_trel_netif))); + udp_recv(task->trel_pcb, handle_trel_udp_recv, NULL); + return ESP_OK; +} + +void otPlatTrelEnable(otInstance *aInstance, uint16_t *aUdpPort) +{ + *aUdpPort = s_ot_trel.port; + if (s_trel_netif == NULL) { + ESP_LOGE(OT_PLAT_LOG_TAG, "netif for trel is not set"); + assert(false); + } + + esp_openthread_task_switching_lock_release(); + esp_err_t err = esp_netif_tcpip_exec(ot_new_trel, &s_ot_trel); + if (err != ESP_OK) { + ESP_LOGE(OT_PLAT_LOG_TAG, "Fail to create trel udp"); + } + mdns_browse_new(TREL_MDNS_TYPE, TREL_MDNS_PROTO, trel_browse_notifier); + esp_openthread_task_switching_lock_acquire(portMAX_DELAY); +} + +static void trel_send_task(void *ctx) +{ + err_t err = ERR_OK; + struct pbuf *send_buf = NULL; + ot_trel_send_task_t *task = (ot_trel_send_task_t *)ctx; + + task->pcb = s_ot_trel.trel_pcb; + task->pcb->ttl = UDP_TTL; + task->pcb->netif_idx = esp_netif_get_netif_impl_index(s_trel_netif); + task->peer_addr.u_addr.ip6.zone = 0; + task->peer_addr.type = IPADDR_TYPE_V6; + task->pcb->flags = (task->pcb->flags & (~UDP_FLAGS_MULTICAST_LOOP)); + task->pcb->local_port = s_ot_trel.port; + send_buf = pbuf_alloc(PBUF_TRANSPORT, task->length, PBUF_RAM); + if (send_buf == NULL) { + ESP_LOGE(OT_PLAT_LOG_TAG, "Failed to allocate data buf when sending Thread TREL message"); + ExitNow(); + } + memcpy(send_buf->payload, task->payload, task->length); + + err = udp_sendto_if(task->pcb, send_buf, &task->peer_addr, task->peer_port, netif_get_by_index(task->pcb->netif_idx)); + if(err != ERR_OK) { + ESP_LOGE(OT_PLAT_LOG_TAG, "Fail to send trel msg to %s:%d %d (%d)", ip6addr_ntoa(&(task->peer_addr.u_addr.ip6)), task->peer_port, task->pcb->netif_idx, err); + } + +exit: + pbuf_free(send_buf); + free(task); +} + +void otPlatTrelSend(otInstance *aInstance, + const uint8_t *aUdpPayload, + uint16_t aUdpPayloadLen, + const otSockAddr *aDestSockAddr) +{ + ot_trel_send_task_t *task = (ot_trel_send_task_t *)malloc(sizeof(ot_trel_send_task_t)); + if (task == NULL) { + ESP_LOGE(OT_PLAT_LOG_TAG, "Failed to allocate buf for Thread TREL"); + return; + } + memcpy(task->peer_addr.u_addr.ip6.addr, aDestSockAddr->mAddress.mFields.m32, OT_IP6_ADDRESS_SIZE); + task->peer_port = aDestSockAddr->mPort; + ESP_LOGD(OT_PLAT_LOG_TAG, "send trel msg to %s:%d", ip6addr_ntoa(&(task->peer_addr.u_addr.ip6)), task->peer_port); + task->payload = aUdpPayload; + task->length = aUdpPayloadLen; + + esp_openthread_task_switching_lock_release(); + tcpip_callback(trel_send_task, task); + esp_openthread_task_switching_lock_acquire(portMAX_DELAY); +} + +void otPlatTrelRegisterService(otInstance *aInstance, uint16_t aPort, const uint8_t *aTxtData, uint8_t aTxtLength) +{ + esp_err_t ret = ESP_OK; + esp_openthread_task_switching_lock_release(); + if (s_is_service_registered) { + mdns_service_remove(TREL_MDNS_TYPE, TREL_MDNS_PROTO); + } + + mdns_service_add(NULL, TREL_MDNS_TYPE, TREL_MDNS_PROTO, aPort, NULL, 0); + s_is_service_registered = true; + uint16_t index = 0; + while (index < aTxtLength) { + const uint8_t *item_header = aTxtData + index + 1; + uint8_t item_len = aTxtData[index]; + + char key[UINT8_MAX + 1]; + for (uint16_t i = 0; i < item_len; i++) { + if (item_header[i] == '=') { + ESP_GOTO_ON_FALSE(i != 0, ESP_FAIL, exit, OT_PLAT_LOG_TAG, "Wrong format of _trel._udp txt key"); + key[i] = '\0'; + uint16_t value_len = item_len - i - 1; + ESP_GOTO_ON_FALSE(value_len != 0, ESP_FAIL, exit, OT_PLAT_LOG_TAG, "Wrong format of _trel._udp txt value"); + mdns_service_txt_item_set_with_explicit_value_len(TREL_MDNS_TYPE, TREL_MDNS_PROTO, key, (const char *)item_header + i + 1, value_len); + break; + } + key[i] = item_header[i]; + } + index += item_len + 1; + } +exit: + if (ret != ESP_OK) { + ESP_LOGE(OT_PLAT_LOG_TAG, "Registered TREL service with some errors"); + } + esp_openthread_task_switching_lock_acquire(portMAX_DELAY); +} + +void otPlatTrelResetCounters(otInstance *aInstance) +{ + memset(&s_trel_counters, 0, sizeof(otPlatTrelCounters)); +} + +static void trel_disable_task(void *ctx) +{ + struct udp_pcb *pcb = (struct udp_pcb *)ctx; + udp_remove(pcb); +} + +void otPlatTrelDisable(otInstance *aInstance) +{ + esp_openthread_task_switching_lock_release(); + if (s_ot_trel.trel_pcb) { + tcpip_callback(trel_disable_task, s_ot_trel.trel_pcb); + } + mdns_service_remove(TREL_MDNS_TYPE, TREL_MDNS_PROTO); + s_is_service_registered = false; + mdns_browse_delete(TREL_MDNS_TYPE, TREL_MDNS_PROTO); + esp_openthread_task_switching_lock_acquire(portMAX_DELAY); + s_ot_trel.trel_pcb = NULL; +} + +const otPlatTrelCounters *otPlatTrelGetCounters(otInstance *aInstance) +{ + return &s_trel_counters; +} + +void esp_openthread_set_trel_netif(esp_netif_t *trel_netif) +{ + s_trel_netif = trel_netif; +} + +esp_netif_t *esp_openthread_get_trel_netif(void) +{ + return s_trel_netif; +} + +OT_TOOL_WEAK otError otPlatRadioSetTransmitPower(otInstance *aInstance, int8_t aPower) +{ + ESP_LOGW(OT_PLAT_LOG_TAG, "Running in TREL mode and not support `otPlatRadioSetTransmitPower`"); + return OT_ERROR_NONE; +} + +OT_TOOL_WEAK otError otPlatRadioGetTransmitPower(otInstance *aInstance, int8_t *aPower) +{ + ESP_LOGW(OT_PLAT_LOG_TAG, "Running in TREL mode and not support `otPlatRadioGetTransmitPower`"); + return OT_ERROR_NONE; +} + +OT_TOOL_WEAK bool otPlatRadioGetPromiscuous(otInstance *aInstance) +{ + ESP_LOGW(OT_PLAT_LOG_TAG, "Running in TREL mode and not support `otPlatRadioGetPromiscuous`"); + return false; +} + +OT_TOOL_WEAK otError otPlatRadioSetCcaEnergyDetectThreshold(otInstance *aInstance, int8_t aThreshold) +{ + ESP_LOGW(OT_PLAT_LOG_TAG, "Running in TREL mode and not support `otPlatRadioSetCcaEnergyDetectThreshold`"); + return OT_ERROR_NONE; +} + +OT_TOOL_WEAK otError otPlatRadioGetCcaEnergyDetectThreshold(otInstance *aInstance, int8_t *aThreshold) +{ + ESP_LOGW(OT_PLAT_LOG_TAG, "Running in TREL mode and not support `otPlatRadioGetCcaEnergyDetectThreshold`"); + return OT_ERROR_NONE; +} + +OT_TOOL_WEAK void otPlatRadioGetIeeeEui64(otInstance *aInstance, uint8_t *aIeeeEui64) +{ + ESP_LOGW(OT_PLAT_LOG_TAG, "Running in TREL mode and not support `otPlatRadioGetIeeeEui64`"); +} + +OT_TOOL_WEAK otRadioFrame *otPlatRadioGetTransmitBuffer(otInstance *aInstance) +{ + return NULL; +} + +#if CONFIG_OPENTHREAD_DIAG + +OT_TOOL_WEAK void otPlatDiagSetOutputCallback(otInstance *aInstance, otPlatDiagOutputCallback aCallback, void *aContext) +{ + OT_UNUSED_VARIABLE(aInstance); + OT_UNUSED_VARIABLE(aCallback); + OT_UNUSED_VARIABLE(aContext); +} + +OT_TOOL_WEAK void otPlatDiagModeSet(bool mode) +{ + ESP_LOGW(OT_PLAT_LOG_TAG, "Running in TREL mode and not support `otPlatDiagModeSet`"); +} + +OT_TOOL_WEAK bool otPlatDiagModeGet(void) +{ + return false; +} + +OT_TOOL_WEAK void otPlatDiagTxPowerSet(int8_t tx_power) +{ + ESP_LOGW(OT_PLAT_LOG_TAG, "Running in TREL mode and not support `otPlatDiagTxPowerSet`"); +} + +OT_TOOL_WEAK void otPlatDiagChannelSet(uint8_t channel) +{ + ESP_LOGW(OT_PLAT_LOG_TAG, "Running in TREL mode and not support `otPlatDiagChannelSet`"); +} + +OT_TOOL_WEAK void otPlatDiagAlarmCallback(otInstance *aInstance) +{ + ESP_LOGW(OT_PLAT_LOG_TAG, "Running in TREL mode and not support `otPlatDiagAlarmCallback`"); +} + +#endif // CONFIG_OPENTHREAD_DIAG + +OT_TOOL_WEAK esp_err_t esp_openthread_radio_init(const esp_openthread_platform_config_t *config) +{ + ESP_LOGI(OT_PLAT_LOG_TAG, "Running in TREL mode"); + return ESP_OK; +} + +OT_TOOL_WEAK void esp_openthread_radio_deinit(void) +{ + ESP_LOGI(OT_PLAT_LOG_TAG, "Running in TREL mode"); +} diff --git a/components/openthread/src/port/esp_spi_spinel_interface.cpp b/components/openthread/src/port/esp_spi_spinel_interface.cpp index e19acd91527..61d6cfab2fa 100644 --- a/components/openthread/src/port/esp_spi_spinel_interface.cpp +++ b/components/openthread/src/port/esp_spi_spinel_interface.cpp @@ -6,7 +6,7 @@ #include "esp_spi_spinel_interface.hpp" -#include "error.h" +#include "openthread/error.h" #include "esp_check.h" #include "esp_openthread_common_macro.h" #include "esp_rom_sys.h" diff --git a/examples/openthread/.build-test-rules.yml b/examples/openthread/.build-test-rules.yml index ddd95daa389..81dfa9d20d6 100644 --- a/examples/openthread/.build-test-rules.yml +++ b/examples/openthread/.build-test-rules.yml @@ -59,3 +59,8 @@ examples/openthread/ot_sleepy_device/light_sleep: temporary: true reason: Not supported yet, TZ-958 <<: [*openthread_dependencies, *openthread_sleep_dependencies] + +examples/openthread/ot_trel: + enable: + - if: SOC_WIFI_SUPPORTED == 1 + <<: *openthread_dependencies diff --git a/examples/openthread/ot_trel/CMakeLists.txt b/examples/openthread/ot_trel/CMakeLists.txt new file mode 100644 index 00000000000..b12d49bfa30 --- /dev/null +++ b/examples/openthread/ot_trel/CMakeLists.txt @@ -0,0 +1,6 @@ +# The following lines of boilerplate have to be in your project's CMakeLists +# in this exact order for cmake to work correctly +cmake_minimum_required(VERSION 3.16) + +include($ENV{IDF_PATH}/tools/cmake/project.cmake) +project(esp_ot_cli) diff --git a/examples/openthread/ot_trel/README.md b/examples/openthread/ot_trel/README.md new file mode 100644 index 00000000000..ca6e9942d5a --- /dev/null +++ b/examples/openthread/ot_trel/README.md @@ -0,0 +1,132 @@ +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | + +# Thread Radio Encapsulation Link Example + +This example demonstrates a Thread Radio Encapsulation Link (TREL) Example. + +## How to use example + +### Hardware Required + +To run this example, a board with Wi-Fi module (for example ESP32-S3) is required. + +### Configure the project + +``` +idf.py menuconfig +``` + +The Wi-Fi ssid and password should be set through the menuconfig: +``` +Component config → → Example Connection Configuration → → WiFi SSID +Component config → → Example Connection Configuration → → WiFi Password +``` + +The example can run with the default configuration. OpenThread Command Line is enabled with UART as the default interface. Additionally, USB JTAG is also supported and can be activated through the menuconfig: + +``` +Component config → ESP System Settings → Channel for console output → USB Serial/JTAG Controller +``` + +### Build, Flash, and Run + +Build the project and flash it to the board, then run monitor tool to view serial output: + +``` +idf.py -p PORT build flash monitor +``` + +Now you'll get an OpenThread command line shell. + +### Example Output + +The `help` command will print all of the supported commands. +```bash +> help +I(7058) OPENTHREAD:[INFO]-CLI-----: execute command: help +bbr +bufferinfo +ccathreshold +channel +child +childip +childmax +childsupervision +childtimeout +coap +contextreusedelay +counters +dataset +delaytimermin +diag +discover +dns +domainname +eidcache +eui64 +extaddr +extpanid +factoryreset +... +``` + +## Set Up Network + +To run this example, at least two ESP32-S3 boards flashed with this ot_trel example are required. And they must connect to the same wifi AP. + +On the first device, run the following commands: +```bash +> factoryreset +... # the device will reboot + +> dataset init new +Done +> dataset commit active +Done +> ifconfig up +Done +> thread start +Done + +# After some seconds + +> state +leader +Done +``` +Now the first device has formed a Thread network as a leader. Get some information which will be used in next steps: +```bash +> ipaddr +fdde:ad00:beef:0:0:ff:fe00:fc00 +fdde:ad00:beef:0:0:ff:fe00:8000 +fdde:ad00:beef:0:a7c6:6311:9c8c:271b +fe80:0:0:0:5c27:a723:7115:c8f8 + +# Get the Active Dataset +> dataset active -x +0e080000000000010000000300001835060004001fffe00208fe7bb701f5f1125d0708fd75cbde7c6647bd0510b3914792d44f45b6c7d76eb9306eec94030f4f70656e5468726561642d35383332010258320410e35c581af5029b054fc904a24c2b27700c0402a0fff8 +``` + +On the second device, set the active dataset from leader, and start Thread interface: +```bash +> factoryreset +... # the device will reboot + +> dataset set active 0e080000000000010000000300001835060004001fffe00208fe7bb701f5f1125d0708fd75cbde7c6647bd0510b3914792d44f45b6c7d76eb9306eec94030f4f70656e5468726561642d35383332010258320410e35c581af5029b054fc904a24c2b27700c0402a0fff8 +> ifconfig up +Done +> thread start +Done + +# After some seconds + +> state +router # child is also a valid state +Done +``` +The second device has joined the Thread network as a router (or a child). + +## Extension commands + +You can refer to the [extension command](https://github.com/espressif/esp-thread-br/blob/main/components/esp_ot_cli_extension/README.md) about the extension commands. diff --git a/examples/openthread/ot_trel/main/CMakeLists.txt b/examples/openthread/ot_trel/main/CMakeLists.txt new file mode 100644 index 00000000000..cea684e5f9f --- /dev/null +++ b/examples/openthread/ot_trel/main/CMakeLists.txt @@ -0,0 +1,2 @@ +idf_component_register(SRCS "esp_ot_trel.c" + INCLUDE_DIRS ".") diff --git a/examples/openthread/ot_trel/main/Kconfig.projbuild b/examples/openthread/ot_trel/main/Kconfig.projbuild new file mode 100644 index 00000000000..32146234e0b --- /dev/null +++ b/examples/openthread/ot_trel/main/Kconfig.projbuild @@ -0,0 +1,9 @@ +menu "OpenThread CLI Example" + + config OPENTHREAD_AUTO_START + bool 'Enable the automatic start mode.' + default False + help + If enabled, the Openthread Device will create or connect to thread network with pre-configured + network parameters automatically. Otherwise, user need to configure Thread via CLI command manually. +endmenu diff --git a/examples/openthread/ot_trel/main/esp_ot_config.h b/examples/openthread/ot_trel/main/esp_ot_config.h new file mode 100644 index 00000000000..be8eff0e21c --- /dev/null +++ b/examples/openthread/ot_trel/main/esp_ot_config.h @@ -0,0 +1,58 @@ +/* + * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: CC0-1.0 + * + * OpenThread Command Line Example + * + * This example code is in the Public Domain (or CC0 licensed, at your option.) + * + * Unless required by applicable law or agreed to in writing, this + * software is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR + * CONDITIONS OF ANY KIND, either express or implied. + */ + +#pragma once + +#include "sdkconfig.h" +#include "esp_openthread_types.h" + +#define ESP_OPENTHREAD_DEFAULT_RADIO_CONFIG() \ + { \ + .radio_mode = RADIO_MODE_TREL, \ + } + +#if CONFIG_OPENTHREAD_CONSOLE_TYPE_UART +#define ESP_OPENTHREAD_DEFAULT_HOST_CONFIG() \ + { \ + .host_connection_mode = HOST_CONNECTION_MODE_CLI_UART, \ + .host_uart_config = { \ + .port = 0, \ + .uart_config = \ + { \ + .baud_rate = 115200, \ + .data_bits = UART_DATA_8_BITS, \ + .parity = UART_PARITY_DISABLE, \ + .stop_bits = UART_STOP_BITS_1, \ + .flow_ctrl = UART_HW_FLOWCTRL_DISABLE, \ + .rx_flow_ctrl_thresh = 0, \ + .source_clk = UART_SCLK_DEFAULT, \ + }, \ + .rx_pin = UART_PIN_NO_CHANGE, \ + .tx_pin = UART_PIN_NO_CHANGE, \ + }, \ + } +#elif CONFIG_OPENTHREAD_CONSOLE_TYPE_USB_SERIAL_JTAG +#define ESP_OPENTHREAD_DEFAULT_HOST_CONFIG() \ + { \ + .host_connection_mode = HOST_CONNECTION_MODE_CLI_USB, \ + .host_usb_config = USB_SERIAL_JTAG_DRIVER_CONFIG_DEFAULT(), \ + } +#endif + +#define ESP_OPENTHREAD_DEFAULT_PORT_CONFIG() \ + { \ + .storage_partition_name = "nvs", \ + .netif_queue_size = 10, \ + .task_queue_size = 10, \ + } diff --git a/examples/openthread/ot_trel/main/esp_ot_trel.c b/examples/openthread/ot_trel/main/esp_ot_trel.c new file mode 100644 index 00000000000..94c50799856 --- /dev/null +++ b/examples/openthread/ot_trel/main/esp_ot_trel.c @@ -0,0 +1,141 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: CC0-1.0 + * + * OpenThread Command Line Example + * + * This example code is in the Public Domain (or CC0 licensed, at your option.) + * + * Unless required by applicable law or agreed to in writing, this + * software is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR + * CONDITIONS OF ANY KIND, either express or implied. +*/ + +#include +#include +#include + +#include "sdkconfig.h" +#include "esp_err.h" +#include "esp_event.h" +#include "esp_log.h" +#include "esp_netif.h" +#include "esp_netif_types.h" +#include "esp_openthread.h" +#include "esp_openthread_cli.h" +#include "esp_openthread_lock.h" +#include "esp_openthread_netif_glue.h" +#include "esp_openthread_types.h" +#include "esp_ot_config.h" +#include "esp_vfs_eventfd.h" +#include "driver/uart.h" +#include "freertos/FreeRTOS.h" +#include "freertos/task.h" +#include "hal/uart_types.h" +#include "nvs_flash.h" +#include "openthread/cli.h" +#include "openthread/instance.h" +#include "openthread/logging.h" +#include "openthread/tasklet.h" +#include "esp_openthread_trel.h" +#include "protocol_examples_common.h" +#include "mdns.h" + +#if CONFIG_OPENTHREAD_STATE_INDICATOR_ENABLE +#include "ot_led_strip.h" +#endif + +#if CONFIG_OPENTHREAD_CLI_ESP_EXTENSION +#include "esp_ot_cli_extension.h" +#endif // CONFIG_OPENTHREAD_CLI_ESP_EXTENSION + + +#define TAG "ot_esp_trel" + +static esp_netif_t *init_openthread_netif(const esp_openthread_platform_config_t *config) +{ + esp_netif_config_t cfg = ESP_NETIF_DEFAULT_OPENTHREAD(); + esp_netif_t *netif = esp_netif_new(&cfg); + assert(netif != NULL); + ESP_ERROR_CHECK(esp_netif_attach(netif, esp_openthread_netif_glue_init(config))); + + return netif; +} + +static void ot_task_worker(void *aContext) +{ + esp_openthread_platform_config_t config = { + .radio_config = ESP_OPENTHREAD_DEFAULT_RADIO_CONFIG(), + .host_config = ESP_OPENTHREAD_DEFAULT_HOST_CONFIG(), + .port_config = ESP_OPENTHREAD_DEFAULT_PORT_CONFIG(), + }; + +#if !CONFIG_EXAMPLE_CONNECT_WIFI && !CONFIG_EXAMPLE_CONNECT_ETHERNET +#error No netif for TREL! +#endif + ESP_ERROR_CHECK(example_connect()); + assert(esp_openthread_get_trel_netif() == NULL); + esp_openthread_set_trel_netif(get_example_netif()); + + // Initialize the OpenThread stack + ESP_ERROR_CHECK(esp_openthread_init(&config)); + +#if CONFIG_OPENTHREAD_STATE_INDICATOR_ENABLE + ESP_ERROR_CHECK(esp_openthread_state_indicator_init(esp_openthread_get_instance())); +#endif + +#if CONFIG_OPENTHREAD_LOG_LEVEL_DYNAMIC + // The OpenThread log level directly matches ESP log level + (void)otLoggingSetLevel(CONFIG_LOG_DEFAULT_LEVEL); +#endif + // Initialize the OpenThread cli +#if CONFIG_OPENTHREAD_CLI + esp_openthread_cli_init(); +#endif + + esp_netif_t *openthread_netif; + // Initialize the esp_netif bindings + openthread_netif = init_openthread_netif(&config); + esp_netif_set_default_netif(openthread_netif); + +#if CONFIG_OPENTHREAD_CLI_ESP_EXTENSION + esp_cli_custom_command_init(); +#endif // CONFIG_OPENTHREAD_CLI_ESP_EXTENSION + + // Run the main loop +#if CONFIG_OPENTHREAD_CLI + esp_openthread_cli_create_task(); +#endif +#if CONFIG_OPENTHREAD_AUTO_START + otOperationalDatasetTlvs dataset; + otError error = otDatasetGetActiveTlvs(esp_openthread_get_instance(), &dataset); + ESP_ERROR_CHECK(esp_openthread_auto_start((error == OT_ERROR_NONE) ? &dataset : NULL)); +#endif + esp_openthread_launch_mainloop(); + + // Clean up + esp_openthread_netif_glue_deinit(); + esp_netif_destroy(openthread_netif); + + esp_vfs_eventfd_unregister(); + vTaskDelete(NULL); +} + +void app_main(void) +{ + // Used eventfds: + // * netif + // * ot task queue + esp_vfs_eventfd_config_t eventfd_config = { + .max_fds = 2, + }; + + ESP_ERROR_CHECK(nvs_flash_init()); + ESP_ERROR_CHECK(esp_event_loop_create_default()); + ESP_ERROR_CHECK(esp_netif_init()); + ESP_ERROR_CHECK(esp_vfs_eventfd_register(&eventfd_config)); + ESP_ERROR_CHECK(mdns_init()); + ESP_ERROR_CHECK(mdns_hostname_set("esp-ot-trel")); + xTaskCreate(ot_task_worker, "ot_trel_main", 8192, xTaskGetCurrentTaskHandle(), 5, NULL); +} diff --git a/examples/openthread/ot_trel/main/idf_component.yml b/examples/openthread/ot_trel/main/idf_component.yml new file mode 100644 index 00000000000..68d7abc65b5 --- /dev/null +++ b/examples/openthread/ot_trel/main/idf_component.yml @@ -0,0 +1,11 @@ +## IDF Component Manager Manifest File +dependencies: + espressif/esp_ot_cli_extension: + version: "~1.1.0" + espressif/mdns: "^1.0.3" + idf: + version: ">=4.1.0" + protocol_examples_common: + path: ${IDF_PATH}/examples/common_components/protocol_examples_common + ot_led: + path: ${IDF_PATH}/examples/openthread/ot_common_components/ot_led diff --git a/examples/openthread/ot_trel/partitions.csv b/examples/openthread/ot_trel/partitions.csv new file mode 100644 index 00000000000..641bcc9afcc --- /dev/null +++ b/examples/openthread/ot_trel/partitions.csv @@ -0,0 +1,5 @@ +# Name, Type, SubType, Offset, Size, Flags +# Note: if you have increased the bootloader size, make sure to update the offsets to avoid overlap +nvs, data, nvs, 0x9000, 0x6000, +phy_init, data, phy, 0xf000, 0x1000, +factory, app, factory, 0x10000, 0x170000, diff --git a/examples/openthread/ot_trel/sdkconfig.defaults b/examples/openthread/ot_trel/sdkconfig.defaults new file mode 100644 index 00000000000..0e7a865be63 --- /dev/null +++ b/examples/openthread/ot_trel/sdkconfig.defaults @@ -0,0 +1,42 @@ +# +# Partition Table +# +CONFIG_PARTITION_TABLE_CUSTOM=y +CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="partitions.csv" +CONFIG_PARTITION_TABLE_FILENAME="partitions.csv" +CONFIG_PARTITION_TABLE_OFFSET=0x8000 +CONFIG_PARTITION_TABLE_MD5=y +# end of Partition Table + +# +# mbedTLS +# +CONFIG_MBEDTLS_CMAC_C=y +CONFIG_MBEDTLS_SSL_PROTO_DTLS=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ECJPAKE=y +CONFIG_MBEDTLS_ECJPAKE_C=y +# end of mbedTLS + +# +# OpenThread +# +CONFIG_OPENTHREAD_ENABLED=y +CONFIG_OPENTHREAD_BORDER_ROUTER=n +CONFIG_OPENTHREAD_DNS64_CLIENT=y +CONFIG_OPENTHREAD_RADIO_154_NONE=y +CONFIG_OPENTHREAD_RADIO_TREL=y +# end of OpenThread + +# +# lwIP +# +CONFIG_LWIP_TCPIP_TASK_STACK_SIZE=4096 +CONFIG_LWIP_IPV6_NUM_ADDRESSES=8 +CONFIG_LWIP_MULTICAST_PING=y +CONFIG_LWIP_HOOK_IP6_SELECT_SRC_ADDR_CUSTOM=y +# end of lwIP + +# +# Configurations for optimizing the size of firmware +# +CONFIG_COMPILER_OPTIMIZATION_SIZE=y From 99f1eace072cdc79d41c46312d9c206f8828117f Mon Sep 17 00:00:00 2001 From: "C.S.M" Date: Sat, 12 Oct 2024 15:09:03 +0800 Subject: [PATCH 134/472] feat(bod): Update bod threshold on esp32p4-eco2 --- .../esp_hw_support/port/esp32p4/Kconfig.hw_support | 7 +++++-- components/hal/esp32h2/include/hal/brownout_ll.h | 3 ++- components/hal/esp32p4/include/hal/brownout_ll.h | 3 ++- components/soc/esp32h2/include/soc/regi2c_brownout.h | 12 ++++++++---- components/soc/esp32p4/include/soc/regi2c_brownout.h | 11 +++++++---- 5 files changed, 24 insertions(+), 12 deletions(-) diff --git a/components/esp_hw_support/port/esp32p4/Kconfig.hw_support b/components/esp_hw_support/port/esp32p4/Kconfig.hw_support index fe31a3aebef..46f9a88f302 100644 --- a/components/esp_hw_support/port/esp32p4/Kconfig.hw_support +++ b/components/esp_hw_support/port/esp32p4/Kconfig.hw_support @@ -13,12 +13,15 @@ choice ESP32P4_REV_MIN bool "Rev v0.0" config ESP32P4_REV_MIN_1 bool "Rev v0.1" + config ESP32P4_REV_MIN_100 + bool "Rev v1.0" endchoice config ESP32P4_REV_MIN_FULL int default 0 if ESP32P4_REV_MIN_0 default 1 if ESP32P4_REV_MIN_1 + default 100 if ESP32P4_REV_MIN_100 config ESP_REV_MIN_FULL int @@ -28,7 +31,7 @@ config ESP_REV_MIN_FULL # MAX Revision # - comment "Maximum Supported ESP32-P4 Revision (Rev v0.99)" + comment "Maximum Supported ESP32-P4 Revision (Rev v1.99)" # Maximum revision that IDF supports. # It can not be changed by user. # Only Espressif can change it when a new version will be supported in IDF. @@ -36,7 +39,7 @@ config ESP_REV_MIN_FULL config ESP32P4_REV_MAX_FULL int - default 99 + default 199 # keep in sync the "Maximum Supported Revision" description with this value config ESP_REV_MAX_FULL diff --git a/components/hal/esp32h2/include/hal/brownout_ll.h b/components/hal/esp32h2/include/hal/brownout_ll.h index 6553c8bd141..9dce284ac8b 100644 --- a/components/hal/esp32h2/include/hal/brownout_ll.h +++ b/components/hal/esp32h2/include/hal/brownout_ll.h @@ -69,7 +69,8 @@ static inline void brownout_ll_reset_config(bool reset_ena, uint32_t reset_wait, */ static inline void brownout_ll_set_threshold(uint8_t threshold) { - REGI2C_WRITE_MASK(I2C_BOD, I2C_BOD_THRESHOLD, threshold); + REGI2C_WRITE_MASK(I2C_BOD, I2C_BOD_THRESHOLD_L, threshold); + REGI2C_WRITE_MASK(I2C_BOD, I2C_BOD_THRESHOLD_H, threshold); } /** diff --git a/components/hal/esp32p4/include/hal/brownout_ll.h b/components/hal/esp32p4/include/hal/brownout_ll.h index 8327f9f8901..91e0e4560d0 100644 --- a/components/hal/esp32p4/include/hal/brownout_ll.h +++ b/components/hal/esp32p4/include/hal/brownout_ll.h @@ -68,7 +68,8 @@ static inline void brownout_ll_reset_config(bool reset_ena, uint32_t reset_wait, */ static inline void brownout_ll_set_threshold(uint8_t threshold) { - REGI2C_WRITE_MASK(I2C_BOD, I2C_BOD_THRESHOLD, threshold); + REGI2C_WRITE_MASK(I2C_BOD, I2C_BOD_THRESHOLD_L, threshold); + REGI2C_WRITE_MASK(I2C_BOD, I2C_BOD_THRESHOLD_H, threshold); } /** diff --git a/components/soc/esp32h2/include/soc/regi2c_brownout.h b/components/soc/esp32h2/include/soc/regi2c_brownout.h index 9daf67f093b..0d2caf531c1 100644 --- a/components/soc/esp32h2/include/soc/regi2c_brownout.h +++ b/components/soc/esp32h2/include/soc/regi2c_brownout.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -44,6 +44,10 @@ #define I2C_PMU_OR_DREFH_VDDA_MSB 7 #define I2C_PMU_OR_DREFH_VDDA_LSB 5 -#define I2C_BOD_THRESHOLD I2C_PMU_OR_DREFL_VDDA -#define I2C_BOD_THRESHOLD_MSB I2C_PMU_OR_DREFL_VDDA_MSB -#define I2C_BOD_THRESHOLD_LSB I2C_PMU_OR_DREFL_VDDA_LSB +#define I2C_BOD_THRESHOLD_L I2C_PMU_OR_DREFL_VDDA +#define I2C_BOD_THRESHOLD_L_MSB I2C_PMU_OR_DREFL_VDDA_MSB +#define I2C_BOD_THRESHOLD_L_LSB I2C_PMU_OR_DREFL_VDDA_LSB + +#define I2C_BOD_THRESHOLD_H I2C_PMU_OR_DREFH_VDDA +#define I2C_BOD_THRESHOLD_H_MSB I2C_PMU_OR_DREFH_VDDA_MSB +#define I2C_BOD_THRESHOLD_H_LSB I2C_PMU_OR_DREFH_VDDA_LSB diff --git a/components/soc/esp32p4/include/soc/regi2c_brownout.h b/components/soc/esp32p4/include/soc/regi2c_brownout.h index 0504a137056..b7297808f49 100644 --- a/components/soc/esp32p4/include/soc/regi2c_brownout.h +++ b/components/soc/esp32p4/include/soc/regi2c_brownout.h @@ -14,9 +14,12 @@ * bus. These definitions are used via macros defined in regi2c_ctrl.h. */ -#define I2C_BOD 0x61 +#define I2C_BOD 0x6a #define I2C_BOD_HOSTID 0 -#define I2C_BOD_THRESHOLD 0x5 -#define I2C_BOD_THRESHOLD_MSB 2 -#define I2C_BOD_THRESHOLD_LSB 0 +#define I2C_BOD_THRESHOLD_L 0x9 +#define I2C_BOD_THRESHOLD_L_MSB 4 +#define I2C_BOD_THRESHOLD_L_LSB 2 +#define I2C_BOD_THRESHOLD_H 0x9 +#define I2C_BOD_THRESHOLD_H_MSB 7 +#define I2C_BOD_THRESHOLD_H_LSB 5 From a26858618ae86a9e6cdf3dd0b61de66ca018136f Mon Sep 17 00:00:00 2001 From: diplfranzhoepfinger Date: Fri, 28 Jun 2024 13:22:17 +0200 Subject: [PATCH 135/472] fix(esp_wifi): Correct typos in example/scan.c Closes https://github.com/espressif/esp-idf/issues/14102 Closes https://github.com/espressif/esp-idf/pull/14103 --- examples/wifi/scan/main/scan.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/examples/wifi/scan/main/scan.c b/examples/wifi/scan/main/scan.c index 243b4a7a98f..1f4be36b224 100644 --- a/examples/wifi/scan/main/scan.c +++ b/examples/wifi/scan/main/scan.c @@ -22,7 +22,7 @@ #define DEFAULT_SCAN_LIST_SIZE CONFIG_EXAMPLE_SCAN_LIST_SIZE #ifdef CONFIG_EXAMPLE_USE_SCAN_CHANNEL_BITMAP -#define USE_CHANNEL_BTIMAP 1 +#define USE_CHANNEL_BITMAP 1 #define CHANNEL_LIST_SIZE 3 static uint8_t channel_list[CHANNEL_LIST_SIZE] = {1, 6, 11}; #endif /*CONFIG_EXAMPLE_USE_SCAN_CHANNEL_BITMAP*/ @@ -140,7 +140,7 @@ static void print_cipher_type(int pairwise_cipher, int group_cipher) } } -#ifdef USE_CHANNEL_BTIMAP +#ifdef USE_CHANNEL_BITMAP static void array_2_channel_bitmap(const uint8_t channel_list[], const uint8_t channel_list_size, wifi_scan_config_t *scan_config) { for(uint8_t i = 0; i < channel_list_size; i++) { @@ -148,7 +148,7 @@ static void array_2_channel_bitmap(const uint8_t channel_list[], const uint8_t c scan_config->channel_bitmap.ghz_2_channels |= (1 << channel); } } -#endif /*USE_CHANNEL_BTIMAP*/ +#endif /*USE_CHANNEL_BITMAP*/ /* Initialize Wi-Fi as sta and set scan method */ @@ -171,7 +171,7 @@ static void wifi_scan(void) ESP_ERROR_CHECK(esp_wifi_set_mode(WIFI_MODE_STA)); ESP_ERROR_CHECK(esp_wifi_start()); -#ifdef USE_CHANNEL_BTIMAP +#ifdef USE_CHANNEL_BITMAP wifi_scan_config_t *scan_config = (wifi_scan_config_t *)calloc(1,sizeof(wifi_scan_config_t)); if (!scan_config) { ESP_LOGE(TAG, "Memory Allocation for scan config failed!"); @@ -183,7 +183,7 @@ static void wifi_scan(void) #else esp_wifi_scan_start(NULL, true); -#endif /*USE_CHANNEL_BTIMAP*/ +#endif /*USE_CHANNEL_BITMAP*/ ESP_LOGI(TAG, "Max AP number ap_info can hold = %u", number); ESP_ERROR_CHECK(esp_wifi_scan_get_ap_num(&ap_count)); From 72bbb8c857fd4b6d7f6d992233b2abd6a6c1f7b4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Adam=20M=C3=BAdry?= Date: Fri, 11 Oct 2024 18:39:06 +0200 Subject: [PATCH 136/472] fix(sdmmc): Retry to get another RCA if the previous response was 0 --- components/sdmmc/sdmmc_cmd.c | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/components/sdmmc/sdmmc_cmd.c b/components/sdmmc/sdmmc_cmd.c index fb18a9d6962..ccd85402872 100644 --- a/components/sdmmc/sdmmc_cmd.c +++ b/components/sdmmc/sdmmc_cmd.c @@ -264,7 +264,22 @@ esp_err_t sdmmc_send_cmd_set_relative_addr(sdmmc_card_t* card, uint16_t* out_rca if (err != ESP_OK) { return err; } - *out_rca = (card->is_mmc) ? mmc_rca : SD_R6_RCA(cmd.response); + + if (card->is_mmc) { + *out_rca = mmc_rca; + } else { + uint16_t response_rca = SD_R6_RCA(cmd.response); + if (response_rca == 0) { + // Try to get another RCA value if RCA value in the previous response was 0x0000 + // The value 0x0000 is reserved to set all cards into the Stand-by State with CMD7 + err = sdmmc_send_cmd(card, &cmd); + if (err != ESP_OK) { + return err; + } + response_rca = SD_R6_RCA(cmd.response); + } + *out_rca = response_rca; + } return ESP_OK; } From 73aede6cc9d0c182faaf088babf4a990f84c0497 Mon Sep 17 00:00:00 2001 From: Xu Si Yu Date: Wed, 11 Sep 2024 22:00:59 +0800 Subject: [PATCH 137/472] feat(openthread): allow enabling trel before getting interface --- components/openthread/CMakeLists.txt | 2 +- components/openthread/Kconfig | 2 +- .../openthread/include/esp_openthread_trel.h | 38 --------- .../openthread-core-esp32x-ftd-config.h | 2 +- .../src/port/esp_openthread_radio.c | 2 +- .../openthread/src/port/esp_openthread_trel.c | 80 +++++++------------ examples/openthread/.build-test-rules.yml | 3 + examples/openthread/ot_trel/README.md | 7 +- .../openthread/ot_trel/main/Kconfig.projbuild | 2 +- .../openthread/ot_trel/main/esp_ot_trel.c | 10 +-- .../openthread/ot_trel/main/idf_component.yml | 2 +- examples/openthread/ot_trel/sdkconfig.ci.trel | 3 + .../openthread/ot_trel/sdkconfig.defaults | 1 + examples/openthread/pytest_otbr.py | 53 ++++++++++++ 14 files changed, 103 insertions(+), 104 deletions(-) delete mode 100644 components/openthread/include/esp_openthread_trel.h create mode 100644 examples/openthread/ot_trel/sdkconfig.ci.trel diff --git a/components/openthread/CMakeLists.txt b/components/openthread/CMakeLists.txt index 0b555bbf04e..66119f65aa4 100644 --- a/components/openthread/CMakeLists.txt +++ b/components/openthread/CMakeLists.txt @@ -272,7 +272,7 @@ idf_component_register(SRC_DIRS "${src_dirs}" ieee802154 mbedtls nvs_flash) if(CONFIG_OPENTHREAD_RADIO_TREL) -idf_component_optional_requires(PRIVATE espressif__mdns) + idf_component_optional_requires(PRIVATE espressif__mdns) endif() if(CONFIG_OPENTHREAD_ENABLED OR CONFIG_OPENTHREAD_SPINEL_ONLY) diff --git a/components/openthread/Kconfig b/components/openthread/Kconfig index 9ae0a6c63b9..d344f596152 100644 --- a/components/openthread/Kconfig +++ b/components/openthread/Kconfig @@ -132,7 +132,7 @@ menu "OpenThread" config OPENTHREAD_RADIO_TREL bool "Enable Thread Radio Encapsulation Link (TREL)" - depends on SOC_WIFI_SUPPORTED + depends on EXAMPLE_CONNECT_WIFI || EXAMPLE_CONNECT_ETHERNET default n help Select this option to enable Thread Radio Encapsulation Link. diff --git a/components/openthread/include/esp_openthread_trel.h b/components/openthread/include/esp_openthread_trel.h deleted file mode 100644 index c2dc8c58b47..00000000000 --- a/components/openthread/include/esp_openthread_trel.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#pragma once - -#include "sdkconfig.h" -#include "esp_netif.h" -#include "esp_netif_types.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief Sets the interface used for trel feature. - * - * @note This function must be called after connect to wifi/ethernet - * - * @param[in] trel_netif The network interface (WiFi or ethernet) - * - */ -void esp_openthread_set_trel_netif(esp_netif_t *trel_netif); - -/** - * @brief Gets the trel interface of OpenThread device. - * - * @return - * The trel interface or NULL if trel not initialized. - * - */ -esp_netif_t *esp_openthread_get_trel_netif(void); - -#ifdef __cplusplus -} -#endif diff --git a/components/openthread/private_include/openthread-core-esp32x-ftd-config.h b/components/openthread/private_include/openthread-core-esp32x-ftd-config.h index 0cd3542a914..ec948015059 100644 --- a/components/openthread/private_include/openthread-core-esp32x-ftd-config.h +++ b/components/openthread/private_include/openthread-core-esp32x-ftd-config.h @@ -231,7 +231,7 @@ * Set to 1 to enable support for IEEE802.15.4 radio link. * */ -#if CONFIG_OPENTHREAD_RADIO_NATIVE || CONFIG_OPENTHREAD_RADIO_SPINEL_UART || CONFIG_OPENTHREAD_RADIO_SPINEL_SPI +#if !CONFIG_OPENTHREAD_RADIO_154_NONE #define OPENTHREAD_CONFIG_RADIO_LINK_IEEE_802_15_4_ENABLE 1 #else #define OPENTHREAD_CONFIG_RADIO_LINK_IEEE_802_15_4_ENABLE 0 diff --git a/components/openthread/src/port/esp_openthread_radio.c b/components/openthread/src/port/esp_openthread_radio.c index aac760c260d..3e0f4286fe1 100644 --- a/components/openthread/src/port/esp_openthread_radio.c +++ b/components/openthread/src/port/esp_openthread_radio.c @@ -7,7 +7,6 @@ #include #include "esp_openthread_radio.h" -#include "openthread/error.h" #include "esp_err.h" #include "sdkconfig.h" #include "esp_check.h" @@ -25,6 +24,7 @@ #include "rom/ets_sys.h" #include "openthread-core-config.h" +#include "openthread/error.h" #include "openthread/link.h" #include "openthread/platform/diag.h" #include "openthread/platform/radio.h" diff --git a/components/openthread/src/port/esp_openthread_trel.c b/components/openthread/src/port/esp_openthread_trel.c index 69c43f00ec7..8424a7631d4 100644 --- a/components/openthread/src/port/esp_openthread_trel.c +++ b/components/openthread/src/port/esp_openthread_trel.c @@ -17,21 +17,17 @@ #include "mdns.h" #include "esp_netif_ip_addr.h" #include "esp_openthread.h" +#include "esp_openthread_border_router.h" #include "esp_openthread_common_macro.h" #include "esp_openthread_lock.h" #include "esp_openthread_radio.h" #include "esp_openthread_task_queue.h" -#include "esp_openthread_trel.h" #include "lwip/pbuf.h" #include "lwip/tcpip.h" #include "lwip/udp.h" #include "openthread/trel.h" #include "openthread/platform/diag.h" -#if CONFIG_OPENTHREAD_BORDER_ROUTER -#include "esp_openthread_border_router.h" -#endif - static esp_netif_t *s_trel_netif = NULL; static otPlatTrelCounters s_trel_counters; @@ -61,8 +57,7 @@ static bool s_is_service_registered = false; static void trel_browse_notifier(mdns_result_t *result) { while (result) { - - if (result->addr->addr.type == IPADDR_TYPE_V6) { + if (result->addr && result->addr->addr.type == IPADDR_TYPE_V6) { otPlatTrelPeerInfo info; uint8_t trel_txt[1024] = {0}; uint16_t trel_txt_len = 0; @@ -76,21 +71,19 @@ static void trel_browse_notifier(mdns_result_t *result) trel_txt_len += result->txt_value_len[index]; index++; } - + if (!s_trel_netif) { + s_trel_netif = result->esp_netif; + } info.mTxtData = trel_txt; info.mTxtLength = trel_txt_len; info.mSockAddr.mPort = result->port; - memcpy(info.mSockAddr.mAddress.mFields.m32, result->addr->addr.u_addr.ip6.addr, OT_IP6_ADDRESS_SIZE); - info.mRemoved = (result->ttl == 0); - ESP_LOGI(OT_PLAT_LOG_TAG, "Found TREL peer: address: %s, port:%d", ip6addr_ntoa(((ip6_addr_t*)(&result->addr->addr.u_addr.ip6))), info.mSockAddr.mPort); - + ESP_LOGI(OT_PLAT_LOG_TAG, "%s TREL peer: address: %s, port:%d", info.mRemoved ? "Remove" : "Found", ip6addr_ntoa(((ip6_addr_t*)(&result->addr->addr.u_addr.ip6))), info.mSockAddr.mPort); esp_openthread_task_switching_lock_acquire(portMAX_DELAY); otPlatTrelHandleDiscoveredPeerInfo(esp_openthread_get_instance(), &info); esp_openthread_task_switching_lock_release(); } - result = result->next; } } @@ -125,7 +118,6 @@ static void trel_recv_task(void *ctx) static void handle_trel_udp_recv(void *ctx, struct udp_pcb *pcb, struct pbuf *p, const ip_addr_t *addr, uint16_t port) { ESP_LOGD(OT_PLAT_LOG_TAG, "Receive from %s:%d", ip6addr_ntoa(&(addr->u_addr.ip6)), port); - if (esp_openthread_task_queue_post(trel_recv_task, p) != ESP_OK) { ESP_LOGE(OT_PLAT_LOG_TAG, "Failed to receive OpenThread TREL message"); } @@ -138,7 +130,6 @@ static esp_err_t ot_new_trel(void *ctx) task->trel_pcb = udp_new(); ESP_RETURN_ON_FALSE(task->trel_pcb != NULL, ESP_ERR_NO_MEM, OT_PLAT_LOG_TAG, "Failed to create a new UDP pcb"); udp_bind(task->trel_pcb, IP6_ADDR_ANY, task->port); - udp_bind_netif(task->trel_pcb, netif_get_by_index(esp_netif_get_netif_impl_index(s_trel_netif))); udp_recv(task->trel_pcb, handle_trel_udp_recv, NULL); return ESP_OK; } @@ -146,11 +137,6 @@ static esp_err_t ot_new_trel(void *ctx) void otPlatTrelEnable(otInstance *aInstance, uint16_t *aUdpPort) { *aUdpPort = s_ot_trel.port; - if (s_trel_netif == NULL) { - ESP_LOGE(OT_PLAT_LOG_TAG, "netif for trel is not set"); - assert(false); - } - esp_openthread_task_switching_lock_release(); esp_err_t err = esp_netif_tcpip_exec(ot_new_trel, &s_ot_trel); if (err != ESP_OK) { @@ -179,12 +165,10 @@ static void trel_send_task(void *ctx) ExitNow(); } memcpy(send_buf->payload, task->payload, task->length); - err = udp_sendto_if(task->pcb, send_buf, &task->peer_addr, task->peer_port, netif_get_by_index(task->pcb->netif_idx)); if(err != ERR_OK) { ESP_LOGE(OT_PLAT_LOG_TAG, "Fail to send trel msg to %s:%d %d (%d)", ip6addr_ntoa(&(task->peer_addr.u_addr.ip6)), task->peer_port, task->pcb->netif_idx, err); } - exit: pbuf_free(send_buf); free(task); @@ -195,6 +179,10 @@ void otPlatTrelSend(otInstance *aInstance, uint16_t aUdpPayloadLen, const otSockAddr *aDestSockAddr) { + if (!s_trel_netif) { + ESP_LOGE(OT_PLAT_LOG_TAG, "None Thread TREL interface"); + return; + } ot_trel_send_task_t *task = (ot_trel_send_task_t *)malloc(sizeof(ot_trel_send_task_t)); if (task == NULL) { ESP_LOGE(OT_PLAT_LOG_TAG, "Failed to allocate buf for Thread TREL"); @@ -205,7 +193,6 @@ void otPlatTrelSend(otInstance *aInstance, ESP_LOGD(OT_PLAT_LOG_TAG, "send trel msg to %s:%d", ip6addr_ntoa(&(task->peer_addr.u_addr.ip6)), task->peer_port); task->payload = aUdpPayload; task->length = aUdpPayloadLen; - esp_openthread_task_switching_lock_release(); tcpip_callback(trel_send_task, task); esp_openthread_task_switching_lock_acquire(portMAX_DELAY); @@ -214,11 +201,11 @@ void otPlatTrelSend(otInstance *aInstance, void otPlatTrelRegisterService(otInstance *aInstance, uint16_t aPort, const uint8_t *aTxtData, uint8_t aTxtLength) { esp_err_t ret = ESP_OK; + esp_openthread_task_switching_lock_release(); if (s_is_service_registered) { mdns_service_remove(TREL_MDNS_TYPE, TREL_MDNS_PROTO); } - mdns_service_add(NULL, TREL_MDNS_TYPE, TREL_MDNS_PROTO, aPort, NULL, 0); s_is_service_registered = true; uint16_t index = 0; @@ -276,53 +263,45 @@ const otPlatTrelCounters *otPlatTrelGetCounters(otInstance *aInstance) return &s_trel_counters; } -void esp_openthread_set_trel_netif(esp_netif_t *trel_netif) -{ - s_trel_netif = trel_netif; -} - -esp_netif_t *esp_openthread_get_trel_netif(void) -{ - return s_trel_netif; -} - +// TODO: TZ-1169 OT_TOOL_WEAK otError otPlatRadioSetTransmitPower(otInstance *aInstance, int8_t aPower) { - ESP_LOGW(OT_PLAT_LOG_TAG, "Running in TREL mode and not support `otPlatRadioSetTransmitPower`"); - return OT_ERROR_NONE; + ESP_LOGD(OT_PLAT_LOG_TAG, "Running in TREL mode and not support `otPlatRadioSetTransmitPower`"); + return OT_ERROR_NOT_IMPLEMENTED; } OT_TOOL_WEAK otError otPlatRadioGetTransmitPower(otInstance *aInstance, int8_t *aPower) { - ESP_LOGW(OT_PLAT_LOG_TAG, "Running in TREL mode and not support `otPlatRadioGetTransmitPower`"); - return OT_ERROR_NONE; + ESP_LOGD(OT_PLAT_LOG_TAG, "Running in TREL mode and not support `otPlatRadioGetTransmitPower`"); + return OT_ERROR_NOT_IMPLEMENTED; } OT_TOOL_WEAK bool otPlatRadioGetPromiscuous(otInstance *aInstance) { - ESP_LOGW(OT_PLAT_LOG_TAG, "Running in TREL mode and not support `otPlatRadioGetPromiscuous`"); + ESP_LOGD(OT_PLAT_LOG_TAG, "Running in TREL mode and not support `otPlatRadioGetPromiscuous`"); return false; } OT_TOOL_WEAK otError otPlatRadioSetCcaEnergyDetectThreshold(otInstance *aInstance, int8_t aThreshold) { - ESP_LOGW(OT_PLAT_LOG_TAG, "Running in TREL mode and not support `otPlatRadioSetCcaEnergyDetectThreshold`"); - return OT_ERROR_NONE; + ESP_LOGD(OT_PLAT_LOG_TAG, "Running in TREL mode and not support `otPlatRadioSetCcaEnergyDetectThreshold`"); + return OT_ERROR_NOT_IMPLEMENTED; } OT_TOOL_WEAK otError otPlatRadioGetCcaEnergyDetectThreshold(otInstance *aInstance, int8_t *aThreshold) { - ESP_LOGW(OT_PLAT_LOG_TAG, "Running in TREL mode and not support `otPlatRadioGetCcaEnergyDetectThreshold`"); - return OT_ERROR_NONE; + ESP_LOGD(OT_PLAT_LOG_TAG, "Running in TREL mode and not support `otPlatRadioGetCcaEnergyDetectThreshold`"); + return OT_ERROR_NOT_IMPLEMENTED; } OT_TOOL_WEAK void otPlatRadioGetIeeeEui64(otInstance *aInstance, uint8_t *aIeeeEui64) { - ESP_LOGW(OT_PLAT_LOG_TAG, "Running in TREL mode and not support `otPlatRadioGetIeeeEui64`"); + ESP_LOGD(OT_PLAT_LOG_TAG, "Running in TREL mode and not support `otPlatRadioGetIeeeEui64`"); } OT_TOOL_WEAK otRadioFrame *otPlatRadioGetTransmitBuffer(otInstance *aInstance) { + ESP_LOGD(OT_PLAT_LOG_TAG, "Running in TREL mode and not support `otPlatRadioGetTransmitBuffer`"); return NULL; } @@ -330,34 +309,33 @@ OT_TOOL_WEAK otRadioFrame *otPlatRadioGetTransmitBuffer(otInstance *aInstance) OT_TOOL_WEAK void otPlatDiagSetOutputCallback(otInstance *aInstance, otPlatDiagOutputCallback aCallback, void *aContext) { - OT_UNUSED_VARIABLE(aInstance); - OT_UNUSED_VARIABLE(aCallback); - OT_UNUSED_VARIABLE(aContext); + ESP_LOGD(OT_PLAT_LOG_TAG, "Running in TREL mode and not support `otPlatDiagSetOutputCallback`"); } OT_TOOL_WEAK void otPlatDiagModeSet(bool mode) { - ESP_LOGW(OT_PLAT_LOG_TAG, "Running in TREL mode and not support `otPlatDiagModeSet`"); + ESP_LOGD(OT_PLAT_LOG_TAG, "Running in TREL mode and not support `otPlatDiagModeSet`"); } OT_TOOL_WEAK bool otPlatDiagModeGet(void) { + ESP_LOGD(OT_PLAT_LOG_TAG, "Running in TREL mode and not support `otPlatDiagModeGet`"); return false; } OT_TOOL_WEAK void otPlatDiagTxPowerSet(int8_t tx_power) { - ESP_LOGW(OT_PLAT_LOG_TAG, "Running in TREL mode and not support `otPlatDiagTxPowerSet`"); + ESP_LOGD(OT_PLAT_LOG_TAG, "Running in TREL mode and not support `otPlatDiagTxPowerSet`"); } OT_TOOL_WEAK void otPlatDiagChannelSet(uint8_t channel) { - ESP_LOGW(OT_PLAT_LOG_TAG, "Running in TREL mode and not support `otPlatDiagChannelSet`"); + ESP_LOGD(OT_PLAT_LOG_TAG, "Running in TREL mode and not support `otPlatDiagChannelSet`"); } OT_TOOL_WEAK void otPlatDiagAlarmCallback(otInstance *aInstance) { - ESP_LOGW(OT_PLAT_LOG_TAG, "Running in TREL mode and not support `otPlatDiagAlarmCallback`"); + ESP_LOGD(OT_PLAT_LOG_TAG, "Running in TREL mode and not support `otPlatDiagAlarmCallback`"); } #endif // CONFIG_OPENTHREAD_DIAG diff --git a/examples/openthread/.build-test-rules.yml b/examples/openthread/.build-test-rules.yml index 81dfa9d20d6..9b109179895 100644 --- a/examples/openthread/.build-test-rules.yml +++ b/examples/openthread/.build-test-rules.yml @@ -63,4 +63,7 @@ examples/openthread/ot_sleepy_device/light_sleep: examples/openthread/ot_trel: enable: - if: SOC_WIFI_SUPPORTED == 1 + disable_test: + - if: IDF_TARGET not in ["esp32c6", "esp32s3"] + reason: only test on esp32c6 and esp32s3 <<: *openthread_dependencies diff --git a/examples/openthread/ot_trel/README.md b/examples/openthread/ot_trel/README.md index ca6e9942d5a..5cc60dfa2f1 100644 --- a/examples/openthread/ot_trel/README.md +++ b/examples/openthread/ot_trel/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | # Thread Radio Encapsulation Link Example @@ -34,7 +34,8 @@ Component config → ESP System Settings → Channel for console output → USB Build the project and flash it to the board, then run monitor tool to view serial output: ``` -idf.py -p PORT build flash monitor +idf.py build +idf.py -p PORT erase-flash flash monitor ``` Now you'll get an OpenThread command line shell. diff --git a/examples/openthread/ot_trel/main/Kconfig.projbuild b/examples/openthread/ot_trel/main/Kconfig.projbuild index 32146234e0b..7a37072f949 100644 --- a/examples/openthread/ot_trel/main/Kconfig.projbuild +++ b/examples/openthread/ot_trel/main/Kconfig.projbuild @@ -1,4 +1,4 @@ -menu "OpenThread CLI Example" +menu "OpenThread TREL Example" config OPENTHREAD_AUTO_START bool 'Enable the automatic start mode.' diff --git a/examples/openthread/ot_trel/main/esp_ot_trel.c b/examples/openthread/ot_trel/main/esp_ot_trel.c index 94c50799856..05b7251da4f 100644 --- a/examples/openthread/ot_trel/main/esp_ot_trel.c +++ b/examples/openthread/ot_trel/main/esp_ot_trel.c @@ -38,10 +38,13 @@ #include "openthread/instance.h" #include "openthread/logging.h" #include "openthread/tasklet.h" -#include "esp_openthread_trel.h" #include "protocol_examples_common.h" #include "mdns.h" +#if !CONFIG_EXAMPLE_CONNECT_WIFI && !CONFIG_EXAMPLE_CONNECT_ETHERNET +#error No netif for TREL! +#endif + #if CONFIG_OPENTHREAD_STATE_INDICATOR_ENABLE #include "ot_led_strip.h" #endif @@ -71,12 +74,7 @@ static void ot_task_worker(void *aContext) .port_config = ESP_OPENTHREAD_DEFAULT_PORT_CONFIG(), }; -#if !CONFIG_EXAMPLE_CONNECT_WIFI && !CONFIG_EXAMPLE_CONNECT_ETHERNET -#error No netif for TREL! -#endif ESP_ERROR_CHECK(example_connect()); - assert(esp_openthread_get_trel_netif() == NULL); - esp_openthread_set_trel_netif(get_example_netif()); // Initialize the OpenThread stack ESP_ERROR_CHECK(esp_openthread_init(&config)); diff --git a/examples/openthread/ot_trel/main/idf_component.yml b/examples/openthread/ot_trel/main/idf_component.yml index 68d7abc65b5..a52a17085f0 100644 --- a/examples/openthread/ot_trel/main/idf_component.yml +++ b/examples/openthread/ot_trel/main/idf_component.yml @@ -1,7 +1,7 @@ ## IDF Component Manager Manifest File dependencies: espressif/esp_ot_cli_extension: - version: "~1.1.0" + version: "~1.2.0" espressif/mdns: "^1.0.3" idf: version: ">=4.1.0" diff --git a/examples/openthread/ot_trel/sdkconfig.ci.trel b/examples/openthread/ot_trel/sdkconfig.ci.trel new file mode 100644 index 00000000000..994413fa4fc --- /dev/null +++ b/examples/openthread/ot_trel/sdkconfig.ci.trel @@ -0,0 +1,3 @@ +CONFIG_EXAMPLE_CONNECT_WIFI=y +CONFIG_EXAMPLE_WIFI_SSID="OTCITE" +CONFIG_EXAMPLE_WIFI_PASSWORD="otcitest888" diff --git a/examples/openthread/ot_trel/sdkconfig.defaults b/examples/openthread/ot_trel/sdkconfig.defaults index 0e7a865be63..99f65081b92 100644 --- a/examples/openthread/ot_trel/sdkconfig.defaults +++ b/examples/openthread/ot_trel/sdkconfig.defaults @@ -34,6 +34,7 @@ CONFIG_LWIP_TCPIP_TASK_STACK_SIZE=4096 CONFIG_LWIP_IPV6_NUM_ADDRESSES=8 CONFIG_LWIP_MULTICAST_PING=y CONFIG_LWIP_HOOK_IP6_SELECT_SRC_ADDR_CUSTOM=y +CONFIG_LWIP_IPV6_AUTOCONFIG=y # end of lwIP # diff --git a/examples/openthread/pytest_otbr.py b/examples/openthread/pytest_otbr.py index 604862d8d34..2abb6e4cb9c 100644 --- a/examples/openthread/pytest_otbr.py +++ b/examples/openthread/pytest_otbr.py @@ -59,6 +59,9 @@ # Case 14: Curl a website over HTTPS via DNS and NAT64 # A border router joins a Wi-Fi network and forms a Thread network, a Thread devices attached to it and curl a https website. +# Case 15: Thread network formation and attaching with TREL +# A TREL device forms a Thread network, other TREL devices attach to it, then test ping connection between them. + @pytest.fixture(scope='module', name='Init_avahi') def fixture_Init_avahi() -> bool: @@ -792,3 +795,53 @@ def test_https_NAT64_DNS(Init_interface:bool, dut: Tuple[IdfDut, IdfDut, IdfDut] ocf.execute_command(br, 'factoryreset') ocf.execute_command(cli, 'factoryreset') time.sleep(3) + + +# Case 15: Thread network formation and attaching with TREL +@pytest.mark.supported_targets +@pytest.mark.esp32c6 +@pytest.mark.openthread_br +@pytest.mark.flaky(reruns=1, reruns_delay=1) +@pytest.mark.parametrize( + 'config, count, app_path, target', [ + ('trel|trel', 2, + f'{os.path.join(os.path.dirname(__file__), "ot_trel")}' + f'|{os.path.join(os.path.dirname(__file__), "ot_trel")}', + 'esp32c6|esp32s3'), + ], + indirect=True, +) +def test_trel_connect(dut: Tuple[IdfDut, IdfDut]) -> None: + trel_s3 = dut[1] + trel_c6 = dut[0] + trel_list = [trel_c6] + router_extaddr_list = ['7766554433221101'] + + trel_s3.expect('IPv4 address:', timeout=10) + trel_c6.expect('IPv4 address:', timeout=10) + ocf.init_thread(trel_s3) + for trel in trel_list: + ocf.init_thread(trel) + trel_leader_para = copy.copy(default_br_ot_para) + trel_leader_para.bbr = False + ocf.joinThreadNetwork(trel_s3, trel_leader_para) + trel_para = copy.copy(default_cli_ot_para) + trel_para.dataset = ocf.getDataset(trel_s3) + try: + order = 0 + for trel in trel_list: + trel_para.exaddr = router_extaddr_list[order] + order = order + 1 + ocf.joinThreadNetwork(trel, trel_para) + for trel in trel_list: + trel_mleid_addr = ocf.get_mleid_addr(trel) + trel_s3_mleid_addr = ocf.get_mleid_addr(trel_s3) + rx_nums = ocf.ot_ping(trel, trel_s3_mleid_addr, 5)[1] + assert rx_nums == 5 + rx_nums = ocf.ot_ping(trel_s3, trel_mleid_addr, 5)[1] + assert rx_nums == 5 + finally: + ocf.execute_command(trel_s3, 'factoryreset') + for trel in trel_list: + ocf.execute_command(trel, 'factoryreset') + time.sleep(3) From 1c1198cf4a1ffaecbeddc806ac15f42b5ff3c6d3 Mon Sep 17 00:00:00 2001 From: morris Date: Sat, 12 Oct 2024 16:29:45 +0800 Subject: [PATCH 138/472] feat(dedic_gpio): enable pad input for the input signal previously, we asked the user to enable the gpio direction before initialize the dedicated GPIO. Now the dedicated GPIO driver will help enable the input/output path according to the in_en and out_en flags. --- components/esp_driver_gpio/src/dedic_gpio.c | 12 ++ .../main/test_dedicated_gpio.c | 26 +---- .../api-reference/peripherals/dedic_gpio.rst | 33 ++---- .../api-reference/peripherals/dedic_gpio.rst | 29 ++--- .../generic_gpio/main/gpio_example_main.c | 12 +- .../gpio/matrix_keyboard/README.md | 10 +- .../matrix_keyboard/include/matrix_keyboard.h | 18 +-- .../matrix_keyboard/src/matrix_keyboard.c | 107 ++++++------------ .../main/matrix_keyboard_example_main.c | 12 +- tools/ci/check_copyright_ignore.txt | 3 - 10 files changed, 89 insertions(+), 173 deletions(-) diff --git a/components/esp_driver_gpio/src/dedic_gpio.c b/components/esp_driver_gpio/src/dedic_gpio.c index bbc66995b2c..3faf0d9de7e 100644 --- a/components/esp_driver_gpio/src/dedic_gpio.c +++ b/components/esp_driver_gpio/src/dedic_gpio.c @@ -269,6 +269,7 @@ esp_err_t dedic_gpio_new_bundle(const dedic_gpio_bundle_config_t *config, dedic_ if (config->flags.in_en) { for (size_t i = 0; i < config->array_size; i++) { gpio_func_sel(config->gpio_array[i], PIN_FUNC_GPIO); + gpio_input_enable(config->gpio_array[i]); esp_rom_gpio_connect_in_signal(config->gpio_array[i], dedic_gpio_periph_signals.cores[core_id].in_sig_per_channel[in_offset + i], config->flags.in_invert); } } @@ -325,6 +326,17 @@ esp_err_t dedic_gpio_del_bundle(dedic_gpio_bundle_handle_t bundle) } portEXIT_CRITICAL(&s_platform[core_id]->spinlock); + if (bundle->in_mask > 0) { + for (size_t i = 0; i < bundle->nr_gpio; i++) { + esp_rom_gpio_connect_in_signal(GPIO_MATRIX_CONST_ZERO_INPUT, dedic_gpio_periph_signals.cores[core_id].in_sig_per_channel[bundle->in_offset + i], 0); + } + } + if (bundle->out_mask > 0) { + for (size_t i = 0; i < bundle->nr_gpio; i++) { + gpio_output_disable(bundle->gpio_array[i]); + } + } + free(bundle); if (recycle_all) { diff --git a/components/esp_driver_gpio/test_apps/gpio_extensions/main/test_dedicated_gpio.c b/components/esp_driver_gpio/test_apps/gpio_extensions/main/test_dedicated_gpio.c index fb306b523ee..9b3f73635e6 100644 --- a/components/esp_driver_gpio/test_apps/gpio_extensions/main/test_dedicated_gpio.c +++ b/components/esp_driver_gpio/test_apps/gpio_extensions/main/test_dedicated_gpio.c @@ -70,16 +70,8 @@ static void test_dedic_gpio_on_specific_core(void *args) uint32_t value = 0; dedic_gpio_cpu_ll_write_all(0x0); // clear all out channels - // configure a group of GPIOs, output only - const int bundleA_gpios[] = {ctx->gpios[0], ctx->gpios[1]}; - gpio_config_t io_conf = { - .mode = GPIO_MODE_OUTPUT, - }; - for (int i = 0; i < sizeof(bundleA_gpios) / sizeof(bundleA_gpios[0]); i++) { - io_conf.pin_bit_mask = 1ULL << bundleA_gpios[i]; - gpio_config(&io_conf); - } // Create bundleA, output only + const int bundleA_gpios[] = {ctx->gpios[0], ctx->gpios[1]}; dedic_gpio_bundle_handle_t bundleA = NULL; dedic_gpio_bundle_config_t bundleA_config = { .gpio_array = bundleA_gpios, @@ -90,15 +82,8 @@ static void test_dedic_gpio_on_specific_core(void *args) }; TEST_ESP_OK(dedic_gpio_new_bundle(&bundleA_config, &bundleA)); - // configure another group of GPIOs, input and output - const int bundleB_gpios[] = {ctx->gpios[2], ctx->gpios[3]}; - io_conf.mode = GPIO_MODE_INPUT_OUTPUT; - for (int i = 0; i < sizeof(bundleB_gpios) / sizeof(bundleB_gpios[0]); i++) { - io_conf.pin_bit_mask = 1ULL << bundleB_gpios[i]; - gpio_config(&io_conf); - } - // GPIO bundleB, input and output + const int bundleB_gpios[] = {ctx->gpios[2], ctx->gpios[3]}; dedic_gpio_bundle_handle_t bundleB = NULL; dedic_gpio_bundle_config_t bundleB_config = { .gpio_array = bundleB_gpios, @@ -192,13 +177,6 @@ TEST_CASE("Dedicated_GPIO_interrupt_and_callback", "[dedic_gpio]") #else const int bundle_gpios[] = {0, 1}; #endif - gpio_config_t io_conf = { - .mode = GPIO_MODE_INPUT_OUTPUT, - }; - for (int i = 0; i < sizeof(bundle_gpios) / sizeof(bundle_gpios[0]); i++) { - io_conf.pin_bit_mask = 1ULL << bundle_gpios[i]; - gpio_config(&io_conf); - } dedic_gpio_bundle_handle_t bundle = NULL; dedic_gpio_bundle_config_t bundle_config = { .gpio_array = bundle_gpios, diff --git a/docs/en/api-reference/peripherals/dedic_gpio.rst b/docs/en/api-reference/peripherals/dedic_gpio.rst index 319586f4f66..108abd73e18 100644 --- a/docs/en/api-reference/peripherals/dedic_gpio.rst +++ b/docs/en/api-reference/peripherals/dedic_gpio.rst @@ -16,32 +16,21 @@ A GPIO bundle is a group of GPIOs, which can be manipulated at the same time in .. note:: - Dedicated GPIO is more of a CPU peripheral, so it has a strong relationship with CPU core. It's highly recommended to install and operate GPIO bundle in a pin-to-core task. For example, if GPIOA is connected to CPU0, and the dedicated GPIO instruction is issued from CPU1, then it's impossible to control GPIOA. + Dedicated GPIO is more like a CPU peripheral, it has a strong relationship with CPU core. It's highly recommended to install and operate GPIO bundle in the same task, and the task should be pined to a CPU core. For example, if GPIO_A is connected to CPU_0, but the dedicated GPIO instruction is issued from CPU_1, then it's impossible to control GPIO_A. To install a GPIO bundle, one needs to call :cpp:func:`dedic_gpio_new_bundle` to allocate the software resources and connect the dedicated channels to user selected GPIOs. Configurations for a GPIO bundle are covered in :cpp:type:`dedic_gpio_bundle_config_t` structure: -- :cpp:member:`gpio_array`: An array that contains GPIO number. -- :cpp:member:`array_size`: Element number of :cpp:member:`gpio_array`. -- :cpp:member:`flags`: Extra flags to control the behavior of GPIO Bundle. +- :cpp:member:`dedic_gpio_bundle_config_t::gpio_array`: An array that contains GPIO number. +- :cpp:member:`dedic_gpio_bundle_config_t::array_size`: Element number of :cpp:member:`dedic_gpio_bundle_config_t::gpio_array`. +- :cpp:member:`dedic_gpio_bundle_config_t::in_en` and :cpp:member:`dedic_gpio_bundle_config_t::out_en` are used to configure whether to enable the input and output ability of the GPIO(s). +- :cpp:member:`dedic_gpio_bundle_config_t::in_invert` and :cpp:member:`dedic_gpio_bundle_config_t::out_invert` are used to configure whether to invert the GPIO signal. - - :cpp:member:`in_en` and :cpp:member:`out_en` are used to select whether to enable the input and output function (note, they can be enabled together). - - :cpp:member:`in_invert` and :cpp:member:`out_invert` are used to select whether to invert the GPIO signal. - -The following code shows how to install a output only GPIO bundle: +The following code shows how to install an output only GPIO bundle: .. highlight:: c :: - // configure GPIO - const int bundleA_gpios[] = {0, 1}; - gpio_config_t io_conf = { - .mode = GPIO_MODE_OUTPUT, - }; - for (int i = 0; i < sizeof(bundleA_gpios) / sizeof(bundleA_gpios[0]); i++) { - io_conf.pin_bit_mask = 1ULL << bundleA_gpios[i]; - gpio_config(&io_conf); - } // Create bundleA, output only dedic_gpio_bundle_handle_t bundleA = NULL; dedic_gpio_bundle_config_t bundleA_config = { @@ -53,11 +42,7 @@ The following code shows how to install a output only GPIO bundle: }; ESP_ERROR_CHECK(dedic_gpio_new_bundle(&bundleA_config, &bundleA)); -To uninstall the GPIO bundle, one needs to call :cpp:func:`dedic_gpio_del_bundle`. - -.. note:: - - :cpp:func:`dedic_gpio_new_bundle` doesn't cover any GPIO pad configuration (e.g., pull up/down, drive ability, output/input enable), so before installing a dedicated GPIO bundle, you have to configure the GPIO separately using GPIO driver API (e.g., :cpp:func:`gpio_config`). For more information about GPIO driver, please refer to :doc:`GPIO API Reference `. +To uninstall the GPIO bundle, you should call :cpp:func:`dedic_gpio_del_bundle`. GPIO Bundle Operations @@ -92,13 +77,13 @@ For advanced users, they can always manipulate the GPIOs by writing assembly cod 3. Call CPU LL apis (e.g., `dedic_gpio_cpu_ll_write_mask`) or write assembly code with that mask 4. The fastest way of toggling IO is to use the dedicated "set/clear" instructions: - .. only:: esp32s2 or esp32s3 + .. only:: CONFIG_IDF_TARGET_ARCH_XTENSA - Set bits of GPIO: ``set_bit_gpio_out imm[7:0]`` - Clear bits of GPIO: ``clr_bit_gpio_out imm[7:0]`` - Note: Immediate value width depends on the number of dedicated GPIO channels - .. only:: esp32c2 or esp32c3 or esp32c6 or esp32h2 + .. only:: CONFIG_IDF_TARGET_ARCH_RISCV - Set bits of GPIO: ``csrrsi rd, csr, imm[4:0]`` - Clear bits of GPIO: ``csrrci rd, csr, imm[4:0]`` diff --git a/docs/zh_CN/api-reference/peripherals/dedic_gpio.rst b/docs/zh_CN/api-reference/peripherals/dedic_gpio.rst index 68d58211dbb..37f4979bf97 100644 --- a/docs/zh_CN/api-reference/peripherals/dedic_gpio.rst +++ b/docs/zh_CN/api-reference/peripherals/dedic_gpio.rst @@ -16,16 +16,14 @@ GPIO 捆绑包是一组 GPIO，该组 GPIO 可以在一个 CPU 周期内同时 .. note:: - 专用 GPIO 更像是 CPU 外设，因此与 CPU 内核关系密切。强烈建议在 pin-to-core 任务中安装和操作 GPIO 捆绑包。例如，如果 GPIOA 连接到了 CPU0，而专用的 GPIO 指令却是从 CPU1 发出的，那么就无法控制 GPIOA。 + 专用 GPIO 更像是 CPU 外设，因此与 CPU 内核关系密切。强烈建议在 pin-to-core 任务中安装和操作 GPIO 捆绑包。例如，如果 GPIO_A 连接到了 CPU_0，而专用的 GPIO 指令却是从 CPU_1 发出的，那么就无法控制 GPIO_A。 安装 GPIO 捆绑包需要调用 :cpp:func:`dedic_gpio_new_bundle` 来分配软件资源并将专用通道连接到用户选择的 GPIO。GPIO 捆绑包的配置在 :cpp:type:`dedic_gpio_bundle_config_t` 结构体中： -- :cpp:member:`gpio_array`：包含 GPIO 编号的数组。 -- :cpp:member:`array_size`：:cpp:member:`gpio_array` 的元素个数。 -- :cpp:member:`flags`：用于控制 GPIO 捆绑包行为的标志。 - - - :cpp:member:`in_en` 和 :cpp:member:`out_en` 用于选择是否开启输入输出功能（这两个功能可以同时开启）。 - - :cpp:member:`in_invert` 和 :cpp:member:`out_invert` 用于选择是否反转 GPIO 信号。 +- :cpp:member:`dedic_gpio_bundle_config_t::gpio_array`：包含 GPIO 编号的数组。 +- :cpp:member:`dedic_gpio_bundle_config_t::array_size`: :cpp:member:`dedic_gpio_bundle_config_t::gpio_array` 的元素个数。 +- :cpp:member:`dedic_gpio_bundle_config_t::in_en` 和 :cpp:member:`dedic_gpio_bundle_config_t::out_en` 用于选择是否开启输入输出功能（这两个功能可以同时开启）。 +- :cpp:member:`dedic_gpio_bundle_config_t::in_invert` 和 :cpp:member:`dedic_gpio_bundle_config_t::out_invert` 用于选择是否反转 GPIO 信号。 以下代码展示了如何安装只有输出功能的 GPIO 捆绑包： @@ -33,15 +31,6 @@ GPIO 捆绑包是一组 GPIO，该组 GPIO 可以在一个 CPU 周期内同时 :: - // 配置 GPIO - const int bundleA_gpios[] = {0, 1}; - gpio_config_t io_conf = { - .mode = GPIO_MODE_OUTPUT, - }; - for (int i = 0; i < sizeof(bundleA_gpios) / sizeof(bundleA_gpios[0]); i++) { - io_conf.pin_bit_mask = 1ULL << bundleA_gpios[i]; - gpio_config(&io_conf); - } // 创建 bundleA，仅输出 dedic_gpio_bundle_handle_t bundleA = NULL; dedic_gpio_bundle_config_t bundleA_config = { @@ -55,10 +44,6 @@ GPIO 捆绑包是一组 GPIO，该组 GPIO 可以在一个 CPU 周期内同时 如需卸载 GPIO 捆绑包，可调用 :cpp:func:`dedic_gpio_del_bundle`。 -.. note:: - - :cpp:func:`dedic_gpio_new_bundle` 不包含任何 GPIO pad 配置（例如上拉/下拉、驱动能力、输出/输入使能）。因此，在安装专用 GPIO 捆绑包之前，必须使用 GPIO 驱动程序 API（如 :cpp:func:`gpio_config`）单独配置 GPIO。更多关于 GPIO 驱动的信息，请参考 :doc:`GPIO API 参考 `。 - GPIO 捆绑包操作 ---------------------- @@ -92,13 +77,13 @@ GPIO 捆绑包操作 3. 调用 CPU LL apis（如 `cpu_ll_write_dedic_gpio_mask`）或使用该掩码编写汇编代码 4. 切换 IO 的最快捷方式是使用专用的“设置/清除”指令： - .. only:: esp32s2 or esp32s3 + .. only:: CONFIG_IDF_TARGET_ARCH_XTENSA - 设置 GPIO 位：``set_bit_gpio_out imm[7:0]`` - 清除 GPIO 位：``clr_bit_gpio_out imm[7:0]`` - 注意：立即数宽度取决于专用 GPIO 通道的数量 - .. only:: esp32c2 or esp32c3 or esp32c6 or esp32h2 + .. only:: CONFIG_IDF_TARGET_ARCH_RISCV - 设置 GPIO 位：``csrrsi rd, csr, imm[4:0]`` - 清除 GPIO 位：``csrrci rd, csr, imm[4:0]`` diff --git a/examples/peripherals/gpio/generic_gpio/main/gpio_example_main.c b/examples/peripherals/gpio/generic_gpio/main/gpio_example_main.c index 27b22cdaa4d..89b7bbc88a4 100644 --- a/examples/peripherals/gpio/generic_gpio/main/gpio_example_main.c +++ b/examples/peripherals/gpio/generic_gpio/main/gpio_example_main.c @@ -1,11 +1,9 @@ -/* GPIO Example - - This example code is in the Public Domain (or CC0 licensed, at your option.) +/* + * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ - Unless required by applicable law or agreed to in writing, this - software is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR - CONDITIONS OF ANY KIND, either express or implied. -*/ #include #include #include diff --git a/examples/peripherals/gpio/matrix_keyboard/README.md b/examples/peripherals/gpio/matrix_keyboard/README.md index 31cd207e55d..76d095e4172 100644 --- a/examples/peripherals/gpio/matrix_keyboard/README.md +++ b/examples/peripherals/gpio/matrix_keyboard/README.md @@ -23,7 +23,7 @@ This matrix keyboard driver is interrupt-driven, supports a configurable debounc This example can run on any target that has the dedicated feature (e.g. ESP32-S2). It's not necessary for your matrix board to have pull-up resisters on row/column lines. The driver has enabled internal pull-up resister by default. A typical matrix board should look as follows: -``` +```text row_0 +--------+-------------------+------------------------------+-----------------+ | | | | + | + | + @@ -51,7 +51,7 @@ row_n +--------+-------------------+------------------------------+----------- Build the project and flash it to the board, then run monitor tool to view serial output: -``` +```text idf.py -p PORT flash monitor ``` @@ -63,7 +63,7 @@ See the Getting Started Guide for full steps to configure and use ESP-IDF to bui ## Example Output -``` +```text I (2883) example: press event, key code = 0002 I (3003) example: release event, key code = 0002 I (5053) example: press event, key code = 0001 @@ -77,3 +77,7 @@ I (8923) example: release event, key code = 0103 I (9543) example: press event, key code = 0203 I (9683) example: release event, key code = 0203 ``` + +## Troubleshooting + +For any technical queries, please open an [issue](https://github.com/espressif/esp-idf/issues) on GitHub. We will get back to you soon. diff --git a/examples/peripherals/gpio/matrix_keyboard/components/matrix_keyboard/include/matrix_keyboard.h b/examples/peripherals/gpio/matrix_keyboard/components/matrix_keyboard/include/matrix_keyboard.h index 825ae314693..f4598c74cb9 100644 --- a/examples/peripherals/gpio/matrix_keyboard/components/matrix_keyboard/include/matrix_keyboard.h +++ b/examples/peripherals/gpio/matrix_keyboard/components/matrix_keyboard/include/matrix_keyboard.h @@ -1,16 +1,8 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #pragma once diff --git a/examples/peripherals/gpio/matrix_keyboard/components/matrix_keyboard/src/matrix_keyboard.c b/examples/peripherals/gpio/matrix_keyboard/components/matrix_keyboard/src/matrix_keyboard.c index daf1b6a3416..48b7a23506e 100644 --- a/examples/peripherals/gpio/matrix_keyboard/components/matrix_keyboard/src/matrix_keyboard.c +++ b/examples/peripherals/gpio/matrix_keyboard/components/matrix_keyboard/src/matrix_keyboard.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -7,24 +7,15 @@ #include "freertos/FreeRTOS.h" #include "freertos/task.h" #include "freertos/timers.h" -#include "esp_compiler.h" #include "esp_log.h" +#include "esp_check.h" #include "driver/dedic_gpio.h" #include "driver/gpio.h" +#include "esp_private/gpio.h" #include "matrix_keyboard.h" -#include "esp_rom_sys.h" static const char *TAG = "mkbd"; -#define MKBD_CHECK(a, msg, tag, ret, ...) \ - do { \ - if (unlikely(!(a))) { \ - ESP_LOGE(TAG, "%s(%d): " msg, __FUNCTION__, __LINE__, ##__VA_ARGS__); \ - ret_code = ret; \ - goto tag; \ - } \ - } while (0) - typedef struct matrix_kbd_t matrix_kbd_t; struct matrix_kbd_t { @@ -91,45 +82,36 @@ static void matrix_kbd_debounce_timer_callback(TimerHandle_t xTimer) esp_err_t matrix_kbd_install(const matrix_kbd_config_t *config, matrix_kbd_handle_t *mkbd_handle) { - esp_err_t ret_code = ESP_OK; + esp_err_t ret = ESP_OK; matrix_kbd_t *mkbd = NULL; - MKBD_CHECK(config, "matrix keyboard configuration can't be null", err, ESP_ERR_INVALID_ARG); - MKBD_CHECK(mkbd_handle, "matrix keyboard handle can't be null", err, ESP_ERR_INVALID_ARG); + ESP_RETURN_ON_FALSE(config && mkbd_handle, ESP_ERR_INVALID_ARG, TAG, "invalid argument"); mkbd = calloc(1, sizeof(matrix_kbd_t) + (config->nr_row_gpios) * sizeof(uint32_t)); - MKBD_CHECK(mkbd, "allocate matrix keyboard context failed", err, ESP_ERR_NO_MEM); + ESP_RETURN_ON_FALSE(mkbd, ESP_ERR_NO_MEM, TAG, "no mem for matrix keyboard context"); + + // Create a ont-shot os timer, used for key debounce + mkbd->debounce_timer = xTimerCreate("kb_debounce", pdMS_TO_TICKS(config->debounce_ms), pdFALSE, mkbd, matrix_kbd_debounce_timer_callback); + ESP_GOTO_ON_FALSE(mkbd->debounce_timer, ESP_FAIL, err, TAG, "create debounce timer failed"); mkbd->nr_col_gpios = config->nr_col_gpios; mkbd->nr_row_gpios = config->nr_row_gpios; - // GPIO pad configuration - // Each GPIO used in matrix key board should be able to input and output - // In case the keyboard doesn't design a resister to pull up row/col line - // We enable the internal pull up resister, enable Open Drain as well - gpio_config_t io_conf = { - .mode = GPIO_MODE_INPUT_OUTPUT_OD, - .pull_up_en = 1 - }; - - for (int i = 0; i < config->nr_row_gpios; i++) { - io_conf.pin_bit_mask = 1ULL << config->row_gpios[i]; - gpio_config(&io_conf); - } - dedic_gpio_bundle_config_t bundle_row_config = { .gpio_array = config->row_gpios, .array_size = config->nr_row_gpios, + // Each GPIO used in matrix key board should be able to input and output .flags = { .in_en = 1, .out_en = 1, }, }; - MKBD_CHECK(dedic_gpio_new_bundle(&bundle_row_config, &mkbd->row_bundle) == ESP_OK, - "create row bundle failed", err, ESP_FAIL); + ESP_GOTO_ON_ERROR(dedic_gpio_new_bundle(&bundle_row_config, &mkbd->row_bundle), err, TAG, "create row bundle failed"); - for (int i = 0; i < config->nr_col_gpios; i++) { - io_conf.pin_bit_mask = 1ULL << config->col_gpios[i]; - gpio_config(&io_conf); + // In case the keyboard doesn't design a resister to pull up row/col line + // We enable the internal pull up resister, enable Open Drain as well + for (int i = 0; i < config->nr_row_gpios; i++) { + gpio_pullup_en(config->row_gpios[i]); + gpio_od_enable(config->row_gpios[i]); } dedic_gpio_bundle_config_t bundle_col_config = { @@ -140,8 +122,12 @@ esp_err_t matrix_kbd_install(const matrix_kbd_config_t *config, matrix_kbd_handl .out_en = 1, }, }; - MKBD_CHECK(dedic_gpio_new_bundle(&bundle_col_config, &mkbd->col_bundle) == ESP_OK, - "create col bundle failed", err, ESP_FAIL); + ESP_GOTO_ON_ERROR(dedic_gpio_new_bundle(&bundle_col_config, &mkbd->col_bundle), err, TAG, "create col bundle failed"); + + for (int i = 0; i < config->nr_col_gpios; i++) { + gpio_pullup_en(config->col_gpios[i]); + gpio_od_enable(config->col_gpios[i]); + } // Disable interrupt dedic_gpio_bundle_set_interrupt_and_callback(mkbd->row_bundle, (1 << config->nr_row_gpios) - 1, @@ -149,45 +135,35 @@ esp_err_t matrix_kbd_install(const matrix_kbd_config_t *config, matrix_kbd_handl dedic_gpio_bundle_set_interrupt_and_callback(mkbd->col_bundle, (1 << config->nr_col_gpios) - 1, DEDIC_GPIO_INTR_NONE, NULL, NULL); - // Create a ont-shot os timer, used for key debounce - mkbd->debounce_timer = xTimerCreate("kb_debounce", pdMS_TO_TICKS(config->debounce_ms), pdFALSE, mkbd, matrix_kbd_debounce_timer_callback); - MKBD_CHECK(mkbd->debounce_timer, "create debounce timer failed", err, ESP_FAIL); - * mkbd_handle = mkbd; return ESP_OK; err: - if (mkbd) { - if (mkbd->debounce_timer) { - xTimerDelete(mkbd->debounce_timer, 0); - } - if (mkbd->col_bundle) { - dedic_gpio_del_bundle(mkbd->col_bundle); - } - if (mkbd->row_bundle) { - dedic_gpio_del_bundle(mkbd->row_bundle); - } - free(mkbd); + if (mkbd->debounce_timer) { + xTimerDelete(mkbd->debounce_timer, 0); } - return ret_code; + if (mkbd->col_bundle) { + dedic_gpio_del_bundle(mkbd->col_bundle); + } + if (mkbd->row_bundle) { + dedic_gpio_del_bundle(mkbd->row_bundle); + } + free(mkbd); + return ret; } esp_err_t matrix_kbd_uninstall(matrix_kbd_handle_t mkbd_handle) { - esp_err_t ret_code = ESP_OK; - MKBD_CHECK(mkbd_handle, "matrix keyboard handle can't be null", err, ESP_ERR_INVALID_ARG); + ESP_RETURN_ON_FALSE(mkbd_handle, ESP_ERR_INVALID_ARG, TAG, "invalid argument"); xTimerDelete(mkbd_handle->debounce_timer, 0); dedic_gpio_del_bundle(mkbd_handle->col_bundle); dedic_gpio_del_bundle(mkbd_handle->row_bundle); free(mkbd_handle); return ESP_OK; -err: - return ret_code; } esp_err_t matrix_kbd_start(matrix_kbd_handle_t mkbd_handle) { - esp_err_t ret_code = ESP_OK; - MKBD_CHECK(mkbd_handle, "matrix keyboard handle can't be null", err, ESP_ERR_INVALID_ARG); + ESP_RETURN_ON_FALSE(mkbd_handle, ESP_ERR_INVALID_ARG, TAG, "invalid argument"); // row lines set to high level dedic_gpio_bundle_write(mkbd_handle->row_bundle, (1 << mkbd_handle->nr_row_gpios) - 1, (1 << mkbd_handle->nr_row_gpios) - 1); @@ -203,15 +179,11 @@ esp_err_t matrix_kbd_start(matrix_kbd_handle_t mkbd_handle) DEDIC_GPIO_INTR_BOTH_EDGE, matrix_kbd_row_isr_callback, mkbd_handle); return ESP_OK; -err: - return ret_code; } esp_err_t matrix_kbd_stop(matrix_kbd_handle_t mkbd_handle) { - esp_err_t ret_code = ESP_OK; - MKBD_CHECK(mkbd_handle, "matrix keyboard handle can't be null", err, ESP_ERR_INVALID_ARG); - + ESP_RETURN_ON_FALSE(mkbd_handle, ESP_ERR_INVALID_ARG, TAG, "invalid argument"); xTimerStop(mkbd_handle->debounce_timer, 0); // Disable interrupt @@ -221,17 +193,12 @@ esp_err_t matrix_kbd_stop(matrix_kbd_handle_t mkbd_handle) DEDIC_GPIO_INTR_NONE, NULL, NULL); return ESP_OK; -err: - return ret_code; } esp_err_t matrix_kbd_register_event_handler(matrix_kbd_handle_t mkbd_handle, matrix_kbd_event_handler handler, void *args) { - esp_err_t ret_code = ESP_OK; - MKBD_CHECK(mkbd_handle, "matrix keyboard handle can't be null", err, ESP_ERR_INVALID_ARG); + ESP_RETURN_ON_FALSE(mkbd_handle, ESP_ERR_INVALID_ARG, TAG, "invalid argument"); mkbd_handle->event_handler = handler; mkbd_handle->event_handler_args = args; return ESP_OK; -err: - return ret_code; } diff --git a/examples/peripherals/gpio/matrix_keyboard/main/matrix_keyboard_example_main.c b/examples/peripherals/gpio/matrix_keyboard/main/matrix_keyboard_example_main.c index fd1008e90ba..657d24136a0 100644 --- a/examples/peripherals/gpio/matrix_keyboard/main/matrix_keyboard_example_main.c +++ b/examples/peripherals/gpio/matrix_keyboard/main/matrix_keyboard_example_main.c @@ -1,11 +1,9 @@ -/* Matrix Keyboard (based on dedicated GPIO) example - - This example code is in the Public Domain (or CC0 licensed, at your option.) +/* + * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ - Unless required by applicable law or agreed to in writing, this - software is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR - CONDITIONS OF ANY KIND, either express or implied. -*/ #include #include "esp_log.h" #include "matrix_keyboard.h" diff --git a/tools/ci/check_copyright_ignore.txt b/tools/ci/check_copyright_ignore.txt index 681279a268e..8fc70c2ab78 100644 --- a/tools/ci/check_copyright_ignore.txt +++ b/tools/ci/check_copyright_ignore.txt @@ -876,9 +876,6 @@ examples/mesh/manual_networking/main/mesh_main.c examples/network/simple_sniffer/main/cmd_sniffer.c examples/network/simple_sniffer/main/cmd_sniffer.h examples/network/simple_sniffer/main/simple_sniffer_example_main.c -examples/peripherals/gpio/generic_gpio/main/gpio_example_main.c -examples/peripherals/gpio/matrix_keyboard/components/matrix_keyboard/include/matrix_keyboard.h -examples/peripherals/gpio/matrix_keyboard/main/matrix_keyboard_example_main.c examples/peripherals/ledc/ledc_basic/main/ledc_basic_example_main.c examples/peripherals/ledc/ledc_fade/main/ledc_fade_example_main.c examples/peripherals/sdio/host/main/app_main.c From b1ac4773a57ee9c2b998f215f1f83c8fe390a30a Mon Sep 17 00:00:00 2001 From: Aditya Patwardhan Date: Thu, 3 Oct 2024 10:23:42 +0530 Subject: [PATCH 139/472] fix(security): Fixed README file for security_features_app --- .../security/security_features_app/README.md | 40 +++++++++++-------- 1 file changed, 23 insertions(+), 17 deletions(-) diff --git a/examples/security/security_features_app/README.md b/examples/security/security_features_app/README.md index 9272b81c227..ea48a61b256 100644 --- a/examples/security/security_features_app/README.md +++ b/examples/security/security_features_app/README.md @@ -1,25 +1,24 @@ | Supported Targets | ESP32-C3 | | ----------------- | -------- | +# Security Features Application -# All Secure - -This example demonstrates how to enable all of the available security features on the esp32c3 target at once. +This example demonstrates how to enable all of the available security features on the ESP32-C3 target at once. This example shall use combination of host based python tools and firmware for enabling all the related security eFuses. -For simplicity the security features such as Secure Boot V2, Flash Encryption, NVS Encryption shall be enabled through host based python tools (e.g., espefuse). +For simplicity, the security features such as Secure Boot V2, Flash Encryption, NVS Encryption shall be enabled through host based python tools (e.g., espefuse). Some additional security eFuses shall be enabled in the firmware. **The device that has followed all the steps mentioned below can be used for production use-cases.** > [!CAUTION] -> The instructions in the example directly burn eFuses and once done, it cannot be reverted. Please go through the below steps carefully before executing the example. All the steps must be followed without any changes and in the exact sequence, otherwise the device may end up in an unrecoverable state. +> The instructions in the example directly burn eFuses and once done, it cannot be reverted. Please go through the below steps carefully before executing the example. All the steps must be followed without any changes and in the exact sequence, otherwise the device may end up in an unrecoverable state. Follow the [QEMU workflow](#enable-security-features-with-help-of-qemu) if you want to test the example without the risk of bricking an actual device. ### Hardware Required -* A development board with ESP32C3 SoC +* A development board with ESP32-C3 SoC * A USB cable for power supply and programming -**Note: The hardware is not required if you plan to run the example with help of QEMU.** +**Note: The hardware is not required if you plan to run the example with help of [QEMU](#enable-security-features-with-help-of-qemu).** ## Pre-requisites @@ -32,7 +31,7 @@ export ESPPORT=/* Serial port to which esp is connected */

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