From 2b44d62e43bdaff8962d391432b3891be6dd686d Mon Sep 17 00:00:00 2001 From: laokaiyao Date: Tue, 5 Dec 2023 15:38:55 +0800 Subject: [PATCH] feat(esp32c5): support esp32c5 g0 components --- .../esp_rom/include/esp32c5/rom/cache.h | 4 +- .../esp_rom/include/esp32c5/rom/libc_stubs.h | 2 +- .../patches/esp_rom_hp_regi2c_esp32c5.c | 183 ++- components/hal/esp32c5/include/.gitkeep | 0 components/hal/esp32c5/include/hal/cache_ll.h | 328 ++++ components/hal/esp32c5/include/hal/efuse_ll.h | 173 ++ components/hal/esp32c5/include/hal/lpwdt_ll.h | 349 ++++ components/hal/esp32c5/include/hal/mmu_ll.h | 433 +++++ components/hal/esp32c5/include/hal/mwdt_ll.h | 341 ++++ components/hal/esp32c5/include/hal/rwdt_ll.h | 80 + components/hal/esp32c5/include/hal/uart_ll.h | 1413 +++++++++++++++++ components/riscv/include/riscv/rv_utils.h | 3 + components/soc/esp32c2/include/soc/soc_caps.h | 5 - components/soc/esp32c3/include/soc/soc_caps.h | 5 - .../esp32c5/include/soc/Kconfig.soc_caps.in | 48 + .../soc/esp32c5/include/soc/apb_saradc_reg.h | 50 +- components/soc/esp32c5/include/soc/clic_reg.h | 108 ++ .../soc/esp32c5/include/soc/clk_tree_defs.h | 485 ++++++ .../soc/esp32c5/include/soc/dport_access.h | 108 ++ .../soc/esp32c5/include/soc/efuse_struct.h | 3 +- .../soc/esp32c5/include/soc/gpio_pins.h | 20 + .../soc/esp32c5/include/soc/gpio_sig_map.h | 177 +++ .../include/soc/interrupt_matrix_reg.h | 2 +- .../soc/esp32c5/include/soc/interrupt_reg.h | 22 + .../soc/esp32c5/include/soc/interrupts.h | 106 ++ .../soc/esp32c5/include/soc/lp_timer_struct.h | 1 + .../soc/esp32c5/include/soc/pcr_struct.h | 4 +- .../soc/esp32c5/include/soc/periph_defs.h | 87 + components/soc/esp32c5/include/soc/reg_base.h | 5 +- .../soc/esp32c5/include/soc/reset_reasons.h | 55 + .../soc/esp32c5/include/soc/rtc_io_channel.h | 33 + components/soc/esp32c5/include/soc/soc.h | 242 +++ components/soc/esp32c5/include/soc/soc_caps.h | 562 +++++++ components/soc/esp32c5/include/soc/soc_pins.h | 16 + .../soc/esp32c5/include/soc/spi1_mem_reg.h | 82 +- .../soc/esp32c5/include/soc/spi_mem_reg.h | 146 +- components/soc/esp32c5/include/soc/spi_pins.h | 25 + components/soc/esp32c5/include/soc/spi_reg.h | 76 +- .../soc/esp32c6/include/soc/interrupts.h | 4 +- components/soc/esp32c6/include/soc/soc_caps.h | 5 - .../soc/esp32h2/include/soc/interrupts.h | 2 +- components/soc/esp32h2/include/soc/soc_caps.h | 5 - components/soc/esp32p4/include/soc/soc_caps.h | 5 - components/soc/include/soc/rtc_cntl_periph.h | 4 +- components/soc/linux/include/soc/soc_caps.h | 5 - tools/test_apps/.build-test-rules.yml | 2 +- .../test_apps/system/g0_components/README.md | 4 +- 47 files changed, 5507 insertions(+), 311 deletions(-) delete mode 100644 components/hal/esp32c5/include/.gitkeep create mode 100644 components/hal/esp32c5/include/hal/cache_ll.h create mode 100644 components/hal/esp32c5/include/hal/efuse_ll.h create mode 100644 components/hal/esp32c5/include/hal/lpwdt_ll.h create mode 100644 components/hal/esp32c5/include/hal/mmu_ll.h create mode 100644 components/hal/esp32c5/include/hal/mwdt_ll.h create mode 100644 components/hal/esp32c5/include/hal/rwdt_ll.h create mode 100644 components/hal/esp32c5/include/hal/uart_ll.h create mode 100644 components/soc/esp32c5/include/soc/Kconfig.soc_caps.in create mode 100644 components/soc/esp32c5/include/soc/clic_reg.h create mode 100644 components/soc/esp32c5/include/soc/clk_tree_defs.h create mode 100644 components/soc/esp32c5/include/soc/dport_access.h create mode 100644 components/soc/esp32c5/include/soc/gpio_pins.h create mode 100644 components/soc/esp32c5/include/soc/gpio_sig_map.h create mode 100644 components/soc/esp32c5/include/soc/interrupt_reg.h create mode 100644 components/soc/esp32c5/include/soc/interrupts.h create mode 100644 components/soc/esp32c5/include/soc/periph_defs.h create mode 100644 components/soc/esp32c5/include/soc/reset_reasons.h create mode 100644 components/soc/esp32c5/include/soc/rtc_io_channel.h create mode 100644 components/soc/esp32c5/include/soc/soc.h create mode 100644 components/soc/esp32c5/include/soc/soc_caps.h create mode 100644 components/soc/esp32c5/include/soc/soc_pins.h create mode 100644 components/soc/esp32c5/include/soc/spi_pins.h diff --git a/components/esp_rom/include/esp32c5/rom/cache.h b/components/esp_rom/include/esp32c5/rom/cache.h index dfa657e865ba..b2f09f321229 100644 --- a/components/esp_rom/include/esp32c5/rom/cache.h +++ b/components/esp_rom/include/esp32c5/rom/cache.h @@ -181,7 +181,7 @@ void ROM_Boot_Cache_Init(void); * @param uint32_t senitive : Config this page should apply flash encryption or not * * @param uint32_t ext_ram : DPORT_MMU_ACCESS_FLASH for flash, DPORT_MMU_INVALID for invalid. In - * esp32c6, external memory is always flash + * esp32c5, external memory is always flash * * @param uint32_t vaddr : virtual address in CPU address space. * Can be Iram0,Iram1,Irom0,Drom0 and AHB buses address. @@ -209,7 +209,7 @@ int Cache_MSPI_MMU_Set(uint32_t sensitive, uint32_t ext_ram, uint32_t vaddr, uin * Please do not call this function in your SDK application. * * @param uint32_t ext_ram : DPORT_MMU_ACCESS_FLASH for flash, DPORT_MMU_INVALID for invalid. In - * esp32c6, external memory is always flash + * esp32c5, external memory is always flash * * @param uint32_t vaddr : virtual address in CPU address space. * Can be DRam0, DRam1, DRom0, DPort and AHB buses address. diff --git a/components/esp_rom/include/esp32c5/rom/libc_stubs.h b/components/esp_rom/include/esp32c5/rom/libc_stubs.h index cf1ffbbbf382..e31dcc6e6792 100644 --- a/components/esp_rom/include/esp32c5/rom/libc_stubs.h +++ b/components/esp_rom/include/esp32c5/rom/libc_stubs.h @@ -20,7 +20,7 @@ extern "C" { #endif /* -ESP32-C6 ROM code contains implementations of some of C library functions. +ESP32-C5 ROM code contains implementations of some of C library functions. Whenever a function in ROM needs to use a syscall, it calls a pointer to the corresponding syscall implementation defined in the following struct. diff --git a/components/esp_rom/patches/esp_rom_hp_regi2c_esp32c5.c b/components/esp_rom/patches/esp_rom_hp_regi2c_esp32c5.c index f89538d21040..c9695022ecf7 100644 --- a/components/esp_rom/patches/esp_rom_hp_regi2c_esp32c5.c +++ b/components/esp_rom/patches/esp_rom_hp_regi2c_esp32c5.c @@ -5,8 +5,9 @@ */ #include "esp_rom_sys.h" #include "esp_attr.h" -#include "soc/i2c_ana_mst_reg.h" -#include "modem/modem_lpcon_reg.h" +// TODO: [ESP32C5] IDF-8824 (inherit from C6) +// #include "soc/i2c_ana_mst_reg.h" +// #include "modem/modem_lpcon_reg.h" /** * BB - 0x67 - BIT0 * TXRF - 0x6B - BIT1 @@ -82,107 +83,115 @@ uint8_t esp_rom_regi2c_read_mask(uint8_t block, uint8_t host_id, uint8_t reg_add void esp_rom_regi2c_write(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data) __attribute__((alias("regi2c_write_impl"))); void esp_rom_regi2c_write_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data) __attribute__((alias("regi2c_write_mask_impl"))); +__attribute__((unused)) static IRAM_ATTR uint8_t regi2c_enable_block(uint8_t block) { - uint32_t i2c_sel = 0; - - REG_SET_BIT(MODEM_LPCON_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_EN); - REG_SET_BIT(MODEM_LPCON_I2C_MST_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_SEL_160M); - - /* Before config I2C register, enable corresponding slave. */ - switch (block) { - case REGI2C_BBPLL : - i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_BBPLL_MST_SEL); - REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, REGI2C_BBPLL_RD_MASK); - break; - case REGI2C_BIAS : - i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_BIAS_MST_SEL); - REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, REGI2C_BIAS_RD_MASK); - break; - case REGI2C_DIG_REG: - i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_DIG_REG_MST_SEL); - REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, REGI2C_DIG_REG_RD_MASK); - break; - case REGI2C_ULP_CAL: - i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_ULP_CAL_MST_SEL); - REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, REGI2C_ULP_CAL_RD_MASK); - break; - case REGI2C_SAR_I2C: - i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_SAR_I2C_MST_SEL); - REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, REGI2C_SAR_I2C_RD_MASK); - break; - } - - return (uint8_t)(i2c_sel ? 0: 1); + // TODO: [ESP32C5] IDF-8824 (inherit from C6) + // uint32_t i2c_sel = 0; + + // REG_SET_BIT(MODEM_LPCON_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_EN); + // REG_SET_BIT(MODEM_LPCON_I2C_MST_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_SEL_160M); + + // /* Before config I2C register, enable corresponding slave. */ + // switch (block) { + // case REGI2C_BBPLL : + // i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_BBPLL_MST_SEL); + // REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, REGI2C_BBPLL_RD_MASK); + // break; + // case REGI2C_BIAS : + // i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_BIAS_MST_SEL); + // REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, REGI2C_BIAS_RD_MASK); + // break; + // case REGI2C_DIG_REG: + // i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_DIG_REG_MST_SEL); + // REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, REGI2C_DIG_REG_RD_MASK); + // break; + // case REGI2C_ULP_CAL: + // i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_ULP_CAL_MST_SEL); + // REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, REGI2C_ULP_CAL_RD_MASK); + // break; + // case REGI2C_SAR_I2C: + // i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_SAR_I2C_MST_SEL); + // REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, REGI2C_SAR_I2C_RD_MASK); + // break; + // } + + // return (uint8_t)(i2c_sel ? 0: 1); + return (uint8_t)0; } uint8_t IRAM_ATTR regi2c_read_impl(uint8_t block, uint8_t host_id, uint8_t reg_add) { - (void)host_id; - uint8_t i2c_sel = regi2c_enable_block(block); - - while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); // wait i2c idle - uint32_t temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S) - | (reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S; - REG_WRITE(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), temp); - while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); - uint8_t ret = REG_GET_FIELD(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_DATA); - - return ret; + // TODO: [ESP32C5] IDF-8824 (inherit from C6) + // (void)host_id; + // uint8_t i2c_sel = regi2c_enable_block(block); + + // while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); // wait i2c idle + // uint32_t temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S) + // | (reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S; + // REG_WRITE(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), temp); + // while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); + // uint8_t ret = REG_GET_FIELD(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_DATA); + + // return ret; + return (uint8_t)0; } uint8_t IRAM_ATTR regi2c_read_mask_impl(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb) { - assert(msb - lsb < 8); - uint8_t i2c_sel = regi2c_enable_block(block); - - (void)host_id; - while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); // wait i2c idle - uint32_t temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S) - | (reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S; - REG_WRITE(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), temp); - while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); - uint32_t data = REG_GET_FIELD(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_DATA); - uint8_t ret = (uint8_t)((data >> lsb) & (~(0xFFFFFFFF << (msb - lsb + 1)))); - - return ret; + // TODO: [ESP32C5] IDF-8824 (inherit from C6) + // assert(msb - lsb < 8); + // uint8_t i2c_sel = regi2c_enable_block(block); + + // (void)host_id; + // while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); // wait i2c idle + // uint32_t temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S) + // | (reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S; + // REG_WRITE(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), temp); + // while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); + // uint32_t data = REG_GET_FIELD(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_DATA); + // uint8_t ret = (uint8_t)((data >> lsb) & (~(0xFFFFFFFF << (msb - lsb + 1)))); + + // return ret; + return (uint8_t)0; } void IRAM_ATTR regi2c_write_impl(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data) { - (void)host_id; - uint8_t i2c_sel = regi2c_enable_block(block); - - while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); // wait i2c idle - uint32_t temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S) - | ((reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S) - | ((0x1 & REGI2C_RTC_WR_CNTL_V) << REGI2C_RTC_WR_CNTL_S) // 0: READ I2C register; 1: Write I2C register; - | (((uint32_t)data & REGI2C_RTC_DATA_V) << REGI2C_RTC_DATA_S); - REG_WRITE(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), temp); - while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); - + // TODO: [ESP32C5] IDF-8824 (inherit from C6) + // (void)host_id; + // uint8_t i2c_sel = regi2c_enable_block(block); + + // while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); // wait i2c idle + // uint32_t temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S) + // | ((reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S) + // | ((0x1 & REGI2C_RTC_WR_CNTL_V) << REGI2C_RTC_WR_CNTL_S) // 0: READ I2C register; 1: Write I2C register; + // | (((uint32_t)data & REGI2C_RTC_DATA_V) << REGI2C_RTC_DATA_S); + // REG_WRITE(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), temp); + // while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); } void IRAM_ATTR regi2c_write_mask_impl(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data) { - (void)host_id; - assert(msb - lsb < 8); - uint8_t i2c_sel = regi2c_enable_block(block); - - while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); - /*Read the i2c bus register*/ - uint32_t temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S) - | (reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S; - REG_WRITE(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), temp); - while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); - temp = REG_GET_FIELD(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_DATA); - /*Write the i2c bus register*/ - temp &= ((~(0xFFFFFFFF << lsb)) | (0xFFFFFFFF << (msb + 1))); - temp = (((uint32_t)data & (~(0xFFFFFFFF << (msb - lsb + 1)))) << lsb) | temp; - temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S) - | ((reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S) - | ((0x1 & REGI2C_RTC_WR_CNTL_V) << REGI2C_RTC_WR_CNTL_S) - | ((temp & REGI2C_RTC_DATA_V) << REGI2C_RTC_DATA_S); - REG_WRITE(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), temp); - while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); + // TODO: [ESP32C5] IDF-8824 (inherit from C6) + // (void)host_id; + // assert(msb - lsb < 8); + // uint8_t i2c_sel = regi2c_enable_block(block); + + // while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); + // /*Read the i2c bus register*/ + // uint32_t temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S) + // | (reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S; + // REG_WRITE(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), temp); + // while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); + // temp = REG_GET_FIELD(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_DATA); + // /*Write the i2c bus register*/ + // temp &= ((~(0xFFFFFFFF << lsb)) | (0xFFFFFFFF << (msb + 1))); + // temp = (((uint32_t)data & (~(0xFFFFFFFF << (msb - lsb + 1)))) << lsb) | temp; + // temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S) + // | ((reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S) + // | ((0x1 & REGI2C_RTC_WR_CNTL_V) << REGI2C_RTC_WR_CNTL_S) + // | ((temp & REGI2C_RTC_DATA_V) << REGI2C_RTC_DATA_S); + // REG_WRITE(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), temp); + // while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); } diff --git a/components/hal/esp32c5/include/.gitkeep b/components/hal/esp32c5/include/.gitkeep deleted file mode 100644 index e69de29bb2d1..000000000000 diff --git a/components/hal/esp32c5/include/hal/cache_ll.h b/components/hal/esp32c5/include/hal/cache_ll.h new file mode 100644 index 000000000000..2f460651aded --- /dev/null +++ b/components/hal/esp32c5/include/hal/cache_ll.h @@ -0,0 +1,328 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +// The LL layer for Cache register operations + +#pragma once + +#include +// TODO: [ESP32C5] IDF-8646 (inherit from C6) +// #include "soc/extmem_reg.h" +// #include "soc/ext_mem_defs.h" +#include "hal/cache_types.h" +#include "hal/assert.h" + +#ifdef __cplusplus +extern "C" { +#endif +#define CACHE_LL_ENABLE_DISABLE_STATE_SW 1 //There's no register indicating cache enable/disable state, we need to use software way for this state. + +#define CACHE_LL_DEFAULT_IBUS_MASK CACHE_BUS_IBUS0 +#define CACHE_LL_DEFAULT_DBUS_MASK CACHE_BUS_DBUS0 + +#define CACHE_LL_L1_ACCESS_EVENT_MASK (1<<4) +#define CACHE_LL_L1_ACCESS_EVENT_CACHE_FAIL (1<<4) + +#define CACHE_LL_ID_ALL 1 //All of the caches in a type and level, make this value greater than any ID +#define CACHE_LL_LEVEL_INT_MEM 0 //Cache level for accessing internal mem +#define CACHE_LL_LEVEL_EXT_MEM 1 //Cache level for accessing external mem +#define CACHE_LL_LEVEL_ALL 2 //All of the cache levels, make this value greater than any level +#define CACHE_LL_LEVEL_NUMS 1 //Number of cache levels +#define CACHE_LL_L1_ICACHE_AUTOLOAD (1<<0) + +/** + * @brief Check if Cache auto preload is enabled or not. + * + * @param cache_level level of the cache + * @param type see `cache_type_t` + * @param cache_id id of the cache in this type and level + * + * @return true: enabled; false: disabled + */ +__attribute__((always_inline)) +static inline bool cache_ll_is_cache_autoload_enabled(uint32_t cache_level, cache_type_t type, uint32_t cache_id) +{ + // TODO: [ESP32C5] IDF-8646 (inherit from C6) + // HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL); + // bool enabled = false; + // if (REG_GET_BIT(EXTMEM_L1_CACHE_AUTOLOAD_CTRL_REG, EXTMEM_L1_CACHE_AUTOLOAD_ENA)) { + // enabled = true; + // } + // return enabled; + return (bool)0; +} + +/** + * @brief Disable Cache + * + * @param cache_level level of the cache + * @param type see `cache_type_t` + * @param cache_id id of the cache in this type and level + */ +__attribute__((always_inline)) +static inline void cache_ll_disable_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id) +{ + // TODO: [ESP32C5] IDF-8646 (inherit from C6) + // (void) type; + // Cache_Disable_ICache(); +} + +/** + * @brief Enable Cache + * + * @param cache_level level of the cache + * @param type see `cache_type_t` + * @param cache_id id of the cache in this type and level + * @param data_autoload_en data autoload enabled or not + * @param inst_autoload_en inst autoload enabled or not + */ +__attribute__((always_inline)) +static inline void cache_ll_enable_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id, bool inst_autoload_en, bool data_autoload_en) +{ + // TODO: [ESP32C5] IDF-8646 (inherit from C6) + // Cache_Enable_ICache(inst_autoload_en ? CACHE_LL_L1_ICACHE_AUTOLOAD : 0); +} + +/** + * @brief Suspend Cache + * + * @param cache_level level of the cache + * @param type see `cache_type_t` + * @param cache_id id of the cache in this type and level + */ +__attribute__((always_inline)) +static inline void cache_ll_suspend_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id) +{ + // TODO: [ESP32C5] IDF-8646 (inherit from C6) + // Cache_Suspend_ICache(); +} + +/** + * @brief Resume Cache + * + * @param cache_level level of the cache + * @param type see `cache_type_t` + * @param cache_id id of the cache in this type and level + * @param data_autoload_en data autoload enabled or not + * @param inst_autoload_en inst autoload enabled or not + */ +__attribute__((always_inline)) +static inline void cache_ll_resume_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id, bool inst_autoload_en, bool data_autoload_en) +{ + // TODO: [ESP32C5] IDF-8646 (inherit from C6) + // Cache_Resume_ICache(inst_autoload_en ? CACHE_LL_L1_ICACHE_AUTOLOAD : 0); +} + +/** + * @brief Invalidate cache supported addr + * + * Invalidate a cache item + * + * @param cache_level level of the cache + * @param type see `cache_type_t` + * @param cache_id id of the cache in this type and level + * @param vaddr start address of the region to be invalidated + * @param size size of the region to be invalidated + */ +__attribute__((always_inline)) +static inline void cache_ll_invalidate_addr(uint32_t cache_level, cache_type_t type, uint32_t cache_id, uint32_t vaddr, uint32_t size) +{ + // TODO: [ESP32C5] IDF-8646 (inherit from C6) + // Cache_Invalidate_Addr(vaddr, size); +} + +/** + * @brief Freeze Cache + * + * @param cache_level level of the cache + * @param type see `cache_type_t` + * @param cache_id id of the cache in this type and level + */ +__attribute__((always_inline)) +static inline void cache_ll_freeze_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id) +{ + // TODO: [ESP32C5] IDF-8646 (inherit from C6) + // Cache_Freeze_ICache_Enable(CACHE_FREEZE_ACK_BUSY); +} + +/** + * @brief Unfreeze Cache + * + * @param cache_level level of the cache + * @param type see `cache_type_t` + * @param cache_id id of the cache in this type and level + */ +__attribute__((always_inline)) +static inline void cache_ll_unfreeze_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id) +{ + // TODO: [ESP32C5] IDF-8646 (inherit from C6) + // Cache_Freeze_ICache_Disable(); +} + +/** + * @brief Get Cache line size, in bytes + * + * @param cache_level level of the cache + * @param type see `cache_type_t` + * @param cache_id id of the cache in this type and level + * + * @return Cache line size, in bytes + */ +__attribute__((always_inline)) +static inline uint32_t cache_ll_get_line_size(uint32_t cache_level, cache_type_t type, uint32_t cache_id) +{ + // TODO: [ESP32C5] IDF-8646 (inherit from C6) + // uint32_t size = 0; + // size = Cache_Get_ICache_Line_Size(); + // return size; + return (uint32_t)0; +} + +/** + * @brief Get the buses of a particular cache that are mapped to a virtual address range + * + * External virtual address can only be accessed when the involved cache buses are enabled. + * This API is to get the cache buses where the memory region (from `vaddr_start` to `vaddr_start + len`) reside. + * + * @param cache_id cache ID (when l1 cache is per core) + * @param vaddr_start virtual address start + * @param len vaddr length + */ +#if !BOOTLOADER_BUILD +__attribute__((always_inline)) +#endif +static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t vaddr_start, uint32_t len) +{ + // TODO: [ESP32C5] IDF-8646 (inherit from C6) + // HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL); + // cache_bus_mask_t mask = (cache_bus_mask_t)0; + // // uint32_t vaddr_end = vaddr_start + len - 1; + // if (vaddr_start >= SOC_IRAM0_CACHE_ADDRESS_LOW && vaddr_end < SOC_IRAM0_CACHE_ADDRESS_HIGH) { + // //c5 the I/D bus memory are shared, so we always return `CACHE_BUS_IBUS0 | CACHE_BUS_DBUS0` + // mask = (cache_bus_mask_t)(mask | (CACHE_BUS_IBUS0 | CACHE_BUS_DBUS0)); + // } else { + // HAL_ASSERT(0); //Out of region + // } + // // return mask; + return (cache_bus_mask_t)0; +} + +/** + * Enable the Cache Buses + * + * @param cache_id cache ID (when l1 cache is per core) + * @param mask To know which buses should be enabled + */ +#if !BOOTLOADER_BUILD +__attribute__((always_inline)) +#endif +static inline void cache_ll_l1_enable_bus(uint32_t cache_id, cache_bus_mask_t mask) +{ + // TODO: [ESP32C5] IDF-8646 (inherit from C6) + // HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL); + // //On esp32c5, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first + // HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); + // // uint32_t ibus_mask = 0; + // ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS0) ? EXTMEM_L1_CACHE_SHUT_IBUS : 0); + // REG_CLR_BIT(EXTMEM_L1_CACHE_CTRL_REG, ibus_mask); + // // uint32_t dbus_mask = 0; + // dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS0) ? EXTMEM_L1_CACHE_SHUT_DBUS : 0); + // REG_CLR_BIT(EXTMEM_L1_CACHE_CTRL_REG, dbus_mask); +} + +/** + * Disable the Cache Buses + * + * @param cache_id cache ID (when l1 cache is per core) + * @param mask To know which buses should be disabled + */ +__attribute__((always_inline)) +static inline void cache_ll_l1_disable_bus(uint32_t cache_id, cache_bus_mask_t mask) +{ + // TODO: [ESP32C5] IDF-8646 (inherit from C6) + // HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL); + // //On esp32c5, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first + // HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); + // // uint32_t ibus_mask = 0; + // ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS0) ? EXTMEM_L1_CACHE_SHUT_IBUS : 0); + // REG_SET_BIT(EXTMEM_L1_CACHE_CTRL_REG, ibus_mask); + // // uint32_t dbus_mask = 0; + // dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS0) ? EXTMEM_L1_CACHE_SHUT_DBUS : 0); + // REG_SET_BIT(EXTMEM_L1_CACHE_CTRL_REG, dbus_mask); +} + +/** + * @brief Get Cache level and the ID of the vaddr + * + * @param vaddr_start virtual address start + * @param len vaddr length + * @param out_level cache level + * @param out_id cache id + * + * @return true for valid + */ +__attribute__((always_inline)) +static inline bool cache_ll_vaddr_to_cache_level_id(uint32_t vaddr_start, uint32_t len, uint32_t *out_level, uint32_t *out_id) +{ + // TODO: [ESP32C5] IDF-8646 (inherit from C6) + // bool valid = false; + // uint32_t vaddr_end = vaddr_start + len - 1; + // // valid |= (SOC_ADDRESS_IN_IRAM0_CACHE(vaddr_start) && SOC_ADDRESS_IN_IRAM0_CACHE(vaddr_end)); + // valid |= (SOC_ADDRESS_IN_DRAM0_CACHE(vaddr_start) && SOC_ADDRESS_IN_DRAM0_CACHE(vaddr_end)); + // // if (valid) { + // *out_level = 1; + // *out_id = 0; + // } + // // return valid; + return (bool)0; +} + +/*------------------------------------------------------------------------------ + * Interrupt + *----------------------------------------------------------------------------*/ +/** + * @brief Enable Cache access error interrupt + * + * @param cache_id Cache ID, not used on C3. For compabitlity + * @param mask Interrupt mask + */ +static inline void cache_ll_l1_enable_access_error_intr(uint32_t cache_id, uint32_t mask) +{ + // TODO: [ESP32C5] IDF-8646 (inherit from C6) + // SET_PERI_REG_MASK(EXTMEM_L1_CACHE_ACS_FAIL_INT_ENA_REG, mask); +} + +/** + * @brief Clear Cache access error interrupt status + * + * @param cache_id Cache ID, not used on C3. For compabitlity + * @param mask Interrupt mask + */ +static inline void cache_ll_l1_clear_access_error_intr(uint32_t cache_id, uint32_t mask) +{ + // TODO: [ESP32C5] IDF-8646 (inherit from C6) + // SET_PERI_REG_MASK(EXTMEM_L1_CACHE_ACS_FAIL_INT_CLR_REG, mask); +} + +/** + * @brief Get Cache access error interrupt status + * + * @param cache_id Cache ID, not used on C3. For compabitlity + * @param mask Interrupt mask + * + * @return Status mask + */ +static inline uint32_t cache_ll_l1_get_access_error_intr_status(uint32_t cache_id, uint32_t mask) +{ + // TODO: [ESP32C5] IDF-8646 (inherit from C6) + // return GET_PERI_REG_MASK(EXTMEM_L1_CACHE_ACS_FAIL_INT_ST_REG, mask); + return (uint32_t)0; +} + +#ifdef __cplusplus + return (uint32_t)0; +} +#endif diff --git a/components/hal/esp32c5/include/hal/efuse_ll.h b/components/hal/esp32c5/include/hal/efuse_ll.h new file mode 100644 index 000000000000..cbf184410025 --- /dev/null +++ b/components/hal/esp32c5/include/hal/efuse_ll.h @@ -0,0 +1,173 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include +#include "soc/efuse_periph.h" +#include "hal/assert.h" +#include "esp32p4/rom/efuse.h" + +#ifdef __cplusplus +extern "C" { +#endif + +// Always inline these functions even no gcc optimization is applied. + +/******************* eFuse fields *************************/ + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_flash_crypt_cnt(void) +{ + // TODO: [ESP32C5] IDF-8674 (inherit from C6) + // return EFUSE.rd_repeat_data1.spi_boot_crypt_cnt; + return (uint32_t)0; +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_wdt_delay_sel(void) +{ + // TODO: [ESP32C5] IDF-8674 (inherit from C6) + // return EFUSE.rd_repeat_data1.wdt_delay_sel; + return (uint32_t)0; +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_mac0(void) +{ + // TODO: [ESP32C5] IDF-8674 (inherit from C6) + // return EFUSE.rd_mac_sys_0.mac_0; + return (uint32_t)0; +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_mac1(void) +{ + // TODO: [ESP32C5] IDF-8674 (inherit from C6) + // return EFUSE.rd_mac_sys_1.mac_1; + return (uint32_t)0; +} + +__attribute__((always_inline)) static inline bool efuse_ll_get_secure_boot_v2_en(void) +{ + // TODO: [ESP32C5] IDF-8674 (inherit from C6) + // return EFUSE.rd_repeat_data2.secure_boot_en; + return (bool)0; +} + +// use efuse_hal_get_major_chip_version() to get major chip version +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_wafer_version_major(void) +{ + // TODO: [ESP32C5] IDF-8674 (inherit from C6) + // // return EFUSE.rd_mac_sys_5; + // return 0; + return (uint32_t)0; +} + +// use efuse_hal_get_minor_chip_version() to get minor chip version +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_wafer_version_minor(void) +{ + // TODO: [ESP32C5] IDF-8674 (inherit from C6) + // return 0; + return (uint32_t)0; +} + +__attribute__((always_inline)) static inline bool efuse_ll_get_disable_wafer_version_major(void) +{ + // TODO: [ESP32C5] IDF-8674 (inherit from C6) + // return 0; + return (bool)0; +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_blk_version_major(void) +{ + // TODO: [ESP32C5] IDF-8674 (inherit from C6) + // return 0; + return (uint32_t)0; +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_blk_version_minor(void) +{ + // TODO: [ESP32C5] IDF-8674 (inherit from C6) + // return 0; + return (uint32_t)0; +} + +__attribute__((always_inline)) static inline bool efuse_ll_get_disable_blk_version_major(void) +{ + // TODO: [ESP32C5] IDF-8674 (inherit from C6) + // return 0; + return (bool)0; +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_ver_pkg(void) +{ + // TODO: [ESP32C5] IDF-8674 (inherit from C6) + // return 0; + return (uint32_t)0; +} + +__attribute__((always_inline)) static inline void efuse_ll_set_ecdsa_key_blk(int efuse_blk) +{ + // TODO: [ESP32C5] IDF-8674 (inherit from C6) + // EFUSE.conf.cfg_ecdsa_blk = efuse_blk; +} + +/******************* eFuse control functions *************************/ + +__attribute__((always_inline)) static inline bool efuse_ll_get_read_cmd(void) +{ + // TODO: [ESP32C5] IDF-8674 (inherit from C6) + // return EFUSE.cmd.read_cmd; + return (bool)0; +} + +__attribute__((always_inline)) static inline bool efuse_ll_get_pgm_cmd(void) +{ + // TODO: [ESP32C5] IDF-8674 (inherit from C6) + // return EFUSE.cmd.pgm_cmd; + return (bool)0; +} + +__attribute__((always_inline)) static inline void efuse_ll_set_read_cmd(void) +{ + // TODO: [ESP32C5] IDF-8674 (inherit from C6) + // EFUSE.cmd.read_cmd = 1; +} + +__attribute__((always_inline)) static inline void efuse_ll_set_pgm_cmd(uint32_t block) +{ + // TODO: [ESP32C5] IDF-8674 (inherit from C6) + // HAL_ASSERT(block < ETS_EFUSE_BLOCK_MAX); + // EFUSE.cmd.val = ((block << EFUSE_BLK_NUM_S) & EFUSE_BLK_NUM_M) | EFUSE_PGM_CMD; +} + +__attribute__((always_inline)) static inline void efuse_ll_set_conf_read_op_code(void) +{ + // TODO: [ESP32C5] IDF-8674 (inherit from C6) + // EFUSE.conf.op_code = EFUSE_READ_OP_CODE; +} + +__attribute__((always_inline)) static inline void efuse_ll_set_conf_write_op_code(void) +{ + // TODO: [ESP32C5] IDF-8674 (inherit from C6) + // EFUSE.conf.op_code = EFUSE_WRITE_OP_CODE; +} + +__attribute__((always_inline)) static inline void efuse_ll_set_pwr_off_num(uint16_t value) +{ + // TODO: [ESP32C5] IDF-8674 (inherit from C6) + // EFUSE.wr_tim_conf2.pwr_off_num = value; +} + +__attribute__((always_inline)) static inline void efuse_ll_rs_bypass_update(void) +{ + // TODO: [ESP32C5] IDF-8674 (inherit from C6) + // EFUSE.wr_tim_conf0_rs_bypass.update = 1; +} + +/******************* eFuse control functions *************************/ + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32c5/include/hal/lpwdt_ll.h b/components/hal/esp32c5/include/hal/lpwdt_ll.h new file mode 100644 index 000000000000..7bd643be2d99 --- /dev/null +++ b/components/hal/esp32c5/include/hal/lpwdt_ll.h @@ -0,0 +1,349 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +// The LL layer for Timer Group register operations. +// Note that most of the register operations in this layer are non-atomic operations. + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include "hal/misc.h" +#include "hal/wdt_types.h" +#include "soc/rtc_cntl_periph.h" +#include "soc/efuse_reg.h" +#include "esp_attr.h" +#include "esp_assert.h" + +#include "esp32c5/rom/ets_sys.h" + +/* The value that needs to be written to LP_WDT_WPROTECT_REG to write-enable the wdt registers */ +#define LP_WDT_WKEY_VALUE 0x50D83AA1 +/* The value that needs to be written to LP_WDT_SWD_WPROTECT_REG to write-enable the swd registers */ +#define LP_WDT_SWD_WKEY_VALUE 0x50D83AA1 + +/* Possible values for RTC_CNTL_WDT_CPU_RESET_LENGTH and RTC_CNTL_WDT_SYS_RESET_LENGTH */ +#define LP_WDT_RESET_LENGTH_100_NS 0 +#define LP_WDT_RESET_LENGTH_200_NS 1 +#define LP_WDT_RESET_LENGTH_300_NS 2 +#define LP_WDT_RESET_LENGTH_400_NS 3 +#define LP_WDT_RESET_LENGTH_500_NS 4 +#define LP_WDT_RESET_LENGTH_800_NS 5 +#define LP_WDT_RESET_LENGTH_1600_NS 6 +#define LP_WDT_RESET_LENGTH_3200_NS 7 + +#define LP_WDT_STG_SEL_OFF 0 +#define LP_WDT_STG_SEL_INT 1 +#define LP_WDT_STG_SEL_RESET_CPU 2 +#define LP_WDT_STG_SEL_RESET_SYSTEM 3 +#define LP_WDT_STG_SEL_RESET_RTC 4 + +//Type check wdt_stage_action_t +ESP_STATIC_ASSERT(WDT_STAGE_ACTION_OFF == LP_WDT_STG_SEL_OFF, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t"); +ESP_STATIC_ASSERT(WDT_STAGE_ACTION_INT == LP_WDT_STG_SEL_INT, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t"); +ESP_STATIC_ASSERT(WDT_STAGE_ACTION_RESET_CPU == LP_WDT_STG_SEL_RESET_CPU, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t"); +ESP_STATIC_ASSERT(WDT_STAGE_ACTION_RESET_SYSTEM == LP_WDT_STG_SEL_RESET_SYSTEM, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t"); +ESP_STATIC_ASSERT(WDT_STAGE_ACTION_RESET_RTC == LP_WDT_STG_SEL_RESET_RTC, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t"); +//Type check wdt_reset_sig_length_t +ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_100ns == LP_WDT_RESET_LENGTH_100_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t"); +ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_200ns == LP_WDT_RESET_LENGTH_200_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t"); +ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_300ns == LP_WDT_RESET_LENGTH_300_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t"); +ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_400ns == LP_WDT_RESET_LENGTH_400_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t"); +ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_500ns == LP_WDT_RESET_LENGTH_500_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t"); +ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_800ns == LP_WDT_RESET_LENGTH_800_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t"); +ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_1_6us == LP_WDT_RESET_LENGTH_1600_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t"); +ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_3_2us == LP_WDT_RESET_LENGTH_3200_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t"); + +/** + * @brief Enable the RWDT + * + * @param hw Start address of the peripheral registers. + */ +FORCE_INLINE_ATTR void lpwdt_ll_enable(lp_wdt_dev_t *hw) +{ + // TODO: [ESP32C5] IDF-8635 (inherit from C6) + // hw->config0.wdt_en = 1; +} + +/** + * @brief Disable the RWDT + * + * @param hw Start address of the peripheral registers. + * @note This function does not disable the flashboot mode. Therefore, given that + * the MWDT is disabled using this function, a timeout can still occur + * if the flashboot mode is simultaneously enabled. + */ +FORCE_INLINE_ATTR void lpwdt_ll_disable(lp_wdt_dev_t *hw) +{ + // TODO: [ESP32C5] IDF-8635 (inherit from C6) + // hw->config0.wdt_en = 0; +} + +/** + * @brief Check if the RWDT is enabled + * + * @param hw Start address of the peripheral registers. + * @return True if RTC WDT is enabled + */ +FORCE_INLINE_ATTR bool lpwdt_ll_check_if_enabled(lp_wdt_dev_t *hw) +{ + // TODO: [ESP32C5] IDF-8635 (inherit from C6) + // return (hw->config0.wdt_en) ? true : false; + return (bool)0; +} + +/** + * @brief Configure a particular stage of the RWDT + * + * @param hw Start address of the peripheral registers. + * @param stage Which stage to configure + * @param timeout Number of timer ticks for the stage to timeout (see note). + * @param behavior What action to take when the stage times out + * + * @note The value of of RWDT stage 0 timeout register is special, in + * that an implicit multiplier is applied to that value to produce + * and effective timeout tick value. The multiplier is dependent + * on an EFuse value. Therefore, when configuring stage 0, the valid + * values for the timeout argument are: + * - If Efuse value is 0, any even number between [2,2*UINT32_MAX] + * - If Efuse value is 1, any multiple of 4 between [4,4*UINT32_MAX] + * - If Efuse value is 2, any multiple of 8 between [8,8*UINT32_MAX] + * - If Efuse value is 3, any multiple of 16 between [16,16*UINT32_MAX] + */ +FORCE_INLINE_ATTR void lpwdt_ll_config_stage(lp_wdt_dev_t *hw, wdt_stage_t stage, uint32_t timeout_ticks, wdt_stage_action_t behavior) +{ + // TODO: [ESP32C5] IDF-8635 (inherit from C6) + // switch (stage) { + // case WDT_STAGE0: + // hw->config0.wdt_stg0 = behavior; + // //Account of implicty multiplier applied to stage 0 timeout tick config value + // hw->config1.val = timeout_ticks >> (1 + REG_GET_FIELD(EFUSE_RD_REPEAT_DATA1_REG, EFUSE_WDT_DELAY_SEL)); + // break; + // case WDT_STAGE1: + // hw->config0.wdt_stg1 = behavior; + // hw->config2.val = timeout_ticks; + // break; + // case WDT_STAGE2: + // hw->config0.wdt_stg2 = behavior; + // hw->config3.val = timeout_ticks; + // break; + // case WDT_STAGE3: + // hw->config0.wdt_stg3 = behavior; + // hw->config4.val = timeout_ticks; + // break; + // default: + // abort(); + // } +} + +/** + * @brief Disable a particular stage of the RWDT + * + * @param hw Start address of the peripheral registers. + * @param stage Which stage to disable + */ +FORCE_INLINE_ATTR void lpwdt_ll_disable_stage(lp_wdt_dev_t *hw, wdt_stage_t stage) +{ + // TODO: [ESP32C5] IDF-8635 (inherit from C6) + // switch (stage) { + // case WDT_STAGE0: + // hw->config0.wdt_stg0 = WDT_STAGE_ACTION_OFF; + // break; + // case WDT_STAGE1: + // hw->config0.wdt_stg1 = WDT_STAGE_ACTION_OFF; + // break; + // case WDT_STAGE2: + // hw->config0.wdt_stg2 = WDT_STAGE_ACTION_OFF; + // break; + // case WDT_STAGE3: + // hw->config0.wdt_stg3 = WDT_STAGE_ACTION_OFF; + // break; + // default: + // abort(); + // } +} + +/** + * @brief Set the length of the CPU reset action + * + * @param hw Start address of the peripheral registers. + * @param length Length of CPU reset signal + */ +FORCE_INLINE_ATTR void lpwdt_ll_set_cpu_reset_length(lp_wdt_dev_t *hw, wdt_reset_sig_length_t length) +{ + // TODO: [ESP32C5] IDF-8635 (inherit from C6) + // hw->config0.wdt_cpu_reset_length = length; +} + +/** + * @brief Set the length of the system reset action + * + * @param hw Start address of the peripheral registers. + * @param length Length of system reset signal + */ +FORCE_INLINE_ATTR void lpwdt_ll_set_sys_reset_length(lp_wdt_dev_t *hw, wdt_reset_sig_length_t length) +{ + // TODO: [ESP32C5] IDF-8635 (inherit from C6) + // hw->config0.wdt_sys_reset_length = length; +} + +/** + * @brief Enable/Disable the RWDT flashboot mode. + * + * @param hw Start address of the peripheral registers. + * @param enable True to enable RWDT flashboot mode, false to disable RWDT flashboot mode. + * + * @note Flashboot mode is independent and can trigger a WDT timeout event if the + * WDT's enable bit is set to 0. Flashboot mode for RWDT is automatically enabled + * on flashboot, and should be disabled by software when flashbooting completes. + */ +FORCE_INLINE_ATTR void lpwdt_ll_set_flashboot_en(lp_wdt_dev_t *hw, bool enable) +{ + // TODO: [ESP32C5] IDF-8635 (inherit from C6) + // hw->config0.wdt_flashboot_mod_en = (enable) ? 1 : 0; +} + +/** + * @brief Enable/Disable the CPU0 to be reset on WDT_STAGE_ACTION_RESET_CPU + * + * @param hw Start address of the peripheral registers. + * @param enable True to enable CPU0 to be reset, false to disable. + */ +FORCE_INLINE_ATTR void lpwdt_ll_set_procpu_reset_en(lp_wdt_dev_t *hw, bool enable) +{ + // TODO: [ESP32C5] IDF-8635 (inherit from C6) + // hw->config0.wdt_procpu_reset_en = (enable) ? 1 : 0; +} + +/** + * @brief Enable/Disable the CPU1 to be reset on WDT_STAGE_ACTION_RESET_CPU + * + * @param hw Start address of the peripheral registers. + * @param enable True to enable CPU1 to be reset, false to disable. + */ +FORCE_INLINE_ATTR void lpwdt_ll_set_appcpu_reset_en(lp_wdt_dev_t *hw, bool enable) +{ + // TODO: [ESP32C5] IDF-8635 (inherit from C6) + // hw->config0.wdt_appcpu_reset_en = (enable) ? 1 : 0; +} + +/** + * @brief Enable/Disable the RWDT pause during sleep functionality + * + * @param hw Start address of the peripheral registers. + * @param enable True to enable, false to disable. + */ +FORCE_INLINE_ATTR void lpwdt_ll_set_pause_in_sleep_en(lp_wdt_dev_t *hw, bool enable) +{ + // TODO: [ESP32C5] IDF-8635 (inherit from C6) + // hw->config0.wdt_pause_in_slp = (enable) ? 1 : 0; +} + +/** + * @brief Enable/Disable chip reset on RWDT timeout. + * + * A chip reset also resets the analog portion of the chip. It will appear as a + * POWERON reset rather than an RTC reset. + * + * @param hw Start address of the peripheral registers. + * @param enable True to enable, false to disable. + */ +FORCE_INLINE_ATTR void lpwdt_ll_set_chip_reset_en(lp_wdt_dev_t *hw, bool enable) +{ + // TODO: [ESP32C5] IDF-8635 (inherit from C6) + // hw->config0.wdt_chip_reset_en = (enable) ? 1 : 0; +} + +/** + * @brief Set width of chip reset signal + * + * @param hw Start address of the peripheral registers. + * @param width Width of chip reset signal in terms of number of RTC_SLOW_CLK cycles + */ +FORCE_INLINE_ATTR void lpwdt_ll_set_chip_reset_width(lp_wdt_dev_t *hw, uint32_t width) +{ + // TODO: [ESP32C5] IDF-8635 (inherit from C6) + // HAL_FORCE_MODIFY_U32_REG_FIELD(hw->config0, wdt_chip_reset_width, width); +} + +/** + * @brief Feed the RWDT + * + * Resets the current timer count and current stage. + * + * @param hw Start address of the peripheral registers. + */ +FORCE_INLINE_ATTR void lpwdt_ll_feed(lp_wdt_dev_t *hw) +{ + // TODO: [ESP32C5] IDF-8635 (inherit from C6) + // hw->feed.rtc_wdt_feed = 1; +} + +/** + * @brief Enable write protection of the RWDT registers + * + * @param hw Start address of the peripheral registers. + */ +FORCE_INLINE_ATTR void lpwdt_ll_write_protect_enable(lp_wdt_dev_t *hw) +{ + // TODO: [ESP32C5] IDF-8635 (inherit from C6) + // hw->wprotect.val = 0; +} + +/** + * @brief Disable write protection of the RWDT registers + * + * @param hw Start address of the peripheral registers. + */ +FORCE_INLINE_ATTR void lpwdt_ll_write_protect_disable(lp_wdt_dev_t *hw) +{ + // TODO: [ESP32C5] IDF-8635 (inherit from C6) + // hw->wprotect.val = LP_WDT_WKEY_VALUE; +} + +/** + * @brief Enable the RWDT interrupt. + * + * @param hw Start address of the peripheral registers. + * @param enable True to enable RWDT interrupt, false to disable. + */ +FORCE_INLINE_ATTR void lpwdt_ll_set_intr_enable(lp_wdt_dev_t *hw, bool enable) +{ + // TODO: [ESP32C5] IDF-8635 (inherit from C6) + // hw->int_ena.lp_wdt_int_ena = (enable) ? 1 : 0; +} + +/** + * @brief Check if the RWDT interrupt has been triggered + * + * @param hw Start address of the peripheral registers. + * @return True if the RWDT interrupt was triggered + */ +FORCE_INLINE_ATTR bool lpwdt_ll_check_intr_status(lp_wdt_dev_t *hw) +{ + // TODO: [ESP32C5] IDF-8635 (inherit from C6) + // return (hw->int_st.lp_wdt_int_st) ? true : false; + return (bool)0; +} + +/** + * @brief Clear the RWDT interrupt status. + * + * @param hw Start address of the peripheral registers. + */ +FORCE_INLINE_ATTR void lpwdt_ll_clear_intr_status(lp_wdt_dev_t *hw) +{ + // TODO: [ESP32C5] IDF-8635 (inherit from C6) + // hw->int_clr.lp_wdt_int_clr = 1; +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32c5/include/hal/mmu_ll.h b/components/hal/esp32c5/include/hal/mmu_ll.h new file mode 100644 index 000000000000..c63225b0d541 --- /dev/null +++ b/components/hal/esp32c5/include/hal/mmu_ll.h @@ -0,0 +1,433 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +// The LL layer for MMU register operations + +#pragma once + +#include "soc/spi_mem_reg.h" +// #include "soc/ext_mem_defs.h" +#include "hal/assert.h" +#include "hal/mmu_types.h" +#include "hal/efuse_ll.h" + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * Convert MMU virtual address to linear address + * + * @param vaddr virtual address + * + * @return linear address + */ +static inline uint32_t mmu_ll_vaddr_to_laddr(uint32_t vaddr) +{ + // TODO: [ESP32C5] IDF-8658 (inherit from C6) + // return vaddr & SOC_MMU_LINEAR_ADDR_MASK; + return (uint32_t)0; +} + +/** + * Convert MMU linear address to virtual address + * + * @param laddr linear address + * @param vaddr_type virtual address type, could be instruction type or data type. See `mmu_vaddr_t` + * @param target virtual address aimed physical memory target, not used + * + * @return virtual address + */ +static inline uint32_t mmu_ll_laddr_to_vaddr(uint32_t laddr, mmu_vaddr_t vaddr_type, mmu_target_t target) +{ + // TODO: [ESP32C5] IDF-8658 (inherit from C6) + // (void)target; + // (void)vaddr_type; + // //On ESP32C5, I/D share the same vaddr range + // return SOC_MMU_IBUS_VADDR_BASE | laddr; + return (uint32_t)0; +} + +__attribute__((always_inline)) static inline bool mmu_ll_cache_encryption_enabled(void) +{ + // TODO: [ESP32C5] IDF-8658 (inherit from C6) + // unsigned cnt = efuse_ll_get_flash_crypt_cnt(); + // // 3 bits wide, any odd number - 1 or 3 - bits set means encryption is on + // cnt = ((cnt >> 2) ^ (cnt >> 1) ^ cnt) & 0x1; + // return (cnt == 1); + return (bool)0; +} + +/** + * Get MMU page size + * + * @param mmu_id MMU ID + * + * @return MMU page size code + */ +__attribute__((always_inline)) +static inline mmu_page_size_t mmu_ll_get_page_size(uint32_t mmu_id) +{ + // TODO: [ESP32C5] IDF-8658 (inherit from C6) + // (void)mmu_id; + // uint32_t page_size_code = REG_GET_FIELD(SPI_MEM_MMU_POWER_CTRL_REG(0), SPI_MEM_MMU_PAGE_SIZE); + // return (page_size_code == 0) ? MMU_PAGE_64KB : + // (page_size_code == 1) ? MMU_PAGE_32KB : + // (page_size_code == 2) ? MMU_PAGE_16KB : + // MMU_PAGE_8KB; + return (mmu_page_size_t)0; +} + +/** + * Set MMU page size + * + * @param size MMU page size + */ +__attribute__((always_inline)) +static inline void mmu_ll_set_page_size(uint32_t mmu_id, uint32_t size) +{ + // TODO: [ESP32C5] IDF-8658 (inherit from C6) + // uint8_t reg_val = (size == MMU_PAGE_64KB) ? 0 : + // (size == MMU_PAGE_32KB) ? 1 : + // (size == MMU_PAGE_16KB) ? 2 : + // (size == MMU_PAGE_8KB) ? 3 : 0; + // REG_SET_FIELD(SPI_MEM_MMU_POWER_CTRL_REG(0), SPI_MEM_MMU_PAGE_SIZE, reg_val); +} + +/** + * Check if the external memory vaddr region is valid + * + * @param mmu_id MMU ID + * @param vaddr_start start of the virtual address + * @param len length, in bytes + * @param type virtual address type, could be instruction type or data type. See `mmu_vaddr_t` + * + * @return + * True for valid + */ +__attribute__((always_inline)) +static inline bool mmu_ll_check_valid_ext_vaddr_region(uint32_t mmu_id, uint32_t vaddr_start, uint32_t len, mmu_vaddr_t type) +{ + // TODO: [ESP32C5] IDF-8658 (inherit from C6) + // (void)mmu_id; + // (void)type; + // uint32_t vaddr_end = vaddr_start + len - 1; + // return (SOC_ADDRESS_IN_IRAM0_CACHE(vaddr_start) && SOC_ADDRESS_IN_IRAM0_CACHE(vaddr_end)) || (SOC_ADDRESS_IN_DRAM0_CACHE(vaddr_start) && SOC_ADDRESS_IN_DRAM0_CACHE(vaddr_end)); + return (bool)0; +} + +/** + * Check if the paddr region is valid + * + * @param mmu_id MMU ID + * @param paddr_start start of the physical address + * @param len length, in bytes + * + * @return + * True for valid + */ +static inline bool mmu_ll_check_valid_paddr_region(uint32_t mmu_id, uint32_t paddr_start, uint32_t len) +{ + // TODO: [ESP32C5] IDF-8658 (inherit from C6) + // (void)mmu_id; + // return (paddr_start < (mmu_ll_get_page_size(mmu_id) * SOC_MMU_MAX_PADDR_PAGE_NUM)) && + // (len < (mmu_ll_get_page_size(mmu_id) * SOC_MMU_MAX_PADDR_PAGE_NUM)) && + // ((paddr_start + len - 1) < (mmu_ll_get_page_size(mmu_id) * SOC_MMU_MAX_PADDR_PAGE_NUM)); + return (bool)0; +} + +/** + * To get the MMU table entry id to be mapped + * + * @param mmu_id MMU ID + * @param vaddr virtual address to be mapped + * + * @return + * MMU table entry id + */ +__attribute__((always_inline)) +static inline uint32_t mmu_ll_get_entry_id(uint32_t mmu_id, uint32_t vaddr) +{ + // TODO: [ESP32C5] IDF-8658 (inherit from C6) + // (void)mmu_id; + // mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id); + // uint32_t shift_code = 0; + // switch (page_size) { + // case MMU_PAGE_64KB: + // shift_code = 16; + // break; + // case MMU_PAGE_32KB: + // shift_code = 15; + // break; + // case MMU_PAGE_16KB: + // shift_code = 14; + // break; + // case MMU_PAGE_8KB: + // shift_code = 13; + // break; + // default: + // HAL_ASSERT(shift_code); + // } + // return ((vaddr & SOC_MMU_VADDR_MASK) >> shift_code); + return (uint32_t)0; +} + +/** + * Format the paddr to be mappable + * + * @param mmu_id MMU ID + * @param paddr physical address to be mapped + * @param target paddr memory target, not used + * + * @return + * mmu_val - paddr in MMU table supported format + */ +__attribute__((always_inline)) +static inline uint32_t mmu_ll_format_paddr(uint32_t mmu_id, uint32_t paddr, mmu_target_t target) +{ + // TODO: [ESP32C5] IDF-8658 (inherit from C6) + // (void)mmu_id; + // (void)target; + // mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id); + // uint32_t shift_code = 0; + // switch (page_size) { + // case MMU_PAGE_64KB: + // shift_code = 16; + // break; + // case MMU_PAGE_32KB: + // shift_code = 15; + // break; + // case MMU_PAGE_16KB: + // shift_code = 14; + // break; + // case MMU_PAGE_8KB: + // shift_code = 13; + // break; + // default: + // HAL_ASSERT(shift_code); + // } + // return paddr >> shift_code; + return (uint32_t)0; +} + +/** + * Write to the MMU table to map the virtual memory and the physical memory + * + * @param mmu_id MMU ID + * @param entry_id MMU entry ID + * @param mmu_val Value to be set into an MMU entry, for physical address + * @param target MMU target physical memory. + */ +__attribute__((always_inline)) static inline void mmu_ll_write_entry(uint32_t mmu_id, uint32_t entry_id, uint32_t mmu_val, mmu_target_t target) +{ + // TODO: [ESP32C5] IDF-8658 (inherit from C6) + // (void)mmu_id; + // (void)target; + // uint32_t mmu_raw_value; + // if (mmu_ll_cache_encryption_enabled()) { + // mmu_val |= SOC_MMU_SENSITIVE; + // } + // // mmu_raw_value = mmu_val | SOC_MMU_VALID; + // REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id); + // REG_WRITE(SPI_MEM_MMU_ITEM_CONTENT_REG(0), mmu_raw_value); +} + +/** + * Read the raw value from MMU table + * + * @param mmu_id MMU ID + * @param entry_id MMU entry ID + * @param mmu_val Value to be read from MMU table + */ +__attribute__((always_inline)) static inline uint32_t mmu_ll_read_entry(uint32_t mmu_id, uint32_t entry_id) +{ + // TODO: [ESP32C5] IDF-8658 (inherit from C6) + // (void)mmu_id; + // uint32_t mmu_raw_value; + // uint32_t ret; + // REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id); + // mmu_raw_value = REG_READ(SPI_MEM_MMU_ITEM_CONTENT_REG(0)); + // if (mmu_ll_cache_encryption_enabled()) { + // mmu_raw_value &= ~SOC_MMU_SENSITIVE; + // } + // if (!(mmu_raw_value & SOC_MMU_VALID)) { + // return 0; + // } + // ret = mmu_raw_value & SOC_MMU_VALID_VAL_MASK; + // return ret; + return (uint32_t)0; +} + +/** + * Set MMU table entry as invalid + * + * @param mmu_id MMU ID + * @param entry_id MMU entry + */ +__attribute__((always_inline)) static inline void mmu_ll_set_entry_invalid(uint32_t mmu_id, uint32_t entry_id) +{ + // TODO: [ESP32C5] IDF-8658 (inherit from C6) + // (void)mmu_id; + // REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id); + // REG_WRITE(SPI_MEM_MMU_ITEM_CONTENT_REG(0), SOC_MMU_INVALID); +} + +/** + * Unmap all the items in the MMU table + * + * @param mmu_id MMU ID + */ +__attribute__((always_inline)) +static inline void mmu_ll_unmap_all(uint32_t mmu_id) +{ + // TODO: [ESP32C5] IDF-8658 (inherit from C6) + // for (int i = 0; i < SOC_MMU_ENTRY_NUM; i++) { + // mmu_ll_set_entry_invalid(mmu_id, i); + // } +} + +/** + * Check MMU table entry value is valid + * + * @param mmu_id MMU ID + * @param entry_id MMU entry ID + * + * @return Ture for MMU entry is valid; False for invalid + */ +static inline bool mmu_ll_check_entry_valid(uint32_t mmu_id, uint32_t entry_id) +{ + // TODO: [ESP32C5] IDF-8658 (inherit from C6) + // (void)mmu_id; + // HAL_ASSERT(entry_id < SOC_MMU_ENTRY_NUM); + // // REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id); + // return (REG_READ(SPI_MEM_MMU_ITEM_CONTENT_REG(0)) & SOC_MMU_VALID) ? true : false; + return (bool)0; +} + +/** + * Get the MMU table entry target + * + * @param mmu_id MMU ID + * @param entry_id MMU entry ID + * + * @return Target, see `mmu_target_t` + */ +static inline mmu_target_t mmu_ll_get_entry_target(uint32_t mmu_id, uint32_t entry_id) +{ + // TODO: [ESP32C5] IDF-8658 (inherit from C6) + // (void)mmu_id; + // return MMU_TARGET_FLASH0; + return (mmu_target_t)0; +} + +/** + * Convert MMU entry ID to paddr base + * + * @param mmu_id MMU ID + * @param entry_id MMU entry ID + * + * @return paddr base + */ +static inline uint32_t mmu_ll_entry_id_to_paddr_base(uint32_t mmu_id, uint32_t entry_id) +{ + // TODO: [ESP32C5] IDF-8658 (inherit from C6) + // (void)mmu_id; + // HAL_ASSERT(entry_id < SOC_MMU_ENTRY_NUM); + // // mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id); + // uint32_t shift_code = 0; + // switch (page_size) { + // case MMU_PAGE_64KB: + // shift_code = 16; + // break; + // case MMU_PAGE_32KB: + // shift_code = 15; + // break; + // case MMU_PAGE_16KB: + // shift_code = 14; + // break; + // case MMU_PAGE_8KB: + // shift_code = 13; + // break; + // default: + // HAL_ASSERT(shift_code); + // } + // // REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id); + // return (REG_READ(SPI_MEM_MMU_ITEM_CONTENT_REG(0)) & SOC_MMU_VALID_VAL_MASK) << shift_code; + return (uint32_t)0; +} + +/** + * Find the MMU table entry ID based on table map value + * @note This function can only find the first match entry ID. However it is possible that a physical address + * is mapped to multiple virtual addresses + * + * @param mmu_id MMU ID + * @param mmu_val map value to be read from MMU table standing for paddr + * @param target physical memory target, see `mmu_target_t` + * + * @return MMU entry ID, -1 for invalid + */ +static inline int mmu_ll_find_entry_id_based_on_map_value(uint32_t mmu_id, uint32_t mmu_val, mmu_target_t target) +{ + // TODO: [ESP32C5] IDF-8658 (inherit from C6) + // (void)mmu_id; + // for (int i = 0; i < SOC_MMU_ENTRY_NUM; i++) { + // if (mmu_ll_check_entry_valid(mmu_id, i)) { + // if (mmu_ll_get_entry_target(mmu_id, i) == target) { + // REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), i); + // if ((REG_READ(SPI_MEM_MMU_ITEM_CONTENT_REG(0)) & SOC_MMU_VALID_VAL_MASK) == mmu_val) { + // return i; + // } + // } + // } + // } + // // return -1; + return (int)0; +} + +/** + * Convert MMU entry ID to vaddr base + * + * @param mmu_id MMU ID + * @param entry_id MMU entry ID + * @param type virtual address type, could be instruction type or data type. See `mmu_vaddr_t` + */ +static inline uint32_t mmu_ll_entry_id_to_vaddr_base(uint32_t mmu_id, uint32_t entry_id, mmu_vaddr_t type) +{ + // TODO: [ESP32C5] IDF-8658 (inherit from C6) + // (void)mmu_id; + // mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id); + // uint32_t shift_code = 0; + // // switch (page_size) { + // case MMU_PAGE_64KB: + // shift_code = 16; + // break; + // case MMU_PAGE_32KB: + // shift_code = 15; + // break; + // case MMU_PAGE_16KB: + // shift_code = 14; + // break; + // case MMU_PAGE_8KB: + // shift_code = 13; + // break; + // default: + // HAL_ASSERT(shift_code); + // } + // uint32_t laddr = entry_id << shift_code; + // // /** + // * For `mmu_ll_laddr_to_vaddr`, target is for compatibility on this chip. + // * Here we just pass MMU_TARGET_FLASH0 to get vaddr + // */ + // return mmu_ll_laddr_to_vaddr(laddr, type, MMU_TARGET_FLASH0); + return (uint32_t)0; +} + +#ifdef __cplusplus + return (uint32_t)0; +} +#endif diff --git a/components/hal/esp32c5/include/hal/mwdt_ll.h b/components/hal/esp32c5/include/hal/mwdt_ll.h new file mode 100644 index 000000000000..48e6af7d2788 --- /dev/null +++ b/components/hal/esp32c5/include/hal/mwdt_ll.h @@ -0,0 +1,341 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +// The LL layer for Timer Group register operations. +// Note that most of the register operations in this layer are non-atomic operations. + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include "soc/timer_periph.h" +#include "soc/timer_group_struct.h" +#include "soc/pcr_struct.h" +#include "hal/wdt_types.h" +#include "hal/assert.h" +#include "esp_attr.h" +#include "esp_assert.h" +#include "hal/misc.h" + +/* Pre-calculated prescaler to achieve 500 ticks/us (MWDT1_TICKS_PER_US) when using default clock (MWDT_CLK_SRC_DEFAULT ) */ +#define MWDT_LL_DEFAULT_CLK_PRESCALER 20000 + +/* The value that needs to be written to TIMG_WDT_WKEY to write-enable the wdt registers */ +#define TIMG_WDT_WKEY_VALUE 0x50D83AA1 + +/* Possible values for TIMG_WDT_STGx */ +#define TIMG_WDT_STG_SEL_OFF 0 +#define TIMG_WDT_STG_SEL_INT 1 +#define TIMG_WDT_STG_SEL_RESET_CPU 2 +#define TIMG_WDT_STG_SEL_RESET_SYSTEM 3 + +#define TIMG_WDT_RESET_LENGTH_100_NS 0 +#define TIMG_WDT_RESET_LENGTH_200_NS 1 +#define TIMG_WDT_RESET_LENGTH_300_NS 2 +#define TIMG_WDT_RESET_LENGTH_400_NS 3 +#define TIMG_WDT_RESET_LENGTH_500_NS 4 +#define TIMG_WDT_RESET_LENGTH_800_NS 5 +#define TIMG_WDT_RESET_LENGTH_1600_NS 6 +#define TIMG_WDT_RESET_LENGTH_3200_NS 7 + +//Type check wdt_stage_action_t +ESP_STATIC_ASSERT(WDT_STAGE_ACTION_OFF == TIMG_WDT_STG_SEL_OFF, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t"); +ESP_STATIC_ASSERT(WDT_STAGE_ACTION_INT == TIMG_WDT_STG_SEL_INT, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t"); +ESP_STATIC_ASSERT(WDT_STAGE_ACTION_RESET_CPU == TIMG_WDT_STG_SEL_RESET_CPU, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t"); +ESP_STATIC_ASSERT(WDT_STAGE_ACTION_RESET_SYSTEM == TIMG_WDT_STG_SEL_RESET_SYSTEM, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t"); +//Type check wdt_reset_sig_length_t +ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_100ns == TIMG_WDT_RESET_LENGTH_100_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t"); +ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_200ns == TIMG_WDT_RESET_LENGTH_200_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t"); +ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_300ns == TIMG_WDT_RESET_LENGTH_300_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t"); +ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_400ns == TIMG_WDT_RESET_LENGTH_400_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t"); +ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_500ns == TIMG_WDT_RESET_LENGTH_500_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t"); +ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_800ns == TIMG_WDT_RESET_LENGTH_800_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t"); +ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_1_6us == TIMG_WDT_RESET_LENGTH_1600_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t"); +ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_3_2us == TIMG_WDT_RESET_LENGTH_3200_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t"); + +/** + * @brief Enable the MWDT + * + * @param hw Start address of the peripheral registers. + */ +FORCE_INLINE_ATTR void mwdt_ll_enable(timg_dev_t *hw) +{ + // TODO: [ESP32C5] IDF-8650 (inherit from C6) + // hw->wdtconfig0.wdt_en = 1; +} + +/** + * @brief Disable the MWDT + * + * @param hw Start address of the peripheral registers. + * @note This function does not disable the flashboot mode. Therefore, given that + * the MWDT is disabled using this function, a timeout can still occur + * if the flashboot mode is simultaneously enabled. + */ +FORCE_INLINE_ATTR void mwdt_ll_disable(timg_dev_t *hw) +{ + // TODO: [ESP32C5] IDF-8650 (inherit from C6) + // hw->wdtconfig0.wdt_en = 0; +} + +/** + * Check if the MWDT is enabled + * + * @param hw Start address of the peripheral registers. + * @return True if the MWDT is enabled, false otherwise + */ +FORCE_INLINE_ATTR bool mwdt_ll_check_if_enabled(timg_dev_t *hw) +{ + // TODO: [ESP32C5] IDF-8650 (inherit from C6) + // return (hw->wdtconfig0.wdt_en) ? true : false; + return (bool)0; +} + +/** + * @brief Configure a particular stage of the MWDT + * + * @param hw Start address of the peripheral registers. + * @param stage Which stage to configure + * @param timeout Number of timer ticks for the stage to timeout + * @param behavior What action to take when the stage times out + */ +FORCE_INLINE_ATTR void mwdt_ll_config_stage(timg_dev_t *hw, wdt_stage_t stage, uint32_t timeout, wdt_stage_action_t behavior) +{ + // TODO: [ESP32C5] IDF-8650 (inherit from C6) + // switch (stage) { + // case WDT_STAGE0: + // hw->wdtconfig0.wdt_stg0 = behavior; + // hw->wdtconfig2.wdt_stg0_hold = timeout; + // break; + // case WDT_STAGE1: + // hw->wdtconfig0.wdt_stg1 = behavior; + // hw->wdtconfig3.wdt_stg1_hold = timeout; + // break; + // case WDT_STAGE2: + // hw->wdtconfig0.wdt_stg2 = behavior; + // hw->wdtconfig4.wdt_stg2_hold = timeout; + // break; + // case WDT_STAGE3: + // hw->wdtconfig0.wdt_stg3 = behavior; + // hw->wdtconfig5.wdt_stg3_hold = timeout; + // break; + // default: + // HAL_ASSERT(false && "unsupported WDT stage"); + // break; + // } + // //Config registers are updated asynchronously + // hw->wdtconfig0.wdt_conf_update_en = 1; +} + +/** + * @brief Disable a particular stage of the MWDT + * + * @param hw Start address of the peripheral registers. + * @param stage Which stage to disable + */ +FORCE_INLINE_ATTR void mwdt_ll_disable_stage(timg_dev_t *hw, uint32_t stage) +{ + // TODO: [ESP32C5] IDF-8650 (inherit from C6) + // switch (stage) { + // case WDT_STAGE0: + // hw->wdtconfig0.wdt_stg0 = WDT_STAGE_ACTION_OFF; + // break; + // case WDT_STAGE1: + // hw->wdtconfig0.wdt_stg1 = WDT_STAGE_ACTION_OFF; + // break; + // case WDT_STAGE2: + // hw->wdtconfig0.wdt_stg2 = WDT_STAGE_ACTION_OFF; + // break; + // case WDT_STAGE3: + // hw->wdtconfig0.wdt_stg3 = WDT_STAGE_ACTION_OFF; + // break; + // default: + // HAL_ASSERT(false && "unsupported WDT stage"); + // break; + // } + // //Config registers are updated asynchronously + // hw->wdtconfig0.wdt_conf_update_en = 1; +} + +/** + * @brief Set the length of the CPU reset action + * + * @param hw Start address of the peripheral registers. + * @param length Length of CPU reset signal + */ +FORCE_INLINE_ATTR void mwdt_ll_set_cpu_reset_length(timg_dev_t *hw, wdt_reset_sig_length_t length) +{ + // TODO: [ESP32C5] IDF-8650 (inherit from C6) + // hw->wdtconfig0.wdt_cpu_reset_length = length; + // //Config registers are updated asynchronously + // hw->wdtconfig0.wdt_conf_update_en = 1; +} + +/** + * @brief Set the length of the system reset action + * + * @param hw Start address of the peripheral registers. + * @param length Length of system reset signal + */ +FORCE_INLINE_ATTR void mwdt_ll_set_sys_reset_length(timg_dev_t *hw, wdt_reset_sig_length_t length) +{ + // TODO: [ESP32C5] IDF-8650 (inherit from C6) + // hw->wdtconfig0.wdt_sys_reset_length = length; + // //Config registers are updated asynchronously + // hw->wdtconfig0.wdt_conf_update_en = 1; +} + +/** + * @brief Enable/Disable the MWDT flashboot mode. + * + * @param hw Beginning address of the peripheral registers. + * @param enable True to enable WDT flashboot mode, false to disable WDT flashboot mode. + * + * @note Flashboot mode is independent and can trigger a WDT timeout event if the + * WDT's enable bit is set to 0. Flashboot mode for TG0 is automatically enabled + * on flashboot, and should be disabled by software when flashbooting completes. + */ +FORCE_INLINE_ATTR void mwdt_ll_set_flashboot_en(timg_dev_t *hw, bool enable) +{ + // TODO: [ESP32C5] IDF-8650 (inherit from C6) + // hw->wdtconfig0.wdt_flashboot_mod_en = (enable) ? 1 : 0; + // //Config registers are updated asynchronously + // hw->wdtconfig0.wdt_conf_update_en = 1; +} + +/** + * @brief Set the clock prescaler of the MWDT + * + * @param hw Start address of the peripheral registers. + * @param prescaler Prescaler value between 1 to 65535 + */ +FORCE_INLINE_ATTR void mwdt_ll_set_prescaler(timg_dev_t *hw, uint32_t prescaler) +{ + // TODO: [ESP32C5] IDF-8650 (inherit from C6) + // // In case the compiler optimise a 32bit instruction (e.g. s32i) into 8/16bit instruction (e.g. s8i, which is not allowed to access a register) + // // We take care of the "read-modify-write" procedure by ourselves. + // HAL_FORCE_MODIFY_U32_REG_FIELD(hw->wdtconfig1, wdt_clk_prescale, prescaler); + // //Config registers are updated asynchronously + // hw->wdtconfig0.wdt_conf_update_en = 1; +} + +/** + * @brief Feed the MWDT + * + * Resets the current timer count and current stage. + * + * @param hw Start address of the peripheral registers. + */ +FORCE_INLINE_ATTR void mwdt_ll_feed(timg_dev_t *hw) +{ + // TODO: [ESP32C5] IDF-8650 (inherit from C6) + // hw->wdtfeed.wdt_feed = 1; +} + +/** + * @brief Enable write protection of the MWDT registers + * + * Locking the MWDT will prevent any of the MWDT's registers from being modified + * + * @param hw Start address of the peripheral registers. + */ +FORCE_INLINE_ATTR void mwdt_ll_write_protect_enable(timg_dev_t *hw) +{ + // TODO: [ESP32C5] IDF-8650 (inherit from C6) + // hw->wdtwprotect.wdt_wkey = 0; +} + +/** + * @brief Disable write protection of the MWDT registers + * + * @param hw Start address of the peripheral registers. + */ +FORCE_INLINE_ATTR void mwdt_ll_write_protect_disable(timg_dev_t *hw) +{ + // TODO: [ESP32C5] IDF-8650 (inherit from C6) + // hw->wdtwprotect.wdt_wkey = TIMG_WDT_WKEY_VALUE; +} + +/** + * @brief Clear the MWDT interrupt status. + * + * @param hw Start address of the peripheral registers. + */ +FORCE_INLINE_ATTR void mwdt_ll_clear_intr_status(timg_dev_t *hw) +{ + // TODO: [ESP32C5] IDF-8650 (inherit from C6) + // hw->int_clr_timers.wdt_int_clr = 1; +} + +/** + * @brief Set the interrupt enable bit for the MWDT interrupt. + * + * @param hw Beginning address of the peripheral registers. + * @param enable Whether to enable the MWDT interrupt + */ +FORCE_INLINE_ATTR void mwdt_ll_set_intr_enable(timg_dev_t *hw, bool enable) +{ + // TODO: [ESP32C5] IDF-8650 (inherit from C6) + // hw->int_ena_timers.wdt_int_ena = (enable) ? 1 : 0; +} + +/** + * @brief Set the clock source for the MWDT. + * + * @param hw Beginning address of the peripheral registers. + * @param clk_src Clock source + */ +FORCE_INLINE_ATTR void mwdt_ll_set_clock_source(timg_dev_t *hw, mwdt_clock_source_t clk_src) +{ + // TODO: [ESP32C5] IDF-8650 (inherit from C6) + // uint8_t clk_id = 0; + // switch (clk_src) { + // case MWDT_CLK_SRC_XTAL: + // clk_id = 0; + // break; + // case MWDT_CLK_SRC_PLL_F80M: + // clk_id = 1; + // break; + // case MWDT_CLK_SRC_RC_FAST: + // clk_id = 2; + // break; + // default: + // HAL_ASSERT(false); + // break; + // } + // // if (hw == &TIMERG0) { + // PCR.timergroup0_wdt_clk_conf.tg0_wdt_clk_sel = clk_id; + // } else { + // PCR.timergroup1_wdt_clk_conf.tg1_wdt_clk_sel = clk_id; + // } +} + +/** + * @brief Enable MWDT module clock + * + * @param hw Beginning address of the peripheral registers. + * @param en true to enable, false to disable + */ +__attribute__((always_inline)) +static inline void mwdt_ll_enable_clock(timg_dev_t *hw, bool en) +{ + // TODO: [ESP32C5] IDF-8650 (inherit from C6) + // if (hw == &TIMERG0) { + // PCR.timergroup0_wdt_clk_conf.tg0_wdt_clk_en = en; + // } else { + // PCR.timergroup1_wdt_clk_conf.tg1_wdt_clk_en = en; + // } +} + + + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32c5/include/hal/rwdt_ll.h b/components/hal/esp32c5/include/hal/rwdt_ll.h new file mode 100644 index 000000000000..f4f059934261 --- /dev/null +++ b/components/hal/esp32c5/include/hal/rwdt_ll.h @@ -0,0 +1,80 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +// The LL layer for RTC(LP) watchdog register operations. +// Note that most of the register operations in this layer are non-atomic operations. + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include "hal/lpwdt_ll.h" + +typedef lp_wdt_dev_t rwdt_dev_t; + +#define RWDT_DEV_GET() &LP_WDT + +#define rwdt_ll_enable(hw) \ + lpwdt_ll_enable(hw) + +#define rwdt_ll_disable(hw) \ + lpwdt_ll_disable(hw) + +#define rwdt_ll_check_if_enabled(hw) \ + lpwdt_ll_check_if_enabled(hw) + +#define rwdt_ll_config_stage(hw, stage, timeout_ticks, behavior) \ + lpwdt_ll_config_stage(hw, stage, timeout_ticks, behavior) + +#define rwdt_ll_disable_stage(hw, stage) \ + lpwdt_ll_disable_stage(hw, stage) + +#define rwdt_ll_set_cpu_reset_length(hw, length) \ + lpwdt_ll_set_cpu_reset_length(hw, length) + +#define rwdt_ll_set_sys_reset_length(hw, length) \ + lpwdt_ll_set_sys_reset_length(hw, length) + +#define rwdt_ll_set_flashboot_en(hw, enable) \ + lpwdt_ll_set_flashboot_en(hw, enable) + +#define rwdt_ll_set_procpu_reset_en(hw, enable) \ + lpwdt_ll_set_procpu_reset_en(hw, enable) + +#define rwdt_ll_set_appcpu_reset_en(hw, enable) \ + lpwdt_ll_set_appcpu_reset_en(hw, enable) + +#define rwdt_ll_set_pause_in_sleep_en(hw, enable) \ + lpwdt_ll_set_pause_in_sleep_en(hw, enable) + +#define rwdt_ll_set_chip_reset_en(hw, enable) \ + lpwdt_ll_set_chip_reset_en(hw, enable) + +#define rwdt_ll_set_chip_reset_width(hw, width) \ + lpwdt_ll_set_chip_reset_width(hw, width) + +#define rwdt_ll_feed(hw) \ + lpwdt_ll_feed(hw) + +#define rwdt_ll_write_protect_enable(hw) \ + lpwdt_ll_write_protect_enable(hw) + +#define rwdt_ll_write_protect_disable(hw) \ + lpwdt_ll_write_protect_disable(hw) + +#define rwdt_ll_set_intr_enable(hw, enable) \ + lpwdt_ll_set_intr_enable(hw, enable) + +#define rwdt_ll_check_intr_status(hw) \ + lpwdt_ll_check_intr_status(hw) + +#define rwdt_ll_clear_intr_status(hw) \ + lpwdt_ll_clear_intr_status(hw) + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32c5/include/hal/uart_ll.h b/components/hal/esp32c5/include/hal/uart_ll.h new file mode 100644 index 000000000000..ab304bc657a1 --- /dev/null +++ b/components/hal/esp32c5/include/hal/uart_ll.h @@ -0,0 +1,1413 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +// The LL layer for UART register operations. +// Note that most of the register operations in this layer are non-atomic operations. + +#pragma once + +#include "esp_attr.h" +#include "hal/misc.h" +#include "hal/uart_types.h" +#include "soc/uart_reg.h" +#include "soc/uart_struct.h" +#include "soc/lp_uart_reg.h" +#include "soc/pcr_struct.h" +#include "soc/pcr_reg.h" +#include "soc/lp_clkrst_struct.h" +#include "soc/lpperi_struct.h" +#include "hal/assert.h" + +#ifdef __cplusplus +extern "C" { +#endif + +// The default fifo depth +#define UART_LL_FIFO_DEF_LEN (SOC_UART_FIFO_LEN) +#define LP_UART_LL_FIFO_DEF_LEN (SOC_LP_UART_FIFO_LEN) +// Get UART hardware instance with giving uart num +#define UART_LL_GET_HW(num) (((num) == UART_NUM_0) ? (&UART0) : (((num) == UART_NUM_1) ? (&UART1) : (&LP_UART))) + +#define UART_LL_REG_FIELD_BIT_SHIFT(hw) (((hw) == &LP_UART) ? 3 : 0) + +#define UART_LL_MIN_WAKEUP_THRESH (2) +#define UART_LL_INTR_MASK (0x7ffff) //All interrupt mask + +#define UART_LL_FSM_IDLE (0x0) +#define UART_LL_FSM_TX_WAIT_SEND (0xf) + +#define UART_LL_PCR_REG_U32_SET(hw, reg_suffix, field_suffix, val) \ + if ((hw) == &UART0) { \ + HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.uart0_##reg_suffix, uart0_##field_suffix, (val)) \ + } else { \ + HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.uart1_##reg_suffix, uart1_##field_suffix, (val)) \ + } + +#define UART_LL_PCR_REG_U32_GET(hw, reg_suffix, field_suffix) \ + (((hw) == &UART0) ? \ + HAL_FORCE_READ_U32_REG_FIELD(PCR.uart0_##reg_suffix, uart0_##field_suffix) : \ + HAL_FORCE_READ_U32_REG_FIELD(PCR.uart1_##reg_suffix, uart1_##field_suffix)) + +#define UART_LL_PCR_REG_SET(hw, reg_suffix, field_suffix, val) \ + if ((hw) == &UART0) { \ + PCR.uart0_##reg_suffix.uart0_##field_suffix = (val); \ + } else { \ + PCR.uart1_##reg_suffix.uart1_##field_suffix = (val); \ + } + +#define UART_LL_PCR_REG_GET(hw, reg_suffix, field_suffix) \ + (((hw) == &UART0) ? PCR.uart0_##reg_suffix.uart0_##field_suffix : PCR.uart1_##reg_suffix.uart1_##field_suffix) + +// Define UART interrupts +typedef enum { + UART_INTR_RXFIFO_FULL = (0x1 << 0), + UART_INTR_TXFIFO_EMPTY = (0x1 << 1), + UART_INTR_PARITY_ERR = (0x1 << 2), + UART_INTR_FRAM_ERR = (0x1 << 3), + UART_INTR_RXFIFO_OVF = (0x1 << 4), + UART_INTR_DSR_CHG = (0x1 << 5), + UART_INTR_CTS_CHG = (0x1 << 6), + UART_INTR_BRK_DET = (0x1 << 7), + UART_INTR_RXFIFO_TOUT = (0x1 << 8), + UART_INTR_SW_XON = (0x1 << 9), + UART_INTR_SW_XOFF = (0x1 << 10), + UART_INTR_GLITCH_DET = (0x1 << 11), + UART_INTR_TX_BRK_DONE = (0x1 << 12), + UART_INTR_TX_BRK_IDLE = (0x1 << 13), + UART_INTR_TX_DONE = (0x1 << 14), + UART_INTR_RS485_PARITY_ERR = (0x1 << 15), + UART_INTR_RS485_FRM_ERR = (0x1 << 16), + UART_INTR_RS485_CLASH = (0x1 << 17), + UART_INTR_CMD_CHAR_DET = (0x1 << 18), + UART_INTR_WAKEUP = (0x1 << 19), +} uart_intr_t; + +/** + * @brief Sync the update to UART core clock domain + * + * @param hw Beginning address of the peripheral registers. + * + * @return None. + */ +FORCE_INLINE_ATTR void uart_ll_update(uart_dev_t *hw) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // hw->reg_update.reg_update = 1; + // while (hw->reg_update.reg_update); +} + +/****************************************** LP_UART Specific ********************************************/ +/** + * @brief Get the LP_UART source clock. + * + * @param hw Beginning address of the peripheral registers. + * @param source_clk Current LP_UART clock source, one in soc_periph_lp_uart_clk_src_t. + */ +FORCE_INLINE_ATTR void lp_uart_ll_get_sclk(uart_dev_t *hw, soc_module_clk_t *source_clk) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // (void)hw; + // switch (LP_CLKRST.lpperi.lp_uart_clk_sel) { + // default: + // case 0: + // *source_clk = (soc_module_clk_t)LP_UART_SCLK_LP_FAST; + // break; + // case 1: + // *source_clk = (soc_module_clk_t)LP_UART_SCLK_XTAL_D2; + // break; + // } +} + +/** + * @brief Set LP UART source clock + * + * @param hw Address offset of the LP UART peripheral registers + * @param src_clk Source clock for the LP UART peripheral + */ +static inline void lp_uart_ll_set_source_clk(uart_dev_t *hw, soc_periph_lp_uart_clk_src_t src_clk) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // (void)hw; + // switch (src_clk) { + // case LP_UART_SCLK_LP_FAST: + // LP_CLKRST.lpperi.lp_uart_clk_sel = 0; + // break; + // case LP_UART_SCLK_XTAL_D2: + // LP_CLKRST.lpperi.lp_uart_clk_sel = 1; + // break; + // default: + // // Invalid LP_UART clock source + // HAL_ASSERT(false); + // } +} + +/// LP_CLKRST.lpperi is a shared register, so this function must be used in an atomic way +#define lp_uart_ll_set_source_clk(...) (void)__DECLARE_RCC_ATOMIC_ENV; lp_uart_ll_set_source_clk(__VA_ARGS__) + +/** + * @brief Configure the lp uart baud-rate. + * + * @param hw Beginning address of the peripheral registers. + * @param baud The baud rate to be set. + * @param sclk_freq Frequency of the clock source of UART, in Hz. + * + * @return None + */ +FORCE_INLINE_ATTR void lp_uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t sclk_freq) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // ine DIV_UP(a, b) (((a) + (b) - 1) / (b)) + // const uint32_t max_div = BIT(12) - 1; // UART divider integer part only has 12 bits + // uint32_t sclk_div = DIV_UP(sclk_freq, (uint64_t)max_div * baud); + // // if (sclk_div == 0) abort(); + // // uint32_t clk_div = ((sclk_freq) << 4) / (baud * sclk_div); + // // The baud rate configuration register is divided into + // // an integer part and a fractional part. + // hw->clkdiv_sync.clkdiv_int = clk_div >> 4; + // hw->clkdiv_sync.clkdiv_frag = clk_div & 0xf; + // HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clk_conf, sclk_div_num, sclk_div - 1); + // uart_ll_update(hw); +} + +/** + * @brief Enable bus clock for the LP UART module + * + * @param hw_id LP UART instance ID + * @param enable True to enable, False to disable + */ +static inline void lp_uart_ll_enable_bus_clock(int hw_id, bool enable) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // (void)hw_id; + // LPPERI.clk_en.lp_uart_ck_en = enable; +} + +/// LPPERI.clk_en is a shared register, so this function must be used in an atomic way +#define lp_uart_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; lp_uart_ll_enable_bus_clock(__VA_ARGS__) + +/** + * @brief Reset LP UART module + * + * @param hw_id LP UART instance ID + */ +static inline void lp_uart_ll_reset_register(int hw_id) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // (void)hw_id; + // LPPERI.reset_en.lp_uart_reset_en = 1; + // LPPERI.reset_en.lp_uart_reset_en = 0; +} + +/// LPPERI.reset_en is a shared register, so this function must be used in an atomic way +#define lp_uart_ll_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; lp_uart_ll_reset_register(__VA_ARGS__) + +/*************************************** General LL functions ******************************************/ + +/** + * @brief Check if UART is enabled or disabled. + * + * @param uart_num UART port number, the max port number is (UART_NUM_MAX -1). + * + * @return true: enabled; false: disabled + */ +FORCE_INLINE_ATTR bool uart_ll_is_enabled(uint32_t uart_num) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // HAL_ASSERT(uart_num < SOC_UART_HP_NUM); + // uint32_t uart_clk_config_reg = ((uart_num == 0) ? PCR_UART0_CONF_REG : + // (uart_num == 1) ? PCR_UART1_CONF_REG : 0); + // uint32_t uart_rst_bit = ((uart_num == 0) ? PCR_UART0_RST_EN : + // (uart_num == 1) ? PCR_UART1_RST_EN : 0); + // uint32_t uart_en_bit = ((uart_num == 0) ? PCR_UART0_CLK_EN : + // (uart_num == 1) ? PCR_UART1_CLK_EN : 0); + // return REG_GET_BIT(uart_clk_config_reg, uart_rst_bit) == 0 && + // REG_GET_BIT(uart_clk_config_reg, uart_en_bit) != 0; + return (bool)0; +} + +/** + * @brief Enable the bus clock for uart + * @param uart_num UART port number, the max port number is (UART_NUM_MAX -1). + * @param enable true to enable, false to disable + */ +static inline void uart_ll_enable_bus_clock(uart_port_t uart_num, bool enable) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // switch (uart_num) { + // case 0: + // PCR.uart0_conf.uart0_clk_en = enable; + // break; + // case 1: + // PCR.uart1_conf.uart1_clk_en = enable; + // break; + // default: + // // LP_UART + // abort(); + // break; + // } +} + +/** + * @brief Reset UART module + * @param uart_num UART port number, the max port number is (UART_NUM_MAX -1). + */ +static inline void uart_ll_reset_register(uart_port_t uart_num) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // switch (uart_num) { + // case 0: + // PCR.uart0_conf.uart0_rst_en = 1; + // PCR.uart0_conf.uart0_rst_en = 0; + // break; + // case 1: + // PCR.uart1_conf.uart1_rst_en = 1; + // PCR.uart1_conf.uart1_rst_en = 0; + // break; + // default: + // // LP_UART + // abort(); + // break; + // } +} + +/** + * @brief Enable the UART clock. + * + * @param hw Beginning address of the peripheral registers. + * + * @return None. + */ +FORCE_INLINE_ATTR void uart_ll_sclk_enable(uart_dev_t *hw) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // if ((hw) != &LP_UART) { + // UART_LL_PCR_REG_SET(hw, sclk_conf, sclk_en, 1); + // } else { + // // LP_UART clk_en shares the same register with other LP peripherals + // // Needs to be protected with a lock, therefore, it has its unique LL function + // abort(); + // } +} + +/** + * @brief Disable the UART clock. + * + * @param hw Beginning address of the peripheral registers. + * + * @return None. + */ +FORCE_INLINE_ATTR void uart_ll_sclk_disable(uart_dev_t *hw) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // if ((hw) != &LP_UART) { + // UART_LL_PCR_REG_SET(hw, sclk_conf, sclk_en, 0); + // } else { + // // LP_UART clk_en shares the same register with other LP peripherals + // // Needs to be protected with a lock, therefore, it has its unique LL function + // abort(); + // } +} + +/** + * @brief Set the UART source clock. + * + * @param hw Beginning address of the peripheral registers. + * @param source_clk The UART source clock. The source clock can be PLL_F80M clock, RTC clock or XTAL clock. + * All clock sources can remain at their original frequencies during DFS. + * + * @return None. + */ +FORCE_INLINE_ATTR void uart_ll_set_sclk(uart_dev_t *hw, soc_module_clk_t source_clk) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // if ((hw) != &LP_UART) { + // uint32_t sel_value = 0; + // switch (source_clk) { + // case UART_SCLK_PLL_F80M: + // sel_value = 1; + // break; + // case UART_SCLK_RTC: + // sel_value = 2; + // break; + // case UART_SCLK_XTAL: + // sel_value = 3; + // break; + // default: + // // Invalid HP_UART clock source + // abort(); + // } + // UART_LL_PCR_REG_SET(hw, sclk_conf, sclk_sel, sel_value); + // } else { + // // LP_UART clk_sel shares the same register with other LP peripherals + // // Needs to be protected with a lock, therefore, it has its unique LL function + // abort(); + // } +} + +/** + * @brief Get the UART source clock type. + * + * @param hw Beginning address of the peripheral registers. + * @param source_clk The pointer to accept the UART source clock type. + * + * @return None. + */ +FORCE_INLINE_ATTR void uart_ll_get_sclk(uart_dev_t *hw, soc_module_clk_t *source_clk) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // if ((hw) != &LP_UART) { + // switch (UART_LL_PCR_REG_GET(hw, sclk_conf, sclk_sel)) { + // default: + // case 1: + // *source_clk = (soc_module_clk_t)UART_SCLK_PLL_F80M; + // break; + // case 2: + // *source_clk = (soc_module_clk_t)UART_SCLK_RTC; + // break; + // case 3: + // *source_clk = (soc_module_clk_t)UART_SCLK_XTAL; + // break; + // } + // } else { + // lp_uart_ll_get_sclk(hw, source_clk); + // } +} + +/** + * @brief Configure the baud-rate. + * + * @param hw Beginning address of the peripheral registers. + * @param baud The baud rate to be set. + * @param sclk_freq Frequency of the clock source of UART, in Hz. + * + * @return None + */ +FORCE_INLINE_ATTR void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t sclk_freq) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // ine DIV_UP(a, b) (((a) + (b) - 1) / (b)) + // const uint32_t max_div = BIT(12) - 1; // UART divider integer part only has 12 bits + // uint32_t sclk_div = DIV_UP(sclk_freq, (uint64_t)max_div * baud); + // // if (sclk_div == 0) abort(); + // // uint32_t clk_div = ((sclk_freq) << 4) / (baud * sclk_div); + // // The baud rate configuration register is divided into + // // an integer part and a fractional part. + // hw->clkdiv_sync.clkdiv_int = clk_div >> 4; + // hw->clkdiv_sync.clkdiv_frag = clk_div & 0xf; + // if ((hw) == &LP_UART) { + // abort(); + // } else { + // UART_LL_PCR_REG_U32_SET(hw, sclk_conf, sclk_div_num, sclk_div - 1); + // } + // ef DIV_UP + // uart_ll_update(hw); +} + +/** + * @brief Get the current baud-rate. + * + * @param hw Beginning address of the peripheral registers. + * @param sclk_freq Frequency of the clock source of UART, in Hz. + * + * @return The current baudrate + */ +FORCE_INLINE_ATTR uint32_t uart_ll_get_baudrate(uart_dev_t *hw, uint32_t sclk_freq) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // typeof(hw->clkdiv_sync) div_reg; + // div_reg.val = hw->clkdiv_sync.val; + // int sclk_div; + // if ((hw) == &LP_UART) { + // sclk_div = HAL_FORCE_READ_U32_REG_FIELD(hw->clk_conf, sclk_div_num) + 1; + // } else { + // sclk_div = UART_LL_PCR_REG_U32_GET(hw, sclk_conf, sclk_div_num) + 1; + // } + // return ((sclk_freq << 4)) / (((div_reg.clkdiv_int << 4) | div_reg.clkdiv_frag) * sclk_div); + return (uint32_t)0; +} + +/** + * @brief Enable the UART interrupt based on the given mask. + * + * @param hw Beginning address of the peripheral registers. + * @param mask The bitmap of the interrupts need to be enabled. + * + * @return None + */ +FORCE_INLINE_ATTR void uart_ll_ena_intr_mask(uart_dev_t *hw, uint32_t mask) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // hw->int_ena.val = hw->int_ena.val | mask; +} + +/** + * @brief Disable the UART interrupt based on the given mask. + * + * @param hw Beginning address of the peripheral registers. + * @param mask The bitmap of the interrupts need to be disabled. + * + * @return None + */ +FORCE_INLINE_ATTR void uart_ll_disable_intr_mask(uart_dev_t *hw, uint32_t mask) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // hw->int_ena.val = hw->int_ena.val & (~mask); +} + +/** + * @brief Get the UART raw interrupt status. + * + * @param hw Beginning address of the peripheral registers. + * + * @return The UART interrupt status. + */ +FORCE_INLINE_ATTR uint32_t uart_ll_get_intraw_mask(uart_dev_t *hw) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // return hw->int_raw.val; + return (uint32_t)0; +} + +/** + * @brief Get the UART interrupt status. + * + * @param hw Beginning address of the peripheral registers. + * + * @return The UART interrupt status. + */ +FORCE_INLINE_ATTR uint32_t uart_ll_get_intsts_mask(uart_dev_t *hw) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // return hw->int_st.val; + return (uint32_t)0; +} + +/** + * @brief Clear the UART interrupt status based on the given mask. + * + * @param hw Beginning address of the peripheral registers. + * @param mask The bitmap of the interrupts need to be cleared. + * + * @return None + */ +FORCE_INLINE_ATTR void uart_ll_clr_intsts_mask(uart_dev_t *hw, uint32_t mask) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // hw->int_clr.val = mask; +} + +/** + * @brief Get status of enabled interrupt. + * + * @param hw Beginning address of the peripheral registers. + * + * @return interrupt enable value + */ +FORCE_INLINE_ATTR uint32_t uart_ll_get_intr_ena_status(uart_dev_t *hw) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // return hw->int_ena.val; + return (uint32_t)0; +} + +/** + * @brief Read the UART rxfifo. + * + * @param hw Beginning address of the peripheral registers. + * @param buf The data buffer. The buffer size should be large than 128 byts. + * @param rd_len The data length needs to be read. + * + * @return None. + */ +FORCE_INLINE_ATTR void uart_ll_read_rxfifo(uart_dev_t *hw, uint8_t *buf, uint32_t rd_len) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // for (int i = 0; i < (int)rd_len; i++) { + // buf[i] = hw->fifo.rxfifo_rd_byte; + // } +} + +/** + * @brief Write byte to the UART txfifo. + * + * @param hw Beginning address of the peripheral registers. + * @param buf The data buffer. + * @param wr_len The data length needs to be written. + * + * @return None + */ +FORCE_INLINE_ATTR void uart_ll_write_txfifo(uart_dev_t *hw, const uint8_t *buf, uint32_t wr_len) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // for (int i = 0; i < (int)wr_len; i++) { + // hw->fifo.rxfifo_rd_byte = buf[i]; + // } +} + +/** + * @brief Reset the UART hw rxfifo. + * + * @param hw Beginning address of the peripheral registers. + * + * @return None + */ +FORCE_INLINE_ATTR void uart_ll_rxfifo_rst(uart_dev_t *hw) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // hw->conf0_sync.rxfifo_rst = 1; + // uart_ll_update(hw); + // hw->conf0_sync.rxfifo_rst = 0; + // uart_ll_update(hw); +} + +/** + * @brief Reset the UART hw txfifo. + * + * @param hw Beginning address of the peripheral registers. + * + * @return None + */ +FORCE_INLINE_ATTR void uart_ll_txfifo_rst(uart_dev_t *hw) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // hw->conf0_sync.txfifo_rst = 1; + // uart_ll_update(hw); + // hw->conf0_sync.txfifo_rst = 0; + // uart_ll_update(hw); +} + +/** + * @brief Get the length of readable data in UART rxfifo. + * + * @param hw Beginning address of the peripheral registers. + * + * @return The readable data length in rxfifo. + */ +FORCE_INLINE_ATTR uint32_t uart_ll_get_rxfifo_len(uart_dev_t *hw) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // return (hw->status.rxfifo_cnt) >> UART_LL_REG_FIELD_BIT_SHIFT(hw); + return (uint32_t)0; +} + +/** + * @brief Get the writable data length of UART txfifo. + * + * @param hw Beginning address of the peripheral registers. + * + * @return The data length of txfifo can be written. + */ +FORCE_INLINE_ATTR uint32_t uart_ll_get_txfifo_len(uart_dev_t *hw) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // uint32_t total_fifo_len = ((hw) == &LP_UART) ? LP_UART_LL_FIFO_DEF_LEN : UART_LL_FIFO_DEF_LEN; + // uint32_t txfifo_len = (hw->status.txfifo_cnt) >> UART_LL_REG_FIELD_BIT_SHIFT(hw); + // return (total_fifo_len - txfifo_len); + return (uint32_t)0; +} + +/** + * @brief Configure the UART stop bit. + * + * @param hw Beginning address of the peripheral registers. + * @param stop_bit The stop bit number to be set. + * + * @return None. + */ +FORCE_INLINE_ATTR void uart_ll_set_stop_bits(uart_dev_t *hw, uart_stop_bits_t stop_bit) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // hw->conf0_sync.stop_bit_num = stop_bit; + // uart_ll_update(hw); +} + +/** + * @brief Get the configuration of the UART stop bit. + * + * @param hw Beginning address of the peripheral registers. + * @param stop_bit The pointer to accept the stop bit configuration + * + * @return None. + */ +FORCE_INLINE_ATTR void uart_ll_get_stop_bits(uart_dev_t *hw, uart_stop_bits_t *stop_bit) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // *stop_bit = (uart_stop_bits_t)hw->conf0_sync.stop_bit_num; +} + +/** + * @brief Configure the UART parity check mode. + * + * @param hw Beginning address of the peripheral registers. + * @param parity_mode The parity check mode to be set. + * + * @return None. + */ +FORCE_INLINE_ATTR void uart_ll_set_parity(uart_dev_t *hw, uart_parity_t parity_mode) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // if (parity_mode != UART_PARITY_DISABLE) { + // hw->conf0_sync.parity = parity_mode & 0x1; + // } + // hw->conf0_sync.parity_en = (parity_mode >> 1) & 0x1; + // uart_ll_update(hw); +} + +/** + * @brief Get the UART parity check mode configuration. + * + * @param hw Beginning address of the peripheral registers. + * @param parity_mode The pointer to accept the parity check mode configuration. + * + * @return None. + */ +FORCE_INLINE_ATTR void uart_ll_get_parity(uart_dev_t *hw, uart_parity_t *parity_mode) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // if (hw->conf0_sync.parity_en) { + // *parity_mode = (uart_parity_t)(0x2 | hw->conf0_sync.parity); + // } else { + // *parity_mode = UART_PARITY_DISABLE; + // } +} + +/** + * @brief Set the UART rxfifo full threshold value. When the data in rxfifo is more than the threshold value, + * it will produce rxfifo_full_int_raw interrupt. + * + * @param hw Beginning address of the peripheral registers. + * @param full_thrhd The full threshold value of the rxfifo. `full_thrhd` should be less than `(LP_)UART_LL_FIFO_DEF_LEN`. + * + * @return None. + */ +FORCE_INLINE_ATTR void uart_ll_set_rxfifo_full_thr(uart_dev_t *hw, uint16_t full_thrhd) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // hw->conf1.rxfifo_full_thrhd = full_thrhd << UART_LL_REG_FIELD_BIT_SHIFT(hw); +} + +/** + * @brief Set the txfifo empty threshold. when the data length in txfifo is less than threshold value, + * it will produce txfifo_empty_int_raw interrupt. + * + * @param hw Beginning address of the peripheral registers. + * @param empty_thrhd The empty threshold of txfifo. + * + * @return None. + */ +FORCE_INLINE_ATTR void uart_ll_set_txfifo_empty_thr(uart_dev_t *hw, uint16_t empty_thrhd) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // hw->conf1.txfifo_empty_thrhd = empty_thrhd << UART_LL_REG_FIELD_BIT_SHIFT(hw); +} + +/** + * @brief Set the UART rx-idle threshold value. when receiver takes more time than rx_idle_thrhd to receive a byte data, + * it will produce frame end signal for uhci to stop receiving data. + * + * @param hw Beginning address of the peripheral registers. + * @param rx_idle_thr The rx-idle threshold to be set. + * + * @return None. + */ +FORCE_INLINE_ATTR void uart_ll_set_rx_idle_thr(uart_dev_t *hw, uint32_t rx_idle_thr) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // hw->idle_conf_sync.rx_idle_thrhd = rx_idle_thr; + // uart_ll_update(hw); +} + +/** + * @brief Configure the duration time between transfers. + * + * @param hw Beginning address of the peripheral registers. + * @param idle_num the duration time between transfers. + * + * @return None. + */ +FORCE_INLINE_ATTR void uart_ll_set_tx_idle_num(uart_dev_t *hw, uint32_t idle_num) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // hw->idle_conf_sync.tx_idle_num = idle_num; + // uart_ll_update(hw); +} + +/** + * @brief Configure the transmiter to send break chars. + * + * @param hw Beginning address of the peripheral registers. + * @param break_num The number of the break chars need to be send. + * + * @return None. + */ +FORCE_INLINE_ATTR void uart_ll_tx_break(uart_dev_t *hw, uint32_t break_num) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // if (break_num > 0) { + // HAL_FORCE_MODIFY_U32_REG_FIELD(hw->txbrk_conf_sync, tx_brk_num, break_num); + // hw->conf0_sync.txd_brk = 1; + // } else { + // hw->conf0_sync.txd_brk = 0; + // } + // uart_ll_update(hw); +} + +/** + * @brief Configure the UART hardware flow control. + * + * @param hw Beginning address of the peripheral registers. + * @param flow_ctrl The hw flow control configuration. + * @param rx_thrs The rx flow control signal will be active if the data length in rxfifo is more than this value. + * + * @return None. + */ +FORCE_INLINE_ATTR void uart_ll_set_hw_flow_ctrl(uart_dev_t *hw, uart_hw_flowcontrol_t flow_ctrl, uint32_t rx_thrs) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // //only when UART_HW_FLOWCTRL_RTS is set , will the rx_thresh value be set. + // if (flow_ctrl & UART_HW_FLOWCTRL_RTS) { + // hw->hwfc_conf_sync.rx_flow_thrhd = rx_thrs << UART_LL_REG_FIELD_BIT_SHIFT(hw); + // hw->hwfc_conf_sync.rx_flow_en = 1; + // } else { + // hw->hwfc_conf_sync.rx_flow_en = 0; + // } + // if (flow_ctrl & UART_HW_FLOWCTRL_CTS) { + // hw->conf0_sync.tx_flow_en = 1; + // } else { + // hw->conf0_sync.tx_flow_en = 0; + // } + // uart_ll_update(hw); +} + +/** + * @brief Configure the hardware flow control. + * + * @param hw Beginning address of the peripheral registers. + * @param flow_ctrl A pointer to accept the hw flow control configuration. + * + * @return None. + */ +FORCE_INLINE_ATTR void uart_ll_get_hw_flow_ctrl(uart_dev_t *hw, uart_hw_flowcontrol_t *flow_ctrl) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // *flow_ctrl = UART_HW_FLOWCTRL_DISABLE; + // if (hw->hwfc_conf_sync.rx_flow_en) { + // *flow_ctrl = (uart_hw_flowcontrol_t)((unsigned int)(*flow_ctrl) | (unsigned int)UART_HW_FLOWCTRL_RTS); + // } + // if (hw->conf0_sync.tx_flow_en) { + // *flow_ctrl = (uart_hw_flowcontrol_t)((unsigned int)(*flow_ctrl) | (unsigned int)UART_HW_FLOWCTRL_CTS); + // } +} + +/** + * @brief Configure the software flow control. + * + * @param hw Beginning address of the peripheral registers. + * @param flow_ctrl The UART sofware flow control settings. + * @param sw_flow_ctrl_en Set true to enable software flow control, otherwise set it false. + * + * @return None. + */ +FORCE_INLINE_ATTR void uart_ll_set_sw_flow_ctrl(uart_dev_t *hw, uart_sw_flowctrl_t *flow_ctrl, bool sw_flow_ctrl_en) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // if (sw_flow_ctrl_en) { + // hw->swfc_conf0_sync.xonoff_del = 1; + // hw->swfc_conf0_sync.sw_flow_con_en = 1; + // hw->swfc_conf1.xon_threshold = (flow_ctrl->xon_thrd) << UART_LL_REG_FIELD_BIT_SHIFT(hw); + // hw->swfc_conf1.xoff_threshold = (flow_ctrl->xoff_thrd) << UART_LL_REG_FIELD_BIT_SHIFT(hw); + // HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf0_sync, xon_char, flow_ctrl->xon_char); + // HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf0_sync, xoff_char, flow_ctrl->xoff_char); + // } else { + // hw->swfc_conf0_sync.sw_flow_con_en = 0; + // hw->swfc_conf0_sync.xonoff_del = 0; + // } + // uart_ll_update(hw); +} + +/** + * @brief Configure the AT cmd char. When the receiver receives a continuous AT cmd char, it will produce at_cmd_char_det interrupt. + * + * @param hw Beginning address of the peripheral registers. + * @param cmd_char The AT cmd char configuration.The configuration member is: + * - cmd_char The AT cmd character + * - char_num The number of received AT cmd char must be equal to or greater than this value + * - gap_tout The interval between each AT cmd char, when the duration is less than this value, it will not take this data as AT cmd char + * - pre_idle The idle time before the first AT cmd char, when the duration is less than this value, it will not take the previous data as the last AT cmd char + * - post_idle The idle time after the last AT cmd char, when the duration is less than this value, it will not take this data as the first AT cmd char + * + * @return None. + */ +FORCE_INLINE_ATTR void uart_ll_set_at_cmd_char(uart_dev_t *hw, uart_at_cmd_t *cmd_char) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_char_sync, data, cmd_char->cmd_char); + // HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_char_sync, char_num, cmd_char->char_num); + // HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_postcnt_sync, post_idle_num, cmd_char->post_idle); + // HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_precnt_sync, pre_idle_num, cmd_char->pre_idle); + // HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_gaptout_sync, rx_gap_tout, cmd_char->gap_tout); + // uart_ll_update(hw); +} + +/** + * @brief Set the UART data bit mode. + * + * @param hw Beginning address of the peripheral registers. + * @param data_bit The data bit mode to be set. + * + * @return None. + */ +FORCE_INLINE_ATTR void uart_ll_set_data_bit_num(uart_dev_t *hw, uart_word_length_t data_bit) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // hw->conf0_sync.bit_num = data_bit; + // uart_ll_update(hw); +} + +/** + * @brief Set the rts active level. + * + * @param hw Beginning address of the peripheral registers. + * @param level The rts active level, 0 or 1. + * + * @return None. + */ +FORCE_INLINE_ATTR void uart_ll_set_rts_active_level(uart_dev_t *hw, int level) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // hw->conf0_sync.sw_rts = level & 0x1; + // uart_ll_update(hw); +} + +/** + * @brief Set the dtr active level. + * + * @param hw Beginning address of the peripheral registers. + * @param level The dtr active level, 0 or 1. + * + * @return None. + */ +FORCE_INLINE_ATTR void uart_ll_set_dtr_active_level(uart_dev_t *hw, int level) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // hw->conf1.sw_dtr = level & 0x1; +} + +/** + * @brief Set the UART wakeup threshold. + * + * @param hw Beginning address of the peripheral registers. + * @param wakeup_thrd The wakeup threshold value to be set. When the input rx edge changes more than this value, + * the UART will active from light sleeping mode. + * + * @return None. + */ +FORCE_INLINE_ATTR void uart_ll_set_wakeup_thrd(uart_dev_t *hw, uint32_t wakeup_thrd) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // hw->sleep_conf2.active_threshold = wakeup_thrd - UART_LL_MIN_WAKEUP_THRESH; +} + +/** + * @brief Configure the UART work in normal mode. + * + * @param hw Beginning address of the peripheral registers. + * + * @return None. + */ +FORCE_INLINE_ATTR void uart_ll_set_mode_normal(uart_dev_t *hw) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // // This function is only for HP_UART use + // // LP_UART can only work in normal mode + // // lp_uart_dev_t has no following fields (reserved), but no harm since we map the LP_UART instance to the uart_dev_t struct + // // hw->rs485_conf_sync.rs485_en = 0; + // hw->rs485_conf_sync.rs485tx_rx_en = 0; + // hw->rs485_conf_sync.rs485rxby_tx_en = 0; + // hw->conf0_sync.irda_en = 0; + // uart_ll_update(hw); +} + +/** + * @brief Configure the UART work in rs485_app_ctrl mode. + * + * @param hw Beginning address of the peripheral registers. + * + * @return None. + */ +FORCE_INLINE_ATTR void uart_ll_set_mode_rs485_app_ctrl(uart_dev_t *hw) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // // This function is only for HP_UART use + // // LP_UART can only work in normal mode + // // lp_uart_dev_t has no following fields (reserved), but no harm since we map the LP_UART instance to the uart_dev_t struct + // // // Application software control, remove echo + // hw->rs485_conf_sync.rs485rxby_tx_en = 1; + // hw->conf0_sync.irda_en = 0; + // hw->conf0_sync.sw_rts = 0; + // hw->conf0_sync.irda_en = 0; + // hw->rs485_conf_sync.dl0_en = 1; + // hw->rs485_conf_sync.dl1_en = 1; + // hw->rs485_conf_sync.rs485_en = 1; + // uart_ll_update(hw); +} + +/** + * @brief Configure the UART work in rs485_half_duplex mode. + * + * @param hw Beginning address of the peripheral registers. + * + * @return None. + */ +FORCE_INLINE_ATTR void uart_ll_set_mode_rs485_half_duplex(uart_dev_t *hw) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // // This function is only for HP_UART use + // // LP_UART can only work in normal mode + // // lp_uart_dev_t has no following fields (reserved), but no harm since we map the LP_UART instance to the uart_dev_t struct + // // // Enable receiver, sw_rts = 1 generates low level on RTS pin + // hw->conf0_sync.sw_rts = 1; + // // Half duplex mode + // hw->rs485_conf_sync.rs485tx_rx_en = 0; + // // Setting this bit will allow data to be transmitted while receiving data(full-duplex mode). + // // But note that this full-duplex mode has no conflict detection function + // hw->rs485_conf_sync.rs485rxby_tx_en = 0; + // hw->conf0_sync.irda_en = 0; + // hw->rs485_conf_sync.dl0_en = 1; + // hw->rs485_conf_sync.dl1_en = 1; + // hw->rs485_conf_sync.rs485_en = 1; + // uart_ll_update(hw); +} + +/** + * @brief Configure the UART work in collision_detect mode. + * + * @param hw Beginning address of the peripheral registers. + * + * @return None. + */ +FORCE_INLINE_ATTR void uart_ll_set_mode_collision_detect(uart_dev_t *hw) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // // This function is only for HP_UART use + // // LP_UART can only work in normal mode + // // lp_uart_dev_t has no following fields (reserved), but no harm since we map the LP_UART instance to the uart_dev_t struct + // // hw->conf0_sync.irda_en = 0; + // // Enable full-duplex mode + // hw->rs485_conf_sync.rs485tx_rx_en = 1; + // // Transmitter should send data when the receiver is busy, + // hw->rs485_conf_sync.rs485rxby_tx_en = 1; + // hw->rs485_conf_sync.dl0_en = 1; + // hw->rs485_conf_sync.dl1_en = 1; + // hw->conf0_sync.sw_rts = 0; + // hw->rs485_conf_sync.rs485_en = 1; + // uart_ll_update(hw); +} + +/** + * @brief Configure the UART work in irda mode. + * + * @param hw Beginning address of the peripheral registers. + * + * @return None. + */ +FORCE_INLINE_ATTR void uart_ll_set_mode_irda(uart_dev_t *hw) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // // This function is only for HP_UART use + // // LP_UART can only work in normal mode + // // lp_uart_dev_t has no following fields (reserved), but no harm since we map the LP_UART instance to the uart_dev_t struct + // // hw->rs485_conf_sync.rs485_en = 0; + // hw->rs485_conf_sync.rs485tx_rx_en = 0; + // hw->rs485_conf_sync.rs485rxby_tx_en = 0; + // hw->conf0_sync.sw_rts = 0; + // hw->conf0_sync.irda_en = 1; + // uart_ll_update(hw); +} + +/** + * @brief Set uart mode. + * + * @param hw Beginning address of the peripheral registers. + * @param mode The UART mode to be set. + * + * @return None. + */ +FORCE_INLINE_ATTR void uart_ll_set_mode(uart_dev_t *hw, uart_mode_t mode) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // switch (mode) { + // default: + // case UART_MODE_UART: + // uart_ll_set_mode_normal(hw); + // break; + // case UART_MODE_RS485_COLLISION_DETECT: + // // Only HP_UART support this mode + // uart_ll_set_mode_collision_detect(hw); + // break; + // case UART_MODE_RS485_APP_CTRL: + // // Only HP_UART support this mode + // uart_ll_set_mode_rs485_app_ctrl(hw); + // break; + // case UART_MODE_RS485_HALF_DUPLEX: + // // Only HP_UART support this mode + // uart_ll_set_mode_rs485_half_duplex(hw); + // break; + // case UART_MODE_IRDA: + // // Only HP_UART support this mode + // uart_ll_set_mode_irda(hw); + // break; + // } +} + +/** + * @brief Get the UART AT cmd char configuration. + * + * @param hw Beginning address of the peripheral registers. + * @param cmd_char The Pointer to accept value of UART AT cmd char. + * @param char_num Pointer to accept the repeat number of UART AT cmd char. + * + * @return None. + */ +FORCE_INLINE_ATTR void uart_ll_get_at_cmd_char(uart_dev_t *hw, uint8_t *cmd_char, uint8_t *char_num) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // *cmd_char = HAL_FORCE_READ_U32_REG_FIELD(hw->at_cmd_char_sync, data); + // *char_num = HAL_FORCE_READ_U32_REG_FIELD(hw->at_cmd_char_sync, char_num); +} + +/** + * @brief Get the UART wakeup threshold value. + * + * @param hw Beginning address of the peripheral registers. + * + * @return The UART wakeup threshold value. + */ +FORCE_INLINE_ATTR uint32_t uart_ll_get_wakeup_thrd(uart_dev_t *hw) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // return hw->sleep_conf2.active_threshold + UART_LL_MIN_WAKEUP_THRESH; + return (uint32_t)0; +} + +/** + * @brief Get the UART data bit configuration. + * + * @param hw Beginning address of the peripheral registers. + * @param data_bit The pointer to accept the UART data bit configuration. + * + * @return The bit mode. + */ +FORCE_INLINE_ATTR void uart_ll_get_data_bit_num(uart_dev_t *hw, uart_word_length_t *data_bit) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // *data_bit = (uart_word_length_t)hw->conf0_sync.bit_num; +} + +/** + * @brief Check if the UART sending state machine is in the IDLE state. + * + * @param hw Beginning address of the peripheral registers. + * + * @return True if the state machine is in the IDLE state, otherwise false is returned. + */ +FORCE_INLINE_ATTR bool uart_ll_is_tx_idle(uart_dev_t *hw) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // return ((((hw->status.txfifo_cnt) >> UART_LL_REG_FIELD_BIT_SHIFT(hw)) == 0) && (hw->fsm_status.st_utx_out == 0)); + return (bool)0; +} + +/** + * @brief Check if the UART rts flow control is enabled. + * + * @param hw Beginning address of the peripheral registers. + * + * @return True if hw rts flow control is enabled, otherwise false is returned. + */ +FORCE_INLINE_ATTR bool uart_ll_is_hw_rts_en(uart_dev_t *hw) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // return hw->hwfc_conf_sync.rx_flow_en; + return (bool)0; +} + +/** + * @brief Check if the UART cts flow control is enabled. + * + * @param hw Beginning address of the peripheral registers. + * + * @return True if hw cts flow control is enabled, otherwise false is returned. + */ +FORCE_INLINE_ATTR bool uart_ll_is_hw_cts_en(uart_dev_t *hw) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // return hw->conf0_sync.tx_flow_en; + return (bool)0; +} + +/** + * @brief Configure TX signal loop back to RX module, just for the testing purposes + * + * @param hw Beginning address of the peripheral registers. + * @param loop_back_en Set ture to enable the loop back function, else set it false. + * + * @return None + */ +FORCE_INLINE_ATTR void uart_ll_set_loop_back(uart_dev_t *hw, bool loop_back_en) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // hw->conf0_sync.loopback = loop_back_en; + // uart_ll_update(hw); +} + +FORCE_INLINE_ATTR void uart_ll_xon_force_on(uart_dev_t *hw, bool always_on) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // hw->swfc_conf0_sync.force_xon = 1; + // uart_ll_update(hw); + // if (!always_on) { + // hw->swfc_conf0_sync.force_xon = 0; + // uart_ll_update(hw); + // } +} + +/** + * @brief Inverse the UART signal with the given mask. + * + * @param hw Beginning address of the peripheral registers. + * @param inv_mask The UART signal bitmap needs to be inversed. + * Use the ORred mask of `uart_signal_inv_t`; + * + * @return None. + */ +FORCE_INLINE_ATTR void uart_ll_inverse_signal(uart_dev_t *hw, uint32_t inv_mask) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // // LP_UART does not support UART_SIGNAL_IRDA_TX_INV and UART_SIGNAL_IRDA_RX_INV + // // lp_uart_dev_t has no these fields (reserved), but no harm since we map the LP_UART instance to the uart_dev_t struct + // // typeof(hw->conf0_sync) conf0_reg; + // conf0_reg.val = hw->conf0_sync.val; + // conf0_reg.irda_tx_inv = (inv_mask & UART_SIGNAL_IRDA_TX_INV) ? 1 : 0; + // conf0_reg.irda_rx_inv = (inv_mask & UART_SIGNAL_IRDA_RX_INV) ? 1 : 0; + // conf0_reg.rxd_inv = (inv_mask & UART_SIGNAL_RXD_INV) ? 1 : 0; + // conf0_reg.txd_inv = (inv_mask & UART_SIGNAL_TXD_INV) ? 1 : 0; + // hw->conf0_sync.val = conf0_reg.val; + // // typeof(hw->conf1) conf1_reg; + // conf1_reg.val = hw->conf1.val; + // conf1_reg.rts_inv = (inv_mask & UART_SIGNAL_RTS_INV) ? 1 : 0; + // conf1_reg.dtr_inv = (inv_mask & UART_SIGNAL_DTR_INV) ? 1 : 0; + // conf1_reg.cts_inv = (inv_mask & UART_SIGNAL_CTS_INV) ? 1 : 0; + // conf1_reg.dsr_inv = (inv_mask & UART_SIGNAL_DSR_INV) ? 1 : 0; + // hw->conf1.val = conf1_reg.val; + // uart_ll_update(hw); +} + +/** + * @brief Configure the timeout value for receiver receiving a byte, and enable rx timeout function. + * + * @param hw Beginning address of the peripheral registers. + * @param tout_thrd The timeout value as UART bit time. The rx timeout function will be disabled if `tout_thrd == 0`. + * + * @return None. + */ +FORCE_INLINE_ATTR void uart_ll_set_rx_tout(uart_dev_t *hw, uint16_t tout_thrd) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // uint16_t tout_val = tout_thrd; + // if (tout_thrd > 0) { + // hw->tout_conf_sync.rx_tout_thrhd = tout_val; + // hw->tout_conf_sync.rx_tout_en = 1; + // } else { + // hw->tout_conf_sync.rx_tout_en = 0; + // } + // uart_ll_update(hw); +} + +/** + * @brief Get the timeout value for receiver receiving a byte. + * + * @param hw Beginning address of the peripheral registers. + * + * @return tout_thr The timeout threshold value. If timeout feature is disabled returns 0. + */ +FORCE_INLINE_ATTR uint16_t uart_ll_get_rx_tout_thr(uart_dev_t *hw) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // uint16_t tout_thrd = 0; + // if (hw->tout_conf_sync.rx_tout_en > 0) { + // tout_thrd = hw->tout_conf_sync.rx_tout_thrhd; + // } + // return tout_thrd; + return (uint16_t)0; +} + +/** + * @brief Get UART maximum timeout threshold. + * + * @param hw Beginning address of the peripheral registers. + * + * @return maximum timeout threshold. + */ +FORCE_INLINE_ATTR uint16_t uart_ll_max_tout_thrd(uart_dev_t *hw) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // return ((hw) == &LP_UART) ? LP_UART_RX_TOUT_THRHD_V : UART_RX_TOUT_THRHD_V; + return (uint16_t)0; +} + +/** + * @brief Configure the auto baudrate. + * + * @param hw Beginning address of the peripheral registers. + * @param enable Boolean marking whether the auto baudrate should be enabled or not. + */ +FORCE_INLINE_ATTR void uart_ll_set_autobaud_en(uart_dev_t *hw, bool enable) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // // LP_UART does not support autobaud + // // lp_uart_dev_t has no following fields (reserved), but no harm since we map the LP_UART instance to the uart_dev_t struct + // // hw->conf0_sync.autobaud_en = enable ? 1 : 0; + // uart_ll_update(hw); +} + +/** + * @brief Get the RXD edge count. + * + * @param hw Beginning address of the peripheral registers. + */ +FORCE_INLINE_ATTR uint32_t uart_ll_get_rxd_edge_cnt(uart_dev_t *hw) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // // LP_UART does not support this feature + // // lp_uart_dev_t has no following fields (reserved), but no harm since we map the LP_UART instance to the uart_dev_t struct + // // return hw->rxd_cnt.rxd_edge_cnt; + return (uint32_t)0; +} + +/** + * @brief Get the positive pulse minimum count. + * + * @param hw Beginning address of the peripheral registers. + */ +FORCE_INLINE_ATTR uint32_t uart_ll_get_pos_pulse_cnt(uart_dev_t *hw) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // // LP_UART does not support this feature + // // lp_uart_dev_t has no following fields (reserved), but no harm since we map the LP_UART instance to the uart_dev_t struct + // // return hw->pospulse.posedge_min_cnt; + return (uint32_t)0; +} + +/** + * @brief Get the negative pulse minimum count. + * + * @param hw Beginning address of the peripheral registers. + */ +FORCE_INLINE_ATTR uint32_t uart_ll_get_neg_pulse_cnt(uart_dev_t *hw) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // // LP_UART does not support this feature + // // lp_uart_dev_t has no following fields (reserved), but no harm since we map the LP_UART instance to the uart_dev_t struct + // // return hw->negpulse.negedge_min_cnt; + return (uint32_t)0; +} + +/** + * @brief Get the high pulse minimum count. + * + * @param hw Beginning address of the peripheral registers. + */ +FORCE_INLINE_ATTR uint32_t uart_ll_get_high_pulse_cnt(uart_dev_t *hw) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // // LP_UART does not support this feature + // // lp_uart_dev_t has no following fields (reserved), but no harm since we map the LP_UART instance to the uart_dev_t struct + // // return hw->highpulse.highpulse_min_cnt; + return (uint32_t)0; +} + +/** + * @brief Get the low pulse minimum count. + * + * @param hw Beginning address of the peripheral registers. + */ +FORCE_INLINE_ATTR uint32_t uart_ll_get_low_pulse_cnt(uart_dev_t *hw) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // // LP_UART does not support this feature + // // lp_uart_dev_t has no following fields (reserved), but no harm since we map the LP_UART instance to the uart_dev_t struct + // // return hw->lowpulse.lowpulse_min_cnt; + return (uint32_t)0; +} + +/** + * @brief Force UART xoff. + * + * @param uart_num UART port number, the max port number is (UART_NUM_MAX -1). + * + * @return None. + */ +FORCE_INLINE_ATTR void uart_ll_force_xoff(uart_port_t uart_num) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // uart_dev_t *hw = UART_LL_GET_HW(uart_num); + // hw->swfc_conf0_sync.force_xon = 0; + // hw->swfc_conf0_sync.sw_flow_con_en = 1; + // hw->swfc_conf0_sync.force_xoff = 1; + // uart_ll_update(hw); +} + +/** + * @brief Force UART xon. + * + * @param uart_num UART port number, the max port number is (UART_NUM_MAX -1). + * + * @return None. + */ +FORCE_INLINE_ATTR void uart_ll_force_xon(uart_port_t uart_num) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // uart_dev_t *hw = UART_LL_GET_HW(uart_num); + // hw->swfc_conf0_sync.force_xoff = 0; + // hw->swfc_conf0_sync.force_xon = 1; + // hw->swfc_conf0_sync.sw_flow_con_en = 0; + // hw->swfc_conf0_sync.force_xon = 0; + // uart_ll_update(hw); +} + +/** + * @brief Get UART finite-state machine status. + * + * @param uart_num UART port number, the max port number is (UART_NUM_MAX -1). + * + * @return UART module FSM status. + */ +FORCE_INLINE_ATTR uint32_t uart_ll_get_tx_fsm_status(uart_port_t uart_num) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // uart_dev_t *hw = UART_LL_GET_HW(uart_num); + // return hw->fsm_status.st_utx_out; + return (uint32_t)0; +} + +/** + * @brief Configure UART whether to discard when receiving wrong data + * + * @param hw Beginning address of the peripheral registers. + * @param discard true: Receiver stops storing data into FIFO when data is wrong + * false: Receiver continue storing data into FIFO when data is wrong + */ +FORCE_INLINE_ATTR void uart_ll_discard_error_data(uart_dev_t *hw, bool discard) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // hw->conf0_sync.err_wr_mask = discard ? 1 : 0; + // uart_ll_update(hw); +} + +#ifdef __cplusplus +} +#endif diff --git a/components/riscv/include/riscv/rv_utils.h b/components/riscv/include/riscv/rv_utils.h index 23f65db3f6e7..9048f52785e5 100644 --- a/components/riscv/include/riscv/rv_utils.h +++ b/components/riscv/include/riscv/rv_utils.h @@ -134,6 +134,9 @@ FORCE_INLINE_ATTR void rv_utils_set_mtvec(uint32_t mtvec_val) #if CONFIG_IDF_TARGET_ESP32P4 // As per CLIC specs, mintstatus CSR should be at 0xFB1, however esp32p4 implements it at 0x346 #define MINTSTATUS 0x346 +#elif CONFIG_IDF_TARGET_ESP32C5 + // TODO: [ESP32C5] IDF-8654, IDF-8655 (inherit from P4) Check the correctness + #define MINTSTATUS 0x346 #else #error "rv_utils_get_mintstatus() is not implemented. Check for correct mintstatus register address." #endif /* CONFIG_IDF_TARGET_ESP32P4 */ diff --git a/components/soc/esp32c2/include/soc/soc_caps.h b/components/soc/esp32c2/include/soc/soc_caps.h index 15b026dd3b13..88a34bdfde0c 100644 --- a/components/soc/esp32c2/include/soc/soc_caps.h +++ b/components/soc/esp32c2/include/soc/soc_caps.h @@ -4,11 +4,6 @@ * SPDX-License-Identifier: Apache-2.0 */ -// The long term plan is to have a single soc_caps.h for each peripheral. -// During the refactoring and multichip support development process, we -// seperate these information into periph_caps.h for each peripheral and -// include them here. - /* * These defines are parsed and imported as kconfig variables via the script * `tools/gen_soc_caps_kconfig/gen_soc_caps_kconfig.py` diff --git a/components/soc/esp32c3/include/soc/soc_caps.h b/components/soc/esp32c3/include/soc/soc_caps.h index bf11ccdf0a10..0d8d988c7e71 100644 --- a/components/soc/esp32c3/include/soc/soc_caps.h +++ b/components/soc/esp32c3/include/soc/soc_caps.h @@ -4,11 +4,6 @@ * SPDX-License-Identifier: Apache-2.0 */ -// The long term plan is to have a single soc_caps.h for each peripheral. -// During the refactoring and multichip support development process, we -// seperate these information into periph_caps.h for each peripheral and -// include them here. - /* * These defines are parsed and imported as kconfig variables via the script * `tools/gen_soc_caps_kconfig/gen_soc_caps_kconfig.py` diff --git a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in new file mode 100644 index 000000000000..bf54e30ab722 --- /dev/null +++ b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in @@ -0,0 +1,48 @@ +##################################################### +# This file is auto-generated from SoC caps +# using gen_soc_caps_kconfig.py, do not edit manually +##################################################### + +config SOC_INT_HW_NESTED_SUPPORTED + bool + default y + +config SOC_CPU_CORES_NUM + int + default 1 + +config SOC_INT_CLIC_SUPPORTED + bool + default y + +config SOC_GPIO_PIN_COUNT + int + default 31 + +config SOC_SPI_PERIPH_NUM + int + default 2 + +config SOC_SPI_MAX_CS_NUM + int + default 6 + +config SOC_TIMER_GROUPS + int + default 2 + +config SOC_TIMER_GROUP_TIMERS_PER_GROUP + int + default 1 + +config SOC_UART_NUM + int + default 3 + +config SOC_UART_HP_NUM + int + default 2 + +config SOC_UART_LP_NUM + int + default 1 diff --git a/components/soc/esp32c5/include/soc/apb_saradc_reg.h b/components/soc/esp32c5/include/soc/apb_saradc_reg.h index 27bb876c35b6..179fe6a7d6ee 100644 --- a/components/soc/esp32c5/include/soc/apb_saradc_reg.h +++ b/components/soc/esp32c5/include/soc/apb_saradc_reg.h @@ -14,7 +14,7 @@ extern "C" { /** APB_SARADC_CTRL_REG register * digital saradc configure register */ -#define APB_SARADC_CTRL_REG (DR_REG_APB_BASE + 0x0) +#define APB_SARADC_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x0) /** APB_SARADC_SARADC_START_FORCE : R/W; bitpos: [0]; default: 0; * select software enable saradc sample */ @@ -82,7 +82,7 @@ extern "C" { /** APB_SARADC_CTRL2_REG register * digital saradc configure register */ -#define APB_SARADC_CTRL2_REG (DR_REG_APB_BASE + 0x4) +#define APB_SARADC_CTRL2_REG (DR_REG_APB_SARADC_BASE + 0x4) /** APB_SARADC_SARADC_MEAS_NUM_LIMIT : R/W; bitpos: [0]; default: 0; * enable max meas num */ @@ -129,7 +129,7 @@ extern "C" { /** APB_SARADC_FILTER_CTRL1_REG register * digital saradc configure register */ -#define APB_SARADC_FILTER_CTRL1_REG (DR_REG_APB_BASE + 0x8) +#define APB_SARADC_FILTER_CTRL1_REG (DR_REG_APB_SARADC_BASE + 0x8) /** APB_SARADC_APB_SARADC_FILTER_FACTOR1 : R/W; bitpos: [28:26]; default: 0; * Factor of saradc filter1 */ @@ -148,7 +148,7 @@ extern "C" { /** APB_SARADC_SAR_PATT_TAB1_REG register * digital saradc configure register */ -#define APB_SARADC_SAR_PATT_TAB1_REG (DR_REG_APB_BASE + 0x18) +#define APB_SARADC_SAR_PATT_TAB1_REG (DR_REG_APB_SARADC_BASE + 0x18) /** APB_SARADC_SARADC_SAR_PATT_TAB1 : R/W; bitpos: [23:0]; default: 16777215; * item 0 ~ 3 for pattern table 1 (each item one byte) */ @@ -160,7 +160,7 @@ extern "C" { /** APB_SARADC_SAR_PATT_TAB2_REG register * digital saradc configure register */ -#define APB_SARADC_SAR_PATT_TAB2_REG (DR_REG_APB_BASE + 0x1c) +#define APB_SARADC_SAR_PATT_TAB2_REG (DR_REG_APB_SARADC_BASE + 0x1c) /** APB_SARADC_SARADC_SAR_PATT_TAB2 : R/W; bitpos: [23:0]; default: 16777215; * Item 4 ~ 7 for pattern table 1 (each item one byte) */ @@ -172,7 +172,7 @@ extern "C" { /** APB_SARADC_ONETIME_SAMPLE_REG register * digital saradc configure register */ -#define APB_SARADC_ONETIME_SAMPLE_REG (DR_REG_APB_BASE + 0x20) +#define APB_SARADC_ONETIME_SAMPLE_REG (DR_REG_APB_SARADC_BASE + 0x20) /** APB_SARADC_SARADC_ONETIME_ATTEN : R/W; bitpos: [24:23]; default: 0; * configure onetime atten */ @@ -212,7 +212,7 @@ extern "C" { /** APB_SARADC_ARB_CTRL_REG register * digital saradc configure register */ -#define APB_SARADC_ARB_CTRL_REG (DR_REG_APB_BASE + 0x24) +#define APB_SARADC_ARB_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x24) /** APB_SARADC_ADC_ARB_APB_FORCE : R/W; bitpos: [2]; default: 0; * adc2 arbiter force to enableapb controller */ @@ -273,7 +273,7 @@ extern "C" { /** APB_SARADC_FILTER_CTRL0_REG register * digital saradc configure register */ -#define APB_SARADC_FILTER_CTRL0_REG (DR_REG_APB_BASE + 0x28) +#define APB_SARADC_FILTER_CTRL0_REG (DR_REG_APB_SARADC_BASE + 0x28) /** APB_SARADC_APB_SARADC_FILTER_CHANNEL1 : R/W; bitpos: [21:18]; default: 13; * configure filter1 to adc channel */ @@ -299,7 +299,7 @@ extern "C" { /** APB_SARADC_SAR1DATA_STATUS_REG register * digital saradc configure register */ -#define APB_SARADC_SAR1DATA_STATUS_REG (DR_REG_APB_BASE + 0x2c) +#define APB_SARADC_SAR1DATA_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x2c) /** APB_SARADC_APB_SARADC1_DATA : RO; bitpos: [16:0]; default: 0; * saradc1 data */ @@ -311,7 +311,7 @@ extern "C" { /** APB_SARADC_SAR2DATA_STATUS_REG register * digital saradc configure register */ -#define APB_SARADC_SAR2DATA_STATUS_REG (DR_REG_APB_BASE + 0x30) +#define APB_SARADC_SAR2DATA_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x30) /** APB_SARADC_APB_SARADC2_DATA : RO; bitpos: [16:0]; default: 0; * saradc2 data */ @@ -323,7 +323,7 @@ extern "C" { /** APB_SARADC_THRES0_CTRL_REG register * digital saradc configure register */ -#define APB_SARADC_THRES0_CTRL_REG (DR_REG_APB_BASE + 0x34) +#define APB_SARADC_THRES0_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x34) /** APB_SARADC_APB_SARADC_THRES0_CHANNEL : R/W; bitpos: [3:0]; default: 13; * configure thres0 to adc channel */ @@ -349,7 +349,7 @@ extern "C" { /** APB_SARADC_THRES1_CTRL_REG register * digital saradc configure register */ -#define APB_SARADC_THRES1_CTRL_REG (DR_REG_APB_BASE + 0x38) +#define APB_SARADC_THRES1_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x38) /** APB_SARADC_APB_SARADC_THRES1_CHANNEL : R/W; bitpos: [3:0]; default: 13; * configure thres1 to adc channel */ @@ -375,7 +375,7 @@ extern "C" { /** APB_SARADC_THRES_CTRL_REG register * digital saradc configure register */ -#define APB_SARADC_THRES_CTRL_REG (DR_REG_APB_BASE + 0x3c) +#define APB_SARADC_THRES_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x3c) /** APB_SARADC_APB_SARADC_THRES_ALL_EN : R/W; bitpos: [27]; default: 0; * enable thres to all channel */ @@ -401,7 +401,7 @@ extern "C" { /** APB_SARADC_INT_ENA_REG register * digital saradc int register */ -#define APB_SARADC_INT_ENA_REG (DR_REG_APB_BASE + 0x40) +#define APB_SARADC_INT_ENA_REG (DR_REG_APB_SARADC_BASE + 0x40) /** APB_SARADC_APB_SARADC_TSENS_INT_ENA : R/W; bitpos: [25]; default: 0; * tsens low interrupt enable */ @@ -455,7 +455,7 @@ extern "C" { /** APB_SARADC_INT_RAW_REG register * digital saradc int register */ -#define APB_SARADC_INT_RAW_REG (DR_REG_APB_BASE + 0x44) +#define APB_SARADC_INT_RAW_REG (DR_REG_APB_SARADC_BASE + 0x44) /** APB_SARADC_APB_SARADC_TSENS_INT_RAW : R/WTC/SS; bitpos: [25]; default: 0; * saradc tsens interrupt raw */ @@ -509,7 +509,7 @@ extern "C" { /** APB_SARADC_INT_ST_REG register * digital saradc int register */ -#define APB_SARADC_INT_ST_REG (DR_REG_APB_BASE + 0x48) +#define APB_SARADC_INT_ST_REG (DR_REG_APB_SARADC_BASE + 0x48) /** APB_SARADC_APB_SARADC_TSENS_INT_ST : RO; bitpos: [25]; default: 0; * saradc tsens interrupt state */ @@ -563,7 +563,7 @@ extern "C" { /** APB_SARADC_INT_CLR_REG register * digital saradc int register */ -#define APB_SARADC_INT_CLR_REG (DR_REG_APB_BASE + 0x4c) +#define APB_SARADC_INT_CLR_REG (DR_REG_APB_SARADC_BASE + 0x4c) /** APB_SARADC_APB_SARADC_TSENS_INT_CLR : WT; bitpos: [25]; default: 0; * saradc tsens interrupt clear */ @@ -617,7 +617,7 @@ extern "C" { /** APB_SARADC_DMA_CONF_REG register * digital saradc configure register */ -#define APB_SARADC_DMA_CONF_REG (DR_REG_APB_BASE + 0x50) +#define APB_SARADC_DMA_CONF_REG (DR_REG_APB_SARADC_BASE + 0x50) /** APB_SARADC_APB_ADC_EOF_NUM : R/W; bitpos: [15:0]; default: 255; * the dma_in_suc_eof gen when sample cnt = spi_eof_num */ @@ -643,7 +643,7 @@ extern "C" { /** APB_SARADC_CLKM_CONF_REG register * digital saradc configure register */ -#define APB_SARADC_CLKM_CONF_REG (DR_REG_APB_BASE + 0x54) +#define APB_SARADC_CLKM_CONF_REG (DR_REG_APB_SARADC_BASE + 0x54) /** APB_SARADC_CLKM_DIV_NUM : R/W; bitpos: [7:0]; default: 4; * Integral I2S clock divider value */ @@ -683,7 +683,7 @@ extern "C" { /** APB_SARADC_APB_TSENS_CTRL_REG register * digital tsens configure register */ -#define APB_SARADC_APB_TSENS_CTRL_REG (DR_REG_APB_BASE + 0x58) +#define APB_SARADC_APB_TSENS_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x58) /** APB_SARADC_TSENS_OUT : RO; bitpos: [7:0]; default: 128; * temperature sensor data out */ @@ -716,7 +716,7 @@ extern "C" { /** APB_SARADC_TSENS_CTRL2_REG register * digital tsens configure register */ -#define APB_SARADC_TSENS_CTRL2_REG (DR_REG_APB_BASE + 0x5c) +#define APB_SARADC_TSENS_CTRL2_REG (DR_REG_APB_SARADC_BASE + 0x5c) /** APB_SARADC_TSENS_CLK_SEL : R/W; bitpos: [15]; default: 0; * tsens clk select */ @@ -728,7 +728,7 @@ extern "C" { /** APB_SARADC_CALI_REG register * digital saradc configure register */ -#define APB_SARADC_CALI_REG (DR_REG_APB_BASE + 0x60) +#define APB_SARADC_CALI_REG (DR_REG_APB_SARADC_BASE + 0x60) /** APB_SARADC_APB_SARADC_CALI_CFG : R/W; bitpos: [16:0]; default: 32768; * saradc cali factor */ @@ -740,7 +740,7 @@ extern "C" { /** APB_TSENS_WAKE_REG register * digital tsens configure register */ -#define APB_TSENS_WAKE_REG (DR_REG_APB_BASE + 0x64) +#define APB_TSENS_WAKE_REG (DR_REG_APB_SARADC_BASE + 0x64) /** APB_SARADC_WAKEUP_TH_LOW : R/W; bitpos: [7:0]; default: 0; * reg_wakeup_th_low */ @@ -780,7 +780,7 @@ extern "C" { /** APB_TSENS_SAMPLE_REG register * digital tsens configure register */ -#define APB_TSENS_SAMPLE_REG (DR_REG_APB_BASE + 0x68) +#define APB_TSENS_SAMPLE_REG (DR_REG_APB_SARADC_BASE + 0x68) /** APB_SARADC_TSENS_SAMPLE_RATE : R/W; bitpos: [15:0]; default: 20; * HW sample rate */ @@ -799,7 +799,7 @@ extern "C" { /** APB_SARADC_CTRL_DATE_REG register * version */ -#define APB_SARADC_CTRL_DATE_REG (DR_REG_APB_BASE + 0x3fc) +#define APB_SARADC_CTRL_DATE_REG (DR_REG_APB_SARADC_BASE + 0x3fc) /** APB_SARADC_DATE : R/W; bitpos: [31:0]; default: 35676736; * version */ diff --git a/components/soc/esp32c5/include/soc/clic_reg.h b/components/soc/esp32c5/include/soc/clic_reg.h new file mode 100644 index 000000000000..1bfe74d623e6 --- /dev/null +++ b/components/soc/esp32c5/include/soc/clic_reg.h @@ -0,0 +1,108 @@ +/* + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +#define NLBITS 3 +#define CLIC_EXT_INTR_NUM_OFFSET 16 +#define DUALCORE_CLIC_CTRL_OFF 0x10000 + +#define DR_REG_CLIC_BASE ( 0x20800000 ) +#define DR_REG_CLIC_CTRL_BASE ( 0x20801000 ) + +#define CLIC_INT_CONFIG_REG (DR_REG_CLIC_BASE + 0x0) +/* CLIC_INT_CONFIG_NMBITS : R/W ;bitpos:[6:5] ;default: 2'd0 ; */ +/*description: .*/ +#define CLIC_INT_CONFIG_NMBITS 0x00000003 +#define CLIC_INT_CONFIG_NMBITS_M ((CLIC_INT_CONFIG_NMBITS_V)<<(CLIC_INT_CONFIG_NMBITS_S)) +#define CLIC_INT_CONFIG_NMBITS_V 0x3 +#define CLIC_INT_CONFIG_NMBITS_S 5 +/* CLIC_INT_CONFIG_NLBITS : R/W ;bitpos:[4:1] ;default: 4'd0 ; */ +/*description: .*/ +#define CLIC_INT_CONFIG_NLBITS 0x0000000F +#define CLIC_INT_CONFIG_NLBITS_M ((CLIC_INT_CONFIG_NLBITS_V)<<(CCLIC_INT_CONFIG_NLBITS_S)) +#define CLIC_INT_CONFIG_NLBITS_V 0xF +#define CLIC_INT_CONFIG_NLBITS_S 1 +/* CLIC_INT_CONFIG_NVBITS : R/W ;bitpos:[0] ;default: 1'd1 ; */ +/*description: .*/ +#define CLIC_INT_CONFIG_NVBITS (BIT(0)) +#define CLIC_INT_CONFIG_NVBITS_M (BIT(0)) +#define CLIC_INT_CONFIG_NVBITS_V 0x1 +#define CLIC_INT_CONFIG_NVBITS_S 0 + +#define CLIC_INT_INFO_REG (DR_REG_CLIC_BASE + 0x4) +/* CLIC_INT_INFO_NUM_INT : R/W ;bitpos:[24:21] ;default: 4'd0 ; */ +/*description: .*/ +#define CLIC_INT_INFO_CTLBITS 0x0000000F +#define CLIC_INT_INFO_CTLBITS_M ((CLIC_INT_INFO_CTLBITS_V)<<(CLIC_INT_INFO_CTLBITS_S)) +#define CLIC_INT_INFO_CTLBITS_V 0xF +#define CLIC_INT_INFO_CTLBITS_S 21 +/* CLIC_INT_INFO_VERSION : R/W ;bitpos:[20:13] ;default: 8'd0 ; */ +/*description: .*/ +#define CLIC_INT_INFO_VERSION 0x000000FF +#define CLIC_INT_INFO_VERSION_M ((CLIC_INT_INFO_VERSION_V)<<(CLIC_INT_INFO_VERSION_S)) +#define CLIC_INT_INFO_VERSION_V 0xFF +#define CLIC_INT_INFO_VERSION_S 13 +/* CLIC_INT_INFO_NUM_INT : R/W ;bitpos:[12:0] ;default: 13'd0 ; */ +/*description: .*/ +#define CLIC_INT_INFO_NUM_INT 0x00001FFF +#define CLIC_INT_INFO_NUM_INT_M ((CLIC_INT_INFO_NUM_INT_V)<<(CLIC_INT_INFO_NUM_INT_S)) +#define CLIC_INT_INFO_NUM_INT_V 0x1FFF +#define CLIC_INT_INFO_NUM_INT_S 0 + +#define CLIC_INT_THRESH_REG (DR_REG_CLIC_BASE + 0x8) +/* CLIC_CPU_INT_THRESH : R/W ;bitpos:[31:24] ;default: 8'd0 ; */ +/*description: .*/ +#define CLIC_CPU_INT_THRESH 0x000000FF +#define CLIC_CPU_INT_THRESH_M ((CLIC_CPU_INT_THRESH_V)<<(CLIC_CPU_INT_THRESH_S)) +#define CLIC_CPU_INT_THRESH_V 0xFF +#define CLIC_CPU_INT_THRESH_S 24 + +#define CLIC_INT_CTRL_REG(i) (DR_REG_CLIC_CTRL_BASE + (i) * 4) +/* CLIC_INT_CTL : R/W ;bitpos:[31:24] ;default: 8'd0 ; */ +/*description: .*/ +#define CLIC_INT_CTL 0x000000FF +#define CLIC_INT_CTL_M ((CLIC_INT_CTL_V)<<(CLIC_INT_CTL_S)) +#define CLIC_INT_CTL_V 0xFF +#define CLIC_INT_CTL_S 24 +/* CLIC_INT_ATTR_MODE : R/W ;bitpos:[23:22] ;default: 2'b11 ; */ +/*description: .*/ +#define CLIC_INT_ATTR_MODE 0x00000003 +#define CLIC_INT_ATTR_MODE_M ((CLIC_INT_ATTR_MODE_V)<<(CLIC_INT_ATTR_MODE_S)) +#define CLIC_INT_ATTR_MODE_V 0x3 +#define CLIC_INT_ATTR_MODE_S 22 +/* CLIC_INT_ATTR_TRIG : R/W ;bitpos:[18:17] ;default: 2'd0 ; */ +/*description: .*/ +#define CLIC_INT_ATTR_TRIG 0x00000003 +#define CLIC_INT_ATTR_TRIG_M ((CLIC_INT_ATTR_TRIG_V)<<(CLIC_INT_ATTR_TRIG_S)) +#define CLIC_INT_ATTR_TRIG_V 0x3 +#define CLIC_INT_ATTR_TRIG_S 17 +/* CLIC_INT_ATTR_SHV : R/W ;bitpos:[16] ;default: 1'd0 ; */ +/*description: .*/ +#define CLIC_INT_ATTR_SHV (BIT(16)) +#define CLIC_INT_ATTR_SHV_M (BIT(16)) +#define CLIC_INT_ATTR_SHV_V 0x1 +#define CLIC_INT_ATTR_SHV_S 16 +/* CLIC_INT_IE : R/W ;bitpos:[8] ;default: 1'd0 ; */ +/*description: .*/ +#define CLIC_INT_IE (BIT(8)) +#define CLIC_INT_IE_M (BIT(8)) +#define CLIC_INT_IE_V 0x1 +#define CLIC_INT_IE_S 8 +/* CLIC_INT_IP : R/W ;bitpos:[0] ;default: 1'd0 ; */ +/*description: .*/ +#define CLIC_INT_IP (BIT(0)) +#define CLIC_INT_IP_M (BIT(0)) +#define CLIC_INT_IP_V 0x1 +#define CLIC_INT_IP_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/clk_tree_defs.h b/components/soc/esp32c5/include/soc/clk_tree_defs.h new file mode 100644 index 000000000000..774122340047 --- /dev/null +++ b/components/soc/esp32c5/include/soc/clk_tree_defs.h @@ -0,0 +1,485 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +/* + ************************* ESP32C5 Root Clock Source **************************** + * 1) Internal 17.5MHz RC Oscillator: RC_FAST (may also referred as FOSC in TRM and reg. description) + * + * This RC oscillator generates a ~17.5MHz clock signal output as the RC_FAST_CLK. + * + * The exact frequency of RC_FAST_CLK can be computed in runtime through calibration. + * + * 2) External 40MHz Crystal Clock: XTAL + * + * 3) Internal 136kHz RC Oscillator: RC_SLOW (may also referrred as SOSC in TRM or reg. description) + * + * This RC oscillator generates a ~136kHz clock signal output as the RC_SLOW_CLK. The exact frequency of this clock + * can be computed in runtime through calibration. + * + * 4) Internal 32kHz RC Oscillator: RC32K + * + * The exact frequency of this clock can be computed in runtime through calibration. + * + * 5) External 32kHz Crystal Clock (optional): XTAL32K + * + * The clock source for this XTAL32K_CLK should be a 32kHz crystal connecting to the XTAL_32K_P and XTAL_32K_N + * pins. + * + * XTAL32K_CLK can also be calibrated to get its exact frequency. + * + * 6) External Slow Clock (optional): OSC_SLOW + * + * A slow clock signal generated by an external circuit can be connected to GPIO0 to be the clock source for the + * RTC_SLOW_CLK. + * + * OSC_SLOW_CLK can also be calibrated to get its exact frequency. + */ + +// TODO: [ESP32C5] IDF-8642 (inherit from C6) +/* With the default value of FOSC_DFREQ = 100, RC_FAST clock frequency is 17.5 MHz +/- 7% */ +#define SOC_CLK_RC_FAST_FREQ_APPROX 17500000 /*!< Approximate RC_FAST_CLK frequency in Hz */ +#define SOC_CLK_RC_SLOW_FREQ_APPROX 136000 /*!< Approximate RC_SLOW_CLK frequency in Hz */ +#define SOC_CLK_RC32K_FREQ_APPROX 32768 /*!< Approximate RC32K_CLK frequency in Hz */ +#define SOC_CLK_XTAL32K_FREQ_APPROX 32768 /*!< Approximate XTAL32K_CLK frequency in Hz */ +#define SOC_CLK_OSC_SLOW_FREQ_APPROX 32768 /*!< Approximate OSC_SLOW_CLK (external slow clock) frequency in Hz */ + +// Naming convention: SOC_ROOT_CLK_{loc}_{type}_[attr] +// {loc}: EXT, INT +// {type}: XTAL, RC +// [attr] - optional: [frequency], FAST, SLOW +/** + * @brief Root clock + */ +typedef enum { // TODO: [ESP32C5] IDF-8642 (inherit from C6) + SOC_ROOT_CLK_INT_RC_FAST, /*!< Internal 17.5MHz RC oscillator */ + SOC_ROOT_CLK_INT_RC_SLOW, /*!< Internal 136kHz RC oscillator */ + SOC_ROOT_CLK_EXT_XTAL, /*!< External 40MHz crystal */ + SOC_ROOT_CLK_EXT_XTAL32K, /*!< External 32kHz crystal */ + SOC_ROOT_CLK_INT_RC32K, /*!< Internal 32kHz RC oscillator */ + SOC_ROOT_CLK_EXT_OSC_SLOW, /*!< External slow clock signal at pin0 */ +} soc_root_clk_t; + +/** + * @brief CPU_CLK mux inputs, which are the supported clock sources for the CPU_CLK + * @note Enum values are matched with the register field values on purpose + */ +typedef enum { // TODO: [ESP32C5] IDF-8642 (inherit from C6) + SOC_CPU_CLK_SRC_XTAL = 0, /*!< Select XTAL_CLK as CPU_CLK source */ + SOC_CPU_CLK_SRC_PLL = 1, /*!< Select PLL_CLK as CPU_CLK source (PLL_CLK is the output of 40MHz crystal oscillator frequency multiplier, 480MHz) */ + SOC_CPU_CLK_SRC_RC_FAST = 2, /*!< Select RC_FAST_CLK as CPU_CLK source */ + SOC_CPU_CLK_SRC_INVALID, /*!< Invalid CPU_CLK source */ +} soc_cpu_clk_src_t; + +/** + * @brief RTC_SLOW_CLK mux inputs, which are the supported clock sources for the RTC_SLOW_CLK + * @note Enum values are matched with the register field values on purpose + */ +typedef enum { // TODO: [ESP32C5] IDF-8642 (inherit from C6) + SOC_RTC_SLOW_CLK_SRC_RC_SLOW = 0, /*!< Select RC_SLOW_CLK as RTC_SLOW_CLK source */ + SOC_RTC_SLOW_CLK_SRC_XTAL32K = 1, /*!< Select XTAL32K_CLK as RTC_SLOW_CLK source */ + SOC_RTC_SLOW_CLK_SRC_RC32K = 2, /*!< Select RC32K_CLK as RTC_SLOW_CLK source */ + SOC_RTC_SLOW_CLK_SRC_OSC_SLOW = 3, /*!< Select OSC_SLOW_CLK (external slow clock) as RTC_SLOW_CLK source */ + SOC_RTC_SLOW_CLK_SRC_INVALID, /*!< Invalid RTC_SLOW_CLK source */ +} soc_rtc_slow_clk_src_t; + +/** + * @brief RTC_FAST_CLK mux inputs, which are the supported clock sources for the RTC_FAST_CLK + * @note Enum values are matched with the register field values on purpose + */ +typedef enum { // TODO: [ESP32C5] IDF-8642 (inherit from C6) + SOC_RTC_FAST_CLK_SRC_RC_FAST = 0, /*!< Select RC_FAST_CLK as RTC_FAST_CLK source */ + SOC_RTC_FAST_CLK_SRC_XTAL_D2 = 1, /*!< Select XTAL_D2_CLK as RTC_FAST_CLK source */ + SOC_RTC_FAST_CLK_SRC_XTAL_DIV = SOC_RTC_FAST_CLK_SRC_XTAL_D2, /*!< Alias name for `SOC_RTC_FAST_CLK_SRC_XTAL_D2` */ + SOC_RTC_FAST_CLK_SRC_INVALID, /*!< Invalid RTC_FAST_CLK source */ +} soc_rtc_fast_clk_src_t; + +// Naming convention: SOC_MOD_CLK_{[upstream]clock_name}_[attr] +// {[upstream]clock_name}: XTAL, (BB)PLL, etc. +// [attr] - optional: FAST, SLOW, D, F +/** + * @brief Supported clock sources for modules (CPU, peripherals, RTC, etc.) + * + * @note enum starts from 1, to save 0 for special purpose + */ +typedef enum { // TODO: [ESP32C5] IDF-8642 (inherit from C6) + // For CPU domain + SOC_MOD_CLK_CPU = 1, /*!< CPU_CLK can be sourced from XTAL, PLL, or RC_FAST by configuring soc_cpu_clk_src_t */ + // For RTC domain + SOC_MOD_CLK_RTC_FAST, /*!< RTC_FAST_CLK can be sourced from XTAL_D2 or RC_FAST by configuring soc_rtc_fast_clk_src_t */ + SOC_MOD_CLK_RTC_SLOW, /*!< RTC_SLOW_CLK can be sourced from RC_SLOW, XTAL32K, RC32K, or OSC_SLOW by configuring soc_rtc_slow_clk_src_t */ + // For digital domain: peripherals, WIFI, BLE + SOC_MOD_CLK_PLL_F80M, /*!< PLL_F80M_CLK is derived from PLL (clock gating + fixed divider of 6), it has a fixed frequency of 80MHz */ + SOC_MOD_CLK_PLL_F160M, /*!< PLL_F160M_CLK is derived from PLL (clock gating + fixed divider of 3), it has a fixed frequency of 160MHz */ + SOC_MOD_CLK_PLL_F240M, /*!< PLL_F240M_CLK is derived from PLL (clock gating + fixed divider of 2), it has a fixed frequency of 240MHz */ + SOC_MOD_CLK_XTAL32K, /*!< XTAL32K_CLK comes from the external 32kHz crystal, passing a clock gating to the peripherals */ + SOC_MOD_CLK_RC_FAST, /*!< RC_FAST_CLK comes from the internal 20MHz rc oscillator, passing a clock gating to the peripherals */ + SOC_MOD_CLK_XTAL, /*!< XTAL_CLK comes from the external 40MHz crystal */ + // For LP peripherals + SOC_MOD_CLK_XTAL_D2, /*!< XTAL_D2_CLK comes from the external 40MHz crystal, passing a div of 2 to the LP peripherals */ + + SOC_MOD_CLK_INVALID, /*!< Indication of the end of the available module clock sources */ +} soc_module_clk_t; + +//////////////////////////////////////////////////SYSTIMER////////////////////////////////////////////////////////////// + +/** + * @brief Type of SYSTIMER clock source + */ +typedef enum { // TODO: [ESP32C5] IDF-8676 (inherit from C6) + SYSTIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< SYSTIMER source clock is XTAL */ + SYSTIMER_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< SYSTIMER source clock is RC_FAST */ + SYSTIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< SYSTIMER source clock default choice is XTAL */ +} soc_periph_systimer_clk_src_t; + +//////////////////////////////////////////////////GPTimer/////////////////////////////////////////////////////////////// + +/** + * @brief Array initializer for all supported clock sources of GPTimer + * + * The following code can be used to iterate all possible clocks: + * @code{c} + * soc_periph_gptimer_clk_src_t gptimer_clks[] = (soc_periph_gptimer_clk_src_t)SOC_GPTIMER_CLKS; + * for (size_t i = 0; i< sizeof(gptimer_clks) / sizeof(gptimer_clks[0]); i++) { + * soc_periph_gptimer_clk_src_t clk = gptimer_clks[i]; + * // Test GPTimer with the clock `clk` + * } + * @endcode + */ +#define SOC_GPTIMER_CLKS {SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_XTAL} + +/** + * @brief Type of GPTimer clock source + */ +typedef enum { // TODO: [ESP32C5] IDF-8705 (inherit from C6) + GPTIMER_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the source clock */ + GPTIMER_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */ + GPTIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ + GPTIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the default choice */ +} soc_periph_gptimer_clk_src_t; + +/** + * @brief Type of Timer Group clock source, reserved for the legacy timer group driver + */ +typedef enum { // TODO: [ESP32C5] IDF-8705 (inherit from C6) + TIMER_SRC_CLK_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Timer group clock source is PLL_F80M */ + TIMER_SRC_CLK_XTAL = SOC_MOD_CLK_XTAL, /*!< Timer group clock source is XTAL */ + TIMER_SRC_CLK_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Timer group clock source default choice is PLL_F80M */ +} soc_periph_tg_clk_src_legacy_t; + +//////////////////////////////////////////////////RMT/////////////////////////////////////////////////////////////////// + +/** + * @brief Array initializer for all supported clock sources of RMT + */ +#define SOC_RMT_CLKS {SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_XTAL} + +/** + * @brief Type of RMT clock source + */ +typedef enum { // TODO: [ESP32C5] IDF-8726 (inherit from C6) + RMT_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the source clock */ + RMT_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */ + RMT_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ + RMT_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the default choice */ +} soc_periph_rmt_clk_src_t; + +/** + * @brief Type of RMT clock source, reserved for the legacy RMT driver + */ +typedef enum { // TODO: [ESP32C5] IDF-8726 (inherit from C6) + RMT_BASECLK_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< RMT source clock is PLL_F80M */ + RMT_BASECLK_XTAL = SOC_MOD_CLK_XTAL, /*!< RMT source clock is XTAL */ + RMT_BASECLK_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< RMT source clock default choice is PLL_F80M */ +} soc_periph_rmt_clk_src_legacy_t; + +//////////////////////////////////////////////////Temp Sensor/////////////////////////////////////////////////////////// + +/** + * @brief Array initializer for all supported clock sources of Temperature Sensor + */ +#define SOC_TEMP_SENSOR_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST} + +/** + * @brief Type of Temp Sensor clock source + */ +typedef enum { // TODO: [ESP32C5] IDF-8727 (inherit from C6) + TEMPERATURE_SENSOR_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ + TEMPERATURE_SENSOR_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */ + TEMPERATURE_SENSOR_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default choice */ +} soc_periph_temperature_sensor_clk_src_t; + +///////////////////////////////////////////////////UART///////////////////////////////////////////////////////////////// + +/** + * @brief Type of UART clock source, reserved for the legacy UART driver + */ +typedef enum { // TODO: [ESP32C5] IDF-8722 (inherit from C6) + UART_SCLK_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< UART source clock is PLL_F80M */ + UART_SCLK_RTC = SOC_MOD_CLK_RC_FAST, /*!< UART source clock is RC_FAST */ + UART_SCLK_XTAL = SOC_MOD_CLK_XTAL, /*!< UART source clock is XTAL */ + UART_SCLK_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< UART source clock default choice is PLL_F80M */ +} soc_periph_uart_clk_src_legacy_t; + +/** + * @brief Type of LP_UART clock source + */ +typedef enum { // TODO: [ESP32C5] IDF-8633 (inherit from C6) + LP_UART_SCLK_LP_FAST = SOC_MOD_CLK_RTC_FAST, /*!< LP_UART source clock is LP(RTC)_FAST */ + LP_UART_SCLK_XTAL_D2 = SOC_MOD_CLK_XTAL_D2, /*!< LP_UART source clock is XTAL_D2 */ + LP_UART_SCLK_DEFAULT = SOC_MOD_CLK_RTC_FAST, /*!< LP_UART source clock default choice is LP(RTC)_FAST */ +} soc_periph_lp_uart_clk_src_t; + +//////////////////////////////////////////////////MCPWM///////////////////////////////////////////////////////////////// + +/** + * @brief Array initializer for all supported clock sources of MCPWM Timer + */ +#define SOC_MCPWM_TIMER_CLKS {SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_XTAL} + +/** + * @brief Type of MCPWM timer clock source + */ +typedef enum { // TODO: [ESP32C5] IDF-8709 (inherit from C6) + MCPWM_TIMER_CLK_SRC_PLL160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */ + MCPWM_TIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ + MCPWM_TIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default clock choice */ +} soc_periph_mcpwm_timer_clk_src_t; + +/** + * @brief Array initializer for all supported clock sources of MCPWM Capture Timer + */ +#define SOC_MCPWM_CAPTURE_CLKS {SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_XTAL} + +/** + * @brief Type of MCPWM capture clock source + */ +typedef enum { // TODO: [ESP32C5] IDF-8709 (inherit from C6) + MCPWM_CAPTURE_CLK_SRC_PLL160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */ + MCPWM_CAPTURE_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ + MCPWM_CAPTURE_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default clock choice */ +} soc_periph_mcpwm_capture_clk_src_t; + +/** + * @brief Array initializer for all supported clock sources of MCPWM Carrier + */ +#define SOC_MCPWM_CARRIER_CLKS {SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_XTAL} + +/** + * @brief Type of MCPWM carrier clock source + */ +typedef enum { // TODO: [ESP32C5] IDF-8709 (inherit from C6) + MCPWM_CARRIER_CLK_SRC_PLL160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */ + MCPWM_CARRIER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ + MCPWM_CARRIER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default clock choice */ +} soc_periph_mcpwm_carrier_clk_src_t; + +///////////////////////////////////////////////////// I2S ////////////////////////////////////////////////////////////// + +/** + * @brief Array initializer for all supported clock sources of I2S + */ +#define SOC_I2S_CLKS {SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_XTAL, I2S_CLK_SRC_EXTERNAL} + +/** + * @brief I2S clock source enum + */ +typedef enum { // TODO: [ESP32C5] IDF-8713 (inherit from C6) + I2S_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default source clock */ + I2S_CLK_SRC_PLL_160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */ + I2S_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ + I2S_CLK_SRC_EXTERNAL = -1, /*!< Select external clock as source clock */ +} soc_periph_i2s_clk_src_t; + +/////////////////////////////////////////////////I2C//////////////////////////////////////////////////////////////////// + +/** + * @brief Array initializer for all supported clock sources of I2C + */ +#define SOC_I2C_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST} + +/** + * @brief Type of I2C clock source. + */ +typedef enum { // TODO: [ESP32C5] IDF-8694, IDF-8696 (inherit from C6) + I2C_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ + I2C_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */ + I2C_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default source clock */ +} soc_periph_i2c_clk_src_t; + +///////////////////////////////////////////////LP_I2C/////////////////////////////////////////////////////////////////// + +/** + * @brief Array initializer for all supported clock sources of LP_I2C + */ +#define SOC_LP_I2C_CLKS {SOC_MOD_CLK_RTC_FAST, SOC_MOD_CLK_XTAL_D2} + +/** + * @brief Type of LP_I2C clock source. + */ +typedef enum { // TODO: [ESP32C5] IDF-8695 (inherit from C6) + LP_I2C_SCLK_LP_FAST = SOC_MOD_CLK_RTC_FAST, /*!< LP_I2C source clock is RTC_FAST */ + LP_I2C_SCLK_XTAL_D2 = SOC_MOD_CLK_XTAL_D2, /*!< LP_I2C source clock is XTAL_D2 */ + LP_I2C_SCLK_DEFAULT = SOC_MOD_CLK_RTC_FAST, /*!< LP_I2C source clock default choice is RTC_FAST */ +} soc_periph_lp_i2c_clk_src_t; + +/////////////////////////////////////////////////SPI//////////////////////////////////////////////////////////////////// + +/** + * @brief Array initializer for all supported clock sources of SPI + */ +#define SOC_SPI_CLKS {SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST} + +/** + * @brief Type of SPI clock source. + */ +typedef enum { // TODO: [ESP32C5] IDF-8698, IDF-8699 (inherit from C6) + SPI_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_80M as SPI source clock */ + SPI_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_80M as SPI source clock */ + SPI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as SPI source clock */ + SPI_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as SPI source clock */ +} soc_periph_spi_clk_src_t; + +//////////////////////////////////////////////////SDM////////////////////////////////////////////////////////////// + +/** + * @brief Array initializer for all supported clock sources of SDM + */ +#define SOC_SDM_CLKS {SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_XTAL} + +/** + * @brief Sigma Delta Modulator clock source + */ +typedef enum { // TODO: [ESP32C5] IDF-8687 (inherit from C6) + SDM_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL clock as the source clock */ + SDM_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the source clock */ + SDM_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the default clock choice */ +} soc_periph_sdm_clk_src_t; + +//////////////////////////////////////////////////GPIO Glitch Filter//////////////////////////////////////////////////// + +/** + * @brief Array initializer for all supported clock sources of Glitch Filter + */ +#define SOC_GLITCH_FILTER_CLKS {SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_XTAL} + +/** + * @brief Glitch filter clock source + */ + +typedef enum { // TODO: [ESP32C5] IDF-8718 (inherit from C6) + GLITCH_FILTER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL clock as the source clock */ + GLITCH_FILTER_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the source clock */ + GLITCH_FILTER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the default clock choice */ +} soc_periph_glitch_filter_clk_src_t; + +//////////////////////////////////////////////////TWAI////////////////////////////////////////////////////////////////// + +/** + * @brief Array initializer for all supported clock sources of TWAI + */ +#define SOC_TWAI_CLKS {SOC_MOD_CLK_XTAL} + +/** + * @brief TWAI clock source + */ +typedef enum { // TODO: [ESP32C5] IDF-8691, IDF-8692 (inherit from C6) + TWAI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ + TWAI_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default clock choice */ +} soc_periph_twai_clk_src_t; + +//////////////////////////////////////////////////ADC/////////////////////////////////////////////////////////////////// + +/** + * @brief Array initializer for all supported clock sources of ADC digital controller + */ +#define SOC_ADC_DIGI_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_RC_FAST} + +/** + * @brief ADC digital controller clock source + */ +typedef enum { // TODO: [ESP32C5] IDF-8701, IDF-8702, IDF-8703 (inherit from C6) + ADC_DIGI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ + ADC_DIGI_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the source clock */ + ADC_DIGI_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */ + ADC_DIGI_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the default clock choice */ +} soc_periph_adc_digi_clk_src_t; + +//////////////////////////////////////////////////MWDT///////////////////////////////////////////////////////////////// + +/** + * @brief Array initializer for all supported clock sources of MWDT + */ +#define SOC_MWDT_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_RC_FAST} + +/** + * @brief MWDT clock source + */ +typedef enum { // TODO: [ESP32C5] IDF-8650 (inherit from C6) + MWDT_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ + MWDT_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL fixed 80 MHz as the source clock */ + MWDT_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RTC fast as the source clock */ + MWDT_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select PLL fixed 80 MHz as the default clock choice */ +} soc_periph_mwdt_clk_src_t; + +//////////////////////////////////////////////////LEDC///////////////////////////////////////////////////////////////// + +/** + * @brief Array initializer for all supported clock sources of LEDC + */ +#define SOC_LEDC_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_RC_FAST} + +/** + * @brief Type of LEDC clock source, reserved for the legacy LEDC driver + */ +typedef enum { // TODO: [ESP32C5] IDF-8684 (inherit from C6) + LEDC_AUTO_CLK = 0, /*!< LEDC source clock will be automatically selected based on the giving resolution and duty parameter when init the timer*/ + LEDC_USE_PLL_DIV_CLK = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the source clock */ + LEDC_USE_RC_FAST_CLK = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */ + LEDC_USE_XTAL_CLK = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ + + LEDC_USE_RTC8M_CLK __attribute__((deprecated("please use 'LEDC_USE_RC_FAST_CLK' instead"))) = LEDC_USE_RC_FAST_CLK, /*!< Alias of 'LEDC_USE_RC_FAST_CLK' */ +} soc_periph_ledc_clk_src_legacy_t; + +//////////////////////////////////////////////////PARLIO//////////////////////////////////////////////////////////////// + +/** + * @brief Array initializer for all supported clock sources of PARLIO + */ +#define SOC_PARLIO_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_PLL_F240M} + +/** + * @brief PARLIO clock source + */ +typedef enum { // TODO: [ESP32C5] IDF-8685, IDF-8686 (inherit from C6) + PARLIO_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ + PARLIO_CLK_SRC_PLL_F240M = SOC_MOD_CLK_PLL_F240M, /*!< Select PLL_F240M as the source clock */ + PARLIO_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F240M, /*!< Select PLL_F240M as the default clock choice */ +} soc_periph_parlio_clk_src_t; + +//////////////////////////////////////////////CLOCK OUTPUT/////////////////////////////////////////////////////////// +typedef enum { // TODO: [ESP32C5] IDF-8642 (inherit from C6) + CLKOUT_SIG_PLL = 1, /*!< PLL_CLK is the output of crystal oscillator frequency multiplier */ + CLKOUT_SIG_XTAL = 5, /*!< Main crystal oscillator clock */ + CLKOUT_SIG_PLL_F80M = 13, /*!< From PLL, usually be 80MHz */ + CLKOUT_SIG_CPU = 16, /*!< CPU clock */ + CLKOUT_SIG_AHB = 17, /*!< AHB clock */ + CLKOUT_SIG_APB = 18, /*!< APB clock */ + CLKOUT_SIG_XTAL32K = 21, /*!< External 32kHz crystal clock */ + CLKOUT_SIG_EXT32K = 22, /*!< External slow clock input through XTAL_32K_P */ + CLKOUT_SIG_RC_FAST = 23, /*!< RC fast clock, about 17.5MHz */ + CLKOUT_SIG_RC_32K = 24, /*!< Internal slow RC oscillator */ + CLKOUT_SIG_RC_SLOW = 25, /*!< RC slow clock, depends on the RTC_CLK_SRC configuration */ + CLKOUT_SIG_INVALID = 0xFF, +} soc_clkout_sig_id_t; + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/dport_access.h b/components/soc/esp32c5/include/soc/dport_access.h new file mode 100644 index 000000000000..d5d1550b6077 --- /dev/null +++ b/components/soc/esp32c5/include/soc/dport_access.h @@ -0,0 +1,108 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include "soc.h" + +#ifdef __cplusplus +extern "C" { +#endif + +// Target does not have DPORT bus, so these macros are all same as the non-DPORT versions + +#define DPORT_INTERRUPT_DISABLE() +#define DPORT_INTERRUPT_RESTORE() + +/** + * @brief Read a sequence of DPORT registers to the buffer. + * + * @param[out] buff_out Contains the read data. + * @param[in] address Initial address for reading registers. + * @param[in] num_words The number of words. + */ +void esp_dport_access_read_buffer(uint32_t *buff_out, uint32_t address, uint32_t num_words); + +// _DPORT_REG_WRITE & DPORT_REG_WRITE are equivalent. +#define _DPORT_REG_READ(_r) (*(volatile uint32_t *)(_r)) +#define _DPORT_REG_WRITE(_r, _v) (*(volatile uint32_t *)(_r)) = (_v) + +// Write value to DPORT register (does not require protecting) +#define DPORT_REG_WRITE(_r, _v) _DPORT_REG_WRITE((_r), (_v)) + +#define DPORT_REG_READ(_r) _DPORT_REG_READ(_r) +#define DPORT_SEQUENCE_REG_READ(_r) _DPORT_REG_READ(_r) + +//get bit or get bits from register +#define DPORT_REG_GET_BIT(_r, _b) (DPORT_REG_READ(_r) & (_b)) + +//set bit or set bits to register +#define DPORT_REG_SET_BIT(_r, _b) DPORT_REG_WRITE((_r), (DPORT_REG_READ(_r)|(_b))) + +//clear bit or clear bits of register +#define DPORT_REG_CLR_BIT(_r, _b) DPORT_REG_WRITE((_r), (DPORT_REG_READ(_r) & (~(_b)))) + +//set bits of register controlled by mask +#define DPORT_REG_SET_BITS(_r, _b, _m) DPORT_REG_WRITE((_r), ((DPORT_REG_READ(_r) & (~(_m))) | ((_b) & (_m)))) + +//get field from register, uses field _S & _V to determine mask +#define DPORT_REG_GET_FIELD(_r, _f) ((DPORT_REG_READ(_r) >> (_f##_S)) & (_f##_V)) + +//set field to register, used when _f is not left shifted by _f##_S +#define DPORT_REG_SET_FIELD(_r, _f, _v) DPORT_REG_WRITE((_r), ((DPORT_REG_READ(_r) & (~((_f##_V) << (_f##_S))))|(((_v) & (_f##_V))<<(_f##_S)))) + +//get field value from a variable, used when _f is not left shifted by _f##_S +#define DPORT_VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f)) + +//get field value from a variable, used when _f is left shifted by _f##_S +#define DPORT_VALUE_GET_FIELD2(_r, _f) (((_r) & (_f))>> (_f##_S)) + +//set field value to a variable, used when _f is not left shifted by _f##_S +#define DPORT_VALUE_SET_FIELD(_r, _f, _v) ((_r)=(((_r) & ~((_f) << (_f##_S)))|((_v)<<(_f##_S)))) + +//set field value to a variable, used when _f is left shifted by _f##_S +#define DPORT_VALUE_SET_FIELD2(_r, _f, _v) ((_r)=(((_r) & ~(_f))|((_v)<<(_f##_S)))) + +//generate a value from a field value, used when _f is not left shifted by _f##_S +#define DPORT_FIELD_TO_VALUE(_f, _v) (((_v)&(_f))<<_f##_S) + +//generate a value from a field value, used when _f is left shifted by _f##_S +#define DPORT_FIELD_TO_VALUE2(_f, _v) (((_v)<<_f##_S) & (_f)) + +//Register read macros with an underscore prefix access DPORT memory directly. In IDF apps, use the non-underscore versions to be SMP-safe. +#define _DPORT_READ_PERI_REG(addr) (*((volatile uint32_t *)(addr))) +#define _DPORT_WRITE_PERI_REG(addr, val) (*((volatile uint32_t *)(addr))) = (uint32_t)(val) +#define _DPORT_REG_SET_BIT(_r, _b) _DPORT_REG_WRITE((_r), (_DPORT_REG_READ(_r)|(_b))) +#define _DPORT_REG_CLR_BIT(_r, _b) _DPORT_REG_WRITE((_r), (_DPORT_REG_READ(_r) & (~(_b)))) + +#define DPORT_READ_PERI_REG(addr) _DPORT_READ_PERI_REG(addr) + +//write value to register +#define DPORT_WRITE_PERI_REG(addr, val) _DPORT_WRITE_PERI_REG((addr), (val)) + +//clear bits of register controlled by mask +#define DPORT_CLEAR_PERI_REG_MASK(reg, mask) DPORT_WRITE_PERI_REG((reg), (DPORT_READ_PERI_REG(reg)&(~(mask)))) + +//set bits of register controlled by mask +#define DPORT_SET_PERI_REG_MASK(reg, mask) DPORT_WRITE_PERI_REG((reg), (DPORT_READ_PERI_REG(reg)|(mask))) + +//get bits of register controlled by mask +#define DPORT_GET_PERI_REG_MASK(reg, mask) (DPORT_READ_PERI_REG(reg) & (mask)) + +//get bits of register controlled by highest bit and lowest bit +#define DPORT_GET_PERI_REG_BITS(reg, hipos,lowpos) ((DPORT_READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1)) + +//set bits of register controlled by mask and shift +#define DPORT_SET_PERI_REG_BITS(reg,bit_map,value,shift) DPORT_WRITE_PERI_REG((reg), ((DPORT_READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & bit_map)<<(shift)))) + +//get field of register +#define DPORT_GET_PERI_REG_BITS2(reg, mask,shift) ((DPORT_READ_PERI_REG(reg)>>(shift))&(mask)) +//}} + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/efuse_struct.h b/components/soc/esp32c5/include/soc/efuse_struct.h index 56b2222b8349..56bdc22ca28c 100644 --- a/components/soc/esp32c5/include/soc/efuse_struct.h +++ b/components/soc/esp32c5/include/soc/efuse_struct.h @@ -431,11 +431,12 @@ typedef union { */ typedef union { struct { + // TODO: [ESP32C5] IDF-8674 (inherit from C6) seems an error in csv, need to check uint32_t reserved_0:24; /** reserved_0 : RO; bitpos: [31:24]; default: 0; * Reserved. */ - uint32_t reserved_0:8; + uint32_t reserved_24:8; }; uint32_t val; } efuse_rd_repeat_data4_reg_t; diff --git a/components/soc/esp32c5/include/soc/gpio_pins.h b/components/soc/esp32c5/include/soc/gpio_pins.h new file mode 100644 index 000000000000..b6d59de94cf1 --- /dev/null +++ b/components/soc/esp32c5/include/soc/gpio_pins.h @@ -0,0 +1,20 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +// TODO: [ESP32C5] IDF-8717 (inherit from C6) +#define GPIO_MATRIX_CONST_ONE_INPUT (0x3F) +#define GPIO_MATRIX_CONST_ZERO_INPUT (0x3E) + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/gpio_sig_map.h b/components/soc/esp32c5/include/soc/gpio_sig_map.h new file mode 100644 index 000000000000..b998fffc807f --- /dev/null +++ b/components/soc/esp32c5/include/soc/gpio_sig_map.h @@ -0,0 +1,177 @@ +/* + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define EXT_ADC_START_IDX 0 +#define LEDC_LS_SIG_OUT0_IDX 0 +#define LEDC_LS_SIG_OUT1_IDX 1 +#define LEDC_LS_SIG_OUT2_IDX 2 +#define LEDC_LS_SIG_OUT3_IDX 3 +#define LEDC_LS_SIG_OUT4_IDX 4 +#define LEDC_LS_SIG_OUT5_IDX 5 +#define U0RXD_IN_IDX 6 +#define U0TXD_OUT_IDX 6 +#define U0CTS_IN_IDX 7 +#define U0RTS_OUT_IDX 7 +#define U0DSR_IN_IDX 8 +#define U0DTR_OUT_IDX 8 +#define U1RXD_IN_IDX 9 +#define U1TXD_OUT_IDX 9 +#define U1CTS_IN_IDX 10 +#define U1RTS_OUT_IDX 10 +#define U1DSR_IN_IDX 11 +#define U1DTR_OUT_IDX 11 +#define I2S_MCLK_IN_IDX 12 +#define I2S_MCLK_OUT_IDX 12 +#define I2SO_BCK_IN_IDX 13 +#define I2SO_BCK_OUT_IDX 13 +#define I2SO_WS_IN_IDX 14 +#define I2SO_WS_OUT_IDX 14 +#define I2SI_SD_IN_IDX 15 +#define I2SO_SD_OUT_IDX 15 +#define I2SI_BCK_IN_IDX 16 +#define I2SI_BCK_OUT_IDX 16 +#define I2SI_WS_IN_IDX 17 +#define I2SI_WS_OUT_IDX 17 +#define I2SO_SD1_OUT_IDX 18 +#define USB_JTAG_TDO_BRIDGE_IDX 19 +#define USB_JTAG_TRST_IDX 19 +#define USB_OTG_32K_IN_IDX 21 +#define CPU_GPIO_IN0_IDX 28 +#define CPU_GPIO_OUT0_IDX 28 +#define CPU_GPIO_IN1_IDX 29 +#define CPU_GPIO_OUT1_IDX 29 +#define CPU_GPIO_IN2_IDX 30 +#define CPU_GPIO_OUT2_IDX 30 +#define CPU_GPIO_IN3_IDX 31 +#define CPU_GPIO_OUT3_IDX 31 +#define CPU_GPIO_IN4_IDX 32 +#define CPU_GPIO_OUT4_IDX 32 +#define CPU_GPIO_IN5_IDX 33 +#define CPU_GPIO_OUT5_IDX 33 +#define CPU_GPIO_IN6_IDX 34 +#define CPU_GPIO_OUT6_IDX 34 +#define CPU_GPIO_IN7_IDX 35 +#define CPU_GPIO_OUT7_IDX 35 +#define I2CEXT0_SCL_IN_IDX 45 +#define I2CEXT0_SCL_OUT_IDX 45 +#define I2CEXT0_SDA_IN_IDX 46 +#define I2CEXT0_SDA_OUT_IDX 46 +#define PARL_RX_DATA0_IDX 47 +#define PARL_TX_DATA0_IDX 47 +#define PARL_RX_DATA1_IDX 48 +#define PARL_TX_DATA1_IDX 48 +#define PARL_RX_DATA2_IDX 49 +#define PARL_TX_DATA2_IDX 49 +#define PARL_RX_DATA3_IDX 50 +#define PARL_TX_DATA3_IDX 50 +#define PARL_RX_DATA4_IDX 51 +#define PARL_TX_DATA4_IDX 51 +#define PARL_RX_DATA5_IDX 52 +#define PARL_TX_DATA5_IDX 52 +#define PARL_RX_DATA6_IDX 53 +#define PARL_TX_DATA6_IDX 53 +#define PARL_RX_DATA7_IDX 54 +#define PARL_TX_DATA7_IDX 54 +#define SDIO_TOHOST_INT_OUT_IDX 62 +#define FSPICLK_IN_IDX 63 +#define FSPICLK_OUT_MUX_IDX 63 +#define FSPIQ_IN_IDX 64 +#define FSPIQ_OUT_IDX 64 +#define FSPID_IN_IDX 65 +#define FSPID_OUT_IDX 65 +#define FSPIHD_IN_IDX 66 +#define FSPIHD_OUT_IDX 66 +#define FSPIWP_IN_IDX 67 +#define FSPIWP_OUT_IDX 67 +#define FSPICS0_IN_IDX 68 +#define FSPICS0_OUT_IDX 68 +#define PARL_RX_CLK_IN_IDX 69 +#define PARL_RX_CLK_OUT_IDX 69 +#define PARL_TX_CLK_IN_IDX 70 +#define PARL_TX_CLK_OUT_IDX 70 +#define RMT_SIG_IN0_IDX 71 +#define RMT_SIG_OUT0_IDX 71 +#define RMT_SIG_IN1_IDX 72 +#define RMT_SIG_OUT1_IDX 72 +#define TWAI0_RX_IDX 73 +#define TWAI0_TX_IDX 73 +#define TWAI0_BUS_OFF_ON_IDX 74 +#define TWAI0_CLKOUT_IDX 75 +#define TWAI0_STANDBY_IDX 76 +#define TWAI1_RX_IDX 77 +#define TWAI1_TX_IDX 77 +#define TWAI1_BUS_OFF_ON_IDX 78 +#define TWAI1_CLKOUT_IDX 79 +#define TWAI1_STANDBY_IDX 80 +#define PCNT_RST_IN0_IDX 83 +#define GPIO_SD0_OUT_IDX 83 +#define PCNT_RST_IN1_IDX 84 +#define GPIO_SD1_OUT_IDX 84 +#define PCNT_RST_IN2_IDX 85 +#define GPIO_SD2_OUT_IDX 85 +#define PCNT_RST_IN3_IDX 86 +#define GPIO_SD3_OUT_IDX 86 +#define PWM0_SYNC0_IN_IDX 87 +#define PWM0_OUT0A_IDX 87 +#define PWM0_SYNC1_IN_IDX 88 +#define PWM0_OUT0B_IDX 88 +#define PWM0_SYNC2_IN_IDX 89 +#define PWM0_OUT1A_IDX 89 +#define PWM0_F0_IN_IDX 90 +#define PWM0_OUT1B_IDX 90 +#define PWM0_F1_IN_IDX 91 +#define PWM0_OUT2A_IDX 91 +#define PWM0_F2_IN_IDX 92 +#define PWM0_OUT2B_IDX 92 +#define PWM0_CAP0_IN_IDX 93 +#define PWM0_CAP1_IN_IDX 94 +#define PWM0_CAP2_IN_IDX 95 +#define SIG_IN_FUNC_97_IDX 97 +#define SIG_IN_FUNC97_IDX 97 +#define SIG_IN_FUNC_98_IDX 98 +#define SIG_IN_FUNC98_IDX 98 +#define SIG_IN_FUNC_99_IDX 99 +#define SIG_IN_FUNC99_IDX 99 +#define SIG_IN_FUNC_100_IDX 100 +#define SIG_IN_FUNC100_IDX 100 +#define PCNT_SIG_CH0_IN0_IDX 101 +#define FSPICS1_OUT_IDX 101 +#define PCNT_SIG_CH1_IN0_IDX 102 +#define FSPICS2_OUT_IDX 102 +#define PCNT_CTRL_CH0_IN0_IDX 103 +#define FSPICS3_OUT_IDX 103 +#define PCNT_CTRL_CH1_IN0_IDX 104 +#define FSPICS4_OUT_IDX 104 +#define PCNT_SIG_CH0_IN1_IDX 105 +#define FSPICS5_OUT_IDX 105 +#define PCNT_SIG_CH1_IN1_IDX 106 +#define PCNT_CTRL_CH0_IN1_IDX 107 +#define PCNT_CTRL_CH1_IN1_IDX 108 +#define PCNT_SIG_CH0_IN2_IDX 109 +#define PCNT_SIG_CH1_IN2_IDX 110 +#define PCNT_CTRL_CH0_IN2_IDX 111 +#define PCNT_CTRL_CH1_IN2_IDX 112 +#define PCNT_SIG_CH0_IN3_IDX 113 +#define PCNT_SIG_CH1_IN3_IDX 114 +#define SPICLK_OUT_MUX_IDX 114 +#define PCNT_CTRL_CH0_IN3_IDX 115 +#define SPICS0_OUT_IDX 115 +#define PCNT_CTRL_CH1_IN3_IDX 116 +#define SPICS1_OUT_IDX 116 +#define SPIQ_IN_IDX 121 +#define SPIQ_OUT_IDX 121 +#define SPID_IN_IDX 122 +#define SPID_OUT_IDX 122 +#define SPIHD_IN_IDX 123 +#define SPIHD_OUT_IDX 123 +#define SPIWP_IN_IDX 124 +#define SPIWP_OUT_IDX 124 +#define CLK_OUT_OUT1_IDX 125 +#define CLK_OUT_OUT2_IDX 126 +#define CLK_OUT_OUT3_IDX 127 +#define GPIO_MAP_DATE_IDX 0x2301100 diff --git a/components/soc/esp32c5/include/soc/interrupt_matrix_reg.h b/components/soc/esp32c5/include/soc/interrupt_matrix_reg.h index f8d5d41bb5af..81c3db3d25b1 100644 --- a/components/soc/esp32c5/include/soc/interrupt_matrix_reg.h +++ b/components/soc/esp32c5/include/soc/interrupt_matrix_reg.h @@ -5,8 +5,8 @@ */ #pragma once -#include #include "soc/soc.h" + #ifdef __cplusplus extern "C" { #endif diff --git a/components/soc/esp32c5/include/soc/interrupt_reg.h b/components/soc/esp32c5/include/soc/interrupt_reg.h new file mode 100644 index 000000000000..c2ee2f9e2f68 --- /dev/null +++ b/components/soc/esp32c5/include/soc/interrupt_reg.h @@ -0,0 +1,22 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/reg_base.h" +#include "soc/interrupt_matrix_reg.h" +#include "soc/clic_reg.h" +#include "soc/soc_caps.h" + +/** + * ESP32C5 uses the CLIC controller as the interrupt controller (SOC_INT_CLIC_SUPPORTED = y) + * + * The memory map for interrupt registers is on a per-core basis, CLIC_INT_THRESH_REG points to + * the current core interrupt register, whereas CLIC_INT_THRESH_REG + DUALCORE_CLIC_CTRL_OFF points + * to the other core registers, regardless of the core we are currently running on. + */ +#define INTERRUPT_CURRENT_CORE_INT_THRESH_REG (CLIC_INT_THRESH_REG) +#define INTERRUPT_OTHER_CORE_INT_THRESH_REG (CLIC_INT_THRESH_REG + DUALCORE_CLIC_CTRL_OFF) + +#define INTERRUPT_CORE0_CPU_INT_THRESH_REG INTERRUPT_CURRENT_CORE_INT_THRESH_REG diff --git a/components/soc/esp32c5/include/soc/interrupts.h b/components/soc/esp32c5/include/soc/interrupts.h new file mode 100644 index 000000000000..c3fce3799701 --- /dev/null +++ b/components/soc/esp32c5/include/soc/interrupts.h @@ -0,0 +1,106 @@ +/* + * SPDX-FileCopyrightText: 2018-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once +#include + +#ifdef __cplusplus +extern "C" +{ +#endif + +// TODO: [ESP32C5] IDF-8654, IDF-8655 (inherit from C6) + +//Interrupt hardware source table +//This table is decided by hardware, don't touch this. +typedef enum { + ETS_WIFI_MAC_INTR_SOURCE = 0, /**< interrupt of WiFi MAC, level*/ + ETS_WIFI_MAC_NMI_SOURCE, /**< interrupt of WiFi MAC, NMI, use if MAC have bug to fix in NMI*/ + ETS_WIFI_PWR_INTR_SOURCE, /**< */ + ETS_WIFI_BB_INTR_SOURCE, /**< interrupt of WiFi BB, level, we can do some calibartion*/ + ETS_BT_MAC_INTR_SOURCE, /**< will be cancelled*/ + ETS_BT_BB_INTR_SOURCE, /**< interrupt of BT BB, level*/ + ETS_BT_BB_NMI_SOURCE, /**< interrupt of BT BB, NMI, use if BB have bug to fix in NMI*/ + ETS_LP_TIMER_INTR_SOURCE, + ETS_COEX_INTR_SOURCE, + ETS_BLE_TIMER_INTR_SOURCE, + ETS_BLE_SEC_INTR_SOURCE, + ETS_I2C_MASTER_SOURCE, /**< interrupt of I2C Master, level*/ + ETS_ZB_MAC_SOURCE, + ETS_PMU_INTR_SOURCE, + ETS_EFUSE_INTR_SOURCE, /**< interrupt of efuse, level, not likely to use*/ + ETS_LP_RTC_TIMER_INTR_SOURCE, + ETS_LP_UART_INTR_SOURCE, + ETS_LP_I2C_INTR_SOURCE, + ETS_LP_WDT_INTR_SOURCE, + ETS_LP_PERI_TIMEOUT_INTR_SOURCE, + ETS_LP_APM_M0_INTR_SOURCE, + ETS_LP_APM_M1_INTR_SOURCE, + ETS_FROM_CPU_INTR0_SOURCE, /**< interrupt0 generated from a CPU, level*/ /* Used for FreeRTOS */ + ETS_FROM_CPU_INTR1_SOURCE, /**< interrupt1 generated from a CPU, level*/ /* Used for FreeRTOS */ + ETS_FROM_CPU_INTR2_SOURCE, /**< interrupt2 generated from a CPU, level*/ + ETS_FROM_CPU_INTR3_SOURCE, /**< interrupt3 generated from a CPU, level*/ + ETS_ASSIST_DEBUG_INTR_SOURCE, /**< interrupt of Assist debug module, LEVEL*/ + ETS_TRACE_INTR_SOURCE, + ETS_CACHE_INTR_SOURCE, + ETS_CPU_PERI_TIMEOUT_INTR_SOURCE, + ETS_GPIO_INTR_SOURCE, /**< interrupt of GPIO, level*/ + ETS_GPIO_NMI_SOURCE, /**< interrupt of GPIO, NMI*/ + ETS_PAU_INTR_SOURCE, + ETS_HP_PERI_TIMEOUT_INTR_SOURCE, + ETS_MODEM_PERI_TIMEOUT_INTR_SOURCE, + ETS_HP_APM_M0_INTR_SOURCE, + ETS_HP_APM_M1_INTR_SOURCE, + ETS_HP_APM_M2_INTR_SOURCE, + ETS_HP_APM_M3_INTR_SOURCE, + ETS_LP_APM0_INTR_SOURCE, + ETS_MSPI_INTR_SOURCE, + ETS_I2S1_INTR_SOURCE, /**< interrupt of I2S1, level*/ + ETS_UHCI0_INTR_SOURCE, /**< interrupt of UHCI0, level*/ + ETS_UART0_INTR_SOURCE, /**< interrupt of UART0, level*/ + ETS_UART1_INTR_SOURCE, /**< interrupt of UART1, level*/ + ETS_LEDC_INTR_SOURCE, /**< interrupt of LED PWM, level*/ + ETS_TWAI0_INTR_SOURCE, /**< interrupt of twai0, level*/ + ETS_TWAI1_INTR_SOURCE, /**< interrupt of twai1, level*/ + ETS_USB_SERIAL_JTAG_INTR_SOURCE, /**< interrupt of USB, level*/ + ETS_RMT_INTR_SOURCE, /**< interrupt of remote controller, level*/ + ETS_I2C_EXT0_INTR_SOURCE, /**< interrupt of I2C controller1, level*/ + ETS_TG0_T0_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, TIMER0, level*/ + ETS_TG0_T1_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, TIMER1, level*/ + ETS_TG0_WDT_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, WATCH DOG, level*/ + ETS_TG1_T0_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, TIMER0, level*/ + ETS_TG1_T1_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, TIMER1, level*/ + ETS_TG1_WDT_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, WATCHDOG, level*/ + ETS_SYSTIMER_TARGET0_INTR_SOURCE, /**< interrupt of system timer 0 */ + ETS_SYSTIMER_TARGET1_INTR_SOURCE, /**< interrupt of system timer 1 */ + ETS_SYSTIMER_TARGET2_INTR_SOURCE, /**< interrupt of system timer 2 */ + ETS_SYSTIMER_TARGET0_EDGE_INTR_SOURCE = ETS_SYSTIMER_TARGET0_INTR_SOURCE, /**< use ETS_SYSTIMER_TARGET0_INTR_SOURCE */ + ETS_SYSTIMER_TARGET1_EDGE_INTR_SOURCE = ETS_SYSTIMER_TARGET1_INTR_SOURCE, /**< use ETS_SYSTIMER_TARGET1_INTR_SOURCE */ + ETS_SYSTIMER_TARGET2_EDGE_INTR_SOURCE = ETS_SYSTIMER_TARGET2_INTR_SOURCE, /**< use ETS_SYSTIMER_TARGET2_INTR_SOURCE */ + ETS_APB_ADC_INTR_SOURCE = 60, /**< interrupt of APB ADC, LEVEL*/ + ETS_MCPWM0_INTR_SOURCE, /**< interrupt of MCPWM0, LEVEL*/ + ETS_PCNT_INTR_SOURCE, + ETS_PARL_IO_INTR_SOURCE, + ETS_SLC0_INTR_SOURCE, + ETS_DMA_IN_CH0_INTR_SOURCE, /**< interrupt of general DMA IN channel 0, LEVEL*/ + ETS_DMA_IN_CH1_INTR_SOURCE, /**< interrupt of general DMA IN channel 1, LEVEL*/ + ETS_DMA_IN_CH2_INTR_SOURCE, /**< interrupt of general DMA IN channel 2, LEVEL*/ + ETS_DMA_OUT_CH0_INTR_SOURCE, /**< interrupt of general DMA OUT channel 0, LEVEL*/ + ETS_DMA_OUT_CH1_INTR_SOURCE, /**< interrupt of general DMA OUT channel 1, LEVEL*/ + ETS_DMA_OUT_CH2_INTR_SOURCE, /**< interrupt of general DMA OUT channel 2, LEVEL*/ + ETS_GSPI2_INTR_SOURCE, + ETS_AES_INTR_SOURCE, /**< interrupt of AES accelerator, level*/ + ETS_SHA_INTR_SOURCE, /**< interrupt of SHA accelerator, level*/ + ETS_RSA_INTR_SOURCE, /**< interrupt of RSA accelerator, level*/ + ETS_ECC_INTR_SOURCE, /**< interrupt of ECC accelerator, level*/ + ETS_MAX_INTR_SOURCE, +} periph_interrput_t; + +extern const char * const esp_isr_names[ETS_MAX_INTR_SOURCE]; + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/lp_timer_struct.h b/components/soc/esp32c5/include/soc/lp_timer_struct.h index 75194c69d680..2af34d6a37a9 100644 --- a/components/soc/esp32c5/include/soc/lp_timer_struct.h +++ b/components/soc/esp32c5/include/soc/lp_timer_struct.h @@ -311,6 +311,7 @@ typedef struct lp_timer_dev_t { volatile lp_timer_target_reg_t target[2]; volatile lp_timer_update_reg_t update; volatile lp_timer_counter_reg_t counter[2]; + volatile lp_timer_main_overflow_reg_t main_overflow; volatile lp_timer_int_raw_reg_t int_raw; volatile lp_timer_int_st_reg_t int_st; volatile lp_timer_int_ena_reg_t int_ena; diff --git a/components/soc/esp32c5/include/soc/pcr_struct.h b/components/soc/esp32c5/include/soc/pcr_struct.h index d47ae1ad51af..2f9176a9b119 100644 --- a/components/soc/esp32c5/include/soc/pcr_struct.h +++ b/components/soc/esp32c5/include/soc/pcr_struct.h @@ -1795,11 +1795,11 @@ typedef union { */ typedef union { struct { - /** 32k_sel : R/W; bitpos: [1:0]; default: 0; + /** clk_32k_sel : R/W; bitpos: [1:0]; default: 0; * This field indicates which one 32KHz clock will be used by timergroup. 0: * OSC32K(default), 1: XTAL32K, 2/3: 32KHz from pad GPIO0. */ - uint32_t 32k_sel:2; + uint32_t clk_32k_sel:2; uint32_t reserved_2:30; }; uint32_t val; diff --git a/components/soc/esp32c5/include/soc/periph_defs.h b/components/soc/esp32c5/include/soc/periph_defs.h new file mode 100644 index 000000000000..33268bcb1da4 --- /dev/null +++ b/components/soc/esp32c5/include/soc/periph_defs.h @@ -0,0 +1,87 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include "soc/interrupts.h" + +#ifdef __cplusplus +extern "C" { +#endif + +// TODO: [ESP32C5-PERIPH] (inherit from C6) + +typedef enum { + /* HP peripherals */ + PERIPH_LEDC_MODULE = 0, + PERIPH_UART0_MODULE, + PERIPH_UART1_MODULE, + PERIPH_USB_DEVICE_MODULE, // USB Serial Jtag + PERIPH_I2C0_MODULE, + PERIPH_I2C1_MODULE, + PERIPH_I2S1_MODULE, + PERIPH_TIMG0_MODULE, + PERIPH_TIMG1_MODULE, + PERIPH_UHCI0_MODULE, + PERIPH_RMT_MODULE, + PERIPH_PCNT_MODULE, + PERIPH_MSPI0_MODULE, //SPI0 + PERIPH_MSPI1_MODULE, //SPI1 + PERIPH_GPSPI2_MODULE, //SPI2 + PERIPH_TWAI0_MODULE, + PERIPH_TWAI1_MODULE, + PERIPH_RNG_MODULE, + PERIPH_RSA_MODULE, + PERIPH_AES_MODULE, + PERIPH_SHA_MODULE, + PERIPH_ECC_MODULE, + PERIPH_HMAC_MODULE, + PERIPH_DS_MODULE, + PERIPH_GDMA_MODULE, + PERIPH_MCPWM0_MODULE, + PERIPH_ETM_MODULE, + PERIPH_PARLIO_MODULE, + PERIPH_SYSTIMER_MODULE, + PERIPH_SARADC_MODULE, + PERIPH_TEMPSENSOR_MODULE, + PERIPH_ASSIST_DEBUG_MODULE, + PERIPH_INT_MATRIX_MODULE, + PERIPH_PVT_MONITOR_MODULE, + PERIPH_BITSCRAMBLER_MODULE, + PERIPH_KEY_MANAGE_MODULE, + PERIPH_ECDSA_MODULE, + PERIPH_MEM_MONITOR_MODULE, + PERIPH_TEE_MODULE, + PERIPH_HP_APM_MODULE, + /* LP peripherals */ + PERIPH_LP_I2C0_MODULE, + PERIPH_LP_UART0_MODULE, + PERIPH_LP_TEE_MODULE, + PERIPH_LP_APM_MODULE, + PERIPH_LP_ANA_PERI_MODULE, + PERIPH_LP_PERI_MODULE, + PERIPH_HUK_MODULE, + PERIPH_OTP_DEBUG_MODULE, + /* Peripherals clock managed by the modem_clock driver must be listed last in the enumeration */ + PERIPH_WIFI_MODULE, + PERIPH_BT_MODULE, + PERIPH_COEX_MODULE, + PERIPH_PHY_MODULE, + PERIPH_ANA_I2C_MASTER_MODULE, + PERIPH_MODEM_ETM_MODULE, + PERIPH_MODEM_ADC_COMMON_FE_MODULE, + PERIPH_MODULE_MAX + /* !!! Don't append soc modules here !!! */ +} periph_module_t; + +#define PERIPH_MODEM_MODULE_MIN PERIPH_WIFI_MODULE +#define PERIPH_MODEM_MODULE_MAX PERIPH_MODEM_ADC_COMMON_FE_MODULE +#define PERIPH_MODEM_MODULE_NUM (PERIPH_MODEM_MODULE_MAX - PERIPH_MODEM_MODULE_MIN + 1) +#define IS_MODEM_MODULE(periph) ((periph>=PERIPH_MODEM_MODULE_MIN) && (periph<=PERIPH_MODEM_MODULE_MAX)) + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/reg_base.h b/components/soc/esp32c5/include/soc/reg_base.h index d002cd1259b3..c91ef0596e9e 100644 --- a/components/soc/esp32c5/include/soc/reg_base.h +++ b/components/soc/esp32c5/include/soc/reg_base.h @@ -13,7 +13,7 @@ #define DR_REG_SPIMEM0_BASE 0x60002000 #define DR_REG_SPIMEM1_BASE 0x60003000 #define DR_REG_I2C0_BASE 0x60004000 -#define DR_REG_UHCI0_BASE 0x60005000 +#define DR_REG_UHCI_BASE 0x60005000 #define DR_REG_RMT_BASE 0x60006000 #define DR_REG_LEDC_BASE 0x60007000 #define DR_REG_TIMERG0_BASE 0x60008000 @@ -24,7 +24,8 @@ #define DR_REG_TWAI1_BASE 0x6000D000 #define DR_REG_APB_SARADC_BASE 0x6000E000 #define DR_REG_USB_SERIAL_JTAG_BASE 0x6000F000 -#define DR_REG_INTMTX_BASE 0x60010000 +#define DR_REG_INTERRUPT_MATRIX_BASE 0x60010000 +#define DR_REG_INTERRUPT_CORE0_BASE DR_REG_INTERRUPT_MATRIX_BASE #define DR_REG_I2C1_BASE 0x60011000 #define DR_REG_PCNT_BASE 0x60012000 #define DR_REG_SOC_ETM_BASE 0x60013000 diff --git a/components/soc/esp32c5/include/soc/reset_reasons.h b/components/soc/esp32c5/include/soc/reset_reasons.h new file mode 100644 index 000000000000..9576fb759f3a --- /dev/null +++ b/components/soc/esp32c5/include/soc/reset_reasons.h @@ -0,0 +1,55 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +//+-----------------------------------------------Terminology---------------------------------------------+ +//| | +//| CPU Reset: Reset CPU core only, once reset done, CPU will execute from reset vector | +//| | +//| Core Reset: Reset the whole digital system except RTC sub-system | +//| | +//| System Reset: Reset the whole digital system, including RTC sub-system | +//| | +//| Chip Reset: Reset the whole chip, including the analog part | +//| | +//+-------------------------------------------------------------------------------------------------------+ + +#ifdef __cplusplus +extern "C" { +#endif + + +// TODO: [ESP32C5] IDF-8660 (inherit from P4) +/** + * @brief Naming conventions: RESET_REASON_{reset level}_{reset reason} + * @note refer to TRM: chapter + */ +typedef enum { + RESET_REASON_CHIP_POWER_ON = 0x01, // Power on reset + RESET_REASON_CORE_SW = 0x03, // Software resets the digital core + RESET_REASON_CORE_DEEP_SLEEP = 0x05, // Deep sleep reset the digital core, check when doing sleep bringup if 0x5/0x6 is deepsleep wakeup TODO IDF-7529 + RESET_REASON_SYS_PMU_PWR_DOWN = 0x05, // PMU HP power down system reset + RESET_REASON_CPU_PMU_PWR_DOWN = 0x06, // PMU HP power down CPU reset + RESET_REASON_SYS_HP_WDT = 0x07, // HP WDT resets system + RESET_REASON_SYS_LP_WDT = 0x09, // LP WDT resets system + RESET_REASON_CORE_HP_WDT = 0x0B, // HP WDT resets digital core + RESET_REASON_CPU0_SW = 0x0C, // Software resets CPU 0 + RESET_REASON_CORE_LP_WDT = 0x0D, // LP WDT resets digital core + RESET_REASON_SYS_BROWN_OUT = 0x0F, // VDD voltage is not stable and resets the digital core + RESET_REASON_CHIP_LP_WDT = 0x10, // LP WDT resets chip + RESET_REASON_SYS_SUPER_WDT = 0x12, // Super watch dog resets the digital core and rtc module + RESET_REASON_SYS_CLK_GLITCH = 0x13, // Glitch on clock resets the digital core and rtc module + RESET_REASON_CORE_EFUSE_CRC = 0x14, // eFuse CRC error resets the digital core + RESET_REASON_CORE_USB_JTAG = 0x16, // USB Serial/JTAG controller's JTAG resets the digital core + RESET_REASON_CORE_USB_UART = 0x17, // USB Serial/JTAG controller's UART resets the digital core + RESET_REASON_CPU_JTAG = 0x18, // Glitch on power resets the digital core +} soc_reset_reason_t; + + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/rtc_io_channel.h b/components/soc/esp32c5/include/soc/rtc_io_channel.h new file mode 100644 index 000000000000..f9544599395c --- /dev/null +++ b/components/soc/esp32c5/include/soc/rtc_io_channel.h @@ -0,0 +1,33 @@ +/* + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +// TODO: [ESP32C5] IDF-8719 (inherit from C6) +//RTC GPIO channels +#define RTCIO_GPIO0_CHANNEL 0 //RTCIO_CHANNEL_0 +#define RTCIO_CHANNEL_0_GPIO_NUM 0 + +#define RTCIO_GPIO1_CHANNEL 1 //RTCIO_CHANNEL_1 +#define RTCIO_CHANNEL_1_GPIO_NUM 1 + +#define RTCIO_GPIO2_CHANNEL 2 //RTCIO_CHANNEL_2 +#define RTCIO_CHANNEL_2_GPIO_NUM 2 + +#define RTCIO_GPIO3_CHANNEL 3 //RTCIO_CHANNEL_3 +#define RTCIO_CHANNEL_3_GPIO_NUM 3 + +#define RTCIO_GPIO4_CHANNEL 4 //RTCIO_CHANNEL_4 +#define RTCIO_CHANNEL_4_GPIO_NUM 4 + +#define RTCIO_GPIO5_CHANNEL 5 //RTCIO_CHANNEL_5 +#define RTCIO_CHANNEL_5_GPIO_NUM 5 + +#define RTCIO_GPIO6_CHANNEL 6 //RTCIO_CHANNEL_6 +#define RTCIO_CHANNEL_6_GPIO_NUM 6 + +#define RTCIO_GPIO7_CHANNEL 7 //RTCIO_CHANNEL_7 +#define RTCIO_CHANNEL_7_GPIO_NUM 7 diff --git a/components/soc/esp32c5/include/soc/soc.h b/components/soc/esp32c5/include/soc/soc.h new file mode 100644 index 000000000000..f7a2ee0a1331 --- /dev/null +++ b/components/soc/esp32c5/include/soc/soc.h @@ -0,0 +1,242 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#ifndef __ASSEMBLER__ +#include +#include "esp_assert.h" +#endif + +#include "esp_bit_defs.h" +#include "reg_base.h" + +#define PRO_CPU_NUM (0) + +/** + * @brief Reg base address for multi-instance peripherals + * @note common multi-instance peripherals includes + * I2C, I2S, UART, UHCI, SPI, SPIMEM, MCPWM, TWAI, TIMER_GROUP + * please check `reg_base.h` and the corresponding `xxx_reg.h` whether the base addresses are match + */ +#define REG_I2C_BASE(i) ((i) == 0 ? DR_REG_I2C0_BASE : DR_REG_I2C1_BASE) // two I2C on C5 +#define REG_TIMG_BASE(i) (DR_REG_TIMERG0_BASE + (i) * 0x1000) // TIMERG0 and TIMERG1 +#define REG_TWAI_BASE(i) ((i) == 0 ? DR_REG_TWAI0_BASE : DR_REG_TWAI1_BASE) // TWAI0 and TWAI1 +#define REG_UART_BASE(i) (DR_REG_UART0_BASE + (i) * 0x1000) // UART0 and UART1 + +//Registers Operation {{ +#define ETS_UNCACHED_ADDR(addr) (addr) +#define ETS_CACHED_ADDR(addr) (addr) + +#ifndef __ASSEMBLER__ + +//write value to register +#define REG_WRITE(_r, _v) do { \ + (*(volatile uint32_t *)(_r)) = (_v); \ + } while(0) + +//read value from register +#define REG_READ(_r) ({ \ + (*(volatile uint32_t *)(_r)); \ + }) + +//get bit or get bits from register +#define REG_GET_BIT(_r, _b) ({ \ + (*(volatile uint32_t*)(_r) & (_b)); \ + }) + +//set bit or set bits to register +#define REG_SET_BIT(_r, _b) do { \ + *(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r)) | (_b); \ + } while(0) + +//clear bit or clear bits of register +#define REG_CLR_BIT(_r, _b) do { \ + *(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r)) & (~(_b)); \ + } while(0) + +//set bits of register controlled by mask +#define REG_SET_BITS(_r, _b, _m) do { \ + *(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r) & ~(_m)) | ((_b) & (_m)); \ + } while(0) + +//get field from register, uses field _S & _V to determine mask +#define REG_GET_FIELD(_r, _f) ({ \ + ((REG_READ(_r) >> (_f##_S)) & (_f##_V)); \ + }) + +//set field of a register from variable, uses field _S & _V to determine mask +#define REG_SET_FIELD(_r, _f, _v) do { \ + REG_WRITE((_r),((REG_READ(_r) & ~((_f##_V) << (_f##_S)))|(((_v) & (_f##_V))<<(_f##_S)))); \ + } while(0) + +//get field value from a variable, used when _f is not left shifted by _f##_S +#define VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f)) + +//get field value from a variable, used when _f is left shifted by _f##_S +#define VALUE_GET_FIELD2(_r, _f) (((_r) & (_f))>> (_f##_S)) + +//set field value to a variable, used when _f is not left shifted by _f##_S +#define VALUE_SET_FIELD(_r, _f, _v) ((_r)=(((_r) & ~((_f) << (_f##_S)))|((_v)<<(_f##_S)))) + +//set field value to a variable, used when _f is left shifted by _f##_S +#define VALUE_SET_FIELD2(_r, _f, _v) ((_r)=(((_r) & ~(_f))|((_v)<<(_f##_S)))) + +//generate a value from a field value, used when _f is not left shifted by _f##_S +#define FIELD_TO_VALUE(_f, _v) (((_v)&(_f))<<_f##_S) + +//generate a value from a field value, used when _f is left shifted by _f##_S +#define FIELD_TO_VALUE2(_f, _v) (((_v)<<_f##_S) & (_f)) + +//read value from register +#define READ_PERI_REG(addr) ({ \ + (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))); \ + }) + +//write value to register +#define WRITE_PERI_REG(addr, val) do { \ + (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))) = (uint32_t)(val); \ + } while(0) + +//clear bits of register controlled by mask +#define CLEAR_PERI_REG_MASK(reg, mask) do { \ + WRITE_PERI_REG((reg), (READ_PERI_REG(reg)&(~(mask)))); \ + } while(0) + +//set bits of register controlled by mask +#define SET_PERI_REG_MASK(reg, mask) do { \ + WRITE_PERI_REG((reg), (READ_PERI_REG(reg)|(mask))); \ + } while(0) + +//get bits of register controlled by mask +#define GET_PERI_REG_MASK(reg, mask) ({ \ + (READ_PERI_REG(reg) & (mask)); \ + }) + +//get bits of register controlled by highest bit and lowest bit +#define GET_PERI_REG_BITS(reg, hipos,lowpos) ({ \ + ((READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1)); \ + }) + +//set bits of register controlled by mask and shift +#define SET_PERI_REG_BITS(reg,bit_map,value,shift) do { \ + WRITE_PERI_REG((reg),(READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & (bit_map))<<(shift)) ); \ + } while(0) + +//get field of register +#define GET_PERI_REG_BITS2(reg, mask,shift) ({ \ + ((READ_PERI_REG(reg)>>(shift))&(mask)); \ + }) + +#endif /* !__ASSEMBLER__ */ +//}} + +//Periheral Clock {{ +#define APB_CLK_FREQ_ROM ( 40*1000000 ) +#define CPU_CLK_FREQ_ROM APB_CLK_FREQ_ROM +#define EFUSE_CLK_FREQ_ROM ( 20*1000000) +#define CPU_CLK_FREQ_MHZ_BTLD (80) // The cpu clock frequency (in MHz) to set at 2nd stage bootloader system clock configuration +#define CPU_CLK_FREQ APB_CLK_FREQ +#define APB_CLK_FREQ ( 40*1000000 ) +#define MODEM_REQUIRED_MIN_APB_CLK_FREQ ( 80*1000000 ) +#define REF_CLK_FREQ ( 1000000 ) +#define XTAL_CLK_FREQ (40*1000000) +#define GPIO_MATRIX_DELAY_NS 0 +//}} + +/* Overall memory map */ +/* Note: We should not use MACROs similar in cache_memory.h + * those are defined during run-time. But the MACROs here + * should be defined statically! + */ + +#define SOC_IROM_LOW 0x42000000 +#define SOC_IROM_HIGH (SOC_IROM_LOW + (SOC_MMU_PAGE_SIZE<<8)) +#define SOC_DROM_LOW SOC_IROM_LOW +#define SOC_DROM_HIGH SOC_IROM_HIGH +#define SOC_IROM_MASK_LOW 0x40000000 +#define SOC_IROM_MASK_HIGH 0x40050000 +#define SOC_DROM_MASK_LOW 0x40000000 +#define SOC_DROM_MASK_HIGH 0x40050000 +#define SOC_IRAM_LOW 0x40800000 +#define SOC_IRAM_HIGH 0x40880000 +#define SOC_DRAM_LOW 0x40800000 +#define SOC_DRAM_HIGH 0x40880000 +#define SOC_RTC_IRAM_LOW 0x50000000 // ESP32-C5 only has 16k LP memory +#define SOC_RTC_IRAM_HIGH 0x50004000 +#define SOC_RTC_DRAM_LOW 0x50000000 +#define SOC_RTC_DRAM_HIGH 0x50004000 +#define SOC_RTC_DATA_LOW 0x50000000 +#define SOC_RTC_DATA_HIGH 0x50004000 + +//First and last words of the D/IRAM region, for both the DRAM address as well as the IRAM alias. +#define SOC_DIRAM_IRAM_LOW 0x40800000 +#define SOC_DIRAM_IRAM_HIGH 0x40880000 +#define SOC_DIRAM_DRAM_LOW 0x40800000 +#define SOC_DIRAM_DRAM_HIGH 0x40880000 + +#define MAP_DRAM_TO_IRAM(addr) (addr) +#define MAP_IRAM_TO_DRAM(addr) (addr) + +// Region of memory accessible via DMA. See esp_ptr_dma_capable(). +#define SOC_DMA_LOW 0x40800000 +#define SOC_DMA_HIGH 0x40880000 + +// Region of RAM that is byte-accessible. See esp_ptr_byte_accessible(). +#define SOC_BYTE_ACCESSIBLE_LOW 0x40800000 +#define SOC_BYTE_ACCESSIBLE_HIGH 0x40880000 + +//Region of memory that is internal, as in on the same silicon die as the ESP32 CPUs +//(excluding RTC data region, that's checked separately.) See esp_ptr_internal(). +#define SOC_MEM_INTERNAL_LOW 0x40800000 +#define SOC_MEM_INTERNAL_HIGH 0x40880000 +#define SOC_MEM_INTERNAL_LOW1 0x40800000 +#define SOC_MEM_INTERNAL_HIGH1 0x40880000 + +#define SOC_MAX_CONTIGUOUS_RAM_SIZE (SOC_IRAM_HIGH - SOC_IRAM_LOW) ///< Largest span of contiguous memory (DRAM or IRAM) in the address space + +// Region of address space that holds peripherals +#define SOC_PERIPHERAL_LOW 0x60000000 +#define SOC_PERIPHERAL_HIGH 0x60100000 + +// Debug region, not used by software +#define SOC_DEBUG_LOW 0x20000000 +#define SOC_DEBUG_HIGH 0x28000000 + +// Start (highest address) of ROM boot stack, only relevant during early boot +#define SOC_ROM_STACK_START 0x4087e610 +#define SOC_ROM_STACK_SIZE 0x2000 + +//On RISC-V CPUs, the interrupt sources are all external interrupts, whose type, source and priority are configured by SW. +//There is no HW NMI conception. SW should controlled the masked levels through INT_THRESH_REG. + +//CPU0 Interrupt numbers used in components/riscv/vectors.S. Change it's logic if modifying +#define ETS_T1_WDT_INUM 24 +#define ETS_CACHEERR_INUM 25 +#define ETS_MEMPROT_ERR_INUM 26 +#define ETS_ASSIST_DEBUG_INUM 27 // Note: this interrupt can be combined with others (e.g., CACHEERR), as we can identify its trigger is activated + +//CPU0 Max valid interrupt number +#define ETS_MAX_INUM 31 + +//CPU0 Interrupt number used in ROM, should be cancelled in SDK +#define ETS_SLC_INUM 1 +#define ETS_UART0_INUM 5 +#define ETS_UART1_INUM 5 +#define ETS_SPI2_INUM 1 +//CPU0 Interrupt number used in ROM code only when module init function called, should pay attention here. +#define ETS_GPIO_INUM 4 + +//Other interrupt number should be managed by the user + +//Invalid interrupt for number interrupt matrix +#define ETS_INVALID_INUM 0 + +//Interrupt medium level, used for INT WDT for example +#define SOC_INTERRUPT_LEVEL_MEDIUM 4 + +// Interrupt number for the Interrupt watchdog +#define ETS_INT_WDT_INUM (ETS_T1_WDT_INUM) diff --git a/components/soc/esp32c5/include/soc/soc_caps.h b/components/soc/esp32c5/include/soc/soc_caps.h new file mode 100644 index 000000000000..bd01111d290d --- /dev/null +++ b/components/soc/esp32c5/include/soc/soc_caps.h @@ -0,0 +1,562 @@ +/* + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* + * These defines are parsed and imported as kconfig variables via the script + * `tools/gen_soc_caps_kconfig/gen_soc_caps_kconfig.py` + * + * If this file is changed the script will automatically run the script + * and generate the kconfig variables as part of the pre-commit hooks. + * + * It can also be run manually. For more information, see `${IDF_PATH}/tools/gen_soc_caps_kconfig/README.md` + */ + +#pragma once + +/*-------------------------- COMMON CAPS ---------------------------------------*/ +// #define SOC_ADC_SUPPORTED 1 +// #define SOC_DEDICATED_GPIO_SUPPORTED 1 +// #define SOC_UART_SUPPORTED 1 +// #define SOC_GDMA_SUPPORTED 1 +// #define SOC_AHB_GDMA_SUPPORTED 1 +// #define SOC_GPTIMER_SUPPORTED 1 +// #define SOC_PCNT_SUPPORTED 1 +// #define SOC_MCPWM_SUPPORTED 1 +// #define SOC_TWAI_SUPPORTED 1 +// #define SOC_ETM_SUPPORTED 1 +// #define SOC_PARLIO_SUPPORTED 1 +// #define SOC_BT_SUPPORTED 1 +// #define SOC_IEEE802154_SUPPORTED 1 +// #define SOC_ASYNC_MEMCPY_SUPPORTED 1 +// #define SOC_USB_SERIAL_JTAG_SUPPORTED 1 +// #define SOC_TEMP_SENSOR_SUPPORTED 1 +// #define SOC_WIFI_SUPPORTED 1 +// #define SOC_SUPPORTS_SECURE_DL_MODE 1 +// #define SOC_ULP_SUPPORTED 1 +// #define SOC_LP_CORE_SUPPORTED 1 +// #define SOC_EFUSE_KEY_PURPOSE_FIELD 1 +// #define SOC_EFUSE_SUPPORTED 1 +// #define SOC_RTC_FAST_MEM_SUPPORTED 1 +// #define SOC_RTC_MEM_SUPPORTED 1 +// #define SOC_I2S_SUPPORTED 1 +// #define SOC_RMT_SUPPORTED 1 +// #define SOC_SDM_SUPPORTED 1 +// #define SOC_GPSPI_SUPPORTED 1 +// #define SOC_LEDC_SUPPORTED 1 +// #define SOC_I2C_SUPPORTED 1 +// #define SOC_SYSTIMER_SUPPORTED 1 +// #define SOC_SUPPORT_COEXISTENCE 1 +// #define SOC_AES_SUPPORTED 1 +// #define SOC_MPI_SUPPORTED 1 +// #define SOC_SHA_SUPPORTED 1 +// #define SOC_HMAC_SUPPORTED 1 +// #define SOC_DIG_SIGN_SUPPORTED 1 +// #define SOC_ECC_SUPPORTED 1 +// #define SOC_FLASH_ENC_SUPPORTED 1 +// #define SOC_SECURE_BOOT_SUPPORTED 1 +// #define SOC_SDIO_SLAVE_SUPPORTED 1 +// #define SOC_BOD_SUPPORTED 1 +// #define SOC_APM_SUPPORTED 1 +// #define SOC_PMU_SUPPORTED 1 +// #define SOC_PAU_SUPPORTED 1 +// #define SOC_LP_TIMER_SUPPORTED 1 +// #define SOC_LP_AON_SUPPORTED 1 +// #define SOC_LP_PERIPHERALS_SUPPORTED 1 +// #define SOC_LP_I2C_SUPPORTED 1 +// #define SOC_ULP_LP_UART_SUPPORTED 1 +// #define SOC_CLK_TREE_SUPPORTED 1 +// #define SOC_ASSIST_DEBUG_SUPPORTED 1 +// #define SOC_WDT_SUPPORTED 1 +// #define SOC_SPI_FLASH_SUPPORTED 1 +// #define SOC_BITSCRAMBLER_SUPPORTED 1 +// #define SOC_ECDSA_SUPPORTED 1 +// #define SOC_KEY_MANAGER_SUPPORTED 1 +#define SOC_INT_HW_NESTED_SUPPORTED 1 + +/*-------------------------- XTAL CAPS ---------------------------------------*/ +// #define SOC_XTAL_SUPPORT_40M 1 + +/*-------------------------- AES CAPS -----------------------------------------*/ +// #define SOC_AES_SUPPORT_DMA (1) + +/* Has a centralized DMA, which is shared with all peripherals */ +// #define SOC_AES_GDMA (1) + +// #define SOC_AES_SUPPORT_AES_128 (1) +// #define SOC_AES_SUPPORT_AES_256 (1) + +/*-------------------------- ADC CAPS -------------------------------*/ +/*!< SAR ADC Module*/ +// #define SOC_ADC_DIG_CTRL_SUPPORTED 1 +// #define SOC_ADC_DIG_IIR_FILTER_SUPPORTED 1 +// #define SOC_ADC_MONITOR_SUPPORTED 1 +// #define SOC_ADC_DIG_SUPPORTED_UNIT(UNIT) 1 //Digital controller supported ADC unit +// #define SOC_ADC_DMA_SUPPORTED 1 +// #define SOC_ADC_PERIPH_NUM (1U) +// #define SOC_ADC_CHANNEL_NUM(PERIPH_NUM) (7) +// #define SOC_ADC_MAX_CHANNEL_NUM (7) +// #define SOC_ADC_ATTEN_NUM (4) + +/*!< Digital */ +// #define SOC_ADC_DIGI_CONTROLLER_NUM (1U) +// #define SOC_ADC_PATT_LEN_MAX (8) /*!< Two pattern tables, each contains 4 items. Each item takes 1 byte */ +// #define SOC_ADC_DIGI_MAX_BITWIDTH (12) +// #define SOC_ADC_DIGI_MIN_BITWIDTH (12) +// #define SOC_ADC_DIGI_IIR_FILTER_NUM (2) +// #define SOC_ADC_DIGI_MONITOR_NUM (2) +// #define SOC_ADC_DIGI_RESULT_BYTES (4) +// #define SOC_ADC_DIGI_DATA_BYTES_PER_CONV (4) +/*!< F_sample = F_digi_con / 2 / interval. F_digi_con = 5M for now. 30 <= interval <= 4095 */ +// #define SOC_ADC_SAMPLE_FREQ_THRES_HIGH 83333 +// #define SOC_ADC_SAMPLE_FREQ_THRES_LOW 611 + +/*!< RTC */ +// #define SOC_ADC_RTC_MIN_BITWIDTH (12) +// #define SOC_ADC_RTC_MAX_BITWIDTH (12) + +/*!< Calibration */ +// #define SOC_ADC_CALIBRATION_V1_SUPPORTED (1) /*!< support HW offset calibration version 1*/ +// #define SOC_ADC_SELF_HW_CALI_SUPPORTED (1) /*!< support HW offset self calibration */ +// #define SOC_ADC_CALIB_CHAN_COMPENS_SUPPORTED (1) /*!< support channel compensation to the HW offset calibration */ + +/*!< Interrupt */ +// #define SOC_ADC_TEMPERATURE_SHARE_INTR (1) + +/*!< ADC power control is shared by PWDET */ +// #define SOC_ADC_SHARED_POWER 1 + +// ESP32C5-TODO: Copy from esp32C5, need check +/*-------------------------- APB BACKUP DMA CAPS -------------------------------*/ +// #define SOC_APB_BACKUP_DMA (0) + +/*-------------------------- BROWNOUT CAPS -----------------------------------*/ +// #define SOC_BROWNOUT_RESET_SUPPORTED 1 + +/*-------------------------- CACHE CAPS --------------------------------------*/ +// #define SOC_SHARED_IDCACHE_SUPPORTED 1 //Shared Cache for both instructions and data +// #define SOC_CACHE_FREEZE_SUPPORTED 1 + +/*-------------------------- CPU CAPS ----------------------------------------*/ +#define SOC_CPU_CORES_NUM (1U) +// #define SOC_CPU_INTR_NUM 32 +// #define SOC_CPU_HAS_FLEXIBLE_INTC 1 +#define SOC_INT_CLIC_SUPPORTED 1 + +// #define SOC_CPU_BREAKPOINTS_NUM 4 +// #define SOC_CPU_WATCHPOINTS_NUM 4 +// #define SOC_CPU_WATCHPOINT_MAX_REGION_SIZE 0x80000000 // bytes + +// #define SOC_CPU_HAS_PMA 1 +// #define SOC_CPU_IDRAM_SPLIT_USING_PMP 1 + +/*-------------------------- DIGITAL SIGNATURE CAPS ----------------------------------------*/ +/** The maximum length of a Digital Signature in bits. */ +// #define SOC_DS_SIGNATURE_MAX_BIT_LEN (3072) + +/** Initialization vector (IV) length for the RSA key parameter message digest (MD) in bytes. */ +// #define SOC_DS_KEY_PARAM_MD_IV_LENGTH (16) + +/** Maximum wait time for DS parameter decryption key. If overdue, then key error. + See TRM DS chapter for more details */ +// #define SOC_DS_KEY_CHECK_MAX_WAIT_US (1100) + +/*-------------------------- GDMA CAPS -------------------------------------*/ +// #define SOC_AHB_GDMA_VERSION 1U +// #define SOC_GDMA_NUM_GROUPS_MAX 1U +// #define SOC_GDMA_PAIRS_PER_GROUP_MAX 3 +// #define SOC_GDMA_SUPPORT_ETM 1 // Support ETM submodule + +/*-------------------------- ETM CAPS --------------------------------------*/ +// #define SOC_ETM_GROUPS 1U // Number of ETM groups +// #define SOC_ETM_CHANNELS_PER_GROUP 50 // Number of ETM channels in the group + +/*-------------------------- GPIO CAPS ---------------------------------------*/ +// ESP32-C5 has 1 GPIO peripheral +// #define SOC_GPIO_PORT 1U +#define SOC_GPIO_PIN_COUNT 31 +// #define SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER 1 +// #define SOC_GPIO_FLEX_GLITCH_FILTER_NUM 8 + +// GPIO peripheral has the ETM extension +// #define SOC_GPIO_SUPPORT_ETM 1 +// #define SOC_GPIO_ETM_EVENTS_PER_GROUP 8 +// #define SOC_GPIO_ETM_TASKS_PER_GROUP 8 + +// Target has the full LP IO subsystem +// On ESP32-C5, Digital IOs have their own registers to control pullup/down capability, independent of LP registers. +// #define SOC_GPIO_SUPPORT_RTC_INDEPENDENT (1) +// GPIO0~7 on ESP32C5 can support chip deep sleep wakeup +// #define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP (1) + +// #define SOC_GPIO_VALID_GPIO_MASK ((1U< SPI0/SPI1, host_id = 1 -> SPI2, +// #define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(host_id) ({(void)host_id; 1;}) + +// #define SOC_MEMSPI_IS_INDEPENDENT 1 +// #define SOC_SPI_MAX_PRE_DIVIDER 16 + +/*-------------------------- SPI MEM CAPS ---------------------------------------*/ +// #define SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE (1) +// #define SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND (1) +// #define SOC_SPI_MEM_SUPPORT_AUTO_RESUME (1) +// #define SOC_SPI_MEM_SUPPORT_IDLE_INTR (1) +// #define SOC_SPI_MEM_SUPPORT_SW_SUSPEND (1) +// #define SOC_SPI_MEM_SUPPORT_CHECK_SUS (1) +// #define SOC_SPI_MEM_SUPPORT_WRAP (1) + +// #define SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED 1 +// #define SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED 1 +// #define SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED 1 + +/*-------------------------- SYSTIMER CAPS ----------------------------------*/ +// #define SOC_SYSTIMER_COUNTER_NUM 2 // Number of counter units +// #define SOC_SYSTIMER_ALARM_NUM 3 // Number of alarm units +// #define SOC_SYSTIMER_BIT_WIDTH_LO 32 // Bit width of systimer low part +// #define SOC_SYSTIMER_BIT_WIDTH_HI 20 // Bit width of systimer high part +// #define SOC_SYSTIMER_FIXED_DIVIDER 1 // Clock source divider is fixed: 2.5 +// #define SOC_SYSTIMER_SUPPORT_RC_FAST 1 // Systimer can use RC_FAST clock source +// #define SOC_SYSTIMER_INT_LEVEL 1 // Systimer peripheral uses level interrupt +// #define SOC_SYSTIMER_ALARM_MISS_COMPENSATE 1 // Systimer peripheral can generate interrupt immediately if t(target) > t(current) +// #define SOC_SYSTIMER_SUPPORT_ETM 1 // Systimer comparator can generate ETM event + +/*-------------------------- LP_TIMER CAPS ----------------------------------*/ +// #define SOC_LP_TIMER_BIT_WIDTH_LO 32 // Bit width of lp_timer low part +// #define SOC_LP_TIMER_BIT_WIDTH_HI 16 // Bit width of lp_timer high part + +/*--------------------------- TIMER GROUP CAPS ---------------------------------------*/ +#define SOC_TIMER_GROUPS (2) +#define SOC_TIMER_GROUP_TIMERS_PER_GROUP (1U) +// #define SOC_TIMER_GROUP_COUNTER_BIT_WIDTH (54) +// #define SOC_TIMER_GROUP_SUPPORT_XTAL (1) +// #define SOC_TIMER_GROUP_SUPPORT_RC_FAST (1) +// #define SOC_TIMER_GROUP_TOTAL_TIMERS (2) +// #define SOC_TIMER_SUPPORT_ETM (1) + +/*--------------------------- WATCHDOG CAPS ---------------------------------------*/ +// #define SOC_MWDT_SUPPORT_XTAL (1) + +/*-------------------------- TWAI CAPS ---------------------------------------*/ +// #define SOC_TWAI_CONTROLLER_NUM 2 +// #define SOC_TWAI_CLK_SUPPORT_XTAL 1 +// #define SOC_TWAI_BRP_MIN 2 +// #define SOC_TWAI_BRP_MAX 32768 +// #define SOC_TWAI_SUPPORTS_RX_STATUS 1 + +/*-------------------------- eFuse CAPS----------------------------*/ +// #define SOC_EFUSE_DIS_DOWNLOAD_ICACHE 1 +// #define SOC_EFUSE_DIS_PAD_JTAG 1 +// #define SOC_EFUSE_DIS_USB_JTAG 1 +// #define SOC_EFUSE_DIS_DIRECT_BOOT 1 +// #define SOC_EFUSE_SOFT_DIS_JTAG 1 +// #define SOC_EFUSE_DIS_ICACHE 1 +// #define SOC_EFUSE_BLOCK9_KEY_PURPOSE_QUIRK 1 // XTS-AES key purpose not supported for this block + +/*-------------------------- Secure Boot CAPS----------------------------*/ +// #define SOC_SECURE_BOOT_V2_RSA 1 +// #define SOC_SECURE_BOOT_V2_ECC 1 +// #define SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 3 +// #define SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS 1 +// #define SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY 1 + +/*-------------------------- Flash Encryption CAPS----------------------------*/ +// #define SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX (64) +// #define SOC_FLASH_ENCRYPTION_XTS_AES 1 +// #define SOC_FLASH_ENCRYPTION_XTS_AES_128 1 + +/*------------------------ Anti DPA (Security) CAPS --------------------------*/ +// #define SOC_CRYPTO_DPA_PROTECTION_SUPPORTED 1 + +/*-------------------------- UART CAPS ---------------------------------------*/ +// ESP32-C5 has 3 UARTs (2 HP UART, and 1 LP UART) +#define SOC_UART_NUM (3) +#define SOC_UART_HP_NUM (2) +#define SOC_UART_LP_NUM (1U) +// #define SOC_UART_FIFO_LEN (128) /*!< The UART hardware FIFO length */ +// #define SOC_LP_UART_FIFO_LEN (16) /*!< The LP UART hardware FIFO length */ +// #define SOC_UART_BITRATE_MAX (5000000) /*!< Max bit rate supported by UART */ +// #define SOC_UART_SUPPORT_PLL_F80M_CLK (1) /*!< Support PLL_F80M as the clock source */ +// #define SOC_UART_SUPPORT_RTC_CLK (1) /*!< Support RTC clock as the clock source */ +// #define SOC_UART_SUPPORT_XTAL_CLK (1) /*!< Support XTAL clock as the clock source */ +// #define SOC_UART_SUPPORT_WAKEUP_INT (1) /*!< Support UART wakeup interrupt */ + +// UART has an extra TX_WAIT_SEND state when the FIFO is not empty and XOFF is enabled +// #define SOC_UART_SUPPORT_FSM_TX_WAIT_SEND (1) + +/*-------------------------- COEXISTENCE HARDWARE PTI CAPS -------------------------------*/ +// #define SOC_COEX_HW_PTI (1) + +/*-------------------------- EXTERNAL COEXISTENCE CAPS -------------------------------------*/ +// #define SOC_EXTERNAL_COEX_ADVANCE (1) /*!< HARDWARE ADVANCED EXTERNAL COEXISTENCE CAPS */ +// #define SOC_EXTERNAL_COEX_LEADER_TX_LINE (0) /*!< EXTERNAL COEXISTENCE TX LINE CAPS */ + +/*--------------- PHY REGISTER AND MEMORY SIZE CAPS --------------------------*/ +// #define SOC_PHY_DIG_REGS_MEM_SIZE (21*4) + +/*--------------- WIFI LIGHT SLEEP CLOCK WIDTH CAPS --------------------------*/ +// #define SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH (12) + +/*-------------------------- Power Management CAPS ----------------------------*/ +// #define SOC_PM_SUPPORT_WIFI_WAKEUP (1) +// #define SOC_PM_SUPPORT_BEACON_WAKEUP (1) +// #define SOC_PM_SUPPORT_BT_WAKEUP (1) +// #define SOC_PM_SUPPORT_EXT1_WAKEUP (1) +// #define SOC_PM_SUPPORT_EXT1_WAKEUP_MODE_PER_PIN (1) /*!