Questasim simulation not working

[victor-unican]

Trying to run X-Heep with Questasim simulator.

No problems with Verilator or running on Nexys A7 board. Not working with Questasim. Our version is what Europractice distribute: 2022.4

In this case, we are booting from flash, but booting with memory preloading or JTAG reports the same error

Message is:

0ns: the parameter COREV_PULP is 00000000

0ns: the parameter FPU is 00000000

0ns: the parameter ZFINX is 00000000

0ns: the parameter X_EXT is 00000000

0ns: the parameter ZFINX is 00000000

0ns: the parameter JTAG_DPI is 00000000

0ns: the parameter EXT_DOMAINS is 00000000

0ns: the parameter USE_EXTERNAL_DEVICE_EXAMPLE is 00000001

0ns: the parameter CLK_FREQUENCY is 100000 KHz

[X-HEEP]: NUM_BYTES = 96KB

UART: Created /dev/pts/11 for uart0. Connect to it with any terminal program, e.g.

$ screen /dev/pts/11

UART: Additionally writing all UART output to 'uart0.log'.

[TESTBENCH]: loading firmware ../../../sw/build/main.hex

[TESTBENCH]: Booting from flash

[TESTBENCH]: Using OpenTitan SPI

** Fatal: This rule has a higher start than end address!!!

Violating rule 5.

Rule> IDX: xxxxxxxx START: xxxxxxxx END: xxxxxxxx

Time: 0 ps Scope: tb_top.testharness_i.x_heep_system_i.core_v_mini_mcu_i.system_bus_i.system_xbar_i.gen_xbar_1toM.xbar_varlat_one_to_n_i.u_addr_decode.proc_check_addr_map.#anonblk#97275429#144#5#.check_start File: ../../../hw/vendor/pulp_platform_common_cells/src/addr_decode.sv Line: 147

** Note: $finish : ../../../hw/vendor/pulp_platform_common_cells/src/addr_decode.sv(147)

Time: 0 ps Iteration: 6 Instance: /tb_top/testharness_i/x_heep_system_i/core_v_mini_mcu_i/system_bus_i/system_xbar_i/gen_xbar_1toM/xbar_varlat_one_to_n_i/u_addr_decode

1

Break at ../../../hw/vendor/pulp_platform_common_cells/src/addr_decode.sv line 147