From a64f88eddc7f1e9bce2240e3d153928745fdf035 Mon Sep 17 00:00:00 2001
From: Davide Schiavone <davide@openhwgroup.org>
Date: Thu, 5 Oct 2023 18:23:14 +0200
Subject: [PATCH] fix cv32e40px fpga (#396)

---
 core-v-mini-mcu.core                   |  1 +
 hw/fpga/cv32e40px_xilinx_clock_gate.sv | 25 +++++++++++++++++++++++++
 hw/vendor/esl_epfl_cv32e40px.core      |  2 +-
 3 files changed, 27 insertions(+), 1 deletion(-)
 create mode 100644 hw/fpga/cv32e40px_xilinx_clock_gate.sv

diff --git a/core-v-mini-mcu.core b/core-v-mini-mcu.core
index 52b58b04a..7bebad444 100644
--- a/core-v-mini-mcu.core
+++ b/core-v-mini-mcu.core
@@ -108,6 +108,7 @@ filesets:
     - hw/fpga/cv32e40p_xilinx_clock_gate.sv:  { file_type: systemVerilogSource }
     - hw/fpga/cv32e40x_xilinx_clock_gate.sv:  { file_type: systemVerilogSource }
     - hw/fpga/cve2_xilinx_clock_gate.sv:  { file_type: systemVerilogSource }
+    - hw/fpga/cv32e40px_xilinx_clock_gate.sv:  { file_type: systemVerilogSource }
     - hw/fpga/pad_cell_input_xilinx.sv:  { file_type: systemVerilogSource }
     - hw/fpga/pad_cell_output_xilinx.sv:  { file_type: systemVerilogSource }
     - hw/fpga/pad_cell_inout_xilinx.sv:  { file_type: systemVerilogSource }
diff --git a/hw/fpga/cv32e40px_xilinx_clock_gate.sv b/hw/fpga/cv32e40px_xilinx_clock_gate.sv
new file mode 100644
index 000000000..291f3b035
--- /dev/null
+++ b/hw/fpga/cv32e40px_xilinx_clock_gate.sv
@@ -0,0 +1,25 @@
+// Copyright 2017 ETH Zurich and University of Bologna.
+// Copyright and related rights are licensed under the Solderpad Hardware
+// License, Version 0.51 (the "License"); you may not use this file except in
+// compliance with the License.  You may obtain a copy of the License at
+// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
+// or agreed to in writing, software, hardware and materials distributed under
+// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
+// CONDITIONS OF ANY KIND, either express or implied. See the License for the
+// specific language governing permissions and limitations under the License.
+
+module cv32e40px_clock_gate (
+    input  logic clk_i,
+    input  logic en_i,
+    input  logic scan_cg_en_i,
+    output logic clk_o
+);
+
+  xilinx_clk_gating clk_gate_i (
+      .clk_i,
+      .en_i,
+      .test_en_i(scan_cg_en_i),
+      .clk_o
+  );
+
+endmodule  // cv32e40p_clock_gate
diff --git a/hw/vendor/esl_epfl_cv32e40px.core b/hw/vendor/esl_epfl_cv32e40px.core
index 0373fed05..56a485a41 100644
--- a/hw/vendor/esl_epfl_cv32e40px.core
+++ b/hw/vendor/esl_epfl_cv32e40px.core
@@ -38,7 +38,7 @@ filesets:
     - esl_epfl_cv32e40px/rtl/cv32e40px_sleep_unit.sv
     - esl_epfl_cv32e40px/rtl/cv32e40px_core.sv
     - esl_epfl_cv32e40px/rtl/cv32e40px_apu_disp.sv
-    - esl_epfl_cv32e40px/rtl/cv32e40px_x_disp
+    - esl_epfl_cv32e40px/rtl/cv32e40px_x_disp.sv
     - esl_epfl_cv32e40px/rtl/cv32e40px_fifo.sv
     - esl_epfl_cv32e40px/rtl/cv32e40px_fp_wrapper.sv
     - esl_epfl_cv32e40px/rtl/cv32e40px_top.sv