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add dips / better sound / dock detection
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@ericlewis
ericlewis committed Oct 11, 2022
1 parent 5f65e81 commit e502ac2
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Showing 14 changed files with 218 additions and 151 deletions.
Binary file modified dist/Cores/ericlewis.SpaceRace/bitstream.rbf_r
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32 changes: 8 additions & 24 deletions dist/Cores/ericlewis.SpaceRace/interact.json
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Expand Up @@ -3,46 +3,30 @@
"magic": "APF_VER_1",
"variables": [
{
"id": 1,
"name": "Use Ctrl 2 for P2",
"name": "2 Credits Per Coin",
"id": 2,
"type": "check",
"enabled": true,
"persist": true,
"writeonly": true,
"address": "0x00300000",
"address": "0x00400000",
"defaultval": 0,
"value": 1
},
{
"name": "Credit Per Coin",
"id": 2,
"type": "slider_u32",
"enabled": true,
"persist": true,
"writeonly": true,
"address": "0x00400000",
"defaultval": 2,
"graphical": {
"min": 1,
"max": 2,
"adjust_small": 1,
"adjust_large": 1
}
},
{
"name": "Playtime [%]",
"name": "Playtime",
"id": 3,
"type": "slider_u32",
"enabled": true,
"persist": true,
"writeonly": true,
"address": "0x00500000",
"defaultval": 100,
"defaultval": 10,
"graphical": {
"min": 0,
"max": 100,
"adjust_small": 10,
"adjust_large": 20
"max": 10,
"adjust_small": 1,
"adjust_large": 2
}
}
],
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1 change: 1 addition & 0 deletions src/fpga/ap_core.qsf
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Expand Up @@ -737,6 +737,7 @@ set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top

# end ENTITY(mf_pllbase_0002)
# ---------------------------
set_global_assignment -name SYSTEMVERILOG_FILE core/sync_fifo.sv
set_global_assignment -name SYSTEMVERILOG_FILE core/sound_i2s.sv
set_global_assignment -name SYSTEMVERILOG_FILE core/core_top.sv
set_global_assignment -name SYSTEMVERILOG_FILE core/rtl/videosync.sv
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9 changes: 4 additions & 5 deletions src/fpga/apf/apf_top.v
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Expand Up @@ -280,10 +280,10 @@ mf_ddio_bidir_12 isclk(


// controller data (pad) controller.
wire [15:0] cont1_key;
wire [15:0] cont2_key;
wire [15:0] cont3_key;
wire [15:0] cont4_key;
wire [31:0] cont1_key;
wire [31:0] cont2_key;
wire [31:0] cont3_key;
wire [31:0] cont4_key;
wire [31:0] cont1_joy;
wire [31:0] cont2_joy;
wire [31:0] cont3_joy;
Expand Down Expand Up @@ -472,4 +472,3 @@ core_top ic (
);

endmodule

6 changes: 3 additions & 3 deletions src/fpga/apf/build_id.mif
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Expand Up @@ -9,8 +9,8 @@ DATA_RADIX = HEX;
CONTENT
BEGIN

0E0 : 20220916;
0E1 : 00080124;
0E2 : a7ddf1b2;
0E0 : 20221011;
0E1 : 00125820;
0E2 : 0f5bd7d6;

END;
2 changes: 1 addition & 1 deletion src/fpga/apf/common.v
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Expand Up @@ -153,4 +153,4 @@ always @(posedge b_clk) begin
b_dout <= mem[b_addr];
end

endmodule
endmodule
2 changes: 1 addition & 1 deletion src/fpga/apf/io_bridge_peripheral.v
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Expand Up @@ -331,4 +331,4 @@ always @(posedge phy_spiclk or posedge phy_spiss) begin
end
end

endmodule
endmodule
18 changes: 9 additions & 9 deletions src/fpga/apf/io_pad_controller.v
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Expand Up @@ -45,10 +45,10 @@ input wire reset_n,

inout reg pad_1wire,

output reg [15:0] cont1_key,
output reg [15:0] cont2_key,
output reg [15:0] cont3_key,
output reg [15:0] cont4_key,
output reg [31:0] cont1_key,
output reg [31:0] cont2_key,
output reg [31:0] cont3_key,
output reg [31:0] cont4_key,
output reg [31:0] cont1_joy,
output reg [31:0] cont2_joy,
output reg [31:0] cont3_joy,
Expand Down Expand Up @@ -140,19 +140,19 @@ always @(posedge clk) begin
if(rx_word_done) begin
cnt <= cnt + 1'b1;
case(cnt)
0: cont1_key <= rx_word[15:0];
0: cont1_key <= rx_word;
1: cont1_joy <= rx_word;
2: cont1_trig <= rx_word[15:0];

3: cont2_key <= rx_word[15:0];
3: cont2_key <= rx_word;
4: cont2_joy <= rx_word;
5: cont2_trig <= rx_word[15:0];

6: cont3_key <= rx_word[15:0];
6: cont3_key <= rx_word;
7: cont3_joy <= rx_word;
8: cont3_trig <= rx_word[15:0];

9: cont4_key <= rx_word[15:0];
9: cont4_key <= rx_word;
10: cont4_joy <= rx_word;
11: begin
cont4_trig <= rx_word[15:0];
Expand Down Expand Up @@ -325,4 +325,4 @@ always @(posedge clk) begin
if(~reset_n_s | ~reset_tr_n) tr_state <= TR_IDLE;
end

endmodule
endmodule
95 changes: 23 additions & 72 deletions src/fpga/core/core_top.sv
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Expand Up @@ -209,10 +209,10 @@ input wire [31:0] bridge_wr_data,
// [ 7: 0] ltrig
// [15: 8] rtrig
//
input wire [15:0] cont1_key,
input wire [15:0] cont2_key,
input wire [15:0] cont3_key,
input wire [15:0] cont4_key,
input wire [31:0] cont1_key,
input wire [31:0] cont2_key,
input wire [31:0] cont3_key,
input wire [31:0] cont4_key,
input wire [31:0] cont1_joy,
input wire [31:0] cont2_joy,
input wire [31:0] cont3_joy,
Expand Down Expand Up @@ -461,19 +461,16 @@ mf_pllbase mp1 (
// Core Settings
////////////////////////////////////////////

reg disable_p2_on_pad_1 = 0;
wire disable_p2_on_pad_1 = cont1_key_s[31:29];
reg COINAGE = 1'b0;
reg [3:0] PLAYTIME = 4'd10;

always @(posedge clk_74a)
begin
if(bridge_wr) begin
casex(bridge_addr)
32'h00300000: begin
disable_p2_on_pad_1 <= bridge_wr_data[0:0];
end
32'h00400000: begin
COINAGE <= bridge_wr_data[0:0];
COINAGE <= bridge_wr_data[0];
end
32'h00500000: begin
PLAYTIME <= bridge_wr_data[3:0];
Expand All @@ -494,9 +491,6 @@ wire HSYNC, VSYNC, HBLANK, VBLANK;

wire [7:0] video = (VIDEO ? 8'd255 : (SCORE ? 8'd187 : 8'd0));

// Does not do anything - just to satisfy the top.
wire CLK_CORE_VIDEO;

//
// Video cleanup
// APF scaler requires HSync and VSync to last for a single clock, and video_rgb to be 0 when video_de is low
Expand Down Expand Up @@ -538,80 +532,38 @@ end

wire [15:0] SOUND;

assign audio_mclk = audgen_mclk;
assign audio_dac = audgen_dac;
assign audio_lrck = audgen_lrck;

reg audgen_nextsamp;

// generate MCLK = 12.288mhz with fractional accumulator
reg [21:0] audgen_accum;
reg audgen_mclk;
parameter [20:0] CYCLE_48KHZ = 21'd122880 * 2;
always @(posedge clk_74a)
begin
audgen_accum <= audgen_accum + CYCLE_48KHZ;
if(audgen_accum >= 21'd742500) begin
audgen_mclk <= ~audgen_mclk;
audgen_accum <= audgen_accum - 21'd742500 + CYCLE_48KHZ;
end
end

// generate SCLK = 3.072mhz by dividing MCLK by 4
reg [1:0] aud_mclk_divider;
wire audgen_sclk = aud_mclk_divider[1] /* synthesis keep*/;
always @(posedge audgen_mclk) begin
aud_mclk_divider <= aud_mclk_divider + 1'b1;
end

// shift out audio data as I2S
// 32 total bits per channel, but only 16 active bits at the start and then 16 dummy bits
//
// synchronize audio samples coming from the core
wire [31:0] audgen_sampdata_s;
synch_3 #(.WIDTH(32)) s5({SOUND, SOUND}, audgen_sampdata_s, audgen_sclk);
reg [31:0] audgen_sampshift;
reg [4:0] audgen_lrck_cnt;
reg audgen_lrck;
reg audgen_dac;
always @(negedge audgen_sclk) begin
// output the next bit
audgen_dac <= audgen_sampshift[31];

// 48khz * 64
audgen_lrck_cnt <= audgen_lrck_cnt + 1'b1;
if(audgen_lrck_cnt == 31) begin
// switch channels
audgen_lrck <= ~audgen_lrck;

// Reload sample shifter
if(~audgen_lrck) begin
audgen_sampshift <= audgen_sampdata_s;
end
end else if(audgen_lrck_cnt < 16) begin
// only shift for 16 clocks per channel
audgen_sampshift <= {audgen_sampshift[30:0], 1'b0};
end
end
sound_i2s #(
.CHANNEL_WIDTH(16),
.SIGNED_INPUT (1)
) sound_i2s (
.clk_74a(clk_74a),
.clk_audio(clk_sys),

.audio_l(SOUND),
.audio_r(SOUND),

.audio_mclk(audio_mclk),
.audio_lrck(audio_lrck),
.audio_dac(audio_dac)
);

////////////////////////////////////////////
// Core Controls
////////////////////////////////////////////

wire [15:0] cont1_key_s;
wire [15:0] cont2_key_s;
wire [31:0] cont1_key_s;
wire [31:0] cont2_key_s;

synch_2 #(
.WIDTH(16)
.WIDTH(32)
) cont1_s (
cont1_key,
cont1_key_s,
clk_sys
);

synch_2 #(
.WIDTH(16)
.WIDTH(32)
) cont2_s (
cont2_key,
cont2_key_s,
Expand Down Expand Up @@ -666,7 +618,6 @@ space_race_top space_race_top(
.START_GAME,
.UP1_N, .DOWN1_N,
.UP2_N, .DOWN2_N,
.CLK_VIDEO(CLK_CORE_VIDEO),
.VIDEO, .SCORE,
.HSYNC, .VSYNC,
.HBLANK, .VBLANK,
Expand Down
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