From a84a9313f019661941c9304dc7aab6ac5736ffa5 Mon Sep 17 00:00:00 2001
From: Robin Hundt <24554122+robinhundt@users.noreply.github.com>
Date: Mon, 5 Feb 2024 13:42:26 +0100
Subject: [PATCH] SEEC: Use low-depth adder in mixed-gmw

---
 Cargo.lock                                   |   7 +
 crates/seec-channel/src/tcp.rs               |   3 +
 crates/seec/Cargo.toml                       |   1 +
 crates/seec/circuits/int_add16_depth.bristol | 128 ++++
 crates/seec/circuits/int_add32_depth.bristol | 304 ++++++++
 crates/seec/circuits/int_add64_depth.bristol | 704 +++++++++++++++++++
 crates/seec/circuits/int_add8_depth.bristol  |  52 ++
 crates/seec/src/circuit/base_circuit.rs      |  26 +-
 crates/seec/src/circuit/mod.rs               |  17 +-
 crates/seec/src/executor.rs                  |  18 +-
 crates/seec/src/mul_triple/storage.rs        |   3 +
 crates/seec/src/parse/fuse/mod.rs            |  13 +-
 crates/seec/src/private_test_utils.rs        |  20 +-
 crates/seec/src/protocols/aby2.rs            |   3 +-
 crates/seec/src/protocols/mixed_gmw.rs       |  67 +-
 crates/seec/src/protocols/tensor_aby2.rs     |   3 +-
 16 files changed, 1339 insertions(+), 30 deletions(-)
 create mode 100644 crates/seec/circuits/int_add16_depth.bristol
 create mode 100644 crates/seec/circuits/int_add32_depth.bristol
 create mode 100644 crates/seec/circuits/int_add64_depth.bristol
 create mode 100644 crates/seec/circuits/int_add8_depth.bristol

diff --git a/Cargo.lock b/Cargo.lock
index 5b06e9f..740b4bd 100644
--- a/Cargo.lock
+++ b/Cargo.lock
@@ -2045,6 +2045,7 @@ dependencies = [
  "tracing-appender",
  "tracing-subscriber",
  "typemap",
+ "typemap_rev",
  "zappot",
 ]
 
@@ -2528,6 +2529,12 @@ dependencies = [
  "unsafe-any",
 ]
 
+[[package]]
+name = "typemap_rev"
+version = "0.3.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "74b08b0c1257381af16a5c3605254d529d3e7e109f3c62befc5d168968192998"
+
 [[package]]
 name = "typenum"
 version = "1.17.0"
diff --git a/crates/seec-channel/src/tcp.rs b/crates/seec-channel/src/tcp.rs
index 8381208..80a7b92 100644
--- a/crates/seec-channel/src/tcp.rs
+++ b/crates/seec-channel/src/tcp.rs
@@ -134,11 +134,14 @@ mod tests {
     use crate::tcp::new_local_pair;
     use remoc::codec;
     use remoc::rch::mpsc::channel;
+    use std::time::Duration;
 
     #[tokio::test]
     async fn establish_connection() {
         let (ch1, ch2) = new_local_pair::<()>(None).await.unwrap();
 
+        // Sleep to ensure values have been actually sent and counters are correct
+        tokio::time::sleep(Duration::from_millis(10)).await;
         let (_tx1, bytes_written1, _rx1, bytes_read1) = ch1;
         let (_tx2, bytes_written2, _rx2, bytes_read2) = ch2;
         assert_eq!(bytes_written1.get(), bytes_read2.get());
diff --git a/crates/seec/Cargo.toml b/crates/seec/Cargo.toml
index c9df1e1..32db71e 100644
--- a/crates/seec/Cargo.toml
+++ b/crates/seec/Cargo.toml
@@ -68,6 +68,7 @@ seec-channel = { path = "../seec-channel" }
 remoc = { workspace = true }
 zappot = { path = "../zappot" }
 typemap = "0.3.3"
+typemap_rev = "0.3.0"
 seec-bitmatrix = { path = "../seec-bitmatrix" }
 either = "1.10.0"
 flatbuffers = "23.5.26"
diff --git a/crates/seec/circuits/int_add16_depth.bristol b/crates/seec/circuits/int_add16_depth.bristol
new file mode 100644
index 0000000..2a95757
--- /dev/null
+++ b/crates/seec/circuits/int_add16_depth.bristol
@@ -0,0 +1,128 @@
+125 157
+16 16 16
+
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+2 1 1 17 32 XOR
+2 1 0 16 33 AND
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+2 1 2 18 34 XOR
+2 1 1 17 35 AND
+2 1 32 33 36 AND
+2 1 35 36 37 XOR
+2 1 34 37 143 XOR
+2 1 3 19 38 XOR
+2 1 2 18 39 AND
+2 1 34 35 40 AND
+2 1 39 40 41 XOR
+2 1 34 32 42 AND
+2 1 42 33 43 AND
+2 1 41 43 44 XOR
+2 1 38 44 144 XOR
+2 1 4 20 45 XOR
+2 1 3 19 46 AND
+2 1 38 44 47 AND
+2 1 46 47 48 XOR
+2 1 45 48 145 XOR
+2 1 5 21 49 XOR
+2 1 4 20 50 AND
+2 1 45 46 51 AND
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+2 1 45 38 53 AND
+2 1 53 44 54 AND
+2 1 52 54 55 XOR
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+2 1 5 21 57 AND
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+2 1 49 53 60 AND
+2 1 60 44 61 AND
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diff --git a/crates/seec/circuits/int_add32_depth.bristol b/crates/seec/circuits/int_add32_depth.bristol
new file mode 100644
index 0000000..de5c4ef
--- /dev/null
+++ b/crates/seec/circuits/int_add32_depth.bristol
@@ -0,0 +1,304 @@
+301 365
+32 32 32
+
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diff --git a/crates/seec/circuits/int_add64_depth.bristol b/crates/seec/circuits/int_add64_depth.bristol
new file mode 100644
index 0000000..80dd95b
--- /dev/null
+++ b/crates/seec/circuits/int_add64_depth.bristol
@@ -0,0 +1,704 @@
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+
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+2 1 338 340 341 XOR
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+2 1 332 344 792 XOR
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+2 1 332 339 349 AND
+2 1 349 301 350 AND
+2 1 348 350 351 XOR
+2 1 349 302 352 AND
+2 1 352 236 353 AND
+2 1 351 353 354 XOR
+2 1 345 354 793 XOR
+2 1 29 93 355 XOR
+2 1 28 92 356 AND
+2 1 345 346 357 AND
+2 1 356 357 358 XOR
+2 1 345 332 359 AND
+2 1 359 338 360 AND
+2 1 358 360 361 XOR
+2 1 359 339 362 AND
+2 1 362 301 363 AND
+2 1 361 363 364 XOR
+2 1 362 302 365 AND
+2 1 365 236 366 AND
+2 1 364 366 367 XOR
+2 1 355 367 794 XOR
+2 1 30 94 368 XOR
+2 1 29 93 369 AND
+2 1 355 358 370 AND
+2 1 369 370 371 XOR
+2 1 355 359 372 AND
+2 1 372 338 373 AND
+2 1 371 373 374 XOR
+2 1 372 339 375 AND
+2 1 375 301 376 AND
+2 1 374 376 377 XOR
+2 1 375 302 378 AND
+2 1 378 236 379 AND
+2 1 377 379 380 XOR
+2 1 368 380 795 XOR
+2 1 31 95 381 XOR
+2 1 30 94 382 AND
+2 1 368 369 383 AND
+2 1 382 383 384 XOR
+2 1 368 355 385 AND
+2 1 385 358 386 AND
+2 1 384 386 387 XOR
+2 1 385 359 388 AND
+2 1 388 338 389 AND
+2 1 387 389 390 XOR
+2 1 388 339 391 AND
+2 1 391 301 392 AND
+2 1 390 392 393 XOR
+2 1 391 302 394 AND
+2 1 394 236 395 AND
+2 1 393 395 396 XOR
+2 1 381 396 796 XOR
+2 1 32 96 397 XOR
+2 1 31 95 398 AND
+2 1 381 396 399 AND
+2 1 398 399 400 XOR
+2 1 397 400 797 XOR
+2 1 33 97 401 XOR
+2 1 32 96 402 AND
+2 1 397 398 403 AND
+2 1 402 403 404 XOR
+2 1 397 381 405 AND
+2 1 405 396 406 AND
+2 1 404 406 407 XOR
+2 1 401 407 798 XOR
+2 1 34 98 408 XOR
+2 1 33 97 409 AND
+2 1 401 404 410 AND
+2 1 409 410 411 XOR
+2 1 401 405 412 AND
+2 1 412 396 413 AND
+2 1 411 413 414 XOR
+2 1 408 414 799 XOR
+2 1 35 99 415 XOR
+2 1 34 98 416 AND
+2 1 408 409 417 AND
+2 1 416 417 418 XOR
+2 1 408 401 419 AND
+2 1 419 404 420 AND
+2 1 418 420 421 XOR
+2 1 419 405 422 AND
+2 1 422 396 423 AND
+2 1 421 423 424 XOR
+2 1 415 424 800 XOR
+2 1 36 100 425 XOR
+2 1 35 99 426 AND
+2 1 415 421 427 AND
+2 1 426 427 428 XOR
+2 1 415 422 429 AND
+2 1 429 396 430 AND
+2 1 428 430 431 XOR
+2 1 425 431 801 XOR
+2 1 37 101 432 XOR
+2 1 36 100 433 AND
+2 1 425 426 434 AND
+2 1 433 434 435 XOR
+2 1 425 415 436 AND
+2 1 436 421 437 AND
+2 1 435 437 438 XOR
+2 1 436 422 439 AND
+2 1 439 396 440 AND
+2 1 438 440 441 XOR
+2 1 432 441 802 XOR
+2 1 38 102 442 XOR
+2 1 37 101 443 AND
+2 1 432 435 444 AND
+2 1 443 444 445 XOR
+2 1 432 436 446 AND
+2 1 446 421 447 AND
+2 1 445 447 448 XOR
+2 1 446 422 449 AND
+2 1 449 396 450 AND
+2 1 448 450 451 XOR
+2 1 442 451 803 XOR
+2 1 39 103 452 XOR
+2 1 38 102 453 AND
+2 1 442 443 454 AND
+2 1 453 454 455 XOR
+2 1 442 432 456 AND
+2 1 456 435 457 AND
+2 1 455 457 458 XOR
+2 1 456 436 459 AND
+2 1 459 421 460 AND
+2 1 458 460 461 XOR
+2 1 459 422 462 AND
+2 1 462 396 463 AND
+2 1 461 463 464 XOR
+2 1 452 464 804 XOR
+2 1 40 104 465 XOR
+2 1 39 103 466 AND
+2 1 452 461 467 AND
+2 1 466 467 468 XOR
+2 1 452 462 469 AND
+2 1 469 396 470 AND
+2 1 468 470 471 XOR
+2 1 465 471 805 XOR
+2 1 41 105 472 XOR
+2 1 40 104 473 AND
+2 1 465 466 474 AND
+2 1 473 474 475 XOR
+2 1 465 452 476 AND
+2 1 476 461 477 AND
+2 1 475 477 478 XOR
+2 1 476 462 479 AND
+2 1 479 396 480 AND
+2 1 478 480 481 XOR
+2 1 472 481 806 XOR
+2 1 42 106 482 XOR
+2 1 41 105 483 AND
+2 1 472 475 484 AND
+2 1 483 484 485 XOR
+2 1 472 476 486 AND
+2 1 486 461 487 AND
+2 1 485 487 488 XOR
+2 1 486 462 489 AND
+2 1 489 396 490 AND
+2 1 488 490 491 XOR
+2 1 482 491 807 XOR
+2 1 43 107 492 XOR
+2 1 42 106 493 AND
+2 1 482 483 494 AND
+2 1 493 494 495 XOR
+2 1 482 472 496 AND
+2 1 496 475 497 AND
+2 1 495 497 498 XOR
+2 1 496 476 499 AND
+2 1 499 461 500 AND
+2 1 498 500 501 XOR
+2 1 499 462 502 AND
+2 1 502 396 503 AND
+2 1 501 503 504 XOR
+2 1 492 504 808 XOR
+2 1 44 108 505 XOR
+2 1 43 107 506 AND
+2 1 492 498 507 AND
+2 1 506 507 508 XOR
+2 1 492 499 509 AND
+2 1 509 461 510 AND
+2 1 508 510 511 XOR
+2 1 509 462 512 AND
+2 1 512 396 513 AND
+2 1 511 513 514 XOR
+2 1 505 514 809 XOR
+2 1 45 109 515 XOR
+2 1 44 108 516 AND
+2 1 505 506 517 AND
+2 1 516 517 518 XOR
+2 1 505 492 519 AND
+2 1 519 498 520 AND
+2 1 518 520 521 XOR
+2 1 519 499 522 AND
+2 1 522 461 523 AND
+2 1 521 523 524 XOR
+2 1 522 462 525 AND
+2 1 525 396 526 AND
+2 1 524 526 527 XOR
+2 1 515 527 810 XOR
+2 1 46 110 528 XOR
+2 1 45 109 529 AND
+2 1 515 518 530 AND
+2 1 529 530 531 XOR
+2 1 515 519 532 AND
+2 1 532 498 533 AND
+2 1 531 533 534 XOR
+2 1 532 499 535 AND
+2 1 535 461 536 AND
+2 1 534 536 537 XOR
+2 1 535 462 538 AND
+2 1 538 396 539 AND
+2 1 537 539 540 XOR
+2 1 528 540 811 XOR
+2 1 47 111 541 XOR
+2 1 46 110 542 AND
+2 1 528 529 543 AND
+2 1 542 543 544 XOR
+2 1 528 515 545 AND
+2 1 545 518 546 AND
+2 1 544 546 547 XOR
+2 1 545 519 548 AND
+2 1 548 498 549 AND
+2 1 547 549 550 XOR
+2 1 548 499 551 AND
+2 1 551 461 552 AND
+2 1 550 552 553 XOR
+2 1 551 462 554 AND
+2 1 554 396 555 AND
+2 1 553 555 556 XOR
+2 1 541 556 812 XOR
+2 1 48 112 557 XOR
+2 1 47 111 558 AND
+2 1 541 553 559 AND
+2 1 558 559 560 XOR
+2 1 541 554 561 AND
+2 1 561 396 562 AND
+2 1 560 562 563 XOR
+2 1 557 563 813 XOR
+2 1 49 113 564 XOR
+2 1 48 112 565 AND
+2 1 557 558 566 AND
+2 1 565 566 567 XOR
+2 1 557 541 568 AND
+2 1 568 553 569 AND
+2 1 567 569 570 XOR
+2 1 568 554 571 AND
+2 1 571 396 572 AND
+2 1 570 572 573 XOR
+2 1 564 573 814 XOR
+2 1 50 114 574 XOR
+2 1 49 113 575 AND
+2 1 564 567 576 AND
+2 1 575 576 577 XOR
+2 1 564 568 578 AND
+2 1 578 553 579 AND
+2 1 577 579 580 XOR
+2 1 578 554 581 AND
+2 1 581 396 582 AND
+2 1 580 582 583 XOR
+2 1 574 583 815 XOR
+2 1 51 115 584 XOR
+2 1 50 114 585 AND
+2 1 574 575 586 AND
+2 1 585 586 587 XOR
+2 1 574 564 588 AND
+2 1 588 567 589 AND
+2 1 587 589 590 XOR
+2 1 588 568 591 AND
+2 1 591 553 592 AND
+2 1 590 592 593 XOR
+2 1 591 554 594 AND
+2 1 594 396 595 AND
+2 1 593 595 596 XOR
+2 1 584 596 816 XOR
+2 1 52 116 597 XOR
+2 1 51 115 598 AND
+2 1 584 590 599 AND
+2 1 598 599 600 XOR
+2 1 584 591 601 AND
+2 1 601 553 602 AND
+2 1 600 602 603 XOR
+2 1 601 554 604 AND
+2 1 604 396 605 AND
+2 1 603 605 606 XOR
+2 1 597 606 817 XOR
+2 1 53 117 607 XOR
+2 1 52 116 608 AND
+2 1 597 598 609 AND
+2 1 608 609 610 XOR
+2 1 597 584 611 AND
+2 1 611 590 612 AND
+2 1 610 612 613 XOR
+2 1 611 591 614 AND
+2 1 614 553 615 AND
+2 1 613 615 616 XOR
+2 1 614 554 617 AND
+2 1 617 396 618 AND
+2 1 616 618 619 XOR
+2 1 607 619 818 XOR
+2 1 54 118 620 XOR
+2 1 53 117 621 AND
+2 1 607 610 622 AND
+2 1 621 622 623 XOR
+2 1 607 611 624 AND
+2 1 624 590 625 AND
+2 1 623 625 626 XOR
+2 1 624 591 627 AND
+2 1 627 553 628 AND
+2 1 626 628 629 XOR
+2 1 627 554 630 AND
+2 1 630 396 631 AND
+2 1 629 631 632 XOR
+2 1 620 632 819 XOR
+2 1 55 119 633 XOR
+2 1 54 118 634 AND
+2 1 620 621 635 AND
+2 1 634 635 636 XOR
+2 1 620 607 637 AND
+2 1 637 610 638 AND
+2 1 636 638 639 XOR
+2 1 637 611 640 AND
+2 1 640 590 641 AND
+2 1 639 641 642 XOR
+2 1 640 591 643 AND
+2 1 643 553 644 AND
+2 1 642 644 645 XOR
+2 1 643 554 646 AND
+2 1 646 396 647 AND
+2 1 645 647 648 XOR
+2 1 633 648 820 XOR
+2 1 56 120 649 XOR
+2 1 55 119 650 AND
+2 1 633 642 651 AND
+2 1 650 651 652 XOR
+2 1 633 643 653 AND
+2 1 653 553 654 AND
+2 1 652 654 655 XOR
+2 1 653 554 656 AND
+2 1 656 396 657 AND
+2 1 655 657 658 XOR
+2 1 649 658 821 XOR
+2 1 57 121 659 XOR
+2 1 56 120 660 AND
+2 1 649 650 661 AND
+2 1 660 661 662 XOR
+2 1 649 633 663 AND
+2 1 663 642 664 AND
+2 1 662 664 665 XOR
+2 1 663 643 666 AND
+2 1 666 553 667 AND
+2 1 665 667 668 XOR
+2 1 666 554 669 AND
+2 1 669 396 670 AND
+2 1 668 670 671 XOR
+2 1 659 671 822 XOR
+2 1 58 122 672 XOR
+2 1 57 121 673 AND
+2 1 659 662 674 AND
+2 1 673 674 675 XOR
+2 1 659 663 676 AND
+2 1 676 642 677 AND
+2 1 675 677 678 XOR
+2 1 676 643 679 AND
+2 1 679 553 680 AND
+2 1 678 680 681 XOR
+2 1 679 554 682 AND
+2 1 682 396 683 AND
+2 1 681 683 684 XOR
+2 1 672 684 823 XOR
+2 1 59 123 685 XOR
+2 1 58 122 686 AND
+2 1 672 673 687 AND
+2 1 686 687 688 XOR
+2 1 672 659 689 AND
+2 1 689 662 690 AND
+2 1 688 690 691 XOR
+2 1 689 663 692 AND
+2 1 692 642 693 AND
+2 1 691 693 694 XOR
+2 1 692 643 695 AND
+2 1 695 553 696 AND
+2 1 694 696 697 XOR
+2 1 695 554 698 AND
+2 1 698 396 699 AND
+2 1 697 699 700 XOR
+2 1 685 700 824 XOR
+2 1 60 124 701 XOR
+2 1 59 123 702 AND
+2 1 685 691 703 AND
+2 1 702 703 704 XOR
+2 1 685 692 705 AND
+2 1 705 642 706 AND
+2 1 704 706 707 XOR
+2 1 705 643 708 AND
+2 1 708 553 709 AND
+2 1 707 709 710 XOR
+2 1 708 554 711 AND
+2 1 711 396 712 AND
+2 1 710 712 713 XOR
+2 1 701 713 825 XOR
+2 1 61 125 714 XOR
+2 1 60 124 715 AND
+2 1 701 702 716 AND
+2 1 715 716 717 XOR
+2 1 701 685 718 AND
+2 1 718 691 719 AND
+2 1 717 719 720 XOR
+2 1 718 692 721 AND
+2 1 721 642 722 AND
+2 1 720 722 723 XOR
+2 1 721 643 724 AND
+2 1 724 553 725 AND
+2 1 723 725 726 XOR
+2 1 724 554 727 AND
+2 1 727 396 728 AND
+2 1 726 728 729 XOR
+2 1 714 729 826 XOR
+2 1 62 126 730 XOR
+2 1 61 125 731 AND
+2 1 714 717 732 AND
+2 1 731 732 733 XOR
+2 1 714 718 734 AND
+2 1 734 691 735 AND
+2 1 733 735 736 XOR
+2 1 734 692 737 AND
+2 1 737 642 738 AND
+2 1 736 738 739 XOR
+2 1 737 643 740 AND
+2 1 740 553 741 AND
+2 1 739 741 742 XOR
+2 1 740 554 743 AND
+2 1 743 396 744 AND
+2 1 742 744 745 XOR
+2 1 730 745 827 XOR
+2 1 63 127 746 XOR
+2 1 62 126 747 AND
+2 1 730 731 748 AND
+2 1 747 748 749 XOR
+2 1 730 714 750 AND
+2 1 750 717 751 AND
+2 1 749 751 752 XOR
+2 1 750 718 753 AND
+2 1 753 691 754 AND
+2 1 752 754 755 XOR
+2 1 753 692 756 AND
+2 1 756 642 757 AND
+2 1 755 757 758 XOR
+2 1 756 643 759 AND
+2 1 759 553 760 AND
+2 1 758 760 761 XOR
+2 1 759 554 762 AND
+2 1 762 396 763 AND
+2 1 761 763 764 XOR
+2 1 746 764 828 XOR
diff --git a/crates/seec/circuits/int_add8_depth.bristol b/crates/seec/circuits/int_add8_depth.bristol
new file mode 100644
index 0000000..775db71
--- /dev/null
+++ b/crates/seec/circuits/int_add8_depth.bristol
@@ -0,0 +1,52 @@
+49 65
+8 8 8
+
+2 1 0 8 57 XOR
+2 1 1 9 16 XOR
+2 1 0 8 17 AND
+2 1 16 17 58 XOR
+2 1 2 10 18 XOR
+2 1 1 9 19 AND
+2 1 16 17 20 AND
+2 1 19 20 21 XOR
+2 1 18 21 59 XOR
+2 1 3 11 22 XOR
+2 1 2 10 23 AND
+2 1 18 19 24 AND
+2 1 23 24 25 XOR
+2 1 18 16 26 AND
+2 1 26 17 27 AND
+2 1 25 27 28 XOR
+2 1 22 28 60 XOR
+2 1 4 12 29 XOR
+2 1 3 11 30 AND
+2 1 22 28 31 AND
+2 1 30 31 32 XOR
+2 1 29 32 61 XOR
+2 1 5 13 33 XOR
+2 1 4 12 34 AND
+2 1 29 30 35 AND
+2 1 34 35 36 XOR
+2 1 29 22 37 AND
+2 1 37 28 38 AND
+2 1 36 38 39 XOR
+2 1 33 39 62 XOR
+2 1 6 14 40 XOR
+2 1 5 13 41 AND
+2 1 33 36 42 AND
+2 1 41 42 43 XOR
+2 1 33 37 44 AND
+2 1 44 28 45 AND
+2 1 43 45 46 XOR
+2 1 40 46 63 XOR
+2 1 7 15 47 XOR
+2 1 6 14 48 AND
+2 1 40 41 49 AND
+2 1 48 49 50 XOR
+2 1 40 33 51 AND
+2 1 51 36 52 AND
+2 1 50 52 53 XOR
+2 1 51 37 54 AND
+2 1 54 28 55 AND
+2 1 53 55 56 XOR
+2 1 47 56 64 XOR
diff --git a/crates/seec/src/circuit/base_circuit.rs b/crates/seec/src/circuit/base_circuit.rs
index 482f2de..e2f43c1 100644
--- a/crates/seec/src/circuit/base_circuit.rs
+++ b/crates/seec/src/circuit/base_circuit.rs
@@ -55,6 +55,8 @@ pub enum BaseGate<T, D = ScalarDim> {
     /// Connects a sub circuit to the main circuit and selects the i'th individual value from
     /// the SIMD output
     ConnectToMainFromSimd((D, u32)),
+    /// Identity gate, simply outputs its input
+    Identity,
     Constant(T),
     Debug,
 }
@@ -117,7 +119,7 @@ impl<G: Gate, Idx: GateIdx, W: Wire> BaseCircuit<G, Idx, W> {
                 BaseGate::SubCircuitInput(_)
                 | BaseGate::ConnectToMain(_)
                 | BaseGate::ConnectToMainFromSimd(_) => self.sub_circuit_input_gates.push(gate_id),
-                BaseGate::Debug => (/* nothing special to do */),
+                BaseGate::Debug | BaseGate::Identity => (/* nothing special to do */),
             }
         }
         if gate.is_interactive() {
@@ -223,6 +225,14 @@ impl<G: Gate, Idx: GateIdx> BaseCircuit<G, Idx, ()> {
         );
         let mut gate_id_map = vec![GateId::default(); circuit.gate_count()];
         for (gate, id) in circuit.iter() {
+            // Map ScInput/Output gates to identity gates. Otherwise, we can't add_sub_circuit a circuit
+            // which itself was built using add_sub_circuit
+            let gate = match gate.as_base_gate() {
+                Some(BaseGate::SubCircuitInput(_) | BaseGate::SubCircuitOutput(_)) => {
+                    G::wrap_base_gate(BaseGate::Identity)
+                }
+                _ => gate,
+            };
             let new_id = self.add_gate(gate);
             gate_id_map[id.as_usize()] = new_id;
             for parent in circuit.parent_gates(id) {
@@ -309,7 +319,7 @@ where
     Share: Clone,
     G: Gate<Share = Share> + From<BaseGate<Share>> + for<'a> From<&'a bristol::Gate>,
 {
-    #[tracing::instrument(skip(bristol))]
+    #[tracing::instrument(skip(bristol), ret)]
     pub fn from_bristol(bristol: bristol::Circuit, load: Load) -> Result<Self, CircuitError> {
         info!(
             "Converting bristol circuit with header: {:?}",
@@ -464,7 +474,8 @@ impl<T: Share, D: Dimension> Gate for BaseGate<T, D> {
             | Self::Input(_)
             | Self::SubCircuitInput(_)
             | Self::SubCircuitOutput(_)
-            | Self::ConnectToMain(_) => inputs
+            | Self::ConnectToMain(_)
+            | Self::Identity => inputs
                 .next()
                 .unwrap_or_else(|| panic!("Empty input for {self:?}")),
             Self::ConnectToMainFromSimd(_) => {
@@ -488,12 +499,9 @@ impl<T: Share, D: Dimension> Gate for BaseGate<T, D> {
             | BaseGate::Input(_)
             | BaseGate::ConnectToMain(_)
             | BaseGate::SubCircuitInput(_)
-            | BaseGate::ConnectToMainFromSimd(_) => {
-                inputs.next().expect("Missing input to {self:?}").clone()
-            }
-            BaseGate::SubCircuitOutput(_) => {
-                inputs.next().expect("Missing input to {self:?}").clone()
-            }
+            | BaseGate::SubCircuitOutput(_)
+            | BaseGate::ConnectToMainFromSimd(_)
+            | BaseGate::Identity => inputs.next().expect("Missing input to {self:?}").clone(),
             BaseGate::Constant(_constant) => {
                 todo!("SimdShare from constant")
             }
diff --git a/crates/seec/src/circuit/mod.rs b/crates/seec/src/circuit/mod.rs
index d412620..ba26b46 100644
--- a/crates/seec/src/circuit/mod.rs
+++ b/crates/seec/src/circuit/mod.rs
@@ -1,6 +1,6 @@
 //! Circuit builder and executable circuit types.
+use crate::protocols::Gate;
 use crate::SubCircuitGate;
-pub use builder::SubCircCache;
 use bytemuck::Pod;
 use either::Either;
 use num_integer::Integer;
@@ -18,9 +18,20 @@ pub mod dyn_layers;
 pub mod static_layers;
 
 pub use crate::protocols::boolean_gmw::BooleanGate;
-use crate::protocols::Gate;
 pub use base_circuit::{BaseCircuit, GateId};
-pub use builder::{CircuitBuilder, SharedCircuit};
+pub use builder::{CircuitBuilder, SharedCircuit, SubCircCache};
+
+macro_rules! circ_path {
+    ($file:expr) => {
+        include_str!(concat!(env!("CARGO_MANIFEST_DIR"), "/circuits/", $file))
+    };
+}
+// TODO the plain text of these bristol circuits is currently always embedded into the binary
+//  maybe we can find a better solution for this, or toggle this via a feature
+pub const BRISTOL_ADD_8: &str = circ_path!("int_add8_depth.bristol");
+pub const BRISTOL_ADD_16: &str = circ_path!("int_add16_depth.bristol");
+pub const BRISTOL_ADD_32: &str = circ_path!("int_add32_depth.bristol");
+pub const BRISTOL_ADD_64: &str = circ_path!("int_add64_depth.bristol");
 
 pub type CircuitId = u32;
 
diff --git a/crates/seec/src/executor.rs b/crates/seec/src/executor.rs
index ebcfdbf..56bf30e 100644
--- a/crates/seec/src/executor.rs
+++ b/crates/seec/src/executor.rs
@@ -139,7 +139,12 @@ where
         receiver: &mut Receiver<Message<P>>,
     ) -> Result<Output<P::ShareStorage>, ExecutorError> {
         info!("Executing circuit");
-        debug!(?inputs);
+        if inputs.should_debug() {
+            debug!(?inputs);
+        } else {
+            debug!("Inputs too large for debug printing. Use trace if necessary.");
+            trace!(?inputs);
+        }
         let now = Instant::now();
         let inp_len = match &inputs {
             Input::Scalar(shares) => shares.len(),
@@ -527,6 +532,17 @@ impl<Shares> Input<Shares> {
             Input::Simd(shares) => Some(shares),
         }
     }
+
+    fn should_debug<Sh>(&self) -> bool
+    where
+        Shares: ShareStorage<Sh>,
+    {
+        match self {
+            Input::Scalar(shares) if shares.len() <= 1024 => true,
+            Input::Simd(simd_shares) if simd_shares.len() <= 256 => true,
+            _ => false,
+        }
+    }
 }
 
 impl<Shares: Clone> GateOutputs<Shares> {
diff --git a/crates/seec/src/mul_triple/storage.rs b/crates/seec/src/mul_triple/storage.rs
index 82ca858..43d9b66 100644
--- a/crates/seec/src/mul_triple/storage.rs
+++ b/crates/seec/src/mul_triple/storage.rs
@@ -19,6 +19,7 @@ pub struct MTStorage<F, MulTriples> {
     file: F,
     write_batch_size: usize,
     stored_mts: MulTriples,
+    #[cfg(feature = "bench-api")]
     /// can only be set when feature bench-api is enabled
     insecure_loop_file: bool,
 }
@@ -36,6 +37,7 @@ where
             file: BufWriter::new(file),
             write_batch_size: DEFAULT_BATCH_SIZE,
             stored_mts: Default::default(),
+            #[cfg(feature = "bench-api")]
             insecure_loop_file: false,
         })
     }
@@ -50,6 +52,7 @@ where
             file,
             write_batch_size: DEFAULT_BATCH_SIZE,
             stored_mts: Default::default(),
+            #[cfg(feature = "bench-api")]
             insecure_loop_file: false,
         }
     }
diff --git a/crates/seec/src/parse/fuse/mod.rs b/crates/seec/src/parse/fuse/mod.rs
index 82706db..a30ca0f 100644
--- a/crates/seec/src/parse/fuse/mod.rs
+++ b/crates/seec/src/parse/fuse/mod.rs
@@ -13,6 +13,7 @@ use rand::distributions::{Distribution, Standard};
 use std::path::Path;
 use std::{fs, io};
 use thiserror::Error;
+use tracing::{debug, instrument};
 
 #[allow(unused_imports, dead_code, clippy::all)]
 #[rustfmt::skip]
@@ -124,6 +125,7 @@ where
         Ok(self.builder.into_circuit())
     }
 
+    #[instrument(level = "debug", skip(self, circ), fields(name = circ.name()))]
     fn add_fuse_sub_circ(
         &mut self,
         circ: CircuitTable<'_>,
@@ -200,7 +202,11 @@ where
         match prim_op {
             PO::Split => {
                 assert_eq!(1, inputs.len(), "Expecting 1 input for Split gate");
-                let b_shares = mixed_gmw::a2b(bc, inputs[0]);
+                let mut b_shares = mixed_gmw::a2b(bc, inputs[0]);
+                // Insert identity gates so that output of a2b has contiguous gate ids
+                for sh in &mut b_shares {
+                    *sh = bc.add_wired_gate(Base(BaseGate::Identity), &[*sh]);
+                }
                 // we return the first one, if we encounter a node with an input offset, we
                 // can retrieve this gate_id from the map and add the offset
                 b_shares[0]
@@ -239,6 +245,7 @@ where
                 main_inputs[0]
             }
             PO::CallSubcircuit if self.call_mode == CallMode::InlineCircuits => {
+                debug!(name = node.subcircuit_name(), "CallSubcircuit");
                 let circ = self
                     .sc_map
                     .get(
@@ -333,7 +340,7 @@ mod tests {
             .convert_module(mod_table)
             .expect("Fuse conversion");
         let ec = ExecutableCircuit::DynLayers(circ);
-        let inputs: Vec<u32> = ChaChaRng::seed_from_u64(4242)
+        let inputs: Vec<u32> = ChaChaRng::seed_from_u64(46456315)
             .sample_iter(Standard)
             .take(ec.input_count())
             .collect();
@@ -345,7 +352,7 @@ mod tests {
         .await
         .unwrap();
         // TODO, this is very likely not the correct output
-        let exp = vec![i32::MAX as u32; 10];
+        let exp = vec![u32::MAX; 10];
         let exp = MixedShareStorage::Arith(exp);
         assert_eq!(out, exp)
     }
diff --git a/crates/seec/src/private_test_utils.rs b/crates/seec/src/private_test_utils.rs
index 7bdc6a4..d4eba27 100644
--- a/crates/seec/src/private_test_utils.rs
+++ b/crates/seec/src/private_test_utils.rs
@@ -3,6 +3,7 @@
 //! This module is activated by the "_integration_tests" feature and should not be used by
 //! downstream code. It can change in any version.
 use std::convert::Infallible;
+use std::env;
 use std::fmt::Debug;
 use std::path::Path;
 
@@ -13,14 +14,17 @@ use bitvec::prelude::BitSlice;
 use bitvec::vec;
 use bitvec::view::BitViewSized;
 use itertools::Itertools;
+use once_cell::sync::Lazy;
+use parking_lot::Mutex;
 use rand::distributions::Standard;
 use rand::prelude::Distribution;
 use rand::rngs::ThreadRng;
-use rand::thread_rng;
+use rand::{thread_rng, Rng, SeedableRng};
+use rand_chacha::ChaCha8Rng;
 use seec_channel::sub_channel;
 use tokio::task::spawn_blocking;
 use tokio::time::Instant;
-use tracing::info;
+use tracing::{debug, info};
 use tracing_subscriber::util::SubscriberInitExt;
 use tracing_subscriber::EnvFilter;
 
@@ -142,7 +146,17 @@ macro_rules! impl_into_shares {
                 for $typ
             {
                 fn into_shares(self) -> (MixedShareStorage<$typ>, MixedShareStorage<$typ>) {
-                    let [a, b] = AdditiveSharing::new(thread_rng()).share(vec![self]);
+                    static RNG: Lazy<Mutex<ChaCha8Rng>> = Lazy::new(|| {
+                        let seed = match env::var("RNG_SEED") {
+                            Ok(seed) => seed.parse().expect("failed to parse RNG_SEED env var as u64"),
+                            Err(_) => thread_rng().gen()
+                        };
+                        debug!(seed, "Input sharing rng seed");
+                        Mutex::new(ChaCha8Rng::seed_from_u64(seed))
+                    });
+                    let mut rng = RNG.lock();
+                    // let [a, b] = AdditiveSharing::new(ChaCha8Rng::seed_from_u64(65432)).share(vec![self]);
+                    let [a, b] = AdditiveSharing::new(&mut *rng).share(vec![self]);
                     (MixedShareStorage::Arith(a), MixedShareStorage::Arith(b))
                 }
             }
diff --git a/crates/seec/src/protocols/aby2.rs b/crates/seec/src/protocols/aby2.rs
index c9458d7..f74457a 100644
--- a/crates/seec/src/protocols/aby2.rs
+++ b/crates/seec/src/protocols/aby2.rs
@@ -234,7 +234,8 @@ impl BooleanGate {
                 | BaseGate::SubCircuitInput(_)
                 | BaseGate::SubCircuitOutput(_)
                 | BaseGate::ConnectToMain(_)
-                | BaseGate::Debug => inputs.next().expect("Empty input"),
+                | BaseGate::Debug
+                | BaseGate::Identity => inputs.next().expect("Empty input"),
                 BaseGate::Constant(_) => todo!(),
                 BaseGate::ConnectToMainFromSimd(_) => {
                     unimplemented!("SIMD currently not supported for ABY2")
diff --git a/crates/seec/src/protocols/mixed_gmw.rs b/crates/seec/src/protocols/mixed_gmw.rs
index abdb499..91275cc 100644
--- a/crates/seec/src/protocols/mixed_gmw.rs
+++ b/crates/seec/src/protocols/mixed_gmw.rs
@@ -1,4 +1,4 @@
-use crate::circuit::base_circuit::BaseGate;
+use crate::circuit::base_circuit::{BaseGate, Load};
 use crate::circuit::{BaseCircuit, ExecutableCircuit, GateIdx};
 use crate::common::BitVec;
 use crate::executor::{GateOutputs, Input};
@@ -9,11 +9,13 @@ use crate::protocols::{
     arithmetic_gmw, boolean_gmw, Gate, Protocol, Ring, ScalarDim, SetupStorage, Share,
     ShareStorage, Sharing,
 };
-use crate::GateId;
+use crate::{bristol, circuit, GateId};
 use async_trait::async_trait;
 use bitvec::array::BitArray;
 use bitvec::order::Lsb0;
 use bitvec::view::BitViewSized;
+use once_cell::sync::Lazy;
+use parking_lot::Mutex;
 use rand::distributions::Standard;
 use rand::prelude::Distribution;
 use rand::{random, Rng, SeedableRng};
@@ -22,7 +24,8 @@ use serde::{Deserialize, Serialize};
 use std::convert::Infallible;
 use std::marker::PhantomData;
 use std::{iter, mem};
-use tracing::trace;
+use tracing::{instrument, trace};
+use typemap_rev::{TypeMap, TypeMapKey};
 
 #[derive(Clone, Debug, Default, Hash, Eq, PartialEq)]
 pub struct MixedGmw<R>(PhantomData<R>);
@@ -679,6 +682,22 @@ impl<R: Ring> Gate for MixedGate<R> {
     }
 }
 
+impl<R> From<&bristol::Gate> for MixedGate<R> {
+    fn from(gate: &bristol::Gate) -> Self {
+        match gate {
+            bristol::Gate::And(_) => MixedGate::Bool(boolean_gmw::BooleanGate::And),
+            bristol::Gate::Xor(_) => MixedGate::Bool(boolean_gmw::BooleanGate::Xor),
+            bristol::Gate::Inv(_) => MixedGate::Bool(boolean_gmw::BooleanGate::Inv),
+        }
+    }
+}
+
+impl<R> From<BaseGate<MixedShare<R>>> for MixedGate<R> {
+    fn from(value: BaseGate<MixedShare<R>>) -> Self {
+        Self::Base(value)
+    }
+}
+
 #[derive(Debug)]
 pub struct MixedSharing<B, A, R> {
     bool: B,
@@ -733,10 +752,40 @@ pub fn a2b<R: Ring>(bc: &mut BaseCircuit<MixedGate<R>>, a: GateId) -> Vec<GateId
     };
     let split_a2b0 = split(a2b0_sw);
     let split_a2b1 = split(a2b1_sw);
-    // TODO log depth addition circuit
-    basic_add(bc, &split_a2b0, &split_a2b1)
+    depth_optimized_add(bc, &split_a2b0, &split_a2b1)
+}
+
+fn depth_optimized_add<R: Ring>(
+    bc: &mut BaseCircuit<MixedGate<R>>,
+    a: &[GateId],
+    b: &[GateId],
+) -> Vec<GateId> {
+    // We can't have a generic static, so we resort to a lazy typemap to cache
+    // the addition circuits
+    static ADDERS: Lazy<Mutex<TypeMap>> = Lazy::new(Mutex::default);
+    struct Key<R>(PhantomData<R>);
+    impl<R: Ring> TypeMapKey for Key<R> {
+        type Value = BaseCircuit<MixedGate<R>>;
+    }
+    assert_eq!(R::BITS, a.len(), "Wrong number of inputs");
+    assert_eq!(R::BITS, b.len(), "Wrong number of inputs");
+    let mut guard = ADDERS.lock();
+    let adder = guard.entry::<Key<R>>().or_insert_with(|| {
+        let bristol = match R::BITS {
+            8 => circuit::BRISTOL_ADD_8,
+            16 => circuit::BRISTOL_ADD_16,
+            32 => circuit::BRISTOL_ADD_32,
+            64 => circuit::BRISTOL_ADD_64,
+            other => panic!("Unsupported bit size {other}"),
+        };
+        let bristol = bristol::circuit(bristol).expect("Unable to parse stored bristol circuit");
+        BaseCircuit::from_bristol(bristol, Load::SubCircuit)
+            .expect("Unable to convert to BaseCircuit")
+    });
+    bc.add_sub_circuit(adder, a.iter().chain(b).copied())
 }
 
+#[instrument(level = "debug", ret, skip_all)]
 fn basic_add<R: Ring>(
     bc: &mut BaseCircuit<MixedGate<R>>,
     a: &[GateId],
@@ -775,7 +824,7 @@ fn basic_add<R: Ring>(
 
 #[cfg(test)]
 mod tests {
-    use super::basic_add;
+    use super::depth_optimized_add;
     use crate::circuit::base_circuit::BaseGate;
     use crate::circuit::{BaseCircuit, DefaultIdx, ExecutableCircuit};
     use crate::private_test_utils::{execute_circuit, init_tracing, TestChannel, ToBool};
@@ -834,7 +883,7 @@ mod tests {
     }
 
     #[tokio::test]
-    async fn basic_add_test() -> anyhow::Result<()> {
+    async fn low_depth_add_test() -> anyhow::Result<()> {
         let _g = init_tracing();
         let mut bc = BaseCircuit::<MixedGate<u8>, _>::new();
 
@@ -844,7 +893,7 @@ mod tests {
         let inp2: Vec<_> = (0..8)
             .map(|_| bc.add_gate(MixedGate::Base(BaseGate::Input(ScalarDim))))
             .collect();
-        let added = basic_add(&mut bc, &inp1, &inp2);
+        let added = depth_optimized_add(&mut bc, &inp1, &inp2);
         for g in added {
             bc.add_wired_gate(MixedGate::Base(BaseGate::Output(ScalarDim)), &[g]);
         }
@@ -929,7 +978,7 @@ mod tests {
         let mul = bc.add_wired_gate(MixedGate::Arith(ArithmeticGate::Mul), &[ainp1, ainp2]);
         let mul_b = a2b(&mut bc, mul);
 
-        let added = basic_add(&mut bc, &binps, &mul_b);
+        let added = depth_optimized_add(&mut bc, &binps, &mul_b);
         let res_a = bc.add_wired_gate(MixedGate::Conv(ConvGate::B2A), &added);
         bc.add_wired_gate(MixedGate::Base(BaseGate::Output(ScalarDim)), &[res_a]);
 
diff --git a/crates/seec/src/protocols/tensor_aby2.rs b/crates/seec/src/protocols/tensor_aby2.rs
index a81a3d1..9c4d0bd 100644
--- a/crates/seec/src/protocols/tensor_aby2.rs
+++ b/crates/seec/src/protocols/tensor_aby2.rs
@@ -345,7 +345,8 @@ impl BooleanGate {
                 | BaseGate::SubCircuitInput(_)
                 | BaseGate::SubCircuitOutput(_)
                 | BaseGate::ConnectToMain(_)
-                | BaseGate::Debug => inputs.next().expect("Empty input"),
+                | BaseGate::Debug
+                | BaseGate::Identity => inputs.next().expect("Empty input"),
                 BaseGate::Constant(_) => todo!(),
                 BaseGate::ConnectToMainFromSimd(_) => {
                     panic!("No SIMD support for BoolTensorAby2")