diff --git a/patch/Nimbus/Makefile b/patch/Nimbus/Makefile index b911f4410..29de10f5a 100644 --- a/patch/Nimbus/Makefile +++ b/patch/Nimbus/Makefile @@ -1,6 +1,9 @@ # Project Name TARGET = Nimbus +APP_TYPE = BOOT_SRAM +LDSCRIPT = nimbus_sram.lds + # Sources CPP_SOURCES += \ Nimbus.cpp \ diff --git a/patch/Nimbus/README.md b/patch/Nimbus/README.md index d378887e9..8322eaeee 100644 --- a/patch/Nimbus/README.md +++ b/patch/Nimbus/README.md @@ -5,6 +5,8 @@ Ported by Ben Sergentanis Originally by Emilie Gillet +This app is built for use on the Daisy Bootloader. First, flash your patch with the Daisy Bootloader using the Daisy Web Programmer. Then, flash this app onto the bootloader. + ## Description Nimbus is a port of Mutable Instrument's Clouds. Clouds is a granular diff --git a/patch/Nimbus/nimbus_sram.lds b/patch/Nimbus/nimbus_sram.lds new file mode 100644 index 000000000..2324c29b9 --- /dev/null +++ b/patch/Nimbus/nimbus_sram.lds @@ -0,0 +1,304 @@ +/* Generated by LinkerScriptGenerator [http://visualgdb.com/tools/LinkerScriptGenerator] + * Target: STM32H750IB + * The file is provided under the BSD license. + */ + +ENTRY(Reset_Handler) + +/** Layout modified from nautilus file to have more SRAM + * at the expense of a bit less program memory. + * + */ +MEMORY +{ + FLASH (RX) : ORIGIN = 0x08000000, LENGTH = 128K + DTCMRAM (RWX) : ORIGIN = 0x20000000, LENGTH = 128K + SRAM_EXEC (RWX): ORIGIN = 0x24000000, LENGTH = 200K + SRAM (RWX) : ORIGIN = 0x24000000 + 200K, LENGTH = 312K + RAM_D2 (RWX) : ORIGIN = 0x30000000, LENGTH = 32K + RAM_D2CACHE (RWX) : ORIGIN = 0x30000000 + 32K, LENGTH = 288K - 32K + RAM_D3 (RWX) : ORIGIN = 0x38000000, LENGTH = 64K + ITCMRAM (RWX) : ORIGIN = 0x00000000, LENGTH = 64K + SDRAM (RWX) : ORIGIN = 0xc0000000, LENGTH = 64M + QSPIFLASH (RX) : ORIGIN = 0x90000000, LENGTH = 8M +} + +_estack = 0x20020000; + +SECTIONS +{ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) + . = ALIGN(4); + } > SRAM_EXEC + + .text : + { + . = ALIGN(4); + _stext = .; + + *(.text) + *(.text*) + *(.rodata) + *(.rodata*) + *(.glue_7) + *(.glue_7t) + KEEP(*(.init)) + KEEP(*(.fini)) + . = ALIGN(4); + _etext = .; + + } > SRAM_EXEC + + .ARM.extab : + { + . = ALIGN(4); + *(.ARM.extab) + *(.gnu.linkonce.armextab.*) + . = ALIGN(4); + } > SRAM_EXEC + + .exidx : + { + . = ALIGN(4); + PROVIDE(__exidx_start = .); + *(.ARM.exidx*) + . = ALIGN(4); + PROVIDE(__exidx_end = .); + } > SRAM_EXEC + + .ARM.attributes : + { + *(.ARM.attributes) + } > SRAM_EXEC + + .preinit_array : + { + PROVIDE(__preinit_array_start = .); + KEEP(*(.preinit_array*)) + PROVIDE(__preinit_array_end = .); + } > SRAM_EXEC + + .init_array : + { + PROVIDE(__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array*)) + PROVIDE(__init_array_end = .); + } > SRAM_EXEC + + .fini_array : + { + PROVIDE(__fini_array_start = .); + KEEP(*(.fini_array*)) + KEEP(*(SORT(.fini_array.*))) + PROVIDE(__fini_array_end = .); + } > SRAM_EXEC + +/* + _siitcmdata = LOADADDR(.itcmram); + + .itcmram : + { + . = ALIGN(4); + _sitcmram = .; + PROVIDE(__itcm_start__ = _sitcmram); + *(.itcmram) + *(.itcmram*) + . = ALIGN(4); + _eitcmram = .; + PROVIDE(__itcm_end__ = _eitcmram); + } > ITCMRAM AT >FLASH + */ + + .itcmram_bss (NOLOAD): + { + . = ALIGN(4); + _sitcmbssram = .; + PROVIDE(__itcmbss_start__ = _sitcmbssram); + *(.itcmbssram) + *(.itcmbssram*) + . = ALIGN(4); + _eitcmbssram = .; + PROVIDE(__itcmbss_end__ = _eitcmbssram); + } > ITCMRAM + + + .data : + { + . = ALIGN(4); + _sdata = .; + + PROVIDE(__data_start__ = _sdata); + *(.data) + *(.data*) + . = ALIGN(4); + _edata = .; + + PROVIDE(__data_end__ = _edata); + } > SRAM AT > SRAM_EXEC + + _sidata = LOADADDR(.data); + + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = .; + + PROVIDE(__bss_start__ = _sbss); + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + _ebss = .; + + PROVIDE(__bss_end__ = _ebss); + } > SRAM + + PROVIDE(end = .); + + .dtcmram_bss (NOLOAD) : + { + . = ALIGN(4); + _sdtcmram_bss = .; + + PROVIDE(__dtcmram_bss_start__ = _sdtcmram_bss); + *(.dtcmram_bss) + *(.dtcmram_bss*) + . = ALIGN(4); + _edtcmram_bss = .; + + PROVIDE(__dtcmram_bss_end__ = _edtcmram_bss); + } > DTCMRAM + + .sram1_bss (NOLOAD) : + { + . = ALIGN(4); + _ssram1_bss = .; + + PROVIDE(__sram1_bss_start__ = _sram1_bss); + *(.sram1_bss) + *(.sram1_bss*) + . = ALIGN(4); + _esram1_bss = .; + + PROVIDE(__sram1_bss_end__ = _esram1_bss); + } > RAM_D2 + + .d2_bss (NOLOAD) : + { + . = ALIGN(4); + _sd2_bss = .; + + PROVIDE(__d2_bss_start__ = _d2_bss); + *(.d2_bss) + *(.d2_bss*) + . = ALIGN(4); + _ed2_bss = .; + + PROVIDE(__d2_bss_end__ = _ed2_bss); + } > RAM_D2CACHE + + /* + .sdram_text : + { + . = ALIGN(4); + _ssdram_text = .; + + PROVIDE(__sdram_text_start = _ssdram_text); + *(.sdram_text) + *(.sdram_text*) + . = ALIGN(4); + _esdram_text = .; + + PROVIDE(__sdram_text_end = _esdram_text); + } > SDRAM AT >FLASH + _sisdram_text = LOADADDR(.sdram_text); + */ + + .sdram_bss (NOLOAD) : + { + . = ALIGN(4); + _ssdram_bss = .; + + PROVIDE(__sdram_bss_start = _ssdram_bss); + *(.sdram_bss) + *(.sdram_bss*) + . = ALIGN(4); + _esdram_bss = .; + + PROVIDE(__sdram_bss_end = _esdram_bss); + } > SDRAM + + + .qspiflash_text : + { + . = ALIGN(4); + _sqspiflash_text = .; + + PROVIDE(__qspiflash_text_start = _sqspiflash_text); + *(.qspiflash_text) + *(.qspiflash_text*) + . = ALIGN(4); + _eqspiflash_text = .; + + PROVIDE(__qspiflash_text_end = _eqspiflash_text); + } > QSPIFLASH + + .qspiflash_data : + { + . = ALIGN(4); + _sqspiflash_data = .; + + PROVIDE(__qspiflash_data_start = _sqspiflash_data); + *(.qspiflash_data) + *(.qspiflash_data*) + . = ALIGN(4); + _eqspiflash_data = .; + + PROVIDE(__qspiflash_data_end = _eqspiflash_data); + } > QSPIFLASH + + .qspiflash_bss (NOLOAD) : + { + . = ALIGN(4); + _sqspiflash_bss = .; + + PROVIDE(__qspiflash_bss_start = _sqspiflash_bss); + *(.qspiflash_bss) + *(.qspiflash_bss*) + . = ALIGN(4); + _eqspiflash_bss = .; + + PROVIDE(__qspiflash_bss_end = _eqspiflash_bss); + } > QSPIFLASH + + .heap (NOLOAD) : + { + . = ALIGN(4); + PROVIDE(__heap_start__ = .); + KEEP(*(.heap)) + . = ALIGN(4); + PROVIDE(__heap_end__ = .); + } > SRAM + + .reserved_for_stack (NOLOAD) : + { + . = ALIGN(4); + PROVIDE(__reserved_for_stack_start__ = .); + KEEP(*(.reserved_for_stack)) + . = ALIGN(4); + PROVIDE(__reserved_for_stack_end__ = .); + } > SRAM + + DISCARD : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + +} + diff --git a/patch/Sequencer/Sequencer.cpp b/patch/Sequencer/Sequencer.cpp index 64896b86c..fd0a95a52 100644 --- a/patch/Sequencer/Sequencer.cpp +++ b/patch/Sequencer/Sequencer.cpp @@ -121,6 +121,6 @@ void UpdateOutputs() patch.seed.dac.WriteValue(DacHandle::Channel::TWO, round((values[stepNumber] / 12.f) * 819.2f)); - dsy_gpio_write(&patch.gate_output, trigOut); + patch.gate_output.Write(trigOut); trigOut = false; } diff --git a/patch/Torus/Makefile b/patch/Torus/Makefile index d7b36e612..74ce76f02 100644 --- a/patch/Torus/Makefile +++ b/patch/Torus/Makefile @@ -1,6 +1,9 @@ # Project Name TARGET = torus +APP_TYPE = BOOT_SRAM +LDSCRIPT = torus_sram.lds + # Library Locations LIBDAISY_DIR = ../../libDaisy STMLIB_DIR = ../../stmlib diff --git a/patch/Torus/README.md b/patch/Torus/README.md index a025e06a5..9bc7ef6f6 100644 --- a/patch/Torus/README.md +++ b/patch/Torus/README.md @@ -7,6 +7,8 @@ Originally by: Émilie Gillet Please refer to the [Rings manual](https://mutable-instruments.net/modules/rings/manual/) for more detail on everything Rings. +This app is built for use on the Daisy Bootloader. First, flash your patch with the Daisy Bootloader using the Daisy Web Programmer. Then, flash this app onto the bootloader. + ## Controls and I/O - Ctrl 1-4: Map these to the usual Rings controls. More info in the Control Menu section. - Gate In 1: Trigger In diff --git a/patch/Torus/torus_sram.lds b/patch/Torus/torus_sram.lds new file mode 100644 index 000000000..2324c29b9 --- /dev/null +++ b/patch/Torus/torus_sram.lds @@ -0,0 +1,304 @@ +/* Generated by LinkerScriptGenerator [http://visualgdb.com/tools/LinkerScriptGenerator] + * Target: STM32H750IB + * The file is provided under the BSD license. + */ + +ENTRY(Reset_Handler) + +/** Layout modified from nautilus file to have more SRAM + * at the expense of a bit less program memory. + * + */ +MEMORY +{ + FLASH (RX) : ORIGIN = 0x08000000, LENGTH = 128K + DTCMRAM (RWX) : ORIGIN = 0x20000000, LENGTH = 128K + SRAM_EXEC (RWX): ORIGIN = 0x24000000, LENGTH = 200K + SRAM (RWX) : ORIGIN = 0x24000000 + 200K, LENGTH = 312K + RAM_D2 (RWX) : ORIGIN = 0x30000000, LENGTH = 32K + RAM_D2CACHE (RWX) : ORIGIN = 0x30000000 + 32K, LENGTH = 288K - 32K + RAM_D3 (RWX) : ORIGIN = 0x38000000, LENGTH = 64K + ITCMRAM (RWX) : ORIGIN = 0x00000000, LENGTH = 64K + SDRAM (RWX) : ORIGIN = 0xc0000000, LENGTH = 64M + QSPIFLASH (RX) : ORIGIN = 0x90000000, LENGTH = 8M +} + +_estack = 0x20020000; + +SECTIONS +{ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) + . = ALIGN(4); + } > SRAM_EXEC + + .text : + { + . = ALIGN(4); + _stext = .; + + *(.text) + *(.text*) + *(.rodata) + *(.rodata*) + *(.glue_7) + *(.glue_7t) + KEEP(*(.init)) + KEEP(*(.fini)) + . = ALIGN(4); + _etext = .; + + } > SRAM_EXEC + + .ARM.extab : + { + . = ALIGN(4); + *(.ARM.extab) + *(.gnu.linkonce.armextab.*) + . = ALIGN(4); + } > SRAM_EXEC + + .exidx : + { + . = ALIGN(4); + PROVIDE(__exidx_start = .); + *(.ARM.exidx*) + . = ALIGN(4); + PROVIDE(__exidx_end = .); + } > SRAM_EXEC + + .ARM.attributes : + { + *(.ARM.attributes) + } > SRAM_EXEC + + .preinit_array : + { + PROVIDE(__preinit_array_start = .); + KEEP(*(.preinit_array*)) + PROVIDE(__preinit_array_end = .); + } > SRAM_EXEC + + .init_array : + { + PROVIDE(__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array*)) + PROVIDE(__init_array_end = .); + } > SRAM_EXEC + + .fini_array : + { + PROVIDE(__fini_array_start = .); + KEEP(*(.fini_array*)) + KEEP(*(SORT(.fini_array.*))) + PROVIDE(__fini_array_end = .); + } > SRAM_EXEC + +/* + _siitcmdata = LOADADDR(.itcmram); + + .itcmram : + { + . = ALIGN(4); + _sitcmram = .; + PROVIDE(__itcm_start__ = _sitcmram); + *(.itcmram) + *(.itcmram*) + . = ALIGN(4); + _eitcmram = .; + PROVIDE(__itcm_end__ = _eitcmram); + } > ITCMRAM AT >FLASH + */ + + .itcmram_bss (NOLOAD): + { + . = ALIGN(4); + _sitcmbssram = .; + PROVIDE(__itcmbss_start__ = _sitcmbssram); + *(.itcmbssram) + *(.itcmbssram*) + . = ALIGN(4); + _eitcmbssram = .; + PROVIDE(__itcmbss_end__ = _eitcmbssram); + } > ITCMRAM + + + .data : + { + . = ALIGN(4); + _sdata = .; + + PROVIDE(__data_start__ = _sdata); + *(.data) + *(.data*) + . = ALIGN(4); + _edata = .; + + PROVIDE(__data_end__ = _edata); + } > SRAM AT > SRAM_EXEC + + _sidata = LOADADDR(.data); + + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = .; + + PROVIDE(__bss_start__ = _sbss); + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + _ebss = .; + + PROVIDE(__bss_end__ = _ebss); + } > SRAM + + PROVIDE(end = .); + + .dtcmram_bss (NOLOAD) : + { + . = ALIGN(4); + _sdtcmram_bss = .; + + PROVIDE(__dtcmram_bss_start__ = _sdtcmram_bss); + *(.dtcmram_bss) + *(.dtcmram_bss*) + . = ALIGN(4); + _edtcmram_bss = .; + + PROVIDE(__dtcmram_bss_end__ = _edtcmram_bss); + } > DTCMRAM + + .sram1_bss (NOLOAD) : + { + . = ALIGN(4); + _ssram1_bss = .; + + PROVIDE(__sram1_bss_start__ = _sram1_bss); + *(.sram1_bss) + *(.sram1_bss*) + . = ALIGN(4); + _esram1_bss = .; + + PROVIDE(__sram1_bss_end__ = _esram1_bss); + } > RAM_D2 + + .d2_bss (NOLOAD) : + { + . = ALIGN(4); + _sd2_bss = .; + + PROVIDE(__d2_bss_start__ = _d2_bss); + *(.d2_bss) + *(.d2_bss*) + . = ALIGN(4); + _ed2_bss = .; + + PROVIDE(__d2_bss_end__ = _ed2_bss); + } > RAM_D2CACHE + + /* + .sdram_text : + { + . = ALIGN(4); + _ssdram_text = .; + + PROVIDE(__sdram_text_start = _ssdram_text); + *(.sdram_text) + *(.sdram_text*) + . = ALIGN(4); + _esdram_text = .; + + PROVIDE(__sdram_text_end = _esdram_text); + } > SDRAM AT >FLASH + _sisdram_text = LOADADDR(.sdram_text); + */ + + .sdram_bss (NOLOAD) : + { + . = ALIGN(4); + _ssdram_bss = .; + + PROVIDE(__sdram_bss_start = _ssdram_bss); + *(.sdram_bss) + *(.sdram_bss*) + . = ALIGN(4); + _esdram_bss = .; + + PROVIDE(__sdram_bss_end = _esdram_bss); + } > SDRAM + + + .qspiflash_text : + { + . = ALIGN(4); + _sqspiflash_text = .; + + PROVIDE(__qspiflash_text_start = _sqspiflash_text); + *(.qspiflash_text) + *(.qspiflash_text*) + . = ALIGN(4); + _eqspiflash_text = .; + + PROVIDE(__qspiflash_text_end = _eqspiflash_text); + } > QSPIFLASH + + .qspiflash_data : + { + . = ALIGN(4); + _sqspiflash_data = .; + + PROVIDE(__qspiflash_data_start = _sqspiflash_data); + *(.qspiflash_data) + *(.qspiflash_data*) + . = ALIGN(4); + _eqspiflash_data = .; + + PROVIDE(__qspiflash_data_end = _eqspiflash_data); + } > QSPIFLASH + + .qspiflash_bss (NOLOAD) : + { + . = ALIGN(4); + _sqspiflash_bss = .; + + PROVIDE(__qspiflash_bss_start = _sqspiflash_bss); + *(.qspiflash_bss) + *(.qspiflash_bss*) + . = ALIGN(4); + _eqspiflash_bss = .; + + PROVIDE(__qspiflash_bss_end = _eqspiflash_bss); + } > QSPIFLASH + + .heap (NOLOAD) : + { + . = ALIGN(4); + PROVIDE(__heap_start__ = .); + KEEP(*(.heap)) + . = ALIGN(4); + PROVIDE(__heap_end__ = .); + } > SRAM + + .reserved_for_stack (NOLOAD) : + { + . = ALIGN(4); + PROVIDE(__reserved_for_stack_start__ = .); + KEEP(*(.reserved_for_stack)) + . = ALIGN(4); + PROVIDE(__reserved_for_stack_end__ = .); + } > SRAM + + DISCARD : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + +} + diff --git a/patch_sm/GettingStarted/Gate_Output/Gate_Output.cpp b/patch_sm/GettingStarted/Gate_Output/Gate_Output.cpp index 4c72d36a5..a52ca9f49 100644 --- a/patch_sm/GettingStarted/Gate_Output/Gate_Output.cpp +++ b/patch_sm/GettingStarted/Gate_Output/Gate_Output.cpp @@ -17,13 +17,13 @@ int main(void) while(1) { /** Set the gate high */ - dsy_gpio_write(&patch.gate_out_1, true); + patch.gate_out_1.Write(true); /** Wait 250 ms */ patch.Delay(250); /** Set the gate low */ - dsy_gpio_write(&patch.gate_out_1, false); + patch.gate_out_1.Write(false); /** Wait 250 ms */ patch.Delay(250); diff --git a/patch_sm/HardwareTest/HardwareTest.cpp b/patch_sm/HardwareTest/HardwareTest.cpp index ec8078754..cb4563480 100644 --- a/patch_sm/HardwareTest/HardwareTest.cpp +++ b/patch_sm/HardwareTest/HardwareTest.cpp @@ -132,8 +132,8 @@ int main(void) } if(now - gatet > 1000) { - dsy_gpio_toggle(&hw.gate_out_1); - dsy_gpio_toggle(&hw.gate_out_2); + hw.gate_out_1.Toggle(); + hw.gate_out_2.Toggle(); gatet = now; } diff --git a/seed/Button/Button.cpp b/seed/Button/Button.cpp index 5b48bfd68..d4b5c79d1 100644 --- a/seed/Button/Button.cpp +++ b/seed/Button/Button.cpp @@ -18,7 +18,7 @@ int main(void) //Configure and initialize button Switch button1; //Set button to pin 28, to be updated at a 1kHz samplerate - button1.Init(hw.GetPin(28), 1000); + button1.Init(hw.GetPin(28), 1000.f); // Loop forever for(;;) diff --git a/seed/DSP/fir/Makefile b/seed/DSP/fir/Makefile index babced423..c4d6b6c1a 100644 --- a/seed/DSP/fir/Makefile +++ b/seed/DSP/fir/Makefile @@ -4,7 +4,7 @@ TARGET = fir # Library Locations LIBDAISY_DIR ?= ../../../libDaisy DAISYSP_DIR ?= ../../../DaisySP -CMSIS_DIR ?= $(LIBDAISY_DIR)/Drivers/CMSIS +CMSIS_DIR ?= $(LIBDAISY_DIR)/Drivers/CMSIS-DSP # Sources @@ -13,8 +13,8 @@ CPP_SOURCES = ex_fir.cpp # if USE_ARM_DSP symbol is defined, ARM optimized implementation from the # CMSIS library is used. Add neccessary sources to the list C_DEFS += -DUSE_ARM_DSP -C_SOURCES = $(CMSIS_DIR)/DSP/Source/FilteringFunctions/arm_fir_f32.c \ - $(CMSIS_DIR)/DSP/Source/FilteringFunctions/arm_fir_init_f32.c +C_SOURCES = $(CMSIS_DIR)/Source/FilteringFunctions/arm_fir_f32.c \ + $(CMSIS_DIR)/Source/FilteringFunctions/arm_fir_init_f32.c # Core location, and generic Makefile. SYSTEM_FILES_DIR = $(LIBDAISY_DIR)/core