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openocd.cfg
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openocd.cfg
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#############################################
# Configuration file for openocd
# openocd is an open source on chip debugger
# interface.
# For more information, see doc/openocd.pdf
# Telecom ParisTECH 2009/2010
# Author : Alexis Polti
#############################################
# the target board is the FS44B0XII
#############################################
#############################################
# interfaces port configuration
#############################################
tcl_port 5555
telnet_port 4444
gdb_port 3333
#############################################
# Olimiex ARM-USB-OCD jtag interface
#############################################
interface ft2232
ft2232_device_desc "Olimex OpenOCD JTAG"
ft2232_layout "olimex-jtag"
ft2232_vid_pid 0x15BA 0x0003
adapter_khz 5000
#############################################
# Target specification
#############################################
set _CHIPNAME s3c44B0X
set _ENDIAN little
set _CPUTAPID 0x1f0f0f0f
#############################################
# Reset configuration
#############################################
reset_config trst_and_srst
adapter_nsrst_delay 300
jtag_ntrst_delay 300
#############################################
# jtag scan chain
#############################################
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi
$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x0c7e0000 -work-area-size 0x10000 -work-area-backup 1
# speed up memory downloads
arm7_9 fast_memory_access enable
arm7_9 dcc_downloads enable
# configure the cpu at reset
$_TARGETNAME configure -event reset-init {
puts "Running reset init script for S3C44B0X"
# SVC32 mode
reg cpsr 0x800000d3
# Stack
reg sp_svc 0x0c7ffff0
# WTCON : disable watchdog
mww 0x01d30000 0
# INTMSK
mww 0x01e0000c 0x03fffeff
# INTCON
mww 0x01e00000 0x5
# LOCKTIME
mww 0x01d8000c 0xf0
# PLLCON
mww 0x01d80000 0x0003a031
# CLKCON
mww 0x01d80004 0x00007ff8
# PCONA
mww 0x01d20000 0x000003ff
# PDATB
mww 0x01d2000c 0x7cf
# PCONB
mww 0x01d20008 0x07ff
# PDATC
mww 0x01d20014 0x0100
# PCONC
mww 0x01d20010 0xfff5ff54
# PUPC
mww 0x01d20018 0x00000000
# PCOND
mww 0x01d2001c 0x0000aaaa
# PUPD
mww 0x01d20024 0x00000000
# PCONE
mww 0x01d20028 0x00021569
# PDATE
mww 0x01d2002c 0x00000000
# PUPE
mww 0x01d20030 0x00000000
# PCONF
mww 0x01d20034 0x24900a
# PUPF
mww 0x01d2003c 0x00000000
# PCONG
mww 0x01d20040 0xff3c
# PUPG
mww 0x01d20048 0x00000000
# SPUCR
mww 0x01d2004c 0x6
# INTMSK
mww 0x01e0000c 0x03fffeff
# INTCON
mww 0x01e00000 0x05
# INTMOD
mww 0x01e00008 0x0
# EXTINT
mww 0x01d20050 0x00040440
# SDRAM init
mww 0x1c80000 0x01001102
mww 0x1c80004 0x00007ff4
mww 0x1c80008 0x00000a40
mww 0x1c8000C 0x00001480
mww 0x1c80010 0x00007ffc
mww 0x1c80014 0x00007ffc
mww 0x1c80018 0x00000c40
mww 0x1c8001C 0x00018004
mww 0x1c80020 0x00000a40
mww 0x1c80024 0x008603fb
mww 0x1c80028 0x00000010
mww 0x1c8002C 0x00000020
mww 0x1c80030 0x00000020
}
#############################################
# NOR flash
#############################################
# flash bank CPU.flash cfi <base> <size> <chip width> <bus width> <target#> [jedec_probe]
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME cfi 0x00000000 0x200000 2 2 $_TARGETNAME jedec_probe
# Halt processor then run "reset init" when starting a debug session
noinit
init
halt
reset init