spi_device_testplan.hjson

// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
{
  name: "spi_device"
  import_testplans: ["hw/dv/tools/dvsim/testplans/csr_testplan.hjson",
                     "hw/dv/tools/dvsim/testplans/mem_testplan.hjson",
                     "hw/dv/tools/dvsim/testplans/alert_test_testplan.hjson",
                     "hw/dv/tools/dvsim/testplans/intr_test_testplan.hjson",
                     "hw/dv/tools/dvsim/testplans/tl_device_access_types_testplan.hjson",
                     "hw/dv/tools/dvsim/testplans/stress_all_with_reset_testplan.hjson",
                     "spi_device_sec_cm_testplan.hjson"]
  testpoints: [
    {
      name: smoke
      desc: '''
            Use default SRAM fifo setting. Seq:
            - Write a word data to TX memory and update wptr
            - Send a word SPI transfer
            - Read a word data from RX memory and update rptr
            - Compare the data and check no pending data in SRAM FIFO
            - Repeat above steps'''
      stage: V1
      tests: ["spi_device_smoke"]
    }
    {
      name: base_random_seq
      desc: '''
            Create 3 parallel threads
            - Write random data to TX memory unless fifo is full
            - Send SPI transfer unless TX is empty or RX is full
            - Read RX memory unless RX is empty'''
      stage: V2
      tests: ["spi_device_txrx"]
    }
    {
      name: fifo_full
      desc: '''
            Increase the chance to have fifo full by following
            - Reduce delay to write TX memory
            - Increase delay to read RX memory'''
      stage: V2
      tests: ["spi_device_fifo_full"]
    }
    {
      name: fifo_underflow_overflow
      desc: '''
            Override spi_device_txrx_vseq to send SPI transfer without checking TX/RX fifo, note:
            - When TX is underflow, SW shouldn't update wptr if spi isn't idle, otherwise, spi may
              send mis-aligned data
            - When RX is overflow, data will be lost and if SW update rptr, received data may be
              mis-aligned
            - Ensure underflow/overflow is triggered correctly'''
      stage: V2
      tests: ["spi_device_fifo_underflow_overflow"]
    }
    {
      name: dummy_sck_and_dummy_csb
      desc: '''
            Drive dummy sck without csb or drive dummy csb without sck, and test no impact on the
            design'''
      stage: V2
      tests: ["spi_device_dummy_item_extra_dly"]
    }
    {
      name: extra_delay_on_spi
      desc: '''
            Add extra delay between spi clock edge or extra delay between 2 words data
            This is to test host pause transfer for a while without turning off csb and then stream
            in data again'''
      stage: V2
      tests: ["spi_device_dummy_item_extra_dly"]
    }
    {
      name: tx_async_fifo_reset
      desc: '''
            Reset TX async fifo when SPI interface is idle

            - Fill TX SRAM FIFO with some data, which will be transfered to TX async FIFO
            - Write 0 into read and write point of TX SRAM FIFO
            - Program `rst_txfifo` to reset the async FIFO
            - Check `async_fifo_level.txlvl` is 0
            - Fill TX SRAM FIFO with some other data and enable SPI transfer
            - Check SPI device sends and receives the correct data
            '''
      stage: V2
      tests: ["spi_device_tx_async_fifo_reset"]
    }
    {
      name: rx_async_fifo_reset
      desc: '''
            Reset RX async fifo when SPI interface is idle

            - Configure RX SRAM FIFO with a small size, so that it's easy to fill up
            - Start SPI transfers to fill up the RX SRAM FIFO and at least part of the RX async
              FIFO
            - Program `rst_rxfifo` to reset the async FIFO
            - Check `async_fifo_level.rxlvl` is 0
            - Write 0 into read and write point of RX SRAM FIFO
            - Fill TX SRAM FIFO with some other data and start another SPI transfers
            - Check SPI device sends and receives the correct data
            '''
      stage: V2
      tests: ["spi_device_rx_async_fifo_reset"]
    }
    {
      name: interrupts
      desc: '''
            Test all supported interrupts:
            - tx/rx lvl
            - rx full
            - rx error
            - overflow/underflow'''
      stage: V2
      tests: ["spi_device_intr"]
    }
    {
      name: abort
      desc: '''
            - Fill TX FIFO without host traffic
            - Issue Abort to control register
            - Poll until abort_done in status register
            - TBD additional checking
            '''
      stage: V2
      tests: ["spi_device_abort"]
    }
    {
      name: byte_transfer_on_spi
      desc: '''send spi transfer on byte granularity, and make sure the timer never expires'''
      stage: V2
      tests: ["spi_device_byte_transfer"]
    }
    {
      name: rx_timeout
      desc: '''
            - Send spi transfer on byte granularity, and timer may expires
            - Only check data in sequence level when timer expires. Monitor and scoreboard don't
              model the timer feature
            - Note: Timeout only for RX'''
      stage: V2
      tests: ["spi_device_rx_timeout"]
    }
    {
      name: bit_transfer_on_spi
      desc: '''
            Send spi transfer on bit granularity
            - If TX drives < 7 bits, this byte will be sent in next CSB.
            - If TX drives 7 bits and set CSB to high, this byte won't be sent in next CSB'''
      stage: V2
      tests: ["spi_device_bit_transfer"]
    }
    {
      name: extreme_fifo_setting
      desc: '''Set fifo size to 4 bytes(minimum), 2k-4bytes(maximum) and others'''
      stage: V2
      tests: ["spi_device_extreme_fifo_size"]
    }
    {
      name: perf
      desc: '''Run spi_device_fifi_full_vseq with very small delays'''
      stage: V2
      tests: ["spi_device_perf"]
    }
    {
      name: csb_read
      desc: '''Read CSB value from CSR and check the correctness

               This feature is for debug only, so it's sufficient to verify with this direct sequence:
               - Assign both CSB pins with random values and read the CSB CSRs to check the values'''
      stage: V2
      tests: ["spi_device_csb_read"]
    }
    {
      name: mem_parity
      desc: '''Test memory parity error

               pick a random mem address to inject parity errors and read it back,
               then check it returns d_error with all 1s data.'''
      stage: V2
      tests: ["spi_device_mem_parity"]
    }
    {
      name: mem_cfg
      desc: '''Test cfg_i connectivity between spi_device and prim_ram_2p.

               Randomly set dut.ram_cfg_i and check this value is propagated to prim_mem_2p.'''
      stage: V2
      tests: ["spi_device_ram_cfg"]
    }
    {
      name: tpm_read
      desc: '''
            - Set TPM_CFG.TPM_MODE to CRB mode and set TPM_CFG.EN.
            - Randomise other fields in TPM_CFG.
            - Assert the tpm_csb.
            - Send TPM read command over the SPI bus with a randomised address.
            - Check TPM_CMD_ADDR.
            - Confirm FIFO behaviour dictated by TPM_CFG.tpm_mode.
            - Check TPM_STATUS.cmdaddr_notempty and INTR_STATE.tpm_header_notempty, they should be asserted if hw_reg_dis == 0.
            - If hw_reg_dis == 0, the data is returned to the host via return-by-HW register, else the data is returned via read FIFO.
            - Confirm that the TPM submodule sends WAIT until the read FIFO is available.
            - Check the read FIFO.
            - When available, confirm that the TPM submodule sends START followed by the register value.
            - Compare this value with the expected value.'''
      stage: V2
      tests: ["spi_device_tpm_rw"]
    }
    {
      name: tpm_write
      desc: '''
            - Set TPM_CFG.TPM_MODE to CRB mode and set TPM_CFG.EN.
            - Randomise other fields in TPM_CFG.
            - Assert the tpm_csb.
            - Send TPM write command with a randomised address.
            - Check TPM_CMD_ADDR and write FIFO.
            - Check TPM_STATUS.cmdaddr_notempty and INTR_STATE.tpm_header_notempty.
            - Based on FIFO status, check SPI bus to confirm WAIT or START sent.
            - Check that the TPM submodule accepts write data without the WAIT state if the write FIFO is empty.
            - Otherwise, check WAIT until the write FIFO becomes available (empty).'''
      stage: V2
      tests: ["spi_device_tpm_rw"]
    }
    {
      name: tpm_hw_reg
      desc: '''
            - Configure `TPM_CFG` as follows to have DUT directly respond for the access to the HW
              registers.
              - Set `tpm_mode` to fifo mode.
              - Set `hw_reg_dis` to 0.
              - Set `tpm_reg_chk_dis` to 0.
              - Set `invalid_locality` to 1.
            - Send SPI transactions of varying HW registers. In the meanwhile, SW updates the HW
              registers.
            - Ensure that the data returned is correct for the given address and active locality.'''
      stage: V2
      tests: ["spi_device_tpm_sts_read", "spi_device_tpm_read_hw_reg"]
    }
    {
      name: tpm_fully_random_case
      desc: '''
            - Configure `TPM_CFG.EN` to On and fully randomize other TPM configuration.
            - Run these 3 threads to randomly access TPM HW registers and other addresses.
              - Host issues random TPM reads/writes to spi_device.
              - SW polls the TPM interrupt `tpm_header_not_empty`, then read command/address and
                the corresponding FIFO.
              - SW randomly updates TPM HW registers.
            - Ensure all the data is correct in the scoreboard.'''
      stage: V2
      tests: ["spi_device_tpm_all"]
    }
    {
      name: pass_cmd_filtering
      desc: '''
            - Randomize command opcode.
            - Configure unused CMD_INFO reg with new opcode and set it to valid.
            - Check opcode, address and payload are passing through.
            - Configure filter bit corresponding to opcode to 1.
            - Check the entire command is filtered.
            - Set filter bit back to 0.
            - Check opcode and address are passing through again.
            - Invalid opcode is also filtered'''
      stage: V2
      tests: ["spi_device_pass_cmd_filtering", "spi_device_flash_all"]
    }
    {
      name: pass_addr_translation
      desc: '''
            - Randomize command opcode.
            - Configure unused CMD_INFO reg with new opcode and set it to valid.
            - Enable address translation for given command.
            - Configure address translation bits.
            - Check proper address translation is applied.
            - Disable address translation for given command.
            - Check address is now passing unchanged.'''
      stage: V2
      tests: ["spi_device_pass_addr_payload_swap", "spi_device_flash_all"]
    }
    {
      name: pass_payload_translation
      desc: '''
            - Configure program or write_status command.
            - Enable payload translation for given command.
            - Configure payload translation bits.
            - Check proper payload translation is applied.
            - Disable payload translation for given command.
            - Check payload is now passing unchanged.'''
      stage: V2
      tests: ["spi_device_pass_addr_payload_swap", "spi_device_flash_all"]
    }
    {
      name: cmd_info_slots
      desc: '''
            - Configure first 5 slots according to required configuration.
            - Configure next 6 slots for read commands
            - Randomize configuration of the remaining 13 cmd info slots.
            - Issue commands with various opcodes enabled in info slots.
            - Check proper command propagation.
            - Disable some cmd info slots.
            - Check no propagation of disabled commands.'''
      stage: V2
      tests: ["spi_device_flash_all"]
    }
    {
      name: cmd_read_status
      desc: '''
            - Configure proper read status command info slot.
            - Issue read status command.
            - Check propagation of read status command.
            - Initiate response to the read status.
            - Check proper reception of response.'''
      stage: V2
      tests: ["spi_device_intercept", "spi_device_flash_all"]
    }
    {
      name: cmd_read_jedec
      desc: '''
            - Configure proper read jedec command info slot.
            - Issue read jedec command.
            - Check propagation of read jedec command.
            - Initiate response to the read jedec.
            - Check proper reception of response.'''
      stage: V2
      tests: ["spi_device_intercept", "spi_device_flash_all"]
    }
    {
      name: cmd_read_sfdp
      desc: '''
            - Configure proper read sfdp command info slot.
            - Issue read sfdp command.
            - Check propagation of read sfdp command.
            - Initiate response to the read sfdp.
            - Check proper reception of response.'''
      stage: V2
      tests: ["spi_device_intercept", "spi_device_flash_all"]
    }
    {
      name: cmd_fast_read
      desc: '''
            - Configure proper fast read command info slot.
            - Issue fast read command.
            - Check propagation of fast read command.
            - Initiate response to the fast read.
            - Check proper reception of response.'''
      stage: V2
      tests: ["spi_device_intercept", "spi_device_flash_all"]
    }
    {
      name: flash_cmd_upload
      desc: '''
            - Configure spi_device on flash or passthrough mode.
            - Configure cmd info slots.
            - Set upload to 1 for some of 13 non fixed cmd info slots.
            - Host should poll busy field status to check if command is done.
            - Issue next command upload and poll busy status again.'''
      stage: V2
      tests: ["spi_device_upload"]
    }
    {
      name: mailbox_command
      desc: '''
            - Configure cmd info slots.
            - Issue one of predefined read command targeting mailbox space.
            - Check response to read command.
            - Check if command is processed internally.'''
      stage: V2
      tests: ["spi_device_mailbox"]
    }
    {
      name: mailbox_cross_outside_command
      desc: '''
            - Configure spi_device on passthrough mode. Mailbox boundary crossing is not expected to
              be used on flash mode, so that testing this on flash mode isn't needed.
            - Configure cmd info slots.
            - Issue one of predefined read command targeting mailbox space.
            - Command should start inside mailbox space and cross into read space.
            - When the address falls in the mailbox region, data returns from the mailbox. when the
              address is outside the mailbox, data returns as follows
                - returns high-z if the read command is filtered.
                - returns from downstream port if read command is passed through.'''
      stage: V2
      tests: ["spi_device_mailbox"]
    }
    {
      name: mailbox_cross_inside_command
      desc: '''
            - Similar to `mailbox_cross_outside_command`, except that start address is inside the
              mailbox.'''
      stage: V2
      tests: ["spi_device_mailbox"]
    }
    {
      name: cmd_read_buffer
      desc: '''
            - Configure device in flash mode.
            - Issue read commands.
            - Create another parallel thread that SW updates read buffer contents after a watermark
              or buffer flip event occurs.
            - Check proper read data.
            - Randomly issue read command that crosses read buffer boundary and switches back to
              index 0.
            - Check correctness of `last_read_addr`, `readbuf_watermark` and `readbuf_flip`.'''
      stage: V2
      tests: ["spi_device_flash_mode", "spi_device_read_buffer_direct"]
    }
    {
      name: cmd_dummy_cycle
      desc: '''
            - Configure cmd info slots.
            - Configure dummy cycle of read commands to non default value.
            - For single mode allowed dummy cycle is 0 or more.
            - For dual/quad mode allowed dummy cycle is 2 or more.
            - Check return data timing for configured commands.
            - Check proper read data.
            - Issue new read command that crosses read maibox boundary.
            - Check internal buffer index bit.'''
      stage: V2
      tests: ["spi_device_mailbox", "spi_device_flash_all"]
    }
    {
      name: quad_spi
      desc: '''
            - Configure passthrough or flash mode.
            - Configure cmd info slots.
            - Configure quad mode.
            - Issue supported command.
            - Check data on all four lines.'''
      stage: V2
      tests: ["spi_device_flash_all"]
    }
    {
      name: dual_spi
      desc: '''
            - Configure passthrough or flash mode.
            - Configure cmd info slots.
            - Configure dual mode.
            - Issue supported command.
            - Check data on both lines.'''
      stage: V2
      tests: ["spi_device_flash_all"]
    }
    {
      name: 4b_3b_feature
      desc: '''
            - Configure passthrough or flash mode.
            - Configure command info slots.
            - Configure different values for 4B/3B.
            - Randomize configuration of EN4B and EX4B register fields.
            - Issue supported command with required address.
            - Check proper address propagation.'''
      stage: V2
      tests: ["spi_device_cfg_cmd"]
    }
    {
      name: write_enable_disable
      desc: '''
            - Configure passthrough or flash mode.
            - Randomize WREN and WRDI command info slots.
            - Issue WREN and WRDI commands along with read_status command and others.
            - Read flash status via TL interface.
            - Check WREN/WRDI sets/clears flash status correctly.'''
      stage: V2
      tests: ["spi_device_cfg_cmd"]
    }
    {
      name: TPM_with_flash_or_passthrough_mode
      desc: '''
            - Enable TPM mode.
            - Configure passthrough or flash mode.
            - Issue TPM read/write interleaving with flash transactions.'''
      stage: V2
      tests: ["spi_device_flash_and_tpm"]
    }
    {
      name: tpm_and_flash_trans_with_min_inactive_time
      desc: '''
            Issue these transactions with 2 sys_clk inactive time in between.
            - 2 tpm transactions.
            - 2 flash transactions.
            - a tpm transaction and a flash transaction.'''
      stage: V2
      tests: ["spi_device_flash_and_tpm_min_idle"]
    }
    {
      name: stress_all
      desc: '''
            - Combine above sequences in one test to run sequentially, except csr sequences.
            - Test modes switch among FW, flash, passthrough and tpm.
            - Randomly add reset between each sequence'''
      stage: V2
      tests: ["spi_device_stress_all"]
    }
  ]
  covergroups: [
    {
      name: all_modes_cg
      desc: '''
            Cover every combination of all possible modes:
            - FW mode, passthrough mode and flash mode.
            Cover passthrough mode and flash mode with TPM mode enabled.'''
    }
    // FW mode
    {
      name: bit_order_clk_cfg_cg
      desc: '''
            Cover all configurations of rx/tx order in SPI_DEVICE.CFG for FW mode.
            Note: Flash or TPM mode always use the fixed bit order.

            Cover all combinations of SPI_DEVICE.CFG.CPOL and SPI_DEVICE.CFG.CPHA.
            Cross both bit order and clock configure.'''
    }
    {
      name: fw_tx_fifo_size_cg
      desc: '''
            Cover these values are used to configure TX fifo size for FW mode.
            - min(1 word), typical(half of SRAM size), max(SRAM size - 1 word)
            Sample this when fifo is full.'''
    }
    {
      name: fw_rx_fifo_size_cg
      desc: '''
            The same CG as `fw_tx_fifo_size_cg` for RX.'''
    }
    // TPM mode
    {
      name: tpm_cfg_cg
      desc: '''
            Cover all combinations of these configurations in CSR `tpm_cfg`:
              - tpm_mode, hw_reg_dis, tpm_reg_chk_dis, invalid_locality.
            Cover these address mode:
             - TPM address in both valid and invalid locality.
             - TPM address in/outside TPM address region ('hd4_xxxx).
             - TPM offset matching to any HW return register.
             - Both word aligned and unaligned.
            Cross above with TPM read and write transactions.

            This CG is sampled when receiving a TPM request.'''
    }
    {
      name: tpm_read_hw_reg_cg
      desc: '''
            Cover TPM read on all HW returned registered.'''
    }
    {
      name: tpm_transfer_size_cg
      desc: '''
            Cover both TPM read and write.
            Cover request HW returned and SW handled.
            Cross above with various payload size.
              - min (1B), typical (4B), max (64B).'''
    }
    {
      name: tpm_sts_cg
      desc: '''
            Cover `tpm_sts` read and write on an active/inactive tpm access.
            Cover `tpm_sts` read with HW returned and SW handled.
            Cross above with all locality.'''
    }
    // flash/passthrough mode
    {
      name: flash_cmd_info_cg
      desc: '''
            Cover flash/passthrough mode.
            Cover all opcode enabled in cmd info.
            Cover all payload direction.
            Cover all address modes.
            Cover addr swap enable.
            Cover payload swap enable.
            Cover upload enable.
            Cover busy enable.
            Cover all dummy sizes.
            Cover number of payload lanes (single, dual and quad modes or no payload).

            cross mode, payload directions, address modes, addr/payload swap enable.
            cross mode, dummy sizes, number of lanes.
            '''
    }
    {
      name: passthrough_addr_swap_cg
      desc: '''
            Cover address swap on a transaction with both payload direction (read and program).
            Cover all bits toggled on the swap address and mask.
            Cross with filter enabled and disabled.'''
    }
    {
      name: passthrough_payload_swap_cg
      desc: '''
            Cover payload swap on a transaction with both payload direction (read and program).
            Cover all bits toggled on the swap payload and mask.
            Cross with filter enabled and disabled.'''
    }
    {
      name: passthrough_cmd_filter_cg
      desc: '''
            Cover all possible bits for command filter.
            Every opcode should be enabled and filtering checked.'''
    }
    {
      name: flash_status_cg
      desc: '''
            Cover all status bits toggled.
            Cross above with host reading status and SW reading status.
            Cover SW updating flash_status while CSB is active.'''
    }
    {
      name: flash_upload_payload_size_cg
      desc: '''
            Cover supported payload sizes for IN transactions.
            Cover supported payload sizes for OUT transactions.
            Cover upload transaction payload size.
            Cover payload size of upload transaction exceeds 256B limit (wrap around).'''
    }
    {
      name: flash_command_while_busy_set_cg
      desc: '''
            Cover host sends flash commands while busy bit is set.
            Cover above with filter enabled/disabled on that command.
            '''
    }
    {
      name: flash_read_commands_cg
      desc: '''
            Cover read status/read JEDEC/read SFDP and all other read commands configurable in the
              first 10 slots.
            Cover dummy cycle.
            Cover filter enabled/disabled.
            Cover various payload size
            Cover INTERCEPT_EN.
            Cross all above items.'''
    }
    {
      name: passthrough_mailbox_cg
      desc: '''
            Cover read commands targeting inside mailbox space.
            Cover command starting outside mailbox and crossing into mailbox space.
            Cover command starting in mailbox comming outside mailbox space.
            Cover command starting outside mailbox and crossing the entire mailbox space and coming
            outside mailbox.
            Cross above with filter on and off.'''
    }
    {
      name: flash_mailbox_cg
      desc: '''
            Cover read commands targeting inside mailbox space in the flash mode.'''
    }
    {
      name: spi_device_4B_enter_exit_command_cg
      desc: '''
            Cover both EN4B and EX4B commands.
            Cross this with the previous `cfg_addr_4b_en` value.
            '''
    }
    {
      name: sw_update_addr4b_cg
      desc: '''
            Cover SW updating addr4b to another value.
            '''
    }
    {
      name: spi_device_write_enable_disable_cg
      desc: '''
            Cover write enable and write disable commands.
            Cross this with the previous flash_status.wel value.'''
    }
    {
      name: spi_device_buffer_boundary_cg
      desc: '''
            Cover all the read commands.
            Cover buffer boundary crossing (2 buffer flips).'''
    }
    {
      name: tpm_interleave_with_flash_item_cg
      desc: '''
            Cover TPM transactions interleaving with flash transactions.'''
    }
  ]
}