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libcRSID.c
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libcRSID.c
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// cRSID lightweight (integer-only) RealSID library (with API-calls) by Hermit (Mihaly Horvath), Year 2022
// License: WTF - do what the fuck you want with the code, but please mention me as the original author
#include "libcRSID.h"
#if defined _MSC_VER || (defined __SIZEOF_FLOAT__ && __SIZEOF_FLOAT__ == 4)
#include <stdint.h>
#endif
#include <stdlib.h>
// Emulation of C64 memories and memory bus (PLA & MUXes)
static inline unsigned char *cRSID_getMemReadPtr(unsigned short address)
{
// cRSID_C64instance* const C64 = &cRSID_C64; //for faster (?) operation we use a global object as memory
if (address < 0xA000)
return &cRSID_C64.RAMbank[address];
else if (0xD000 <= address && address < 0xE000 && (cRSID_C64.RAMbank[1] & 3))
{
if (0xD400 <= address && address < 0xD419)
return &cRSID_C64.IObankWR[address]; // emulate bitfading aka SID-read of last written reg (e.g. Lift Off
// ROR $D400,x)
return &cRSID_C64.IObankRD[address];
}
else if ((address < 0xC000 && (cRSID_C64.RAMbank[1] & 3) == 3) || (0xE000 <= address && (cRSID_C64.RAMbank[1] & 2)))
return &cRSID_C64.ROMbanks[address];
return &cRSID_C64.RAMbank[address];
}
static inline unsigned char *cRSID_getMemReadPtrC64(cRSID_C64instance *C64, unsigned short address)
{
if (address < 0xA000)
return &C64->RAMbank[address];
else if (0xD000 <= address && address < 0xE000 && (C64->RAMbank[1] & 3))
{
if (0xD400 <= address && address < 0xD419)
return &cRSID_C64.IObankWR[address]; // emulate peculiar SID-read (e.g. Lift Off)
return &C64->IObankRD[address];
}
else if ((address < 0xC000 && (C64->RAMbank[1] & 3) == 3) || (0xE000 <= address && (C64->RAMbank[1] & 2)))
return &C64->ROMbanks[address];
return &C64->RAMbank[address];
}
static inline unsigned char *cRSID_getMemWritePtr(unsigned short address)
{
// cRSID_C64instance* const C64 = &cRSID_C64; //for faster (?) operation we use a global object as memory
if (address < 0xD000 || 0xE000 <= address)
return &cRSID_C64.RAMbank[address];
else if (cRSID_C64.RAMbank[1] & 3)
{ // handle SID-mirrors! (CJ in the USA workaround (writing above $d420, except SID2/SID3))
if (0xD420 <= address && address < 0xD800)
{ // CIA/VIC mirrors needed?
if (!(cRSID_C64.PSIDdigiMode && 0xD418 <= address && address < 0xD500) &&
!(cRSID_C64.SID[2].BaseAddress <= address && address < cRSID_C64.SID[2].BaseAddress + 0x20) &&
!(cRSID_C64.SID[3].BaseAddress <= address && address < cRSID_C64.SID[3].BaseAddress + 0x20) &&
!(cRSID_C64.SID[4].BaseAddress <= address && address < cRSID_C64.SID[4].BaseAddress + 0x20))
{
return &cRSID_C64.IObankWR[0xD400 +
(address & 0x1F)]; // write to $D400..D41F if not in SID2/SID3 address-space
}
else
return &cRSID_C64.IObankWR[address];
}
else
return &cRSID_C64.IObankWR[address];
}
return &cRSID_C64.RAMbank[address];
}
static inline unsigned char *cRSID_getMemWritePtrC64(cRSID_C64instance *C64, unsigned short address)
{
if (address < 0xD000 || 0xE000 <= address)
return &C64->RAMbank[address];
else if (C64->RAMbank[1] & 3)
{ // handle SID-mirrors! (CJ in the USA workaround (writing above $d420, except SID2/SID3/PSIDdigi))
if (0xD420 <= address && address < 0xD800)
{ // CIA/VIC mirrors needed?
if (!(cRSID_C64.PSIDdigiMode && 0xD418 <= address && address < 0xD500) &&
!(C64->SID[2].BaseAddress <= address && address < C64->SID[2].BaseAddress + 0x20) &&
!(C64->SID[3].BaseAddress <= address && address < C64->SID[3].BaseAddress + 0x20) &&
!(C64->SID[4].BaseAddress <= address && address < C64->SID[4].BaseAddress + 0x20))
{
return &C64->IObankWR[0xD400 +
(address & 0x1F)]; // write to $D400..D41F if not in SID2/SID3 address-space
}
else
return &C64->IObankWR[address];
}
else
return &C64->IObankWR[address];
}
return &C64->RAMbank[address];
}
/*static inline unsigned char cRSID_readMem(unsigned short address)
{
return *cRSID_getMemReadPtr(address);
}*/
static inline unsigned char cRSID_readMemC64(cRSID_C64instance *C64, unsigned short address)
{
return *cRSID_getMemReadPtrC64(C64, address);
}
/*static inline void cRSID_writeMem(unsigned short address, unsigned char data)
{
*cRSID_getMemWritePtr(address) = data;
}*/
static inline void cRSID_writeMemC64(cRSID_C64instance *C64, unsigned short address, unsigned char data)
{
*cRSID_getMemWritePtrC64(C64, address) = data;
}
static void cRSID_setROMcontent(cRSID_C64instance *C64)
{ // fill KERNAL/BASIC-ROM areas with content needed for SID-playback
int i;
static const unsigned char ROM_IRQreturnCode[9] = {0xAD, 0x0D, 0xDC, 0x68, 0xA8,
0x68, 0xAA, 0x68, 0x40}; // CIA1-acknowledge IRQ-return
static const unsigned char ROM_NMIstartCode[5] = {0x78, 0x6c, 0x18, 0x03, 0x40}; // SEI and jmp($0318)
static const unsigned char ROM_IRQBRKstartCode[19] = {
// Full IRQ-return (handling BRK with the same RAM vector as IRQ)
0x48, 0x8A, 0x48, 0x98, 0x48, 0xBA, 0xBD, 0x04, 0x01, 0x29,
0x10, 0xEA, 0xEA, 0xEA, 0xEA, 0xEA, 0x6C, 0x14, 0x03};
for (i = 0xA000; i < 0x10000; ++i)
C64->ROMbanks[i] = 0x60; // RTS (at least return if some unsupported call is made to ROM)
// for (i=0; i<sizeof(KERNAL); ++i) C64->ROMbanks[0xE000+i] = KERNAL[i];
for (i = 0xEA31; i < 0xEA7E; ++i)
C64->ROMbanks[i] = 0xEA; // NOP (full IRQ-return leading to simple IRQ-return without other tasks)
for (i = 0; i < 9; ++i)
C64->ROMbanks[0xEA7E + i] = ROM_IRQreturnCode[i];
for (i = 0; i < 4; ++i)
C64->ROMbanks[0xFE43 + i] = ROM_NMIstartCode[i];
for (i = 0; i < 19; ++i)
C64->ROMbanks[0xFF48 + i] = ROM_IRQBRKstartCode[i];
C64->ROMbanks[0xFFFB] = 0xFE;
C64->ROMbanks[0xFFFA] = 0x43; // ROM NMI-vector
C64->ROMbanks[0xFFFF] = 0xFF;
C64->ROMbanks[0xFFFE] = 0x48; // ROM IRQ-vector
// copy KERNAL & BASIC ROM contents into the RAM under them? (So PSIDs that don't select bank correctly will work
// better.)
for (i = 0xA000; i < 0x10000; ++i)
C64->RAMbank[i] = C64->ROMbanks[i];
}
static void cRSID_initMem(cRSID_C64instance *C64)
{ // set default values that normally KERNEL ensures after startup/reset (only SID-playback related)
static int i;
// data required by both PSID and RSID (according to HVSC SID_file_format.txt):
cRSID_writeMemC64(C64, 0x02A6, C64->VideoStandard); //$02A6 should be pre-set to: 0:NTSC / 1:PAL
cRSID_writeMemC64(C64, 0x0001, 0x37); // initialize bank-reg. (ROM-banks and IO enabled)
// if (C64->ROMbanks[0xE000]==0) { //wasn't a KERNAL-ROM loaded? (e.g. PSID)
cRSID_writeMemC64(C64, 0x00CB, 0x40); // Some tunes might check for keypress here (e.g. Master Blaster Intro)
// if(C64->RealSIDmode) {
cRSID_writeMemC64(C64, 0x0315, 0xEA);
cRSID_writeMemC64(C64, 0x0314, 0x31); // IRQ
cRSID_writeMemC64(C64, 0x0319, 0xEA /*0xFE*/);
cRSID_writeMemC64(C64, 0x0318, 0x81 /*0x47*/); // NMI
//}
for (i = 0xD000; i < 0xD7FF; ++i)
C64->IObankRD[i] = C64->IObankWR[i] = 0; // initialize the whole IO area for a known base-state
if (C64->RealSIDmode)
{
C64->IObankWR[0xD012] = 0x37;
C64->IObankWR[0xD011] = 0x8B;
} // else C64->IObankWR[0xD012] = 0;
// C64->IObankWR[0xD019] = 0; //PSID: rasterrow: any value <= $FF, IRQ:enable later if there is VIC-timingsource
C64->IObankRD[0xDC00] = 0x10;
C64->IObankRD[0xDC01] = 0xFF; // Imitate CIA1 keyboard/joy port, some tunes check if buttons are not pressed
if (C64->VideoStandard)
{
C64->IObankWR[0xDC04] = 0x24;
C64->IObankWR[0xDC05] = 0x40;
} // initialize CIAs
else
{
C64->IObankWR[0xDC04] = 0x95;
C64->IObankWR[0xDC05] = 0x42;
}
if (C64->RealSIDmode)
C64->IObankWR[0xDC0D] =
0x81; // Reset-default, but for PSID CIA1 TimerA IRQ should be enabled anyway if SID is CIA-timed
C64->IObankWR[0xDC0E] = 0x01; // some tunes (and PSID doc) expect already running CIA (Reset-default)
C64->IObankWR[0xDC0F] = 0x00; // All counters other than CIA1 TimerA should be disabled and set to 0xFF for PSID:
C64->IObankWR[0xDD00] = C64->IObankRD[0xDD00] = 0x03; // VICbank-selector default
C64->IObankWR[0xDD04] = C64->IObankWR[0xDD05] = 0xFF; // C64->IObankWR[0xDD0E] = C64->IObank[0xDD0F] = 0x00;
//}
}
// cRSID CPU-emulation
static inline void cRSID_writeCIAIRQmask(cRSID_CIAinstance *CIA, unsigned char value)
{
if (value & 0x80)
CIA->BasePtrWR[0xD] |= (value & 0x1F);
else
CIA->BasePtrWR[0xD] &= ~(value & 0x1F);
}
static inline void cRSID_acknowledgeCIAIRQ(cRSID_CIAinstance *CIA)
{
CIA->BasePtrRD[0xD] = 0x00; // reading a CIA interrupt-register clears its read-part and IRQ-flag
}
static inline void cRSID_acknowledgeVICrasterIRQ(cRSID_VICinstance *VIC)
{
enum VICregisters
{
INTERRUPT = 0x19
};
enum InterruptBitVal
{
VIC_IRQ = 0x80,
RASTERROW_MATCH_IRQ = 0x01
};
// An 1 is to be written into the IRQ-flag (bit0) of $d019 to clear it and deassert IRQ signal
// if (VIC->BasePtrWR[INTERRUPT] & RASTERROW_MATCH_IRQ) { //acknowledge raster-interrupt by writing to $d019 bit0?
// But oftentimes INC/LSR/etc. RMW commands are used to acknowledge VIC IRQ, they work on real
// CPU because it writes the unmodified original value itself to memory before writing the modified there
VIC->BasePtrWR[INTERRUPT] &= ~RASTERROW_MATCH_IRQ; // prepare for next acknowledge-detection
VIC->BasePtrRD[INTERRUPT] &= ~(VIC_IRQ | RASTERROW_MATCH_IRQ); // remove IRQ flag and state
//}
}
enum StatusFlagBitValues
{
N = 0x80,
V = 0x40,
B = 0x10,
D = 0x08,
I = 0x04,
Z = 0x02,
C = 0x01
};
static const unsigned char FlagSwitches[] = {0x01, 0x21, 0x04, 0x24, 0x00, 0x40, 0x08, 0x28},
BranchFlags[] = {0x80, 0x40, 0x01, 0x02};
static cRSID_C64instance *const C64 = &cRSID_C64;
static char Cycles, SamePage;
static unsigned char IR, ST, X, Y;
static short int A, SP, T;
static unsigned int PC, Addr, PrevPC;
static void loadReg(cRSID_CPUinstance *CPU)
{
PC = CPU->PC;
SP = CPU->SP;
ST = CPU->ST;
A = CPU->A;
X = CPU->X;
Y = CPU->Y;
}
static void storeReg(cRSID_CPUinstance *CPU)
{
CPU->PC = PC;
CPU->SP = SP;
CPU->ST = ST;
CPU->A = A;
CPU->X = X;
CPU->Y = Y;
}
static unsigned char rd(unsigned short address)
{
static unsigned char value;
value = *cRSID_getMemReadPtr(address);
if (C64->RealSIDmode)
{
if (C64->RAMbank[1] & 3)
{
if (address == 0xDC0D)
{
cRSID_acknowledgeCIAIRQ(&C64->CIA[1]);
}
else if (address == 0xDD0D)
{
cRSID_acknowledgeCIAIRQ(&C64->CIA[2]);
}
}
}
return value;
}
static void wr(unsigned short address, unsigned char data)
{
*cRSID_getMemWritePtr(address) = data;
if (C64->RealSIDmode && (C64->RAMbank[1] & 3))
{
// if(data&1) { //only writing 1 to $d019 bit0 would acknowledge, not any value (but RMW instructions write
// $d019 back before mod.)
if (address == 0xD019)
{
cRSID_acknowledgeVICrasterIRQ(&C64->VIC);
}
//}
}
}
static void wr2(unsigned short address, unsigned char data)
{ // PSID-hack specific memory-write
static int Tmp;
*cRSID_getMemWritePtr(address) = data;
if (C64->RAMbank[1] & 3)
{
if (C64->RealSIDmode)
{
if (address == 0xDC0D)
cRSID_writeCIAIRQmask(&C64->CIA[1], data);
else if (address == 0xDD0D)
cRSID_writeCIAIRQmask(&C64->CIA[2], data);
else if (address == 0xDD0C)
C64->IObankRD[address] = data; // mirror WR to RD (e.g. Wonderland_XIII_tune_1.sid)
else if (address == 0xD019 && data & 1)
{ // only writing 1 to $d019 bit0 would acknowledge
cRSID_acknowledgeVICrasterIRQ(&C64->VIC);
}
}
else
{
switch (address)
{
case 0xDC05:
case 0xDC04:
if (C64->TimerSource)
{ // dynamic CIA-setting (Galway/Rubicon workaround)
C64->FrameCycles =
((C64->IObankWR[0xDC04] + (C64->IObankWR[0xDC05] << 8))); //<< 4) / C64->SampleClockRatio;
}
break;
case 0xDC08:
C64->IObankRD[0xDC08] = data;
break; // refresh TOD-clock
case 0xDC09:
C64->IObankRD[0xDC09] = data;
break; // refresh TOD-clock
case 0xD012: // dynamic VIC IRQ-rasterline setting (Microprose Soccer V1 workaround)
if (C64->PrevRasterLine >= 0)
{ // was $d012 set before? (or set only once?)
if (C64->IObankWR[0xD012] != C64->PrevRasterLine)
{
Tmp = C64->IObankWR[0xD012] - C64->PrevRasterLine;
if (Tmp < 0)
Tmp += C64->VIC.RasterLines;
C64->FrameCycleCnt = C64->FrameCycles - Tmp * C64->VIC.RasterRowCycles;
}
}
C64->PrevRasterLine = C64->IObankWR[0xD012];
break;
}
}
}
}
static void addrModeImmediate(void)
{
++PC;
Addr = PC;
Cycles = 2;
} // imm.
static void addrModeZeropage(void)
{
++PC;
Addr = rd(PC);
Cycles = 3;
} // zp
static void addrModeAbsolute(void)
{
++PC;
Addr = rd(PC);
++PC;
Addr += rd(PC) << 8;
Cycles = 4;
} // abs
static void addrModeZeropageXindexed(void)
{
++PC;
Addr = (rd(PC) + X) & 0xFF;
Cycles = 4;
} // zp,x (with zeropage-wraparound of 6502)
static void addrModeZeropageYindexed(void)
{
++PC;
Addr = (rd(PC) + Y) & 0xFF;
Cycles = 4;
} // zp,y (with zeropage-wraparound of 6502)
static void addrModeXindexed(void)
{ // abs,x (only STA is 5 cycles, others are 4 if page not crossed, RMW:7)
++PC;
Addr = rd(PC) + X;
++PC;
SamePage = (Addr <= 0xFF);
Addr += rd(PC) << 8;
Cycles = 5;
}
static void addrModeYindexed(void)
{ // abs,y (only STA is 5 cycles, others are 4 if page not crossed, RMW:7)
++PC;
Addr = rd(PC) + Y;
++PC;
SamePage = (Addr <= 0xFF);
Addr += rd(PC) << 8;
Cycles = 5;
}
static void addrModeIndirectYindexed(void)
{ // (zp),y (only STA is 6 cycles, others are 5 if page not crossed, RMW:8)
++PC;
Addr = rd(rd(PC)) + Y;
SamePage = (Addr <= 0xFF);
Addr += rd((rd(PC) + 1) & 0xFF) << 8;
Cycles = 6;
}
static void addrModeXindexedIndirect(void)
{ // (zp,x)
++PC;
Addr = (rd(rd(PC) + X) & 0xFF) + ((rd(rd(PC) + X + 1) & 0xFF) << 8);
Cycles = 6;
}
static void clrC(void)
{
ST &= ~C;
} // clear Carry-flag
static void setC(unsigned char expr)
{
ST &= ~C;
ST |= (expr != 0);
} // set Carry-flag if expression is not zero
static void clrNZC(void)
{
ST &= ~(N | Z | C);
} // clear flags
static void clrNVZC(void)
{
ST &= ~(N | V | Z | C);
} // clear flags
static void setNZbyA(void)
{
ST &= ~(N | Z);
ST |= ((!A) << 1) | (A & N);
} // set Negative-flag and Zero-flag based on result in Accumulator
static void setNZbyT(void)
{
T &= 0xFF;
ST &= ~(N | Z);
ST |= ((!T) << 1) | (T & N);
}
static void setNZbyX(void)
{
ST &= ~(N | Z);
ST |= ((!X) << 1) | (X & N);
} // set Negative-flag and Zero-flag based on result in X-register
static void setNZbyY(void)
{
ST &= ~(N | Z);
ST |= ((!Y) << 1) | (Y & N);
} // set Negative-flag and Zero-flag based on result in Y-register
static void setNZbyM(void)
{
ST &= ~(N | Z);
ST |= ((!rd(Addr)) << 1) | (rd(Addr) & N);
} // set Negative-flag and Zero-flag based on result at Memory-Address
static void setNZCbyAdd(void)
{
ST &= ~(N | Z | C);
ST |= (A & N) | (A > 255);
A &= 0xFF;
ST |= (!A) << 1;
} // after increase/addition
static void setVbyAdd(unsigned char M)
{
ST &= ~V;
ST |= ((~(T ^ M)) & (T ^ A) & N) >> 1;
} // calculate V-flag from A and T (previous A) and input2 (Memory)
static void setNZCbySub(signed short *obj)
{
ST &= ~(N | Z | C);
ST |= (*obj & N) | (*obj >= 0);
*obj &= 0xFF;
ST |= ((!(*obj)) << 1);
}
static void push(unsigned char value)
{
C64->RAMbank[0x100 + SP] = value;
--SP;
SP &= 0xFF;
} // push a value to stack
static unsigned char pop(void)
{
++SP;
SP &= 0xFF;
return C64->RAMbank[0x100 + SP];
} // pop a value from stack
static void cRSID_initCPU(cRSID_CPUinstance *CPU, unsigned short mempos)
{
CPU->PC = mempos;
CPU->A = 0;
CPU->X = 0;
CPU->Y = 0;
CPU->ST = 0x04;
CPU->SP = 0xFF;
CPU->PrevNMI = 0;
}
static unsigned char cRSID_emulateCPU(void)
{ // the CPU emulation for SID/PRG playback (ToDo: CIA/VIC-IRQ/NMI/RESET vectors, BCD-mode)
IR = ST = X = Y = 0;
A = SP = T = 0;
PC = Addr = PrevPC = 0;
loadReg(&C64->CPU);
PrevPC = PC;
IR = rd(PC);
Cycles = 2;
SamePage = 0; //'Cycles': ensure smallest 6510 runtime (for implied/register instructions)
if (IR & 1)
{ // nybble2: 1/5/9/D:accu.instructions, 3/7/B/F:illegal opcodes
switch ((IR & 0x1F) >> 1)
{ // value-forming to cause jump-table //PC wraparound not handled inside to save codespace
case 0:
case 1:
addrModeXindexedIndirect();
break; //(zp,x)
case 2:
case 3:
addrModeZeropage();
break;
case 4:
case 5:
addrModeImmediate();
break;
case 6:
case 7:
addrModeAbsolute();
break;
case 8:
case 9:
addrModeIndirectYindexed();
break; //(zp),y (5..6 cycles, 8 for R-M-W)
case 0xA:
addrModeZeropageXindexed();
break; // zp,x
case 0xB:
if ((IR & 0xC0) != 0x80)
addrModeZeropageXindexed(); // zp,x for illegal opcodes
else
addrModeZeropageYindexed(); // zp,y for LAX/SAX illegal opcodes
break;
case 0xC:
case 0xD:
addrModeYindexed();
break;
case 0xE:
addrModeXindexed();
break;
case 0xF:
if ((IR & 0xC0) != 0x80)
addrModeXindexed(); // abs,x for illegal opcodes
else
addrModeYindexed(); // abs,y for LAX/SAX illegal opcodes
break;
}
Addr &= 0xFFFF;
switch ((IR & 0xE0) >> 5)
{ // value-forming to cause gapless case-values and faster jump-table creation from switch-case
case 0:
if ((IR & 0x1F) != 0xB)
{ // ORA / SLO(ASO)=ASL+ORA
if ((IR & 3) == 3)
{
clrNZC();
setC(rd(Addr) >= N);
wr(Addr, rd(Addr) << 1);
Cycles += 2;
} // for SLO
else
Cycles -= SamePage;
A |= rd(Addr);
setNZbyA(); // ORA
}
else
{
A &= rd(Addr);
setNZbyA();
setC(A >= N);
} // ANC (AND+Carry=bit7)
break;
case 1:
if ((IR & 0x1F) != 0xB)
{ // AND / RLA (ROL+AND)
if ((IR & 3) == 3)
{ // for RLA
T = (rd(Addr) << 1) + (ST & C);
clrNZC();
setC(T > 255);
T &= 0xFF;
wr(Addr, T);
Cycles += 2;
}
else
Cycles -= SamePage;
A &= rd(Addr);
setNZbyA(); // AND
}
else
{
A &= rd(Addr);
setNZbyA();
setC(A >= N);
} // ANC (AND+Carry=bit7)
break;
case 2:
if ((IR & 0x1F) != 0xB)
{ // EOR / SRE(LSE)=LSR+EOR
if ((IR & 3) == 3)
{
clrNZC();
setC(rd(Addr) & 1);
wr(Addr, rd(Addr) >> 1);
Cycles += 2;
} // for SRE
else
Cycles -= SamePage;
A ^= rd(Addr);
setNZbyA(); // EOR
}
else
{
A &= rd(Addr);
setC(A & 1);
A >>= 1;
A &= 0xFF;
setNZbyA();
} // ALR(ASR)=(AND+LSR)
break;
case 3:
if ((IR & 0x1F) != 0xB)
{ // RRA (ROR+ADC) / ADC
if ((IR & 3) == 3)
{ // for RRA
T = (rd(Addr) >> 1) + ((ST & C) << 7);
clrNZC();
setC(T & 1);
wr(Addr, T);
Cycles += 2;
}
else
Cycles -= SamePage;
T = A;
A += rd(Addr) + (ST & C);
if ((ST & D) && (A & 0xF) > 9)
{
A += 0x10;
A &= 0xF0;
} // BCD?
setNZCbyAdd();
setVbyAdd(rd(Addr)); // ADC
}
else
{ // ARR (AND+ROR, bit0 not going to C, but C and bit7 get exchanged.)
A &= rd(Addr);
T += rd(Addr) + (ST & C);
clrNVZC();
setC(T > 255);
setVbyAdd(rd(Addr)); // V-flag set by intermediate ADC mechanism: (A&mem)+mem
T = A;
A = (A >> 1) + ((ST & C) << 7);
setC(T >= N);
setNZbyA();
}
break;
case 4:
if ((IR & 0x1F) == 0xB)
{
A = X & rd(Addr);
setNZbyA();
} // XAA (TXA+AND), highly unstable on real 6502!
else if ((IR & 0x1F) == 0x1B)
{
SP = A & X;
wr(Addr, SP & ((Addr >> 8) + 1));
} // TAS(SHS) (SP=A&X, mem=S&H} - unstable on real 6502
else
{
wr2(Addr, A & (((IR & 3) == 3) ? X : 0xFF));
} // STA / SAX (at times same as AHX/SHX/SHY) (illegal)
break;
case 5:
if ((IR & 0x1F) != 0x1B)
{
A = rd(Addr);
if ((IR & 3) == 3)
X = A;
} // LDA / LAX (illegal, used by my 1 rasterline player) (LAX #imm is unstable on C64)
else
{
A = X = SP = rd(Addr) & SP;
} // LAS(LAR)
setNZbyA();
Cycles -= SamePage;
break;
case 6:
if ((IR & 0x1F) != 0xB)
{ // CMP / DCP(DEC+CMP)
if ((IR & 3) == 3)
{
wr(Addr, rd(Addr) - 1);
Cycles += 2;
} // DCP
else
Cycles -= SamePage;
T = A - rd(Addr);
}
else
{
X = T = (A & X) - rd(Addr);
} // SBX(AXS) //SBX (AXS) (CMP+DEX at the same time)
setNZCbySub(&T);
break;
case 7:
if ((IR & 3) == 3 && (IR & 0x1F) != 0xB)
{
wr(Addr, rd(Addr) + 1);
Cycles += 2;
} // ISC(ISB)=INC+SBC / SBC
else
Cycles -= SamePage;
T = A;
A -= rd(Addr) + !(ST & C);
setNZCbySub(&A);
setVbyAdd(~rd(Addr));
break;
}
}
else if (IR & 2)
{ // nybble2: 2:illegal/LDX, 6:A/X/INC/DEC, A:Accu-shift/reg.transfer/NOP, E:shift/X/INC/DEC
switch (IR & 0x1F)
{ // Addressing modes
case 2:
addrModeImmediate();
break;
case 6:
addrModeZeropage();
break;
case 0xE:
addrModeAbsolute();
break;
case 0x16:
if ((IR & 0xC0) != 0x80)
addrModeZeropageXindexed(); // zp,x
else
addrModeZeropageYindexed(); // zp,y
break;
case 0x1E:
if ((IR & 0xC0) != 0x80)
addrModeXindexed(); // abs,x
else
addrModeYindexed(); // abs,y
break;
}
Addr &= 0xFFFF;
switch ((IR & 0xE0) >> 5)
{
case 0:
clrC();
case 1:
if ((IR & 0xF) == 0xA)
{
A = (A << 1) + (ST & C);
setNZCbyAdd();
} // ASL/ROL (Accu)
else
{
T = (rd(Addr) << 1) + (ST & C);
setC(T > 255);
setNZbyT();
wr(Addr, T);
Cycles += 2;
} // RMW (Read-Write-Modify)
break;
case 2:
clrC();
case 3:
if ((IR & 0xF) == 0xA)
{
T = A;
A = (A >> 1) + ((ST & C) << 7);
setC(T & 1);
A &= 0xFF;
setNZbyA();
} // LSR/ROR (Accu)
else
{
T = (rd(Addr) >> 1) + ((ST & C) << 7);
setC(rd(Addr) & 1);
setNZbyT();
wr(Addr, T);
Cycles += 2;
} // memory (RMW)
break;
case 4:
if (IR & 4)
{
wr2(Addr, X);
} // STX
else if (IR & 0x10)
SP = X; // TXS
else
{
A = X;
setNZbyA();
} // TXA
break;
case 5:
if ((IR & 0xF) != 0xA)
{
X = rd(Addr);
Cycles -= SamePage;
} // LDX
else if (IR & 0x10)
X = SP; // TSX
else
X = A; // TAX
setNZbyX();
break;
case 6:
if (IR & 4)
{
wr(Addr, rd(Addr) - 1);
setNZbyM();
Cycles += 2;
} // DEC
else
{
--X;
setNZbyX();
} // DEX
break;
case 7:
if (IR & 4)
{
wr(Addr, rd(Addr) + 1);
setNZbyM();
Cycles += 2;
} // INC/NOP
break;
}
}
else if ((IR & 0xC) == 8)
{ // nybble2: 8:register/statusflag
if (IR & 0x10)
{
if (IR == 0x98)
{
A = Y;
setNZbyA();
} // TYA
else
{ // CLC/SEC/CLI/SEI/CLV/CLD/SED
if (FlagSwitches[IR >> 5] & 0x20)
ST |= (FlagSwitches[IR >> 5] & 0xDF);
else
ST &= ~(FlagSwitches[IR >> 5] & 0xDF);
}
}
else
{
switch ((IR & 0xF0) >> 5)
{
case 0:
push(ST);
Cycles = 3;
break; // PHP
case 1:
ST = pop();
Cycles = 4;
break; // PLP
case 2:
push(A);
Cycles = 3;
break; // PHA
case 3:
A = pop();
setNZbyA();
Cycles = 4;
break; // PLA
case 4:
--Y;
setNZbyY();
break; // DEY
case 5:
Y = A;
setNZbyY();
break; // TAY
case 6:
++Y;
setNZbyY();
break; // INY
case 7:
++X;
setNZbyX();
break; // INX
}
}
}
else
{ // nybble2: 0: control/branch/Y/compare 4: Y/compare C:Y/compare/JMP
if ((IR & 0x1F) == 0x10)
{ // BPL/BMI/BVC/BVS/BCC/BCS/BNE/BEQ relative branch
++PC;
T = rd(PC);
if (T & 0x80)
T -= 0x100;
if (IR & 0x20)
{
if (ST & BranchFlags[IR >> 6])
{
PC += T;
Cycles = 3;
}
}
else
{
if (!(ST & BranchFlags[IR >> 6]))
{
PC += T;
Cycles = 3;
} // plus 1 cycle if page is crossed?
}
}
else
{ // nybble2: 0:Y/control/Y/compare 4:Y/compare C:Y/compare/JMP
switch (IR & 0x1F)
{ // Addressing modes
case 0:
addrModeImmediate();
break; // imm. (or abs.low for JSR/BRK)
case 4:
addrModeZeropage();
break;
case 0xC:
addrModeAbsolute();
break;
case 0x14:
addrModeZeropageXindexed();
break; // zp,x
case 0x1C:
addrModeXindexed();
break; // abs,x
}
Addr &= 0xFFFF;
switch ((IR & 0xE0) >> 5)
{
case 0:
if (!(IR & 4))
{ // BRK / NOP-absolute/abs,x/zp/zp,x
push((PC + 2 - 1) >> 8);
push((PC + 2 - 1) & 0xFF);