diff --git a/cpus/ibex_custom_pr2166_pregenerated/cellift/generated/sv2v_out.v b/cpus/ibex_custom_pr2166_pregenerated/cellift/generated/sv2v_out.v
index d2006595..1ae3ae27 100644
--- a/cpus/ibex_custom_pr2166_pregenerated/cellift/generated/sv2v_out.v
+++ b/cpus/ibex_custom_pr2166_pregenerated/cellift/generated/sv2v_out.v
@@ -10960,263 +10960,6 @@ module alert_handler_reg_top (
 	assign unused_wdata = ^reg_wdata;
 	assign unused_be = ^reg_be;
 endmodule
-module cellift_rv_core_ibex_mem_top (
-	clk_i,
-	rst_ni,
-	clk_edn_i,
-	rst_edn_ni,
-	clk_esc_i,
-	rst_esc_ni,
-	rst_cpu_n_o,
-	ram_cfg_i,
-	hart_id_i,
-	boot_addr_i,
-	instr_mem_req_o,
-	instr_mem_gnt_i,
-	instr_mem_addr_o,
-	instr_mem_wdata_o,
-	instr_mem_strb_o,
-	instr_mem_we_o,
-	instr_mem_rdata_i,
-	data_mem_req_o,
-	data_mem_gnt_i,
-	data_mem_addr_o,
-	data_mem_wdata_o,
-	data_mem_strb_o,
-	data_mem_we_o,
-	data_mem_rdata_i,
-	irq_software_i,
-	irq_timer_i,
-	irq_external_i,
-	esc_tx_i,
-	esc_rx_o,
-	nmi_wdog_i,
-	debug_req_i,
-	crash_dump_o,
-	pwrmgr_cpu_en_i,
-	lc_cpu_en_i,
-	pwrmgr_o,
-	scan_rst_ni,
-	scanmode_i,
-	cfg_tl_d_i,
-	cfg_tl_d_o,
-	edn_o,
-	edn_i,
-	clk_otp_i,
-	rst_otp_ni,
-	icache_otp_key_o,
-	icache_otp_key_i,
-	fpga_info_i,
-	alert_rx_i,
-	alert_tx_o
-);
-	parameter [31:0] InstrMemAw = 20;
-	parameter [31:0] DataMemAw = 20;
-	input wire clk_i;
-	input wire rst_ni;
-	input wire clk_edn_i;
-	input wire rst_edn_ni;
-	input wire clk_esc_i;
-	input wire rst_esc_ni;
-	output wire rst_cpu_n_o;
-	input wire [9:0] ram_cfg_i;
-	input wire [31:0] hart_id_i;
-	input wire [31:0] boot_addr_i;
-	output wire instr_mem_req_o;
-	input wire instr_mem_gnt_i;
-	output wire [InstrMemAw:0] instr_mem_addr_o;
-	output wire [31:0] instr_mem_wdata_o;
-	output wire [31:0] instr_mem_strb_o;
-	output wire instr_mem_we_o;
-	input wire [31:0] instr_mem_rdata_i;
-	output wire data_mem_req_o;
-	input wire data_mem_gnt_i;
-	output wire [InstrMemAw:0] data_mem_addr_o;
-	output wire [31:0] data_mem_wdata_o;
-	output wire [31:0] data_mem_strb_o;
-	output wire data_mem_we_o;
-	input wire [31:0] data_mem_rdata_i;
-	input wire irq_software_i;
-	input wire irq_timer_i;
-	input wire irq_external_i;
-	input wire [1:0] esc_tx_i;
-	output wire [1:0] esc_rx_o;
-	input wire nmi_wdog_i;
-	input wire debug_req_i;
-	output wire [159:0] crash_dump_o;
-	localparam signed [31:0] lc_ctrl_pkg_TxWidth = 4;
-	input wire [3:0] pwrmgr_cpu_en_i;
-	input wire [3:0] lc_cpu_en_i;
-	output wire [0:0] pwrmgr_o;
-	input scan_rst_ni;
-	localparam signed [31:0] prim_mubi_pkg_MuBi4Width = 4;
-	input wire [3:0] scanmode_i;
-	localparam signed [31:0] tlul_pkg_DataIntgWidth = 7;
-	localparam signed [31:0] tlul_pkg_H2DCmdIntgWidth = 7;
-	localparam signed [31:0] top_pkg_TL_AIW = 8;
-	localparam signed [31:0] top_pkg_TL_AW = 32;
-	localparam signed [31:0] top_pkg_TL_DW = 32;
-	localparam signed [31:0] top_pkg_TL_DBW = top_pkg_TL_DW >> 3;
-	localparam signed [31:0] top_pkg_TL_SZW = $clog2($clog2(top_pkg_TL_DBW) + 1);
-	input wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 23:0] cfg_tl_d_i;
-	localparam signed [31:0] tlul_pkg_D2HRspIntgWidth = 7;
-	localparam signed [31:0] top_pkg_TL_DIW = 1;
-	output wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + (tlul_pkg_D2HRspIntgWidth + tlul_pkg_DataIntgWidth)) + 1:0] cfg_tl_d_o;
-	output wire [0:0] edn_o;
-	localparam [31:0] edn_pkg_ENDPOINT_BUS_WIDTH = 32;
-	input wire [33:0] edn_i;
-	input clk_otp_i;
-	input rst_otp_ni;
-	output wire [0:0] icache_otp_key_o;
-	localparam signed [31:0] otp_ctrl_pkg_SramKeyWidth = 128;
-	localparam signed [31:0] otp_ctrl_pkg_SramNonceWidth = 128;
-	input wire [257:0] icache_otp_key_i;
-	input [31:0] fpga_info_i;
-	localparam signed [31:0] rv_core_ibex_reg_pkg_NumAlerts = 4;
-	input wire [15:0] alert_rx_i;
-	output wire [7:0] alert_tx_o;
-	wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + (tlul_pkg_D2HRspIntgWidth + tlul_pkg_DataIntgWidth)) + 1:0] tl_i_toibex;
-	wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 23:0] tl_i_fromibex;
-	wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + (tlul_pkg_D2HRspIntgWidth + tlul_pkg_DataIntgWidth)) + 1:0] tl_d_toibex;
-	wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 23:0] tl_d_fromibex;
-	wire instr_rvalid_d;
-	reg instr_rvalid_q;
-	wire data_rvalid_d;
-	reg data_rvalid_q;
-	assign instr_rvalid_d = instr_mem_req_o & ~instr_mem_we_o;
-	assign data_rvalid_d = data_mem_req_o & ~data_mem_we_o;
-	always @(posedge clk_i)
-		if (~rst_ni) begin
-			instr_rvalid_q <= 1'sb0;
-			data_rvalid_q <= 1'sb0;
-		end
-		else begin
-			instr_rvalid_q <= instr_rvalid_d;
-			data_rvalid_q <= data_rvalid_d;
-		end
-	function automatic [3:0] sv2v_cast_AC3DB;
-		input reg [3:0] inp;
-		sv2v_cast_AC3DB = inp;
-	endfunction
-	noerr_tlul_adapter_sram #(
-		.SramAw(InstrMemAw),
-		.SramDw(32),
-		.Outstanding(1),
-		.ByteAccess(1),
-		.ErrOnWrite(0),
-		.ErrOnRead(0),
-		.CmdIntgCheck(0),
-		.EnableRspIntgGen(0),
-		.EnableDataIntgGen(0),
-		.EnableDataIntgPt(0)
-	) i_instr_tlul_adapter_sram(
-		.clk_i(clk_i),
-		.rst_ni(rst_ni),
-		.tl_i(tl_i_fromibex),
-		.tl_o(tl_i_toibex),
-		.en_ifetch_i(sv2v_cast_AC3DB(4'h6)),
-		.req_o(instr_mem_req_o),
-		.gnt_i(instr_mem_gnt_i),
-		.we_o(instr_mem_we_o),
-		.addr_o(instr_mem_addr_o),
-		.wdata_o(instr_mem_wdata_o),
-		.wmask_o(instr_mem_strb_o),
-		.rdata_i(instr_mem_rdata_i),
-		.rvalid_i(instr_rvalid_q),
-		.rerror_i(2'b00)
-	);
-	noerr_tlul_adapter_sram #(
-		.SramAw(DataMemAw),
-		.SramDw(32),
-		.Outstanding(1),
-		.ByteAccess(1),
-		.ErrOnWrite(0),
-		.ErrOnRead(0),
-		.CmdIntgCheck(0),
-		.EnableRspIntgGen(0),
-		.EnableDataIntgGen(0),
-		.EnableDataIntgPt(0)
-	) i_data_tlul_adapter_sram(
-		.clk_i(clk_i),
-		.rst_ni(rst_ni),
-		.tl_i(tl_d_fromibex),
-		.tl_o(tl_d_toibex),
-		.en_ifetch_i(sv2v_cast_AC3DB(4'h6)),
-		.req_o(data_mem_req_o),
-		.gnt_i(data_mem_gnt_i),
-		.we_o(data_mem_we_o),
-		.addr_o(data_mem_addr_o),
-		.wdata_o(data_mem_wdata_o),
-		.wmask_o(data_mem_strb_o),
-		.rdata_i(data_mem_rdata_i),
-		.rvalid_i(data_rvalid_q),
-		.rerror_i(2'b00)
-	);
-	localparam signed [31:0] ibex_pkg_LfsrWidth = 32;
-	localparam [159:0] ibex_pkg_RndCnstLfsrPermDefault = 160'h1e35ecba467fd1b12e958152c04fa43878a8daed;
-	localparam [31:0] ibex_pkg_RndCnstLfsrSeedDefault = 32'hac533bf4;
-	noerr_rv_core_ibex #(
-		.PMPEnable(1'b0),
-		.PMPGranularity(0),
-		.PMPNumRegions(4),
-		.MHPMCounterNum(0),
-		.MHPMCounterWidth(40),
-		.RV32E(1'b0),
-		.RV32M(32'sd1),
-		.RV32B(32'sd0),
-		.BranchTargetALU(1'b0),
-		.WritebackStage(1'b1),
-		.ICache(1'b0),
-		.ICacheECC(1'b0),
-		.BranchPredictor(1'b0),
-		.DbgTriggerEn(1'b0),
-		.DbgHwBreakNum(1),
-		.RndCnstLfsrSeed(ibex_pkg_RndCnstLfsrSeedDefault),
-		.RndCnstLfsrPerm(ibex_pkg_RndCnstLfsrPermDefault),
-		.SecureIbex(1'b0),
-		.DmHaltAddr(32'h1a110800),
-		.DmExceptionAddr(32'h01a11080)
-	) i_rv_core_ibex(
-		.clk_i(clk_i),
-		.rst_ni(rst_ni),
-		.clk_edn_i(clk_edn_i),
-		.rst_edn_ni(rst_edn_ni),
-		.clk_esc_i(clk_esc_i),
-		.rst_esc_ni(rst_esc_ni),
-		.rst_cpu_n_o(rst_cpu_n_o),
-		.ram_cfg_i(ram_cfg_i),
-		.hart_id_i(hart_id_i),
-		.boot_addr_i(boot_addr_i),
-		.corei_tl_h_o(tl_i_fromibex),
-		.corei_tl_h_i(tl_i_toibex),
-		.cored_tl_h_o(tl_d_fromibex),
-		.cored_tl_h_i(tl_d_toibex),
-		.irq_software_i(irq_software_i),
-		.irq_timer_i(irq_timer_i),
-		.irq_external_i(irq_external_i),
-		.esc_tx_i(esc_tx_i),
-		.esc_rx_o(esc_rx_o),
-		.nmi_wdog_i(nmi_wdog_i),
-		.debug_req_i(debug_req_i),
-		.crash_dump_o(crash_dump_o),
-		.lc_cpu_en_i(lc_cpu_en_i),
-		.pwrmgr_cpu_en_i(pwrmgr_cpu_en_i),
-		.pwrmgr_o(pwrmgr_o),
-		.scan_rst_ni(scan_rst_ni),
-		.scanmode_i(scanmode_i),
-		.cfg_tl_d_i(cfg_tl_d_i),
-		.cfg_tl_d_o(cfg_tl_d_o),
-		.edn_o(edn_o),
-		.edn_i(edn_i),
-		.clk_otp_i(clk_otp_i),
-		.rst_otp_ni(rst_otp_ni),
-		.icache_otp_key_o(icache_otp_key_o),
-		.icache_otp_key_i(icache_otp_key_i),
-		.fpga_info_i(fpga_info_i),
-		.alert_rx_i(alert_rx_i),
-		.alert_tx_o(alert_tx_o)
-	);
-endmodule
 module ibex_alu (
 	operator_i,
 	operand_a_i,
@@ -21098,1110 +20841,6 @@ module ibex_wb_stage (
 	assign rf_wdata_wb_o = ({32 {rf_wdata_wb_mux_we[0]}} & rf_wdata_wb_mux[0]) | ({32 {rf_wdata_wb_mux_we[1]}} & rf_wdata_wb_mux[1]);
 	assign rf_we_wb_o = |rf_wdata_wb_mux_we;
 endmodule
-module noerr_rv_core_ibex (
-	clk_i,
-	rst_ni,
-	clk_edn_i,
-	rst_edn_ni,
-	clk_esc_i,
-	rst_esc_ni,
-	rst_cpu_n_o,
-	ram_cfg_i,
-	hart_id_i,
-	boot_addr_i,
-	corei_tl_h_o,
-	corei_tl_h_i,
-	cored_tl_h_o,
-	cored_tl_h_i,
-	irq_software_i,
-	irq_timer_i,
-	irq_external_i,
-	esc_tx_i,
-	esc_rx_o,
-	nmi_wdog_i,
-	debug_req_i,
-	crash_dump_o,
-	lc_cpu_en_i,
-	pwrmgr_cpu_en_i,
-	pwrmgr_o,
-	scan_rst_ni,
-	scanmode_i,
-	cfg_tl_d_i,
-	cfg_tl_d_o,
-	edn_o,
-	edn_i,
-	clk_otp_i,
-	rst_otp_ni,
-	icache_otp_key_o,
-	icache_otp_key_i,
-	fpga_info_i,
-	alert_rx_i,
-	alert_tx_o
-);
-	localparam signed [31:0] rv_core_ibex_reg_pkg_NumAlerts = 4;
-	parameter [3:0] AlertAsyncOn = {rv_core_ibex_reg_pkg_NumAlerts {1'b1}};
-	parameter [0:0] PMPEnable = 1'b1;
-	parameter [31:0] PMPGranularity = 0;
-	parameter [31:0] PMPNumRegions = 16;
-	parameter [31:0] MHPMCounterNum = 10;
-	parameter [31:0] MHPMCounterWidth = 32;
-	parameter [0:0] RV32E = 0;
-	parameter integer RV32M = 32'sd3;
-	parameter integer RV32B = 32'sd2;
-	parameter integer RegFile = 32'sd0;
-	parameter [0:0] BranchTargetALU = 1'b1;
-	parameter [0:0] WritebackStage = 1'b1;
-	parameter [0:0] ICache = 1'b1;
-	parameter [0:0] ICacheECC = 1'b1;
-	parameter [0:0] ICacheScramble = 1'b1;
-	parameter [0:0] BranchPredictor = 1'b0;
-	parameter [0:0] DbgTriggerEn = 1'b1;
-	parameter [31:0] DbgHwBreakNum = 4;
-	parameter [0:0] SecureIbex = 1'b1;
-	localparam signed [31:0] ibex_pkg_LfsrWidth = 32;
-	localparam [31:0] ibex_pkg_RndCnstLfsrSeedDefault = 32'hac533bf4;
-	parameter [31:0] RndCnstLfsrSeed = ibex_pkg_RndCnstLfsrSeedDefault;
-	localparam [159:0] ibex_pkg_RndCnstLfsrPermDefault = 160'h1e35ecba467fd1b12e958152c04fa43878a8daed;
-	parameter [159:0] RndCnstLfsrPerm = ibex_pkg_RndCnstLfsrPermDefault;
-	parameter [31:0] DmHaltAddr = 32'h1a110800;
-	parameter [31:0] DmExceptionAddr = 32'h1a110808;
-	parameter [0:0] PipeLine = 1'b0;
-	localparam [31:0] ibex_pkg_SCRAMBLE_KEY_W = 128;
-	localparam [127:0] ibex_pkg_RndCnstIbexKeyDefault = 128'h14e8cecae3040d5e12286bb3cc113298;
-	parameter [127:0] RndCnstIbexKeyDefault = ibex_pkg_RndCnstIbexKeyDefault;
-	localparam [31:0] ibex_pkg_SCRAMBLE_NONCE_W = 64;
-	localparam [63:0] ibex_pkg_RndCnstIbexNonceDefault = 64'hf79780bc735f3843;
-	parameter [63:0] RndCnstIbexNonceDefault = ibex_pkg_RndCnstIbexNonceDefault;
-	input wire clk_i;
-	input wire rst_ni;
-	input wire clk_edn_i;
-	input wire rst_edn_ni;
-	input wire clk_esc_i;
-	input wire rst_esc_ni;
-	output wire rst_cpu_n_o;
-	input wire [9:0] ram_cfg_i;
-	input wire [31:0] hart_id_i;
-	input wire [31:0] boot_addr_i;
-	localparam signed [31:0] prim_mubi_pkg_MuBi4Width = 4;
-	localparam signed [31:0] tlul_pkg_DataIntgWidth = 7;
-	localparam signed [31:0] tlul_pkg_H2DCmdIntgWidth = 7;
-	localparam signed [31:0] top_pkg_TL_AIW = 8;
-	localparam signed [31:0] top_pkg_TL_AW = 32;
-	localparam signed [31:0] top_pkg_TL_DW = 32;
-	localparam signed [31:0] top_pkg_TL_DBW = top_pkg_TL_DW >> 3;
-	localparam signed [31:0] top_pkg_TL_SZW = $clog2($clog2(top_pkg_TL_DBW) + 1);
-	output wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 23:0] corei_tl_h_o;
-	localparam signed [31:0] tlul_pkg_D2HRspIntgWidth = 7;
-	localparam signed [31:0] top_pkg_TL_DIW = 1;
-	input wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + (tlul_pkg_D2HRspIntgWidth + tlul_pkg_DataIntgWidth)) + 1:0] corei_tl_h_i;
-	output wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 23:0] cored_tl_h_o;
-	input wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + (tlul_pkg_D2HRspIntgWidth + tlul_pkg_DataIntgWidth)) + 1:0] cored_tl_h_i;
-	input wire irq_software_i;
-	input wire irq_timer_i;
-	input wire irq_external_i;
-	input wire [1:0] esc_tx_i;
-	output wire [1:0] esc_rx_o;
-	input wire nmi_wdog_i;
-	input wire debug_req_i;
-	output wire [224:0] crash_dump_o;
-	localparam signed [31:0] lc_ctrl_pkg_TxWidth = 4;
-	input wire [3:0] lc_cpu_en_i;
-	input wire [3:0] pwrmgr_cpu_en_i;
-	output wire [0:0] pwrmgr_o;
-	input scan_rst_ni;
-	input wire [3:0] scanmode_i;
-	input wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 23:0] cfg_tl_d_i;
-	output wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + (tlul_pkg_D2HRspIntgWidth + tlul_pkg_DataIntgWidth)) + 1:0] cfg_tl_d_o;
-	output wire [0:0] edn_o;
-	localparam [31:0] edn_pkg_ENDPOINT_BUS_WIDTH = 32;
-	input wire [33:0] edn_i;
-	input clk_otp_i;
-	input rst_otp_ni;
-	output wire [0:0] icache_otp_key_o;
-	localparam signed [31:0] otp_ctrl_pkg_SramKeyWidth = 128;
-	localparam signed [31:0] otp_ctrl_pkg_SramNonceWidth = 128;
-	input wire [257:0] icache_otp_key_i;
-	input [31:0] fpga_info_i;
-	input wire [15:0] alert_rx_i;
-	output wire [7:0] alert_tx_o;
-	wire [312:0] reg2hw;
-	wire [82:0] hw2reg;
-	localparam [0:0] FifoPass = (PipeLine ? 1'b0 : 1'b1);
-	localparam [31:0] FifoDepth = (PipeLine ? 2 : 0);
-	localparam signed [31:0] NumOutstandingReqs = (ICache ? 8 : 2);
-	wire instr_req;
-	wire instr_gnt;
-	wire instr_rvalid;
-	wire [31:0] instr_addr;
-	wire [31:0] instr_rdata;
-	wire [6:0] instr_rdata_intg;
-	wire instr_err;
-	wire data_req;
-	wire data_gnt;
-	wire data_rvalid;
-	wire data_we;
-	wire [3:0] data_be;
-	wire [31:0] data_addr;
-	wire [31:0] data_wdata;
-	wire [6:0] data_wdata_intg;
-	wire [31:0] data_rdata;
-	wire [6:0] data_rdata_intg;
-	wire data_err;
-	wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 23:0] tl_i_ibex2fifo;
-	wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + (tlul_pkg_D2HRspIntgWidth + tlul_pkg_DataIntgWidth)) + 1:0] tl_i_fifo2ibex;
-	wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 23:0] tl_d_ibex2fifo;
-	wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + (tlul_pkg_D2HRspIntgWidth + tlul_pkg_DataIntgWidth)) + 1:0] tl_d_fifo2ibex;
-	wire core_sleep;
-	wire ibex_top_clk_i;
-	wire addr_trans_rst_ni;
-	assign ibex_top_clk_i = clk_i;
-	assign addr_trans_rst_ni = rst_ni;
-	wire ibus_intg_err;
-	wire dbus_intg_err;
-	wire alert_minor;
-	wire alert_major_internal;
-	wire alert_major_bus;
-	wire double_fault;
-	wire fatal_intg_err;
-	wire fatal_core_err;
-	wire recov_core_err;
-	wire fatal_intg_event;
-	wire fatal_core_event;
-	wire recov_core_event;
-	assign fatal_intg_event = (ibus_intg_err | dbus_intg_err) | alert_major_bus;
-	assign fatal_core_event = alert_major_internal | double_fault;
-	assign recov_core_event = alert_minor;
-	localparam signed [31:0] rv_core_ibex_reg_pkg_NumRegions = 2;
-	wire [129:0] ibus_region_cfg;
-	wire [129:0] dbus_region_cfg;
-	assign rst_cpu_n_o = rst_ni;
-	wire esc_irq_nm;
-	localparam signed [31:0] alert_handler_reg_pkg_N_ESC_SEV = 4;
-	localparam signed [31:0] alert_handler_reg_pkg_PING_CNT_DW = 16;
-	prim_esc_receiver #(
-		.N_ESC_SEV(alert_handler_reg_pkg_N_ESC_SEV),
-		.PING_CNT_DW(alert_handler_reg_pkg_PING_CNT_DW)
-	) u_prim_esc_receiver(
-		.clk_i(clk_esc_i),
-		.rst_ni(rst_esc_ni),
-		.esc_req_o(esc_irq_nm),
-		.esc_rx_o(esc_rx_o),
-		.esc_tx_i(esc_tx_i)
-	);
-	wire alert_irq_nm;
-	prim_flop_2sync #(.Width(1)) u_alert_nmi_sync(
-		.clk_i(clk_i),
-		.rst_ni(rst_ni),
-		.d_i(esc_irq_nm),
-		.q_o(alert_irq_nm)
-	);
-	wire wdog_irq_nm;
-	prim_flop_2sync #(.Width(1)) u_wdog_nmi_sync(
-		.clk_i(clk_i),
-		.rst_ni(rst_ni),
-		.d_i(nmi_wdog_i),
-		.q_o(wdog_irq_nm)
-	);
-	assign hw2reg[77] = 1'b1;
-	assign hw2reg[76] = alert_irq_nm;
-	assign hw2reg[75] = 1'b1;
-	assign hw2reg[74] = wdog_irq_nm;
-	wire irq_nm;
-	assign irq_nm = |(reg2hw[34-:2] & reg2hw[36-:2]);
-	wire [3:0] lc_cpu_en;
-	prim_lc_sync u_lc_sync(
-		.clk_i(clk_i),
-		.rst_ni(rst_ni),
-		.lc_en_i(lc_cpu_en_i),
-		.lc_en_o(lc_cpu_en)
-	);
-	wire [3:0] pwrmgr_cpu_en;
-	prim_lc_sync u_pwrmgr_sync(
-		.clk_i(clk_i),
-		.rst_ni(rst_ni),
-		.lc_en_i(pwrmgr_cpu_en_i),
-		.lc_en_o(pwrmgr_cpu_en)
-	);
-	wire irq_timer_sync;
-	prim_flop_2sync #(.Width(1)) u_intr_timer_sync(
-		.clk_i(clk_i),
-		.rst_ni(rst_ni),
-		.d_i(irq_timer_i),
-		.q_o(irq_timer_sync)
-	);
-	wire irq_software;
-	wire irq_timer;
-	wire irq_external;
-	prim_sec_anchor_buf #(.Width(3)) u_prim_buf_irq(
-		.in_i({irq_software_i, irq_timer_sync, irq_external_i}),
-		.out_o({irq_software, irq_timer, irq_external})
-	);
-	wire key_req;
-	wire key_ack;
-	wire [127:0] key;
-	wire [63:0] nonce;
-	wire unused_seed_valid;
-	localparam signed [31:0] PayLoadW = (ibex_pkg_SCRAMBLE_KEY_W + ibex_pkg_SCRAMBLE_NONCE_W) + 1;
-	prim_sync_reqack_data #(
-		.Width(PayLoadW),
-		.DataSrc2Dst(1'b0)
-	) u_prim_sync_reqack_data(
-		.clk_src_i(clk_i),
-		.rst_src_ni(rst_ni),
-		.clk_dst_i(clk_otp_i),
-		.rst_dst_ni(rst_otp_ni),
-		.req_chk_i(1'b1),
-		.src_req_i(key_req),
-		.src_ack_o(key_ack),
-		.dst_req_o(icache_otp_key_o[0]),
-		.dst_ack_i(icache_otp_key_i[257]),
-		.data_i({icache_otp_key_i[256-:128], icache_otp_key_i[64:1], icache_otp_key_i[0]}),
-		.data_o({key, nonce, unused_seed_valid})
-	);
-	wire unused_nonce;
-	assign unused_nonce = |icache_otp_key_i[128-:128];
-	wire [3:0] local_fetch_enable_d;
-	wire [3:0] local_fetch_enable_q;
-	function automatic [3:0] sv2v_cast_A1913;
-		input reg [3:0] inp;
-		sv2v_cast_A1913 = inp;
-	endfunction
-	assign local_fetch_enable_d = (fatal_core_err ? sv2v_cast_A1913(4'b1010) : local_fetch_enable_q);
-	prim_lc_sender #(
-		.AsyncOn(1),
-		.ResetValueIsOn(1)
-	) u_prim_lc_sender(
-		.clk_i(clk_i),
-		.rst_ni(rst_ni),
-		.lc_en_i(local_fetch_enable_d),
-		.lc_en_o(local_fetch_enable_q)
-	);
-	wire [3:0] fetch_enable;
-	function automatic [3:0] lc_ctrl_pkg_lc_tx_and;
-		input reg [3:0] a;
-		input reg [3:0] b;
-		input reg [3:0] act;
-		reg [3:0] a_in;
-		reg [3:0] b_in;
-		reg [3:0] act_in;
-		reg [3:0] out;
-		begin
-			a_in = a;
-			b_in = b;
-			act_in = act;
-			begin : sv2v_autoblock_1
-				reg signed [31:0] k;
-				for (k = 0; k < lc_ctrl_pkg_TxWidth; k = k + 1)
-					if (act_in[k])
-						out[k] = a_in[k] && b_in[k];
-					else
-						out[k] = a_in[k] || b_in[k];
-			end
-			lc_ctrl_pkg_lc_tx_and = out;
-		end
-	endfunction
-	function automatic [3:0] lc_ctrl_pkg_lc_tx_and_hi;
-		input reg [3:0] a;
-		input reg [3:0] b;
-		lc_ctrl_pkg_lc_tx_and_hi = lc_ctrl_pkg_lc_tx_and(a, b, sv2v_cast_A1913(4'b0101));
-	endfunction
-	assign fetch_enable = lc_ctrl_pkg_lc_tx_and_hi(local_fetch_enable_q, lc_ctrl_pkg_lc_tx_and_hi(lc_cpu_en[0+:lc_ctrl_pkg_TxWidth], pwrmgr_cpu_en[0+:lc_ctrl_pkg_TxWidth]));
-	wire [159:0] crash_dump;
-	function automatic [3:0] sv2v_cast_38B98;
-		input reg [3:0] inp;
-		sv2v_cast_38B98 = inp;
-	endfunction
-	function automatic prim_mubi_pkg_mubi4_test_true_strict;
-		input reg [3:0] val;
-		prim_mubi_pkg_mubi4_test_true_strict = sv2v_cast_38B98(4'h6) == val;
-	endfunction
-	ibex_top #(
-		.PMPEnable(PMPEnable),
-		.PMPGranularity(PMPGranularity),
-		.PMPNumRegions(PMPNumRegions),
-		.MHPMCounterNum(MHPMCounterNum),
-		.MHPMCounterWidth(MHPMCounterWidth),
-		.RV32E(RV32E),
-		.RV32M(RV32M),
-		.RV32B(RV32B),
-		.RegFile(RegFile),
-		.BranchTargetALU(BranchTargetALU),
-		.WritebackStage(WritebackStage),
-		.ICache(ICache),
-		.ICacheECC(ICacheECC),
-		.ICacheScramble(ICacheScramble),
-		.BranchPredictor(BranchPredictor),
-		.DbgTriggerEn(DbgTriggerEn),
-		.DbgHwBreakNum(DbgHwBreakNum),
-		.SecureIbex(SecureIbex),
-		.RndCnstLfsrSeed(RndCnstLfsrSeed),
-		.RndCnstLfsrPerm(RndCnstLfsrPerm),
-		.RndCnstIbexKey(RndCnstIbexKeyDefault),
-		.RndCnstIbexNonce(RndCnstIbexNonceDefault),
-		.DmHaltAddr(DmHaltAddr),
-		.DmExceptionAddr(DmExceptionAddr)
-	) u_core(
-		.clk_i(ibex_top_clk_i),
-		.rst_ni(rst_ni),
-		.test_en_i(prim_mubi_pkg_mubi4_test_true_strict(scanmode_i)),
-		.scan_rst_ni(scan_rst_ni),
-		.ram_cfg_i(ram_cfg_i),
-		.hart_id_i(hart_id_i),
-		.boot_addr_i(boot_addr_i),
-		.instr_req_o(instr_req),
-		.instr_gnt_i(instr_gnt),
-		.instr_rvalid_i(instr_rvalid),
-		.instr_addr_o(instr_addr),
-		.instr_rdata_i(instr_rdata),
-		.instr_rdata_intg_i(instr_rdata_intg),
-		.instr_err_i(instr_err),
-		.data_req_o(data_req),
-		.data_gnt_i(data_gnt),
-		.data_rvalid_i(data_rvalid),
-		.data_we_o(data_we),
-		.data_be_o(data_be),
-		.data_addr_o(data_addr),
-		.data_wdata_o(data_wdata),
-		.data_wdata_intg_o(data_wdata_intg),
-		.data_rdata_i(data_rdata),
-		.data_rdata_intg_i(data_rdata_intg),
-		.data_err_i(data_err),
-		.irq_software_i(irq_software),
-		.irq_timer_i(irq_timer),
-		.irq_external_i(irq_external),
-		.irq_fast_i(1'sb0),
-		.irq_nm_i(irq_nm),
-		.debug_req_i(debug_req_i),
-		.crash_dump_o(crash_dump),
-		.scramble_key_valid_i(key_ack),
-		.scramble_key_i(key),
-		.scramble_nonce_i(nonce),
-		.scramble_req_o(key_req),
-		.double_fault_seen_o(double_fault),
-		.fetch_enable_i(fetch_enable),
-		.alert_minor_o(alert_minor),
-		.alert_major_internal_o(alert_major_internal),
-		.alert_major_bus_o(alert_major_bus),
-		.core_sleep_o(core_sleep)
-	);
-	reg core_sleep_q;
-	always @(posedge clk_i or negedge rst_ni)
-		if (!rst_ni)
-			core_sleep_q <= 1'sb0;
-		else
-			core_sleep_q <= core_sleep;
-	prim_buf #(.Width(1)) u_core_sleeping_buf(
-		.in_i(core_sleep_q),
-		.out_o(pwrmgr_o[0])
-	);
-	reg prev_valid;
-	reg [31:0] prev_exception_pc;
-	reg [31:0] prev_exception_addr;
-	assign crash_dump_o[159-:160] = crash_dump;
-	assign crash_dump_o[224] = prev_valid;
-	assign crash_dump_o[223-:32] = prev_exception_pc;
-	assign crash_dump_o[191-:32] = prev_exception_addr;
-	always @(posedge clk_i or negedge rst_ni)
-		if (!rst_ni) begin
-			prev_valid <= 1'sb0;
-			prev_exception_pc <= 1'sb0;
-			prev_exception_addr <= 1'sb0;
-		end
-		else if (double_fault) begin
-			prev_valid <= 1'b1;
-			prev_exception_pc <= crash_dump[63-:32];
-			prev_exception_addr <= crash_dump[31-:32];
-		end
-	wire [31:0] instr_addr_trans;
-	rv_core_addr_trans #(
-		.AddrWidth(32),
-		.NumRegions(rv_core_ibex_reg_pkg_NumRegions)
-	) u_ibus_trans(
-		.clk_i(clk_i),
-		.rst_ni(addr_trans_rst_ni),
-		.region_cfg_i(ibus_region_cfg),
-		.addr_i(instr_addr),
-		.addr_o(instr_addr_trans)
-	);
-	assign instr_err = 0;
-	wire [6:0] instr_wdata_intg;
-	wire [31:0] unused_data;
-	function automatic [38:0] sv2v_cast_39;
-		input reg [38:0] inp;
-		sv2v_cast_39 = inp;
-	endfunction
-	function automatic [38:0] prim_secded_pkg_prim_secded_inv_39_32_enc;
-		input reg [31:0] data_i;
-		reg [38:0] data_o;
-		begin
-			data_o = sv2v_cast_39(data_i);
-			data_o[32] = ^(data_o & 39'h002606bd25);
-			data_o[33] = ^(data_o & 39'h00deba8050);
-			data_o[34] = ^(data_o & 39'h00413d89aa);
-			data_o[35] = ^(data_o & 39'h0031234ed1);
-			data_o[36] = ^(data_o & 39'h00c2c1323b);
-			data_o[37] = ^(data_o & 39'h002dcc624c);
-			data_o[38] = ^(data_o & 39'h0098505586);
-			data_o = data_o ^ 39'h2a00000000;
-			prim_secded_pkg_prim_secded_inv_39_32_enc = data_o;
-		end
-	endfunction
-	assign {instr_wdata_intg, unused_data} = prim_secded_pkg_prim_secded_inv_39_32_enc(instr_rdata);
-	tlul_adapter_host #(
-		.MAX_REQS(NumOutstandingReqs),
-		.EnableDataIntgGen(~SecureIbex)
-	) tl_adapter_host_i_ibex(
-		.clk_i(clk_i),
-		.rst_ni(rst_ni),
-		.req_i(instr_req),
-		.instr_type_i(sv2v_cast_38B98(4'h6)),
-		.gnt_o(instr_gnt),
-		.addr_i(instr_addr_trans),
-		.we_i(1'b0),
-		.wdata_i(32'b00000000000000000000000000000000),
-		.wdata_intg_i(instr_wdata_intg),
-		.be_i(4'hf),
-		.valid_o(instr_rvalid),
-		.rdata_o(instr_rdata),
-		.rdata_intg_o(instr_rdata_intg),
-		.intg_err_o(ibus_intg_err),
-		.tl_o(tl_i_ibex2fifo),
-		.tl_i(tl_i_fifo2ibex)
-	);
-	tlul_fifo_sync #(
-		.ReqPass(FifoPass),
-		.RspPass(FifoPass),
-		.ReqDepth(FifoDepth),
-		.RspDepth(FifoDepth)
-	) fifo_i(
-		.clk_i(clk_i),
-		.rst_ni(rst_ni),
-		.tl_h_i(tl_i_ibex2fifo),
-		.tl_h_o(tl_i_fifo2ibex),
-		.tl_d_o(corei_tl_h_o),
-		.tl_d_i(corei_tl_h_i),
-		.spare_req_i(1'b0),
-		.spare_rsp_i(1'b0)
-	);
-	wire [31:0] data_addr_trans;
-	rv_core_addr_trans #(
-		.AddrWidth(32),
-		.NumRegions(rv_core_ibex_reg_pkg_NumRegions)
-	) u_dbus_trans(
-		.clk_i(clk_i),
-		.rst_ni(addr_trans_rst_ni),
-		.region_cfg_i(dbus_region_cfg),
-		.addr_i(data_addr),
-		.addr_o(data_addr_trans)
-	);
-	assign data_err = 0;
-	tlul_adapter_host #(
-		.MAX_REQS(2),
-		.EnableDataIntgGen(~SecureIbex)
-	) tl_adapter_host_d_ibex(
-		.clk_i(clk_i),
-		.rst_ni(rst_ni),
-		.req_i(data_req),
-		.instr_type_i(sv2v_cast_38B98(4'h9)),
-		.gnt_o(data_gnt),
-		.addr_i(data_addr_trans),
-		.we_i(data_we),
-		.wdata_i(data_wdata),
-		.wdata_intg_i(data_wdata_intg),
-		.be_i(data_be),
-		.valid_o(data_rvalid),
-		.rdata_o(data_rdata),
-		.rdata_intg_o(data_rdata_intg),
-		.intg_err_o(dbus_intg_err),
-		.tl_o(tl_d_ibex2fifo),
-		.tl_i(tl_d_fifo2ibex)
-	);
-	tlul_fifo_sync #(
-		.ReqPass(FifoPass),
-		.RspPass(FifoPass),
-		.ReqDepth(FifoDepth),
-		.RspDepth(FifoDepth)
-	) fifo_d(
-		.clk_i(clk_i),
-		.rst_ni(rst_ni),
-		.tl_h_i(tl_d_ibex2fifo),
-		.tl_h_o(tl_d_fifo2ibex),
-		.tl_d_o(cored_tl_h_o),
-		.tl_d_i(cored_tl_h_i),
-		.spare_req_i(1'b0),
-		.spare_rsp_i(1'b0)
-	);
-	wire intg_err;
-	wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 23:0] tl_win_h2d;
-	wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + (tlul_pkg_D2HRspIntgWidth + tlul_pkg_DataIntgWidth)) + 1:0] tl_win_d2h;
-	rv_core_ibex_cfg_reg_top u_reg_cfg(
-		.clk_i(clk_i),
-		.rst_ni(rst_ni),
-		.tl_i(cfg_tl_d_i),
-		.tl_o(cfg_tl_d_o),
-		.reg2hw(reg2hw),
-		.hw2reg(hw2reg),
-		.intg_err_o(intg_err),
-		.tl_win_o(tl_win_h2d),
-		.tl_win_i(tl_win_d2h),
-		.devmode_i(1'b1)
-	);
-	genvar i;
-	generate
-		for (i = 0; i < rv_core_ibex_reg_pkg_NumRegions; i = i + 1) begin : gen_ibus_region_cfgs
-			assign ibus_region_cfg[(i * 65) + 64] = reg2hw[295 + i+:1];
-			assign ibus_region_cfg[(i * 65) + 63-:32] = reg2hw[231 + (i * 32)+:32];
-			assign ibus_region_cfg[(i * 65) + 31-:32] = reg2hw[167 + (i * 32)+:32];
-		end
-		for (i = 0; i < rv_core_ibex_reg_pkg_NumRegions; i = i + 1) begin : gen_dbus_region_cfgs
-			assign dbus_region_cfg[(i * 65) + 64] = reg2hw[165 + i+:1];
-			assign dbus_region_cfg[(i * 65) + 63-:32] = reg2hw[101 + (i * 32)+:32];
-			assign dbus_region_cfg[(i * 65) + 31-:32] = reg2hw[37 + (i * 32)+:32];
-		end
-	endgenerate
-	assign fatal_intg_err = fatal_intg_event;
-	assign fatal_core_err = fatal_core_event;
-	assign recov_core_err = recov_core_event;
-	assign hw2reg[73] = 1'b1;
-	assign hw2reg[72] = intg_err;
-	assign hw2reg[71] = 1'b1;
-	assign hw2reg[70] = fatal_intg_err;
-	assign hw2reg[69] = 1'b1;
-	assign hw2reg[68] = fatal_core_err;
-	assign hw2reg[67] = 1'b1;
-	assign hw2reg[66] = recov_core_err;
-	wire [3:0] alert_test;
-	assign alert_test[0] = reg2hw[312] & reg2hw[311];
-	assign alert_test[1] = reg2hw[310] & reg2hw[309];
-	assign alert_test[2] = reg2hw[308] & reg2hw[307];
-	assign alert_test[3] = reg2hw[306] & reg2hw[305];
-	localparam [3:0] AlertFatal = 4'b0101;
-	wire [3:0] alert_events;
-	wire [3:0] alert_acks;
-	function automatic prim_mubi_pkg_mubi4_test_true_loose;
-		input reg [3:0] val;
-		prim_mubi_pkg_mubi4_test_true_loose = sv2v_cast_38B98(4'h9) != val;
-	endfunction
-	assign alert_events[0] = prim_mubi_pkg_mubi4_test_true_loose(sv2v_cast_38B98(reg2hw[300-:4]));
-	assign alert_events[1] = prim_mubi_pkg_mubi4_test_true_loose(sv2v_cast_38B98(reg2hw[304-:4]));
-	assign alert_events[2] = (intg_err | fatal_intg_err) | fatal_core_err;
-	assign alert_events[3] = recov_core_err;
-	wire unused_alert_acks;
-	assign unused_alert_acks = |alert_acks;
-	assign hw2reg[78] = alert_acks[1];
-	assign hw2reg[82-:4] = sv2v_cast_38B98(4'h9);
-	generate
-		for (i = 0; i < rv_core_ibex_reg_pkg_NumAlerts; i = i + 1) begin : gen_alert_senders
-			prim_alert_sender #(
-				.AsyncOn(AlertAsyncOn[0]),
-				.IsFatal(AlertFatal[i])
-			) u_alert_sender(
-				.clk_i(clk_i),
-				.rst_ni(rst_ni),
-				.alert_test_i(alert_test[i]),
-				.alert_req_i(alert_events[i]),
-				.alert_ack_o(alert_acks[i]),
-				.alert_rx_i(alert_rx_i[i * 4+:4]),
-				.alert_tx_o(alert_tx_o[i * 2+:2])
-			);
-		end
-	endgenerate
-	reg [31:0] rnd_data_q;
-	reg [31:0] rnd_data_d;
-	reg rnd_valid_q;
-	reg rnd_valid_d;
-	reg rnd_fips_q;
-	reg rnd_fips_d;
-	wire edn_req;
-	wire [31:0] edn_data;
-	wire edn_ack;
-	wire edn_fips;
-	always @(*) begin
-		rnd_valid_d = rnd_valid_q;
-		rnd_data_d = rnd_data_q;
-		rnd_fips_d = rnd_fips_q;
-		if (reg2hw[0]) begin
-			rnd_valid_d = 1'sb0;
-			rnd_data_d = 1'sb0;
-			rnd_fips_d = 1'sb0;
-		end
-		else if (edn_req && edn_ack) begin
-			rnd_valid_d = 1'b1;
-			rnd_data_d = edn_data;
-			rnd_fips_d = edn_fips;
-		end
-	end
-	always @(posedge clk_i or negedge rst_ni)
-		if (!rst_ni) begin
-			rnd_valid_q <= 1'sb0;
-			rnd_data_q <= 1'sb0;
-			rnd_fips_q <= 1'sb0;
-		end
-		else begin
-			rnd_valid_q <= rnd_valid_d;
-			rnd_data_q <= rnd_data_d;
-			rnd_fips_q <= rnd_fips_d;
-		end
-	assign edn_req = ~rnd_valid_q;
-	prim_edn_req #(.OutWidth(32)) u_edn_if(
-		.clk_i(clk_i),
-		.rst_ni(rst_ni),
-		.req_chk_i(1'b1),
-		.req_i(edn_req),
-		.ack_o(edn_ack),
-		.data_o(edn_data),
-		.fips_o(edn_fips),
-		.clk_edn_i(clk_edn_i),
-		.rst_edn_ni(rst_edn_ni),
-		.edn_o(edn_o),
-		.edn_i(edn_i)
-	);
-	assign hw2reg[65-:32] = rnd_data_q;
-	assign hw2reg[33] = rnd_valid_q;
-	assign hw2reg[32] = rnd_fips_q;
-	wire unused_reg2hw;
-	assign unused_reg2hw = |reg2hw[32-:32];
-	assign hw2reg[31-:32] = fpga_info_i;
-	localparam signed [31:0] TlH2DWidth = 1 * ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 24);
-	localparam signed [31:0] TlD2HWidth = 1 * ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + (tlul_pkg_D2HRspIntgWidth + tlul_pkg_DataIntgWidth)) + 2);
-	wire [TlH2DWidth - 1:0] tl_win_h2d_int;
-	wire [TlD2HWidth - 1:0] tl_win_d2h_int;
-	wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + (tlul_pkg_D2HRspIntgWidth + tlul_pkg_DataIntgWidth)) + 1:0] tl_win_d2h_err_rsp;
-	prim_buf #(.Width(TlH2DWidth)) u_tlul_req_buf(
-		.in_i(tl_win_h2d),
-		.out_o(tl_win_h2d_int)
-	);
-	prim_buf #(.Width(TlD2HWidth)) u_tlul_rsp_buf(
-		.in_i(tl_win_d2h_err_rsp),
-		.out_o(tl_win_d2h_int)
-	);
-	function automatic [((((((7 + top_pkg_TL_SZW) + (32'sd8 + 32'sd1)) + 32'sd32) + (32'sd7 + 32'sd7)) + 1) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + (tlul_pkg_D2HRspIntgWidth + tlul_pkg_DataIntgWidth)) + 2 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + (tlul_pkg_D2HRspIntgWidth + tlul_pkg_DataIntgWidth)) + 1)) - 1:0] sv2v_cast_51793;
-		input reg [((((((7 + top_pkg_TL_SZW) + (32'sd8 + 32'sd1)) + 32'sd32) + (32'sd7 + 32'sd7)) + 1) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + (tlul_pkg_D2HRspIntgWidth + tlul_pkg_DataIntgWidth)) + 2 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + (tlul_pkg_D2HRspIntgWidth + tlul_pkg_DataIntgWidth)) + 1)) - 1:0] inp;
-		sv2v_cast_51793 = inp;
-	endfunction
-	assign tl_win_d2h = sv2v_cast_51793(tl_win_d2h_int);
-	wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 23:0] tl_win_h2d_int_tmp;
-	function automatic [(((((7 + top_pkg_TL_SZW) + (32'sd8 + 32'sd32)) + top_pkg_TL_DBW) + 55) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 24 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 23)) - 1:0] sv2v_cast_E9713;
-		input reg [(((((7 + top_pkg_TL_SZW) + (32'sd8 + 32'sd32)) + top_pkg_TL_DBW) + 55) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 24 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 23)) - 1:0] inp;
-		sv2v_cast_E9713 = inp;
-	endfunction
-	assign tl_win_h2d_int_tmp = sv2v_cast_E9713(tl_win_h2d_int);
-	tlul_err_resp u_sim_win_rsp(
-		.clk_i(clk_i),
-		.rst_ni(rst_ni),
-		.tl_h_i(tl_win_h2d_int_tmp),
-		.tl_h_o(tl_win_d2h_err_rsp)
-	);
-endmodule
-module noerr_tlul_adapter_sram (
-	clk_i,
-	rst_ni,
-	tl_i,
-	tl_o,
-	en_ifetch_i,
-	req_o,
-	req_type_o,
-	gnt_i,
-	we_o,
-	addr_o,
-	wdata_o,
-	wmask_o,
-	intg_error_o,
-	rdata_i,
-	rvalid_i,
-	rerror_i
-);
-	parameter signed [31:0] SramAw = 12;
-	parameter signed [31:0] SramDw = 32;
-	parameter signed [31:0] Outstanding = 1;
-	parameter [0:0] ByteAccess = 1;
-	parameter [0:0] ErrOnWrite = 0;
-	parameter [0:0] ErrOnRead = 0;
-	parameter [0:0] CmdIntgCheck = 0;
-	parameter [0:0] EnableRspIntgGen = 0;
-	parameter [0:0] EnableDataIntgGen = 0;
-	parameter [0:0] EnableDataIntgPt = 0;
-	parameter [0:0] SecFifoPtr = 0;
-	localparam signed [31:0] top_pkg_TL_DW = 32;
-	localparam signed [31:0] WidthMult = SramDw / top_pkg_TL_DW;
-	localparam signed [31:0] tlul_pkg_DataIntgWidth = 7;
-	localparam signed [31:0] IntgWidth = tlul_pkg_DataIntgWidth * WidthMult;
-	localparam signed [31:0] DataOutW = (EnableDataIntgPt ? SramDw + IntgWidth : SramDw);
-	input clk_i;
-	input rst_ni;
-	localparam signed [31:0] prim_mubi_pkg_MuBi4Width = 4;
-	localparam signed [31:0] tlul_pkg_H2DCmdIntgWidth = 7;
-	localparam signed [31:0] top_pkg_TL_AIW = 8;
-	localparam signed [31:0] top_pkg_TL_AW = 32;
-	localparam signed [31:0] top_pkg_TL_DBW = top_pkg_TL_DW >> 3;
-	localparam signed [31:0] top_pkg_TL_SZW = $clog2($clog2(top_pkg_TL_DBW) + 1);
-	input wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 23:0] tl_i;
-	localparam signed [31:0] tlul_pkg_D2HRspIntgWidth = 7;
-	localparam signed [31:0] top_pkg_TL_DIW = 1;
-	output wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + (tlul_pkg_D2HRspIntgWidth + tlul_pkg_DataIntgWidth)) + 1:0] tl_o;
-	input wire [3:0] en_ifetch_i;
-	output wire req_o;
-	output wire [3:0] req_type_o;
-	input gnt_i;
-	output wire we_o;
-	output wire [SramAw - 1:0] addr_o;
-	output wire [DataOutW - 1:0] wdata_o;
-	output wire [DataOutW - 1:0] wmask_o;
-	output wire intg_error_o;
-	input [DataOutW - 1:0] rdata_i;
-	input rvalid_i;
-	input [1:0] rerror_i;
-	localparam signed [31:0] SramByte = SramDw / 8;
-	function automatic integer prim_util_pkg_vbits;
-		input integer value;
-		prim_util_pkg_vbits = (value == 1 ? 1 : $clog2(value));
-	endfunction
-	localparam signed [31:0] DataBitWidth = prim_util_pkg_vbits(SramByte);
-	localparam signed [31:0] WoffsetWidth = (SramByte == top_pkg_TL_DBW ? 1 : DataBitWidth - prim_util_pkg_vbits(top_pkg_TL_DBW));
-	wire error_det;
-	wire error_internal;
-	wire wr_attr_error;
-	wire instr_error;
-	wire wr_vld_error;
-	wire rd_vld_error;
-	wire rsp_fifo_error;
-	wire intg_error;
-	wire tlul_error;
-	generate
-		if (CmdIntgCheck) begin : gen_cmd_intg_check
-			tlul_cmd_intg_chk u_cmd_intg_chk(
-				.tl_i(tl_i),
-				.err_o(intg_error)
-			);
-		end
-		else begin : gen_no_cmd_intg_check
-			assign intg_error = 1'sb0;
-		end
-	endgenerate
-	reg intg_error_q;
-	always @(posedge clk_i or negedge rst_ni)
-		if (!rst_ni)
-			intg_error_q <= 1'sb0;
-		else if (intg_error || rsp_fifo_error)
-			intg_error_q <= 1'b1;
-	assign intg_error_o = (intg_error | rsp_fifo_error) | intg_error_q;
-	assign wr_attr_error = ((tl_i[6 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 55)))-:((6 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 55)))) >= (3 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 56)))) ? ((6 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 55)))) - (3 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 56))))) + 1 : ((3 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 56)))) - (6 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 55))))) + 1)] == 3'h0) || (tl_i[6 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 55)))-:((6 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 55)))) >= (3 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 56)))) ? ((6 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 55)))) - (3 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 56))))) + 1 : ((3 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 56)))) - (6 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 55))))) + 1)] == 3'h1) ? (ByteAccess == 0 ? (tl_i[top_pkg_TL_DBW + 55-:((top_pkg_TL_DBW + 55) >= 56 ? top_pkg_TL_DBW : 57 - (top_pkg_TL_DBW + 55))] != {((top_pkg_TL_DBW + 55) >= 56 ? top_pkg_TL_DBW : 57 - (top_pkg_TL_DBW + 55)) * 1 {1'sb1}}) || (tl_i[top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 55)))-:((top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 55))) >= ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 56)) ? ((top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 55)))) - (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 56)))) + 1 : ((top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 56))) - (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 55))))) + 1)] != 2'h2) : 1'b0) : 1'b0);
-	function automatic [3:0] sv2v_cast_A2CB9;
-		input reg [3:0] inp;
-		sv2v_cast_A2CB9 = inp;
-	endfunction
-	function automatic prim_mubi_pkg_mubi4_test_false_loose;
-		input reg [3:0] val;
-		prim_mubi_pkg_mubi4_test_false_loose = sv2v_cast_A2CB9(4'h6) != val;
-	endfunction
-	function automatic prim_mubi_pkg_mubi4_test_invalid;
-		input reg [3:0] val;
-		prim_mubi_pkg_mubi4_test_invalid = ~(|{((sv2v_cast_A2CB9(4'h6) ^ (val ^ val)) === (val ^ (sv2v_cast_A2CB9(4'h6) ^ sv2v_cast_A2CB9(4'h6)))) & ((((val ^ val) ^ (sv2v_cast_A2CB9(4'h6) ^ sv2v_cast_A2CB9(4'h6))) === (sv2v_cast_A2CB9(4'h6) ^ sv2v_cast_A2CB9(4'h6))) | 1'bx), ((sv2v_cast_A2CB9(4'h9) ^ (val ^ val)) === (val ^ (sv2v_cast_A2CB9(4'h9) ^ sv2v_cast_A2CB9(4'h9)))) & ((((val ^ val) ^ (sv2v_cast_A2CB9(4'h9) ^ sv2v_cast_A2CB9(4'h9))) === (sv2v_cast_A2CB9(4'h9) ^ sv2v_cast_A2CB9(4'h9))) | 1'bx)});
-	endfunction
-	function automatic prim_mubi_pkg_mubi4_test_true_strict;
-		input reg [3:0] val;
-		prim_mubi_pkg_mubi4_test_true_strict = sv2v_cast_A2CB9(4'h6) == val;
-	endfunction
-	assign instr_error = prim_mubi_pkg_mubi4_test_invalid(tl_i[18-:4]) | (prim_mubi_pkg_mubi4_test_true_strict(tl_i[18-:4]) & prim_mubi_pkg_mubi4_test_false_loose(en_ifetch_i));
-	generate
-		if (ErrOnWrite == 1) begin : gen_no_writes
-			assign wr_vld_error = tl_i[6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 55))))-:((6 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 55)))) >= (3 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 56)))) ? ((6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 55))))) - (3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 56)))))) + 1 : ((3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 56))))) - (6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 55)))))) + 1)] != 3'h4;
-		end
-		else begin : gen_writes_allowed
-			assign wr_vld_error = 1'b0;
-		end
-		if (ErrOnRead == 1) begin : gen_no_reads
-			assign rd_vld_error = tl_i[6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 55))))-:((6 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 55)))) >= (3 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 56)))) ? ((6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 55))))) - (3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 56)))))) + 1 : ((3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 56))))) - (6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 55)))))) + 1)] == 3'h4;
-		end
-		else begin : gen_reads_allowed
-			assign rd_vld_error = 1'b0;
-		end
-	endgenerate
-	tlul_err u_err(
-		.clk_i(clk_i),
-		.rst_ni(rst_ni),
-		.tl_i(tl_i),
-		.err_o(tlul_error)
-	);
-	assign error_det = ((((wr_attr_error | wr_vld_error) | rd_vld_error) | instr_error) | tlul_error) | intg_error;
-	wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 23:0] tl_i_int;
-	wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + (tlul_pkg_D2HRspIntgWidth + tlul_pkg_DataIntgWidth)) + 1:0] tl_o_int;
-	wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + (tlul_pkg_D2HRspIntgWidth + tlul_pkg_DataIntgWidth)) + 1:0] tl_out;
-	wire unused_tl_i_int;
-	assign unused_tl_i_int = ^tl_i_int;
-	tlul_rsp_intg_gen #(
-		.EnableRspIntgGen(EnableRspIntgGen),
-		.EnableDataIntgGen(EnableDataIntgGen)
-	) u_rsp_gen(
-		.tl_i(tl_out),
-		.tl_o(tl_o)
-	);
-	assign error_internal = 0;
-	tlul_sram_byte #(
-		.EnableIntg((ByteAccess & EnableDataIntgPt) & !ErrOnWrite),
-		.Outstanding(Outstanding)
-	) u_sram_byte(
-		.clk_i(clk_i),
-		.rst_ni(rst_ni),
-		.tl_i(tl_i),
-		.tl_o(tl_out),
-		.tl_sram_o(tl_i_int),
-		.tl_sram_i(tl_o_int),
-		.error_i(error_det)
-	);
-	localparam signed [31:0] SramReqFifoWidth = top_pkg_TL_DBW + WoffsetWidth;
-	localparam signed [31:0] ReqFifoWidth = (7 + top_pkg_TL_SZW) + top_pkg_TL_AIW;
-	localparam signed [31:0] RspFifoWidth = (((top_pkg_TL_DW + tlul_pkg_DataIntgWidth) + 0) >= 0 ? (top_pkg_TL_DW + tlul_pkg_DataIntgWidth) + 1 : 1 - ((top_pkg_TL_DW + tlul_pkg_DataIntgWidth) + 0));
-	wire reqfifo_wvalid;
-	wire reqfifo_wready;
-	wire reqfifo_rvalid;
-	wire reqfifo_rready;
-	wire [((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) - 1:0] reqfifo_wdata;
-	wire [((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) - 1:0] reqfifo_rdata;
-	wire sramreqfifo_wvalid;
-	wire sramreqfifo_wready;
-	wire sramreqfifo_rready;
-	wire [(top_pkg_TL_DBW + WoffsetWidth) - 1:0] sramreqfifo_wdata;
-	wire [(top_pkg_TL_DBW + WoffsetWidth) - 1:0] sramreqfifo_rdata;
-	wire rspfifo_wvalid;
-	wire rspfifo_wready;
-	wire rspfifo_rvalid;
-	wire rspfifo_rready;
-	wire [(top_pkg_TL_DW + tlul_pkg_DataIntgWidth) + 0:0] rspfifo_wdata;
-	wire [(top_pkg_TL_DW + tlul_pkg_DataIntgWidth) + 0:0] rspfifo_rdata;
-	wire a_ack;
-	wire d_ack;
-	wire sram_ack;
-	assign a_ack = tl_i_int[7 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 55))))] & tl_o_int[0];
-	assign d_ack = tl_o_int[7 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + ((tlul_pkg_D2HRspIntgWidth + tlul_pkg_DataIntgWidth) + 1)))))] & tl_i_int[0];
-	assign sram_ack = req_o & gnt_i;
-	reg d_valid;
-	reg d_error;
-	always @(*) begin
-		d_valid = 1'b0;
-		if (reqfifo_rvalid) begin
-			if (reqfifo_rdata[1 + (prim_mubi_pkg_MuBi4Width + (top_pkg_TL_SZW + 7))])
-				d_valid = 1'b1;
-			else if (reqfifo_rdata[3 + (prim_mubi_pkg_MuBi4Width + (top_pkg_TL_SZW + 7))-:((7 + (top_pkg_TL_SZW + 7)) >= (5 + (top_pkg_TL_SZW + 8)) ? ((3 + (prim_mubi_pkg_MuBi4Width + (top_pkg_TL_SZW + 7))) - (1 + (prim_mubi_pkg_MuBi4Width + (top_pkg_TL_SZW + 8)))) + 1 : ((1 + (prim_mubi_pkg_MuBi4Width + (top_pkg_TL_SZW + 8))) - (3 + (prim_mubi_pkg_MuBi4Width + (top_pkg_TL_SZW + 7)))) + 1)] == 2'd1)
-				d_valid = rspfifo_rvalid;
-			else
-				d_valid = 1'b1;
-		end
-		else
-			d_valid = 1'b0;
-	end
-	always @(*) begin
-		d_error = 1'b0;
-		if (reqfifo_rvalid) begin
-			if (reqfifo_rdata[3 + (prim_mubi_pkg_MuBi4Width + (top_pkg_TL_SZW + 7))-:((7 + (top_pkg_TL_SZW + 7)) >= (5 + (top_pkg_TL_SZW + 8)) ? ((3 + (prim_mubi_pkg_MuBi4Width + (top_pkg_TL_SZW + 7))) - (1 + (prim_mubi_pkg_MuBi4Width + (top_pkg_TL_SZW + 8)))) + 1 : ((1 + (prim_mubi_pkg_MuBi4Width + (top_pkg_TL_SZW + 8))) - (3 + (prim_mubi_pkg_MuBi4Width + (top_pkg_TL_SZW + 7)))) + 1)] == 2'd1)
-				d_error = rspfifo_rdata[0] | reqfifo_rdata[1 + (prim_mubi_pkg_MuBi4Width + (top_pkg_TL_SZW + 7))];
-			else
-				d_error = reqfifo_rdata[1 + (prim_mubi_pkg_MuBi4Width + (top_pkg_TL_SZW + 7))];
-		end
-		else
-			d_error = 1'b0;
-	end
-	wire vld_rd_rsp;
-	assign vld_rd_rsp = ((d_valid & reqfifo_rvalid) & rspfifo_rvalid) & (reqfifo_rdata[3 + (prim_mubi_pkg_MuBi4Width + (top_pkg_TL_SZW + 7))-:((7 + (top_pkg_TL_SZW + 7)) >= (5 + (top_pkg_TL_SZW + 8)) ? ((3 + (prim_mubi_pkg_MuBi4Width + (top_pkg_TL_SZW + 7))) - (1 + (prim_mubi_pkg_MuBi4Width + (top_pkg_TL_SZW + 8)))) + 1 : ((1 + (prim_mubi_pkg_MuBi4Width + (top_pkg_TL_SZW + 8))) - (3 + (prim_mubi_pkg_MuBi4Width + (top_pkg_TL_SZW + 7)))) + 1)] == 2'd1);
-	wire [31:0] error_blanking_data;
-	localparam [31:0] tlul_pkg_DataWhenError = {top_pkg_TL_DW {1'b1}};
-	localparam [31:0] tlul_pkg_DataWhenInstrError = 1'sb0;
-	assign error_blanking_data = (prim_mubi_pkg_mubi4_test_true_strict(reqfifo_rdata[prim_mubi_pkg_MuBi4Width + (top_pkg_TL_SZW + 7)-:((prim_mubi_pkg_MuBi4Width + (top_pkg_TL_SZW + 7)) >= (top_pkg_TL_SZW + 8) ? ((prim_mubi_pkg_MuBi4Width + (top_pkg_TL_SZW + 7)) - (top_pkg_TL_SZW + 8)) + 1 : ((top_pkg_TL_SZW + 8) - (prim_mubi_pkg_MuBi4Width + (top_pkg_TL_SZW + 7))) + 1)]) ? tlul_pkg_DataWhenInstrError : tlul_pkg_DataWhenError);
-	wire [31:0] unused_instr;
-	wire [31:0] unused_data;
-	wire [6:0] error_instr_integ;
-	wire [6:0] error_data_integ;
-	localparam signed [31:0] tlul_pkg_DataMaxWidth = 32;
-	function automatic [31:0] sv2v_cast_32;
-		input reg [31:0] inp;
-		sv2v_cast_32 = inp;
-	endfunction
-	tlul_data_integ_enc u_tlul_data_integ_enc_instr(
-		.data_i(sv2v_cast_32(tlul_pkg_DataWhenInstrError)),
-		.data_intg_o({error_instr_integ, unused_instr})
-	);
-	tlul_data_integ_enc u_tlul_data_integ_enc_data(
-		.data_i(sv2v_cast_32(tlul_pkg_DataWhenError)),
-		.data_intg_o({error_data_integ, unused_data})
-	);
-	wire [6:0] error_blanking_integ;
-	assign error_blanking_integ = (prim_mubi_pkg_mubi4_test_true_strict(reqfifo_rdata[prim_mubi_pkg_MuBi4Width + (top_pkg_TL_SZW + 7)-:((prim_mubi_pkg_MuBi4Width + (top_pkg_TL_SZW + 7)) >= (top_pkg_TL_SZW + 8) ? ((prim_mubi_pkg_MuBi4Width + (top_pkg_TL_SZW + 7)) - (top_pkg_TL_SZW + 8)) + 1 : ((top_pkg_TL_SZW + 8) - (prim_mubi_pkg_MuBi4Width + (top_pkg_TL_SZW + 7))) + 1)]) ? error_instr_integ : error_data_integ);
-	wire [31:0] d_data;
-	assign d_data = (vld_rd_rsp & ~d_error ? rspfifo_rdata[39-:32] : error_blanking_data);
-	wire [6:0] data_intg;
-	localparam [6:0] prim_secded_pkg_SecdedInv3932ZeroEcc = 7'h2a;
-	assign data_intg = (vld_rd_rsp && reqfifo_rdata[5 + (top_pkg_TL_SZW + 7)] ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata[7-:7] : prim_secded_pkg_SecdedInv3932ZeroEcc));
-	function automatic [6:0] sv2v_cast_5F39A;
-		input reg [6:0] inp;
-		sv2v_cast_5F39A = inp;
-	endfunction
-	function automatic [top_pkg_TL_SZW - 1:0] sv2v_cast_4660A;
-		input reg [top_pkg_TL_SZW - 1:0] inp;
-		sv2v_cast_4660A = inp;
-	endfunction
-	function automatic [7:0] sv2v_cast_964CB;
-		input reg [7:0] inp;
-		sv2v_cast_964CB = inp;
-	endfunction
-	function automatic [0:0] sv2v_cast_702AC;
-		input reg [0:0] inp;
-		sv2v_cast_702AC = inp;
-	endfunction
-	function automatic [31:0] sv2v_cast_35AE2;
-		input reg [31:0] inp;
-		sv2v_cast_35AE2 = inp;
-	endfunction
-	function automatic [(tlul_pkg_D2HRspIntgWidth + tlul_pkg_DataIntgWidth) - 1:0] sv2v_cast_1D31F;
-		input reg [(tlul_pkg_D2HRspIntgWidth + tlul_pkg_DataIntgWidth) - 1:0] inp;
-		sv2v_cast_1D31F = inp;
-	endfunction
-	assign tl_o_int = {d_valid, (d_valid && (reqfifo_rdata[7 + (top_pkg_TL_SZW + 7)-:((7 + (top_pkg_TL_SZW + 7)) >= (5 + (top_pkg_TL_SZW + 8)) ? ((7 + (top_pkg_TL_SZW + 7)) - (5 + (top_pkg_TL_SZW + 8))) + 1 : ((5 + (top_pkg_TL_SZW + 8)) - (7 + (top_pkg_TL_SZW + 7))) + 1)] != 2'd1) ? 3'h0 : 3'h1), 3'b000, sv2v_cast_4660A((d_valid ? reqfifo_rdata[top_pkg_TL_SZW + 7-:((top_pkg_TL_SZW + 7) >= 8 ? top_pkg_TL_SZW : 9 - (top_pkg_TL_SZW + 7))] : {((top_pkg_TL_SZW + 7) >= 8 ? top_pkg_TL_SZW : 9 - (top_pkg_TL_SZW + 7)) * 1 {1'sb0}})), sv2v_cast_964CB((d_valid ? reqfifo_rdata[7-:top_pkg_TL_AIW] : {8 {1'sb0}})), sv2v_cast_702AC(1'b0), sv2v_cast_35AE2(d_data), sv2v_cast_1D31F({sv2v_cast_5F39A(1'sb0), data_intg}), d_valid && d_error, ((gnt_i | error_internal) & reqfifo_wready) & sramreqfifo_wready};
-	assign req_o = (tl_i_int[7 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 55))))] & reqfifo_wready) & ~error_internal;
-	assign req_type_o = tl_i_int[18-:4];
-	assign we_o = tl_i_int[7 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 55))))] & |{tl_i_int[6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 55))))-:((6 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 55)))) >= (3 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 56)))) ? ((6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 55))))) - (3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 56)))))) + 1 : ((3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 56))))) - (6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 55)))))) + 1)] == 3'h0, tl_i_int[6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 55))))-:((6 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 55)))) >= (3 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 56)))) ? ((6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 55))))) - (3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 56)))))) + 1 : ((3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 56))))) - (6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 55)))))) + 1)] == 3'h1};
-	assign addr_o = (tl_i_int[7 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 55)))] ? tl_i_int[(top_pkg_TL_AW + (top_pkg_TL_DBW + 55)) - (31 - DataBitWidth)+:SramAw] : {SramAw {1'sb0}});
-	wire [WoffsetWidth - 1:0] woffset;
-	generate
-		if (top_pkg_TL_DW != SramDw) begin : gen_wordwidthadapt
-			assign woffset = tl_i_int[(top_pkg_TL_AW + (top_pkg_TL_DBW + 55)) - (32 - DataBitWidth):(top_pkg_TL_AW + (top_pkg_TL_DBW + 55)) - (31 - prim_util_pkg_vbits(top_pkg_TL_DBW))];
-		end
-		else begin : gen_no_wordwidthadapt
-			assign woffset = 1'sb0;
-		end
-	endgenerate
-	localparam signed [31:0] DataWidth = (EnableDataIntgPt ? top_pkg_TL_DW + tlul_pkg_DataIntgWidth : top_pkg_TL_DW);
-	wire [(WidthMult * DataWidth) - 1:0] wmask_combined;
-	wire [(WidthMult * DataWidth) - 1:0] wdata_combined;
-	reg [(WidthMult * top_pkg_TL_DW) - 1:0] wmask_int;
-	reg [(WidthMult * top_pkg_TL_DW) - 1:0] wdata_int;
-	reg [(WidthMult * tlul_pkg_DataIntgWidth) - 1:0] wmask_intg;
-	reg [(WidthMult * tlul_pkg_DataIntgWidth) - 1:0] wdata_intg;
-	always @(*) begin
-		wmask_int = 1'sb0;
-		wdata_int = 1'sb0;
-		if (tl_i_int[7 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 55))))]) begin : sv2v_autoblock_1
-			reg signed [31:0] i;
-			for (i = 0; i < 4; i = i + 1)
-				begin
-					wmask_int[(woffset * top_pkg_TL_DW) + (8 * i)+:8] = {8 {tl_i_int[(top_pkg_TL_DBW + 55) - ((top_pkg_TL_DBW - 1) - i)]}};
-					wdata_int[(woffset * top_pkg_TL_DW) + (8 * i)+:8] = (tl_i_int[(top_pkg_TL_DBW + 55) - ((top_pkg_TL_DBW - 1) - i)] && we_o ? tl_i_int[24 + (8 * i)+:8] : {8 {1'sb0}});
-				end
-		end
-	end
-	always @(*) begin
-		wmask_intg = 1'sb0;
-		wdata_intg = 1'sb0;
-		if (tl_i_int[7 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 55))))]) begin
-			wmask_intg[woffset * tlul_pkg_DataIntgWidth+:tlul_pkg_DataIntgWidth] = {tlul_pkg_DataIntgWidth {1'b1}};
-			wdata_intg[woffset * tlul_pkg_DataIntgWidth+:tlul_pkg_DataIntgWidth] = tl_i_int[7-:tlul_pkg_DataIntgWidth];
-		end
-	end
-	genvar i;
-	generate
-		for (i = 0; i < WidthMult; i = i + 1) begin : gen_write_output
-			if (EnableDataIntgPt) begin : gen_combined_output
-				assign wmask_combined[i * DataWidth+:DataWidth] = {wmask_intg[i * tlul_pkg_DataIntgWidth+:tlul_pkg_DataIntgWidth], wmask_int[i * top_pkg_TL_DW+:top_pkg_TL_DW]};
-				assign wdata_combined[i * DataWidth+:DataWidth] = {wdata_intg[i * tlul_pkg_DataIntgWidth+:tlul_pkg_DataIntgWidth], wdata_int[i * top_pkg_TL_DW+:top_pkg_TL_DW]};
-			end
-			else begin : gen_ft_output
-				wire unused_w;
-				assign wmask_combined[i * DataWidth+:DataWidth] = wmask_int[i * top_pkg_TL_DW+:top_pkg_TL_DW];
-				assign wdata_combined[i * DataWidth+:DataWidth] = wdata_int[i * top_pkg_TL_DW+:top_pkg_TL_DW];
-				assign unused_w = |wmask_intg & |wdata_intg;
-			end
-		end
-	endgenerate
-	assign wmask_o = wmask_combined;
-	assign wdata_o = wdata_combined;
-	assign reqfifo_wvalid = a_ack;
-	assign reqfifo_wdata = {(tl_i_int[6 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 55)))-:((6 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 55)))) >= (3 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 56)))) ? ((6 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 55)))) - (3 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 56))))) + 1 : ((3 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 56)))) - (6 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 55))))) + 1)] != 3'h4 ? 2'd0 : 2'd1), error_internal, sv2v_cast_A2CB9(tl_i_int[18-:4]), tl_i_int[top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 55)))-:((top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 55))) >= ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 56)) ? ((top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 55)))) - (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 56)))) + 1 : ((top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 56))) - (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 55))))) + 1)], tl_i_int[top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 55))-:(((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 55)) >= (32'sd32 + (top_pkg_TL_DBW + 56)) ? ((top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 55))) - (top_pkg_TL_AW + (top_pkg_TL_DBW + 56))) + 1 : ((top_pkg_TL_AW + (top_pkg_TL_DBW + 56)) - (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 55)))) + 1)]};
-	assign reqfifo_rready = d_ack;
-	assign sramreqfifo_wdata = {tl_i_int[top_pkg_TL_DBW + 55-:((top_pkg_TL_DBW + 55) >= 56 ? top_pkg_TL_DBW : 57 - (top_pkg_TL_DBW + 55))], woffset};
-	assign sramreqfifo_wvalid = sram_ack & ~we_o;
-	assign sramreqfifo_rready = rspfifo_wvalid;
-	assign rspfifo_wvalid = rvalid_i & reqfifo_rvalid;
-	wire [(WidthMult * DataWidth) - 1:0] rdata_reshaped;
-	reg [DataWidth - 1:0] rdata_tlword;
-	assign rdata_reshaped = rdata_i;
-	localparam [38:0] prim_secded_pkg_SecdedInv3932ZeroWord = 39'h2a00000000;
-	generate
-		if (EnableDataIntgPt) begin : gen_no_rmask
-			always @(*) begin
-				rdata_tlword = prim_secded_pkg_SecdedInv3932ZeroWord;
-				if (|sramreqfifo_rdata[top_pkg_TL_DBW + (WoffsetWidth - 1)-:((top_pkg_TL_DBW + (WoffsetWidth - 1)) >= (WoffsetWidth + 0) ? ((top_pkg_TL_DBW + (WoffsetWidth - 1)) - (WoffsetWidth + 0)) + 1 : ((WoffsetWidth + 0) - (top_pkg_TL_DBW + (WoffsetWidth - 1))) + 1)])
-					rdata_tlword = rdata_reshaped[sramreqfifo_rdata[WoffsetWidth - 1-:WoffsetWidth] * DataWidth+:DataWidth];
-			end
-		end
-		else begin : gen_rmask
-			reg [DataWidth - 1:0] rmask;
-			always @(*) begin
-				rmask = 1'sb0;
-				begin : sv2v_autoblock_2
-					reg signed [31:0] i;
-					for (i = 0; i < 4; i = i + 1)
-						rmask[8 * i+:8] = {8 {sramreqfifo_rdata[(top_pkg_TL_DBW + (WoffsetWidth - 1)) - ((top_pkg_TL_DBW - 1) - i)]}};
-				end
-			end
-			wire [DataWidth:1] sv2v_tmp_037A0;
-			assign sv2v_tmp_037A0 = rdata_reshaped[sramreqfifo_rdata[WoffsetWidth - 1-:WoffsetWidth] * DataWidth+:DataWidth] & rmask;
-			always @(*) rdata_tlword = sv2v_tmp_037A0;
-		end
-	endgenerate
-	function automatic [6:0] sv2v_cast_8DC45;
-		input reg [6:0] inp;
-		sv2v_cast_8DC45 = inp;
-	endfunction
-	assign rspfifo_wdata = {sv2v_cast_35AE2(rdata_tlword[31:0]), sv2v_cast_8DC45((EnableDataIntgPt ? rdata_tlword[DataWidth - 1-:tlul_pkg_DataIntgWidth] : {7 {1'sb0}})), rerror_i[1]};
-	assign rspfifo_rready = ((reqfifo_rdata[7 + (top_pkg_TL_SZW + 7)-:((7 + (top_pkg_TL_SZW + 7)) >= (5 + (top_pkg_TL_SZW + 8)) ? ((7 + (top_pkg_TL_SZW + 7)) - (5 + (top_pkg_TL_SZW + 8))) + 1 : ((5 + (top_pkg_TL_SZW + 8)) - (7 + (top_pkg_TL_SZW + 7))) + 1)] == 2'd1) & ~reqfifo_rdata[5 + (top_pkg_TL_SZW + 7)] ? reqfifo_rready : 1'b0);
-	wire unused_rerror;
-	assign unused_rerror = rerror_i[0];
-	prim_fifo_sync #(
-		.Width(ReqFifoWidth),
-		.Pass(1'b0),
-		.Depth(Outstanding)
-	) u_reqfifo(
-		.clk_i(clk_i),
-		.rst_ni(rst_ni),
-		.clr_i(1'b0),
-		.wvalid_i(reqfifo_wvalid),
-		.wready_o(reqfifo_wready),
-		.wdata_i(reqfifo_wdata),
-		.rvalid_o(reqfifo_rvalid),
-		.rready_i(reqfifo_rready),
-		.rdata_o(reqfifo_rdata)
-	);
-	prim_fifo_sync #(
-		.Width(SramReqFifoWidth),
-		.Pass(1'b0),
-		.Depth(Outstanding)
-	) u_sramreqfifo(
-		.clk_i(clk_i),
-		.rst_ni(rst_ni),
-		.clr_i(1'b0),
-		.wvalid_i(sramreqfifo_wvalid),
-		.wready_o(sramreqfifo_wready),
-		.wdata_i(sramreqfifo_wdata),
-		.rready_i(sramreqfifo_rready),
-		.rdata_o(sramreqfifo_rdata)
-	);
-	prim_fifo_sync #(
-		.Width(RspFifoWidth),
-		.Pass(1'b1),
-		.Depth(Outstanding),
-		.Secure(SecFifoPtr)
-	) u_rspfifo(
-		.clk_i(clk_i),
-		.rst_ni(rst_ni),
-		.clr_i(1'b0),
-		.wvalid_i(rspfifo_wvalid),
-		.wready_o(rspfifo_wready),
-		.wdata_i(rspfifo_wdata),
-		.rvalid_o(rspfifo_rvalid),
-		.rready_i(rspfifo_rready),
-		.rdata_o(rspfifo_rdata),
-		.err_o(rsp_fifo_error)
-	);
-endmodule
 module prim_alert_receiver (
 	clk_i,
 	rst_ni,
diff --git a/cpus/ibex_custom_pregenerated/cellift/generated/sv2v_out.v b/cpus/ibex_custom_pregenerated/cellift/generated/sv2v_out.v
index c70a5a68..a05fb714 100644
--- a/cpus/ibex_custom_pregenerated/cellift/generated/sv2v_out.v
+++ b/cpus/ibex_custom_pregenerated/cellift/generated/sv2v_out.v
@@ -10960,263 +10960,7 @@ module alert_handler_reg_top (
 	assign unused_wdata = ^reg_wdata;
 	assign unused_be = ^reg_be;
 endmodule
-module cellift_rv_core_ibex_mem_top (
-	clk_i,
-	rst_ni,
-	clk_edn_i,
-	rst_edn_ni,
-	clk_esc_i,
-	rst_esc_ni,
-	rst_cpu_n_o,
-	ram_cfg_i,
-	hart_id_i,
-	boot_addr_i,
-	instr_mem_req_o,
-	instr_mem_gnt_i,
-	instr_mem_addr_o,
-	instr_mem_wdata_o,
-	instr_mem_strb_o,
-	instr_mem_we_o,
-	instr_mem_rdata_i,
-	data_mem_req_o,
-	data_mem_gnt_i,
-	data_mem_addr_o,
-	data_mem_wdata_o,
-	data_mem_strb_o,
-	data_mem_we_o,
-	data_mem_rdata_i,
-	irq_software_i,
-	irq_timer_i,
-	irq_external_i,
-	esc_tx_i,
-	esc_rx_o,
-	nmi_wdog_i,
-	debug_req_i,
-	crash_dump_o,
-	pwrmgr_cpu_en_i,
-	lc_cpu_en_i,
-	pwrmgr_o,
-	scan_rst_ni,
-	scanmode_i,
-	cfg_tl_d_i,
-	cfg_tl_d_o,
-	edn_o,
-	edn_i,
-	clk_otp_i,
-	rst_otp_ni,
-	icache_otp_key_o,
-	icache_otp_key_i,
-	fpga_info_i,
-	alert_rx_i,
-	alert_tx_o
-);
-	parameter [31:0] InstrMemAw = 20;
-	parameter [31:0] DataMemAw = 20;
-	input wire clk_i;
-	input wire rst_ni;
-	input wire clk_edn_i;
-	input wire rst_edn_ni;
-	input wire clk_esc_i;
-	input wire rst_esc_ni;
-	output wire rst_cpu_n_o;
-	input wire [9:0] ram_cfg_i;
-	input wire [31:0] hart_id_i;
-	input wire [31:0] boot_addr_i;
-	output wire instr_mem_req_o;
-	input wire instr_mem_gnt_i;
-	output wire [InstrMemAw:0] instr_mem_addr_o;
-	output wire [31:0] instr_mem_wdata_o;
-	output wire [31:0] instr_mem_strb_o;
-	output wire instr_mem_we_o;
-	input wire [31:0] instr_mem_rdata_i;
-	output wire data_mem_req_o;
-	input wire data_mem_gnt_i;
-	output wire [InstrMemAw:0] data_mem_addr_o;
-	output wire [31:0] data_mem_wdata_o;
-	output wire [31:0] data_mem_strb_o;
-	output wire data_mem_we_o;
-	input wire [31:0] data_mem_rdata_i;
-	input wire irq_software_i;
-	input wire irq_timer_i;
-	input wire irq_external_i;
-	input wire [1:0] esc_tx_i;
-	output wire [1:0] esc_rx_o;
-	input wire nmi_wdog_i;
-	input wire debug_req_i;
-	output wire [159:0] crash_dump_o;
-	localparam signed [31:0] lc_ctrl_pkg_TxWidth = 4;
-	input wire [3:0] pwrmgr_cpu_en_i;
-	input wire [3:0] lc_cpu_en_i;
-	output wire [0:0] pwrmgr_o;
-	input scan_rst_ni;
-	localparam signed [31:0] prim_mubi_pkg_MuBi4Width = 4;
-	input wire [3:0] scanmode_i;
-	localparam signed [31:0] tlul_pkg_DataIntgWidth = 7;
-	localparam signed [31:0] tlul_pkg_H2DCmdIntgWidth = 7;
-	localparam signed [31:0] top_pkg_TL_AIW = 8;
-	localparam signed [31:0] top_pkg_TL_AW = 32;
-	localparam signed [31:0] top_pkg_TL_DW = 32;
-	localparam signed [31:0] top_pkg_TL_DBW = top_pkg_TL_DW >> 3;
-	localparam signed [31:0] top_pkg_TL_SZW = $clog2($clog2(top_pkg_TL_DBW) + 1);
-	input wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 23:0] cfg_tl_d_i;
-	localparam signed [31:0] tlul_pkg_D2HRspIntgWidth = 7;
-	localparam signed [31:0] top_pkg_TL_DIW = 1;
-	output wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + (tlul_pkg_D2HRspIntgWidth + tlul_pkg_DataIntgWidth)) + 1:0] cfg_tl_d_o;
-	output wire [0:0] edn_o;
-	localparam [31:0] edn_pkg_ENDPOINT_BUS_WIDTH = 32;
-	input wire [33:0] edn_i;
-	input clk_otp_i;
-	input rst_otp_ni;
-	output wire [0:0] icache_otp_key_o;
-	localparam signed [31:0] otp_ctrl_pkg_SramKeyWidth = 128;
-	localparam signed [31:0] otp_ctrl_pkg_SramNonceWidth = 128;
-	input wire [257:0] icache_otp_key_i;
-	input [31:0] fpga_info_i;
-	localparam signed [31:0] rv_core_ibex_reg_pkg_NumAlerts = 4;
-	input wire [15:0] alert_rx_i;
-	output wire [7:0] alert_tx_o;
-	wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + (tlul_pkg_D2HRspIntgWidth + tlul_pkg_DataIntgWidth)) + 1:0] tl_i_toibex;
-	wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 23:0] tl_i_fromibex;
-	wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + (tlul_pkg_D2HRspIntgWidth + tlul_pkg_DataIntgWidth)) + 1:0] tl_d_toibex;
-	wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 23:0] tl_d_fromibex;
-	wire instr_rvalid_d;
-	reg instr_rvalid_q;
-	wire data_rvalid_d;
-	reg data_rvalid_q;
-	assign instr_rvalid_d = instr_mem_req_o & ~instr_mem_we_o;
-	assign data_rvalid_d = data_mem_req_o & ~data_mem_we_o;
-	always @(posedge clk_i)
-		if (~rst_ni) begin
-			instr_rvalid_q <= 1'sb0;
-			data_rvalid_q <= 1'sb0;
-		end
-		else begin
-			instr_rvalid_q <= instr_rvalid_d;
-			data_rvalid_q <= data_rvalid_d;
-		end
-	function automatic [3:0] sv2v_cast_AC3DB;
-		input reg [3:0] inp;
-		sv2v_cast_AC3DB = inp;
-	endfunction
-	noerr_tlul_adapter_sram #(
-		.SramAw(InstrMemAw),
-		.SramDw(32),
-		.Outstanding(1),
-		.ByteAccess(1),
-		.ErrOnWrite(0),
-		.ErrOnRead(0),
-		.CmdIntgCheck(0),
-		.EnableRspIntgGen(0),
-		.EnableDataIntgGen(0),
-		.EnableDataIntgPt(0)
-	) i_instr_tlul_adapter_sram(
-		.clk_i(clk_i),
-		.rst_ni(rst_ni),
-		.tl_i(tl_i_fromibex),
-		.tl_o(tl_i_toibex),
-		.en_ifetch_i(sv2v_cast_AC3DB(4'h6)),
-		.req_o(instr_mem_req_o),
-		.gnt_i(instr_mem_gnt_i),
-		.we_o(instr_mem_we_o),
-		.addr_o(instr_mem_addr_o),
-		.wdata_o(instr_mem_wdata_o),
-		.wmask_o(instr_mem_strb_o),
-		.rdata_i(instr_mem_rdata_i),
-		.rvalid_i(instr_rvalid_q),
-		.rerror_i(2'b00)
-	);
-	noerr_tlul_adapter_sram #(
-		.SramAw(DataMemAw),
-		.SramDw(32),
-		.Outstanding(1),
-		.ByteAccess(1),
-		.ErrOnWrite(0),
-		.ErrOnRead(0),
-		.CmdIntgCheck(0),
-		.EnableRspIntgGen(0),
-		.EnableDataIntgGen(0),
-		.EnableDataIntgPt(0)
-	) i_data_tlul_adapter_sram(
-		.clk_i(clk_i),
-		.rst_ni(rst_ni),
-		.tl_i(tl_d_fromibex),
-		.tl_o(tl_d_toibex),
-		.en_ifetch_i(sv2v_cast_AC3DB(4'h6)),
-		.req_o(data_mem_req_o),
-		.gnt_i(data_mem_gnt_i),
-		.we_o(data_mem_we_o),
-		.addr_o(data_mem_addr_o),
-		.wdata_o(data_mem_wdata_o),
-		.wmask_o(data_mem_strb_o),
-		.rdata_i(data_mem_rdata_i),
-		.rvalid_i(data_rvalid_q),
-		.rerror_i(2'b00)
-	);
-	localparam signed [31:0] ibex_pkg_LfsrWidth = 32;
-	localparam [159:0] ibex_pkg_RndCnstLfsrPermDefault = 160'h1e35ecba467fd1b12e958152c04fa43878a8daed;
-	localparam [31:0] ibex_pkg_RndCnstLfsrSeedDefault = 32'hac533bf4;
-	noerr_rv_core_ibex #(
-		.PMPEnable(1'b0),
-		.PMPGranularity(0),
-		.PMPNumRegions(4),
-		.MHPMCounterNum(0),
-		.MHPMCounterWidth(40),
-		.RV32E(1'b0),
-		.RV32M(32'sd1),
-		.RV32B(32'sd0),
-		.BranchTargetALU(1'b0),
-		.WritebackStage(1'b1),
-		.ICache(1'b0),
-		.ICacheECC(1'b0),
-		.BranchPredictor(1'b0),
-		.DbgTriggerEn(1'b0),
-		.DbgHwBreakNum(1),
-		.RndCnstLfsrSeed(ibex_pkg_RndCnstLfsrSeedDefault),
-		.RndCnstLfsrPerm(ibex_pkg_RndCnstLfsrPermDefault),
-		.SecureIbex(1'b0),
-		.DmHaltAddr(32'h1a110800),
-		.DmExceptionAddr(32'h01a11080)
-	) i_rv_core_ibex(
-		.clk_i(clk_i),
-		.rst_ni(rst_ni),
-		.clk_edn_i(clk_edn_i),
-		.rst_edn_ni(rst_edn_ni),
-		.clk_esc_i(clk_esc_i),
-		.rst_esc_ni(rst_esc_ni),
-		.rst_cpu_n_o(rst_cpu_n_o),
-		.ram_cfg_i(ram_cfg_i),
-		.hart_id_i(hart_id_i),
-		.boot_addr_i(boot_addr_i),
-		.corei_tl_h_o(tl_i_fromibex),
-		.corei_tl_h_i(tl_i_toibex),
-		.cored_tl_h_o(tl_d_fromibex),
-		.cored_tl_h_i(tl_d_toibex),
-		.irq_software_i(irq_software_i),
-		.irq_timer_i(irq_timer_i),
-		.irq_external_i(irq_external_i),
-		.esc_tx_i(esc_tx_i),
-		.esc_rx_o(esc_rx_o),
-		.nmi_wdog_i(nmi_wdog_i),
-		.debug_req_i(debug_req_i),
-		.crash_dump_o(crash_dump_o),
-		.lc_cpu_en_i(lc_cpu_en_i),
-		.pwrmgr_cpu_en_i(pwrmgr_cpu_en_i),
-		.pwrmgr_o(pwrmgr_o),
-		.scan_rst_ni(scan_rst_ni),
-		.scanmode_i(scanmode_i),
-		.cfg_tl_d_i(cfg_tl_d_i),
-		.cfg_tl_d_o(cfg_tl_d_o),
-		.edn_o(edn_o),
-		.edn_i(edn_i),
-		.clk_otp_i(clk_otp_i),
-		.rst_otp_ni(rst_otp_ni),
-		.icache_otp_key_o(icache_otp_key_o),
-		.icache_otp_key_i(icache_otp_key_i),
-		.fpga_info_i(fpga_info_i),
-		.alert_rx_i(alert_rx_i),
-		.alert_tx_o(alert_tx_o)
-	);
-endmodule
+
 module ibex_alu (
 	operator_i,
 	operand_a_i,
@@ -21067,1110 +20811,7 @@ module ibex_wb_stage (
 	assign rf_wdata_wb_o = ({32 {rf_wdata_wb_mux_we[0]}} & rf_wdata_wb_mux[0]) | ({32 {rf_wdata_wb_mux_we[1]}} & rf_wdata_wb_mux[1]);
 	assign rf_we_wb_o = |rf_wdata_wb_mux_we;
 endmodule
-module noerr_rv_core_ibex (
-	clk_i,
-	rst_ni,
-	clk_edn_i,
-	rst_edn_ni,
-	clk_esc_i,
-	rst_esc_ni,
-	rst_cpu_n_o,
-	ram_cfg_i,
-	hart_id_i,
-	boot_addr_i,
-	corei_tl_h_o,
-	corei_tl_h_i,
-	cored_tl_h_o,
-	cored_tl_h_i,
-	irq_software_i,
-	irq_timer_i,
-	irq_external_i,
-	esc_tx_i,
-	esc_rx_o,
-	nmi_wdog_i,
-	debug_req_i,
-	crash_dump_o,
-	lc_cpu_en_i,
-	pwrmgr_cpu_en_i,
-	pwrmgr_o,
-	scan_rst_ni,
-	scanmode_i,
-	cfg_tl_d_i,
-	cfg_tl_d_o,
-	edn_o,
-	edn_i,
-	clk_otp_i,
-	rst_otp_ni,
-	icache_otp_key_o,
-	icache_otp_key_i,
-	fpga_info_i,
-	alert_rx_i,
-	alert_tx_o
-);
-	localparam signed [31:0] rv_core_ibex_reg_pkg_NumAlerts = 4;
-	parameter [3:0] AlertAsyncOn = {rv_core_ibex_reg_pkg_NumAlerts {1'b1}};
-	parameter [0:0] PMPEnable = 1'b1;
-	parameter [31:0] PMPGranularity = 0;
-	parameter [31:0] PMPNumRegions = 16;
-	parameter [31:0] MHPMCounterNum = 10;
-	parameter [31:0] MHPMCounterWidth = 32;
-	parameter [0:0] RV32E = 0;
-	parameter integer RV32M = 32'sd3;
-	parameter integer RV32B = 32'sd2;
-	parameter integer RegFile = 32'sd0;
-	parameter [0:0] BranchTargetALU = 1'b1;
-	parameter [0:0] WritebackStage = 1'b1;
-	parameter [0:0] ICache = 1'b1;
-	parameter [0:0] ICacheECC = 1'b1;
-	parameter [0:0] ICacheScramble = 1'b1;
-	parameter [0:0] BranchPredictor = 1'b0;
-	parameter [0:0] DbgTriggerEn = 1'b1;
-	parameter [31:0] DbgHwBreakNum = 4;
-	parameter [0:0] SecureIbex = 1'b1;
-	localparam signed [31:0] ibex_pkg_LfsrWidth = 32;
-	localparam [31:0] ibex_pkg_RndCnstLfsrSeedDefault = 32'hac533bf4;
-	parameter [31:0] RndCnstLfsrSeed = ibex_pkg_RndCnstLfsrSeedDefault;
-	localparam [159:0] ibex_pkg_RndCnstLfsrPermDefault = 160'h1e35ecba467fd1b12e958152c04fa43878a8daed;
-	parameter [159:0] RndCnstLfsrPerm = ibex_pkg_RndCnstLfsrPermDefault;
-	parameter [31:0] DmHaltAddr = 32'h1a110800;
-	parameter [31:0] DmExceptionAddr = 32'h1a110808;
-	parameter [0:0] PipeLine = 1'b0;
-	localparam [31:0] ibex_pkg_SCRAMBLE_KEY_W = 128;
-	localparam [127:0] ibex_pkg_RndCnstIbexKeyDefault = 128'h14e8cecae3040d5e12286bb3cc113298;
-	parameter [127:0] RndCnstIbexKeyDefault = ibex_pkg_RndCnstIbexKeyDefault;
-	localparam [31:0] ibex_pkg_SCRAMBLE_NONCE_W = 64;
-	localparam [63:0] ibex_pkg_RndCnstIbexNonceDefault = 64'hf79780bc735f3843;
-	parameter [63:0] RndCnstIbexNonceDefault = ibex_pkg_RndCnstIbexNonceDefault;
-	input wire clk_i;
-	input wire rst_ni;
-	input wire clk_edn_i;
-	input wire rst_edn_ni;
-	input wire clk_esc_i;
-	input wire rst_esc_ni;
-	output wire rst_cpu_n_o;
-	input wire [9:0] ram_cfg_i;
-	input wire [31:0] hart_id_i;
-	input wire [31:0] boot_addr_i;
-	localparam signed [31:0] prim_mubi_pkg_MuBi4Width = 4;
-	localparam signed [31:0] tlul_pkg_DataIntgWidth = 7;
-	localparam signed [31:0] tlul_pkg_H2DCmdIntgWidth = 7;
-	localparam signed [31:0] top_pkg_TL_AIW = 8;
-	localparam signed [31:0] top_pkg_TL_AW = 32;
-	localparam signed [31:0] top_pkg_TL_DW = 32;
-	localparam signed [31:0] top_pkg_TL_DBW = top_pkg_TL_DW >> 3;
-	localparam signed [31:0] top_pkg_TL_SZW = $clog2($clog2(top_pkg_TL_DBW) + 1);
-	output wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 23:0] corei_tl_h_o;
-	localparam signed [31:0] tlul_pkg_D2HRspIntgWidth = 7;
-	localparam signed [31:0] top_pkg_TL_DIW = 1;
-	input wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + (tlul_pkg_D2HRspIntgWidth + tlul_pkg_DataIntgWidth)) + 1:0] corei_tl_h_i;
-	output wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 23:0] cored_tl_h_o;
-	input wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + (tlul_pkg_D2HRspIntgWidth + tlul_pkg_DataIntgWidth)) + 1:0] cored_tl_h_i;
-	input wire irq_software_i;
-	input wire irq_timer_i;
-	input wire irq_external_i;
-	input wire [1:0] esc_tx_i;
-	output wire [1:0] esc_rx_o;
-	input wire nmi_wdog_i;
-	input wire debug_req_i;
-	output wire [224:0] crash_dump_o;
-	localparam signed [31:0] lc_ctrl_pkg_TxWidth = 4;
-	input wire [3:0] lc_cpu_en_i;
-	input wire [3:0] pwrmgr_cpu_en_i;
-	output wire [0:0] pwrmgr_o;
-	input scan_rst_ni;
-	input wire [3:0] scanmode_i;
-	input wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 23:0] cfg_tl_d_i;
-	output wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + (tlul_pkg_D2HRspIntgWidth + tlul_pkg_DataIntgWidth)) + 1:0] cfg_tl_d_o;
-	output wire [0:0] edn_o;
-	localparam [31:0] edn_pkg_ENDPOINT_BUS_WIDTH = 32;
-	input wire [33:0] edn_i;
-	input clk_otp_i;
-	input rst_otp_ni;
-	output wire [0:0] icache_otp_key_o;
-	localparam signed [31:0] otp_ctrl_pkg_SramKeyWidth = 128;
-	localparam signed [31:0] otp_ctrl_pkg_SramNonceWidth = 128;
-	input wire [257:0] icache_otp_key_i;
-	input [31:0] fpga_info_i;
-	input wire [15:0] alert_rx_i;
-	output wire [7:0] alert_tx_o;
-	wire [312:0] reg2hw;
-	wire [82:0] hw2reg;
-	localparam [0:0] FifoPass = (PipeLine ? 1'b0 : 1'b1);
-	localparam [31:0] FifoDepth = (PipeLine ? 2 : 0);
-	localparam signed [31:0] NumOutstandingReqs = (ICache ? 8 : 2);
-	wire instr_req;
-	wire instr_gnt;
-	wire instr_rvalid;
-	wire [31:0] instr_addr;
-	wire [31:0] instr_rdata;
-	wire [6:0] instr_rdata_intg;
-	wire instr_err;
-	wire data_req;
-	wire data_gnt;
-	wire data_rvalid;
-	wire data_we;
-	wire [3:0] data_be;
-	wire [31:0] data_addr;
-	wire [31:0] data_wdata;
-	wire [6:0] data_wdata_intg;
-	wire [31:0] data_rdata;
-	wire [6:0] data_rdata_intg;
-	wire data_err;
-	wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 23:0] tl_i_ibex2fifo;
-	wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + (tlul_pkg_D2HRspIntgWidth + tlul_pkg_DataIntgWidth)) + 1:0] tl_i_fifo2ibex;
-	wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 23:0] tl_d_ibex2fifo;
-	wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + (tlul_pkg_D2HRspIntgWidth + tlul_pkg_DataIntgWidth)) + 1:0] tl_d_fifo2ibex;
-	wire core_sleep;
-	wire ibex_top_clk_i;
-	wire addr_trans_rst_ni;
-	assign ibex_top_clk_i = clk_i;
-	assign addr_trans_rst_ni = rst_ni;
-	wire ibus_intg_err;
-	wire dbus_intg_err;
-	wire alert_minor;
-	wire alert_major_internal;
-	wire alert_major_bus;
-	wire double_fault;
-	wire fatal_intg_err;
-	wire fatal_core_err;
-	wire recov_core_err;
-	wire fatal_intg_event;
-	wire fatal_core_event;
-	wire recov_core_event;
-	assign fatal_intg_event = (ibus_intg_err | dbus_intg_err) | alert_major_bus;
-	assign fatal_core_event = alert_major_internal | double_fault;
-	assign recov_core_event = alert_minor;
-	localparam signed [31:0] rv_core_ibex_reg_pkg_NumRegions = 2;
-	wire [129:0] ibus_region_cfg;
-	wire [129:0] dbus_region_cfg;
-	assign rst_cpu_n_o = rst_ni;
-	wire esc_irq_nm;
-	localparam signed [31:0] alert_handler_reg_pkg_N_ESC_SEV = 4;
-	localparam signed [31:0] alert_handler_reg_pkg_PING_CNT_DW = 16;
-	prim_esc_receiver #(
-		.N_ESC_SEV(alert_handler_reg_pkg_N_ESC_SEV),
-		.PING_CNT_DW(alert_handler_reg_pkg_PING_CNT_DW)
-	) u_prim_esc_receiver(
-		.clk_i(clk_esc_i),
-		.rst_ni(rst_esc_ni),
-		.esc_req_o(esc_irq_nm),
-		.esc_rx_o(esc_rx_o),
-		.esc_tx_i(esc_tx_i)
-	);
-	wire alert_irq_nm;
-	prim_flop_2sync #(.Width(1)) u_alert_nmi_sync(
-		.clk_i(clk_i),
-		.rst_ni(rst_ni),
-		.d_i(esc_irq_nm),
-		.q_o(alert_irq_nm)
-	);
-	wire wdog_irq_nm;
-	prim_flop_2sync #(.Width(1)) u_wdog_nmi_sync(
-		.clk_i(clk_i),
-		.rst_ni(rst_ni),
-		.d_i(nmi_wdog_i),
-		.q_o(wdog_irq_nm)
-	);
-	assign hw2reg[77] = 1'b1;
-	assign hw2reg[76] = alert_irq_nm;
-	assign hw2reg[75] = 1'b1;
-	assign hw2reg[74] = wdog_irq_nm;
-	wire irq_nm;
-	assign irq_nm = |(reg2hw[34-:2] & reg2hw[36-:2]);
-	wire [3:0] lc_cpu_en;
-	prim_lc_sync u_lc_sync(
-		.clk_i(clk_i),
-		.rst_ni(rst_ni),
-		.lc_en_i(lc_cpu_en_i),
-		.lc_en_o(lc_cpu_en)
-	);
-	wire [3:0] pwrmgr_cpu_en;
-	prim_lc_sync u_pwrmgr_sync(
-		.clk_i(clk_i),
-		.rst_ni(rst_ni),
-		.lc_en_i(pwrmgr_cpu_en_i),
-		.lc_en_o(pwrmgr_cpu_en)
-	);
-	wire irq_timer_sync;
-	prim_flop_2sync #(.Width(1)) u_intr_timer_sync(
-		.clk_i(clk_i),
-		.rst_ni(rst_ni),
-		.d_i(irq_timer_i),
-		.q_o(irq_timer_sync)
-	);
-	wire irq_software;
-	wire irq_timer;
-	wire irq_external;
-	prim_sec_anchor_buf #(.Width(3)) u_prim_buf_irq(
-		.in_i({irq_software_i, irq_timer_sync, irq_external_i}),
-		.out_o({irq_software, irq_timer, irq_external})
-	);
-	wire key_req;
-	wire key_ack;
-	wire [127:0] key;
-	wire [63:0] nonce;
-	wire unused_seed_valid;
-	localparam signed [31:0] PayLoadW = (ibex_pkg_SCRAMBLE_KEY_W + ibex_pkg_SCRAMBLE_NONCE_W) + 1;
-	prim_sync_reqack_data #(
-		.Width(PayLoadW),
-		.DataSrc2Dst(1'b0)
-	) u_prim_sync_reqack_data(
-		.clk_src_i(clk_i),
-		.rst_src_ni(rst_ni),
-		.clk_dst_i(clk_otp_i),
-		.rst_dst_ni(rst_otp_ni),
-		.req_chk_i(1'b1),
-		.src_req_i(key_req),
-		.src_ack_o(key_ack),
-		.dst_req_o(icache_otp_key_o[0]),
-		.dst_ack_i(icache_otp_key_i[257]),
-		.data_i({icache_otp_key_i[256-:128], icache_otp_key_i[64:1], icache_otp_key_i[0]}),
-		.data_o({key, nonce, unused_seed_valid})
-	);
-	wire unused_nonce;
-	assign unused_nonce = |icache_otp_key_i[128-:128];
-	wire [3:0] local_fetch_enable_d;
-	wire [3:0] local_fetch_enable_q;
-	function automatic [3:0] sv2v_cast_A1913;
-		input reg [3:0] inp;
-		sv2v_cast_A1913 = inp;
-	endfunction
-	assign local_fetch_enable_d = (fatal_core_err ? sv2v_cast_A1913(4'b1010) : local_fetch_enable_q);
-	prim_lc_sender #(
-		.AsyncOn(1),
-		.ResetValueIsOn(1)
-	) u_prim_lc_sender(
-		.clk_i(clk_i),
-		.rst_ni(rst_ni),
-		.lc_en_i(local_fetch_enable_d),
-		.lc_en_o(local_fetch_enable_q)
-	);
-	wire [3:0] fetch_enable;
-	function automatic [3:0] lc_ctrl_pkg_lc_tx_and;
-		input reg [3:0] a;
-		input reg [3:0] b;
-		input reg [3:0] act;
-		reg [3:0] a_in;
-		reg [3:0] b_in;
-		reg [3:0] act_in;
-		reg [3:0] out;
-		begin
-			a_in = a;
-			b_in = b;
-			act_in = act;
-			begin : sv2v_autoblock_1
-				reg signed [31:0] k;
-				for (k = 0; k < lc_ctrl_pkg_TxWidth; k = k + 1)
-					if (act_in[k])
-						out[k] = a_in[k] && b_in[k];
-					else
-						out[k] = a_in[k] || b_in[k];
-			end
-			lc_ctrl_pkg_lc_tx_and = out;
-		end
-	endfunction
-	function automatic [3:0] lc_ctrl_pkg_lc_tx_and_hi;
-		input reg [3:0] a;
-		input reg [3:0] b;
-		lc_ctrl_pkg_lc_tx_and_hi = lc_ctrl_pkg_lc_tx_and(a, b, sv2v_cast_A1913(4'b0101));
-	endfunction
-	assign fetch_enable = lc_ctrl_pkg_lc_tx_and_hi(local_fetch_enable_q, lc_ctrl_pkg_lc_tx_and_hi(lc_cpu_en[0+:lc_ctrl_pkg_TxWidth], pwrmgr_cpu_en[0+:lc_ctrl_pkg_TxWidth]));
-	wire [159:0] crash_dump;
-	function automatic [3:0] sv2v_cast_38B98;
-		input reg [3:0] inp;
-		sv2v_cast_38B98 = inp;
-	endfunction
-	function automatic prim_mubi_pkg_mubi4_test_true_strict;
-		input reg [3:0] val;
-		prim_mubi_pkg_mubi4_test_true_strict = sv2v_cast_38B98(4'h6) == val;
-	endfunction
-	ibex_top #(
-		.PMPEnable(PMPEnable),
-		.PMPGranularity(PMPGranularity),
-		.PMPNumRegions(PMPNumRegions),
-		.MHPMCounterNum(MHPMCounterNum),
-		.MHPMCounterWidth(MHPMCounterWidth),
-		.RV32E(RV32E),
-		.RV32M(RV32M),
-		.RV32B(RV32B),
-		.RegFile(RegFile),
-		.BranchTargetALU(BranchTargetALU),
-		.WritebackStage(WritebackStage),
-		.ICache(ICache),
-		.ICacheECC(ICacheECC),
-		.ICacheScramble(ICacheScramble),
-		.BranchPredictor(BranchPredictor),
-		.DbgTriggerEn(DbgTriggerEn),
-		.DbgHwBreakNum(DbgHwBreakNum),
-		.SecureIbex(SecureIbex),
-		.RndCnstLfsrSeed(RndCnstLfsrSeed),
-		.RndCnstLfsrPerm(RndCnstLfsrPerm),
-		.RndCnstIbexKey(RndCnstIbexKeyDefault),
-		.RndCnstIbexNonce(RndCnstIbexNonceDefault),
-		.DmHaltAddr(DmHaltAddr),
-		.DmExceptionAddr(DmExceptionAddr)
-	) u_core(
-		.clk_i(ibex_top_clk_i),
-		.rst_ni(rst_ni),
-		.test_en_i(prim_mubi_pkg_mubi4_test_true_strict(scanmode_i)),
-		.scan_rst_ni(scan_rst_ni),
-		.ram_cfg_i(ram_cfg_i),
-		.hart_id_i(hart_id_i),
-		.boot_addr_i(boot_addr_i),
-		.instr_req_o(instr_req),
-		.instr_gnt_i(instr_gnt),
-		.instr_rvalid_i(instr_rvalid),
-		.instr_addr_o(instr_addr),
-		.instr_rdata_i(instr_rdata),
-		.instr_rdata_intg_i(instr_rdata_intg),
-		.instr_err_i(instr_err),
-		.data_req_o(data_req),
-		.data_gnt_i(data_gnt),
-		.data_rvalid_i(data_rvalid),
-		.data_we_o(data_we),
-		.data_be_o(data_be),
-		.data_addr_o(data_addr),
-		.data_wdata_o(data_wdata),
-		.data_wdata_intg_o(data_wdata_intg),
-		.data_rdata_i(data_rdata),
-		.data_rdata_intg_i(data_rdata_intg),
-		.data_err_i(data_err),
-		.irq_software_i(irq_software),
-		.irq_timer_i(irq_timer),
-		.irq_external_i(irq_external),
-		.irq_fast_i(1'sb0),
-		.irq_nm_i(irq_nm),
-		.debug_req_i(debug_req_i),
-		.crash_dump_o(crash_dump),
-		.scramble_key_valid_i(key_ack),
-		.scramble_key_i(key),
-		.scramble_nonce_i(nonce),
-		.scramble_req_o(key_req),
-		.double_fault_seen_o(double_fault),
-		.fetch_enable_i(fetch_enable),
-		.alert_minor_o(alert_minor),
-		.alert_major_internal_o(alert_major_internal),
-		.alert_major_bus_o(alert_major_bus),
-		.core_sleep_o(core_sleep)
-	);
-	reg core_sleep_q;
-	always @(posedge clk_i or negedge rst_ni)
-		if (!rst_ni)
-			core_sleep_q <= 1'sb0;
-		else
-			core_sleep_q <= core_sleep;
-	prim_buf #(.Width(1)) u_core_sleeping_buf(
-		.in_i(core_sleep_q),
-		.out_o(pwrmgr_o[0])
-	);
-	reg prev_valid;
-	reg [31:0] prev_exception_pc;
-	reg [31:0] prev_exception_addr;
-	assign crash_dump_o[159-:160] = crash_dump;
-	assign crash_dump_o[224] = prev_valid;
-	assign crash_dump_o[223-:32] = prev_exception_pc;
-	assign crash_dump_o[191-:32] = prev_exception_addr;
-	always @(posedge clk_i or negedge rst_ni)
-		if (!rst_ni) begin
-			prev_valid <= 1'sb0;
-			prev_exception_pc <= 1'sb0;
-			prev_exception_addr <= 1'sb0;
-		end
-		else if (double_fault) begin
-			prev_valid <= 1'b1;
-			prev_exception_pc <= crash_dump[63-:32];
-			prev_exception_addr <= crash_dump[31-:32];
-		end
-	wire [31:0] instr_addr_trans;
-	rv_core_addr_trans #(
-		.AddrWidth(32),
-		.NumRegions(rv_core_ibex_reg_pkg_NumRegions)
-	) u_ibus_trans(
-		.clk_i(clk_i),
-		.rst_ni(addr_trans_rst_ni),
-		.region_cfg_i(ibus_region_cfg),
-		.addr_i(instr_addr),
-		.addr_o(instr_addr_trans)
-	);
-	assign instr_err = 0;
-	wire [6:0] instr_wdata_intg;
-	wire [31:0] unused_data;
-	function automatic [38:0] sv2v_cast_39;
-		input reg [38:0] inp;
-		sv2v_cast_39 = inp;
-	endfunction
-	function automatic [38:0] prim_secded_pkg_prim_secded_inv_39_32_enc;
-		input reg [31:0] data_i;
-		reg [38:0] data_o;
-		begin
-			data_o = sv2v_cast_39(data_i);
-			data_o[32] = ^(data_o & 39'h002606bd25);
-			data_o[33] = ^(data_o & 39'h00deba8050);
-			data_o[34] = ^(data_o & 39'h00413d89aa);
-			data_o[35] = ^(data_o & 39'h0031234ed1);
-			data_o[36] = ^(data_o & 39'h00c2c1323b);
-			data_o[37] = ^(data_o & 39'h002dcc624c);
-			data_o[38] = ^(data_o & 39'h0098505586);
-			data_o = data_o ^ 39'h2a00000000;
-			prim_secded_pkg_prim_secded_inv_39_32_enc = data_o;
-		end
-	endfunction
-	assign {instr_wdata_intg, unused_data} = prim_secded_pkg_prim_secded_inv_39_32_enc(instr_rdata);
-	tlul_adapter_host #(
-		.MAX_REQS(NumOutstandingReqs),
-		.EnableDataIntgGen(~SecureIbex)
-	) tl_adapter_host_i_ibex(
-		.clk_i(clk_i),
-		.rst_ni(rst_ni),
-		.req_i(instr_req),
-		.instr_type_i(sv2v_cast_38B98(4'h6)),
-		.gnt_o(instr_gnt),
-		.addr_i(instr_addr_trans),
-		.we_i(1'b0),
-		.wdata_i(32'b00000000000000000000000000000000),
-		.wdata_intg_i(instr_wdata_intg),
-		.be_i(4'hf),
-		.valid_o(instr_rvalid),
-		.rdata_o(instr_rdata),
-		.rdata_intg_o(instr_rdata_intg),
-		.intg_err_o(ibus_intg_err),
-		.tl_o(tl_i_ibex2fifo),
-		.tl_i(tl_i_fifo2ibex)
-	);
-	tlul_fifo_sync #(
-		.ReqPass(FifoPass),
-		.RspPass(FifoPass),
-		.ReqDepth(FifoDepth),
-		.RspDepth(FifoDepth)
-	) fifo_i(
-		.clk_i(clk_i),
-		.rst_ni(rst_ni),
-		.tl_h_i(tl_i_ibex2fifo),
-		.tl_h_o(tl_i_fifo2ibex),
-		.tl_d_o(corei_tl_h_o),
-		.tl_d_i(corei_tl_h_i),
-		.spare_req_i(1'b0),
-		.spare_rsp_i(1'b0)
-	);
-	wire [31:0] data_addr_trans;
-	rv_core_addr_trans #(
-		.AddrWidth(32),
-		.NumRegions(rv_core_ibex_reg_pkg_NumRegions)
-	) u_dbus_trans(
-		.clk_i(clk_i),
-		.rst_ni(addr_trans_rst_ni),
-		.region_cfg_i(dbus_region_cfg),
-		.addr_i(data_addr),
-		.addr_o(data_addr_trans)
-	);
-	assign data_err = 0;
-	tlul_adapter_host #(
-		.MAX_REQS(2),
-		.EnableDataIntgGen(~SecureIbex)
-	) tl_adapter_host_d_ibex(
-		.clk_i(clk_i),
-		.rst_ni(rst_ni),
-		.req_i(data_req),
-		.instr_type_i(sv2v_cast_38B98(4'h9)),
-		.gnt_o(data_gnt),
-		.addr_i(data_addr_trans),
-		.we_i(data_we),
-		.wdata_i(data_wdata),
-		.wdata_intg_i(data_wdata_intg),
-		.be_i(data_be),
-		.valid_o(data_rvalid),
-		.rdata_o(data_rdata),
-		.rdata_intg_o(data_rdata_intg),
-		.intg_err_o(dbus_intg_err),
-		.tl_o(tl_d_ibex2fifo),
-		.tl_i(tl_d_fifo2ibex)
-	);
-	tlul_fifo_sync #(
-		.ReqPass(FifoPass),
-		.RspPass(FifoPass),
-		.ReqDepth(FifoDepth),
-		.RspDepth(FifoDepth)
-	) fifo_d(
-		.clk_i(clk_i),
-		.rst_ni(rst_ni),
-		.tl_h_i(tl_d_ibex2fifo),
-		.tl_h_o(tl_d_fifo2ibex),
-		.tl_d_o(cored_tl_h_o),
-		.tl_d_i(cored_tl_h_i),
-		.spare_req_i(1'b0),
-		.spare_rsp_i(1'b0)
-	);
-	wire intg_err;
-	wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 23:0] tl_win_h2d;
-	wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + (tlul_pkg_D2HRspIntgWidth + tlul_pkg_DataIntgWidth)) + 1:0] tl_win_d2h;
-	rv_core_ibex_cfg_reg_top u_reg_cfg(
-		.clk_i(clk_i),
-		.rst_ni(rst_ni),
-		.tl_i(cfg_tl_d_i),
-		.tl_o(cfg_tl_d_o),
-		.reg2hw(reg2hw),
-		.hw2reg(hw2reg),
-		.intg_err_o(intg_err),
-		.tl_win_o(tl_win_h2d),
-		.tl_win_i(tl_win_d2h),
-		.devmode_i(1'b1)
-	);
-	genvar i;
-	generate
-		for (i = 0; i < rv_core_ibex_reg_pkg_NumRegions; i = i + 1) begin : gen_ibus_region_cfgs
-			assign ibus_region_cfg[(i * 65) + 64] = reg2hw[295 + i+:1];
-			assign ibus_region_cfg[(i * 65) + 63-:32] = reg2hw[231 + (i * 32)+:32];
-			assign ibus_region_cfg[(i * 65) + 31-:32] = reg2hw[167 + (i * 32)+:32];
-		end
-		for (i = 0; i < rv_core_ibex_reg_pkg_NumRegions; i = i + 1) begin : gen_dbus_region_cfgs
-			assign dbus_region_cfg[(i * 65) + 64] = reg2hw[165 + i+:1];
-			assign dbus_region_cfg[(i * 65) + 63-:32] = reg2hw[101 + (i * 32)+:32];
-			assign dbus_region_cfg[(i * 65) + 31-:32] = reg2hw[37 + (i * 32)+:32];
-		end
-	endgenerate
-	assign fatal_intg_err = fatal_intg_event;
-	assign fatal_core_err = fatal_core_event;
-	assign recov_core_err = recov_core_event;
-	assign hw2reg[73] = 1'b1;
-	assign hw2reg[72] = intg_err;
-	assign hw2reg[71] = 1'b1;
-	assign hw2reg[70] = fatal_intg_err;
-	assign hw2reg[69] = 1'b1;
-	assign hw2reg[68] = fatal_core_err;
-	assign hw2reg[67] = 1'b1;
-	assign hw2reg[66] = recov_core_err;
-	wire [3:0] alert_test;
-	assign alert_test[0] = reg2hw[312] & reg2hw[311];
-	assign alert_test[1] = reg2hw[310] & reg2hw[309];
-	assign alert_test[2] = reg2hw[308] & reg2hw[307];
-	assign alert_test[3] = reg2hw[306] & reg2hw[305];
-	localparam [3:0] AlertFatal = 4'b0101;
-	wire [3:0] alert_events;
-	wire [3:0] alert_acks;
-	function automatic prim_mubi_pkg_mubi4_test_true_loose;
-		input reg [3:0] val;
-		prim_mubi_pkg_mubi4_test_true_loose = sv2v_cast_38B98(4'h9) != val;
-	endfunction
-	assign alert_events[0] = prim_mubi_pkg_mubi4_test_true_loose(sv2v_cast_38B98(reg2hw[300-:4]));
-	assign alert_events[1] = prim_mubi_pkg_mubi4_test_true_loose(sv2v_cast_38B98(reg2hw[304-:4]));
-	assign alert_events[2] = (intg_err | fatal_intg_err) | fatal_core_err;
-	assign alert_events[3] = recov_core_err;
-	wire unused_alert_acks;
-	assign unused_alert_acks = |alert_acks;
-	assign hw2reg[78] = alert_acks[1];
-	assign hw2reg[82-:4] = sv2v_cast_38B98(4'h9);
-	generate
-		for (i = 0; i < rv_core_ibex_reg_pkg_NumAlerts; i = i + 1) begin : gen_alert_senders
-			prim_alert_sender #(
-				.AsyncOn(AlertAsyncOn[0]),
-				.IsFatal(AlertFatal[i])
-			) u_alert_sender(
-				.clk_i(clk_i),
-				.rst_ni(rst_ni),
-				.alert_test_i(alert_test[i]),
-				.alert_req_i(alert_events[i]),
-				.alert_ack_o(alert_acks[i]),
-				.alert_rx_i(alert_rx_i[i * 4+:4]),
-				.alert_tx_o(alert_tx_o[i * 2+:2])
-			);
-		end
-	endgenerate
-	reg [31:0] rnd_data_q;
-	reg [31:0] rnd_data_d;
-	reg rnd_valid_q;
-	reg rnd_valid_d;
-	reg rnd_fips_q;
-	reg rnd_fips_d;
-	wire edn_req;
-	wire [31:0] edn_data;
-	wire edn_ack;
-	wire edn_fips;
-	always @(*) begin
-		rnd_valid_d = rnd_valid_q;
-		rnd_data_d = rnd_data_q;
-		rnd_fips_d = rnd_fips_q;
-		if (reg2hw[0]) begin
-			rnd_valid_d = 1'sb0;
-			rnd_data_d = 1'sb0;
-			rnd_fips_d = 1'sb0;
-		end
-		else if (edn_req && edn_ack) begin
-			rnd_valid_d = 1'b1;
-			rnd_data_d = edn_data;
-			rnd_fips_d = edn_fips;
-		end
-	end
-	always @(posedge clk_i or negedge rst_ni)
-		if (!rst_ni) begin
-			rnd_valid_q <= 1'sb0;
-			rnd_data_q <= 1'sb0;
-			rnd_fips_q <= 1'sb0;
-		end
-		else begin
-			rnd_valid_q <= rnd_valid_d;
-			rnd_data_q <= rnd_data_d;
-			rnd_fips_q <= rnd_fips_d;
-		end
-	assign edn_req = ~rnd_valid_q;
-	prim_edn_req #(.OutWidth(32)) u_edn_if(
-		.clk_i(clk_i),
-		.rst_ni(rst_ni),
-		.req_chk_i(1'b1),
-		.req_i(edn_req),
-		.ack_o(edn_ack),
-		.data_o(edn_data),
-		.fips_o(edn_fips),
-		.clk_edn_i(clk_edn_i),
-		.rst_edn_ni(rst_edn_ni),
-		.edn_o(edn_o),
-		.edn_i(edn_i)
-	);
-	assign hw2reg[65-:32] = rnd_data_q;
-	assign hw2reg[33] = rnd_valid_q;
-	assign hw2reg[32] = rnd_fips_q;
-	wire unused_reg2hw;
-	assign unused_reg2hw = |reg2hw[32-:32];
-	assign hw2reg[31-:32] = fpga_info_i;
-	localparam signed [31:0] TlH2DWidth = 1 * ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 24);
-	localparam signed [31:0] TlD2HWidth = 1 * ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + (tlul_pkg_D2HRspIntgWidth + tlul_pkg_DataIntgWidth)) + 2);
-	wire [TlH2DWidth - 1:0] tl_win_h2d_int;
-	wire [TlD2HWidth - 1:0] tl_win_d2h_int;
-	wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + (tlul_pkg_D2HRspIntgWidth + tlul_pkg_DataIntgWidth)) + 1:0] tl_win_d2h_err_rsp;
-	prim_buf #(.Width(TlH2DWidth)) u_tlul_req_buf(
-		.in_i(tl_win_h2d),
-		.out_o(tl_win_h2d_int)
-	);
-	prim_buf #(.Width(TlD2HWidth)) u_tlul_rsp_buf(
-		.in_i(tl_win_d2h_err_rsp),
-		.out_o(tl_win_d2h_int)
-	);
-	function automatic [((((((7 + top_pkg_TL_SZW) + (32'sd8 + 32'sd1)) + 32'sd32) + (32'sd7 + 32'sd7)) + 1) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + (tlul_pkg_D2HRspIntgWidth + tlul_pkg_DataIntgWidth)) + 2 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + (tlul_pkg_D2HRspIntgWidth + tlul_pkg_DataIntgWidth)) + 1)) - 1:0] sv2v_cast_51793;
-		input reg [((((((7 + top_pkg_TL_SZW) + (32'sd8 + 32'sd1)) + 32'sd32) + (32'sd7 + 32'sd7)) + 1) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + (tlul_pkg_D2HRspIntgWidth + tlul_pkg_DataIntgWidth)) + 2 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + (tlul_pkg_D2HRspIntgWidth + tlul_pkg_DataIntgWidth)) + 1)) - 1:0] inp;
-		sv2v_cast_51793 = inp;
-	endfunction
-	assign tl_win_d2h = sv2v_cast_51793(tl_win_d2h_int);
-	wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 23:0] tl_win_h2d_int_tmp;
-	function automatic [(((((7 + top_pkg_TL_SZW) + (32'sd8 + 32'sd32)) + top_pkg_TL_DBW) + 55) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 24 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 23)) - 1:0] sv2v_cast_E9713;
-		input reg [(((((7 + top_pkg_TL_SZW) + (32'sd8 + 32'sd32)) + top_pkg_TL_DBW) + 55) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 24 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 23)) - 1:0] inp;
-		sv2v_cast_E9713 = inp;
-	endfunction
-	assign tl_win_h2d_int_tmp = sv2v_cast_E9713(tl_win_h2d_int);
-	tlul_err_resp u_sim_win_rsp(
-		.clk_i(clk_i),
-		.rst_ni(rst_ni),
-		.tl_h_i(tl_win_h2d_int_tmp),
-		.tl_h_o(tl_win_d2h_err_rsp)
-	);
-endmodule
-module noerr_tlul_adapter_sram (
-	clk_i,
-	rst_ni,
-	tl_i,
-	tl_o,
-	en_ifetch_i,
-	req_o,
-	req_type_o,
-	gnt_i,
-	we_o,
-	addr_o,
-	wdata_o,
-	wmask_o,
-	intg_error_o,
-	rdata_i,
-	rvalid_i,
-	rerror_i
-);
-	parameter signed [31:0] SramAw = 12;
-	parameter signed [31:0] SramDw = 32;
-	parameter signed [31:0] Outstanding = 1;
-	parameter [0:0] ByteAccess = 1;
-	parameter [0:0] ErrOnWrite = 0;
-	parameter [0:0] ErrOnRead = 0;
-	parameter [0:0] CmdIntgCheck = 0;
-	parameter [0:0] EnableRspIntgGen = 0;
-	parameter [0:0] EnableDataIntgGen = 0;
-	parameter [0:0] EnableDataIntgPt = 0;
-	parameter [0:0] SecFifoPtr = 0;
-	localparam signed [31:0] top_pkg_TL_DW = 32;
-	localparam signed [31:0] WidthMult = SramDw / top_pkg_TL_DW;
-	localparam signed [31:0] tlul_pkg_DataIntgWidth = 7;
-	localparam signed [31:0] IntgWidth = tlul_pkg_DataIntgWidth * WidthMult;
-	localparam signed [31:0] DataOutW = (EnableDataIntgPt ? SramDw + IntgWidth : SramDw);
-	input clk_i;
-	input rst_ni;
-	localparam signed [31:0] prim_mubi_pkg_MuBi4Width = 4;
-	localparam signed [31:0] tlul_pkg_H2DCmdIntgWidth = 7;
-	localparam signed [31:0] top_pkg_TL_AIW = 8;
-	localparam signed [31:0] top_pkg_TL_AW = 32;
-	localparam signed [31:0] top_pkg_TL_DBW = top_pkg_TL_DW >> 3;
-	localparam signed [31:0] top_pkg_TL_SZW = $clog2($clog2(top_pkg_TL_DBW) + 1);
-	input wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 23:0] tl_i;
-	localparam signed [31:0] tlul_pkg_D2HRspIntgWidth = 7;
-	localparam signed [31:0] top_pkg_TL_DIW = 1;
-	output wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + (tlul_pkg_D2HRspIntgWidth + tlul_pkg_DataIntgWidth)) + 1:0] tl_o;
-	input wire [3:0] en_ifetch_i;
-	output wire req_o;
-	output wire [3:0] req_type_o;
-	input gnt_i;
-	output wire we_o;
-	output wire [SramAw - 1:0] addr_o;
-	output wire [DataOutW - 1:0] wdata_o;
-	output wire [DataOutW - 1:0] wmask_o;
-	output wire intg_error_o;
-	input [DataOutW - 1:0] rdata_i;
-	input rvalid_i;
-	input [1:0] rerror_i;
-	localparam signed [31:0] SramByte = SramDw / 8;
-	function automatic integer prim_util_pkg_vbits;
-		input integer value;
-		prim_util_pkg_vbits = (value == 1 ? 1 : $clog2(value));
-	endfunction
-	localparam signed [31:0] DataBitWidth = prim_util_pkg_vbits(SramByte);
-	localparam signed [31:0] WoffsetWidth = (SramByte == top_pkg_TL_DBW ? 1 : DataBitWidth - prim_util_pkg_vbits(top_pkg_TL_DBW));
-	wire error_det;
-	wire error_internal;
-	wire wr_attr_error;
-	wire instr_error;
-	wire wr_vld_error;
-	wire rd_vld_error;
-	wire rsp_fifo_error;
-	wire intg_error;
-	wire tlul_error;
-	generate
-		if (CmdIntgCheck) begin : gen_cmd_intg_check
-			tlul_cmd_intg_chk u_cmd_intg_chk(
-				.tl_i(tl_i),
-				.err_o(intg_error)
-			);
-		end
-		else begin : gen_no_cmd_intg_check
-			assign intg_error = 1'sb0;
-		end
-	endgenerate
-	reg intg_error_q;
-	always @(posedge clk_i or negedge rst_ni)
-		if (!rst_ni)
-			intg_error_q <= 1'sb0;
-		else if (intg_error || rsp_fifo_error)
-			intg_error_q <= 1'b1;
-	assign intg_error_o = (intg_error | rsp_fifo_error) | intg_error_q;
-	assign wr_attr_error = ((tl_i[6 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 55)))-:((6 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 55)))) >= (3 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 56)))) ? ((6 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 55)))) - (3 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 56))))) + 1 : ((3 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 56)))) - (6 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 55))))) + 1)] == 3'h0) || (tl_i[6 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 55)))-:((6 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 55)))) >= (3 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 56)))) ? ((6 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 55)))) - (3 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 56))))) + 1 : ((3 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 56)))) - (6 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 55))))) + 1)] == 3'h1) ? (ByteAccess == 0 ? (tl_i[top_pkg_TL_DBW + 55-:((top_pkg_TL_DBW + 55) >= 56 ? top_pkg_TL_DBW : 57 - (top_pkg_TL_DBW + 55))] != {((top_pkg_TL_DBW + 55) >= 56 ? top_pkg_TL_DBW : 57 - (top_pkg_TL_DBW + 55)) * 1 {1'sb1}}) || (tl_i[top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 55)))-:((top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 55))) >= ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 56)) ? ((top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 55)))) - (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 56)))) + 1 : ((top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 56))) - (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 55))))) + 1)] != 2'h2) : 1'b0) : 1'b0);
-	function automatic [3:0] sv2v_cast_A2CB9;
-		input reg [3:0] inp;
-		sv2v_cast_A2CB9 = inp;
-	endfunction
-	function automatic prim_mubi_pkg_mubi4_test_false_loose;
-		input reg [3:0] val;
-		prim_mubi_pkg_mubi4_test_false_loose = sv2v_cast_A2CB9(4'h6) != val;
-	endfunction
-	function automatic prim_mubi_pkg_mubi4_test_invalid;
-		input reg [3:0] val;
-		prim_mubi_pkg_mubi4_test_invalid = ~(|{((sv2v_cast_A2CB9(4'h6) ^ (val ^ val)) === (val ^ (sv2v_cast_A2CB9(4'h6) ^ sv2v_cast_A2CB9(4'h6)))) & ((((val ^ val) ^ (sv2v_cast_A2CB9(4'h6) ^ sv2v_cast_A2CB9(4'h6))) === (sv2v_cast_A2CB9(4'h6) ^ sv2v_cast_A2CB9(4'h6))) | 1'bx), ((sv2v_cast_A2CB9(4'h9) ^ (val ^ val)) === (val ^ (sv2v_cast_A2CB9(4'h9) ^ sv2v_cast_A2CB9(4'h9)))) & ((((val ^ val) ^ (sv2v_cast_A2CB9(4'h9) ^ sv2v_cast_A2CB9(4'h9))) === (sv2v_cast_A2CB9(4'h9) ^ sv2v_cast_A2CB9(4'h9))) | 1'bx)});
-	endfunction
-	function automatic prim_mubi_pkg_mubi4_test_true_strict;
-		input reg [3:0] val;
-		prim_mubi_pkg_mubi4_test_true_strict = sv2v_cast_A2CB9(4'h6) == val;
-	endfunction
-	assign instr_error = prim_mubi_pkg_mubi4_test_invalid(tl_i[18-:4]) | (prim_mubi_pkg_mubi4_test_true_strict(tl_i[18-:4]) & prim_mubi_pkg_mubi4_test_false_loose(en_ifetch_i));
-	generate
-		if (ErrOnWrite == 1) begin : gen_no_writes
-			assign wr_vld_error = tl_i[6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 55))))-:((6 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 55)))) >= (3 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 56)))) ? ((6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 55))))) - (3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 56)))))) + 1 : ((3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 56))))) - (6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 55)))))) + 1)] != 3'h4;
-		end
-		else begin : gen_writes_allowed
-			assign wr_vld_error = 1'b0;
-		end
-		if (ErrOnRead == 1) begin : gen_no_reads
-			assign rd_vld_error = tl_i[6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 55))))-:((6 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 55)))) >= (3 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 56)))) ? ((6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 55))))) - (3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 56)))))) + 1 : ((3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 56))))) - (6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 55)))))) + 1)] == 3'h4;
-		end
-		else begin : gen_reads_allowed
-			assign rd_vld_error = 1'b0;
-		end
-	endgenerate
-	tlul_err u_err(
-		.clk_i(clk_i),
-		.rst_ni(rst_ni),
-		.tl_i(tl_i),
-		.err_o(tlul_error)
-	);
-	assign error_det = ((((wr_attr_error | wr_vld_error) | rd_vld_error) | instr_error) | tlul_error) | intg_error;
-	wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 23:0] tl_i_int;
-	wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + (tlul_pkg_D2HRspIntgWidth + tlul_pkg_DataIntgWidth)) + 1:0] tl_o_int;
-	wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + (tlul_pkg_D2HRspIntgWidth + tlul_pkg_DataIntgWidth)) + 1:0] tl_out;
-	wire unused_tl_i_int;
-	assign unused_tl_i_int = ^tl_i_int;
-	tlul_rsp_intg_gen #(
-		.EnableRspIntgGen(EnableRspIntgGen),
-		.EnableDataIntgGen(EnableDataIntgGen)
-	) u_rsp_gen(
-		.tl_i(tl_out),
-		.tl_o(tl_o)
-	);
-	assign error_internal = 0;
-	tlul_sram_byte #(
-		.EnableIntg((ByteAccess & EnableDataIntgPt) & !ErrOnWrite),
-		.Outstanding(Outstanding)
-	) u_sram_byte(
-		.clk_i(clk_i),
-		.rst_ni(rst_ni),
-		.tl_i(tl_i),
-		.tl_o(tl_out),
-		.tl_sram_o(tl_i_int),
-		.tl_sram_i(tl_o_int),
-		.error_i(error_det)
-	);
-	localparam signed [31:0] SramReqFifoWidth = top_pkg_TL_DBW + WoffsetWidth;
-	localparam signed [31:0] ReqFifoWidth = (7 + top_pkg_TL_SZW) + top_pkg_TL_AIW;
-	localparam signed [31:0] RspFifoWidth = (((top_pkg_TL_DW + tlul_pkg_DataIntgWidth) + 0) >= 0 ? (top_pkg_TL_DW + tlul_pkg_DataIntgWidth) + 1 : 1 - ((top_pkg_TL_DW + tlul_pkg_DataIntgWidth) + 0));
-	wire reqfifo_wvalid;
-	wire reqfifo_wready;
-	wire reqfifo_rvalid;
-	wire reqfifo_rready;
-	wire [((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) - 1:0] reqfifo_wdata;
-	wire [((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) - 1:0] reqfifo_rdata;
-	wire sramreqfifo_wvalid;
-	wire sramreqfifo_wready;
-	wire sramreqfifo_rready;
-	wire [(top_pkg_TL_DBW + WoffsetWidth) - 1:0] sramreqfifo_wdata;
-	wire [(top_pkg_TL_DBW + WoffsetWidth) - 1:0] sramreqfifo_rdata;
-	wire rspfifo_wvalid;
-	wire rspfifo_wready;
-	wire rspfifo_rvalid;
-	wire rspfifo_rready;
-	wire [(top_pkg_TL_DW + tlul_pkg_DataIntgWidth) + 0:0] rspfifo_wdata;
-	wire [(top_pkg_TL_DW + tlul_pkg_DataIntgWidth) + 0:0] rspfifo_rdata;
-	wire a_ack;
-	wire d_ack;
-	wire sram_ack;
-	assign a_ack = tl_i_int[7 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 55))))] & tl_o_int[0];
-	assign d_ack = tl_o_int[7 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + ((tlul_pkg_D2HRspIntgWidth + tlul_pkg_DataIntgWidth) + 1)))))] & tl_i_int[0];
-	assign sram_ack = req_o & gnt_i;
-	reg d_valid;
-	reg d_error;
-	always @(*) begin
-		d_valid = 1'b0;
-		if (reqfifo_rvalid) begin
-			if (reqfifo_rdata[1 + (prim_mubi_pkg_MuBi4Width + (top_pkg_TL_SZW + 7))])
-				d_valid = 1'b1;
-			else if (reqfifo_rdata[3 + (prim_mubi_pkg_MuBi4Width + (top_pkg_TL_SZW + 7))-:((7 + (top_pkg_TL_SZW + 7)) >= (5 + (top_pkg_TL_SZW + 8)) ? ((3 + (prim_mubi_pkg_MuBi4Width + (top_pkg_TL_SZW + 7))) - (1 + (prim_mubi_pkg_MuBi4Width + (top_pkg_TL_SZW + 8)))) + 1 : ((1 + (prim_mubi_pkg_MuBi4Width + (top_pkg_TL_SZW + 8))) - (3 + (prim_mubi_pkg_MuBi4Width + (top_pkg_TL_SZW + 7)))) + 1)] == 2'd1)
-				d_valid = rspfifo_rvalid;
-			else
-				d_valid = 1'b1;
-		end
-		else
-			d_valid = 1'b0;
-	end
-	always @(*) begin
-		d_error = 1'b0;
-		if (reqfifo_rvalid) begin
-			if (reqfifo_rdata[3 + (prim_mubi_pkg_MuBi4Width + (top_pkg_TL_SZW + 7))-:((7 + (top_pkg_TL_SZW + 7)) >= (5 + (top_pkg_TL_SZW + 8)) ? ((3 + (prim_mubi_pkg_MuBi4Width + (top_pkg_TL_SZW + 7))) - (1 + (prim_mubi_pkg_MuBi4Width + (top_pkg_TL_SZW + 8)))) + 1 : ((1 + (prim_mubi_pkg_MuBi4Width + (top_pkg_TL_SZW + 8))) - (3 + (prim_mubi_pkg_MuBi4Width + (top_pkg_TL_SZW + 7)))) + 1)] == 2'd1)
-				d_error = rspfifo_rdata[0] | reqfifo_rdata[1 + (prim_mubi_pkg_MuBi4Width + (top_pkg_TL_SZW + 7))];
-			else
-				d_error = reqfifo_rdata[1 + (prim_mubi_pkg_MuBi4Width + (top_pkg_TL_SZW + 7))];
-		end
-		else
-			d_error = 1'b0;
-	end
-	wire vld_rd_rsp;
-	assign vld_rd_rsp = ((d_valid & reqfifo_rvalid) & rspfifo_rvalid) & (reqfifo_rdata[3 + (prim_mubi_pkg_MuBi4Width + (top_pkg_TL_SZW + 7))-:((7 + (top_pkg_TL_SZW + 7)) >= (5 + (top_pkg_TL_SZW + 8)) ? ((3 + (prim_mubi_pkg_MuBi4Width + (top_pkg_TL_SZW + 7))) - (1 + (prim_mubi_pkg_MuBi4Width + (top_pkg_TL_SZW + 8)))) + 1 : ((1 + (prim_mubi_pkg_MuBi4Width + (top_pkg_TL_SZW + 8))) - (3 + (prim_mubi_pkg_MuBi4Width + (top_pkg_TL_SZW + 7)))) + 1)] == 2'd1);
-	wire [31:0] error_blanking_data;
-	localparam [31:0] tlul_pkg_DataWhenError = {top_pkg_TL_DW {1'b1}};
-	localparam [31:0] tlul_pkg_DataWhenInstrError = 1'sb0;
-	assign error_blanking_data = (prim_mubi_pkg_mubi4_test_true_strict(reqfifo_rdata[prim_mubi_pkg_MuBi4Width + (top_pkg_TL_SZW + 7)-:((prim_mubi_pkg_MuBi4Width + (top_pkg_TL_SZW + 7)) >= (top_pkg_TL_SZW + 8) ? ((prim_mubi_pkg_MuBi4Width + (top_pkg_TL_SZW + 7)) - (top_pkg_TL_SZW + 8)) + 1 : ((top_pkg_TL_SZW + 8) - (prim_mubi_pkg_MuBi4Width + (top_pkg_TL_SZW + 7))) + 1)]) ? tlul_pkg_DataWhenInstrError : tlul_pkg_DataWhenError);
-	wire [31:0] unused_instr;
-	wire [31:0] unused_data;
-	wire [6:0] error_instr_integ;
-	wire [6:0] error_data_integ;
-	localparam signed [31:0] tlul_pkg_DataMaxWidth = 32;
-	function automatic [31:0] sv2v_cast_32;
-		input reg [31:0] inp;
-		sv2v_cast_32 = inp;
-	endfunction
-	tlul_data_integ_enc u_tlul_data_integ_enc_instr(
-		.data_i(sv2v_cast_32(tlul_pkg_DataWhenInstrError)),
-		.data_intg_o({error_instr_integ, unused_instr})
-	);
-	tlul_data_integ_enc u_tlul_data_integ_enc_data(
-		.data_i(sv2v_cast_32(tlul_pkg_DataWhenError)),
-		.data_intg_o({error_data_integ, unused_data})
-	);
-	wire [6:0] error_blanking_integ;
-	assign error_blanking_integ = (prim_mubi_pkg_mubi4_test_true_strict(reqfifo_rdata[prim_mubi_pkg_MuBi4Width + (top_pkg_TL_SZW + 7)-:((prim_mubi_pkg_MuBi4Width + (top_pkg_TL_SZW + 7)) >= (top_pkg_TL_SZW + 8) ? ((prim_mubi_pkg_MuBi4Width + (top_pkg_TL_SZW + 7)) - (top_pkg_TL_SZW + 8)) + 1 : ((top_pkg_TL_SZW + 8) - (prim_mubi_pkg_MuBi4Width + (top_pkg_TL_SZW + 7))) + 1)]) ? error_instr_integ : error_data_integ);
-	wire [31:0] d_data;
-	assign d_data = (vld_rd_rsp & ~d_error ? rspfifo_rdata[39-:32] : error_blanking_data);
-	wire [6:0] data_intg;
-	localparam [6:0] prim_secded_pkg_SecdedInv3932ZeroEcc = 7'h2a;
-	assign data_intg = (vld_rd_rsp && reqfifo_rdata[5 + (top_pkg_TL_SZW + 7)] ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata[7-:7] : prim_secded_pkg_SecdedInv3932ZeroEcc));
-	function automatic [6:0] sv2v_cast_5F39A;
-		input reg [6:0] inp;
-		sv2v_cast_5F39A = inp;
-	endfunction
-	function automatic [top_pkg_TL_SZW - 1:0] sv2v_cast_4660A;
-		input reg [top_pkg_TL_SZW - 1:0] inp;
-		sv2v_cast_4660A = inp;
-	endfunction
-	function automatic [7:0] sv2v_cast_964CB;
-		input reg [7:0] inp;
-		sv2v_cast_964CB = inp;
-	endfunction
-	function automatic [0:0] sv2v_cast_702AC;
-		input reg [0:0] inp;
-		sv2v_cast_702AC = inp;
-	endfunction
-	function automatic [31:0] sv2v_cast_35AE2;
-		input reg [31:0] inp;
-		sv2v_cast_35AE2 = inp;
-	endfunction
-	function automatic [(tlul_pkg_D2HRspIntgWidth + tlul_pkg_DataIntgWidth) - 1:0] sv2v_cast_1D31F;
-		input reg [(tlul_pkg_D2HRspIntgWidth + tlul_pkg_DataIntgWidth) - 1:0] inp;
-		sv2v_cast_1D31F = inp;
-	endfunction
-	assign tl_o_int = {d_valid, (d_valid && (reqfifo_rdata[7 + (top_pkg_TL_SZW + 7)-:((7 + (top_pkg_TL_SZW + 7)) >= (5 + (top_pkg_TL_SZW + 8)) ? ((7 + (top_pkg_TL_SZW + 7)) - (5 + (top_pkg_TL_SZW + 8))) + 1 : ((5 + (top_pkg_TL_SZW + 8)) - (7 + (top_pkg_TL_SZW + 7))) + 1)] != 2'd1) ? 3'h0 : 3'h1), 3'b000, sv2v_cast_4660A((d_valid ? reqfifo_rdata[top_pkg_TL_SZW + 7-:((top_pkg_TL_SZW + 7) >= 8 ? top_pkg_TL_SZW : 9 - (top_pkg_TL_SZW + 7))] : {((top_pkg_TL_SZW + 7) >= 8 ? top_pkg_TL_SZW : 9 - (top_pkg_TL_SZW + 7)) * 1 {1'sb0}})), sv2v_cast_964CB((d_valid ? reqfifo_rdata[7-:top_pkg_TL_AIW] : {8 {1'sb0}})), sv2v_cast_702AC(1'b0), sv2v_cast_35AE2(d_data), sv2v_cast_1D31F({sv2v_cast_5F39A(1'sb0), data_intg}), d_valid && d_error, ((gnt_i | error_internal) & reqfifo_wready) & sramreqfifo_wready};
-	assign req_o = (tl_i_int[7 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 55))))] & reqfifo_wready) & ~error_internal;
-	assign req_type_o = tl_i_int[18-:4];
-	assign we_o = tl_i_int[7 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 55))))] & |{tl_i_int[6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 55))))-:((6 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 55)))) >= (3 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 56)))) ? ((6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 55))))) - (3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 56)))))) + 1 : ((3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 56))))) - (6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 55)))))) + 1)] == 3'h0, tl_i_int[6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 55))))-:((6 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 55)))) >= (3 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 56)))) ? ((6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 55))))) - (3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 56)))))) + 1 : ((3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 56))))) - (6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 55)))))) + 1)] == 3'h1};
-	assign addr_o = (tl_i_int[7 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 55)))] ? tl_i_int[(top_pkg_TL_AW + (top_pkg_TL_DBW + 55)) - (31 - DataBitWidth)+:SramAw] : {SramAw {1'sb0}});
-	wire [WoffsetWidth - 1:0] woffset;
-	generate
-		if (top_pkg_TL_DW != SramDw) begin : gen_wordwidthadapt
-			assign woffset = tl_i_int[(top_pkg_TL_AW + (top_pkg_TL_DBW + 55)) - (32 - DataBitWidth):(top_pkg_TL_AW + (top_pkg_TL_DBW + 55)) - (31 - prim_util_pkg_vbits(top_pkg_TL_DBW))];
-		end
-		else begin : gen_no_wordwidthadapt
-			assign woffset = 1'sb0;
-		end
-	endgenerate
-	localparam signed [31:0] DataWidth = (EnableDataIntgPt ? top_pkg_TL_DW + tlul_pkg_DataIntgWidth : top_pkg_TL_DW);
-	wire [(WidthMult * DataWidth) - 1:0] wmask_combined;
-	wire [(WidthMult * DataWidth) - 1:0] wdata_combined;
-	reg [(WidthMult * top_pkg_TL_DW) - 1:0] wmask_int;
-	reg [(WidthMult * top_pkg_TL_DW) - 1:0] wdata_int;
-	reg [(WidthMult * tlul_pkg_DataIntgWidth) - 1:0] wmask_intg;
-	reg [(WidthMult * tlul_pkg_DataIntgWidth) - 1:0] wdata_intg;
-	always @(*) begin
-		wmask_int = 1'sb0;
-		wdata_int = 1'sb0;
-		if (tl_i_int[7 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 55))))]) begin : sv2v_autoblock_1
-			reg signed [31:0] i;
-			for (i = 0; i < 4; i = i + 1)
-				begin
-					wmask_int[(woffset * top_pkg_TL_DW) + (8 * i)+:8] = {8 {tl_i_int[(top_pkg_TL_DBW + 55) - ((top_pkg_TL_DBW - 1) - i)]}};
-					wdata_int[(woffset * top_pkg_TL_DW) + (8 * i)+:8] = (tl_i_int[(top_pkg_TL_DBW + 55) - ((top_pkg_TL_DBW - 1) - i)] && we_o ? tl_i_int[24 + (8 * i)+:8] : {8 {1'sb0}});
-				end
-		end
-	end
-	always @(*) begin
-		wmask_intg = 1'sb0;
-		wdata_intg = 1'sb0;
-		if (tl_i_int[7 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 55))))]) begin
-			wmask_intg[woffset * tlul_pkg_DataIntgWidth+:tlul_pkg_DataIntgWidth] = {tlul_pkg_DataIntgWidth {1'b1}};
-			wdata_intg[woffset * tlul_pkg_DataIntgWidth+:tlul_pkg_DataIntgWidth] = tl_i_int[7-:tlul_pkg_DataIntgWidth];
-		end
-	end
-	genvar i;
-	generate
-		for (i = 0; i < WidthMult; i = i + 1) begin : gen_write_output
-			if (EnableDataIntgPt) begin : gen_combined_output
-				assign wmask_combined[i * DataWidth+:DataWidth] = {wmask_intg[i * tlul_pkg_DataIntgWidth+:tlul_pkg_DataIntgWidth], wmask_int[i * top_pkg_TL_DW+:top_pkg_TL_DW]};
-				assign wdata_combined[i * DataWidth+:DataWidth] = {wdata_intg[i * tlul_pkg_DataIntgWidth+:tlul_pkg_DataIntgWidth], wdata_int[i * top_pkg_TL_DW+:top_pkg_TL_DW]};
-			end
-			else begin : gen_ft_output
-				wire unused_w;
-				assign wmask_combined[i * DataWidth+:DataWidth] = wmask_int[i * top_pkg_TL_DW+:top_pkg_TL_DW];
-				assign wdata_combined[i * DataWidth+:DataWidth] = wdata_int[i * top_pkg_TL_DW+:top_pkg_TL_DW];
-				assign unused_w = |wmask_intg & |wdata_intg;
-			end
-		end
-	endgenerate
-	assign wmask_o = wmask_combined;
-	assign wdata_o = wdata_combined;
-	assign reqfifo_wvalid = a_ack;
-	assign reqfifo_wdata = {(tl_i_int[6 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 55)))-:((6 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 55)))) >= (3 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 56)))) ? ((6 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 55)))) - (3 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 56))))) + 1 : ((3 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 56)))) - (6 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 55))))) + 1)] != 3'h4 ? 2'd0 : 2'd1), error_internal, sv2v_cast_A2CB9(tl_i_int[18-:4]), tl_i_int[top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 55)))-:((top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 55))) >= ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 56)) ? ((top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 55)))) - (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 56)))) + 1 : ((top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 56))) - (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 55))))) + 1)], tl_i_int[top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 55))-:(((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 55)) >= (32'sd32 + (top_pkg_TL_DBW + 56)) ? ((top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 55))) - (top_pkg_TL_AW + (top_pkg_TL_DBW + 56))) + 1 : ((top_pkg_TL_AW + (top_pkg_TL_DBW + 56)) - (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 55)))) + 1)]};
-	assign reqfifo_rready = d_ack;
-	assign sramreqfifo_wdata = {tl_i_int[top_pkg_TL_DBW + 55-:((top_pkg_TL_DBW + 55) >= 56 ? top_pkg_TL_DBW : 57 - (top_pkg_TL_DBW + 55))], woffset};
-	assign sramreqfifo_wvalid = sram_ack & ~we_o;
-	assign sramreqfifo_rready = rspfifo_wvalid;
-	assign rspfifo_wvalid = rvalid_i & reqfifo_rvalid;
-	wire [(WidthMult * DataWidth) - 1:0] rdata_reshaped;
-	reg [DataWidth - 1:0] rdata_tlword;
-	assign rdata_reshaped = rdata_i;
-	localparam [38:0] prim_secded_pkg_SecdedInv3932ZeroWord = 39'h2a00000000;
-	generate
-		if (EnableDataIntgPt) begin : gen_no_rmask
-			always @(*) begin
-				rdata_tlword = prim_secded_pkg_SecdedInv3932ZeroWord;
-				if (|sramreqfifo_rdata[top_pkg_TL_DBW + (WoffsetWidth - 1)-:((top_pkg_TL_DBW + (WoffsetWidth - 1)) >= (WoffsetWidth + 0) ? ((top_pkg_TL_DBW + (WoffsetWidth - 1)) - (WoffsetWidth + 0)) + 1 : ((WoffsetWidth + 0) - (top_pkg_TL_DBW + (WoffsetWidth - 1))) + 1)])
-					rdata_tlword = rdata_reshaped[sramreqfifo_rdata[WoffsetWidth - 1-:WoffsetWidth] * DataWidth+:DataWidth];
-			end
-		end
-		else begin : gen_rmask
-			reg [DataWidth - 1:0] rmask;
-			always @(*) begin
-				rmask = 1'sb0;
-				begin : sv2v_autoblock_2
-					reg signed [31:0] i;
-					for (i = 0; i < 4; i = i + 1)
-						rmask[8 * i+:8] = {8 {sramreqfifo_rdata[(top_pkg_TL_DBW + (WoffsetWidth - 1)) - ((top_pkg_TL_DBW - 1) - i)]}};
-				end
-			end
-			wire [DataWidth:1] sv2v_tmp_037A0;
-			assign sv2v_tmp_037A0 = rdata_reshaped[sramreqfifo_rdata[WoffsetWidth - 1-:WoffsetWidth] * DataWidth+:DataWidth] & rmask;
-			always @(*) rdata_tlword = sv2v_tmp_037A0;
-		end
-	endgenerate
-	function automatic [6:0] sv2v_cast_8DC45;
-		input reg [6:0] inp;
-		sv2v_cast_8DC45 = inp;
-	endfunction
-	assign rspfifo_wdata = {sv2v_cast_35AE2(rdata_tlword[31:0]), sv2v_cast_8DC45((EnableDataIntgPt ? rdata_tlword[DataWidth - 1-:tlul_pkg_DataIntgWidth] : {7 {1'sb0}})), rerror_i[1]};
-	assign rspfifo_rready = ((reqfifo_rdata[7 + (top_pkg_TL_SZW + 7)-:((7 + (top_pkg_TL_SZW + 7)) >= (5 + (top_pkg_TL_SZW + 8)) ? ((7 + (top_pkg_TL_SZW + 7)) - (5 + (top_pkg_TL_SZW + 8))) + 1 : ((5 + (top_pkg_TL_SZW + 8)) - (7 + (top_pkg_TL_SZW + 7))) + 1)] == 2'd1) & ~reqfifo_rdata[5 + (top_pkg_TL_SZW + 7)] ? reqfifo_rready : 1'b0);
-	wire unused_rerror;
-	assign unused_rerror = rerror_i[0];
-	prim_fifo_sync #(
-		.Width(ReqFifoWidth),
-		.Pass(1'b0),
-		.Depth(Outstanding)
-	) u_reqfifo(
-		.clk_i(clk_i),
-		.rst_ni(rst_ni),
-		.clr_i(1'b0),
-		.wvalid_i(reqfifo_wvalid),
-		.wready_o(reqfifo_wready),
-		.wdata_i(reqfifo_wdata),
-		.rvalid_o(reqfifo_rvalid),
-		.rready_i(reqfifo_rready),
-		.rdata_o(reqfifo_rdata)
-	);
-	prim_fifo_sync #(
-		.Width(SramReqFifoWidth),
-		.Pass(1'b0),
-		.Depth(Outstanding)
-	) u_sramreqfifo(
-		.clk_i(clk_i),
-		.rst_ni(rst_ni),
-		.clr_i(1'b0),
-		.wvalid_i(sramreqfifo_wvalid),
-		.wready_o(sramreqfifo_wready),
-		.wdata_i(sramreqfifo_wdata),
-		.rready_i(sramreqfifo_rready),
-		.rdata_o(sramreqfifo_rdata)
-	);
-	prim_fifo_sync #(
-		.Width(RspFifoWidth),
-		.Pass(1'b1),
-		.Depth(Outstanding),
-		.Secure(SecFifoPtr)
-	) u_rspfifo(
-		.clk_i(clk_i),
-		.rst_ni(rst_ni),
-		.clr_i(1'b0),
-		.wvalid_i(rspfifo_wvalid),
-		.wready_o(rspfifo_wready),
-		.wdata_i(rspfifo_wdata),
-		.rvalid_o(rspfifo_rvalid),
-		.rready_i(rspfifo_rready),
-		.rdata_o(rspfifo_rdata),
-		.err_o(rsp_fifo_error)
-	);
-endmodule
+
 module prim_alert_receiver (
 	clk_i,
 	rst_ni,
diff --git a/cpus/ibex_small_pr2166_pregenerated/cellift/generated/sv2v_out.v b/cpus/ibex_small_pr2166_pregenerated/cellift/generated/sv2v_out.v
index 344ea61c..61f03c22 100644
--- a/cpus/ibex_small_pr2166_pregenerated/cellift/generated/sv2v_out.v
+++ b/cpus/ibex_small_pr2166_pregenerated/cellift/generated/sv2v_out.v
@@ -10960,263 +10960,7 @@ module alert_handler_reg_top (
 	assign unused_wdata = ^reg_wdata;
 	assign unused_be = ^reg_be;
 endmodule
-module cellift_rv_core_ibex_mem_top (
-	clk_i,
-	rst_ni,
-	clk_edn_i,
-	rst_edn_ni,
-	clk_esc_i,
-	rst_esc_ni,
-	rst_cpu_n_o,
-	ram_cfg_i,
-	hart_id_i,
-	boot_addr_i,
-	instr_mem_req_o,
-	instr_mem_gnt_i,
-	instr_mem_addr_o,
-	instr_mem_wdata_o,
-	instr_mem_strb_o,
-	instr_mem_we_o,
-	instr_mem_rdata_i,
-	data_mem_req_o,
-	data_mem_gnt_i,
-	data_mem_addr_o,
-	data_mem_wdata_o,
-	data_mem_strb_o,
-	data_mem_we_o,
-	data_mem_rdata_i,
-	irq_software_i,
-	irq_timer_i,
-	irq_external_i,
-	esc_tx_i,
-	esc_rx_o,
-	nmi_wdog_i,
-	debug_req_i,
-	crash_dump_o,
-	pwrmgr_cpu_en_i,
-	lc_cpu_en_i,
-	pwrmgr_o,
-	scan_rst_ni,
-	scanmode_i,
-	cfg_tl_d_i,
-	cfg_tl_d_o,
-	edn_o,
-	edn_i,
-	clk_otp_i,
-	rst_otp_ni,
-	icache_otp_key_o,
-	icache_otp_key_i,
-	fpga_info_i,
-	alert_rx_i,
-	alert_tx_o
-);
-	parameter [31:0] InstrMemAw = 20;
-	parameter [31:0] DataMemAw = 20;
-	input wire clk_i;
-	input wire rst_ni;
-	input wire clk_edn_i;
-	input wire rst_edn_ni;
-	input wire clk_esc_i;
-	input wire rst_esc_ni;
-	output wire rst_cpu_n_o;
-	input wire [9:0] ram_cfg_i;
-	input wire [31:0] hart_id_i;
-	input wire [31:0] boot_addr_i;
-	output wire instr_mem_req_o;
-	input wire instr_mem_gnt_i;
-	output wire [InstrMemAw:0] instr_mem_addr_o;
-	output wire [31:0] instr_mem_wdata_o;
-	output wire [31:0] instr_mem_strb_o;
-	output wire instr_mem_we_o;
-	input wire [31:0] instr_mem_rdata_i;
-	output wire data_mem_req_o;
-	input wire data_mem_gnt_i;
-	output wire [InstrMemAw:0] data_mem_addr_o;
-	output wire [31:0] data_mem_wdata_o;
-	output wire [31:0] data_mem_strb_o;
-	output wire data_mem_we_o;
-	input wire [31:0] data_mem_rdata_i;
-	input wire irq_software_i;
-	input wire irq_timer_i;
-	input wire irq_external_i;
-	input wire [1:0] esc_tx_i;
-	output wire [1:0] esc_rx_o;
-	input wire nmi_wdog_i;
-	input wire debug_req_i;
-	output wire [159:0] crash_dump_o;
-	localparam signed [31:0] lc_ctrl_pkg_TxWidth = 4;
-	input wire [3:0] pwrmgr_cpu_en_i;
-	input wire [3:0] lc_cpu_en_i;
-	output wire [0:0] pwrmgr_o;
-	input scan_rst_ni;
-	localparam signed [31:0] prim_mubi_pkg_MuBi4Width = 4;
-	input wire [3:0] scanmode_i;
-	localparam signed [31:0] tlul_pkg_DataIntgWidth = 7;
-	localparam signed [31:0] tlul_pkg_H2DCmdIntgWidth = 7;
-	localparam signed [31:0] top_pkg_TL_AIW = 8;
-	localparam signed [31:0] top_pkg_TL_AW = 32;
-	localparam signed [31:0] top_pkg_TL_DW = 32;
-	localparam signed [31:0] top_pkg_TL_DBW = top_pkg_TL_DW >> 3;
-	localparam signed [31:0] top_pkg_TL_SZW = $clog2($clog2(top_pkg_TL_DBW) + 1);
-	input wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 23:0] cfg_tl_d_i;
-	localparam signed [31:0] tlul_pkg_D2HRspIntgWidth = 7;
-	localparam signed [31:0] top_pkg_TL_DIW = 1;
-	output wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + (tlul_pkg_D2HRspIntgWidth + tlul_pkg_DataIntgWidth)) + 1:0] cfg_tl_d_o;
-	output wire [0:0] edn_o;
-	localparam [31:0] edn_pkg_ENDPOINT_BUS_WIDTH = 32;
-	input wire [33:0] edn_i;
-	input clk_otp_i;
-	input rst_otp_ni;
-	output wire [0:0] icache_otp_key_o;
-	localparam signed [31:0] otp_ctrl_pkg_SramKeyWidth = 128;
-	localparam signed [31:0] otp_ctrl_pkg_SramNonceWidth = 128;
-	input wire [257:0] icache_otp_key_i;
-	input [31:0] fpga_info_i;
-	localparam signed [31:0] rv_core_ibex_reg_pkg_NumAlerts = 4;
-	input wire [15:0] alert_rx_i;
-	output wire [7:0] alert_tx_o;
-	wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + (tlul_pkg_D2HRspIntgWidth + tlul_pkg_DataIntgWidth)) + 1:0] tl_i_toibex;
-	wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 23:0] tl_i_fromibex;
-	wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + (tlul_pkg_D2HRspIntgWidth + tlul_pkg_DataIntgWidth)) + 1:0] tl_d_toibex;
-	wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 23:0] tl_d_fromibex;
-	wire instr_rvalid_d;
-	reg instr_rvalid_q;
-	wire data_rvalid_d;
-	reg data_rvalid_q;
-	assign instr_rvalid_d = instr_mem_req_o & ~instr_mem_we_o;
-	assign data_rvalid_d = data_mem_req_o & ~data_mem_we_o;
-	always @(posedge clk_i)
-		if (~rst_ni) begin
-			instr_rvalid_q <= 1'sb0;
-			data_rvalid_q <= 1'sb0;
-		end
-		else begin
-			instr_rvalid_q <= instr_rvalid_d;
-			data_rvalid_q <= data_rvalid_d;
-		end
-	function automatic [3:0] sv2v_cast_AC3DB;
-		input reg [3:0] inp;
-		sv2v_cast_AC3DB = inp;
-	endfunction
-	noerr_tlul_adapter_sram #(
-		.SramAw(InstrMemAw),
-		.SramDw(32),
-		.Outstanding(1),
-		.ByteAccess(1),
-		.ErrOnWrite(0),
-		.ErrOnRead(0),
-		.CmdIntgCheck(0),
-		.EnableRspIntgGen(0),
-		.EnableDataIntgGen(0),
-		.EnableDataIntgPt(0)
-	) i_instr_tlul_adapter_sram(
-		.clk_i(clk_i),
-		.rst_ni(rst_ni),
-		.tl_i(tl_i_fromibex),
-		.tl_o(tl_i_toibex),
-		.en_ifetch_i(sv2v_cast_AC3DB(4'h6)),
-		.req_o(instr_mem_req_o),
-		.gnt_i(instr_mem_gnt_i),
-		.we_o(instr_mem_we_o),
-		.addr_o(instr_mem_addr_o),
-		.wdata_o(instr_mem_wdata_o),
-		.wmask_o(instr_mem_strb_o),
-		.rdata_i(instr_mem_rdata_i),
-		.rvalid_i(instr_rvalid_q),
-		.rerror_i(2'b00)
-	);
-	noerr_tlul_adapter_sram #(
-		.SramAw(DataMemAw),
-		.SramDw(32),
-		.Outstanding(1),
-		.ByteAccess(1),
-		.ErrOnWrite(0),
-		.ErrOnRead(0),
-		.CmdIntgCheck(0),
-		.EnableRspIntgGen(0),
-		.EnableDataIntgGen(0),
-		.EnableDataIntgPt(0)
-	) i_data_tlul_adapter_sram(
-		.clk_i(clk_i),
-		.rst_ni(rst_ni),
-		.tl_i(tl_d_fromibex),
-		.tl_o(tl_d_toibex),
-		.en_ifetch_i(sv2v_cast_AC3DB(4'h6)),
-		.req_o(data_mem_req_o),
-		.gnt_i(data_mem_gnt_i),
-		.we_o(data_mem_we_o),
-		.addr_o(data_mem_addr_o),
-		.wdata_o(data_mem_wdata_o),
-		.wmask_o(data_mem_strb_o),
-		.rdata_i(data_mem_rdata_i),
-		.rvalid_i(data_rvalid_q),
-		.rerror_i(2'b00)
-	);
-	localparam signed [31:0] ibex_pkg_LfsrWidth = 32;
-	localparam [159:0] ibex_pkg_RndCnstLfsrPermDefault = 160'h1e35ecba467fd1b12e958152c04fa43878a8daed;
-	localparam [31:0] ibex_pkg_RndCnstLfsrSeedDefault = 32'hac533bf4;
-	noerr_rv_core_ibex #(
-		.PMPEnable(1'b0),
-		.PMPGranularity(0),
-		.PMPNumRegions(4),
-		.MHPMCounterNum(0),
-		.MHPMCounterWidth(40),
-		.RV32E(1'b0),
-		.RV32M(32'sd1),
-		.RV32B(32'sd0),
-		.BranchTargetALU(1'b0),
-		.WritebackStage(1'b1),
-		.ICache(1'b0),
-		.ICacheECC(1'b0),
-		.BranchPredictor(1'b0),
-		.DbgTriggerEn(1'b0),
-		.DbgHwBreakNum(1),
-		.RndCnstLfsrSeed(ibex_pkg_RndCnstLfsrSeedDefault),
-		.RndCnstLfsrPerm(ibex_pkg_RndCnstLfsrPermDefault),
-		.SecureIbex(1'b0),
-		.DmHaltAddr(32'h1a110800),
-		.DmExceptionAddr(32'h01a11080)
-	) i_rv_core_ibex(
-		.clk_i(clk_i),
-		.rst_ni(rst_ni),
-		.clk_edn_i(clk_edn_i),
-		.rst_edn_ni(rst_edn_ni),
-		.clk_esc_i(clk_esc_i),
-		.rst_esc_ni(rst_esc_ni),
-		.rst_cpu_n_o(rst_cpu_n_o),
-		.ram_cfg_i(ram_cfg_i),
-		.hart_id_i(hart_id_i),
-		.boot_addr_i(boot_addr_i),
-		.corei_tl_h_o(tl_i_fromibex),
-		.corei_tl_h_i(tl_i_toibex),
-		.cored_tl_h_o(tl_d_fromibex),
-		.cored_tl_h_i(tl_d_toibex),
-		.irq_software_i(irq_software_i),
-		.irq_timer_i(irq_timer_i),
-		.irq_external_i(irq_external_i),
-		.esc_tx_i(esc_tx_i),
-		.esc_rx_o(esc_rx_o),
-		.nmi_wdog_i(nmi_wdog_i),
-		.debug_req_i(debug_req_i),
-		.crash_dump_o(crash_dump_o),
-		.lc_cpu_en_i(lc_cpu_en_i),
-		.pwrmgr_cpu_en_i(pwrmgr_cpu_en_i),
-		.pwrmgr_o(pwrmgr_o),
-		.scan_rst_ni(scan_rst_ni),
-		.scanmode_i(scanmode_i),
-		.cfg_tl_d_i(cfg_tl_d_i),
-		.cfg_tl_d_o(cfg_tl_d_o),
-		.edn_o(edn_o),
-		.edn_i(edn_i),
-		.clk_otp_i(clk_otp_i),
-		.rst_otp_ni(rst_otp_ni),
-		.icache_otp_key_o(icache_otp_key_o),
-		.icache_otp_key_i(icache_otp_key_i),
-		.fpga_info_i(fpga_info_i),
-		.alert_rx_i(alert_rx_i),
-		.alert_tx_o(alert_tx_o)
-	);
-endmodule
+
 module ibex_alu (
 	operator_i,
 	operand_a_i,
@@ -21098,1110 +20842,7 @@ module ibex_wb_stage (
 	assign rf_wdata_wb_o = ({32 {rf_wdata_wb_mux_we[0]}} & rf_wdata_wb_mux[0]) | ({32 {rf_wdata_wb_mux_we[1]}} & rf_wdata_wb_mux[1]);
 	assign rf_we_wb_o = |rf_wdata_wb_mux_we;
 endmodule
-module noerr_rv_core_ibex (
-	clk_i,
-	rst_ni,
-	clk_edn_i,
-	rst_edn_ni,
-	clk_esc_i,
-	rst_esc_ni,
-	rst_cpu_n_o,
-	ram_cfg_i,
-	hart_id_i,
-	boot_addr_i,
-	corei_tl_h_o,
-	corei_tl_h_i,
-	cored_tl_h_o,
-	cored_tl_h_i,
-	irq_software_i,
-	irq_timer_i,
-	irq_external_i,
-	esc_tx_i,
-	esc_rx_o,
-	nmi_wdog_i,
-	debug_req_i,
-	crash_dump_o,
-	lc_cpu_en_i,
-	pwrmgr_cpu_en_i,
-	pwrmgr_o,
-	scan_rst_ni,
-	scanmode_i,
-	cfg_tl_d_i,
-	cfg_tl_d_o,
-	edn_o,
-	edn_i,
-	clk_otp_i,
-	rst_otp_ni,
-	icache_otp_key_o,
-	icache_otp_key_i,
-	fpga_info_i,
-	alert_rx_i,
-	alert_tx_o
-);
-	localparam signed [31:0] rv_core_ibex_reg_pkg_NumAlerts = 4;
-	parameter [3:0] AlertAsyncOn = {rv_core_ibex_reg_pkg_NumAlerts {1'b1}};
-	parameter [0:0] PMPEnable = 1'b1;
-	parameter [31:0] PMPGranularity = 0;
-	parameter [31:0] PMPNumRegions = 16;
-	parameter [31:0] MHPMCounterNum = 10;
-	parameter [31:0] MHPMCounterWidth = 32;
-	parameter [0:0] RV32E = 0;
-	parameter integer RV32M = 32'sd3;
-	parameter integer RV32B = 32'sd2;
-	parameter integer RegFile = 32'sd0;
-	parameter [0:0] BranchTargetALU = 1'b1;
-	parameter [0:0] WritebackStage = 1'b1;
-	parameter [0:0] ICache = 1'b1;
-	parameter [0:0] ICacheECC = 1'b1;
-	parameter [0:0] ICacheScramble = 1'b1;
-	parameter [0:0] BranchPredictor = 1'b0;
-	parameter [0:0] DbgTriggerEn = 1'b1;
-	parameter [31:0] DbgHwBreakNum = 4;
-	parameter [0:0] SecureIbex = 1'b1;
-	localparam signed [31:0] ibex_pkg_LfsrWidth = 32;
-	localparam [31:0] ibex_pkg_RndCnstLfsrSeedDefault = 32'hac533bf4;
-	parameter [31:0] RndCnstLfsrSeed = ibex_pkg_RndCnstLfsrSeedDefault;
-	localparam [159:0] ibex_pkg_RndCnstLfsrPermDefault = 160'h1e35ecba467fd1b12e958152c04fa43878a8daed;
-	parameter [159:0] RndCnstLfsrPerm = ibex_pkg_RndCnstLfsrPermDefault;
-	parameter [31:0] DmHaltAddr = 32'h1a110800;
-	parameter [31:0] DmExceptionAddr = 32'h1a110808;
-	parameter [0:0] PipeLine = 1'b0;
-	localparam [31:0] ibex_pkg_SCRAMBLE_KEY_W = 128;
-	localparam [127:0] ibex_pkg_RndCnstIbexKeyDefault = 128'h14e8cecae3040d5e12286bb3cc113298;
-	parameter [127:0] RndCnstIbexKeyDefault = ibex_pkg_RndCnstIbexKeyDefault;
-	localparam [31:0] ibex_pkg_SCRAMBLE_NONCE_W = 64;
-	localparam [63:0] ibex_pkg_RndCnstIbexNonceDefault = 64'hf79780bc735f3843;
-	parameter [63:0] RndCnstIbexNonceDefault = ibex_pkg_RndCnstIbexNonceDefault;
-	input wire clk_i;
-	input wire rst_ni;
-	input wire clk_edn_i;
-	input wire rst_edn_ni;
-	input wire clk_esc_i;
-	input wire rst_esc_ni;
-	output wire rst_cpu_n_o;
-	input wire [9:0] ram_cfg_i;
-	input wire [31:0] hart_id_i;
-	input wire [31:0] boot_addr_i;
-	localparam signed [31:0] prim_mubi_pkg_MuBi4Width = 4;
-	localparam signed [31:0] tlul_pkg_DataIntgWidth = 7;
-	localparam signed [31:0] tlul_pkg_H2DCmdIntgWidth = 7;
-	localparam signed [31:0] top_pkg_TL_AIW = 8;
-	localparam signed [31:0] top_pkg_TL_AW = 32;
-	localparam signed [31:0] top_pkg_TL_DW = 32;
-	localparam signed [31:0] top_pkg_TL_DBW = top_pkg_TL_DW >> 3;
-	localparam signed [31:0] top_pkg_TL_SZW = $clog2($clog2(top_pkg_TL_DBW) + 1);
-	output wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 23:0] corei_tl_h_o;
-	localparam signed [31:0] tlul_pkg_D2HRspIntgWidth = 7;
-	localparam signed [31:0] top_pkg_TL_DIW = 1;
-	input wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + (tlul_pkg_D2HRspIntgWidth + tlul_pkg_DataIntgWidth)) + 1:0] corei_tl_h_i;
-	output wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 23:0] cored_tl_h_o;
-	input wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + (tlul_pkg_D2HRspIntgWidth + tlul_pkg_DataIntgWidth)) + 1:0] cored_tl_h_i;
-	input wire irq_software_i;
-	input wire irq_timer_i;
-	input wire irq_external_i;
-	input wire [1:0] esc_tx_i;
-	output wire [1:0] esc_rx_o;
-	input wire nmi_wdog_i;
-	input wire debug_req_i;
-	output wire [224:0] crash_dump_o;
-	localparam signed [31:0] lc_ctrl_pkg_TxWidth = 4;
-	input wire [3:0] lc_cpu_en_i;
-	input wire [3:0] pwrmgr_cpu_en_i;
-	output wire [0:0] pwrmgr_o;
-	input scan_rst_ni;
-	input wire [3:0] scanmode_i;
-	input wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 23:0] cfg_tl_d_i;
-	output wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + (tlul_pkg_D2HRspIntgWidth + tlul_pkg_DataIntgWidth)) + 1:0] cfg_tl_d_o;
-	output wire [0:0] edn_o;
-	localparam [31:0] edn_pkg_ENDPOINT_BUS_WIDTH = 32;
-	input wire [33:0] edn_i;
-	input clk_otp_i;
-	input rst_otp_ni;
-	output wire [0:0] icache_otp_key_o;
-	localparam signed [31:0] otp_ctrl_pkg_SramKeyWidth = 128;
-	localparam signed [31:0] otp_ctrl_pkg_SramNonceWidth = 128;
-	input wire [257:0] icache_otp_key_i;
-	input [31:0] fpga_info_i;
-	input wire [15:0] alert_rx_i;
-	output wire [7:0] alert_tx_o;
-	wire [312:0] reg2hw;
-	wire [82:0] hw2reg;
-	localparam [0:0] FifoPass = (PipeLine ? 1'b0 : 1'b1);
-	localparam [31:0] FifoDepth = (PipeLine ? 2 : 0);
-	localparam signed [31:0] NumOutstandingReqs = (ICache ? 8 : 2);
-	wire instr_req;
-	wire instr_gnt;
-	wire instr_rvalid;
-	wire [31:0] instr_addr;
-	wire [31:0] instr_rdata;
-	wire [6:0] instr_rdata_intg;
-	wire instr_err;
-	wire data_req;
-	wire data_gnt;
-	wire data_rvalid;
-	wire data_we;
-	wire [3:0] data_be;
-	wire [31:0] data_addr;
-	wire [31:0] data_wdata;
-	wire [6:0] data_wdata_intg;
-	wire [31:0] data_rdata;
-	wire [6:0] data_rdata_intg;
-	wire data_err;
-	wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 23:0] tl_i_ibex2fifo;
-	wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + (tlul_pkg_D2HRspIntgWidth + tlul_pkg_DataIntgWidth)) + 1:0] tl_i_fifo2ibex;
-	wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 23:0] tl_d_ibex2fifo;
-	wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + (tlul_pkg_D2HRspIntgWidth + tlul_pkg_DataIntgWidth)) + 1:0] tl_d_fifo2ibex;
-	wire core_sleep;
-	wire ibex_top_clk_i;
-	wire addr_trans_rst_ni;
-	assign ibex_top_clk_i = clk_i;
-	assign addr_trans_rst_ni = rst_ni;
-	wire ibus_intg_err;
-	wire dbus_intg_err;
-	wire alert_minor;
-	wire alert_major_internal;
-	wire alert_major_bus;
-	wire double_fault;
-	wire fatal_intg_err;
-	wire fatal_core_err;
-	wire recov_core_err;
-	wire fatal_intg_event;
-	wire fatal_core_event;
-	wire recov_core_event;
-	assign fatal_intg_event = (ibus_intg_err | dbus_intg_err) | alert_major_bus;
-	assign fatal_core_event = alert_major_internal | double_fault;
-	assign recov_core_event = alert_minor;
-	localparam signed [31:0] rv_core_ibex_reg_pkg_NumRegions = 2;
-	wire [129:0] ibus_region_cfg;
-	wire [129:0] dbus_region_cfg;
-	assign rst_cpu_n_o = rst_ni;
-	wire esc_irq_nm;
-	localparam signed [31:0] alert_handler_reg_pkg_N_ESC_SEV = 4;
-	localparam signed [31:0] alert_handler_reg_pkg_PING_CNT_DW = 16;
-	prim_esc_receiver #(
-		.N_ESC_SEV(alert_handler_reg_pkg_N_ESC_SEV),
-		.PING_CNT_DW(alert_handler_reg_pkg_PING_CNT_DW)
-	) u_prim_esc_receiver(
-		.clk_i(clk_esc_i),
-		.rst_ni(rst_esc_ni),
-		.esc_req_o(esc_irq_nm),
-		.esc_rx_o(esc_rx_o),
-		.esc_tx_i(esc_tx_i)
-	);
-	wire alert_irq_nm;
-	prim_flop_2sync #(.Width(1)) u_alert_nmi_sync(
-		.clk_i(clk_i),
-		.rst_ni(rst_ni),
-		.d_i(esc_irq_nm),
-		.q_o(alert_irq_nm)
-	);
-	wire wdog_irq_nm;
-	prim_flop_2sync #(.Width(1)) u_wdog_nmi_sync(
-		.clk_i(clk_i),
-		.rst_ni(rst_ni),
-		.d_i(nmi_wdog_i),
-		.q_o(wdog_irq_nm)
-	);
-	assign hw2reg[77] = 1'b1;
-	assign hw2reg[76] = alert_irq_nm;
-	assign hw2reg[75] = 1'b1;
-	assign hw2reg[74] = wdog_irq_nm;
-	wire irq_nm;
-	assign irq_nm = |(reg2hw[34-:2] & reg2hw[36-:2]);
-	wire [3:0] lc_cpu_en;
-	prim_lc_sync u_lc_sync(
-		.clk_i(clk_i),
-		.rst_ni(rst_ni),
-		.lc_en_i(lc_cpu_en_i),
-		.lc_en_o(lc_cpu_en)
-	);
-	wire [3:0] pwrmgr_cpu_en;
-	prim_lc_sync u_pwrmgr_sync(
-		.clk_i(clk_i),
-		.rst_ni(rst_ni),
-		.lc_en_i(pwrmgr_cpu_en_i),
-		.lc_en_o(pwrmgr_cpu_en)
-	);
-	wire irq_timer_sync;
-	prim_flop_2sync #(.Width(1)) u_intr_timer_sync(
-		.clk_i(clk_i),
-		.rst_ni(rst_ni),
-		.d_i(irq_timer_i),
-		.q_o(irq_timer_sync)
-	);
-	wire irq_software;
-	wire irq_timer;
-	wire irq_external;
-	prim_sec_anchor_buf #(.Width(3)) u_prim_buf_irq(
-		.in_i({irq_software_i, irq_timer_sync, irq_external_i}),
-		.out_o({irq_software, irq_timer, irq_external})
-	);
-	wire key_req;
-	wire key_ack;
-	wire [127:0] key;
-	wire [63:0] nonce;
-	wire unused_seed_valid;
-	localparam signed [31:0] PayLoadW = (ibex_pkg_SCRAMBLE_KEY_W + ibex_pkg_SCRAMBLE_NONCE_W) + 1;
-	prim_sync_reqack_data #(
-		.Width(PayLoadW),
-		.DataSrc2Dst(1'b0)
-	) u_prim_sync_reqack_data(
-		.clk_src_i(clk_i),
-		.rst_src_ni(rst_ni),
-		.clk_dst_i(clk_otp_i),
-		.rst_dst_ni(rst_otp_ni),
-		.req_chk_i(1'b1),
-		.src_req_i(key_req),
-		.src_ack_o(key_ack),
-		.dst_req_o(icache_otp_key_o[0]),
-		.dst_ack_i(icache_otp_key_i[257]),
-		.data_i({icache_otp_key_i[256-:128], icache_otp_key_i[64:1], icache_otp_key_i[0]}),
-		.data_o({key, nonce, unused_seed_valid})
-	);
-	wire unused_nonce;
-	assign unused_nonce = |icache_otp_key_i[128-:128];
-	wire [3:0] local_fetch_enable_d;
-	wire [3:0] local_fetch_enable_q;
-	function automatic [3:0] sv2v_cast_A1913;
-		input reg [3:0] inp;
-		sv2v_cast_A1913 = inp;
-	endfunction
-	assign local_fetch_enable_d = (fatal_core_err ? sv2v_cast_A1913(4'b1010) : local_fetch_enable_q);
-	prim_lc_sender #(
-		.AsyncOn(1),
-		.ResetValueIsOn(1)
-	) u_prim_lc_sender(
-		.clk_i(clk_i),
-		.rst_ni(rst_ni),
-		.lc_en_i(local_fetch_enable_d),
-		.lc_en_o(local_fetch_enable_q)
-	);
-	wire [3:0] fetch_enable;
-	function automatic [3:0] lc_ctrl_pkg_lc_tx_and;
-		input reg [3:0] a;
-		input reg [3:0] b;
-		input reg [3:0] act;
-		reg [3:0] a_in;
-		reg [3:0] b_in;
-		reg [3:0] act_in;
-		reg [3:0] out;
-		begin
-			a_in = a;
-			b_in = b;
-			act_in = act;
-			begin : sv2v_autoblock_1
-				reg signed [31:0] k;
-				for (k = 0; k < lc_ctrl_pkg_TxWidth; k = k + 1)
-					if (act_in[k])
-						out[k] = a_in[k] && b_in[k];
-					else
-						out[k] = a_in[k] || b_in[k];
-			end
-			lc_ctrl_pkg_lc_tx_and = out;
-		end
-	endfunction
-	function automatic [3:0] lc_ctrl_pkg_lc_tx_and_hi;
-		input reg [3:0] a;
-		input reg [3:0] b;
-		lc_ctrl_pkg_lc_tx_and_hi = lc_ctrl_pkg_lc_tx_and(a, b, sv2v_cast_A1913(4'b0101));
-	endfunction
-	assign fetch_enable = lc_ctrl_pkg_lc_tx_and_hi(local_fetch_enable_q, lc_ctrl_pkg_lc_tx_and_hi(lc_cpu_en[0+:lc_ctrl_pkg_TxWidth], pwrmgr_cpu_en[0+:lc_ctrl_pkg_TxWidth]));
-	wire [159:0] crash_dump;
-	function automatic [3:0] sv2v_cast_38B98;
-		input reg [3:0] inp;
-		sv2v_cast_38B98 = inp;
-	endfunction
-	function automatic prim_mubi_pkg_mubi4_test_true_strict;
-		input reg [3:0] val;
-		prim_mubi_pkg_mubi4_test_true_strict = sv2v_cast_38B98(4'h6) == val;
-	endfunction
-	ibex_top #(
-		.PMPEnable(PMPEnable),
-		.PMPGranularity(PMPGranularity),
-		.PMPNumRegions(PMPNumRegions),
-		.MHPMCounterNum(MHPMCounterNum),
-		.MHPMCounterWidth(MHPMCounterWidth),
-		.RV32E(RV32E),
-		.RV32M(RV32M),
-		.RV32B(RV32B),
-		.RegFile(RegFile),
-		.BranchTargetALU(BranchTargetALU),
-		.WritebackStage(WritebackStage),
-		.ICache(ICache),
-		.ICacheECC(ICacheECC),
-		.ICacheScramble(ICacheScramble),
-		.BranchPredictor(BranchPredictor),
-		.DbgTriggerEn(DbgTriggerEn),
-		.DbgHwBreakNum(DbgHwBreakNum),
-		.SecureIbex(SecureIbex),
-		.RndCnstLfsrSeed(RndCnstLfsrSeed),
-		.RndCnstLfsrPerm(RndCnstLfsrPerm),
-		.RndCnstIbexKey(RndCnstIbexKeyDefault),
-		.RndCnstIbexNonce(RndCnstIbexNonceDefault),
-		.DmHaltAddr(DmHaltAddr),
-		.DmExceptionAddr(DmExceptionAddr)
-	) u_core(
-		.clk_i(ibex_top_clk_i),
-		.rst_ni(rst_ni),
-		.test_en_i(prim_mubi_pkg_mubi4_test_true_strict(scanmode_i)),
-		.scan_rst_ni(scan_rst_ni),
-		.ram_cfg_i(ram_cfg_i),
-		.hart_id_i(hart_id_i),
-		.boot_addr_i(boot_addr_i),
-		.instr_req_o(instr_req),
-		.instr_gnt_i(instr_gnt),
-		.instr_rvalid_i(instr_rvalid),
-		.instr_addr_o(instr_addr),
-		.instr_rdata_i(instr_rdata),
-		.instr_rdata_intg_i(instr_rdata_intg),
-		.instr_err_i(instr_err),
-		.data_req_o(data_req),
-		.data_gnt_i(data_gnt),
-		.data_rvalid_i(data_rvalid),
-		.data_we_o(data_we),
-		.data_be_o(data_be),
-		.data_addr_o(data_addr),
-		.data_wdata_o(data_wdata),
-		.data_wdata_intg_o(data_wdata_intg),
-		.data_rdata_i(data_rdata),
-		.data_rdata_intg_i(data_rdata_intg),
-		.data_err_i(data_err),
-		.irq_software_i(irq_software),
-		.irq_timer_i(irq_timer),
-		.irq_external_i(irq_external),
-		.irq_fast_i(1'sb0),
-		.irq_nm_i(irq_nm),
-		.debug_req_i(debug_req_i),
-		.crash_dump_o(crash_dump),
-		.scramble_key_valid_i(key_ack),
-		.scramble_key_i(key),
-		.scramble_nonce_i(nonce),
-		.scramble_req_o(key_req),
-		.double_fault_seen_o(double_fault),
-		.fetch_enable_i(fetch_enable),
-		.alert_minor_o(alert_minor),
-		.alert_major_internal_o(alert_major_internal),
-		.alert_major_bus_o(alert_major_bus),
-		.core_sleep_o(core_sleep)
-	);
-	reg core_sleep_q;
-	always @(posedge clk_i or negedge rst_ni)
-		if (!rst_ni)
-			core_sleep_q <= 1'sb0;
-		else
-			core_sleep_q <= core_sleep;
-	prim_buf #(.Width(1)) u_core_sleeping_buf(
-		.in_i(core_sleep_q),
-		.out_o(pwrmgr_o[0])
-	);
-	reg prev_valid;
-	reg [31:0] prev_exception_pc;
-	reg [31:0] prev_exception_addr;
-	assign crash_dump_o[159-:160] = crash_dump;
-	assign crash_dump_o[224] = prev_valid;
-	assign crash_dump_o[223-:32] = prev_exception_pc;
-	assign crash_dump_o[191-:32] = prev_exception_addr;
-	always @(posedge clk_i or negedge rst_ni)
-		if (!rst_ni) begin
-			prev_valid <= 1'sb0;
-			prev_exception_pc <= 1'sb0;
-			prev_exception_addr <= 1'sb0;
-		end
-		else if (double_fault) begin
-			prev_valid <= 1'b1;
-			prev_exception_pc <= crash_dump[63-:32];
-			prev_exception_addr <= crash_dump[31-:32];
-		end
-	wire [31:0] instr_addr_trans;
-	rv_core_addr_trans #(
-		.AddrWidth(32),
-		.NumRegions(rv_core_ibex_reg_pkg_NumRegions)
-	) u_ibus_trans(
-		.clk_i(clk_i),
-		.rst_ni(addr_trans_rst_ni),
-		.region_cfg_i(ibus_region_cfg),
-		.addr_i(instr_addr),
-		.addr_o(instr_addr_trans)
-	);
-	assign instr_err = 0;
-	wire [6:0] instr_wdata_intg;
-	wire [31:0] unused_data;
-	function automatic [38:0] sv2v_cast_39;
-		input reg [38:0] inp;
-		sv2v_cast_39 = inp;
-	endfunction
-	function automatic [38:0] prim_secded_pkg_prim_secded_inv_39_32_enc;
-		input reg [31:0] data_i;
-		reg [38:0] data_o;
-		begin
-			data_o = sv2v_cast_39(data_i);
-			data_o[32] = ^(data_o & 39'h002606bd25);
-			data_o[33] = ^(data_o & 39'h00deba8050);
-			data_o[34] = ^(data_o & 39'h00413d89aa);
-			data_o[35] = ^(data_o & 39'h0031234ed1);
-			data_o[36] = ^(data_o & 39'h00c2c1323b);
-			data_o[37] = ^(data_o & 39'h002dcc624c);
-			data_o[38] = ^(data_o & 39'h0098505586);
-			data_o = data_o ^ 39'h2a00000000;
-			prim_secded_pkg_prim_secded_inv_39_32_enc = data_o;
-		end
-	endfunction
-	assign {instr_wdata_intg, unused_data} = prim_secded_pkg_prim_secded_inv_39_32_enc(instr_rdata);
-	tlul_adapter_host #(
-		.MAX_REQS(NumOutstandingReqs),
-		.EnableDataIntgGen(~SecureIbex)
-	) tl_adapter_host_i_ibex(
-		.clk_i(clk_i),
-		.rst_ni(rst_ni),
-		.req_i(instr_req),
-		.instr_type_i(sv2v_cast_38B98(4'h6)),
-		.gnt_o(instr_gnt),
-		.addr_i(instr_addr_trans),
-		.we_i(1'b0),
-		.wdata_i(32'b00000000000000000000000000000000),
-		.wdata_intg_i(instr_wdata_intg),
-		.be_i(4'hf),
-		.valid_o(instr_rvalid),
-		.rdata_o(instr_rdata),
-		.rdata_intg_o(instr_rdata_intg),
-		.intg_err_o(ibus_intg_err),
-		.tl_o(tl_i_ibex2fifo),
-		.tl_i(tl_i_fifo2ibex)
-	);
-	tlul_fifo_sync #(
-		.ReqPass(FifoPass),
-		.RspPass(FifoPass),
-		.ReqDepth(FifoDepth),
-		.RspDepth(FifoDepth)
-	) fifo_i(
-		.clk_i(clk_i),
-		.rst_ni(rst_ni),
-		.tl_h_i(tl_i_ibex2fifo),
-		.tl_h_o(tl_i_fifo2ibex),
-		.tl_d_o(corei_tl_h_o),
-		.tl_d_i(corei_tl_h_i),
-		.spare_req_i(1'b0),
-		.spare_rsp_i(1'b0)
-	);
-	wire [31:0] data_addr_trans;
-	rv_core_addr_trans #(
-		.AddrWidth(32),
-		.NumRegions(rv_core_ibex_reg_pkg_NumRegions)
-	) u_dbus_trans(
-		.clk_i(clk_i),
-		.rst_ni(addr_trans_rst_ni),
-		.region_cfg_i(dbus_region_cfg),
-		.addr_i(data_addr),
-		.addr_o(data_addr_trans)
-	);
-	assign data_err = 0;
-	tlul_adapter_host #(
-		.MAX_REQS(2),
-		.EnableDataIntgGen(~SecureIbex)
-	) tl_adapter_host_d_ibex(
-		.clk_i(clk_i),
-		.rst_ni(rst_ni),
-		.req_i(data_req),
-		.instr_type_i(sv2v_cast_38B98(4'h9)),
-		.gnt_o(data_gnt),
-		.addr_i(data_addr_trans),
-		.we_i(data_we),
-		.wdata_i(data_wdata),
-		.wdata_intg_i(data_wdata_intg),
-		.be_i(data_be),
-		.valid_o(data_rvalid),
-		.rdata_o(data_rdata),
-		.rdata_intg_o(data_rdata_intg),
-		.intg_err_o(dbus_intg_err),
-		.tl_o(tl_d_ibex2fifo),
-		.tl_i(tl_d_fifo2ibex)
-	);
-	tlul_fifo_sync #(
-		.ReqPass(FifoPass),
-		.RspPass(FifoPass),
-		.ReqDepth(FifoDepth),
-		.RspDepth(FifoDepth)
-	) fifo_d(
-		.clk_i(clk_i),
-		.rst_ni(rst_ni),
-		.tl_h_i(tl_d_ibex2fifo),
-		.tl_h_o(tl_d_fifo2ibex),
-		.tl_d_o(cored_tl_h_o),
-		.tl_d_i(cored_tl_h_i),
-		.spare_req_i(1'b0),
-		.spare_rsp_i(1'b0)
-	);
-	wire intg_err;
-	wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 23:0] tl_win_h2d;
-	wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + (tlul_pkg_D2HRspIntgWidth + tlul_pkg_DataIntgWidth)) + 1:0] tl_win_d2h;
-	rv_core_ibex_cfg_reg_top u_reg_cfg(
-		.clk_i(clk_i),
-		.rst_ni(rst_ni),
-		.tl_i(cfg_tl_d_i),
-		.tl_o(cfg_tl_d_o),
-		.reg2hw(reg2hw),
-		.hw2reg(hw2reg),
-		.intg_err_o(intg_err),
-		.tl_win_o(tl_win_h2d),
-		.tl_win_i(tl_win_d2h),
-		.devmode_i(1'b1)
-	);
-	genvar i;
-	generate
-		for (i = 0; i < rv_core_ibex_reg_pkg_NumRegions; i = i + 1) begin : gen_ibus_region_cfgs
-			assign ibus_region_cfg[(i * 65) + 64] = reg2hw[295 + i+:1];
-			assign ibus_region_cfg[(i * 65) + 63-:32] = reg2hw[231 + (i * 32)+:32];
-			assign ibus_region_cfg[(i * 65) + 31-:32] = reg2hw[167 + (i * 32)+:32];
-		end
-		for (i = 0; i < rv_core_ibex_reg_pkg_NumRegions; i = i + 1) begin : gen_dbus_region_cfgs
-			assign dbus_region_cfg[(i * 65) + 64] = reg2hw[165 + i+:1];
-			assign dbus_region_cfg[(i * 65) + 63-:32] = reg2hw[101 + (i * 32)+:32];
-			assign dbus_region_cfg[(i * 65) + 31-:32] = reg2hw[37 + (i * 32)+:32];
-		end
-	endgenerate
-	assign fatal_intg_err = fatal_intg_event;
-	assign fatal_core_err = fatal_core_event;
-	assign recov_core_err = recov_core_event;
-	assign hw2reg[73] = 1'b1;
-	assign hw2reg[72] = intg_err;
-	assign hw2reg[71] = 1'b1;
-	assign hw2reg[70] = fatal_intg_err;
-	assign hw2reg[69] = 1'b1;
-	assign hw2reg[68] = fatal_core_err;
-	assign hw2reg[67] = 1'b1;
-	assign hw2reg[66] = recov_core_err;
-	wire [3:0] alert_test;
-	assign alert_test[0] = reg2hw[312] & reg2hw[311];
-	assign alert_test[1] = reg2hw[310] & reg2hw[309];
-	assign alert_test[2] = reg2hw[308] & reg2hw[307];
-	assign alert_test[3] = reg2hw[306] & reg2hw[305];
-	localparam [3:0] AlertFatal = 4'b0101;
-	wire [3:0] alert_events;
-	wire [3:0] alert_acks;
-	function automatic prim_mubi_pkg_mubi4_test_true_loose;
-		input reg [3:0] val;
-		prim_mubi_pkg_mubi4_test_true_loose = sv2v_cast_38B98(4'h9) != val;
-	endfunction
-	assign alert_events[0] = prim_mubi_pkg_mubi4_test_true_loose(sv2v_cast_38B98(reg2hw[300-:4]));
-	assign alert_events[1] = prim_mubi_pkg_mubi4_test_true_loose(sv2v_cast_38B98(reg2hw[304-:4]));
-	assign alert_events[2] = (intg_err | fatal_intg_err) | fatal_core_err;
-	assign alert_events[3] = recov_core_err;
-	wire unused_alert_acks;
-	assign unused_alert_acks = |alert_acks;
-	assign hw2reg[78] = alert_acks[1];
-	assign hw2reg[82-:4] = sv2v_cast_38B98(4'h9);
-	generate
-		for (i = 0; i < rv_core_ibex_reg_pkg_NumAlerts; i = i + 1) begin : gen_alert_senders
-			prim_alert_sender #(
-				.AsyncOn(AlertAsyncOn[0]),
-				.IsFatal(AlertFatal[i])
-			) u_alert_sender(
-				.clk_i(clk_i),
-				.rst_ni(rst_ni),
-				.alert_test_i(alert_test[i]),
-				.alert_req_i(alert_events[i]),
-				.alert_ack_o(alert_acks[i]),
-				.alert_rx_i(alert_rx_i[i * 4+:4]),
-				.alert_tx_o(alert_tx_o[i * 2+:2])
-			);
-		end
-	endgenerate
-	reg [31:0] rnd_data_q;
-	reg [31:0] rnd_data_d;
-	reg rnd_valid_q;
-	reg rnd_valid_d;
-	reg rnd_fips_q;
-	reg rnd_fips_d;
-	wire edn_req;
-	wire [31:0] edn_data;
-	wire edn_ack;
-	wire edn_fips;
-	always @(*) begin
-		rnd_valid_d = rnd_valid_q;
-		rnd_data_d = rnd_data_q;
-		rnd_fips_d = rnd_fips_q;
-		if (reg2hw[0]) begin
-			rnd_valid_d = 1'sb0;
-			rnd_data_d = 1'sb0;
-			rnd_fips_d = 1'sb0;
-		end
-		else if (edn_req && edn_ack) begin
-			rnd_valid_d = 1'b1;
-			rnd_data_d = edn_data;
-			rnd_fips_d = edn_fips;
-		end
-	end
-	always @(posedge clk_i or negedge rst_ni)
-		if (!rst_ni) begin
-			rnd_valid_q <= 1'sb0;
-			rnd_data_q <= 1'sb0;
-			rnd_fips_q <= 1'sb0;
-		end
-		else begin
-			rnd_valid_q <= rnd_valid_d;
-			rnd_data_q <= rnd_data_d;
-			rnd_fips_q <= rnd_fips_d;
-		end
-	assign edn_req = ~rnd_valid_q;
-	prim_edn_req #(.OutWidth(32)) u_edn_if(
-		.clk_i(clk_i),
-		.rst_ni(rst_ni),
-		.req_chk_i(1'b1),
-		.req_i(edn_req),
-		.ack_o(edn_ack),
-		.data_o(edn_data),
-		.fips_o(edn_fips),
-		.clk_edn_i(clk_edn_i),
-		.rst_edn_ni(rst_edn_ni),
-		.edn_o(edn_o),
-		.edn_i(edn_i)
-	);
-	assign hw2reg[65-:32] = rnd_data_q;
-	assign hw2reg[33] = rnd_valid_q;
-	assign hw2reg[32] = rnd_fips_q;
-	wire unused_reg2hw;
-	assign unused_reg2hw = |reg2hw[32-:32];
-	assign hw2reg[31-:32] = fpga_info_i;
-	localparam signed [31:0] TlH2DWidth = 1 * ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 24);
-	localparam signed [31:0] TlD2HWidth = 1 * ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + (tlul_pkg_D2HRspIntgWidth + tlul_pkg_DataIntgWidth)) + 2);
-	wire [TlH2DWidth - 1:0] tl_win_h2d_int;
-	wire [TlD2HWidth - 1:0] tl_win_d2h_int;
-	wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + (tlul_pkg_D2HRspIntgWidth + tlul_pkg_DataIntgWidth)) + 1:0] tl_win_d2h_err_rsp;
-	prim_buf #(.Width(TlH2DWidth)) u_tlul_req_buf(
-		.in_i(tl_win_h2d),
-		.out_o(tl_win_h2d_int)
-	);
-	prim_buf #(.Width(TlD2HWidth)) u_tlul_rsp_buf(
-		.in_i(tl_win_d2h_err_rsp),
-		.out_o(tl_win_d2h_int)
-	);
-	function automatic [((((((7 + top_pkg_TL_SZW) + (32'sd8 + 32'sd1)) + 32'sd32) + (32'sd7 + 32'sd7)) + 1) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + (tlul_pkg_D2HRspIntgWidth + tlul_pkg_DataIntgWidth)) + 2 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + (tlul_pkg_D2HRspIntgWidth + tlul_pkg_DataIntgWidth)) + 1)) - 1:0] sv2v_cast_51793;
-		input reg [((((((7 + top_pkg_TL_SZW) + (32'sd8 + 32'sd1)) + 32'sd32) + (32'sd7 + 32'sd7)) + 1) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + (tlul_pkg_D2HRspIntgWidth + tlul_pkg_DataIntgWidth)) + 2 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + (tlul_pkg_D2HRspIntgWidth + tlul_pkg_DataIntgWidth)) + 1)) - 1:0] inp;
-		sv2v_cast_51793 = inp;
-	endfunction
-	assign tl_win_d2h = sv2v_cast_51793(tl_win_d2h_int);
-	wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 23:0] tl_win_h2d_int_tmp;
-	function automatic [(((((7 + top_pkg_TL_SZW) + (32'sd8 + 32'sd32)) + top_pkg_TL_DBW) + 55) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 24 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 23)) - 1:0] sv2v_cast_E9713;
-		input reg [(((((7 + top_pkg_TL_SZW) + (32'sd8 + 32'sd32)) + top_pkg_TL_DBW) + 55) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 24 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 23)) - 1:0] inp;
-		sv2v_cast_E9713 = inp;
-	endfunction
-	assign tl_win_h2d_int_tmp = sv2v_cast_E9713(tl_win_h2d_int);
-	tlul_err_resp u_sim_win_rsp(
-		.clk_i(clk_i),
-		.rst_ni(rst_ni),
-		.tl_h_i(tl_win_h2d_int_tmp),
-		.tl_h_o(tl_win_d2h_err_rsp)
-	);
-endmodule
-module noerr_tlul_adapter_sram (
-	clk_i,
-	rst_ni,
-	tl_i,
-	tl_o,
-	en_ifetch_i,
-	req_o,
-	req_type_o,
-	gnt_i,
-	we_o,
-	addr_o,
-	wdata_o,
-	wmask_o,
-	intg_error_o,
-	rdata_i,
-	rvalid_i,
-	rerror_i
-);
-	parameter signed [31:0] SramAw = 12;
-	parameter signed [31:0] SramDw = 32;
-	parameter signed [31:0] Outstanding = 1;
-	parameter [0:0] ByteAccess = 1;
-	parameter [0:0] ErrOnWrite = 0;
-	parameter [0:0] ErrOnRead = 0;
-	parameter [0:0] CmdIntgCheck = 0;
-	parameter [0:0] EnableRspIntgGen = 0;
-	parameter [0:0] EnableDataIntgGen = 0;
-	parameter [0:0] EnableDataIntgPt = 0;
-	parameter [0:0] SecFifoPtr = 0;
-	localparam signed [31:0] top_pkg_TL_DW = 32;
-	localparam signed [31:0] WidthMult = SramDw / top_pkg_TL_DW;
-	localparam signed [31:0] tlul_pkg_DataIntgWidth = 7;
-	localparam signed [31:0] IntgWidth = tlul_pkg_DataIntgWidth * WidthMult;
-	localparam signed [31:0] DataOutW = (EnableDataIntgPt ? SramDw + IntgWidth : SramDw);
-	input clk_i;
-	input rst_ni;
-	localparam signed [31:0] prim_mubi_pkg_MuBi4Width = 4;
-	localparam signed [31:0] tlul_pkg_H2DCmdIntgWidth = 7;
-	localparam signed [31:0] top_pkg_TL_AIW = 8;
-	localparam signed [31:0] top_pkg_TL_AW = 32;
-	localparam signed [31:0] top_pkg_TL_DBW = top_pkg_TL_DW >> 3;
-	localparam signed [31:0] top_pkg_TL_SZW = $clog2($clog2(top_pkg_TL_DBW) + 1);
-	input wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 23:0] tl_i;
-	localparam signed [31:0] tlul_pkg_D2HRspIntgWidth = 7;
-	localparam signed [31:0] top_pkg_TL_DIW = 1;
-	output wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + (tlul_pkg_D2HRspIntgWidth + tlul_pkg_DataIntgWidth)) + 1:0] tl_o;
-	input wire [3:0] en_ifetch_i;
-	output wire req_o;
-	output wire [3:0] req_type_o;
-	input gnt_i;
-	output wire we_o;
-	output wire [SramAw - 1:0] addr_o;
-	output wire [DataOutW - 1:0] wdata_o;
-	output wire [DataOutW - 1:0] wmask_o;
-	output wire intg_error_o;
-	input [DataOutW - 1:0] rdata_i;
-	input rvalid_i;
-	input [1:0] rerror_i;
-	localparam signed [31:0] SramByte = SramDw / 8;
-	function automatic integer prim_util_pkg_vbits;
-		input integer value;
-		prim_util_pkg_vbits = (value == 1 ? 1 : $clog2(value));
-	endfunction
-	localparam signed [31:0] DataBitWidth = prim_util_pkg_vbits(SramByte);
-	localparam signed [31:0] WoffsetWidth = (SramByte == top_pkg_TL_DBW ? 1 : DataBitWidth - prim_util_pkg_vbits(top_pkg_TL_DBW));
-	wire error_det;
-	wire error_internal;
-	wire wr_attr_error;
-	wire instr_error;
-	wire wr_vld_error;
-	wire rd_vld_error;
-	wire rsp_fifo_error;
-	wire intg_error;
-	wire tlul_error;
-	generate
-		if (CmdIntgCheck) begin : gen_cmd_intg_check
-			tlul_cmd_intg_chk u_cmd_intg_chk(
-				.tl_i(tl_i),
-				.err_o(intg_error)
-			);
-		end
-		else begin : gen_no_cmd_intg_check
-			assign intg_error = 1'sb0;
-		end
-	endgenerate
-	reg intg_error_q;
-	always @(posedge clk_i or negedge rst_ni)
-		if (!rst_ni)
-			intg_error_q <= 1'sb0;
-		else if (intg_error || rsp_fifo_error)
-			intg_error_q <= 1'b1;
-	assign intg_error_o = (intg_error | rsp_fifo_error) | intg_error_q;
-	assign wr_attr_error = ((tl_i[6 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 55)))-:((6 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 55)))) >= (3 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 56)))) ? ((6 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 55)))) - (3 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 56))))) + 1 : ((3 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 56)))) - (6 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 55))))) + 1)] == 3'h0) || (tl_i[6 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 55)))-:((6 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 55)))) >= (3 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 56)))) ? ((6 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 55)))) - (3 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 56))))) + 1 : ((3 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 56)))) - (6 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 55))))) + 1)] == 3'h1) ? (ByteAccess == 0 ? (tl_i[top_pkg_TL_DBW + 55-:((top_pkg_TL_DBW + 55) >= 56 ? top_pkg_TL_DBW : 57 - (top_pkg_TL_DBW + 55))] != {((top_pkg_TL_DBW + 55) >= 56 ? top_pkg_TL_DBW : 57 - (top_pkg_TL_DBW + 55)) * 1 {1'sb1}}) || (tl_i[top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 55)))-:((top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 55))) >= ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 56)) ? ((top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 55)))) - (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 56)))) + 1 : ((top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 56))) - (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 55))))) + 1)] != 2'h2) : 1'b0) : 1'b0);
-	function automatic [3:0] sv2v_cast_A2CB9;
-		input reg [3:0] inp;
-		sv2v_cast_A2CB9 = inp;
-	endfunction
-	function automatic prim_mubi_pkg_mubi4_test_false_loose;
-		input reg [3:0] val;
-		prim_mubi_pkg_mubi4_test_false_loose = sv2v_cast_A2CB9(4'h6) != val;
-	endfunction
-	function automatic prim_mubi_pkg_mubi4_test_invalid;
-		input reg [3:0] val;
-		prim_mubi_pkg_mubi4_test_invalid = ~(|{((sv2v_cast_A2CB9(4'h6) ^ (val ^ val)) === (val ^ (sv2v_cast_A2CB9(4'h6) ^ sv2v_cast_A2CB9(4'h6)))) & ((((val ^ val) ^ (sv2v_cast_A2CB9(4'h6) ^ sv2v_cast_A2CB9(4'h6))) === (sv2v_cast_A2CB9(4'h6) ^ sv2v_cast_A2CB9(4'h6))) | 1'bx), ((sv2v_cast_A2CB9(4'h9) ^ (val ^ val)) === (val ^ (sv2v_cast_A2CB9(4'h9) ^ sv2v_cast_A2CB9(4'h9)))) & ((((val ^ val) ^ (sv2v_cast_A2CB9(4'h9) ^ sv2v_cast_A2CB9(4'h9))) === (sv2v_cast_A2CB9(4'h9) ^ sv2v_cast_A2CB9(4'h9))) | 1'bx)});
-	endfunction
-	function automatic prim_mubi_pkg_mubi4_test_true_strict;
-		input reg [3:0] val;
-		prim_mubi_pkg_mubi4_test_true_strict = sv2v_cast_A2CB9(4'h6) == val;
-	endfunction
-	assign instr_error = prim_mubi_pkg_mubi4_test_invalid(tl_i[18-:4]) | (prim_mubi_pkg_mubi4_test_true_strict(tl_i[18-:4]) & prim_mubi_pkg_mubi4_test_false_loose(en_ifetch_i));
-	generate
-		if (ErrOnWrite == 1) begin : gen_no_writes
-			assign wr_vld_error = tl_i[6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 55))))-:((6 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 55)))) >= (3 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 56)))) ? ((6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 55))))) - (3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 56)))))) + 1 : ((3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 56))))) - (6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 55)))))) + 1)] != 3'h4;
-		end
-		else begin : gen_writes_allowed
-			assign wr_vld_error = 1'b0;
-		end
-		if (ErrOnRead == 1) begin : gen_no_reads
-			assign rd_vld_error = tl_i[6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 55))))-:((6 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 55)))) >= (3 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 56)))) ? ((6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 55))))) - (3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 56)))))) + 1 : ((3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 56))))) - (6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 55)))))) + 1)] == 3'h4;
-		end
-		else begin : gen_reads_allowed
-			assign rd_vld_error = 1'b0;
-		end
-	endgenerate
-	tlul_err u_err(
-		.clk_i(clk_i),
-		.rst_ni(rst_ni),
-		.tl_i(tl_i),
-		.err_o(tlul_error)
-	);
-	assign error_det = ((((wr_attr_error | wr_vld_error) | rd_vld_error) | instr_error) | tlul_error) | intg_error;
-	wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 23:0] tl_i_int;
-	wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + (tlul_pkg_D2HRspIntgWidth + tlul_pkg_DataIntgWidth)) + 1:0] tl_o_int;
-	wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + (tlul_pkg_D2HRspIntgWidth + tlul_pkg_DataIntgWidth)) + 1:0] tl_out;
-	wire unused_tl_i_int;
-	assign unused_tl_i_int = ^tl_i_int;
-	tlul_rsp_intg_gen #(
-		.EnableRspIntgGen(EnableRspIntgGen),
-		.EnableDataIntgGen(EnableDataIntgGen)
-	) u_rsp_gen(
-		.tl_i(tl_out),
-		.tl_o(tl_o)
-	);
-	assign error_internal = 0;
-	tlul_sram_byte #(
-		.EnableIntg((ByteAccess & EnableDataIntgPt) & !ErrOnWrite),
-		.Outstanding(Outstanding)
-	) u_sram_byte(
-		.clk_i(clk_i),
-		.rst_ni(rst_ni),
-		.tl_i(tl_i),
-		.tl_o(tl_out),
-		.tl_sram_o(tl_i_int),
-		.tl_sram_i(tl_o_int),
-		.error_i(error_det)
-	);
-	localparam signed [31:0] SramReqFifoWidth = top_pkg_TL_DBW + WoffsetWidth;
-	localparam signed [31:0] ReqFifoWidth = (7 + top_pkg_TL_SZW) + top_pkg_TL_AIW;
-	localparam signed [31:0] RspFifoWidth = (((top_pkg_TL_DW + tlul_pkg_DataIntgWidth) + 0) >= 0 ? (top_pkg_TL_DW + tlul_pkg_DataIntgWidth) + 1 : 1 - ((top_pkg_TL_DW + tlul_pkg_DataIntgWidth) + 0));
-	wire reqfifo_wvalid;
-	wire reqfifo_wready;
-	wire reqfifo_rvalid;
-	wire reqfifo_rready;
-	wire [((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) - 1:0] reqfifo_wdata;
-	wire [((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) - 1:0] reqfifo_rdata;
-	wire sramreqfifo_wvalid;
-	wire sramreqfifo_wready;
-	wire sramreqfifo_rready;
-	wire [(top_pkg_TL_DBW + WoffsetWidth) - 1:0] sramreqfifo_wdata;
-	wire [(top_pkg_TL_DBW + WoffsetWidth) - 1:0] sramreqfifo_rdata;
-	wire rspfifo_wvalid;
-	wire rspfifo_wready;
-	wire rspfifo_rvalid;
-	wire rspfifo_rready;
-	wire [(top_pkg_TL_DW + tlul_pkg_DataIntgWidth) + 0:0] rspfifo_wdata;
-	wire [(top_pkg_TL_DW + tlul_pkg_DataIntgWidth) + 0:0] rspfifo_rdata;
-	wire a_ack;
-	wire d_ack;
-	wire sram_ack;
-	assign a_ack = tl_i_int[7 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 55))))] & tl_o_int[0];
-	assign d_ack = tl_o_int[7 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + ((tlul_pkg_D2HRspIntgWidth + tlul_pkg_DataIntgWidth) + 1)))))] & tl_i_int[0];
-	assign sram_ack = req_o & gnt_i;
-	reg d_valid;
-	reg d_error;
-	always @(*) begin
-		d_valid = 1'b0;
-		if (reqfifo_rvalid) begin
-			if (reqfifo_rdata[1 + (prim_mubi_pkg_MuBi4Width + (top_pkg_TL_SZW + 7))])
-				d_valid = 1'b1;
-			else if (reqfifo_rdata[3 + (prim_mubi_pkg_MuBi4Width + (top_pkg_TL_SZW + 7))-:((7 + (top_pkg_TL_SZW + 7)) >= (5 + (top_pkg_TL_SZW + 8)) ? ((3 + (prim_mubi_pkg_MuBi4Width + (top_pkg_TL_SZW + 7))) - (1 + (prim_mubi_pkg_MuBi4Width + (top_pkg_TL_SZW + 8)))) + 1 : ((1 + (prim_mubi_pkg_MuBi4Width + (top_pkg_TL_SZW + 8))) - (3 + (prim_mubi_pkg_MuBi4Width + (top_pkg_TL_SZW + 7)))) + 1)] == 2'd1)
-				d_valid = rspfifo_rvalid;
-			else
-				d_valid = 1'b1;
-		end
-		else
-			d_valid = 1'b0;
-	end
-	always @(*) begin
-		d_error = 1'b0;
-		if (reqfifo_rvalid) begin
-			if (reqfifo_rdata[3 + (prim_mubi_pkg_MuBi4Width + (top_pkg_TL_SZW + 7))-:((7 + (top_pkg_TL_SZW + 7)) >= (5 + (top_pkg_TL_SZW + 8)) ? ((3 + (prim_mubi_pkg_MuBi4Width + (top_pkg_TL_SZW + 7))) - (1 + (prim_mubi_pkg_MuBi4Width + (top_pkg_TL_SZW + 8)))) + 1 : ((1 + (prim_mubi_pkg_MuBi4Width + (top_pkg_TL_SZW + 8))) - (3 + (prim_mubi_pkg_MuBi4Width + (top_pkg_TL_SZW + 7)))) + 1)] == 2'd1)
-				d_error = rspfifo_rdata[0] | reqfifo_rdata[1 + (prim_mubi_pkg_MuBi4Width + (top_pkg_TL_SZW + 7))];
-			else
-				d_error = reqfifo_rdata[1 + (prim_mubi_pkg_MuBi4Width + (top_pkg_TL_SZW + 7))];
-		end
-		else
-			d_error = 1'b0;
-	end
-	wire vld_rd_rsp;
-	assign vld_rd_rsp = ((d_valid & reqfifo_rvalid) & rspfifo_rvalid) & (reqfifo_rdata[3 + (prim_mubi_pkg_MuBi4Width + (top_pkg_TL_SZW + 7))-:((7 + (top_pkg_TL_SZW + 7)) >= (5 + (top_pkg_TL_SZW + 8)) ? ((3 + (prim_mubi_pkg_MuBi4Width + (top_pkg_TL_SZW + 7))) - (1 + (prim_mubi_pkg_MuBi4Width + (top_pkg_TL_SZW + 8)))) + 1 : ((1 + (prim_mubi_pkg_MuBi4Width + (top_pkg_TL_SZW + 8))) - (3 + (prim_mubi_pkg_MuBi4Width + (top_pkg_TL_SZW + 7)))) + 1)] == 2'd1);
-	wire [31:0] error_blanking_data;
-	localparam [31:0] tlul_pkg_DataWhenError = {top_pkg_TL_DW {1'b1}};
-	localparam [31:0] tlul_pkg_DataWhenInstrError = 1'sb0;
-	assign error_blanking_data = (prim_mubi_pkg_mubi4_test_true_strict(reqfifo_rdata[prim_mubi_pkg_MuBi4Width + (top_pkg_TL_SZW + 7)-:((prim_mubi_pkg_MuBi4Width + (top_pkg_TL_SZW + 7)) >= (top_pkg_TL_SZW + 8) ? ((prim_mubi_pkg_MuBi4Width + (top_pkg_TL_SZW + 7)) - (top_pkg_TL_SZW + 8)) + 1 : ((top_pkg_TL_SZW + 8) - (prim_mubi_pkg_MuBi4Width + (top_pkg_TL_SZW + 7))) + 1)]) ? tlul_pkg_DataWhenInstrError : tlul_pkg_DataWhenError);
-	wire [31:0] unused_instr;
-	wire [31:0] unused_data;
-	wire [6:0] error_instr_integ;
-	wire [6:0] error_data_integ;
-	localparam signed [31:0] tlul_pkg_DataMaxWidth = 32;
-	function automatic [31:0] sv2v_cast_32;
-		input reg [31:0] inp;
-		sv2v_cast_32 = inp;
-	endfunction
-	tlul_data_integ_enc u_tlul_data_integ_enc_instr(
-		.data_i(sv2v_cast_32(tlul_pkg_DataWhenInstrError)),
-		.data_intg_o({error_instr_integ, unused_instr})
-	);
-	tlul_data_integ_enc u_tlul_data_integ_enc_data(
-		.data_i(sv2v_cast_32(tlul_pkg_DataWhenError)),
-		.data_intg_o({error_data_integ, unused_data})
-	);
-	wire [6:0] error_blanking_integ;
-	assign error_blanking_integ = (prim_mubi_pkg_mubi4_test_true_strict(reqfifo_rdata[prim_mubi_pkg_MuBi4Width + (top_pkg_TL_SZW + 7)-:((prim_mubi_pkg_MuBi4Width + (top_pkg_TL_SZW + 7)) >= (top_pkg_TL_SZW + 8) ? ((prim_mubi_pkg_MuBi4Width + (top_pkg_TL_SZW + 7)) - (top_pkg_TL_SZW + 8)) + 1 : ((top_pkg_TL_SZW + 8) - (prim_mubi_pkg_MuBi4Width + (top_pkg_TL_SZW + 7))) + 1)]) ? error_instr_integ : error_data_integ);
-	wire [31:0] d_data;
-	assign d_data = (vld_rd_rsp & ~d_error ? rspfifo_rdata[39-:32] : error_blanking_data);
-	wire [6:0] data_intg;
-	localparam [6:0] prim_secded_pkg_SecdedInv3932ZeroEcc = 7'h2a;
-	assign data_intg = (vld_rd_rsp && reqfifo_rdata[5 + (top_pkg_TL_SZW + 7)] ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata[7-:7] : prim_secded_pkg_SecdedInv3932ZeroEcc));
-	function automatic [6:0] sv2v_cast_5F39A;
-		input reg [6:0] inp;
-		sv2v_cast_5F39A = inp;
-	endfunction
-	function automatic [top_pkg_TL_SZW - 1:0] sv2v_cast_4660A;
-		input reg [top_pkg_TL_SZW - 1:0] inp;
-		sv2v_cast_4660A = inp;
-	endfunction
-	function automatic [7:0] sv2v_cast_964CB;
-		input reg [7:0] inp;
-		sv2v_cast_964CB = inp;
-	endfunction
-	function automatic [0:0] sv2v_cast_702AC;
-		input reg [0:0] inp;
-		sv2v_cast_702AC = inp;
-	endfunction
-	function automatic [31:0] sv2v_cast_35AE2;
-		input reg [31:0] inp;
-		sv2v_cast_35AE2 = inp;
-	endfunction
-	function automatic [(tlul_pkg_D2HRspIntgWidth + tlul_pkg_DataIntgWidth) - 1:0] sv2v_cast_1D31F;
-		input reg [(tlul_pkg_D2HRspIntgWidth + tlul_pkg_DataIntgWidth) - 1:0] inp;
-		sv2v_cast_1D31F = inp;
-	endfunction
-	assign tl_o_int = {d_valid, (d_valid && (reqfifo_rdata[7 + (top_pkg_TL_SZW + 7)-:((7 + (top_pkg_TL_SZW + 7)) >= (5 + (top_pkg_TL_SZW + 8)) ? ((7 + (top_pkg_TL_SZW + 7)) - (5 + (top_pkg_TL_SZW + 8))) + 1 : ((5 + (top_pkg_TL_SZW + 8)) - (7 + (top_pkg_TL_SZW + 7))) + 1)] != 2'd1) ? 3'h0 : 3'h1), 3'b000, sv2v_cast_4660A((d_valid ? reqfifo_rdata[top_pkg_TL_SZW + 7-:((top_pkg_TL_SZW + 7) >= 8 ? top_pkg_TL_SZW : 9 - (top_pkg_TL_SZW + 7))] : {((top_pkg_TL_SZW + 7) >= 8 ? top_pkg_TL_SZW : 9 - (top_pkg_TL_SZW + 7)) * 1 {1'sb0}})), sv2v_cast_964CB((d_valid ? reqfifo_rdata[7-:top_pkg_TL_AIW] : {8 {1'sb0}})), sv2v_cast_702AC(1'b0), sv2v_cast_35AE2(d_data), sv2v_cast_1D31F({sv2v_cast_5F39A(1'sb0), data_intg}), d_valid && d_error, ((gnt_i | error_internal) & reqfifo_wready) & sramreqfifo_wready};
-	assign req_o = (tl_i_int[7 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 55))))] & reqfifo_wready) & ~error_internal;
-	assign req_type_o = tl_i_int[18-:4];
-	assign we_o = tl_i_int[7 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 55))))] & |{tl_i_int[6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 55))))-:((6 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 55)))) >= (3 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 56)))) ? ((6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 55))))) - (3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 56)))))) + 1 : ((3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 56))))) - (6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 55)))))) + 1)] == 3'h0, tl_i_int[6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 55))))-:((6 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 55)))) >= (3 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 56)))) ? ((6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 55))))) - (3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 56)))))) + 1 : ((3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 56))))) - (6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 55)))))) + 1)] == 3'h1};
-	assign addr_o = (tl_i_int[7 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 55)))] ? tl_i_int[(top_pkg_TL_AW + (top_pkg_TL_DBW + 55)) - (31 - DataBitWidth)+:SramAw] : {SramAw {1'sb0}});
-	wire [WoffsetWidth - 1:0] woffset;
-	generate
-		if (top_pkg_TL_DW != SramDw) begin : gen_wordwidthadapt
-			assign woffset = tl_i_int[(top_pkg_TL_AW + (top_pkg_TL_DBW + 55)) - (32 - DataBitWidth):(top_pkg_TL_AW + (top_pkg_TL_DBW + 55)) - (31 - prim_util_pkg_vbits(top_pkg_TL_DBW))];
-		end
-		else begin : gen_no_wordwidthadapt
-			assign woffset = 1'sb0;
-		end
-	endgenerate
-	localparam signed [31:0] DataWidth = (EnableDataIntgPt ? top_pkg_TL_DW + tlul_pkg_DataIntgWidth : top_pkg_TL_DW);
-	wire [(WidthMult * DataWidth) - 1:0] wmask_combined;
-	wire [(WidthMult * DataWidth) - 1:0] wdata_combined;
-	reg [(WidthMult * top_pkg_TL_DW) - 1:0] wmask_int;
-	reg [(WidthMult * top_pkg_TL_DW) - 1:0] wdata_int;
-	reg [(WidthMult * tlul_pkg_DataIntgWidth) - 1:0] wmask_intg;
-	reg [(WidthMult * tlul_pkg_DataIntgWidth) - 1:0] wdata_intg;
-	always @(*) begin
-		wmask_int = 1'sb0;
-		wdata_int = 1'sb0;
-		if (tl_i_int[7 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 55))))]) begin : sv2v_autoblock_1
-			reg signed [31:0] i;
-			for (i = 0; i < 4; i = i + 1)
-				begin
-					wmask_int[(woffset * top_pkg_TL_DW) + (8 * i)+:8] = {8 {tl_i_int[(top_pkg_TL_DBW + 55) - ((top_pkg_TL_DBW - 1) - i)]}};
-					wdata_int[(woffset * top_pkg_TL_DW) + (8 * i)+:8] = (tl_i_int[(top_pkg_TL_DBW + 55) - ((top_pkg_TL_DBW - 1) - i)] && we_o ? tl_i_int[24 + (8 * i)+:8] : {8 {1'sb0}});
-				end
-		end
-	end
-	always @(*) begin
-		wmask_intg = 1'sb0;
-		wdata_intg = 1'sb0;
-		if (tl_i_int[7 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 55))))]) begin
-			wmask_intg[woffset * tlul_pkg_DataIntgWidth+:tlul_pkg_DataIntgWidth] = {tlul_pkg_DataIntgWidth {1'b1}};
-			wdata_intg[woffset * tlul_pkg_DataIntgWidth+:tlul_pkg_DataIntgWidth] = tl_i_int[7-:tlul_pkg_DataIntgWidth];
-		end
-	end
-	genvar i;
-	generate
-		for (i = 0; i < WidthMult; i = i + 1) begin : gen_write_output
-			if (EnableDataIntgPt) begin : gen_combined_output
-				assign wmask_combined[i * DataWidth+:DataWidth] = {wmask_intg[i * tlul_pkg_DataIntgWidth+:tlul_pkg_DataIntgWidth], wmask_int[i * top_pkg_TL_DW+:top_pkg_TL_DW]};
-				assign wdata_combined[i * DataWidth+:DataWidth] = {wdata_intg[i * tlul_pkg_DataIntgWidth+:tlul_pkg_DataIntgWidth], wdata_int[i * top_pkg_TL_DW+:top_pkg_TL_DW]};
-			end
-			else begin : gen_ft_output
-				wire unused_w;
-				assign wmask_combined[i * DataWidth+:DataWidth] = wmask_int[i * top_pkg_TL_DW+:top_pkg_TL_DW];
-				assign wdata_combined[i * DataWidth+:DataWidth] = wdata_int[i * top_pkg_TL_DW+:top_pkg_TL_DW];
-				assign unused_w = |wmask_intg & |wdata_intg;
-			end
-		end
-	endgenerate
-	assign wmask_o = wmask_combined;
-	assign wdata_o = wdata_combined;
-	assign reqfifo_wvalid = a_ack;
-	assign reqfifo_wdata = {(tl_i_int[6 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 55)))-:((6 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 55)))) >= (3 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 56)))) ? ((6 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 55)))) - (3 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 56))))) + 1 : ((3 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 56)))) - (6 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 55))))) + 1)] != 3'h4 ? 2'd0 : 2'd1), error_internal, sv2v_cast_A2CB9(tl_i_int[18-:4]), tl_i_int[top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 55)))-:((top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 55))) >= ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 56)) ? ((top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 55)))) - (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 56)))) + 1 : ((top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 56))) - (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 55))))) + 1)], tl_i_int[top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 55))-:(((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 55)) >= (32'sd32 + (top_pkg_TL_DBW + 56)) ? ((top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 55))) - (top_pkg_TL_AW + (top_pkg_TL_DBW + 56))) + 1 : ((top_pkg_TL_AW + (top_pkg_TL_DBW + 56)) - (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 55)))) + 1)]};
-	assign reqfifo_rready = d_ack;
-	assign sramreqfifo_wdata = {tl_i_int[top_pkg_TL_DBW + 55-:((top_pkg_TL_DBW + 55) >= 56 ? top_pkg_TL_DBW : 57 - (top_pkg_TL_DBW + 55))], woffset};
-	assign sramreqfifo_wvalid = sram_ack & ~we_o;
-	assign sramreqfifo_rready = rspfifo_wvalid;
-	assign rspfifo_wvalid = rvalid_i & reqfifo_rvalid;
-	wire [(WidthMult * DataWidth) - 1:0] rdata_reshaped;
-	reg [DataWidth - 1:0] rdata_tlword;
-	assign rdata_reshaped = rdata_i;
-	localparam [38:0] prim_secded_pkg_SecdedInv3932ZeroWord = 39'h2a00000000;
-	generate
-		if (EnableDataIntgPt) begin : gen_no_rmask
-			always @(*) begin
-				rdata_tlword = prim_secded_pkg_SecdedInv3932ZeroWord;
-				if (|sramreqfifo_rdata[top_pkg_TL_DBW + (WoffsetWidth - 1)-:((top_pkg_TL_DBW + (WoffsetWidth - 1)) >= (WoffsetWidth + 0) ? ((top_pkg_TL_DBW + (WoffsetWidth - 1)) - (WoffsetWidth + 0)) + 1 : ((WoffsetWidth + 0) - (top_pkg_TL_DBW + (WoffsetWidth - 1))) + 1)])
-					rdata_tlword = rdata_reshaped[sramreqfifo_rdata[WoffsetWidth - 1-:WoffsetWidth] * DataWidth+:DataWidth];
-			end
-		end
-		else begin : gen_rmask
-			reg [DataWidth - 1:0] rmask;
-			always @(*) begin
-				rmask = 1'sb0;
-				begin : sv2v_autoblock_2
-					reg signed [31:0] i;
-					for (i = 0; i < 4; i = i + 1)
-						rmask[8 * i+:8] = {8 {sramreqfifo_rdata[(top_pkg_TL_DBW + (WoffsetWidth - 1)) - ((top_pkg_TL_DBW - 1) - i)]}};
-				end
-			end
-			wire [DataWidth:1] sv2v_tmp_037A0;
-			assign sv2v_tmp_037A0 = rdata_reshaped[sramreqfifo_rdata[WoffsetWidth - 1-:WoffsetWidth] * DataWidth+:DataWidth] & rmask;
-			always @(*) rdata_tlword = sv2v_tmp_037A0;
-		end
-	endgenerate
-	function automatic [6:0] sv2v_cast_8DC45;
-		input reg [6:0] inp;
-		sv2v_cast_8DC45 = inp;
-	endfunction
-	assign rspfifo_wdata = {sv2v_cast_35AE2(rdata_tlword[31:0]), sv2v_cast_8DC45((EnableDataIntgPt ? rdata_tlword[DataWidth - 1-:tlul_pkg_DataIntgWidth] : {7 {1'sb0}})), rerror_i[1]};
-	assign rspfifo_rready = ((reqfifo_rdata[7 + (top_pkg_TL_SZW + 7)-:((7 + (top_pkg_TL_SZW + 7)) >= (5 + (top_pkg_TL_SZW + 8)) ? ((7 + (top_pkg_TL_SZW + 7)) - (5 + (top_pkg_TL_SZW + 8))) + 1 : ((5 + (top_pkg_TL_SZW + 8)) - (7 + (top_pkg_TL_SZW + 7))) + 1)] == 2'd1) & ~reqfifo_rdata[5 + (top_pkg_TL_SZW + 7)] ? reqfifo_rready : 1'b0);
-	wire unused_rerror;
-	assign unused_rerror = rerror_i[0];
-	prim_fifo_sync #(
-		.Width(ReqFifoWidth),
-		.Pass(1'b0),
-		.Depth(Outstanding)
-	) u_reqfifo(
-		.clk_i(clk_i),
-		.rst_ni(rst_ni),
-		.clr_i(1'b0),
-		.wvalid_i(reqfifo_wvalid),
-		.wready_o(reqfifo_wready),
-		.wdata_i(reqfifo_wdata),
-		.rvalid_o(reqfifo_rvalid),
-		.rready_i(reqfifo_rready),
-		.rdata_o(reqfifo_rdata)
-	);
-	prim_fifo_sync #(
-		.Width(SramReqFifoWidth),
-		.Pass(1'b0),
-		.Depth(Outstanding)
-	) u_sramreqfifo(
-		.clk_i(clk_i),
-		.rst_ni(rst_ni),
-		.clr_i(1'b0),
-		.wvalid_i(sramreqfifo_wvalid),
-		.wready_o(sramreqfifo_wready),
-		.wdata_i(sramreqfifo_wdata),
-		.rready_i(sramreqfifo_rready),
-		.rdata_o(sramreqfifo_rdata)
-	);
-	prim_fifo_sync #(
-		.Width(RspFifoWidth),
-		.Pass(1'b1),
-		.Depth(Outstanding),
-		.Secure(SecFifoPtr)
-	) u_rspfifo(
-		.clk_i(clk_i),
-		.rst_ni(rst_ni),
-		.clr_i(1'b0),
-		.wvalid_i(rspfifo_wvalid),
-		.wready_o(rspfifo_wready),
-		.wdata_i(rspfifo_wdata),
-		.rvalid_o(rspfifo_rvalid),
-		.rready_i(rspfifo_rready),
-		.rdata_o(rspfifo_rdata),
-		.err_o(rsp_fifo_error)
-	);
-endmodule
+
 module prim_alert_receiver (
 	clk_i,
 	rst_ni,
diff --git a/cpus/ibex_small_pregenerated/cellift/generated/sv2v_out.v b/cpus/ibex_small_pregenerated/cellift/generated/sv2v_out.v
index 4432926e..1a3bca94 100644
--- a/cpus/ibex_small_pregenerated/cellift/generated/sv2v_out.v
+++ b/cpus/ibex_small_pregenerated/cellift/generated/sv2v_out.v
@@ -10960,263 +10960,7 @@ module alert_handler_reg_top (
 	assign unused_wdata = ^reg_wdata;
 	assign unused_be = ^reg_be;
 endmodule
-module cellift_rv_core_ibex_mem_top (
-	clk_i,
-	rst_ni,
-	clk_edn_i,
-	rst_edn_ni,
-	clk_esc_i,
-	rst_esc_ni,
-	rst_cpu_n_o,
-	ram_cfg_i,
-	hart_id_i,
-	boot_addr_i,
-	instr_mem_req_o,
-	instr_mem_gnt_i,
-	instr_mem_addr_o,
-	instr_mem_wdata_o,
-	instr_mem_strb_o,
-	instr_mem_we_o,
-	instr_mem_rdata_i,
-	data_mem_req_o,
-	data_mem_gnt_i,
-	data_mem_addr_o,
-	data_mem_wdata_o,
-	data_mem_strb_o,
-	data_mem_we_o,
-	data_mem_rdata_i,
-	irq_software_i,
-	irq_timer_i,
-	irq_external_i,
-	esc_tx_i,
-	esc_rx_o,
-	nmi_wdog_i,
-	debug_req_i,
-	crash_dump_o,
-	pwrmgr_cpu_en_i,
-	lc_cpu_en_i,
-	pwrmgr_o,
-	scan_rst_ni,
-	scanmode_i,
-	cfg_tl_d_i,
-	cfg_tl_d_o,
-	edn_o,
-	edn_i,
-	clk_otp_i,
-	rst_otp_ni,
-	icache_otp_key_o,
-	icache_otp_key_i,
-	fpga_info_i,
-	alert_rx_i,
-	alert_tx_o
-);
-	parameter [31:0] InstrMemAw = 20;
-	parameter [31:0] DataMemAw = 20;
-	input wire clk_i;
-	input wire rst_ni;
-	input wire clk_edn_i;
-	input wire rst_edn_ni;
-	input wire clk_esc_i;
-	input wire rst_esc_ni;
-	output wire rst_cpu_n_o;
-	input wire [9:0] ram_cfg_i;
-	input wire [31:0] hart_id_i;
-	input wire [31:0] boot_addr_i;
-	output wire instr_mem_req_o;
-	input wire instr_mem_gnt_i;
-	output wire [InstrMemAw:0] instr_mem_addr_o;
-	output wire [31:0] instr_mem_wdata_o;
-	output wire [31:0] instr_mem_strb_o;
-	output wire instr_mem_we_o;
-	input wire [31:0] instr_mem_rdata_i;
-	output wire data_mem_req_o;
-	input wire data_mem_gnt_i;
-	output wire [InstrMemAw:0] data_mem_addr_o;
-	output wire [31:0] data_mem_wdata_o;
-	output wire [31:0] data_mem_strb_o;
-	output wire data_mem_we_o;
-	input wire [31:0] data_mem_rdata_i;
-	input wire irq_software_i;
-	input wire irq_timer_i;
-	input wire irq_external_i;
-	input wire [1:0] esc_tx_i;
-	output wire [1:0] esc_rx_o;
-	input wire nmi_wdog_i;
-	input wire debug_req_i;
-	output wire [159:0] crash_dump_o;
-	localparam signed [31:0] lc_ctrl_pkg_TxWidth = 4;
-	input wire [3:0] pwrmgr_cpu_en_i;
-	input wire [3:0] lc_cpu_en_i;
-	output wire [0:0] pwrmgr_o;
-	input scan_rst_ni;
-	localparam signed [31:0] prim_mubi_pkg_MuBi4Width = 4;
-	input wire [3:0] scanmode_i;
-	localparam signed [31:0] tlul_pkg_DataIntgWidth = 7;
-	localparam signed [31:0] tlul_pkg_H2DCmdIntgWidth = 7;
-	localparam signed [31:0] top_pkg_TL_AIW = 8;
-	localparam signed [31:0] top_pkg_TL_AW = 32;
-	localparam signed [31:0] top_pkg_TL_DW = 32;
-	localparam signed [31:0] top_pkg_TL_DBW = top_pkg_TL_DW >> 3;
-	localparam signed [31:0] top_pkg_TL_SZW = $clog2($clog2(top_pkg_TL_DBW) + 1);
-	input wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 23:0] cfg_tl_d_i;
-	localparam signed [31:0] tlul_pkg_D2HRspIntgWidth = 7;
-	localparam signed [31:0] top_pkg_TL_DIW = 1;
-	output wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + (tlul_pkg_D2HRspIntgWidth + tlul_pkg_DataIntgWidth)) + 1:0] cfg_tl_d_o;
-	output wire [0:0] edn_o;
-	localparam [31:0] edn_pkg_ENDPOINT_BUS_WIDTH = 32;
-	input wire [33:0] edn_i;
-	input clk_otp_i;
-	input rst_otp_ni;
-	output wire [0:0] icache_otp_key_o;
-	localparam signed [31:0] otp_ctrl_pkg_SramKeyWidth = 128;
-	localparam signed [31:0] otp_ctrl_pkg_SramNonceWidth = 128;
-	input wire [257:0] icache_otp_key_i;
-	input [31:0] fpga_info_i;
-	localparam signed [31:0] rv_core_ibex_reg_pkg_NumAlerts = 4;
-	input wire [15:0] alert_rx_i;
-	output wire [7:0] alert_tx_o;
-	wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + (tlul_pkg_D2HRspIntgWidth + tlul_pkg_DataIntgWidth)) + 1:0] tl_i_toibex;
-	wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 23:0] tl_i_fromibex;
-	wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + (tlul_pkg_D2HRspIntgWidth + tlul_pkg_DataIntgWidth)) + 1:0] tl_d_toibex;
-	wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 23:0] tl_d_fromibex;
-	wire instr_rvalid_d;
-	reg instr_rvalid_q;
-	wire data_rvalid_d;
-	reg data_rvalid_q;
-	assign instr_rvalid_d = instr_mem_req_o & ~instr_mem_we_o;
-	assign data_rvalid_d = data_mem_req_o & ~data_mem_we_o;
-	always @(posedge clk_i)
-		if (~rst_ni) begin
-			instr_rvalid_q <= 1'sb0;
-			data_rvalid_q <= 1'sb0;
-		end
-		else begin
-			instr_rvalid_q <= instr_rvalid_d;
-			data_rvalid_q <= data_rvalid_d;
-		end
-	function automatic [3:0] sv2v_cast_AC3DB;
-		input reg [3:0] inp;
-		sv2v_cast_AC3DB = inp;
-	endfunction
-	noerr_tlul_adapter_sram #(
-		.SramAw(InstrMemAw),
-		.SramDw(32),
-		.Outstanding(1),
-		.ByteAccess(1),
-		.ErrOnWrite(0),
-		.ErrOnRead(0),
-		.CmdIntgCheck(0),
-		.EnableRspIntgGen(0),
-		.EnableDataIntgGen(0),
-		.EnableDataIntgPt(0)
-	) i_instr_tlul_adapter_sram(
-		.clk_i(clk_i),
-		.rst_ni(rst_ni),
-		.tl_i(tl_i_fromibex),
-		.tl_o(tl_i_toibex),
-		.en_ifetch_i(sv2v_cast_AC3DB(4'h6)),
-		.req_o(instr_mem_req_o),
-		.gnt_i(instr_mem_gnt_i),
-		.we_o(instr_mem_we_o),
-		.addr_o(instr_mem_addr_o),
-		.wdata_o(instr_mem_wdata_o),
-		.wmask_o(instr_mem_strb_o),
-		.rdata_i(instr_mem_rdata_i),
-		.rvalid_i(instr_rvalid_q),
-		.rerror_i(2'b00)
-	);
-	noerr_tlul_adapter_sram #(
-		.SramAw(DataMemAw),
-		.SramDw(32),
-		.Outstanding(1),
-		.ByteAccess(1),
-		.ErrOnWrite(0),
-		.ErrOnRead(0),
-		.CmdIntgCheck(0),
-		.EnableRspIntgGen(0),
-		.EnableDataIntgGen(0),
-		.EnableDataIntgPt(0)
-	) i_data_tlul_adapter_sram(
-		.clk_i(clk_i),
-		.rst_ni(rst_ni),
-		.tl_i(tl_d_fromibex),
-		.tl_o(tl_d_toibex),
-		.en_ifetch_i(sv2v_cast_AC3DB(4'h6)),
-		.req_o(data_mem_req_o),
-		.gnt_i(data_mem_gnt_i),
-		.we_o(data_mem_we_o),
-		.addr_o(data_mem_addr_o),
-		.wdata_o(data_mem_wdata_o),
-		.wmask_o(data_mem_strb_o),
-		.rdata_i(data_mem_rdata_i),
-		.rvalid_i(data_rvalid_q),
-		.rerror_i(2'b00)
-	);
-	localparam signed [31:0] ibex_pkg_LfsrWidth = 32;
-	localparam [159:0] ibex_pkg_RndCnstLfsrPermDefault = 160'h1e35ecba467fd1b12e958152c04fa43878a8daed;
-	localparam [31:0] ibex_pkg_RndCnstLfsrSeedDefault = 32'hac533bf4;
-	noerr_rv_core_ibex #(
-		.PMPEnable(1'b0),
-		.PMPGranularity(0),
-		.PMPNumRegions(4),
-		.MHPMCounterNum(0),
-		.MHPMCounterWidth(40),
-		.RV32E(1'b0),
-		.RV32M(32'sd1),
-		.RV32B(32'sd0),
-		.BranchTargetALU(1'b0),
-		.WritebackStage(1'b1),
-		.ICache(1'b0),
-		.ICacheECC(1'b0),
-		.BranchPredictor(1'b0),
-		.DbgTriggerEn(1'b0),
-		.DbgHwBreakNum(1),
-		.RndCnstLfsrSeed(ibex_pkg_RndCnstLfsrSeedDefault),
-		.RndCnstLfsrPerm(ibex_pkg_RndCnstLfsrPermDefault),
-		.SecureIbex(1'b0),
-		.DmHaltAddr(32'h1a110800),
-		.DmExceptionAddr(32'h01a11080)
-	) i_rv_core_ibex(
-		.clk_i(clk_i),
-		.rst_ni(rst_ni),
-		.clk_edn_i(clk_edn_i),
-		.rst_edn_ni(rst_edn_ni),
-		.clk_esc_i(clk_esc_i),
-		.rst_esc_ni(rst_esc_ni),
-		.rst_cpu_n_o(rst_cpu_n_o),
-		.ram_cfg_i(ram_cfg_i),
-		.hart_id_i(hart_id_i),
-		.boot_addr_i(boot_addr_i),
-		.corei_tl_h_o(tl_i_fromibex),
-		.corei_tl_h_i(tl_i_toibex),
-		.cored_tl_h_o(tl_d_fromibex),
-		.cored_tl_h_i(tl_d_toibex),
-		.irq_software_i(irq_software_i),
-		.irq_timer_i(irq_timer_i),
-		.irq_external_i(irq_external_i),
-		.esc_tx_i(esc_tx_i),
-		.esc_rx_o(esc_rx_o),
-		.nmi_wdog_i(nmi_wdog_i),
-		.debug_req_i(debug_req_i),
-		.crash_dump_o(crash_dump_o),
-		.lc_cpu_en_i(lc_cpu_en_i),
-		.pwrmgr_cpu_en_i(pwrmgr_cpu_en_i),
-		.pwrmgr_o(pwrmgr_o),
-		.scan_rst_ni(scan_rst_ni),
-		.scanmode_i(scanmode_i),
-		.cfg_tl_d_i(cfg_tl_d_i),
-		.cfg_tl_d_o(cfg_tl_d_o),
-		.edn_o(edn_o),
-		.edn_i(edn_i),
-		.clk_otp_i(clk_otp_i),
-		.rst_otp_ni(rst_otp_ni),
-		.icache_otp_key_o(icache_otp_key_o),
-		.icache_otp_key_i(icache_otp_key_i),
-		.fpga_info_i(fpga_info_i),
-		.alert_rx_i(alert_rx_i),
-		.alert_tx_o(alert_tx_o)
-	);
-endmodule
+
 module ibex_alu (
 	operator_i,
 	operand_a_i,
@@ -21067,1110 +20811,7 @@ module ibex_wb_stage (
 	assign rf_wdata_wb_o = ({32 {rf_wdata_wb_mux_we[0]}} & rf_wdata_wb_mux[0]) | ({32 {rf_wdata_wb_mux_we[1]}} & rf_wdata_wb_mux[1]);
 	assign rf_we_wb_o = |rf_wdata_wb_mux_we;
 endmodule
-module noerr_rv_core_ibex (
-	clk_i,
-	rst_ni,
-	clk_edn_i,
-	rst_edn_ni,
-	clk_esc_i,
-	rst_esc_ni,
-	rst_cpu_n_o,
-	ram_cfg_i,
-	hart_id_i,
-	boot_addr_i,
-	corei_tl_h_o,
-	corei_tl_h_i,
-	cored_tl_h_o,
-	cored_tl_h_i,
-	irq_software_i,
-	irq_timer_i,
-	irq_external_i,
-	esc_tx_i,
-	esc_rx_o,
-	nmi_wdog_i,
-	debug_req_i,
-	crash_dump_o,
-	lc_cpu_en_i,
-	pwrmgr_cpu_en_i,
-	pwrmgr_o,
-	scan_rst_ni,
-	scanmode_i,
-	cfg_tl_d_i,
-	cfg_tl_d_o,
-	edn_o,
-	edn_i,
-	clk_otp_i,
-	rst_otp_ni,
-	icache_otp_key_o,
-	icache_otp_key_i,
-	fpga_info_i,
-	alert_rx_i,
-	alert_tx_o
-);
-	localparam signed [31:0] rv_core_ibex_reg_pkg_NumAlerts = 4;
-	parameter [3:0] AlertAsyncOn = {rv_core_ibex_reg_pkg_NumAlerts {1'b1}};
-	parameter [0:0] PMPEnable = 1'b1;
-	parameter [31:0] PMPGranularity = 0;
-	parameter [31:0] PMPNumRegions = 16;
-	parameter [31:0] MHPMCounterNum = 10;
-	parameter [31:0] MHPMCounterWidth = 32;
-	parameter [0:0] RV32E = 0;
-	parameter integer RV32M = 32'sd3;
-	parameter integer RV32B = 32'sd2;
-	parameter integer RegFile = 32'sd0;
-	parameter [0:0] BranchTargetALU = 1'b1;
-	parameter [0:0] WritebackStage = 1'b1;
-	parameter [0:0] ICache = 1'b1;
-	parameter [0:0] ICacheECC = 1'b1;
-	parameter [0:0] ICacheScramble = 1'b1;
-	parameter [0:0] BranchPredictor = 1'b0;
-	parameter [0:0] DbgTriggerEn = 1'b1;
-	parameter [31:0] DbgHwBreakNum = 4;
-	parameter [0:0] SecureIbex = 1'b1;
-	localparam signed [31:0] ibex_pkg_LfsrWidth = 32;
-	localparam [31:0] ibex_pkg_RndCnstLfsrSeedDefault = 32'hac533bf4;
-	parameter [31:0] RndCnstLfsrSeed = ibex_pkg_RndCnstLfsrSeedDefault;
-	localparam [159:0] ibex_pkg_RndCnstLfsrPermDefault = 160'h1e35ecba467fd1b12e958152c04fa43878a8daed;
-	parameter [159:0] RndCnstLfsrPerm = ibex_pkg_RndCnstLfsrPermDefault;
-	parameter [31:0] DmHaltAddr = 32'h1a110800;
-	parameter [31:0] DmExceptionAddr = 32'h1a110808;
-	parameter [0:0] PipeLine = 1'b0;
-	localparam [31:0] ibex_pkg_SCRAMBLE_KEY_W = 128;
-	localparam [127:0] ibex_pkg_RndCnstIbexKeyDefault = 128'h14e8cecae3040d5e12286bb3cc113298;
-	parameter [127:0] RndCnstIbexKeyDefault = ibex_pkg_RndCnstIbexKeyDefault;
-	localparam [31:0] ibex_pkg_SCRAMBLE_NONCE_W = 64;
-	localparam [63:0] ibex_pkg_RndCnstIbexNonceDefault = 64'hf79780bc735f3843;
-	parameter [63:0] RndCnstIbexNonceDefault = ibex_pkg_RndCnstIbexNonceDefault;
-	input wire clk_i;
-	input wire rst_ni;
-	input wire clk_edn_i;
-	input wire rst_edn_ni;
-	input wire clk_esc_i;
-	input wire rst_esc_ni;
-	output wire rst_cpu_n_o;
-	input wire [9:0] ram_cfg_i;
-	input wire [31:0] hart_id_i;
-	input wire [31:0] boot_addr_i;
-	localparam signed [31:0] prim_mubi_pkg_MuBi4Width = 4;
-	localparam signed [31:0] tlul_pkg_DataIntgWidth = 7;
-	localparam signed [31:0] tlul_pkg_H2DCmdIntgWidth = 7;
-	localparam signed [31:0] top_pkg_TL_AIW = 8;
-	localparam signed [31:0] top_pkg_TL_AW = 32;
-	localparam signed [31:0] top_pkg_TL_DW = 32;
-	localparam signed [31:0] top_pkg_TL_DBW = top_pkg_TL_DW >> 3;
-	localparam signed [31:0] top_pkg_TL_SZW = $clog2($clog2(top_pkg_TL_DBW) + 1);
-	output wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 23:0] corei_tl_h_o;
-	localparam signed [31:0] tlul_pkg_D2HRspIntgWidth = 7;
-	localparam signed [31:0] top_pkg_TL_DIW = 1;
-	input wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + (tlul_pkg_D2HRspIntgWidth + tlul_pkg_DataIntgWidth)) + 1:0] corei_tl_h_i;
-	output wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 23:0] cored_tl_h_o;
-	input wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + (tlul_pkg_D2HRspIntgWidth + tlul_pkg_DataIntgWidth)) + 1:0] cored_tl_h_i;
-	input wire irq_software_i;
-	input wire irq_timer_i;
-	input wire irq_external_i;
-	input wire [1:0] esc_tx_i;
-	output wire [1:0] esc_rx_o;
-	input wire nmi_wdog_i;
-	input wire debug_req_i;
-	output wire [224:0] crash_dump_o;
-	localparam signed [31:0] lc_ctrl_pkg_TxWidth = 4;
-	input wire [3:0] lc_cpu_en_i;
-	input wire [3:0] pwrmgr_cpu_en_i;
-	output wire [0:0] pwrmgr_o;
-	input scan_rst_ni;
-	input wire [3:0] scanmode_i;
-	input wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 23:0] cfg_tl_d_i;
-	output wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + (tlul_pkg_D2HRspIntgWidth + tlul_pkg_DataIntgWidth)) + 1:0] cfg_tl_d_o;
-	output wire [0:0] edn_o;
-	localparam [31:0] edn_pkg_ENDPOINT_BUS_WIDTH = 32;
-	input wire [33:0] edn_i;
-	input clk_otp_i;
-	input rst_otp_ni;
-	output wire [0:0] icache_otp_key_o;
-	localparam signed [31:0] otp_ctrl_pkg_SramKeyWidth = 128;
-	localparam signed [31:0] otp_ctrl_pkg_SramNonceWidth = 128;
-	input wire [257:0] icache_otp_key_i;
-	input [31:0] fpga_info_i;
-	input wire [15:0] alert_rx_i;
-	output wire [7:0] alert_tx_o;
-	wire [312:0] reg2hw;
-	wire [82:0] hw2reg;
-	localparam [0:0] FifoPass = (PipeLine ? 1'b0 : 1'b1);
-	localparam [31:0] FifoDepth = (PipeLine ? 2 : 0);
-	localparam signed [31:0] NumOutstandingReqs = (ICache ? 8 : 2);
-	wire instr_req;
-	wire instr_gnt;
-	wire instr_rvalid;
-	wire [31:0] instr_addr;
-	wire [31:0] instr_rdata;
-	wire [6:0] instr_rdata_intg;
-	wire instr_err;
-	wire data_req;
-	wire data_gnt;
-	wire data_rvalid;
-	wire data_we;
-	wire [3:0] data_be;
-	wire [31:0] data_addr;
-	wire [31:0] data_wdata;
-	wire [6:0] data_wdata_intg;
-	wire [31:0] data_rdata;
-	wire [6:0] data_rdata_intg;
-	wire data_err;
-	wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 23:0] tl_i_ibex2fifo;
-	wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + (tlul_pkg_D2HRspIntgWidth + tlul_pkg_DataIntgWidth)) + 1:0] tl_i_fifo2ibex;
-	wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 23:0] tl_d_ibex2fifo;
-	wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + (tlul_pkg_D2HRspIntgWidth + tlul_pkg_DataIntgWidth)) + 1:0] tl_d_fifo2ibex;
-	wire core_sleep;
-	wire ibex_top_clk_i;
-	wire addr_trans_rst_ni;
-	assign ibex_top_clk_i = clk_i;
-	assign addr_trans_rst_ni = rst_ni;
-	wire ibus_intg_err;
-	wire dbus_intg_err;
-	wire alert_minor;
-	wire alert_major_internal;
-	wire alert_major_bus;
-	wire double_fault;
-	wire fatal_intg_err;
-	wire fatal_core_err;
-	wire recov_core_err;
-	wire fatal_intg_event;
-	wire fatal_core_event;
-	wire recov_core_event;
-	assign fatal_intg_event = (ibus_intg_err | dbus_intg_err) | alert_major_bus;
-	assign fatal_core_event = alert_major_internal | double_fault;
-	assign recov_core_event = alert_minor;
-	localparam signed [31:0] rv_core_ibex_reg_pkg_NumRegions = 2;
-	wire [129:0] ibus_region_cfg;
-	wire [129:0] dbus_region_cfg;
-	assign rst_cpu_n_o = rst_ni;
-	wire esc_irq_nm;
-	localparam signed [31:0] alert_handler_reg_pkg_N_ESC_SEV = 4;
-	localparam signed [31:0] alert_handler_reg_pkg_PING_CNT_DW = 16;
-	prim_esc_receiver #(
-		.N_ESC_SEV(alert_handler_reg_pkg_N_ESC_SEV),
-		.PING_CNT_DW(alert_handler_reg_pkg_PING_CNT_DW)
-	) u_prim_esc_receiver(
-		.clk_i(clk_esc_i),
-		.rst_ni(rst_esc_ni),
-		.esc_req_o(esc_irq_nm),
-		.esc_rx_o(esc_rx_o),
-		.esc_tx_i(esc_tx_i)
-	);
-	wire alert_irq_nm;
-	prim_flop_2sync #(.Width(1)) u_alert_nmi_sync(
-		.clk_i(clk_i),
-		.rst_ni(rst_ni),
-		.d_i(esc_irq_nm),
-		.q_o(alert_irq_nm)
-	);
-	wire wdog_irq_nm;
-	prim_flop_2sync #(.Width(1)) u_wdog_nmi_sync(
-		.clk_i(clk_i),
-		.rst_ni(rst_ni),
-		.d_i(nmi_wdog_i),
-		.q_o(wdog_irq_nm)
-	);
-	assign hw2reg[77] = 1'b1;
-	assign hw2reg[76] = alert_irq_nm;
-	assign hw2reg[75] = 1'b1;
-	assign hw2reg[74] = wdog_irq_nm;
-	wire irq_nm;
-	assign irq_nm = |(reg2hw[34-:2] & reg2hw[36-:2]);
-	wire [3:0] lc_cpu_en;
-	prim_lc_sync u_lc_sync(
-		.clk_i(clk_i),
-		.rst_ni(rst_ni),
-		.lc_en_i(lc_cpu_en_i),
-		.lc_en_o(lc_cpu_en)
-	);
-	wire [3:0] pwrmgr_cpu_en;
-	prim_lc_sync u_pwrmgr_sync(
-		.clk_i(clk_i),
-		.rst_ni(rst_ni),
-		.lc_en_i(pwrmgr_cpu_en_i),
-		.lc_en_o(pwrmgr_cpu_en)
-	);
-	wire irq_timer_sync;
-	prim_flop_2sync #(.Width(1)) u_intr_timer_sync(
-		.clk_i(clk_i),
-		.rst_ni(rst_ni),
-		.d_i(irq_timer_i),
-		.q_o(irq_timer_sync)
-	);
-	wire irq_software;
-	wire irq_timer;
-	wire irq_external;
-	prim_sec_anchor_buf #(.Width(3)) u_prim_buf_irq(
-		.in_i({irq_software_i, irq_timer_sync, irq_external_i}),
-		.out_o({irq_software, irq_timer, irq_external})
-	);
-	wire key_req;
-	wire key_ack;
-	wire [127:0] key;
-	wire [63:0] nonce;
-	wire unused_seed_valid;
-	localparam signed [31:0] PayLoadW = (ibex_pkg_SCRAMBLE_KEY_W + ibex_pkg_SCRAMBLE_NONCE_W) + 1;
-	prim_sync_reqack_data #(
-		.Width(PayLoadW),
-		.DataSrc2Dst(1'b0)
-	) u_prim_sync_reqack_data(
-		.clk_src_i(clk_i),
-		.rst_src_ni(rst_ni),
-		.clk_dst_i(clk_otp_i),
-		.rst_dst_ni(rst_otp_ni),
-		.req_chk_i(1'b1),
-		.src_req_i(key_req),
-		.src_ack_o(key_ack),
-		.dst_req_o(icache_otp_key_o[0]),
-		.dst_ack_i(icache_otp_key_i[257]),
-		.data_i({icache_otp_key_i[256-:128], icache_otp_key_i[64:1], icache_otp_key_i[0]}),
-		.data_o({key, nonce, unused_seed_valid})
-	);
-	wire unused_nonce;
-	assign unused_nonce = |icache_otp_key_i[128-:128];
-	wire [3:0] local_fetch_enable_d;
-	wire [3:0] local_fetch_enable_q;
-	function automatic [3:0] sv2v_cast_A1913;
-		input reg [3:0] inp;
-		sv2v_cast_A1913 = inp;
-	endfunction
-	assign local_fetch_enable_d = (fatal_core_err ? sv2v_cast_A1913(4'b1010) : local_fetch_enable_q);
-	prim_lc_sender #(
-		.AsyncOn(1),
-		.ResetValueIsOn(1)
-	) u_prim_lc_sender(
-		.clk_i(clk_i),
-		.rst_ni(rst_ni),
-		.lc_en_i(local_fetch_enable_d),
-		.lc_en_o(local_fetch_enable_q)
-	);
-	wire [3:0] fetch_enable;
-	function automatic [3:0] lc_ctrl_pkg_lc_tx_and;
-		input reg [3:0] a;
-		input reg [3:0] b;
-		input reg [3:0] act;
-		reg [3:0] a_in;
-		reg [3:0] b_in;
-		reg [3:0] act_in;
-		reg [3:0] out;
-		begin
-			a_in = a;
-			b_in = b;
-			act_in = act;
-			begin : sv2v_autoblock_1
-				reg signed [31:0] k;
-				for (k = 0; k < lc_ctrl_pkg_TxWidth; k = k + 1)
-					if (act_in[k])
-						out[k] = a_in[k] && b_in[k];
-					else
-						out[k] = a_in[k] || b_in[k];
-			end
-			lc_ctrl_pkg_lc_tx_and = out;
-		end
-	endfunction
-	function automatic [3:0] lc_ctrl_pkg_lc_tx_and_hi;
-		input reg [3:0] a;
-		input reg [3:0] b;
-		lc_ctrl_pkg_lc_tx_and_hi = lc_ctrl_pkg_lc_tx_and(a, b, sv2v_cast_A1913(4'b0101));
-	endfunction
-	assign fetch_enable = lc_ctrl_pkg_lc_tx_and_hi(local_fetch_enable_q, lc_ctrl_pkg_lc_tx_and_hi(lc_cpu_en[0+:lc_ctrl_pkg_TxWidth], pwrmgr_cpu_en[0+:lc_ctrl_pkg_TxWidth]));
-	wire [159:0] crash_dump;
-	function automatic [3:0] sv2v_cast_38B98;
-		input reg [3:0] inp;
-		sv2v_cast_38B98 = inp;
-	endfunction
-	function automatic prim_mubi_pkg_mubi4_test_true_strict;
-		input reg [3:0] val;
-		prim_mubi_pkg_mubi4_test_true_strict = sv2v_cast_38B98(4'h6) == val;
-	endfunction
-	ibex_top #(
-		.PMPEnable(PMPEnable),
-		.PMPGranularity(PMPGranularity),
-		.PMPNumRegions(PMPNumRegions),
-		.MHPMCounterNum(MHPMCounterNum),
-		.MHPMCounterWidth(MHPMCounterWidth),
-		.RV32E(RV32E),
-		.RV32M(RV32M),
-		.RV32B(RV32B),
-		.RegFile(RegFile),
-		.BranchTargetALU(BranchTargetALU),
-		.WritebackStage(WritebackStage),
-		.ICache(ICache),
-		.ICacheECC(ICacheECC),
-		.ICacheScramble(ICacheScramble),
-		.BranchPredictor(BranchPredictor),
-		.DbgTriggerEn(DbgTriggerEn),
-		.DbgHwBreakNum(DbgHwBreakNum),
-		.SecureIbex(SecureIbex),
-		.RndCnstLfsrSeed(RndCnstLfsrSeed),
-		.RndCnstLfsrPerm(RndCnstLfsrPerm),
-		.RndCnstIbexKey(RndCnstIbexKeyDefault),
-		.RndCnstIbexNonce(RndCnstIbexNonceDefault),
-		.DmHaltAddr(DmHaltAddr),
-		.DmExceptionAddr(DmExceptionAddr)
-	) u_core(
-		.clk_i(ibex_top_clk_i),
-		.rst_ni(rst_ni),
-		.test_en_i(prim_mubi_pkg_mubi4_test_true_strict(scanmode_i)),
-		.scan_rst_ni(scan_rst_ni),
-		.ram_cfg_i(ram_cfg_i),
-		.hart_id_i(hart_id_i),
-		.boot_addr_i(boot_addr_i),
-		.instr_req_o(instr_req),
-		.instr_gnt_i(instr_gnt),
-		.instr_rvalid_i(instr_rvalid),
-		.instr_addr_o(instr_addr),
-		.instr_rdata_i(instr_rdata),
-		.instr_rdata_intg_i(instr_rdata_intg),
-		.instr_err_i(instr_err),
-		.data_req_o(data_req),
-		.data_gnt_i(data_gnt),
-		.data_rvalid_i(data_rvalid),
-		.data_we_o(data_we),
-		.data_be_o(data_be),
-		.data_addr_o(data_addr),
-		.data_wdata_o(data_wdata),
-		.data_wdata_intg_o(data_wdata_intg),
-		.data_rdata_i(data_rdata),
-		.data_rdata_intg_i(data_rdata_intg),
-		.data_err_i(data_err),
-		.irq_software_i(irq_software),
-		.irq_timer_i(irq_timer),
-		.irq_external_i(irq_external),
-		.irq_fast_i(1'sb0),
-		.irq_nm_i(irq_nm),
-		.debug_req_i(debug_req_i),
-		.crash_dump_o(crash_dump),
-		.scramble_key_valid_i(key_ack),
-		.scramble_key_i(key),
-		.scramble_nonce_i(nonce),
-		.scramble_req_o(key_req),
-		.double_fault_seen_o(double_fault),
-		.fetch_enable_i(fetch_enable),
-		.alert_minor_o(alert_minor),
-		.alert_major_internal_o(alert_major_internal),
-		.alert_major_bus_o(alert_major_bus),
-		.core_sleep_o(core_sleep)
-	);
-	reg core_sleep_q;
-	always @(posedge clk_i or negedge rst_ni)
-		if (!rst_ni)
-			core_sleep_q <= 1'sb0;
-		else
-			core_sleep_q <= core_sleep;
-	prim_buf #(.Width(1)) u_core_sleeping_buf(
-		.in_i(core_sleep_q),
-		.out_o(pwrmgr_o[0])
-	);
-	reg prev_valid;
-	reg [31:0] prev_exception_pc;
-	reg [31:0] prev_exception_addr;
-	assign crash_dump_o[159-:160] = crash_dump;
-	assign crash_dump_o[224] = prev_valid;
-	assign crash_dump_o[223-:32] = prev_exception_pc;
-	assign crash_dump_o[191-:32] = prev_exception_addr;
-	always @(posedge clk_i or negedge rst_ni)
-		if (!rst_ni) begin
-			prev_valid <= 1'sb0;
-			prev_exception_pc <= 1'sb0;
-			prev_exception_addr <= 1'sb0;
-		end
-		else if (double_fault) begin
-			prev_valid <= 1'b1;
-			prev_exception_pc <= crash_dump[63-:32];
-			prev_exception_addr <= crash_dump[31-:32];
-		end
-	wire [31:0] instr_addr_trans;
-	rv_core_addr_trans #(
-		.AddrWidth(32),
-		.NumRegions(rv_core_ibex_reg_pkg_NumRegions)
-	) u_ibus_trans(
-		.clk_i(clk_i),
-		.rst_ni(addr_trans_rst_ni),
-		.region_cfg_i(ibus_region_cfg),
-		.addr_i(instr_addr),
-		.addr_o(instr_addr_trans)
-	);
-	assign instr_err = 0;
-	wire [6:0] instr_wdata_intg;
-	wire [31:0] unused_data;
-	function automatic [38:0] sv2v_cast_39;
-		input reg [38:0] inp;
-		sv2v_cast_39 = inp;
-	endfunction
-	function automatic [38:0] prim_secded_pkg_prim_secded_inv_39_32_enc;
-		input reg [31:0] data_i;
-		reg [38:0] data_o;
-		begin
-			data_o = sv2v_cast_39(data_i);
-			data_o[32] = ^(data_o & 39'h002606bd25);
-			data_o[33] = ^(data_o & 39'h00deba8050);
-			data_o[34] = ^(data_o & 39'h00413d89aa);
-			data_o[35] = ^(data_o & 39'h0031234ed1);
-			data_o[36] = ^(data_o & 39'h00c2c1323b);
-			data_o[37] = ^(data_o & 39'h002dcc624c);
-			data_o[38] = ^(data_o & 39'h0098505586);
-			data_o = data_o ^ 39'h2a00000000;
-			prim_secded_pkg_prim_secded_inv_39_32_enc = data_o;
-		end
-	endfunction
-	assign {instr_wdata_intg, unused_data} = prim_secded_pkg_prim_secded_inv_39_32_enc(instr_rdata);
-	tlul_adapter_host #(
-		.MAX_REQS(NumOutstandingReqs),
-		.EnableDataIntgGen(~SecureIbex)
-	) tl_adapter_host_i_ibex(
-		.clk_i(clk_i),
-		.rst_ni(rst_ni),
-		.req_i(instr_req),
-		.instr_type_i(sv2v_cast_38B98(4'h6)),
-		.gnt_o(instr_gnt),
-		.addr_i(instr_addr_trans),
-		.we_i(1'b0),
-		.wdata_i(32'b00000000000000000000000000000000),
-		.wdata_intg_i(instr_wdata_intg),
-		.be_i(4'hf),
-		.valid_o(instr_rvalid),
-		.rdata_o(instr_rdata),
-		.rdata_intg_o(instr_rdata_intg),
-		.intg_err_o(ibus_intg_err),
-		.tl_o(tl_i_ibex2fifo),
-		.tl_i(tl_i_fifo2ibex)
-	);
-	tlul_fifo_sync #(
-		.ReqPass(FifoPass),
-		.RspPass(FifoPass),
-		.ReqDepth(FifoDepth),
-		.RspDepth(FifoDepth)
-	) fifo_i(
-		.clk_i(clk_i),
-		.rst_ni(rst_ni),
-		.tl_h_i(tl_i_ibex2fifo),
-		.tl_h_o(tl_i_fifo2ibex),
-		.tl_d_o(corei_tl_h_o),
-		.tl_d_i(corei_tl_h_i),
-		.spare_req_i(1'b0),
-		.spare_rsp_i(1'b0)
-	);
-	wire [31:0] data_addr_trans;
-	rv_core_addr_trans #(
-		.AddrWidth(32),
-		.NumRegions(rv_core_ibex_reg_pkg_NumRegions)
-	) u_dbus_trans(
-		.clk_i(clk_i),
-		.rst_ni(addr_trans_rst_ni),
-		.region_cfg_i(dbus_region_cfg),
-		.addr_i(data_addr),
-		.addr_o(data_addr_trans)
-	);
-	assign data_err = 0;
-	tlul_adapter_host #(
-		.MAX_REQS(2),
-		.EnableDataIntgGen(~SecureIbex)
-	) tl_adapter_host_d_ibex(
-		.clk_i(clk_i),
-		.rst_ni(rst_ni),
-		.req_i(data_req),
-		.instr_type_i(sv2v_cast_38B98(4'h9)),
-		.gnt_o(data_gnt),
-		.addr_i(data_addr_trans),
-		.we_i(data_we),
-		.wdata_i(data_wdata),
-		.wdata_intg_i(data_wdata_intg),
-		.be_i(data_be),
-		.valid_o(data_rvalid),
-		.rdata_o(data_rdata),
-		.rdata_intg_o(data_rdata_intg),
-		.intg_err_o(dbus_intg_err),
-		.tl_o(tl_d_ibex2fifo),
-		.tl_i(tl_d_fifo2ibex)
-	);
-	tlul_fifo_sync #(
-		.ReqPass(FifoPass),
-		.RspPass(FifoPass),
-		.ReqDepth(FifoDepth),
-		.RspDepth(FifoDepth)
-	) fifo_d(
-		.clk_i(clk_i),
-		.rst_ni(rst_ni),
-		.tl_h_i(tl_d_ibex2fifo),
-		.tl_h_o(tl_d_fifo2ibex),
-		.tl_d_o(cored_tl_h_o),
-		.tl_d_i(cored_tl_h_i),
-		.spare_req_i(1'b0),
-		.spare_rsp_i(1'b0)
-	);
-	wire intg_err;
-	wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 23:0] tl_win_h2d;
-	wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + (tlul_pkg_D2HRspIntgWidth + tlul_pkg_DataIntgWidth)) + 1:0] tl_win_d2h;
-	rv_core_ibex_cfg_reg_top u_reg_cfg(
-		.clk_i(clk_i),
-		.rst_ni(rst_ni),
-		.tl_i(cfg_tl_d_i),
-		.tl_o(cfg_tl_d_o),
-		.reg2hw(reg2hw),
-		.hw2reg(hw2reg),
-		.intg_err_o(intg_err),
-		.tl_win_o(tl_win_h2d),
-		.tl_win_i(tl_win_d2h),
-		.devmode_i(1'b1)
-	);
-	genvar i;
-	generate
-		for (i = 0; i < rv_core_ibex_reg_pkg_NumRegions; i = i + 1) begin : gen_ibus_region_cfgs
-			assign ibus_region_cfg[(i * 65) + 64] = reg2hw[295 + i+:1];
-			assign ibus_region_cfg[(i * 65) + 63-:32] = reg2hw[231 + (i * 32)+:32];
-			assign ibus_region_cfg[(i * 65) + 31-:32] = reg2hw[167 + (i * 32)+:32];
-		end
-		for (i = 0; i < rv_core_ibex_reg_pkg_NumRegions; i = i + 1) begin : gen_dbus_region_cfgs
-			assign dbus_region_cfg[(i * 65) + 64] = reg2hw[165 + i+:1];
-			assign dbus_region_cfg[(i * 65) + 63-:32] = reg2hw[101 + (i * 32)+:32];
-			assign dbus_region_cfg[(i * 65) + 31-:32] = reg2hw[37 + (i * 32)+:32];
-		end
-	endgenerate
-	assign fatal_intg_err = fatal_intg_event;
-	assign fatal_core_err = fatal_core_event;
-	assign recov_core_err = recov_core_event;
-	assign hw2reg[73] = 1'b1;
-	assign hw2reg[72] = intg_err;
-	assign hw2reg[71] = 1'b1;
-	assign hw2reg[70] = fatal_intg_err;
-	assign hw2reg[69] = 1'b1;
-	assign hw2reg[68] = fatal_core_err;
-	assign hw2reg[67] = 1'b1;
-	assign hw2reg[66] = recov_core_err;
-	wire [3:0] alert_test;
-	assign alert_test[0] = reg2hw[312] & reg2hw[311];
-	assign alert_test[1] = reg2hw[310] & reg2hw[309];
-	assign alert_test[2] = reg2hw[308] & reg2hw[307];
-	assign alert_test[3] = reg2hw[306] & reg2hw[305];
-	localparam [3:0] AlertFatal = 4'b0101;
-	wire [3:0] alert_events;
-	wire [3:0] alert_acks;
-	function automatic prim_mubi_pkg_mubi4_test_true_loose;
-		input reg [3:0] val;
-		prim_mubi_pkg_mubi4_test_true_loose = sv2v_cast_38B98(4'h9) != val;
-	endfunction
-	assign alert_events[0] = prim_mubi_pkg_mubi4_test_true_loose(sv2v_cast_38B98(reg2hw[300-:4]));
-	assign alert_events[1] = prim_mubi_pkg_mubi4_test_true_loose(sv2v_cast_38B98(reg2hw[304-:4]));
-	assign alert_events[2] = (intg_err | fatal_intg_err) | fatal_core_err;
-	assign alert_events[3] = recov_core_err;
-	wire unused_alert_acks;
-	assign unused_alert_acks = |alert_acks;
-	assign hw2reg[78] = alert_acks[1];
-	assign hw2reg[82-:4] = sv2v_cast_38B98(4'h9);
-	generate
-		for (i = 0; i < rv_core_ibex_reg_pkg_NumAlerts; i = i + 1) begin : gen_alert_senders
-			prim_alert_sender #(
-				.AsyncOn(AlertAsyncOn[0]),
-				.IsFatal(AlertFatal[i])
-			) u_alert_sender(
-				.clk_i(clk_i),
-				.rst_ni(rst_ni),
-				.alert_test_i(alert_test[i]),
-				.alert_req_i(alert_events[i]),
-				.alert_ack_o(alert_acks[i]),
-				.alert_rx_i(alert_rx_i[i * 4+:4]),
-				.alert_tx_o(alert_tx_o[i * 2+:2])
-			);
-		end
-	endgenerate
-	reg [31:0] rnd_data_q;
-	reg [31:0] rnd_data_d;
-	reg rnd_valid_q;
-	reg rnd_valid_d;
-	reg rnd_fips_q;
-	reg rnd_fips_d;
-	wire edn_req;
-	wire [31:0] edn_data;
-	wire edn_ack;
-	wire edn_fips;
-	always @(*) begin
-		rnd_valid_d = rnd_valid_q;
-		rnd_data_d = rnd_data_q;
-		rnd_fips_d = rnd_fips_q;
-		if (reg2hw[0]) begin
-			rnd_valid_d = 1'sb0;
-			rnd_data_d = 1'sb0;
-			rnd_fips_d = 1'sb0;
-		end
-		else if (edn_req && edn_ack) begin
-			rnd_valid_d = 1'b1;
-			rnd_data_d = edn_data;
-			rnd_fips_d = edn_fips;
-		end
-	end
-	always @(posedge clk_i or negedge rst_ni)
-		if (!rst_ni) begin
-			rnd_valid_q <= 1'sb0;
-			rnd_data_q <= 1'sb0;
-			rnd_fips_q <= 1'sb0;
-		end
-		else begin
-			rnd_valid_q <= rnd_valid_d;
-			rnd_data_q <= rnd_data_d;
-			rnd_fips_q <= rnd_fips_d;
-		end
-	assign edn_req = ~rnd_valid_q;
-	prim_edn_req #(.OutWidth(32)) u_edn_if(
-		.clk_i(clk_i),
-		.rst_ni(rst_ni),
-		.req_chk_i(1'b1),
-		.req_i(edn_req),
-		.ack_o(edn_ack),
-		.data_o(edn_data),
-		.fips_o(edn_fips),
-		.clk_edn_i(clk_edn_i),
-		.rst_edn_ni(rst_edn_ni),
-		.edn_o(edn_o),
-		.edn_i(edn_i)
-	);
-	assign hw2reg[65-:32] = rnd_data_q;
-	assign hw2reg[33] = rnd_valid_q;
-	assign hw2reg[32] = rnd_fips_q;
-	wire unused_reg2hw;
-	assign unused_reg2hw = |reg2hw[32-:32];
-	assign hw2reg[31-:32] = fpga_info_i;
-	localparam signed [31:0] TlH2DWidth = 1 * ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 24);
-	localparam signed [31:0] TlD2HWidth = 1 * ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + (tlul_pkg_D2HRspIntgWidth + tlul_pkg_DataIntgWidth)) + 2);
-	wire [TlH2DWidth - 1:0] tl_win_h2d_int;
-	wire [TlD2HWidth - 1:0] tl_win_d2h_int;
-	wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + (tlul_pkg_D2HRspIntgWidth + tlul_pkg_DataIntgWidth)) + 1:0] tl_win_d2h_err_rsp;
-	prim_buf #(.Width(TlH2DWidth)) u_tlul_req_buf(
-		.in_i(tl_win_h2d),
-		.out_o(tl_win_h2d_int)
-	);
-	prim_buf #(.Width(TlD2HWidth)) u_tlul_rsp_buf(
-		.in_i(tl_win_d2h_err_rsp),
-		.out_o(tl_win_d2h_int)
-	);
-	function automatic [((((((7 + top_pkg_TL_SZW) + (32'sd8 + 32'sd1)) + 32'sd32) + (32'sd7 + 32'sd7)) + 1) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + (tlul_pkg_D2HRspIntgWidth + tlul_pkg_DataIntgWidth)) + 2 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + (tlul_pkg_D2HRspIntgWidth + tlul_pkg_DataIntgWidth)) + 1)) - 1:0] sv2v_cast_51793;
-		input reg [((((((7 + top_pkg_TL_SZW) + (32'sd8 + 32'sd1)) + 32'sd32) + (32'sd7 + 32'sd7)) + 1) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + (tlul_pkg_D2HRspIntgWidth + tlul_pkg_DataIntgWidth)) + 2 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + (tlul_pkg_D2HRspIntgWidth + tlul_pkg_DataIntgWidth)) + 1)) - 1:0] inp;
-		sv2v_cast_51793 = inp;
-	endfunction
-	assign tl_win_d2h = sv2v_cast_51793(tl_win_d2h_int);
-	wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 23:0] tl_win_h2d_int_tmp;
-	function automatic [(((((7 + top_pkg_TL_SZW) + (32'sd8 + 32'sd32)) + top_pkg_TL_DBW) + 55) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 24 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 23)) - 1:0] sv2v_cast_E9713;
-		input reg [(((((7 + top_pkg_TL_SZW) + (32'sd8 + 32'sd32)) + top_pkg_TL_DBW) + 55) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 24 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 23)) - 1:0] inp;
-		sv2v_cast_E9713 = inp;
-	endfunction
-	assign tl_win_h2d_int_tmp = sv2v_cast_E9713(tl_win_h2d_int);
-	tlul_err_resp u_sim_win_rsp(
-		.clk_i(clk_i),
-		.rst_ni(rst_ni),
-		.tl_h_i(tl_win_h2d_int_tmp),
-		.tl_h_o(tl_win_d2h_err_rsp)
-	);
-endmodule
-module noerr_tlul_adapter_sram (
-	clk_i,
-	rst_ni,
-	tl_i,
-	tl_o,
-	en_ifetch_i,
-	req_o,
-	req_type_o,
-	gnt_i,
-	we_o,
-	addr_o,
-	wdata_o,
-	wmask_o,
-	intg_error_o,
-	rdata_i,
-	rvalid_i,
-	rerror_i
-);
-	parameter signed [31:0] SramAw = 12;
-	parameter signed [31:0] SramDw = 32;
-	parameter signed [31:0] Outstanding = 1;
-	parameter [0:0] ByteAccess = 1;
-	parameter [0:0] ErrOnWrite = 0;
-	parameter [0:0] ErrOnRead = 0;
-	parameter [0:0] CmdIntgCheck = 0;
-	parameter [0:0] EnableRspIntgGen = 0;
-	parameter [0:0] EnableDataIntgGen = 0;
-	parameter [0:0] EnableDataIntgPt = 0;
-	parameter [0:0] SecFifoPtr = 0;
-	localparam signed [31:0] top_pkg_TL_DW = 32;
-	localparam signed [31:0] WidthMult = SramDw / top_pkg_TL_DW;
-	localparam signed [31:0] tlul_pkg_DataIntgWidth = 7;
-	localparam signed [31:0] IntgWidth = tlul_pkg_DataIntgWidth * WidthMult;
-	localparam signed [31:0] DataOutW = (EnableDataIntgPt ? SramDw + IntgWidth : SramDw);
-	input clk_i;
-	input rst_ni;
-	localparam signed [31:0] prim_mubi_pkg_MuBi4Width = 4;
-	localparam signed [31:0] tlul_pkg_H2DCmdIntgWidth = 7;
-	localparam signed [31:0] top_pkg_TL_AIW = 8;
-	localparam signed [31:0] top_pkg_TL_AW = 32;
-	localparam signed [31:0] top_pkg_TL_DBW = top_pkg_TL_DW >> 3;
-	localparam signed [31:0] top_pkg_TL_SZW = $clog2($clog2(top_pkg_TL_DBW) + 1);
-	input wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 23:0] tl_i;
-	localparam signed [31:0] tlul_pkg_D2HRspIntgWidth = 7;
-	localparam signed [31:0] top_pkg_TL_DIW = 1;
-	output wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + (tlul_pkg_D2HRspIntgWidth + tlul_pkg_DataIntgWidth)) + 1:0] tl_o;
-	input wire [3:0] en_ifetch_i;
-	output wire req_o;
-	output wire [3:0] req_type_o;
-	input gnt_i;
-	output wire we_o;
-	output wire [SramAw - 1:0] addr_o;
-	output wire [DataOutW - 1:0] wdata_o;
-	output wire [DataOutW - 1:0] wmask_o;
-	output wire intg_error_o;
-	input [DataOutW - 1:0] rdata_i;
-	input rvalid_i;
-	input [1:0] rerror_i;
-	localparam signed [31:0] SramByte = SramDw / 8;
-	function automatic integer prim_util_pkg_vbits;
-		input integer value;
-		prim_util_pkg_vbits = (value == 1 ? 1 : $clog2(value));
-	endfunction
-	localparam signed [31:0] DataBitWidth = prim_util_pkg_vbits(SramByte);
-	localparam signed [31:0] WoffsetWidth = (SramByte == top_pkg_TL_DBW ? 1 : DataBitWidth - prim_util_pkg_vbits(top_pkg_TL_DBW));
-	wire error_det;
-	wire error_internal;
-	wire wr_attr_error;
-	wire instr_error;
-	wire wr_vld_error;
-	wire rd_vld_error;
-	wire rsp_fifo_error;
-	wire intg_error;
-	wire tlul_error;
-	generate
-		if (CmdIntgCheck) begin : gen_cmd_intg_check
-			tlul_cmd_intg_chk u_cmd_intg_chk(
-				.tl_i(tl_i),
-				.err_o(intg_error)
-			);
-		end
-		else begin : gen_no_cmd_intg_check
-			assign intg_error = 1'sb0;
-		end
-	endgenerate
-	reg intg_error_q;
-	always @(posedge clk_i or negedge rst_ni)
-		if (!rst_ni)
-			intg_error_q <= 1'sb0;
-		else if (intg_error || rsp_fifo_error)
-			intg_error_q <= 1'b1;
-	assign intg_error_o = (intg_error | rsp_fifo_error) | intg_error_q;
-	assign wr_attr_error = ((tl_i[6 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 55)))-:((6 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 55)))) >= (3 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 56)))) ? ((6 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 55)))) - (3 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 56))))) + 1 : ((3 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 56)))) - (6 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 55))))) + 1)] == 3'h0) || (tl_i[6 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 55)))-:((6 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 55)))) >= (3 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 56)))) ? ((6 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 55)))) - (3 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 56))))) + 1 : ((3 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 56)))) - (6 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 55))))) + 1)] == 3'h1) ? (ByteAccess == 0 ? (tl_i[top_pkg_TL_DBW + 55-:((top_pkg_TL_DBW + 55) >= 56 ? top_pkg_TL_DBW : 57 - (top_pkg_TL_DBW + 55))] != {((top_pkg_TL_DBW + 55) >= 56 ? top_pkg_TL_DBW : 57 - (top_pkg_TL_DBW + 55)) * 1 {1'sb1}}) || (tl_i[top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 55)))-:((top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 55))) >= ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 56)) ? ((top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 55)))) - (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 56)))) + 1 : ((top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 56))) - (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 55))))) + 1)] != 2'h2) : 1'b0) : 1'b0);
-	function automatic [3:0] sv2v_cast_A2CB9;
-		input reg [3:0] inp;
-		sv2v_cast_A2CB9 = inp;
-	endfunction
-	function automatic prim_mubi_pkg_mubi4_test_false_loose;
-		input reg [3:0] val;
-		prim_mubi_pkg_mubi4_test_false_loose = sv2v_cast_A2CB9(4'h6) != val;
-	endfunction
-	function automatic prim_mubi_pkg_mubi4_test_invalid;
-		input reg [3:0] val;
-		prim_mubi_pkg_mubi4_test_invalid = ~(|{((sv2v_cast_A2CB9(4'h6) ^ (val ^ val)) === (val ^ (sv2v_cast_A2CB9(4'h6) ^ sv2v_cast_A2CB9(4'h6)))) & ((((val ^ val) ^ (sv2v_cast_A2CB9(4'h6) ^ sv2v_cast_A2CB9(4'h6))) === (sv2v_cast_A2CB9(4'h6) ^ sv2v_cast_A2CB9(4'h6))) | 1'bx), ((sv2v_cast_A2CB9(4'h9) ^ (val ^ val)) === (val ^ (sv2v_cast_A2CB9(4'h9) ^ sv2v_cast_A2CB9(4'h9)))) & ((((val ^ val) ^ (sv2v_cast_A2CB9(4'h9) ^ sv2v_cast_A2CB9(4'h9))) === (sv2v_cast_A2CB9(4'h9) ^ sv2v_cast_A2CB9(4'h9))) | 1'bx)});
-	endfunction
-	function automatic prim_mubi_pkg_mubi4_test_true_strict;
-		input reg [3:0] val;
-		prim_mubi_pkg_mubi4_test_true_strict = sv2v_cast_A2CB9(4'h6) == val;
-	endfunction
-	assign instr_error = prim_mubi_pkg_mubi4_test_invalid(tl_i[18-:4]) | (prim_mubi_pkg_mubi4_test_true_strict(tl_i[18-:4]) & prim_mubi_pkg_mubi4_test_false_loose(en_ifetch_i));
-	generate
-		if (ErrOnWrite == 1) begin : gen_no_writes
-			assign wr_vld_error = tl_i[6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 55))))-:((6 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 55)))) >= (3 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 56)))) ? ((6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 55))))) - (3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 56)))))) + 1 : ((3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 56))))) - (6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 55)))))) + 1)] != 3'h4;
-		end
-		else begin : gen_writes_allowed
-			assign wr_vld_error = 1'b0;
-		end
-		if (ErrOnRead == 1) begin : gen_no_reads
-			assign rd_vld_error = tl_i[6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 55))))-:((6 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 55)))) >= (3 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 56)))) ? ((6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 55))))) - (3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 56)))))) + 1 : ((3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 56))))) - (6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 55)))))) + 1)] == 3'h4;
-		end
-		else begin : gen_reads_allowed
-			assign rd_vld_error = 1'b0;
-		end
-	endgenerate
-	tlul_err u_err(
-		.clk_i(clk_i),
-		.rst_ni(rst_ni),
-		.tl_i(tl_i),
-		.err_o(tlul_error)
-	);
-	assign error_det = ((((wr_attr_error | wr_vld_error) | rd_vld_error) | instr_error) | tlul_error) | intg_error;
-	wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 23:0] tl_i_int;
-	wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + (tlul_pkg_D2HRspIntgWidth + tlul_pkg_DataIntgWidth)) + 1:0] tl_o_int;
-	wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + (tlul_pkg_D2HRspIntgWidth + tlul_pkg_DataIntgWidth)) + 1:0] tl_out;
-	wire unused_tl_i_int;
-	assign unused_tl_i_int = ^tl_i_int;
-	tlul_rsp_intg_gen #(
-		.EnableRspIntgGen(EnableRspIntgGen),
-		.EnableDataIntgGen(EnableDataIntgGen)
-	) u_rsp_gen(
-		.tl_i(tl_out),
-		.tl_o(tl_o)
-	);
-	assign error_internal = 0;
-	tlul_sram_byte #(
-		.EnableIntg((ByteAccess & EnableDataIntgPt) & !ErrOnWrite),
-		.Outstanding(Outstanding)
-	) u_sram_byte(
-		.clk_i(clk_i),
-		.rst_ni(rst_ni),
-		.tl_i(tl_i),
-		.tl_o(tl_out),
-		.tl_sram_o(tl_i_int),
-		.tl_sram_i(tl_o_int),
-		.error_i(error_det)
-	);
-	localparam signed [31:0] SramReqFifoWidth = top_pkg_TL_DBW + WoffsetWidth;
-	localparam signed [31:0] ReqFifoWidth = (7 + top_pkg_TL_SZW) + top_pkg_TL_AIW;
-	localparam signed [31:0] RspFifoWidth = (((top_pkg_TL_DW + tlul_pkg_DataIntgWidth) + 0) >= 0 ? (top_pkg_TL_DW + tlul_pkg_DataIntgWidth) + 1 : 1 - ((top_pkg_TL_DW + tlul_pkg_DataIntgWidth) + 0));
-	wire reqfifo_wvalid;
-	wire reqfifo_wready;
-	wire reqfifo_rvalid;
-	wire reqfifo_rready;
-	wire [((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) - 1:0] reqfifo_wdata;
-	wire [((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) - 1:0] reqfifo_rdata;
-	wire sramreqfifo_wvalid;
-	wire sramreqfifo_wready;
-	wire sramreqfifo_rready;
-	wire [(top_pkg_TL_DBW + WoffsetWidth) - 1:0] sramreqfifo_wdata;
-	wire [(top_pkg_TL_DBW + WoffsetWidth) - 1:0] sramreqfifo_rdata;
-	wire rspfifo_wvalid;
-	wire rspfifo_wready;
-	wire rspfifo_rvalid;
-	wire rspfifo_rready;
-	wire [(top_pkg_TL_DW + tlul_pkg_DataIntgWidth) + 0:0] rspfifo_wdata;
-	wire [(top_pkg_TL_DW + tlul_pkg_DataIntgWidth) + 0:0] rspfifo_rdata;
-	wire a_ack;
-	wire d_ack;
-	wire sram_ack;
-	assign a_ack = tl_i_int[7 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 55))))] & tl_o_int[0];
-	assign d_ack = tl_o_int[7 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + ((tlul_pkg_D2HRspIntgWidth + tlul_pkg_DataIntgWidth) + 1)))))] & tl_i_int[0];
-	assign sram_ack = req_o & gnt_i;
-	reg d_valid;
-	reg d_error;
-	always @(*) begin
-		d_valid = 1'b0;
-		if (reqfifo_rvalid) begin
-			if (reqfifo_rdata[1 + (prim_mubi_pkg_MuBi4Width + (top_pkg_TL_SZW + 7))])
-				d_valid = 1'b1;
-			else if (reqfifo_rdata[3 + (prim_mubi_pkg_MuBi4Width + (top_pkg_TL_SZW + 7))-:((7 + (top_pkg_TL_SZW + 7)) >= (5 + (top_pkg_TL_SZW + 8)) ? ((3 + (prim_mubi_pkg_MuBi4Width + (top_pkg_TL_SZW + 7))) - (1 + (prim_mubi_pkg_MuBi4Width + (top_pkg_TL_SZW + 8)))) + 1 : ((1 + (prim_mubi_pkg_MuBi4Width + (top_pkg_TL_SZW + 8))) - (3 + (prim_mubi_pkg_MuBi4Width + (top_pkg_TL_SZW + 7)))) + 1)] == 2'd1)
-				d_valid = rspfifo_rvalid;
-			else
-				d_valid = 1'b1;
-		end
-		else
-			d_valid = 1'b0;
-	end
-	always @(*) begin
-		d_error = 1'b0;
-		if (reqfifo_rvalid) begin
-			if (reqfifo_rdata[3 + (prim_mubi_pkg_MuBi4Width + (top_pkg_TL_SZW + 7))-:((7 + (top_pkg_TL_SZW + 7)) >= (5 + (top_pkg_TL_SZW + 8)) ? ((3 + (prim_mubi_pkg_MuBi4Width + (top_pkg_TL_SZW + 7))) - (1 + (prim_mubi_pkg_MuBi4Width + (top_pkg_TL_SZW + 8)))) + 1 : ((1 + (prim_mubi_pkg_MuBi4Width + (top_pkg_TL_SZW + 8))) - (3 + (prim_mubi_pkg_MuBi4Width + (top_pkg_TL_SZW + 7)))) + 1)] == 2'd1)
-				d_error = rspfifo_rdata[0] | reqfifo_rdata[1 + (prim_mubi_pkg_MuBi4Width + (top_pkg_TL_SZW + 7))];
-			else
-				d_error = reqfifo_rdata[1 + (prim_mubi_pkg_MuBi4Width + (top_pkg_TL_SZW + 7))];
-		end
-		else
-			d_error = 1'b0;
-	end
-	wire vld_rd_rsp;
-	assign vld_rd_rsp = ((d_valid & reqfifo_rvalid) & rspfifo_rvalid) & (reqfifo_rdata[3 + (prim_mubi_pkg_MuBi4Width + (top_pkg_TL_SZW + 7))-:((7 + (top_pkg_TL_SZW + 7)) >= (5 + (top_pkg_TL_SZW + 8)) ? ((3 + (prim_mubi_pkg_MuBi4Width + (top_pkg_TL_SZW + 7))) - (1 + (prim_mubi_pkg_MuBi4Width + (top_pkg_TL_SZW + 8)))) + 1 : ((1 + (prim_mubi_pkg_MuBi4Width + (top_pkg_TL_SZW + 8))) - (3 + (prim_mubi_pkg_MuBi4Width + (top_pkg_TL_SZW + 7)))) + 1)] == 2'd1);
-	wire [31:0] error_blanking_data;
-	localparam [31:0] tlul_pkg_DataWhenError = {top_pkg_TL_DW {1'b1}};
-	localparam [31:0] tlul_pkg_DataWhenInstrError = 1'sb0;
-	assign error_blanking_data = (prim_mubi_pkg_mubi4_test_true_strict(reqfifo_rdata[prim_mubi_pkg_MuBi4Width + (top_pkg_TL_SZW + 7)-:((prim_mubi_pkg_MuBi4Width + (top_pkg_TL_SZW + 7)) >= (top_pkg_TL_SZW + 8) ? ((prim_mubi_pkg_MuBi4Width + (top_pkg_TL_SZW + 7)) - (top_pkg_TL_SZW + 8)) + 1 : ((top_pkg_TL_SZW + 8) - (prim_mubi_pkg_MuBi4Width + (top_pkg_TL_SZW + 7))) + 1)]) ? tlul_pkg_DataWhenInstrError : tlul_pkg_DataWhenError);
-	wire [31:0] unused_instr;
-	wire [31:0] unused_data;
-	wire [6:0] error_instr_integ;
-	wire [6:0] error_data_integ;
-	localparam signed [31:0] tlul_pkg_DataMaxWidth = 32;
-	function automatic [31:0] sv2v_cast_32;
-		input reg [31:0] inp;
-		sv2v_cast_32 = inp;
-	endfunction
-	tlul_data_integ_enc u_tlul_data_integ_enc_instr(
-		.data_i(sv2v_cast_32(tlul_pkg_DataWhenInstrError)),
-		.data_intg_o({error_instr_integ, unused_instr})
-	);
-	tlul_data_integ_enc u_tlul_data_integ_enc_data(
-		.data_i(sv2v_cast_32(tlul_pkg_DataWhenError)),
-		.data_intg_o({error_data_integ, unused_data})
-	);
-	wire [6:0] error_blanking_integ;
-	assign error_blanking_integ = (prim_mubi_pkg_mubi4_test_true_strict(reqfifo_rdata[prim_mubi_pkg_MuBi4Width + (top_pkg_TL_SZW + 7)-:((prim_mubi_pkg_MuBi4Width + (top_pkg_TL_SZW + 7)) >= (top_pkg_TL_SZW + 8) ? ((prim_mubi_pkg_MuBi4Width + (top_pkg_TL_SZW + 7)) - (top_pkg_TL_SZW + 8)) + 1 : ((top_pkg_TL_SZW + 8) - (prim_mubi_pkg_MuBi4Width + (top_pkg_TL_SZW + 7))) + 1)]) ? error_instr_integ : error_data_integ);
-	wire [31:0] d_data;
-	assign d_data = (vld_rd_rsp & ~d_error ? rspfifo_rdata[39-:32] : error_blanking_data);
-	wire [6:0] data_intg;
-	localparam [6:0] prim_secded_pkg_SecdedInv3932ZeroEcc = 7'h2a;
-	assign data_intg = (vld_rd_rsp && reqfifo_rdata[5 + (top_pkg_TL_SZW + 7)] ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata[7-:7] : prim_secded_pkg_SecdedInv3932ZeroEcc));
-	function automatic [6:0] sv2v_cast_5F39A;
-		input reg [6:0] inp;
-		sv2v_cast_5F39A = inp;
-	endfunction
-	function automatic [top_pkg_TL_SZW - 1:0] sv2v_cast_4660A;
-		input reg [top_pkg_TL_SZW - 1:0] inp;
-		sv2v_cast_4660A = inp;
-	endfunction
-	function automatic [7:0] sv2v_cast_964CB;
-		input reg [7:0] inp;
-		sv2v_cast_964CB = inp;
-	endfunction
-	function automatic [0:0] sv2v_cast_702AC;
-		input reg [0:0] inp;
-		sv2v_cast_702AC = inp;
-	endfunction
-	function automatic [31:0] sv2v_cast_35AE2;
-		input reg [31:0] inp;
-		sv2v_cast_35AE2 = inp;
-	endfunction
-	function automatic [(tlul_pkg_D2HRspIntgWidth + tlul_pkg_DataIntgWidth) - 1:0] sv2v_cast_1D31F;
-		input reg [(tlul_pkg_D2HRspIntgWidth + tlul_pkg_DataIntgWidth) - 1:0] inp;
-		sv2v_cast_1D31F = inp;
-	endfunction
-	assign tl_o_int = {d_valid, (d_valid && (reqfifo_rdata[7 + (top_pkg_TL_SZW + 7)-:((7 + (top_pkg_TL_SZW + 7)) >= (5 + (top_pkg_TL_SZW + 8)) ? ((7 + (top_pkg_TL_SZW + 7)) - (5 + (top_pkg_TL_SZW + 8))) + 1 : ((5 + (top_pkg_TL_SZW + 8)) - (7 + (top_pkg_TL_SZW + 7))) + 1)] != 2'd1) ? 3'h0 : 3'h1), 3'b000, sv2v_cast_4660A((d_valid ? reqfifo_rdata[top_pkg_TL_SZW + 7-:((top_pkg_TL_SZW + 7) >= 8 ? top_pkg_TL_SZW : 9 - (top_pkg_TL_SZW + 7))] : {((top_pkg_TL_SZW + 7) >= 8 ? top_pkg_TL_SZW : 9 - (top_pkg_TL_SZW + 7)) * 1 {1'sb0}})), sv2v_cast_964CB((d_valid ? reqfifo_rdata[7-:top_pkg_TL_AIW] : {8 {1'sb0}})), sv2v_cast_702AC(1'b0), sv2v_cast_35AE2(d_data), sv2v_cast_1D31F({sv2v_cast_5F39A(1'sb0), data_intg}), d_valid && d_error, ((gnt_i | error_internal) & reqfifo_wready) & sramreqfifo_wready};
-	assign req_o = (tl_i_int[7 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 55))))] & reqfifo_wready) & ~error_internal;
-	assign req_type_o = tl_i_int[18-:4];
-	assign we_o = tl_i_int[7 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 55))))] & |{tl_i_int[6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 55))))-:((6 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 55)))) >= (3 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 56)))) ? ((6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 55))))) - (3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 56)))))) + 1 : ((3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 56))))) - (6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 55)))))) + 1)] == 3'h0, tl_i_int[6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 55))))-:((6 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 55)))) >= (3 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 56)))) ? ((6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 55))))) - (3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 56)))))) + 1 : ((3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 56))))) - (6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 55)))))) + 1)] == 3'h1};
-	assign addr_o = (tl_i_int[7 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 55)))] ? tl_i_int[(top_pkg_TL_AW + (top_pkg_TL_DBW + 55)) - (31 - DataBitWidth)+:SramAw] : {SramAw {1'sb0}});
-	wire [WoffsetWidth - 1:0] woffset;
-	generate
-		if (top_pkg_TL_DW != SramDw) begin : gen_wordwidthadapt
-			assign woffset = tl_i_int[(top_pkg_TL_AW + (top_pkg_TL_DBW + 55)) - (32 - DataBitWidth):(top_pkg_TL_AW + (top_pkg_TL_DBW + 55)) - (31 - prim_util_pkg_vbits(top_pkg_TL_DBW))];
-		end
-		else begin : gen_no_wordwidthadapt
-			assign woffset = 1'sb0;
-		end
-	endgenerate
-	localparam signed [31:0] DataWidth = (EnableDataIntgPt ? top_pkg_TL_DW + tlul_pkg_DataIntgWidth : top_pkg_TL_DW);
-	wire [(WidthMult * DataWidth) - 1:0] wmask_combined;
-	wire [(WidthMult * DataWidth) - 1:0] wdata_combined;
-	reg [(WidthMult * top_pkg_TL_DW) - 1:0] wmask_int;
-	reg [(WidthMult * top_pkg_TL_DW) - 1:0] wdata_int;
-	reg [(WidthMult * tlul_pkg_DataIntgWidth) - 1:0] wmask_intg;
-	reg [(WidthMult * tlul_pkg_DataIntgWidth) - 1:0] wdata_intg;
-	always @(*) begin
-		wmask_int = 1'sb0;
-		wdata_int = 1'sb0;
-		if (tl_i_int[7 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 55))))]) begin : sv2v_autoblock_1
-			reg signed [31:0] i;
-			for (i = 0; i < 4; i = i + 1)
-				begin
-					wmask_int[(woffset * top_pkg_TL_DW) + (8 * i)+:8] = {8 {tl_i_int[(top_pkg_TL_DBW + 55) - ((top_pkg_TL_DBW - 1) - i)]}};
-					wdata_int[(woffset * top_pkg_TL_DW) + (8 * i)+:8] = (tl_i_int[(top_pkg_TL_DBW + 55) - ((top_pkg_TL_DBW - 1) - i)] && we_o ? tl_i_int[24 + (8 * i)+:8] : {8 {1'sb0}});
-				end
-		end
-	end
-	always @(*) begin
-		wmask_intg = 1'sb0;
-		wdata_intg = 1'sb0;
-		if (tl_i_int[7 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 55))))]) begin
-			wmask_intg[woffset * tlul_pkg_DataIntgWidth+:tlul_pkg_DataIntgWidth] = {tlul_pkg_DataIntgWidth {1'b1}};
-			wdata_intg[woffset * tlul_pkg_DataIntgWidth+:tlul_pkg_DataIntgWidth] = tl_i_int[7-:tlul_pkg_DataIntgWidth];
-		end
-	end
-	genvar i;
-	generate
-		for (i = 0; i < WidthMult; i = i + 1) begin : gen_write_output
-			if (EnableDataIntgPt) begin : gen_combined_output
-				assign wmask_combined[i * DataWidth+:DataWidth] = {wmask_intg[i * tlul_pkg_DataIntgWidth+:tlul_pkg_DataIntgWidth], wmask_int[i * top_pkg_TL_DW+:top_pkg_TL_DW]};
-				assign wdata_combined[i * DataWidth+:DataWidth] = {wdata_intg[i * tlul_pkg_DataIntgWidth+:tlul_pkg_DataIntgWidth], wdata_int[i * top_pkg_TL_DW+:top_pkg_TL_DW]};
-			end
-			else begin : gen_ft_output
-				wire unused_w;
-				assign wmask_combined[i * DataWidth+:DataWidth] = wmask_int[i * top_pkg_TL_DW+:top_pkg_TL_DW];
-				assign wdata_combined[i * DataWidth+:DataWidth] = wdata_int[i * top_pkg_TL_DW+:top_pkg_TL_DW];
-				assign unused_w = |wmask_intg & |wdata_intg;
-			end
-		end
-	endgenerate
-	assign wmask_o = wmask_combined;
-	assign wdata_o = wdata_combined;
-	assign reqfifo_wvalid = a_ack;
-	assign reqfifo_wdata = {(tl_i_int[6 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 55)))-:((6 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 55)))) >= (3 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 56)))) ? ((6 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 55)))) - (3 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 56))))) + 1 : ((3 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 56)))) - (6 + (top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 55))))) + 1)] != 3'h4 ? 2'd0 : 2'd1), error_internal, sv2v_cast_A2CB9(tl_i_int[18-:4]), tl_i_int[top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 55)))-:((top_pkg_TL_SZW + ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 55))) >= ((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 56)) ? ((top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 55)))) - (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 56)))) + 1 : ((top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 56))) - (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 55))))) + 1)], tl_i_int[top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 55))-:(((32'sd8 + 32'sd32) + (top_pkg_TL_DBW + 55)) >= (32'sd32 + (top_pkg_TL_DBW + 56)) ? ((top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 55))) - (top_pkg_TL_AW + (top_pkg_TL_DBW + 56))) + 1 : ((top_pkg_TL_AW + (top_pkg_TL_DBW + 56)) - (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + 55)))) + 1)]};
-	assign reqfifo_rready = d_ack;
-	assign sramreqfifo_wdata = {tl_i_int[top_pkg_TL_DBW + 55-:((top_pkg_TL_DBW + 55) >= 56 ? top_pkg_TL_DBW : 57 - (top_pkg_TL_DBW + 55))], woffset};
-	assign sramreqfifo_wvalid = sram_ack & ~we_o;
-	assign sramreqfifo_rready = rspfifo_wvalid;
-	assign rspfifo_wvalid = rvalid_i & reqfifo_rvalid;
-	wire [(WidthMult * DataWidth) - 1:0] rdata_reshaped;
-	reg [DataWidth - 1:0] rdata_tlword;
-	assign rdata_reshaped = rdata_i;
-	localparam [38:0] prim_secded_pkg_SecdedInv3932ZeroWord = 39'h2a00000000;
-	generate
-		if (EnableDataIntgPt) begin : gen_no_rmask
-			always @(*) begin
-				rdata_tlword = prim_secded_pkg_SecdedInv3932ZeroWord;
-				if (|sramreqfifo_rdata[top_pkg_TL_DBW + (WoffsetWidth - 1)-:((top_pkg_TL_DBW + (WoffsetWidth - 1)) >= (WoffsetWidth + 0) ? ((top_pkg_TL_DBW + (WoffsetWidth - 1)) - (WoffsetWidth + 0)) + 1 : ((WoffsetWidth + 0) - (top_pkg_TL_DBW + (WoffsetWidth - 1))) + 1)])
-					rdata_tlword = rdata_reshaped[sramreqfifo_rdata[WoffsetWidth - 1-:WoffsetWidth] * DataWidth+:DataWidth];
-			end
-		end
-		else begin : gen_rmask
-			reg [DataWidth - 1:0] rmask;
-			always @(*) begin
-				rmask = 1'sb0;
-				begin : sv2v_autoblock_2
-					reg signed [31:0] i;
-					for (i = 0; i < 4; i = i + 1)
-						rmask[8 * i+:8] = {8 {sramreqfifo_rdata[(top_pkg_TL_DBW + (WoffsetWidth - 1)) - ((top_pkg_TL_DBW - 1) - i)]}};
-				end
-			end
-			wire [DataWidth:1] sv2v_tmp_037A0;
-			assign sv2v_tmp_037A0 = rdata_reshaped[sramreqfifo_rdata[WoffsetWidth - 1-:WoffsetWidth] * DataWidth+:DataWidth] & rmask;
-			always @(*) rdata_tlword = sv2v_tmp_037A0;
-		end
-	endgenerate
-	function automatic [6:0] sv2v_cast_8DC45;
-		input reg [6:0] inp;
-		sv2v_cast_8DC45 = inp;
-	endfunction
-	assign rspfifo_wdata = {sv2v_cast_35AE2(rdata_tlword[31:0]), sv2v_cast_8DC45((EnableDataIntgPt ? rdata_tlword[DataWidth - 1-:tlul_pkg_DataIntgWidth] : {7 {1'sb0}})), rerror_i[1]};
-	assign rspfifo_rready = ((reqfifo_rdata[7 + (top_pkg_TL_SZW + 7)-:((7 + (top_pkg_TL_SZW + 7)) >= (5 + (top_pkg_TL_SZW + 8)) ? ((7 + (top_pkg_TL_SZW + 7)) - (5 + (top_pkg_TL_SZW + 8))) + 1 : ((5 + (top_pkg_TL_SZW + 8)) - (7 + (top_pkg_TL_SZW + 7))) + 1)] == 2'd1) & ~reqfifo_rdata[5 + (top_pkg_TL_SZW + 7)] ? reqfifo_rready : 1'b0);
-	wire unused_rerror;
-	assign unused_rerror = rerror_i[0];
-	prim_fifo_sync #(
-		.Width(ReqFifoWidth),
-		.Pass(1'b0),
-		.Depth(Outstanding)
-	) u_reqfifo(
-		.clk_i(clk_i),
-		.rst_ni(rst_ni),
-		.clr_i(1'b0),
-		.wvalid_i(reqfifo_wvalid),
-		.wready_o(reqfifo_wready),
-		.wdata_i(reqfifo_wdata),
-		.rvalid_o(reqfifo_rvalid),
-		.rready_i(reqfifo_rready),
-		.rdata_o(reqfifo_rdata)
-	);
-	prim_fifo_sync #(
-		.Width(SramReqFifoWidth),
-		.Pass(1'b0),
-		.Depth(Outstanding)
-	) u_sramreqfifo(
-		.clk_i(clk_i),
-		.rst_ni(rst_ni),
-		.clr_i(1'b0),
-		.wvalid_i(sramreqfifo_wvalid),
-		.wready_o(sramreqfifo_wready),
-		.wdata_i(sramreqfifo_wdata),
-		.rready_i(sramreqfifo_rready),
-		.rdata_o(sramreqfifo_rdata)
-	);
-	prim_fifo_sync #(
-		.Width(RspFifoWidth),
-		.Pass(1'b1),
-		.Depth(Outstanding),
-		.Secure(SecFifoPtr)
-	) u_rspfifo(
-		.clk_i(clk_i),
-		.rst_ni(rst_ni),
-		.clr_i(1'b0),
-		.wvalid_i(rspfifo_wvalid),
-		.wready_o(rspfifo_wready),
-		.wdata_i(rspfifo_wdata),
-		.rvalid_o(rspfifo_rvalid),
-		.rready_i(rspfifo_rready),
-		.rdata_o(rspfifo_rdata),
-		.err_o(rsp_fifo_error)
-	);
-endmodule
+
 module prim_alert_receiver (
 	clk_i,
 	rst_ni,
diff --git a/cpus/kronos_pregenerated/cellift/generated/sv2v_out.v b/cpus/kronos_pregenerated/cellift/generated/sv2v_out.v
index db99c22a..1429e091 100644
--- a/cpus/kronos_pregenerated/cellift/generated/sv2v_out.v
+++ b/cpus/kronos_pregenerated/cellift/generated/sv2v_out.v
@@ -1935,112 +1935,3 @@ module kronos_agu (
 		end
 	endgenerate
 endmodule
-module kronos_mem_top (
-	clk_i,
-	rst_ni,
-	data_mem_req,
-	data_mem_gnt,
-	data_mem_addr,
-	data_mem_wdata,
-	data_mem_strb,
-	data_mem_we,
-	data_mem_rdata,
-	instr_mem_req,
-	instr_mem_gnt,
-	instr_mem_addr,
-	instr_mem_wdata,
-	instr_mem_strb,
-	instr_mem_we,
-	instr_mem_rdata,
-	software_interrupt,
-	timer_interrupt,
-	external_interrupt
-);
-	localparam [31:0] InstrMemAw = 20;
-	localparam [31:0] DataMemAw = 20;
-	input clk_i;
-	input rst_ni;
-	output wire data_mem_req;
-	input wire data_mem_gnt;
-	output wire [19:0] data_mem_addr;
-	output wire [31:0] data_mem_wdata;
-	output wire [31:0] data_mem_strb;
-	output wire data_mem_we;
-	input wire [31:0] data_mem_rdata;
-	output wire instr_mem_req;
-	input wire instr_mem_gnt;
-	output wire [19:0] instr_mem_addr;
-	output wire [31:0] instr_mem_wdata;
-	output wire [31:0] instr_mem_strb;
-	output wire instr_mem_we;
-	input wire [31:0] instr_mem_rdata;
-	input wire software_interrupt;
-	input wire timer_interrupt;
-	input wire external_interrupt;
-	wire [31:0] instr_addr;
-	wire [31:0] instr_data;
-	wire instr_req;
-	wire instr_ack;
-	wire [31:0] data_addr;
-	wire [31:0] data_rd_data;
-	wire [31:0] data_wr_data;
-	wire [3:0] data_mask;
-	wire data_wr_en;
-	wire data_req;
-	wire data_ack;
-	wire instr_ack_d;
-	reg instr_ack_q;
-	wire data_ack_d;
-	reg data_ack_q;
-	assign instr_ack_d = instr_mem_req;
-	assign data_ack_d = data_mem_req;
-	always @(posedge clk_i or negedge rst_ni)
-		if (~rst_ni) begin
-			instr_ack_q <= 1'sb0;
-			data_ack_q <= 1'sb0;
-		end
-		else begin
-			instr_ack_q <= instr_ack_d;
-			data_ack_q <= data_ack_d;
-		end
-	assign instr_mem_req = instr_req;
-	assign instr_ack = instr_ack_q;
-	assign instr_mem_addr = instr_addr;
-	assign instr_mem_wdata = 1'sb0;
-	assign instr_mem_strb = 1'sb0;
-	assign instr_mem_we = 1'sb0;
-	assign instr_data = instr_mem_rdata;
-	assign data_mem_req = data_req;
-	assign data_ack = 1'b1;
-	assign data_mem_addr = data_addr;
-	assign data_mem_wdata = data_wr_data;
-	assign data_mem_strb = {{8 {data_mask[3]}}, {8 {data_mask[2]}}, {8 {data_mask[1]}}, {8 {data_mask[0]}}};
-	assign data_mem_we = data_wr_en;
-	assign data_rd_data = data_mem_rdata;
-	kronos_core #(
-		.BOOT_ADDR(32'h80000000),
-		.FAST_BRANCH(1),
-		.EN_COUNTERS(1),
-		.EN_COUNTERS64B(1),
-		.CATCH_ILLEGAL_INSTR(1),
-		.CATCH_MISALIGNED_JMP(1),
-		.CATCH_MISALIGNED_LDST(1)
-	) i_kronos_core(
-		.clk(clk_i),
-		.rstz(rst_ni),
-		.instr_addr(instr_addr),
-		.instr_data(instr_data),
-		.instr_req(instr_req),
-		.instr_ack(instr_ack),
-		.data_addr(data_addr),
-		.data_rd_data(data_rd_data),
-		.data_wr_data(data_wr_data),
-		.data_mask(data_mask),
-		.data_wr_en(data_wr_en),
-		.data_req(data_req),
-		.data_ack(data_ack),
-		.software_interrupt(software_interrupt),
-		.timer_interrupt(timer_interrupt),
-		.external_interrupt(external_interrupt)
-	);
-endmodule
\ No newline at end of file
diff --git a/mucfi_yosys/passes/find_fwd_mux_selects/README.md b/mucfi_yosys/passes/find_fwd_mux_selects/README.md
index be733035..a32bdb6f 100644
--- a/mucfi_yosys/passes/find_fwd_mux_selects/README.md
+++ b/mucfi_yosys/passes/find_fwd_mux_selects/README.md
@@ -17,6 +17,6 @@ Taint injection into the register read signal is sound, if there is no logic bet
 ## Algorithm
 
 The pass takes a forwarding output signal (that should be declassified in the formal setup, ie., abstracted and set to 'not tainted'), the register read signal, the register write signal and the program counter (PC) signal as input.
-Starting from the forwarding output, the pass follows all outgoing paths of this signal and checks whether it eiter feeds into a declassified signal (precondition fulfilled), or into a multiplexer. Then it checks whether this multiplexer is a forwarding multiplexer. If yes, the mux is tagged. If nto, the search is continued at the output of the mux. Assignments and port connections are followed until a forwarding multiplexer is found. If a path feeds into another cell, the pass checks whether all outgoing paths converge into a declassified signal without passing the PC.
+Starting from the forwarding output, the pass follows all outgoing paths of this signal and checks whether it eiter feeds into a declassified signal (precondition fulfilled), or into a multiplexer. Then it checks whether this multiplexer is a forwarding multiplexer. If yes, the mux is tagged. If not, the search is continued at the output of the mux. Assignments and port connections are followed until a forwarding multiplexer is found. If a path feeds into another cell, the pass checks whether all outgoing paths converge into a declassified signal without passing the PC.
 
 While checking whether a multiplexer is a forwarding multiplexer, the pass also checks for precondition that needs to be satisfied when abstracting the select of a multiplexer (instead of injecting taint into the forwarding input of that multiplexer): There must be no other cell than an fmux (or a non-transformative cell combination like a double negation) between the forwarding input of the fmux and the register reading signal. If the precondition is not fulfilled, the multiplexer is not tagged as forwarding multiplexer and the search continues at the output of the mux (as described above).