From e160e9808c608f33335f7742d8c2d62b80ee9a36 Mon Sep 17 00:00:00 2001 From: Abdul Wadood Date: Mon, 15 May 2023 02:14:28 +0500 Subject: [PATCH 1/8] Added Zcb Opcodes for Quadrant 0 - Zcb Instructions with `OP[1:0] = 2'b0` added. - These are Compressed version of following I-type instructins. - lbu - lhu - lh - sb - sh - These instructions lies in Quadrant 0 based on compressed Opcode. Signed-off-by: Abdul Wadood --- src/main/scala/rocket/Instructions.scala | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/main/scala/rocket/Instructions.scala b/src/main/scala/rocket/Instructions.scala index adf1183388f..da31c20a25b 100644 --- a/src/main/scala/rocket/Instructions.scala +++ b/src/main/scala/rocket/Instructions.scala @@ -76,8 +76,11 @@ object Instructions { def C_J = BitPat("b????????????????101???????????01") def C_JALR = BitPat("b????????????????1001?????0000010") def C_JR = BitPat("b????????????????1000?????0000010") + def C_LBU = BitPat("b????????????????100000????????00") def C_LD = BitPat("b????????????????011???????????00") def C_LDSP = BitPat("b????????????????011???????????10") + def C_LH = BitPat("b????????????????100001???1????00") + def C_LHU = BitPat("b????????????????100001???0????00") def C_LI = BitPat("b????????????????010???????????01") def C_LUI = BitPat("b????????????????011???????????01") def C_LW = BitPat("b????????????????010???????????00") @@ -85,8 +88,10 @@ object Instructions { def C_MV = BitPat("b????????????????1000??????????10") def C_NOP = BitPat("b????????????????000?00000?????01") def C_OR = BitPat("b????????????????100011???10???01") + def C_SB = BitPat("b????????????????100010????????00") def C_SD = BitPat("b????????????????111???????????00") def C_SDSP = BitPat("b????????????????111???????????10") + def C_SH = BitPat("b????????????????100011???0????00") def C_SLLI = BitPat("b????????????????000???????????10") def C_SRAI = BitPat("b????????????????100?01????????01") def C_SRLI = BitPat("b????????????????100?00????????01") From b943cfbf670a82be9bf11f3f091a3286fbfdd325 Mon Sep 17 00:00:00 2001 From: Abdul Wadood Date: Mon, 15 May 2023 02:34:58 +0500 Subject: [PATCH 2/8] Added Support of Q0 `Zcb` Instructions. - Implement the 16 to 32 bit Decoder for `Zcb` Instructions having OP[1:0] == 00 - This decodes the following compressed instructions into its 32-bit equivalent instructions. c.lbu, c.lhu, c.lh, c.cb, c.sh Signed-off-by: Abdul Wadood --- src/main/scala/rocket/RVC.scala | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/src/main/scala/rocket/RVC.scala b/src/main/scala/rocket/RVC.scala index cc54c293558..f8841cfb0e5 100644 --- a/src/main/scala/rocket/RVC.scala +++ b/src/main/scala/rocket/RVC.scala @@ -32,6 +32,8 @@ class RVCDecoder(x: UInt, xLen: Int, useAddiForMv: Boolean = false) { def rs2 = x(6,2) def rd = x(11,7) def addi4spnImm = Cat(x(10,7), x(12,11), x(5), x(6), 0.U(2.W)) + def lbImm = Cat(x(5), x(6)) + def lhImm = Cat(x(5), 0.U(1.W)) def lwImm = Cat(x(5), x(12,10), x(6), 0.U(2.W)) def ldImm = Cat(x(6,5), x(12,10), 0.U(3.W)) def lwspImm = Cat(x(3,2), x(12), x(6,4), 0.U(2.W)) @@ -60,7 +62,16 @@ class RVCDecoder(x: UInt, xLen: Int, useAddiForMv: Boolean = false) { if (xLen == 32) inst(Cat(lwImm, rs1p, 2.U(3.W), rs2p, 0x07.U(7.W)), rs2p, rs1p, rs2p) else ld } - def unimp = inst(Cat(lwImm >> 5, rs2p, rs1p, 2.U(3.W), lwImm(4,0), 0x3F.U(7.W)), rs2p, rs1p, rs2p) + def zcb_q0 = { + def lbu = Cat(lbImm, rs1p, 4.U(3.W), rs2p, 0x03.U(7.W)) + def lh = { + val func3 = Mux(x(6), 1.U(3.W), 5.U(3.W)) + Cat(lhImm, rs1p, func3, rs2p, 0x03.U(7.W)) + } + def sb = Cat(rs2p, rs1p, 0.U(3.W), 0.U(3.W), lbImm(1,0), 0x23.U(7.W)) + def sh = Cat(rs2p, rs1p, 1.U(3.W), 0.U(3.W), lhImm(1,0), 0x23.U(7.W)) + inst(Seq(lbu, lh, sb, sh)(x(11,10)), rs2p, rs1p, rs2p) + } def sd = inst(Cat(ldImm >> 5, rs2p, rs1p, 3.U(3.W), ldImm(4,0), 0x23.U(7.W)), rs2p, rs1p, rs2p) def sw = inst(Cat(lwImm >> 5, rs2p, rs1p, 2.U(3.W), lwImm(4,0), 0x23.U(7.W)), rs2p, rs1p, rs2p) def fsd = inst(Cat(ldImm >> 5, rs2p, rs1p, 3.U(3.W), ldImm(4,0), 0x27.U(7.W)), rs2p, rs1p, rs2p) @@ -68,7 +79,7 @@ class RVCDecoder(x: UInt, xLen: Int, useAddiForMv: Boolean = false) { if (xLen == 32) inst(Cat(lwImm >> 5, rs2p, rs1p, 2.U(3.W), lwImm(4,0), 0x27.U(7.W)), rs2p, rs1p, rs2p) else sd } - Seq(addi4spn, fld, lw, flw, unimp, fsd, sw, fsw) + Seq(addi4spn, fld, lw, flw, zcb_q0, fsd, sw, fsw) } def q1 = { From face7dea711f659f6efd533dce05cd1fca382d33 Mon Sep 17 00:00:00 2001 From: Abdul Wadood Date: Mon, 15 May 2023 02:54:32 +0500 Subject: [PATCH 3/8] Added Zcb Opcodes for Quadrant 1 - Zcb Instructions with `OP[1:0] = 2'b01` added. - These instructions lies in Q1 of Compressed Instructions. Signed-off-by: Abdul Wadood --- src/main/scala/rocket/Instructions.scala | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/src/main/scala/rocket/Instructions.scala b/src/main/scala/rocket/Instructions.scala index da31c20a25b..f79388f64ad 100644 --- a/src/main/scala/rocket/Instructions.scala +++ b/src/main/scala/rocket/Instructions.scala @@ -85,12 +85,16 @@ object Instructions { def C_LUI = BitPat("b????????????????011???????????01") def C_LW = BitPat("b????????????????010???????????00") def C_LWSP = BitPat("b????????????????010???????????10") + def C_MUL = BitPat("b????????????????100111???10???01") def C_MV = BitPat("b????????????????1000??????????10") def C_NOP = BitPat("b????????????????000?00000?????01") + def C_NOT = BitPat("b????????????????100111???1110101") def C_OR = BitPat("b????????????????100011???10???01") def C_SB = BitPat("b????????????????100010????????00") def C_SD = BitPat("b????????????????111???????????00") def C_SDSP = BitPat("b????????????????111???????????10") + def C_SEXT_B = BitPat("b????????????????100111???1100101") + def C_SEXT_H = BitPat("b????????????????100111???1101101") def C_SH = BitPat("b????????????????100011???0????00") def C_SLLI = BitPat("b????????????????000???????????10") def C_SRAI = BitPat("b????????????????100?01????????01") @@ -100,6 +104,9 @@ object Instructions { def C_SW = BitPat("b????????????????110???????????00") def C_SWSP = BitPat("b????????????????110???????????10") def C_XOR = BitPat("b????????????????100011???01???01") + def C_ZEXT_B = BitPat("b????????????????100111???1100001") + def C_ZEXT_H = BitPat("b????????????????100111???1101001") + def C_ZEXT_W = BitPat("b????????????????100111???1110001") def CBO_CLEAN = BitPat("b000000000001?????010000000001111") def CBO_FLUSH = BitPat("b000000000010?????010000000001111") def CBO_INVAL = BitPat("b000000000000?????010000000001111") @@ -1734,4 +1741,4 @@ object CSRs { res += mhpmcounter31h res.toArray } -} +} \ No newline at end of file From 323d57d793bf3310e1b359fc010445e43cd45db4 Mon Sep 17 00:00:00 2001 From: Abdul Wadood Date: Mon, 15 May 2023 03:01:25 +0500 Subject: [PATCH 4/8] Added support of Q1 `Zcb` Instructions. - Implement the 16 to 32 bit Decoder for `Zcb` Instructions having OP[1:0] = 2'b01 - The 16 bit -> 32 bit instruction mapping is given as follows: c.zext.b -> andi c.sext.b -> sext.b (require Zbb) c.zext.h -> zext.h (require Zbb) c.sext.h -> sext.h (require Zbb) c.zext.w -> add.uw (require Zba, only for RV64) c.not -> xori c.mul -> mul (Require M standard extension) Signed-off-by: Abdul Wadood --- src/main/scala/rocket/RVC.scala | 29 ++++++++++++++++++++++------- 1 file changed, 22 insertions(+), 7 deletions(-) diff --git a/src/main/scala/rocket/RVC.scala b/src/main/scala/rocket/RVC.scala index f8841cfb0e5..c98cd625d3f 100644 --- a/src/main/scala/rocket/RVC.scala +++ b/src/main/scala/rocket/RVC.scala @@ -106,16 +106,31 @@ class RVCDecoder(x: UInt, xLen: Int, useAddiForMv: Boolean = false) { def beqz = inst(Cat(bImm(12), bImm(10,5), x0, rs1p, 0.U(3.W), bImm(4,1), bImm(11), 0x63.U(7.W)), rs1p, rs1p, x0) def bnez = inst(Cat(bImm(12), bImm(10,5), x0, rs1p, 1.U(3.W), bImm(4,1), bImm(11), 0x63.U(7.W)), x0, rs1p, x0) def arith = { - def srli = Cat(shamt, rs1p, 5.U(3.W), rs1p, 0x13.U(7.W)) - def srai = srli | (1 << 30).U - def andi = Cat(addiImm, rs1p, 7.U(3.W), rs1p, 0x13.U(7.W)) + def srli = inst(Cat(shamt, rs1p, 5.U(3.W), rs1p, 0x13.U(7.W)), rs1p, rs1p, rs2p) + def srai = inst(Cat(0x10.U, shamt, rs1p, 5.U(3.W), rs1p, 0x13.U(7.W)), rs1p, rs1p, rs2p) + def andi = inst(Cat(addiImm, rs1p, 7.U(3.W), rs1p, 0x13.U(7.W)), rs1p, rs1p, rs2p) def rtype = { - val funct = Seq(0.U, 4.U, 6.U, 7.U, 0.U, 0.U, 2.U, 3.U)(Cat(x(12), x(6,5))) + val funct = Seq(0.U, 4.U, 6.U, 7.U, 0.U, 0.U, 0.U, 3.U)(Cat(x(12), x(6,5))) val sub = Mux(x(6,5) === 0.U, (1 << 30).U, 0.U) - val opc = Mux(x(12), 0x3B.U(7.W), 0x33.U(7.W)) - Cat(rs2p, rs1p, funct, rs1p, opc) | sub + val mul = Mux(Cat(x(12), x(6,5)) === 6.U, (1 << 25).U, 0.U) + val opc = Mux(x(12), Mux(x(6), 0x33.U(7.W), 0x3B.U(7.W)), 0x33.U(7.W)) + def zcb_q1 = { + def zextb = inst(Cat(0xff.U, rs1p, 7.U(3.W), rs1p, 0x13.U(7.W)), rs1p, rs1p, rs2p) + def sextb = inst(Cat(0x604.U, rs1p, 1.U(3.W), rs1p, 0x13.U(7.W)), rs1p, rs1p, rs2p) + def sexth = inst(Cat(0x605.U, rs1p, 1.U(3.W), rs1p, 0x13.U(7.W)), rs1p, rs1p, rs2p) + def not = inst(Cat(0xFFF.U, rs1p, 4.U(3.W), rs1p, 0x13.U(7.W)), rs1p, rs1p, rs2p) + def zextw = inst(Cat(4.U, x0, rs1p, 0.U(3.W), rs1p, 0x3B.U(7.W)), rs1p, rs1p, x0) + def zexth64 = inst(Cat(0x80.U, rs1p, 4.U(3.W), rs1p, 0x3B.U(7.W)), rs1p, rs1p, rs2p) + def zexth = { + if (xLen == 32) inst(Cat(0x80.U, rs1p, 4.U(3.W), rs1p, 0x33.U(7.W)), rs1p, rs1p, rs2p) + else zexth64 + } + Seq(zextb, sextb, zexth, sexth, zextw, not)(x(4,2)) + } + def zca = inst(Cat(rs2p, rs1p, funct, rs1p, opc) | sub | mul, rs1p, rs1p, rs2p) + Mux(Cat(x(12), x(6,5)) === 7.U, zcb_q1, zca) } - inst(Seq(srli, srai, andi, rtype)(x(11,10)), rs1p, rs1p, rs2p) + Seq(srli, srai, andi, rtype)(x(11,10)) } Seq(addi, jal, li, lui, arith, j, beqz, bnez) } From 4a678395c4e1ae839375dd453fd0e540c98e8e29 Mon Sep 17 00:00:00 2001 From: Abdul Wadood Date: Thu, 18 May 2023 02:55:02 +0500 Subject: [PATCH 5/8] Parameterized the `Zcb` extension - Added `usingCompressedSuiteB` to enable/disable `Zcb` extension. - This parameter depends upon existing `usingCompressed` parameter. - By default `Zcb` is disable in RocketCore. - Passed this parameter along with `usingBitManip` and `usingMulDiv` to RVCDecoder enable/disable the decoding of corresponding `Zcb` instructions. Signed-off-by: Abdul Wadood --- src/main/scala/rocket/RVC.scala | 71 +++++++++++++++++--------- src/main/scala/rocket/RocketCore.scala | 1 + src/main/scala/tile/Core.scala | 2 + 3 files changed, 50 insertions(+), 24 deletions(-) diff --git a/src/main/scala/rocket/RVC.scala b/src/main/scala/rocket/RVC.scala index c98cd625d3f..5fbf24158af 100644 --- a/src/main/scala/rocket/RVC.scala +++ b/src/main/scala/rocket/RVC.scala @@ -16,7 +16,7 @@ class ExpandedInstruction extends Bundle { val rs3 = UInt(5.W) } -class RVCDecoder(x: UInt, xLen: Int, useAddiForMv: Boolean = false) { +class RVCDecoder(x: UInt, xLen: Int, useAddiForMv: Boolean = false, usingBitManip: Boolean = false, usingMulDiv: Boolean = false, usingCompressedSuiteB: Boolean = false) { def inst(bits: UInt, rd: UInt = x(11,7), rs1: UInt = x(19,15), rs2: UInt = x(24,20), rs3: UInt = x(31,27)) = { val res = Wire(new ExpandedInstruction) res.bits := bits @@ -63,14 +63,17 @@ class RVCDecoder(x: UInt, xLen: Int, useAddiForMv: Boolean = false) { else ld } def zcb_q0 = { - def lbu = Cat(lbImm, rs1p, 4.U(3.W), rs2p, 0x03.U(7.W)) - def lh = { - val func3 = Mux(x(6), 1.U(3.W), 5.U(3.W)) - Cat(lhImm, rs1p, func3, rs2p, 0x03.U(7.W)) + if (usingCompressedSuiteB){ + def lbu = Cat(lbImm, rs1p, 4.U(3.W), rs2p, 0x03.U(7.W)) + def lh = { + val func3 = Mux(x(6), 1.U(3.W), 5.U(3.W)) + Cat(lhImm, rs1p, func3, rs2p, 0x03.U(7.W)) + } + def sb = Cat(rs2p, rs1p, 0.U(3.W), 0.U(3.W), lbImm(1,0), 0x23.U(7.W)) + def sh = Cat(rs2p, rs1p, 1.U(3.W), 0.U(3.W), lhImm(1,0), 0x23.U(7.W)) + inst(Seq(lbu, lh, sb, sh)(x(11,10)), rs2p, rs1p, rs2p) } - def sb = Cat(rs2p, rs1p, 0.U(3.W), 0.U(3.W), lbImm(1,0), 0x23.U(7.W)) - def sh = Cat(rs2p, rs1p, 1.U(3.W), 0.U(3.W), lhImm(1,0), 0x23.U(7.W)) - inst(Seq(lbu, lh, sb, sh)(x(11,10)), rs2p, rs1p, rs2p) + else inst(Cat(lwImm >> 5, rs2p, rs1p, 2.U(3.W), lwImm(4,0), 0x3F.U(7.W)), rs2p, rs1p, rs2p) // unimp } def sd = inst(Cat(ldImm >> 5, rs2p, rs1p, 3.U(3.W), ldImm(4,0), 0x23.U(7.W)), rs2p, rs1p, rs2p) def sw = inst(Cat(lwImm >> 5, rs2p, rs1p, 2.U(3.W), lwImm(4,0), 0x23.U(7.W)), rs2p, rs1p, rs2p) @@ -106,28 +109,48 @@ class RVCDecoder(x: UInt, xLen: Int, useAddiForMv: Boolean = false) { def beqz = inst(Cat(bImm(12), bImm(10,5), x0, rs1p, 0.U(3.W), bImm(4,1), bImm(11), 0x63.U(7.W)), rs1p, rs1p, x0) def bnez = inst(Cat(bImm(12), bImm(10,5), x0, rs1p, 1.U(3.W), bImm(4,1), bImm(11), 0x63.U(7.W)), x0, rs1p, x0) def arith = { - def srli = inst(Cat(shamt, rs1p, 5.U(3.W), rs1p, 0x13.U(7.W)), rs1p, rs1p, rs2p) - def srai = inst(Cat(0x10.U, shamt, rs1p, 5.U(3.W), rs1p, 0x13.U(7.W)), rs1p, rs1p, rs2p) + val srai_srli_common = Cat(shamt, rs1p, 5.U(3.W), rs1p, 0x13.U(7.W)) + def srli = inst(srai_srli_common, rs1p, rs1p, rs2p) + def srai = inst(Cat(0x10.U, srai_srli_common), rs1p, rs1p, rs2p) def andi = inst(Cat(addiImm, rs1p, 7.U(3.W), rs1p, 0x13.U(7.W)), rs1p, rs1p, rs2p) def rtype = { val funct = Seq(0.U, 4.U, 6.U, 7.U, 0.U, 0.U, 0.U, 3.U)(Cat(x(12), x(6,5))) val sub = Mux(x(6,5) === 0.U, (1 << 30).U, 0.U) - val mul = Mux(Cat(x(12), x(6,5)) === 6.U, (1 << 25).U, 0.U) val opc = Mux(x(12), Mux(x(6), 0x33.U(7.W), 0x3B.U(7.W)), 0x33.U(7.W)) + def mul = { + if(usingMulDiv && usingCompressedSuiteB) Mux(Cat(x(12), x(6,5)) === 6.U, (1 << 25).U, 0.U) + else 0.U + } + def zca = inst(Cat(rs2p, rs1p, funct, rs1p, opc) | sub | mul, rs1p, rs1p, rs2p) def zcb_q1 = { - def zextb = inst(Cat(0xff.U, rs1p, 7.U(3.W), rs1p, 0x13.U(7.W)), rs1p, rs1p, rs2p) - def sextb = inst(Cat(0x604.U, rs1p, 1.U(3.W), rs1p, 0x13.U(7.W)), rs1p, rs1p, rs2p) - def sexth = inst(Cat(0x605.U, rs1p, 1.U(3.W), rs1p, 0x13.U(7.W)), rs1p, rs1p, rs2p) - def not = inst(Cat(0xFFF.U, rs1p, 4.U(3.W), rs1p, 0x13.U(7.W)), rs1p, rs1p, rs2p) - def zextw = inst(Cat(4.U, x0, rs1p, 0.U(3.W), rs1p, 0x3B.U(7.W)), rs1p, rs1p, x0) - def zexth64 = inst(Cat(0x80.U, rs1p, 4.U(3.W), rs1p, 0x3B.U(7.W)), rs1p, rs1p, rs2p) - def zexth = { - if (xLen == 32) inst(Cat(0x80.U, rs1p, 4.U(3.W), rs1p, 0x33.U(7.W)), rs1p, rs1p, rs2p) - else zexth64 + def unimp = inst(Cat(lwImm >> 5, rs2p, rs1p, 2.U(3.W), lwImm(4,0), 0x3F.U(7.W)), rs2p, rs1p, rs2p) + if(usingCompressedSuiteB){ + def zextb = inst(Cat(0xFF.U, rs1p, 7.U(3.W), rs1p, 0x13.U(7.W)), rs1p, rs1p, rs2p) + def not = inst(Cat(0xFFF.U, rs1p, 4.U(3.W), rs1p, 0x13.U(7.W)), rs1p, rs1p, rs2p) + def sextb = { + if(usingBitManip) inst(Cat(0x604.U, rs1p, 1.U(3.W), rs1p, 0x13.U(7.W)), rs1p, rs1p, rs2p) + else unimp + } + def sexth = { + if(usingBitManip) inst(Cat(0x605.U, rs1p, 1.U(3.W), rs1p, 0x13.U(7.W)), rs1p, rs1p, rs2p) + else unimp + } + def zextw = { + if(usingBitManip) inst(Cat(4.U, x0, rs1p, 0.U(3.W), rs1p, 0x3B.U(7.W)), rs1p, rs1p, x0) + else unimp + } + def zexth = { + if(usingBitManip) { + val zexth_common = Cat(0x80.U, rs1p, 4.U(3.W), rs1p) + if (xLen == 32) inst(Cat(zexth_common, 0x33.U(7.W)), rs1p, rs1p, rs2p) + else inst(Cat(zexth_common, 0x3B.U(7.W)), rs1p, rs1p, rs2p) + } + else unimp + } + Seq(zextb, sextb, zexth, sexth, zextw, not)(x(4,2)) } - Seq(zextb, sextb, zexth, sexth, zextw, not)(x(4,2)) + else unimp } - def zca = inst(Cat(rs2p, rs1p, funct, rs1p, opc) | sub | mul, rs1p, rs1p, rs2p) Mux(Cat(x(12), x(6,5)) === 7.U, zcb_q1, zca) } Seq(srli, srai, andi, rtype)(x(11,10)) @@ -190,9 +213,9 @@ class RVCExpander(useAddiForMv: Boolean = false)(implicit val p: Parameters) ext if (usingCompressed) { io.rvc := io.in(1,0) =/= 3.U - io.out := new RVCDecoder(io.in, p(XLen), useAddiForMv).decode + io.out := new RVCDecoder(io.in, p(XLen), useAddiForMv, usingBitManip, usingMulDiv, usingCompressedSuiteB).decode } else { io.rvc := false.B - io.out := new RVCDecoder(io.in, p(XLen), useAddiForMv).passthrough + io.out := new RVCDecoder(io.in, p(XLen), useAddiForMv, usingBitManip, usingMulDiv, usingCompressedSuiteB).passthrough } } diff --git a/src/main/scala/rocket/RocketCore.scala b/src/main/scala/rocket/RocketCore.scala index f07fdb75baa..68bc29332d4 100644 --- a/src/main/scala/rocket/RocketCore.scala +++ b/src/main/scala/rocket/RocketCore.scala @@ -23,6 +23,7 @@ case class RocketCoreParams( useAtomics: Boolean = true, useAtomicsOnlyForIO: Boolean = false, useCompressed: Boolean = true, + useCompressedSuiteB: Boolean = false, useRVE: Boolean = false, useSCIE: Boolean = false, useBitManip: Boolean = false, diff --git a/src/main/scala/tile/Core.scala b/src/main/scala/tile/Core.scala index 70c47836785..934c4dbfeba 100644 --- a/src/main/scala/tile/Core.scala +++ b/src/main/scala/tile/Core.scala @@ -22,6 +22,7 @@ trait CoreParams { val useAtomics: Boolean val useAtomicsOnlyForIO: Boolean val useCompressed: Boolean + val useCompressedSuiteB: Boolean val useBitManip: Boolean val useBitManipCrypto: Boolean val useVector: Boolean = false @@ -86,6 +87,7 @@ trait HasCoreParameters extends HasTileParameters { val usingAtomicsOnlyForIO = coreParams.useAtomicsOnlyForIO val usingAtomicsInCache = usingAtomics && !usingAtomicsOnlyForIO val usingCompressed = coreParams.useCompressed + val usingCompressedSuiteB = coreParams.useCompressedSuiteB && usingCompressed val usingBitManip = coreParams.useBitManip val usingBitManipCrypto = coreParams.hasBitManipCrypto val usingVector = coreParams.useVector From 98064d10032fb4aef3bd409da3a038bafad9c3dc Mon Sep 17 00:00:00 2001 From: Abdul Wadood Date: Sun, 21 May 2023 22:12:01 +0500 Subject: [PATCH 6/8] Added Decription for RVCDecoder Parameters Signed-off-by: Abdul Wadood --- src/main/scala/rocket/RVC.scala | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/src/main/scala/rocket/RVC.scala b/src/main/scala/rocket/RVC.scala index 5fbf24158af..ec8c3092524 100644 --- a/src/main/scala/rocket/RVC.scala +++ b/src/main/scala/rocket/RVC.scala @@ -16,6 +16,16 @@ class ExpandedInstruction extends Bundle { val rs3 = UInt(5.W) } +/* Parameters for RVCDecoder + - Zcb extension contains the compressed I-type (c.lbu, lhu, lh, sb, sh) , M-type (c.mul) + and Bit Manip instructions. + - **usingCompressedSuiteB** parameter is used to enable/disable "Zcb" extension in RocketCore. + - If Zcb is enabled, furthur **usingBitManip** and **usingMulDiv** parameters (if set as True) are used to decode + the corresponding BitManip and M type Instructions. + - If **usingCompressedSuiteB** parameter is not set (i.e. False), decoder will give "unimp" + instruction if it encounters any Zcb instruction. Same is true for **usingBitManip** and **usingMulDiv**. +*/ + class RVCDecoder(x: UInt, xLen: Int, useAddiForMv: Boolean = false, usingBitManip: Boolean = false, usingMulDiv: Boolean = false, usingCompressedSuiteB: Boolean = false) { def inst(bits: UInt, rd: UInt = x(11,7), rs1: UInt = x(19,15), rs2: UInt = x(24,20), rs3: UInt = x(31,27)) = { val res = Wire(new ExpandedInstruction) From 0ebed645fd2b1b4d82c742d5ace4f0a68e944a3d Mon Sep 17 00:00:00 2001 From: Abdul Wadood Date: Sun, 21 May 2023 22:42:01 +0500 Subject: [PATCH 7/8] Added `zca` and `zcb` in Device Tree Source Signed-off-by: Abdul Wadood --- src/main/scala/tile/BaseTile.scala | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/main/scala/tile/BaseTile.scala b/src/main/scala/tile/BaseTile.scala index 1265cb622bb..0ae7674ce66 100644 --- a/src/main/scala/tile/BaseTile.scala +++ b/src/main/scala/tile/BaseTile.scala @@ -113,6 +113,10 @@ trait HasNonDiplomaticTileParameters { Option.when(tileParams.core.useConditionalZero)(Seq("zicond")) ++ Some(Seq("zicsr", "zifencei", "zihpm")) ++ Option.when(tileParams.core.fpu.nonEmpty && tileParams.core.fpu.get.fLen >= 16 && tileParams.core.fpu.get.minFLen <= 16)(Seq("zfh")) ++ + Option.when(tileParams.core.useCompressed)(Seq("zca")) ++ + Option.when(tileParams.core.useCompressedSuiteB)(Seq("zcb")) ++ + Option.when(tileParams.core.useCompressed && tileParams.core.fpu.nonEmpty && tileParams.core.fpu.get.fLen > 32)(Seq("zcd")) ++ + Option.when(tileParams.core.useCompressed && tileParams.core.fpu.nonEmpty)(Seq("zcf")) ++ Option.when(tileParams.core.useBitManip)(Seq("zba", "zbb", "zbc")) ++ Option.when(tileParams.core.hasBitManipCrypto)(Seq("zbkb", "zbkc", "zbkx")) ++ Option.when(tileParams.core.useBitManip)(Seq("zbs")) ++ From 05ee78a296a47d4ec79b757f35c9617242e92619 Mon Sep 17 00:00:00 2001 From: Abdul Wadood Date: Mon, 3 Jul 2023 11:01:22 +0500 Subject: [PATCH 8/8] Optimization: Update RVC.scala for `zcb` instructions Signed-off-by: Abdul Wadood --- src/main/scala/rocket/RVC.scala | 51 +++++++++++++++------------------ 1 file changed, 23 insertions(+), 28 deletions(-) diff --git a/src/main/scala/rocket/RVC.scala b/src/main/scala/rocket/RVC.scala index ec8c3092524..d92a4254957 100644 --- a/src/main/scala/rocket/RVC.scala +++ b/src/main/scala/rocket/RVC.scala @@ -119,10 +119,9 @@ class RVCDecoder(x: UInt, xLen: Int, useAddiForMv: Boolean = false, usingBitMani def beqz = inst(Cat(bImm(12), bImm(10,5), x0, rs1p, 0.U(3.W), bImm(4,1), bImm(11), 0x63.U(7.W)), rs1p, rs1p, x0) def bnez = inst(Cat(bImm(12), bImm(10,5), x0, rs1p, 1.U(3.W), bImm(4,1), bImm(11), 0x63.U(7.W)), x0, rs1p, x0) def arith = { - val srai_srli_common = Cat(shamt, rs1p, 5.U(3.W), rs1p, 0x13.U(7.W)) - def srli = inst(srai_srli_common, rs1p, rs1p, rs2p) - def srai = inst(Cat(0x10.U, srai_srli_common), rs1p, rs1p, rs2p) - def andi = inst(Cat(addiImm, rs1p, 7.U(3.W), rs1p, 0x13.U(7.W)), rs1p, rs1p, rs2p) + def srli = Cat(shamt, rs1p, 5.U(3.W), rs1p, 0x13.U(7.W)) + def srai = Cat(0x10.U, srli) + def andi = Cat(addiImm, rs1p, 7.U(3.W), rs1p, 0x13.U(7.W)) def rtype = { val funct = Seq(0.U, 4.U, 6.U, 7.U, 0.U, 0.U, 0.U, 3.U)(Cat(x(12), x(6,5))) val sub = Mux(x(6,5) === 0.U, (1 << 30).U, 0.U) @@ -131,39 +130,35 @@ class RVCDecoder(x: UInt, xLen: Int, useAddiForMv: Boolean = false, usingBitMani if(usingMulDiv && usingCompressedSuiteB) Mux(Cat(x(12), x(6,5)) === 6.U, (1 << 25).U, 0.U) else 0.U } - def zca = inst(Cat(rs2p, rs1p, funct, rs1p, opc) | sub | mul, rs1p, rs1p, rs2p) + def zca = Cat(rs2p, rs1p, funct, rs1p, opc) | sub | mul def zcb_q1 = { - def unimp = inst(Cat(lwImm >> 5, rs2p, rs1p, 2.U(3.W), lwImm(4,0), 0x3F.U(7.W)), rs2p, rs1p, rs2p) + def unimp = Cat(lwImm >> 5, rs2p, rs1p, 2.U(3.W), lwImm(4,0), 0x3F.U(7.W)) if(usingCompressedSuiteB){ - def zextb = inst(Cat(0xFF.U, rs1p, 7.U(3.W), rs1p, 0x13.U(7.W)), rs1p, rs1p, rs2p) - def not = inst(Cat(0xFFF.U, rs1p, 4.U(3.W), rs1p, 0x13.U(7.W)), rs1p, rs1p, rs2p) - def sextb = { - if(usingBitManip) inst(Cat(0x604.U, rs1p, 1.U(3.W), rs1p, 0x13.U(7.W)), rs1p, rs1p, rs2p) - else unimp - } - def sexth = { - if(usingBitManip) inst(Cat(0x605.U, rs1p, 1.U(3.W), rs1p, 0x13.U(7.W)), rs1p, rs1p, rs2p) - else unimp - } - def zextw = { - if(usingBitManip) inst(Cat(4.U, x0, rs1p, 0.U(3.W), rs1p, 0x3B.U(7.W)), rs1p, rs1p, x0) - else unimp - } + def zextb = Cat(0xFF.U, rs1p, 7.U(3.W), rs1p, 0x13.U(7.W)) + def not = Cat(0xFFF.U, rs1p, 4.U(3.W), rs1p, 0x13.U(7.W)) + def sextb = Cat(0x604.U, rs1p, 1.U(3.W), rs1p, 0x13.U(7.W)) + def sexth = Cat(0x605.U, rs1p, 1.U(3.W), rs1p, 0x13.U(7.W)) + def zextw = Cat(4.U, x0, rs1p, 0.U(3.W), rs1p, 0x3B.U(7.W)) def zexth = { - if(usingBitManip) { - val zexth_common = Cat(0x80.U, rs1p, 4.U(3.W), rs1p) - if (xLen == 32) inst(Cat(zexth_common, 0x33.U(7.W)), rs1p, rs1p, rs2p) - else inst(Cat(zexth_common, 0x3B.U(7.W)), rs1p, rs1p, rs2p) - } - else unimp + val zexth_common = Cat(0x80.U, rs1p, 4.U(3.W), rs1p) + if (xLen == 32) Cat(zexth_common, 0x33.U(7.W)) + else Cat(zexth_common, 0x3B.U(7.W)) + } + if(usingBitManip){ + Seq(zextb, sextb, zexth, sexth, zextw, not, unimp, unimp)(x(4,2)) + } else { + Mux (x(4,2)=== 5.U, not, Mux (x(4,2) === 0.U, zextb, unimp)) } - Seq(zextb, sextb, zexth, sexth, zextw, not)(x(4,2)) } else unimp } Mux(Cat(x(12), x(6,5)) === 7.U, zcb_q1, zca) } - Seq(srli, srai, andi, rtype)(x(11,10)) + def op2 = { + if(usingCompressedSuiteB) Mux(Cat(x(15,10), x(6,2)) === 0x4FC.U, x0, rs2p) + else rs2p + } + inst(Seq(srli, srai, andi, rtype)(x(11,10)), rs1p, rs1p, op2) } Seq(addi, jal, li, lui, arith, j, beqz, bnez) }