From cde5a3bbe84adba7d28143ca4b990435603758ac Mon Sep 17 00:00:00 2001 From: Waxpple Date: Thu, 23 Jun 2022 11:01:39 +0800 Subject: [PATCH] Set initial `clock = 1'b1;` Set `clock = 1'b1;` to avoid the first reset signal only using half of the clock cycle. If want to avoid the first reset cycle using only half clock period causing timing violation, modify `TestDriver.v` like this: ![image](https://user-images.githubusercontent.com/20642651/175191673-3447a393-b064-4dc5-8584-9fd30480d166.png) The waveform will be: ![image](https://user-images.githubusercontent.com/20642651/175193123-431b326b-e706-4f40-ab6b-71150b49065a.png) The original testbench will look like this: ![image](https://user-images.githubusercontent.com/20642651/175190617-b13a16eb-2187-4cf1-8bc5-c6d5c9d23c8b.png) The waveform will be ![image](https://user-images.githubusercontent.com/20642651/175191639-2ae13e6b-ef4b-4026-8282-2dd4f03bd8b5.png) --- src/main/resources/vsrc/TestDriver.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/resources/vsrc/TestDriver.v b/src/main/resources/vsrc/TestDriver.v index f9b7f5ae40a..9df5dc1d48d 100644 --- a/src/main/resources/vsrc/TestDriver.v +++ b/src/main/resources/vsrc/TestDriver.v @@ -8,8 +8,8 @@ `endif module TestDriver; - - reg clock = 1'b0; + // Set `clock = 1'b1;` to avoid the first reset signal only using half of the clock cycle. + reg clock = 1'b1; reg reset = 1'b1; always #(`CLOCK_PERIOD/2.0) clock = ~clock;