From 823559c98b6824b19f25b56c23f3ee663c59d656 Mon Sep 17 00:00:00 2001 From: Nandor Licker Date: Tue, 28 Nov 2023 11:13:56 +0200 Subject: [PATCH 1/7] Define option groups and instance choices --- include/firrtl.xml | 3 ++ revision-history.yaml | 2 ++ spec.md | 68 +++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 73 insertions(+) diff --git a/include/firrtl.xml b/include/firrtl.xml index b59b18d0..3921aa70 100644 --- a/include/firrtl.xml +++ b/include/firrtl.xml @@ -7,6 +7,7 @@ extmodule intmodule layer + option input @@ -27,6 +28,8 @@ propassign public enablelayer + instchoice + case UInt diff --git a/revision-history.yaml b/revision-history.yaml index fde94352..c48c14b9 100644 --- a/revision-history.yaml +++ b/revision-history.yaml @@ -26,12 +26,14 @@ revisionHistory: - Main module must be public. - Make commas mandatory, not whitespace. - Update intrinsic module example to use a real intrinsic. + - Add instance choice. abi: - Add ABI for public modules and filelist output. - Changed ABI for group and ref generated files. These now use the public module and not the circuit. - Use EBNF to describe probe port macros and filename. - Correct mistakes in code examples. + - Add instance choice. # Information about the old versions. This should be static. oldVersions: - version: 3.2.0 diff --git a/spec.md b/spec.md index ecd0c5d4..e30e1228 100644 --- a/spec.md +++ b/spec.md @@ -152,6 +152,32 @@ Private modules have none of the restrictions of public modules. Private modules have no stable, defined interface and may not be used outside the current circuit. A private module may not be physically present in a compiled circuit. +## Option Groups + +The option group mechanism declares configurable parameters with a pre-defined set of values to enable the specialization of designs during or after lowering. +Options groups address the need for configurability. +For example, designs may need to behave differently on ASIC and FPGA platforms, but at the time of FIRRTL elaboration it is not known which platform the design will be used on. +This feature allows such choices to be expressed and embedded into the design. + +The `option`{.firrtl} keyword declares an option group, which contains `case`{.firrtl} declarations naming the settings allotted to that option. +The circuit can be specialized for a single case of a given option at any time. +Multiple option groups can be declared to capture orthogonal dimensions of configuration. + +Specialization can occur either in the compiler or it can be materialized in the lowering. +For details, consult the FIRRTL ABI specification. +Specialization is not mandatory: options can be left unspecified, resorting to explicitly-defined default behaviour. + +``` firrtl +circuit: + option Platform: + case FPGA: + case ASIC: + + option Performance: + case Slow: + case Fast +``` + ## Externally Defined Modules Externally defined modules are modules whose implementation is not provided in the current circuit. @@ -481,6 +507,36 @@ circuit Foo: ;; snippetend ``` +#### Instance Choices + +FIRRTL supports the specialization of designs through the `instchoice`{.firrtl} declaration, which selects the instantiated module based on an `option`{.firrtl}. + +Example: + +``` firrtl +circuit: + option Platform: + case FPGA: + case ASIC: + + module InstanceChoice: + instchoice clock_gate of DefaultTarget, Platform: + FPGA => FPGATarget + + module DefaultTarget: + + module FPGATarget: +``` + +The instance choice declaration specifies the instance name and names the option group based on which the choices are selected. +A default module is provided, to be instantiated when the design is not specialized or it is not specialised for a known case. +Subsequently, modules can be specified for the known choices of the selected option group. +The operation does not need to specify modules for all cases. +The references must be either modules or extmodules. + +The type of the instance bundle is determined identically to regular instances. +The port lists of all modules must match and the ports are limited to ground and aggregate types. + ### Memories Memories are stateful elements of a design. @@ -4128,6 +4184,7 @@ decl = | decl_extmodule | decl_intmodule | decl_layer + | decl_option | decl_type_alias ; decl_module = @@ -4156,6 +4213,11 @@ decl_layer = { decl_layer , newline } , dedent ; +decl_option = + "option" , id , ":" , [info] , newline, indent , + { "case" , id , ":" , [ info ] , newline } , + dedent ; + decl_type_alias = "type", id, "=", type ; port = ( "input" | "output" ) , id , ":" , (type | type_property) , [ info ] ; @@ -4177,11 +4239,17 @@ circuit_component = | circuit_component_wire | circuit_component_reg | circuit_component_inst + | circuit_component_instchoice | circuit_component_mem ; circuit_component_node = "node" , id , "=" , expr , [ info ] ; circuit_component_wire = "wire" , id , ":" , type , [ info ] ; circuit_component_inst = "inst" , id , "of" , id , [ info ] ; +circuit_component_instchoice = + "instchoice" , id , "of" , id , "," , id , ":" , newline , + indent , + { id , "=>" , id , newline } , + dedent; circuit_component_reg = "reg" , id , ":" , type , expr , [ info ] From 6b11e2e9fdbc1c79bd5f59d4f660496d9cf3a9f7 Mon Sep 17 00:00:00 2001 From: Schuyler Eldridge Date: Wed, 8 May 2024 19:46:09 -0400 Subject: [PATCH 2/7] squash! Define option groups and instance choices Rewrite to use language of "targets" and "options". Decouple targets/options from instance choices. An instance choice is associated with a target, but the two are not intrinsically linked. --- spec.md | 109 +++++++++++++++++++++++++++++++++----------------------- 1 file changed, 64 insertions(+), 45 deletions(-) diff --git a/spec.md b/spec.md index e30e1228..110bee3a 100644 --- a/spec.md +++ b/spec.md @@ -152,32 +152,6 @@ Private modules have none of the restrictions of public modules. Private modules have no stable, defined interface and may not be used outside the current circuit. A private module may not be physically present in a compiled circuit. -## Option Groups - -The option group mechanism declares configurable parameters with a pre-defined set of values to enable the specialization of designs during or after lowering. -Options groups address the need for configurability. -For example, designs may need to behave differently on ASIC and FPGA platforms, but at the time of FIRRTL elaboration it is not known which platform the design will be used on. -This feature allows such choices to be expressed and embedded into the design. - -The `option`{.firrtl} keyword declares an option group, which contains `case`{.firrtl} declarations naming the settings allotted to that option. -The circuit can be specialized for a single case of a given option at any time. -Multiple option groups can be declared to capture orthogonal dimensions of configuration. - -Specialization can occur either in the compiler or it can be materialized in the lowering. -For details, consult the FIRRTL ABI specification. -Specialization is not mandatory: options can be left unspecified, resorting to explicitly-defined default behaviour. - -``` firrtl -circuit: - option Platform: - case FPGA: - case ASIC: - - option Performance: - case Slow: - case Fast -``` - ## Externally Defined Modules Externally defined modules are modules whose implementation is not provided in the current circuit. @@ -333,6 +307,40 @@ circuit Foo : public module Foo enablelayer A : ``` +## Targets + +A `target`{.firrtl} describes one way that a FIRRTL circuit may be specialized for a certain use case. +Here, specialization means choosing a specific option for a target. + +It is often desirable to have one FIRRTL circuit that has different logic when simulated, synthesized and mapped to a field-programmable gate array (FPGA), or synthesized to a given process technology and standard cell library. +While this per-target customizability can be expressed and specialized in a frontend language that produces FIRRTL, it is often desirable to expose the target specialization in the FIRRTL. +By delaying the specialization, the specialization can either be done by a FIRRTL compiler or exposed in the artifacts of a FIRRTL compiler for specialization by the consumer. + +Practically, targets describe a limited form of parameterization and, if not specialized by a FIRRTL compiler, allow for FIRRTL compilers to generate parametric artifacts (e.g., parametric Verilog). + +The `option`{.firrtl} keyword declares an option group, which contains `case`{.firrtl} declarations naming the settings allotted to that option. +The circuit can be specialized for a single case of a given option at any time. +Multiple option groups can be declared to capture orthogonal dimensions of configuration. + +Specialization can occur either in the compiler or it can be materialized in the lowering. +For details, consult the FIRRTL ABI specification. +Specialization is not mandatory: options can be left unspecified, resorting to explicitly-defined default behaviour. + +A target may be delcared using the `target`{.firrtl} keyword. +The availble options for which a target may take are listed using the `option`{.firrtl} keyword. +An example FIRRTL circuit showing two targets, `Platform` and `Performance`, and their allowable options is shown below: + +``` firrtl +circuit: + target Platform: + option FPGA + option ASIC + + target Performance: + option Slow + option Fast +``` + # Circuit Components Circuit components are the named parts of a module corresponding to hardware. @@ -507,35 +515,46 @@ circuit Foo: ;; snippetend ``` -#### Instance Choices +#### Instance Choice -FIRRTL supports the specialization of designs through the `instchoice`{.firrtl} declaration, which selects the instantiated module based on an `option`{.firrtl}. +An instance choice is a submodule instance where the choice of submodule is conditioned based on the value of a `target`{.firrtl}. +This enables per-instance specialization for different targets. +Additionally, this is a mechanism for module replacement. -Example: +An instance choice declaration specifies the instance name and names the option group based on which the choices are selected. +A default module must be provided. +The default module is instantiated by the instance choice when an option for its associated target is not specified. +Subsequently, modules can be specified for the known choices of the selected option group. +An instance choice does not need to specify modules for all cases. +The instantiated modules must be either modules or external modules. + +An example of an instance choice is shown below. +This instance choice is conditioned on the `Platform` target. +By default, it will instantiate `DefaultClockGate` and when `Platform` is `FPGA` it will instantiate `FPGAClockGate`. ``` firrtl circuit: - option Platform: - case FPGA: - case ASIC: + targe Platform: + option FPGA + option ASIC - module InstanceChoice: - instchoice clock_gate of DefaultTarget, Platform: - FPGA => FPGATarget + module DefaultClockGate: + input clock_in: Clock + output clock_out: Clock + input enable: UInt<1> - module DefaultTarget: + extmodule FPGAClockGate: + input clock_in: Clock + output clock_out: Clock + input enable: UInt<1> - module FPGATarget: + module InstanceChoice: + instchoice clock_gate of DefaultClockGate, Platform: + FPGA => FPGAClockGate ``` -The instance choice declaration specifies the instance name and names the option group based on which the choices are selected. -A default module is provided, to be instantiated when the design is not specialized or it is not specialised for a known case. -Subsequently, modules can be specified for the known choices of the selected option group. -The operation does not need to specify modules for all cases. -The references must be either modules or extmodules. - -The type of the instance bundle is determined identically to regular instances. -The port lists of all modules must match and the ports are limited to ground and aggregate types. +The type of an instance choice is the same as an instantiation of the default module. +The ports of all module choices must be the same as the default module. ### Memories From bce9deb7aa75fd2fc35309f340bf5c16bd4f8ff4 Mon Sep 17 00:00:00 2001 From: Schuyler Eldridge Date: Wed, 8 May 2024 21:28:39 -0400 Subject: [PATCH 3/7] squash! Define option groups and instance choices Add ABI for targets. --- abi.md | 104 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 104 insertions(+) diff --git a/abi.md b/abi.md index e9041f95..a8b8e3af 100644 --- a/abi.md +++ b/abi.md @@ -311,6 +311,110 @@ bind Bar Bar_Layer1_Layer2 layer1_layer2(.notA(Bar.layer1.notA)); The `` `ifdef ``{.verilog} guards enable any combination of the bind files to be included while still producing legal SystemVerilog. I.e., the end user may safely include none, either, or both of the bindings files. +## On Targets + +A target will result in the creation of one file per option for that target. +When one of these files is included in elaboration of the Verilog produced by a FIRRTL compiler, this will have the effect of specializing the design with that option. + +Each file must have the following filename where `target` is the name of the target and `option` is the name of the option: + +``` ebnf +filename = "targets_" , target , "_", option , ".sv" ; +``` + +This file will guard for multiple inclusion. +Namely, if two files that specialize the same target are included, this must produce an error. +If the file is included after a module which relies on the specialization, this must produce an error. + +### Example + +The following circuit is an example implementation of how a target can be lowered to align with the ABI defined above. +This circuit has one target named `Target` with two options, `A` and `B`. +Module `Foo` may be specialized using an instance choice that will instantiate `Bar` by default and `Baz` if `Target` is set to `A`. +If `Target` is set to `B`, then the default instantiation, `Bar`, will occur. + +``` firrtl +FIRRTL version 4.0.0 +circuit Foo: + + target Target: + option A + option B + + module Baz: + output a: UInt<1> + + connect a, UInt<1>(1) + + module Bar: + output a: UInt<1> + + connect b, UInt<1>(0) + + public module Foo: + output a: UInt<1> + + instchoice x of Bar, Target: + A => Baz + + connect a, x.a +``` + +To align with the ABI, this must produce the following files to specialize the circuit for option `A` or option `B`, respectively: + +- `targets_Target_A.sv` +- `targets_Target_B.sv` + +What follows describes a possible implementation that aligns with the ABI. +Note that the internal details are not part of the ABI. + +When compiled, this produces the following Verilog: + +``` systemverilog +module Baz(output a); + assign a = 1'h1; +endmodule + +module Bar(output a); + assign a = 1'h0; +endmodule + +module Foo(output a); + +`ifndef target_Target_foo_x + `define target_Target_foo_x Bar +`endif + `target_Target_foo_x x(.a(a)); + +endmodule +``` + +The contents of the two option enabling files are shown below: + +``` systemverilog +// Contents of "targets_Target_A.sv" +`ifdef target_Target_foo_x + `ERROR__target_Target_foo_x__must__not__be__set +`endif + +`define target_Target_foo_x Baz +``` + +``` systemverilog +// Contents of "targets_Target_B.sv" +`ifdef target_Target_foo_x + `ERROR__target_Target_foo_x__must__not__be__set +`endif + +// This file has no defines. +``` + +If neither of the option enabling files are included, then `Bar` will by default be instantiated. +If `targets_Target_A.sv` is included before elaboration of `Foo`, then `Baz` will be instantiated. +If `targets_Target_B.sv` is included before elaboration of `Foo`, then `Bar` will be instantiated. +If both `targets_Target_A.sv` and `targets_Target_B.sv` are included, then an error (by means of an undefined macro error) will be produced. +If either `targets_Target_A.sv` or `targets_Target_B.sv` are included after `Foo` is elaborated, then an error will be produced. + ## On Types Types are only guaranteed to follow this lowering when the Verilog type is on an element which is part of the ABI defined public elements. From 9e1756319f6df163fbafab2ded4ae75651f98b0e Mon Sep 17 00:00:00 2001 From: Schuyler Eldridge Date: Tue, 14 May 2024 00:22:31 -0400 Subject: [PATCH 4/7] fixup! Define option groups and instance choices --- abi.md | 78 ++++++++++++++++++++++++++++++++++++++-------------------- 1 file changed, 52 insertions(+), 26 deletions(-) diff --git a/abi.md b/abi.md index a8b8e3af..6d790b00 100644 --- a/abi.md +++ b/abi.md @@ -313,16 +313,18 @@ I.e., the end user may safely include none, either, or both of the bindings file ## On Targets -A target will result in the creation of one file per option for that target. -When one of these files is included in elaboration of the Verilog produced by a FIRRTL compiler, this will have the effect of specializing the design with that option. +A target will result in the creation of specialization files. +One specialization file per public module per option for a given target will be created. -Each file must have the following filename where `target` is the name of the target and `option` is the name of the option: +Including a specialization file in the elaboration of Verilog produced by a FIRRTL compiler specializes the instantiation hierarchy of a public module with that option. + +Each specialization file must have the following filename where `module` is the name of the public module, `target` is the name of the target, and `option` is the name of the option: ``` ebnf -filename = "targets_" , target , "_", option , ".sv" ; +filename = "targets_" , module , "_" , target , "_", option , ".sv" ; ``` -This file will guard for multiple inclusion. +Each specialization file will guard for multiple inclusion. Namely, if two files that specialize the same target are included, this must produce an error. If the file is included after a module which relies on the specialization, this must produce an error. @@ -332,6 +334,7 @@ The following circuit is an example implementation of how a target can be lowere This circuit has one target named `Target` with two options, `A` and `B`. Module `Foo` may be specialized using an instance choice that will instantiate `Bar` by default and `Baz` if `Target` is set to `A`. If `Target` is set to `B`, then the default instantiation, `Bar`, will occur. +Module `Foo` includes a probe whose define is inside the instance choice. ``` firrtl FIRRTL version 4.0.0 @@ -342,28 +345,30 @@ circuit Foo: option B module Baz: - output a: UInt<1> + output a: Probe> - connect a, UInt<1>(1) + node c = UInt<1>(1) + define a = probe(c) module Bar: - output a: UInt<1> + output a: Probe> - connect b, UInt<1>(0) + node b = UInt<1>(0) + define a = probe(b) public module Foo: - output a: UInt<1> + output a: Probe> instchoice x of Bar, Target: A => Baz - connect a, x.a + define a = x.a ``` To align with the ABI, this must produce the following files to specialize the circuit for option `A` or option `B`, respectively: -- `targets_Target_A.sv` -- `targets_Target_B.sv` +- `targets_Foo_Target_A.sv` +- `targets_Foo_Target_B.sv` What follows describes a possible implementation that aligns with the ABI. Note that the internal details are not part of the ABI. @@ -379,12 +384,14 @@ module Bar(output a); assign a = 1'h0; endmodule -module Foo(output a); - -`ifndef target_Target_foo_x - `define target_Target_foo_x Bar +// Defines for the instance choices +`ifndef __target_Target_foo_x + `define __target_Target_foo_x Bar `endif - `target_Target_foo_x x(.a(a)); + +module Foo(); + + `__target_Target_foo_x x(); endmodule ``` @@ -393,27 +400,46 @@ The contents of the two option enabling files are shown below: ``` systemverilog // Contents of "targets_Target_A.sv" -`ifdef target_Target_foo_x - `ERROR__target_Target_foo_x__must__not__be__set +`ifdef __target_Target_foo_x + `ERROR__target_Target_foo_x__must__not__be__set +`else + `define __target_Target_foo_x Baz `endif -`define target_Target_foo_x Baz +`ifdef __targetref_Foo_x_a a + `ERROR__targetref_Foo_x_a__must__not__be__set +`else + `define __targetref_Foo_x_a a +`endif ``` ``` systemverilog // Contents of "targets_Target_B.sv" -`ifdef target_Target_foo_x +`ifdef __target_Target_foo_x `ERROR__target_Target_foo_x__must__not__be__set `endif // This file has no defines. ``` +Additionally, probe on public module `Foo` requires that the following file is produced: + +``` systemverilog +// Contents of "refs_Foo.sv" +`ifndef __targetref_Foo_x_a + `define __targetref_Foo_x_a b +`endif + +`define ref_Foo_x x.`__targetref_Foo_x_a +``` + If neither of the option enabling files are included, then `Bar` will by default be instantiated. -If `targets_Target_A.sv` is included before elaboration of `Foo`, then `Baz` will be instantiated. -If `targets_Target_B.sv` is included before elaboration of `Foo`, then `Bar` will be instantiated. -If both `targets_Target_A.sv` and `targets_Target_B.sv` are included, then an error (by means of an undefined macro error) will be produced. -If either `targets_Target_A.sv` or `targets_Target_B.sv` are included after `Foo` is elaborated, then an error will be produced. +If `targets_Foo_Target_A.sv` is included before elaboration of `Foo`, then `Baz` will be instantiated. +If `targets_Foo_Target_B.sv` is included before elaboration of `Foo`, then `Bar` will be instantiated. +If both `targets_Foo_Target_A.sv` and `targets_Foo_Target_B.sv` are included, then an error (by means of an undefined macro error) will be produced. +If either `targets_Foo_Target_A.sv` or `targets_Foo_Target_B.sv` are included after `Foo` is elaborated, then an error will be produced. + +If `ref_Foo.sv` is included before either `targets_Foo_Target_A.sv` or `targets_Foo_Target_B.sv`, then an error will be produced. ## On Types From ce20ae2bc2cb7a6e560d8dc5910c090bfb4cf173 Mon Sep 17 00:00:00 2001 From: Schuyler Eldridge Date: Tue, 14 May 2024 00:56:42 -0400 Subject: [PATCH 5/7] fixup! Define option groups and instance choices --- abi.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/abi.md b/abi.md index 6d790b00..ac9eeab8 100644 --- a/abi.md +++ b/abi.md @@ -316,7 +316,7 @@ I.e., the end user may safely include none, either, or both of the bindings file A target will result in the creation of specialization files. One specialization file per public module per option for a given target will be created. -Including a specialization file in the elaboration of Verilog produced by a FIRRTL compiler specializes the instantiation hierarchy of a public module with that option. +Including a specialization file in the elaboration of Verilog produced by a FIRRTL compiler specializes the instantiation hierarchy under the associated public module with that option. Each specialization file must have the following filename where `module` is the name of the public module, `target` is the name of the target, and `option` is the name of the option: From 9cece18f595c7bd9a4a89d8118af05e817836401 Mon Sep 17 00:00:00 2001 From: Schuyler Eldridge Date: Tue, 14 May 2024 01:00:34 -0400 Subject: [PATCH 6/7] fixup! Define option groups and instance choices --- include/firrtl.xml | 4 ++-- spec.md | 14 +++++++------- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/include/firrtl.xml b/include/firrtl.xml index 3921aa70..a7ecf1d1 100644 --- a/include/firrtl.xml +++ b/include/firrtl.xml @@ -7,7 +7,7 @@ extmodule intmodule layer - option + target input @@ -29,7 +29,7 @@ public enablelayer instchoice - case + option UInt diff --git a/spec.md b/spec.md index 110bee3a..76aab539 100644 --- a/spec.md +++ b/spec.md @@ -326,8 +326,8 @@ Specialization can occur either in the compiler or it can be materialized in the For details, consult the FIRRTL ABI specification. Specialization is not mandatory: options can be left unspecified, resorting to explicitly-defined default behaviour. -A target may be delcared using the `target`{.firrtl} keyword. -The availble options for which a target may take are listed using the `option`{.firrtl} keyword. +A target may be declared using the `target`{.firrtl} keyword. +The available options for which a target may take are listed using the `option`{.firrtl} keyword. An example FIRRTL circuit showing two targets, `Platform` and `Performance`, and their allowable options is shown below: ``` firrtl @@ -534,7 +534,7 @@ By default, it will instantiate `DefaultClockGate` and when `Platform` is `FPGA` ``` firrtl circuit: - targe Platform: + target Platform: option FPGA option ASIC @@ -4203,7 +4203,7 @@ decl = | decl_extmodule | decl_intmodule | decl_layer - | decl_option + | decl_target | decl_type_alias ; decl_module = @@ -4232,9 +4232,9 @@ decl_layer = { decl_layer , newline } , dedent ; -decl_option = - "option" , id , ":" , [info] , newline, indent , - { "case" , id , ":" , [ info ] , newline } , +decl_target = + "target" , id , ":" , [info] , newline, indent , + { "option" , id , ":" , [ info ] , newline } , dedent ; decl_type_alias = "type", id, "=", type ; From a5dae254e67f6d22735b86c76f47bbcea492d7e2 Mon Sep 17 00:00:00 2001 From: Schuyler Eldridge Date: Tue, 14 May 2024 01:13:28 -0400 Subject: [PATCH 7/7] fixup! Define option groups and instance choices --- abi.md | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/abi.md b/abi.md index ac9eeab8..b61511d1 100644 --- a/abi.md +++ b/abi.md @@ -321,7 +321,7 @@ Including a specialization file in the elaboration of Verilog produced by a FIRR Each specialization file must have the following filename where `module` is the name of the public module, `target` is the name of the target, and `option` is the name of the option: ``` ebnf -filename = "targets_" , module , "_" , target , "_", option , ".sv" ; +filename = "targets_" , module , "_" , target , "_", option , ".vh" ; ``` Each specialization file will guard for multiple inclusion. @@ -367,8 +367,8 @@ circuit Foo: To align with the ABI, this must produce the following files to specialize the circuit for option `A` or option `B`, respectively: -- `targets_Foo_Target_A.sv` -- `targets_Foo_Target_B.sv` +- `targets_Foo_Target_A.vh` +- `targets_Foo_Target_B.vh` What follows describes a possible implementation that aligns with the ABI. Note that the internal details are not part of the ABI. @@ -399,7 +399,7 @@ endmodule The contents of the two option enabling files are shown below: ``` systemverilog -// Contents of "targets_Target_A.sv" +// Contents of "targets_Target_A.vh" `ifdef __target_Target_foo_x `ERROR__target_Target_foo_x__must__not__be__set `else @@ -414,7 +414,7 @@ The contents of the two option enabling files are shown below: ``` ``` systemverilog -// Contents of "targets_Target_B.sv" +// Contents of "targets_Target_B.vh" `ifdef __target_Target_foo_x `ERROR__target_Target_foo_x__must__not__be__set `endif @@ -434,12 +434,12 @@ Additionally, probe on public module `Foo` requires that the following file is p ``` If neither of the option enabling files are included, then `Bar` will by default be instantiated. -If `targets_Foo_Target_A.sv` is included before elaboration of `Foo`, then `Baz` will be instantiated. -If `targets_Foo_Target_B.sv` is included before elaboration of `Foo`, then `Bar` will be instantiated. -If both `targets_Foo_Target_A.sv` and `targets_Foo_Target_B.sv` are included, then an error (by means of an undefined macro error) will be produced. -If either `targets_Foo_Target_A.sv` or `targets_Foo_Target_B.sv` are included after `Foo` is elaborated, then an error will be produced. +If `targets_Foo_Target_A.vh` is included before elaboration of `Foo`, then `Baz` will be instantiated. +If `targets_Foo_Target_B.vh` is included before elaboration of `Foo`, then `Bar` will be instantiated. +If both `targets_Foo_Target_A.vh` and `targets_Foo_Target_B.vh` are included, then an error (by means of an undefined macro error) will be produced. +If either `targets_Foo_Target_A.vh` or `targets_Foo_Target_B.vh` are included after `Foo` is elaborated, then an error will be produced. -If `ref_Foo.sv` is included before either `targets_Foo_Target_A.sv` or `targets_Foo_Target_B.sv`, then an error will be produced. +If `ref_Foo.vh` is included before either `targets_Foo_Target_A.vh` or `targets_Foo_Target_B.vh`, then an error will be produced. ## On Types