info.yaml

--- 
# TinyTapeout project information
project:
  wokwi_id:    0        # If using wokwi, set this to your project's ID
  source_files:        # If using an HDL, set wokwi_id as 0 and uncomment and list your source files here. Source files must be in ./src
    - fp8.v
  top_module:  "cchan_fp8_multiplier"      # put the name of your top module here, make it unique by prepending your github username

# As everyone will have access to all designs, try to make it easy for someone new to your design to know what
# it does and how to operate it.
#
# Here is an example: https://github.com/mattvenn/tinytapeout_m_segments/blob/main/info.yaml
#
# This info will be automatically collected and used to make a datasheet for the chip.
documentation: 
  author:       "Clive Chan"      # Your name
  discord:      "mrgoose#9005"      # Your discord handle - make sure to include the # part as well
  title:        "8-bit (E4M3) Floating Point Multiplier"      # Project title
  description:  "8-bit (E4M3) Floating Point Multiplier"      # Short description of what your project does
  how_it_works: >
    A small mux in front to fill up two 8-bit buffers in halves,
    which feed the actual 8-bit multiplier.

    When ctrl0 is 0, you can clock in 4 bits from data[3:0] into the upper or lower
    halves of two buffers according to the values of ctrl[1] and ctrl[2]:
    - 00 STORE 1 LOWER
    - 01 STORE 1 UPPER
    - 10 STORE 2 LOWER
    - 11 STORE 2 UPPER
    The clock is intended for manual use instead of actually being driven by a clock,
    but it probably can work.

    The 8 bits in each of the two buffers are interpreted as an 8-bit floating point number.
    From MSB to LSB:
    - sign bit
    - exponent[3:0]
    - mantissa[2:0]
    These are interpreted according to an approximation of IEEE 754, i.e.
      (-1)**sign * 2**(exponent - EXP_BIAS) * 1.mantissa
    with the following implementation details / differences:
    - EXP_BIAS = 7, analogous to 2**(exp-1) - 1 for all IEEE-defined formats
    - Denormals (i.e. exponent == 0) are flushed to zero on input and output
    - exponent = 0b1111 is interpreted as more normal numbers instead of NaN/inf,
        and overflows saturate to the largest representable number (0bx1111111 = +/- 480.0)
    - Negative zero is interpreted as NaN instead.
    - Round to nearest even is implemented.

    The output 8 bits will always display the results of the multiplication
    of the two FP8's in the buffers, regardless of the clock.

    The module has been verified over all possible pairs of 8-bit inputs.
  how_to_test:  >
    cd src && make
  external_hw:  ""      # Describe any external hardware needed
  language:     "Verilog" # other examples include Verilog, Amaranth, VHDL, etc
  doc_link:     ""      # URL to longer form documentation, eg the README.md in your repository
  clock_hz:     0       # Clock frequency in Hz (if required) we are expecting max clock frequency to be ~6khz. Provided on input 0.
  picture:      ""      # relative path to a picture in your repository
  inputs:               # a description of what the inputs do
    - clock
    - ctrl0
    - ctrl1
    - ctrl2
    - data0
    - data1
    - data2
    - data3
  outputs:
    - sign         # a description of what the outputs do
    - exponent
    - exponent
    - exponent
    - exponent
    - mantissa
    - mantissa
    - mantissa