From 5f5bb708a911ed88b6692c56f9bcd2c162365d24 Mon Sep 17 00:00:00 2001 From: Ayaka Yorihiro <36107281+ayakayorihiro@users.noreply.github.com> Date: Tue, 7 Jan 2025 02:47:58 +0900 Subject: [PATCH] Add reset to comb_mem_d4 (#2389) Turns out there was no reset input port to `comb_mem_d4` in `comb.futil`! :rofl: --- primitives/memories/comb.futil | 3 ++- tests/import/a.expect | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/primitives/memories/comb.futil b/primitives/memories/comb.futil index cbe4754ae5..556e345828 100644 --- a/primitives/memories/comb.futil +++ b/primitives/memories/comb.futil @@ -65,7 +65,8 @@ extern "comb.sv" { @read_together(1) @write_together(2) addr3: D3_IDX_SIZE, @write_together(1) @data write_data: WIDTH, @write_together(1) @interval(1) @go write_en: 1, - @clk clk: 1 + @clk clk: 1, + @reset reset: 1 ) -> ( @read_together(1) read_data: WIDTH, @done done: 1 diff --git a/tests/import/a.expect b/tests/import/a.expect index 5db2002bcb..7a7573e88e 100644 --- a/tests/import/a.expect +++ b/tests/import/a.expect @@ -8,7 +8,7 @@ extern "/calyx/primitives/memories/comb.sv" { primitive comb_mem_d1[WIDTH, SIZE, IDX_SIZE](@read_together addr0: IDX_SIZE, @write_together @data write_data: WIDTH, @write_together @interval @go write_en: 1, @clk clk: 1, @reset reset: 1) -> (@read_together read_data: WIDTH, @done done: 1); primitive comb_mem_d2[WIDTH, D0_SIZE, D1_SIZE, D0_IDX_SIZE, D1_IDX_SIZE](@read_together @write_together(2) addr0: D0_IDX_SIZE, @read_together @write_together(2) addr1: D1_IDX_SIZE, @write_together @data write_data: WIDTH, @write_together @interval @go write_en: 1, @clk clk: 1, @reset reset: 1) -> (@read_together read_data: WIDTH, @done done: 1); primitive comb_mem_d3[WIDTH, D0_SIZE, D1_SIZE, D2_SIZE, D0_IDX_SIZE, D1_IDX_SIZE, D2_IDX_SIZE](@read_together @write_together(2) addr0: D0_IDX_SIZE, @read_together @write_together(2) addr1: D1_IDX_SIZE, @read_together @write_together(2) addr2: D2_IDX_SIZE, @write_together @data write_data: WIDTH, @write_together @interval @go write_en: 1, @clk clk: 1, @reset reset: 1) -> (@read_together read_data: WIDTH, @done done: 1); - primitive comb_mem_d4[WIDTH, D0_SIZE, D1_SIZE, D2_SIZE, D3_SIZE, D0_IDX_SIZE, D1_IDX_SIZE, D2_IDX_SIZE, D3_IDX_SIZE](@read_together @write_together(2) addr0: D0_IDX_SIZE, @read_together @write_together(2) addr1: D1_IDX_SIZE, @read_together @write_together(2) addr2: D2_IDX_SIZE, @read_together @write_together(2) addr3: D3_IDX_SIZE, @write_together @data write_data: WIDTH, @write_together @interval @go write_en: 1, @clk clk: 1) -> (@read_together read_data: WIDTH, @done done: 1); + primitive comb_mem_d4[WIDTH, D0_SIZE, D1_SIZE, D2_SIZE, D3_SIZE, D0_IDX_SIZE, D1_IDX_SIZE, D2_IDX_SIZE, D3_IDX_SIZE](@read_together @write_together(2) addr0: D0_IDX_SIZE, @read_together @write_together(2) addr1: D1_IDX_SIZE, @read_together @write_together(2) addr2: D2_IDX_SIZE, @read_together @write_together(2) addr3: D3_IDX_SIZE, @write_together @data write_data: WIDTH, @write_together @interval @go write_en: 1, @clk clk: 1, @reset reset: 1) -> (@read_together read_data: WIDTH, @done done: 1); } extern "/calyx/primitives/core.sv" { comb primitive std_slice<"share"=1>[IN_WIDTH, OUT_WIDTH](@data in: IN_WIDTH) -> (out: OUT_WIDTH);