diff --git a/Makefile b/Makefile index 48e25b0..7b8f37a 100644 --- a/Makefile +++ b/Makefile @@ -39,7 +39,7 @@ LIBS = \ MAINTAINER_NAME = "$(shell git config user.name)" MAINTAINER_EMAIL = "$(shell git config user.email)" -all: version lib +all: lib version: @git fetch --tags --no-recurse-submodules diff --git a/VERSION b/VERSION index a3f5a8e..d9df1bb 100644 --- a/VERSION +++ b/VERSION @@ -1 +1 @@ -0.10.3 +0.11.0 diff --git a/bin/ckt b/bin/ckt index df53a29..7b89d16 160000 --- a/bin/ckt +++ b/bin/ckt @@ -1 +1 @@ -Subproject commit df53a29b51c23e5a26eb64805ac7afd14007df05 +Subproject commit 7b89d16ca7a25f54f59c6bc46bba363295a70914 diff --git a/lib/interpret_phy b/lib/interpret_phy index f968a51..dfcdf7c 160000 --- a/lib/interpret_phy +++ b/lib/interpret_phy @@ -1 +1 @@ -Subproject commit f968a518b6ab273b82f9729956f8450fc989e6da +Subproject commit dfcdf7c69db0d9668706c92bc66a9e0f167fccbb diff --git a/lib/interpret_prs b/lib/interpret_prs index 4b88fa1..e2ba837 160000 --- a/lib/interpret_prs +++ b/lib/interpret_prs @@ -1 +1 @@ -Subproject commit 4b88fa15460cd72c3bd07db6c216ff6f377d3d0c +Subproject commit e2ba8371d01ae2c7b2a195ae652d26f81dc949f6 diff --git a/lib/parse_prs b/lib/parse_prs index d7c6e38..05662de 160000 --- a/lib/parse_prs +++ b/lib/parse_prs @@ -1 +1 @@ -Subproject commit d7c6e385f8d96c1bc63d9bda82621a7bab935648 +Subproject commit 05662de6b2d62a341fbea495ffa800512b312607 diff --git a/lib/phy b/lib/phy index 42c1be8..bd7e07c 160000 --- a/lib/phy +++ b/lib/phy @@ -1 +1 @@ -Subproject commit 42c1be8aed730bbb755bd00e7e62da8d84ed22c4 +Subproject commit bd7e07c08e4e2ef67165d8926576d5b7d0397fb5 diff --git a/lib/prs b/lib/prs index f031601..630e382 160000 --- a/lib/prs +++ b/lib/prs @@ -1 +1 @@ -Subproject commit f03160151ed55c5f41f4a6810501f60a57e14781 +Subproject commit 630e382b9270b69cdca24a6d893cebbfc729104f diff --git a/lib/sch b/lib/sch index db9b9ef..369b98b 160000 --- a/lib/sch +++ b/lib/sch @@ -1 +1 @@ -Subproject commit db9b9ef007d1915cd657b148cb5cd2ea71f5cb1e +Subproject commit 369b98b60b71496c7f5c3ce64ca1c1615dcbd151 diff --git a/tech/sky130/tech.py b/tech/sky130/tech.py index d3dcf88..ac1ea5f 100755 --- a/tech/sky130/tech.py +++ b/tech/sky130/tech.py @@ -358,48 +358,63 @@ bound(areaid_sc) # Define Routing and Device Models -df = subst(diff, diff_label, diff_pin) -ns = subst(nsdm, no, no) -ps = subst(psdm, no, no) -hvp = subst(hvtp, no, no) -hvn = subst(hvntm, no, no) # TODO(edward.bingham) DRC rules -lvn = subst(lvtn, no, no) # TODO(edward.bingham) DRC rules -nvn = subst(nvtn, no, no) # TODO(edward.bingham) DRC rules -hvx = subst(hvi, no, no) # TODO(edward.bingham) DRC rules -nw = well(nwell, nwell_label, nwell_pin) -pw = well(no, pwell_label, pwell_pin) +nw = well(nwell, nwell_label, nwell_pin, resist=1700) +pw = well(no, pwell_label, pwell_pin, resist=3050) -p = route(poly, poly_label, poly_pin) -m0 = route(li1, li1_label, li1_pin) -m1 = route(met1, met1_label, met1_pin) -m2 = route(met2, met2_label, met2_pin) -m3 = route(met3, met3_label, met3_pin) -m4 = route(met4, met4_label, met4_pin) -m5 = route(met5, met5_label, met5_pin) +nd = subst(diff, diff_label, diff_pin, mask=[nsdm], excl=[hvtp, lvtn, hvi], well=pw, thick=.12, resist=120) +nd_lvt = subst(diff, diff_label, diff_pin, mask=[nsdm, lvtn], excl=[nvtn], well=pw, thick=.12, resist=120) +nd_nvt = subst(diff, diff_label, diff_pin, mask=[nsdm, nvtn], well=pw, thick=.12, resist=120) +nd_pin = subst(diff, diff_label, diff_pin, mask=[nsdm, hvtp, hvi], well=pw, thick=.12, resist=120) -nfet = nmos("svt", "sky130_fd_pr__nfet_01v8", [df, ns, pw], exclude=[hvp, lvn, hvx], bins=[(0,500)]) -nfet_lvt = nmos("lvt", "sky130_fd_pr__nfet_01v8_lvt", [df, ns, lvn, pw], exclude=[nvn], bins=[(0,500)]) -nfet_pin = nmos("npin", "sky130_fd_pr__nfet_g5v0d10v5", [df, ns, hvn, pw, hvx]) -nfet_nvt = nmos("nvt", "sky130_fd_pr__nfet_05v0_nvt", [df, ns, nvn, lvn, pw]) +pd = subst(diff, diff_label, diff_pin, mask=[psdm], excl=[hvtp, lvtn, hvi], well=nw, thick=.12, resist=197) +pd_hvt = subst(diff, diff_label, diff_pin, mask=[psdm, hvtp], well=nw, thick=.12, resist=197) +pd_lvt = subst(diff, diff_label, diff_pin, mask=[psdm, lvtn], well=nw, thick=.12, resist=197) +pd_pin = subst(diff, diff_label, diff_pin, mask=[psdm, hvi], well=nw, thick=.12, resist=197) -pfet = pmos("svt", "sky130_fd_pr__pfet_01v8", [df, ps, nw], exclude=[hvp, lvn, hvx], bins=[(0,500)]) -pfet_hvt = pmos("hvt", "sky130_fd_pr__pfet_01v8_hvt", [df, ps, hvp, nw], bins=[(0,500)]) -pfet_lvt = pmos("lvt", "sky130_fd_pr__pfet_01v8_lvt", [df, ps, lvn, nw], bins=[(0,500)]) -pfet_pin = pmos("ppin", "sky130_fd_pr__pfet_g5v0d10v5", [df, ps, nw, hvx]) +p = route(poly, poly_label, poly_pin, thick=.18, resist=48.2) +m0 = route(li1, li1_label, li1_pin, thick=.1, resist=12.8) +m1 = route(met1, met1_label, met1_pin, thick=.36, resist=0.125) +m2 = route(met2, met2_label, met2_pin, thick=.36, resist=0.125) +m3 = route(met3, met3_label, met3_pin, thick=.845, resist=0.047) +m4 = route(met4, met4_label, met4_pin, thick=.845, resist=0.047) +m5 = route(met5, met5_label, met5_pin, thick=1.26, resist=0.029) -via(nfet, m0, licon1) -via(nfet_lvt, m0, licon1) -via(nfet_pin, m0, licon1) -via(nfet_nvt, m0, licon1) -via(pfet, m0, licon1) -via(pfet_hvt, m0, licon1) -via(pfet_lvt, m0, licon1) -via(pfet_pin, m0, licon1) -via(p, m0, licon1) -via(m0, m1, mcon) -via(m1, m2, via1) -via(m2, m3, via2) -via(m3, m4, via3) -via(m4, m5, via4) +via(nd, m0, licon1, thick=.9361, resist=185) +via(nd_lvt, m0, licon1, thick=.9361, resist=185) +via(nd_pin, m0, licon1, thick=.9361, resist=185) +via(nd_nvt, m0, licon1, thick=.9361, resist=185) +via(pd, m0, licon1, thick=.9361, resist=585) +via(pd_hvt, m0, licon1, thick=.9361, resist=585) +via(pd_lvt, m0, licon1, thick=.9361, resist=585) +via(pd_pin, m0, licon1, thick=.9361, resist=585) +via(p, m0, licon1, thick=.4299, resist=150) +via(m0, m1, mcon, thick=.365, resist=152) +via(m1, m2, via1, thick=.27, resist=4.5) +via(m2, m3, via2, thick=.42, resist=3.41) +via(m3, m4, via3, thick=.39, resist=3.41) +via(m4, m5, via4, thick=.505, resist=.380) +dielec(nd, p, thick=.3262, permit=34.6193) +dielec(nd_lvt, p, thick=.3262, permit=34.6193) +dielec(nd_nvt, p, thick=.3262, permit=34.6193) +dielec(nd_pin, p, thick=.3262, permit=34.6193) +dielec(pd, p, thick=.3262, permit=34.6193) +dielec(pd_hvt, p, thick=.3262, permit=34.6193) +dielec(pd_lvt, p, thick=.3262, permit=34.6193) +dielec(pd_pin, p, thick=.3262, permit=34.6193) +dielec(p, m0, thick=0.4299, permit=40.48127556) +dielec(m0, m1, thick=0.365, permit=41.681905) +dielec(m1, m2, thick=0.27, permit=36.14247) +dielec(m2, m3, thick=0.42, permit=36.198162) +dielec(m3, m4, thick=0.39, permit=32.773494) +dielec(m4, m5, thick=0.505, permit=34.504226) +nmos("svt", "sky130_fd_pr__nfet_01v8", nd, bins=[(0,500)]) +nmos("lvt", "sky130_fd_pr__nfet_01v8_lvt", nd_lvt, bins=[(0,500)]) +nmos("nvt", "sky130_fd_pr__nfet_05v0_nvt", nd_nvt) +nmos("npin", "sky130_fd_pr__nfet_g5v0d10v5", nd_pin) + +pmos("svt", "sky130_fd_pr__pfet_01v8", pd, bins=[(0,500)]) +pmos("hvt", "sky130_fd_pr__pfet_01v8_hvt", pd_hvt, bins=[(0,500)]) +pmos("lvt", "sky130_fd_pr__pfet_01v8_lvt", pd_lvt, bins=[(0,500)]) +pmos("ppin", "sky130_fd_pr__pfet_g5v0d10v5", pd_pin)