Placer fails to find obvious gate alignments

[nbingham1]

Description

The transistor placement engine fails to find gate alignments that should be obvious.

Steps to Reproduce

lm -c cells build cell_imlmpalj.spi
klayout cell_imlmpalj.gds

Observe poor layout

cell_imlmpalj

.subckt cell_imlmpalj o3 GND Vdd i2 i0 i1
x0 GND i2 o3 GND sky130_fd_pr__nfet_01v8 w=0.45 l=0.15 ad=0.07875 as=0.07875 pd=0.8 ps=0.8
x1 GND i0 o3 GND sky130_fd_pr__nfet_01v8 w=0.45 l=0.15 ad=0.07875 as=0.07875 pd=0.8 ps=0.8
x2 GND i1 o3 GND sky130_fd_pr__nfet_01v8 w=0.45 l=0.15 ad=0.07875 as=0.07875 pd=0.8 ps=0.8
x3 __6 i0 o3 Vdd sky130_fd_pr__pfet_01v8 w=1.35 l=0.15 ad=0.23625 as=0.23625 pd=1.7 ps=1.7
x4 __7 i2 Vdd Vdd sky130_fd_pr__pfet_01v8 w=1.35 l=0.15 ad=0.23625 as=0.23625 pd=1.7 ps=1.7
x5 __6 i1 __7 Vdd sky130_fd_pr__pfet_01v8 w=1.35 l=0.15 ad=0.23625 as=0.23625 pd=1.7 ps=1.7
.ends

Expected Behavior

The pmos and nmos gates for i1 and i2 should be aligned.

Versions

• OS: Ubuntu 24.04.1 LTS
• Loom Version: v0.10.3

Supporting Files and Screenshots