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Virtual pin placement and layout constraint #21

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nbingham1 opened this issue Nov 15, 2024 · 0 comments
Open

Virtual pin placement and layout constraint #21

nbingham1 opened this issue Nov 15, 2024 · 0 comments
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@nbingham1
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enhancement New feature or request
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DRC and LVS Clean...

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@nbingham1
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Related Problem

Virtual pins are currently being placed at the very left of the cell. This creates long routes around the cell and increases parasitic capacitance.

Preferred Solution

Virtual pins should be placed optimally, and new RouteConstraints and PinConstraints should be created to enforce design rules.
@nbingham1 nbingham1 added the enhancement New feature or request label Nov 15, 2024
@nbingham1 nbingham1 self-assigned this Nov 15, 2024
@nbingham1 nbingham1 added this to the DRC and LVS Clean Cells milestone Nov 15, 2024
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enhancement New feature or request
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DRC and LVS Clean Cells
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@nbingham1