IO Pins are buried under routing layers

[nbingham1]

Description

Cell IO pins are buried under other routing layers, making it not possible to route wires between the IO of multiple cells.

Steps to Reproduce

lm -c cells build --no-cells cell_rgcsit1e.spi

cell_rgcsit1e.spi

.subckt cell_rgcsit1e o2 o3 GND Vdd i6 i5 i4
x0 __8 i5 o2 GND sky130_fd_pr__nfet_01v8 w=0.9 l=0.15 ad=0.1575 as=0.1575 pd=1.25 ps=1.25
x1 __9 i4 o3 GND sky130_fd_pr__nfet_01v8 w=0.9 l=0.15 ad=0.1575 as=0.1575 pd=1.25 ps=1.25
x2 GND i6 o3 GND sky130_fd_pr__nfet_01v8 w=0.45 l=0.15 ad=0.07875 as=0.07875 pd=0.8 ps=0.8
x3 GND o3 __8 GND sky130_fd_pr__nfet_01v8 w=0.9 l=0.15 ad=0.1575 as=0.1575 pd=1.25 ps=1.25
x4 GND o2 __9 GND sky130_fd_pr__nfet_01v8 w=0.9 l=0.15 ad=0.1575 as=0.1575 pd=1.25 ps=1.25
x5 Vdd o3 o2 Vdd sky130_fd_pr__pfet_01v8 w=0.45 l=0.15 ad=0.07875 as=0.07875 pd=0.8 ps=0.8
x6 Vdd i5 o2 Vdd sky130_fd_pr__pfet_01v8 w=0.45 l=0.15 ad=0.07875 as=0.07875 pd=0.8 ps=0.8
x7 __7 o2 o3 Vdd sky130_fd_pr__pfet_01v8 w=0.9 l=0.15 ad=0.1575 as=0.1575 pd=1.25 ps=1.25
x8 __7 i4 o3 Vdd sky130_fd_pr__pfet_01v8 w=0.9 l=0.15 ad=0.1575 as=0.1575 pd=1.25 ps=1.25
x9 __7 i6 Vdd Vdd sky130_fd_pr__pfet_01v8 w=0.9 l=0.15 ad=0.1575 as=0.1575 pd=1.25 ps=1.25
.ends

Observe that i6 cannot be reached through a via from metal 2.

Expected Behavior

IO pins are exposed with easy via connection.

Versions

• OS: Ubuntu 24.04.1 LTS
• Loom Version: v0.10.3

Supporting Files and Screenshots