From 12c303d89d54839a78b9d4d02018ff0ce747d376 Mon Sep 17 00:00:00 2001 From: Ned Bingham Date: Mon, 28 Oct 2024 20:19:19 -0400 Subject: [PATCH] fixing tech --- tech/sky130.py | 26 +++++++++++++++++++------- 1 file changed, 19 insertions(+), 7 deletions(-) diff --git a/tech/sky130.py b/tech/sky130.py index d9d6d71..a4b5ee5 100644 --- a/tech/sky130.py +++ b/tech/sky130.py @@ -263,6 +263,7 @@ cp1m_waffleDrop = paint("cp1m.waffleDrop", 33, 24) cfom_waffleDrop = paint("cfom.waffleDrop", 22, 24) cmm5_waffleDrop = paint("cmm5.waffleDrop", 117, 4) +nvtn = paint("nvtn", 251, 0) # Define DRC Rules fill(nwell) @@ -341,8 +342,11 @@ df = subst(diff, diff_label, diff_pin) ns = subst(nsdm, no, no) ps = subst(psdm, no, no) -hv = subst(hvtp, no, no) -lv = subst(lvtn, no, no) +hvp = subst(hvtp, no, no) +hvn = subst(hvntm, no, no) +lvn = subst(lvtn, no, no) +nvn = subst(nvtn, no, no) +hvx = subst(hvi, no, no) nw = well(nwell, nwell_label, nwell_pin) pw = well(no, pwell_label, pwell_pin) @@ -354,16 +358,24 @@ m4 = route(met4, met4_label, met4_pin) m5 = route(met5, met5_label, met5_pin) -nfet = nmos("svt", "sky130_fd_pr__nfet_01v8", [df, ns, pw], [hv, lv]) -nfet_lvt = nmos("lvt", "sky130_fd_pr__nfet_01v8_lvt", [df, ns, lv, pw]) +nfet = nmos("svt", "sky130_fd_pr__nfet_01v8", [df, ns, pw], [hvp, lvn, hvx]) +nfet_lvt = nmos("lvt", "sky130_fd_pr__nfet_01v8_lvt", [df, ns, lvn, pw], [nvn]) +nfet_pin = nmos("npin", "sky130_fd_pr__nfet_g5v0d10v5", [df, ns, hvn, pw, hvx]) +nfet_nvt = nmos("nvt", "sky130_fd_pr__nfet_05v0_nvt", [df, ns, nvn, lvn, pw]) -pfet = pmos("svt", "sky130_fd_pr__pfet_01v8", [df, ps, nw], [hv, lv]) -pfet_hvt = pmos("hvt", "sky130_fd_pr__pfet_01v8_hvt", [df, ps, hv, nw]) -pfet_lvt = pmos("lvt", "sky130_fd_pr__pfet_01v8_lvt", [df, ps, lv, nw]) +pfet = pmos("svt", "sky130_fd_pr__pfet_01v8", [df, ps, nw], [hvp, lvn, hvx]) +pfet_hvt = pmos("hvt", "sky130_fd_pr__pfet_01v8_hvt", [df, ps, hvp, nw]) +pfet_lvt = pmos("lvt", "sky130_fd_pr__pfet_01v8_lvt", [df, ps, lvn, nw]) +pfet_pin = nmos("ppin", "sky130_fd_pr__pfet_g5v0d10v5", [df, ps, nw, hvx]) via(nfet, m0, licon1) +via(nfet_lvt, m0, licon1) +via(nfet_pin, m0, licon1) +via(nfet_nvt, m0, licon1) via(pfet, m0, licon1) via(pfet_hvt, m0, licon1) +via(pfet_lvt, m0, licon1) +via(pfet_pin, m0, licon1) via(p, m0, licon1) via(m0, m1, mcon) via(m1, m2, via1)