From afee8f964ec7974bcc8a57bc447810c30a9bdc75 Mon Sep 17 00:00:00 2001 From: Dan Petrisko Date: Thu, 27 Jun 2024 23:42:40 -0700 Subject: [PATCH] Updating pearls to sv --- ...lk_gen_pearl_v3.v => bsg_clk_gen_pearl.sv} | 4 +- bsg_clk_gen_pearl/bsg_clk_gen_pearl.v | 82 ------------------- ...iv30.v => bsg_clk_gen_pearl_lfsr_div30.sv} | 0 ...monitor.v => bsg_clk_gen_pearl_monitor.sv} | 2 +- ...v => bsg_clk_gen_pearl_monitor_clk_buf.sv} | 0 ...n_pearl_pkg.v => bsg_clk_gen_pearl_pkg.sv} | 0 .../{bsg_dmc_pearl.v => bsg_dmc_pearl.sv} | 30 +++---- ...g_dmc_pearl_pkg.v => bsg_dmc_pearl_pkg.sv} | 0 8 files changed, 18 insertions(+), 100 deletions(-) rename bsg_clk_gen_pearl/{bsg_clk_gen_pearl_v3.v => bsg_clk_gen_pearl.sv} (97%) delete mode 100755 bsg_clk_gen_pearl/bsg_clk_gen_pearl.v rename bsg_clk_gen_pearl/{bsg_clk_gen_pearl_lfsr_div30.v => bsg_clk_gen_pearl_lfsr_div30.sv} (100%) rename bsg_clk_gen_pearl/{bsg_clk_gen_pearl_monitor.v => bsg_clk_gen_pearl_monitor.sv} (96%) rename bsg_clk_gen_pearl/{bsg_clk_gen_pearl_monitor_clk_buf.v => bsg_clk_gen_pearl_monitor_clk_buf.sv} (100%) rename bsg_clk_gen_pearl/{bsg_clk_gen_pearl_pkg.v => bsg_clk_gen_pearl_pkg.sv} (100%) rename bsg_dmc_pearl/{bsg_dmc_pearl.v => bsg_dmc_pearl.sv} (93%) rename bsg_dmc_pearl/{bsg_dmc_pearl_pkg.v => bsg_dmc_pearl_pkg.sv} (100%) diff --git a/bsg_clk_gen_pearl/bsg_clk_gen_pearl_v3.v b/bsg_clk_gen_pearl/bsg_clk_gen_pearl.sv similarity index 97% rename from bsg_clk_gen_pearl/bsg_clk_gen_pearl_v3.v rename to bsg_clk_gen_pearl/bsg_clk_gen_pearl.sv index 15f98c9..8397b5f 100755 --- a/bsg_clk_gen_pearl/bsg_clk_gen_pearl_v3.v +++ b/bsg_clk_gen_pearl/bsg_clk_gen_pearl.sv @@ -1,6 +1,6 @@ -`include "bsg_defines.v" -`include "bsg_clk_gen.vh" +`include "bsg_defines.sv" +`include "bsg_clk_gen.svh" module bsg_clk_gen_pearl_v3 import bsg_tag_pkg::*; diff --git a/bsg_clk_gen_pearl/bsg_clk_gen_pearl.v b/bsg_clk_gen_pearl/bsg_clk_gen_pearl.v deleted file mode 100755 index b4189cf..0000000 --- a/bsg_clk_gen_pearl/bsg_clk_gen_pearl.v +++ /dev/null @@ -1,82 +0,0 @@ - -`include "bsg_defines.v" -`include "bsg_clk_gen.vh" - -module bsg_clk_gen_pearl - import bsg_tag_pkg::*; - import bsg_clk_gen_pearl_pkg::*; - #(parameter `BSG_INV_PARAM(ds_width_p) - , parameter `BSG_INV_PARAM(num_adgs_p) - , parameter `BSG_INV_PARAM(tag_els_p) - , parameter `BSG_INV_PARAM(tag_lg_width_p) - ) - (input ext_clk_i - , input async_output_disable_i - - , input tag_clk_i - , input tag_data_i - , input [`BSG_SAFE_CLOG2(tag_els_p)-1:0] tag_node_id_offset_i - - , output logic clk_o - // downsampled clock, for viewing off-chip - , output logic clk_monitor_o - ); - - bsg_clk_gen_pearl_tag_lines_s tag_lines_lo; - bsg_tag_master_decentralized - #(.els_p(tag_els_p) - ,.local_els_p(bsg_clk_gen_pearl_tag_local_els_gp) - ,.lg_width_p(tag_lg_width_p) - ) - btm - (.clk_i(tag_clk_i) - ,.data_i(tag_data_i) - ,.node_id_offset_i(tag_node_id_offset_i) - ,.clients_o(tag_lines_lo) - ); - - logic async_reset_lo; - bsg_tag_client_unsync - #(.width_p(1)) - btc_async_reset - (.bsg_tag_i(tag_lines_lo.async_reset) - ,.data_async_r_o(async_reset_lo) - ); - - logic [1:0] clk_select_lo; - bsg_tag_client_unsync - #(.width_p(2)) - btc_clk_select - (.bsg_tag_i(tag_lines_lo.sel) - ,.data_async_r_o(clk_select_lo) - ); - - wire [1:0] clk_select_n = async_output_disable_i ? 2'b11 : clk_select_lo; - - logic clk_lo; - bsg_clk_gen - #(.downsample_width_p(ds_width_p) - ,.num_adgs_p(num_adgs_p) - ,.version_p(2) - ) - clk_gen_inst - (.bsg_osc_tag_i(tag_lines_lo.osc) - ,.bsg_osc_trigger_tag_i(tag_lines_lo.osc_trigger) - ,.bsg_ds_tag_i(tag_lines_lo.ds) - ,.async_osc_reset_i(async_reset_lo) - ,.ext_clk_i(ext_clk_i) - ,.select_i(clk_select_n) - ,.clk_o(clk_lo) - ); - - bsg_clk_gen_pearl_monitor - monitor - (.bsg_tag_i(tag_lines_lo.monitor_reset) - ,.clk_i(clk_lo) - ,.clk_monitor_o(clk_monitor_o) - ); - - assign clk_o = clk_lo; - -endmodule - diff --git a/bsg_clk_gen_pearl/bsg_clk_gen_pearl_lfsr_div30.v b/bsg_clk_gen_pearl/bsg_clk_gen_pearl_lfsr_div30.sv similarity index 100% rename from bsg_clk_gen_pearl/bsg_clk_gen_pearl_lfsr_div30.v rename to bsg_clk_gen_pearl/bsg_clk_gen_pearl_lfsr_div30.sv diff --git a/bsg_clk_gen_pearl/bsg_clk_gen_pearl_monitor.v b/bsg_clk_gen_pearl/bsg_clk_gen_pearl_monitor.sv similarity index 96% rename from bsg_clk_gen_pearl/bsg_clk_gen_pearl_monitor.v rename to bsg_clk_gen_pearl/bsg_clk_gen_pearl_monitor.sv index b1fb361..61e72c5 100755 --- a/bsg_clk_gen_pearl/bsg_clk_gen_pearl_monitor.v +++ b/bsg_clk_gen_pearl/bsg_clk_gen_pearl_monitor.sv @@ -1,5 +1,5 @@ -`include "bsg_tag.vh" +`include "bsg_tag.svh" module bsg_clk_gen_pearl_monitor import bsg_tag_pkg::*; diff --git a/bsg_clk_gen_pearl/bsg_clk_gen_pearl_monitor_clk_buf.v b/bsg_clk_gen_pearl/bsg_clk_gen_pearl_monitor_clk_buf.sv similarity index 100% rename from bsg_clk_gen_pearl/bsg_clk_gen_pearl_monitor_clk_buf.v rename to bsg_clk_gen_pearl/bsg_clk_gen_pearl_monitor_clk_buf.sv diff --git a/bsg_clk_gen_pearl/bsg_clk_gen_pearl_pkg.v b/bsg_clk_gen_pearl/bsg_clk_gen_pearl_pkg.sv similarity index 100% rename from bsg_clk_gen_pearl/bsg_clk_gen_pearl_pkg.v rename to bsg_clk_gen_pearl/bsg_clk_gen_pearl_pkg.sv diff --git a/bsg_dmc_pearl/bsg_dmc_pearl.v b/bsg_dmc_pearl/bsg_dmc_pearl.sv similarity index 93% rename from bsg_dmc_pearl/bsg_dmc_pearl.v rename to bsg_dmc_pearl/bsg_dmc_pearl.sv index 4d2180f..0e4b18d 100644 --- a/bsg_dmc_pearl/bsg_dmc_pearl.v +++ b/bsg_dmc_pearl/bsg_dmc_pearl.sv @@ -1,6 +1,6 @@ -`include "bsg_tag.vh" -`include "bsg_dmc.vh" +`include "bsg_tag.svh" +`include "bsg_dmc.svh" module bsg_dmc_pearl import bsg_tag_pkg::*; @@ -53,14 +53,14 @@ module bsg_dmc_pearl , output logic calib_clk_monitor_o , output logic calib_dqs_monitor_o , output logic calib_dqs_dly_monitor_o - , output logic init_calib_complete_o - , output logic stall_transactions_o - , output logic transaction_in_progress_o - , output logic refresh_in_progress_o - , output logic test_mode_o + , output logic dfi_init_calib_complete_o + , output logic dfi_stall_transactions_o + , output logic ui_transaction_in_progress_o + , output logic dfi_refresh_in_progress_o + , output logic dfi_test_mode_o // Trace-replay interface - , output logic trace_ready_o + , output logic trace_ready_and_o , input [trace_data_width_lp-1:0] trace_data_i , input trace_v_i @@ -140,7 +140,7 @@ module bsg_dmc_pearl ,.data_i(trace_data_i) ,.v_i(trace_v_i) - ,.ready_o(trace_ready_o) + ,.ready_and_o(trace_ready_and_o) ,.data_o(trace_data_o) ,.v_o(trace_v_o) @@ -211,11 +211,11 @@ module bsg_dmc_pearl ,.app_sr_req_i('0) ,.app_sr_active_o() - ,.init_calib_complete_o (init_calib_complete_o) - ,.stall_transactions_o(stall_transactions_o) - ,.transaction_in_progress_o(transaction_in_progress_o) - ,.refresh_in_progress_o(refresh_in_progress_o) - ,.test_mode_o(test_mode_o) + ,.dfi_init_calib_complete_o(dfi_init_calib_complete_o) + ,.ui_transaction_in_progress_o(ui_transaction_in_progress_o) + ,.dfi_stall_transactions_o(dfi_stall_transactions_o) + ,.dfi_refresh_in_progress_o(dfi_refresh_in_progress_o) + ,.dfi_test_mode_o(dfi_test_mode_o) ,.ddr_ck_p_o(ddr_ck_p_o) ,.ddr_ck_n_o(ddr_ck_n_o) @@ -277,7 +277,7 @@ module bsg_dmc_pearl app_rd_data_o = '0; app_rd_data_end_o = '0; - if (test_mode_o) + if (dfi_test_mode_o) begin app_addr = trace_app_addr; app_cmd = trace_app_cmd; diff --git a/bsg_dmc_pearl/bsg_dmc_pearl_pkg.v b/bsg_dmc_pearl/bsg_dmc_pearl_pkg.sv similarity index 100% rename from bsg_dmc_pearl/bsg_dmc_pearl_pkg.v rename to bsg_dmc_pearl/bsg_dmc_pearl_pkg.sv