diff --git a/machines/Makefile b/machines/Makefile index 94f4d5d57..87434fc86 100644 --- a/machines/Makefile +++ b/machines/Makefile @@ -3,6 +3,7 @@ BSG_MANYCORE_DIR := $(shell git rev-parse --show-toplevel) # By convention, basejump_stl is in the same directory as $(BSG_MANYCORE_DIR) BASEJUMP_STL_DIR := $(abspath $(BSG_MANYCORE_DIR)/../basejump_stl) +BSG_MANYCORE_ISA_DIR := $(abspath $(BSG_MANYCORE_DIR)/../bsg_manycore_ISA) ifeq ($(wildcard $(BASEJUMP_STL_DIR)/imports/DRAMSim3/Makefile),) $(error DRAMSim3 has not been submoduled in basejump_stl, see top-level README.md) @@ -20,8 +21,19 @@ DEFAULT_PROFILE_TARGETS = $(foreach machine, $(DEFAULT_MACHINES),$(machine)/$(BS all: $(DEFAULT_TARGETS) $(DEFAULT_DEBUG_TARGETS) $(DEFAULT_PROFILE_TARGETS) # Include source lists -include arch_filelist.mk -include sim_filelist.mk +# We include different source lists for different ISAs +ifeq ($(BSG_MACHINE_ISA),VANILLA) +include $(BSG_MANYCORE_DIR)/machines/arch_filelist.mk +else ifeq ($(BSG_MACHINE_ISA),RISCV) +include $(BSG_MANYCORE_ISA_DIR)/RISCV/arch_filelist.mk +endif + +# We include different sim lists for different ISAs +ifeq ($(BSG_MACHINE_ISA),VANILLA) +include $(BSG_MANYCORE_DIR)/machines/sim_filelist.mk +else ifeq ($(BSG_MACHINE_ISA),RISCV) +include $(BSG_MANYCORE_ISA_DIR)/RISCV/sim_filelist.mk +endif include Makefile.vcs include Makefile.verilator diff --git a/machines/platform.mk b/machines/platform.mk index 3d2065787..8c0f38cad 100644 --- a/machines/platform.mk +++ b/machines/platform.mk @@ -1,5 +1,10 @@ BSG_PLATFORM ?= vcs +# Default Machine ISA is Vanilla. This can be modified to any of the supported ISA in the repository bsg_manycore_ISA +# Note that you would have to sync the above repository as well to use another ISA +# You can change the below to modify the machine built +# BSG_MACHINE_ISA ?= VANILLA +BSG_MACHINE_ISA ?= RISCV ifeq ($(BSG_PLATFORM),vcs) DEFAULT_MACHINES = pod_1x1 pod_1x1_hbm2 pod_4x4 pod_4x4_hbm2 diff --git a/testbenches/common/v/bsg_nonsynth_manycore_vanilla_core_pc_cov.sv b/testbenches/common/v/bsg_nonsynth_manycore_vanilla_core_pc_cov.sv index 54bdde94f..44c8669ac 100644 --- a/testbenches/common/v/bsg_nonsynth_manycore_vanilla_core_pc_cov.sv +++ b/testbenches/common/v/bsg_nonsynth_manycore_vanilla_core_pc_cov.sv @@ -16,7 +16,7 @@ module bsg_nonsynth_manycore_vanilla_core_pc_cov ,input reset_down // Instruction - ,input instruction_s instruction + ,input instruction_s instruction_r // Pipeline registers ,input id_signals_s id_r @@ -47,7 +47,7 @@ module bsg_nonsynth_manycore_vanilla_core_pc_cov ,input coverage_en_i ); - wire take_br = decode.is_branch_op & instruction[0]; + wire take_br = decode.is_branch_op & instruction_r[0]; wire take_jalr = decode.is_jal_op | decode.is_jalr_op; covergroup cg_pc_reset @(negedge clk_i); @@ -131,7 +131,7 @@ module bsg_nonsynth_manycore_vanilla_core_pc_cov covergroup cg_pc_take_jump @(negedge clk_i iff ~reset_down); br_op: coverpoint decode.is_branch_op; - instr0: coverpoint instruction[0]; + instr0: coverpoint instruction_r[0]; jal_op: coverpoint decode.is_jal_op; jalr_op: coverpoint decode.is_jalr_op; diff --git a/testbenches/common/v/nb_waw_detector.sv b/testbenches/common/v/nb_waw_detector.sv index 9f1c6ea67..bcf67c09d 100644 --- a/testbenches/common/v/nb_waw_detector.sv +++ b/testbenches/common/v/nb_waw_detector.sv @@ -4,8 +4,8 @@ module nb_waw_detector , parameter x_cord_width_p="inv" , parameter y_cord_width_p="inv" - , parameter reg_els_lp=RV32_reg_els_gp - , parameter instr_width_lp=RV32_instr_width_gp + , parameter reg_els_lp=reg_els_gp + , parameter instr_width_lp=instr_width_gp ) ( input clk_i @@ -18,7 +18,7 @@ module nb_waw_detector , input int_remote_load_resp_v_i , input int_remote_load_resp_force_i - , input [RV32_reg_addr_width_gp-1:0] int_remote_load_resp_rd_i + , input [reg_addr_width_gp-1:0] int_remote_load_resp_rd_i , input mem_signals_s mem_r , input wb_signals_s wb_r diff --git a/testbenches/common/v/remote_load_trace.sv b/testbenches/common/v/remote_load_trace.sv index 7ec9153cc..d7afd9cd4 100644 --- a/testbenches/common/v/remote_load_trace.sv +++ b/testbenches/common/v/remote_load_trace.sv @@ -55,7 +55,7 @@ module remote_load_trace // Load response coming back , input returned_v_i - , input [RV32_reg_addr_width_gp-1:0] returned_reg_id_i + , input [reg_addr_width_gp-1:0] returned_reg_id_i , input bsg_manycore_return_packet_type_e returned_pkt_type_i , input returned_yumi_o @@ -95,8 +95,8 @@ module remote_load_trace } remote_load_status_s; - remote_load_status_s [RV32_reg_els_gp-1:0] int_rl_status_r; - remote_load_status_s [RV32_reg_els_gp-1:0] float_rl_status_r; + remote_load_status_s [reg_els_gp-1:0] int_rl_status_r; + remote_load_status_s [reg_els_gp-1:0] float_rl_status_r; remote_load_status_s icache_status_r; wire int_rl_v = out_v_o & ( @@ -112,11 +112,11 @@ module remote_load_trace wire icache_rl_v = out_v_o & ( (out_packet.op_v2 == e_remote_load) & load_info.icache_fetch); - logic [RV32_reg_els_gp-1:0] int_rl_we; - logic [RV32_reg_els_gp-1:0] float_rl_we; + logic [reg_els_gp-1:0] int_rl_we; + logic [reg_els_gp-1:0] float_rl_we; bsg_decode_with_v #( - .num_out_p(RV32_reg_els_gp) + .num_out_p(reg_els_gp) ) dv0 ( .i(out_packet.reg_id) ,.v_i(int_rl_v) @@ -124,7 +124,7 @@ module remote_load_trace ); bsg_decode_with_v #( - .num_out_p(RV32_reg_els_gp) + .num_out_p(reg_els_gp) ) dv1 ( .i(out_packet.reg_id) ,.v_i(float_rl_v) @@ -148,7 +148,7 @@ module remote_load_trace end else begin - for (integer i = 0 ; i < RV32_reg_els_gp; i++) begin + for (integer i = 0 ; i < reg_els_gp; i++) begin if (int_rl_we[i]) int_rl_status_r[i] <= next_rl; if (float_rl_we[i]) diff --git a/testbenches/common/v/vanilla_core_pc_histogram.sv b/testbenches/common/v/vanilla_core_pc_histogram.sv index 29a421fb0..4b4e7df6b 100644 --- a/testbenches/common/v/vanilla_core_pc_histogram.sv +++ b/testbenches/common/v/vanilla_core_pc_histogram.sv @@ -15,8 +15,8 @@ module vanilla_core_pc_histogram ,parameter `BSG_INV_PARAM(origin_y_cord_p) ,parameter icache_addr_width_lp=`BSG_SAFE_CLOG2(icache_entries_p) ,parameter pc_width_lp=(icache_tag_width_p+icache_addr_width_lp) - ,parameter reg_els_lp=RV32_reg_els_gp - ,parameter reg_addr_width_lp=RV32_reg_addr_width_gp + ,parameter reg_els_lp=reg_els_gp + ,parameter reg_addr_width_lp=reg_addr_width_gp ) ( input clk_i @@ -28,7 +28,7 @@ module vanilla_core_pc_histogram , input [data_width_p-1:0] if_pc , input [data_width_p-1:0] id_pc , input [data_width_p-1:0] exe_pc - , input instruction_s instruction + , input instruction_s instruction_r , input decode_s decode , input flush @@ -61,7 +61,7 @@ module vanilla_core_pc_histogram , input jalr_mispredict , input [data_width_p-1:0] rs1_val_to_exe - , input [RV32_Iimm_width_gp-1:0] mem_addr_op2 + , input [Iimm_width_gp-1:0] mem_addr_op2 , input int_sb_clear , input float_sb_clear diff --git a/testbenches/common/v/vanilla_core_profiler.sv b/testbenches/common/v/vanilla_core_profiler.sv index 40f1479da..17abbf422 100644 --- a/testbenches/common/v/vanilla_core_profiler.sv +++ b/testbenches/common/v/vanilla_core_profiler.sv @@ -1,5 +1,5 @@ /** - * vanilla_core_profiler.v + * vanilla_core_profiler.sv * */ @@ -32,8 +32,8 @@ module vanilla_core_profiler , parameter icache_addr_width_lp=`BSG_SAFE_CLOG2(icache_entries_p) , parameter pc_width_lp=(icache_tag_width_p+icache_addr_width_lp) - , parameter reg_els_lp = RV32_reg_els_gp - , parameter reg_addr_width_lp = RV32_reg_addr_width_gp + , parameter reg_els_lp = reg_els_gp + , parameter reg_addr_width_lp = reg_addr_width_gp , parameter period_p = 250 , parameter enable_periodic_p=0 @@ -82,7 +82,7 @@ module vanilla_core_profiler , input remote_req_s remote_req_o , input [data_width_p-1:0] rs1_val_to_exe - , input [RV32_Iimm_width_gp-1:0] mem_addr_op2 + , input [Iimm_width_gp-1:0] mem_addr_op2 , input int_sb_clear , input float_sb_clear @@ -94,7 +94,7 @@ module vanilla_core_profiler , input fp_exe_ctrl_signals_s fp_exe_ctrl_r // IF stage - , input instruction_s instruction + , input instruction_s instruction_r , input decode_s decode , input [x_cord_width_p-1:0] global_x_i @@ -207,12 +207,12 @@ module vanilla_core_profiler wire amoadd_inc = exe_r.decode.is_amo_op & (exe_r.decode.amo_type == e_vanilla_amoadd); // branch & jump - wire beq_inc = exe_r.decode.is_branch_op & (exe_r.instruction ==? `RV32_BEQ); - wire bne_inc = exe_r.decode.is_branch_op & (exe_r.instruction ==? `RV32_BNE); - wire blt_inc = exe_r.decode.is_branch_op & (exe_r.instruction ==? `RV32_BLT); - wire bge_inc = exe_r.decode.is_branch_op & (exe_r.instruction ==? `RV32_BGE); - wire bltu_inc = exe_r.decode.is_branch_op & (exe_r.instruction ==? `RV32_BLTU); - wire bgeu_inc = exe_r.decode.is_branch_op & (exe_r.instruction ==? `RV32_BGEU); + wire beq_inc = exe_r.decode.is_branch_op & (exe_r.instruction ==? `VANILLA_BEQ); + wire bne_inc = exe_r.decode.is_branch_op & (exe_r.instruction ==? `VANILLA_BNE); + wire blt_inc = exe_r.decode.is_branch_op & (exe_r.instruction ==? `VANILLA_BLT); + wire bge_inc = exe_r.decode.is_branch_op & (exe_r.instruction ==? `VANILLA_BGE); + wire bltu_inc = exe_r.decode.is_branch_op & (exe_r.instruction ==? `VANILLA_BLTU); + wire bgeu_inc = exe_r.decode.is_branch_op & (exe_r.instruction ==? `VANILLA_BGEU); wire jal_inc = exe_r.decode.is_jal_op; wire jalr_inc = exe_r.decode.is_jalr_op; @@ -227,29 +227,29 @@ module vanilla_core_profiler wire jalr_miss_inc = jalr_inc & jalr_mispredict; // ALU - wire sll_inc = (exe_r.instruction ==? `RV32_SLL); - wire slli_inc = (exe_r.instruction ==? `RV32_SLLI); - wire srl_inc = (exe_r.instruction ==? `RV32_SRL); - wire srli_inc = (exe_r.instruction ==? `RV32_SRLI); - wire sra_inc = (exe_r.instruction ==? `RV32_SRA); - wire srai_inc = (exe_r.instruction ==? `RV32_SRAI); - - wire add_inc = (exe_r.instruction ==? `RV32_ADD); - wire addi_inc = (exe_r.instruction ==? `RV32_ADDI); - wire sub_inc = (exe_r.instruction ==? `RV32_SUB); - wire lui_inc = (exe_r.instruction ==? `RV32_LUI); - wire auipc_inc = (exe_r.instruction ==? `RV32_AUIPC); - wire xor_inc = (exe_r.instruction ==? `RV32_XOR); - wire xori_inc = (exe_r.instruction ==? `RV32_XORI); - wire or_inc = (exe_r.instruction ==? `RV32_OR); - wire ori_inc = (exe_r.instruction ==? `RV32_ORI); - wire and_inc = (exe_r.instruction ==? `RV32_AND); - wire andi_inc = (exe_r.instruction ==? `RV32_ANDI); - - wire slt_inc = (exe_r.instruction ==? `RV32_SLT); - wire slti_inc = (exe_r.instruction ==? `RV32_SLTI); - wire sltu_inc = (exe_r.instruction ==? `RV32_SLTU); - wire sltiu_inc = (exe_r.instruction ==? `RV32_SLTIU); + wire sll_inc = (exe_r.instruction ==? `VANILLA_SLL); + wire slli_inc = (exe_r.instruction ==? `VANILLA_SLLI); + wire srl_inc = (exe_r.instruction ==? `VANILLA_SRL); + wire srli_inc = (exe_r.instruction ==? `VANILLA_SRLI); + wire sra_inc = (exe_r.instruction ==? `VANILLA_SRA); + wire srai_inc = (exe_r.instruction ==? `VANILLA_SRAI); + + wire add_inc = (exe_r.instruction ==? `VANILLA_ADD); + wire addi_inc = (exe_r.instruction ==? `VANILLA_ADDI); + wire sub_inc = (exe_r.instruction ==? `VANILLA_SUB); + wire lui_inc = (exe_r.instruction ==? `VANILLA_LUI); + wire auipc_inc = (exe_r.instruction ==? `VANILLA_AUIPC); + wire xor_inc = (exe_r.instruction ==? `VANILLA_XOR); + wire xori_inc = (exe_r.instruction ==? `VANILLA_XORI); + wire or_inc = (exe_r.instruction ==? `VANILLA_OR); + wire ori_inc = (exe_r.instruction ==? `VANILLA_ORI); + wire and_inc = (exe_r.instruction ==? `VANILLA_AND); + wire andi_inc = (exe_r.instruction ==? `VANILLA_ANDI); + + wire slt_inc = (exe_r.instruction ==? `VANILLA_SLT); + wire slti_inc = (exe_r.instruction ==? `VANILLA_SLTI); + wire sltu_inc = (exe_r.instruction ==? `VANILLA_SLTU); + wire sltiu_inc = (exe_r.instruction ==? `VANILLA_SLTIU); // IDIV wire div_inc = exe_r.decode.is_idiv_op & (exe_r.decode.idiv_op == eDIV); @@ -264,16 +264,16 @@ module vanilla_core_profiler wire fence_inc = exe_r.decode.is_fence_op; // CSR - wire csrrw_inc = (exe_r.instruction ==? `RV32_CSRRW); - wire csrrs_inc = (exe_r.instruction ==? `RV32_CSRRS); - wire csrrc_inc = (exe_r.instruction ==? `RV32_CSRRC); - wire csrrwi_inc = (exe_r.instruction ==? `RV32_CSRRWI); - wire csrrsi_inc = (exe_r.instruction ==? `RV32_CSRRSI); - wire csrrci_inc = (exe_r.instruction ==? `RV32_CSRRCI); + wire csrrw_inc = (exe_r.instruction ==? `VANILLA_CSRRW); + wire csrrs_inc = (exe_r.instruction ==? `VANILLA_CSRRS); + wire csrrc_inc = (exe_r.instruction ==? `VANILLA_CSRRC); + wire csrrwi_inc = (exe_r.instruction ==? `VANILLA_CSRRWI); + wire csrrsi_inc = (exe_r.instruction ==? `VANILLA_CSRRSI); + wire csrrci_inc = (exe_r.instruction ==? `VANILLA_CSRRCI); // Barrier Instruction - wire barsend_inc = (exe_r.instruction ==? `RV32_FENCE_OP) & (exe_r.instruction[31:28] == `RV32_BARSEND_FM); - wire barrecv_inc = (exe_r.instruction ==? `RV32_FENCE_OP) & (exe_r.instruction[31:28] == `RV32_BARRECV_FM); + wire barsend_inc = (exe_r.instruction ==? `VANILLA_FENCE_OP) & (exe_r.instruction[31:28] == `VANILLA_BARSEND_FM); + wire barrecv_inc = (exe_r.instruction ==? `VANILLA_FENCE_OP) & (exe_r.instruction[31:28] == `VANILLA_BARRECV_FM); // Track bubbles in the EXE stage // and their associated PC diff --git a/testbenches/common/v/vanilla_core_trace.sv b/testbenches/common/v/vanilla_core_trace.sv index c0a901b94..7e8667364 100644 --- a/testbenches/common/v/vanilla_core_trace.sv +++ b/testbenches/common/v/vanilla_core_trace.sv @@ -13,7 +13,7 @@ module vanilla_core_trace , localparam icache_addr_width_lp=`BSG_SAFE_CLOG2(icache_entries_p) , localparam dmem_addr_width_lp=`BSG_SAFE_CLOG2(dmem_size_p) , localparam pc_width_lp=(icache_tag_width_p+icache_addr_width_lp) - , localparam reg_addr_width_lp=RV32_reg_addr_width_gp + , localparam reg_addr_width_lp=reg_addr_width_gp ) ( @@ -56,52 +56,52 @@ module vanilla_core_trace typedef struct packed { - logic [RV32_reg_data_width_gp-1:0] pc; - logic [RV32_instr_width_gp-1:0] instr; + logic [reg_data_width_gp-1:0] pc; + logic [instr_width_gp-1:0] instr; logic branch_or_jump; - logic [RV32_instr_width_gp-1:0] btarget; + logic [instr_width_gp-1:0] btarget; logic is_local_load; logic is_local_store; logic [dmem_addr_width_lp-1:0] local_dmem_addr; - logic [RV32_reg_data_width_gp-1:0] local_store_data; + logic [reg_data_width_gp-1:0] local_store_data; logic is_remote_load; logic is_remote_store; - logic [RV32_reg_data_width_gp-1:0] remote_addr; - logic [RV32_reg_data_width_gp-1:0] remote_store_data; + logic [reg_data_width_gp-1:0] remote_addr; + logic [reg_data_width_gp-1:0] remote_store_data; } exe_debug_s; typedef struct packed { - logic [RV32_reg_data_width_gp-1:0] pc; - logic [RV32_instr_width_gp-1:0] instr; + logic [reg_data_width_gp-1:0] pc; + logic [instr_width_gp-1:0] instr; logic branch_or_jump; - logic [RV32_instr_width_gp-1:0] btarget; + logic [instr_width_gp-1:0] btarget; logic is_local_load; logic is_local_store; logic [dmem_addr_width_lp-1:0] local_dmem_addr; - logic [RV32_reg_data_width_gp-1:0] local_store_data; + logic [reg_data_width_gp-1:0] local_store_data; logic is_remote_load; logic is_remote_store; - logic [RV32_reg_data_width_gp-1:0] remote_addr; - logic [RV32_reg_data_width_gp-1:0] remote_store_data; + logic [reg_data_width_gp-1:0] remote_addr; + logic [reg_data_width_gp-1:0] remote_store_data; } mem_debug_s; typedef struct packed { - logic [RV32_reg_data_width_gp-1:0] pc; - logic [RV32_instr_width_gp-1:0] instr; + logic [reg_data_width_gp-1:0] pc; + logic [instr_width_gp-1:0] instr; logic branch_or_jump; - logic [RV32_instr_width_gp-1:0] btarget; + logic [instr_width_gp-1:0] btarget; logic is_local_load; logic is_local_store; logic [dmem_addr_width_lp-1:0] local_dmem_addr; - logic [RV32_reg_data_width_gp-1:0] local_load_data; - logic [RV32_reg_data_width_gp-1:0] local_store_data; + logic [reg_data_width_gp-1:0] local_load_data; + logic [reg_data_width_gp-1:0] local_store_data; logic is_remote_load; logic is_remote_store; - logic [RV32_reg_data_width_gp-1:0] remote_addr; - logic [RV32_reg_data_width_gp-1:0] remote_store_data; + logic [reg_data_width_gp-1:0] remote_addr; + logic [reg_data_width_gp-1:0] remote_store_data; } wb_debug_s; exe_debug_s exe_debug; diff --git a/testbenches/common/v/vanilla_exe_bubble_classifier.sv b/testbenches/common/v/vanilla_exe_bubble_classifier.sv index 6a16186dc..0b0ff96dc 100644 --- a/testbenches/common/v/vanilla_exe_bubble_classifier.sv +++ b/testbenches/common/v/vanilla_exe_bubble_classifier.sv @@ -45,18 +45,18 @@ module vanilla_exe_bubble_classifier ,input jalr_mispredict ,input [data_width_p-1:0] rs1_val_to_exe - ,input [RV32_Iimm_width_gp-1:0] mem_addr_op2 + ,input [Iimm_width_gp-1:0] mem_addr_op2 ,input int_sb_clear ,input float_sb_clear - ,input [RV32_reg_addr_width_gp-1:0] int_sb_clear_id - ,input [RV32_reg_addr_width_gp-1:0] float_sb_clear_id + ,input [reg_addr_width_gp-1:0] int_sb_clear_id + ,input [reg_addr_width_gp-1:0] float_sb_clear_id ,input id_signals_s id_r ,input exe_signals_s exe_r ,input fp_exe_ctrl_signals_s fp_exe_ctrl_r - ,input instruction_s instruction + ,input instruction_s instruction_r ,input decode_s decode ,output [pc_width_p-1:0] exe_bubble_pc_o @@ -122,8 +122,8 @@ module vanilla_exe_bubble_classifier exe_bubble_type_e exe_bubble_r; logic [data_width_p-1:0] exe_bubble_pc_r; - vanilla_isb_info_s [RV32_reg_els_gp-1:0] int_sb; - vanilla_fsb_info_s [RV32_reg_els_gp-1:0] float_sb; + vanilla_isb_info_s [reg_els_gp-1:0] int_sb; + vanilla_fsb_info_s [reg_els_gp-1:0] float_sb; logic is_id_seq_lw, is_id_seq_flw; vanilla_scoreboard_tracker diff --git a/testbenches/common/v/vanilla_scoreboard_tracker.sv b/testbenches/common/v/vanilla_scoreboard_tracker.sv index b6c1d929e..6b7a8060c 100644 --- a/testbenches/common/v/vanilla_scoreboard_tracker.sv +++ b/testbenches/common/v/vanilla_scoreboard_tracker.sv @@ -5,7 +5,7 @@ module vanilla_scoreboard_tracker import bsg_vanilla_pkg::*; import vanilla_scoreboard_tracker_pkg::*; #(parameter `BSG_INV_PARAM(data_width_p) - ,parameter reg_addr_width_lp=RV32_reg_addr_width_gp + ,parameter reg_addr_width_lp=reg_addr_width_gp ) (input clk_i ,input reset_i @@ -15,7 +15,7 @@ module vanilla_scoreboard_tracker ,input stall_id ,input [data_width_p-1:0] rs1_val_to_exe - ,input [RV32_Iimm_width_gp-1:0] mem_addr_op2 + ,input [Iimm_width_gp-1:0] mem_addr_op2 ,input int_sb_clear ,input float_sb_clear @@ -26,21 +26,21 @@ module vanilla_scoreboard_tracker ,input exe_signals_s exe_r ,input fp_exe_ctrl_signals_s fp_exe_ctrl_r - ,input instruction_s instruction + ,input instruction_s instruction_r ,input decode_s decode - ,output vanilla_isb_info_s [RV32_reg_els_gp-1:0] int_sb_o - ,output vanilla_fsb_info_s [RV32_reg_els_gp-1:0] float_sb_o + ,output vanilla_isb_info_s [reg_els_gp-1:0] int_sb_o + ,output vanilla_fsb_info_s [reg_els_gp-1:0] float_sb_o // is the load in ID sequential load? ,output logic is_id_seq_lw_o ,output logic is_id_seq_flw_o ); - wire [reg_addr_width_lp-1:0] if_rs1 = instruction.rs1; + wire [reg_addr_width_lp-1:0] if_rs1 = instruction_r.rs1; wire [reg_addr_width_lp-1:0] id_rs1 = id_r.instruction.rs1; wire [reg_addr_width_lp-1:0] id_rd = id_r.instruction.rd; wire [9:0] id_imm_plus4 = 1'b1 + mem_addr_op2[11:2]; - wire [11:0] if_load_imm = `RV32_Iimm_12extract(instruction); + wire [11:0] if_load_imm = `VANILLA_Iimm_12extract(instruction_r); wire is_seq_lw = id_r.decode.is_load_op & decode.is_load_op & id_r.decode.write_rd & decode.write_rd @@ -71,8 +71,8 @@ module vanilla_scoreboard_tracker // remote/local scoreboard tracking - vanilla_isb_info_s [RV32_reg_els_gp-1:0] int_sb_r; - vanilla_fsb_info_s [RV32_reg_els_gp-1:0] float_sb_r; + vanilla_isb_info_s [reg_els_gp-1:0] int_sb_r; + vanilla_fsb_info_s [reg_els_gp-1:0] float_sb_r; always_ff @ (posedge clk_i) begin if (reset_i) begin @@ -82,7 +82,7 @@ module vanilla_scoreboard_tracker else begin // int sb - for (integer i = 0; i < RV32_reg_els_gp; i++) begin + for (integer i = 0; i < reg_els_gp; i++) begin // idiv if (~stall_id & ~stall_all & ~flush & id_r.decode.is_idiv_op & (id_rd == i)) begin int_sb_r[i].idiv <= 1'b1; @@ -128,7 +128,7 @@ module vanilla_scoreboard_tracker end // float sb - for (integer i = 0; i < RV32_reg_els_gp; i++) begin + for (integer i = 0; i < reg_els_gp; i++) begin // fdiv, fsqrt if (~stall_id & ~stall_all & ~flush & (id_r.decode.is_fp_op & (id_r.fp_decode.is_fdiv_op | id_r.fp_decode.is_fsqrt_op)) & (id_rd == i)) begin float_sb_r[i].fdiv_fsqrt <= 1'b1; diff --git a/testbenches/hardfloat/fpu_fdiv_fsqrt/test_fpu_fdiv_fsqrt.sv b/testbenches/hardfloat/fpu_fdiv_fsqrt/test_fpu_fdiv_fsqrt.sv index 366f27145..972a035a4 100644 --- a/testbenches/hardfloat/fpu_fdiv_fsqrt/test_fpu_fdiv_fsqrt.sv +++ b/testbenches/hardfloat/fpu_fdiv_fsqrt/test_fpu_fdiv_fsqrt.sv @@ -4,7 +4,7 @@ module test_fpu_fdiv_fsqrt import bsg_vanilla_pkg::*; - #(parameter expWidth = 8, parameter sigWidth = 24, parameter bits_per_iter_p = 1, parameter reg_addr_width_p = RV32_reg_addr_width_gp); + #(parameter expWidth = 8, parameter sigWidth = 24, parameter bits_per_iter_p = 1, parameter reg_addr_width_p = reg_addr_width_gp); parameter maxNumErrors = 20; diff --git a/v/vanilla_bean/alu.sv b/v/vanilla_bean/alu.sv index 80d35eead..9a1871070 100644 --- a/v/vanilla_bean/alu.sv +++ b/v/vanilla_bean/alu.sv @@ -1,14 +1,14 @@ -`include "bsg_vanilla_defines.svh" +`include "bsg_manycore_instruction_defines.svh" module alu import bsg_vanilla_pkg::*; #(`BSG_INV_PARAM(pc_width_p )) - ( input [RV32_reg_data_width_gp-1:0] rs1_i - ,input [RV32_reg_data_width_gp-1:0] rs2_i - ,input [RV32_reg_data_width_gp-1:0] pc_plus4_i + ( input [reg_data_width_gp-1:0] rs1_i + ,input [reg_data_width_gp-1:0] rs2_i + ,input [reg_data_width_gp-1:0] pc_plus4_i ,input instruction_s op_i - ,output logic [RV32_reg_data_width_gp-1:0] result_o + ,output logic [reg_data_width_gp-1:0] result_o ,output logic [pc_width_p-1:0] jalr_addr_o ,output logic jump_now_o ); @@ -23,10 +23,10 @@ logic [32:0] shr_out; logic [31:0] shl_out, xor_out, and_out, or_out; ///////////////////////////////////////////////////////// -assign is_imm_op = (op_i.op ==? `RV32_OP_IMM) | (op_i.op ==? `RV32_JALR_OP); +assign is_imm_op = (op_i.op ==? `MANYCORE_OP_IMM) | (op_i.op ==? `MANYCORE_JALR_OP); ///////////////////////////////////////////////////////// -assign op2 = is_imm_op ? `RV32_signext_Iimm(op_i) : rs2_i; +assign op2 = is_imm_op ? `MANYCORE_signext_Iimm(op_i) : rs2_i; /////////////////////////////////////////////////////////// @@ -49,61 +49,61 @@ always_comb sign_ex_or_zero = 1'b0; unique casez (op_i) - `RV32_LUI: - result_o = `RV32_signext_Uimm(op_i); + `MANYCORE_LUI: + result_o = `MANYCORE_signext_Uimm(op_i); - `RV32_AUIPC: - result_o = `RV32_signext_Uimm(op_i) + pc_plus4_i - 3'b100; + `MANYCORE_AUIPC: + result_o = `MANYCORE_signext_Uimm(op_i) + pc_plus4_i - 3'b100; - `RV32_ADDI, `RV32_ADD: + `MANYCORE_ADDI, `MANYCORE_ADD: begin result_o = sum[31:0]; sub_not_add = 1'b0; end - `RV32_SLTI, `RV32_SLT: + `MANYCORE_SLTI, `MANYCORE_SLT: begin sub_not_add = 1'b1; result_o = {{31{1'b0}},sum[32]}; end - `RV32_SLTIU, `RV32_SLTU: + `MANYCORE_SLTIU, `MANYCORE_SLTU: begin sub_not_add = 1'b1; result_o = {{31{1'b0}},~carry}; end - `RV32_XORI, `RV32_XOR: + `MANYCORE_XORI, `MANYCORE_XOR: result_o = xor_out; - `RV32_ORI, `RV32_OR: + `MANYCORE_ORI, `MANYCORE_OR: result_o = or_out; - `RV32_ANDI, `RV32_AND: + `MANYCORE_ANDI, `MANYCORE_AND: result_o = and_out; - `RV32_SLLI, `RV32_SLL: + `MANYCORE_SLLI, `MANYCORE_SLL: result_o = shl_out; - `RV32_SRLI, `RV32_SRL: + `MANYCORE_SRLI, `MANYCORE_SRL: begin result_o = shr_out[31:0]; sign_ex_or_zero = 1'b0; end - `RV32_SRAI, `RV32_SRA: + `MANYCORE_SRAI, `MANYCORE_SRA: begin result_o = shr_out[31:0]; sign_ex_or_zero = rs1_i[31]; end - `RV32_SUB: + `MANYCORE_SUB: begin result_o = sum[31:0]; sub_not_add = 1'b1; end - `RV32_JALR: + `MANYCORE_JALR: begin sub_not_add = 1'b0; // jalr_addr_o = sum[31:0] & 32'hfffe; @@ -111,7 +111,7 @@ always_comb result_o = pc_plus4_i; end - `RV32_JAL: + `MANYCORE_JAL: begin result_o =pc_plus4_i; end @@ -129,12 +129,12 @@ wire rs1_lt_rs2_signed = ( $signed(rs1_i) < $signed( rs2_i ) ); always_comb begin unique casez(op_i ) - `RV32_BEQ: jump_now_o = rs1_eq_rs2; - `RV32_BNE: jump_now_o = ~rs1_eq_rs2; - `RV32_BLT: jump_now_o = rs1_lt_rs2_signed; - `RV32_BGE: jump_now_o = ~rs1_lt_rs2_signed; - `RV32_BLTU: jump_now_o = rs1_lt_rs2_unsigned; - `RV32_BGEU: jump_now_o = ~rs1_lt_rs2_unsigned; + `MANYCORE_BEQ: jump_now_o = rs1_eq_rs2; + `MANYCORE_BNE: jump_now_o = ~rs1_eq_rs2; + `MANYCORE_BLT: jump_now_o = rs1_lt_rs2_signed; + `MANYCORE_BGE: jump_now_o = ~rs1_lt_rs2_signed; + `MANYCORE_BLTU: jump_now_o = rs1_lt_rs2_unsigned; + `MANYCORE_BGEU: jump_now_o = ~rs1_lt_rs2_unsigned; default: jump_now_o = 1'b0; endcase end diff --git a/v/vanilla_bean/bsg_manycore_instruction_defines.svh b/v/vanilla_bean/bsg_manycore_instruction_defines.svh new file mode 100644 index 000000000..2b1717006 --- /dev/null +++ b/v/vanilla_bean/bsg_manycore_instruction_defines.svh @@ -0,0 +1,159 @@ +`ifndef BSG_MANYCORE_INSTRUCTION_DEFINES_SVH +`define BSG_MANYCORE_INSTRUCTION_DEFINES_SVH + +/** + * bsg_manycore_instructions_defines.svh + * + * This file defines the macros + * used throughout the vanilla core. (Outside the decoder) + * + */ + +`include "bsg_defines.sv" + +`define declare_icache_format_s(tag_width_mp, block_size_in_words_mp) \ + typedef struct packed { \ + logic [block_size_in_words_mp-1:0] lower_cout; \ + logic [block_size_in_words_mp-1:0] lower_sign; \ + logic [tag_width_mp-1:0] tag; \ + instruction_s [block_size_in_words_mp-1:0] instr; \ + } icache_format_s + +`define icache_format_width(tag_width_mp, block_size_in_words_mp) \ + ((2*block_size_in_words_mp)+tag_width_mp+(block_size_in_words_mp*$bits(instruction_s))) + +// FPU recoded Constants +`define FPU_RECODED_ONE 33'h080000000 +`define FPU_RECODED_ZERO 33'h0 +`define FPU_RECODED_CANONICAL_NAN 33'h0e0400000 + +`define REMOTE_INTERRUPT_JUMP_ADDR 0 // remote interrupt jump addr (word addr) +`define TRACE_INTERRUPT_JUMP_ADDR 1 // trace interrupt jump addr (word addr) + +// 32M Instruction Encodings +`define MD_MUL_FUN3 3'b000 +`define MD_MULH_FUN3 3'b001 +`define MD_MULHSU_FUN3 3'b010 +`define MD_MULHU_FUN3 3'b011 +`define MD_DIV_FUN3 3'b100 +`define MD_DIVU_FUN3 3'b101 +`define MD_REM_FUN3 3'b110 +`define MD_REMU_FUN3 3'b111 + +// Generic Many Core Opcodes +`define MANYCORE_LOAD 7'b1111100 +`define MANYCORE_STORE 7'b1011100 + +`define MANYCORE_BRANCH 7'b001110? + +`define MANYCORE_JALR_OP 7'b0011000 +`define MANYCORE_MISC_MEM 7'b1110000 +`define MANYCORE_AMO_OP 7'b1010000 +`define MANYCORE_JAL_OP 7'b0010000 +`define MANYCORE_OP_IMM 7'b1101100 +`define MANYCORE_OP 7'b1001100 +`define MANYCORE_SYSTEM 7'b0001100 +`define MANYCORE_AUIPC_OP 7'b1101000 +`define MANYCORE_LUI_OP 7'b1001000 + +// Some useful ManyCore instruction macros +`define MANYCORE_Rtype(op, funct3, funct7) {``funct7``, {5{1'b?}}, {5{1'b?}},``funct3``, {5{1'b?}},``op``} +`define MANYCORE_Itype(op, funct3) {{12{1'b?}},{5{1'b?}},``funct3``,{5{1'b?}},``op``} +`define MANYCORE_Stype(op, funct3) {{7{1'b?}},{5{1'b?}},{5{1'b?}},``funct3``,{5{1'b?}},``op``} +`define MANYCORE_Utype(op) {{20{1'b?}},{5{1'b?}},``op``} + +// ManyCore Immediate sign extension macros +`define MANYCORE_signext_Iimm(instr) {{21{``instr``[31]}},``instr``[30:20]} +`define MANYCORE_signext_Simm(instr) {{21{``instr``[31]}},``instr[30:25],``instr``[11:7]} +`define MANYCORE_signext_Bimm(instr) {{20{``instr``[31]}},``instr``[7],``instr``[30:25],``instr``[11:8], {1'b0}} +`define MANYCORE_signext_Uimm(instr) {``instr``[31:12], {12{1'b0}}} +`define MANYCORE_signext_Jimm(instr) {{12{``instr``[31]}},``instr``[19:12],``instr``[20],``instr``[30:21], {1'b0}} + +`define MANYCORE_Bimm_12inject1(instr,value) {``value``[12], ``value``[10:5], ``instr``[24:12],\ + ``value``[4:1],``value``[11],``instr``[0],``instr``[1],``instr``[2],``instr``[3],\ + ``instr``[4],``instr``[5],``instr``[6]} +`define MANYCORE_Jimm_20inject1(instr,value) {``value``[20], ``value``[10:1], ``value``[11],``value``[19:12], ``instr``[11:7],\ + ``instr``[0],``instr``[1],``instr``[2],``instr``[3],``instr``[4],``instr``[5],``instr``[6]} + +// Both JAL and BRANCH use 2-byte address, we need to pad 1'b0 at MSB to get +// the real byte address +`define MANYCORE_Bimm_13extract(instr) {``instr``[31], ``instr``[7], ``instr``[30:25], ``instr``[11:8], 1'b0} +`define MANYCORE_Jimm_21extract(instr) {``instr``[31], ``instr``[19:12],``instr``[20],``instr``[30:21], 1'b0} + +`define MANYCORE_Iimm_12extract(instr) {``instr``[31:20]} +`define MANYCORE_Simm_12extract(instr) {``instr[31:25],``instr``[11:7]} + +// Manycore Instruction encodings +// We have to delete the white space in macro definition, +// otherwise Design Compiler would issue warings. +`define MANYCORE_LUI `MANYCORE_Utype(`MANYCORE_LUI_OP) +`define MANYCORE_AUIPC `MANYCORE_Utype(`MANYCORE_AUIPC_OP) +`define MANYCORE_JAL `MANYCORE_Utype(`MANYCORE_JAL_OP) +`define MANYCORE_JALR `MANYCORE_Itype(`MANYCORE_JALR_OP, 3'b000) +`define MANYCORE_BEQ `MANYCORE_Stype(`MANYCORE_BRANCH, 3'b000) +`define MANYCORE_BNE `MANYCORE_Stype(`MANYCORE_BRANCH, 3'b001) +`define MANYCORE_BLT `MANYCORE_Stype(`MANYCORE_BRANCH, 3'b100) +`define MANYCORE_BGE `MANYCORE_Stype(`MANYCORE_BRANCH, 3'b101) +`define MANYCORE_BLTU `MANYCORE_Stype(`MANYCORE_BRANCH, 3'b110) +`define MANYCORE_BGEU `MANYCORE_Stype(`MANYCORE_BRANCH, 3'b111) +`define MANYCORE_LB `MANYCORE_Itype(`MANYCORE_LOAD, 3'b000) +`define MANYCORE_LH `MANYCORE_Itype(`MANYCORE_LOAD, 3'b001) +`define MANYCORE_LW `MANYCORE_Itype(`MANYCORE_LOAD, 3'b010) +`define MANYCORE_LBU `MANYCORE_Itype(`MANYCORE_LOAD, 3'b100) +`define MANYCORE_LHU `MANYCORE_Itype(`MANYCORE_LOAD, 3'b101) +`define MANYCORE_SB `MANYCORE_Stype(`MANYCORE_STORE, 3'b000) +`define MANYCORE_SH `MANYCORE_Stype(`MANYCORE_STORE, 3'b001) +`define MANYCORE_SW `MANYCORE_Stype(`MANYCORE_STORE, 3'b010) +`define MANYCORE_ADDI `MANYCORE_Itype(`MANYCORE_OP_IMM,3'b000) +`define MANYCORE_SLTI `MANYCORE_Itype(`MANYCORE_OP_IMM, 3'b010) +`define MANYCORE_SLTIU `MANYCORE_Itype(`MANYCORE_OP_IMM, 3'b011) +`define MANYCORE_XORI `MANYCORE_Itype(`MANYCORE_OP_IMM, 3'b100) +`define MANYCORE_ORI `MANYCORE_Itype(`MANYCORE_OP_IMM, 3'b110) +`define MANYCORE_ANDI `MANYCORE_Itype(`MANYCORE_OP_IMM, 3'b111) +`define MANYCORE_SLLI `MANYCORE_Rtype(`MANYCORE_OP_IMM, 3'b001, 7'b0000000) +`define MANYCORE_SRLI `MANYCORE_Rtype(`MANYCORE_OP_IMM, 3'b101, 7'b0000000) +`define MANYCORE_SRAI `MANYCORE_Rtype(`MANYCORE_OP_IMM, 3'b101, 7'b0100000) +`define MANYCORE_ADD `MANYCORE_Rtype(`MANYCORE_OP,3'b000,7'b0000000) +`define MANYCORE_SUB `MANYCORE_Rtype(`MANYCORE_OP, 3'b000, 7'b0100000) +`define MANYCORE_SLL `MANYCORE_Rtype(`MANYCORE_OP, 3'b001, 7'b0000000) +`define MANYCORE_SLT `MANYCORE_Rtype(`MANYCORE_OP, 3'b010, 7'b0000000) +`define MANYCORE_SLTU `MANYCORE_Rtype(`MANYCORE_OP, 3'b011, 7'b0000000) +`define MANYCORE_XOR `MANYCORE_Rtype(`MANYCORE_OP, 3'b100, 7'b0000000) +`define MANYCORE_SRL `MANYCORE_Rtype(`MANYCORE_OP, 3'b101, 7'b0000000) +`define MANYCORE_SRA `MANYCORE_Rtype(`MANYCORE_OP, 3'b101, 7'b0100000) +`define MANYCORE_OR `MANYCORE_Rtype(`MANYCORE_OP, 3'b110, 7'b0000000) +`define MANYCORE_AND `MANYCORE_Rtype(`MANYCORE_OP, 3'b111, 7'b0000000) + +// CSR encoding +`define MANYCORE_CSRRW_FUN3 3'b001 +`define MANYCORE_CSRRS_FUN3 3'b010 +`define MANYCORE_CSRRC_FUN3 3'b011 +`define MANYCORE_CSRRWI_FUN3 3'b101 +`define MANYCORE_CSRRSI_FUN3 3'b110 +`define MANYCORE_CSRRCI_FUN3 3'b111 + +`define MANYCORE_CSRRW `MANYCORE_Itype(`MANYCORE_SYSTEM, `MANYCORE_CSRRW_FUN3) +`define MANYCORE_CSRRS `MANYCORE_Itype(`MANYCORE_SYSTEM, `MANYCORE_CSRRS_FUN3) +`define MANYCORE_CSRRC `MANYCORE_Itype(`MANYCORE_SYSTEM, `MANYCORE_CSRRC_FUN3) +`define MANYCORE_CSRRWI `MANYCORE_Itype(`MANYCORE_SYSTEM, `MANYCORE_CSRRWI_FUN3) +`define MANYCORE_CSRRSI `MANYCORE_Itype(`MANYCORE_SYSTEM, `MANYCORE_CSRRSI_FUN3) +`define MANYCORE_CSRRCI `MANYCORE_Itype(`MANYCORE_SYSTEM, `MANYCORE_CSRRCI_FUN3) + +// fcsr CSR addr +`define MANYCORE_CSR_FFLAGS_ADDR 12'h001 +`define MANYCORE_CSR_FRM_ADDR 12'h002 +`define MANYCORE_CSR_FCSR_ADDR 12'h003 +// machine CSR addr +`define MANYCORE_CSR_CFG_POD_ADDR 12'h360 + +// machine custom CSR addr +`define MANYCORE_CSR_CREDIT_LIMIT_ADDR 12'hfc0 +`define MANYCORE_CSR_BARCFG_ADDR 12'hfc1 +`define MANYCORE_CSR_BAR_PI_ADDR 12'hfc2 +`define MANYCORE_CSR_BAR_PO_ADDR 12'hfc3 + +// FENCE defines +`define MANYCORE_FENCE_FUN3 3'b000 +`define MANYCORE_FENCE_OP {4'b????,4'b????,4'b????,5'b00000,`MANYCORE_FENCE_FUN3,5'b00000,`MANYCORE_MISC_MEM} +`endif + diff --git a/v/vanilla_bean/bsg_manycore_proc_vanilla.sv b/v/vanilla_bean/bsg_manycore_proc_vanilla.sv index 49481565b..724bbbb78 100644 --- a/v/vanilla_bean/bsg_manycore_proc_vanilla.sv +++ b/v/vanilla_bean/bsg_manycore_proc_vanilla.sv @@ -43,7 +43,7 @@ module bsg_manycore_proc_vanilla , dmem_addr_width_lp = `BSG_SAFE_CLOG2(dmem_size_p) , pc_width_lp=(icache_addr_width_lp+icache_tag_width_p) , data_mask_width_lp=(data_width_p>>3) - , reg_addr_width_lp=RV32_reg_addr_width_gp + , reg_addr_width_lp=reg_addr_width_gp , parameter `BSG_INV_PARAM(barrier_dirs_p) , localparam barrier_lg_dirs_lp=`BSG_SAFE_CLOG2(barrier_dirs_p+1) diff --git a/v/vanilla_bean/bsg_vanilla_defines.svh b/v/vanilla_bean/bsg_vanilla_defines.svh index fe8f0e413..1d6a934ed 100644 --- a/v/vanilla_bean/bsg_vanilla_defines.svh +++ b/v/vanilla_bean/bsg_vanilla_defines.svh @@ -1,250 +1,216 @@ -`ifndef BSG_VANILLA_DEFINES_VH -`define BSG_VANILLA_DEFINES_VH +`ifndef BSG_RISCV_DEFINES_SVH +`define BSG_RISCV_DEFINES_SVH /** - * bsg_vanilla_defines.vh + * bsg_vanilla_defines.svh * * This file defines the macros - * used throughout the vanilla core. + * used for Vanilla ISA operations throughout the vanilla core. * */ -`include "bsg_defines.sv" +`include "bsg_manycore_instruction_defines.svh" -`define declare_icache_format_s(tag_width_mp, block_size_in_words_mp) \ - typedef struct packed { \ - logic [block_size_in_words_mp-1:0] lower_cout; \ - logic [block_size_in_words_mp-1:0] lower_sign; \ - logic [tag_width_mp-1:0] tag; \ - instruction_s [block_size_in_words_mp-1:0] instr; \ - } icache_format_s - -`define icache_format_width(tag_width_mp, block_size_in_words_mp) \ - ((2*block_size_in_words_mp)+tag_width_mp+(block_size_in_words_mp*$bits(instruction_s))) - -// FPU recoded Constants -`define FPU_RECODED_ONE 33'h080000000 -`define FPU_RECODED_ZERO 33'h0 -`define FPU_RECODED_CANONICAL_NAN 33'h0e0400000 - -`define RV32_MSTATUS_MIE_BIT_IDX 3 -`define RV32_MSTATUS_MPIE_BIT_IDX 7 - -`define REMOTE_INTERRUPT_JUMP_ADDR 0 // remote interrupt jump addr (word addr) -`define TRACE_INTERRUPT_JUMP_ADDR 1 // trace interrupt jump addr (word addr) - -// RV32 Opcodes -`define RV32_LOAD 7'b0000011 -`define RV32_STORE 7'b0100011 +// Vanilla Opcodes +`define VANILLA_LOAD `MANYCORE_LOAD +`define VANILLA_STORE `MANYCORE_STORE // we have branch instructions ignore the low bit so that we can place the prediction bit there. // RISC-V by default has the low bits set to 11 in the icache, so we can use those creatively. // note this relies on all code using ==? and casez. -`define RV32_BRANCH 7'b110001? - -`define RV32_JALR_OP 7'b1100111 -`define RV32_MISC_MEM 7'b0001111 -`define RV32_AMO_OP 7'b0101111 -`define RV32_JAL_OP 7'b1101111 -`define RV32_OP_IMM 7'b0010011 -`define RV32_OP 7'b0110011 -`define RV32_SYSTEM 7'b1110011 -`define RV32_AUIPC_OP 7'b0010111 -`define RV32_LUI_OP 7'b0110111 - - -// Some useful RV32 instruction macros -`define RV32_Rtype(op, funct3, funct7) {``funct7``, {5{1'b?}}, {5{1'b?}},``funct3``, {5{1'b?}},``op``} -`define RV32_Itype(op, funct3) {{12{1'b?}},{5{1'b?}},``funct3``,{5{1'b?}},``op``} -`define RV32_Stype(op, funct3) {{7{1'b?}},{5{1'b?}},{5{1'b?}},``funct3``,{5{1'b?}},``op``} -`define RV32_Utype(op) {{20{1'b?}},{5{1'b?}},``op``} - -// RV32 Immediate sign extension macros -`define RV32_signext_Iimm(instr) {{21{``instr``[31]}},``instr``[30:20]} -`define RV32_signext_Simm(instr) {{21{``instr``[31]}},``instr[30:25],``instr``[11:7]} -`define RV32_signext_Bimm(instr) {{20{``instr``[31]}},``instr``[7],``instr``[30:25],``instr``[11:8], {1'b0}} -`define RV32_signext_Uimm(instr) {``instr``[31:12], {12{1'b0}}} -`define RV32_signext_Jimm(instr) {{12{``instr``[31]}},``instr``[19:12],``instr``[20],``instr``[30:21], {1'b0}} - -`define RV32_Bimm_12inject1(instr,value) {``value``[12], ``value``[10:5], ``instr``[24:12],\ - ``value``[4:1],``value``[11],``instr``[6:0]} -`define RV32_Jimm_20inject1(instr,value) {``value``[20], ``value``[10:1], ``value``[11],``value``[19:12], ``instr``[11:0]} +`define VANILLA_BRANCH `MANYCORE_BRANCH + +`define VANILLA_JALR_OP `MANYCORE_JALR_OP +`define VANILLA_MISC_MEM `MANYCORE_MISC_MEM +`define VANILLA_AMO_OP `MANYCORE_AMO_OP +`define VANILLA_JAL_OP `MANYCORE_JAL_OP +`define VANILLA_OP_IMM `MANYCORE_OP_IMM +`define VANILLA_OP `MANYCORE_OP +`define VANILLA_SYSTEM `MANYCORE_SYSTEM +`define VANILLA_AUIPC_OP `MANYCORE_AUIPC_OP +`define VANILLA_LUI_OP `MANYCORE_LUI_OP + + +// Some useful Vanilla instruction macros +`define VANILLA_Rtype(op, funct3, funct7) {``funct7``, {5{1'b?}}, {5{1'b?}},``funct3``, {5{1'b?}},``op``} +`define VANILLA_Itype(op, funct3) {{12{1'b?}},{5{1'b?}},``funct3``,{5{1'b?}},``op``} +`define VANILLA_Stype(op, funct3) {{7{1'b?}},{5{1'b?}},{5{1'b?}},``funct3``,{5{1'b?}},``op``} +`define VANILLA_Utype(op) {{20{1'b?}},{5{1'b?}},``op``} + +// Vanilla Immediate sign extension macros +`define VANILLA_signext_Iimm(instr) {{21{``instr``[31]}},``instr``[30:20]} +`define VANILLA_signext_Simm(instr) {{21{``instr``[31]}},``instr[30:25],``instr``[11:7]} +`define VANILLA_signext_Bimm(instr) {{20{``instr``[31]}},``instr``[7],``instr``[30:25],``instr``[11:8], {1'b0}} +`define VANILLA_signext_Uimm(instr) {``instr``[31:12], {12{1'b0}}} +`define VANILLA_signext_Jimm(instr) {{12{``instr``[31]}},``instr``[19:12],``instr``[20],``instr``[30:21], {1'b0}} + +`define VANILLA_Bimm_12inject1(instr,value) {``value``[12], ``value``[10:5], ``instr``[24:12],\ + ``value``[4:1],``value``[11],``instr``[0],``instr``[1],``instr``[2],\ + ``instr``[3],``instr``[4],``instr``[5],``instr``[6]} +`define VANILLA_Jimm_20inject1(instr,value) {``value``[20], ``value``[10:1], ``value``[11],``value``[19:12], ``instr``[11:7],\ + ``instr``[0],``instr``[1],``instr``[2],``instr``[3],``instr``[4].``instr``[5],``instr``[6]} // Both JAL and BRANCH use 2-byte address, we need to pad 1'b0 at MSB to get // the real byte address -`define RV32_Bimm_13extract(instr) {``instr``[31], ``instr``[7], ``instr``[30:25], ``instr``[11:8], 1'b0} -`define RV32_Jimm_21extract(instr) {``instr``[31], ``instr``[19:12],``instr``[20],``instr``[30:21], 1'b0} +`define VANILLA_Bimm_13extract(instr) {``instr``[31], ``instr``[7], ``instr``[30:25], ``instr``[11:8], 1'b0} +`define VANILLA_Jimm_21extract(instr) {``instr``[31], ``instr``[19:12],``instr``[20],``instr``[30:21], 1'b0} -`define RV32_Iimm_12extract(instr) {``instr``[31:20]} -`define RV32_Simm_12extract(instr) {``instr[31:25],``instr``[11:7]} +`define VANILLA_Iimm_12extract(instr) {``instr``[31:20]} +`define VANILLA_Simm_12extract(instr) {``instr[31:25],``instr``[11:7]} -// RV32I Instruction encodings +// VanillaI Instruction encodings // We have to delete the white space in macro definition, // otherwise Design Compiler would issue warings. -`define RV32_LUI `RV32_Utype(`RV32_LUI_OP) -`define RV32_AUIPC `RV32_Utype(`RV32_AUIPC_OP) -`define RV32_JAL `RV32_Utype(`RV32_JAL_OP) -`define RV32_JALR `RV32_Itype(`RV32_JALR_OP, 3'b000) -`define RV32_BEQ `RV32_Stype(`RV32_BRANCH, 3'b000) -`define RV32_BNE `RV32_Stype(`RV32_BRANCH, 3'b001) -`define RV32_BLT `RV32_Stype(`RV32_BRANCH, 3'b100) -`define RV32_BGE `RV32_Stype(`RV32_BRANCH, 3'b101) -`define RV32_BLTU `RV32_Stype(`RV32_BRANCH, 3'b110) -`define RV32_BGEU `RV32_Stype(`RV32_BRANCH, 3'b111) -`define RV32_LB `RV32_Itype(`RV32_LOAD, 3'b000) -`define RV32_LH `RV32_Itype(`RV32_LOAD, 3'b001) -`define RV32_LW `RV32_Itype(`RV32_LOAD, 3'b010) -`define RV32_LBU `RV32_Itype(`RV32_LOAD, 3'b100) -`define RV32_LHU `RV32_Itype(`RV32_LOAD, 3'b101) -`define RV32_SB `RV32_Stype(`RV32_STORE, 3'b000) -`define RV32_SH `RV32_Stype(`RV32_STORE, 3'b001) -`define RV32_SW `RV32_Stype(`RV32_STORE, 3'b010) -`define RV32_ADDI `RV32_Itype(`RV32_OP_IMM,3'b000) -`define RV32_SLTI `RV32_Itype(`RV32_OP_IMM, 3'b010) -`define RV32_SLTIU `RV32_Itype(`RV32_OP_IMM, 3'b011) -`define RV32_XORI `RV32_Itype(`RV32_OP_IMM, 3'b100) -`define RV32_ORI `RV32_Itype(`RV32_OP_IMM, 3'b110) -`define RV32_ANDI `RV32_Itype(`RV32_OP_IMM, 3'b111) -`define RV32_SLLI `RV32_Rtype(`RV32_OP_IMM, 3'b001, 7'b0000000) -`define RV32_SRLI `RV32_Rtype(`RV32_OP_IMM, 3'b101, 7'b0000000) -`define RV32_SRAI `RV32_Rtype(`RV32_OP_IMM, 3'b101, 7'b0100000) -`define RV32_ADD `RV32_Rtype(`RV32_OP,3'b000,7'b0000000) -`define RV32_SUB `RV32_Rtype(`RV32_OP, 3'b000, 7'b0100000) -`define RV32_SLL `RV32_Rtype(`RV32_OP, 3'b001, 7'b0000000) -`define RV32_SLT `RV32_Rtype(`RV32_OP, 3'b010, 7'b0000000) -`define RV32_SLTU `RV32_Rtype(`RV32_OP, 3'b011, 7'b0000000) -`define RV32_XOR `RV32_Rtype(`RV32_OP, 3'b100, 7'b0000000) -`define RV32_SRL `RV32_Rtype(`RV32_OP, 3'b101, 7'b0000000) -`define RV32_SRA `RV32_Rtype(`RV32_OP, 3'b101, 7'b0100000) -`define RV32_OR `RV32_Rtype(`RV32_OP, 3'b110, 7'b0000000) -`define RV32_AND `RV32_Rtype(`RV32_OP, 3'b111, 7'b0000000) +`define VANILLA_LUI `MANYCORE_LUI +`define VANILLA_AUIPC `MANYCORE_AUIPC +`define VANILLA_JAL `MANYCORE_JAL +`define VANILLA_JALR `MANYCORE_JALR +`define VANILLA_BEQ `MANYCORE_BEQ +`define VANILLA_BNE `MANYCORE_BNE +`define VANILLA_BLT `MANYCORE_BLT +`define VANILLA_BGE `MANYCORE_BGE +`define VANILLA_BLTU `MANYCORE_BLTU +`define VANILLA_BGEU `MANYCORE_BGEU +`define VANILLA_LB `MANYCORE_LB +`define VANILLA_LH `MANYCORE_LH +`define VANILLA_LW `MANYCORE_LW +`define VANILLA_LBU `MANYCORE_LBU +`define VANILLA_LHU `MANYCORE_LHU +`define VANILLA_SB `MANYCORE_SB +`define VANILLA_SH `MANYCORE_SH +`define VANILLA_SW `MANYCORE_SW +`define VANILLA_ADDI `MANYCORE_ADDI +`define VANILLA_SLTI `MANYCORE_SLTI +`define VANILLA_SLTIU `MANYCORE_SLTIU +`define VANILLA_XORI `MANYCORE_XORI +`define VANILLA_ORI `MANYCORE_ORI +`define VANILLA_ANDI `MANYCORE_ANDI +`define VANILLA_SLLI `MANYCORE_SLLI +`define VANILLA_SRLI `MANYCORE_SRLI +`define VANILLA_SRAI `MANYCORE_SRAI +`define VANILLA_ADD `MANYCORE_ADD +`define VANILLA_SUB `MANYCORE_SUB +`define VANILLA_SLL `MANYCORE_SLL +`define VANILLA_SLT `MANYCORE_SLT +`define VANILLA_SLTU `MANYCORE_SLTU +`define VANILLA_XOR `MANYCORE_XOR +`define VANILLA_SRL `MANYCORE_SRL +`define VANILLA_SRA `MANYCORE_SRA +`define VANILLA_OR `MANYCORE_OR +`define VANILLA_AND `MANYCORE_AND // FENCE defines -`define RV32_FENCE_FUN3 3'b000 -`define RV32_FENCE_OP {4'b????,4'b????,4'b????,5'b00000,`RV32_FENCE_FUN3,5'b00000,`RV32_MISC_MEM} -`define RV32_FENCE_FM 4'b0000 -`define RV32_BARSEND_FM 4'b0001 -`define RV32_BARRECV_FM 4'b0010 +`define VANILLA_FENCE_FUN3 3'b000 +`define VANILLA_FENCE_OP {4'b????,4'b????,4'b????,5'b00000,`VANILLA_FENCE_FUN3,5'b00000,`VANILLA_MISC_MEM} +`define VANILLA_FENCE_FM 4'b0000 +`define VANILLA_BARSEND_FM 4'b0001 +`define VANILLA_BARRECV_FM 4'b0010 //TRIGGER SAIF DUMP defines -`define SAIF_TRIGGER_START {12'b000000000001,5'b00000,3'b000,5'b00000,`RV32_OP_IMM} -`define SAIF_TRIGGER_END {12'b000000000010,5'b00000,3'b000,5'b00000,`RV32_OP_IMM} +`define SAIF_TRIGGER_START {12'b000000000001,5'b00000,3'b000,5'b00000,`VANILLA_OP_IMM} +`define SAIF_TRIGGER_END {12'b000000000010,5'b00000,3'b000,5'b00000,`VANILLA_OP_IMM} // CSR encoding -`define RV32_CSRRW_FUN3 3'b001 -`define RV32_CSRRS_FUN3 3'b010 -`define RV32_CSRRC_FUN3 3'b011 -`define RV32_CSRRWI_FUN3 3'b101 -`define RV32_CSRRSI_FUN3 3'b110 -`define RV32_CSRRCI_FUN3 3'b111 - -`define RV32_CSRRW `RV32_Itype(`RV32_SYSTEM, `RV32_CSRRW_FUN3) -`define RV32_CSRRS `RV32_Itype(`RV32_SYSTEM, `RV32_CSRRS_FUN3) -`define RV32_CSRRC `RV32_Itype(`RV32_SYSTEM, `RV32_CSRRC_FUN3) -`define RV32_CSRRWI `RV32_Itype(`RV32_SYSTEM, `RV32_CSRRWI_FUN3) -`define RV32_CSRRSI `RV32_Itype(`RV32_SYSTEM, `RV32_CSRRSI_FUN3) -`define RV32_CSRRCI `RV32_Itype(`RV32_SYSTEM, `RV32_CSRRCI_FUN3) +`define VANILLA_CSRRW_FUN3 3'b001 +`define VANILLA_CSRRS_FUN3 3'b010 +`define VANILLA_CSRRC_FUN3 3'b011 +`define VANILLA_CSRRWI_FUN3 3'b101 +`define VANILLA_CSRRSI_FUN3 3'b110 +`define VANILLA_CSRRCI_FUN3 3'b111 + +`define VANILLA_CSRRW `VANILLA_Itype(`VANILLA_SYSTEM, `VANILLA_CSRRW_FUN3) +`define VANILLA_CSRRS `VANILLA_Itype(`VANILLA_SYSTEM, `VANILLA_CSRRS_FUN3) +`define VANILLA_CSRRC `VANILLA_Itype(`VANILLA_SYSTEM, `VANILLA_CSRRC_FUN3) +`define VANILLA_CSRRWI `VANILLA_Itype(`VANILLA_SYSTEM, `VANILLA_CSRRWI_FUN3) +`define VANILLA_CSRRSI `VANILLA_Itype(`VANILLA_SYSTEM, `VANILLA_CSRRSI_FUN3) +`define VANILLA_CSRRCI `VANILLA_Itype(`VANILLA_SYSTEM, `VANILLA_CSRRCI_FUN3) // fcsr CSR addr -`define RV32_CSR_FFLAGS_ADDR 12'h001 -`define RV32_CSR_FRM_ADDR 12'h002 -`define RV32_CSR_FCSR_ADDR 12'h003 +`define VANILLA_CSR_FFLAGS_ADDR 12'h001 +`define VANILLA_CSR_FRM_ADDR 12'h002 +`define VANILLA_CSR_FCSR_ADDR 12'h003 // machine CSR addr -`define RV32_CSR_MSTATUS_ADDR 12'h300 -`define RV32_CSR_MTVEC_ADDR 12'h305 -`define RV32_CSR_MIE_ADDR 12'h304 -`define RV32_CSR_MIP_ADDR 12'h344 -`define RV32_CSR_MEPC_ADDR 12'h341 -`define RV32_CSR_CFG_POD_ADDR 12'h360 +`define VANILLA_CSR_CFG_POD_ADDR 12'h360 // machine custom CSR addr -`define RV32_CSR_CREDIT_LIMIT_ADDR 12'hfc0 -`define RV32_CSR_BARCFG_ADDR 12'hfc1 -`define RV32_CSR_BAR_PI_ADDR 12'hfc2 -`define RV32_CSR_BAR_PO_ADDR 12'hfc3 +`define VANILLA_CSR_CREDIT_LIMIT_ADDR 12'hfc0 +`define VANILLA_CSR_BARCFG_ADDR 12'hfc1 +`define VANILLA_CSR_BAR_PI_ADDR 12'hfc2 +`define VANILLA_CSR_BAR_PO_ADDR 12'hfc3 // mret // used for returning from the interrupt -`define RV32_MRET {7'b0011000, 5'b00010, 5'b00000, 3'b000, 5'b00000, `RV32_SYSTEM} - -// RV32M Instruction Encodings -`define MD_MUL_FUN3 3'b000 -`define MD_MULH_FUN3 3'b001 -`define MD_MULHSU_FUN3 3'b010 -`define MD_MULHU_FUN3 3'b011 -`define MD_DIV_FUN3 3'b100 -`define MD_DIVU_FUN3 3'b101 -`define MD_REM_FUN3 3'b110 -`define MD_REMU_FUN3 3'b111 -`define RV32_MUL `RV32_Rtype(`RV32_OP, `MD_MUL_FUN3 , 7'b0000001) -`define RV32_MULH `RV32_Rtype(`RV32_OP, `MD_MULH_FUN3 , 7'b0000001) -`define RV32_MULHSU `RV32_Rtype(`RV32_OP, `MD_MULHSU_FUN3, 7'b0000001) -`define RV32_MULHU `RV32_Rtype(`RV32_OP, `MD_MULHU_FUN3 , 7'b0000001) -`define RV32_DIV `RV32_Rtype(`RV32_OP, `MD_DIV_FUN3 , 7'b0000001) -`define RV32_DIVU `RV32_Rtype(`RV32_OP, `MD_DIVU_FUN3 , 7'b0000001) -`define RV32_REM `RV32_Rtype(`RV32_OP, `MD_REM_FUN3 , 7'b0000001) -`define RV32_REMU `RV32_Rtype(`RV32_OP, `MD_REMU_FUN3 , 7'b0000001) - -// RV32A Instruction Encodings -`define RV32_LR_W {5'b00010,2'b00,5'b00000,5'b?????,3'b010,5'b?????,`RV32_AMO_OP} -`define RV32_LR_W_AQ {5'b00010,2'b10,5'b00000,5'b?????,3'b010,5'b?????,`RV32_AMO_OP} -`define RV32_AMOSWAP_W {5'b00001,2'b??,5'b?????,5'b?????,3'b010,5'b?????,`RV32_AMO_OP} -`define RV32_AMOOR_W {5'b01000,2'b??,5'b?????,5'b?????,3'b010,5'b?????,`RV32_AMO_OP} -`define RV32_AMOADD_W {5'b00000,2'b??,5'b?????,5'b?????,3'b010,5'b?????,`RV32_AMO_OP} - -// RV32F Instruction Encodings -`define RV32_OP_FP 7'b1010011 -`define RV32_LOAD_FP 7'b0000111 -`define RV32_STORE_FP 7'b0100111 - -`define RV32_FCMP_S_FUN7 7'b1010000 -`define RV32_FCLASS_S_FUN7 7'b1110000 -`define RV32_FCVT_S_F2I_FUN7 7'b1100000 -`define RV32_FCVT_S_I2F_FUN7 7'b1101000 -`define RV32_FMV_W_X_FUN7 7'b1111000 -`define RV32_FMV_X_W_FUN7 7'b1110000 - -`define RV32_FADD_S `RV32_Rtype(`RV32_OP_FP, 3'b???, 7'b0000000) -`define RV32_FSUB_S `RV32_Rtype(`RV32_OP_FP, 3'b???, 7'b0000100) -`define RV32_FMUL_S `RV32_Rtype(`RV32_OP_FP, 3'b???, 7'b0001000) - -`define RV32_FSGNJ_S `RV32_Rtype(`RV32_OP_FP, 3'b000, 7'b0010000) -`define RV32_FSGNJN_S `RV32_Rtype(`RV32_OP_FP, 3'b001, 7'b0010000) -`define RV32_FSGNJX_S `RV32_Rtype(`RV32_OP_FP, 3'b010, 7'b0010000) - -`define RV32_FMIN_S `RV32_Rtype(`RV32_OP_FP, 3'b000, 7'b0010100) -`define RV32_FMAX_S `RV32_Rtype(`RV32_OP_FP, 3'b001, 7'b0010100) - -`define RV32_FEQ_S `RV32_Rtype(`RV32_OP_FP, 3'b010, `RV32_FCMP_S_FUN7) -`define RV32_FLT_S `RV32_Rtype(`RV32_OP_FP, 3'b001, `RV32_FCMP_S_FUN7) -`define RV32_FLE_S `RV32_Rtype(`RV32_OP_FP, 3'b000, `RV32_FCMP_S_FUN7) - -`define RV32_FCLASS_S {`RV32_FCLASS_S_FUN7, 5'b00000, 5'b?????, 3'b001, 5'b?????, `RV32_OP_FP} +`define VANILLA_MRET {7'b0011000, 5'b00010, 5'b00000, 3'b000, 5'b00000, `VANILLA_SYSTEM} + +// VANILLA M Instruction Encodings +`define VANILLA_MUL `VANILLA_Rtype(`VANILLA_OP, `MD_MUL_FUN3 , 7'b0000001) +`define VANILLA_MULH `VANILLA_Rtype(`VANILLA_OP, `MD_MULH_FUN3 , 7'b0000001) +`define VANILLA_MULHSU `VANILLA_Rtype(`VANILLA_OP, `MD_MULHSU_FUN3, 7'b0000001) +`define VANILLA_MULHU `VANILLA_Rtype(`VANILLA_OP, `MD_MULHU_FUN3 , 7'b0000001) +`define VANILLA_DIV `VANILLA_Rtype(`VANILLA_OP, `MD_DIV_FUN3 , 7'b0000001) +`define VANILLA_DIVU `VANILLA_Rtype(`VANILLA_OP, `MD_DIVU_FUN3 , 7'b0000001) +`define VANILLA_REM `VANILLA_Rtype(`VANILLA_OP, `MD_REM_FUN3 , 7'b0000001) +`define VANILLA_REMU `VANILLA_Rtype(`VANILLA_OP, `MD_REMU_FUN3 , 7'b0000001) + +// VANILLA A Instruction Encodings +`define VANILLA_LR_W {5'b00010,2'b00,5'b00000,5'b?????,3'b010,5'b?????,`VANILLA_AMO_OP} +`define VANILLA_LR_W_AQ {5'b00010,2'b10,5'b00000,5'b?????,3'b010,5'b?????,`VANILLA_AMO_OP} +`define VANILLA_AMOSWAP_W {5'b00001,2'b??,5'b?????,5'b?????,3'b010,5'b?????,`VANILLA_AMO_OP} +`define VANILLA_AMOOR_W {5'b01000,2'b??,5'b?????,5'b?????,3'b010,5'b?????,`VANILLA_AMO_OP} +`define VANILLA_AMOADD_W {5'b00000,2'b??,5'b?????,5'b?????,3'b010,5'b?????,`VANILLA_AMO_OP} + +// VANILLA F Instruction Encodings +`define VANILLA_OP_FP 7'b0101100 +`define VANILLA_LOAD_FP 7'b1111000 +`define VANILLA_STORE_FP 7'b1011000 + +`define VANILLA_FCMP_S_FUN7 7'b1010000 +`define VANILLA_FCLASS_S_FUN7 7'b1110000 +`define VANILLA_FCVT_S_F2I_FUN7 7'b1100000 +`define VANILLA_FCVT_S_I2F_FUN7 7'b1101000 +`define VANILLA_FMV_W_X_FUN7 7'b1111000 +`define VANILLA_FMV_X_W_FUN7 7'b1110000 + +`define VANILLA_FADD_S `VANILLA_Rtype(`VANILLA_OP_FP, 3'b???, 7'b0000000) +`define VANILLA_FSUB_S `VANILLA_Rtype(`VANILLA_OP_FP, 3'b???, 7'b0000100) +`define VANILLA_FMUL_S `VANILLA_Rtype(`VANILLA_OP_FP, 3'b???, 7'b0001000) + +`define VANILLA_FSGNJ_S `VANILLA_Rtype(`VANILLA_OP_FP, 3'b000, 7'b0010000) +`define VANILLA_FSGNJN_S `VANILLA_Rtype(`VANILLA_OP_FP, 3'b001, 7'b0010000) +`define VANILLA_FSGNJX_S `VANILLA_Rtype(`VANILLA_OP_FP, 3'b010, 7'b0010000) + +`define VANILLA_FMIN_S `VANILLA_Rtype(`VANILLA_OP_FP, 3'b000, 7'b0010100) +`define VANILLA_FMAX_S `VANILLA_Rtype(`VANILLA_OP_FP, 3'b001, 7'b0010100) + +`define VANILLA_FEQ_S `VANILLA_Rtype(`VANILLA_OP_FP, 3'b010, `VANILLA_FCMP_S_FUN7) +`define VANILLA_FLT_S `VANILLA_Rtype(`VANILLA_OP_FP, 3'b001, `VANILLA_FCMP_S_FUN7) +`define VANILLA_FLE_S `VANILLA_Rtype(`VANILLA_OP_FP, 3'b000, `VANILLA_FCMP_S_FUN7) + +`define VANILLA_FCLASS_S {`VANILLA_FCLASS_S_FUN7, 5'b00000, 5'b?????, 3'b001, 5'b?????, `VANILLA_OP_FP} // i2f -`define RV32_FCVT_S_W {`RV32_FCVT_S_I2F_FUN7, 5'b00000, 5'b?????, 3'b???, 5'b?????, `RV32_OP_FP} -`define RV32_FCVT_S_WU {`RV32_FCVT_S_I2F_FUN7, 5'b00001, 5'b?????, 3'b???, 5'b?????, `RV32_OP_FP} +`define VANILLA_FCVT_S_W {`VANILLA_FCVT_S_I2F_FUN7, 5'b00000, 5'b?????, 3'b???, 5'b?????, `VANILLA_OP_FP} +`define VANILLA_FCVT_S_WU {`VANILLA_FCVT_S_I2F_FUN7, 5'b00001, 5'b?????, 3'b???, 5'b?????, `VANILLA_OP_FP} // f2i -`define RV32_FCVT_W_S {`RV32_FCVT_S_F2I_FUN7, 5'b00000, 5'b?????, 3'b???, 5'b?????, `RV32_OP_FP} -`define RV32_FCVT_WU_S {`RV32_FCVT_S_F2I_FUN7, 5'b00001, 5'b?????, 3'b???, 5'b?????, `RV32_OP_FP} +`define VANILLA_FCVT_W_S {`VANILLA_FCVT_S_F2I_FUN7, 5'b00000, 5'b?????, 3'b???, 5'b?????, `VANILLA_OP_FP} +`define VANILLA_FCVT_WU_S {`VANILLA_FCVT_S_F2I_FUN7, 5'b00001, 5'b?????, 3'b???, 5'b?????, `VANILLA_OP_FP} // move (i->f) -`define RV32_FMV_W_X {`RV32_FMV_W_X_FUN7, 5'b0000, 5'b?????, 3'b000, 5'b?????, `RV32_OP_FP} +`define VANILLA_FMV_W_X {`VANILLA_FMV_W_X_FUN7, 5'b0000, 5'b?????, 3'b000, 5'b?????, `VANILLA_OP_FP} // move (f->i) -`define RV32_FMV_X_W {`RV32_FMV_X_W_FUN7, 5'b0000, 5'b?????, 3'b000, 5'b?????, `RV32_OP_FP} +`define VANILLA_FMV_X_W {`VANILLA_FMV_X_W_FUN7, 5'b0000, 5'b?????, 3'b000, 5'b?????, `VANILLA_OP_FP} -`define RV32_FLW_S `RV32_Itype(`RV32_LOAD_FP, 3'b010) -`define RV32_FSW_S `RV32_Stype(`RV32_STORE_FP, 3'b010) +`define VANILLA_FLW_S `VANILLA_Itype(`VANILLA_LOAD_FP, 3'b010) +`define VANILLA_FSW_S `VANILLA_Stype(`VANILLA_STORE_FP, 3'b010) -`define RV32_FMADD_S {5'b?????, 2'b00, 5'b?????, 5'b?????, 3'b???, 5'b?????, 7'b1000011} -`define RV32_FMSUB_S {5'b?????, 2'b00, 5'b?????, 5'b?????, 3'b???, 5'b?????, 7'b1000111} -`define RV32_FNMSUB_S {5'b?????, 2'b00, 5'b?????, 5'b?????, 3'b???, 5'b?????, 7'b1001011} -`define RV32_FNMADD_S {5'b?????, 2'b00, 5'b?????, 5'b?????, 3'b???, 5'b?????, 7'b1001111} +`define VANILLA_FMADD_S {5'b?????, 2'b00, 5'b?????, 5'b?????, 3'b???, 5'b?????, 7'b0111100} +`define VANILLA_FMSUB_S {5'b?????, 2'b00, 5'b?????, 5'b?????, 3'b???, 5'b?????, 7'b0111000} +`define VANILLA_FNMSUB_S {5'b?????, 2'b00, 5'b?????, 5'b?????, 3'b???, 5'b?????, 7'b0110100} +`define VANILLA_FNMADD_S {5'b?????, 2'b00, 5'b?????, 5'b?????, 3'b???, 5'b?????, 7'b0110000} -`define RV32_FDIV_S `RV32_Rtype(`RV32_OP_FP, 3'b???, 7'b0001100) -`define RV32_FSQRT_S {7'b0101100, 5'b00000, 5'b?????, 3'b???, 5'b?????, 7'b1010011} +`define VANILLA_FDIV_S `VANILLA_Rtype(`VANILLA_OP_FP, 3'b???, 7'b0001100) +`define VANILLA_FSQRT_S {7'b0101100, 5'b00000, 5'b?????, 3'b???, 5'b?????, 7'b0101100} `endif - diff --git a/v/vanilla_bean/bsg_vanilla_pkg.sv b/v/vanilla_bean/bsg_vanilla_pkg.sv index 12147d102..062896a7f 100644 --- a/v/vanilla_bean/bsg_vanilla_pkg.sv +++ b/v/vanilla_bean/bsg_vanilla_pkg.sv @@ -12,18 +12,18 @@ package bsg_vanilla_pkg; import bsg_manycore_pkg::*; // vanilla_core global parameters -localparam RV32_reg_data_width_gp = 32; -localparam RV32_instr_width_gp = 32; -localparam RV32_reg_els_gp = 32; -localparam RV32_reg_addr_width_gp = 5; -localparam RV32_opcode_width_gp = 7; -localparam RV32_funct3_width_gp = 3; -localparam RV32_funct7_width_gp = 7; -localparam RV32_Iimm_width_gp = 12; -localparam RV32_Simm_width_gp = 12; -localparam RV32_Bimm_width_gp = 12; -localparam RV32_Uimm_width_gp = 20; -localparam RV32_Jimm_width_gp = 20; +localparam reg_data_width_gp = 32; +localparam instr_width_gp = 32; +localparam reg_els_gp = 32; +localparam reg_addr_width_gp = 5; +localparam opcode_width_gp = 7; +localparam funct3_width_gp = 3; +localparam funct7_width_gp = 7; +localparam Iimm_width_gp = 12; +localparam Simm_width_gp = 12; +localparam Bimm_width_gp = 12; +localparam Uimm_width_gp = 20; +localparam Jimm_width_gp = 20; localparam fpu_recoded_exp_width_gp = 8; localparam fpu_recoded_sig_width_gp = 24; @@ -33,16 +33,17 @@ localparam fpu_recoded_data_width_gp = (1+fpu_recoded_exp_width_gp+fpu_recoded localparam epa_word_addr_width_gp=16; -// RV32 Instruction structure +// Vanilla Core Instruction structure (Optimised towards RV32 format, may +// require changes while adding new formats) // Ideally represents a R-type instruction; these fields if // present in other types of instructions, appear at same positions typedef struct packed { - logic [RV32_funct7_width_gp-1:0] funct7; - logic [RV32_reg_addr_width_gp-1:0] rs2; - logic [RV32_reg_addr_width_gp-1:0] rs1; - logic [RV32_funct3_width_gp-1:0] funct3; - logic [RV32_reg_addr_width_gp-1:0] rd; - logic [RV32_opcode_width_gp-1:0] op; + logic [funct7_width_gp-1:0] funct7; + logic [reg_addr_width_gp-1:0] rs2; + logic [reg_addr_width_gp-1:0] rs1; + logic [funct3_width_gp-1:0] funct3; + logic [reg_addr_width_gp-1:0] rd; + logic [opcode_width_gp-1:0] op; } instruction_s; // remote request from vanilla core @@ -214,8 +215,8 @@ typedef struct packed { // Instruction decode stage signals typedef struct packed { - logic [RV32_reg_data_width_gp-1:0] pc_plus4; // PC + 4 - logic [RV32_reg_data_width_gp-1:0] pred_or_jump_addr; // Jump target PC + logic [reg_data_width_gp-1:0] pc_plus4; // PC + 4 + logic [reg_data_width_gp-1:0] pred_or_jump_addr; // Jump target PC instruction_s instruction; // Instruction being executed decode_s decode; // Decode signals fp_decode_s fp_decode; @@ -227,14 +228,14 @@ typedef struct packed // Execute stage signals typedef struct packed { - logic [RV32_reg_data_width_gp-1:0] pc_plus4; // PC + 4 - logic [RV32_reg_data_width_gp-1:0] pred_or_jump_addr; // Jump target PC + logic [reg_data_width_gp-1:0] pc_plus4; // PC + 4 + logic [reg_data_width_gp-1:0] pred_or_jump_addr; // Jump target PC instruction_s instruction; // Instruction being executed decode_s decode; // Decode signals - logic [RV32_reg_data_width_gp-1:0] rs1_val; // RF output data from RS1 address - logic [RV32_reg_data_width_gp-1:0] rs2_val; // RF output data from RS2 address + logic [reg_data_width_gp-1:0] rs1_val; // RF output data from RS1 address + logic [reg_data_width_gp-1:0] rs2_val; // RF output data from RS2 address // CSR instructions use this register for loading CSR vals - logic [RV32_Iimm_width_gp-1:0] mem_addr_op2; // the second operands to compute + logic [Iimm_width_gp-1:0] mem_addr_op2; // the second operands to compute // memory address logic icache_miss; logic valid; // valid instruction in EXE @@ -244,7 +245,7 @@ typedef struct packed // Memory stage signals typedef struct packed { - logic [RV32_reg_addr_width_gp-1:0] rd_addr; + logic [reg_addr_width_gp-1:0] rd_addr; logic write_rd; logic write_frd; logic is_byte_op; @@ -256,26 +257,26 @@ typedef struct packed { } mem_ctrl_signals_s; typedef struct packed { - logic [RV32_reg_data_width_gp-1:0] exe_result; + logic [reg_data_width_gp-1:0] exe_result; } mem_data_signals_s; // RF write back stage signals typedef struct packed { logic write_rd; - logic [RV32_reg_addr_width_gp-1:0] rd_addr; + logic [reg_addr_width_gp-1:0] rd_addr; logic icache_miss; logic clear_sb; } wb_ctrl_signals_s; typedef struct packed { - logic [RV32_reg_data_width_gp-1:0] rf_data; + logic [reg_data_width_gp-1:0] rf_data; } wb_data_signals_s; // FP Execute stage signals typedef struct packed { - logic [RV32_reg_addr_width_gp-1:0] rd; - fp_decode_s fp_decode; - frm_e rm; + logic [reg_addr_width_gp-1:0] rd; + fp_decode_s fp_decode; + frm_e rm; } fp_exe_ctrl_signals_s; typedef struct packed { @@ -287,11 +288,11 @@ typedef struct packed { // FLW write back stage signals typedef struct packed { logic valid; - logic [RV32_reg_addr_width_gp-1:0] rd_addr; + logic [reg_addr_width_gp-1:0] rd_addr; } flw_wb_ctrl_signals_s; typedef struct packed { - logic [RV32_reg_data_width_gp-1:0] rf_data; + logic [reg_data_width_gp-1:0] rf_data; } flw_wb_data_signals_s; diff --git a/v/vanilla_bean/cl_decode.sv b/v/vanilla_bean/cl_decode.sv index b69112de3..d0d3b67c5 100644 --- a/v/vanilla_bean/cl_decode.sv +++ b/v/vanilla_bean/cl_decode.sv @@ -20,6 +20,7 @@ import bsg_manycore_pkg::*; input instruction_s instruction_i , output decode_s decode_o , output fp_decode_s fp_decode_o + , output instruction_s instruction_o ); @@ -30,19 +31,19 @@ always_comb begin end else begin unique casez (instruction_i.op) - `RV32_LUI_OP, `RV32_AUIPC_OP, - `RV32_JAL_OP, `RV32_JALR_OP, - `RV32_LOAD, `RV32_OP, - `RV32_OP_IMM, `RV32_AMO_OP: begin + `VANILLA_LUI_OP, `VANILLA_AUIPC_OP, + `VANILLA_JAL_OP, `VANILLA_JALR_OP, + `VANILLA_LOAD, `VANILLA_OP, + `VANILLA_OP_IMM, `VANILLA_AMO_OP: begin decode_o.write_rd = 1'b1; end - `RV32_OP_FP: begin + `VANILLA_OP_FP: begin decode_o.write_rd = - (instruction_i.funct7 == `RV32_FCMP_S_FUN7) // FEQ, FLT, FLE - | ((instruction_i.funct7 == `RV32_FCLASS_S_FUN7) & (instruction_i.rs2 == 5'b00000)) // FCLASS, FMV.X.W - | ((instruction_i.funct7 == `RV32_FCVT_S_F2I_FUN7)); // FCVT.W.S, FCVT.WU.S + (instruction_i.funct7 == `VANILLA_FCMP_S_FUN7) // FEQ, FLT, FLE + | ((instruction_i.funct7 == `VANILLA_FCLASS_S_FUN7) & (instruction_i.rs2 == 5'b00000)) // FCLASS, FMV.X.W + | ((instruction_i.funct7 == `VANILLA_FCVT_S_F2I_FUN7)); // FCVT.W.S, FCVT.WU.S end - `RV32_SYSTEM: begin + `VANILLA_SYSTEM: begin decode_o.write_rd = 1'b1; // CSRRW, CSRRS end default: begin @@ -55,23 +56,23 @@ end // declares if OP reads from first port of register file always_comb begin unique casez (instruction_i.op) - `RV32_JALR_OP, `RV32_BRANCH, - `RV32_LOAD, `RV32_STORE, - `RV32_OP, `RV32_OP_IMM, - `RV32_AMO_OP: begin + `VANILLA_JALR_OP, `VANILLA_BRANCH, + `VANILLA_LOAD, `VANILLA_STORE, + `VANILLA_OP, `VANILLA_OP_IMM, + `VANILLA_AMO_OP: begin decode_o.read_rs1 = 1'b1; end - `RV32_OP_FP: begin + `VANILLA_OP_FP: begin decode_o.read_rs1 = - (instruction_i.funct7 == `RV32_FCVT_S_I2F_FUN7) // FCVT.S.W, FCVT.S.WU - | (instruction_i.funct7 == `RV32_FMV_W_X_FUN7); // FMV.W.X + (instruction_i.funct7 == `VANILLA_FCVT_S_I2F_FUN7) // FCVT.S.W, FCVT.S.WU + | (instruction_i.funct7 == `VANILLA_FMV_W_X_FUN7); // FMV.W.X end - `RV32_LOAD_FP, `RV32_STORE_FP: begin // FLW, FSW + `VANILLA_LOAD_FP, `VANILLA_STORE_FP: begin // FLW, FSW decode_o.read_rs1 = 1'b1; end - `RV32_SYSTEM: begin + `VANILLA_SYSTEM: begin case (instruction_i.funct3) - `RV32_CSRRW_FUN3, `RV32_CSRRS_FUN3, `RV32_CSRRC_FUN3: begin + `VANILLA_CSRRW_FUN3, `VANILLA_CSRRS_FUN3, `VANILLA_CSRRC_FUN3: begin decode_o.read_rs1 = 1'b1; end default: begin @@ -88,10 +89,10 @@ end // declares if Op reads from second port of register file always_comb begin unique casez (instruction_i.op) - `RV32_BRANCH, `RV32_STORE, `RV32_OP: begin + `VANILLA_BRANCH, `VANILLA_STORE, `VANILLA_OP: begin decode_o.read_rs2 = 1'b1; end - `RV32_AMO_OP: begin + `VANILLA_AMO_OP: begin // According the ISA, LR instruction don't read rs2 decode_o.read_rs2 = (instruction_i.funct7 ==? 7'b00001??) // amoswap | (instruction_i.funct7 ==? 7'b01000??) // amoor @@ -104,36 +105,36 @@ always_comb begin end // Load & Store -wire is_rv32_load = (instruction_i.op == `RV32_LOAD); -wire is_rv32_store = (instruction_i.op == `RV32_STORE); -assign decode_o.is_load_op = is_rv32_load | (instruction_i.op == `RV32_LOAD_FP); -assign decode_o.is_store_op = is_rv32_store | (instruction_i.op == `RV32_STORE_FP); +wire is_vanilla_load = (instruction_i.op == `VANILLA_LOAD); +wire is_vanilla_store = (instruction_i.op == `VANILLA_STORE); +assign decode_o.is_load_op = is_vanilla_load | (instruction_i.op == `VANILLA_LOAD_FP); +assign decode_o.is_store_op = is_vanilla_store | (instruction_i.op == `VANILLA_STORE_FP); assign decode_o.is_byte_op = - (is_rv32_load & (instruction_i.funct3 ==? 3'b?00)) | - (is_rv32_store & (instruction_i.funct3 == 3'b000)); + (is_vanilla_load & (instruction_i.funct3 ==? 3'b?00)) | + (is_vanilla_store & (instruction_i.funct3 == 3'b000)); assign decode_o.is_hex_op = - (is_rv32_load & (instruction_i.funct3 ==? 3'b?01)) | - (is_rv32_store & (instruction_i.funct3 == 3'b001)); + (is_vanilla_load & (instruction_i.funct3 ==? 3'b?01)) | + (is_vanilla_store & (instruction_i.funct3 == 3'b001)); assign decode_o.is_load_unsigned = - is_rv32_load & (instruction_i.funct3 ==? 3'b10?); + is_vanilla_load & (instruction_i.funct3 ==? 3'b10?); // Branch & Jump -assign decode_o.is_branch_op = instruction_i.op ==? `RV32_BRANCH; -assign decode_o.is_jal_op = instruction_i.op == `RV32_JAL_OP; -assign decode_o.is_jalr_op = instruction_i.op == `RV32_JALR_OP; +assign decode_o.is_branch_op = instruction_i.op ==? `VANILLA_BRANCH; +assign decode_o.is_jal_op = instruction_i.op == `VANILLA_JAL_OP; +assign decode_o.is_jalr_op = instruction_i.op == `VANILLA_JALR_OP; // MEMORY FENCE always_comb begin decode_o.is_fence_op = 1'b0; decode_o.is_barsend_op = 1'b0; decode_o.is_barrecv_op = 1'b0; - if (instruction_i ==? `RV32_FENCE_OP) begin + if (instruction_i ==? `VANILLA_FENCE_OP) begin // fence FM unique casez (instruction_i[31:28]) - `RV32_FENCE_FM: decode_o.is_fence_op = 1'b1; - `RV32_BARSEND_FM: decode_o.is_barsend_op = 1'b1; - `RV32_BARRECV_FM: decode_o.is_barrecv_op = 1'b1; + `VANILLA_FENCE_FM: decode_o.is_fence_op = 1'b1; + `VANILLA_BARSEND_FM: decode_o.is_barsend_op = 1'b1; + `VANILLA_BARRECV_FM: decode_o.is_barrecv_op = 1'b1; default: begin decode_o.is_fence_op = 1'b0; decode_o.is_barsend_op = 1'b0; @@ -145,14 +146,14 @@ end // CSR always_comb begin - if (instruction_i.op == `RV32_SYSTEM) begin + if (instruction_i.op == `VANILLA_SYSTEM) begin case (instruction_i.funct3) - `RV32_CSRRW_FUN3, - `RV32_CSRRS_FUN3, - `RV32_CSRRC_FUN3, - `RV32_CSRRWI_FUN3, - `RV32_CSRRSI_FUN3, - `RV32_CSRRCI_FUN3: begin + `VANILLA_CSRRW_FUN3, + `VANILLA_CSRRS_FUN3, + `VANILLA_CSRRC_FUN3, + `VANILLA_CSRRWI_FUN3, + `VANILLA_CSRRSI_FUN3, + `VANILLA_CSRRCI_FUN3: begin decode_o.is_csr_op = 1'b1; end default: begin @@ -166,7 +167,7 @@ always_comb begin end // MRET -assign decode_o.is_mret_op = (instruction_i == `RV32_MRET); +assign decode_o.is_mret_op = (instruction_i == `VANILLA_MRET); //+---------------------------------------------- @@ -175,23 +176,23 @@ assign decode_o.is_mret_op = (instruction_i == `RV32_MRET); //| //+---------------------------------------------- -assign decode_o.is_imul_op = (instruction_i ==? `RV32_MUL); +assign decode_o.is_imul_op = (instruction_i ==? `VANILLA_MUL); always_comb begin unique casez (instruction_i) - `RV32_DIV: begin + `VANILLA_DIV: begin decode_o.is_idiv_op = 1'b1; decode_o.idiv_op = eDIV; end - `RV32_DIVU: begin + `VANILLA_DIVU: begin decode_o.is_idiv_op = 1'b1; decode_o.idiv_op = eDIVU; end - `RV32_REM: begin + `VANILLA_REM: begin decode_o.is_idiv_op = 1'b1; decode_o.idiv_op = eREM; end - `RV32_REMU: begin + `VANILLA_REMU: begin decode_o.is_idiv_op = 1'b1; decode_o.idiv_op = eREMU; end @@ -210,21 +211,21 @@ end //+---------------------------------------------- // LOAD RESERVATION -assign decode_o.is_lr_op = (instruction_i ==? `RV32_LR_W); -assign decode_o.is_lr_aq_op = (instruction_i ==? `RV32_LR_W_AQ); +assign decode_o.is_lr_op = (instruction_i ==? `VANILLA_LR_W); +assign decode_o.is_lr_aq_op = (instruction_i ==? `VANILLA_LR_W_AQ); // ATOMICS always_comb begin unique casez (instruction_i) - `RV32_AMOSWAP_W: begin + `VANILLA_AMOSWAP_W: begin decode_o.is_amo_op = 1'b1; decode_o.amo_type = e_vanilla_amoswap; end - `RV32_AMOOR_W: begin + `VANILLA_AMOOR_W: begin decode_o.is_amo_op = 1'b1; decode_o.amo_type = e_vanilla_amoor; end - `RV32_AMOADD_W: begin + `VANILLA_AMOADD_W: begin decode_o.is_amo_op = 1'b1; decode_o.amo_type = e_vanilla_amoadd; end @@ -253,9 +254,9 @@ always_comb begin decode_o.is_fp_op = 1'b0; unique casez (instruction_i) // Rtype float instr - `RV32_FADD_S, `RV32_FSUB_S, `RV32_FMUL_S, - `RV32_FSGNJ_S, `RV32_FSGNJN_S, `RV32_FSGNJX_S, - `RV32_FMIN_S, `RV32_FMAX_S: begin + `VANILLA_FADD_S, `VANILLA_FSUB_S, `VANILLA_FMUL_S, + `VANILLA_FSGNJ_S, `VANILLA_FSGNJN_S, `VANILLA_FSGNJX_S, + `VANILLA_FMIN_S, `VANILLA_FMAX_S: begin decode_o.read_frs1 = 1'b1; decode_o.read_frs2 = 1'b1; decode_o.read_frs3 = 1'b0; @@ -263,7 +264,7 @@ always_comb begin decode_o.is_fp_op = 1'b1; end // compare - `RV32_FEQ_S, `RV32_FLT_S, `RV32_FLE_S: begin + `VANILLA_FEQ_S, `VANILLA_FLT_S, `VANILLA_FLE_S: begin decode_o.read_frs1 = 1'b1; decode_o.read_frs2 = 1'b1; decode_o.read_frs3 = 1'b0; @@ -271,7 +272,7 @@ always_comb begin decode_o.is_fp_op = 1'b1; end // classify - `RV32_FCLASS_S: begin + `VANILLA_FCLASS_S: begin decode_o.read_frs1 = 1'b1; decode_o.read_frs2 = 1'b0; decode_o.read_frs3 = 1'b0; @@ -279,7 +280,7 @@ always_comb begin decode_o.is_fp_op = 1'b1; end // i2f (signed int) - `RV32_FCVT_S_W, `RV32_FCVT_S_WU: begin + `VANILLA_FCVT_S_W, `VANILLA_FCVT_S_WU: begin decode_o.read_frs1 = 1'b0; decode_o.read_frs2 = 1'b0; decode_o.read_frs3 = 1'b0; @@ -287,7 +288,7 @@ always_comb begin decode_o.is_fp_op = 1'b1; end // f2i - `RV32_FCVT_W_S, `RV32_FCVT_WU_S: begin + `VANILLA_FCVT_W_S, `VANILLA_FCVT_WU_S: begin decode_o.read_frs1 = 1'b1; decode_o.read_frs2 = 1'b0; decode_o.read_frs3 = 1'b0; @@ -295,7 +296,7 @@ always_comb begin decode_o.is_fp_op = 1'b1; end // FMV (fp -> int) - `RV32_FMV_X_W: begin + `VANILLA_FMV_X_W: begin decode_o.read_frs1 = 1'b1; decode_o.read_frs2 = 1'b0; decode_o.read_frs3 = 1'b0; @@ -303,7 +304,7 @@ always_comb begin decode_o.is_fp_op = 1'b1; end // FMV (int -> fp) - `RV32_FMV_W_X: begin + `VANILLA_FMV_W_X: begin decode_o.read_frs1 = 1'b0; decode_o.read_frs2 = 1'b0; decode_o.read_frs3 = 1'b0; @@ -311,7 +312,7 @@ always_comb begin decode_o.is_fp_op = 1'b1; end // Float load - `RV32_FLW_S: begin + `VANILLA_FLW_S: begin decode_o.read_frs1 = 1'b0; decode_o.read_frs2 = 1'b0; decode_o.read_frs3 = 1'b0; @@ -319,7 +320,7 @@ always_comb begin decode_o.is_fp_op = 1'b0; end // Float store - `RV32_FSW_S: begin + `VANILLA_FSW_S: begin decode_o.read_frs1 = 1'b0; decode_o.read_frs2 = 1'b1; decode_o.read_frs3 = 1'b0; @@ -327,7 +328,7 @@ always_comb begin decode_o.is_fp_op = 1'b0; end // FMA - `RV32_FMADD_S, `RV32_FMSUB_S, `RV32_FNMSUB_S, `RV32_FNMADD_S: begin + `VANILLA_FMADD_S, `VANILLA_FMSUB_S, `VANILLA_FNMSUB_S, `VANILLA_FNMADD_S: begin decode_o.read_frs1 = 1'b1; decode_o.read_frs2 = 1'b1; decode_o.read_frs3 = 1'b1; @@ -335,7 +336,7 @@ always_comb begin decode_o.is_fp_op = 1'b1; end // FDIV, SQRT - `RV32_FDIV_S, `RV32_FSQRT_S: begin + `VANILLA_FDIV_S, `VANILLA_FSQRT_S: begin decode_o.read_frs1 = 1'b1; decode_o.read_frs2 = 1'b1; decode_o.read_frs3 = 1'b0; @@ -363,103 +364,103 @@ always_comb begin fp_decode_o.fpu_int_op = eFEQ; unique casez (instruction_i) - `RV32_FADD_S: begin + `VANILLA_FADD_S: begin fp_decode_o.is_fpu_float_op = 1'b1; fp_decode_o.fpu_float_op = eFADD; end - `RV32_FSUB_S: begin + `VANILLA_FSUB_S: begin fp_decode_o.is_fpu_float_op = 1'b1; fp_decode_o.fpu_float_op = eFSUB; end - `RV32_FMUL_S: begin + `VANILLA_FMUL_S: begin fp_decode_o.is_fpu_float_op = 1'b1; fp_decode_o.fpu_float_op = eFMUL; end - `RV32_FSGNJ_S: begin + `VANILLA_FSGNJ_S: begin fp_decode_o.is_fpu_float_op = 1'b1; fp_decode_o.fpu_float_op = eFSGNJ; end - `RV32_FSGNJN_S: begin + `VANILLA_FSGNJN_S: begin fp_decode_o.is_fpu_float_op = 1'b1; fp_decode_o.fpu_float_op = eFSGNJN; end - `RV32_FSGNJX_S: begin + `VANILLA_FSGNJX_S: begin fp_decode_o.is_fpu_float_op = 1'b1; fp_decode_o.fpu_float_op = eFSGNJX; end - `RV32_FMIN_S: begin + `VANILLA_FMIN_S: begin fp_decode_o.is_fpu_float_op = 1'b1; fp_decode_o.fpu_float_op = eFMIN; end - `RV32_FMAX_S: begin + `VANILLA_FMAX_S: begin fp_decode_o.is_fpu_float_op = 1'b1; fp_decode_o.fpu_float_op = eFMAX; end // i2f signed - `RV32_FCVT_S_W: begin + `VANILLA_FCVT_S_W: begin fp_decode_o.is_fpu_float_op = 1'b1; fp_decode_o.fpu_float_op = eFCVT_S_W; end // i2f unsigned - `RV32_FCVT_S_WU: begin + `VANILLA_FCVT_S_WU: begin fp_decode_o.is_fpu_float_op = 1'b1; fp_decode_o.fpu_float_op = eFCVT_S_WU; end // move i->f - `RV32_FMV_W_X: begin + `VANILLA_FMV_W_X: begin fp_decode_o.is_fpu_float_op = 1'b1; fp_decode_o.fpu_float_op = eFMV_W_X; end - `RV32_FMADD_S: begin + `VANILLA_FMADD_S: begin fp_decode_o.is_fpu_float_op = 1'b1; fp_decode_o.fpu_float_op = eFMADD; end - `RV32_FMSUB_S: begin + `VANILLA_FMSUB_S: begin fp_decode_o.is_fpu_float_op = 1'b1; fp_decode_o.fpu_float_op = eFMSUB; end - `RV32_FNMSUB_S: begin + `VANILLA_FNMSUB_S: begin fp_decode_o.is_fpu_float_op = 1'b1; fp_decode_o.fpu_float_op = eFNMSUB; end - `RV32_FNMADD_S: begin + `VANILLA_FNMADD_S: begin fp_decode_o.is_fpu_float_op = 1'b1; fp_decode_o.fpu_float_op = eFNMADD; end - `RV32_FDIV_S: begin + `VANILLA_FDIV_S: begin fp_decode_o.is_fdiv_op = 1'b1; end - `RV32_FSQRT_S: begin + `VANILLA_FSQRT_S: begin fp_decode_o.is_fsqrt_op = 1'b1; end - `RV32_FEQ_S: begin + `VANILLA_FEQ_S: begin fp_decode_o.is_fpu_int_op = 1'b1; fp_decode_o.fpu_int_op = eFEQ; end - `RV32_FLE_S: begin + `VANILLA_FLE_S: begin fp_decode_o.is_fpu_int_op = 1'b1; fp_decode_o.fpu_int_op = eFLE; end - `RV32_FLT_S: begin + `VANILLA_FLT_S: begin fp_decode_o.is_fpu_int_op = 1'b1; fp_decode_o.fpu_int_op = eFLT; end // f2i signed - `RV32_FCVT_W_S: begin + `VANILLA_FCVT_W_S: begin fp_decode_o.is_fpu_int_op = 1'b1; fp_decode_o.fpu_int_op = eFCVT_W_S; end // f2i unsigned - `RV32_FCVT_WU_S: begin + `VANILLA_FCVT_WU_S: begin fp_decode_o.is_fpu_int_op = 1'b1; fp_decode_o.fpu_int_op = eFCVT_WU_S; end - `RV32_FCLASS_S: begin + `VANILLA_FCLASS_S: begin fp_decode_o.is_fpu_int_op = 1'b1; fp_decode_o.fpu_int_op = eFCLASS; end // move f->i - `RV32_FMV_X_W: begin + `VANILLA_FMV_X_W: begin fp_decode_o.is_fpu_int_op = 1'b1; fp_decode_o.fpu_int_op = eFMV_X_W; end @@ -474,11 +475,15 @@ always_comb begin endcase end +always_comb begin + instruction_o <= instruction_i; +end + // Unsupported ops: // mulh, mulhsu, mulhu always_comb begin unique casez (instruction_i) - `RV32_MULH, `RV32_MULHSU, `RV32_MULHU: begin + `VANILLA_MULH, `VANILLA_MULHSU, `VANILLA_MULHU: begin decode_o.unsupported = 1'b1; end default: begin @@ -488,4 +493,3 @@ always_comb begin end endmodule - diff --git a/v/vanilla_bean/fcsr.sv b/v/vanilla_bean/fcsr.sv index e95090a46..8295448fd 100644 --- a/v/vanilla_bean/fcsr.sv +++ b/v/vanilla_bean/fcsr.sv @@ -1,15 +1,15 @@ /** - * fcsr.v + * fcsr.sv * */ -`include "bsg_vanilla_defines.svh" +`include "bsg_manycore_instruction_defines.svh" module fcsr import bsg_vanilla_pkg::*; #(localparam fflags_width_lp=$bits(fflags_s) , frm_width_lp=$bits(frm_e) - , reg_addr_width_lp=RV32_reg_addr_width_gp + , reg_addr_width_lp=reg_addr_width_gp ) ( input clk_i @@ -41,27 +41,27 @@ module fcsr always_comb begin if (v_i) begin case (funct3_i) - `RV32_CSRRW_FUN3: begin + `MANYCORE_CSRRW_FUN3: begin write_mask = {8{1'b1}}; write_data = data_i; end - `RV32_CSRRS_FUN3: begin + `MANYCORE_CSRRS_FUN3: begin write_mask = data_i; write_data = data_i; end - `RV32_CSRRC_FUN3: begin + `MANYCORE_CSRRC_FUN3: begin write_mask = data_i; write_data = ~data_i; end - `RV32_CSRRWI_FUN3: begin + `MANYCORE_CSRRWI_FUN3: begin write_mask = {8{1'b1}}; write_data = {3'b000, rs1_i}; end - `RV32_CSRRSI_FUN3: begin + `MANYCORE_CSRRSI_FUN3: begin write_mask = {3'b000, rs1_i}; write_data = {3'b000, rs1_i}; end - `RV32_CSRRCI_FUN3: begin + `MANYCORE_CSRRCI_FUN3: begin write_mask = {3'b000, rs1_i}; write_data = {3'b000, ~rs1_i}; end @@ -87,12 +87,12 @@ module fcsr always_comb begin case (addr_i) // frm - `RV32_CSR_FRM_ADDR: begin + `MANYCORE_CSR_FRM_ADDR: begin frm_write_mask = write_mask[0+:frm_width_lp]; frm_write_data = write_data[0+:frm_width_lp]; end // fcsr - `RV32_CSR_FCSR_ADDR: begin + `MANYCORE_CSR_FCSR_ADDR: begin frm_write_mask = write_mask[fflags_width_lp+:frm_width_lp]; frm_write_data = write_data[fflags_width_lp+:frm_width_lp]; end @@ -120,8 +120,8 @@ module fcsr if (v_i) begin case (addr_i) // fflags, fcsr - `RV32_CSR_FFLAGS_ADDR, - `RV32_CSR_FCSR_ADDR: begin + `MANYCORE_CSR_FFLAGS_ADDR, + `MANYCORE_CSR_FCSR_ADDR: begin fflags_write_mask = write_mask[0+:fflags_width_lp]; fflags_write_data = write_data[0+:fflags_width_lp]; end @@ -158,16 +158,16 @@ module fcsr // output always_comb begin case (addr_i) - `RV32_CSR_FFLAGS_ADDR: begin + `MANYCORE_CSR_FFLAGS_ADDR: begin data_o = {3'b0, fflags_r}; data_v_o = 1'b1; end - `RV32_CSR_FRM_ADDR: begin + `MANYCORE_CSR_FRM_ADDR: begin data_o = {5'b0, frm_r}; data_v_o = 1'b1; end - `RV32_CSR_FCSR_ADDR: begin - data_o = {frm_r, fflags_r}; + `MANYCORE_CSR_FCSR_ADDR: begin + data_o = {frm_r, fflags_r}; data_v_o = 1'b1; end default: begin @@ -185,7 +185,7 @@ module fcsr if (~reset_i) begin // this assertion checks that there are no fflags exception being accrued // while fflags are being accessed by CSR instruction in ID. - if (v_i & ((addr_i == `RV32_CSR_FFLAGS_ADDR) || (addr_i == `RV32_CSR_FCSR_ADDR))) begin + if (v_i & ((addr_i == `MANYCORE_CSR_FFLAGS_ADDR) || (addr_i == `MANYCORE_CSR_FCSR_ADDR))) begin assert(~(|fflags_v_i)) else $error("[BSG_ERROR] Exception cannot be accrued while being written by fcsr op."); end end diff --git a/v/vanilla_bean/fpu_fdiv_fsqrt.sv b/v/vanilla_bean/fpu_fdiv_fsqrt.sv index fae1e0103..d47a633c9 100644 --- a/v/vanilla_bean/fpu_fdiv_fsqrt.sv +++ b/v/vanilla_bean/fpu_fdiv_fsqrt.sv @@ -12,7 +12,7 @@ module fpu_fdiv_fsqrt import bsg_vanilla_pkg::*; #( parameter exp_width_p=fpu_recoded_exp_width_gp ,parameter sig_width_p=fpu_recoded_sig_width_gp - ,parameter reg_addr_width_p=RV32_reg_addr_width_gp + ,parameter reg_addr_width_p=reg_addr_width_gp ,parameter bits_per_iter_p=2 ,localparam recoded_data_width_lp=(1+exp_width_p+sig_width_p) ) diff --git a/v/vanilla_bean/fpu_float.sv b/v/vanilla_bean/fpu_float.sv index 5a42d3056..96f0626b9 100644 --- a/v/vanilla_bean/fpu_float.sv +++ b/v/vanilla_bean/fpu_float.sv @@ -15,8 +15,8 @@ module fpu_float import bsg_vanilla_pkg::*; #(parameter exp_width_p=fpu_recoded_exp_width_gp , sig_width_p=fpu_recoded_sig_width_gp - , data_width_p=RV32_reg_data_width_gp // integer width - , reg_addr_width_p=RV32_reg_addr_width_gp + , data_width_p=reg_data_width_gp // integer width + , reg_addr_width_p=reg_addr_width_gp , localparam recoded_data_width_lp=(1+exp_width_p+sig_width_p) ) ( diff --git a/v/vanilla_bean/fpu_float_aux.sv b/v/vanilla_bean/fpu_float_aux.sv index a9c95cdfe..bb893adeb 100644 --- a/v/vanilla_bean/fpu_float_aux.sv +++ b/v/vanilla_bean/fpu_float_aux.sv @@ -11,7 +11,7 @@ module fpu_float_aux import bsg_vanilla_pkg::*; #(parameter sig_width_p=fpu_recoded_sig_width_gp , exp_width_p=fpu_recoded_exp_width_gp - , data_width_p=RV32_reg_data_width_gp + , data_width_p=reg_data_width_gp , localparam recoded_data_width_lp=(1+sig_width_p+exp_width_p) ) diff --git a/v/vanilla_bean/fpu_float_fma.sv b/v/vanilla_bean/fpu_float_fma.sv index 22fdfb4fb..3dc4272cd 100644 --- a/v/vanilla_bean/fpu_float_fma.sv +++ b/v/vanilla_bean/fpu_float_fma.sv @@ -4,7 +4,7 @@ */ -`include "bsg_vanilla_defines.svh" +`include "bsg_manycore_instruction_defines.svh" `include "HardFloat_consts.vi" `include "HardFloat_specialize.vi" @@ -13,7 +13,7 @@ module fpu_float_fma import bsg_hardfloat_pkg::*; #(parameter exp_width_p=fpu_recoded_exp_width_gp , sig_width_p=fpu_recoded_sig_width_gp - , data_width_p=RV32_reg_data_width_gp + , data_width_p=reg_data_width_gp , localparam recoded_data_width_lp=(1+exp_width_p+sig_width_p) ) ( diff --git a/v/vanilla_bean/fpu_fmin_fmax.sv b/v/vanilla_bean/fpu_fmin_fmax.sv index 72dd75a25..df4d88973 100644 --- a/v/vanilla_bean/fpu_fmin_fmax.sv +++ b/v/vanilla_bean/fpu_fmin_fmax.sv @@ -1,5 +1,5 @@ /** - * fpu_fmin_fmax.v + * fpu_fmin_fmax.sv * */ @@ -10,7 +10,7 @@ // If only one operand is a NaN, the result is non-NaN operand. // Signaling NaN inputs set the invalid exception flag, even when the result is not NaN. -`include "bsg_vanilla_defines.svh" +`include "bsg_manycore_instruction_defines.svh" module fpu_fmin_fmax #(`BSG_INV_PARAM(exp_width_p) diff --git a/v/vanilla_bean/fpu_int.sv b/v/vanilla_bean/fpu_int.sv index 18b28025d..0ad5e9232 100644 --- a/v/vanilla_bean/fpu_int.sv +++ b/v/vanilla_bean/fpu_int.sv @@ -16,7 +16,7 @@ module fpu_int import bsg_vanilla_pkg::*; #(parameter exp_width_p=fpu_recoded_exp_width_gp , sig_width_p=fpu_recoded_sig_width_gp - , data_width_p=RV32_reg_data_width_gp // integer width + , data_width_p=reg_data_width_gp // integer width , localparam recoded_data_width_lp=(1+exp_width_p+sig_width_p) ) ( diff --git a/v/vanilla_bean/icache.sv b/v/vanilla_bean/icache.sv index c2181f8e4..ebe6a1eca 100644 --- a/v/vanilla_bean/icache.sv +++ b/v/vanilla_bean/icache.sv @@ -1,5 +1,5 @@ /** - * icache.v + * icache.sv * * Instruction cache for manycore. * @@ -9,7 +9,7 @@ * https://docs.google.com/presentation/d/1ZeRHYhqMHJQ0mRgDTilLuWQrZF7On-Be_KNNosgeW0c/edit#slide=id.g10d2e6febb9_1_0 */ -`include "bsg_vanilla_defines.svh" +`include "bsg_manycore_instruction_defines.svh" module icache import bsg_vanilla_pkg::*; @@ -33,12 +33,12 @@ module icache // icache write , input [pc_width_lp-1:0] w_pc_i - , input [RV32_instr_width_gp-1:0] w_instr_i + , input [instr_width_gp-1:0] w_instr_i // icache read (by processor) , input [pc_width_lp-1:0] pc_i , input [pc_width_lp-1:0] jalr_prediction_i - , output [RV32_instr_width_gp-1:0] instr_o + , output [instr_width_gp-1:0] instr_o , output [pc_width_lp-1:0] pred_or_jump_addr_o , output [pc_width_lp-1:0] pc_r_o , output icache_miss_o @@ -48,8 +48,8 @@ module icache // localparam // - localparam branch_pc_low_width_lp = (RV32_Bimm_width_gp+1); - localparam jal_pc_low_width_lp = (RV32_Jimm_width_gp+1); + localparam branch_pc_low_width_lp = (Bimm_width_gp+1); + localparam jal_pc_low_width_lp = (Jimm_width_gp+1); localparam branch_pc_high_width_lp = (pc_width_lp+2) - branch_pc_low_width_lp; localparam jal_pc_high_width_lp = (pc_width_lp+2) - jal_pc_low_width_lp; @@ -103,14 +103,14 @@ module icache // instruction_s w_instr; assign w_instr = w_instr_i; - wire write_branch_instr = w_instr.op ==? `RV32_BRANCH; - wire write_jal_instr = w_instr.op ==? `RV32_JAL_OP; + wire write_branch_instr = w_instr.op ==? `MANYCORE_BRANCH; + wire write_jal_instr = w_instr.op ==? `MANYCORE_JAL_OP; // BYTE address computation - wire [branch_pc_low_width_lp-1:0] branch_imm_val = `RV32_Bimm_13extract(w_instr); + wire [branch_pc_low_width_lp-1:0] branch_imm_val = `MANYCORE_Bimm_13extract(w_instr); wire [branch_pc_low_width_lp-1:0] branch_pc_val = branch_pc_low_width_lp'({w_pc_i, 2'b0}); - wire [jal_pc_low_width_lp-1:0] jal_imm_val = `RV32_Jimm_21extract(w_instr); + wire [jal_pc_low_width_lp-1:0] jal_imm_val = `MANYCORE_Jimm_21extract(w_instr); wire [jal_pc_low_width_lp-1:0] jal_pc_val = jal_pc_low_width_lp'({w_pc_i, 2'b0}); logic [branch_pc_low_width_lp-1:0] branch_pc_lower_res; @@ -123,15 +123,15 @@ module icache // Inject the 2-BYTE (half) address, the LSB is ignored. - wire [RV32_instr_width_gp-1:0] injected_instr = write_branch_instr - ? `RV32_Bimm_12inject1(w_instr, branch_pc_lower_res) + wire [instr_width_gp-1:0] injected_instr = write_branch_instr + ? `MANYCORE_Bimm_12inject1(w_instr, branch_pc_lower_res) : (write_jal_instr - ? `RV32_Jimm_20inject1(w_instr, jal_pc_lower_res) + ? `MANYCORE_Jimm_20inject1(w_instr, jal_pc_lower_res) : w_instr); wire imm_sign = write_branch_instr - ? branch_imm_val[RV32_Bimm_width_gp] - : jal_imm_val[RV32_Jimm_width_gp]; + ? branch_imm_val[Bimm_width_gp] + : jal_imm_val[Jimm_width_gp]; wire pc_lower_cout = write_branch_instr ? branch_pc_lower_cout @@ -141,7 +141,7 @@ module icache // buffered writes logic [icache_block_size_in_words_p-2:0] imm_sign_r; logic [icache_block_size_in_words_p-2:0] pc_lower_cout_r; - logic [icache_block_size_in_words_p-2:0][RV32_instr_width_gp-1:0] buffered_instr_r; + logic [icache_block_size_in_words_p-2:0][instr_width_gp-1:0] buffered_instr_r; assign icache_data_li = '{ lower_sign : {imm_sign, imm_sign_r}, @@ -275,15 +275,15 @@ module icache end end - wire is_jal_instr = instr_out.op == `RV32_JAL_OP; - wire is_jalr_instr = instr_out.op == `RV32_JALR_OP; + wire is_jal_instr = instr_out.op == `MANYCORE_JAL_OP; + wire is_jalr_instr = instr_out.op == `MANYCORE_JALR_OP; // these are bytes address logic [pc_width_lp+2-1:0] jal_pc; logic [pc_width_lp+2-1:0] branch_pc; - assign branch_pc = {branch_pc_high_out, `RV32_Bimm_13extract(instr_out)}; - assign jal_pc = {jal_pc_high_out, `RV32_Jimm_21extract(instr_out)}; + assign branch_pc = {branch_pc_high_out, `MANYCORE_Bimm_13extract(instr_out)}; + assign jal_pc = {jal_pc_high_out, `MANYCORE_Jimm_21extract(instr_out)}; // assign outputs. assign instr_o = instr_out; diff --git a/v/vanilla_bean/idiv.sv b/v/vanilla_bean/idiv.sv index 33c7930c7..1e9d6c45a 100644 --- a/v/vanilla_bean/idiv.sv +++ b/v/vanilla_bean/idiv.sv @@ -9,8 +9,8 @@ module idiv import bsg_vanilla_pkg::*; - #(data_width_p=RV32_reg_data_width_gp - ,reg_addr_width_p=RV32_reg_addr_width_gp + #(data_width_p=reg_data_width_gp + ,reg_addr_width_p=reg_addr_width_gp ) ( input clk_i diff --git a/v/vanilla_bean/load_packer.sv b/v/vanilla_bean/load_packer.sv index f8fc8adc1..221f04dd6 100644 --- a/v/vanilla_bean/load_packer.sv +++ b/v/vanilla_bean/load_packer.sv @@ -7,7 +7,7 @@ module load_packer import bsg_vanilla_pkg::*; - #(data_width_p = RV32_reg_data_width_gp) + #(data_width_p = reg_data_width_gp) ( input [data_width_p-1:0] mem_data_i diff --git a/v/vanilla_bean/lsu.sv b/v/vanilla_bean/lsu.sv index 0e8b99f83..939dfc38c 100644 --- a/v/vanilla_bean/lsu.sv +++ b/v/vanilla_bean/lsu.sv @@ -23,7 +23,7 @@ module lsu , localparam dmem_addr_width_lp=`BSG_SAFE_CLOG2(dmem_size_p) , data_mask_width_lp=(data_width_p>>3) - , reg_addr_width_lp=RV32_reg_addr_width_gp + , reg_addr_width_lp=reg_addr_width_gp ) ( input clk_i @@ -34,7 +34,7 @@ module lsu , input [data_width_p-1:0] exe_rs1_i , input [data_width_p-1:0] exe_rs2_i , input [reg_addr_width_lp-1:0] exe_rd_i - , input [RV32_Iimm_width_gp-1:0] mem_offset_i + , input [Iimm_width_gp-1:0] mem_offset_i , input [data_width_p-1:0] pc_plus4_i , input icache_miss_i diff --git a/v/vanilla_bean/mcsr.sv b/v/vanilla_bean/mcsr.sv index 6ca01fa43..8c48040ca 100644 --- a/v/vanilla_bean/mcsr.sv +++ b/v/vanilla_bean/mcsr.sv @@ -1,5 +1,5 @@ /** - * mcsr.v + * mcsr.sv * * machine CSR */ @@ -13,8 +13,8 @@ module mcsr import bsg_vanilla_pkg::*; - #(localparam reg_addr_width_lp = RV32_reg_addr_width_gp - , reg_data_width_lp = RV32_reg_data_width_gp + #(localparam reg_addr_width_lp = reg_addr_width_gp + , reg_data_width_lp = reg_data_width_gp , parameter `BSG_INV_PARAM(pc_width_p) , `BSG_INV_PARAM(barrier_dirs_p) , localparam barrier_lg_dirs_lp=`BSG_SAFE_CLOG2(barrier_dirs_p+1) @@ -87,186 +87,30 @@ module mcsr // mstatus - // priority (high to low) - // 1) mret - // 2) interrupt taken - // 3) csr instr - // *1,2 are mutually exclusive events. + // Not used in Vanilla ISA Manycore. RISCV uses a seperate mcsr.v files in + // bsg_manycore_ISA. always_comb begin mstatus_n = mstatus_r; - - if (mret_called_i) begin - mstatus_n.mie = mstatus_r.mpie; - mstatus_n.mpie = 1'b0; - end - else if (interrupt_entered_i) begin - mstatus_n.mie = 1'b0; - mstatus_n.mpie = mstatus_r.mie; - end - else if (we_i & (addr_i == `RV32_CSR_MSTATUS_ADDR)) begin - case (funct3_i) - `RV32_CSRRW_FUN3: begin - mstatus_n.mpie = data_i[`RV32_MSTATUS_MPIE_BIT_IDX]; - mstatus_n.mie = data_i[`RV32_MSTATUS_MIE_BIT_IDX]; - end - `RV32_CSRRS_FUN3: begin - mstatus_n.mpie = data_i[`RV32_MSTATUS_MPIE_BIT_IDX] - ? 1'b1 - : mstatus_r.mpie; - mstatus_n.mie = data_i[`RV32_MSTATUS_MIE_BIT_IDX] - ? 1'b1 - : mstatus_r.mie; - end - `RV32_CSRRC_FUN3: begin - mstatus_n.mpie = data_i[`RV32_MSTATUS_MPIE_BIT_IDX] - ? 1'b0 - : mstatus_r.mpie; - mstatus_n.mie = data_i[`RV32_MSTATUS_MIE_BIT_IDX] - ? 1'b0 - : mstatus_r.mie; - end - `RV32_CSRRWI_FUN3: begin - mstatus_n.mie = rs1_i[`RV32_MSTATUS_MIE_BIT_IDX]; - end - `RV32_CSRRSI_FUN3: begin - mstatus_n.mie = rs1_i[`RV32_MSTATUS_MIE_BIT_IDX] - ? 1'b1 - : mstatus_r.mie; - end - `RV32_CSRRCI_FUN3: begin - mstatus_n.mie = rs1_i[`RV32_MSTATUS_MIE_BIT_IDX] - ? 1'b0 - : mstatus_r.mie; - end - default: begin - mstatus_n = mstatus_r; - end - endcase - end + mstatus_n.mie = 1'b0; + mstatus_n.mpie = 1'b0; end - // mie - // this can be only modified by csr instr. + // mie : Do nothing for vanilla ISA always_comb begin mie_n = mie_r; - if (we_i & (addr_i == `RV32_CSR_MIE_ADDR)) begin - case (funct3_i) - `RV32_CSRRW_FUN3: begin - mie_n = data_i[17:16]; - end - `RV32_CSRRS_FUN3: begin - mie_n.trace = data_i[17] - ? 1'b1 - : mie_r.trace; - mie_n.remote = data_i[16] - ? 1'b1 - : mie_r.remote; - end - `RV32_CSRRC_FUN3: begin - mie_n.trace = data_i[17] - ? 1'b0 - : mie_r.trace; - mie_n.remote = data_i[16] - ? 1'b0 - : mie_r.remote; - end - default: mie_n = mie_r; - endcase - end end - // mip - // mip.trace is set when an instruction is executed (ID->EXE), while outside interrupt. - // mip.remote can be set/clear by remote packet. - // Both can be modified by CSR instr, which has lower priority. + // mip : Do nothing for vanilla ISA always_comb begin mip_n = mip_r; - - // trace - // if trace enable bit is low, then execute instruction signal does not set the trace pending bit. - if (instr_executed_i & mie_r.trace) begin - mip_n.trace = 1'b1; - end - else if (we_i & (addr_i == `RV32_CSR_MIP_ADDR)) begin - case (funct3_i) - `RV32_CSRRW_FUN3: begin - mip_n.trace = data_i[17]; - end - `RV32_CSRRS_FUN3: begin - mip_n.trace = data_i[17] - ? 1'b1 - : mip_r.trace; - end - `RV32_CSRRC_FUN3: begin - mip_n.trace = data_i[17] - ? 1'b0 - : mip_r.trace; - end - default: mip_n = mip_r; - endcase - end - - // remote - if (remote_interrupt_set_i) begin - mip_n.remote = 1'b1; - end - else if (remote_interrupt_clear_i) begin - mip_n.remote = 1'b0; - end - else if (we_i & (addr_i == `RV32_CSR_MIP_ADDR)) begin - case (funct3_i) - `RV32_CSRRW_FUN3: begin - mip_n.remote = data_i[16]; - end - `RV32_CSRRS_FUN3: begin - mip_n.remote = data_i[16] - ? 1'b1 - : mip_r.remote; - end - `RV32_CSRRC_FUN3: begin - mip_n.remote = data_i[16] - ? 1'b0 - : mip_r.remote; - end - default: mip_n = mip_r; - endcase - end end - // mepc - // mepc is set when the interrupt is taken. - // when the interrupt is taken, ID stage will be flushed, so CSR instr in ID will not get a chance to modify. + // mepc : Do nothing for vanilla ISA always_comb begin mepc_n = mepc_r; - - if (interrupt_entered_i) begin - mepc_n = npc_r_i; - end - else if (we_i & (addr_i == `RV32_CSR_MEPC_ADDR)) begin - case (funct3_i) - `RV32_CSRRW_FUN3: begin - mepc_n = data_i[2+:pc_width_p]; - end - `RV32_CSRRS_FUN3: begin - for (integer i = 0; i < pc_width_p; i++) begin - mepc_n[i] = data_i[2+i] - ? 1'b1 - : mepc_r[i]; - end - end - `RV32_CSRRC_FUN3: begin - for (integer i = 0; i < pc_width_p; i++) begin - mepc_n[i] = data_i[2+i] - ? 1'b0 - : mepc_r[i]; - end - end - default: mepc_n = mepc_r; - endcase - end end @@ -274,7 +118,7 @@ module mcsr always_comb begin credit_limit_n = credit_limit_r; - if (we_i & (addr_i == `RV32_CSR_CREDIT_LIMIT_ADDR) & (funct3_i == `RV32_CSRRW_FUN3)) begin + if (we_i & (addr_i == `VANILLA_CSR_CREDIT_LIMIT_ADDR) & (funct3_i == `VANILLA_CSRRW_FUN3)) begin credit_limit_n = data_i[0+:credit_counter_width_p]; end end @@ -286,7 +130,7 @@ module mcsr cfg_pod_r <= cfg_pod_reset_val_i; end else begin - if (we_i && (addr_i == `RV32_CSR_CFG_POD_ADDR) && (funct3_i == `RV32_CSRRW_FUN3)) begin + if (we_i && (addr_i == `VANILLA_CSR_CFG_POD_ADDR) && (funct3_i == `VANILLA_CSRRW_FUN3)) begin cfg_pod_r <= data_i[0+:cfg_pod_width_p]; end end @@ -300,7 +144,7 @@ module mcsr {barrier_src_r, barrier_dest_r} <= '0; end else begin - if (we_i && (addr_i == `RV32_CSR_BARCFG_ADDR) && (funct3_i == `RV32_CSRRW_FUN3)) begin + if (we_i && (addr_i == `VANILLA_CSR_BARCFG_ADDR) && (funct3_i == `VANILLA_CSRRW_FUN3)) begin barrier_src_r <= data_i[0+:barrier_dirs_p]; barrier_dest_r <= data_i[16+:barrier_lg_dirs_lp]; end @@ -317,14 +161,14 @@ module mcsr barrier_data_r <= 1'b0; end else begin - if (we_i && (addr_i == `RV32_CSR_BAR_PI_ADDR)) begin + if (we_i && (addr_i == `VANILLA_CSR_BAR_PI_ADDR)) begin case (funct3_i) - `RV32_CSRRW_FUN3: barrier_data_r <= data_i[0]; - `RV32_CSRRS_FUN3: barrier_data_r <= data_i[0] ? 1'b1 : barrier_data_r; - `RV32_CSRRC_FUN3: barrier_data_r <= data_i[0] ? 1'b0 : barrier_data_r; - `RV32_CSRRWI_FUN3: barrier_data_r <= rs1_i[0]; - `RV32_CSRRSI_FUN3: barrier_data_r <= rs1_i[0] ? 1'b1 : barrier_data_r; - `RV32_CSRRCI_FUN3: barrier_data_r <= rs1_i[0] ? 1'b0 : barrier_data_r; + `VANILLA_CSRRW_FUN3: barrier_data_r <= data_i[0]; + `VANILLA_CSRRS_FUN3: barrier_data_r <= data_i[0] ? 1'b1 : barrier_data_r; + `VANILLA_CSRRC_FUN3: barrier_data_r <= data_i[0] ? 1'b0 : barrier_data_r; + `VANILLA_CSRRWI_FUN3: barrier_data_r <= rs1_i[0]; + `VANILLA_CSRRSI_FUN3: barrier_data_r <= rs1_i[0] ? 1'b1 : barrier_data_r; + `VANILLA_CSRRCI_FUN3: barrier_data_r <= rs1_i[0] ? 1'b0 : barrier_data_r; endcase end else if (barsend_i) begin @@ -340,36 +184,22 @@ module mcsr always_comb begin data_o = '0; case (addr_i) - `RV32_CSR_MSTATUS_ADDR: begin - data_o[`RV32_MSTATUS_MPIE_BIT_IDX] = mstatus_r.mpie; - data_o[`RV32_MSTATUS_MIE_BIT_IDX] = mstatus_r.mie; - end - `RV32_CSR_MIE_ADDR: begin - data_o[17:16] = mie_r; - end - `RV32_CSR_MIP_ADDR: begin - data_o[17:16] = mip_r; - end - `RV32_CSR_MEPC_ADDR: begin - data_o[2+:pc_width_p] = mepc_r; - end - `RV32_CSR_CREDIT_LIMIT_ADDR: begin + `VANILLA_CSR_CREDIT_LIMIT_ADDR: begin data_o[0+:credit_counter_width_p] = credit_limit_r; end - `RV32_CSR_CFG_POD_ADDR: begin - data_o[0+:cfg_pod_width_p] = cfg_pod_r; + `VANILLA_CSR_CFG_POD_ADDR: begin + data_o[0+:cfg_pod_width_p] = cfg_pod_r; end - `RV32_CSR_BARCFG_ADDR: begin + `VANILLA_CSR_BARCFG_ADDR: begin data_o[0+:barrier_dirs_p] = barrier_src_r; data_o[16+:barrier_lg_dirs_lp] = barrier_dest_r; end - `RV32_CSR_BAR_PO_ADDR: begin + `VANILLA_CSR_BAR_PO_ADDR: begin data_o[0] = barrier_data_i; end - `RV32_CSR_BAR_PI_ADDR: begin + `VANILLA_CSR_BAR_PI_ADDR: begin data_o[0] = barrier_data_r; end - default: data_o = '0; endcase end diff --git a/v/vanilla_bean/network_tx.sv b/v/vanilla_bean/network_tx.sv index 417bb1d80..735c0a405 100644 --- a/v/vanilla_bean/network_tx.sv +++ b/v/vanilla_bean/network_tx.sv @@ -35,7 +35,7 @@ module network_tx , icache_addr_width_lp=`BSG_SAFE_CLOG2(icache_entries_p) , pc_width_lp=(icache_tag_width_p+icache_addr_width_lp) - , reg_addr_width_lp=RV32_reg_addr_width_gp + , reg_addr_width_lp=reg_addr_width_gp , packet_width_lp= `bsg_manycore_packet_width(addr_width_p,data_width_p,x_cord_width_p,y_cord_width_p) diff --git a/v/vanilla_bean/scoreboard.sv b/v/vanilla_bean/scoreboard.sv index e2d3978a5..e7aa0d0bb 100644 --- a/v/vanilla_bean/scoreboard.sv +++ b/v/vanilla_bean/scoreboard.sv @@ -9,7 +9,7 @@ module scoreboard import bsg_vanilla_pkg::*; - #(els_p = RV32_reg_els_gp + #(els_p = reg_els_gp , `BSG_INV_PARAM(num_src_port_p) , num_clear_port_p=1 , x0_tied_to_zero_p = 0 diff --git a/v/vanilla_bean/vanilla_core.sv b/v/vanilla_bean/vanilla_core.sv index cfe56b7ac..78fe80f8d 100644 --- a/v/vanilla_bean/vanilla_core.sv +++ b/v/vanilla_bean/vanilla_core.sv @@ -7,7 +7,7 @@ */ `include "bsg_manycore_defines.svh" -`include "bsg_vanilla_defines.svh" +`include "bsg_manycore_instruction_defines.svh" module vanilla_core import bsg_vanilla_pkg::*; @@ -39,7 +39,7 @@ module vanilla_core , dmem_addr_width_lp=`BSG_SAFE_CLOG2(dmem_size_p) , pc_width_lp=(icache_tag_width_p+`BSG_SAFE_CLOG2(icache_entries_p)) - , reg_addr_width_lp = RV32_reg_addr_width_gp + , reg_addr_width_lp = reg_addr_width_gp , data_mask_width_lp=(data_width_p>>3) , parameter debug_p=0 @@ -152,7 +152,7 @@ module vanilla_core logic [data_width_p-1:0] icache_winstr; logic [pc_width_lp-1:0] pc_n, pc_r; - instruction_s instruction; + instruction_s instruction_n, instruction_r; logic icache_miss; logic icache_flush; logic icache_flush_r_lo; @@ -182,7 +182,7 @@ module vanilla_core ,.pc_i(pc_n) ,.jalr_prediction_i(jalr_prediction) - ,.instr_o(instruction) + ,.instr_o(instruction_n) ,.pred_or_jump_addr_o(pred_or_jump_addr) ,.pc_r_o(pc_r) ,.icache_miss_o(icache_miss) @@ -218,9 +218,10 @@ module vanilla_core fp_decode_s fp_decode; cl_decode decode0 ( - .instruction_i(instruction) + .instruction_i(instruction_n) ,.decode_o(decode) ,.fp_decode_o(fp_decode) + ,.instruction_o(instruction_r) ); @@ -251,7 +252,7 @@ module vanilla_core regfile #( .width_p(data_width_p) - ,.els_p(RV32_reg_els_gp) + ,.els_p(reg_els_gp) ,.num_rs_p(2) ,.x0_tied_to_zero_p(1) ) int_rf ( @@ -263,7 +264,7 @@ module vanilla_core ,.w_data_i(int_rf_wdata) ,.r_v_i(int_rf_read) - ,.r_addr_i({instruction.rs2, instruction.rs1}) + ,.r_addr_i({instruction_r.rs2, instruction_r.rs1}) ,.r_data_o(int_rf_rdata) ); @@ -277,7 +278,7 @@ module vanilla_core logic [reg_addr_width_lp-1:0] int_sb_clear_id; scoreboard #( - .els_p(RV32_reg_els_gp) + .els_p(reg_els_gp) ,.num_src_port_p(2) ,.num_clear_port_p(1) ,.x0_tied_to_zero_p(1) @@ -312,7 +313,7 @@ module vanilla_core regfile #( .width_p(fpu_recoded_data_width_gp) - ,.els_p(RV32_reg_els_gp) + ,.els_p(reg_els_gp) ,.num_rs_p(3) ,.x0_tied_to_zero_p(0) ) float_rf ( @@ -324,7 +325,7 @@ module vanilla_core ,.w_data_i(float_rf_wdata) ,.r_v_i(float_rf_read) - ,.r_addr_i({instruction[31:27], instruction.rs2, instruction.rs1}) + ,.r_addr_i({instruction_r[31:27], instruction_r.rs2, instruction_r.rs1}) ,.r_data_o(float_rf_rdata) ); @@ -338,7 +339,7 @@ module vanilla_core logic [reg_addr_width_lp-1:0] float_sb_clear_id; scoreboard #( - .els_p(RV32_reg_els_gp) + .els_p(reg_els_gp) ,.x0_tied_to_zero_p(0) ,.num_src_port_p(3) ,.num_clear_port_p(1) @@ -480,10 +481,10 @@ module vanilla_core // calculate mem address offset // - wire [RV32_Iimm_width_gp-1:0] mem_addr_op2 = id_r.decode.is_store_op - ? `RV32_Simm_12extract(id_r.instruction) + wire [Iimm_width_gp-1:0] mem_addr_op2 = id_r.decode.is_store_op + ? `MANYCORE_Simm_12extract(id_r.instruction) : (id_r.decode.is_load_op - ? `RV32_Iimm_12extract(id_r.instruction) + ? `MANYCORE_Iimm_12extract(id_r.instruction) : '0); // 'aq' register @@ -1273,7 +1274,7 @@ module vanilla_core id_n = '{ pc_plus4: {{(data_width_p-pc_width_lp-2){1'b0}}, pc_plus4, 2'b0}, pred_or_jump_addr: {{(data_width_p-pc_width_lp-2){1'b0}}, pred_or_jump_addr, 2'b0}, - instruction: instruction, + instruction: instruction_r, decode: decode, fp_decode: fp_decode, icache_miss: 1'b0, @@ -1469,8 +1470,8 @@ module vanilla_core // stall_fcsr assign stall_fcsr = (id_r.decode.is_csr_op) - & ((id_r.instruction[31:20] == `RV32_CSR_FFLAGS_ADDR) - |(id_r.instruction[31:20] == `RV32_CSR_FCSR_ADDR)) + & ((id_r.instruction[31:20] == `MANYCORE_CSR_FFLAGS_ADDR) + |(id_r.instruction[31:20] == `MANYCORE_CSR_FCSR_ADDR)) & (fp_exe_ctrl_r.fp_decode.is_fpu_float_op |fp_exe_ctrl_r.fp_decode.is_fpu_int_op |fp_exe_ctrl_r.fp_decode.is_fdiv_op