From f534118d688fa70c0fc3a8892654d53b13dc5323 Mon Sep 17 00:00:00 2001 From: Dan Petrisko Date: Tue, 30 Nov 2021 09:06:29 -0800 Subject: [PATCH] Removing deprecated files (#609) --- v/bsg_manycore_link_to_rocc.v | 408 ------------------------ v/bsg_manycore_links_to_fsb.v | 281 ---------------- v/bsg_manycore_mesh.v | 142 --------- v/bsg_manycore_packet_streamer.v | 115 ------- v/bsg_manycore_rocc_dma.v | 283 ---------------- v/bsg_manycore_rocc_streambuf_wrapper.v | 385 ---------------------- v/bsg_manycore_rocc_wrapper.v | 309 ------------------ v/bsg_ruche_anti_buffer.v | 72 ----- 8 files changed, 1995 deletions(-) delete mode 100644 v/bsg_manycore_link_to_rocc.v delete mode 100644 v/bsg_manycore_links_to_fsb.v delete mode 100644 v/bsg_manycore_mesh.v delete mode 100644 v/bsg_manycore_packet_streamer.v delete mode 100644 v/bsg_manycore_rocc_dma.v delete mode 100644 v/bsg_manycore_rocc_streambuf_wrapper.v delete mode 100644 v/bsg_manycore_rocc_wrapper.v delete mode 100644 v/bsg_ruche_anti_buffer.v diff --git a/v/bsg_manycore_link_to_rocc.v b/v/bsg_manycore_link_to_rocc.v deleted file mode 100644 index 89907c25b..000000000 --- a/v/bsg_manycore_link_to_rocc.v +++ /dev/null @@ -1,408 +0,0 @@ -//==================================================================== -// bsg_manycore_link_to_rocc.v -// 01/18/2016, shawnless.xie@gmail.com -//==================================================================== -// This module acts as a converter between the bsg_manycore_link_sif -// of a manycore and rocc interface. -// -// Pleas contact Prof Taylor for the document. -// -`include "bsg_defines.v" -`include "bsg_rocc.v" -`include "bsg_manycore_packet.vh" - -module bsg_manycore_link_to_rocc - #( `BSG_INV_PARAM(addr_width_p) - , `BSG_INV_PARAM(data_width_p) - , `BSG_INV_PARAM(x_cord_width_p) - , `BSG_INV_PARAM(y_cord_width_p) - , parameter load_id_width_p = 5 - , parameter fifo_els_p = 4 - , parameter bsg_manycore_link_sif_width_lp=`bsg_manycore_link_sif_width(addr_width_p,data_width_p,x_cord_width_p,y_cord_width_p,load_id_width_p) - , parameter debug_lp =0 - ) - ( - // manycore side: manycore_link_sif - //the manycore clock and reset - - input [x_cord_width_p-1:0] my_x_i - , input [y_cord_width_p-1:0] my_y_i - - , input [bsg_manycore_link_sif_width_lp-1:0] link_sif_i - , output [bsg_manycore_link_sif_width_lp-1:0] link_sif_o - - // Rocket side - , input rocket_clk_i - , input rocket_reset_i - - //core control signals - , input core_status_i - , input core_exception_i - , output acc_interrupt_o - , output acc_busy_o - //command signals - , input core_cmd_valid_i - , input rocc_core_cmd_s core_cmd_s_i - , output core_cmd_ready_o - - , output core_resp_valid_o - , output rocc_core_resp_s core_resp_s_o - , input core_resp_ready_i - - //mem signals - , output mem_req_valid_o - , output rocc_mem_req_s mem_req_s_o - , input mem_req_ready_i - - , input mem_resp_valid_i - , input rocc_mem_resp_s mem_resp_s_i - - //the reset signal output to the manycore - , output reset_manycore_r_o - ); - - //local parameter definition - localparam max_out_credits_lp =200; - localparam packet_width_lp = `bsg_manycore_packet_width(addr_width_p,data_width_p,x_cord_width_p,y_cord_width_p,load_id_width_p); - localparam byte_addr_width_lp = addr_width_p + 2; - - /////////////////////////////////////////////////////////////////////////////////// - // instantiate the endpoint - logic manycore2rocc_v ; - logic manycore2rocc_yumi ; - logic [data_width_p-1:0] manycore2rocc_data ; - logic [(data_width_p>>3)-1:0] manycore2rocc_mask ; - logic [addr_width_p-1:0] manycore2rocc_addr ; - logic manycore2rocc_we ; - - logic [packet_width_lp-1:0] rocc2manycore_packet; - logic rocc2manycore_v ; - logic rocc2manycore_ready ; - - logic [$clog2(max_out_credits_lp+1)-1:0] out_credits ; - - logic [data_width_p-1:0] returned_data_r_lo ; - logic returned_v_r_lo ; - - logic [data_width_p-1:0] returning_data_li ; - logic returning_v_li ; - - bsg_manycore_endpoint_standard #( - .x_cord_width_p ( x_cord_width_p ) - ,.y_cord_width_p ( y_cord_width_p ) - ,.fifo_els_p ( fifo_els_p ) - ,.data_width_p ( data_width_p ) - ,.addr_width_p ( addr_width_p ) - ,.max_out_credits_p ( max_out_credits_lp) - )rocc_endpoint_standard - ( - .clk_i ( rocket_clk_i ) - ,.reset_i ( rocket_reset_i ) - - // mesh network - ,.link_sif_i - ,.link_sif_o - - // local incoming data interface - ,.in_v_o ( manycore2rocc_v ) - ,.in_yumi_i ( manycore2rocc_yumi ) - ,.in_data_o ( manycore2rocc_data ) - ,.in_mask_o ( manycore2rocc_mask ) - ,.in_addr_o ( manycore2rocc_addr ) - ,.in_we_o ( manycore2rocc_we ) - - // local outgoing data interface (does not include credits) - ,.out_v_i ( rocc2manycore_v ) - ,.out_packet_i ( rocc2manycore_packet ) - ,.out_ready_o ( rocc2manycore_ready ) - - // returned data for RoCC read command - ,.returned_data_r_o ( returned_data_r_lo ) - ,.returned_v_r_o ( returned_v_r_lo ) - - // The memory read value - ,.returning_data_i ( returning_data_li ) - ,.returning_v_i ( returning_v_li ) - - // whether a credit was returned; not flow controlled - ,.out_credits_o ( out_credits ) - ,.freeze_r_o ( ) - ,.reverse_arb_pr_o( ) - - ,.my_x_i - ,.my_y_i - ); - - /////////////////////////////////////////////////////////////////////////////////// - // Code for rocket reset manycore - logic reset_manycore_r; - - wire is_core_reset= core_cmd_valid_i - &( core_cmd_s_i.instr.funct7 == eRoCC_core_reset ); - - always_ff@(posedge rocket_clk_i) begin - if( rocket_reset_i ) reset_manycore_r <= 1'b0 ; - else if ( is_core_reset ) reset_manycore_r <= 1'b1 ; - else if ( reset_manycore_r ) reset_manycore_r <= 1'b0 ; - end - - /////////////////////////////////////////////////////////////////////////////////// - // Code for Segment Register - - //write segment address register, which is BYTE address - localparam seg_addr_width_lp = rocc_addr_width_gp - byte_addr_width_lp; - logic [seg_addr_width_lp-1:0] seg_addr_r; - - wire write_seg_en = core_cmd_valid_i - & ( core_cmd_s_i.instr.funct7 == eRoCC_core_seg_addr ); - - always_ff@(posedge rocket_clk_i ) - if( write_seg_en ) - seg_addr_r <= core_cmd_s_i.rs1_val[ rocc_addr_width_gp-1 : byte_addr_width_lp ]; - - /////////////////////////////////////////////////////////////////////////////////// - // Code for write manycore memory - - //control signals coming from DMA - wire dma_core_cmd_ready ; - - wire dma_core_resp_valid_lo; - rocc_core_resp_s dma_core_resp_s_lo ; - - - wire dma_mem_req_valid ; - rocc_mem_req_s dma_mem_req_s ; - wire dma_rocc2manycore_v; - rocc_manycore_addr_s dma_rocc2manycore_addr_s; - wire [data_width_p-1:0] dma_rocc2manycore_data ; - wire rocket_mem_req_credit ; - - wire is_dma_cmd = ( core_cmd_s_i.instr.funct7 == eRoCC_core_dma_addr ) - |( core_cmd_s_i.instr.funct7 == eRoCC_core_dma_skip ) - |( core_cmd_s_i.instr.funct7 == eRoCC_core_dma_xfer ) - ; - - //control signals coming from core - wire is_core_write = ( core_cmd_s_i.instr.funct7 == eRoCC_core_write ); - wire is_core_read = ( core_cmd_s_i.instr.funct7 == eRoCC_core_read ); - wire is_mc_access_cmd = core_cmd_valid_i & (is_core_write | is_core_read); - - rocc_manycore_addr_s core_rocc2manycore_addr_s; - wire [data_width_p-1:0] core_rocc2manycore_data = core_cmd_s_i.rs2_val[data_width_p-1:0]; - assign core_rocc2manycore_addr_s = core_cmd_s_i.rs1_val; - - - - /////////////////////////////////////////////////////////////////////////////////// - // Code for read manycore memory - logic [rocc_reg_addr_width_gp-1:0] wb_reg_id_r; - logic on_fly_read_r; - - wire update_wb_reg_id = is_core_read & core_cmd_valid_i & rocc2manycore_ready ; - - always_ff@( posedge rocket_clk_i ) begin - if( update_wb_reg_id ) wb_reg_id_r <= core_cmd_s_i.instr.rd ; - end - - always_ff@( posedge rocket_clk_i ) begin - if( rocket_reset_i ) on_fly_read_r <= 1'b0; - else if ( returned_v_r_lo ) on_fly_read_r <= 1'b0; - else if( update_wb_reg_id ) on_fly_read_r <= 1'b1; - end - - assign core_resp_valid_o = returned_v_r_lo | dma_core_resp_valid_lo ; - assign core_resp_s_o.rd = wb_reg_id_r; - assign core_resp_s_o.rd_data = returned_v_r_lo ? returned_data_r_lo - : dma_core_resp_s_lo.rd_data; - //merged control signals sent to manycore - //DMA and core can't write at the same time. ready signal to core will be - //disasserted while DMA is running. - rocc_manycore_addr_s mc_addr_s ; - wire [data_width_p-1:0] mc_data = dma_rocc2manycore_v ? dma_rocc2manycore_data - : core_rocc2manycore_data ; - assign mc_addr_s = dma_rocc2manycore_v ? dma_rocc2manycore_addr_s - : core_rocc2manycore_addr_s; - - wire mc_wen = is_core_write | dma_rocc2manycore_v ; - - assign rocc2manycore_v = dma_rocc2manycore_v | (is_mc_access_cmd & (~on_fly_read_r)) ; - assign rocc2manycore_packet = get_manycore_pkt( mc_addr_s, mc_data, mc_wen) ; - - - /////////////////////////////////////////////////////////////////////////////////// - // Code for accessing rocket memory - // Mancyore and DMA can't access the rocket memory at the same time. We - // won't yumi the fifo while DMA is running - rocc_mem_req_s mc_mem_req_s; - assign mc_mem_req_s = get_rocket_mem_req( manycore2rocc_data, - manycore2rocc_mask, - manycore2rocc_addr, - manycore2rocc_we ); - - //As the response will be returned out of order, we only send one request at - // a time - assign mem_req_valid_o = (dma_mem_req_valid | manycore2rocc_v) - & rocket_mem_req_credit ; - - assign mem_req_s_o = dma_mem_req_valid ? dma_mem_req_s : mc_mem_req_s; - - // We only complete the request in following case: - // 1. Rocket memory is ready - // 2. DMA is not running. - // 3. No pending rocket memory request - // manycore2rocc_v : high only if is load or store and the returning path is - // ready. - assign manycore2rocc_yumi = manycore2rocc_v & mem_req_ready_i & dma_core_cmd_ready - & rocket_mem_req_credit; - - assign returning_v_li = mem_resp_valid_i - &(mem_resp_s_i.resp_cmd == eRoCC_mem_load ) - & dma_core_cmd_ready ; - - assign returning_data_li = mem_resp_s_i.resp_data ; - -/////////////////////////////////////////////////////////////////////////////// -// THE DMA CONTROLLER - - wire dma_mem_resp_v_li = mem_resp_valid_i & (~dma_core_cmd_ready); -bsg_manycore_rocc_dma #( - .addr_width_p ( addr_width_p ) - ,.data_width_p ( data_width_p ) - ,.cfg_width_p ( rocc_cfg_width_gp ) - )rocc_dma_controller( - .clk_i (rocket_clk_i ) - ,.reset_i (rocket_reset_i ) - //command signals - ,.core_cmd_valid_i (core_cmd_valid_i ) - ,.core_cmd_s_i (core_cmd_s_i ) - ,.core_cmd_ready_o (dma_core_cmd_ready ) - - ,.core_resp_valid_o (dma_core_resp_valid_lo ) - ,.core_resp_s_o (dma_core_resp_s_lo ) - ,.core_resp_ready_i (core_resp_ready_i ) - - //rocket mem signals - ,.mem_req_valid_o (dma_mem_req_valid ) - ,.mem_req_s_o (dma_mem_req_s ) - ,.mem_req_ready_i (mem_req_ready_i ) - - ,.mem_resp_valid_i (mem_resp_valid_i ) - ,.mem_resp_s_i (mem_resp_s_i ) - //manycore mem signals - ,.rocc2manycore_v_o (dma_rocc2manycore_v ) - ,.rocc2manycore_addr_s_o (dma_rocc2manycore_addr_s) - ,.rocc2manycore_data_o (dma_rocc2manycore_data ) - ,.rocc2manycore_ready_i (rocc2manycore_ready ) - - //DMA status signals - ,.mem_req_credit_i (rocket_mem_req_credit ) - ); - - // counting the pending request into rocket - logic [$clog2(max_out_credits_lp+1)-1:0] rocket_out_credits_o ; - wire launch_rocket_mem_req = mem_req_valid_o & mem_req_ready_i ; - - bsg_counter_up_down #(.max_val_p (max_out_credits_lp) - ,.init_val_p(max_out_credits_lp) - ) out_credit_ctr - ( .clk_i (rocket_clk_i ) - ,.reset_i (rocket_reset_i ) - ,.down_i (launch_rocket_mem_req ) // launch remote store - ,.up_i (mem_resp_valid_i ) // receive credit back - ,.count_o (rocket_out_credits_o ) - ); - //only allows 1 pending rocket memory request - assign rocket_mem_req_credit = rocket_out_credits_o > (max_out_credits_lp -1); - /////////////////////////////////////////////////////////////////////////////////// - // assign the outputs to rocc_core - assign core_cmd_ready_o = rocc2manycore_ready & dma_core_cmd_ready & (~on_fly_read_r) ; - - assign acc_interrupt_o = 1'b0 ; - assign acc_busy_o = (rocket_out_credits_o != max_out_credits_lp) | (~dma_core_cmd_ready); - /////////////////////////////////////////////////////////////////////////////////// - // functions and tasks - function [rocc_addr_width_gp-1:0] get_rocket_addr( input logic [ addr_width_p-1 : 0] manycore_addr); - return { seg_addr_r, manycore_addr,2'b0 }; - endfunction - - //functions to encode the manycore packet - `declare_bsg_manycore_packet_s(addr_width_p, data_width_p, x_cord_width_p, y_cord_width_p, load_id_width_p); - function bsg_manycore_packet_s get_manycore_pkt( - input rocc_manycore_addr_s rocket_addr_s - , input [data_width_p-1 : 0] manycore_value - , input wen - ); - - logic [1:0] op_n ; - op_n= wen ? `ePacketOp_remote_store - : `ePacketOp_remote_load ; - - - get_manycore_pkt = '{ - op : op_n - //this is acutally the mask - ,op_ex : 4'b1111 - - // remote top bit of address, which is the special op code space. - // low bits are automatically cut off - ,addr : { rocket_addr_s.cfg, rocket_addr_s.word_addr [ addr_width_p-2: 0]} - - ,data : manycore_value - ,x_cord : rocket_addr_s.x_cord [ x_cord_width_p-1: 0] - ,y_cord : rocket_addr_s.y_cord [ y_cord_width_p-1: 0] - - ,src_x_cord : my_x_i - ,src_y_cord : my_y_i - - }; - - endfunction - - //functions to encode the rocket memory request - function rocc_mem_req_s get_rocket_mem_req(input [data_width_p-1:0 ] data, - input [(data_width_p>>3)-1:0 ] mask, - input [addr_width_p-1:0 ] word_addr , - input we - ); - get_rocket_mem_req.req_addr = get_rocket_addr( word_addr ) ; - get_rocket_mem_req.req_tag = rocc_mem_tag_width_gp'(0) ; - get_rocket_mem_req.req_cmd = we ? eRoCC_mem_store : eRoCC_mem_load ; - //currently only support 32bits - get_rocket_mem_req.req_typ = eRoCC_mem_32bits ; - get_rocket_mem_req.req_phys = 1'b1 ; - get_rocket_mem_req.req_data = rocc_data_width_gp'(data) ; - - endfunction - - /////////////////////////////////////////////////////////////////////////////////// - //synopsys translate_off - if( debug_lp ) begin:debug_link_to_rocc - always@(negedge rocket_clk_i ) begin - if( write_seg_en ) begin - $display("Configuring Segment Register with value :\ - %h, Seg Reg bitwidth=%d, Maycore Byte Addr bitwidth=%d", seg_addr_r, seg_addr_width_lp, byte_addr_width_lp); - end - end - end - - always@(negedge rocket_clk_i ) begin - if( returned_data_r_lo ) assert( core_resp_ready_i ) else - $error("Rocket must ready to receive the read data"); - end - - always@(negedge rocket_clk_i ) begin - if( manycore2rocc_v & manycore2rocc_we) assert ( & manycore2rocc_mask) else - $error("Only supports word access to rocket right now"); - end - - always@(negedge rocket_clk_i) begin - if( manycore2rocc_v ) assert( dma_core_cmd_ready ) else - $error("Memory traffics from manycore can not be handled with the DMA is running"); - end - //synopsys translate_on - - assign reset_manycore_r_o = reset_manycore_r ; -endmodule - -`BSG_ABSTRACT_MODULE(bsg_manycore_link_to_rocc) - diff --git a/v/bsg_manycore_links_to_fsb.v b/v/bsg_manycore_links_to_fsb.v deleted file mode 100644 index 707f1b995..000000000 --- a/v/bsg_manycore_links_to_fsb.v +++ /dev/null @@ -1,281 +0,0 @@ - -// This module acts as a converter between the interconnect -// of a manycore and the FSB interconnect. -// -// We make use of the bsg_channel_tunnel to virtualize the -// links. -// -`include "bsg_defines.v" -`include "bsg_fsb_pkg.v" - -module bsg_manycore_links_to_fsb - #(`BSG_INV_PARAM(ring_width_p) - , `BSG_INV_PARAM(id_width_p) - , `BSG_INV_PARAM(dest_id_p) - , `BSG_INV_PARAM(num_links_p) - , `BSG_INV_PARAM(addr_width_p) - , `BSG_INV_PARAM(data_width_p) - , parameter load_id_width_p = 5 - , `BSG_INV_PARAM(x_cord_width_p) - , `BSG_INV_PARAM(y_cord_width_p) - - // how many remote credits we have; see bsg_channel_tunnel for how to do this calculation. - // typically this number is fairly large - - , `BSG_INV_PARAM(remote_credits_p) - - , parameter use_pseudo_large_fifo_p = 0 - , parameter bsg_manycore_link_sif_width_lp=`bsg_manycore_link_sif_width(addr_width_p,data_width_p,x_cord_width_p,y_cord_width_p,load_id_width_p) - ) - (input clk_i - , input reset_i - - // manycore side: array of links - - , input [num_links_p-1:0][bsg_manycore_link_sif_width_lp-1:0] links_sif_i - , output [num_links_p-1:0][bsg_manycore_link_sif_width_lp-1:0] links_sif_o - - // FSB side - - // input channel - , input v_i - , input [ring_width_p-1:0] data_i - , output ready_o - - // output channel - , output v_o - , output [ring_width_p-1:0] data_o - , input yumi_i - ); - - `declare_bsg_manycore_link_sif_s(addr_width_p,data_width_p,x_cord_width_p,y_cord_width_p,load_id_width_p); - - // also defines return packet - `declare_bsg_manycore_packet_s (addr_width_p,data_width_p,x_cord_width_p,y_cord_width_p,load_id_width_p); - - bsg_manycore_link_sif_s [num_links_p-1:0] links_sif_i_cast, links_sif_o_cast; - - assign links_sif_i_cast = links_sif_i; - assign links_sif_o = links_sif_o_cast; - - localparam num_nets_lp = 2; - localparam num_in_lp = num_nets_lp * num_links_p; - localparam width_lp = `BSG_MAX($bits(bsg_manycore_packet_s),$bits(bsg_manycore_return_packet_s)); - localparam tagged_width_lp = $clog2(num_in_lp+1) + width_lp; - - // **** - // **** Signals for manycore link side of bsg_channel_tunnel - // **** - - // incoming demultiplexed data - logic [num_in_lp-1:0][width_lp-1:0] data_li; - logic [num_in_lp-1:0] v_li; - logic [num_in_lp-1:0] yumi_lo; - - // outgoing demultiplexed data - logic [num_in_lp-1:0][width_lp-1:0] data_lo; - logic [num_in_lp-1:0] v_lo; - logic [num_in_lp-1:0] yumi_li; - - genvar i,j; - - // **** - // **** Handle manycore link side of bsg_channel_tunnel - // **** - - for (i = 0; i < num_links_p; i=i+1) - begin: rof - bsg_manycore_fwd_link_sif_s fwd_li, fwd_lo; - bsg_manycore_rev_link_sif_s rev_li, rev_lo; - - // coming in from manycore - assign fwd_lo = links_sif_i_cast[i].fwd; - assign rev_lo = links_sif_i_cast[i].rev; - - // going out to manycore - assign links_sif_o_cast[i].fwd = fwd_li; - assign links_sif_o_cast[i].rev = rev_li; - - for (j = 0; j < num_nets_lp; j=j+1) - begin: rof2 - localparam localwidth_lp = j ? $bits(bsg_manycore_return_packet_s) : $bits(bsg_manycore_packet_s); - logic ready_lo; - - logic [localwidth_lp-1:0] data; - - if (j) - begin - assign rev_li.ready_and_rev = ready_lo; - assign data = rev_lo.data; - end - else - begin - assign fwd_li.ready_and_rev = ready_lo; - assign data = fwd_lo.data; - end - - // ** place a two fifo on both channels going from manycore to outside world - bsg_two_fifo #(.width_p(localwidth_lp)) fifo - (.clk_i (clk_i ) - ,.reset_i(reset_i) - - // input - ,.ready_o(ready_lo) - ,.data_i (data) - ,.v_i (j ? rev_lo.v : fwd_lo.v ) - - // output - ,.v_o ( v_li[i*2+j]) - ,.data_o (data_li[i*2+j][localwidth_lp-1:0]) - ,.yumi_i (yumi_lo[i*2+j]) - ); - - // zero extra bits for shorter packet - if (localwidth_lp < width_lp) - assign data_li[i*2+j][width_lp-1:localwidth_lp] = 0; - end // block: rof2sd - - // ** for fwd channels going from outside world to manycore - assign fwd_li.data = data_lo[i*2 ][$bits(bsg_manycore_packet_s)-1:0]; - assign fwd_li.v = v_lo[i*2 ]; - assign yumi_li[i*2] = v_lo[i*2 ] & fwd_lo.ready_and_rev; // v/y to v&r conversion - - // ** for rev channels going from outside world to manycore - assign rev_li.data = data_lo[i*2+1][$bits(bsg_manycore_return_packet_s)-1:0]; - assign rev_li.v = v_lo[i*2+1]; - assign yumi_li[i*2+1] = v_lo[i*2+1] & rev_lo.ready_and_rev; // v/y to v&r conversion - end - - - // **** - // **** Handle FSB side of bsg_channel_tunnel - // **** - - // incoming multiplexed data - logic [tagged_width_lp-1:0] multi_data_li; - logic multi_v_li; - logic multi_yumi_lo; - - // ** place a FIFO on FSB traffic coming in from outside world towards bsg_channel_tunnel - - bsg_two_fifo #(.width_p(tagged_width_lp)) fifo - (.clk_i (clk_i ) - ,.reset_i(reset_i) - - // input - ,.ready_o(ready_o ) - ,.data_i (data_i[0+:tagged_width_lp]) // note: we assume that the useful data in the packet - // is in the low-order bits. - ,.v_i (v_i ) - - // output - ,.v_o (multi_v_li) - ,.data_o (multi_data_li) - ,.yumi_i (multi_yumi_lo) - ); - - // outgoing multiplexed data; we need to append the packet header info to convert into data_o, of size ring_width_p - logic [tagged_width_lp-1:0] multi_data_lo; - - `declare_bsg_fsb_pkt_s(ring_width_p,id_width_p); - - bsg_fsb_pkt_client_s out_pkt; - - // synopsys translate_off - initial begin - assert($bits(bsg_fsb_pkt_client_s)==ring_width_p) - else $error("bsg_fsb_pkt_client_s and ring_width_p do not line up",$bits(bsg_fsb_pkt_client_s),ring_width_p); - - assert(tagged_width_lp <= (ring_width_p - (id_width_p+1) )) - else $error("manycore packet size (tagged:%0d bits) exceed that of fsb (avaliable:%0d).", - tagged_width_lp, (ring_width_p - (id_width_p+1) )); - end - // synopsys translate_on - - localparam bsg_fsb_pkt_client_s_data_size_lp = $bits(bsg_fsb_pkt_client_data_t); - - assign out_pkt.destid = dest_id_p; - assign out_pkt.cmd = 0; - assign out_pkt.data = bsg_fsb_pkt_client_s_data_size_lp ' (multi_data_lo); - assign data_o = out_pkt; - - // **** - // **** Finally, the bsg_channel_tunnel itself - // **** - - // we tunnel a manycore packet - bsg_channel_tunnel #(.width_p (width_lp ) - ,.num_in_p(num_in_lp) - ,.remote_credits_p(remote_credits_p) // fixme - ,.use_pseudo_large_fifo_p(use_pseudo_large_fifo_p) - ) bct - (.clk_i - ,.reset_i - - // fsb side - // in - ,.multi_data_i (multi_data_li) - ,.multi_v_i (multi_v_li ) - ,.multi_yumi_o (multi_yumi_lo) - - // out - ,.multi_data_o (multi_data_lo) - ,.multi_v_o (v_o ) - ,.multi_yumi_i (yumi_i ) - - // manycore side - - ,.data_i (data_li) - ,.v_i (v_li ) - ,.yumi_o (yumi_lo) - - ,.data_o (data_lo) - ,.v_o (v_lo ) - ,.yumi_i (yumi_li) - ); - - -endmodule - -`BSG_ABSTRACT_MODULE(bsg_manycore_links_to_fsb) - - - -/* - localparam addr_width_lp = 20; - localparam data_width_lp = 32; - - localparam x_cord_width_lp =`BSG_SAFE_CLOG2(num_tiles_x_p); - localparam y_cord_width_lp =`BSG_SAFE_CLOG2(num_tiles_y_p+extra_io_rows_p); - - // both E and W links will get stubbed off - // bsg_manycore_link_sif_s [E:W][num_tiles_y_p-1:0][bsg_manycore_link_sif_width_lp-1:0] hor_link_sif_lo, hor_link_sif_li; - - // the north link portion of this will get stubbed off - bsg_manycore_link_sif_s [S:N][num_tiles_x_p-1:0][bsg_manycore_link_sif_width_lp-1:0] ver_link_sif_lo, ver_link_sif_lo; - - bsg_manycore #(.bank_size_p (bank_size_p) - - ,.num_banks_p (num_banks_p ) - ,.num_tiles_x_p(num_tiles_x_p) - ,.num_tiles_y_p(num_tiles_y_p) - ,.extra_io_rows_p(extra_io_rows_p) - - ,.stub_w_p ( num_tiles_y_p { 1'b1 } ) - ,.stub_e_p ( num_tiles_y_p { 1'b1 } ) - ,.stub_n_p ( num_tiles_x_p { 1'b1 } ) - ,.stub_s_p ( num_tiles_x_p { 1'b0 } ) - - ,.addr_width_p (addr_width_lp) - ,.data_width_p (data_width_lp) - - ) bmc - (.clk_i (clk_i ) - ,.reset_i(reset_i) - - ,.hor_link_sif_i() // stubbed - ,.hor_link_sif_o() // stubbed - ,.ver_link_sif_i(ver_link_sif_li) - ,.ver_link_sif_o(ver_link_sif_lo) - ); - */ diff --git a/v/bsg_manycore_mesh.v b/v/bsg_manycore_mesh.v deleted file mode 100644 index d2c74fe4c..000000000 --- a/v/bsg_manycore_mesh.v +++ /dev/null @@ -1,142 +0,0 @@ - -`include "bsg_defines.v" -`include "bsg_manycore_packet.vh" - -module bsg_manycore_mesh - -import bsg_noc_pkg::*; // {P=0, W, E, N, S} - - #( - // array params - parameter num_tiles_x_p = -1 - ,parameter num_tiles_y_p = -1 - - // array i/o params - ,parameter stub_w_p = {num_tiles_y_p{1'b0}} - ,parameter stub_e_p = {num_tiles_y_p{1'b0}} - ,parameter stub_n_p = {num_tiles_x_p{1'b0}} - ,parameter stub_s_p = {num_tiles_x_p{1'b0}} - - // enable debugging - ,parameter debug_p = 0 - - // this control how many extra IO rows are addressable in - // the network outside of the manycore array - - ,parameter extra_io_rows_p = 1 - - // this parameter sets the size of addresses that are transmitted in the network - // and corresponds to the amount of physical words that are addressable by a remote - // tile. here are some various settings: - // - // 30: maximum value, i.e. 2^30 words. - // 20: maximum value to allow for traversal over a bsg_fsb - // 13: value for 8 banks of 1024 words of ram in each tile - // - // obviously smaller values take up less die area. - // - - ,`BSG_INV_PARAM(addr_width_p ) - - ,parameter x_cord_width_lp = `BSG_SAFE_CLOG2(num_tiles_x_p) - ,parameter y_cord_width_lp = `BSG_SAFE_CLOG2(num_tiles_y_p + extra_io_rows_p) // extra row for I/O at bottom of chip - - - // changing this parameter is untested - - ,parameter data_width_p = 32 - - ,parameter load_id_width_p = 5 - - ,parameter bsg_manycore_link_sif_width_lp = `bsg_manycore_link_sif_width(addr_width_p,data_width_p,x_cord_width_lp,y_cord_width_lp,load_id_width_p) - - // insert bufx8's on outputs - ,parameter repeater_output_p = 0 // snew * x * y bits. - - ) - ( input clk_i - ,input reset_i - - // horizontal -- {E,W} - ,input [E:W][num_tiles_y_p-1:0][bsg_manycore_link_sif_width_lp-1:0] hor_link_sif_i - ,output [E:W][num_tiles_y_p-1:0][bsg_manycore_link_sif_width_lp-1:0] hor_link_sif_o - - // vertical -- {S,N} - ,input [S:N][num_tiles_x_p-1:0][bsg_manycore_link_sif_width_lp-1:0] ver_link_sif_i - ,output [S:N][num_tiles_x_p-1:0][bsg_manycore_link_sif_width_lp-1:0] ver_link_sif_o - - ,input [num_tiles_y_p-1:0][num_tiles_x_p-1:0][bsg_manycore_link_sif_width_lp-1:0] proc_link_sif_i - ,output [num_tiles_y_p-1:0][num_tiles_x_p-1:0][bsg_manycore_link_sif_width_lp-1:0] proc_link_sif_o - ); - - // synopsys translate_off - initial - begin - assert ((num_tiles_x_p > 0) && (num_tiles_y_p>0)) - else $error("num_tiles_x_p and num_tiles_y_p must be positive constants"); - - $display("$bits(addr)=%-d, $bits(op)=%-d, $bits(op_ex)=%-d, $bits(data)=%-d, $bits(return_pkt)=%-d, $bits(y_cord)=%-d, $bits(x_cord)=%-d", - addr_width_p,2,(data_width_p>>3),data_width_p,y_cord_width_lp+x_cord_width_lp,y_cord_width_lp,x_cord_width_lp); - end - // synopsys translate_on - - `declare_bsg_manycore_link_sif_s(addr_width_p,data_width_p,x_cord_width_lp,y_cord_width_lp,load_id_width_p); - - bsg_manycore_link_sif_s [num_tiles_y_p-1:0][num_tiles_x_p-1:0][S:W] link_in; - bsg_manycore_link_sif_s [num_tiles_y_p-1:0][num_tiles_x_p-1:0][S:W] link_out; - - localparam dirs_lp = 4; - - /* TILES */ - - genvar r,c; - - for (r = 0; r < num_tiles_y_p; r = r+1) - begin: y - for (c = 0; c < num_tiles_x_p; c = c+1) - begin: x - bsg_manycore_mesh_node # - (.stub_p ({ (r == num_tiles_y_p-1) ? (((stub_s_p>>c) & 1'b1) == 1) : 1'b0 // s - ,(r == 0) ? (((stub_n_p>>c) & 1'b1) == 1) : 1'b0 // n - ,(c == num_tiles_x_p-1) ? (((stub_e_p>>r) & 1'b1) == 1) : 1'b0 // e - ,(c == 0) ? (((stub_w_p>>r) & 1'b1) == 1) : 1'b0 // w - } - ) - ,.x_cord_width_p (x_cord_width_lp) - ,.y_cord_width_p (y_cord_width_lp) - ,.data_width_p (data_width_p) - ,.addr_width_p (addr_width_p) - ,.load_id_width_p (load_id_width_p) - ,.debug_p (debug_p) - // select buffer instructions for this particular node - ,.repeater_output_p( (repeater_output_p >> (4*(r*num_tiles_x_p+c))) & 4'b1111) - ) rtr - ( .clk_i (clk_i) - ,.reset_i(reset_i) - - ,.links_sif_i (link_in [r][c]) - ,.links_sif_o (link_out[r][c]) - - ,.proc_link_sif_i(proc_link_sif_i [r][c]) - ,.proc_link_sif_o(proc_link_sif_o [r][c]) - - ,.my_x_i (x_cord_width_lp'(c)) - ,.my_y_i (y_cord_width_lp'(r)) - ); - end - end - - // stitch together all of the tiles into a mesh - - bsg_mesh_stitch #( .width_p(bsg_manycore_link_sif_width_lp) - ,.x_max_p(num_tiles_x_p) - ,.y_max_p(num_tiles_y_p) - ) link - (.outs_i(link_out), .ins_o(link_in) - ,.hor_i(hor_link_sif_i), .hor_o(hor_link_sif_o) - ,.ver_i(ver_link_sif_i), .ver_o(ver_link_sif_o) - ); - -endmodule - -`BSG_ABSTRACT_MODULE(bsg_manycore_mesh) diff --git a/v/bsg_manycore_packet_streamer.v b/v/bsg_manycore_packet_streamer.v deleted file mode 100644 index 650ec14f6..000000000 --- a/v/bsg_manycore_packet_streamer.v +++ /dev/null @@ -1,115 +0,0 @@ - -`include "bsg_defines.v" - -module bsg_manycore_packet_streamer #( - // maximum number of outstanding words - max_out_credits_p) - , rom_words_p) - , freeze_init_p=1'b1 - , `BSG_INV_PARAM(x_cord_width_p ) - , `BSG_INV_PARAM(y_cord_width_p ) - , `BSG_INV_PARAM(addr_width_p ) - , `BSG_INV_PARAM(data_width_p ) - , debug_p = 1 - , packet_width_lp = `bsg_manycore_packet_width(addr_width_p,data_width_p,x_cord_width_p,y_cord_width_p) - , bsg_manycore_link_sif_width_lp = `bsg_manycore_link_sif_width(addr_width_p,data_width_p,x_cord_width_p,y_cord_width_p) - ) - (input clk_i - , input reset_i - - , input [bsg_manycore_link_sif_width_lp-1:0] link_sif_i - , output [bsg_manycore_link_sif_width_lp-1:0] link_sif_o - - , input [x_cord_width_p-1:0] my_x_i - , input [y_cord_width_p-1:0] my_y_i - - // connection to the rom - , output [`BSG_SAFE_CLOG2(rom_words_p)-1:0] rom_addr_o - , input [packet_width_lp-1:0] rom_data_i - , output done_o - ); - - logic pkt_v, pkt_yumi; - logic [data_width_p-1:0 ] pkt_data; - logic [addr_width_p-1:0 ] pkt_addr; - logic [(data_width_p>>3)-1:0] pkt_mask; - - logic freeze_r; - - `declare_bsg_manycore_packet_s(addr_width_p, data_width_p, x_cord_width_p, y_cord_width_p); - - bsg_manycore_packet_s out_packet_li; - logic out_v_li; - logic out_ready_lo; - logic [$clog2(max_out_credits_p+1)-1:0] out_credits_lo; - - // we are not receiving data with this node, so we tie this off to - // the input and absorb packets - assign pkt_yumi = pkt_v; - - bsg_manycore_endpoint_standard #(.x_cord_width_p (x_cord_width_p) - ,.y_cord_width_p (y_cord_width_p) - ,.fifo_els_p (2) // since this module is not receiving data - ,.freeze_init_p (freeze_init_p) // the input fifo small - ,.max_out_credits_p(max_out_credits_p) - ,.data_width_p (data_width_p) - ,.addr_width_p (addr_width_p) - ) endp - (.clk_i - ,.reset_i - ,.link_sif_i - ,.link_sif_o - ,.in_v_o (pkt_v) - ,.in_yumi_i(pkt_yumi) - ,.in_data_o(pkt_data) - ,.in_mask_o(pkt_mask) - ,.in_addr_o(pkt_addr) - - ,.out_v_i (out_v_li) - ,.out_packet_i (out_packet_li) - ,.out_ready_o (out_ready_lo) - ,.out_credits_o(out_credits_lo) - - ,.my_x_i - ,.my_y_i - - ,.freeze_r_o(freeze_r) - ); - - wire data_transferred = out_v_li & out_ready_lo; - - wire done_n, done_r; - assign done_n = done_r | ((rom_addr_o == (rom_words_p-1)) & data_transferred); - - bsg_dff_reset #(.width_p(1), .harden_p(0)) done_reg - (.clock_i(clk_i) - ,.data_i(done_n) - ,.reset_i - ,.data_o(done_r) - ); - - assign out_v_li = (~done_r & ~freeze_r & (|out_credits_lo)); - assign out_packet_li = rom_data_i; - - bsg_counter_clear_up #(.max_val_p(rom_words_p-1) - ,.init_val_p(0) - ) bccu - (.clk_i - ,.reset_i - ,.clear_i(1'b0) - ,.up_i(data_transferred & ~done_n) - ,.count_o(rom_addr_o) - ); - - if (debug_p) - always @(negedge clk_i) - begin - if (data_transferred) - $display("## bsg_manycore_packet_streamer v=%b packet=%b ready=%b out_credits_lo=%b rom_addr=%b freeze=%b done_o=%b" - , out_v_li, out_packet_li, out_ready_lo, out_credits_lo, rom_addr_o, freeze_r, done_o); - if (done_n & ~done_r) - $display("## bsg_manycore_packet_streamer finished transmission (%m)"); - end -endmodule - -`BSG_ABSTRACT_MODULE(bsg_manycore_packet_streamer) diff --git a/v/bsg_manycore_rocc_dma.v b/v/bsg_manycore_rocc_dma.v deleted file mode 100644 index 8024ce275..000000000 --- a/v/bsg_manycore_rocc_dma.v +++ /dev/null @@ -1,283 +0,0 @@ -//==================================================================== -// bsg_manycore_rocc_dma.v -// 02/21/2016, shawnless.xie@gmail.com -//==================================================================== -// This module implements the DMA function for movind data from Rocket -// to the manycore memory -// 1. ONLY supports word transfer yet. -// 2. Address must be aligned with 4 bytes. -// 3. The bit width of the manycore related registers are rocc_addr_width -// because the information of x_tiles, y_tiles are included in manycore -// address, the related registers should be 64 bits. So does the adder. -// 4. The bit width of the rocket related registers are rocc_mem_addr_width -// -// 5. The bit width of following registers is determined by cfg_width_p -// run_bytes register -// repeats register -// -`include "bsg_defines.v" -`include "bsg_rocc.v" - -module bsg_manycore_rocc_dma #( - `BSG_INV_PARAM(addr_width_p ) //the data width for manycore data - ,`BSG_INV_PARAM(data_width_p ) //the addr width for manycore address - ,cfg_width_p = 16 //the configuration register width - )( - input clk_i - ,input reset_i - //command signals - ,input core_cmd_valid_i - ,input rocc_core_cmd_s core_cmd_s_i - ,output core_cmd_ready_o - - ,output core_resp_valid_o - ,output rocc_core_resp_s core_resp_s_o - ,input core_resp_ready_i - //rocket mem signals - ,output mem_req_valid_o - ,output rocc_mem_req_s mem_req_s_o - ,input mem_req_ready_i - - ,input mem_resp_valid_i - ,input rocc_mem_resp_s mem_resp_s_i - //manycore mem signals - ,output rocc2manycore_v_o - ,output rocc_manycore_addr_s rocc2manycore_addr_s_o - ,output [data_width_p-1:0] rocc2manycore_data_o - ,input rocc2manycore_ready_i - - //DMA status signals - ,input mem_req_credit_i - ); - - localparam zero_ext_lp = (rocc_data_width_gp - 2*cfg_width_p); -///////////////////////////////////////////////////////////////////////// -// manycore address registers. - logic [rocc_addr_width_gp-1 : 0 ] manycore_byte_addr_r; - //save the address that will send to the manycore - logic [rocc_addr_width_gp-1 : 0 ] manycore_byte_addr_r_r; - - wire manycore_addr_cfg_en = core_cmd_valid_i - & ( core_cmd_s_i.instr.funct7 == eRoCC_core_dma_addr); - - wire [rocc_addr_width_gp-1 : 0] manycore_addr_cfg_value = - core_cmd_s_i.rs1_val[ rocc_addr_width_gp-1:0 ] ; - - wire manycore_addr_update_en; - wire [rocc_addr_width_gp-1 : 0] manycore_addr_update_value; - - always_ff@(posedge clk_i) begin - if( reset_i) manycore_byte_addr_r <= 'b0; - else if( manycore_addr_cfg_en) manycore_byte_addr_r <= manycore_addr_cfg_value; - else if( manycore_addr_update_en)manycore_byte_addr_r <= manycore_addr_update_value; - end - - always_ff@(posedge clk_i) begin - if( manycore_addr_update_en) manycore_byte_addr_r_r <= manycore_byte_addr_r ; - end - -///////////////////////////////////////////////////////////////////////// -// rocket address registers. - logic [rocc_mem_addr_width_gp-1:0 ] rocket_byte_addr_r; - wire rocket_addr_cfg_en = core_cmd_valid_i - & ( core_cmd_s_i.instr.funct7 == eRoCC_core_dma_addr); - - wire [rocc_mem_addr_width_gp-1 : 0] rocket_addr_cfg_value = - core_cmd_s_i.rs2_val[ rocc_mem_addr_width_gp-1:0 ]; - - wire rocket_addr_update_en; - wire [rocc_mem_addr_width_gp-1 : 0] rocket_addr_update_value; - - always_ff@(posedge clk_i) begin - if( reset_i) rocket_byte_addr_r <= 'b0; - else if( rocket_addr_cfg_en) rocket_byte_addr_r <= rocket_addr_cfg_value; - else if( rocket_addr_update_en) rocket_byte_addr_r <= rocket_addr_update_value; - end - -///////////////////////////////////////////////////////////////////////// -// manycore skip registers. - logic [rocc_addr_width_gp-1 : 0] manycore_byte_skip_r; - - wire manycore_skip_cfg_en = core_cmd_valid_i - & ( core_cmd_s_i.instr.funct7 == eRoCC_core_dma_skip); - - wire [rocc_addr_width_gp-1 : 0] manycore_skip_cfg_value = - core_cmd_s_i.rs1_val[ rocc_addr_width_gp-1:0 ]; - - always_ff@(posedge clk_i) begin - if( reset_i) manycore_byte_skip_r <= 'b0; - else if( manycore_skip_cfg_en) manycore_byte_skip_r <= manycore_skip_cfg_value; - end - -///////////////////////////////////////////////////////////////////////// -// rocket skip registers. - logic [rocc_mem_addr_width_gp-1:0 ] rocket_byte_skip_r; - wire rocket_skip_cfg_en = core_cmd_valid_i - & ( core_cmd_s_i.instr.funct7 == eRoCC_core_dma_skip); - - wire [rocc_mem_addr_width_gp-1 : 0] rocket_skip_cfg_value = - core_cmd_s_i.rs2_val[rocc_mem_addr_width_gp-1:0]; - - - always_ff@(posedge clk_i) begin - if( reset_i) rocket_byte_skip_r <= 'b0; - else if( rocket_skip_cfg_en) rocket_byte_skip_r <= rocket_skip_cfg_value; - end - -///////////////////////////////////////////////////////////////////////// -// run_bytes register - logic [cfg_width_p -1:0 ] run_bytes_r; - wire run_bytes_cfg_en = core_cmd_valid_i - & ( core_cmd_s_i.instr.funct7 == eRoCC_core_dma_xfer); - - wire [cfg_width_p-1 : 0] run_bytes_cfg_value = - core_cmd_s_i.rs1_val[cfg_width_p-1:0] ; - - - always_ff@(posedge clk_i) begin - if( reset_i) run_bytes_r <= 'b0; - else if( run_bytes_cfg_en) run_bytes_r <= run_bytes_cfg_value; - end -///////////////////////////////////////////////////////////////////////// -// repeats register - logic [cfg_width_p-1:0 ] repeats_r; - wire repeats_cfg_en = core_cmd_valid_i - & ( core_cmd_s_i.instr.funct7 == eRoCC_core_dma_xfer); - - wire [cfg_width_p-1 : 0] repeats_cfg_value = - core_cmd_s_i.rs2_val[ cfg_width_p-1:0 ]; - - - always_ff@(posedge clk_i) begin - if( reset_i) repeats_r <= 'b0; - else if( repeats_cfg_en) repeats_r <= repeats_cfg_value; - end -///////////////////////////////////////////////////////////////////////// -// The state machine & related counters - -// this is the signal which control the pulse of DMA - wire rocket_mem_req_valid; - wire dma_repeats_finish; - - eRoCC_dma_stat curr_stat_e_r, next_stat_e ; - - always_ff@(posedge clk_i) begin - if( reset_i ) curr_stat_e_r <= eRoCC_dma_idle; - else curr_stat_e_r <= next_stat_e ; - end - - wire dma_run_en = core_cmd_valid_i & (core_cmd_s_i.instr.funct7 == eRoCC_core_dma_xfer ); - always_comb begin - case ( curr_stat_e_r ) - eRoCC_dma_idle : - if( dma_run_en) next_stat_e = eRoCC_dma_busy; - else next_stat_e = eRoCC_dma_idle; - eRoCC_dma_busy : - if( dma_repeats_finish) next_stat_e = eRoCC_dma_idle; - else next_stat_e = eRoCC_dma_busy; - endcase - end - -//the run_bytes counter - wire run_word_overflowed; - bsg_counter_en_overflow #( .width_p ( cfg_width_p-2 ) ) run_word_counter ( - .clk_i ( clk_i ) - ,.reset_i ( reset_i | run_bytes_cfg_en ) - ,.en_i ( rocket_mem_req_valid ) - ,.limit_i ( run_bytes_r[cfg_width_p-1:2] ) - ,.counter_o ( ) - ,.overflowed_o( run_word_overflowed ) - ); - -//the repeats counter - wire repeats_overflowed; - bsg_counter_en_overflow #( .width_p ( cfg_width_p) ) repeats_counter ( - .clk_i ( clk_i ) - ,.reset_i ( reset_i | repeats_cfg_en ) - ,.en_i ( run_word_overflowed & rocket_mem_req_valid) - ,.limit_i ( repeats_r ) - ,.counter_o ( ) - ,.overflowed_o( repeats_overflowed ) - ); - - assign dma_repeats_finish = run_word_overflowed & repeats_overflowed; -//the manycore address update - assign manycore_addr_update_en = rocket_mem_req_valid ; - assign manycore_addr_update_value = run_word_overflowed - ? (manycore_byte_addr_r + manycore_byte_skip_r+4) - : (manycore_byte_addr_r + 4 ) ; - -//the rocket address update - assign rocket_addr_update_en = rocket_mem_req_valid ; - assign rocket_addr_update_value = run_word_overflowed - ? (rocket_byte_addr_r + rocket_byte_skip_r + 4 ) - : (rocket_byte_addr_r + 4 ) ; - -///////////////////////////////////////////////////////////////////////// -// The signals to the rocket memory - - //TODO: We issue request only if it is able to receive the result. We check - //the rocc2manycore_ready_i to see if we are able to receive the result. - //this should work under current design because there won't be more RoCC - //commands writing manycore memory while there is a dma on goning, - //but this is not strictly correct. - - //TODO: We issue request only if there is no pending request in rocket - //memory. We can improve this by using FIFO which can outputs the number of - //current empty slots, and counts the pending request - assign rocket_mem_req_valid = ( curr_stat_e_r == eRoCC_dma_busy ) - & mem_req_ready_i - & mem_req_credit_i - & rocc2manycore_ready_i ; - - //assgin the output signals. - assign mem_req_valid_o = rocket_mem_req_valid ; - assign mem_req_s_o = get_rocket_load_req( rocket_byte_addr_r ) ; - -///////////////////////////////////////////////////////////////////////// -// The signals to the manycore memory - assign rocc2manycore_v_o = mem_resp_valid_i - & ( mem_resp_s_i.resp_cmd == eRoCC_mem_load) - & ( curr_stat_e_r == eRoCC_dma_busy ); - - assign rocc2manycore_data_o = mem_resp_s_i.resp_data[ data_width_p-1:0]; - assign rocc2manycore_addr_s_o = manycore_byte_addr_r_r ; - -//functions to encode the rocket memory request - function rocc_mem_req_s get_rocket_load_req( - input [rocc_mem_addr_width_gp-1:0 ] addr); - get_rocket_load_req = '{ req_addr : addr , - req_tag : rocc_mem_tag_width_gp'(0), - req_cmd : eRoCC_mem_load , - //currently only support 32bits - req_typ : eRoCC_mem_32bits , - req_phys : 1'b1 , - req_data : rocc_data_width_gp'(0) - }; - - endfunction -///////////////////////////////////////////////////////////////////////// -/* - logic [2*cfg_width_p-1:0] bytes_transferred_r; - always_ff@(posedge clk_i) begin - if( reset_i ) bytes_transferred_r <= '0; - else if( rocket_mem_req_valid ) bytes_transferred_r <= bytes_transferred_r + 4; - end - - logic core_fence_req_r; - wire core_fence_req = core_cmd_valid_i &( core_cmd_s_i.instr.funct7 == eRoCC_core_dma_fence); - always_ff@(posedge clk_i) begin - if( reset_i ) core_fence_req_r <= 1'b0; - else if(core_fence_req) core_fence_req_r <= 1'b1; - else if(core_resp_valid_o) core_fence_req_r <= 1'b0; - end - assign core_resp_valid_o = core_fence_req_r & core_cmd_ready_o; - - assign core_resp_s_o = { {zero_ext_lp'(0)}, bytes_transferred_r}; -*/ - assign core_resp_valid_o = 1'b0; - assign core_resp_s_o = 'b0; - assign core_cmd_ready_o = (curr_stat_e_r != eRoCC_dma_busy); -endmodule - -`BSG_ABSTRACT_MODULE(bsg_manycore_rocc_dma) diff --git a/v/bsg_manycore_rocc_streambuf_wrapper.v b/v/bsg_manycore_rocc_streambuf_wrapper.v deleted file mode 100644 index df6fb5a8b..000000000 --- a/v/bsg_manycore_rocc_streambuf_wrapper.v +++ /dev/null @@ -1,385 +0,0 @@ -//==================================================================== -// bsg_manycore_rocc_wrapper.v -// 01/21/2016, shawnless.xie@gmail.com -//==================================================================== -// This module wrapper the bsg_manycore with RoCC interface -// The RoCC distributed at the south of the manycore. -// ******* ID of each RoCC is (num_tiles_y, x) -// -// Pleas contact Prof Taylor for the document. -// -`include "bsg_defines.v" -`include "bsg_manycore_packet.vh" -`include "bsg_rocc.v" - -module bsg_manycore_rocc_streambuf_wrapper - import bsg_noc_pkg ::*; // {P=0, W, E, N, S} - #( - ////////////////////////////////////////////////////// - //Parameters for RoCC interface - `BSG_INV_PARAM( rocc_num_p ) - //The distribution of the rocc interface. - //1. Non-zero value is the index of the rocc interface, - // starting from 1. - //2. for example, {32'h0000_2010} - // indicates there are two rocc interface, their x_cords are 1 and 3. - //3. rocc_num_p must not bigger than tiles_x - ,parameter rocc_dist_vec_p = 0 - - ////////////////////////////////////////////////////// - //Parameters for out_fifo interface - ,`BSG_INV_PARAM( out_fifo_num_p ) - //The distribution of the out_fifo interface. - //The same meaning with rocc_dist_vect_p - ,parameter out_fifo_dist_vec_p = 0 - //The output fifo width must be multiple times of data_width_p - ,parameter out_fifo_width_scale_p = 2 - ,parameter out_fifo_in_channel_num_lp = out_fifo_num_p / out_fifo_width_scale_p - - ////////////////////////////////////////////////////// - //Parameters for manycore - // tile params - ,`BSG_INV_PARAM(bank_size_p ) - ,`BSG_INV_PARAM(num_banks_p ) - ,`BSG_INV_PARAM(imem_size_p ) // in words - - // array params - ,parameter num_tiles_x_p = -1 - ,parameter num_tiles_y_p = -1 - - ,parameter hetero_type_vec_p = 0 - // enable debugging - ,parameter debug_p = 0 - ,parameter extra_io_rows_p = 1 - ,`BSG_INV_PARAM(addr_width_p ) - - ,parameter x_cord_width_lp = `BSG_SAFE_CLOG2(num_tiles_x_p) - ,parameter y_cord_width_lp = `BSG_SAFE_CLOG2(num_tiles_y_p + extra_io_rows_p) // extra row for I/O at bottom of chip - - // changing this parameter is untested - ,parameter data_width_p = 32 - ,parameter bsg_manycore_link_sif_width_lp = `bsg_manycore_link_sif_width(addr_width_p,data_width_p,x_cord_width_lp,y_cord_width_lp) - // snew * y * x bits - ,parameter repeater_output_p = 0 - //the async FIFO depth - ,parameter async_fifo_els_p = 8 - - ,parameter out_fifo_width_lp = data_width_p * out_fifo_width_scale_p - ) - ( input clk_i - ,input manycore_clk_i - ,input [rocc_num_p-1:0] reset_i - - //core control signals - , input [rocc_num_p-1:0] core_status_i - , input [rocc_num_p-1:0] core_exception_i - , output [rocc_num_p-1:0] acc_interrupt_o - , output [rocc_num_p-1:0] acc_busy_o - //command signals - , input [rocc_num_p-1:0] core_cmd_valid_i - , input rocc_core_cmd_s [rocc_num_p-1:0] core_cmd_s_i - , output [rocc_num_p-1:0] core_cmd_ready_o - - , output [rocc_num_p-1:0] core_resp_valid_o - , output rocc_core_resp_s [rocc_num_p-1:0] core_resp_s_o - , input [rocc_num_p-1:0] core_resp_ready_i - //mem signals - , output [rocc_num_p-1:0] mem_req_valid_o - , output rocc_mem_req_s [rocc_num_p-1:0] mem_req_s_o - , input [rocc_num_p-1:0] mem_req_ready_i - - , input [rocc_num_p-1:0] mem_resp_valid_i - , input rocc_mem_resp_s [rocc_num_p-1:0] mem_resp_s_i - - //FIFO output - , output v_o - , output [out_fifo_width_lp-1:0] data_o - , input ready_i - ); - - //get one hex from the parameter vector p - `define GET_HEX(p, ind) ( (p >> (ind* 4)) & 4'hF ) - `define GET_HEX_MIN_1(p, ind) ( `GET_HEX(p,ind) - 4'h1 ) - - //declare the interface to the bsg_manycore - `declare_bsg_manycore_link_sif_s(addr_width_p, data_width_p, x_cord_width_lp, y_cord_width_lp); - - bsg_manycore_link_sif_s [S:N][num_tiles_x_p-1:0] MC_ver_link_li, MC_ver_link_lo; - bsg_manycore_link_sif_s [E:W][num_tiles_y_p-1:0] MC_hor_link_li, MC_hor_link_lo; - - - - //generate the reset signal into the manycore - //1. if all rocket are in reset status, the manycore are all reseted. - //2. if any rocket is dis-reseted, the manycore reset is the reset signal - // from the rocc interface, which is reset command from rocket core. - wire RC_all_rocket_reset = & reset_i ; - wire [rocc_num_p-1:0] RC_rocc_output_reset ; - - wire RC_reset_n = RC_all_rocket_reset | ( | RC_rocc_output_reset ) ; - - - wire MC_reset_n; - bsg_launch_sync_sync#(.width_p (1) )manycore_reset_sync( - . iclk_i ( clk_i ) - ,. iclk_reset_i ( 1'b0 ) - ,. oclk_i ( manycore_clk_i) - ,. iclk_data_i ( RC_reset_n ) - ,. iclk_data_o ( ) - ,. oclk_data_o ( MC_reset_n) - ); - - logic MC_reset_r; - always_ff@(posedge manycore_clk_i) MC_reset_r <= MC_reset_n; - - //instantiate the manycore - bsg_manycore # ( - .bank_size_p (bank_size_p ) - ,.imem_size_p (imem_size_p ) - ,.num_banks_p (num_banks_p ) - ,.data_width_p (data_width_p ) - ,.addr_width_p (addr_width_p ) - ,.num_tiles_x_p (num_tiles_x_p ) - ,.num_tiles_y_p (num_tiles_y_p ) - ,.hetero_type_vec_p(hetero_type_vec_p ) - - ,.stub_w_p ({num_tiles_y_p{1'b0}}) - ,.stub_e_p ({num_tiles_y_p{1'b0}}) - ,.stub_n_p ({num_tiles_x_p{1'b0}}) - // south side is unstubbed. - ,.stub_s_p ({num_tiles_x_p{1'b0}}) - ,.debug_p(debug_p) - ,.extra_io_rows_p ( extra_io_rows_p ) - ,.repeater_output_p( repeater_output_p ) - ) UUT - ( .clk_i (manycore_clk_i ) - //We only sent the synchronized but not registered reset into manycore. - //As the manycore will distribute across large area, it will take long - //time for the reset signal to propgate. - //Each tile should register the reset inside itself - ,.reset_i (MC_reset_n ) - - ,.hor_link_sif_i(MC_hor_link_li) - ,.hor_link_sif_o(MC_hor_link_lo) - - ,.ver_link_sif_i(MC_ver_link_li) - ,.ver_link_sif_o(MC_ver_link_lo) - - ); - - ///////////////////////////////////////////////////////////////////////////////// - // tie off West and North side; which is inaccessible - genvar i; - for (i = 0; i < num_tiles_y_p; i=i+1) - begin: rof2 - bsg_manycore_link_sif_tieoff #(.addr_width_p (addr_width_p ) - ,.data_width_p (data_width_p ) - ,.x_cord_width_p(x_cord_width_lp) - ,.y_cord_width_p(y_cord_width_lp) - ) bmlst - (.clk_i(manycore_clk_i) - ,.reset_i(MC_reset_r) - ,.link_sif_i(MC_hor_link_lo[W][i]) - ,.link_sif_o(MC_hor_link_li[W][i]) - ); - - bsg_manycore_link_sif_tieoff #(.addr_width_p (addr_width_p ) - ,.data_width_p (data_width_p ) - ,.x_cord_width_p(x_cord_width_lp) - ,.y_cord_width_p(y_cord_width_lp) - ) bmlst2 - (.clk_i(manycore_clk_i) - ,.reset_i(MC_reset_r) - ,.link_sif_i(MC_hor_link_lo[E][i]) - ,.link_sif_o(MC_hor_link_li[E][i]) - ); - end - - - // tie off north side; which is inaccessible - for (i = 0; i < num_tiles_x_p; i=i+1) - begin: rof - bsg_manycore_link_sif_tieoff #(.addr_width_p (addr_width_p) - ,.data_width_p (data_width_p) - ,.x_cord_width_p(x_cord_width_lp) - ,.y_cord_width_p(y_cord_width_lp) - ) bmlst3 - (.clk_i(manycore_clk_i) - ,.reset_i(MC_reset_r) - ,.link_sif_i(MC_ver_link_lo[N][i]) - ,.link_sif_o(MC_ver_link_li[N][i]) - ); - end - ///////////////////////////////////////////////////////////////////////////////// - // Instantiate the RoCC & out_fifo interface - wire [out_fifo_num_p-1:0] [bsg_manycore_link_sif_width_lp-1:0] out_fifo_link_sif_li ; - wire [out_fifo_num_p-1:0] [bsg_manycore_link_sif_width_lp-1:0] out_fifo_link_sif_lo ; - wire [out_fifo_num_p-1:0] [x_cord_width_lp-1:0] out_fifo_x_cord ; - wire [out_fifo_num_p-1:0] [y_cord_width_lp-1:0] out_fifo_y_cord ; - - localparam rocc_index_limit_lp = num_tiles_x_p ; - genvar io_ind; - for( io_ind=0; io_ind < rocc_index_limit_lp; io_ind ++) begin: rocc_out_fifo_inst - if( `GET_HEX(rocc_dist_vec_p, io_ind) != 0 ) begin: rocc_inst_real - - bsg_manycore_link_sif_s RC_rocc_link_input, RC_rocc_link_output; - bsg_manycore_link_sif_async_buffer - #( .addr_width_p (addr_width_p) - ,.data_width_p (data_width_p) - ,.x_cord_width_p(x_cord_width_lp) - ,.y_cord_width_p(y_cord_width_lp) - ,.fifo_els_p (async_fifo_els_p) - )manycore_rocc_async_buffer( - .L_clk_i ( manycore_clk_i ) - ,.L_reset_i ( MC_reset_r ) - ,.L_link_sif_i( MC_ver_link_lo[S][ io_ind ]) - ,.L_link_sif_o( MC_ver_link_li[S][ io_ind ]) - - ,.R_clk_i ( clk_i ) - ,.R_reset_i ( reset_i [`GET_HEX_MIN_1(rocc_dist_vec_p, io_ind) ] ) - ,.R_link_sif_i( RC_rocc_link_output ) - ,.R_link_sif_o( RC_rocc_link_input ) - ); - - bsg_manycore_link_to_rocc - #( .addr_width_p (addr_width_p ) - , .data_width_p (data_width_p ) - , .x_cord_width_p(x_cord_width_lp ) - , .y_cord_width_p(y_cord_width_lp ) - ) rocc ( - .my_x_i( x_cord_width_lp'(io_ind ) ) - ,.my_y_i( y_cord_width_lp'(num_tiles_y_p) ) - - ,.link_sif_i ( RC_rocc_link_input ) - ,.link_sif_o ( RC_rocc_link_output ) - - ,.rocket_clk_i ( clk_i ) - ,.rocket_reset_i( reset_i [`GET_HEX_MIN_1(rocc_dist_vec_p, io_ind) ] ) - - ,.core_status_i (core_status_i [`GET_HEX_MIN_1(rocc_dist_vec_p, io_ind) ] ) - ,.core_exception_i (core_exception_i [`GET_HEX_MIN_1(rocc_dist_vec_p, io_ind) ] ) - ,.acc_interrupt_o (acc_interrupt_o [`GET_HEX_MIN_1(rocc_dist_vec_p, io_ind) ] ) - ,.acc_busy_o (acc_busy_o [`GET_HEX_MIN_1(rocc_dist_vec_p, io_ind) ] ) - - ,.core_cmd_valid_i (core_cmd_valid_i [`GET_HEX_MIN_1(rocc_dist_vec_p, io_ind) ] ) - ,.core_cmd_s_i (core_cmd_s_i [`GET_HEX_MIN_1(rocc_dist_vec_p, io_ind) ] ) - ,.core_cmd_ready_o (core_cmd_ready_o [`GET_HEX_MIN_1(rocc_dist_vec_p, io_ind) ] ) - - ,.core_resp_valid_o (core_resp_valid_o[`GET_HEX_MIN_1(rocc_dist_vec_p, io_ind) ] ) - ,.core_resp_s_o (core_resp_s_o [`GET_HEX_MIN_1(rocc_dist_vec_p, io_ind) ] ) - ,.core_resp_ready_i (core_resp_ready_i[`GET_HEX_MIN_1(rocc_dist_vec_p, io_ind) ] ) - - ,.mem_req_valid_o (mem_req_valid_o [`GET_HEX_MIN_1(rocc_dist_vec_p, io_ind) ] ) - ,.mem_req_s_o (mem_req_s_o [`GET_HEX_MIN_1(rocc_dist_vec_p, io_ind) ] ) - ,.mem_req_ready_i (mem_req_ready_i [`GET_HEX_MIN_1(rocc_dist_vec_p, io_ind) ] ) - - ,.mem_resp_valid_i (mem_resp_valid_i [`GET_HEX_MIN_1(rocc_dist_vec_p, io_ind) ] ) - ,.mem_resp_s_i (mem_resp_s_i [`GET_HEX_MIN_1(rocc_dist_vec_p, io_ind) ] ) - - ,.reset_manycore_r_o (RC_rocc_output_reset[`GET_HEX_MIN_1(rocc_dist_vec_p, io_ind) ] ) - ); - //---------------------------------------------------- - //Check if we need to instantiate out_fifo interface - end else if( `GET_HEX(out_fifo_dist_vec_p, io_ind) != 0 ) begin: out_fifo_inst_real - - bsg_manycore_link_sif_async_buffer - #( .addr_width_p (addr_width_p) - ,.data_width_p (data_width_p) - ,.x_cord_width_p(x_cord_width_lp) - ,.y_cord_width_p(y_cord_width_lp) - ,.fifo_els_p (async_fifo_els_p) - )manycore_out_fifo_async_buffer( - .L_clk_i ( manycore_clk_i ) - ,.L_reset_i ( MC_reset_r ) - ,.L_link_sif_i( MC_ver_link_lo[S][ io_ind ]) - ,.L_link_sif_o( MC_ver_link_li[S][ io_ind ]) - - ,.R_clk_i ( clk_i ) - //This FIFO will be reseted as Manycore is reseted. - ,.R_reset_i ( RC_reset_n ) - ,.R_link_sif_i( out_fifo_link_sif_lo [ `GET_HEX_MIN_1(out_fifo_dist_vec_p, io_ind) ] ) - ,.R_link_sif_o( out_fifo_link_sif_li [ `GET_HEX_MIN_1(out_fifo_dist_vec_p, io_ind) ] ) - ); - - assign out_fifo_x_cord [ `GET_HEX_MIN_1(out_fifo_dist_vec_p, io_ind) ] = x_cord_width_lp'(io_ind ); - assign out_fifo_y_cord [ `GET_HEX_MIN_1(out_fifo_dist_vec_p, io_ind) ] = y_cord_width_lp'(num_tiles_y_p); - //---------------------------------------------------- - //otherwise tieoff - end else begin: rocc_inst_tieoff - bsg_manycore_link_sif_tieoff #(.addr_width_p (addr_width_p) - ,.data_width_p (data_width_p) - ,.x_cord_width_p(x_cord_width_lp) - ,.y_cord_width_p(y_cord_width_lp) - ) bmlst4 - ( .clk_i(manycore_clk_i) - ,.reset_i(MC_reset_r) - ,.link_sif_i(MC_ver_link_lo[S][ io_ind ]) - ,.link_sif_o(MC_ver_link_li[S][ io_ind ]) - ); - end:rocc_inst_tieoff - end:rocc_out_fifo_inst - ///////////////////////////////////////////////////////////////////////////////// - // instantiate the link_to_fifo - bsg_manycore_link_to_fifo #( - .addr_width_p ( addr_width_p ) - ,.data_width_p ( data_width_p ) - ,.x_cord_width_p ( x_cord_width_lp ) - ,.y_cord_width_p ( y_cord_width_lp ) - - //The output fifo width must be multiple times of data_width_p - , .out_fifo_width_scale_p ( out_fifo_width_scale_p ) - //multiple channel are merged to increase the output bandwidth - , .in_channel_scale_p ( out_fifo_in_channel_num_lp ) - )link_to_fifo_inst - ( - //this will work under rocket clock domain - .clk_i ( clk_i ) - //This FIFO will be reseted as Manycore is reseted. - , .reset_i ( RC_reset_n ) - - , .my_x_i ( out_fifo_x_cord) - , .my_y_i ( out_fifo_y_cord) - - //input from the manycore, in the same clock domain with the FIFO - , .link_sif_i( out_fifo_link_sif_li ) - , .link_sif_o( out_fifo_link_sif_lo ) - - //FIFO output - , .v_o ( v_o ) - , .data_o ( data_o ) - , .ready_i ( ready_i ) - ); - - ///////////////////////////////////////////////////////////////////////////////// - // parameter check - // synopsys translate_off - int rocc_index = 0; - int k=0; - initial begin - assert( rocc_num_p <= num_tiles_x_p ) - else $error(" rocc_num_p must less or equal num_tiles_x_p"); - - //validate the rocc_dis_vec_p - for( k = 0; k< num_tiles_x_p; k++) begin - if( `GET_HEX(rocc_dist_vec_p, k) != 4'h0 ) begin - rocc_index++; - assert( rocc_index == `GET_HEX(rocc_dist_vec_p,k) ) - else begin - $error(" the rocc index must inrease one by one "); - $finish(); - end - end - end - //if( rocc_num_p != 0 ) begin - // assert ( rocc_num_p == rocc_index ) - // else begin - // $display(" rocc_dist_vec_p = %h ", rocc_dist_vec_p ); - // $error("the rocc_num_p(%d) must match the maximum rocc index(%d)", rocc_num_p, rocc_index); - // $finish(); - // end - //end - end - // synopsys translate_on -endmodule - -`BSG_ABSTRACT_MODULE(bsg_manycore_rocc_streambuf_wrapper) diff --git a/v/bsg_manycore_rocc_wrapper.v b/v/bsg_manycore_rocc_wrapper.v deleted file mode 100644 index b55a83385..000000000 --- a/v/bsg_manycore_rocc_wrapper.v +++ /dev/null @@ -1,309 +0,0 @@ -//==================================================================== -// bsg_manycore_rocc_wrapper.v -// 01/21/2016, shawnless.xie@gmail.com -//==================================================================== -// This module wrapper the bsg_manycore with RoCC interface -// The RoCC distributed at the south of the manycore. -// ******* ID of each RoCC is (num_tiles_y, x) -// ******* NUMBER of RoCC IS LIMITED to 8 -// -// Pleas contact Prof Taylor for the document. -// -`include "bsg_defines.v" -`include "bsg_manycore_packet.vh" -`include "bsg_rocc.v" - -module bsg_manycore_rocc_wrapper - import bsg_noc_pkg ::*; // {P=0, W, E, N, S} - #( - ////////////////////////////////////////////////////// - //Parameters for RoCC interface - `BSG_INV_PARAM( rocc_num_p ) - //The distribution of the rocc interface. - //1. Non-zero value is the index of the rocc interface, - // starting from 1. - //2. for example, {32'h0000_2010} - // indicates there are two rocc interface, their x_cords are 1 and 3. - //3. rocc_num_p must not bigger than tiles_x - ,parameter rocc_dist_vec_p = 0 - - ////////////////////////////////////////////////////// - //Parameters for manycore - // tile params - ,`BSG_INV_PARAM(bank_size_p ) - ,`BSG_INV_PARAM(num_banks_p ) - ,`BSG_INV_PARAM(imem_size_p ) // in words - - // array params - ,parameter num_tiles_x_p = -1 - ,parameter num_tiles_y_p = -1 - - ,parameter hetero_type_vec_p = 0 - // enable debugging - ,parameter debug_p = 0 - ,parameter extra_io_rows_p = 1 - ,`BSG_INV_PARAM(addr_width_p ) - - ,parameter x_cord_width_lp = `BSG_SAFE_CLOG2(num_tiles_x_p) - ,parameter y_cord_width_lp = `BSG_SAFE_CLOG2(num_tiles_y_p + extra_io_rows_p) // extra row for I/O at bottom of chip - - // changing this parameter is untested - ,parameter data_width_p = 32 - - ,parameter load_id_width_p = 5 - ,parameter bsg_manycore_link_sif_width_lp = `bsg_manycore_link_sif_width(addr_width_p,data_width_p,x_cord_width_lp,y_cord_width_lp,load_id_width_p) - // snew * y * x bits - ,parameter repeater_output_p = 0 - - ) - ( input clk_i - ,input manycore_clk_i - ,input [rocc_num_p-1:0] reset_i - - //core control signals - , input [rocc_num_p-1:0] core_status_i - , input [rocc_num_p-1:0] core_exception_i - , output [rocc_num_p-1:0] acc_interrupt_o - , output [rocc_num_p-1:0] acc_busy_o - //command signals - , input [rocc_num_p-1:0] core_cmd_valid_i - , input rocc_core_cmd_s [rocc_num_p-1:0] core_cmd_s_i - , output [rocc_num_p-1:0] core_cmd_ready_o - - , output [rocc_num_p-1:0] core_resp_valid_o - , output rocc_core_resp_s [rocc_num_p-1:0] core_resp_s_o - , input [rocc_num_p-1:0] core_resp_ready_i - //mem signals - , output [rocc_num_p-1:0] mem_req_valid_o - , output rocc_mem_req_s [rocc_num_p-1:0] mem_req_s_o - , input [rocc_num_p-1:0] mem_req_ready_i - - , input [rocc_num_p-1:0] mem_resp_valid_i - , input rocc_mem_resp_s [rocc_num_p-1:0] mem_resp_s_i - ); - - //get one byte from the parameter p - `define GET_HEX(p, ind) ( (p >> (ind* 4)) & 4'hF ) - `define GET_HEX_MIN_1(p, ind) ( `GET_HEX(p,ind) - 4'h1 ) - - //declare the interface to the bsg_manycore - `declare_bsg_manycore_link_sif_s(addr_width_p, data_width_p, x_cord_width_lp, y_cord_width_lp, load_id_width_p); - - bsg_manycore_link_sif_s [S:N][num_tiles_x_p-1:0] MC_ver_link_li, MC_ver_link_lo; - bsg_manycore_link_sif_s [E:W][num_tiles_y_p-1:0] MC_hor_link_li, MC_hor_link_lo; - - - - //generate the reset signal into the manycore - //1. if all rocket are in reset status, the manycore are all reseted. - //2. if any rocket is dis-reseted, the manycore reset is the reset signal - // from the rocc interface, which is reset command from rocket core. - wire RC_all_rocket_reset = & reset_i ; - wire [rocc_num_p-1:0] RC_rocc_output_reset ; - - wire RC_reset_n = RC_all_rocket_reset | ( | RC_rocc_output_reset ) ; - - - wire MC_reset_n; - bsg_launch_sync_sync#(.width_p (1) )manycore_reset_sync( - . iclk_i ( clk_i ) - ,. iclk_reset_i ( 1'b0 ) - ,. oclk_i ( manycore_clk_i) - ,. iclk_data_i ( RC_reset_n ) - ,. iclk_data_o ( ) - ,. oclk_data_o ( MC_reset_n) - ); - - logic MC_reset_r; - always_ff@(posedge manycore_clk_i) MC_reset_r <= MC_reset_n; - - //instantiate the manycore - bsg_manycore # ( - .bank_size_p (bank_size_p ) - ,.imem_size_p (imem_size_p ) - ,.num_banks_p (num_banks_p ) - ,.data_width_p (data_width_p ) - ,.addr_width_p (addr_width_p ) - ,.num_tiles_x_p (num_tiles_x_p ) - ,.num_tiles_y_p (num_tiles_y_p ) - ,.hetero_type_vec_p(hetero_type_vec_p ) - - ,.stub_w_p ({num_tiles_y_p{1'b0}}) - ,.stub_e_p ({num_tiles_y_p{1'b0}}) - ,.stub_n_p ({num_tiles_x_p{1'b0}}) - // south side is unstubbed. - ,.stub_s_p ({num_tiles_x_p{1'b0}}) - ,.debug_p(debug_p) - ,.extra_io_rows_p ( extra_io_rows_p ) - ,.repeater_output_p( repeater_output_p ) - ) UUT - ( .clk_i (manycore_clk_i ) - //We only sent the synchronized but not registered reset into manycore. - //As the manycore will distribute across large area, it will take long - //time for the reset signal to propgate. - //Each tile should register the reset inside itself - ,.reset_i (MC_reset_n ) - - ,.hor_link_sif_i(MC_hor_link_li) - ,.hor_link_sif_o(MC_hor_link_lo) - - ,.ver_link_sif_i(MC_ver_link_li) - ,.ver_link_sif_o(MC_ver_link_lo) - - ); - - ///////////////////////////////////////////////////////////////////////////////// - // tie off West and North side; which is inaccessible - genvar i; - for (i = 0; i < num_tiles_y_p; i=i+1) - begin: rof2 - bsg_manycore_link_sif_tieoff #(.addr_width_p (addr_width_p ) - ,.data_width_p (data_width_p ) - ,.x_cord_width_p(x_cord_width_lp) - ,.y_cord_width_p(y_cord_width_lp) - ) bmlst - (.clk_i(manycore_clk_i) - ,.reset_i(MC_reset_r) - ,.link_sif_i(MC_hor_link_lo[W][i]) - ,.link_sif_o(MC_hor_link_li[W][i]) - ); - - bsg_manycore_link_sif_tieoff #(.addr_width_p (addr_width_p ) - ,.data_width_p (data_width_p ) - ,.x_cord_width_p(x_cord_width_lp) - ,.y_cord_width_p(y_cord_width_lp) - ) bmlst2 - (.clk_i(manycore_clk_i) - ,.reset_i(MC_reset_r) - ,.link_sif_i(MC_hor_link_lo[E][i]) - ,.link_sif_o(MC_hor_link_li[E][i]) - ); - end - - - // tie off north side; which is inaccessible - for (i = 0; i < num_tiles_x_p; i=i+1) - begin: rof - bsg_manycore_link_sif_tieoff #(.addr_width_p (addr_width_p) - ,.data_width_p (data_width_p) - ,.x_cord_width_p(x_cord_width_lp) - ,.y_cord_width_p(y_cord_width_lp) - ) bmlst3 - (.clk_i(manycore_clk_i) - ,.reset_i(MC_reset_r) - ,.link_sif_i(MC_ver_link_lo[N][i]) - ,.link_sif_o(MC_ver_link_li[N][i]) - ); - end - ///////////////////////////////////////////////////////////////////////////////// - // Instantiate the RoCC interface - localparam rocc_index_limit_lp = num_tiles_x_p ; - - genvar io_ind; - for( io_ind=0; io_ind < rocc_index_limit_lp; io_ind ++) begin: rocc_inst - if( `GET_HEX(rocc_dist_vec_p, io_ind) != 0 ) begin: rocc_inst_real - - bsg_manycore_link_sif_s RC_rocc_link_input, RC_rocc_link_output; - bsg_manycore_link_sif_async_buffer - #( .addr_width_p (addr_width_p) - ,.data_width_p (data_width_p) - ,.x_cord_width_p(x_cord_width_lp) - ,.y_cord_width_p(y_cord_width_lp) - ,.fifo_els_p (4) - )manycore_rocc_async_buffer( - .L_clk_i ( manycore_clk_i ) - ,.L_reset_i ( MC_reset_r ) - ,.L_link_sif_i( MC_ver_link_lo[S][ io_ind ]) - ,.L_link_sif_o( MC_ver_link_li[S][ io_ind ]) - - ,.R_clk_i ( clk_i ) - ,.R_reset_i ( reset_i [`GET_HEX_MIN_1(rocc_dist_vec_p, io_ind) ] ) - ,.R_link_sif_i( RC_rocc_link_output ) - ,.R_link_sif_o( RC_rocc_link_input ) - ); - - bsg_manycore_link_to_rocc - #( .addr_width_p (addr_width_p ) - , .data_width_p (data_width_p ) - , .x_cord_width_p(x_cord_width_lp ) - , .y_cord_width_p(y_cord_width_lp ) - ) rocc ( - .my_x_i( x_cord_width_lp'(io_ind ) ) - ,.my_y_i( y_cord_width_lp'(num_tiles_y_p) ) - - ,.link_sif_i ( RC_rocc_link_input ) - ,.link_sif_o ( RC_rocc_link_output ) - - ,.rocket_clk_i ( clk_i ) - ,.rocket_reset_i( reset_i [`GET_HEX_MIN_1(rocc_dist_vec_p, io_ind) ] ) - - ,.core_status_i (core_status_i [`GET_HEX_MIN_1(rocc_dist_vec_p, io_ind) ] ) - ,.core_exception_i (core_exception_i [`GET_HEX_MIN_1(rocc_dist_vec_p, io_ind) ] ) - ,.acc_interrupt_o (acc_interrupt_o [`GET_HEX_MIN_1(rocc_dist_vec_p, io_ind) ] ) - ,.acc_busy_o (acc_busy_o [`GET_HEX_MIN_1(rocc_dist_vec_p, io_ind) ] ) - - ,.core_cmd_valid_i (core_cmd_valid_i [`GET_HEX_MIN_1(rocc_dist_vec_p, io_ind) ] ) - ,.core_cmd_s_i (core_cmd_s_i [`GET_HEX_MIN_1(rocc_dist_vec_p, io_ind) ] ) - ,.core_cmd_ready_o (core_cmd_ready_o [`GET_HEX_MIN_1(rocc_dist_vec_p, io_ind) ] ) - - ,.core_resp_valid_o (core_resp_valid_o[`GET_HEX_MIN_1(rocc_dist_vec_p, io_ind) ] ) - ,.core_resp_s_o (core_resp_s_o [`GET_HEX_MIN_1(rocc_dist_vec_p, io_ind) ] ) - ,.core_resp_ready_i (core_resp_ready_i[`GET_HEX_MIN_1(rocc_dist_vec_p, io_ind) ] ) - - ,.mem_req_valid_o (mem_req_valid_o [`GET_HEX_MIN_1(rocc_dist_vec_p, io_ind) ] ) - ,.mem_req_s_o (mem_req_s_o [`GET_HEX_MIN_1(rocc_dist_vec_p, io_ind) ] ) - ,.mem_req_ready_i (mem_req_ready_i [`GET_HEX_MIN_1(rocc_dist_vec_p, io_ind) ] ) - - ,.mem_resp_valid_i (mem_resp_valid_i [`GET_HEX_MIN_1(rocc_dist_vec_p, io_ind) ] ) - ,.mem_resp_s_i (mem_resp_s_i [`GET_HEX_MIN_1(rocc_dist_vec_p, io_ind) ] ) - - ,.reset_manycore_r_o (RC_rocc_output_reset[`GET_HEX_MIN_1(rocc_dist_vec_p, io_ind) ] ) - ); - //otherwise tieoff - end else begin: rocc_inst_tieoff - bsg_manycore_link_sif_tieoff #(.addr_width_p (addr_width_p) - ,.data_width_p (data_width_p) - ,.x_cord_width_p(x_cord_width_lp) - ,.y_cord_width_p(y_cord_width_lp) - ) bmlst4 - ( .clk_i(manycore_clk_i) - ,.reset_i(MC_reset_r) - ,.link_sif_i(MC_ver_link_lo[S][ io_ind ]) - ,.link_sif_o(MC_ver_link_li[S][ io_ind ]) - ); - end:rocc_inst_tieoff - end:rocc_inst - - ///////////////////////////////////////////////////////////////////////////////// - // parameter check - // synopsys translate_off - int rocc_index = 0; - int k=0; - initial begin - assert( rocc_num_p <= num_tiles_x_p ) - else $error(" rocc_num_p must less or equal num_tiles_x_p"); - - //validate the rocc_dis_vec_p - for( k = 0; k< num_tiles_x_p; k++) begin - if( `GET_HEX(rocc_dist_vec_p, k) != 4'h0 ) begin - rocc_index++; - assert( rocc_index == `GET_HEX(rocc_dist_vec_p,k) ) - else begin - $error(" the rocc index must inrease one by one "); - $finish(); - end - end - end - //if( rocc_num_p != 0 ) begin - // assert ( rocc_num_p == rocc_index ) - // else begin - // $display(" rocc_dist_vec_p = %h ", rocc_dist_vec_p ); - // $error("the rocc_num_p(%d) must match the maximum rocc index(%d)", rocc_num_p, rocc_index); - // $finish(); - // end - //end - end - // synopsys translate_on -endmodule - -`BSG_ABSTRACT_MODULE(bsg_manycore_rocc_wrapper) diff --git a/v/bsg_ruche_anti_buffer.v b/v/bsg_ruche_anti_buffer.v deleted file mode 100644 index eecff71e1..000000000 --- a/v/bsg_ruche_anti_buffer.v +++ /dev/null @@ -1,72 +0,0 @@ -/** - * bsg_ruche_anti_buffer.v - * - * used at the end of the ruche link, to bring all the buses to the positive polarity before making connection to other modules - * such as wormhole concentrators. - */ - -`include "bsg_defines.v" - -module bsg_ruche_anti_buffer - #(`BSG_INV_PARAM(width_p) - - , `BSG_INV_PARAM(ruche_factor_p ) - , `BSG_INV_PARAM(ruche_stage_p ) - , `BSG_INV_PARAM(bit west_not_east_p) - , `BSG_INV_PARAM(bit input_not_output_p) - - , parameter bit ruche_factor_even_lp = (ruche_factor_p % 2 == 0) - , parameter bit ruche_stage_even_lp = (ruche_stage_p % 2 == 0) - - , parameter bit invert_input_lp = (ruche_stage_p > 0) - & (ruche_factor_even_lp - ? ~ruche_stage_even_lp - : (west_not_east_p - ? ruche_stage_even_lp - : ~ruche_stage_even_lp)) - , parameter bit invert_output_lp = (ruche_stage_p > 0) - & (ruche_factor_even_lp - ? ~ruche_stage_even_lp - : (west_not_east_p - ? ~ruche_stage_even_lp - : ruche_stage_even_lp)) - - , parameter bit invert_lp = input_not_output_p - ? invert_input_lp - : invert_output_lp - - , parameter harden_p=1 - ) - ( - input [width_p-1:0] i - , output [width_p-1:0] o - ); - - - if (invert_lp) begin: inv - - bsg_inv #( - .width_p(width_p) - ,.harden_p(harden_p) - ) inv0 ( - .i(i) - ,.o(o) - ); - - end - else begin: bf - - bsg_buf #( - .width_p(width_p) - ,.harden_p(harden_p) - ) buf0 ( - .i(i) - ,.o(o) - ); - - end - - -endmodule - -`BSG_ABSTRACT_MODULE(bsg_ruche_anti_buffer)