From 63ff81e5bdd206f650a81ae2fa7fddec8d1c5c31 Mon Sep 17 00:00:00 2001 From: Dan Petrisko Date: Tue, 30 Nov 2021 09:05:53 -0800 Subject: [PATCH] Replacing parameters with localparams (#606) * parameter->localparam * Adding parameter to localparam inference * Minor adjustments * Purging unnecessary keywords * Reverting changes --- v/bsg_cache_dma_to_wormhole.v | 6 ++-- v/bsg_manycore_accel_default.v | 22 +++++++------- v/bsg_manycore_endpoint.v | 8 +++--- v/bsg_manycore_endpoint_fc.v | 16 +++++------ v/bsg_manycore_endpoint_standard.v | 16 +++++------ v/bsg_manycore_eva_to_npa.v | 6 ++-- v/bsg_manycore_gather_scatter.v | 22 +++++++------- v/bsg_manycore_hetero_socket.v | 14 ++++----- v/bsg_manycore_hor_io_router.v | 14 ++++----- v/bsg_manycore_hor_io_router_column.v | 4 +-- v/bsg_manycore_link_async_to_wormhole.v | 12 ++++---- v/bsg_manycore_link_sif_async_buffer.v | 6 ++-- v/bsg_manycore_link_sif_tieoff.v | 2 +- v/bsg_manycore_link_to_cache.v | 24 ++++++++-------- v/bsg_manycore_link_to_cache_non_blocking.v | 12 ++++---- v/bsg_manycore_link_to_fifo.v | 14 ++++----- v/bsg_manycore_mesh_node.v | 22 +++++++------- v/bsg_manycore_pod_ruche.v | 18 ++++++------ v/bsg_manycore_pod_ruche_array.v | 24 ++++++++-------- v/bsg_manycore_pod_ruche_row.v | 22 +++++++------- v/bsg_manycore_reg_id_decode.v | 2 +- v/bsg_manycore_reg_id_encode.v | 2 +- v/bsg_manycore_ruche_x_link_sif_tieoff.v | 14 ++++----- v/bsg_manycore_tile_compute_array_mesh.v | 14 ++++----- v/bsg_manycore_tile_compute_array_ruche.v | 32 ++++++++++----------- v/bsg_manycore_tile_compute_mesh.v | 14 ++++----- v/bsg_manycore_tile_compute_ruche.v | 24 ++++++++-------- v/bsg_manycore_tile_vcache.v | 10 +++---- v/bsg_manycore_tile_vcache_array.v | 12 ++++---- v/bsg_manycore_vcache_blocking.v | 8 +++--- v/bsg_manycore_vcache_non_blocking.v | 8 +++--- v/bsg_ruche_buffer.v | 2 +- v/bsg_ruche_link_sif_tieoff.v | 10 +++---- v/vanilla_bean/bsg_cache_to_axi_hashed.v | 14 ++++----- v/vanilla_bean/bsg_manycore_proc_vanilla.v | 28 +++++++++--------- v/vanilla_bean/fcsr.v | 6 ++-- v/vanilla_bean/fpu_fdiv_fsqrt.v | 8 +++--- v/vanilla_bean/fpu_float.v | 8 +++--- v/vanilla_bean/fpu_float_aux.v | 6 ++-- v/vanilla_bean/fpu_float_fma.v | 6 ++-- v/vanilla_bean/fpu_float_fma_round.v | 4 +-- v/vanilla_bean/fpu_fmin_fmax.v | 2 +- v/vanilla_bean/fpu_int.v | 6 ++-- v/vanilla_bean/fpu_int_fclass.v | 4 +-- v/vanilla_bean/hash_function_reverse.v | 4 +-- v/vanilla_bean/icache.v | 4 +-- v/vanilla_bean/idiv.v | 4 +-- v/vanilla_bean/load_packer.v | 2 +- v/vanilla_bean/lsu.v | 4 +-- v/vanilla_bean/mcsr.v | 12 ++++---- v/vanilla_bean/network_rx.v | 8 +++--- v/vanilla_bean/network_tx.v | 18 ++++++------ v/vanilla_bean/regfile.v | 4 +-- v/vanilla_bean/regfile_hard.v | 2 +- v/vanilla_bean/regfile_synth.v | 2 +- v/vanilla_bean/scoreboard.v | 8 +++--- v/vanilla_bean/vanilla_core.v | 14 ++++----- 57 files changed, 307 insertions(+), 307 deletions(-) diff --git a/v/bsg_cache_dma_to_wormhole.v b/v/bsg_cache_dma_to_wormhole.v index 6015c71c3..26a64bb07 100644 --- a/v/bsg_cache_dma_to_wormhole.v +++ b/v/bsg_cache_dma_to_wormhole.v @@ -24,10 +24,10 @@ module bsg_cache_dma_to_wormhole , `BSG_INV_PARAM(wh_len_width_p) , `BSG_INV_PARAM(wh_cord_width_p) - , parameter data_len_lp = (vcache_data_width_p*vcache_block_size_in_words_p/vcache_dma_data_width_p) + , localparam data_len_lp = (vcache_data_width_p*vcache_block_size_in_words_p/vcache_dma_data_width_p) - , parameter dma_pkt_width_lp=`bsg_cache_dma_pkt_width(vcache_addr_width_p) - , parameter wh_link_sif_width_lp = + , dma_pkt_width_lp=`bsg_cache_dma_pkt_width(vcache_addr_width_p) + , wh_link_sif_width_lp = `bsg_ready_and_link_sif_width(wh_flit_width_p) ) ( diff --git a/v/bsg_manycore_accel_default.v b/v/bsg_manycore_accel_default.v index 2d0a930b1..b736ce41e 100644 --- a/v/bsg_manycore_accel_default.v +++ b/v/bsg_manycore_accel_default.v @@ -8,7 +8,7 @@ module bsg_manycore_accel_default , `BSG_INV_PARAM(y_cord_width_p ) , `BSG_INV_PARAM(pod_x_cord_width_p ) , `BSG_INV_PARAM(pod_y_cord_width_p ) - , parameter data_width_p = 32 + , `BSG_INV_PARAM(data_width_p ) , `BSG_INV_PARAM(addr_width_p ) , `BSG_INV_PARAM(icache_entries_p ) @@ -23,23 +23,23 @@ module bsg_manycore_accel_default , `BSG_INV_PARAM(num_tiles_x_p ) , `BSG_INV_PARAM(num_tiles_y_p ) - , parameter x_subcord_width_lp = `BSG_SAFE_CLOG2(num_tiles_x_p) - , parameter y_subcord_width_lp = `BSG_SAFE_CLOG2(num_tiles_y_p) + , localparam x_subcord_width_lp = `BSG_SAFE_CLOG2(num_tiles_x_p) + , y_subcord_width_lp = `BSG_SAFE_CLOG2(num_tiles_y_p) , `BSG_INV_PARAM(rev_fifo_els_p) // for FIFO credit counting. , `BSG_INV_PARAM(fwd_fifo_els_p) // for FIFO credit counting. - , parameter credit_counter_width_lp = `BSG_WIDTH(32) + , localparam credit_counter_width_lp = `BSG_WIDTH(32) , parameter proc_fifo_els_p = 4 - , parameter debug_p = 1 + , debug_p = 1 - , parameter icache_addr_width_lp = `BSG_SAFE_CLOG2(icache_entries_p) - , parameter dmem_addr_width_lp = `BSG_SAFE_CLOG2(dmem_size_p) - , parameter pc_width_lp=(icache_addr_width_lp+icache_tag_width_p) - , parameter data_mask_width_lp=(data_width_p>>3) - , parameter reg_addr_width_lp=RV32_reg_addr_width_gp + , localparam icache_addr_width_lp = `BSG_SAFE_CLOG2(icache_entries_p) + , dmem_addr_width_lp = `BSG_SAFE_CLOG2(dmem_size_p) + , pc_width_lp=(icache_addr_width_lp+icache_tag_width_p) + , data_mask_width_lp=(data_width_p>>3) + , reg_addr_width_lp=RV32_reg_addr_width_gp - , parameter link_sif_width_lp = + , link_sif_width_lp = `bsg_manycore_link_sif_width(addr_width_p,data_width_p,x_cord_width_p,y_cord_width_p) ) diff --git a/v/bsg_manycore_endpoint.v b/v/bsg_manycore_endpoint.v index 7bd4e1ab7..4af9bad26 100644 --- a/v/bsg_manycore_endpoint.v +++ b/v/bsg_manycore_endpoint.v @@ -10,14 +10,14 @@ module bsg_manycore_endpoint #(`BSG_INV_PARAM(x_cord_width_p ) , `BSG_INV_PARAM(y_cord_width_p ) , `BSG_INV_PARAM(fifo_els_p ) - , parameter data_width_p = 32 + , `BSG_INV_PARAM(data_width_p ) , `BSG_INV_PARAM(addr_width_p ) - , parameter packet_width_lp = + , localparam packet_width_lp = `bsg_manycore_packet_width(addr_width_p,data_width_p,x_cord_width_p,y_cord_width_p) - , parameter return_packet_width_lp = + , return_packet_width_lp = `bsg_manycore_return_packet_width(x_cord_width_p,y_cord_width_p,data_width_p) - , parameter bsg_manycore_link_sif_width_lp = + , bsg_manycore_link_sif_width_lp = `bsg_manycore_link_sif_width(addr_width_p,data_width_p,x_cord_width_p,y_cord_width_p) ) ( diff --git a/v/bsg_manycore_endpoint_fc.v b/v/bsg_manycore_endpoint_fc.v index 33fa6d608..24c730b44 100644 --- a/v/bsg_manycore_endpoint_fc.v +++ b/v/bsg_manycore_endpoint_fc.v @@ -17,24 +17,24 @@ module bsg_manycore_endpoint_fc #(`BSG_INV_PARAM(x_cord_width_p ) , `BSG_INV_PARAM(y_cord_width_p ) , `BSG_INV_PARAM(fifo_els_p ) - , parameter data_width_p = 32 + , `BSG_INV_PARAM(data_width_p ) , `BSG_INV_PARAM(addr_width_p ) - , parameter credit_counter_width_p = `BSG_WIDTH(32) - , parameter warn_out_of_credits_p = 1 + , credit_counter_width_p = `BSG_WIDTH(32) + , warn_out_of_credits_p = 1 // size of outgoing response fifo - , parameter rev_fifo_els_p = 3 - , parameter lg_rev_fifo_els_lp = `BSG_WIDTH(rev_fifo_els_p) + , rev_fifo_els_p = 3 + , localparam lg_rev_fifo_els_lp = `BSG_WIDTH(rev_fifo_els_p) // fwd fifo interface , parameter use_credits_for_local_fifo_p = 0 - , parameter packet_width_lp = + , localparam packet_width_lp = `bsg_manycore_packet_width(addr_width_p,data_width_p,x_cord_width_p,y_cord_width_p) - , parameter return_packet_width_lp = + , return_packet_width_lp = `bsg_manycore_return_packet_width(x_cord_width_p,y_cord_width_p,data_width_p) - , parameter bsg_manycore_link_sif_width_lp = + , bsg_manycore_link_sif_width_lp = `bsg_manycore_link_sif_width(addr_width_p,data_width_p,x_cord_width_p,y_cord_width_p) ) ( diff --git a/v/bsg_manycore_endpoint_standard.v b/v/bsg_manycore_endpoint_standard.v index 6f3bab79e..2b5832846 100644 --- a/v/bsg_manycore_endpoint_standard.v +++ b/v/bsg_manycore_endpoint_standard.v @@ -30,24 +30,24 @@ module bsg_manycore_endpoint_standard #(`BSG_INV_PARAM(x_cord_width_p ) , `BSG_INV_PARAM(y_cord_width_p ) , `BSG_INV_PARAM(fifo_els_p ) - , parameter data_width_p = 32 + , `BSG_INV_PARAM(data_width_p ) , `BSG_INV_PARAM(addr_width_p ) - , parameter credit_counter_width_p = `BSG_WIDTH(32) - , parameter warn_out_of_credits_p = 1 + , credit_counter_width_p = `BSG_WIDTH(32) + , warn_out_of_credits_p = 1 // size of outgoing response fifo - , parameter rev_fifo_els_p = 3 - , parameter lg_rev_fifo_els_lp = `BSG_WIDTH(rev_fifo_els_p) + , rev_fifo_els_p = 3 + , localparam lg_rev_fifo_els_lp = `BSG_WIDTH(rev_fifo_els_p) // fwd fifo interface , parameter use_credits_for_local_fifo_p = 0 - , parameter packet_width_lp = + , localparam packet_width_lp = `bsg_manycore_packet_width(addr_width_p,data_width_p,x_cord_width_p,y_cord_width_p) - , parameter return_packet_width_lp = + , return_packet_width_lp = `bsg_manycore_return_packet_width(x_cord_width_p,y_cord_width_p,data_width_p) - , parameter bsg_manycore_link_sif_width_lp = + , bsg_manycore_link_sif_width_lp = `bsg_manycore_link_sif_width(addr_width_p,data_width_p,x_cord_width_p,y_cord_width_p) ) ( diff --git a/v/bsg_manycore_eva_to_npa.v b/v/bsg_manycore_eva_to_npa.v index 452eed632..e75723483 100644 --- a/v/bsg_manycore_eva_to_npa.v +++ b/v/bsg_manycore_eva_to_npa.v @@ -29,10 +29,10 @@ module bsg_manycore_eva_to_npa , `BSG_INV_PARAM(num_tiles_x_p) , `BSG_INV_PARAM(num_tiles_y_p) - , parameter x_subcord_width_lp=`BSG_SAFE_CLOG2(num_tiles_x_p) - , parameter y_subcord_width_lp=`BSG_SAFE_CLOG2(num_tiles_y_p) + , localparam x_subcord_width_lp=`BSG_SAFE_CLOG2(num_tiles_x_p) + , y_subcord_width_lp=`BSG_SAFE_CLOG2(num_tiles_y_p) - , `BSG_INV_PARAM(num_vcache_rows_p ) + , parameter `BSG_INV_PARAM(num_vcache_rows_p ) , `BSG_INV_PARAM(vcache_block_size_in_words_p) // block size in vcache , `BSG_INV_PARAM(vcache_size_p) // vcache capacity in words , `BSG_INV_PARAM(vcache_sets_p) // number of sets in vcache diff --git a/v/bsg_manycore_gather_scatter.v b/v/bsg_manycore_gather_scatter.v index 7e54392a6..bfb372ca5 100644 --- a/v/bsg_manycore_gather_scatter.v +++ b/v/bsg_manycore_gather_scatter.v @@ -52,23 +52,23 @@ module bsg_manycore_gather_scatter , `BSG_INV_PARAM(num_tiles_x_p ) , `BSG_INV_PARAM(num_tiles_y_p ) - , parameter x_subcord_width_lp = `BSG_SAFE_CLOG2(num_tiles_x_p) - , parameter y_subcord_width_lp = `BSG_SAFE_CLOG2(num_tiles_y_p) + , localparam x_subcord_width_lp = `BSG_SAFE_CLOG2(num_tiles_x_p) + , y_subcord_width_lp = `BSG_SAFE_CLOG2(num_tiles_y_p) - , `BSG_INV_PARAM(rev_fifo_els_p) // for FIFO credit counting. + , parameter `BSG_INV_PARAM(rev_fifo_els_p) // for FIFO credit counting. , `BSG_INV_PARAM(fwd_fifo_els_p) // for FIFO credit counting. - , parameter credit_counter_width_lp = `BSG_WIDTH(32) + , localparam credit_counter_width_lp = `BSG_WIDTH(32) , parameter proc_fifo_els_p = 4 - , parameter debug_p = 1 + , debug_p = 1 - , parameter icache_addr_width_lp = `BSG_SAFE_CLOG2(icache_entries_p) - , parameter dmem_addr_width_lp = `BSG_SAFE_CLOG2(dmem_size_p) - , parameter pc_width_lp=(icache_addr_width_lp+icache_tag_width_p) - , parameter data_mask_width_lp = (data_width_p>>3) - , parameter reg_addr_width_lp=RV32_reg_addr_width_gp + , localparam icache_addr_width_lp = `BSG_SAFE_CLOG2(icache_entries_p) + , dmem_addr_width_lp = `BSG_SAFE_CLOG2(dmem_size_p) + , pc_width_lp=(icache_addr_width_lp+icache_tag_width_p) + , data_mask_width_lp = (data_width_p>>3) + , reg_addr_width_lp=RV32_reg_addr_width_gp - , parameter link_sif_width_lp = + , link_sif_width_lp = `bsg_manycore_link_sif_width(addr_width_p,data_width_p,x_cord_width_p,y_cord_width_p) ) ( diff --git a/v/bsg_manycore_hetero_socket.v b/v/bsg_manycore_hetero_socket.v index 632945cef..c04fe426b 100644 --- a/v/bsg_manycore_hetero_socket.v +++ b/v/bsg_manycore_hetero_socket.v @@ -63,22 +63,22 @@ module bsg_manycore_hetero_socket , `BSG_INV_PARAM(icache_tag_width_p ) , `BSG_INV_PARAM(num_vcache_rows_p ) , `BSG_INV_PARAM(vcache_size_p ) - , parameter debug_p = 0 - , parameter int hetero_type_p = 0 + , debug_p = 0 + , int hetero_type_p = 0 , `BSG_INV_PARAM(pod_x_cord_width_p) , `BSG_INV_PARAM(pod_y_cord_width_p) , `BSG_INV_PARAM(num_tiles_x_p) , `BSG_INV_PARAM(num_tiles_y_p) - , parameter x_subcord_width_lp = `BSG_SAFE_CLOG2(num_tiles_x_p) - , parameter y_subcord_width_lp = `BSG_SAFE_CLOG2(num_tiles_y_p) - , `BSG_INV_PARAM(vcache_block_size_in_words_p) + , localparam x_subcord_width_lp = `BSG_SAFE_CLOG2(num_tiles_x_p) + , y_subcord_width_lp = `BSG_SAFE_CLOG2(num_tiles_y_p) + , parameter `BSG_INV_PARAM(vcache_block_size_in_words_p) , `BSG_INV_PARAM(vcache_sets_p) , `BSG_INV_PARAM(fwd_fifo_els_p ) , `BSG_INV_PARAM(rev_fifo_els_p ) , `BSG_INV_PARAM(barrier_dirs_p ) - , parameter barrier_lg_dirs_lp=`BSG_SAFE_CLOG2(barrier_dirs_p+1) + , localparam barrier_lg_dirs_lp=`BSG_SAFE_CLOG2(barrier_dirs_p+1) - , parameter bsg_manycore_link_sif_width_lp = + , bsg_manycore_link_sif_width_lp = `bsg_manycore_link_sif_width(addr_width_p,data_width_p,x_cord_width_p,y_cord_width_p) ) ( diff --git a/v/bsg_manycore_hor_io_router.v b/v/bsg_manycore_hor_io_router.v index 2d6271e7d..b6ffd281f 100644 --- a/v/bsg_manycore_hor_io_router.v +++ b/v/bsg_manycore_hor_io_router.v @@ -25,18 +25,18 @@ module bsg_manycore_hor_io_router , `BSG_INV_PARAM(tieoff_west_p) , `BSG_INV_PARAM(tieoff_east_p) - , parameter tieoff_proc_p=0 + , tieoff_proc_p=0 - , parameter dims_lp=3 // only support 3 + , localparam dims_lp=3 // only support 3 , parameter fwd_use_credits_p = 7'b0000000 - , parameter int fwd_fifo_els_p[dims_lp*2:0] = '{2,2,2,2,2,2,2} - , parameter rev_use_credits_p = 7'b0000000 - , parameter int rev_fifo_els_p[dims_lp*2:0] = '{2,2,2,2,2,2,2} + , int fwd_fifo_els_p[dims_lp*2:0] = '{2,2,2,2,2,2,2} + , rev_use_credits_p = 7'b0000000 + , int rev_fifo_els_p[dims_lp*2:0] = '{2,2,2,2,2,2,2} - , parameter link_sif_width_lp = + , localparam link_sif_width_lp = `bsg_manycore_link_sif_width(addr_width_p,data_width_p,x_cord_width_p,y_cord_width_p) - , parameter ruche_x_link_sif_width_lp = + , ruche_x_link_sif_width_lp = `bsg_manycore_ruche_x_link_sif_width(addr_width_p,data_width_p,x_cord_width_p,y_cord_width_p) ) ( diff --git a/v/bsg_manycore_hor_io_router_column.v b/v/bsg_manycore_hor_io_router_column.v index ea6835945..5e8f2bf5b 100644 --- a/v/bsg_manycore_hor_io_router_column.v +++ b/v/bsg_manycore_hor_io_router_column.v @@ -21,9 +21,9 @@ module bsg_manycore_hor_io_router_column , `BSG_INV_PARAM(bit [num_row_p-1:0] tieoff_east_p ) - , parameter link_sif_width_lp = + , localparam link_sif_width_lp = `bsg_manycore_link_sif_width(addr_width_p,data_width_p,x_cord_width_p,y_cord_width_p) - , parameter ruche_x_link_sif_width_lp = + , localparam ruche_x_link_sif_width_lp = `bsg_manycore_ruche_x_link_sif_width(addr_width_p,data_width_p,x_cord_width_p,y_cord_width_p) ) ( diff --git a/v/bsg_manycore_link_async_to_wormhole.v b/v/bsg_manycore_link_async_to_wormhole.v index e03aed6f6..3307ba83e 100644 --- a/v/bsg_manycore_link_async_to_wormhole.v +++ b/v/bsg_manycore_link_async_to_wormhole.v @@ -22,18 +22,18 @@ module bsg_manycore_link_async_to_wormhole // Wormhole link parameters ,`BSG_INV_PARAM(flit_width_p ) - ,parameter dims_p = 2 - ,parameter int cord_markers_pos_p[dims_p:0] = '{5, 4, 0} + ,dims_p = 2 + ,int cord_markers_pos_p[dims_p:0] = '{5, 4, 0} ,`BSG_INV_PARAM(len_width_p ) // The number of registers between reset_i and reset sinks. - ,parameter mc_reset_depth_p = 3 + ,mc_reset_depth_p = 3 ,localparam num_nets_lp = 2 - ,localparam bsg_manycore_link_sif_width_lp = `bsg_manycore_link_sif_width(addr_width_p,data_width_p,x_cord_width_p,y_cord_width_p) - ,localparam bsg_ready_and_link_sif_width_lp = `bsg_ready_and_link_sif_width(flit_width_p) + ,bsg_manycore_link_sif_width_lp = `bsg_manycore_link_sif_width(addr_width_p,data_width_p,x_cord_width_p,y_cord_width_p) + ,bsg_ready_and_link_sif_width_lp = `bsg_ready_and_link_sif_width(flit_width_p) - ,localparam cord_width_lp = cord_markers_pos_p[dims_p] + ,cord_width_lp = cord_markers_pos_p[dims_p] ) (// Manycore side diff --git a/v/bsg_manycore_link_sif_async_buffer.v b/v/bsg_manycore_link_sif_async_buffer.v index f1336ab30..948783433 100644 --- a/v/bsg_manycore_link_sif_async_buffer.v +++ b/v/bsg_manycore_link_sif_async_buffer.v @@ -10,12 +10,12 @@ module bsg_manycore_link_sif_async_buffer import bsg_manycore_pkg::*; - #( addr_width_p = 32 - , data_width_p = 32 + #( `BSG_INV_PARAM(addr_width_p ) + , `BSG_INV_PARAM(data_width_p ) , `BSG_INV_PARAM(x_cord_width_p) , `BSG_INV_PARAM(y_cord_width_p) , fifo_els_p = 2 - , bsg_manycore_link_sif_width_lp = `bsg_manycore_link_sif_width(addr_width_p, data_width_p, x_cord_width_p, y_cord_width_p) + , localparam bsg_manycore_link_sif_width_lp = `bsg_manycore_link_sif_width(addr_width_p, data_width_p, x_cord_width_p, y_cord_width_p) )( //the left side signal input L_clk_i diff --git a/v/bsg_manycore_link_sif_tieoff.v b/v/bsg_manycore_link_sif_tieoff.v index 49fa8a418..96be64369 100644 --- a/v/bsg_manycore_link_sif_tieoff.v +++ b/v/bsg_manycore_link_sif_tieoff.v @@ -14,7 +14,7 @@ module bsg_manycore_link_sif_tieoff , `BSG_INV_PARAM(data_width_p ) , `BSG_INV_PARAM(x_cord_width_p ) , `BSG_INV_PARAM(y_cord_width_p ) - , parameter link_sif_width_lp = + , localparam link_sif_width_lp = `bsg_manycore_link_sif_width(addr_width_p, data_width_p, x_cord_width_p, y_cord_width_p) ) ( diff --git a/v/bsg_manycore_link_to_cache.v b/v/bsg_manycore_link_to_cache.v index e42dec28d..e81cb07bd 100644 --- a/v/bsg_manycore_link_to_cache.v +++ b/v/bsg_manycore_link_to_cache.v @@ -20,21 +20,21 @@ module bsg_manycore_link_to_cache , `BSG_INV_PARAM(ways_p) , `BSG_INV_PARAM(block_size_in_words_p) - , parameter fifo_els_p=4 - - , parameter lg_sets_lp=`BSG_SAFE_CLOG2(sets_p) - , parameter lg_ways_lp=`BSG_SAFE_CLOG2(ways_p) - , parameter word_offset_width_lp=`BSG_SAFE_CLOG2(block_size_in_words_p) - , parameter data_mask_width_lp=(data_width_p>>3) - , parameter byte_offset_width_lp=`BSG_SAFE_CLOG2(data_width_p>>3) - , parameter cache_addr_width_lp=(link_addr_width_p-1+byte_offset_width_lp) - , parameter block_offset_width_lp=(word_offset_width_lp+byte_offset_width_lp) + , fifo_els_p=4 + + , localparam lg_sets_lp=`BSG_SAFE_CLOG2(sets_p) + , lg_ways_lp=`BSG_SAFE_CLOG2(ways_p) + , word_offset_width_lp=`BSG_SAFE_CLOG2(block_size_in_words_p) + , data_mask_width_lp=(data_width_p>>3) + , byte_offset_width_lp=`BSG_SAFE_CLOG2(data_width_p>>3) + , cache_addr_width_lp=(link_addr_width_p-1+byte_offset_width_lp) + , block_offset_width_lp=(word_offset_width_lp+byte_offset_width_lp) - , parameter link_sif_width_lp= + , link_sif_width_lp= `bsg_manycore_link_sif_width(link_addr_width_p,data_width_p,x_cord_width_p,y_cord_width_p) - , parameter bsg_cache_pkt_width_lp= + , bsg_cache_pkt_width_lp= `bsg_cache_pkt_width(cache_addr_width_lp,data_width_p) - , parameter manycore_packet_width_lp= + , manycore_packet_width_lp= `bsg_manycore_packet_width(link_addr_width_p,data_width_p,x_cord_width_p,y_cord_width_p) ) ( diff --git a/v/bsg_manycore_link_to_cache_non_blocking.v b/v/bsg_manycore_link_to_cache_non_blocking.v index c2446d87d..8625681ad 100644 --- a/v/bsg_manycore_link_to_cache_non_blocking.v +++ b/v/bsg_manycore_link_to_cache_non_blocking.v @@ -15,20 +15,20 @@ module bsg_manycore_link_to_cache_non_blocking , `BSG_INV_PARAM(x_cord_width_p) , `BSG_INV_PARAM(y_cord_width_p) - , parameter link_sif_width_lp= + , localparam link_sif_width_lp= `bsg_manycore_link_sif_width(addr_width_p,data_width_p,x_cord_width_p,y_cord_width_p) // cache parmeters - , `BSG_INV_PARAM(sets_p) + , parameter `BSG_INV_PARAM(sets_p) , `BSG_INV_PARAM(ways_p) , `BSG_INV_PARAM(block_size_in_words_p) , `BSG_INV_PARAM(miss_fifo_els_p) - , parameter byte_offset_width_lp=`BSG_SAFE_CLOG2(data_width_p>>3) - , parameter cache_addr_width_lp=(addr_width_p-1+byte_offset_width_lp) + , byte_offset_width_lp=`BSG_SAFE_CLOG2(data_width_p>>3) + , cache_addr_width_lp=(addr_width_p-1+byte_offset_width_lp) - , parameter id_width_lp=(x_cord_width_p+y_cord_width_p+5+2) - , parameter cache_pkt_width_lp= + , id_width_lp=(x_cord_width_p+y_cord_width_p+5+2) + , cache_pkt_width_lp= `bsg_cache_non_blocking_pkt_width(id_width_lp,cache_addr_width_lp,data_width_p) ) ( diff --git a/v/bsg_manycore_link_to_fifo.v b/v/bsg_manycore_link_to_fifo.v index 09c1914a5..5fa6bdb12 100644 --- a/v/bsg_manycore_link_to_fifo.v +++ b/v/bsg_manycore_link_to_fifo.v @@ -17,15 +17,15 @@ module bsg_manycore_link_to_fifo , `BSG_INV_PARAM(y_cord_width_p) //The output fifo width must be multiple times of data_width_p - , parameter out_fifo_width_scale_p = 2 + , out_fifo_width_scale_p = 2 //multiple channel are merged to increase the output bandwidth - , parameter in_channel_scale_p = 2 - , parameter fifo_els_p = 4 + , in_channel_scale_p = 2 + , fifo_els_p = 4 - , parameter bsg_manycore_link_sif_width_lp=`bsg_manycore_link_sif_width(addr_width_p,data_width_p,x_cord_width_p,y_cord_width_p) - , parameter link_sif_num_lp = in_channel_scale_p * out_fifo_width_scale_p - , parameter out_fifo_width_lp = data_width_p * out_fifo_width_scale_p - , parameter debug_lp = 0 + , localparam bsg_manycore_link_sif_width_lp=`bsg_manycore_link_sif_width(addr_width_p,data_width_p,x_cord_width_p,y_cord_width_p) + , link_sif_num_lp = in_channel_scale_p * out_fifo_width_scale_p + , out_fifo_width_lp = data_width_p * out_fifo_width_scale_p + , debug_lp = 0 ) ( diff --git a/v/bsg_manycore_mesh_node.v b/v/bsg_manycore_mesh_node.v index 3a161e9f2..870d10cee 100644 --- a/v/bsg_manycore_mesh_node.v +++ b/v/bsg_manycore_mesh_node.v @@ -13,30 +13,30 @@ module bsg_manycore_mesh_node , `BSG_INV_PARAM(data_width_p) , `BSG_INV_PARAM(addr_width_p) - , parameter dims_p=2 - , parameter dirs_lp=(dims_p*2)+1 + , dims_p=2 + , localparam dirs_lp=(dims_p*2)+1 , parameter ruche_factor_X_p=0 - , parameter ruche_factor_Y_p=0 + , ruche_factor_Y_p=0 - , parameter stub_p = {(dirs_lp-1){1'b0}} // {s,n,e,w} - , parameter repeater_output_p = {(dirs_lp-1){1'b0}} // {s,n,e,w} + , stub_p = {(dirs_lp-1){1'b0}} // {s,n,e,w} + , repeater_output_p = {(dirs_lp-1){1'b0}} // {s,n,e,w} // bit vector to choose which direction in the router to use credit interface. - , parameter fwd_use_credits_p = {dirs_lp{1'b0}} - , parameter rev_use_credits_p = {dirs_lp{1'b0}} + , fwd_use_credits_p = {dirs_lp{1'b0}} + , rev_use_credits_p = {dirs_lp{1'b0}} // number of elements in the input FIFO for each direction. , parameter int fwd_fifo_els_p[dirs_lp-1:0] = '{2,2,2,2,2} , parameter int rev_fifo_els_p[dirs_lp-1:0] = '{2,2,2,2,2} - , parameter debug_p = 0 + , debug_p = 0 - , parameter packet_width_lp = + , localparam packet_width_lp = `bsg_manycore_packet_width(addr_width_p,data_width_p,x_cord_width_p,y_cord_width_p) - , parameter return_packet_width_lp = + , return_packet_width_lp = `bsg_manycore_return_packet_width(x_cord_width_p,y_cord_width_p,data_width_p) - , parameter bsg_manycore_link_sif_width_lp = + , bsg_manycore_link_sif_width_lp = `bsg_manycore_link_sif_width(addr_width_p,data_width_p,x_cord_width_p,y_cord_width_p) ) ( diff --git a/v/bsg_manycore_pod_ruche.v b/v/bsg_manycore_pod_ruche.v index 77bdb6323..79185956d 100644 --- a/v/bsg_manycore_pod_ruche.v +++ b/v/bsg_manycore_pod_ruche.v @@ -26,14 +26,14 @@ module bsg_manycore_pod_ruche , `BSG_INV_PARAM(num_subarray_x_p) , `BSG_INV_PARAM(num_subarray_y_p) // Number of tiles in a subarray - , parameter subarray_num_tiles_x_lp = (num_tiles_x_p/num_subarray_x_p) - , parameter subarray_num_tiles_y_lp = (num_tiles_y_p/num_subarray_y_p) + , localparam subarray_num_tiles_x_lp = (num_tiles_x_p/num_subarray_x_p) + , subarray_num_tiles_y_lp = (num_tiles_y_p/num_subarray_y_p) // coordinate width within a pod - , parameter x_subcord_width_lp=`BSG_SAFE_CLOG2(num_tiles_x_p) - , parameter y_subcord_width_lp=`BSG_SAFE_CLOG2(num_tiles_y_p) + , x_subcord_width_lp=`BSG_SAFE_CLOG2(num_tiles_x_p) + , y_subcord_width_lp=`BSG_SAFE_CLOG2(num_tiles_y_p) - , `BSG_INV_PARAM(dmem_size_p) + , parameter `BSG_INV_PARAM(dmem_size_p) , `BSG_INV_PARAM(icache_entries_p) , `BSG_INV_PARAM(icache_tag_width_p) @@ -56,15 +56,15 @@ module bsg_manycore_pod_ruche , `BSG_INV_PARAM(wh_len_width_p) // number of clock ports on vcache/tile subarray - , parameter num_clk_ports_p=1 + , num_clk_ports_p=1 - , parameter manycore_link_sif_width_lp = + , localparam manycore_link_sif_width_lp = `bsg_manycore_link_sif_width(addr_width_p,data_width_p,x_cord_width_p,y_cord_width_p) - , parameter manycore_ruche_link_sif_width_lp = + , manycore_ruche_link_sif_width_lp = `bsg_manycore_ruche_x_link_sif_width(addr_width_p,data_width_p,x_cord_width_p,y_cord_width_p) - , parameter wh_link_sif_width_lp = + , wh_link_sif_width_lp = `bsg_ready_and_link_sif_width(wh_flit_width_p) // This is used to define heterogeneous arrays. Each index defines diff --git a/v/bsg_manycore_pod_ruche_array.v b/v/bsg_manycore_pod_ruche_array.v index 001eb64de..a5774ae93 100644 --- a/v/bsg_manycore_pod_ruche_array.v +++ b/v/bsg_manycore_pod_ruche_array.v @@ -21,17 +21,17 @@ module bsg_manycore_pod_ruche_array , `BSG_INV_PARAM(y_cord_width_p) , `BSG_INV_PARAM(addr_width_p) , `BSG_INV_PARAM(data_width_p) - , parameter ruche_factor_X_p=3 // only support 3 for now - , parameter barrier_ruche_factor_X_p = 3 + , ruche_factor_X_p=3 // only support 3 for now + , barrier_ruche_factor_X_p = 3 - , parameter num_subarray_x_p=1 - , parameter num_subarray_y_p=1 + , num_subarray_x_p=1 + , num_subarray_y_p=1 , `BSG_INV_PARAM(dmem_size_p) , `BSG_INV_PARAM(icache_entries_p) , `BSG_INV_PARAM(icache_tag_width_p) - , parameter num_vcache_rows_p=1 + , num_vcache_rows_p=1 , `BSG_INV_PARAM(vcache_addr_width_p) , `BSG_INV_PARAM(vcache_data_width_p) , `BSG_INV_PARAM(vcache_ways_p) @@ -40,7 +40,7 @@ module bsg_manycore_pod_ruche_array , `BSG_INV_PARAM(vcache_size_p) , `BSG_INV_PARAM(vcache_dma_data_width_p) - , parameter wh_ruche_factor_p=2 // only support 2 for now + , wh_ruche_factor_p=2 // only support 2 for now , `BSG_INV_PARAM(wh_cid_width_p) , `BSG_INV_PARAM(wh_flit_width_p) , `BSG_INV_PARAM(wh_cord_width_p) @@ -50,17 +50,17 @@ module bsg_manycore_pod_ruche_array , `BSG_INV_PARAM(num_pods_y_p) , `BSG_INV_PARAM(num_pods_x_p) - , parameter reset_depth_p=3 + , reset_depth_p=3 - , parameter x_subcord_width_lp=`BSG_SAFE_CLOG2(num_tiles_x_p) - , parameter y_subcord_width_lp=`BSG_SAFE_CLOG2(num_tiles_y_p) + , localparam x_subcord_width_lp=`BSG_SAFE_CLOG2(num_tiles_x_p) + , y_subcord_width_lp=`BSG_SAFE_CLOG2(num_tiles_y_p) - , parameter manycore_link_sif_width_lp = + , manycore_link_sif_width_lp = `bsg_manycore_link_sif_width(addr_width_p,data_width_p,x_cord_width_p,y_cord_width_p) - , parameter wh_link_sif_width_lp = + , wh_link_sif_width_lp = `bsg_ready_and_link_sif_width(wh_flit_width_p) - , parameter ruche_x_link_sif_width_lp = + , ruche_x_link_sif_width_lp = `bsg_manycore_ruche_x_link_sif_width(addr_width_p,data_width_p,x_cord_width_p,y_cord_width_p) // This is used to define heterogeneous arrays. Each index defines diff --git a/v/bsg_manycore_pod_ruche_row.v b/v/bsg_manycore_pod_ruche_row.v index 23ef3994a..06dbf098b 100644 --- a/v/bsg_manycore_pod_ruche_row.v +++ b/v/bsg_manycore_pod_ruche_row.v @@ -18,16 +18,16 @@ module bsg_manycore_pod_ruche_row , `BSG_INV_PARAM(y_cord_width_p) , `BSG_INV_PARAM(addr_width_p) , `BSG_INV_PARAM(data_width_p) - , parameter ruche_factor_X_p=3 // only support 3 for now - , parameter barrier_ruche_factor_X_p=3 - , parameter num_subarray_x_p=1 - , parameter num_subarray_y_p=1 + , ruche_factor_X_p=3 // only support 3 for now + , barrier_ruche_factor_X_p=3 + , num_subarray_x_p=1 + , num_subarray_y_p=1 , `BSG_INV_PARAM(dmem_size_p) , `BSG_INV_PARAM(icache_entries_p) , `BSG_INV_PARAM(icache_tag_width_p) - , parameter num_vcache_rows_p=1 + , num_vcache_rows_p=1 , `BSG_INV_PARAM(vcache_addr_width_p) , `BSG_INV_PARAM(vcache_data_width_p) , `BSG_INV_PARAM(vcache_ways_p) @@ -36,7 +36,7 @@ module bsg_manycore_pod_ruche_row , `BSG_INV_PARAM(vcache_size_p) , `BSG_INV_PARAM(vcache_dma_data_width_p) - , parameter wh_ruche_factor_p=2 // only support 2 for now + , wh_ruche_factor_p=2 // only support 2 for now , `BSG_INV_PARAM(wh_cid_width_p) , `BSG_INV_PARAM(wh_flit_width_p) , `BSG_INV_PARAM(wh_cord_width_p) @@ -45,17 +45,17 @@ module bsg_manycore_pod_ruche_row // number of pods to instantiate , `BSG_INV_PARAM(num_pods_x_p) - , parameter x_subcord_width_lp=`BSG_SAFE_CLOG2(num_tiles_x_p) - , parameter y_subcord_width_lp=`BSG_SAFE_CLOG2(num_tiles_y_p) + , localparam x_subcord_width_lp=`BSG_SAFE_CLOG2(num_tiles_x_p) + , y_subcord_width_lp=`BSG_SAFE_CLOG2(num_tiles_y_p) // subarray num clk ports , parameter num_clk_ports_p=1 - , parameter manycore_link_sif_width_lp = + , localparam manycore_link_sif_width_lp = `bsg_manycore_link_sif_width(addr_width_p,data_width_p,x_cord_width_p,y_cord_width_p) - , parameter wh_link_sif_width_lp = + , wh_link_sif_width_lp = `bsg_ready_and_link_sif_width(wh_flit_width_p) - , parameter ruche_x_link_sif_width_lp = + , ruche_x_link_sif_width_lp = `bsg_manycore_ruche_x_link_sif_width(addr_width_p,data_width_p,x_cord_width_p,y_cord_width_p) // This is used to define heterogeneous arrays. Each index defines diff --git a/v/bsg_manycore_reg_id_decode.v b/v/bsg_manycore_reg_id_decode.v index 1e94ee095..77adafb43 100644 --- a/v/bsg_manycore_reg_id_decode.v +++ b/v/bsg_manycore_reg_id_decode.v @@ -4,7 +4,7 @@ module bsg_manycore_reg_id_decode import bsg_manycore_pkg::*; #(parameter data_width_p=32 - , parameter data_mask_width_lp=data_width_p>>3 + , localparam data_mask_width_lp=data_width_p>>3 , parameter reg_id_width_p=bsg_manycore_reg_id_width_gp ) ( diff --git a/v/bsg_manycore_reg_id_encode.v b/v/bsg_manycore_reg_id_encode.v index 461ccd064..5e23f0cde 100644 --- a/v/bsg_manycore_reg_id_encode.v +++ b/v/bsg_manycore_reg_id_encode.v @@ -11,7 +11,7 @@ module bsg_manycore_reg_id_encode import bsg_manycore_pkg::*; #(parameter data_width_p=32 - , parameter data_mask_width_lp=(data_width_p>>3) + , localparam data_mask_width_lp=(data_width_p>>3) , parameter reg_id_width_p=bsg_manycore_reg_id_width_gp ) ( diff --git a/v/bsg_manycore_ruche_x_link_sif_tieoff.v b/v/bsg_manycore_ruche_x_link_sif_tieoff.v index 59d5843d7..81cb1f777 100644 --- a/v/bsg_manycore_ruche_x_link_sif_tieoff.v +++ b/v/bsg_manycore_ruche_x_link_sif_tieoff.v @@ -21,32 +21,32 @@ module bsg_manycore_ruche_x_link_sif_tieoff , `BSG_INV_PARAM(ruche_stage_p) , `BSG_INV_PARAM(bit west_not_east_p) // 1'b0 or 1'b1 - , parameter bit ruche_factor_even_lp = (ruche_factor_X_p % 2 == 0) - , parameter bit ruche_stage_even_lp = (ruche_stage_p % 2 == 0) + , localparam bit ruche_factor_even_lp = (ruche_factor_X_p % 2 == 0) + , localparam bit ruche_stage_even_lp = (ruche_stage_p % 2 == 0) - , parameter bit invert_output_lp = (ruche_stage_p > 0) + , localparam bit invert_output_lp = (ruche_stage_p > 0) & (ruche_factor_even_lp ? ~ruche_stage_even_lp : (west_not_east_p ? ruche_stage_even_lp : ~ruche_stage_even_lp)) - , parameter bit invert_input_lp = (ruche_stage_p > 0) + , localparam bit invert_input_lp = (ruche_stage_p > 0) & (ruche_factor_even_lp ? ~ruche_stage_even_lp : (west_not_east_p ? ~ruche_stage_even_lp : ruche_stage_even_lp)) /* - , parameter bit invert_output_lp = (ruche_stage_p > 0) + , localparam bit invert_output_lp = (ruche_stage_p > 0) & (west_not_east_p ? (ruche_factor_X_even_lp ^ ruche_stage_even_lp) : (ruche_factor_X_even_lp ^ ~ruche_stage_even_lp)) - , parameter bit invert_input_lp = (ruche_stage_p > 0) + , localparam bit invert_input_lp = (ruche_stage_p > 0) & (west_not_east_p ? (ruche_factor_X_even_lp ^ ~ruche_stage_even_lp) : (ruche_factor_X_even_lp ^ ruche_stage_even_lp)) */ - , parameter ruche_x_link_sif_width_lp= + , ruche_x_link_sif_width_lp= `bsg_manycore_ruche_x_link_sif_width(addr_width_p,data_width_p,x_cord_width_p,y_cord_width_p) ) ( diff --git a/v/bsg_manycore_tile_compute_array_mesh.v b/v/bsg_manycore_tile_compute_array_mesh.v index db44c64de..ea82c0b88 100644 --- a/v/bsg_manycore_tile_compute_array_mesh.v +++ b/v/bsg_manycore_tile_compute_array_mesh.v @@ -20,8 +20,8 @@ module bsg_manycore_tile_compute_array_mesh // since num_tiles_x_p and num_tiles_y_p will be used to define the size of 2D array // hetero_type_vec_p, they should be int by default to avoid tool crash during // DC synthesis (versions at least up to 2018.06) - , parameter int num_tiles_x_p = -1 - , parameter int num_tiles_y_p = -1 + , `BSG_INV_PARAM(parameter int num_tiles_x_p) + , `BSG_INV_PARAM(parameter int num_tiles_y_p) // This is used to define heterogeneous arrays. Each index defines // the type of an X/Y coordinate in the array. This is a vector of @@ -35,21 +35,21 @@ module bsg_manycore_tile_compute_array_mesh , `BSG_INV_PARAM(data_width_p ) // 32 // Enable branch/jalr trace - , parameter branch_trace_en_p = 0 + , branch_trace_en_p = 0 // x-coordinate of the leftmost tiles // This can be set to 1 or greater to allow attaching accelerators on the left side. - , parameter start_x_cord_p = 0 + , start_x_cord_p = 0 // y = 0 top vcache // y = 1 IO routers // y = num_tiles_y_p+1 bottom vcache - , parameter y_cord_width_lp = `BSG_SAFE_CLOG2(num_tiles_y_p+2) + , localparam y_cord_width_lp = `BSG_SAFE_CLOG2(num_tiles_y_p+2) // By default, x-coordinate is clog2(num_tiles_x_p), but it can be set to greater value to allow attaching accelerators on the side. , parameter x_cord_width_p = `BSG_SAFE_CLOG2(start_x_cord_p+num_tiles_x_p) - , parameter link_sif_width_lp = + , localparam link_sif_width_lp = `bsg_manycore_link_sif_width(addr_width_p,data_width_p,x_cord_width_p,y_cord_width_lp) // The number of registers between the reset_i port and the reset sinks @@ -57,7 +57,7 @@ module bsg_manycore_tile_compute_array_mesh , parameter reset_depth_p = 3 // enable debugging - , parameter debug_p = 0 + , debug_p = 0 ) ( input clk_i diff --git a/v/bsg_manycore_tile_compute_array_ruche.v b/v/bsg_manycore_tile_compute_array_ruche.v index 73e408925..89837c6fa 100644 --- a/v/bsg_manycore_tile_compute_array_ruche.v +++ b/v/bsg_manycore_tile_compute_array_ruche.v @@ -25,12 +25,12 @@ module bsg_manycore_tile_compute_array_ruche // DC synthesis (versions at least up to 2018.06) // Number of tiles in the entire pod - , parameter int num_tiles_x_p = -1 - , parameter int num_tiles_y_p = -1 + , `BSG_INV_PARAM(parameter int num_tiles_x_p) + , `BSG_INV_PARAM(parameter int num_tiles_y_p) // Number of tiles in this subarray. - , parameter subarray_num_tiles_x_p = -1 - , parameter subarray_num_tiles_y_p = -1 + , `BSG_INV_PARAM(subarray_num_tiles_x_p) + , `BSG_INV_PARAM(subarray_num_tiles_y_p) // This is used to define heterogeneous arrays. Each index defines // the type of an X/Y coordinate in the array. This is a vector of @@ -44,34 +44,34 @@ module bsg_manycore_tile_compute_array_ruche , `BSG_INV_PARAM(data_width_p ) // 32 // default ruche factor - , parameter ruche_factor_X_p=3 + , ruche_factor_X_p=3 // barrier ruche factor - , parameter barrier_ruche_factor_X_p=3 + , barrier_ruche_factor_X_p=3 // global coordinate width // global_x/y_i // pod_*_cord_width_p and *_subcord_width_p should sum up to *_cord_width_p. - , parameter y_cord_width_p = -1 - , parameter x_cord_width_p = -1 + , `BSG_INV_PARAM(y_cord_width_p) + , `BSG_INV_PARAM(x_cord_width_p) // pod coordinate width // pod_x/y_i - , parameter pod_y_cord_width_p = -1 - , parameter pod_x_cord_width_p = -1 + , `BSG_INV_PARAM(pod_y_cord_width_p) + , `BSG_INV_PARAM(pod_x_cord_width_p) - , parameter num_clk_ports_p=1 + , num_clk_ports_p=1 // coordinate within a pod // my_x/y_i // A multiple of these modules can be instantiated within a pod as a subarray to form a larger array. - , parameter y_subcord_width_lp=`BSG_SAFE_CLOG2(num_tiles_y_p) - , parameter x_subcord_width_lp=`BSG_SAFE_CLOG2(num_tiles_x_p) + , localparam y_subcord_width_lp=`BSG_SAFE_CLOG2(num_tiles_y_p) + , x_subcord_width_lp=`BSG_SAFE_CLOG2(num_tiles_x_p) - , parameter link_sif_width_lp = + , link_sif_width_lp = `bsg_manycore_link_sif_width(addr_width_p,data_width_p,x_cord_width_p,y_cord_width_p) - , parameter ruche_x_link_sif_width_lp = + , ruche_x_link_sif_width_lp = `bsg_manycore_ruche_x_link_sif_width(addr_width_p,data_width_p,x_cord_width_p,y_cord_width_p) // The number of registers between the reset_i port and the reset sinks @@ -79,7 +79,7 @@ module bsg_manycore_tile_compute_array_ruche , parameter reset_depth_p = 3 // enable debugging - , parameter debug_p = 0 + , debug_p = 0 ) ( input [num_clk_ports_p-1:0] clk_i diff --git a/v/bsg_manycore_tile_compute_mesh.v b/v/bsg_manycore_tile_compute_mesh.v index 845b40088..139373964 100644 --- a/v/bsg_manycore_tile_compute_mesh.v +++ b/v/bsg_manycore_tile_compute_mesh.v @@ -21,8 +21,8 @@ module bsg_manycore_tile_compute_mesh // Number of tiles in a pod , `BSG_INV_PARAM(num_tiles_x_p) , `BSG_INV_PARAM(num_tiles_y_p) - , parameter x_subcord_width_lp = `BSG_SAFE_CLOG2(num_tiles_x_p) - , parameter y_subcord_width_lp = `BSG_SAFE_CLOG2(num_tiles_y_p) + , localparam x_subcord_width_lp = `BSG_SAFE_CLOG2(num_tiles_x_p) + , y_subcord_width_lp = `BSG_SAFE_CLOG2(num_tiles_y_p) @@ -34,16 +34,16 @@ module bsg_manycore_tile_compute_mesh , `BSG_INV_PARAM(vcache_sets_p) , parameter dims_p = 2 - , parameter dirs_lp = (dims_p*2) + , localparam dirs_lp = (dims_p*2) , parameter stub_p = {dirs_lp{1'b0}} // {re,rw,s,n,e,w} - , parameter repeater_output_p = {dirs_lp{1'b0}} // {re,rw,s,n,e,w} - , parameter hetero_type_p = 0 - , parameter debug_p = 0 + , repeater_output_p = {dirs_lp{1'b0}} // {re,rw,s,n,e,w} + , hetero_type_p = 0 + , debug_p = 0 - , parameter link_sif_width_lp = + , localparam link_sif_width_lp = `bsg_manycore_link_sif_width(addr_width_p,data_width_p,x_cord_width_p,y_cord_width_p) ) ( diff --git a/v/bsg_manycore_tile_compute_ruche.v b/v/bsg_manycore_tile_compute_ruche.v index 9b5f4e4a4..cee059b5c 100644 --- a/v/bsg_manycore_tile_compute_ruche.v +++ b/v/bsg_manycore_tile_compute_ruche.v @@ -20,33 +20,33 @@ module bsg_manycore_tile_compute_ruche // Number of tiles in a pod , `BSG_INV_PARAM(num_tiles_x_p) , `BSG_INV_PARAM(num_tiles_y_p) - , parameter x_subcord_width_lp = `BSG_SAFE_CLOG2(num_tiles_x_p) - , parameter y_subcord_width_lp = `BSG_SAFE_CLOG2(num_tiles_y_p) + , localparam x_subcord_width_lp = `BSG_SAFE_CLOG2(num_tiles_x_p) + , y_subcord_width_lp = `BSG_SAFE_CLOG2(num_tiles_y_p) - , `BSG_INV_PARAM(data_width_p ) + , parameter `BSG_INV_PARAM(data_width_p ) , `BSG_INV_PARAM(addr_width_p ) - , parameter ruche_factor_X_p = 3 - , parameter barrier_ruche_factor_X_p = 3 + , ruche_factor_X_p = 3 + , barrier_ruche_factor_X_p = 3 , `BSG_INV_PARAM(num_vcache_rows_p ) , `BSG_INV_PARAM(vcache_block_size_in_words_p) , `BSG_INV_PARAM(vcache_sets_p) , parameter dims_p = 3 - , parameter dirs_lp = (dims_p*2) + , localparam dirs_lp = (dims_p*2) // The topology of the barrier network is matched to the one of manycore links, so that we don't add any additional timing path complexity. , parameter barrier_dirs_p=7 - , parameter barrier_lg_dirs_lp=`BSG_SAFE_CLOG2(barrier_dirs_p+1) + , localparam barrier_lg_dirs_lp=`BSG_SAFE_CLOG2(barrier_dirs_p+1) , parameter stub_p = {dirs_lp{1'b0}} // {re,rw,s,n,e,w} - , parameter repeater_output_p = {dirs_lp{1'b0}} // {re,rw,s,n,e,w} - , parameter hetero_type_p = 0 - , parameter debug_p = 0 + , repeater_output_p = {dirs_lp{1'b0}} // {re,rw,s,n,e,w} + , hetero_type_p = 0 + , debug_p = 0 - , parameter link_sif_width_lp = + , localparam link_sif_width_lp = `bsg_manycore_link_sif_width(addr_width_p,data_width_p,x_cord_width_p,y_cord_width_p) - , parameter ruche_x_link_sif_width_lp = + , ruche_x_link_sif_width_lp = `bsg_manycore_ruche_x_link_sif_width(addr_width_p,data_width_p,x_cord_width_p,y_cord_width_p) ) ( diff --git a/v/bsg_manycore_tile_vcache.v b/v/bsg_manycore_tile_vcache.v index 2ca48aad2..b3d3eef92 100644 --- a/v/bsg_manycore_tile_vcache.v +++ b/v/bsg_manycore_tile_vcache.v @@ -34,18 +34,18 @@ module bsg_manycore_tile_vcache , `BSG_INV_PARAM(wh_flit_width_p) , `BSG_INV_PARAM(wh_len_width_p) , `BSG_INV_PARAM(wh_cord_width_p) - , parameter int wh_cord_markers_pos_lp[1:0] = '{wh_cord_width_p, 0} + , localparam int wh_cord_markers_pos_lp[1:0] = '{wh_cord_width_p, 0} , parameter req_fifo_els_p=4 - , parameter lg_wh_ruche_factor_lp = `BSG_SAFE_CLOG2(wh_ruche_factor_p) + , localparam lg_wh_ruche_factor_lp = `BSG_SAFE_CLOG2(wh_ruche_factor_p) - , parameter y_subcord_width_lp = `BSG_SAFE_CLOG2(num_tiles_y_p) + , y_subcord_width_lp = `BSG_SAFE_CLOG2(num_tiles_y_p) - , parameter manycore_link_sif_width_lp = + , manycore_link_sif_width_lp = `bsg_manycore_link_sif_width(addr_width_p,data_width_p,x_cord_width_p,y_cord_width_p) - , parameter wh_link_sif_width_lp = + , wh_link_sif_width_lp = `bsg_ready_and_link_sif_width(wh_flit_width_p) , parameter vcache_amo_support_p = (1 << e_cache_amo_swap) diff --git a/v/bsg_manycore_tile_vcache_array.v b/v/bsg_manycore_tile_vcache_array.v index 5101296e3..9cc9c8c03 100644 --- a/v/bsg_manycore_tile_vcache_array.v +++ b/v/bsg_manycore_tile_vcache_array.v @@ -20,11 +20,11 @@ module bsg_manycore_tile_vcache_array , `BSG_INV_PARAM(num_tiles_x_p) , `BSG_INV_PARAM(num_tiles_y_p) - , parameter x_subcord_width_lp=`BSG_SAFE_CLOG2(num_tiles_x_p) - , parameter y_subcord_width_lp=`BSG_SAFE_CLOG2(num_tiles_y_p) + , localparam x_subcord_width_lp=`BSG_SAFE_CLOG2(num_tiles_x_p) + , localparam y_subcord_width_lp=`BSG_SAFE_CLOG2(num_tiles_y_p) // Number of tiles in a subarray - , `BSG_INV_PARAM(subarray_num_tiles_x_p) + , parameter `BSG_INV_PARAM(subarray_num_tiles_x_p) , `BSG_INV_PARAM(num_vcache_rows_p ) , `BSG_INV_PARAM(vcache_addr_width_p ) @@ -40,13 +40,13 @@ module bsg_manycore_tile_vcache_array , `BSG_INV_PARAM(wh_len_width_p) , `BSG_INV_PARAM(wh_cord_width_p) - , parameter num_clk_ports_p=1 + , num_clk_ports_p=1 //, parameter reset_depth_p = 3 - , parameter manycore_link_sif_width_lp = + , localparam manycore_link_sif_width_lp = `bsg_manycore_link_sif_width(addr_width_p,data_width_p,x_cord_width_p,y_cord_width_p) - , parameter wh_link_sif_width_lp = + , wh_link_sif_width_lp = `bsg_ready_and_link_sif_width(wh_flit_width_p) ) ( diff --git a/v/bsg_manycore_vcache_blocking.v b/v/bsg_manycore_vcache_blocking.v index ce0f39fc6..7f0705c88 100644 --- a/v/bsg_manycore_vcache_blocking.v +++ b/v/bsg_manycore_vcache_blocking.v @@ -19,12 +19,12 @@ module bsg_manycore_vcache_blocking , `BSG_INV_PARAM(x_cord_width_p) , `BSG_INV_PARAM(y_cord_width_p) - , parameter byte_offset_width_lp=`BSG_SAFE_CLOG2(data_width_p>>3) - , parameter cache_addr_width_lp=(addr_width_p-1+byte_offset_width_lp) + , localparam byte_offset_width_lp=`BSG_SAFE_CLOG2(data_width_p>>3) + , cache_addr_width_lp=(addr_width_p-1+byte_offset_width_lp) - , parameter link_sif_width_lp = + , link_sif_width_lp = `bsg_manycore_link_sif_width(addr_width_p,data_width_p,x_cord_width_p,y_cord_width_p) - , parameter cache_dma_pkt_width_lp = + , cache_dma_pkt_width_lp = `bsg_cache_dma_pkt_width(cache_addr_width_lp) ) ( diff --git a/v/bsg_manycore_vcache_non_blocking.v b/v/bsg_manycore_vcache_non_blocking.v index cc3c4a26c..6afa5676b 100644 --- a/v/bsg_manycore_vcache_non_blocking.v +++ b/v/bsg_manycore_vcache_non_blocking.v @@ -18,13 +18,13 @@ module bsg_manycore_vcache_non_blocking , `BSG_INV_PARAM(block_size_in_words_p) , `BSG_INV_PARAM(miss_fifo_els_p) - , parameter byte_offset_width_lp=`BSG_SAFE_CLOG2(data_width_p>>3) - , parameter cache_addr_width_lp=(addr_width_p-1+byte_offset_width_lp) + , localparam byte_offset_width_lp=`BSG_SAFE_CLOG2(data_width_p>>3) + , cache_addr_width_lp=(addr_width_p-1+byte_offset_width_lp) - , parameter link_sif_width_lp= + , link_sif_width_lp= `bsg_manycore_link_sif_width(addr_width_p,data_width_p,x_cord_width_p,y_cord_width_p) - , parameter cache_dma_pkt_width_lp= + , cache_dma_pkt_width_lp= `bsg_cache_non_blocking_dma_pkt_width(cache_addr_width_lp) ) diff --git a/v/bsg_ruche_buffer.v b/v/bsg_ruche_buffer.v index 7c1be5d9d..5734df51e 100644 --- a/v/bsg_ruche_buffer.v +++ b/v/bsg_ruche_buffer.v @@ -10,7 +10,7 @@ module bsg_ruche_buffer , `BSG_INV_PARAM(ruche_factor_p) , `BSG_INV_PARAM(ruche_stage_p) - , parameter bit invert_lp = (ruche_stage_p == 0) + , localparam bit invert_lp = (ruche_stage_p == 0) ? (ruche_factor_p % 2 == 0) : 1'b1 diff --git a/v/bsg_ruche_link_sif_tieoff.v b/v/bsg_ruche_link_sif_tieoff.v index 0de050129..07c012379 100644 --- a/v/bsg_ruche_link_sif_tieoff.v +++ b/v/bsg_ruche_link_sif_tieoff.v @@ -14,16 +14,16 @@ module bsg_ruche_link_sif_tieoff , `BSG_INV_PARAM(bit west_not_east_p) // tie-off on west or east side?? - , parameter bit ruche_factor_even_lp = (ruche_factor_p % 2 == 0) - , parameter bit ruche_stage_even_lp = (ruche_stage_p % 2 == 0) + , localparam bit ruche_factor_even_lp = (ruche_factor_p % 2 == 0) + , localparam bit ruche_stage_even_lp = (ruche_stage_p % 2 == 0) - , parameter bit invert_output_lp = (ruche_stage_p > 0) + , localparam bit invert_output_lp = (ruche_stage_p > 0) & (ruche_factor_even_lp ? ~ruche_stage_even_lp : (west_not_east_p ? ruche_stage_even_lp : ~ruche_stage_even_lp)) - , parameter bit invert_input_lp = (ruche_stage_p > 0) + , localparam bit invert_input_lp = (ruche_stage_p > 0) & (ruche_factor_even_lp ? ~ruche_stage_even_lp : (west_not_east_p @@ -31,7 +31,7 @@ module bsg_ruche_link_sif_tieoff : ruche_stage_even_lp)) - , parameter link_width_lp=`bsg_ready_and_link_sif_width(link_data_width_p) + , link_width_lp=`bsg_ready_and_link_sif_width(link_data_width_p) ) ( // debug only diff --git a/v/vanilla_bean/bsg_cache_to_axi_hashed.v b/v/vanilla_bean/bsg_cache_to_axi_hashed.v index 83416f845..bda5e975a 100644 --- a/v/vanilla_bean/bsg_cache_to_axi_hashed.v +++ b/v/vanilla_bean/bsg_cache_to_axi_hashed.v @@ -17,17 +17,17 @@ module bsg_cache_to_axi_hashed ,`BSG_INV_PARAM(axi_data_width_p) ,`BSG_INV_PARAM(axi_burst_len_p) - ,parameter data_mask_width_lp=(data_width_p>>3) - ,parameter lg_data_mask_width_lp=`BSG_SAFE_CLOG2(data_mask_width_lp) - ,parameter lg_block_size_in_words_lp=`BSG_SAFE_CLOG2(block_size_in_words_p) + ,localparam data_mask_width_lp=(data_width_p>>3) + ,lg_data_mask_width_lp=`BSG_SAFE_CLOG2(data_mask_width_lp) + ,lg_block_size_in_words_lp=`BSG_SAFE_CLOG2(block_size_in_words_p) - ,parameter lg_num_cache_lp=`BSG_SAFE_CLOG2(num_cache_p) - ,parameter dma_pkt_width_lp=`bsg_cache_dma_pkt_width(addr_width_p) + ,lg_num_cache_lp=`BSG_SAFE_CLOG2(num_cache_p) + ,dma_pkt_width_lp=`bsg_cache_dma_pkt_width(addr_width_p) - ,parameter axi_strb_width_lp=(axi_data_width_p>>3) + ,axi_strb_width_lp=(axi_data_width_p>>3) ,parameter dram_size_in_words_p=2**29 - ,parameter block_number_width_lp=`BSG_SAFE_CLOG2(dram_size_in_words_p)-lg_block_size_in_words_lp + ,localparam block_number_width_lp=`BSG_SAFE_CLOG2(dram_size_in_words_p)-lg_block_size_in_words_lp ) ( input clk_i diff --git a/v/vanilla_bean/bsg_manycore_proc_vanilla.v b/v/vanilla_bean/bsg_manycore_proc_vanilla.v index 8bc59bab6..6141ca5c4 100644 --- a/v/vanilla_bean/bsg_manycore_proc_vanilla.v +++ b/v/vanilla_bean/bsg_manycore_proc_vanilla.v @@ -27,26 +27,26 @@ module bsg_manycore_proc_vanilla , `BSG_INV_PARAM(num_tiles_x_p) , `BSG_INV_PARAM(num_tiles_y_p) - , parameter x_subcord_width_lp = `BSG_SAFE_CLOG2(num_tiles_x_p) - , parameter y_subcord_width_lp = `BSG_SAFE_CLOG2(num_tiles_y_p) + , localparam x_subcord_width_lp = `BSG_SAFE_CLOG2(num_tiles_x_p) + , y_subcord_width_lp = `BSG_SAFE_CLOG2(num_tiles_y_p) - , `BSG_INV_PARAM(rev_fifo_els_p) // for FIFO credit counting. + , parameter `BSG_INV_PARAM(rev_fifo_els_p) // for FIFO credit counting. , `BSG_INV_PARAM(fwd_fifo_els_p) // for FIFO credit counting. - , parameter credit_counter_width_p = `BSG_WIDTH(32) - , parameter proc_fifo_els_p = 4 - , parameter debug_p = 1 + , credit_counter_width_p = `BSG_WIDTH(32) + , proc_fifo_els_p = 4 + , debug_p = 1 - , parameter icache_addr_width_lp = `BSG_SAFE_CLOG2(icache_entries_p) - , parameter dmem_addr_width_lp = `BSG_SAFE_CLOG2(dmem_size_p) - , parameter pc_width_lp=(icache_addr_width_lp+icache_tag_width_p) - , parameter data_mask_width_lp=(data_width_p>>3) - , parameter reg_addr_width_lp=RV32_reg_addr_width_gp + , localparam icache_addr_width_lp = `BSG_SAFE_CLOG2(icache_entries_p) + , dmem_addr_width_lp = `BSG_SAFE_CLOG2(dmem_size_p) + , pc_width_lp=(icache_addr_width_lp+icache_tag_width_p) + , data_mask_width_lp=(data_width_p>>3) + , reg_addr_width_lp=RV32_reg_addr_width_gp - , parameter barrier_dirs_p = "inv" - , parameter barrier_lg_dirs_lp=`BSG_SAFE_CLOG2(barrier_dirs_p+1) + , parameter `BSG_INV_PARAM(barrier_dirs_p) + , localparam barrier_lg_dirs_lp=`BSG_SAFE_CLOG2(barrier_dirs_p+1) - , parameter link_sif_width_lp = + , link_sif_width_lp = `bsg_manycore_link_sif_width(addr_width_p,data_width_p,x_cord_width_p,y_cord_width_p) ) diff --git a/v/vanilla_bean/fcsr.v b/v/vanilla_bean/fcsr.v index 63d8fa389..728844dce 100644 --- a/v/vanilla_bean/fcsr.v +++ b/v/vanilla_bean/fcsr.v @@ -7,9 +7,9 @@ module fcsr import bsg_vanilla_pkg::*; - #(parameter fflags_width_lp=$bits(fflags_s) - , parameter frm_width_lp=$bits(frm_e) - , parameter reg_addr_width_lp=RV32_reg_addr_width_gp + #(localparam fflags_width_lp=$bits(fflags_s) + , frm_width_lp=$bits(frm_e) + , reg_addr_width_lp=RV32_reg_addr_width_gp ) ( input clk_i diff --git a/v/vanilla_bean/fpu_fdiv_fsqrt.v b/v/vanilla_bean/fpu_fdiv_fsqrt.v index 83ddd184e..d7eaf8a08 100644 --- a/v/vanilla_bean/fpu_fdiv_fsqrt.v +++ b/v/vanilla_bean/fpu_fdiv_fsqrt.v @@ -11,10 +11,10 @@ module fpu_fdiv_fsqrt import bsg_vanilla_pkg::*; - #(parameter exp_width_p=fpu_recoded_exp_width_gp - , parameter sig_width_p=fpu_recoded_sig_width_gp - , parameter reg_addr_width_p=RV32_reg_addr_width_gp - , parameter recoded_data_width_lp=(1+exp_width_p+sig_width_p) + #(exp_width_p=fpu_recoded_exp_width_gp + ,sig_width_p=fpu_recoded_sig_width_gp + ,reg_addr_width_p=RV32_reg_addr_width_gp + , localparam recoded_data_width_lp=(1+exp_width_p+sig_width_p) ) ( input clk_i diff --git a/v/vanilla_bean/fpu_float.v b/v/vanilla_bean/fpu_float.v index 18762fb71..01117d27e 100644 --- a/v/vanilla_bean/fpu_float.v +++ b/v/vanilla_bean/fpu_float.v @@ -14,10 +14,10 @@ module fpu_float import bsg_vanilla_pkg::*; #(parameter exp_width_p=fpu_recoded_exp_width_gp - , parameter sig_width_p=fpu_recoded_sig_width_gp - , parameter data_width_p=RV32_reg_data_width_gp // integer width - , parameter reg_addr_width_p=RV32_reg_addr_width_gp - , parameter recoded_data_width_lp=(1+exp_width_p+sig_width_p) + , sig_width_p=fpu_recoded_sig_width_gp + , data_width_p=RV32_reg_data_width_gp // integer width + , reg_addr_width_p=RV32_reg_addr_width_gp + , localparam recoded_data_width_lp=(1+exp_width_p+sig_width_p) ) ( input clk_i diff --git a/v/vanilla_bean/fpu_float_aux.v b/v/vanilla_bean/fpu_float_aux.v index f24123bab..1caf1cbc5 100644 --- a/v/vanilla_bean/fpu_float_aux.v +++ b/v/vanilla_bean/fpu_float_aux.v @@ -10,10 +10,10 @@ module fpu_float_aux import bsg_vanilla_pkg::*; #(parameter sig_width_p=fpu_recoded_sig_width_gp - , parameter exp_width_p=fpu_recoded_exp_width_gp - , parameter data_width_p=RV32_reg_data_width_gp + , exp_width_p=fpu_recoded_exp_width_gp + , data_width_p=RV32_reg_data_width_gp - , parameter recoded_data_width_lp=(1+sig_width_p+exp_width_p) + , localparam recoded_data_width_lp=(1+sig_width_p+exp_width_p) ) ( input fp_v_i diff --git a/v/vanilla_bean/fpu_float_fma.v b/v/vanilla_bean/fpu_float_fma.v index 22a62738d..fe4c6b05e 100644 --- a/v/vanilla_bean/fpu_float_fma.v +++ b/v/vanilla_bean/fpu_float_fma.v @@ -12,9 +12,9 @@ module fpu_float_fma import bsg_vanilla_pkg::*; import bsg_hardfloat_pkg::*; #(parameter exp_width_p=fpu_recoded_exp_width_gp - , parameter sig_width_p=fpu_recoded_sig_width_gp - , parameter data_width_p=RV32_reg_data_width_gp - , parameter recoded_data_width_lp=(1+exp_width_p+sig_width_p) + , sig_width_p=fpu_recoded_sig_width_gp + , data_width_p=RV32_reg_data_width_gp + , localparam recoded_data_width_lp=(1+exp_width_p+sig_width_p) ) ( input clk_i diff --git a/v/vanilla_bean/fpu_float_fma_round.v b/v/vanilla_bean/fpu_float_fma_round.v index ec711fff9..c99a26bd7 100644 --- a/v/vanilla_bean/fpu_float_fma_round.v +++ b/v/vanilla_bean/fpu_float_fma_round.v @@ -10,9 +10,9 @@ module fpu_float_fma_round import bsg_vanilla_pkg::*; #(parameter exp_width_p = fpu_recoded_exp_width_gp - , parameter sig_width_p = fpu_recoded_sig_width_gp + , sig_width_p = fpu_recoded_sig_width_gp - , parameter recoded_data_width_lp=(1+exp_width_p+sig_width_p) + , localparam recoded_data_width_lp=(1+exp_width_p+sig_width_p) ) ( input clk_i diff --git a/v/vanilla_bean/fpu_fmin_fmax.v b/v/vanilla_bean/fpu_fmin_fmax.v index d2a1605ab..e91805f86 100644 --- a/v/vanilla_bean/fpu_fmin_fmax.v +++ b/v/vanilla_bean/fpu_fmin_fmax.v @@ -16,7 +16,7 @@ module fpu_fmin_fmax #(`BSG_INV_PARAM(exp_width_p) , `BSG_INV_PARAM(sig_width_p) - , parameter recoded_data_width_lp=(exp_width_p+sig_width_p+1) + , localparam recoded_data_width_lp=(exp_width_p+sig_width_p+1) ) ( input [recoded_data_width_lp-1:0] fp_rs1_i diff --git a/v/vanilla_bean/fpu_int.v b/v/vanilla_bean/fpu_int.v index 6634f8f5d..6faae48ef 100644 --- a/v/vanilla_bean/fpu_int.v +++ b/v/vanilla_bean/fpu_int.v @@ -15,9 +15,9 @@ module fpu_int import bsg_vanilla_pkg::*; #(parameter exp_width_p=fpu_recoded_exp_width_gp - , parameter sig_width_p=fpu_recoded_sig_width_gp - , parameter data_width_p=RV32_reg_data_width_gp // integer width - , parameter recoded_data_width_lp=(1+exp_width_p+sig_width_p) + , sig_width_p=fpu_recoded_sig_width_gp + , data_width_p=RV32_reg_data_width_gp // integer width + , localparam recoded_data_width_lp=(1+exp_width_p+sig_width_p) ) ( input [recoded_data_width_lp-1:0] fp_rs1_i diff --git a/v/vanilla_bean/fpu_int_fclass.v b/v/vanilla_bean/fpu_int_fclass.v index 521d03f15..1bf0f6b28 100644 --- a/v/vanilla_bean/fpu_int_fclass.v +++ b/v/vanilla_bean/fpu_int_fclass.v @@ -8,8 +8,8 @@ module fpu_int_fclass import bsg_vanilla_pkg::*; #(parameter exp_width_p=fpu_recoded_exp_width_gp - , parameter sig_width_p=fpu_recoded_sig_width_gp - , parameter recoded_data_width_lp=(1+exp_width_p+sig_width_p) + , sig_width_p=fpu_recoded_sig_width_gp + , localparam recoded_data_width_lp=(1+exp_width_p+sig_width_p) ) ( input [recoded_data_width_lp-1:0] i diff --git a/v/vanilla_bean/hash_function_reverse.v b/v/vanilla_bean/hash_function_reverse.v index 466869f37..5e92fbcf5 100644 --- a/v/vanilla_bean/hash_function_reverse.v +++ b/v/vanilla_bean/hash_function_reverse.v @@ -5,8 +5,8 @@ module hash_function_reverse #(`BSG_INV_PARAM(width_p) ,`BSG_INV_PARAM(banks_p) - , parameter lg_banks_lp=`BSG_SAFE_CLOG2(banks_p) - , parameter index_width_lp=$clog2((2**width_p+banks_p-1)/banks_p) + , localparam lg_banks_lp=`BSG_SAFE_CLOG2(banks_p) + , index_width_lp=$clog2((2**width_p+banks_p-1)/banks_p) ) ( input [index_width_lp-1:0] index_i diff --git a/v/vanilla_bean/icache.v b/v/vanilla_bean/icache.v index e74db250d..cfbab5076 100644 --- a/v/vanilla_bean/icache.v +++ b/v/vanilla_bean/icache.v @@ -14,8 +14,8 @@ module icache #(`BSG_INV_PARAM(icache_tag_width_p) , `BSG_INV_PARAM(icache_entries_p) - , parameter icache_addr_width_lp=`BSG_SAFE_CLOG2(icache_entries_p) - , parameter pc_width_lp=(icache_tag_width_p+icache_addr_width_lp) + , localparam icache_addr_width_lp=`BSG_SAFE_CLOG2(icache_entries_p) + , pc_width_lp=(icache_tag_width_p+icache_addr_width_lp) ) ( input clk_i diff --git a/v/vanilla_bean/idiv.v b/v/vanilla_bean/idiv.v index dc171f71b..c690ae32e 100644 --- a/v/vanilla_bean/idiv.v +++ b/v/vanilla_bean/idiv.v @@ -9,8 +9,8 @@ module idiv import bsg_vanilla_pkg::*; - #(parameter data_width_p=RV32_reg_data_width_gp - ,parameter reg_addr_width_p=RV32_reg_addr_width_gp + #(data_width_p=RV32_reg_data_width_gp + ,reg_addr_width_p=RV32_reg_addr_width_gp ) ( input clk_i diff --git a/v/vanilla_bean/load_packer.v b/v/vanilla_bean/load_packer.v index 4728c0599..8cb0eb3f7 100644 --- a/v/vanilla_bean/load_packer.v +++ b/v/vanilla_bean/load_packer.v @@ -7,7 +7,7 @@ module load_packer import bsg_vanilla_pkg::*; - #(parameter data_width_p = RV32_reg_data_width_gp) + #(data_width_p = RV32_reg_data_width_gp) ( input [data_width_p-1:0] mem_data_i diff --git a/v/vanilla_bean/lsu.v b/v/vanilla_bean/lsu.v index 71626e499..d992ff257 100644 --- a/v/vanilla_bean/lsu.v +++ b/v/vanilla_bean/lsu.v @@ -22,8 +22,8 @@ module lsu , `BSG_INV_PARAM(dmem_size_p) , localparam dmem_addr_width_lp=`BSG_SAFE_CLOG2(dmem_size_p) - , localparam data_mask_width_lp=(data_width_p>>3) - , localparam reg_addr_width_lp=RV32_reg_addr_width_gp + , data_mask_width_lp=(data_width_p>>3) + , reg_addr_width_lp=RV32_reg_addr_width_gp ) ( input clk_i diff --git a/v/vanilla_bean/mcsr.v b/v/vanilla_bean/mcsr.v index f4f1ff3c6..84a5e9ced 100644 --- a/v/vanilla_bean/mcsr.v +++ b/v/vanilla_bean/mcsr.v @@ -13,14 +13,14 @@ module mcsr import bsg_vanilla_pkg::*; - #(parameter reg_addr_width_lp = RV32_reg_addr_width_gp - , parameter reg_data_width_lp = RV32_reg_data_width_gp - , `BSG_INV_PARAM(pc_width_p) + #(localparam reg_addr_width_lp = RV32_reg_addr_width_gp + , reg_data_width_lp = RV32_reg_data_width_gp + , parameter `BSG_INV_PARAM(pc_width_p) , `BSG_INV_PARAM(barrier_dirs_p) - , parameter barrier_lg_dirs_lp=`BSG_SAFE_CLOG2(barrier_dirs_p+1) + , localparam barrier_lg_dirs_lp=`BSG_SAFE_CLOG2(barrier_dirs_p+1) , parameter credit_limit_default_val_p = 32 - , parameter credit_counter_width_p=`BSG_WIDTH(32) - , parameter cfg_pod_width_p=32 + , credit_counter_width_p=`BSG_WIDTH(32) + , cfg_pod_width_p=32 ) ( input clk_i diff --git a/v/vanilla_bean/network_rx.v b/v/vanilla_bean/network_rx.v index 1e4b866ac..74d0675d7 100644 --- a/v/vanilla_bean/network_rx.v +++ b/v/vanilla_bean/network_rx.v @@ -20,10 +20,10 @@ module network_rx , `BSG_INV_PARAM(x_subcord_width_p) , `BSG_INV_PARAM(y_subcord_width_p) - , parameter tgo_x_init_val_p = 0 - , parameter tgo_y_init_val_p = 0 - , parameter freeze_init_val_p = 1 - , parameter default_pc_init_val_p = 0 + , tgo_x_init_val_p = 0 + , tgo_y_init_val_p = 0 + , freeze_init_val_p = 1 + , default_pc_init_val_p = 0 , localparam data_mask_width_lp=(data_width_p>>3) , localparam dmem_addr_width_lp=`BSG_SAFE_CLOG2(dmem_size_p) diff --git a/v/vanilla_bean/network_tx.v b/v/vanilla_bean/network_tx.v index 2640e11ca..495cb2465 100644 --- a/v/vanilla_bean/network_tx.v +++ b/v/vanilla_bean/network_tx.v @@ -22,22 +22,22 @@ module network_tx , `BSG_INV_PARAM(num_tiles_x_p) , `BSG_INV_PARAM(num_tiles_y_p) - , parameter x_subcord_width_lp=`BSG_SAFE_CLOG2(num_tiles_x_p) - , parameter y_subcord_width_lp=`BSG_SAFE_CLOG2(num_tiles_y_p) + , localparam x_subcord_width_lp=`BSG_SAFE_CLOG2(num_tiles_x_p) + , y_subcord_width_lp=`BSG_SAFE_CLOG2(num_tiles_y_p) - , `BSG_INV_PARAM(icache_entries_p) + , parameter `BSG_INV_PARAM(icache_entries_p) , `BSG_INV_PARAM(icache_tag_width_p) - , parameter vcache_addr_width_lp=`BSG_SAFE_CLOG2(vcache_size_p) + , localparam vcache_addr_width_lp=`BSG_SAFE_CLOG2(vcache_size_p) - , parameter vcache_word_offset_width_lp = `BSG_SAFE_CLOG2(vcache_block_size_in_words_p) + , vcache_word_offset_width_lp = `BSG_SAFE_CLOG2(vcache_block_size_in_words_p) - , parameter icache_addr_width_lp=`BSG_SAFE_CLOG2(icache_entries_p) - , parameter pc_width_lp=(icache_tag_width_p+icache_addr_width_lp) + , icache_addr_width_lp=`BSG_SAFE_CLOG2(icache_entries_p) + , pc_width_lp=(icache_tag_width_p+icache_addr_width_lp) - , parameter reg_addr_width_lp=RV32_reg_addr_width_gp + , reg_addr_width_lp=RV32_reg_addr_width_gp - , parameter packet_width_lp= + , packet_width_lp= `bsg_manycore_packet_width(addr_width_p,data_width_p,x_cord_width_p,y_cord_width_p) ) ( diff --git a/v/vanilla_bean/regfile.v b/v/vanilla_bean/regfile.v index 884108ecd..d1a19ec01 100644 --- a/v/vanilla_bean/regfile.v +++ b/v/vanilla_bean/regfile.v @@ -15,9 +15,9 @@ module regfile , `BSG_INV_PARAM(els_p) , `BSG_INV_PARAM(num_rs_p) , `BSG_INV_PARAM(x0_tied_to_zero_p) - , parameter harden_p=0 + , harden_p=0 - , parameter addr_width_lp=`BSG_SAFE_CLOG2(els_p) + , localparam addr_width_lp=`BSG_SAFE_CLOG2(els_p) ) ( input clk_i diff --git a/v/vanilla_bean/regfile_hard.v b/v/vanilla_bean/regfile_hard.v index 3b3dba002..43dd7e2b6 100644 --- a/v/vanilla_bean/regfile_hard.v +++ b/v/vanilla_bean/regfile_hard.v @@ -14,7 +14,7 @@ module regfile_hard #(`BSG_INV_PARAM(width_p ) , `BSG_INV_PARAM(els_p ) , `BSG_INV_PARAM(num_rs_p ) // number of read ports. only supports 2 and 3. - , parameter x0_tied_to_zero_p=0 + , x0_tied_to_zero_p=0 , localparam addr_width_lp = `BSG_SAFE_CLOG2(els_p) ) ( diff --git a/v/vanilla_bean/regfile_synth.v b/v/vanilla_bean/regfile_synth.v index 329c32b21..ca531da68 100644 --- a/v/vanilla_bean/regfile_synth.v +++ b/v/vanilla_bean/regfile_synth.v @@ -14,7 +14,7 @@ module regfile_synth , `BSG_INV_PARAM(num_rs_p) , `BSG_INV_PARAM(x0_tied_to_zero_p) - , parameter addr_width_lp=`BSG_SAFE_CLOG2(els_p) + , localparam addr_width_lp=`BSG_SAFE_CLOG2(els_p) ) ( input clk_i diff --git a/v/vanilla_bean/scoreboard.v b/v/vanilla_bean/scoreboard.v index b649303b5..f81447d92 100644 --- a/v/vanilla_bean/scoreboard.v +++ b/v/vanilla_bean/scoreboard.v @@ -9,11 +9,11 @@ module scoreboard import bsg_vanilla_pkg::*; - #(parameter els_p = RV32_reg_els_gp + #(els_p = RV32_reg_els_gp , `BSG_INV_PARAM(num_src_port_p) - , parameter num_clear_port_p=1 - , parameter x0_tied_to_zero_p = 0 - , parameter id_width_lp = `BSG_SAFE_CLOG2(els_p) + , num_clear_port_p=1 + , x0_tied_to_zero_p = 0 + , localparam id_width_lp = `BSG_SAFE_CLOG2(els_p) ) ( input clk_i diff --git a/v/vanilla_bean/vanilla_core.v b/v/vanilla_bean/vanilla_core.v index d801f0d4b..1cca1a9b8 100644 --- a/v/vanilla_bean/vanilla_core.v +++ b/v/vanilla_bean/vanilla_core.v @@ -25,20 +25,20 @@ module vanilla_core , `BSG_INV_PARAM(pod_y_cord_width_p) , `BSG_INV_PARAM(barrier_dirs_p) - , parameter barrier_lg_dirs_lp=`BSG_SAFE_CLOG2(barrier_dirs_p+1) + , localparam barrier_lg_dirs_lp=`BSG_SAFE_CLOG2(barrier_dirs_p+1) , parameter credit_counter_width_p=`BSG_WIDTH(32) // For network input FIFO credit counting // By default, 3 credits are needed, because the round trip to get the credit back takes three cycles. // ID->EXE->FIFO->CREDIT. , `BSG_INV_PARAM(fwd_fifo_els_p) - , parameter lg_fwd_fifo_els_lp=`BSG_WIDTH(fwd_fifo_els_p) + , localparam lg_fwd_fifo_els_lp=`BSG_WIDTH(fwd_fifo_els_p) - , parameter dmem_addr_width_lp=`BSG_SAFE_CLOG2(dmem_size_p) - , parameter icache_addr_width_lp=`BSG_SAFE_CLOG2(icache_entries_p) - , parameter pc_width_lp=(icache_tag_width_p+icache_addr_width_lp) - , parameter reg_addr_width_lp = RV32_reg_addr_width_gp - , parameter data_mask_width_lp=(data_width_p>>3) + , dmem_addr_width_lp=`BSG_SAFE_CLOG2(dmem_size_p) + , icache_addr_width_lp=`BSG_SAFE_CLOG2(icache_entries_p) + , pc_width_lp=(icache_tag_width_p+icache_addr_width_lp) + , reg_addr_width_lp = RV32_reg_addr_width_gp + , data_mask_width_lp=(data_width_p>>3) , parameter debug_p=0 )