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DDR3 SSTL Design for SKY130

This repo contains a DDR3 SSTL driver circuit designed for the Skywater 130nm PDK.

Introduction and design overview found here.

Installation simulation script instructions here.
PDK installation instructions found here.

Directory structure:

  • schem Xschem schematic files for SSTL design.
  • layout Magic format layout files for SSTL design.
  • scripts Simulation handling and automation Python scripts.
  • docs Some extra documentation files.
  • sky130 Sky130 specific files (standard cell "include" files.)
  • spice Output directory for spice scripts generated by Xschem.
  • out Output directory for simulation results.
  • tools Instillation directory for the open source DEA tools used for design and simulation.

Implementation

This circuit was implemented in a Efabless MPW-5 project which can be found in (this repo).