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Should the reset be asynchronous in case of signals like PC in pc.vhdl added by #9? It may cause errors in functioning due to erratic changes in PC. (We might need to change in other places as well.)
The text was updated successfully, but these errors were encountered:
Should the reset be asynchronous in case of signals like PC in pc.vhdl added by #9? It may cause errors in functioning due to erratic changes in PC. (We might need to change in other places as well.)
The text was updated successfully, but these errors were encountered: