From defc653a1eb2e444b1a97df0fe2b92498f62cfca Mon Sep 17 00:00:00 2001 From: Olliver Schinagl Date: Sun, 9 Apr 2023 20:19:51 +0200 Subject: [PATCH 1/4] Remove incorrect executable bits on headers Headers don't need executable bits set, especially if it is only done on a handful. Lets drop them. Signed-off-by: Olliver Schinagl --- include/avr/ioa6616c.h | 0 include/avr/iom16hvbrevb.h | 0 include/avr/iom32hvbrevb.h | 0 include/avr/iotn441.h | 0 include/avr/iotn841.h | 0 include/avr/iotn84a.h | 0 6 files changed, 0 insertions(+), 0 deletions(-) mode change 100755 => 100644 include/avr/ioa6616c.h mode change 100755 => 100644 include/avr/iom16hvbrevb.h mode change 100755 => 100644 include/avr/iom32hvbrevb.h mode change 100755 => 100644 include/avr/iotn441.h mode change 100755 => 100644 include/avr/iotn841.h mode change 100755 => 100644 include/avr/iotn84a.h diff --git a/include/avr/ioa6616c.h b/include/avr/ioa6616c.h old mode 100755 new mode 100644 diff --git a/include/avr/iom16hvbrevb.h b/include/avr/iom16hvbrevb.h old mode 100755 new mode 100644 diff --git a/include/avr/iom32hvbrevb.h b/include/avr/iom32hvbrevb.h old mode 100755 new mode 100644 diff --git a/include/avr/iotn441.h b/include/avr/iotn441.h old mode 100755 new mode 100644 diff --git a/include/avr/iotn841.h b/include/avr/iotn841.h old mode 100755 new mode 100644 diff --git a/include/avr/iotn84a.h b/include/avr/iotn84a.h old mode 100755 new mode 100644 From 17837af5a2aff3c8c3100d7b4304e5eb8e5aff8f Mon Sep 17 00:00:00 2001 From: Olliver Schinagl Date: Sun, 9 Apr 2023 20:43:18 +0200 Subject: [PATCH 2/4] io2323: Drop duplicate signatures Having the signature defined outside of the ifguard is probably not a good idea anyway. Signed-off-by: Olliver Schinagl --- include/avr/io2323.h | 6 ------ 1 file changed, 6 deletions(-) diff --git a/include/avr/io2323.h b/include/avr/io2323.h index c7147ba3..3c246dc3 100644 --- a/include/avr/io2323.h +++ b/include/avr/io2323.h @@ -202,9 +202,3 @@ #endif /* _AVR_IO2323_H_ */ - -/* Signature */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x91 -#define SIGNATURE_2 0x02 - From eb54dc867b5a2fc077f3660df24836f35c6e80ab Mon Sep 17 00:00:00 2001 From: Olliver Schinagl Date: Sun, 9 Apr 2023 21:01:46 +0200 Subject: [PATCH 3/4] iom???a: Add missing include guards We should avoid "already included" errors where we can. Signed-off-by: Olliver Schinagl --- include/avr/iom168a.h | 5 +++++ include/avr/iom48a.h | 5 +++++ include/avr/iom88a.h | 5 +++++ 3 files changed, 15 insertions(+) diff --git a/include/avr/iom168a.h b/include/avr/iom168a.h index 8e24416d..f4c105c9 100644 --- a/include/avr/iom168a.h +++ b/include/avr/iom168a.h @@ -31,5 +31,10 @@ * POSSIBILITY OF SUCH DAMAGE. ****************************************************************************/ +#ifndef _AVR_IOM168A_H_ +#define _AVR_IOM168A_H_ 1 + #include "iom168.h" #define SLEEP_MODE_EXT_STANDBY (0x07<<1) + +#endif /* _AVR_IOM168A_H_ */ diff --git a/include/avr/iom48a.h b/include/avr/iom48a.h index 0673f623..1f71b033 100644 --- a/include/avr/iom48a.h +++ b/include/avr/iom48a.h @@ -31,6 +31,11 @@ /* $Id$ */ +#ifndef _AVR_IOM48A_H_ +#define _AVR_IOM48A_H_ 1 + #include "iom48.h" #define SLEEP_MODE_EXT_STANDBY (0x07<<1) + +#endif /* _AVR_IOM48A_H_ */ diff --git a/include/avr/iom88a.h b/include/avr/iom88a.h index 49f2dba2..412b2f74 100644 --- a/include/avr/iom88a.h +++ b/include/avr/iom88a.h @@ -31,5 +31,10 @@ * POSSIBILITY OF SUCH DAMAGE. ****************************************************************************/ +#ifndef _AVR_IOM88A_H_ +#define _AVR_IOM88A_H_ 1 + #include "iom88.h" #define SLEEP_MODE_EXT_STANDBY (0x07<<1) + +#endif /* _AVR_IOM88A_H_ */ From 24c0befddd281797d05ba8e02d6b5a25bf14dcde Mon Sep 17 00:00:00 2001 From: Olliver Schinagl Date: Sun, 9 Apr 2023 23:41:34 +0200 Subject: [PATCH 4/4] cosmetic: Whitespace cleanup Just whitespace changes, no code changes where performed. Most where caught with `git --no-pager log --check --oneline master..HEAD`, something that can be caught in the future in the CI, where 'master' would be replaced with the source branch. Signed-off-by: Olliver Schinagl --- crt1/Makefile.am | 1 - crt1/gcrt1.S | 4 +- include/alloca.h | 2 +- include/avr/boot.h | 38 +- include/avr/common.h | 14 +- include/avr/eeprom.h | 4 +- include/avr/fuse.h | 80 +- include/avr/interrupt.h | 12 +- include/avr/io.h | 20 +- include/avr/io1200.h | 2 +- include/avr/io2313.h | 58 +- include/avr/io2323.h | 2 +- include/avr/io2333.h | 2 +- include/avr/io2343.h | 2 +- include/avr/io43u32x.h | 4 +- include/avr/io43u35x.h | 4 +- include/avr/io4414.h | 2 +- include/avr/io4433.h | 2 +- include/avr/io4434.h | 2 +- include/avr/io76c711.h | 2 +- include/avr/io8515.h | 2 +- include/avr/io8534.h | 2 +- include/avr/io8535.h | 2 +- include/avr/io86r401.h | 2 +- include/avr/io90pwm1.h | 4 +- include/avr/io90pwm161.h | 1 - include/avr/io90pwm216.h | 4 +- include/avr/io90pwm2b.h | 12 +- include/avr/io90pwm316.h | 4 +- include/avr/io90pwm3b.h | 12 +- include/avr/io90pwm81.h | 3 +- include/avr/io90pwmx.h | 4 +- include/avr/io90scr100.h | 3 +- include/avr/ioa5272.h | 1 - include/avr/ioa5505.h | 1 - include/avr/ioa5702m322.h | 5181 ++++++----- include/avr/ioa5782.h | 3685 ++++---- include/avr/ioa5790.h | 1 - include/avr/ioa5790n.h | 1843 ++-- include/avr/ioa5795.h | 1 - include/avr/ioa5831.h | 3897 +++++---- include/avr/ioa6285.h | 1 - include/avr/ioa6286.h | 1 - include/avr/ioa6289.h | 3 +- include/avr/ioa6612c.h | 1589 ++-- include/avr/ioa6613c.h | 1589 ++-- include/avr/ioa6614q.h | 1595 ++-- include/avr/ioa6616c.h | 1729 ++-- include/avr/ioa6617c.h | 1729 ++-- include/avr/ioa664251.h | 1713 ++-- include/avr/ioat94k.h | 42 +- include/avr/ioavr128da28.h | 1 - include/avr/ioavr128da32.h | 1 - include/avr/ioavr128da48.h | 1 - include/avr/ioavr128da64.h | 1 - include/avr/ioavr128db28.h | 1 - include/avr/ioavr128db32.h | 1 - include/avr/ioavr128db48.h | 1 - include/avr/ioavr128db64.h | 1 - include/avr/ioavr16dd14.h | 1 - include/avr/ioavr16dd20.h | 1 - include/avr/ioavr16dd28.h | 1 - include/avr/ioavr16dd32.h | 1 - include/avr/ioavr32da28.h | 1 - include/avr/ioavr32da32.h | 1 - include/avr/ioavr32da48.h | 1 - include/avr/ioavr32db28.h | 1 - include/avr/ioavr32db32.h | 1 - include/avr/ioavr32db48.h | 1 - include/avr/ioavr32dd14.h | 1 - include/avr/ioavr32dd20.h | 1 - include/avr/ioavr32dd28.h | 1 - include/avr/ioavr32dd32.h | 1 - include/avr/ioavr64da28.h | 1 - include/avr/ioavr64da32.h | 1 - include/avr/ioavr64da48.h | 1 - include/avr/ioavr64da64.h | 1 - include/avr/ioavr64db28.h | 1 - include/avr/ioavr64db32.h | 1 - include/avr/ioavr64db48.h | 1 - include/avr/ioavr64db64.h | 1 - include/avr/ioavr64dd14.h | 1 - include/avr/ioavr64dd20.h | 1 - include/avr/ioavr64dd28.h | 1 - include/avr/ioavr64dd32.h | 1 - include/avr/iocan128.h | 2 +- include/avr/iocan32.h | 2 +- include/avr/iocan64.h | 2 +- include/avr/iocanxx.h | 12 +- include/avr/iom103.h | 6 +- include/avr/iom128.h | 26 +- include/avr/iom1280.h | 4 +- include/avr/iom1281.h | 4 +- include/avr/iom1284.h | 1 - include/avr/iom1284p.h | 6 +- include/avr/iom128a.h | 1 - include/avr/iom16.h | 12 +- include/avr/iom1608.h | 3 - include/avr/iom1609.h | 3 - include/avr/iom161.h | 4 +- include/avr/iom162.h | 8 +- include/avr/iom163.h | 4 +- include/avr/iom164.h | 4 +- include/avr/iom164pa.h | 1 - include/avr/iom165.h | 4 +- include/avr/iom165a.h | 1 - include/avr/iom165p.h | 4 +- include/avr/iom165pa.h | 1 - include/avr/iom168.h | 2 +- include/avr/iom168p.h | 10 +- include/avr/iom168pa.h | 1 - include/avr/iom169.h | 6 +- include/avr/iom169p.h | 4 +- include/avr/iom169pa.h | 3 +- include/avr/iom16a.h | 3 +- include/avr/iom16hva.h | 2 +- include/avr/iom16hva2.h | 5 +- include/avr/iom16hvb.h | 5 +- include/avr/iom16hvbrevb.h | 5 +- include/avr/iom16m1.h | 3 +- include/avr/iom16u2.h | 3 +- include/avr/iom16u4.h | 1 - include/avr/iom2560.h | 4 +- include/avr/iom2561.h | 4 +- include/avr/iom3000.h | 5 +- include/avr/iom32.h | 4 +- include/avr/iom3208.h | 3 - include/avr/iom3209.h | 3 - include/avr/iom323.h | 4 +- include/avr/iom324.h | 4 +- include/avr/iom324pa.h | 3 +- include/avr/iom325.h | 4 +- include/avr/iom3250.h | 4 +- include/avr/iom3250pa.h | 1 - include/avr/iom325pa.h | 1 - include/avr/iom328p.h | 8 +- include/avr/iom329.h | 6 +- include/avr/iom3290.h | 6 +- include/avr/iom3290pa.h | 1 - include/avr/iom32a.h | 1 - include/avr/iom32c1.h | 3 +- include/avr/iom32hvb.h | 5 +- include/avr/iom32hvbrevb.h | 4 +- include/avr/iom32m1.h | 3 +- include/avr/iom32u2.h | 3 +- include/avr/iom32u4.h | 2 +- include/avr/iom32u6.h | 3 +- include/avr/iom406.h | 18 +- include/avr/iom4808.h | 3 - include/avr/iom4809.h | 3 - include/avr/iom48a.h | 1 - include/avr/iom48p.h | 8 +- include/avr/iom48pa.h | 1 - include/avr/iom48pb.h | 1779 ++-- include/avr/iom64.h | 32 +- include/avr/iom640.h | 4 +- include/avr/iom644.h | 2 +- include/avr/iom644a.h | 1 - include/avr/iom644p.h | 2 +- include/avr/iom644pa.h | 3 +- include/avr/iom645.h | 4 +- include/avr/iom6450.h | 4 +- include/avr/iom649.h | 6 +- include/avr/iom6490.h | 6 +- include/avr/iom649p.h | 3 +- include/avr/iom64a.h | 1 - include/avr/iom64c1.h | 3 +- include/avr/iom64hve.h | 5 +- include/avr/iom64hve2.h | 1533 ++-- include/avr/iom64m1.h | 3 +- include/avr/iom8.h | 10 +- include/avr/iom808.h | 2 - include/avr/iom809.h | 3 - include/avr/iom8515.h | 4 +- include/avr/iom8535.h | 10 +- include/avr/iom88.h | 2 +- include/avr/iom88p.h | 10 +- include/avr/iom88pa.h | 3 +- include/avr/iom88pb.h | 1797 ++-- include/avr/iom8a.h | 1 - include/avr/iom8hva.h | 3 +- include/avr/iom8u2.h | 3 +- include/avr/iomx8.h | 6 +- include/avr/iomxx0_1.h | 12 +- include/avr/iomxxhva.h | 6 +- include/avr/iotn10.h | 3 +- include/avr/iotn11.h | 2 +- include/avr/iotn12.h | 2 +- include/avr/iotn13.h | 2 +- include/avr/iotn13a.h | 3 +- include/avr/iotn15.h | 2 +- include/avr/iotn1604.h | 3 - include/avr/iotn1606.h | 3 - include/avr/iotn1607.h | 3 - include/avr/iotn1614.h | 3 - include/avr/iotn1616.h | 3 - include/avr/iotn1617.h | 3 - include/avr/iotn1624.h | 3 - include/avr/iotn1626.h | 3 - include/avr/iotn1627.h | 3 - include/avr/iotn1634.h | 1 - include/avr/iotn167.h | 6 +- include/avr/iotn20.h | 3 +- include/avr/iotn202.h | 3 - include/avr/iotn204.h | 3 - include/avr/iotn212.h | 3 - include/avr/iotn214.h | 3 - include/avr/iotn22.h | 2 +- include/avr/iotn2313a.h | 3 +- include/avr/iotn24a.h | 3 +- include/avr/iotn26.h | 2 +- include/avr/iotn261a.h | 3 +- include/avr/iotn28.h | 2 +- include/avr/iotn3214.h | 3 - include/avr/iotn3216.h | 3 - include/avr/iotn3217.h | 3 - include/avr/iotn3224.h | 3 - include/avr/iotn3226.h | 3 - include/avr/iotn3227.h | 3 - include/avr/iotn4.h | 3 +- include/avr/iotn40.h | 3 +- include/avr/iotn402.h | 3 - include/avr/iotn404.h | 3 - include/avr/iotn406.h | 3 - include/avr/iotn412.h | 3 - include/avr/iotn414.h | 3 - include/avr/iotn416.h | 3 - include/avr/iotn417.h | 3 - include/avr/iotn424.h | 3 - include/avr/iotn426.h | 3 - include/avr/iotn427.h | 3 - include/avr/iotn4313.h | 3 +- include/avr/iotn43u.h | 6 +- include/avr/iotn441.h | 1829 ++-- include/avr/iotn44a.h | 3 +- include/avr/iotn461a.h | 3 +- include/avr/iotn48.h | 6 +- include/avr/iotn5.h | 3 +- include/avr/iotn804.h | 3 - include/avr/iotn806.h | 3 - include/avr/iotn807.h | 3 - include/avr/iotn814.h | 3 - include/avr/iotn816.h | 3 - include/avr/iotn817.h | 3 - include/avr/iotn824.h | 3 - include/avr/iotn826.h | 3 - include/avr/iotn827.h | 3 - include/avr/iotn828.h | 1 - include/avr/iotn841.h | 1829 ++-- include/avr/iotn84a.h | 3 +- include/avr/iotn861a.h | 3 +- include/avr/iotn87.h | 3 +- include/avr/iotn88.h | 6 +- include/avr/iotn9.h | 3 +- include/avr/iotnx4.h | 6 +- include/avr/iotnx5.h | 6 +- include/avr/iotnx61.h | 2 +- include/avr/iousb1286.h | 4 +- include/avr/iousb1287.h | 4 +- include/avr/iousb162.h | 2 +- include/avr/iousb646.h | 2 +- include/avr/iousb647.h | 4 +- include/avr/iousb82.h | 2 +- include/avr/iousbxx2.h | 6 +- include/avr/iousbxx6_7.h | 8 +- include/avr/iox128a1.h | 17 +- include/avr/iox128a1u.h | 17 +- include/avr/iox128a3.h | 17 +- include/avr/iox128a3u.h | 1 - include/avr/iox128a4u.h | 1 - include/avr/iox128b1.h | 1 - include/avr/iox128b3.h | 1 - include/avr/iox128c3.h | 1 - include/avr/iox128d3.h | 19 +- include/avr/iox128d4.h | 1 - include/avr/iox16a4.h | 17 +- include/avr/iox16a4u.h | 1 - include/avr/iox16c4.h | 1 - include/avr/iox16d4.h | 19 +- include/avr/iox192a3.h | 17 +- include/avr/iox192a3u.h | 1 - include/avr/iox192c3.h | 1 - include/avr/iox192d3.h | 19 +- include/avr/iox256a3.h | 17 +- include/avr/iox256a3b.h | 17 +- include/avr/iox256a3bu.h | 1 - include/avr/iox256a3u.h | 1 - include/avr/iox256c3.h | 1 - include/avr/iox256d3.h | 19 +- include/avr/iox32a4.h | 17 +- include/avr/iox32a4u.h | 1 - include/avr/iox32c3.h | 12527 ++++++++++++++------------- include/avr/iox32c4.h | 1 - include/avr/iox32d3.h | 10209 +++++++++++----------- include/avr/iox32d4.h | 19 +- include/avr/iox32e5.h | 15397 ++++++++++++++++----------------- include/avr/iox384c3.h | 1 - include/avr/iox384d3.h | 1 - include/avr/iox64a1.h | 17 +- include/avr/iox64a1u.h | 17 +- include/avr/iox64a3.h | 17 +- include/avr/iox64a3u.h | 1 - include/avr/iox64a4u.h | 1 - include/avr/iox64b1.h | 1 - include/avr/iox64b3.h | 1 - include/avr/iox64c3.h | 1 - include/avr/iox64d3.h | 19 +- include/avr/iox64d4.h | 1 - include/avr/iox8e5.h | 15397 ++++++++++++++++----------------- include/avr/lock.h | 90 +- include/avr/pgmspace.h | 116 +- include/avr/power.h | 50 +- include/avr/sfr_defs.h | 6 +- include/avr/signature.h | 14 +- include/avr/sleep.h | 10 +- include/avr/wdt.h | 26 +- include/compat/deprecated.h | 4 +- include/compat/ina90.h | 1 - include/ctype.h | 4 +- include/errno.h | 2 +- include/math.h | 2 +- include/stdio.h | 6 +- include/stdlib.h | 12 +- include/string.h | 3 +- include/util/crc16.h | 10 +- libc/misc/ccp_write.S | 3 +- libc/misc/eerd_block.S | 6 +- libc/misc/eerd_byte.S | 4 +- libc/misc/eewr_block_xmega.c | 1 - libc/misc/eewr_byte.S | 4 +- libc/misc/mul10.S | 4 +- libc/misc/readme_eeprom.txt | 4 +- libc/pmstring/memcmp_P.S | 2 +- libc/pmstring/strncat_P.S | 2 +- libc/stdio/Rules.am | 2 +- libc/stdio/clearerr.c | 2 +- libc/stdio/fgetc.c | 1 - libc/stdio/ultoa_invert.S | 2 +- libc/stdio/ungetc.c | 1 - libc/stdio/vfprintf.c | 22 +- libc/stdio/vfscanf.c | 26 +- libc/stdlib/atoi.S | 8 +- libc/stdlib/atol.S | 2 +- libc/stdlib/ctype.S | 2 +- libc/stdlib/div.S | 1 - libc/stdlib/dtoa_prf.c | 6 +- libc/stdlib/dtostre.c | 8 +- libc/stdlib/ftoa_engine.S | 4 +- libc/stdlib/ldiv.S | 3 +- libc/stdlib/malloc.c | 7 +- libc/stdlib/qsort.c | 1 - libc/stdlib/rand.c | 1 - libc/stdlib/random.c | 1 - libc/stdlib/realloc.c | 1 - libc/stdlib/setjmp.S | 2 +- libc/stdlib/stdlib_private.h | 4 +- libc/stdlib/strtod.c | 16 +- libc/string/ffsll.S | 6 +- libc/string/memmem.S | 6 +- libc/string/strcasestr_P.S | 2 +- libc/string/strrev.S | 2 +- libm/fplib/Files.am | 2 +- libm/fplib/acos.S | 6 +- libm/fplib/asmdef.h | 6 +- libm/fplib/atan2.S | 2 +- libm/fplib/cbrt.S | 2 +- libm/fplib/divsf3x.S | 8 +- libm/fplib/exp.S | 2 +- libm/fplib/fixsfdi.S | 6 +- libm/fplib/fixunssfsi.S | 4 +- libm/fplib/floatsisf.S | 4 +- libm/fplib/floatundisf.S | 4 +- libm/fplib/fma.S | 4 +- libm/fplib/fp_arccos.S | 6 +- libm/fplib/fp_mintl.S | 2 +- libm/fplib/fp_powser.S | 4 +- libm/fplib/fp_powsodd.S | 2 +- libm/fplib/fp_sinus.S | 6 +- libm/fplib/hypot.S | 24 +- libm/fplib/log.S | 10 +- libm/fplib/pow.S | 20 +- libm/fplib/sinh.S | 2 +- libm/fplib/sqrt.S | 4 +- libm/fplib/tan.S | 2 +- libm/fplib/unordsf2.S | 2 +- 385 files changed, 44305 insertions(+), 44615 deletions(-) diff --git a/crt1/Makefile.am b/crt1/Makefile.am index 835f0f44..6ff74866 100644 --- a/crt1/Makefile.am +++ b/crt1/Makefile.am @@ -29,4 +29,3 @@ EXTRA_DIST = gcrt1.S SUBDIRS = iosym DIST_SUBDIRS = iosym - diff --git a/crt1/gcrt1.S b/crt1/gcrt1.S index a84ee186..b4ee0f88 100644 --- a/crt1/gcrt1.S +++ b/crt1/gcrt1.S @@ -373,9 +373,9 @@ __do_copy_data: .balign 4 /* Set REGION_LENGTH symbol values for well known memory regions. - The default linker script uses these symbols to set MEMORY + The default linker script uses these symbols to set MEMORY region lengths, and by defining these here, the linker can detect - memory overflows accurately on a per device basis, since the + memory overflows accurately on a per device basis, since the values are picked up from the device header file. */ diff --git a/include/alloca.h b/include/alloca.h index a213c0c2..790724a5 100644 --- a/include/alloca.h +++ b/include/alloca.h @@ -48,7 +48,7 @@ \return alloca() returns a pointer to the beginning of the allocated space. If the allocation causes stack overflow, program behaviour is undefined. - + \warning Avoid use alloca() inside the list of arguments of a function call. */ diff --git a/include/avr/boot.h b/include/avr/boot.h index eed57291..b3e7016c 100644 --- a/include/avr/boot.h +++ b/include/avr/boot.h @@ -43,8 +43,8 @@ macros are designed to work with all sizes of flash memory. Global interrupts are not automatically disabled for these macros. It - is left up to the programmer to do this. See the code example below. - Also see the processor datasheet for caveats on having global interrupts + is left up to the programmer to do this. See the code example below. + Also see the processor datasheet for caveats on having global interrupts enabled during writing of the Flash. \note Not all AVR processors provide bootloader support. See your @@ -62,7 +62,7 @@ #include #include #include - + void boot_program_page (uint32_t page, uint8_t *buf) { uint16_t i; @@ -72,7 +72,7 @@ sreg = SREG; cli(); - + eeprom_busy_wait (); boot_page_erase (page); @@ -84,7 +84,7 @@ uint16_t w = *buf++; w += (*buf++) << 8; - + boot_page_fill (page + i, w); } @@ -388,11 +388,11 @@ If bits 5..2 in R0 are cleared (zero), the corresponding Boot Lock bit will be programmed if an SPM instruction is executed within four cycles - after BLBSET and SPMEN (or SELFPRGEN) are set in SPMCR. The Z-pointer is - don't care during this operation, but for future compatibility it is - recommended to load the Z-pointer with $0001 (same as used for reading the - Lock bits). For future compatibility It is also recommended to set bits 7, - 6, 1, and 0 in R0 to 1 when writing the Lock bits. When programming the + after BLBSET and SPMEN (or SELFPRGEN) are set in SPMCR. The Z-pointer is + don't care during this operation, but for future compatibility it is + recommended to load the Z-pointer with $0001 (same as used for reading the + Lock bits). For future compatibility It is also recommended to set bits 7, + 6, 1, and 0 in R0 to 1 when writing the Lock bits. When programming the Lock bits the entire Flash can be read during the operation. */ #define __boot_lock_bits_set(lock_bits) \ @@ -437,8 +437,8 @@ /* Reading lock and fuse bits: - Similarly to writing the lock bits above, set BLBSET and SPMEN (or - SELFPRGEN) bits in __SPMREG, and then (within four clock cycles) issue an + Similarly to writing the lock bits above, set BLBSET and SPMEN (or + SELFPRGEN) bits in __SPMREG, and then (within four clock cycles) issue an LPM instruction. Z address: contents: @@ -533,13 +533,13 @@ /** \ingroup avr_boot \def boot_page_fill(address, data) - Fill the bootloader temporary page buffer for flash - address with data word. + Fill the bootloader temporary page buffer for flash + address with data word. - \note The address is a byte address. The data is a word. The AVR + \note The address is a byte address. The data is a word. The AVR writes data to the buffer a word at a time, but addresses the buffer per byte! So, increment your address by 2 between calls, and send 2 - data bytes in a word format! The LSB of the data is written to the lower + data bytes in a word format! The LSB of the data is written to the lower address; the MSB of the data is written to the higher address.*/ /** \ingroup avr_boot @@ -552,9 +552,9 @@ /** \ingroup avr_boot \def boot_page_write(address) - Write the bootloader temporary page buffer + Write the bootloader temporary page buffer to flash page that contains address. - + \note address is a byte address in flash, not a word address. */ /** \ingroup avr_boot @@ -589,7 +589,7 @@ instruction sequences after LPM. FLASHEND is defined in the ioXXXX.h file. - USHRT_MAX is defined in . */ + USHRT_MAX is defined in . */ #if defined(__AVR_ATmega161__) || defined(__AVR_ATmega163__) \ || defined(__AVR_ATmega323__) diff --git a/include/avr/common.h b/include/avr/common.h index 358b3289..ea1a2baa 100644 --- a/include/avr/common.h +++ b/include/avr/common.h @@ -36,9 +36,9 @@ #include -/* -This purpose of this header is to define registers that have not been -previously defined in the individual device IO header files, and to define +/* +This purpose of this header is to define registers that have not been +previously defined in the individual device IO header files, and to define other symbols that are common across AVR device families. This file is designed to be included in after the individual @@ -48,7 +48,7 @@ device IO header files, and after /*------------ Registers Not Previously Defined ------------*/ -/* +/* These are registers that are not previously defined in the individual IO header files, OR they are defined here because they are used in parts of avr-libc even if a device is not selected but a general architecture has @@ -59,7 +59,7 @@ been selected. /* Stack pointer register. -AVR architecture 1 has no RAM, thus no stack pointer. +AVR architecture 1 has no RAM, thus no stack pointer. All other architectures do have a stack pointer. Some devices have only less than 256 bytes of possible RAM locations (128 Bytes of SRAM @@ -76,7 +76,7 @@ for them. # ifndef SP # define SP _SFR_MEM16(0x3D) # endif -#elif __AVR_ARCH__ != 1 +#elif __AVR_ARCH__ != 1 # ifndef SPL # define SPL _SFR_IO8(0x3D) # endif @@ -205,7 +205,7 @@ keep the EEPROM-related definitions here. /*------------ Common Symbols ------------*/ -/* +/* Generic definitions for registers that are common across multiple AVR devices and families. */ diff --git a/include/avr/eeprom.h b/include/avr/eeprom.h index 6f435d3c..7bed1b52 100644 --- a/include/avr/eeprom.h +++ b/include/avr/eeprom.h @@ -82,7 +82,7 @@ them). - All write functions force erase_and_write programming mode. - + - For Xmega the EEPROM start address is 0, like other architectures. The reading functions add the 0x2000 value to use EEPROM mapping into data space. @@ -129,7 +129,7 @@ extern "C" { \ingroup avr_eeprom Loops until the eeprom is no longer busy. \returns Nothing. - */ + */ #define eeprom_busy_wait() do {} while (!eeprom_is_ready()) diff --git a/include/avr/fuse.h b/include/avr/fuse.h index 22888a03..bd5f878d 100644 --- a/include/avr/fuse.h +++ b/include/avr/fuse.h @@ -54,37 +54,37 @@ the ELF file, by extracting this information and determining if the fuses need to be programmed before programming the Flash and EEPROM memories. This also allows a single ELF file to contain all the - information needed to program an AVR. + information needed to program an AVR. To use the Fuse API, include the header file, which in turn automatically includes the individual I/O header file and the file. These other two files provides everything necessary to set the AVR fuses. - + \par Fuse API - + Each I/O header file must define the FUSE_MEMORY_SIZE macro which is defined to the number of fuse bytes that exist in the AVR device. - - A new type, __fuse_t, is defined as a structure. The number of fields in - this structure are determined by the number of fuse bytes in the + + A new type, __fuse_t, is defined as a structure. The number of fields in + this structure are determined by the number of fuse bytes in the FUSE_MEMORY_SIZE macro. - + If FUSE_MEMORY_SIZE == 1, there is only a single field: byte, of type unsigned char. - + If FUSE_MEMORY_SIZE == 2, there are two fields: low, and high, of type unsigned char. - + If FUSE_MEMORY_SIZE == 3, there are three fields: low, high, and extended, of type unsigned char. - + If FUSE_MEMORY_SIZE > 3, there is a single field: byte, which is an array of unsigned char with the size of the array being FUSE_MEMORY_SIZE. - - A convenience macro, FUSEMEM, is defined as a GCC attribute for a + + A convenience macro, FUSEMEM, is defined as a GCC attribute for a custom-named section of ".fuse". - + A convenience macro, FUSES, is defined that declares a variable, __fuse, of type __fuse_t with the attribute defined by FUSEMEM. This variable allows the end user to easily set the fuse data. @@ -102,20 +102,20 @@ \code #define FUSE_EESAVE ~_BV(3) \endcode - \note The _BV macro creates a bit mask from a bit number. It is then + \note The _BV macro creates a bit mask from a bit number. It is then inverted to represent logical values for a fuse memory byte. - + To combine the fuse bits macros together to represent a whole fuse byte, use the bitwise AND operator, like so: \code (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_EESAVE & FUSE_SPIEN & FUSE_JTAGEN) \endcode - + Each device I/O header file also defines macros that provide default values for each fuse byte that is available. LFUSE_DEFAULT is defined for a Low Fuse byte. HFUSE_DEFAULT is defined for a High Fuse byte. EFUSE_DEFAULT is defined for an Extended Fuse byte. - + If FUSE_MEMORY_SIZE > 3, then the I/O header file defines macros that provide default values for each fuse byte like so: FUSE0_DEFAULT @@ -124,15 +124,15 @@ FUSE3_DEFAULT FUSE4_DEFAULT .... - + \par API Usage Example - + Putting all of this together is easy. Using C99's designated initializers: - + \code #include - FUSES = + FUSES = { .low = LFUSE_DEFAULT, .high = (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_EESAVE & FUSE_SPIEN & FUSE_JTAGEN), @@ -144,13 +144,13 @@ return 0; } \endcode - + Or, using the variable directly instead of the FUSES macro, - + \code #include - __fuse_t __fuse __attribute__((section (".fuse"))) = + __fuse_t __fuse __attribute__((section (".fuse"))) = { .low = LFUSE_DEFAULT, .high = (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_EESAVE & FUSE_SPIEN & FUSE_JTAGEN), @@ -162,14 +162,14 @@ return 0; } \endcode - + If you are compiling in C++, you cannot use the designated intializers so you must do: \code #include - FUSES = + FUSES = { LFUSE_DEFAULT, // .low (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_EESAVE & FUSE_SPIEN & FUSE_JTAGEN), // .high @@ -181,33 +181,33 @@ return 0; } \endcode - - + + However there are a number of caveats that you need to be aware of to use this API properly. - + Be sure to include to get all of the definitions for the API. - The FUSES macro defines a global variable to store the fuse data. This - variable is assigned to its own linker section. Assign the desired fuse + The FUSES macro defines a global variable to store the fuse data. This + variable is assigned to its own linker section. Assign the desired fuse values immediately in the variable initialization. - - The .fuse section in the ELF file will get its values from the initial - variable assignment ONLY. This means that you can NOT assign values to + + The .fuse section in the ELF file will get its values from the initial + variable assignment ONLY. This means that you can NOT assign values to this variable in functions and the new values will not be put into the ELF .fuse section. - - The global variable is declared in the FUSES macro has two leading + + The global variable is declared in the FUSES macro has two leading underscores, which means that it is reserved for the "implementation", meaning the library, so it will not conflict with a user-named variable. - + You must initialize ALL fields in the __fuse_t structure. This is because - the fuse bits in all bytes default to a logical 1, meaning unprogrammed. + the fuse bits in all bytes default to a logical 1, meaning unprogrammed. Normal uninitialized data defaults to all locgial zeros. So it is vital that all fuse bytes are initialized, even with default data. If they are not, then the fuse bits may not programmed to the desired settings. - + Be sure to have the -mmcu=device flag in your compile command line and - your linker command line to have the correct device selected and to have + your linker command line to have the correct device selected and to have the correct I/O header file included when you include . You can print out the contents of the .fuse section in the ELF file by diff --git a/include/avr/interrupt.h b/include/avr/interrupt.h index a36e2ba6..48e89843 100644 --- a/include/avr/interrupt.h +++ b/include/avr/interrupt.h @@ -42,9 +42,9 @@ #define __STRINGIFY(x) #x #endif /* !defined(__DOXYGEN__) */ -/** -\file -\@{ +/** +\file +\@{ */ @@ -218,8 +218,8 @@ } ISR_ALIAS(INT1_vect, INT0_vect); - \endcode - + \endcode + */ # define ISR_ALIAS(vector, target_vector) #else /* real code */ @@ -346,7 +346,7 @@ } ISR (INT1_vect, ISR_ALIASOF (INT0_vect)); - \endcode + \endcode */ # define ISR_ALIASOF(target_vector) #else /* !DOXYGEN */ diff --git a/include/avr/io.h b/include/avr/io.h index 2d36d168..43fdd51d 100644 --- a/include/avr/io.h +++ b/include/avr/io.h @@ -45,7 +45,7 @@ but most of the details come from the respective include file. Note that this file always includes the following files: - \code + \code #include #include #include @@ -71,8 +71,8 @@
- \b XRAMEND
- The last possible RAM location that is addressable. This is equal to - RAMEND for devices that do not allow for external RAM. For devices + The last possible RAM location that is addressable. This is equal to + RAMEND for devices that do not allow for external RAM. For devices that allow external RAM, this will be larger than RAMEND.
- \b E2END @@ -86,11 +86,11 @@ - \b SPM_PAGESIZE
For devices with bootloader support, the flash pagesize - (in bytes) to be used for the \c SPM instruction. + (in bytes) to be used for the \c SPM instruction. - \b E2PAGESIZE
The size of the EEPROM page. - + */ #ifndef _AVR_IO_H_ @@ -241,13 +241,13 @@ #elif defined (__AVR_ATmega325P__) # include #elif defined (__AVR_ATmega325PA__) -# include +# include #elif defined (__AVR_ATmega3250__) || defined (__AVR_ATmega3250A__) # include #elif defined (__AVR_ATmega3250P__) # include #elif defined (__AVR_ATmega3250PA__) -# include +# include #elif defined (__AVR_ATmega328P__) || defined (__AVR_ATmega328__) # include #elif defined (__AVR_ATmega329__) || defined (__AVR_ATmega329A__) @@ -259,7 +259,7 @@ #elif defined (__AVR_ATmega3290P__) # include #elif defined (__AVR_ATmega3290PA__) -# include +# include #elif defined (__AVR_ATmega32HVB__) # include #elif defined (__AVR_ATmega32HVBREVB__) @@ -405,9 +405,9 @@ #elif defined (__AVR_ATtiny84__) # include #elif defined (__AVR_ATtiny84A__) -# include +# include #elif defined (__AVR_ATtiny841__) -# include +# include #elif defined (__AVR_ATtiny261__) # include #elif defined (__AVR_ATtiny261A__) diff --git a/include/avr/io1200.h b/include/avr/io1200.h index 0ca99c64..f99acbb0 100644 --- a/include/avr/io1200.h +++ b/include/avr/io1200.h @@ -45,7 +45,7 @@ # define _AVR_IOXXX_H_ "io1200.h" #else # error "Attempt to include more than one file." -#endif +#endif #ifndef __ASSEMBLER__ # warning "MCU not supported by the C compiler" diff --git a/include/avr/io2313.h b/include/avr/io2313.h index 7ec5d165..a92764d9 100644 --- a/include/avr/io2313.h +++ b/include/avr/io2313.h @@ -45,7 +45,7 @@ # define _AVR_IOXXX_H_ "io2313.h" #else # error "Attempt to include more than one file." -#endif +#endif /* I/O registers */ @@ -200,48 +200,48 @@ /* * The Register Bit names are represented by their bit number (0-7). - */ - + */ + /* General Interrupt MaSK register */ #define INT1 7 #define INT0 6 - + /* General Interrupt Flag Register */ #define INTF1 7 #define INTF0 6 - -/* Timer/Counter Interrupt MaSK register */ + +/* Timer/Counter Interrupt MaSK register */ #define TOIE1 7 #define OCIE1A 6 -#define TICIE 3 /* old name */ +#define TICIE 3 /* old name */ #define TICIE1 3 #define TOIE0 1 - -/* Timer/Counter Interrupt Flag register */ + +/* Timer/Counter Interrupt Flag register */ #define TOV1 7 #define OCF1A 6 #define ICF1 3 #define TOV0 1 - -/* MCU general Control Register */ + +/* MCU general Control Register */ #define SE 5 #define SM 4 #define ISC11 3 #define ISC10 2 #define ISC01 1 #define ISC00 0 - + /* Timer/Counter 0 Control Register */ #define CS02 2 #define CS01 1 #define CS00 0 - + /* Timer/Counter 1 Control Register */ #define COM1A1 7 #define COM1A0 6 #define PWM11 1 #define PWM10 0 - + /* Timer/Counter 1 Control and Status Register */ #define ICNC1 7 #define ICES1 6 @@ -249,20 +249,20 @@ #define CS12 2 #define CS11 1 #define CS10 0 - + /* Watchdog Timer Control Register */ #define WDTOE 4 #define WDE 3 #define WDP2 2 #define WDP1 1 #define WDP0 0 - + /* EEPROM Control Register */ #define EEMWE 2 #define EEWE 1 #define EERE 0 - -/* Data Register, Port B */ + +/* Data Register, Port B */ #define PB7 7 #define PB6 6 #define PB5 5 @@ -271,7 +271,7 @@ #define PB2 2 #define PB1 1 #define PB0 0 - + /* Data Direction Register, Port B */ #define DDB7 7 #define DDB6 6 @@ -281,7 +281,7 @@ #define DDB2 2 #define DDB1 1 #define DDB0 0 - + /* Input Pins, Port B */ #define PINB7 7 #define PINB6 6 @@ -291,7 +291,7 @@ #define PINB2 2 #define PINB1 1 #define PINB0 0 - + /* Data Register, Port D */ #define PD6 6 #define PD5 5 @@ -300,7 +300,7 @@ #define PD2 2 #define PD1 1 #define PD0 0 - + /* Data Direction Register, Port D */ #define DDD6 6 #define DDD5 5 @@ -309,7 +309,7 @@ #define DDD2 2 #define DDD1 1 #define DDD0 0 - + /* Input Pins, Port D */ #define PIND6 6 #define PIND5 5 @@ -318,14 +318,14 @@ #define PIND2 2 #define PIND1 1 #define PIND0 0 - + /* UART Status Register */ #define RXC 7 #define TXC 6 #define UDRE 5 #define FE 4 #define DOR 3 - + /* UART Control Register */ #define RXCIE 7 #define TXCIE 6 @@ -335,8 +335,8 @@ #define CHR9 2 #define RXB8 1 #define TXB8 0 - -/* Analog Comparator Control and Status Register */ + +/* Analog Comparator Control and Status Register */ #define ACD 7 #define ACO 5 #define ACI 4 @@ -350,8 +350,8 @@ #define EEMWE 2 #define EEWE 1 #define EERE 0 - -/* Constants */ + +/* Constants */ #define RAMSTART 0x60 #define RAMEND 0xDF #define XRAMEND RAMEND diff --git a/include/avr/io2323.h b/include/avr/io2323.h index 3c246dc3..29e20978 100644 --- a/include/avr/io2323.h +++ b/include/avr/io2323.h @@ -45,7 +45,7 @@ # define _AVR_IOXXX_H_ "io2323.h" #else # error "Attempt to include more than one file." -#endif +#endif /* I/O registers */ diff --git a/include/avr/io2333.h b/include/avr/io2333.h index befa866e..3d631429 100644 --- a/include/avr/io2333.h +++ b/include/avr/io2333.h @@ -45,7 +45,7 @@ # define _AVR_IOXXX_H_ "io2333.h" #else # error "Attempt to include more than one file." -#endif +#endif /* I/O registers */ diff --git a/include/avr/io2343.h b/include/avr/io2343.h index 8fa63667..c72bd072 100644 --- a/include/avr/io2343.h +++ b/include/avr/io2343.h @@ -45,7 +45,7 @@ # define _AVR_IOXXX_H_ "io2343.h" #else # error "Attempt to include more than one file." -#endif +#endif /* I/O registers */ diff --git a/include/avr/io43u32x.h b/include/avr/io43u32x.h index cc9bb955..69330d9e 100644 --- a/include/avr/io43u32x.h +++ b/include/avr/io43u32x.h @@ -45,7 +45,7 @@ # define _AVR_IOXXX_H_ "io43u32x.h" #else # error "Attempt to include more than one file." -#endif +#endif /* I/O registers */ @@ -71,7 +71,7 @@ #define DDRE _SFR_IO8(0x02) /* Data Register, Port E */ -#define PORTE _SFR_IO8(0x03) +#define PORTE _SFR_IO8(0x03) /* SPI Control Register */ #define SPCR _SFR_IO8(0x0D) diff --git a/include/avr/io43u35x.h b/include/avr/io43u35x.h index c590e638..c40c9cf5 100644 --- a/include/avr/io43u35x.h +++ b/include/avr/io43u35x.h @@ -45,7 +45,7 @@ # define _AVR_IOXXX_H_ "io43u35x.h" #else # error "Attempt to include more than one file." -#endif +#endif /* I/O registers */ @@ -417,7 +417,7 @@ #define ADIE 3 #define ADPS2 2 #define ADPS1 1 -#define ADPS0 0 +#define ADPS0 0 /* Constants */ #define RAMSTART 0x60 diff --git a/include/avr/io4414.h b/include/avr/io4414.h index fe3ff3a8..8fd5914a 100644 --- a/include/avr/io4414.h +++ b/include/avr/io4414.h @@ -45,7 +45,7 @@ # define _AVR_IOXXX_H_ "io4414.h" #else # error "Attempt to include more than one file." -#endif +#endif /* I/O registers */ diff --git a/include/avr/io4433.h b/include/avr/io4433.h index 7ab9f3cc..0108242e 100644 --- a/include/avr/io4433.h +++ b/include/avr/io4433.h @@ -45,7 +45,7 @@ # define _AVR_IOXXX_H_ "io4433.h" #else # error "Attempt to include more than one file." -#endif +#endif /* I/O registers */ diff --git a/include/avr/io4434.h b/include/avr/io4434.h index 66831b62..1e36c7d6 100644 --- a/include/avr/io4434.h +++ b/include/avr/io4434.h @@ -45,7 +45,7 @@ # define _AVR_IOXXX_H_ "io4434.h" #else # error "Attempt to include more than one file." -#endif +#endif /* I/O registers */ diff --git a/include/avr/io76c711.h b/include/avr/io76c711.h index db211973..56c2ec2b 100644 --- a/include/avr/io76c711.h +++ b/include/avr/io76c711.h @@ -45,7 +45,7 @@ # define _AVR_IOXXX_H_ "io76c711.h" #else # error "Attempt to include more than one file." -#endif +#endif /* I/O registers */ diff --git a/include/avr/io8515.h b/include/avr/io8515.h index ccb7bdc8..948cb512 100644 --- a/include/avr/io8515.h +++ b/include/avr/io8515.h @@ -45,7 +45,7 @@ # define _AVR_IOXXX_H_ "io8515.h" #else # error "Attempt to include more than one file." -#endif +#endif /* I/O registers */ diff --git a/include/avr/io8534.h b/include/avr/io8534.h index ce1688f9..5c691141 100644 --- a/include/avr/io8534.h +++ b/include/avr/io8534.h @@ -45,7 +45,7 @@ # define _AVR_IOXXX_H_ "io8534.h" #else # error "Attempt to include more than one file." -#endif +#endif /* I/O registers */ diff --git a/include/avr/io8535.h b/include/avr/io8535.h index fe651a7a..af6036fb 100644 --- a/include/avr/io8535.h +++ b/include/avr/io8535.h @@ -45,7 +45,7 @@ # define _AVR_IOXXX_H_ "io8535.h" #else # error "Attempt to include more than one file." -#endif +#endif /* I/O registers */ diff --git a/include/avr/io86r401.h b/include/avr/io86r401.h index 86d99263..f57b2822 100644 --- a/include/avr/io86r401.h +++ b/include/avr/io86r401.h @@ -85,7 +85,7 @@ #define BTCNT _SFR_IO8(0x20) -/* +/* NOTE: EEPROM name's changed to have D in front on them, per datasheet, but you may want to remove the leading D. */ diff --git a/include/avr/io90pwm1.h b/include/avr/io90pwm1.h index bd1b66b4..3679edd4 100644 --- a/include/avr/io90pwm1.h +++ b/include/avr/io90pwm1.h @@ -46,7 +46,7 @@ # define _AVR_IOXXX_H_ "iopwm1.h" #else # error "Attempt to include more than one file." -#endif +#endif /* I/O registers */ @@ -1147,7 +1147,7 @@ /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST -#define __BOOT_LOCK_BITS_1_EXIST +#define __BOOT_LOCK_BITS_1_EXIST #define SLEEP_MODE_IDLE (0x00<<1) diff --git a/include/avr/io90pwm161.h b/include/avr/io90pwm161.h index 4b38548b..cdf2a2c2 100644 --- a/include/avr/io90pwm161.h +++ b/include/avr/io90pwm161.h @@ -871,4 +871,3 @@ #define SLEEP_MODE_STANDBY (0x06<<1) #endif /* #ifdef _AVR_AT90PWM161_H_INCLUDED */ - diff --git a/include/avr/io90pwm216.h b/include/avr/io90pwm216.h index 598af513..12924624 100644 --- a/include/avr/io90pwm216.h +++ b/include/avr/io90pwm216.h @@ -45,7 +45,7 @@ # define _AVR_IOXXX_H_ "io90pwm216.h" #else # error "Attempt to include more than one file." -#endif +#endif /* I/O registers */ @@ -1209,7 +1209,7 @@ /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST -#define __BOOT_LOCK_BITS_1_EXIST +#define __BOOT_LOCK_BITS_1_EXIST /* Signature */ diff --git a/include/avr/io90pwm2b.h b/include/avr/io90pwm2b.h index a3bec894..f0251f40 100644 --- a/include/avr/io90pwm2b.h +++ b/include/avr/io90pwm2b.h @@ -26,7 +26,7 @@ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. + POSSIBILITY OF SUCH DAMAGE. */ /* $Id$ */ @@ -43,7 +43,7 @@ # define _AVR_IOXXX_H_ "io90pwm2b.h" #else # error "Attempt to include more than one file." -#endif +#endif #ifndef _AVR_IO90PWM2B_H_ @@ -80,7 +80,7 @@ #define PORTB5 5 #define PORTB6 6 #define PORTB7 7 - + #define PINC _SFR_IO8(0x06) #define PINC0 0 #define PINC1 1 @@ -828,7 +828,7 @@ #define STP0 0 #define STP1 1 #define F1617 2 -#define FEM 3 +#define FEM 3 #define MUBRR _SFR_MEM16(0xCC) @@ -1433,7 +1433,7 @@ #define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ #define FUSE_DWEN (unsigned char)~_BV(6) /* debugWIRE Enable */ #define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External Reset Disable */ -#define HFUSE_DEFAULT (FUSE_SPIEN) +#define HFUSE_DEFAULT (FUSE_SPIEN) /* Extended Fuse Byte */ @@ -1450,7 +1450,7 @@ /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST -#define __BOOT_LOCK_BITS_1_EXIST +#define __BOOT_LOCK_BITS_1_EXIST /* Signature */ diff --git a/include/avr/io90pwm316.h b/include/avr/io90pwm316.h index c0222358..5244e721 100644 --- a/include/avr/io90pwm316.h +++ b/include/avr/io90pwm316.h @@ -45,7 +45,7 @@ # define _AVR_IOXXX_H_ "io90pwm316.h" #else # error "Attempt to include more than one file." -#endif +#endif /* I/O registers */ @@ -1256,7 +1256,7 @@ /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST -#define __BOOT_LOCK_BITS_1_EXIST +#define __BOOT_LOCK_BITS_1_EXIST /* Signature */ diff --git a/include/avr/io90pwm3b.h b/include/avr/io90pwm3b.h index 39d09c9a..21bc448f 100644 --- a/include/avr/io90pwm3b.h +++ b/include/avr/io90pwm3b.h @@ -26,7 +26,7 @@ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. + POSSIBILITY OF SUCH DAMAGE. */ /* $Id$ */ @@ -43,7 +43,7 @@ # define _AVR_IOXXX_H_ "io90pwm3b.h" #else # error "Attempt to include more than one file." -#endif +#endif #ifndef _AVR_IO90PWM3B_H_ @@ -80,7 +80,7 @@ #define PORTB5 5 #define PORTB6 6 #define PORTB7 7 - + #define PINC _SFR_IO8(0x06) #define PINC0 0 #define PINC1 1 @@ -828,7 +828,7 @@ #define STP0 0 #define STP1 1 #define F1617 2 -#define FEM 3 +#define FEM 3 #define MUBRR _SFR_MEM16(0xCC) @@ -1433,7 +1433,7 @@ #define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ #define FUSE_DWEN (unsigned char)~_BV(6) /* debugWIRE Enable */ #define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External Reset Disable */ -#define HFUSE_DEFAULT (FUSE_SPIEN) +#define HFUSE_DEFAULT (FUSE_SPIEN) /* Extended Fuse Byte */ @@ -1450,7 +1450,7 @@ /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST -#define __BOOT_LOCK_BITS_1_EXIST +#define __BOOT_LOCK_BITS_1_EXIST /* Signature */ diff --git a/include/avr/io90pwm81.h b/include/avr/io90pwm81.h index 13ad1b8b..307f5a38 100644 --- a/include/avr/io90pwm81.h +++ b/include/avr/io90pwm81.h @@ -42,7 +42,7 @@ # define _AVR_IOXXX_H_ "io90pwm81.h" #else # error "Attempt to include more than one file." -#endif +#endif #ifndef _AVR_AT90PWM81_H_ @@ -1035,4 +1035,3 @@ #define SLEEP_MODE_STANDBY (0x06<<1) #endif /* _AVR_AT90PWM81_H_ */ - diff --git a/include/avr/io90pwmx.h b/include/avr/io90pwmx.h index af0a020d..472f4403 100644 --- a/include/avr/io90pwmx.h +++ b/include/avr/io90pwmx.h @@ -45,7 +45,7 @@ # define _AVR_IOXXX_H_ "io90pwmX.h" #else # error "Attempt to include more than one file." -#endif +#endif /* I/O registers */ @@ -1405,7 +1405,7 @@ /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST -#define __BOOT_LOCK_BITS_1_EXIST +#define __BOOT_LOCK_BITS_1_EXIST #define SLEEP_MODE_IDLE (0) diff --git a/include/avr/io90scr100.h b/include/avr/io90scr100.h index 75cd8bfc..01718fa0 100644 --- a/include/avr/io90scr100.h +++ b/include/avr/io90scr100.h @@ -42,7 +42,7 @@ # define _AVR_IOXXX_H_ "io90scr100.h" #else # error "Attempt to include more than one file." -#endif +#endif #ifndef _AVR_AT90SCR100_H_ @@ -1718,4 +1718,3 @@ #define SLEEP_MODE_EXT_STANDBY (_BV(SM0) | _BV(SM1) | _BV(SM2)) #endif /* _AVR_AT90SCR100_H_ */ - diff --git a/include/avr/ioa5272.h b/include/avr/ioa5272.h index 0b2931bb..15b5a31a 100644 --- a/include/avr/ioa5272.h +++ b/include/avr/ioa5272.h @@ -758,4 +758,3 @@ #define SLEEP_MODE_PWR_SAVE (0x03<<1) #endif /* #ifdef _AVR_ATA5272_H_INCLUDED */ - diff --git a/include/avr/ioa5505.h b/include/avr/ioa5505.h index b77ac265..e3308a25 100644 --- a/include/avr/ioa5505.h +++ b/include/avr/ioa5505.h @@ -758,4 +758,3 @@ #define SLEEP_MODE_PWR_SAVE (0x03<<1) #endif /* #ifdef _AVR_ATA5505_H_INCLUDED */ - diff --git a/include/avr/ioa5702m322.h b/include/avr/ioa5702m322.h index 9c0f9e6d..56ecb811 100644 --- a/include/avr/ioa5702m322.h +++ b/include/avr/ioa5702m322.h @@ -1,2591 +1,2590 @@ -/***************************************************************************** - * - * Copyright (C) 2016 Atmel Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * * Neither the name of the copyright holders nor the names of - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************/ - - -#ifndef _AVR_ATA5702M322_H_INCLUDED -#define _AVR_ATA5702M322_H_INCLUDED - - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "ioa5702m322.h" -#else -# error "Attempt to include more than one file." -#endif - -/* Registers and associated bit numbers */ - -#define GPIOR0 _SFR_IO8(0x00) - -#define PRR1 _SFR_IO8(0x01) -#define PRT1 0 -#define PRT2 1 -#define PRT3 2 -#define PRT4 3 -#define PRT5 4 -#define PRLFR 5 -#define PRLFTP 6 -#define PRLFPH 7 - -#define __AVR_HAVE_PRR1 ((1< instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "ioa5702m322.h" +#else +# error "Attempt to include more than one file." +#endif + +/* Registers and associated bit numbers */ + +#define GPIOR0 _SFR_IO8(0x00) + +#define PRR1 _SFR_IO8(0x01) +#define PRT1 0 +#define PRT2 1 +#define PRT3 2 +#define PRT4 3 +#define PRT5 4 +#define PRLFR 5 +#define PRLFTP 6 +#define PRLFPH 7 + +#define __AVR_HAVE_PRR1 ((1< instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "ioa5782.h" -#else -# error "Attempt to include more than one file." -#endif - -/* Registers and associated bit numbers */ - -#define PRR0 _SFR_IO8(0x01) -#define PRSPI 0 -#define PRRXDC 1 -#define PRTXDC 2 -#define PRCRC 3 -#define PRVM 4 -#define PRCO 5 - -#define __AVR_HAVE_PRR0 ((1< instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "ioa5782.h" +#else +# error "Attempt to include more than one file." +#endif + +/* Registers and associated bit numbers */ + +#define PRR0 _SFR_IO8(0x01) +#define PRSPI 0 +#define PRRXDC 1 +#define PRTXDC 2 +#define PRCRC 3 +#define PRVM 4 +#define PRCO 5 + +#define __AVR_HAVE_PRR0 ((1< instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "ioa5790n.h" -#else -# error "Attempt to include more than one file." -#endif - -/* Registers and associated bit numbers */ - -#define PINB _SFR_IO8(0x03) -#define PINB7 7 -#define PINB6 6 -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -#define DDRB _SFR_IO8(0x04) -#define DDRB7 7 -// Inserted "DDB7" from "DDRB7" due to compatibility -#define DDB7 7 -#define DDRB6 6 -// Inserted "DDB6" from "DDRB6" due to compatibility -#define DDB6 6 -#define DDRB5 5 -// Inserted "DDB5" from "DDRB5" due to compatibility -#define DDB5 5 -#define DDRB4 4 -// Inserted "DDB4" from "DDRB4" due to compatibility -#define DDB4 4 -#define DDRB3 3 -// Inserted "DDB3" from "DDRB3" due to compatibility -#define DDB3 3 -#define DDRB2 2 -// Inserted "DDB2" from "DDRB2" due to compatibility -#define DDB2 2 -#define DDRB1 1 -// Inserted "DDB1" from "DDRB1" due to compatibility -#define DDB1 1 -#define DDRB0 0 -// Inserted "DDB0" from "DDRB0" due to compatibility -#define DDB0 0 - -#define PORTB _SFR_IO8(0x05) -#define PORTB7 7 -#define PORTB6 6 -#define PORTB5 5 -#define PORTB4 4 -#define PORTB3 3 -#define PORTB2 2 -#define PORTB1 1 -#define PORTB0 0 - -#define PINC _SFR_IO8(0x06) -#define PINC7 7 -#define PINC6 6 -#define PINC5 5 -#define PINC4 4 -#define PINC3 3 -#define PINC2 2 -#define PINC1 1 -#define PINC0 0 - -#define DDRC _SFR_IO8(0x07) -#define DDRC7 7 -// Inserted "DDC7" from "DDRC7" due to compatibility -#define DDC7 7 -#define DDRC6 6 -// Inserted "DDC6" from "DDRC6" due to compatibility -#define DDC6 6 -#define DDRC5 5 -// Inserted "DDC5" from "DDRC5" due to compatibility -#define DDC5 5 -#define DDRC4 4 -// Inserted "DDC4" from "DDRC4" due to compatibility -#define DDC4 4 -#define DDRC3 3 -// Inserted "DDC3" from "DDRC3" due to compatibility -#define DDC3 3 -#define DDRC2 2 -// Inserted "DDC2" from "DDRC2" due to compatibility -#define DDC2 2 -#define DDRC1 1 -// Inserted "DDC1" from "DDRC1" due to compatibility -#define DDC1 1 -#define DDRC0 0 -// Inserted "DDC0" from "DDRC0" due to compatibility -#define DDC0 0 - -#define PORTC _SFR_IO8(0x08) -#define PORTC7 7 -#define PORTC6 6 -#define PORTC5 5 -#define PORTC4 4 -#define PORTC3 3 -#define PORTC2 2 -#define PORTC1 1 -#define PORTC0 0 - -#define PIND _SFR_IO8(0x09) -#define PIND7 7 -#define PIND6 6 -#define PIND5 5 -#define PIND4 4 -#define PIND3 3 -#define PIND2 2 -#define PIND1 1 -#define PIND0 0 - -#define DDRD _SFR_IO8(0x0A) -#define DDRD7 7 -// Inserted "DDD7" from "DDRD7" due to compatibility -#define DDD7 7 -#define DDRD6 6 -// Inserted "DDD6" from "DDRD6" due to compatibility -#define DDD6 6 -#define DDRD5 5 -// Inserted "DDD5" from "DDRD5" due to compatibility -#define DDD5 5 -#define DDRD4 4 -// Inserted "DDD4" from "DDRD4" due to compatibility -#define DDD4 4 -#define DDRD3 3 -// Inserted "DDD3" from "DDRD3" due to compatibility -#define DDD3 3 -#define DDRD2 2 -// Inserted "DDD2" from "DDRD2" due to compatibility -#define DDD2 2 -#define DDRD1 1 -// Inserted "DDD1" from "DDRD1" due to compatibility -#define DDD1 1 -#define DDRD0 0 -// Inserted "DDD0" from "DDRD0" due to compatibility -#define DDD0 0 - -#define PORTD _SFR_IO8(0x0B) -#define PORTD7 7 -#define PORTD6 6 -#define PORTD5 5 -#define PORTD4 4 -#define PORTD3 3 -#define PORTD2 2 -#define PORTD1 1 -#define PORTD0 0 - -#define T3CR2 _SFR_IO8(0x0C) -#define T3GRES 0 -#define T3C2TM 1 -#define T3C2RM 2 - -#define TPCR _SFR_IO8(0x0D) -#define TPMA 0 -#define TPMOD 1 -#define TPMS0 2 -#define TPMS1 3 -#define TPMD0 4 -#define TPMD1 5 -#define TPPSD 6 -#define TPD 7 - -#define TPFR _SFR_IO8(0x0E) -#define TPF 0 -#define TPA 1 -#define TPGAP 2 -#define TPPSW 3 - -#define CMCR _SFR_IO8(0x0F) -#define CMM0 0 -#define CMM1 1 -#define SRCD 2 -#define CO32D 3 -#define CCS 4 -#define ECINS 5 -#define CMONEN 6 -#define CMCCE 7 - -#define CMSR _SFR_IO8(0x10) -#define ECF 0 -#define SXF 1 -#define RTCF 2 - -#define T2CR _SFR_IO8(0x11) -#define T2OTM 0 -#define T2CTM 1 -#define T2CRM 2 -#define T2GRM 3 -#define T2TOP 4 -#define T2RES 5 -#define T2TS 6 -#define T2E 7 - -#define T3CR _SFR_IO8(0x12) -#define T3OTM 0 -#define T3CTM 1 -#define T3CRM 2 -#define T3CPRM 3 -#define T3TOP 4 -#define T3RES 5 -#define T3CPTM 6 -#define T3E 7 - -#define AESCR _SFR_IO8(0x13) -#define AESWK 0 -#define AESWD 1 -#define AESIM 2 -#define AESD 3 -#define AESXOR 4 -#define AESRES 5 -#define AESE 7 - -#define AESSR _SFR_IO8(0x14) -#define AESRF 0 -#define AESERF 7 - -#define TMIFR _SFR_IO8(0x15) -#define TMRXF 0 -#define TMTXF 1 -#define TMTCF 2 -#define TMRXS 3 -#define TMTXS 4 - -#define VMSR _SFR_IO8(0x16) -#define VMF 0 - -#define PCIFR _SFR_IO8(0x17) -#define PCIF0 0 -#define PCIF1 1 - -#define LFFR _SFR_IO8(0x18) -#define LFID0F 0 -#define LFID1F 1 -#define LFFEF 2 -#define LFDBF 3 -#define LFRSF 4 -#define LFSDF 5 -#define LFMDF 6 -#define LFCAF 7 - -#define T0IFR _SFR_IO8(0x19) -#define T0F 0 - -#define T1IFR _SFR_IO8(0x1A) -#define T1F 0 - -#define T2IFR _SFR_IO8(0x1B) -#define T2OFF 0 -#define T2COF 1 - -#define T3IFR _SFR_IO8(0x1C) -#define T3OFF 0 -#define T3COF 1 -#define T3ICF 2 -#define T3CO2F 3 - -#define EIFR _SFR_IO8(0x1D) -#define INTF0 0 - -#define GPIOR _SFR_IO8(0x1E) - -#define EECR _SFR_IO8(0x1F) -#define EERE 0 -#define EEWE 1 -#define EEMWE 2 -#define EERIE 3 -#define EEPM0 4 -#define EEPM1 5 -#define EELP 6 -#define NVMBSY 7 - -#define EEDR _SFR_IO8(0x20) - -/* Combine EEARL and EEARH */ -#define EEAR _SFR_IO16(0x21) - -#define EEARL _SFR_IO8(0x21) -#define EEARH _SFR_IO8(0x22) - -#define EEPR _SFR_IO8(0x23) -#define EEAP0 0 -#define EEAP1 1 -#define EEAP2 2 -#define EEAP3 3 - -#define EECCR _SFR_IO8(0x24) -#define EEL0 0 -#define EEL1 1 -#define EEL2 2 -#define EEL3 3 - -#define EECR2 _SFR_IO8(0x25) -#define EEBRE 0 -#define EEPAGE 1 - -#define PCICR _SFR_IO8(0x26) -#define PCIE0 0 -#define PCIE1 1 - -#define EIMSK _SFR_IO8(0x27) -#define INT0 0 - -#define TMDR _SFR_IO8(0x28) - -#define AESDR _SFR_IO8(0x29) - -#define AESKR _SFR_IO8(0x2A) -#define AESKR0 0 -#define AESKR1 1 -#define AESKR2 2 -#define AESKR3 3 -#define AESKR4 4 -#define AESKR5 5 -#define AESKR6 6 -#define AESKR7 7 - -#define VMCR _SFR_IO8(0x2B) -#define VMLS0 0 -#define VMLS1 1 -#define VMLS2 2 -#define VMLS3 3 -#define VMIM 4 -#define VMPS 5 -#define BODPD 6 -#define BODLS 7 - -#define SPCR _SFR_IO8(0x2C) -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -#define SPSR _SFR_IO8(0x2D) -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -#define SPDR _SFR_IO8(0x2E) - -#define LFCR0 _SFR_IO8(0x2F) -#define LFCE1 0 -#define LFCE2 1 -#define LFCE3 2 -#define LFBRS 3 -#define LFRBS 4 -#define LFMG 5 -#define LFVC0 6 -#define LFVC1 7 - -#define LFCR1 _SFR_IO8(0x30) -#define LFM0 0 -#define LFM1 1 -#define LFFM0 2 -#define LFFM1 3 -#define LFRMS 4 -#define LFRMSA 5 -#define LFQCE 6 -#define LFRE 7 - -/* Reserved [0x31] */ - -#define LFRDB _SFR_IO8(0x32) - -#define SMCR _SFR_IO8(0x33) -#define SE 0 -#define SM0 1 -#define SM1 2 -#define SM2 3 - -#define MCUSR _SFR_IO8(0x34) -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 -#define TPRF 5 - -#define MCUCR _SFR_IO8(0x35) -#define IVCE 0 -#define IVSEL 1 -#define PUD 4 - -#define LFSR _SFR_IO8(0x36) -#define LFES 0 -#define LFSD 1 - -#define SPMCSR _SFR_IO8(0x37) -#define SPMEN 0 -#define PGERS 1 -#define PGWRT 2 -#define BLBSET 3 -#define RWWSRE 4 -#define SIGRD 5 -#define RWWSB 6 -#define SPMIE 7 - -#define T1CR _SFR_IO8(0x38) -#define T1PS0 0 -#define T1PS1 1 -#define T1IE 2 -#define T1CS0 3 -#define T1CS1 4 -#define T1E 7 - -#define T0CR _SFR_IO8(0x39) -#define T0PS0 0 -#define T0PS1 1 -#define T0PS2 2 -#define T0IE 3 -#define T0PR 4 - -/* Reserved [0x3A] */ - -#define CMIMR _SFR_IO8(0x3B) -#define ECIE 0 -#define SXIE 1 -#define RTCIE 2 - -#define CLKPR _SFR_IO8(0x3C) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPS2 2 -#define CLTPS0 3 -#define CLTPS1 4 -#define CLTPS2 5 -#define CLKPCE 7 - -/* SP [0x3D..0x3E] */ - -/* SREG [0x3F] */ - -#define WDTCR _SFR_MEM8(0x60) -#define WDPS0 0 -#define WDPS1 1 -#define WDPS2 2 -#define WDE 3 -#define WDCE 4 - -/* Reserved [0x61..0x62] */ - -#define PRR0 _SFR_MEM8(0x63) -#define PRLFR 0 -#define PRT1 1 -#define PRT2 2 -#define PRT3 3 -#define PRTM 4 -#define PRCU 5 -#define PRDS 6 -#define PRVM 7 - -#define __AVR_HAVE_PRR0 ((1< instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "ioa5790n.h" +#else +# error "Attempt to include more than one file." +#endif + +/* Registers and associated bit numbers */ + +#define PINB _SFR_IO8(0x03) +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +#define DDRB _SFR_IO8(0x04) +#define DDRB7 7 +// Inserted "DDB7" from "DDRB7" due to compatibility +#define DDB7 7 +#define DDRB6 6 +// Inserted "DDB6" from "DDRB6" due to compatibility +#define DDB6 6 +#define DDRB5 5 +// Inserted "DDB5" from "DDRB5" due to compatibility +#define DDB5 5 +#define DDRB4 4 +// Inserted "DDB4" from "DDRB4" due to compatibility +#define DDB4 4 +#define DDRB3 3 +// Inserted "DDB3" from "DDRB3" due to compatibility +#define DDB3 3 +#define DDRB2 2 +// Inserted "DDB2" from "DDRB2" due to compatibility +#define DDB2 2 +#define DDRB1 1 +// Inserted "DDB1" from "DDRB1" due to compatibility +#define DDB1 1 +#define DDRB0 0 +// Inserted "DDB0" from "DDRB0" due to compatibility +#define DDB0 0 + +#define PORTB _SFR_IO8(0x05) +#define PORTB7 7 +#define PORTB6 6 +#define PORTB5 5 +#define PORTB4 4 +#define PORTB3 3 +#define PORTB2 2 +#define PORTB1 1 +#define PORTB0 0 + +#define PINC _SFR_IO8(0x06) +#define PINC7 7 +#define PINC6 6 +#define PINC5 5 +#define PINC4 4 +#define PINC3 3 +#define PINC2 2 +#define PINC1 1 +#define PINC0 0 + +#define DDRC _SFR_IO8(0x07) +#define DDRC7 7 +// Inserted "DDC7" from "DDRC7" due to compatibility +#define DDC7 7 +#define DDRC6 6 +// Inserted "DDC6" from "DDRC6" due to compatibility +#define DDC6 6 +#define DDRC5 5 +// Inserted "DDC5" from "DDRC5" due to compatibility +#define DDC5 5 +#define DDRC4 4 +// Inserted "DDC4" from "DDRC4" due to compatibility +#define DDC4 4 +#define DDRC3 3 +// Inserted "DDC3" from "DDRC3" due to compatibility +#define DDC3 3 +#define DDRC2 2 +// Inserted "DDC2" from "DDRC2" due to compatibility +#define DDC2 2 +#define DDRC1 1 +// Inserted "DDC1" from "DDRC1" due to compatibility +#define DDC1 1 +#define DDRC0 0 +// Inserted "DDC0" from "DDRC0" due to compatibility +#define DDC0 0 + +#define PORTC _SFR_IO8(0x08) +#define PORTC7 7 +#define PORTC6 6 +#define PORTC5 5 +#define PORTC4 4 +#define PORTC3 3 +#define PORTC2 2 +#define PORTC1 1 +#define PORTC0 0 + +#define PIND _SFR_IO8(0x09) +#define PIND7 7 +#define PIND6 6 +#define PIND5 5 +#define PIND4 4 +#define PIND3 3 +#define PIND2 2 +#define PIND1 1 +#define PIND0 0 + +#define DDRD _SFR_IO8(0x0A) +#define DDRD7 7 +// Inserted "DDD7" from "DDRD7" due to compatibility +#define DDD7 7 +#define DDRD6 6 +// Inserted "DDD6" from "DDRD6" due to compatibility +#define DDD6 6 +#define DDRD5 5 +// Inserted "DDD5" from "DDRD5" due to compatibility +#define DDD5 5 +#define DDRD4 4 +// Inserted "DDD4" from "DDRD4" due to compatibility +#define DDD4 4 +#define DDRD3 3 +// Inserted "DDD3" from "DDRD3" due to compatibility +#define DDD3 3 +#define DDRD2 2 +// Inserted "DDD2" from "DDRD2" due to compatibility +#define DDD2 2 +#define DDRD1 1 +// Inserted "DDD1" from "DDRD1" due to compatibility +#define DDD1 1 +#define DDRD0 0 +// Inserted "DDD0" from "DDRD0" due to compatibility +#define DDD0 0 + +#define PORTD _SFR_IO8(0x0B) +#define PORTD7 7 +#define PORTD6 6 +#define PORTD5 5 +#define PORTD4 4 +#define PORTD3 3 +#define PORTD2 2 +#define PORTD1 1 +#define PORTD0 0 + +#define T3CR2 _SFR_IO8(0x0C) +#define T3GRES 0 +#define T3C2TM 1 +#define T3C2RM 2 + +#define TPCR _SFR_IO8(0x0D) +#define TPMA 0 +#define TPMOD 1 +#define TPMS0 2 +#define TPMS1 3 +#define TPMD0 4 +#define TPMD1 5 +#define TPPSD 6 +#define TPD 7 + +#define TPFR _SFR_IO8(0x0E) +#define TPF 0 +#define TPA 1 +#define TPGAP 2 +#define TPPSW 3 + +#define CMCR _SFR_IO8(0x0F) +#define CMM0 0 +#define CMM1 1 +#define SRCD 2 +#define CO32D 3 +#define CCS 4 +#define ECINS 5 +#define CMONEN 6 +#define CMCCE 7 + +#define CMSR _SFR_IO8(0x10) +#define ECF 0 +#define SXF 1 +#define RTCF 2 + +#define T2CR _SFR_IO8(0x11) +#define T2OTM 0 +#define T2CTM 1 +#define T2CRM 2 +#define T2GRM 3 +#define T2TOP 4 +#define T2RES 5 +#define T2TS 6 +#define T2E 7 + +#define T3CR _SFR_IO8(0x12) +#define T3OTM 0 +#define T3CTM 1 +#define T3CRM 2 +#define T3CPRM 3 +#define T3TOP 4 +#define T3RES 5 +#define T3CPTM 6 +#define T3E 7 + +#define AESCR _SFR_IO8(0x13) +#define AESWK 0 +#define AESWD 1 +#define AESIM 2 +#define AESD 3 +#define AESXOR 4 +#define AESRES 5 +#define AESE 7 + +#define AESSR _SFR_IO8(0x14) +#define AESRF 0 +#define AESERF 7 + +#define TMIFR _SFR_IO8(0x15) +#define TMRXF 0 +#define TMTXF 1 +#define TMTCF 2 +#define TMRXS 3 +#define TMTXS 4 + +#define VMSR _SFR_IO8(0x16) +#define VMF 0 + +#define PCIFR _SFR_IO8(0x17) +#define PCIF0 0 +#define PCIF1 1 + +#define LFFR _SFR_IO8(0x18) +#define LFID0F 0 +#define LFID1F 1 +#define LFFEF 2 +#define LFDBF 3 +#define LFRSF 4 +#define LFSDF 5 +#define LFMDF 6 +#define LFCAF 7 + +#define T0IFR _SFR_IO8(0x19) +#define T0F 0 + +#define T1IFR _SFR_IO8(0x1A) +#define T1F 0 + +#define T2IFR _SFR_IO8(0x1B) +#define T2OFF 0 +#define T2COF 1 + +#define T3IFR _SFR_IO8(0x1C) +#define T3OFF 0 +#define T3COF 1 +#define T3ICF 2 +#define T3CO2F 3 + +#define EIFR _SFR_IO8(0x1D) +#define INTF0 0 + +#define GPIOR _SFR_IO8(0x1E) + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEWE 1 +#define EEMWE 2 +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 +#define EELP 6 +#define NVMBSY 7 + +#define EEDR _SFR_IO8(0x20) + +/* Combine EEARL and EEARH */ +#define EEAR _SFR_IO16(0x21) + +#define EEARL _SFR_IO8(0x21) +#define EEARH _SFR_IO8(0x22) + +#define EEPR _SFR_IO8(0x23) +#define EEAP0 0 +#define EEAP1 1 +#define EEAP2 2 +#define EEAP3 3 + +#define EECCR _SFR_IO8(0x24) +#define EEL0 0 +#define EEL1 1 +#define EEL2 2 +#define EEL3 3 + +#define EECR2 _SFR_IO8(0x25) +#define EEBRE 0 +#define EEPAGE 1 + +#define PCICR _SFR_IO8(0x26) +#define PCIE0 0 +#define PCIE1 1 + +#define EIMSK _SFR_IO8(0x27) +#define INT0 0 + +#define TMDR _SFR_IO8(0x28) + +#define AESDR _SFR_IO8(0x29) + +#define AESKR _SFR_IO8(0x2A) +#define AESKR0 0 +#define AESKR1 1 +#define AESKR2 2 +#define AESKR3 3 +#define AESKR4 4 +#define AESKR5 5 +#define AESKR6 6 +#define AESKR7 7 + +#define VMCR _SFR_IO8(0x2B) +#define VMLS0 0 +#define VMLS1 1 +#define VMLS2 2 +#define VMLS3 3 +#define VMIM 4 +#define VMPS 5 +#define BODPD 6 +#define BODLS 7 + +#define SPCR _SFR_IO8(0x2C) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x2D) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0x2E) + +#define LFCR0 _SFR_IO8(0x2F) +#define LFCE1 0 +#define LFCE2 1 +#define LFCE3 2 +#define LFBRS 3 +#define LFRBS 4 +#define LFMG 5 +#define LFVC0 6 +#define LFVC1 7 + +#define LFCR1 _SFR_IO8(0x30) +#define LFM0 0 +#define LFM1 1 +#define LFFM0 2 +#define LFFM1 3 +#define LFRMS 4 +#define LFRMSA 5 +#define LFQCE 6 +#define LFRE 7 + +/* Reserved [0x31] */ + +#define LFRDB _SFR_IO8(0x32) + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 +#define SM2 3 + +#define MCUSR _SFR_IO8(0x34) +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 +#define TPRF 5 + +#define MCUCR _SFR_IO8(0x35) +#define IVCE 0 +#define IVSEL 1 +#define PUD 4 + +#define LFSR _SFR_IO8(0x36) +#define LFES 0 +#define LFSD 1 + +#define SPMCSR _SFR_IO8(0x37) +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define BLBSET 3 +#define RWWSRE 4 +#define SIGRD 5 +#define RWWSB 6 +#define SPMIE 7 + +#define T1CR _SFR_IO8(0x38) +#define T1PS0 0 +#define T1PS1 1 +#define T1IE 2 +#define T1CS0 3 +#define T1CS1 4 +#define T1E 7 + +#define T0CR _SFR_IO8(0x39) +#define T0PS0 0 +#define T0PS1 1 +#define T0PS2 2 +#define T0IE 3 +#define T0PR 4 + +/* Reserved [0x3A] */ + +#define CMIMR _SFR_IO8(0x3B) +#define ECIE 0 +#define SXIE 1 +#define RTCIE 2 + +#define CLKPR _SFR_IO8(0x3C) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLTPS0 3 +#define CLTPS1 4 +#define CLTPS2 5 +#define CLKPCE 7 + +/* SP [0x3D..0x3E] */ + +/* SREG [0x3F] */ + +#define WDTCR _SFR_MEM8(0x60) +#define WDPS0 0 +#define WDPS1 1 +#define WDPS2 2 +#define WDE 3 +#define WDCE 4 + +/* Reserved [0x61..0x62] */ + +#define PRR0 _SFR_MEM8(0x63) +#define PRLFR 0 +#define PRT1 1 +#define PRT2 2 +#define PRT3 3 +#define PRTM 4 +#define PRCU 5 +#define PRDS 6 +#define PRVM 7 + +#define __AVR_HAVE_PRR0 ((1< instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "ioa5831.h" -#else -# error "Attempt to include more than one file." -#endif - -/* Registers and associated bit numbers */ - -#define PRR0 _SFR_IO8(0x01) -#define PRSPI 0 -#define PRRXDC 1 -#define PRTXDC 2 -#define PRCRC 3 -#define PRVM 4 -#define PRCO 5 - -#define __AVR_HAVE_PRR0 ((1< instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "ioa5831.h" +#else +# error "Attempt to include more than one file." +#endif + +/* Registers and associated bit numbers */ + +#define PRR0 _SFR_IO8(0x01) +#define PRSPI 0 +#define PRRXDC 1 +#define PRTXDC 2 +#define PRCRC 3 +#define PRVM 4 +#define PRCO 5 + +#define __AVR_HAVE_PRR0 ((1< file." -#endif +#endif #ifndef _AVR_ATA6289_H_ @@ -846,4 +846,3 @@ #define SLEEP_MODE_PWR_DOWN (_BV(SM1)) #endif /* _AVR_ATA6289_H_ */ - diff --git a/include/avr/ioa6612c.h b/include/avr/ioa6612c.h index 1fc43300..f6a411f8 100644 --- a/include/avr/ioa6612c.h +++ b/include/avr/ioa6612c.h @@ -1,795 +1,794 @@ -/***************************************************************************** - * - * Copyright (C) 2016 Atmel Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * * Neither the name of the copyright holders nor the names of - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************/ - - -#ifndef _AVR_ATA6612C_H_INCLUDED -#define _AVR_ATA6612C_H_INCLUDED - - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "ioa6612c.h" -#else -# error "Attempt to include more than one file." -#endif - -/* Registers and associated bit numbers */ - -#define PINB _SFR_IO8(0x03) -#define PINB7 7 -#define PINB6 6 -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -#define DDRB _SFR_IO8(0x04) -#define DDB0 0 -#define DDB1 1 -#define DDB2 2 -#define DDB3 3 -#define DDB4 4 -#define DDB5 5 -#define DDB6 6 -#define DDB7 7 - -#define PORTB _SFR_IO8(0x05) -#define PORTB7 7 -#define PORTB6 6 -#define PORTB5 5 -#define PORTB4 4 -#define PORTB3 3 -#define PORTB2 2 -#define PORTB1 1 -#define PORTB0 0 - -#define PINC _SFR_IO8(0x06) -#define PINC6 6 -#define PINC5 5 -#define PINC4 4 -#define PINC3 3 -#define PINC2 2 -#define PINC1 1 -#define PINC0 0 - -#define DDRC _SFR_IO8(0x07) -#define DDC0 0 -#define DDC1 1 -#define DDC2 2 -#define DDC3 3 -#define DDC4 4 -#define DDC5 5 -#define DDC6 6 - -#define PORTC _SFR_IO8(0x08) -#define PORTC6 6 -#define PORTC5 5 -#define PORTC4 4 -#define PORTC3 3 -#define PORTC2 2 -#define PORTC1 1 -#define PORTC0 0 - -#define PIND _SFR_IO8(0x09) -#define PIND7 7 -#define PIND6 6 -#define PIND5 5 -#define PIND4 4 -#define PIND3 3 -#define PIND2 2 -#define PIND1 1 -#define PIND0 0 - -#define DDRD _SFR_IO8(0x0A) -#define DDD0 0 -#define DDD1 1 -#define DDD2 2 -#define DDD3 3 -#define DDD4 4 -#define DDD5 5 -#define DDD6 6 -#define DDD7 7 - -#define PORTD _SFR_IO8(0x0B) -#define PORTD7 7 -#define PORTD6 6 -#define PORTD5 5 -#define PORTD4 4 -#define PORTD3 3 -#define PORTD2 2 -#define PORTD1 1 -#define PORTD0 0 - -/* Reserved [0x0C..0x14] */ - -#define TIFR0 _SFR_IO8(0x15) -#define TOV0 0 -#define OCF0A 1 -#define OCF0B 2 - -#define TIFR1 _SFR_IO8(0x16) -#define TOV1 0 -#define OCF1A 1 -#define OCF1B 2 -#define ICF1 5 - -#define TIFR2 _SFR_IO8(0x17) -#define TOV2 0 -#define OCF2A 1 -#define OCF2B 2 - -/* Reserved [0x18..0x1A] */ - -#define PCIFR _SFR_IO8(0x1B) -#define PCIF0 0 -#define PCIF1 1 -#define PCIF2 2 - -#define EIFR _SFR_IO8(0x1C) -#define INTF0 0 -#define INTF1 1 - -#define EIMSK _SFR_IO8(0x1D) -#define INT0 0 -#define INT1 1 - -#define GPIOR0 _SFR_IO8(0x1E) - -#define EECR _SFR_IO8(0x1F) -#define EERE 0 -#define EEPE 1 -#define EEMPE 2 -#define EERIE 3 -#define EEPM0 4 -#define EEPM1 5 - -#define EEDR _SFR_IO8(0x20) - -/* Combine EEARL and EEARH */ -#define EEAR _SFR_IO16(0x21) - -#define EEARL _SFR_IO8(0x21) -#define EEARH _SFR_IO8(0x22) - -#define GTCCR _SFR_IO8(0x23) -#define PSRSYNC 0 -#define TSM 7 -#define PSRASY 1 - -#define TCCR0A _SFR_IO8(0x24) -#define WGM00 0 -#define WGM01 1 -#define COM0B0 4 -#define COM0B1 5 -#define COM0A0 6 -#define COM0A1 7 - -#define TCCR0B _SFR_IO8(0x25) -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define WGM02 3 -#define FOC0B 6 -#define FOC0A 7 - -#define TCNT0 _SFR_IO8(0x26) - -#define OCR0A _SFR_IO8(0x27) - -#define OCR0B _SFR_IO8(0x28) - -/* Reserved [0x29] */ - -#define GPIOR1 _SFR_IO8(0x2A) - -#define GPIOR2 _SFR_IO8(0x2B) - -#define SPCR _SFR_IO8(0x2C) -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -#define SPSR _SFR_IO8(0x2D) -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -#define SPDR _SFR_IO8(0x2E) - -/* Reserved [0x2F] */ - -#define ACSR _SFR_IO8(0x30) -#define ACIS0 0 -#define ACIS1 1 -#define ACIC 2 -#define ACIE 3 -#define ACI 4 -#define ACO 5 -#define ACBG 6 -#define ACD 7 - -/* Reserved [0x31..0x32] */ - -#define SMCR _SFR_IO8(0x33) -#define SE 0 -#define SM0 1 -#define SM1 2 -#define SM2 3 - -#define MCUSR _SFR_IO8(0x34) -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 - -#define MCUCR _SFR_IO8(0x35) -#define IVCE 0 -#define IVSEL 1 -#define PUD 4 - -/* Reserved [0x36] */ - -#define SPMCSR _SFR_IO8(0x37) -#define SELFPRGEN 0 -#define PGERS 1 -#define PGWRT 2 -#define BLBSET 3 -#define RWWSRE 4 -#define RWWSB 6 -#define SPMIE 7 - -/* Reserved [0x38..0x3C] */ - -/* SP [0x3D..0x3E] */ - -/* SREG [0x3F] */ - -#define WDTCSR _SFR_MEM8(0x60) -#define WDE 3 -#define WDCE 4 -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDP3 5 -#define WDIE 6 -#define WDIF 7 - -#define CLKPR _SFR_MEM8(0x61) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPS2 2 -#define CLKPS3 3 -#define CLKPCE 7 - -/* Reserved [0x62..0x63] */ - -#define PRR _SFR_MEM8(0x64) -#define PRADC 0 -#define PRUSART0 1 -#define PRSPI 2 -#define PRTIM1 3 -#define PRTIM0 5 -#define PRTIM2 6 -#define PRTWI 7 - -#define __AVR_HAVE_PRR ((1< instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "ioa6612c.h" +#else +# error "Attempt to include more than one file." +#endif + +/* Registers and associated bit numbers */ + +#define PINB _SFR_IO8(0x03) +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +#define DDRB _SFR_IO8(0x04) +#define DDB0 0 +#define DDB1 1 +#define DDB2 2 +#define DDB3 3 +#define DDB4 4 +#define DDB5 5 +#define DDB6 6 +#define DDB7 7 + +#define PORTB _SFR_IO8(0x05) +#define PORTB7 7 +#define PORTB6 6 +#define PORTB5 5 +#define PORTB4 4 +#define PORTB3 3 +#define PORTB2 2 +#define PORTB1 1 +#define PORTB0 0 + +#define PINC _SFR_IO8(0x06) +#define PINC6 6 +#define PINC5 5 +#define PINC4 4 +#define PINC3 3 +#define PINC2 2 +#define PINC1 1 +#define PINC0 0 + +#define DDRC _SFR_IO8(0x07) +#define DDC0 0 +#define DDC1 1 +#define DDC2 2 +#define DDC3 3 +#define DDC4 4 +#define DDC5 5 +#define DDC6 6 + +#define PORTC _SFR_IO8(0x08) +#define PORTC6 6 +#define PORTC5 5 +#define PORTC4 4 +#define PORTC3 3 +#define PORTC2 2 +#define PORTC1 1 +#define PORTC0 0 + +#define PIND _SFR_IO8(0x09) +#define PIND7 7 +#define PIND6 6 +#define PIND5 5 +#define PIND4 4 +#define PIND3 3 +#define PIND2 2 +#define PIND1 1 +#define PIND0 0 + +#define DDRD _SFR_IO8(0x0A) +#define DDD0 0 +#define DDD1 1 +#define DDD2 2 +#define DDD3 3 +#define DDD4 4 +#define DDD5 5 +#define DDD6 6 +#define DDD7 7 + +#define PORTD _SFR_IO8(0x0B) +#define PORTD7 7 +#define PORTD6 6 +#define PORTD5 5 +#define PORTD4 4 +#define PORTD3 3 +#define PORTD2 2 +#define PORTD1 1 +#define PORTD0 0 + +/* Reserved [0x0C..0x14] */ + +#define TIFR0 _SFR_IO8(0x15) +#define TOV0 0 +#define OCF0A 1 +#define OCF0B 2 + +#define TIFR1 _SFR_IO8(0x16) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define ICF1 5 + +#define TIFR2 _SFR_IO8(0x17) +#define TOV2 0 +#define OCF2A 1 +#define OCF2B 2 + +/* Reserved [0x18..0x1A] */ + +#define PCIFR _SFR_IO8(0x1B) +#define PCIF0 0 +#define PCIF1 1 +#define PCIF2 2 + +#define EIFR _SFR_IO8(0x1C) +#define INTF0 0 +#define INTF1 1 + +#define EIMSK _SFR_IO8(0x1D) +#define INT0 0 +#define INT1 1 + +#define GPIOR0 _SFR_IO8(0x1E) + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEPE 1 +#define EEMPE 2 +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 + +#define EEDR _SFR_IO8(0x20) + +/* Combine EEARL and EEARH */ +#define EEAR _SFR_IO16(0x21) + +#define EEARL _SFR_IO8(0x21) +#define EEARH _SFR_IO8(0x22) + +#define GTCCR _SFR_IO8(0x23) +#define PSRSYNC 0 +#define TSM 7 +#define PSRASY 1 + +#define TCCR0A _SFR_IO8(0x24) +#define WGM00 0 +#define WGM01 1 +#define COM0B0 4 +#define COM0B1 5 +#define COM0A0 6 +#define COM0A1 7 + +#define TCCR0B _SFR_IO8(0x25) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define WGM02 3 +#define FOC0B 6 +#define FOC0A 7 + +#define TCNT0 _SFR_IO8(0x26) + +#define OCR0A _SFR_IO8(0x27) + +#define OCR0B _SFR_IO8(0x28) + +/* Reserved [0x29] */ + +#define GPIOR1 _SFR_IO8(0x2A) + +#define GPIOR2 _SFR_IO8(0x2B) + +#define SPCR _SFR_IO8(0x2C) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x2D) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0x2E) + +/* Reserved [0x2F] */ + +#define ACSR _SFR_IO8(0x30) +#define ACIS0 0 +#define ACIS1 1 +#define ACIC 2 +#define ACIE 3 +#define ACI 4 +#define ACO 5 +#define ACBG 6 +#define ACD 7 + +/* Reserved [0x31..0x32] */ + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 +#define SM2 3 + +#define MCUSR _SFR_IO8(0x34) +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 + +#define MCUCR _SFR_IO8(0x35) +#define IVCE 0 +#define IVSEL 1 +#define PUD 4 + +/* Reserved [0x36] */ + +#define SPMCSR _SFR_IO8(0x37) +#define SELFPRGEN 0 +#define PGERS 1 +#define PGWRT 2 +#define BLBSET 3 +#define RWWSRE 4 +#define RWWSB 6 +#define SPMIE 7 + +/* Reserved [0x38..0x3C] */ + +/* SP [0x3D..0x3E] */ + +/* SREG [0x3F] */ + +#define WDTCSR _SFR_MEM8(0x60) +#define WDE 3 +#define WDCE 4 +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDP3 5 +#define WDIE 6 +#define WDIF 7 + +#define CLKPR _SFR_MEM8(0x61) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLKPS3 3 +#define CLKPCE 7 + +/* Reserved [0x62..0x63] */ + +#define PRR _SFR_MEM8(0x64) +#define PRADC 0 +#define PRUSART0 1 +#define PRSPI 2 +#define PRTIM1 3 +#define PRTIM0 5 +#define PRTIM2 6 +#define PRTWI 7 + +#define __AVR_HAVE_PRR ((1< instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "ioa6613c.h" -#else -# error "Attempt to include more than one file." -#endif - -/* Registers and associated bit numbers */ - -#define PINB _SFR_IO8(0x03) -#define PINB7 7 -#define PINB6 6 -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -#define DDRB _SFR_IO8(0x04) -#define DDB0 0 -#define DDB1 1 -#define DDB2 2 -#define DDB3 3 -#define DDB4 4 -#define DDB5 5 -#define DDB6 6 -#define DDB7 7 - -#define PORTB _SFR_IO8(0x05) -#define PORTB7 7 -#define PORTB6 6 -#define PORTB5 5 -#define PORTB4 4 -#define PORTB3 3 -#define PORTB2 2 -#define PORTB1 1 -#define PORTB0 0 - -#define PINC _SFR_IO8(0x06) -#define PINC6 6 -#define PINC5 5 -#define PINC4 4 -#define PINC3 3 -#define PINC2 2 -#define PINC1 1 -#define PINC0 0 - -#define DDRC _SFR_IO8(0x07) -#define DDC0 0 -#define DDC1 1 -#define DDC2 2 -#define DDC3 3 -#define DDC4 4 -#define DDC5 5 -#define DDC6 6 - -#define PORTC _SFR_IO8(0x08) -#define PORTC6 6 -#define PORTC5 5 -#define PORTC4 4 -#define PORTC3 3 -#define PORTC2 2 -#define PORTC1 1 -#define PORTC0 0 - -#define PIND _SFR_IO8(0x09) -#define PIND7 7 -#define PIND6 6 -#define PIND5 5 -#define PIND4 4 -#define PIND3 3 -#define PIND2 2 -#define PIND1 1 -#define PIND0 0 - -#define DDRD _SFR_IO8(0x0A) -#define DDD0 0 -#define DDD1 1 -#define DDD2 2 -#define DDD3 3 -#define DDD4 4 -#define DDD5 5 -#define DDD6 6 -#define DDD7 7 - -#define PORTD _SFR_IO8(0x0B) -#define PORTD7 7 -#define PORTD6 6 -#define PORTD5 5 -#define PORTD4 4 -#define PORTD3 3 -#define PORTD2 2 -#define PORTD1 1 -#define PORTD0 0 - -/* Reserved [0x0C..0x14] */ - -#define TIFR0 _SFR_IO8(0x15) -#define TOV0 0 -#define OCF0A 1 -#define OCF0B 2 - -#define TIFR1 _SFR_IO8(0x16) -#define TOV1 0 -#define OCF1A 1 -#define OCF1B 2 -#define ICF1 5 - -#define TIFR2 _SFR_IO8(0x17) -#define TOV2 0 -#define OCF2A 1 -#define OCF2B 2 - -/* Reserved [0x18..0x1A] */ - -#define PCIFR _SFR_IO8(0x1B) -#define PCIF0 0 -#define PCIF1 1 -#define PCIF2 2 - -#define EIFR _SFR_IO8(0x1C) -#define INTF0 0 -#define INTF1 1 - -#define EIMSK _SFR_IO8(0x1D) -#define INT0 0 -#define INT1 1 - -#define GPIOR0 _SFR_IO8(0x1E) - -#define EECR _SFR_IO8(0x1F) -#define EERE 0 -#define EEPE 1 -#define EEMPE 2 -#define EERIE 3 -#define EEPM0 4 -#define EEPM1 5 - -#define EEDR _SFR_IO8(0x20) - -/* Combine EEARL and EEARH */ -#define EEAR _SFR_IO16(0x21) - -#define EEARL _SFR_IO8(0x21) -#define EEARH _SFR_IO8(0x22) - -#define GTCCR _SFR_IO8(0x23) -#define PSRSYNC 0 -#define TSM 7 -#define PSRASY 1 - -#define TCCR0A _SFR_IO8(0x24) -#define WGM00 0 -#define WGM01 1 -#define COM0B0 4 -#define COM0B1 5 -#define COM0A0 6 -#define COM0A1 7 - -#define TCCR0B _SFR_IO8(0x25) -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define WGM02 3 -#define FOC0B 6 -#define FOC0A 7 - -#define TCNT0 _SFR_IO8(0x26) - -#define OCR0A _SFR_IO8(0x27) - -#define OCR0B _SFR_IO8(0x28) - -/* Reserved [0x29] */ - -#define GPIOR1 _SFR_IO8(0x2A) - -#define GPIOR2 _SFR_IO8(0x2B) - -#define SPCR _SFR_IO8(0x2C) -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -#define SPSR _SFR_IO8(0x2D) -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -#define SPDR _SFR_IO8(0x2E) - -/* Reserved [0x2F] */ - -#define ACSR _SFR_IO8(0x30) -#define ACIS0 0 -#define ACIS1 1 -#define ACIC 2 -#define ACIE 3 -#define ACI 4 -#define ACO 5 -#define ACBG 6 -#define ACD 7 - -/* Reserved [0x31..0x32] */ - -#define SMCR _SFR_IO8(0x33) -#define SE 0 -#define SM0 1 -#define SM1 2 -#define SM2 3 - -#define MCUSR _SFR_IO8(0x34) -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 - -#define MCUCR _SFR_IO8(0x35) -#define IVCE 0 -#define IVSEL 1 -#define PUD 4 - -/* Reserved [0x36] */ - -#define SPMCSR _SFR_IO8(0x37) -#define SELFPRGEN 0 -#define PGERS 1 -#define PGWRT 2 -#define BLBSET 3 -#define RWWSRE 4 -#define RWWSB 6 -#define SPMIE 7 - -/* Reserved [0x38..0x3C] */ - -/* SP [0x3D..0x3E] */ - -/* SREG [0x3F] */ - -#define WDTCSR _SFR_MEM8(0x60) -#define WDE 3 -#define WDCE 4 -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDP3 5 -#define WDIE 6 -#define WDIF 7 - -#define CLKPR _SFR_MEM8(0x61) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPS2 2 -#define CLKPS3 3 -#define CLKPCE 7 - -/* Reserved [0x62..0x63] */ - -#define PRR _SFR_MEM8(0x64) -#define PRADC 0 -#define PRUSART0 1 -#define PRSPI 2 -#define PRTIM1 3 -#define PRTIM0 5 -#define PRTIM2 6 -#define PRTWI 7 - -#define __AVR_HAVE_PRR ((1< instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "ioa6613c.h" +#else +# error "Attempt to include more than one file." +#endif + +/* Registers and associated bit numbers */ + +#define PINB _SFR_IO8(0x03) +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +#define DDRB _SFR_IO8(0x04) +#define DDB0 0 +#define DDB1 1 +#define DDB2 2 +#define DDB3 3 +#define DDB4 4 +#define DDB5 5 +#define DDB6 6 +#define DDB7 7 + +#define PORTB _SFR_IO8(0x05) +#define PORTB7 7 +#define PORTB6 6 +#define PORTB5 5 +#define PORTB4 4 +#define PORTB3 3 +#define PORTB2 2 +#define PORTB1 1 +#define PORTB0 0 + +#define PINC _SFR_IO8(0x06) +#define PINC6 6 +#define PINC5 5 +#define PINC4 4 +#define PINC3 3 +#define PINC2 2 +#define PINC1 1 +#define PINC0 0 + +#define DDRC _SFR_IO8(0x07) +#define DDC0 0 +#define DDC1 1 +#define DDC2 2 +#define DDC3 3 +#define DDC4 4 +#define DDC5 5 +#define DDC6 6 + +#define PORTC _SFR_IO8(0x08) +#define PORTC6 6 +#define PORTC5 5 +#define PORTC4 4 +#define PORTC3 3 +#define PORTC2 2 +#define PORTC1 1 +#define PORTC0 0 + +#define PIND _SFR_IO8(0x09) +#define PIND7 7 +#define PIND6 6 +#define PIND5 5 +#define PIND4 4 +#define PIND3 3 +#define PIND2 2 +#define PIND1 1 +#define PIND0 0 + +#define DDRD _SFR_IO8(0x0A) +#define DDD0 0 +#define DDD1 1 +#define DDD2 2 +#define DDD3 3 +#define DDD4 4 +#define DDD5 5 +#define DDD6 6 +#define DDD7 7 + +#define PORTD _SFR_IO8(0x0B) +#define PORTD7 7 +#define PORTD6 6 +#define PORTD5 5 +#define PORTD4 4 +#define PORTD3 3 +#define PORTD2 2 +#define PORTD1 1 +#define PORTD0 0 + +/* Reserved [0x0C..0x14] */ + +#define TIFR0 _SFR_IO8(0x15) +#define TOV0 0 +#define OCF0A 1 +#define OCF0B 2 + +#define TIFR1 _SFR_IO8(0x16) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define ICF1 5 + +#define TIFR2 _SFR_IO8(0x17) +#define TOV2 0 +#define OCF2A 1 +#define OCF2B 2 + +/* Reserved [0x18..0x1A] */ + +#define PCIFR _SFR_IO8(0x1B) +#define PCIF0 0 +#define PCIF1 1 +#define PCIF2 2 + +#define EIFR _SFR_IO8(0x1C) +#define INTF0 0 +#define INTF1 1 + +#define EIMSK _SFR_IO8(0x1D) +#define INT0 0 +#define INT1 1 + +#define GPIOR0 _SFR_IO8(0x1E) + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEPE 1 +#define EEMPE 2 +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 + +#define EEDR _SFR_IO8(0x20) + +/* Combine EEARL and EEARH */ +#define EEAR _SFR_IO16(0x21) + +#define EEARL _SFR_IO8(0x21) +#define EEARH _SFR_IO8(0x22) + +#define GTCCR _SFR_IO8(0x23) +#define PSRSYNC 0 +#define TSM 7 +#define PSRASY 1 + +#define TCCR0A _SFR_IO8(0x24) +#define WGM00 0 +#define WGM01 1 +#define COM0B0 4 +#define COM0B1 5 +#define COM0A0 6 +#define COM0A1 7 + +#define TCCR0B _SFR_IO8(0x25) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define WGM02 3 +#define FOC0B 6 +#define FOC0A 7 + +#define TCNT0 _SFR_IO8(0x26) + +#define OCR0A _SFR_IO8(0x27) + +#define OCR0B _SFR_IO8(0x28) + +/* Reserved [0x29] */ + +#define GPIOR1 _SFR_IO8(0x2A) + +#define GPIOR2 _SFR_IO8(0x2B) + +#define SPCR _SFR_IO8(0x2C) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x2D) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0x2E) + +/* Reserved [0x2F] */ + +#define ACSR _SFR_IO8(0x30) +#define ACIS0 0 +#define ACIS1 1 +#define ACIC 2 +#define ACIE 3 +#define ACI 4 +#define ACO 5 +#define ACBG 6 +#define ACD 7 + +/* Reserved [0x31..0x32] */ + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 +#define SM2 3 + +#define MCUSR _SFR_IO8(0x34) +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 + +#define MCUCR _SFR_IO8(0x35) +#define IVCE 0 +#define IVSEL 1 +#define PUD 4 + +/* Reserved [0x36] */ + +#define SPMCSR _SFR_IO8(0x37) +#define SELFPRGEN 0 +#define PGERS 1 +#define PGWRT 2 +#define BLBSET 3 +#define RWWSRE 4 +#define RWWSB 6 +#define SPMIE 7 + +/* Reserved [0x38..0x3C] */ + +/* SP [0x3D..0x3E] */ + +/* SREG [0x3F] */ + +#define WDTCSR _SFR_MEM8(0x60) +#define WDE 3 +#define WDCE 4 +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDP3 5 +#define WDIE 6 +#define WDIF 7 + +#define CLKPR _SFR_MEM8(0x61) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLKPS3 3 +#define CLKPCE 7 + +/* Reserved [0x62..0x63] */ + +#define PRR _SFR_MEM8(0x64) +#define PRADC 0 +#define PRUSART0 1 +#define PRSPI 2 +#define PRTIM1 3 +#define PRTIM0 5 +#define PRTIM2 6 +#define PRTWI 7 + +#define __AVR_HAVE_PRR ((1< instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "ioa6614q.h" -#else -# error "Attempt to include more than one file." -#endif - -/* Registers and associated bit numbers */ - -#define PINB _SFR_IO8(0x03) -#define PINB7 7 -#define PINB6 6 -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -#define DDRB _SFR_IO8(0x04) -#define DDB0 0 -#define DDB1 1 -#define DDB2 2 -#define DDB3 3 -#define DDB4 4 -#define DDB5 5 -#define DDB6 6 -#define DDB7 7 - -#define PORTB _SFR_IO8(0x05) -#define PORTB7 7 -#define PORTB6 6 -#define PORTB5 5 -#define PORTB4 4 -#define PORTB3 3 -#define PORTB2 2 -#define PORTB1 1 -#define PORTB0 0 - -#define PINC _SFR_IO8(0x06) -#define PINC6 6 -#define PINC5 5 -#define PINC4 4 -#define PINC3 3 -#define PINC2 2 -#define PINC1 1 -#define PINC0 0 - -#define DDRC _SFR_IO8(0x07) -#define DDC0 0 -#define DDC1 1 -#define DDC2 2 -#define DDC3 3 -#define DDC4 4 -#define DDC5 5 -#define DDC6 6 - -#define PORTC _SFR_IO8(0x08) -#define PORTC6 6 -#define PORTC5 5 -#define PORTC4 4 -#define PORTC3 3 -#define PORTC2 2 -#define PORTC1 1 -#define PORTC0 0 - -#define PIND _SFR_IO8(0x09) -#define PIND7 7 -#define PIND6 6 -#define PIND5 5 -#define PIND4 4 -#define PIND3 3 -#define PIND2 2 -#define PIND1 1 -#define PIND0 0 - -#define DDRD _SFR_IO8(0x0A) -#define DDD0 0 -#define DDD1 1 -#define DDD2 2 -#define DDD3 3 -#define DDD4 4 -#define DDD5 5 -#define DDD6 6 -#define DDD7 7 - -#define PORTD _SFR_IO8(0x0B) -#define PORTD7 7 -#define PORTD6 6 -#define PORTD5 5 -#define PORTD4 4 -#define PORTD3 3 -#define PORTD2 2 -#define PORTD1 1 -#define PORTD0 0 - -/* Reserved [0x0C..0x14] */ - -#define TIFR0 _SFR_IO8(0x15) -#define TOV0 0 -#define OCF0A 1 -#define OCF0B 2 - -#define TIFR1 _SFR_IO8(0x16) -#define TOV1 0 -#define OCF1A 1 -#define OCF1B 2 -#define ICF1 5 - -#define TIFR2 _SFR_IO8(0x17) -#define TOV2 0 -#define OCF2A 1 -#define OCF2B 2 - -/* Reserved [0x18..0x1A] */ - -#define PCIFR _SFR_IO8(0x1B) -#define PCIF0 0 -#define PCIF1 1 -#define PCIF2 2 - -#define EIFR _SFR_IO8(0x1C) -#define INTF0 0 -#define INTF1 1 - -#define EIMSK _SFR_IO8(0x1D) -#define INT0 0 -#define INT1 1 - -#define GPIOR0 _SFR_IO8(0x1E) - -#define EECR _SFR_IO8(0x1F) -#define EERE 0 -#define EEPE 1 -#define EEMPE 2 -#define EERIE 3 -#define EEPM0 4 -#define EEPM1 5 - -#define EEDR _SFR_IO8(0x20) - -/* Combine EEARL and EEARH */ -#define EEAR _SFR_IO16(0x21) - -#define EEARL _SFR_IO8(0x21) -#define EEARH _SFR_IO8(0x22) - -#define GTCCR _SFR_IO8(0x23) -#define PSRSYNC 0 -#define TSM 7 -#define PSRASY 1 - -#define TCCR0A _SFR_IO8(0x24) -#define WGM00 0 -#define WGM01 1 -#define COM0B0 4 -#define COM0B1 5 -#define COM0A0 6 -#define COM0A1 7 - -#define TCCR0B _SFR_IO8(0x25) -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define WGM02 3 -#define FOC0B 6 -#define FOC0A 7 - -#define TCNT0 _SFR_IO8(0x26) - -#define OCR0A _SFR_IO8(0x27) - -#define OCR0B _SFR_IO8(0x28) - -/* Reserved [0x29] */ - -#define GPIOR1 _SFR_IO8(0x2A) - -#define GPIOR2 _SFR_IO8(0x2B) - -#define SPCR _SFR_IO8(0x2C) -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -#define SPSR _SFR_IO8(0x2D) -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -#define SPDR _SFR_IO8(0x2E) - -/* Reserved [0x2F] */ - -#define ACSR _SFR_IO8(0x30) -#define ACIS0 0 -#define ACIS1 1 -#define ACIC 2 -#define ACIE 3 -#define ACI 4 -#define ACO 5 -#define ACBG 6 -#define ACD 7 - -/* Reserved [0x31..0x32] */ - -#define SMCR _SFR_IO8(0x33) -#define SE 0 -#define SM0 1 -#define SM1 2 -#define SM2 3 - -#define MCUSR _SFR_IO8(0x34) -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 - -#define MCUCR _SFR_IO8(0x35) -#define IVCE 0 -#define IVSEL 1 -#define PUD 4 -#define BODSE 5 -#define BODS 6 - -/* Reserved [0x36] */ - -#define SPMCSR _SFR_IO8(0x37) -#define SELFPRGEN 0 -#define PGERS 1 -#define PGWRT 2 -#define BLBSET 3 -#define RWWSRE 4 -#define RWWSB 6 -#define SPMIE 7 - -/* Reserved [0x38..0x3C] */ - -/* SP [0x3D..0x3E] */ - -/* SREG [0x3F] */ - -#define WDTCSR _SFR_MEM8(0x60) -#define WDE 3 -#define WDCE 4 -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDP3 5 -#define WDIE 6 -#define WDIF 7 - -#define CLKPR _SFR_MEM8(0x61) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPS2 2 -#define CLKPS3 3 -#define CLKPCE 7 - -/* Reserved [0x62..0x63] */ - -#define PRR _SFR_MEM8(0x64) -#define PRADC 0 -#define PRUSART0 1 -#define PRSPI 2 -#define PRTIM1 3 -#define PRTIM0 5 -#define PRTIM2 6 -#define PRTWI 7 - -#define __AVR_HAVE_PRR ((1< instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "ioa6614q.h" +#else +# error "Attempt to include more than one file." +#endif + +/* Registers and associated bit numbers */ + +#define PINB _SFR_IO8(0x03) +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +#define DDRB _SFR_IO8(0x04) +#define DDB0 0 +#define DDB1 1 +#define DDB2 2 +#define DDB3 3 +#define DDB4 4 +#define DDB5 5 +#define DDB6 6 +#define DDB7 7 + +#define PORTB _SFR_IO8(0x05) +#define PORTB7 7 +#define PORTB6 6 +#define PORTB5 5 +#define PORTB4 4 +#define PORTB3 3 +#define PORTB2 2 +#define PORTB1 1 +#define PORTB0 0 + +#define PINC _SFR_IO8(0x06) +#define PINC6 6 +#define PINC5 5 +#define PINC4 4 +#define PINC3 3 +#define PINC2 2 +#define PINC1 1 +#define PINC0 0 + +#define DDRC _SFR_IO8(0x07) +#define DDC0 0 +#define DDC1 1 +#define DDC2 2 +#define DDC3 3 +#define DDC4 4 +#define DDC5 5 +#define DDC6 6 + +#define PORTC _SFR_IO8(0x08) +#define PORTC6 6 +#define PORTC5 5 +#define PORTC4 4 +#define PORTC3 3 +#define PORTC2 2 +#define PORTC1 1 +#define PORTC0 0 + +#define PIND _SFR_IO8(0x09) +#define PIND7 7 +#define PIND6 6 +#define PIND5 5 +#define PIND4 4 +#define PIND3 3 +#define PIND2 2 +#define PIND1 1 +#define PIND0 0 + +#define DDRD _SFR_IO8(0x0A) +#define DDD0 0 +#define DDD1 1 +#define DDD2 2 +#define DDD3 3 +#define DDD4 4 +#define DDD5 5 +#define DDD6 6 +#define DDD7 7 + +#define PORTD _SFR_IO8(0x0B) +#define PORTD7 7 +#define PORTD6 6 +#define PORTD5 5 +#define PORTD4 4 +#define PORTD3 3 +#define PORTD2 2 +#define PORTD1 1 +#define PORTD0 0 + +/* Reserved [0x0C..0x14] */ + +#define TIFR0 _SFR_IO8(0x15) +#define TOV0 0 +#define OCF0A 1 +#define OCF0B 2 + +#define TIFR1 _SFR_IO8(0x16) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define ICF1 5 + +#define TIFR2 _SFR_IO8(0x17) +#define TOV2 0 +#define OCF2A 1 +#define OCF2B 2 + +/* Reserved [0x18..0x1A] */ + +#define PCIFR _SFR_IO8(0x1B) +#define PCIF0 0 +#define PCIF1 1 +#define PCIF2 2 + +#define EIFR _SFR_IO8(0x1C) +#define INTF0 0 +#define INTF1 1 + +#define EIMSK _SFR_IO8(0x1D) +#define INT0 0 +#define INT1 1 + +#define GPIOR0 _SFR_IO8(0x1E) + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEPE 1 +#define EEMPE 2 +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 + +#define EEDR _SFR_IO8(0x20) + +/* Combine EEARL and EEARH */ +#define EEAR _SFR_IO16(0x21) + +#define EEARL _SFR_IO8(0x21) +#define EEARH _SFR_IO8(0x22) + +#define GTCCR _SFR_IO8(0x23) +#define PSRSYNC 0 +#define TSM 7 +#define PSRASY 1 + +#define TCCR0A _SFR_IO8(0x24) +#define WGM00 0 +#define WGM01 1 +#define COM0B0 4 +#define COM0B1 5 +#define COM0A0 6 +#define COM0A1 7 + +#define TCCR0B _SFR_IO8(0x25) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define WGM02 3 +#define FOC0B 6 +#define FOC0A 7 + +#define TCNT0 _SFR_IO8(0x26) + +#define OCR0A _SFR_IO8(0x27) + +#define OCR0B _SFR_IO8(0x28) + +/* Reserved [0x29] */ + +#define GPIOR1 _SFR_IO8(0x2A) + +#define GPIOR2 _SFR_IO8(0x2B) + +#define SPCR _SFR_IO8(0x2C) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x2D) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0x2E) + +/* Reserved [0x2F] */ + +#define ACSR _SFR_IO8(0x30) +#define ACIS0 0 +#define ACIS1 1 +#define ACIC 2 +#define ACIE 3 +#define ACI 4 +#define ACO 5 +#define ACBG 6 +#define ACD 7 + +/* Reserved [0x31..0x32] */ + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 +#define SM2 3 + +#define MCUSR _SFR_IO8(0x34) +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 + +#define MCUCR _SFR_IO8(0x35) +#define IVCE 0 +#define IVSEL 1 +#define PUD 4 +#define BODSE 5 +#define BODS 6 + +/* Reserved [0x36] */ + +#define SPMCSR _SFR_IO8(0x37) +#define SELFPRGEN 0 +#define PGERS 1 +#define PGWRT 2 +#define BLBSET 3 +#define RWWSRE 4 +#define RWWSB 6 +#define SPMIE 7 + +/* Reserved [0x38..0x3C] */ + +/* SP [0x3D..0x3E] */ + +/* SREG [0x3F] */ + +#define WDTCSR _SFR_MEM8(0x60) +#define WDE 3 +#define WDCE 4 +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDP3 5 +#define WDIE 6 +#define WDIF 7 + +#define CLKPR _SFR_MEM8(0x61) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLKPS3 3 +#define CLKPCE 7 + +/* Reserved [0x62..0x63] */ + +#define PRR _SFR_MEM8(0x64) +#define PRADC 0 +#define PRUSART0 1 +#define PRSPI 2 +#define PRTIM1 3 +#define PRTIM0 5 +#define PRTIM2 6 +#define PRTWI 7 + +#define __AVR_HAVE_PRR ((1< instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "ioa6616c.h" -#else -# error "Attempt to include more than one file." -#endif - -/* Registers and associated bit numbers */ - -#define PINA _SFR_IO8(0x00) -#define PINA7 7 -#define PINA6 6 -#define PINA5 5 -#define PINA4 4 -#define PINA3 3 -#define PINA2 2 -#define PINA1 1 -#define PINA0 0 - -#define DDRA _SFR_IO8(0x01) -#define DDA0 0 -#define DDA1 1 -#define DDA2 2 -#define DDA3 3 -#define DDA4 4 -#define DDA5 5 -#define DDA6 6 -#define DDA7 7 - -#define PORTA _SFR_IO8(0x02) -#define PORTA7 7 -#define PORTA6 6 -#define PORTA5 5 -#define PORTA4 4 -#define PORTA3 3 -#define PORTA2 2 -#define PORTA1 1 -#define PORTA0 0 - -#define PINB _SFR_IO8(0x03) -#define PINB7 7 -#define PINB6 6 -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -#define DDRB _SFR_IO8(0x04) -#define DDB0 0 -#define DDB1 1 -#define DDB2 2 -#define DDB3 3 -#define DDB4 4 -#define DDB5 5 -#define DDB6 6 -#define DDB7 7 - -#define PORTB _SFR_IO8(0x05) -#define PORTB7 7 -#define PORTB6 6 -#define PORTB5 5 -#define PORTB4 4 -#define PORTB3 3 -#define PORTB2 2 -#define PORTB1 1 -#define PORTB0 0 - -/* Reserved [0x06..0x11] */ - -#define PORTCR _SFR_IO8(0x12) -#define PUDA 0 -#define PUDB 1 -#define BBMA 4 -#define BBMB 5 - -/* Reserved [0x13..0x14] */ - -#define TIFR0 _SFR_IO8(0x15) -#define TOV0 0 -#define OCF0A 1 - -#define TIFR1 _SFR_IO8(0x16) -#define TOV1 0 -#define OCF1A 1 -#define OCF1B 2 -#define ICF1 5 - -/* Reserved [0x17..0x1A] */ - -#define PCIFR _SFR_IO8(0x1B) -#define PCIF0 0 -#define PCIF1 1 - -#define EIFR _SFR_IO8(0x1C) -#define INTF0 0 -#define INTF1 1 - -#define EIMSK _SFR_IO8(0x1D) -#define INT0 0 -#define INT1 1 - -#define GPIOR0 _SFR_IO8(0x1E) -#define GPIOR00 0 -#define GPIOR01 1 -#define GPIOR02 2 -#define GPIOR03 3 -#define GPIOR04 4 -#define GPIOR05 5 -#define GPIOR06 6 -#define GPIOR07 7 - -#define EECR _SFR_IO8(0x1F) -#define EERE 0 -#define EEPE 1 -#define EEMPE 2 -#define EERIE 3 -#define EEPM0 4 -#define EEPM1 5 - -#define EEDR _SFR_IO8(0x20) -#define EEDR0 0 -#define EEDR1 1 -#define EEDR2 2 -#define EEDR3 3 -#define EEDR4 4 -#define EEDR5 5 -#define EEDR6 6 -#define EEDR7 7 - -/* Combine EEARL and EEARH */ -#define EEAR _SFR_IO16(0x21) - -#define EEARL _SFR_IO8(0x21) -#define EEARH _SFR_IO8(0x22) - -#define GTCCR _SFR_IO8(0x23) -#define PSR1 0 -#define PSR0 1 -#define TSM 7 - -/* Reserved [0x24] */ - -#define TCCR0A _SFR_IO8(0x25) -#define WGM00 0 -#define WGM01 1 -#define COM0A0 6 -#define COM0A1 7 - -#define TCCR0B _SFR_IO8(0x26) -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define FOC0A 7 - -#define TCNT0 _SFR_IO8(0x27) -#define TCNT00 0 -#define TCNT01 1 -#define TCNT02 2 -#define TCNT03 3 -#define TCNT04 4 -#define TCNT05 5 -#define TCNT06 6 -#define TCNT07 7 - -#define OCR0A _SFR_IO8(0x28) -#define OCR00 0 -#define OCR01 1 -#define OCR02 2 -#define OCR03 3 -#define OCR04 4 -#define OCR05 5 -#define OCR06 6 -#define OCR07 7 - -/* Reserved [0x29] */ - -#define GPIOR1 _SFR_IO8(0x2A) -#define GPIOR10 0 -#define GPIOR11 1 -#define GPIOR12 2 -#define GPIOR13 3 -#define GPIOR14 4 -#define GPIOR15 5 -#define GPIOR16 6 -#define GPIOR17 7 - -#define GPIOR2 _SFR_IO8(0x2B) -#define GPIOR20 0 -#define GPIOR21 1 -#define GPIOR22 2 -#define GPIOR23 3 -#define GPIOR24 4 -#define GPIOR25 5 -#define GPIOR26 6 -#define GPIOR27 7 - -#define SPCR _SFR_IO8(0x2C) -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -#define SPSR _SFR_IO8(0x2D) -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -#define SPDR _SFR_IO8(0x2E) -#define SPDR0 0 -#define SPDR1 1 -#define SPDR2 2 -#define SPDR3 3 -#define SPDR4 4 -#define SPDR5 5 -#define SPDR6 6 -#define SPDR7 7 - -/* Reserved [0x2F] */ - -#define ACSR _SFR_IO8(0x30) -#define ACIS0 0 -#define ACIS1 1 -#define ACIC 2 -#define ACIE 3 -#define ACI 4 -#define ACO 5 -#define ACIRS 6 -#define ACD 7 - -#define DWDR _SFR_IO8(0x31) -#define DWDR0 0 -#define DWDR1 1 -#define DWDR2 2 -#define DWDR3 3 -#define DWDR4 4 -#define DWDR5 5 -#define DWDR6 6 -#define DWDR7 7 - -/* Reserved [0x32] */ - -#define SMCR _SFR_IO8(0x33) -#define SE 0 -#define SM0 1 -#define SM1 2 - -#define MCUSR _SFR_IO8(0x34) -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 - -#define MCUCR _SFR_IO8(0x35) -#define PUD 4 -#define BODSE 5 -#define BODS 6 - -/* Reserved [0x36] */ - -#define SPMCSR _SFR_IO8(0x37) -#define SPMEN 0 -#define PGERS 1 -#define PGWRT 2 -#define RFLB 3 -#define CTPB 4 -#define SIGRD 5 -#define RWWSB 6 - -/* Reserved [0x38..0x3C] */ - -/* SP [0x3D..0x3E] */ - -/* SREG [0x3F] */ - -#define WDTCR _SFR_MEM8(0x60) -#define WDE 3 -#define WDCE 4 -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDP3 5 -#define WDIE 6 -#define WDIF 7 - -#define CLKPR _SFR_MEM8(0x61) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPS2 2 -#define CLKPS3 3 -#define CLKPCE 7 - -#define CLKCSR _SFR_MEM8(0x62) -#define CLKC0 0 -#define CLKC1 1 -#define CLKC2 2 -#define CLKC3 3 -#define CLKRDY 4 -#define CLKCCE 7 - -#define CLKSELR _SFR_MEM8(0x63) -#define CSEL0 0 -#define CSEL1 1 -#define CSEL2 2 -#define CSEL3 3 -#define CSUT0 4 -#define CSUT1 5 -#define COUT 6 - -#define PRR _SFR_MEM8(0x64) -#define PRADC 0 -#define PRUSI 1 -#define PRTIM0 2 -#define PRTIM1 3 -#define PRSPI 4 -#define PRLIN 5 - -#define __AVR_HAVE_PRR ((1< instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "ioa6616c.h" +#else +# error "Attempt to include more than one file." +#endif + +/* Registers and associated bit numbers */ + +#define PINA _SFR_IO8(0x00) +#define PINA7 7 +#define PINA6 6 +#define PINA5 5 +#define PINA4 4 +#define PINA3 3 +#define PINA2 2 +#define PINA1 1 +#define PINA0 0 + +#define DDRA _SFR_IO8(0x01) +#define DDA0 0 +#define DDA1 1 +#define DDA2 2 +#define DDA3 3 +#define DDA4 4 +#define DDA5 5 +#define DDA6 6 +#define DDA7 7 + +#define PORTA _SFR_IO8(0x02) +#define PORTA7 7 +#define PORTA6 6 +#define PORTA5 5 +#define PORTA4 4 +#define PORTA3 3 +#define PORTA2 2 +#define PORTA1 1 +#define PORTA0 0 + +#define PINB _SFR_IO8(0x03) +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +#define DDRB _SFR_IO8(0x04) +#define DDB0 0 +#define DDB1 1 +#define DDB2 2 +#define DDB3 3 +#define DDB4 4 +#define DDB5 5 +#define DDB6 6 +#define DDB7 7 + +#define PORTB _SFR_IO8(0x05) +#define PORTB7 7 +#define PORTB6 6 +#define PORTB5 5 +#define PORTB4 4 +#define PORTB3 3 +#define PORTB2 2 +#define PORTB1 1 +#define PORTB0 0 + +/* Reserved [0x06..0x11] */ + +#define PORTCR _SFR_IO8(0x12) +#define PUDA 0 +#define PUDB 1 +#define BBMA 4 +#define BBMB 5 + +/* Reserved [0x13..0x14] */ + +#define TIFR0 _SFR_IO8(0x15) +#define TOV0 0 +#define OCF0A 1 + +#define TIFR1 _SFR_IO8(0x16) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define ICF1 5 + +/* Reserved [0x17..0x1A] */ + +#define PCIFR _SFR_IO8(0x1B) +#define PCIF0 0 +#define PCIF1 1 + +#define EIFR _SFR_IO8(0x1C) +#define INTF0 0 +#define INTF1 1 + +#define EIMSK _SFR_IO8(0x1D) +#define INT0 0 +#define INT1 1 + +#define GPIOR0 _SFR_IO8(0x1E) +#define GPIOR00 0 +#define GPIOR01 1 +#define GPIOR02 2 +#define GPIOR03 3 +#define GPIOR04 4 +#define GPIOR05 5 +#define GPIOR06 6 +#define GPIOR07 7 + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEPE 1 +#define EEMPE 2 +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 + +#define EEDR _SFR_IO8(0x20) +#define EEDR0 0 +#define EEDR1 1 +#define EEDR2 2 +#define EEDR3 3 +#define EEDR4 4 +#define EEDR5 5 +#define EEDR6 6 +#define EEDR7 7 + +/* Combine EEARL and EEARH */ +#define EEAR _SFR_IO16(0x21) + +#define EEARL _SFR_IO8(0x21) +#define EEARH _SFR_IO8(0x22) + +#define GTCCR _SFR_IO8(0x23) +#define PSR1 0 +#define PSR0 1 +#define TSM 7 + +/* Reserved [0x24] */ + +#define TCCR0A _SFR_IO8(0x25) +#define WGM00 0 +#define WGM01 1 +#define COM0A0 6 +#define COM0A1 7 + +#define TCCR0B _SFR_IO8(0x26) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define FOC0A 7 + +#define TCNT0 _SFR_IO8(0x27) +#define TCNT00 0 +#define TCNT01 1 +#define TCNT02 2 +#define TCNT03 3 +#define TCNT04 4 +#define TCNT05 5 +#define TCNT06 6 +#define TCNT07 7 + +#define OCR0A _SFR_IO8(0x28) +#define OCR00 0 +#define OCR01 1 +#define OCR02 2 +#define OCR03 3 +#define OCR04 4 +#define OCR05 5 +#define OCR06 6 +#define OCR07 7 + +/* Reserved [0x29] */ + +#define GPIOR1 _SFR_IO8(0x2A) +#define GPIOR10 0 +#define GPIOR11 1 +#define GPIOR12 2 +#define GPIOR13 3 +#define GPIOR14 4 +#define GPIOR15 5 +#define GPIOR16 6 +#define GPIOR17 7 + +#define GPIOR2 _SFR_IO8(0x2B) +#define GPIOR20 0 +#define GPIOR21 1 +#define GPIOR22 2 +#define GPIOR23 3 +#define GPIOR24 4 +#define GPIOR25 5 +#define GPIOR26 6 +#define GPIOR27 7 + +#define SPCR _SFR_IO8(0x2C) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x2D) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0x2E) +#define SPDR0 0 +#define SPDR1 1 +#define SPDR2 2 +#define SPDR3 3 +#define SPDR4 4 +#define SPDR5 5 +#define SPDR6 6 +#define SPDR7 7 + +/* Reserved [0x2F] */ + +#define ACSR _SFR_IO8(0x30) +#define ACIS0 0 +#define ACIS1 1 +#define ACIC 2 +#define ACIE 3 +#define ACI 4 +#define ACO 5 +#define ACIRS 6 +#define ACD 7 + +#define DWDR _SFR_IO8(0x31) +#define DWDR0 0 +#define DWDR1 1 +#define DWDR2 2 +#define DWDR3 3 +#define DWDR4 4 +#define DWDR5 5 +#define DWDR6 6 +#define DWDR7 7 + +/* Reserved [0x32] */ + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 + +#define MCUSR _SFR_IO8(0x34) +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 + +#define MCUCR _SFR_IO8(0x35) +#define PUD 4 +#define BODSE 5 +#define BODS 6 + +/* Reserved [0x36] */ + +#define SPMCSR _SFR_IO8(0x37) +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define RFLB 3 +#define CTPB 4 +#define SIGRD 5 +#define RWWSB 6 + +/* Reserved [0x38..0x3C] */ + +/* SP [0x3D..0x3E] */ + +/* SREG [0x3F] */ + +#define WDTCR _SFR_MEM8(0x60) +#define WDE 3 +#define WDCE 4 +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDP3 5 +#define WDIE 6 +#define WDIF 7 + +#define CLKPR _SFR_MEM8(0x61) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLKPS3 3 +#define CLKPCE 7 + +#define CLKCSR _SFR_MEM8(0x62) +#define CLKC0 0 +#define CLKC1 1 +#define CLKC2 2 +#define CLKC3 3 +#define CLKRDY 4 +#define CLKCCE 7 + +#define CLKSELR _SFR_MEM8(0x63) +#define CSEL0 0 +#define CSEL1 1 +#define CSEL2 2 +#define CSEL3 3 +#define CSUT0 4 +#define CSUT1 5 +#define COUT 6 + +#define PRR _SFR_MEM8(0x64) +#define PRADC 0 +#define PRUSI 1 +#define PRTIM0 2 +#define PRTIM1 3 +#define PRSPI 4 +#define PRLIN 5 + +#define __AVR_HAVE_PRR ((1< instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "ioa6617c.h" -#else -# error "Attempt to include more than one file." -#endif - -/* Registers and associated bit numbers */ - -#define PINA _SFR_IO8(0x00) -#define PINA7 7 -#define PINA6 6 -#define PINA5 5 -#define PINA4 4 -#define PINA3 3 -#define PINA2 2 -#define PINA1 1 -#define PINA0 0 - -#define DDRA _SFR_IO8(0x01) -#define DDA0 0 -#define DDA1 1 -#define DDA2 2 -#define DDA3 3 -#define DDA4 4 -#define DDA5 5 -#define DDA6 6 -#define DDA7 7 - -#define PORTA _SFR_IO8(0x02) -#define PORTA7 7 -#define PORTA6 6 -#define PORTA5 5 -#define PORTA4 4 -#define PORTA3 3 -#define PORTA2 2 -#define PORTA1 1 -#define PORTA0 0 - -#define PINB _SFR_IO8(0x03) -#define PINB7 7 -#define PINB6 6 -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -#define DDRB _SFR_IO8(0x04) -#define DDB0 0 -#define DDB1 1 -#define DDB2 2 -#define DDB3 3 -#define DDB4 4 -#define DDB5 5 -#define DDB6 6 -#define DDB7 7 - -#define PORTB _SFR_IO8(0x05) -#define PORTB7 7 -#define PORTB6 6 -#define PORTB5 5 -#define PORTB4 4 -#define PORTB3 3 -#define PORTB2 2 -#define PORTB1 1 -#define PORTB0 0 - -/* Reserved [0x06..0x11] */ - -#define PORTCR _SFR_IO8(0x12) -#define PUDA 0 -#define PUDB 1 -#define BBMA 4 -#define BBMB 5 - -/* Reserved [0x13..0x14] */ - -#define TIFR0 _SFR_IO8(0x15) -#define TOV0 0 -#define OCF0A 1 - -#define TIFR1 _SFR_IO8(0x16) -#define TOV1 0 -#define OCF1A 1 -#define OCF1B 2 -#define ICF1 5 - -/* Reserved [0x17..0x1A] */ - -#define PCIFR _SFR_IO8(0x1B) -#define PCIF0 0 -#define PCIF1 1 - -#define EIFR _SFR_IO8(0x1C) -#define INTF0 0 -#define INTF1 1 - -#define EIMSK _SFR_IO8(0x1D) -#define INT0 0 -#define INT1 1 - -#define GPIOR0 _SFR_IO8(0x1E) -#define GPIOR00 0 -#define GPIOR01 1 -#define GPIOR02 2 -#define GPIOR03 3 -#define GPIOR04 4 -#define GPIOR05 5 -#define GPIOR06 6 -#define GPIOR07 7 - -#define EECR _SFR_IO8(0x1F) -#define EERE 0 -#define EEPE 1 -#define EEMPE 2 -#define EERIE 3 -#define EEPM0 4 -#define EEPM1 5 - -#define EEDR _SFR_IO8(0x20) -#define EEDR0 0 -#define EEDR1 1 -#define EEDR2 2 -#define EEDR3 3 -#define EEDR4 4 -#define EEDR5 5 -#define EEDR6 6 -#define EEDR7 7 - -/* Combine EEARL and EEARH */ -#define EEAR _SFR_IO16(0x21) - -#define EEARL _SFR_IO8(0x21) -#define EEARH _SFR_IO8(0x22) - -#define GTCCR _SFR_IO8(0x23) -#define PSR1 0 -#define PSR0 1 -#define TSM 7 - -/* Reserved [0x24] */ - -#define TCCR0A _SFR_IO8(0x25) -#define WGM00 0 -#define WGM01 1 -#define COM0A0 6 -#define COM0A1 7 - -#define TCCR0B _SFR_IO8(0x26) -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define FOC0A 7 - -#define TCNT0 _SFR_IO8(0x27) -#define TCNT00 0 -#define TCNT01 1 -#define TCNT02 2 -#define TCNT03 3 -#define TCNT04 4 -#define TCNT05 5 -#define TCNT06 6 -#define TCNT07 7 - -#define OCR0A _SFR_IO8(0x28) -#define OCR00 0 -#define OCR01 1 -#define OCR02 2 -#define OCR03 3 -#define OCR04 4 -#define OCR05 5 -#define OCR06 6 -#define OCR07 7 - -/* Reserved [0x29] */ - -#define GPIOR1 _SFR_IO8(0x2A) -#define GPIOR10 0 -#define GPIOR11 1 -#define GPIOR12 2 -#define GPIOR13 3 -#define GPIOR14 4 -#define GPIOR15 5 -#define GPIOR16 6 -#define GPIOR17 7 - -#define GPIOR2 _SFR_IO8(0x2B) -#define GPIOR20 0 -#define GPIOR21 1 -#define GPIOR22 2 -#define GPIOR23 3 -#define GPIOR24 4 -#define GPIOR25 5 -#define GPIOR26 6 -#define GPIOR27 7 - -#define SPCR _SFR_IO8(0x2C) -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -#define SPSR _SFR_IO8(0x2D) -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -#define SPDR _SFR_IO8(0x2E) -#define SPDR0 0 -#define SPDR1 1 -#define SPDR2 2 -#define SPDR3 3 -#define SPDR4 4 -#define SPDR5 5 -#define SPDR6 6 -#define SPDR7 7 - -/* Reserved [0x2F] */ - -#define ACSR _SFR_IO8(0x30) -#define ACIS0 0 -#define ACIS1 1 -#define ACIC 2 -#define ACIE 3 -#define ACI 4 -#define ACO 5 -#define ACIRS 6 -#define ACD 7 - -#define DWDR _SFR_IO8(0x31) -#define DWDR0 0 -#define DWDR1 1 -#define DWDR2 2 -#define DWDR3 3 -#define DWDR4 4 -#define DWDR5 5 -#define DWDR6 6 -#define DWDR7 7 - -/* Reserved [0x32] */ - -#define SMCR _SFR_IO8(0x33) -#define SE 0 -#define SM0 1 -#define SM1 2 - -#define MCUSR _SFR_IO8(0x34) -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 - -#define MCUCR _SFR_IO8(0x35) -#define PUD 4 -#define BODSE 5 -#define BODS 6 - -/* Reserved [0x36] */ - -#define SPMCSR _SFR_IO8(0x37) -#define SPMEN 0 -#define PGERS 1 -#define PGWRT 2 -#define RFLB 3 -#define CTPB 4 -#define SIGRD 5 -#define RWWSB 6 - -/* Reserved [0x38..0x3C] */ - -/* SP [0x3D..0x3E] */ - -/* SREG [0x3F] */ - -#define WDTCR _SFR_MEM8(0x60) -#define WDE 3 -#define WDCE 4 -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDP3 5 -#define WDIE 6 -#define WDIF 7 - -#define CLKPR _SFR_MEM8(0x61) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPS2 2 -#define CLKPS3 3 -#define CLKPCE 7 - -#define CLKCSR _SFR_MEM8(0x62) -#define CLKC0 0 -#define CLKC1 1 -#define CLKC2 2 -#define CLKC3 3 -#define CLKRDY 4 -#define CLKCCE 7 - -#define CLKSELR _SFR_MEM8(0x63) -#define CSEL0 0 -#define CSEL1 1 -#define CSEL2 2 -#define CSEL3 3 -#define CSUT0 4 -#define CSUT1 5 -#define COUT 6 - -#define PRR _SFR_MEM8(0x64) -#define PRADC 0 -#define PRUSI 1 -#define PRTIM0 2 -#define PRTIM1 3 -#define PRSPI 4 -#define PRLIN 5 - -#define __AVR_HAVE_PRR ((1< instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "ioa6617c.h" +#else +# error "Attempt to include more than one file." +#endif + +/* Registers and associated bit numbers */ + +#define PINA _SFR_IO8(0x00) +#define PINA7 7 +#define PINA6 6 +#define PINA5 5 +#define PINA4 4 +#define PINA3 3 +#define PINA2 2 +#define PINA1 1 +#define PINA0 0 + +#define DDRA _SFR_IO8(0x01) +#define DDA0 0 +#define DDA1 1 +#define DDA2 2 +#define DDA3 3 +#define DDA4 4 +#define DDA5 5 +#define DDA6 6 +#define DDA7 7 + +#define PORTA _SFR_IO8(0x02) +#define PORTA7 7 +#define PORTA6 6 +#define PORTA5 5 +#define PORTA4 4 +#define PORTA3 3 +#define PORTA2 2 +#define PORTA1 1 +#define PORTA0 0 + +#define PINB _SFR_IO8(0x03) +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +#define DDRB _SFR_IO8(0x04) +#define DDB0 0 +#define DDB1 1 +#define DDB2 2 +#define DDB3 3 +#define DDB4 4 +#define DDB5 5 +#define DDB6 6 +#define DDB7 7 + +#define PORTB _SFR_IO8(0x05) +#define PORTB7 7 +#define PORTB6 6 +#define PORTB5 5 +#define PORTB4 4 +#define PORTB3 3 +#define PORTB2 2 +#define PORTB1 1 +#define PORTB0 0 + +/* Reserved [0x06..0x11] */ + +#define PORTCR _SFR_IO8(0x12) +#define PUDA 0 +#define PUDB 1 +#define BBMA 4 +#define BBMB 5 + +/* Reserved [0x13..0x14] */ + +#define TIFR0 _SFR_IO8(0x15) +#define TOV0 0 +#define OCF0A 1 + +#define TIFR1 _SFR_IO8(0x16) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define ICF1 5 + +/* Reserved [0x17..0x1A] */ + +#define PCIFR _SFR_IO8(0x1B) +#define PCIF0 0 +#define PCIF1 1 + +#define EIFR _SFR_IO8(0x1C) +#define INTF0 0 +#define INTF1 1 + +#define EIMSK _SFR_IO8(0x1D) +#define INT0 0 +#define INT1 1 + +#define GPIOR0 _SFR_IO8(0x1E) +#define GPIOR00 0 +#define GPIOR01 1 +#define GPIOR02 2 +#define GPIOR03 3 +#define GPIOR04 4 +#define GPIOR05 5 +#define GPIOR06 6 +#define GPIOR07 7 + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEPE 1 +#define EEMPE 2 +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 + +#define EEDR _SFR_IO8(0x20) +#define EEDR0 0 +#define EEDR1 1 +#define EEDR2 2 +#define EEDR3 3 +#define EEDR4 4 +#define EEDR5 5 +#define EEDR6 6 +#define EEDR7 7 + +/* Combine EEARL and EEARH */ +#define EEAR _SFR_IO16(0x21) + +#define EEARL _SFR_IO8(0x21) +#define EEARH _SFR_IO8(0x22) + +#define GTCCR _SFR_IO8(0x23) +#define PSR1 0 +#define PSR0 1 +#define TSM 7 + +/* Reserved [0x24] */ + +#define TCCR0A _SFR_IO8(0x25) +#define WGM00 0 +#define WGM01 1 +#define COM0A0 6 +#define COM0A1 7 + +#define TCCR0B _SFR_IO8(0x26) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define FOC0A 7 + +#define TCNT0 _SFR_IO8(0x27) +#define TCNT00 0 +#define TCNT01 1 +#define TCNT02 2 +#define TCNT03 3 +#define TCNT04 4 +#define TCNT05 5 +#define TCNT06 6 +#define TCNT07 7 + +#define OCR0A _SFR_IO8(0x28) +#define OCR00 0 +#define OCR01 1 +#define OCR02 2 +#define OCR03 3 +#define OCR04 4 +#define OCR05 5 +#define OCR06 6 +#define OCR07 7 + +/* Reserved [0x29] */ + +#define GPIOR1 _SFR_IO8(0x2A) +#define GPIOR10 0 +#define GPIOR11 1 +#define GPIOR12 2 +#define GPIOR13 3 +#define GPIOR14 4 +#define GPIOR15 5 +#define GPIOR16 6 +#define GPIOR17 7 + +#define GPIOR2 _SFR_IO8(0x2B) +#define GPIOR20 0 +#define GPIOR21 1 +#define GPIOR22 2 +#define GPIOR23 3 +#define GPIOR24 4 +#define GPIOR25 5 +#define GPIOR26 6 +#define GPIOR27 7 + +#define SPCR _SFR_IO8(0x2C) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x2D) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0x2E) +#define SPDR0 0 +#define SPDR1 1 +#define SPDR2 2 +#define SPDR3 3 +#define SPDR4 4 +#define SPDR5 5 +#define SPDR6 6 +#define SPDR7 7 + +/* Reserved [0x2F] */ + +#define ACSR _SFR_IO8(0x30) +#define ACIS0 0 +#define ACIS1 1 +#define ACIC 2 +#define ACIE 3 +#define ACI 4 +#define ACO 5 +#define ACIRS 6 +#define ACD 7 + +#define DWDR _SFR_IO8(0x31) +#define DWDR0 0 +#define DWDR1 1 +#define DWDR2 2 +#define DWDR3 3 +#define DWDR4 4 +#define DWDR5 5 +#define DWDR6 6 +#define DWDR7 7 + +/* Reserved [0x32] */ + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 + +#define MCUSR _SFR_IO8(0x34) +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 + +#define MCUCR _SFR_IO8(0x35) +#define PUD 4 +#define BODSE 5 +#define BODS 6 + +/* Reserved [0x36] */ + +#define SPMCSR _SFR_IO8(0x37) +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define RFLB 3 +#define CTPB 4 +#define SIGRD 5 +#define RWWSB 6 + +/* Reserved [0x38..0x3C] */ + +/* SP [0x3D..0x3E] */ + +/* SREG [0x3F] */ + +#define WDTCR _SFR_MEM8(0x60) +#define WDE 3 +#define WDCE 4 +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDP3 5 +#define WDIE 6 +#define WDIF 7 + +#define CLKPR _SFR_MEM8(0x61) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLKPS3 3 +#define CLKPCE 7 + +#define CLKCSR _SFR_MEM8(0x62) +#define CLKC0 0 +#define CLKC1 1 +#define CLKC2 2 +#define CLKC3 3 +#define CLKRDY 4 +#define CLKCCE 7 + +#define CLKSELR _SFR_MEM8(0x63) +#define CSEL0 0 +#define CSEL1 1 +#define CSEL2 2 +#define CSEL3 3 +#define CSUT0 4 +#define CSUT1 5 +#define COUT 6 + +#define PRR _SFR_MEM8(0x64) +#define PRADC 0 +#define PRUSI 1 +#define PRTIM0 2 +#define PRTIM1 3 +#define PRSPI 4 +#define PRLIN 5 + +#define __AVR_HAVE_PRR ((1< instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "ioa664251.h" -#else -# error "Attempt to include more than one file." -#endif - -/* Registers and associated bit numbers */ - -#define PINA _SFR_IO8(0x00) -#define PINA7 7 -#define PINA6 6 -#define PINA5 5 -#define PINA4 4 -#define PINA3 3 -#define PINA2 2 -#define PINA1 1 -#define PINA0 0 - -#define DDRA _SFR_IO8(0x01) -#define DDA0 0 -#define DDA1 1 -#define DDA2 2 -#define DDA3 3 -#define DDA4 4 -#define DDA5 5 -#define DDA6 6 -#define DDA7 7 - -#define PORTA _SFR_IO8(0x02) -#define PORTA7 7 -#define PORTA6 6 -#define PORTA5 5 -#define PORTA4 4 -#define PORTA3 3 -#define PORTA2 2 -#define PORTA1 1 -#define PORTA0 0 - -#define PINB _SFR_IO8(0x03) -#define PINB7 7 -#define PINB6 6 -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -#define DDRB _SFR_IO8(0x04) -#define DDB0 0 -#define DDB1 1 -#define DDB2 2 -#define DDB3 3 -#define DDB4 4 -#define DDB5 5 -#define DDB6 6 -#define DDB7 7 - -#define PORTB _SFR_IO8(0x05) -#define PORTB7 7 -#define PORTB6 6 -#define PORTB5 5 -#define PORTB4 4 -#define PORTB3 3 -#define PORTB2 2 -#define PORTB1 1 -#define PORTB0 0 - -/* Reserved [0x06..0x11] */ - -#define PORTCR _SFR_IO8(0x12) -#define PUDA 0 -#define PUDB 1 -#define BBMA 4 -#define BBMB 5 - -/* Reserved [0x13..0x14] */ - -#define TIFR0 _SFR_IO8(0x15) -#define TOV0 0 -#define OCF0A 1 - -#define TIFR1 _SFR_IO8(0x16) -#define TOV1 0 -#define OCF1A 1 -#define OCF1B 2 -#define ICF1 5 - -/* Reserved [0x17..0x1A] */ - -#define PCIFR _SFR_IO8(0x1B) -#define PCIF0 0 -#define PCIF1 1 - -#define EIFR _SFR_IO8(0x1C) -#define INTF0 0 -#define INTF1 1 - -#define EIMSK _SFR_IO8(0x1D) -#define INT0 0 -#define INT1 1 - -#define GPIOR0 _SFR_IO8(0x1E) -#define GPIOR00 0 -#define GPIOR01 1 -#define GPIOR02 2 -#define GPIOR03 3 -#define GPIOR04 4 -#define GPIOR05 5 -#define GPIOR06 6 -#define GPIOR07 7 - -#define EECR _SFR_IO8(0x1F) -#define EERE 0 -#define EEPE 1 -#define EEMPE 2 -#define EERIE 3 -#define EEPM0 4 -#define EEPM1 5 - -#define EEDR _SFR_IO8(0x20) -#define EEDR0 0 -#define EEDR1 1 -#define EEDR2 2 -#define EEDR3 3 -#define EEDR4 4 -#define EEDR5 5 -#define EEDR6 6 -#define EEDR7 7 - -/* Combine EEARL and EEARH */ -#define EEAR _SFR_IO16(0x21) - -#define EEARL _SFR_IO8(0x21) -#define EEARH _SFR_IO8(0x22) - -#define GTCCR _SFR_IO8(0x23) -#define PSR1 0 -#define PSR0 1 -#define TSM 7 - -/* Reserved [0x24] */ - -#define TCCR0A _SFR_IO8(0x25) -#define WGM00 0 -#define WGM01 1 -#define COM0A0 6 -#define COM0A1 7 - -#define TCCR0B _SFR_IO8(0x26) -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define FOC0A 7 - -#define TCNT0 _SFR_IO8(0x27) -#define TCNT00 0 -#define TCNT01 1 -#define TCNT02 2 -#define TCNT03 3 -#define TCNT04 4 -#define TCNT05 5 -#define TCNT06 6 -#define TCNT07 7 - -#define OCR0A _SFR_IO8(0x28) -#define OCR00 0 -#define OCR01 1 -#define OCR02 2 -#define OCR03 3 -#define OCR04 4 -#define OCR05 5 -#define OCR06 6 -#define OCR07 7 - -/* Reserved [0x29] */ - -#define GPIOR1 _SFR_IO8(0x2A) -#define GPIOR10 0 -#define GPIOR11 1 -#define GPIOR12 2 -#define GPIOR13 3 -#define GPIOR14 4 -#define GPIOR15 5 -#define GPIOR16 6 -#define GPIOR17 7 - -#define GPIOR2 _SFR_IO8(0x2B) -#define GPIOR20 0 -#define GPIOR21 1 -#define GPIOR22 2 -#define GPIOR23 3 -#define GPIOR24 4 -#define GPIOR25 5 -#define GPIOR26 6 -#define GPIOR27 7 - -#define SPCR _SFR_IO8(0x2C) -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -#define SPSR _SFR_IO8(0x2D) -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -#define SPDR _SFR_IO8(0x2E) -#define SPDR0 0 -#define SPDR1 1 -#define SPDR2 2 -#define SPDR3 3 -#define SPDR4 4 -#define SPDR5 5 -#define SPDR6 6 -#define SPDR7 7 - -/* Reserved [0x2F] */ - -#define ACSR _SFR_IO8(0x30) -#define ACIS0 0 -#define ACIS1 1 -#define ACIC 2 -#define ACIE 3 -#define ACI 4 -#define ACO 5 -#define ACIRS 6 -#define ACD 7 - -#define DWDR _SFR_IO8(0x31) -#define DWDR0 0 -#define DWDR1 1 -#define DWDR2 2 -#define DWDR3 3 -#define DWDR4 4 -#define DWDR5 5 -#define DWDR6 6 -#define DWDR7 7 - -/* Reserved [0x32] */ - -#define SMCR _SFR_IO8(0x33) -#define SE 0 -#define SM0 1 -#define SM1 2 - -#define MCUSR _SFR_IO8(0x34) -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 - -#define MCUCR _SFR_IO8(0x35) -#define PUD 4 -#define BODSE 5 -#define BODS 6 - -/* Reserved [0x36] */ - -#define SPMCSR _SFR_IO8(0x37) -#define SPMEN 0 -#define PGERS 1 -#define PGWRT 2 -#define RFLB 3 -#define CTPB 4 -#define SIGRD 5 -#define RWWSB 6 - -/* Reserved [0x38..0x3C] */ - -/* SP [0x3D..0x3E] */ - -/* SREG [0x3F] */ - -#define WDTCR _SFR_MEM8(0x60) -#define WDE 3 -#define WDCE 4 -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDP3 5 -#define WDIE 6 -#define WDIF 7 - -#define CLKPR _SFR_MEM8(0x61) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPS2 2 -#define CLKPS3 3 -#define CLKPCE 7 - -#define CLKCSR _SFR_MEM8(0x62) -#define CLKC0 0 -#define CLKC1 1 -#define CLKC2 2 -#define CLKC3 3 -#define CLKRDY 4 -#define CLKCCE 7 - -#define CLKSELR _SFR_MEM8(0x63) -#define CSEL0 0 -#define CSEL1 1 -#define CSEL2 2 -#define CSEL3 3 -#define CSUT0 4 -#define CSUT1 5 -#define COUT 6 - -#define PRR _SFR_MEM8(0x64) -#define PRADC 0 -#define PRUSI 1 -#define PRTIM0 2 -#define PRTIM1 3 -#define PRSPI 4 -#define PRLIN 5 - -#define __AVR_HAVE_PRR ((1< instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "ioa664251.h" +#else +# error "Attempt to include more than one file." +#endif + +/* Registers and associated bit numbers */ + +#define PINA _SFR_IO8(0x00) +#define PINA7 7 +#define PINA6 6 +#define PINA5 5 +#define PINA4 4 +#define PINA3 3 +#define PINA2 2 +#define PINA1 1 +#define PINA0 0 + +#define DDRA _SFR_IO8(0x01) +#define DDA0 0 +#define DDA1 1 +#define DDA2 2 +#define DDA3 3 +#define DDA4 4 +#define DDA5 5 +#define DDA6 6 +#define DDA7 7 + +#define PORTA _SFR_IO8(0x02) +#define PORTA7 7 +#define PORTA6 6 +#define PORTA5 5 +#define PORTA4 4 +#define PORTA3 3 +#define PORTA2 2 +#define PORTA1 1 +#define PORTA0 0 + +#define PINB _SFR_IO8(0x03) +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +#define DDRB _SFR_IO8(0x04) +#define DDB0 0 +#define DDB1 1 +#define DDB2 2 +#define DDB3 3 +#define DDB4 4 +#define DDB5 5 +#define DDB6 6 +#define DDB7 7 + +#define PORTB _SFR_IO8(0x05) +#define PORTB7 7 +#define PORTB6 6 +#define PORTB5 5 +#define PORTB4 4 +#define PORTB3 3 +#define PORTB2 2 +#define PORTB1 1 +#define PORTB0 0 + +/* Reserved [0x06..0x11] */ + +#define PORTCR _SFR_IO8(0x12) +#define PUDA 0 +#define PUDB 1 +#define BBMA 4 +#define BBMB 5 + +/* Reserved [0x13..0x14] */ + +#define TIFR0 _SFR_IO8(0x15) +#define TOV0 0 +#define OCF0A 1 + +#define TIFR1 _SFR_IO8(0x16) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define ICF1 5 + +/* Reserved [0x17..0x1A] */ + +#define PCIFR _SFR_IO8(0x1B) +#define PCIF0 0 +#define PCIF1 1 + +#define EIFR _SFR_IO8(0x1C) +#define INTF0 0 +#define INTF1 1 + +#define EIMSK _SFR_IO8(0x1D) +#define INT0 0 +#define INT1 1 + +#define GPIOR0 _SFR_IO8(0x1E) +#define GPIOR00 0 +#define GPIOR01 1 +#define GPIOR02 2 +#define GPIOR03 3 +#define GPIOR04 4 +#define GPIOR05 5 +#define GPIOR06 6 +#define GPIOR07 7 + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEPE 1 +#define EEMPE 2 +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 + +#define EEDR _SFR_IO8(0x20) +#define EEDR0 0 +#define EEDR1 1 +#define EEDR2 2 +#define EEDR3 3 +#define EEDR4 4 +#define EEDR5 5 +#define EEDR6 6 +#define EEDR7 7 + +/* Combine EEARL and EEARH */ +#define EEAR _SFR_IO16(0x21) + +#define EEARL _SFR_IO8(0x21) +#define EEARH _SFR_IO8(0x22) + +#define GTCCR _SFR_IO8(0x23) +#define PSR1 0 +#define PSR0 1 +#define TSM 7 + +/* Reserved [0x24] */ + +#define TCCR0A _SFR_IO8(0x25) +#define WGM00 0 +#define WGM01 1 +#define COM0A0 6 +#define COM0A1 7 + +#define TCCR0B _SFR_IO8(0x26) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define FOC0A 7 + +#define TCNT0 _SFR_IO8(0x27) +#define TCNT00 0 +#define TCNT01 1 +#define TCNT02 2 +#define TCNT03 3 +#define TCNT04 4 +#define TCNT05 5 +#define TCNT06 6 +#define TCNT07 7 + +#define OCR0A _SFR_IO8(0x28) +#define OCR00 0 +#define OCR01 1 +#define OCR02 2 +#define OCR03 3 +#define OCR04 4 +#define OCR05 5 +#define OCR06 6 +#define OCR07 7 + +/* Reserved [0x29] */ + +#define GPIOR1 _SFR_IO8(0x2A) +#define GPIOR10 0 +#define GPIOR11 1 +#define GPIOR12 2 +#define GPIOR13 3 +#define GPIOR14 4 +#define GPIOR15 5 +#define GPIOR16 6 +#define GPIOR17 7 + +#define GPIOR2 _SFR_IO8(0x2B) +#define GPIOR20 0 +#define GPIOR21 1 +#define GPIOR22 2 +#define GPIOR23 3 +#define GPIOR24 4 +#define GPIOR25 5 +#define GPIOR26 6 +#define GPIOR27 7 + +#define SPCR _SFR_IO8(0x2C) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x2D) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0x2E) +#define SPDR0 0 +#define SPDR1 1 +#define SPDR2 2 +#define SPDR3 3 +#define SPDR4 4 +#define SPDR5 5 +#define SPDR6 6 +#define SPDR7 7 + +/* Reserved [0x2F] */ + +#define ACSR _SFR_IO8(0x30) +#define ACIS0 0 +#define ACIS1 1 +#define ACIC 2 +#define ACIE 3 +#define ACI 4 +#define ACO 5 +#define ACIRS 6 +#define ACD 7 + +#define DWDR _SFR_IO8(0x31) +#define DWDR0 0 +#define DWDR1 1 +#define DWDR2 2 +#define DWDR3 3 +#define DWDR4 4 +#define DWDR5 5 +#define DWDR6 6 +#define DWDR7 7 + +/* Reserved [0x32] */ + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 + +#define MCUSR _SFR_IO8(0x34) +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 + +#define MCUCR _SFR_IO8(0x35) +#define PUD 4 +#define BODSE 5 +#define BODS 6 + +/* Reserved [0x36] */ + +#define SPMCSR _SFR_IO8(0x37) +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define RFLB 3 +#define CTPB 4 +#define SIGRD 5 +#define RWWSB 6 + +/* Reserved [0x38..0x3C] */ + +/* SP [0x3D..0x3E] */ + +/* SREG [0x3F] */ + +#define WDTCR _SFR_MEM8(0x60) +#define WDE 3 +#define WDCE 4 +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDP3 5 +#define WDIE 6 +#define WDIF 7 + +#define CLKPR _SFR_MEM8(0x61) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLKPS3 3 +#define CLKPCE 7 + +#define CLKCSR _SFR_MEM8(0x62) +#define CLKC0 0 +#define CLKC1 1 +#define CLKC2 2 +#define CLKC3 3 +#define CLKRDY 4 +#define CLKCCE 7 + +#define CLKSELR _SFR_MEM8(0x63) +#define CSEL0 0 +#define CSEL1 1 +#define CSEL2 2 +#define CSEL3 3 +#define CSUT0 4 +#define CSUT1 5 +#define COUT 6 + +#define PRR _SFR_MEM8(0x64) +#define PRADC 0 +#define PRUSI 1 +#define PRTIM0 2 +#define PRTIM1 3 +#define PRSPI 4 +#define PRLIN 5 + +#define __AVR_HAVE_PRR ((1< file." -#endif +#endif /* I/O registers */ @@ -210,33 +210,33 @@ /* Interrupt vectors */ -#define SIG_FPGA_INTERRUPT0 _VECTOR(1) /* FPGA_INT0 */ +#define SIG_FPGA_INTERRUPT0 _VECTOR(1) /* FPGA_INT0 */ #define SIG_INTERRUPT0 _VECTOR(2) /* EXT_INT0 */ -#define SIG_FPGA_INTERRUPT1 _VECTOR(3) /* FPGA_INT1 */ +#define SIG_FPGA_INTERRUPT1 _VECTOR(3) /* FPGA_INT1 */ #define SIG_INTERRUPT1 _VECTOR(4) /* EXT_INT1 */ -#define SIG_FPGA_INTERRUPT2 _VECTOR(5) /* FPGA_INT2 */ +#define SIG_FPGA_INTERRUPT2 _VECTOR(5) /* FPGA_INT2 */ #define SIG_INTERRUPT2 _VECTOR(6) /* EXT_INT2 */ -#define SIG_FPGA_INTERRUPT3 _VECTOR(7) /* FPGA_INT3 */ +#define SIG_FPGA_INTERRUPT3 _VECTOR(7) /* FPGA_INT3 */ #define SIG_INTERRUPT3 _VECTOR(8) /* EXT_INT3 */ -#define SIG_OUTPUT_COMPARE2 _VECTOR(9) /* TIM2_COMP */ -#define SIG_OVERFLOW2 _VECTOR(10) /* TIM2_OVF */ -#define SIG_INPUT_CAPTURE1 _VECTOR(11) /* TIM1_CAPT */ -#define SIG_OUTPUT_COMPARE1A _VECTOR(12) /* TIM1_COMPA */ -#define SIG_OUTPUT_COMPARE1B _VECTOR(13) /* TIM1_COMPB */ -#define SIG_OVERFLOW1 _VECTOR(14) /* TIM1_OVF */ -#define SIG_OUTPUT_COMPARE0 _VECTOR(15) /* TIM0_COMP */ -#define SIG_OVERFLOW0 _VECTOR(16) /* TIM0_OVF */ -#define SIG_FPGA_INTERRUPT4 _VECTOR(17) /* FPGA_INT4 */ -#define SIG_FPGA_INTERRUPT5 _VECTOR(18) /* FPGA_INT5 */ -#define SIG_FPGA_INTERRUPT6 _VECTOR(19) /* FPGA_INT6 */ -#define SIG_FPGA_INTERRUPT7 _VECTOR(20) /* FPGA_INT7 */ +#define SIG_OUTPUT_COMPARE2 _VECTOR(9) /* TIM2_COMP */ +#define SIG_OVERFLOW2 _VECTOR(10) /* TIM2_OVF */ +#define SIG_INPUT_CAPTURE1 _VECTOR(11) /* TIM1_CAPT */ +#define SIG_OUTPUT_COMPARE1A _VECTOR(12) /* TIM1_COMPA */ +#define SIG_OUTPUT_COMPARE1B _VECTOR(13) /* TIM1_COMPB */ +#define SIG_OVERFLOW1 _VECTOR(14) /* TIM1_OVF */ +#define SIG_OUTPUT_COMPARE0 _VECTOR(15) /* TIM0_COMP */ +#define SIG_OVERFLOW0 _VECTOR(16) /* TIM0_OVF */ +#define SIG_FPGA_INTERRUPT4 _VECTOR(17) /* FPGA_INT4 */ +#define SIG_FPGA_INTERRUPT5 _VECTOR(18) /* FPGA_INT5 */ +#define SIG_FPGA_INTERRUPT6 _VECTOR(19) /* FPGA_INT6 */ +#define SIG_FPGA_INTERRUPT7 _VECTOR(20) /* FPGA_INT7 */ #define SIG_UART0_RECV _VECTOR(21) /* UART0_RXC */ #define SIG_UART0_DATA _VECTOR(22) /* UART0_DRE */ #define SIG_UART0_TRANS _VECTOR(23) /* UART0_TXC */ -#define SIG_FPGA_INTERRUPT8 _VECTOR(24) /* FPGA_INT8 */ -#define SIG_FPGA_INTERRUPT9 _VECTOR(25) /* FPGA_INT9 */ -#define SIG_FPGA_INTERRUPT10 _VECTOR(26) /* FPGA_INT10 */ -#define SIG_FPGA_INTERRUPT11 _VECTOR(27) /* FPGA_INT11 */ +#define SIG_FPGA_INTERRUPT8 _VECTOR(24) /* FPGA_INT8 */ +#define SIG_FPGA_INTERRUPT9 _VECTOR(25) /* FPGA_INT9 */ +#define SIG_FPGA_INTERRUPT10 _VECTOR(26) /* FPGA_INT10 */ +#define SIG_FPGA_INTERRUPT11 _VECTOR(27) /* FPGA_INT11 */ #define SIG_UART1_RECV _VECTOR(28) /* UART1_RXC */ #define SIG_UART1_DATA _VECTOR(29) /* UART1_DRE */ #define SIG_UART1_TRANS _VECTOR(30) /* UART1_TXC */ diff --git a/include/avr/ioavr128da28.h b/include/avr/ioavr128da28.h index cd997db0..f56156ce 100644 --- a/include/avr/ioavr128da28.h +++ b/include/avr/ioavr128da28.h @@ -6484,4 +6484,3 @@ IO Module Instances. Mapped to memory. #define SIGNATURE_2 0x0A #endif /* #ifdef _AVR_AVR128DA28_H_INCLUDED */ - diff --git a/include/avr/ioavr128da32.h b/include/avr/ioavr128da32.h index b3f7a265..2c36c06c 100644 --- a/include/avr/ioavr128da32.h +++ b/include/avr/ioavr128da32.h @@ -6544,4 +6544,3 @@ IO Module Instances. Mapped to memory. #define SIGNATURE_2 0x09 #endif /* #ifdef _AVR_AVR128DA32_H_INCLUDED */ - diff --git a/include/avr/ioavr128da48.h b/include/avr/ioavr128da48.h index 82c67269..d912accc 100644 --- a/include/avr/ioavr128da48.h +++ b/include/avr/ioavr128da48.h @@ -7360,4 +7360,3 @@ IO Module Instances. Mapped to memory. #define SIGNATURE_2 0x08 #endif /* #ifdef _AVR_AVR128DA48_H_INCLUDED */ - diff --git a/include/avr/ioavr128da64.h b/include/avr/ioavr128da64.h index 4fd74516..d2753949 100644 --- a/include/avr/ioavr128da64.h +++ b/include/avr/ioavr128da64.h @@ -7615,4 +7615,3 @@ IO Module Instances. Mapped to memory. #define SIGNATURE_2 0x07 #endif /* #ifdef _AVR_AVR128DA64_H_INCLUDED */ - diff --git a/include/avr/ioavr128db28.h b/include/avr/ioavr128db28.h index f9bf7b32..6cabb7d2 100644 --- a/include/avr/ioavr128db28.h +++ b/include/avr/ioavr128db28.h @@ -7062,4 +7062,3 @@ IO Module Instances. Mapped to memory. #define SIGNATURE_2 0x0E #endif /* #ifdef _AVR_AVR128DB28_H_INCLUDED */ - diff --git a/include/avr/ioavr128db32.h b/include/avr/ioavr128db32.h index 3be8baa6..820a9a8b 100644 --- a/include/avr/ioavr128db32.h +++ b/include/avr/ioavr128db32.h @@ -7109,4 +7109,3 @@ IO Module Instances. Mapped to memory. #define SIGNATURE_2 0x0D #endif /* #ifdef _AVR_AVR128DB32_H_INCLUDED */ - diff --git a/include/avr/ioavr128db48.h b/include/avr/ioavr128db48.h index be1f0d30..438cafee 100644 --- a/include/avr/ioavr128db48.h +++ b/include/avr/ioavr128db48.h @@ -8082,4 +8082,3 @@ IO Module Instances. Mapped to memory. #define SIGNATURE_2 0x0C #endif /* #ifdef _AVR_AVR128DB48_H_INCLUDED */ - diff --git a/include/avr/ioavr128db64.h b/include/avr/ioavr128db64.h index 6dc5371a..83a55605 100644 --- a/include/avr/ioavr128db64.h +++ b/include/avr/ioavr128db64.h @@ -8278,4 +8278,3 @@ IO Module Instances. Mapped to memory. #define SIGNATURE_2 0x0B #endif /* #ifdef _AVR_AVR128DB64_H_INCLUDED */ - diff --git a/include/avr/ioavr16dd14.h b/include/avr/ioavr16dd14.h index 8a83d927..cbdf2b93 100644 --- a/include/avr/ioavr16dd14.h +++ b/include/avr/ioavr16dd14.h @@ -6405,4 +6405,3 @@ IO Module Instances. Mapped to memory. #define SIGNATURE_2 0x34 #endif /* #ifdef _AVR_AVR16DD14_H_INCLUDED */ - diff --git a/include/avr/ioavr16dd20.h b/include/avr/ioavr16dd20.h index c4513451..02361af2 100644 --- a/include/avr/ioavr16dd20.h +++ b/include/avr/ioavr16dd20.h @@ -6417,4 +6417,3 @@ IO Module Instances. Mapped to memory. #define SIGNATURE_2 0x33 #endif /* #ifdef _AVR_AVR16DD20_H_INCLUDED */ - diff --git a/include/avr/ioavr16dd28.h b/include/avr/ioavr16dd28.h index 12f975e3..f3c53684 100644 --- a/include/avr/ioavr16dd28.h +++ b/include/avr/ioavr16dd28.h @@ -6438,4 +6438,3 @@ IO Module Instances. Mapped to memory. #define SIGNATURE_2 0x32 #endif /* #ifdef _AVR_AVR16DD28_H_INCLUDED */ - diff --git a/include/avr/ioavr16dd32.h b/include/avr/ioavr16dd32.h index e983c75a..ddfa6688 100644 --- a/include/avr/ioavr16dd32.h +++ b/include/avr/ioavr16dd32.h @@ -6446,4 +6446,3 @@ IO Module Instances. Mapped to memory. #define SIGNATURE_2 0x31 #endif /* #ifdef _AVR_AVR16DD32_H_INCLUDED */ - diff --git a/include/avr/ioavr32da28.h b/include/avr/ioavr32da28.h index bb9cf16a..afc68e41 100644 --- a/include/avr/ioavr32da28.h +++ b/include/avr/ioavr32da28.h @@ -6475,4 +6475,3 @@ IO Module Instances. Mapped to memory. #define SIGNATURE_2 0x34 #endif /* #ifdef _AVR_AVR32DA28_H_INCLUDED */ - diff --git a/include/avr/ioavr32da32.h b/include/avr/ioavr32da32.h index 026f7ae1..419426e8 100644 --- a/include/avr/ioavr32da32.h +++ b/include/avr/ioavr32da32.h @@ -6535,4 +6535,3 @@ IO Module Instances. Mapped to memory. #define SIGNATURE_2 0x33 #endif /* #ifdef _AVR_AVR32DA32_H_INCLUDED */ - diff --git a/include/avr/ioavr32da48.h b/include/avr/ioavr32da48.h index 2e9213f2..85ec4ea0 100644 --- a/include/avr/ioavr32da48.h +++ b/include/avr/ioavr32da48.h @@ -7351,4 +7351,3 @@ IO Module Instances. Mapped to memory. #define SIGNATURE_2 0x32 #endif /* #ifdef _AVR_AVR32DA48_H_INCLUDED */ - diff --git a/include/avr/ioavr32db28.h b/include/avr/ioavr32db28.h index 97175c02..26638b1b 100644 --- a/include/avr/ioavr32db28.h +++ b/include/avr/ioavr32db28.h @@ -7058,4 +7058,3 @@ IO Module Instances. Mapped to memory. #define SIGNATURE_2 0x37 #endif /* #ifdef _AVR_AVR32DB28_H_INCLUDED */ - diff --git a/include/avr/ioavr32db32.h b/include/avr/ioavr32db32.h index e6322b8e..8ad041ab 100644 --- a/include/avr/ioavr32db32.h +++ b/include/avr/ioavr32db32.h @@ -7105,4 +7105,3 @@ IO Module Instances. Mapped to memory. #define SIGNATURE_2 0x36 #endif /* #ifdef _AVR_AVR32DB32_H_INCLUDED */ - diff --git a/include/avr/ioavr32db48.h b/include/avr/ioavr32db48.h index 4f71b815..f76593b3 100644 --- a/include/avr/ioavr32db48.h +++ b/include/avr/ioavr32db48.h @@ -8078,4 +8078,3 @@ IO Module Instances. Mapped to memory. #define SIGNATURE_2 0x35 #endif /* #ifdef _AVR_AVR32DB48_H_INCLUDED */ - diff --git a/include/avr/ioavr32dd14.h b/include/avr/ioavr32dd14.h index 7c626e67..6a052b4c 100644 --- a/include/avr/ioavr32dd14.h +++ b/include/avr/ioavr32dd14.h @@ -6405,4 +6405,3 @@ IO Module Instances. Mapped to memory. #define SIGNATURE_2 0x3B #endif /* #ifdef _AVR_AVR32DD14_H_INCLUDED */ - diff --git a/include/avr/ioavr32dd20.h b/include/avr/ioavr32dd20.h index 557f8c45..3db3ca6c 100644 --- a/include/avr/ioavr32dd20.h +++ b/include/avr/ioavr32dd20.h @@ -6417,4 +6417,3 @@ IO Module Instances. Mapped to memory. #define SIGNATURE_2 0x3A #endif /* #ifdef _AVR_AVR32DD20_H_INCLUDED */ - diff --git a/include/avr/ioavr32dd28.h b/include/avr/ioavr32dd28.h index c9efef7a..932b3260 100644 --- a/include/avr/ioavr32dd28.h +++ b/include/avr/ioavr32dd28.h @@ -6438,4 +6438,3 @@ IO Module Instances. Mapped to memory. #define SIGNATURE_2 0x39 #endif /* #ifdef _AVR_AVR32DD28_H_INCLUDED */ - diff --git a/include/avr/ioavr32dd32.h b/include/avr/ioavr32dd32.h index 89996edb..1d414f43 100644 --- a/include/avr/ioavr32dd32.h +++ b/include/avr/ioavr32dd32.h @@ -6446,4 +6446,3 @@ IO Module Instances. Mapped to memory. #define SIGNATURE_2 0x38 #endif /* #ifdef _AVR_AVR32DD32_H_INCLUDED */ - diff --git a/include/avr/ioavr64da28.h b/include/avr/ioavr64da28.h index df9a4ef3..3f123a44 100644 --- a/include/avr/ioavr64da28.h +++ b/include/avr/ioavr64da28.h @@ -6480,4 +6480,3 @@ IO Module Instances. Mapped to memory. #define SIGNATURE_2 0x15 #endif /* #ifdef _AVR_AVR64DA28_H_INCLUDED */ - diff --git a/include/avr/ioavr64da32.h b/include/avr/ioavr64da32.h index 7b99b91d..72e6781b 100644 --- a/include/avr/ioavr64da32.h +++ b/include/avr/ioavr64da32.h @@ -6540,4 +6540,3 @@ IO Module Instances. Mapped to memory. #define SIGNATURE_2 0x14 #endif /* #ifdef _AVR_AVR64DA32_H_INCLUDED */ - diff --git a/include/avr/ioavr64da48.h b/include/avr/ioavr64da48.h index 02a14758..97aaadee 100644 --- a/include/avr/ioavr64da48.h +++ b/include/avr/ioavr64da48.h @@ -7356,4 +7356,3 @@ IO Module Instances. Mapped to memory. #define SIGNATURE_2 0x13 #endif /* #ifdef _AVR_AVR64DA48_H_INCLUDED */ - diff --git a/include/avr/ioavr64da64.h b/include/avr/ioavr64da64.h index 0a86c778..8bedf3bf 100644 --- a/include/avr/ioavr64da64.h +++ b/include/avr/ioavr64da64.h @@ -7611,4 +7611,3 @@ IO Module Instances. Mapped to memory. #define SIGNATURE_2 0x12 #endif /* #ifdef _AVR_AVR64DA64_H_INCLUDED */ - diff --git a/include/avr/ioavr64db28.h b/include/avr/ioavr64db28.h index fac4600c..adf49a76 100644 --- a/include/avr/ioavr64db28.h +++ b/include/avr/ioavr64db28.h @@ -7058,4 +7058,3 @@ IO Module Instances. Mapped to memory. #define SIGNATURE_2 0x19 #endif /* #ifdef _AVR_AVR64DB28_H_INCLUDED */ - diff --git a/include/avr/ioavr64db32.h b/include/avr/ioavr64db32.h index 7acf07e1..c767c317 100644 --- a/include/avr/ioavr64db32.h +++ b/include/avr/ioavr64db32.h @@ -7105,4 +7105,3 @@ IO Module Instances. Mapped to memory. #define SIGNATURE_2 0x18 #endif /* #ifdef _AVR_AVR64DB32_H_INCLUDED */ - diff --git a/include/avr/ioavr64db48.h b/include/avr/ioavr64db48.h index 8a56bc47..b4fe20ff 100644 --- a/include/avr/ioavr64db48.h +++ b/include/avr/ioavr64db48.h @@ -8078,4 +8078,3 @@ IO Module Instances. Mapped to memory. #define SIGNATURE_2 0x17 #endif /* #ifdef _AVR_AVR64DB48_H_INCLUDED */ - diff --git a/include/avr/ioavr64db64.h b/include/avr/ioavr64db64.h index 084b9caf..50fb3750 100644 --- a/include/avr/ioavr64db64.h +++ b/include/avr/ioavr64db64.h @@ -8274,4 +8274,3 @@ IO Module Instances. Mapped to memory. #define SIGNATURE_2 0x16 #endif /* #ifdef _AVR_AVR64DB64_H_INCLUDED */ - diff --git a/include/avr/ioavr64dd14.h b/include/avr/ioavr64dd14.h index 971baa20..398c5464 100644 --- a/include/avr/ioavr64dd14.h +++ b/include/avr/ioavr64dd14.h @@ -6405,4 +6405,3 @@ IO Module Instances. Mapped to memory. #define SIGNATURE_2 0x1D #endif /* #ifdef _AVR_AVR64DD14_H_INCLUDED */ - diff --git a/include/avr/ioavr64dd20.h b/include/avr/ioavr64dd20.h index adf8a2d5..51a3000e 100644 --- a/include/avr/ioavr64dd20.h +++ b/include/avr/ioavr64dd20.h @@ -6417,4 +6417,3 @@ IO Module Instances. Mapped to memory. #define SIGNATURE_2 0x1C #endif /* #ifdef _AVR_AVR64DD20_H_INCLUDED */ - diff --git a/include/avr/ioavr64dd28.h b/include/avr/ioavr64dd28.h index 80e331bf..1c77a8c7 100644 --- a/include/avr/ioavr64dd28.h +++ b/include/avr/ioavr64dd28.h @@ -6438,4 +6438,3 @@ IO Module Instances. Mapped to memory. #define SIGNATURE_2 0x1B #endif /* #ifdef _AVR_AVR64DD28_H_INCLUDED */ - diff --git a/include/avr/ioavr64dd32.h b/include/avr/ioavr64dd32.h index b64434fa..69b64cd3 100644 --- a/include/avr/ioavr64dd32.h +++ b/include/avr/ioavr64dd32.h @@ -6446,4 +6446,3 @@ IO Module Instances. Mapped to memory. #define SIGNATURE_2 0x1A #endif /* #ifdef _AVR_AVR64DD32_H_INCLUDED */ - diff --git a/include/avr/iocan128.h b/include/avr/iocan128.h index 680d40df..a158482f 100644 --- a/include/avr/iocan128.h +++ b/include/avr/iocan128.h @@ -83,7 +83,7 @@ /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST -#define __BOOT_LOCK_BITS_1_EXIST +#define __BOOT_LOCK_BITS_1_EXIST /* Signature */ diff --git a/include/avr/iocan32.h b/include/avr/iocan32.h index d5c80a98..9e05e755 100644 --- a/include/avr/iocan32.h +++ b/include/avr/iocan32.h @@ -83,7 +83,7 @@ /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST -#define __BOOT_LOCK_BITS_1_EXIST +#define __BOOT_LOCK_BITS_1_EXIST /* Signature */ diff --git a/include/avr/iocan64.h b/include/avr/iocan64.h index 5252df04..364112ba 100644 --- a/include/avr/iocan64.h +++ b/include/avr/iocan64.h @@ -83,7 +83,7 @@ /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST -#define __BOOT_LOCK_BITS_1_EXIST +#define __BOOT_LOCK_BITS_1_EXIST /* Signature */ diff --git a/include/avr/iocanxx.h b/include/avr/iocanxx.h index 2f27101e..f9e9e0aa 100644 --- a/include/avr/iocanxx.h +++ b/include/avr/iocanxx.h @@ -53,7 +53,7 @@ # define _AVR_IOXXX_H_ "iocanxx.h" #else # error "Attempt to include more than one file." -#endif +#endif /* I/O registers and bit definitions. */ @@ -378,7 +378,7 @@ #define CANGIE _SFR_MEM8(0xDB) /* Word Definition: CAN Enable MOb Register*/ -#define CANEN _SFR_MEM16(0xDC) +#define CANEN _SFR_MEM16(0xDC) /* RegDef: CAN Enable MOb Register*/ #define CANEN2 _SFR_MEM8(0xDC) @@ -387,7 +387,7 @@ #define CANEN1 _SFR_MEM8(0xDD) /* Word Definition: CAN Enable Interrupt MOb Register*/ -#define CANIE _SFR_MEM16(0xDE) +#define CANIE _SFR_MEM16(0xDE) /* RegDef: CAN Enable Interrupt MOb Register*/ #define CANIE2 _SFR_MEM8(0xDE) @@ -994,9 +994,9 @@ #define ADPS0 0 /* End Register Bits */ -/* - The ADHSM bit has been removed from all documentation, - as being not needed at all since the comparator has proven +/* + The ADHSM bit has been removed from all documentation, + as being not needed at all since the comparator has proven to be fast enough even without feeding it more power. */ diff --git a/include/avr/iom103.h b/include/avr/iom103.h index 0897274b..5511747b 100644 --- a/include/avr/iom103.h +++ b/include/avr/iom103.h @@ -45,7 +45,7 @@ # define _AVR_IOXXX_H_ "iom103.h" #else # error "Attempt to include more than one file." -#endif +#endif /* I/O registers */ @@ -202,7 +202,7 @@ /* Timer/Counter Interrupt MaSK register */ #define TIMSK _SFR_IO8(0x37) -/* Èxternal Interrupt Flag Register */ +/* Èxternal Interrupt Flag Register */ #define EIFR _SFR_IO8(0x38) /* External Interrupt MaSK register */ @@ -377,7 +377,7 @@ #define INT1 1 #define INT0 0 -/* Èxternal Interrupt Flag Register */ +/* Èxternal Interrupt Flag Register */ #define INTF7 7 #define INTF6 6 #define INTF5 5 diff --git a/include/avr/iom128.h b/include/avr/iom128.h index f9bc637b..af672334 100644 --- a/include/avr/iom128.h +++ b/include/avr/iom128.h @@ -31,7 +31,7 @@ /* $Id$ */ -/* avr/iom128.h - defines for ATmega128 +/* avr/iom128.h - defines for ATmega128 As of 2002-08-27: - This should be up to date with data sheet 2467E-AVR-05/02 */ @@ -49,7 +49,7 @@ # define _AVR_IOXXX_H_ "iom128.h" #else # error "Attempt to include more than one file." -#endif +#endif /* I/O registers */ @@ -829,9 +829,9 @@ #define WDP1 1 #define WDP0 0 -/* - The ADHSM bit has been removed from all documentation, - as being not needed at all since the comparator has proven +/* + The ADHSM bit has been removed from all documentation, + as being not needed at all since the comparator has proven to be fast enough even without feeding it more power. */ @@ -1001,7 +1001,7 @@ #define PINA5 5 #define PINA4 4 #define PINA3 3 -#define PINA2 2 +#define PINA2 2 #define PINA1 1 #define PINA0 0 @@ -1031,7 +1031,7 @@ #define PINB5 5 #define PINB4 4 #define PINB3 3 -#define PINB2 2 +#define PINB2 2 #define PINB1 1 #define PINB0 0 @@ -1061,7 +1061,7 @@ #define PINC5 5 #define PINC4 4 #define PINC3 3 -#define PINC2 2 +#define PINC2 2 #define PINC1 1 #define PINC0 0 @@ -1091,7 +1091,7 @@ #define PIND5 5 #define PIND4 4 #define PIND3 3 -#define PIND2 2 +#define PIND2 2 #define PIND1 1 #define PIND0 0 @@ -1121,7 +1121,7 @@ #define PINE5 5 #define PINE4 4 #define PINE3 3 -#define PINE2 2 +#define PINE2 2 #define PINE1 1 #define PINE0 0 @@ -1151,7 +1151,7 @@ #define PINF5 5 #define PINF4 4 #define PINF3 3 -#define PINF2 2 +#define PINF2 2 #define PINF1 1 #define PINF0 0 @@ -1172,7 +1172,7 @@ /* Port G Input Pins - PING */ #define PING4 4 #define PING3 3 -#define PING2 2 +#define PING2 2 #define PING1 1 #define PING0 0 @@ -1227,7 +1227,7 @@ /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST -#define __BOOT_LOCK_BITS_1_EXIST +#define __BOOT_LOCK_BITS_1_EXIST /* Signature */ diff --git a/include/avr/iom1280.h b/include/avr/iom1280.h index 406e630a..05db737d 100644 --- a/include/avr/iom1280.h +++ b/include/avr/iom1280.h @@ -1,4 +1,4 @@ -/* Copyright (c) 2005 Anatoly Sokolov +/* Copyright (c) 2005 Anatoly Sokolov All rights reserved. Redistribution and use in source and binary forms, with or without @@ -83,7 +83,7 @@ /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST -#define __BOOT_LOCK_BITS_1_EXIST +#define __BOOT_LOCK_BITS_1_EXIST /* Signature */ diff --git a/include/avr/iom1281.h b/include/avr/iom1281.h index bc406f40..13dd7666 100644 --- a/include/avr/iom1281.h +++ b/include/avr/iom1281.h @@ -1,4 +1,4 @@ -/* Copyright (c) 2005 Anatoly Sokolov +/* Copyright (c) 2005 Anatoly Sokolov All rights reserved. Redistribution and use in source and binary forms, with or without @@ -83,7 +83,7 @@ /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST -#define __BOOT_LOCK_BITS_1_EXIST +#define __BOOT_LOCK_BITS_1_EXIST /* Signature */ diff --git a/include/avr/iom1284.h b/include/avr/iom1284.h index 8e2fb81f..fb1b845f 100644 --- a/include/avr/iom1284.h +++ b/include/avr/iom1284.h @@ -1026,4 +1026,3 @@ #define SLEEP_MODE_EXT_STANDBY (0x07<<1) #endif /* #ifdef _AVR_ATMEGA1284_H_INCLUDED */ - diff --git a/include/avr/iom1284p.h b/include/avr/iom1284p.h index 215454ab..ba83b085 100644 --- a/include/avr/iom1284p.h +++ b/include/avr/iom1284p.h @@ -26,7 +26,7 @@ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. + POSSIBILITY OF SUCH DAMAGE. */ /* $Id$ */ @@ -43,7 +43,7 @@ # define _AVR_IOXXX_H_ "iom1284p.h" #else # error "Attempt to include more than one file." -#endif +#endif #ifndef _AVR_IOM1284P_H_ @@ -1201,7 +1201,7 @@ /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST -#define __BOOT_LOCK_BITS_1_EXIST +#define __BOOT_LOCK_BITS_1_EXIST /* Signature */ diff --git a/include/avr/iom128a.h b/include/avr/iom128a.h index 80838093..7232153c 100644 --- a/include/avr/iom128a.h +++ b/include/avr/iom128a.h @@ -955,4 +955,3 @@ #define SLEEP_MODE_EXT_STANDBY (0x07<<2) #endif /* #ifdef _AVR_ATMEGA128A_H_INCLUDED */ - diff --git a/include/avr/iom16.h b/include/avr/iom16.h index 20db6469..f213dd21 100644 --- a/include/avr/iom16.h +++ b/include/avr/iom16.h @@ -45,7 +45,7 @@ # define _AVR_IOXXX_H_ "iom16.h" #else # error "Attempt to include more than one file." -#endif +#endif /* Registers and associated bit numbers */ @@ -369,9 +369,9 @@ #define COM1A0 6 #define COM1A1 7 -/* - The ADHSM bit has been removed from all documentation, - as being not needed at all since the comparator has proven +/* + The ADHSM bit has been removed from all documentation, + as being not needed at all since the comparator has proven to be fast enough even without feeding it more power. */ @@ -623,7 +623,7 @@ /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST -#define __BOOT_LOCK_BITS_1_EXIST +#define __BOOT_LOCK_BITS_1_EXIST /* Signature */ @@ -638,7 +638,7 @@ #pragma GCC system_header -#pragma GCC poison +#pragma GCC poison #pragma GCC poison SIG_INTERRUPT0 #pragma GCC poison SIG_INTERRUPT1 diff --git a/include/avr/iom1608.h b/include/avr/iom1608.h index e80e5468..167a4489 100644 --- a/include/avr/iom1608.h +++ b/include/avr/iom1608.h @@ -1,4 +1,3 @@ - /* This file is part of avr-libc. Automatically created by devtools/gen-ioheader-atdf-avr8x.py @@ -5057,5 +5056,3 @@ IO Module Instances. Mapped to memory. #endif /* #ifdef _AVR_ATMEGA1608_H_INCLUDED */ - - diff --git a/include/avr/iom1609.h b/include/avr/iom1609.h index 96fd1af2..40316f73 100644 --- a/include/avr/iom1609.h +++ b/include/avr/iom1609.h @@ -1,4 +1,3 @@ - /* This file is part of avr-libc. Automatically created by devtools/gen-ioheader-atdf-avr8x.py @@ -5132,5 +5131,3 @@ IO Module Instances. Mapped to memory. #endif /* #ifdef _AVR_ATMEGA1609_H_INCLUDED */ - - diff --git a/include/avr/iom161.h b/include/avr/iom161.h index b129d391..1d7e2be2 100644 --- a/include/avr/iom161.h +++ b/include/avr/iom161.h @@ -45,7 +45,7 @@ # define _AVR_IOXXX_H_ "iom161.h" #else # error "Attempt to include more than one file." -#endif +#endif /* I/O registers */ @@ -682,7 +682,7 @@ /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST -#define __BOOT_LOCK_BITS_1_EXIST +#define __BOOT_LOCK_BITS_1_EXIST /* Signature */ diff --git a/include/avr/iom162.h b/include/avr/iom162.h index 550e5dea..425468ec 100644 --- a/include/avr/iom162.h +++ b/include/avr/iom162.h @@ -45,7 +45,7 @@ # define _AVR_IOXXX_H_ "iom162.h" #else # error "Attempt to include more than one file." -#endif +#endif /* Memory mapped I/O registers */ @@ -164,7 +164,7 @@ #define UCSR1A _SFR_IO8(0x02) /* USART 1 Control and Status Register A */ #define UCSR1B _SFR_IO8(0x01) /* USART 1 Control and Status Register B */ #define UBRR1L _SFR_IO8(0x00) /* USART 0 Baud Rate Register High Byte */ - + /* Interrupt vectors (byte addresses) */ @@ -484,7 +484,7 @@ -/* SPMCR bit definitions */ +/* SPMCR bit definitions */ #define SPMIE 7 #define RWWSB 6 @@ -968,7 +968,7 @@ /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST -#define __BOOT_LOCK_BITS_1_EXIST +#define __BOOT_LOCK_BITS_1_EXIST /* Signature */ diff --git a/include/avr/iom163.h b/include/avr/iom163.h index f746a854..4aa96c03 100644 --- a/include/avr/iom163.h +++ b/include/avr/iom163.h @@ -45,7 +45,7 @@ # define _AVR_IOXXX_H_ "iom163.h" #else # error "Attempt to include more than one file." -#endif +#endif /* I/O registers */ @@ -645,7 +645,7 @@ /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST -#define __BOOT_LOCK_BITS_1_EXIST +#define __BOOT_LOCK_BITS_1_EXIST /* Signature */ diff --git a/include/avr/iom164.h b/include/avr/iom164.h index fcd31817..f1e50ddd 100644 --- a/include/avr/iom164.h +++ b/include/avr/iom164.h @@ -83,13 +83,13 @@ /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST -#define __BOOT_LOCK_BITS_1_EXIST +#define __BOOT_LOCK_BITS_1_EXIST /* Signature (ATmega164P) */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x94 -#define SIGNATURE_2 0x0A +#define SIGNATURE_2 0x0A #define SLEEP_MODE_IDLE (0x00<<1) diff --git a/include/avr/iom164pa.h b/include/avr/iom164pa.h index 83636e52..284e40c9 100644 --- a/include/avr/iom164pa.h +++ b/include/avr/iom164pa.h @@ -943,4 +943,3 @@ #define SLEEP_MODE_EXT_STANDBY (0x07<<1) #endif /* #ifdef _AVR_ATMEGA164PA_H_INCLUDED */ - diff --git a/include/avr/iom165.h b/include/avr/iom165.h index 8746229a..c1907894 100644 --- a/include/avr/iom165.h +++ b/include/avr/iom165.h @@ -45,7 +45,7 @@ # define _AVR_IOXXX_H_ "iom165.h" #else # error "Attempt to include more than one file." -#endif +#endif /* Registers and associated bit numbers */ @@ -836,7 +836,7 @@ /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST -#define __BOOT_LOCK_BITS_1_EXIST +#define __BOOT_LOCK_BITS_1_EXIST /* Signature */ diff --git a/include/avr/iom165a.h b/include/avr/iom165a.h index 13997ae3..376cb711 100644 --- a/include/avr/iom165a.h +++ b/include/avr/iom165a.h @@ -831,4 +831,3 @@ #define SLEEP_MODE_STANDBY (0x06<<1) #endif /* #ifdef _AVR_ATMEGA165A_H_INCLUDED */ - diff --git a/include/avr/iom165p.h b/include/avr/iom165p.h index 04253a47..4972c7e0 100644 --- a/include/avr/iom165p.h +++ b/include/avr/iom165p.h @@ -46,7 +46,7 @@ # define _AVR_IOXXX_H_ "iom165p.h" #else # error "Attempt to include more than one file." -#endif +#endif /* Registers and associated bit numbers */ @@ -839,7 +839,7 @@ /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST -#define __BOOT_LOCK_BITS_1_EXIST +#define __BOOT_LOCK_BITS_1_EXIST /* Signature */ diff --git a/include/avr/iom165pa.h b/include/avr/iom165pa.h index f9ae2af4..c6ee4b85 100644 --- a/include/avr/iom165pa.h +++ b/include/avr/iom165pa.h @@ -833,4 +833,3 @@ #define SLEEP_MODE_STANDBY (0x06<<1) #endif /* #ifdef _AVR_ATMEGA165PA_H_INCLUDED */ - diff --git a/include/avr/iom168.h b/include/avr/iom168.h index 55d06118..57f9f11d 100644 --- a/include/avr/iom168.h +++ b/include/avr/iom168.h @@ -80,7 +80,7 @@ /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST -#define __BOOT_LOCK_BITS_1_EXIST +#define __BOOT_LOCK_BITS_1_EXIST /* Signature */ diff --git a/include/avr/iom168p.h b/include/avr/iom168p.h index 87737e1a..99161842 100644 --- a/include/avr/iom168p.h +++ b/include/avr/iom168p.h @@ -26,7 +26,7 @@ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. + POSSIBILITY OF SUCH DAMAGE. */ /* $Id$ */ @@ -43,7 +43,7 @@ # define _AVR_IOXXX_H_ "iom168p.h" #else # error "Attempt to include more than one file." -#endif +#endif #ifndef _AVR_IOM168P_H_ @@ -331,7 +331,7 @@ #define WDRF 3 #define MCUCR _SFR_IO8(0x35) -#define IVCE 0 +#define IVCE 0 #define IVSEL 1 #define PUD 4 #define BODSE 5 @@ -831,7 +831,7 @@ #define TIMER1_COMPA_vect _VECTOR(11) /* Timer/Counter1 Compare Match A */ #define TIMER1_COMPB_vect_num 12 -#define TIMER1_COMPB_vect _VECTOR(12) /* Timer/Counter1 Compare Match B */ +#define TIMER1_COMPB_vect _VECTOR(12) /* Timer/Counter1 Compare Match B */ #define TIMER1_OVF_vect_num 13 #define TIMER1_OVF_vect _VECTOR(13) /* Timer/Counter1 Overflow */ @@ -924,7 +924,7 @@ /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST -#define __BOOT_LOCK_BITS_1_EXIST +#define __BOOT_LOCK_BITS_1_EXIST /* Signature */ diff --git a/include/avr/iom168pa.h b/include/avr/iom168pa.h index c5282758..180ce7d5 100644 --- a/include/avr/iom168pa.h +++ b/include/avr/iom168pa.h @@ -787,4 +787,3 @@ #define SLEEP_MODE_EXT_STANDBY (0x07<<1) #endif /* #ifdef _AVR_ATMEGA168PA_H_INCLUDED */ - diff --git a/include/avr/iom169.h b/include/avr/iom169.h index e42d207e..d7a150fa 100644 --- a/include/avr/iom169.h +++ b/include/avr/iom169.h @@ -1,4 +1,4 @@ -/* Copyright (c) 2002, 2003, 2004, 2005 +/* Copyright (c) 2002, 2003, 2004, 2005 Juergen Schilling Eric B. Weddington All rights reserved. @@ -49,7 +49,7 @@ # define _AVR_IOXXX_H_ "iom169.h" #else # error "Attempt to include more than one file." -#endif +#endif /* I/O registers */ @@ -1125,7 +1125,7 @@ /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST -#define __BOOT_LOCK_BITS_1_EXIST +#define __BOOT_LOCK_BITS_1_EXIST /* Signature */ diff --git a/include/avr/iom169p.h b/include/avr/iom169p.h index 442552e3..e4bf0514 100644 --- a/include/avr/iom169p.h +++ b/include/avr/iom169p.h @@ -48,7 +48,7 @@ # define _AVR_IOXXX_H_ "iom169p.h" #else # error "Attempt to include more than one file." -#endif +#endif /* I/O registers */ @@ -1048,7 +1048,7 @@ /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST -#define __BOOT_LOCK_BITS_1_EXIST +#define __BOOT_LOCK_BITS_1_EXIST /* Signature */ diff --git a/include/avr/iom169pa.h b/include/avr/iom169pa.h index 55e04950..9c000821 100644 --- a/include/avr/iom169pa.h +++ b/include/avr/iom169pa.h @@ -42,7 +42,7 @@ # define _AVR_IOXXX_H_ "iom169pa.h" #else # error "Attempt to include more than one file." -#endif +#endif #ifndef _AVR_ATmega169PA_H_ @@ -1483,4 +1483,3 @@ #define SLEEP_MODE_STANDBY (0x06<<1) #endif /* _AVR_ATmega169PA_H_ */ - diff --git a/include/avr/iom16a.h b/include/avr/iom16a.h index 78d1ee4b..e6bc8f84 100644 --- a/include/avr/iom16a.h +++ b/include/avr/iom16a.h @@ -42,7 +42,7 @@ # define _AVR_IOXXX_H_ "iom16a.h" #else # error "Attempt to include more than one file." -#endif +#endif #ifndef _AVR_ATmega16A_H_ @@ -923,4 +923,3 @@ #define SLEEP_MODE_EXT_STANDBY (0x0B<<4) #endif /* _AVR_ATmega16A_H_ */ - diff --git a/include/avr/iom16hva.h b/include/avr/iom16hva.h index 60abedaf..77052224 100644 --- a/include/avr/iom16hva.h +++ b/include/avr/iom16hva.h @@ -1,4 +1,4 @@ -/* Copyright (c) 2007, Anatoly Sokolov +/* Copyright (c) 2007, Anatoly Sokolov All rights reserved. Redistribution and use in source and binary forms, with or without diff --git a/include/avr/iom16hva2.h b/include/avr/iom16hva2.h index 64b36ca9..f0657a6c 100644 --- a/include/avr/iom16hva2.h +++ b/include/avr/iom16hva2.h @@ -42,7 +42,7 @@ # define _AVR_IOXXX_H_ "iom16hva2.h" #else # error "Attempt to include more than one file." -#endif +#endif #ifndef _AVR_ATmega16HVA2_H_ @@ -817,7 +817,7 @@ #define PI_DDR DDRI #define PI_PORT PORTI #define PI_PIN PINI -#define PI_BIT +#define PI_BIT #define NI_DDR DDRNI #define NI_PORT PORTNI @@ -881,4 +881,3 @@ #define SLEEP_MODE_PWR_OFF (0x04<<1) #endif /* _AVR_ATmega16HVA2_H_ */ - diff --git a/include/avr/iom16hvb.h b/include/avr/iom16hvb.h index dd8eae6f..3c5ff4de 100644 --- a/include/avr/iom16hvb.h +++ b/include/avr/iom16hvb.h @@ -42,7 +42,7 @@ # define _AVR_IOXXX_H_ "iom16hvb.h" #else # error "Attempt to include more than one file." -#endif +#endif #ifndef _AVR_ATmega16HVB_H_ @@ -986,7 +986,7 @@ #define PI_DDR DDRI #define PI_PORT PORTI #define PI_PIN PINI -#define PI_BIT +#define PI_BIT #define NI_DDR DDRNI #define NI_PORT PORTNI @@ -1050,4 +1050,3 @@ #define SLEEP_MODE_PWR_OFF (0x04<<1) #endif /* _AVR_ATmega16HVB_H_ */ - diff --git a/include/avr/iom16hvbrevb.h b/include/avr/iom16hvbrevb.h index 253a98f5..ad4ee15f 100644 --- a/include/avr/iom16hvbrevb.h +++ b/include/avr/iom16hvbrevb.h @@ -42,7 +42,7 @@ # define _AVR_IOXXX_H_ "iom16hvbrevb.h" #else # error "Attempt to include more than one file." -#endif +#endif #ifndef _AVR_ATmega16HVBREVB_H_ @@ -986,7 +986,7 @@ #define PI_DDR DDRI #define PI_PORT PORTI #define PI_PIN PINI -#define PI_BIT +#define PI_BIT #define NI_DDR DDRNI #define NI_PORT PORTNI @@ -1050,4 +1050,3 @@ #define SLEEP_MODE_PWR_OFF (0x04<<1) #endif /* _AVR_ATmega16HVBREVB_H_ */ - diff --git a/include/avr/iom16m1.h b/include/avr/iom16m1.h index a9d55045..48c64e62 100644 --- a/include/avr/iom16m1.h +++ b/include/avr/iom16m1.h @@ -42,7 +42,7 @@ # define _AVR_IOXXX_H_ "iom16m1.h" #else # error "Attempt to include more than one file." -#endif +#endif #ifndef _AVR_ATmega16M1_H_ @@ -1569,4 +1569,3 @@ #define SLEEP_MODE_STANDBY (0x06<<1) #endif /* _AVR_ATmega16M1_H_ */ - diff --git a/include/avr/iom16u2.h b/include/avr/iom16u2.h index c596b8f3..b52fd266 100644 --- a/include/avr/iom16u2.h +++ b/include/avr/iom16u2.h @@ -42,7 +42,7 @@ # define _AVR_IOXXX_H_ "iom16u2.h" #else # error "Attempt to include more than one file." -#endif +#endif #ifndef _AVR_ATmega16U2_H_ @@ -999,4 +999,3 @@ #define SLEEP_MODE_EXT_STANDBY (0x07<<1) #endif /* _AVR_ATmega16U2_H_ */ - diff --git a/include/avr/iom16u4.h b/include/avr/iom16u4.h index 6e5d6f8e..68fb81f7 100644 --- a/include/avr/iom16u4.h +++ b/include/avr/iom16u4.h @@ -1422,4 +1422,3 @@ #define SLEEP_MODE_EXT_STANDBY (0x07<<1) #endif /* _AVR_ATmega16U4_H_ */ - diff --git a/include/avr/iom2560.h b/include/avr/iom2560.h index a30a9acd..8e85c498 100644 --- a/include/avr/iom2560.h +++ b/include/avr/iom2560.h @@ -1,4 +1,4 @@ -/* Copyright (c) 2005 Anatoly Sokolov +/* Copyright (c) 2005 Anatoly Sokolov All rights reserved. Redistribution and use in source and binary forms, with or without @@ -83,7 +83,7 @@ /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST -#define __BOOT_LOCK_BITS_1_EXIST +#define __BOOT_LOCK_BITS_1_EXIST /* Signature */ diff --git a/include/avr/iom2561.h b/include/avr/iom2561.h index c4756172..dfdf7983 100644 --- a/include/avr/iom2561.h +++ b/include/avr/iom2561.h @@ -1,4 +1,4 @@ -/* Copyright (c) 2005 Anatoly Sokolov +/* Copyright (c) 2005 Anatoly Sokolov All rights reserved. Redistribution and use in source and binary forms, with or without @@ -83,7 +83,7 @@ /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST -#define __BOOT_LOCK_BITS_1_EXIST +#define __BOOT_LOCK_BITS_1_EXIST /* Signature */ diff --git a/include/avr/iom3000.h b/include/avr/iom3000.h index 5a955528..9e506fe3 100644 --- a/include/avr/iom3000.h +++ b/include/avr/iom3000.h @@ -42,7 +42,7 @@ # define _AVR_IOXXX_H_ "iom3000.h" #else # error "Attempt to include more than one file." -#endif +#endif #ifndef _AVR_IOM3000_H_ @@ -79,7 +79,7 @@ #define UBRRH _SFR_IO8(0x15) /* Alias. */ #define UBRRLO _SFR_IO8(0x14) /* Name according to datasheet. */ #define UBRRHI _SFR_IO8(0x15) /* Name according to datasheet. */ -#define GIFR _SFR_IO8(0x16) +#define GIFR _SFR_IO8(0x16) #define GIMSK _SFR_IO8(0x17) #define DACVAL _SFR_IO16(0x18) #define DACVALL _SFR_IO8(0x18) /* Alias. */ @@ -234,4 +234,3 @@ #endif /* _AVR_IOM3000_H_ */ - diff --git a/include/avr/iom32.h b/include/avr/iom32.h index 0c1577b8..e58f4dac 100644 --- a/include/avr/iom32.h +++ b/include/avr/iom32.h @@ -45,7 +45,7 @@ # define _AVR_IOXXX_H_ "iom32.h" #else # error "Attempt to include more than one file." -#endif +#endif /* I/O registers */ @@ -705,7 +705,7 @@ /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST -#define __BOOT_LOCK_BITS_1_EXIST +#define __BOOT_LOCK_BITS_1_EXIST /* Signature */ diff --git a/include/avr/iom3208.h b/include/avr/iom3208.h index 7074ad80..683fe29e 100644 --- a/include/avr/iom3208.h +++ b/include/avr/iom3208.h @@ -1,4 +1,3 @@ - /* This file is part of avr-libc. Automatically created by devtools/gen-ioheader-atdf-avr8x.py @@ -5057,5 +5056,3 @@ IO Module Instances. Mapped to memory. #endif /* #ifdef _AVR_ATMEGA3208_H_INCLUDED */ - - diff --git a/include/avr/iom3209.h b/include/avr/iom3209.h index 5a053dbf..59fbd120 100644 --- a/include/avr/iom3209.h +++ b/include/avr/iom3209.h @@ -1,4 +1,3 @@ - /* This file is part of avr-libc. Automatically created by devtools/gen-ioheader-atdf-avr8x.py @@ -5130,5 +5129,3 @@ IO Module Instances. Mapped to memory. #endif /* #ifdef _AVR_ATMEGA3209_H_INCLUDED */ - - diff --git a/include/avr/iom323.h b/include/avr/iom323.h index e0236f5e..22c4c298 100644 --- a/include/avr/iom323.h +++ b/include/avr/iom323.h @@ -45,7 +45,7 @@ # define _AVR_IOXXX_H_ "iom323.h" #else # error "Attempt to include more than one file." -#endif +#endif /* I/O registers */ @@ -697,7 +697,7 @@ /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST -#define __BOOT_LOCK_BITS_1_EXIST +#define __BOOT_LOCK_BITS_1_EXIST /* Signature */ diff --git a/include/avr/iom324.h b/include/avr/iom324.h index e672771e..c15c53eb 100644 --- a/include/avr/iom324.h +++ b/include/avr/iom324.h @@ -83,13 +83,13 @@ /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST -#define __BOOT_LOCK_BITS_1_EXIST +#define __BOOT_LOCK_BITS_1_EXIST /* Signature (ATmega324P) */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x95 -#define SIGNATURE_2 0x08 +#define SIGNATURE_2 0x08 #define SLEEP_MODE_IDLE (0x00<<1) #define SLEEP_MODE_ADC (0x01<<1) diff --git a/include/avr/iom324pa.h b/include/avr/iom324pa.h index 8acafa33..8489648f 100644 --- a/include/avr/iom324pa.h +++ b/include/avr/iom324pa.h @@ -42,7 +42,7 @@ # define _AVR_IOXXX_H_ "iom324pa.h" #else # error "Attempt to include more than one file." -#endif +#endif #ifndef _AVR_ATmega324PA_H_ @@ -1370,4 +1370,3 @@ #define SLEEP_MODE_EXT_STANDBY (0x07<<1) #endif /* _AVR_ATmega324PA_H_ */ - diff --git a/include/avr/iom325.h b/include/avr/iom325.h index da906d94..7d5ccb88 100644 --- a/include/avr/iom325.h +++ b/include/avr/iom325.h @@ -45,7 +45,7 @@ # define _AVR_IOXXX_H_ "iom325.h" #else # error "Attempt to include more than one file." -#endif +#endif /* Registers and associated bit numbers */ @@ -838,7 +838,7 @@ /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST -#define __BOOT_LOCK_BITS_1_EXIST +#define __BOOT_LOCK_BITS_1_EXIST /* Signature */ diff --git a/include/avr/iom3250.h b/include/avr/iom3250.h index 171f0469..6ded1d28 100644 --- a/include/avr/iom3250.h +++ b/include/avr/iom3250.h @@ -45,7 +45,7 @@ # define _AVR_IOXXX_H_ "iom3250.h" #else # error "Attempt to include more than one file." -#endif +#endif /* Registers and associated bit numbers */ @@ -930,7 +930,7 @@ /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST -#define __BOOT_LOCK_BITS_1_EXIST +#define __BOOT_LOCK_BITS_1_EXIST /* Signature */ diff --git a/include/avr/iom3250pa.h b/include/avr/iom3250pa.h index f499b158..f3b34cac 100644 --- a/include/avr/iom3250pa.h +++ b/include/avr/iom3250pa.h @@ -897,4 +897,3 @@ #define SLEEP_MODE_STANDBY (0x06<<1) #endif /* #ifdef _AVR_ATMEGA3250PA_H_INCLUDED */ - diff --git a/include/avr/iom325pa.h b/include/avr/iom325pa.h index 10a92477..de6c8f9d 100644 --- a/include/avr/iom325pa.h +++ b/include/avr/iom325pa.h @@ -822,4 +822,3 @@ #define SLEEP_MODE_STANDBY (0x06<<1) #endif /* #ifdef _AVR_ATMEGA325PA_H_INCLUDED */ - diff --git a/include/avr/iom328p.h b/include/avr/iom328p.h index 2470ba10..c116062b 100644 --- a/include/avr/iom328p.h +++ b/include/avr/iom328p.h @@ -26,7 +26,7 @@ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. + POSSIBILITY OF SUCH DAMAGE. */ /* $Id$ */ @@ -43,7 +43,7 @@ # define _AVR_IOXXX_H_ "iom328p.h" #else # error "Attempt to include more than one file." -#endif +#endif #ifndef _AVR_IOM328P_H_ @@ -833,7 +833,7 @@ #define TIMER1_COMPA_vect _VECTOR(11) /* Timer/Counter1 Compare Match A */ #define TIMER1_COMPB_vect_num 12 -#define TIMER1_COMPB_vect _VECTOR(12) /* Timer/Counter1 Compare Match B */ +#define TIMER1_COMPB_vect _VECTOR(12) /* Timer/Counter1 Compare Match B */ #define TIMER1_OVF_vect_num 13 #define TIMER1_OVF_vect _VECTOR(13) /* Timer/Counter1 Overflow */ @@ -926,7 +926,7 @@ /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST -#define __BOOT_LOCK_BITS_1_EXIST +#define __BOOT_LOCK_BITS_1_EXIST /* Signature */ diff --git a/include/avr/iom329.h b/include/avr/iom329.h index cfb6e006..f19268c0 100644 --- a/include/avr/iom329.h +++ b/include/avr/iom329.h @@ -1,5 +1,5 @@ /* Copyright (c) 2004 Eric B. Weddington - Copyright (c) 2005, 2006, 2007 Anatoly Sokolov + Copyright (c) 2005, 2006, 2007 Anatoly Sokolov All rights reserved. Redistribution and use in source and binary forms, with or without @@ -46,7 +46,7 @@ # define _AVR_IOXXX_H_ "iom329.h" #else # error "Attempt to include more than one file." -#endif +#endif /* Registers and associated bit numbers */ @@ -1023,7 +1023,7 @@ /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST -#define __BOOT_LOCK_BITS_1_EXIST +#define __BOOT_LOCK_BITS_1_EXIST /* Signature */ diff --git a/include/avr/iom3290.h b/include/avr/iom3290.h index b91340a7..159182a7 100644 --- a/include/avr/iom3290.h +++ b/include/avr/iom3290.h @@ -1,5 +1,5 @@ /* Copyright (c) 2004 Eric B. Weddington - Copyright (c) 2005, 2006, 2007 Anatoly Sokolov + Copyright (c) 2005, 2006, 2007 Anatoly Sokolov All rights reserved. Redistribution and use in source and binary forms, with or without @@ -46,7 +46,7 @@ # define _AVR_IOXXX_H_ "iom3290.h" #else # error "Attempt to include more than one file." -#endif +#endif /* Registers and associated bit numbers */ @@ -1178,7 +1178,7 @@ /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST -#define __BOOT_LOCK_BITS_1_EXIST +#define __BOOT_LOCK_BITS_1_EXIST /* Signature */ diff --git a/include/avr/iom3290pa.h b/include/avr/iom3290pa.h index dd0661b2..3cd80354 100644 --- a/include/avr/iom3290pa.h +++ b/include/avr/iom3290pa.h @@ -978,4 +978,3 @@ #define SLEEP_MODE_STANDBY (0x06<<1) #endif /* #ifdef _AVR_ATMEGA3290PA_H_INCLUDED */ - diff --git a/include/avr/iom32a.h b/include/avr/iom32a.h index e1a4047f..0edb15ab 100644 --- a/include/avr/iom32a.h +++ b/include/avr/iom32a.h @@ -615,4 +615,3 @@ #define SLEEP_MODE_EXT_STANDBY (0x07<<4) #endif /* #ifdef _AVR_ATMEGA32A_H_INCLUDED */ - diff --git a/include/avr/iom32c1.h b/include/avr/iom32c1.h index 47ea11b7..65f6ebe7 100644 --- a/include/avr/iom32c1.h +++ b/include/avr/iom32c1.h @@ -42,7 +42,7 @@ # define _AVR_IOXXX_H_ "iom32c1.h" #else # error "Attempt to include more than one file." -#endif +#endif #ifndef _AVR_ATmega32C1_H_ @@ -1318,4 +1318,3 @@ #define SLEEP_MODE_STANDBY (0x06<<1) #endif /* _AVR_ATmega32C1_H_ */ - diff --git a/include/avr/iom32hvb.h b/include/avr/iom32hvb.h index b5745b49..072de30f 100644 --- a/include/avr/iom32hvb.h +++ b/include/avr/iom32hvb.h @@ -42,7 +42,7 @@ # define _AVR_IOXXX_H_ "iom32hvb.h" #else # error "Attempt to include more than one file." -#endif +#endif #ifndef _AVR_ATmega32HVB_H_ @@ -986,7 +986,7 @@ #define PI_DDR DDRI #define PI_PORT PORTI #define PI_PIN PINI -#define PI_BIT +#define PI_BIT #define NI_DDR DDRNI #define NI_PORT PORTNI @@ -1050,4 +1050,3 @@ #define SLEEP_MODE_PWR_OFF (0x04<<1) #endif /* _AVR_ATmega32HVB_H_ */ - diff --git a/include/avr/iom32hvbrevb.h b/include/avr/iom32hvbrevb.h index 06c9f9c4..5f6489aa 100644 --- a/include/avr/iom32hvbrevb.h +++ b/include/avr/iom32hvbrevb.h @@ -26,7 +26,7 @@ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. + POSSIBILITY OF SUCH DAMAGE. */ /* $Id$ */ @@ -43,7 +43,7 @@ # define _AVR_IOXXX_H_ "iom32hvbrevb.h" #else # error "Attempt to include more than one file." -#endif +#endif #ifndef _AVR_IOM32HVBREVB_H_ diff --git a/include/avr/iom32m1.h b/include/avr/iom32m1.h index 59c7926e..98efd8f6 100644 --- a/include/avr/iom32m1.h +++ b/include/avr/iom32m1.h @@ -42,7 +42,7 @@ # define _AVR_IOXXX_H_ "iom32m1.h" #else # error "Attempt to include more than one file." -#endif +#endif #ifndef _AVR_ATmega32M1_H_ @@ -1623,4 +1623,3 @@ #define SLEEP_MODE_STANDBY (0x06<<1) #endif /* _AVR_ATmega32M1_H_ */ - diff --git a/include/avr/iom32u2.h b/include/avr/iom32u2.h index e8fa1788..35700342 100644 --- a/include/avr/iom32u2.h +++ b/include/avr/iom32u2.h @@ -42,7 +42,7 @@ # define _AVR_IOXXX_H_ "iom32u2.h" #else # error "Attempt to include more than one file." -#endif +#endif #ifndef _AVR_ATmega32U2_H_ @@ -999,4 +999,3 @@ #define SLEEP_MODE_EXT_STANDBY (0x07<<1) #endif /* _AVR_ATmega32U2_H_ */ - diff --git a/include/avr/iom32u4.h b/include/avr/iom32u4.h index a52f0f67..47fba78a 100644 --- a/include/avr/iom32u4.h +++ b/include/avr/iom32u4.h @@ -26,7 +26,7 @@ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. + POSSIBILITY OF SUCH DAMAGE. */ /* $Id$ */ diff --git a/include/avr/iom32u6.h b/include/avr/iom32u6.h index 8098cc0a..4e0dd443 100644 --- a/include/avr/iom32u6.h +++ b/include/avr/iom32u6.h @@ -42,7 +42,7 @@ # define _AVR_IOXXX_H_ "iom32u6.h" #else # error "Attempt to include more than one file." -#endif +#endif #ifndef _AVR_ATmega32U6_H_ @@ -1429,4 +1429,3 @@ #define SLEEP_MODE_EXT_STANDBY (0x07<<1) #endif /* _AVR_ATmega32U6_H_ */ - diff --git a/include/avr/iom406.h b/include/avr/iom406.h index 968f102d..09c2aab7 100644 --- a/include/avr/iom406.h +++ b/include/avr/iom406.h @@ -45,7 +45,7 @@ # define _AVR_IOXXX_H_ "iom406.h" #else # error "Attempt to include more than one file." -#endif +#endif /* I/O registers */ @@ -355,13 +355,13 @@ /* Pin Change Mask Register 1 */ #define PCMSK1 _SFR_MEM8(0x6C) -#define PCINT15 7 -#define PCINT14 6 -#define PCINT13 5 -#define PCINT12 4 -#define PCINT11 3 -#define PCINT10 2 -#define PCINT9 1 +#define PCINT15 7 +#define PCINT14 6 +#define PCINT13 5 +#define PCINT12 4 +#define PCINT11 3 +#define PCINT10 2 +#define PCINT9 1 #define PCINT8 0 /* Reserved [0x6D] */ @@ -766,7 +766,7 @@ /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST -#define __BOOT_LOCK_BITS_1_EXIST +#define __BOOT_LOCK_BITS_1_EXIST /* Signature */ diff --git a/include/avr/iom4808.h b/include/avr/iom4808.h index 08f3c2ab..406ceb81 100644 --- a/include/avr/iom4808.h +++ b/include/avr/iom4808.h @@ -1,4 +1,3 @@ - /* This file is part of avr-libc. Automatically created by devtools/gen-ioheader-atdf-avr8x.py @@ -5059,5 +5058,3 @@ IO Module Instances. Mapped to memory. #endif /* #ifdef _AVR_ATMEGA4808_H_INCLUDED */ - - diff --git a/include/avr/iom4809.h b/include/avr/iom4809.h index 81e484ea..6b332006 100644 --- a/include/avr/iom4809.h +++ b/include/avr/iom4809.h @@ -1,4 +1,3 @@ - /* This file is part of avr-libc. Automatically created by devtools/gen-ioheader-atdf-avr8x.py @@ -5132,5 +5131,3 @@ IO Module Instances. Mapped to memory. #endif /* #ifdef _AVR_ATMEGA4809_H_INCLUDED */ - - diff --git a/include/avr/iom48a.h b/include/avr/iom48a.h index 1f71b033..7a6a03be 100644 --- a/include/avr/iom48a.h +++ b/include/avr/iom48a.h @@ -1,4 +1,3 @@ - /* Copyright (c) 2004, Theodore A. Roth All rights reserved. diff --git a/include/avr/iom48p.h b/include/avr/iom48p.h index 4bd900dd..81d4b553 100644 --- a/include/avr/iom48p.h +++ b/include/avr/iom48p.h @@ -26,7 +26,7 @@ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. + POSSIBILITY OF SUCH DAMAGE. */ /* $Id$ */ @@ -43,7 +43,7 @@ # define _AVR_IOXXX_H_ "iom48p.h" #else # error "Attempt to include more than one file." -#endif +#endif #ifndef _AVR_IOM48P_H_ @@ -827,7 +827,7 @@ #define TIMER1_COMPA_vect _VECTOR(11) /* Timer/Counter1 Compare Match A */ #define TIMER1_COMPB_vect_num 12 -#define TIMER1_COMPB_vect _VECTOR(12) /* Timer/Counter1 Compare Match B */ +#define TIMER1_COMPB_vect _VECTOR(12) /* Timer/Counter1 Compare Match B */ #define TIMER1_OVF_vect_num 13 #define TIMER1_OVF_vect _VECTOR(13) /* Timer/Counter1 Overflow */ @@ -918,7 +918,7 @@ /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST -#define __BOOT_LOCK_BITS_1_EXIST +#define __BOOT_LOCK_BITS_1_EXIST /* Signature */ diff --git a/include/avr/iom48pa.h b/include/avr/iom48pa.h index 3ea906f3..6c8aeb56 100644 --- a/include/avr/iom48pa.h +++ b/include/avr/iom48pa.h @@ -779,4 +779,3 @@ #define SLEEP_MODE_EXT_STANDBY (0x07<<1) #endif /* #ifdef _AVR_ATMEGA48PA_H_INCLUDED */ - diff --git a/include/avr/iom48pb.h b/include/avr/iom48pb.h index d9e7e2d9..3451c54c 100644 --- a/include/avr/iom48pb.h +++ b/include/avr/iom48pb.h @@ -1,890 +1,889 @@ -/***************************************************************************** - * - * Copyright (C) 2016 Atmel Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * * Neither the name of the copyright holders nor the names of - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************/ - - -#ifndef _AVR_ATMEGA48PB_H_INCLUDED -#define _AVR_ATMEGA48PB_H_INCLUDED - - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iom48pb.h" -#else -# error "Attempt to include more than one file." -#endif - -/* Registers and associated bit numbers */ - -#define PINB _SFR_IO8(0x03) -#define PINB7 7 -#define PINB6 6 -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -#define DDRB _SFR_IO8(0x04) -#define DDRB7 7 -// Inserted "DDB7" from "DDRB7" due to compatibility -#define DDB7 7 -#define DDRB6 6 -// Inserted "DDB6" from "DDRB6" due to compatibility -#define DDB6 6 -#define DDRB5 5 -// Inserted "DDB5" from "DDRB5" due to compatibility -#define DDB5 5 -#define DDRB4 4 -// Inserted "DDB4" from "DDRB4" due to compatibility -#define DDB4 4 -#define DDRB3 3 -// Inserted "DDB3" from "DDRB3" due to compatibility -#define DDB3 3 -#define DDRB2 2 -// Inserted "DDB2" from "DDRB2" due to compatibility -#define DDB2 2 -#define DDRB1 1 -// Inserted "DDB1" from "DDRB1" due to compatibility -#define DDB1 1 -#define DDRB0 0 -// Inserted "DDB0" from "DDRB0" due to compatibility -#define DDB0 0 - -#define PORTB _SFR_IO8(0x05) -#define PORTB7 7 -#define PORTB6 6 -#define PORTB5 5 -#define PORTB4 4 -#define PORTB3 3 -#define PORTB2 2 -#define PORTB1 1 -#define PORTB0 0 - -#define PINC _SFR_IO8(0x06) -#define PINC6 6 -#define PINC5 5 -#define PINC4 4 -#define PINC3 3 -#define PINC2 2 -#define PINC1 1 -#define PINC0 0 - -#define DDRC _SFR_IO8(0x07) -#define DDRC6 6 -// Inserted "DDC6" from "DDRC6" due to compatibility -#define DDC6 6 -#define DDRC5 5 -// Inserted "DDC5" from "DDRC5" due to compatibility -#define DDC5 5 -#define DDRC4 4 -// Inserted "DDC4" from "DDRC4" due to compatibility -#define DDC4 4 -#define DDRC3 3 -// Inserted "DDC3" from "DDRC3" due to compatibility -#define DDC3 3 -#define DDRC2 2 -// Inserted "DDC2" from "DDRC2" due to compatibility -#define DDC2 2 -#define DDRC1 1 -// Inserted "DDC1" from "DDRC1" due to compatibility -#define DDC1 1 -#define DDRC0 0 -// Inserted "DDC0" from "DDRC0" due to compatibility -#define DDC0 0 - -#define PORTC _SFR_IO8(0x08) -#define PORTC6 6 -#define PORTC5 5 -#define PORTC4 4 -#define PORTC3 3 -#define PORTC2 2 -#define PORTC1 1 -#define PORTC0 0 - -#define PIND _SFR_IO8(0x09) -#define PIND7 7 -#define PIND6 6 -#define PIND5 5 -#define PIND4 4 -#define PIND3 3 -#define PIND2 2 -#define PIND1 1 -#define PIND0 0 - -#define DDRD _SFR_IO8(0x0A) -#define DDRD7 7 -// Inserted "DDD7" from "DDRD7" due to compatibility -#define DDD7 7 -#define DDRD6 6 -// Inserted "DDD6" from "DDRD6" due to compatibility -#define DDD6 6 -#define DDRD5 5 -// Inserted "DDD5" from "DDRD5" due to compatibility -#define DDD5 5 -#define DDRD4 4 -// Inserted "DDD4" from "DDRD4" due to compatibility -#define DDD4 4 -#define DDRD3 3 -// Inserted "DDD3" from "DDRD3" due to compatibility -#define DDD3 3 -#define DDRD2 2 -// Inserted "DDD2" from "DDRD2" due to compatibility -#define DDD2 2 -#define DDRD1 1 -// Inserted "DDD1" from "DDRD1" due to compatibility -#define DDD1 1 -#define DDRD0 0 -// Inserted "DDD0" from "DDRD0" due to compatibility -#define DDD0 0 - -#define PORTD _SFR_IO8(0x0B) -#define PORTD7 7 -#define PORTD6 6 -#define PORTD5 5 -#define PORTD4 4 -#define PORTD3 3 -#define PORTD2 2 -#define PORTD1 1 -#define PORTD0 0 - -#define PINE _SFR_IO8(0x0C) -#define PINE3 3 -#define PINE2 2 -#define PINE1 1 -#define PINE0 0 - -#define DDRE _SFR_IO8(0x0D) -#define DDRE3 3 -// Inserted "DDE3" from "DDRE3" due to compatibility -#define DDE3 3 -#define DDRE2 2 -// Inserted "DDE2" from "DDRE2" due to compatibility -#define DDE2 2 -#define DDRE1 1 -// Inserted "DDE1" from "DDRE1" due to compatibility -#define DDE1 1 -#define DDRE0 0 -// Inserted "DDE0" from "DDRE0" due to compatibility -#define DDE0 0 - -#define PORTE _SFR_IO8(0x0E) -#define PORTE3 3 -#define PORTE2 2 -#define PORTE1 1 -#define PORTE0 0 - -#define ACSRB _SFR_IO8(0x0F) -#define ACOE 0 - -/* Reserved [0x10..0x14] */ - -#define TIFR0 _SFR_IO8(0x15) -#define TOV0 0 -#define OCF0A 1 -#define OCF0B 2 - -#define TIFR1 _SFR_IO8(0x16) -#define TOV1 0 -#define OCF1A 1 -#define OCF1B 2 -#define ICF1 5 - -#define TIFR2 _SFR_IO8(0x17) -#define TOV2 0 -#define OCF2A 1 -#define OCF2B 2 - -/* Reserved [0x18..0x1A] */ - -#define PCIFR _SFR_IO8(0x1B) -#define PCIF0 0 -#define PCIF1 1 -#define PCIF2 2 - -#define EIFR _SFR_IO8(0x1C) -#define INTF0 0 -#define INTF1 1 - -#define EIMSK _SFR_IO8(0x1D) -#define INT0 0 -#define INT1 1 - -#define GPIOR0 _SFR_IO8(0x1E) - -#define EECR _SFR_IO8(0x1F) -#define EERE 0 -#define EEPE 1 -#define EEMPE 2 -#define EERIE 3 -#define EEPM0 4 -#define EEPM1 5 - -#define EEDR _SFR_IO8(0x20) - -#define EEARL _SFR_IO8(0x21) - -/* Reserved [0x22] */ - -#define GTCCR _SFR_IO8(0x23) -#define PSRSYNC 0 -#define TSM 7 -#define PSRASY 1 - -#define TCCR0A _SFR_IO8(0x24) -#define WGM00 0 -#define WGM01 1 -#define COM0B0 4 -#define COM0B1 5 -#define COM0A0 6 -#define COM0A1 7 - -#define TCCR0B _SFR_IO8(0x25) -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define WGM02 3 -#define FOC0B 6 -#define FOC0A 7 - -#define TCNT0 _SFR_IO8(0x26) - -#define OCR0A _SFR_IO8(0x27) - -#define OCR0B _SFR_IO8(0x28) - -/* Reserved [0x29] */ - -#define GPIOR1 _SFR_IO8(0x2A) - -#define GPIOR2 _SFR_IO8(0x2B) - -#define SPCR _SFR_IO8(0x2C) -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -#define SPSR _SFR_IO8(0x2D) -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -#define SPDR _SFR_IO8(0x2E) - -/* Reserved [0x2F] */ - -#define ACSR _SFR_IO8(0x30) -#define ACIS0 0 -#define ACIS1 1 -#define ACIC 2 -#define ACIE 3 -#define ACI 4 -#define ACO 5 -#define ACBG 6 -#define ACD 7 - -/* Reserved [0x31..0x32] */ - -#define SMCR _SFR_IO8(0x33) -#define SE 0 -#define SM0 1 -#define SM1 2 -#define SM2 3 - -#define MCUSR _SFR_IO8(0x34) -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 - -#define MCUCR _SFR_IO8(0x35) -#define PUD 4 -#define BODSE 5 -#define BODS 6 - -/* Reserved [0x36] */ - -#define SPMCSR _SFR_IO8(0x37) -#define SELFPRGEN 0 -#define PGERS 1 -#define PGWRT 2 -#define BLBSET 3 -#define RWWSRE 4 -#define RWWSB 6 -#define SPMIE 7 - -/* Reserved [0x38..0x3C] */ - -/* SP [0x3D..0x3E] */ - -/* SREG [0x3F] */ - -#define WDTCSR _SFR_MEM8(0x60) -#define WDE 3 -#define WDCE 4 -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDP3 5 -#define WDIE 6 -#define WDIF 7 - -#define CLKPR _SFR_MEM8(0x61) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPS2 2 -#define CLKPS3 3 -#define CLKPCE 7 - -/* Reserved [0x62..0x63] */ - -#define PRR _SFR_MEM8(0x64) -#define PRADC 0 -#define PRUSART0 1 -#define PRSPI 2 -#define PRTIM1 3 -#define PRTIM0 5 -#define PRTIM2 6 -#define PRTWI 7 - -#define __AVR_HAVE_PRR ((1< instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iom48pb.h" +#else +# error "Attempt to include more than one file." +#endif + +/* Registers and associated bit numbers */ + +#define PINB _SFR_IO8(0x03) +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +#define DDRB _SFR_IO8(0x04) +#define DDRB7 7 +// Inserted "DDB7" from "DDRB7" due to compatibility +#define DDB7 7 +#define DDRB6 6 +// Inserted "DDB6" from "DDRB6" due to compatibility +#define DDB6 6 +#define DDRB5 5 +// Inserted "DDB5" from "DDRB5" due to compatibility +#define DDB5 5 +#define DDRB4 4 +// Inserted "DDB4" from "DDRB4" due to compatibility +#define DDB4 4 +#define DDRB3 3 +// Inserted "DDB3" from "DDRB3" due to compatibility +#define DDB3 3 +#define DDRB2 2 +// Inserted "DDB2" from "DDRB2" due to compatibility +#define DDB2 2 +#define DDRB1 1 +// Inserted "DDB1" from "DDRB1" due to compatibility +#define DDB1 1 +#define DDRB0 0 +// Inserted "DDB0" from "DDRB0" due to compatibility +#define DDB0 0 + +#define PORTB _SFR_IO8(0x05) +#define PORTB7 7 +#define PORTB6 6 +#define PORTB5 5 +#define PORTB4 4 +#define PORTB3 3 +#define PORTB2 2 +#define PORTB1 1 +#define PORTB0 0 + +#define PINC _SFR_IO8(0x06) +#define PINC6 6 +#define PINC5 5 +#define PINC4 4 +#define PINC3 3 +#define PINC2 2 +#define PINC1 1 +#define PINC0 0 + +#define DDRC _SFR_IO8(0x07) +#define DDRC6 6 +// Inserted "DDC6" from "DDRC6" due to compatibility +#define DDC6 6 +#define DDRC5 5 +// Inserted "DDC5" from "DDRC5" due to compatibility +#define DDC5 5 +#define DDRC4 4 +// Inserted "DDC4" from "DDRC4" due to compatibility +#define DDC4 4 +#define DDRC3 3 +// Inserted "DDC3" from "DDRC3" due to compatibility +#define DDC3 3 +#define DDRC2 2 +// Inserted "DDC2" from "DDRC2" due to compatibility +#define DDC2 2 +#define DDRC1 1 +// Inserted "DDC1" from "DDRC1" due to compatibility +#define DDC1 1 +#define DDRC0 0 +// Inserted "DDC0" from "DDRC0" due to compatibility +#define DDC0 0 + +#define PORTC _SFR_IO8(0x08) +#define PORTC6 6 +#define PORTC5 5 +#define PORTC4 4 +#define PORTC3 3 +#define PORTC2 2 +#define PORTC1 1 +#define PORTC0 0 + +#define PIND _SFR_IO8(0x09) +#define PIND7 7 +#define PIND6 6 +#define PIND5 5 +#define PIND4 4 +#define PIND3 3 +#define PIND2 2 +#define PIND1 1 +#define PIND0 0 + +#define DDRD _SFR_IO8(0x0A) +#define DDRD7 7 +// Inserted "DDD7" from "DDRD7" due to compatibility +#define DDD7 7 +#define DDRD6 6 +// Inserted "DDD6" from "DDRD6" due to compatibility +#define DDD6 6 +#define DDRD5 5 +// Inserted "DDD5" from "DDRD5" due to compatibility +#define DDD5 5 +#define DDRD4 4 +// Inserted "DDD4" from "DDRD4" due to compatibility +#define DDD4 4 +#define DDRD3 3 +// Inserted "DDD3" from "DDRD3" due to compatibility +#define DDD3 3 +#define DDRD2 2 +// Inserted "DDD2" from "DDRD2" due to compatibility +#define DDD2 2 +#define DDRD1 1 +// Inserted "DDD1" from "DDRD1" due to compatibility +#define DDD1 1 +#define DDRD0 0 +// Inserted "DDD0" from "DDRD0" due to compatibility +#define DDD0 0 + +#define PORTD _SFR_IO8(0x0B) +#define PORTD7 7 +#define PORTD6 6 +#define PORTD5 5 +#define PORTD4 4 +#define PORTD3 3 +#define PORTD2 2 +#define PORTD1 1 +#define PORTD0 0 + +#define PINE _SFR_IO8(0x0C) +#define PINE3 3 +#define PINE2 2 +#define PINE1 1 +#define PINE0 0 + +#define DDRE _SFR_IO8(0x0D) +#define DDRE3 3 +// Inserted "DDE3" from "DDRE3" due to compatibility +#define DDE3 3 +#define DDRE2 2 +// Inserted "DDE2" from "DDRE2" due to compatibility +#define DDE2 2 +#define DDRE1 1 +// Inserted "DDE1" from "DDRE1" due to compatibility +#define DDE1 1 +#define DDRE0 0 +// Inserted "DDE0" from "DDRE0" due to compatibility +#define DDE0 0 + +#define PORTE _SFR_IO8(0x0E) +#define PORTE3 3 +#define PORTE2 2 +#define PORTE1 1 +#define PORTE0 0 + +#define ACSRB _SFR_IO8(0x0F) +#define ACOE 0 + +/* Reserved [0x10..0x14] */ + +#define TIFR0 _SFR_IO8(0x15) +#define TOV0 0 +#define OCF0A 1 +#define OCF0B 2 + +#define TIFR1 _SFR_IO8(0x16) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define ICF1 5 + +#define TIFR2 _SFR_IO8(0x17) +#define TOV2 0 +#define OCF2A 1 +#define OCF2B 2 + +/* Reserved [0x18..0x1A] */ + +#define PCIFR _SFR_IO8(0x1B) +#define PCIF0 0 +#define PCIF1 1 +#define PCIF2 2 + +#define EIFR _SFR_IO8(0x1C) +#define INTF0 0 +#define INTF1 1 + +#define EIMSK _SFR_IO8(0x1D) +#define INT0 0 +#define INT1 1 + +#define GPIOR0 _SFR_IO8(0x1E) + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEPE 1 +#define EEMPE 2 +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 + +#define EEDR _SFR_IO8(0x20) + +#define EEARL _SFR_IO8(0x21) + +/* Reserved [0x22] */ + +#define GTCCR _SFR_IO8(0x23) +#define PSRSYNC 0 +#define TSM 7 +#define PSRASY 1 + +#define TCCR0A _SFR_IO8(0x24) +#define WGM00 0 +#define WGM01 1 +#define COM0B0 4 +#define COM0B1 5 +#define COM0A0 6 +#define COM0A1 7 + +#define TCCR0B _SFR_IO8(0x25) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define WGM02 3 +#define FOC0B 6 +#define FOC0A 7 + +#define TCNT0 _SFR_IO8(0x26) + +#define OCR0A _SFR_IO8(0x27) + +#define OCR0B _SFR_IO8(0x28) + +/* Reserved [0x29] */ + +#define GPIOR1 _SFR_IO8(0x2A) + +#define GPIOR2 _SFR_IO8(0x2B) + +#define SPCR _SFR_IO8(0x2C) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x2D) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0x2E) + +/* Reserved [0x2F] */ + +#define ACSR _SFR_IO8(0x30) +#define ACIS0 0 +#define ACIS1 1 +#define ACIC 2 +#define ACIE 3 +#define ACI 4 +#define ACO 5 +#define ACBG 6 +#define ACD 7 + +/* Reserved [0x31..0x32] */ + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 +#define SM2 3 + +#define MCUSR _SFR_IO8(0x34) +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 + +#define MCUCR _SFR_IO8(0x35) +#define PUD 4 +#define BODSE 5 +#define BODS 6 + +/* Reserved [0x36] */ + +#define SPMCSR _SFR_IO8(0x37) +#define SELFPRGEN 0 +#define PGERS 1 +#define PGWRT 2 +#define BLBSET 3 +#define RWWSRE 4 +#define RWWSB 6 +#define SPMIE 7 + +/* Reserved [0x38..0x3C] */ + +/* SP [0x3D..0x3E] */ + +/* SREG [0x3F] */ + +#define WDTCSR _SFR_MEM8(0x60) +#define WDE 3 +#define WDCE 4 +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDP3 5 +#define WDIE 6 +#define WDIF 7 + +#define CLKPR _SFR_MEM8(0x61) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLKPS3 3 +#define CLKPCE 7 + +/* Reserved [0x62..0x63] */ + +#define PRR _SFR_MEM8(0x64) +#define PRADC 0 +#define PRUSART0 1 +#define PRSPI 2 +#define PRTIM1 3 +#define PRTIM0 5 +#define PRTIM2 6 +#define PRTWI 7 + +#define __AVR_HAVE_PRR ((1< file." -#endif +#endif /* I/O registers */ @@ -74,7 +74,7 @@ /* ADC Control and Status Register A */ #define ADCSR _SFR_IO8(0x06) /* for backwards compatibility */ -#define ADCSRA _SFR_IO8(0x06) +#define ADCSRA _SFR_IO8(0x06) /* ADC Multiplexer select */ #define ADMUX _SFR_IO8(0x07) @@ -208,7 +208,7 @@ /* MCU Status Register */ #define MCUSR _SFR_IO8(0x34) /* for backwards compatibility */ -#define MCUCSR _SFR_IO8(0x34) +#define MCUCSR _SFR_IO8(0x34) /* MCU general Control Register */ #define MCUCR _SFR_IO8(0x35) @@ -253,7 +253,7 @@ #define PORTG _SFR_MEM8(0x65) /* Store Program Memory Control and Status Register */ -#define SPMCR _SFR_MEM8(0x68) +#define SPMCR _SFR_MEM8(0x68) #define SPMCSR _SFR_MEM8(0x68) /* for backwards compatibility with m128*/ /* External Interrupt Control Register A */ @@ -817,9 +817,9 @@ #define WDP1 1 #define WDP0 0 -/* - The ADHSM bit has been removed from all documentation, - as being not needed at all since the comparator has proven +/* + The ADHSM bit has been removed from all documentation, + as being not needed at all since the comparator has proven to be fast enough even without feeding it more power. */ @@ -1024,7 +1024,7 @@ #define PINA5 5 #define PINA4 4 #define PINA3 3 -#define PINA2 2 +#define PINA2 2 #define PINA1 1 #define PINA0 0 @@ -1054,7 +1054,7 @@ #define PINB5 5 #define PINB4 4 #define PINB3 3 -#define PINB2 2 +#define PINB2 2 #define PINB1 1 #define PINB0 0 @@ -1084,7 +1084,7 @@ #define PINC5 5 #define PINC4 4 #define PINC3 3 -#define PINC2 2 +#define PINC2 2 #define PINC1 1 #define PINC0 0 @@ -1114,7 +1114,7 @@ #define PIND5 5 #define PIND4 4 #define PIND3 3 -#define PIND2 2 +#define PIND2 2 #define PIND1 1 #define PIND0 0 @@ -1144,7 +1144,7 @@ #define PINE5 5 #define PINE4 4 #define PINE3 3 -#define PINE2 2 +#define PINE2 2 #define PINE1 1 #define PINE0 0 @@ -1174,7 +1174,7 @@ #define PINF5 5 #define PINF4 4 #define PINF3 3 -#define PINF2 2 +#define PINF2 2 #define PINF1 1 #define PINF0 0 @@ -1195,7 +1195,7 @@ /* Port G Input Pins - PING */ #define PING4 4 #define PING3 3 -#define PING2 2 +#define PING2 2 #define PING1 1 #define PING0 0 @@ -1250,7 +1250,7 @@ /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST -#define __BOOT_LOCK_BITS_1_EXIST +#define __BOOT_LOCK_BITS_1_EXIST /* Signature */ diff --git a/include/avr/iom640.h b/include/avr/iom640.h index dfe0fee3..fbf5fd94 100644 --- a/include/avr/iom640.h +++ b/include/avr/iom640.h @@ -1,4 +1,4 @@ -/* Copyright (c) 2005 Anatoly Sokolov +/* Copyright (c) 2005 Anatoly Sokolov All rights reserved. Redistribution and use in source and binary forms, with or without @@ -83,7 +83,7 @@ /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST -#define __BOOT_LOCK_BITS_1_EXIST +#define __BOOT_LOCK_BITS_1_EXIST /* Signature */ diff --git a/include/avr/iom644.h b/include/avr/iom644.h index 4af7754a..0e67a17b 100644 --- a/include/avr/iom644.h +++ b/include/avr/iom644.h @@ -83,7 +83,7 @@ /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST -#define __BOOT_LOCK_BITS_1_EXIST +#define __BOOT_LOCK_BITS_1_EXIST /* Signature */ diff --git a/include/avr/iom644a.h b/include/avr/iom644a.h index 7bb51f05..1d3014be 100644 --- a/include/avr/iom644a.h +++ b/include/avr/iom644a.h @@ -1063,4 +1063,3 @@ #endif /* #ifdef _AVR_ATMEGA644A_H_INCLUDED */ - diff --git a/include/avr/iom644p.h b/include/avr/iom644p.h index 55618e8e..b57a9a13 100644 --- a/include/avr/iom644p.h +++ b/include/avr/iom644p.h @@ -83,7 +83,7 @@ /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST -#define __BOOT_LOCK_BITS_1_EXIST +#define __BOOT_LOCK_BITS_1_EXIST /* Signature */ diff --git a/include/avr/iom644pa.h b/include/avr/iom644pa.h index eac60e11..24e98a43 100644 --- a/include/avr/iom644pa.h +++ b/include/avr/iom644pa.h @@ -42,7 +42,7 @@ # define _AVR_IOXXX_H_ "iom644PA.h" #else # error "Attempt to include more than one file." -#endif +#endif #ifndef _AVR_ATmega644PA_H_ @@ -1385,4 +1385,3 @@ #define SLEEP_MODE_EXT_STANDBY (0x07<<1) #endif /* _AVR_ATmega644PA_H_ */ - diff --git a/include/avr/iom645.h b/include/avr/iom645.h index 330fee4c..25dcf884 100644 --- a/include/avr/iom645.h +++ b/include/avr/iom645.h @@ -45,7 +45,7 @@ # define _AVR_IOXXX_H_ "iom645.h" #else # error "Attempt to include more than one file." -#endif +#endif /* Registers and associated bit numbers */ @@ -832,7 +832,7 @@ /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST -#define __BOOT_LOCK_BITS_1_EXIST +#define __BOOT_LOCK_BITS_1_EXIST /* Signature */ diff --git a/include/avr/iom6450.h b/include/avr/iom6450.h index 4afef4b1..82cecf55 100644 --- a/include/avr/iom6450.h +++ b/include/avr/iom6450.h @@ -45,7 +45,7 @@ # define _AVR_IOXXX_H_ "iom6450.h" #else # error "Attempt to include more than one file." -#endif +#endif /* Registers and associated bit numbers */ @@ -926,7 +926,7 @@ /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST -#define __BOOT_LOCK_BITS_1_EXIST +#define __BOOT_LOCK_BITS_1_EXIST /* Signature */ diff --git a/include/avr/iom649.h b/include/avr/iom649.h index c1f4478e..a6c0df43 100644 --- a/include/avr/iom649.h +++ b/include/avr/iom649.h @@ -1,5 +1,5 @@ /* Copyright (c) 2004 Eric B. Weddington - Copyright (c) 2005,2006 Anatoly Sokolov + Copyright (c) 2005,2006 Anatoly Sokolov All rights reserved. Redistribution and use in source and binary forms, with or without @@ -46,7 +46,7 @@ # define _AVR_IOXXX_H_ "iom649.h" #else # error "Attempt to include more than one file." -#endif +#endif /* Registers and associated bit numbers */ @@ -1013,7 +1013,7 @@ /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST -#define __BOOT_LOCK_BITS_1_EXIST +#define __BOOT_LOCK_BITS_1_EXIST /* Signature */ diff --git a/include/avr/iom6490.h b/include/avr/iom6490.h index 958eff53..feb099a2 100644 --- a/include/avr/iom6490.h +++ b/include/avr/iom6490.h @@ -1,5 +1,5 @@ /* Copyright (c) 2004 Eric B. Weddington - Copyright (c) 2005,2006 Anatoly Sokolov + Copyright (c) 2005,2006 Anatoly Sokolov All rights reserved. Redistribution and use in source and binary forms, with or without @@ -46,7 +46,7 @@ # define _AVR_IOXXX_H_ "iom6490.h" #else # error "Attempt to include more than one file." -#endif +#endif /* Registers and associated bit numbers */ @@ -1167,7 +1167,7 @@ /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST -#define __BOOT_LOCK_BITS_1_EXIST +#define __BOOT_LOCK_BITS_1_EXIST /* Signature */ diff --git a/include/avr/iom649p.h b/include/avr/iom649p.h index 2b09a02d..7d9feb3c 100644 --- a/include/avr/iom649p.h +++ b/include/avr/iom649p.h @@ -42,7 +42,7 @@ # define _AVR_IOXXX_H_ "iom649p.h" #else # error "Attempt to include more than one file." -#endif +#endif #ifndef _AVR_ATmega649_H_ @@ -1488,4 +1488,3 @@ #define SLEEP_MODE_STANDBY (0x06<<1) #endif /* _AVR_ATmega649_H_ */ - diff --git a/include/avr/iom64a.h b/include/avr/iom64a.h index b5bb706d..ef9b5300 100644 --- a/include/avr/iom64a.h +++ b/include/avr/iom64a.h @@ -975,4 +975,3 @@ #define SLEEP_MODE_EXT_STANDBY (0x07<<2) #endif /* #ifdef _AVR_ATMEGA64A_H_INCLUDED */ - diff --git a/include/avr/iom64c1.h b/include/avr/iom64c1.h index 2c261f60..fc027599 100644 --- a/include/avr/iom64c1.h +++ b/include/avr/iom64c1.h @@ -42,7 +42,7 @@ # define _AVR_IOXXX_H_ "iom64c1.h" #else # error "Attempt to include more than one file." -#endif +#endif #ifndef _AVR_ATmega64C1_H_ @@ -1319,4 +1319,3 @@ #define SLEEP_MODE_STANDBY (0x06<<1) #endif /* _AVR_ATmega64C1_H_ */ - diff --git a/include/avr/iom64hve.h b/include/avr/iom64hve.h index 1e2aa838..e1d95cd0 100644 --- a/include/avr/iom64hve.h +++ b/include/avr/iom64hve.h @@ -42,7 +42,7 @@ # define _AVR_IOXXX_H_ "iom64hve.h" #else # error "Attempt to include more than one file." -#endif +#endif #ifndef _AVR_ATmega64HVE_H_ @@ -965,7 +965,7 @@ #define PI_DDR DDRI #define PI_PORT PORTI #define PI_PIN PINI -#define PI_BIT +#define PI_BIT #define NI_DDR DDRNI #define NI_PORT PORTNI @@ -1031,4 +1031,3 @@ #define SLEEP_MODE_EXT_STANDBY (0x07<<1) #endif /* _AVR_ATmega64HVE_H_ */ - diff --git a/include/avr/iom64hve2.h b/include/avr/iom64hve2.h index 91a310c9..6726923b 100644 --- a/include/avr/iom64hve2.h +++ b/include/avr/iom64hve2.h @@ -1,767 +1,766 @@ -/***************************************************************************** - * - * Copyright (C) 2016 Atmel Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * * Neither the name of the copyright holders nor the names of - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************/ - - -#ifndef _AVR_ATMEGA64HVE2_H_INCLUDED -#define _AVR_ATMEGA64HVE2_H_INCLUDED - - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iom64hve2.h" -#else -# error "Attempt to include more than one file." -#endif - -/* Registers and associated bit numbers */ - -#define PINA _SFR_IO8(0x00) -#define PINA1 1 -#define PINA0 0 - -#define DDRA _SFR_IO8(0x01) -#define DDRA1 1 -// Inserted "DDA1" from "DDRA1" due to compatibility -#define DDA1 1 -#define DDRA0 0 -// Inserted "DDA0" from "DDRA0" due to compatibility -#define DDA0 0 - -#define PORTA _SFR_IO8(0x02) -#define PORTA1 1 -#define PORTA0 0 - -#define PINB _SFR_IO8(0x03) -#define PINB7 7 -#define PINB6 6 -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -#define DDRB _SFR_IO8(0x04) -#define DDRB7 7 -// Inserted "DDB7" from "DDRB7" due to compatibility -#define DDB7 7 -#define DDRB6 6 -// Inserted "DDB6" from "DDRB6" due to compatibility -#define DDB6 6 -#define DDRB5 5 -// Inserted "DDB5" from "DDRB5" due to compatibility -#define DDB5 5 -#define DDRB4 4 -// Inserted "DDB4" from "DDRB4" due to compatibility -#define DDB4 4 -#define DDRB3 3 -// Inserted "DDB3" from "DDRB3" due to compatibility -#define DDB3 3 -#define DDRB2 2 -// Inserted "DDB2" from "DDRB2" due to compatibility -#define DDB2 2 -#define DDRB1 1 -// Inserted "DDB1" from "DDRB1" due to compatibility -#define DDB1 1 -#define DDRB0 0 -// Inserted "DDB0" from "DDRB0" due to compatibility -#define DDB0 0 - -#define PORTB _SFR_IO8(0x05) -#define PORTB7 7 -#define PORTB6 6 -#define PORTB5 5 -#define PORTB4 4 -#define PORTB3 3 -#define PORTB2 2 -#define PORTB1 1 -#define PORTB0 0 - -/* Reserved [0x06..0x14] */ - -#define TIFR0 _SFR_IO8(0x15) -#define TOV0 0 -#define OCF0A 1 -#define OCF0B 2 -#define ICF0 3 - -#define TIFR1 _SFR_IO8(0x16) -#define TOV1 0 -#define OCF1A 1 -#define OCF1B 2 -#define ICF1 3 - -/* Reserved [0x17..0x1A] */ - -#define PCIFR _SFR_IO8(0x1B) -#define PCIF0 0 -#define PCIF1 1 - -#define EIFR _SFR_IO8(0x1C) -#define INTF0 0 - -#define EIMSK _SFR_IO8(0x1D) -#define INT0 0 - -#define GPIOR0 _SFR_IO8(0x1E) - -#define EECR _SFR_IO8(0x1F) -#define EERE 0 -#define EEPE 1 -#define EEMPE 2 -#define EERIE 3 -#define EEPM0 4 -#define EEPM1 5 - -#define EEDR _SFR_IO8(0x20) - -/* Combine EEARL and EEARH */ -#define EEAR _SFR_IO16(0x21) - -#define EEARL _SFR_IO8(0x21) -#define EEARH _SFR_IO8(0x22) - -#define GTCCR _SFR_IO8(0x23) -#define PSRSYNC 0 -#define TSM 7 - -#define TCCR0A _SFR_IO8(0x24) -#define WGM00 0 -#define ICS0 3 -#define ICES0 4 -#define ICNC0 5 -#define ICEN0 6 -#define TCW0 7 - -#define TCCR0B _SFR_IO8(0x25) -#define CS00 0 -#define CS01 1 -#define CS02 2 - -/* Combine TCNT0L and TCNT0H */ -#define TCNT0 _SFR_IO16(0x26) - -#define TCNT0L _SFR_IO8(0x26) -#define TCNT0H _SFR_IO8(0x27) - -#define OCR0A _SFR_IO8(0x28) - -#define OCR0B _SFR_IO8(0x29) - -#define GPIOR1 _SFR_IO8(0x2A) - -#define GPIOR2 _SFR_IO8(0x2B) - -#define SPCR _SFR_IO8(0x2C) -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -#define SPSR _SFR_IO8(0x2D) -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -#define SPDR _SFR_IO8(0x2E) - -/* Reserved [0x2F..0x32] */ - -#define SMCR _SFR_IO8(0x33) -#define SE 0 -#define SM0 1 -#define SM1 2 -#define SM2 3 - -#define MCUSR _SFR_IO8(0x34) -#define PORF 0 -#define EXTRF 1 -#define BODRF 2 -#define WDRF 3 -#define OCDRF 4 - -#define MCUCR _SFR_IO8(0x35) -#define IVCE 0 -#define IVSEL 1 -#define PUD 4 -#define CKOE 5 - -/* Reserved [0x36] */ - -#define SPMCSR _SFR_IO8(0x37) -#define SPMEN 0 -#define PGERS 1 -#define PGWRT 2 -#define LBSET 3 -#define RWWSRE 4 -#define SIGRD 5 -#define RWWSB 6 -#define SPMIE 7 - -/* Reserved [0x38..0x3C] */ - -/* SP [0x3D..0x3E] */ - -/* SREG [0x3F] */ - -#define WDTCSR _SFR_MEM8(0x60) -#define WDE 3 -#define WDCE 4 -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDP3 5 -#define WDIE 6 -#define WDIF 7 - -#define CLKPR _SFR_MEM8(0x61) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPCE 7 - -#define WUTCSR _SFR_MEM8(0x62) -#define WUTP0 0 -#define WUTP1 1 -#define WUTP2 2 -#define WUTE 3 -#define WUTR 4 -#define WUTIE 6 -#define WUTIF 7 - -#define WDTCLR _SFR_MEM8(0x63) -#define WDCLE 0 -#define WDCL0 1 -#define WDCL1 2 - -#define PRR0 _SFR_MEM8(0x64) -#define PRTIM0 0 -#define PRTIM1 1 -#define PRSPI 2 -#define PRLIN 3 - -#define __AVR_HAVE_PRR0 ((1< instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iom64hve2.h" +#else +# error "Attempt to include more than one file." +#endif + +/* Registers and associated bit numbers */ + +#define PINA _SFR_IO8(0x00) +#define PINA1 1 +#define PINA0 0 + +#define DDRA _SFR_IO8(0x01) +#define DDRA1 1 +// Inserted "DDA1" from "DDRA1" due to compatibility +#define DDA1 1 +#define DDRA0 0 +// Inserted "DDA0" from "DDRA0" due to compatibility +#define DDA0 0 + +#define PORTA _SFR_IO8(0x02) +#define PORTA1 1 +#define PORTA0 0 + +#define PINB _SFR_IO8(0x03) +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +#define DDRB _SFR_IO8(0x04) +#define DDRB7 7 +// Inserted "DDB7" from "DDRB7" due to compatibility +#define DDB7 7 +#define DDRB6 6 +// Inserted "DDB6" from "DDRB6" due to compatibility +#define DDB6 6 +#define DDRB5 5 +// Inserted "DDB5" from "DDRB5" due to compatibility +#define DDB5 5 +#define DDRB4 4 +// Inserted "DDB4" from "DDRB4" due to compatibility +#define DDB4 4 +#define DDRB3 3 +// Inserted "DDB3" from "DDRB3" due to compatibility +#define DDB3 3 +#define DDRB2 2 +// Inserted "DDB2" from "DDRB2" due to compatibility +#define DDB2 2 +#define DDRB1 1 +// Inserted "DDB1" from "DDRB1" due to compatibility +#define DDB1 1 +#define DDRB0 0 +// Inserted "DDB0" from "DDRB0" due to compatibility +#define DDB0 0 + +#define PORTB _SFR_IO8(0x05) +#define PORTB7 7 +#define PORTB6 6 +#define PORTB5 5 +#define PORTB4 4 +#define PORTB3 3 +#define PORTB2 2 +#define PORTB1 1 +#define PORTB0 0 + +/* Reserved [0x06..0x14] */ + +#define TIFR0 _SFR_IO8(0x15) +#define TOV0 0 +#define OCF0A 1 +#define OCF0B 2 +#define ICF0 3 + +#define TIFR1 _SFR_IO8(0x16) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define ICF1 3 + +/* Reserved [0x17..0x1A] */ + +#define PCIFR _SFR_IO8(0x1B) +#define PCIF0 0 +#define PCIF1 1 + +#define EIFR _SFR_IO8(0x1C) +#define INTF0 0 + +#define EIMSK _SFR_IO8(0x1D) +#define INT0 0 + +#define GPIOR0 _SFR_IO8(0x1E) + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEPE 1 +#define EEMPE 2 +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 + +#define EEDR _SFR_IO8(0x20) + +/* Combine EEARL and EEARH */ +#define EEAR _SFR_IO16(0x21) + +#define EEARL _SFR_IO8(0x21) +#define EEARH _SFR_IO8(0x22) + +#define GTCCR _SFR_IO8(0x23) +#define PSRSYNC 0 +#define TSM 7 + +#define TCCR0A _SFR_IO8(0x24) +#define WGM00 0 +#define ICS0 3 +#define ICES0 4 +#define ICNC0 5 +#define ICEN0 6 +#define TCW0 7 + +#define TCCR0B _SFR_IO8(0x25) +#define CS00 0 +#define CS01 1 +#define CS02 2 + +/* Combine TCNT0L and TCNT0H */ +#define TCNT0 _SFR_IO16(0x26) + +#define TCNT0L _SFR_IO8(0x26) +#define TCNT0H _SFR_IO8(0x27) + +#define OCR0A _SFR_IO8(0x28) + +#define OCR0B _SFR_IO8(0x29) + +#define GPIOR1 _SFR_IO8(0x2A) + +#define GPIOR2 _SFR_IO8(0x2B) + +#define SPCR _SFR_IO8(0x2C) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x2D) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0x2E) + +/* Reserved [0x2F..0x32] */ + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 +#define SM2 3 + +#define MCUSR _SFR_IO8(0x34) +#define PORF 0 +#define EXTRF 1 +#define BODRF 2 +#define WDRF 3 +#define OCDRF 4 + +#define MCUCR _SFR_IO8(0x35) +#define IVCE 0 +#define IVSEL 1 +#define PUD 4 +#define CKOE 5 + +/* Reserved [0x36] */ + +#define SPMCSR _SFR_IO8(0x37) +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define LBSET 3 +#define RWWSRE 4 +#define SIGRD 5 +#define RWWSB 6 +#define SPMIE 7 + +/* Reserved [0x38..0x3C] */ + +/* SP [0x3D..0x3E] */ + +/* SREG [0x3F] */ + +#define WDTCSR _SFR_MEM8(0x60) +#define WDE 3 +#define WDCE 4 +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDP3 5 +#define WDIE 6 +#define WDIF 7 + +#define CLKPR _SFR_MEM8(0x61) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPCE 7 + +#define WUTCSR _SFR_MEM8(0x62) +#define WUTP0 0 +#define WUTP1 1 +#define WUTP2 2 +#define WUTE 3 +#define WUTR 4 +#define WUTIE 6 +#define WUTIF 7 + +#define WDTCLR _SFR_MEM8(0x63) +#define WDCLE 0 +#define WDCL0 1 +#define WDCL1 2 + +#define PRR0 _SFR_MEM8(0x64) +#define PRTIM0 0 +#define PRTIM1 1 +#define PRSPI 2 +#define PRLIN 3 + +#define __AVR_HAVE_PRR0 ((1< file." -#endif +#endif #ifndef _AVR_ATmega64M1_H_ @@ -1570,4 +1570,3 @@ #define SLEEP_MODE_STANDBY (0x06<<1) #endif /* _AVR_ATmega64M1_H_ */ - diff --git a/include/avr/iom8.h b/include/avr/iom8.h index 9f185d95..fbec1efd 100644 --- a/include/avr/iom8.h +++ b/include/avr/iom8.h @@ -45,7 +45,7 @@ # define _AVR_IOXXX_H_ "iom8.h" #else # error "Attempt to include more than one file." -#endif +#endif /* I/O registers */ @@ -346,9 +346,9 @@ #define EXTRF 1 #define PORF 0 -/* - The ADHSM bit has been removed from all documentation, - as being not needed at all since the comparator has proven +/* + The ADHSM bit has been removed from all documentation, + as being not needed at all since the comparator has proven to be fast enough even without feeding it more power. */ @@ -621,7 +621,7 @@ /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST -#define __BOOT_LOCK_BITS_1_EXIST +#define __BOOT_LOCK_BITS_1_EXIST /* Signature */ diff --git a/include/avr/iom808.h b/include/avr/iom808.h index e950f296..bee2e053 100644 --- a/include/avr/iom808.h +++ b/include/avr/iom808.h @@ -5057,5 +5057,3 @@ IO Module Instances. Mapped to memory. #endif /* #ifdef _AVR_ATMEGA808_H_INCLUDED */ - - diff --git a/include/avr/iom809.h b/include/avr/iom809.h index da2262df..171b4185 100644 --- a/include/avr/iom809.h +++ b/include/avr/iom809.h @@ -1,4 +1,3 @@ - /* This file is part of avr-libc. Automatically created by devtools/gen-ioheader-atdf-avr8x.py @@ -5132,5 +5131,3 @@ IO Module Instances. Mapped to memory. #endif /* #ifdef _AVR_ATMEGA809_H_INCLUDED */ - - diff --git a/include/avr/iom8515.h b/include/avr/iom8515.h index a62432f3..d589e206 100644 --- a/include/avr/iom8515.h +++ b/include/avr/iom8515.h @@ -45,7 +45,7 @@ # define _AVR_IOXXX_H_ "iom8515.h" #else # error "Attempt to include more than one file." -#endif +#endif /* I/O registers */ @@ -641,7 +641,7 @@ /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST -#define __BOOT_LOCK_BITS_1_EXIST +#define __BOOT_LOCK_BITS_1_EXIST /* Signature */ diff --git a/include/avr/iom8535.h b/include/avr/iom8535.h index 9754e340..bf8e424e 100644 --- a/include/avr/iom8535.h +++ b/include/avr/iom8535.h @@ -45,7 +45,7 @@ # define _AVR_IOXXX_H_ "iom8535.h" #else # error "Attempt to include more than one file." -#endif +#endif /* I/O registers */ @@ -414,9 +414,9 @@ #define CS01 1 #define CS00 0 -/* - The ADHSM bit has been removed from all documentation, - as being not needed at all since the comparator has proven +/* + The ADHSM bit has been removed from all documentation, + as being not needed at all since the comparator has proven to be fast enough even without feeding it more power. */ @@ -724,7 +724,7 @@ /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST -#define __BOOT_LOCK_BITS_1_EXIST +#define __BOOT_LOCK_BITS_1_EXIST /* Signature */ diff --git a/include/avr/iom88.h b/include/avr/iom88.h index 3286413c..c5d44ce8 100644 --- a/include/avr/iom88.h +++ b/include/avr/iom88.h @@ -80,7 +80,7 @@ /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST -#define __BOOT_LOCK_BITS_1_EXIST +#define __BOOT_LOCK_BITS_1_EXIST /* Signature */ diff --git a/include/avr/iom88p.h b/include/avr/iom88p.h index 2ab4bc49..0c0837ba 100644 --- a/include/avr/iom88p.h +++ b/include/avr/iom88p.h @@ -26,7 +26,7 @@ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. + POSSIBILITY OF SUCH DAMAGE. */ /* $Id$ */ @@ -43,7 +43,7 @@ # define _AVR_IOXXX_H_ "iom88p.h" #else # error "Attempt to include more than one file." -#endif +#endif #ifndef _AVR_IOM88P_H_ @@ -331,7 +331,7 @@ #define WDRF 3 #define MCUCR _SFR_IO8(0x35) -#define IVCE 0 +#define IVCE 0 #define IVSEL 1 #define PUD 4 #define BODSE 5 @@ -830,7 +830,7 @@ #define TIMER1_COMPA_vect _VECTOR(11) /* Timer/Counter1 Compare Match A */ #define TIMER1_COMPB_vect_num 12 -#define TIMER1_COMPB_vect _VECTOR(12) /* Timer/Counter1 Compare Match B */ +#define TIMER1_COMPB_vect _VECTOR(12) /* Timer/Counter1 Compare Match B */ #define TIMER1_OVF_vect_num 13 #define TIMER1_OVF_vect _VECTOR(13) /* Timer/Counter1 Overflow */ @@ -923,7 +923,7 @@ /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST -#define __BOOT_LOCK_BITS_1_EXIST +#define __BOOT_LOCK_BITS_1_EXIST /* Signature */ diff --git a/include/avr/iom88pa.h b/include/avr/iom88pa.h index 62792d44..ea0611e7 100644 --- a/include/avr/iom88pa.h +++ b/include/avr/iom88pa.h @@ -42,7 +42,7 @@ # define _AVR_IOXXX_H_ "iom88pa.h" #else # error "Attempt to include more than one file." -#endif +#endif #ifndef _AVR_ATmega88PA_H_ @@ -1183,4 +1183,3 @@ #define SLEEP_MODE_EXT_STANDBY (0x07<<1) #endif /* _AVR_ATmega88PA_H_ */ - diff --git a/include/avr/iom88pb.h b/include/avr/iom88pb.h index 9ec34dbf..c148f062 100644 --- a/include/avr/iom88pb.h +++ b/include/avr/iom88pb.h @@ -1,899 +1,898 @@ -/***************************************************************************** - * - * Copyright (C) 2016 Atmel Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * * Neither the name of the copyright holders nor the names of - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************/ - - -#ifndef _AVR_ATMEGA88PB_H_INCLUDED -#define _AVR_ATMEGA88PB_H_INCLUDED - - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iom88pb.h" -#else -# error "Attempt to include more than one file." -#endif - -/* Registers and associated bit numbers */ - -#define PINB _SFR_IO8(0x03) -#define PINB7 7 -#define PINB6 6 -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -#define DDRB _SFR_IO8(0x04) -#define DDRB7 7 -// Inserted "DDB7" from "DDRB7" due to compatibility -#define DDB7 7 -#define DDRB6 6 -// Inserted "DDB6" from "DDRB6" due to compatibility -#define DDB6 6 -#define DDRB5 5 -// Inserted "DDB5" from "DDRB5" due to compatibility -#define DDB5 5 -#define DDRB4 4 -// Inserted "DDB4" from "DDRB4" due to compatibility -#define DDB4 4 -#define DDRB3 3 -// Inserted "DDB3" from "DDRB3" due to compatibility -#define DDB3 3 -#define DDRB2 2 -// Inserted "DDB2" from "DDRB2" due to compatibility -#define DDB2 2 -#define DDRB1 1 -// Inserted "DDB1" from "DDRB1" due to compatibility -#define DDB1 1 -#define DDRB0 0 -// Inserted "DDB0" from "DDRB0" due to compatibility -#define DDB0 0 - -#define PORTB _SFR_IO8(0x05) -#define PORTB7 7 -#define PORTB6 6 -#define PORTB5 5 -#define PORTB4 4 -#define PORTB3 3 -#define PORTB2 2 -#define PORTB1 1 -#define PORTB0 0 - -#define PINC _SFR_IO8(0x06) -#define PINC6 6 -#define PINC5 5 -#define PINC4 4 -#define PINC3 3 -#define PINC2 2 -#define PINC1 1 -#define PINC0 0 - -#define DDRC _SFR_IO8(0x07) -#define DDRC6 6 -// Inserted "DDC6" from "DDRC6" due to compatibility -#define DDC6 6 -#define DDRC5 5 -// Inserted "DDC5" from "DDRC5" due to compatibility -#define DDC5 5 -#define DDRC4 4 -// Inserted "DDC4" from "DDRC4" due to compatibility -#define DDC4 4 -#define DDRC3 3 -// Inserted "DDC3" from "DDRC3" due to compatibility -#define DDC3 3 -#define DDRC2 2 -// Inserted "DDC2" from "DDRC2" due to compatibility -#define DDC2 2 -#define DDRC1 1 -// Inserted "DDC1" from "DDRC1" due to compatibility -#define DDC1 1 -#define DDRC0 0 -// Inserted "DDC0" from "DDRC0" due to compatibility -#define DDC0 0 - -#define PORTC _SFR_IO8(0x08) -#define PORTC6 6 -#define PORTC5 5 -#define PORTC4 4 -#define PORTC3 3 -#define PORTC2 2 -#define PORTC1 1 -#define PORTC0 0 - -#define PIND _SFR_IO8(0x09) -#define PIND7 7 -#define PIND6 6 -#define PIND5 5 -#define PIND4 4 -#define PIND3 3 -#define PIND2 2 -#define PIND1 1 -#define PIND0 0 - -#define DDRD _SFR_IO8(0x0A) -#define DDRD7 7 -// Inserted "DDD7" from "DDRD7" due to compatibility -#define DDD7 7 -#define DDRD6 6 -// Inserted "DDD6" from "DDRD6" due to compatibility -#define DDD6 6 -#define DDRD5 5 -// Inserted "DDD5" from "DDRD5" due to compatibility -#define DDD5 5 -#define DDRD4 4 -// Inserted "DDD4" from "DDRD4" due to compatibility -#define DDD4 4 -#define DDRD3 3 -// Inserted "DDD3" from "DDRD3" due to compatibility -#define DDD3 3 -#define DDRD2 2 -// Inserted "DDD2" from "DDRD2" due to compatibility -#define DDD2 2 -#define DDRD1 1 -// Inserted "DDD1" from "DDRD1" due to compatibility -#define DDD1 1 -#define DDRD0 0 -// Inserted "DDD0" from "DDRD0" due to compatibility -#define DDD0 0 - -#define PORTD _SFR_IO8(0x0B) -#define PORTD7 7 -#define PORTD6 6 -#define PORTD5 5 -#define PORTD4 4 -#define PORTD3 3 -#define PORTD2 2 -#define PORTD1 1 -#define PORTD0 0 - -#define PINE _SFR_IO8(0x0C) -#define PINE3 3 -#define PINE2 2 -#define PINE1 1 -#define PINE0 0 - -#define DDRE _SFR_IO8(0x0D) -#define DDRE3 3 -// Inserted "DDE3" from "DDRE3" due to compatibility -#define DDE3 3 -#define DDRE2 2 -// Inserted "DDE2" from "DDRE2" due to compatibility -#define DDE2 2 -#define DDRE1 1 -// Inserted "DDE1" from "DDRE1" due to compatibility -#define DDE1 1 -#define DDRE0 0 -// Inserted "DDE0" from "DDRE0" due to compatibility -#define DDE0 0 - -#define PORTE _SFR_IO8(0x0E) -#define PORTE3 3 -#define PORTE2 2 -#define PORTE1 1 -#define PORTE0 0 - -#define ACSRB _SFR_IO8(0x0F) -#define ACOE 0 - -/* Reserved [0x10..0x14] */ - -#define TIFR0 _SFR_IO8(0x15) -#define TOV0 0 -#define OCF0A 1 -#define OCF0B 2 - -#define TIFR1 _SFR_IO8(0x16) -#define TOV1 0 -#define OCF1A 1 -#define OCF1B 2 -#define ICF1 5 - -#define TIFR2 _SFR_IO8(0x17) -#define TOV2 0 -#define OCF2A 1 -#define OCF2B 2 - -/* Reserved [0x18..0x1A] */ - -#define PCIFR _SFR_IO8(0x1B) -#define PCIF0 0 -#define PCIF1 1 -#define PCIF2 2 - -#define EIFR _SFR_IO8(0x1C) -#define INTF0 0 -#define INTF1 1 - -#define EIMSK _SFR_IO8(0x1D) -#define INT0 0 -#define INT1 1 - -#define GPIOR0 _SFR_IO8(0x1E) - -#define EECR _SFR_IO8(0x1F) -#define EERE 0 -#define EEPE 1 -#define EEMPE 2 -#define EERIE 3 -#define EEPM0 4 -#define EEPM1 5 - -#define EEDR _SFR_IO8(0x20) - -/* Combine EEARL and EEARH */ -#define EEAR _SFR_IO16(0x21) - -#define EEARL _SFR_IO8(0x21) -#define EEARH _SFR_IO8(0x22) - -#define GTCCR _SFR_IO8(0x23) -#define PSRSYNC 0 -#define TSM 7 -#define PSRASY 1 - -#define TCCR0A _SFR_IO8(0x24) -#define WGM00 0 -#define WGM01 1 -#define COM0B0 4 -#define COM0B1 5 -#define COM0A0 6 -#define COM0A1 7 - -#define TCCR0B _SFR_IO8(0x25) -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define WGM02 3 -#define FOC0B 6 -#define FOC0A 7 - -#define TCNT0 _SFR_IO8(0x26) - -#define OCR0A _SFR_IO8(0x27) - -#define OCR0B _SFR_IO8(0x28) - -/* Reserved [0x29] */ - -#define GPIOR1 _SFR_IO8(0x2A) - -#define GPIOR2 _SFR_IO8(0x2B) - -#define SPCR _SFR_IO8(0x2C) -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -#define SPSR _SFR_IO8(0x2D) -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -#define SPDR _SFR_IO8(0x2E) - -/* Reserved [0x2F] */ - -#define ACSR _SFR_IO8(0x30) -#define ACIS0 0 -#define ACIS1 1 -#define ACIC 2 -#define ACIE 3 -#define ACI 4 -#define ACO 5 -#define ACBG 6 -#define ACD 7 - -/* Reserved [0x31..0x32] */ - -#define SMCR _SFR_IO8(0x33) -#define SE 0 -#define SM0 1 -#define SM1 2 -#define SM2 3 - -#define MCUSR _SFR_IO8(0x34) -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 - -#define MCUCR _SFR_IO8(0x35) -#define IVCE 0 -#define IVSEL 1 -#define PUD 4 -#define BODSE 5 -#define BODS 6 - -/* Reserved [0x36] */ - -#define SPMCSR _SFR_IO8(0x37) -#define SPMEN 0 -#define PGERS 1 -#define PGWRT 2 -#define BLBSET 3 -#define RWWSRE 4 -#define SIGRD 5 -#define RWWSB 6 -#define SPMIE 7 - -/* Reserved [0x38..0x3C] */ - -/* SP [0x3D..0x3E] */ - -/* SREG [0x3F] */ - -#define WDTCSR _SFR_MEM8(0x60) -#define WDE 3 -#define WDCE 4 -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDP3 5 -#define WDIE 6 -#define WDIF 7 - -#define CLKPR _SFR_MEM8(0x61) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPS2 2 -#define CLKPS3 3 -#define CLKPCE 7 - -/* Reserved [0x62..0x63] */ - -#define PRR _SFR_MEM8(0x64) -#define PRADC 0 -#define PRUSART0 1 -#define PRSPI 2 -#define PRTIM1 3 -#define PRTIM0 5 -#define PRTIM2 6 -#define PRTWI 7 - -#define __AVR_HAVE_PRR ((1< instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iom88pb.h" +#else +# error "Attempt to include more than one file." +#endif + +/* Registers and associated bit numbers */ + +#define PINB _SFR_IO8(0x03) +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +#define DDRB _SFR_IO8(0x04) +#define DDRB7 7 +// Inserted "DDB7" from "DDRB7" due to compatibility +#define DDB7 7 +#define DDRB6 6 +// Inserted "DDB6" from "DDRB6" due to compatibility +#define DDB6 6 +#define DDRB5 5 +// Inserted "DDB5" from "DDRB5" due to compatibility +#define DDB5 5 +#define DDRB4 4 +// Inserted "DDB4" from "DDRB4" due to compatibility +#define DDB4 4 +#define DDRB3 3 +// Inserted "DDB3" from "DDRB3" due to compatibility +#define DDB3 3 +#define DDRB2 2 +// Inserted "DDB2" from "DDRB2" due to compatibility +#define DDB2 2 +#define DDRB1 1 +// Inserted "DDB1" from "DDRB1" due to compatibility +#define DDB1 1 +#define DDRB0 0 +// Inserted "DDB0" from "DDRB0" due to compatibility +#define DDB0 0 + +#define PORTB _SFR_IO8(0x05) +#define PORTB7 7 +#define PORTB6 6 +#define PORTB5 5 +#define PORTB4 4 +#define PORTB3 3 +#define PORTB2 2 +#define PORTB1 1 +#define PORTB0 0 + +#define PINC _SFR_IO8(0x06) +#define PINC6 6 +#define PINC5 5 +#define PINC4 4 +#define PINC3 3 +#define PINC2 2 +#define PINC1 1 +#define PINC0 0 + +#define DDRC _SFR_IO8(0x07) +#define DDRC6 6 +// Inserted "DDC6" from "DDRC6" due to compatibility +#define DDC6 6 +#define DDRC5 5 +// Inserted "DDC5" from "DDRC5" due to compatibility +#define DDC5 5 +#define DDRC4 4 +// Inserted "DDC4" from "DDRC4" due to compatibility +#define DDC4 4 +#define DDRC3 3 +// Inserted "DDC3" from "DDRC3" due to compatibility +#define DDC3 3 +#define DDRC2 2 +// Inserted "DDC2" from "DDRC2" due to compatibility +#define DDC2 2 +#define DDRC1 1 +// Inserted "DDC1" from "DDRC1" due to compatibility +#define DDC1 1 +#define DDRC0 0 +// Inserted "DDC0" from "DDRC0" due to compatibility +#define DDC0 0 + +#define PORTC _SFR_IO8(0x08) +#define PORTC6 6 +#define PORTC5 5 +#define PORTC4 4 +#define PORTC3 3 +#define PORTC2 2 +#define PORTC1 1 +#define PORTC0 0 + +#define PIND _SFR_IO8(0x09) +#define PIND7 7 +#define PIND6 6 +#define PIND5 5 +#define PIND4 4 +#define PIND3 3 +#define PIND2 2 +#define PIND1 1 +#define PIND0 0 + +#define DDRD _SFR_IO8(0x0A) +#define DDRD7 7 +// Inserted "DDD7" from "DDRD7" due to compatibility +#define DDD7 7 +#define DDRD6 6 +// Inserted "DDD6" from "DDRD6" due to compatibility +#define DDD6 6 +#define DDRD5 5 +// Inserted "DDD5" from "DDRD5" due to compatibility +#define DDD5 5 +#define DDRD4 4 +// Inserted "DDD4" from "DDRD4" due to compatibility +#define DDD4 4 +#define DDRD3 3 +// Inserted "DDD3" from "DDRD3" due to compatibility +#define DDD3 3 +#define DDRD2 2 +// Inserted "DDD2" from "DDRD2" due to compatibility +#define DDD2 2 +#define DDRD1 1 +// Inserted "DDD1" from "DDRD1" due to compatibility +#define DDD1 1 +#define DDRD0 0 +// Inserted "DDD0" from "DDRD0" due to compatibility +#define DDD0 0 + +#define PORTD _SFR_IO8(0x0B) +#define PORTD7 7 +#define PORTD6 6 +#define PORTD5 5 +#define PORTD4 4 +#define PORTD3 3 +#define PORTD2 2 +#define PORTD1 1 +#define PORTD0 0 + +#define PINE _SFR_IO8(0x0C) +#define PINE3 3 +#define PINE2 2 +#define PINE1 1 +#define PINE0 0 + +#define DDRE _SFR_IO8(0x0D) +#define DDRE3 3 +// Inserted "DDE3" from "DDRE3" due to compatibility +#define DDE3 3 +#define DDRE2 2 +// Inserted "DDE2" from "DDRE2" due to compatibility +#define DDE2 2 +#define DDRE1 1 +// Inserted "DDE1" from "DDRE1" due to compatibility +#define DDE1 1 +#define DDRE0 0 +// Inserted "DDE0" from "DDRE0" due to compatibility +#define DDE0 0 + +#define PORTE _SFR_IO8(0x0E) +#define PORTE3 3 +#define PORTE2 2 +#define PORTE1 1 +#define PORTE0 0 + +#define ACSRB _SFR_IO8(0x0F) +#define ACOE 0 + +/* Reserved [0x10..0x14] */ + +#define TIFR0 _SFR_IO8(0x15) +#define TOV0 0 +#define OCF0A 1 +#define OCF0B 2 + +#define TIFR1 _SFR_IO8(0x16) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define ICF1 5 + +#define TIFR2 _SFR_IO8(0x17) +#define TOV2 0 +#define OCF2A 1 +#define OCF2B 2 + +/* Reserved [0x18..0x1A] */ + +#define PCIFR _SFR_IO8(0x1B) +#define PCIF0 0 +#define PCIF1 1 +#define PCIF2 2 + +#define EIFR _SFR_IO8(0x1C) +#define INTF0 0 +#define INTF1 1 + +#define EIMSK _SFR_IO8(0x1D) +#define INT0 0 +#define INT1 1 + +#define GPIOR0 _SFR_IO8(0x1E) + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEPE 1 +#define EEMPE 2 +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 + +#define EEDR _SFR_IO8(0x20) + +/* Combine EEARL and EEARH */ +#define EEAR _SFR_IO16(0x21) + +#define EEARL _SFR_IO8(0x21) +#define EEARH _SFR_IO8(0x22) + +#define GTCCR _SFR_IO8(0x23) +#define PSRSYNC 0 +#define TSM 7 +#define PSRASY 1 + +#define TCCR0A _SFR_IO8(0x24) +#define WGM00 0 +#define WGM01 1 +#define COM0B0 4 +#define COM0B1 5 +#define COM0A0 6 +#define COM0A1 7 + +#define TCCR0B _SFR_IO8(0x25) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define WGM02 3 +#define FOC0B 6 +#define FOC0A 7 + +#define TCNT0 _SFR_IO8(0x26) + +#define OCR0A _SFR_IO8(0x27) + +#define OCR0B _SFR_IO8(0x28) + +/* Reserved [0x29] */ + +#define GPIOR1 _SFR_IO8(0x2A) + +#define GPIOR2 _SFR_IO8(0x2B) + +#define SPCR _SFR_IO8(0x2C) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x2D) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0x2E) + +/* Reserved [0x2F] */ + +#define ACSR _SFR_IO8(0x30) +#define ACIS0 0 +#define ACIS1 1 +#define ACIC 2 +#define ACIE 3 +#define ACI 4 +#define ACO 5 +#define ACBG 6 +#define ACD 7 + +/* Reserved [0x31..0x32] */ + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 +#define SM2 3 + +#define MCUSR _SFR_IO8(0x34) +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 + +#define MCUCR _SFR_IO8(0x35) +#define IVCE 0 +#define IVSEL 1 +#define PUD 4 +#define BODSE 5 +#define BODS 6 + +/* Reserved [0x36] */ + +#define SPMCSR _SFR_IO8(0x37) +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define BLBSET 3 +#define RWWSRE 4 +#define SIGRD 5 +#define RWWSB 6 +#define SPMIE 7 + +/* Reserved [0x38..0x3C] */ + +/* SP [0x3D..0x3E] */ + +/* SREG [0x3F] */ + +#define WDTCSR _SFR_MEM8(0x60) +#define WDE 3 +#define WDCE 4 +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDP3 5 +#define WDIE 6 +#define WDIF 7 + +#define CLKPR _SFR_MEM8(0x61) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLKPS3 3 +#define CLKPCE 7 + +/* Reserved [0x62..0x63] */ + +#define PRR _SFR_MEM8(0x64) +#define PRADC 0 +#define PRUSART0 1 +#define PRSPI 2 +#define PRTIM1 3 +#define PRTIM0 5 +#define PRTIM2 6 +#define PRTWI 7 + +#define __AVR_HAVE_PRR ((1< file." -#endif +#endif #ifndef _AVR_ATmega8U2_H_ @@ -996,4 +996,3 @@ #define SLEEP_MODE_EXT_STANDBY (0x07<<1) #endif /* _AVR_ATmega8U2_H_ */ - diff --git a/include/avr/iomx8.h b/include/avr/iomx8.h index b1cc8e78..f836ee4e 100644 --- a/include/avr/iomx8.h +++ b/include/avr/iomx8.h @@ -45,7 +45,7 @@ # define _AVR_IOXXX_H_ "iomx8.h" #else # error "Attempt to include more than one file." -#endif +#endif /* I/O registers */ @@ -203,7 +203,7 @@ #define EEAR _SFR_IO16(0x21) #define EEARL _SFR_IO8(0x21) #define EEARH _SFR_IO8(0X22) -/* +/* Even though EEARH is not used by the mega48, the EEAR8 bit in the register must be written to 0, according to the datasheet, hence the EEARH register must be defined for the mega48. @@ -297,7 +297,7 @@ must be defined for the mega48. #define MCUCR _SFR_IO8 (0x35) /* MCUCR */ #define PUD 4 -#if defined (__AVR_ATmega88__) || defined (__AVR_ATmega168__) +#if defined (__AVR_ATmega88__) || defined (__AVR_ATmega168__) #define IVSEL 1 #define IVCE 0 #endif diff --git a/include/avr/iomxx0_1.h b/include/avr/iomxx0_1.h index 273aee1b..93d25c23 100644 --- a/include/avr/iomxx0_1.h +++ b/include/avr/iomxx0_1.h @@ -1,4 +1,4 @@ -/* Copyright (c) 2005 Anatoly Sokolov +/* Copyright (c) 2005 Anatoly Sokolov All rights reserved. Redistribution and use in source and binary forms, with or without @@ -46,7 +46,7 @@ # define _AVR_IOXXX_H_ "iomxx0_1.h" #else # error "Attempt to include more than one file." -#endif +#endif #if defined(__AVR_ATmega640__) || defined(__AVR_ATmega1280__) || defined(__AVR_ATmega2560__) # define __ATmegaxx0__ @@ -299,7 +299,7 @@ #define TOV5 0 #define PCIFR _SFR_IO8(0x1B) -#if defined(__ATmegaxx0__) +#if defined(__ATmegaxx0__) # define PCIF2 2 #endif /* __ATmegaxx0__ */ #define PCIF1 1 @@ -322,7 +322,7 @@ #define INT4 4 #define INT3 3 #define INT2 2 -#define INT1 1 +#define INT1 1 #define INT0 0 #define GPIOR0 _SFR_IO8(0x1E) @@ -573,7 +573,7 @@ #define PCINT9 1 #define PCINT8 0 -#if defined(__ATmegaxx0__) +#if defined(__ATmegaxx0__) # define PCMSK2 _SFR_MEM8(0x6D) # define PCINT23 7 # define PCINT22 6 @@ -1268,7 +1268,7 @@ /* Reserved [0x12E..0x12F] */ -#if defined(__ATmegaxx0__) +#if defined(__ATmegaxx0__) # define UCSR3A _SFR_MEM8(0x130) # define RXC3 7 diff --git a/include/avr/iomxxhva.h b/include/avr/iomxxhva.h index c3499dd1..a773fbd8 100644 --- a/include/avr/iomxxhva.h +++ b/include/avr/iomxxhva.h @@ -1,4 +1,4 @@ -/* Copyright (c) 2007, Anatoly Sokolov +/* Copyright (c) 2007, Anatoly Sokolov All rights reserved. Redistribution and use in source and binary forms, with or without @@ -45,7 +45,7 @@ # define _AVR_IOXXX_H_ "iomxxhva.h" #else # error "Attempt to include more than one file." -#endif +#endif /* Registers and associated bit numbers */ @@ -115,7 +115,7 @@ #define EIMSK _SFR_IO8(0x1D) #define INT2 2 -#define INT1 1 +#define INT1 1 #define INT0 0 #define GPIOR0 _SFR_IO8(0x1E) diff --git a/include/avr/iotn10.h b/include/avr/iotn10.h index eebb92ae..5ffc0cca 100644 --- a/include/avr/iotn10.h +++ b/include/avr/iotn10.h @@ -42,7 +42,7 @@ # define _AVR_IOXXX_H_ "iotn10.h" #else # error "Attempt to include more than one file." -#endif +#endif #ifndef _AVR_ATtiny10_H_ @@ -510,4 +510,3 @@ #define SLEEP_MODE_STANDBY (0x04<<1) #endif /* _AVR_ATtiny10_H_ */ - diff --git a/include/avr/iotn11.h b/include/avr/iotn11.h index eb487edf..0638b300 100644 --- a/include/avr/iotn11.h +++ b/include/avr/iotn11.h @@ -45,7 +45,7 @@ # define _AVR_IOXXX_H_ "iotn11.h" #else # error "Attempt to include more than one file." -#endif +#endif #ifndef __ASSEMBLER__ # warning "MCU not supported by the C compiler" diff --git a/include/avr/iotn12.h b/include/avr/iotn12.h index b572e787..4f088866 100644 --- a/include/avr/iotn12.h +++ b/include/avr/iotn12.h @@ -45,7 +45,7 @@ # define _AVR_IOXXX_H_ "iotn12.h" #else # error "Attempt to include more than one file." -#endif +#endif #ifndef __ASSEMBLER__ # warning "MCU not supported by the C compiler" diff --git a/include/avr/iotn13.h b/include/avr/iotn13.h index 0c80f663..257fe4a3 100644 --- a/include/avr/iotn13.h +++ b/include/avr/iotn13.h @@ -47,7 +47,7 @@ # define _AVR_IOXXX_H_ "iotn13.h" #else # error "Attempt to include more than one file." -#endif +#endif /* I/O registers and bit names */ diff --git a/include/avr/iotn13a.h b/include/avr/iotn13a.h index 743c6ab9..aee3cd55 100644 --- a/include/avr/iotn13a.h +++ b/include/avr/iotn13a.h @@ -42,7 +42,7 @@ # define _AVR_IOXXX_H_ "iotn13a.h" #else # error "Attempt to include more than one file." -#endif +#endif #ifndef _AVR_ATTINY13A_H_ @@ -392,4 +392,3 @@ #define SLEEP_MODE_PWR_DOWN (0x02<<3) #endif /* _AVR_ATTINY13A_H_ */ - diff --git a/include/avr/iotn15.h b/include/avr/iotn15.h index f29fa098..83f99584 100644 --- a/include/avr/iotn15.h +++ b/include/avr/iotn15.h @@ -45,7 +45,7 @@ # define _AVR_IOXXX_H_ "iotn15.h" #else # error "Attempt to include more than one file." -#endif +#endif #ifndef __ASSEMBLER__ # warning "MCU not supported by the C compiler" diff --git a/include/avr/iotn1604.h b/include/avr/iotn1604.h index b787cb7e..a93fe735 100644 --- a/include/avr/iotn1604.h +++ b/include/avr/iotn1604.h @@ -1,4 +1,3 @@ - /* This file is part of avr-libc. Automatically created by devtools/gen-ioheader-atdf-avr8x.py @@ -4793,5 +4792,3 @@ IO Module Instances. Mapped to memory. #endif /* #ifdef _AVR_ATTINY1604_H_INCLUDED */ - - diff --git a/include/avr/iotn1606.h b/include/avr/iotn1606.h index 90da4e8a..a6b1d564 100644 --- a/include/avr/iotn1606.h +++ b/include/avr/iotn1606.h @@ -1,4 +1,3 @@ - /* This file is part of avr-libc. Automatically created by devtools/gen-ioheader-atdf-avr8x.py @@ -4793,5 +4792,3 @@ IO Module Instances. Mapped to memory. #endif /* #ifdef _AVR_ATTINY1606_H_INCLUDED */ - - diff --git a/include/avr/iotn1607.h b/include/avr/iotn1607.h index 6fd6925c..00a782b1 100644 --- a/include/avr/iotn1607.h +++ b/include/avr/iotn1607.h @@ -1,4 +1,3 @@ - /* This file is part of avr-libc. Automatically created by devtools/gen-ioheader-atdf-avr8x.py @@ -4793,5 +4792,3 @@ IO Module Instances. Mapped to memory. #endif /* #ifdef _AVR_ATTINY1607_H_INCLUDED */ - - diff --git a/include/avr/iotn1614.h b/include/avr/iotn1614.h index 5da69322..84c0f7c0 100644 --- a/include/avr/iotn1614.h +++ b/include/avr/iotn1614.h @@ -1,4 +1,3 @@ - /* This file is part of avr-libc. Automatically created by devtools/gen-ioheader-atdf-avr8x.py @@ -5671,5 +5670,3 @@ IO Module Instances. Mapped to memory. #endif /* #ifdef _AVR_ATTINY1614_H_INCLUDED */ - - diff --git a/include/avr/iotn1616.h b/include/avr/iotn1616.h index 41fe1493..f5481bef 100644 --- a/include/avr/iotn1616.h +++ b/include/avr/iotn1616.h @@ -1,4 +1,3 @@ - /* This file is part of avr-libc. Automatically created by devtools/gen-ioheader-atdf-avr8x.py @@ -5697,5 +5696,3 @@ IO Module Instances. Mapped to memory. #endif /* #ifdef _AVR_ATTINY1616_H_INCLUDED */ - - diff --git a/include/avr/iotn1617.h b/include/avr/iotn1617.h index ea4c64da..fc0137d7 100644 --- a/include/avr/iotn1617.h +++ b/include/avr/iotn1617.h @@ -1,4 +1,3 @@ - /* This file is part of avr-libc. Automatically created by devtools/gen-ioheader-atdf-avr8x.py @@ -5697,5 +5696,3 @@ IO Module Instances. Mapped to memory. #endif /* #ifdef _AVR_ATTINY1617_H_INCLUDED */ - - diff --git a/include/avr/iotn1624.h b/include/avr/iotn1624.h index ea8f27a4..e00e9f66 100644 --- a/include/avr/iotn1624.h +++ b/include/avr/iotn1624.h @@ -1,4 +1,3 @@ - /* This file is part of avr-libc. Automatically created by devtools/gen-ioheader-atdf-avr8x.py @@ -5289,5 +5288,3 @@ IO Module Instances. Mapped to memory. #endif /* #ifdef _AVR_ATTINY1624_H_INCLUDED */ - - diff --git a/include/avr/iotn1626.h b/include/avr/iotn1626.h index 49a4e046..bcdf97c4 100644 --- a/include/avr/iotn1626.h +++ b/include/avr/iotn1626.h @@ -1,4 +1,3 @@ - /* This file is part of avr-libc. Automatically created by devtools/gen-ioheader-atdf-avr8x.py @@ -5333,5 +5332,3 @@ IO Module Instances. Mapped to memory. #endif /* #ifdef _AVR_ATTINY1626_H_INCLUDED */ - - diff --git a/include/avr/iotn1627.h b/include/avr/iotn1627.h index 215f316d..ec93dbd7 100644 --- a/include/avr/iotn1627.h +++ b/include/avr/iotn1627.h @@ -1,4 +1,3 @@ - /* This file is part of avr-libc. Automatically created by devtools/gen-ioheader-atdf-avr8x.py @@ -5356,5 +5355,3 @@ IO Module Instances. Mapped to memory. #endif /* #ifdef _AVR_ATTINY1627_H_INCLUDED */ - - diff --git a/include/avr/iotn1634.h b/include/avr/iotn1634.h index d0ca51af..6c2abcf7 100644 --- a/include/avr/iotn1634.h +++ b/include/avr/iotn1634.h @@ -869,4 +869,3 @@ #define SLEEP_MODE_STANDBY (0x03<<5) #endif /* #ifdef _AVR_ATTINY1634_H_INCLUDED */ - diff --git a/include/avr/iotn167.h b/include/avr/iotn167.h index 4cc89782..ef637f25 100644 --- a/include/avr/iotn167.h +++ b/include/avr/iotn167.h @@ -26,7 +26,7 @@ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. + POSSIBILITY OF SUCH DAMAGE. */ /* $Id$ */ @@ -43,7 +43,7 @@ # define _AVR_IOXXX_H_ "iotn167.h" #else # error "Attempt to include more than one file." -#endif +#endif #ifndef _AVR_IOTN167_H_ @@ -826,7 +826,7 @@ #define XRAMSIZE (0) #define XRAMEND RAMEND #define E2END (0x1FF) -#define E2PAGESIZE (4) +#define E2PAGESIZE (4) #define FLASHEND (0x3FFF) diff --git a/include/avr/iotn20.h b/include/avr/iotn20.h index 0cb21e94..63be577e 100644 --- a/include/avr/iotn20.h +++ b/include/avr/iotn20.h @@ -42,7 +42,7 @@ # define _AVR_IOXXX_H_ "iotn20.h" #else # error "Attempt to include more than one file." -#endif +#endif #ifndef _AVR_ATtiny20_H_ @@ -774,4 +774,3 @@ #define SLEEP_MODE_STANDBY (0x04<<1) #endif /* _AVR_ATtiny20_H_ */ - diff --git a/include/avr/iotn202.h b/include/avr/iotn202.h index 1ed4b79f..a1a52556 100644 --- a/include/avr/iotn202.h +++ b/include/avr/iotn202.h @@ -1,4 +1,3 @@ - /* This file is part of avr-libc. Automatically created by devtools/gen-ioheader-atdf-avr8x.py @@ -4661,5 +4660,3 @@ IO Module Instances. Mapped to memory. #endif /* #ifdef _AVR_ATTINY202_H_INCLUDED */ - - diff --git a/include/avr/iotn204.h b/include/avr/iotn204.h index ff5194df..0a8ebbdf 100644 --- a/include/avr/iotn204.h +++ b/include/avr/iotn204.h @@ -1,4 +1,3 @@ - /* This file is part of avr-libc. Automatically created by devtools/gen-ioheader-atdf-avr8x.py @@ -4736,5 +4735,3 @@ IO Module Instances. Mapped to memory. #endif /* #ifdef _AVR_ATTINY204_H_INCLUDED */ - - diff --git a/include/avr/iotn212.h b/include/avr/iotn212.h index d6a53b51..11f0ae84 100644 --- a/include/avr/iotn212.h +++ b/include/avr/iotn212.h @@ -1,4 +1,3 @@ - /* This file is part of avr-libc. Automatically created by devtools/gen-ioheader-atdf-avr8x.py @@ -5334,5 +5333,3 @@ IO Module Instances. Mapped to memory. #endif /* #ifdef _AVR_ATTINY212_H_INCLUDED */ - - diff --git a/include/avr/iotn214.h b/include/avr/iotn214.h index fad74238..bf87d0fc 100644 --- a/include/avr/iotn214.h +++ b/include/avr/iotn214.h @@ -1,4 +1,3 @@ - /* This file is part of avr-libc. Automatically created by devtools/gen-ioheader-atdf-avr8x.py @@ -5387,5 +5386,3 @@ IO Module Instances. Mapped to memory. #endif /* #ifdef _AVR_ATTINY214_H_INCLUDED */ - - diff --git a/include/avr/iotn22.h b/include/avr/iotn22.h index da83bc18..257e238d 100644 --- a/include/avr/iotn22.h +++ b/include/avr/iotn22.h @@ -45,7 +45,7 @@ # define _AVR_IOXXX_H_ "iotn22.h" #else # error "Attempt to include more than one file." -#endif +#endif /* I/O registers */ diff --git a/include/avr/iotn2313a.h b/include/avr/iotn2313a.h index adb3c831..9a68d8e6 100644 --- a/include/avr/iotn2313a.h +++ b/include/avr/iotn2313a.h @@ -42,7 +42,7 @@ # define _AVR_IOXXX_H_ "iotn2313a.h" #else # error "Attempt to include more than one file." -#endif +#endif #ifndef _AVR_ATtiny2313A_H_ @@ -810,4 +810,3 @@ #define SLEEP_MODE_PWR_DOWN (0x05<<4) #endif /* _AVR_ATtiny2313A_H_ */ - diff --git a/include/avr/iotn24a.h b/include/avr/iotn24a.h index 92aa1703..89fedb99 100644 --- a/include/avr/iotn24a.h +++ b/include/avr/iotn24a.h @@ -42,7 +42,7 @@ # define _AVR_IOXXX_H_ "iotn24a.h" #else # error "Attempt to include more than one file." -#endif +#endif #ifndef _AVR_ATtiny24A_H_ @@ -844,4 +844,3 @@ #define SLEEP_MODE_STANDBY (0x03<<3) #endif /* _AVR_ATtiny24A_H_ */ - diff --git a/include/avr/iotn26.h b/include/avr/iotn26.h index 5df1ded4..560f3ccd 100644 --- a/include/avr/iotn26.h +++ b/include/avr/iotn26.h @@ -42,7 +42,7 @@ # define _AVR_IOXXX_H_ "iotn26.h" #else # error "Attempt to include more than one file." -#endif +#endif #ifndef _AVR_IOTN26_H_ #define _AVR_IOTN26_H_ 1 diff --git a/include/avr/iotn261a.h b/include/avr/iotn261a.h index 933b3af5..4c404f93 100644 --- a/include/avr/iotn261a.h +++ b/include/avr/iotn261a.h @@ -42,7 +42,7 @@ # define _AVR_IOXXX_H_ "iotn261a.h" #else # error "Attempt to include more than one file." -#endif +#endif #ifndef _AVR_ATtiny261A_H_ @@ -985,4 +985,3 @@ #define SLEEP_MODE_STANDBY (0x03<<3) #endif /* _AVR_ATtiny261A_H_ */ - diff --git a/include/avr/iotn28.h b/include/avr/iotn28.h index 3ffc69c0..283e000a 100644 --- a/include/avr/iotn28.h +++ b/include/avr/iotn28.h @@ -45,7 +45,7 @@ # define _AVR_IOXXX_H_ "iotn28.h" #else # error "Attempt to include more than one file." -#endif +#endif #ifndef __ASSEMBLER__ # warning "MCU not supported by the C compiler" diff --git a/include/avr/iotn3214.h b/include/avr/iotn3214.h index 8719cecb..1047afeb 100644 --- a/include/avr/iotn3214.h +++ b/include/avr/iotn3214.h @@ -1,4 +1,3 @@ - /* This file is part of avr-libc. Automatically created by devtools/gen-ioheader-atdf-avr8x.py @@ -5719,5 +5718,3 @@ IO Module Instances. Mapped to memory. #endif /* #ifdef _AVR_ATTINY3214_H_INCLUDED */ - - diff --git a/include/avr/iotn3216.h b/include/avr/iotn3216.h index bbc1fa66..201eb9ed 100644 --- a/include/avr/iotn3216.h +++ b/include/avr/iotn3216.h @@ -1,4 +1,3 @@ - /* This file is part of avr-libc. Automatically created by devtools/gen-ioheader-atdf-avr8x.py @@ -5714,5 +5713,3 @@ IO Module Instances. Mapped to memory. #endif /* #ifdef _AVR_ATTINY3216_H_INCLUDED */ - - diff --git a/include/avr/iotn3217.h b/include/avr/iotn3217.h index cfbc8f30..a03efe57 100644 --- a/include/avr/iotn3217.h +++ b/include/avr/iotn3217.h @@ -1,4 +1,3 @@ - /* This file is part of avr-libc. Automatically created by devtools/gen-ioheader-atdf-avr8x.py @@ -5714,5 +5713,3 @@ IO Module Instances. Mapped to memory. #endif /* #ifdef _AVR_ATTINY3217_H_INCLUDED */ - - diff --git a/include/avr/iotn3224.h b/include/avr/iotn3224.h index d0aea722..5d5ecfb0 100644 --- a/include/avr/iotn3224.h +++ b/include/avr/iotn3224.h @@ -1,4 +1,3 @@ - /* This file is part of avr-libc. Automatically created by devtools/gen-ioheader-atdf-avr8x.py @@ -5289,5 +5288,3 @@ IO Module Instances. Mapped to memory. #endif /* #ifdef _AVR_ATTINY3224_H_INCLUDED */ - - diff --git a/include/avr/iotn3226.h b/include/avr/iotn3226.h index e325541c..8e5bd76a 100644 --- a/include/avr/iotn3226.h +++ b/include/avr/iotn3226.h @@ -1,4 +1,3 @@ - /* This file is part of avr-libc. Automatically created by devtools/gen-ioheader-atdf-avr8x.py @@ -5333,5 +5332,3 @@ IO Module Instances. Mapped to memory. #endif /* #ifdef _AVR_ATTINY3226_H_INCLUDED */ - - diff --git a/include/avr/iotn3227.h b/include/avr/iotn3227.h index 9811f29a..f43d8274 100644 --- a/include/avr/iotn3227.h +++ b/include/avr/iotn3227.h @@ -1,4 +1,3 @@ - /* This file is part of avr-libc. Automatically created by devtools/gen-ioheader-atdf-avr8x.py @@ -5356,5 +5355,3 @@ IO Module Instances. Mapped to memory. #endif /* #ifdef _AVR_ATTINY3227_H_INCLUDED */ - - diff --git a/include/avr/iotn4.h b/include/avr/iotn4.h index 65b545a8..87f9bd6e 100644 --- a/include/avr/iotn4.h +++ b/include/avr/iotn4.h @@ -42,7 +42,7 @@ # define _AVR_IOXXX_H_ "iotn4.h" #else # error "Attempt to include more than one file." -#endif +#endif #ifndef _AVR_ATtiny4_H_ @@ -475,4 +475,3 @@ #define SLEEP_MODE_STANDBY (0x04<<1) #endif /* _AVR_ATtiny4_H_ */ - diff --git a/include/avr/iotn40.h b/include/avr/iotn40.h index ef37b4e7..b263066c 100644 --- a/include/avr/iotn40.h +++ b/include/avr/iotn40.h @@ -42,7 +42,7 @@ # define _AVR_IOXXX_H_ "iotn40.h" #else # error "Attempt to include more than one file." -#endif +#endif #ifndef _AVR_ATtiny40_H_ @@ -765,4 +765,3 @@ #define SLEEP_MODE_STANDBY (0x04<<1) #endif /* _AVR_ATtiny40_H_ */ - diff --git a/include/avr/iotn402.h b/include/avr/iotn402.h index 19ba7f09..e789a40b 100644 --- a/include/avr/iotn402.h +++ b/include/avr/iotn402.h @@ -1,4 +1,3 @@ - /* This file is part of avr-libc. Automatically created by devtools/gen-ioheader-atdf-avr8x.py @@ -4661,5 +4660,3 @@ IO Module Instances. Mapped to memory. #endif /* #ifdef _AVR_ATTINY402_H_INCLUDED */ - - diff --git a/include/avr/iotn404.h b/include/avr/iotn404.h index 5eab7bc6..11cbad1e 100644 --- a/include/avr/iotn404.h +++ b/include/avr/iotn404.h @@ -1,4 +1,3 @@ - /* This file is part of avr-libc. Automatically created by devtools/gen-ioheader-atdf-avr8x.py @@ -4736,5 +4735,3 @@ IO Module Instances. Mapped to memory. #endif /* #ifdef _AVR_ATTINY404_H_INCLUDED */ - - diff --git a/include/avr/iotn406.h b/include/avr/iotn406.h index b611bd2c..63d4a6e1 100644 --- a/include/avr/iotn406.h +++ b/include/avr/iotn406.h @@ -1,4 +1,3 @@ - /* This file is part of avr-libc. Automatically created by devtools/gen-ioheader-atdf-avr8x.py @@ -4733,5 +4732,3 @@ IO Module Instances. Mapped to memory. #endif /* #ifdef _AVR_ATTINY406_H_INCLUDED */ - - diff --git a/include/avr/iotn412.h b/include/avr/iotn412.h index 7af3c12b..06a1de3d 100644 --- a/include/avr/iotn412.h +++ b/include/avr/iotn412.h @@ -1,4 +1,3 @@ - /* This file is part of avr-libc. Automatically created by devtools/gen-ioheader-atdf-avr8x.py @@ -5334,5 +5333,3 @@ IO Module Instances. Mapped to memory. #endif /* #ifdef _AVR_ATTINY412_H_INCLUDED */ - - diff --git a/include/avr/iotn414.h b/include/avr/iotn414.h index 97445659..934aad5c 100644 --- a/include/avr/iotn414.h +++ b/include/avr/iotn414.h @@ -1,4 +1,3 @@ - /* This file is part of avr-libc. Automatically created by devtools/gen-ioheader-atdf-avr8x.py @@ -5387,5 +5386,3 @@ IO Module Instances. Mapped to memory. #endif /* #ifdef _AVR_ATTINY414_H_INCLUDED */ - - diff --git a/include/avr/iotn416.h b/include/avr/iotn416.h index ab2e8736..cf25ff5c 100644 --- a/include/avr/iotn416.h +++ b/include/avr/iotn416.h @@ -1,4 +1,3 @@ - /* This file is part of avr-libc. Automatically created by devtools/gen-ioheader-atdf-avr8x.py @@ -5415,5 +5414,3 @@ IO Module Instances. Mapped to memory. #endif /* #ifdef _AVR_ATTINY416_H_INCLUDED */ - - diff --git a/include/avr/iotn417.h b/include/avr/iotn417.h index b7e7b0a2..7114fed3 100644 --- a/include/avr/iotn417.h +++ b/include/avr/iotn417.h @@ -1,4 +1,3 @@ - /* This file is part of avr-libc. Automatically created by devtools/gen-ioheader-atdf-avr8x.py @@ -5393,5 +5392,3 @@ IO Module Instances. Mapped to memory. #endif /* #ifdef _AVR_ATTINY417_H_INCLUDED */ - - diff --git a/include/avr/iotn424.h b/include/avr/iotn424.h index 5922e0e6..2e15b9a1 100644 --- a/include/avr/iotn424.h +++ b/include/avr/iotn424.h @@ -1,4 +1,3 @@ - /* This file is part of avr-libc. Automatically created by devtools/gen-ioheader-atdf-avr8x.py @@ -5289,5 +5288,3 @@ IO Module Instances. Mapped to memory. #endif /* #ifdef _AVR_ATTINY424_H_INCLUDED */ - - diff --git a/include/avr/iotn426.h b/include/avr/iotn426.h index d6c7fb4d..3e4257e2 100644 --- a/include/avr/iotn426.h +++ b/include/avr/iotn426.h @@ -1,4 +1,3 @@ - /* This file is part of avr-libc. Automatically created by devtools/gen-ioheader-atdf-avr8x.py @@ -5333,5 +5332,3 @@ IO Module Instances. Mapped to memory. #endif /* #ifdef _AVR_ATTINY426_H_INCLUDED */ - - diff --git a/include/avr/iotn427.h b/include/avr/iotn427.h index e7ff12fc..aa020e93 100644 --- a/include/avr/iotn427.h +++ b/include/avr/iotn427.h @@ -1,4 +1,3 @@ - /* This file is part of avr-libc. Automatically created by devtools/gen-ioheader-atdf-avr8x.py @@ -5356,5 +5355,3 @@ IO Module Instances. Mapped to memory. #endif /* #ifdef _AVR_ATTINY427_H_INCLUDED */ - - diff --git a/include/avr/iotn4313.h b/include/avr/iotn4313.h index 5f2d6187..31f0f548 100644 --- a/include/avr/iotn4313.h +++ b/include/avr/iotn4313.h @@ -42,7 +42,7 @@ # define _AVR_IOXXX_H_ "iotn4313.h" #else # error "Attempt to include more than one file." -#endif +#endif #ifndef _AVR_ATtiny4313_H_ @@ -810,4 +810,3 @@ #define SLEEP_MODE_PWR_DOWN (0x05<<4) #endif /* _AVR_ATtiny4313_H_ */ - diff --git a/include/avr/iotn43u.h b/include/avr/iotn43u.h index 88a08487..098acb5f 100644 --- a/include/avr/iotn43u.h +++ b/include/avr/iotn43u.h @@ -26,7 +26,7 @@ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. + POSSIBILITY OF SUCH DAMAGE. */ /* $Id$ */ @@ -43,7 +43,7 @@ # define _AVR_IOXXX_H_ "iotn43u.h" #else # error "Attempt to include more than one file." -#endif +#endif #ifndef _AVR_IOTN43U_H_ @@ -580,7 +580,7 @@ #define FUSE_SPIEN (unsigned char)~_BV(5) #define FUSE_DWEN (unsigned char)~_BV(6) #define FUSE_RSTDISBL (unsigned char)~_BV(7) -#define HFUSE_DEFAULT (FUSE_SPIEN) +#define HFUSE_DEFAULT (FUSE_SPIEN) /* Extended Fuse Byte */ #define FUSE_SELFPRGEN (unsigned char)~_BV(0) diff --git a/include/avr/iotn441.h b/include/avr/iotn441.h index 07693546..4cf05fe3 100644 --- a/include/avr/iotn441.h +++ b/include/avr/iotn441.h @@ -1,915 +1,914 @@ -/***************************************************************************** - * - * Copyright (C) 2016 Atmel Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * * Neither the name of the copyright holders nor the names of - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************/ - - -#ifndef _AVR_ATTINY441_H_INCLUDED -#define _AVR_ATTINY441_H_INCLUDED - - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iotn441.h" -#else -# error "Attempt to include more than one file." -#endif - -/* Registers and associated bit numbers */ - -#define ADCSRB _SFR_IO8(0x04) -#define ADTS0 0 -#define ADTS1 1 -#define ADTS2 2 -#define ADLAR 3 - -#define ADCSRA _SFR_IO8(0x05) -#define ADPS0 0 -#define ADPS1 1 -#define ADPS2 2 -#define ADIE 3 -#define ADIF 4 -#define ADATE 5 -#define ADSC 6 -#define ADEN 7 - -/* Combine ADCL and ADCH */ -#ifndef __ASSEMBLER__ -#define ADC _SFR_IO16(0x06) -#endif -#define ADCW _SFR_IO16(0x06) - -#define ADCL _SFR_IO8(0x06) -#define ADCH _SFR_IO8(0x07) - -#define ADMUXB _SFR_IO8(0x08) -#define GSEL0 0 -#define GSEL1 1 -#define REFS0 5 -#define REFS1 6 -#define REFS2 7 - -#define ADMUXA _SFR_IO8(0x09) -#define MUX0 0 -#define MUX1 1 -#define MUX2 2 -#define MUX3 3 -#define MUX4 4 -#define MUX5 5 - -#define ACSR0A _SFR_IO8(0x0A) -#define ACIS00 0 -#define ACIS01 1 -#define ACIC0 2 -#define ACIE0 3 -#define ACI0 4 -#define ACO0 5 -#define ACPMUX2 6 -#define ACD0 7 - -#define ACSR0B _SFR_IO8(0x0B) -#define ACPMUX0 0 -#define ACPMUX1 1 -#define ACNMUX0 2 -#define ACNMUX1 3 -#define ACOE0 4 -#define HLEV0 6 -#define HSEL0 7 - -#define ACSR1A _SFR_IO8(0x0C) -#define ACIS10 0 -#define ACIS11 1 -#define ACIC1 2 -#define ACIE1 3 -#define ACI1 4 -#define ACO1 5 -#define ACBG1 6 -#define ACD1 7 - -#define ACSR1B _SFR_IO8(0x0D) -#define ACME1 2 -#define ACOE1 4 -#define HLEV1 6 -#define HSEL1 7 - -#define TIFR1 _SFR_IO8(0x0E) -#define TOV1 0 -#define OCF1A 1 -#define OCF1B 2 -#define ICF1 5 - -#define TIMSK1 _SFR_IO8(0x0F) -#define TOIE1 0 -#define OCIE1A 1 -#define OCIE1B 2 -#define ICIE1 5 - -#define TIFR2 _SFR_IO8(0x10) -#define TOV2 0 -#define OCF2A 1 -#define OCF2B 2 -#define ICF2 5 - -#define TIMSK2 _SFR_IO8(0x11) -#define TOIE2 0 -#define OCIE2A 1 -#define OCIE2B 2 -#define ICIE2 5 - -#define PCMSK0 _SFR_IO8(0x12) -#define PCINT0 0 -#define PCINT1 1 -#define PCINT2 2 -#define PCINT3 3 -#define PCINT4 4 -#define PCINT5 5 -#define PCINT6 6 -#define PCINT7 7 - -#define GPIOR0 _SFR_IO8(0x13) - -#define GPIOR1 _SFR_IO8(0x14) - -#define GPIOR2 _SFR_IO8(0x15) - -#define PINB _SFR_IO8(0x16) -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -#define DDRB _SFR_IO8(0x17) -#define DDRB3 3 -// Inserted "DDB3" from "DDRB3" due to compatibility -#define DDB3 3 -#define DDRB2 2 -// Inserted "DDB2" from "DDRB2" due to compatibility -#define DDB2 2 -#define DDRB1 1 -// Inserted "DDB1" from "DDRB1" due to compatibility -#define DDB1 1 -#define DDRB0 0 -// Inserted "DDB0" from "DDRB0" due to compatibility -#define DDB0 0 - -#define PORTB _SFR_IO8(0x18) -#define PORTB3 3 -#define PORTB2 2 -#define PORTB1 1 -#define PORTB0 0 - -#define PINA _SFR_IO8(0x19) -#define PINA7 7 -#define PINA6 6 -#define PINA5 5 -#define PINA4 4 -#define PINA3 3 -#define PINA2 2 -#define PINA1 1 -#define PINA0 0 - -#define DDRA _SFR_IO8(0x1A) -#define DDRA7 7 -// Inserted "DDA7" from "DDRA7" due to compatibility -#define DDA7 7 -#define DDRA6 6 -// Inserted "DDA6" from "DDRA6" due to compatibility -#define DDA6 6 -#define DDRA5 5 -// Inserted "DDA5" from "DDRA5" due to compatibility -#define DDA5 5 -#define DDRA4 4 -// Inserted "DDA4" from "DDRA4" due to compatibility -#define DDA4 4 -#define DDRA3 3 -// Inserted "DDA3" from "DDRA3" due to compatibility -#define DDA3 3 -#define DDRA2 2 -// Inserted "DDA2" from "DDRA2" due to compatibility -#define DDA2 2 -#define DDRA1 1 -// Inserted "DDA1" from "DDRA1" due to compatibility -#define DDA1 1 -#define DDRA0 0 -// Inserted "DDA0" from "DDRA0" due to compatibility -#define DDA0 0 - -#define PORTA _SFR_IO8(0x1B) -#define PORTA7 7 -#define PORTA6 6 -#define PORTA5 5 -#define PORTA4 4 -#define PORTA3 3 -#define PORTA2 2 -#define PORTA1 1 -#define PORTA0 0 - -#define EECR _SFR_IO8(0x1C) -#define EERE 0 -#define EEPE 1 -#define EEMPE 2 -#define EERIE 3 -#define EEPM0 4 -#define EEPM1 5 - -#define EEDR _SFR_IO8(0x1D) - -/* Combine EEARL and EEARH */ -#define EEAR _SFR_IO16(0x1E) - -#define EEARL _SFR_IO8(0x1E) -#define EEARH _SFR_IO8(0x1F) - -#define PCMSK1 _SFR_IO8(0x20) -#define PCINT8 0 -#define PCINT9 1 -#define PCINT10 2 -#define PCINT11 3 - -#define WDTCSR _SFR_IO8(0x21) -#define WDE 3 -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDP3 5 -#define WDIE 6 -#define WDIF 7 - -#define TCCR1C _SFR_IO8(0x22) -#define FOC1B 6 -#define FOC1A 7 - -#define GTCCR _SFR_IO8(0x23) -#define PSR 0 -#define TSM 7 - -/* Combine ICR1L and ICR1H */ -#define ICR1 _SFR_IO16(0x24) - -#define ICR1L _SFR_IO8(0x24) -#define ICR1H _SFR_IO8(0x25) - -/* Reserved [0x26..0x27] */ - -/* Combine OCR1BL and OCR1BH */ -#define OCR1B _SFR_IO16(0x28) - -#define OCR1BL _SFR_IO8(0x28) -#define OCR1BH _SFR_IO8(0x29) - -/* Combine OCR1AL and OCR1AH */ -#define OCR1A _SFR_IO16(0x2A) - -#define OCR1AL _SFR_IO8(0x2A) -#define OCR1AH _SFR_IO8(0x2B) - -/* Combine TCNT1L and TCNT1H */ -#define TCNT1 _SFR_IO16(0x2C) - -#define TCNT1L _SFR_IO8(0x2C) -#define TCNT1H _SFR_IO8(0x2D) - -#define TCCR1B _SFR_IO8(0x2E) -#define CS10 0 -#define CS11 1 -#define CS12 2 -#define WGM12 3 -#define WGM13 4 -#define ICES1 6 -#define ICNC1 7 - -#define TCCR1A _SFR_IO8(0x2F) -#define WGM10 0 -#define WGM11 1 -#define COM1B0 4 -#define COM1B1 5 -#define COM1A0 6 -#define COM1A1 7 - -#define TCCR0A _SFR_IO8(0x30) -#define WGM00 0 -#define WGM01 1 -#define COM0B0 4 -#define COM0B1 5 -#define COM0A0 6 -#define COM0A1 7 - -/* Reserved [0x31] */ - -#define TCNT0 _SFR_IO8(0x32) - -#define TCCR0B _SFR_IO8(0x33) -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define WGM02 3 -#define FOC0B 6 -#define FOC0A 7 - -#define MCUSR _SFR_IO8(0x34) -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 - -#define MCUCR _SFR_IO8(0x35) -#define ISC00 0 -#define ISC01 1 -#define SM0 3 -#define SM1 4 -#define SE 5 - -#define OCR0A _SFR_IO8(0x36) - -#define SPMCSR _SFR_IO8(0x37) -#define SPMEN 0 -#define PGERS 1 -#define PGWRT 2 -#define RFLB 3 -#define CTPB 4 -#define RSIG 5 - -#define TIFR0 _SFR_IO8(0x38) -#define TOV0 0 -#define OCF0A 1 -#define OCF0B 2 - -#define TIMSK0 _SFR_IO8(0x39) -#define TOIE0 0 -#define OCIE0A 1 -#define OCIE0B 2 - -#define GIFR _SFR_IO8(0x3A) -#define PCIF0 4 -#define PCIF1 5 -#define INTF0 6 - -#define GIMSK _SFR_IO8(0x3B) -#define PCIE0 4 -#define PCIE1 5 -#define INT0 6 - -#define OCR0B _SFR_IO8(0x3C) - -/* SP [0x3D..0x3E] */ - -/* SREG [0x3F] */ - -#define DIDR0 _SFR_MEM8(0x60) -#define ADC0D 0 -#define ADC1D 1 -#define ADC2D 2 -#define ADC3D 3 -#define ADC4D 4 -#define ADC5D 5 -#define ADC6D 6 -#define ADC7D 7 - -#define DIDR1 _SFR_MEM8(0x61) -#define ADC11D 0 -#define ADC10D 1 -#define ADC8D 2 -#define ADC9D 3 - -#define PUEB _SFR_MEM8(0x62) -#define PUEB3 3 -#define PUEB2 2 -#define PUEB1 1 -#define PUEB0 0 - -#define PUEA _SFR_MEM8(0x63) -#define PUEA7 7 -#define PUEA6 6 -#define PUEA5 5 -#define PUEA4 4 -#define PUEA3 3 -#define PUEA2 2 -#define PUEA1 1 -#define PUEA0 0 - -#define PORTCR _SFR_MEM8(0x64) -#define BBMB 1 -#define BBMA 0 - -#define REMAP _SFR_MEM8(0x65) -#define U0MAP 0 -#define SPIMAP 1 - -#define TOCPMCOE _SFR_MEM8(0x66) -#define TOCC0OE 0 -#define TOCC1OE 1 -#define TOCC2OE 2 -#define TOCC3OE 3 -#define TOCC4OE 4 -#define TOCC5OE 5 -#define TOCC6OE 6 -#define TOCC7OE 7 - -#define TOCPMSA0 _SFR_MEM8(0x67) -#define TOCC0S0 0 -#define TOCC0S1 1 -#define TOCC1S0 2 -#define TOCC1S1 3 -#define TOCC2S0 4 -#define TOCC2S1 5 -#define TOCC3S0 6 -#define TOCC3S1 7 - -#define TOCPMSA1 _SFR_MEM8(0x68) -#define TOCC4S0 0 -#define TOCC4S1 1 -#define TOCC5S0 2 -#define TOCC5S1 3 -#define TOCC6S0 4 -#define TOCC6S1 5 -#define TOCC7S0 6 -#define TOCC7S1 7 - -/* Reserved [0x69] */ - -#define PHDE _SFR_MEM8(0x6A) -#define PHDEA0 0 -#define PHDEA1 1 - -/* Reserved [0x6B..0x6F] */ - -#define PRR _SFR_MEM8(0x70) -#define PRADC 0 -#define PRTIM0 1 -#define PRTIM1 2 -#define PRTIM2 3 -#define PRSPI 4 -#define PRUSART0 5 -#define PRUSART1 6 -#define PRTWI 7 - -#define __AVR_HAVE_PRR ((1< instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iotn441.h" +#else +# error "Attempt to include more than one file." +#endif + +/* Registers and associated bit numbers */ + +#define ADCSRB _SFR_IO8(0x04) +#define ADTS0 0 +#define ADTS1 1 +#define ADTS2 2 +#define ADLAR 3 + +#define ADCSRA _SFR_IO8(0x05) +#define ADPS0 0 +#define ADPS1 1 +#define ADPS2 2 +#define ADIE 3 +#define ADIF 4 +#define ADATE 5 +#define ADSC 6 +#define ADEN 7 + +/* Combine ADCL and ADCH */ +#ifndef __ASSEMBLER__ +#define ADC _SFR_IO16(0x06) +#endif +#define ADCW _SFR_IO16(0x06) + +#define ADCL _SFR_IO8(0x06) +#define ADCH _SFR_IO8(0x07) + +#define ADMUXB _SFR_IO8(0x08) +#define GSEL0 0 +#define GSEL1 1 +#define REFS0 5 +#define REFS1 6 +#define REFS2 7 + +#define ADMUXA _SFR_IO8(0x09) +#define MUX0 0 +#define MUX1 1 +#define MUX2 2 +#define MUX3 3 +#define MUX4 4 +#define MUX5 5 + +#define ACSR0A _SFR_IO8(0x0A) +#define ACIS00 0 +#define ACIS01 1 +#define ACIC0 2 +#define ACIE0 3 +#define ACI0 4 +#define ACO0 5 +#define ACPMUX2 6 +#define ACD0 7 + +#define ACSR0B _SFR_IO8(0x0B) +#define ACPMUX0 0 +#define ACPMUX1 1 +#define ACNMUX0 2 +#define ACNMUX1 3 +#define ACOE0 4 +#define HLEV0 6 +#define HSEL0 7 + +#define ACSR1A _SFR_IO8(0x0C) +#define ACIS10 0 +#define ACIS11 1 +#define ACIC1 2 +#define ACIE1 3 +#define ACI1 4 +#define ACO1 5 +#define ACBG1 6 +#define ACD1 7 + +#define ACSR1B _SFR_IO8(0x0D) +#define ACME1 2 +#define ACOE1 4 +#define HLEV1 6 +#define HSEL1 7 + +#define TIFR1 _SFR_IO8(0x0E) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define ICF1 5 + +#define TIMSK1 _SFR_IO8(0x0F) +#define TOIE1 0 +#define OCIE1A 1 +#define OCIE1B 2 +#define ICIE1 5 + +#define TIFR2 _SFR_IO8(0x10) +#define TOV2 0 +#define OCF2A 1 +#define OCF2B 2 +#define ICF2 5 + +#define TIMSK2 _SFR_IO8(0x11) +#define TOIE2 0 +#define OCIE2A 1 +#define OCIE2B 2 +#define ICIE2 5 + +#define PCMSK0 _SFR_IO8(0x12) +#define PCINT0 0 +#define PCINT1 1 +#define PCINT2 2 +#define PCINT3 3 +#define PCINT4 4 +#define PCINT5 5 +#define PCINT6 6 +#define PCINT7 7 + +#define GPIOR0 _SFR_IO8(0x13) + +#define GPIOR1 _SFR_IO8(0x14) + +#define GPIOR2 _SFR_IO8(0x15) + +#define PINB _SFR_IO8(0x16) +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +#define DDRB _SFR_IO8(0x17) +#define DDRB3 3 +// Inserted "DDB3" from "DDRB3" due to compatibility +#define DDB3 3 +#define DDRB2 2 +// Inserted "DDB2" from "DDRB2" due to compatibility +#define DDB2 2 +#define DDRB1 1 +// Inserted "DDB1" from "DDRB1" due to compatibility +#define DDB1 1 +#define DDRB0 0 +// Inserted "DDB0" from "DDRB0" due to compatibility +#define DDB0 0 + +#define PORTB _SFR_IO8(0x18) +#define PORTB3 3 +#define PORTB2 2 +#define PORTB1 1 +#define PORTB0 0 + +#define PINA _SFR_IO8(0x19) +#define PINA7 7 +#define PINA6 6 +#define PINA5 5 +#define PINA4 4 +#define PINA3 3 +#define PINA2 2 +#define PINA1 1 +#define PINA0 0 + +#define DDRA _SFR_IO8(0x1A) +#define DDRA7 7 +// Inserted "DDA7" from "DDRA7" due to compatibility +#define DDA7 7 +#define DDRA6 6 +// Inserted "DDA6" from "DDRA6" due to compatibility +#define DDA6 6 +#define DDRA5 5 +// Inserted "DDA5" from "DDRA5" due to compatibility +#define DDA5 5 +#define DDRA4 4 +// Inserted "DDA4" from "DDRA4" due to compatibility +#define DDA4 4 +#define DDRA3 3 +// Inserted "DDA3" from "DDRA3" due to compatibility +#define DDA3 3 +#define DDRA2 2 +// Inserted "DDA2" from "DDRA2" due to compatibility +#define DDA2 2 +#define DDRA1 1 +// Inserted "DDA1" from "DDRA1" due to compatibility +#define DDA1 1 +#define DDRA0 0 +// Inserted "DDA0" from "DDRA0" due to compatibility +#define DDA0 0 + +#define PORTA _SFR_IO8(0x1B) +#define PORTA7 7 +#define PORTA6 6 +#define PORTA5 5 +#define PORTA4 4 +#define PORTA3 3 +#define PORTA2 2 +#define PORTA1 1 +#define PORTA0 0 + +#define EECR _SFR_IO8(0x1C) +#define EERE 0 +#define EEPE 1 +#define EEMPE 2 +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 + +#define EEDR _SFR_IO8(0x1D) + +/* Combine EEARL and EEARH */ +#define EEAR _SFR_IO16(0x1E) + +#define EEARL _SFR_IO8(0x1E) +#define EEARH _SFR_IO8(0x1F) + +#define PCMSK1 _SFR_IO8(0x20) +#define PCINT8 0 +#define PCINT9 1 +#define PCINT10 2 +#define PCINT11 3 + +#define WDTCSR _SFR_IO8(0x21) +#define WDE 3 +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDP3 5 +#define WDIE 6 +#define WDIF 7 + +#define TCCR1C _SFR_IO8(0x22) +#define FOC1B 6 +#define FOC1A 7 + +#define GTCCR _SFR_IO8(0x23) +#define PSR 0 +#define TSM 7 + +/* Combine ICR1L and ICR1H */ +#define ICR1 _SFR_IO16(0x24) + +#define ICR1L _SFR_IO8(0x24) +#define ICR1H _SFR_IO8(0x25) + +/* Reserved [0x26..0x27] */ + +/* Combine OCR1BL and OCR1BH */ +#define OCR1B _SFR_IO16(0x28) + +#define OCR1BL _SFR_IO8(0x28) +#define OCR1BH _SFR_IO8(0x29) + +/* Combine OCR1AL and OCR1AH */ +#define OCR1A _SFR_IO16(0x2A) + +#define OCR1AL _SFR_IO8(0x2A) +#define OCR1AH _SFR_IO8(0x2B) + +/* Combine TCNT1L and TCNT1H */ +#define TCNT1 _SFR_IO16(0x2C) + +#define TCNT1L _SFR_IO8(0x2C) +#define TCNT1H _SFR_IO8(0x2D) + +#define TCCR1B _SFR_IO8(0x2E) +#define CS10 0 +#define CS11 1 +#define CS12 2 +#define WGM12 3 +#define WGM13 4 +#define ICES1 6 +#define ICNC1 7 + +#define TCCR1A _SFR_IO8(0x2F) +#define WGM10 0 +#define WGM11 1 +#define COM1B0 4 +#define COM1B1 5 +#define COM1A0 6 +#define COM1A1 7 + +#define TCCR0A _SFR_IO8(0x30) +#define WGM00 0 +#define WGM01 1 +#define COM0B0 4 +#define COM0B1 5 +#define COM0A0 6 +#define COM0A1 7 + +/* Reserved [0x31] */ + +#define TCNT0 _SFR_IO8(0x32) + +#define TCCR0B _SFR_IO8(0x33) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define WGM02 3 +#define FOC0B 6 +#define FOC0A 7 + +#define MCUSR _SFR_IO8(0x34) +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 + +#define MCUCR _SFR_IO8(0x35) +#define ISC00 0 +#define ISC01 1 +#define SM0 3 +#define SM1 4 +#define SE 5 + +#define OCR0A _SFR_IO8(0x36) + +#define SPMCSR _SFR_IO8(0x37) +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define RFLB 3 +#define CTPB 4 +#define RSIG 5 + +#define TIFR0 _SFR_IO8(0x38) +#define TOV0 0 +#define OCF0A 1 +#define OCF0B 2 + +#define TIMSK0 _SFR_IO8(0x39) +#define TOIE0 0 +#define OCIE0A 1 +#define OCIE0B 2 + +#define GIFR _SFR_IO8(0x3A) +#define PCIF0 4 +#define PCIF1 5 +#define INTF0 6 + +#define GIMSK _SFR_IO8(0x3B) +#define PCIE0 4 +#define PCIE1 5 +#define INT0 6 + +#define OCR0B _SFR_IO8(0x3C) + +/* SP [0x3D..0x3E] */ + +/* SREG [0x3F] */ + +#define DIDR0 _SFR_MEM8(0x60) +#define ADC0D 0 +#define ADC1D 1 +#define ADC2D 2 +#define ADC3D 3 +#define ADC4D 4 +#define ADC5D 5 +#define ADC6D 6 +#define ADC7D 7 + +#define DIDR1 _SFR_MEM8(0x61) +#define ADC11D 0 +#define ADC10D 1 +#define ADC8D 2 +#define ADC9D 3 + +#define PUEB _SFR_MEM8(0x62) +#define PUEB3 3 +#define PUEB2 2 +#define PUEB1 1 +#define PUEB0 0 + +#define PUEA _SFR_MEM8(0x63) +#define PUEA7 7 +#define PUEA6 6 +#define PUEA5 5 +#define PUEA4 4 +#define PUEA3 3 +#define PUEA2 2 +#define PUEA1 1 +#define PUEA0 0 + +#define PORTCR _SFR_MEM8(0x64) +#define BBMB 1 +#define BBMA 0 + +#define REMAP _SFR_MEM8(0x65) +#define U0MAP 0 +#define SPIMAP 1 + +#define TOCPMCOE _SFR_MEM8(0x66) +#define TOCC0OE 0 +#define TOCC1OE 1 +#define TOCC2OE 2 +#define TOCC3OE 3 +#define TOCC4OE 4 +#define TOCC5OE 5 +#define TOCC6OE 6 +#define TOCC7OE 7 + +#define TOCPMSA0 _SFR_MEM8(0x67) +#define TOCC0S0 0 +#define TOCC0S1 1 +#define TOCC1S0 2 +#define TOCC1S1 3 +#define TOCC2S0 4 +#define TOCC2S1 5 +#define TOCC3S0 6 +#define TOCC3S1 7 + +#define TOCPMSA1 _SFR_MEM8(0x68) +#define TOCC4S0 0 +#define TOCC4S1 1 +#define TOCC5S0 2 +#define TOCC5S1 3 +#define TOCC6S0 4 +#define TOCC6S1 5 +#define TOCC7S0 6 +#define TOCC7S1 7 + +/* Reserved [0x69] */ + +#define PHDE _SFR_MEM8(0x6A) +#define PHDEA0 0 +#define PHDEA1 1 + +/* Reserved [0x6B..0x6F] */ + +#define PRR _SFR_MEM8(0x70) +#define PRADC 0 +#define PRTIM0 1 +#define PRTIM1 2 +#define PRTIM2 3 +#define PRSPI 4 +#define PRUSART0 5 +#define PRUSART1 6 +#define PRTWI 7 + +#define __AVR_HAVE_PRR ((1< file." -#endif +#endif #ifndef _AVR_ATtiny44A_H_ @@ -842,4 +842,3 @@ #define SLEEP_MODE_STANDBY (0x03<<3) #endif /* _AVR_ATtiny44A_H_ */ - diff --git a/include/avr/iotn461a.h b/include/avr/iotn461a.h index 810ab0b7..535aafa5 100644 --- a/include/avr/iotn461a.h +++ b/include/avr/iotn461a.h @@ -42,7 +42,7 @@ # define _AVR_IOXXX_H_ "iotn461a.h" #else # error "Attempt to include more than one file." -#endif +#endif #ifndef _AVR_ATtiny461A_H_ @@ -985,4 +985,3 @@ #define SLEEP_MODE_STANDBY (0x03<<3) #endif /* _AVR_ATtiny461A_H_ */ - diff --git a/include/avr/iotn48.h b/include/avr/iotn48.h index b6a730e5..0f66aa70 100644 --- a/include/avr/iotn48.h +++ b/include/avr/iotn48.h @@ -26,7 +26,7 @@ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. + POSSIBILITY OF SUCH DAMAGE. */ /* $Id$ */ @@ -43,7 +43,7 @@ # define _AVR_IOXXX_H_ "iotn48.h" #else # error "Attempt to include more than one file." -#endif +#endif #ifndef _AVR_IOTN48_H_ @@ -782,7 +782,7 @@ #define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ #define FUSE_DWEN (unsigned char)~_BV(6) /* debugWIRE Enable */ #define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External reset disable */ -#define HFUSE_DEFAULT (FUSE_SPIEN) +#define HFUSE_DEFAULT (FUSE_SPIEN) /* Extended Fuse Byte */ #define FUSE_SELFPRGEN (unsigned char)~_BV(0) /* Self Programming Enable */ diff --git a/include/avr/iotn5.h b/include/avr/iotn5.h index 8787b6e4..87098d42 100644 --- a/include/avr/iotn5.h +++ b/include/avr/iotn5.h @@ -42,7 +42,7 @@ # define _AVR_IOXXX_H_ "iotn5.h" #else # error "Attempt to include more than one file." -#endif +#endif #ifndef _AVR_ATtiny5_H_ @@ -510,4 +510,3 @@ #define SLEEP_MODE_STANDBY (0x04<<1) #endif /* _AVR_ATtiny5_H_ */ - diff --git a/include/avr/iotn804.h b/include/avr/iotn804.h index 0be35639..9a2fd363 100644 --- a/include/avr/iotn804.h +++ b/include/avr/iotn804.h @@ -1,4 +1,3 @@ - /* This file is part of avr-libc. Automatically created by devtools/gen-ioheader-atdf-avr8x.py @@ -4793,5 +4792,3 @@ IO Module Instances. Mapped to memory. #endif /* #ifdef _AVR_ATTINY804_H_INCLUDED */ - - diff --git a/include/avr/iotn806.h b/include/avr/iotn806.h index d6721ef6..b06791fb 100644 --- a/include/avr/iotn806.h +++ b/include/avr/iotn806.h @@ -1,4 +1,3 @@ - /* This file is part of avr-libc. Automatically created by devtools/gen-ioheader-atdf-avr8x.py @@ -4793,5 +4792,3 @@ IO Module Instances. Mapped to memory. #endif /* #ifdef _AVR_ATTINY806_H_INCLUDED */ - - diff --git a/include/avr/iotn807.h b/include/avr/iotn807.h index cc933634..03133c6c 100644 --- a/include/avr/iotn807.h +++ b/include/avr/iotn807.h @@ -1,4 +1,3 @@ - /* This file is part of avr-libc. Automatically created by devtools/gen-ioheader-atdf-avr8x.py @@ -4793,5 +4792,3 @@ IO Module Instances. Mapped to memory. #endif /* #ifdef _AVR_ATTINY807_H_INCLUDED */ - - diff --git a/include/avr/iotn814.h b/include/avr/iotn814.h index b71c6617..d1a66acd 100644 --- a/include/avr/iotn814.h +++ b/include/avr/iotn814.h @@ -1,4 +1,3 @@ - /* This file is part of avr-libc. Automatically created by devtools/gen-ioheader-atdf-avr8x.py @@ -5367,5 +5366,3 @@ IO Module Instances. Mapped to memory. #endif /* #ifdef _AVR_ATTINY814_H_INCLUDED */ - - diff --git a/include/avr/iotn816.h b/include/avr/iotn816.h index 6b91b800..2a56c9d3 100644 --- a/include/avr/iotn816.h +++ b/include/avr/iotn816.h @@ -1,4 +1,3 @@ - /* This file is part of avr-libc. Automatically created by devtools/gen-ioheader-atdf-avr8x.py @@ -5393,5 +5392,3 @@ IO Module Instances. Mapped to memory. #endif /* #ifdef _AVR_ATTINY816_H_INCLUDED */ - - diff --git a/include/avr/iotn817.h b/include/avr/iotn817.h index e88d32a4..5108fea0 100644 --- a/include/avr/iotn817.h +++ b/include/avr/iotn817.h @@ -1,4 +1,3 @@ - /* This file is part of avr-libc. Automatically created by devtools/gen-ioheader-atdf-avr8x.py @@ -5393,5 +5392,3 @@ IO Module Instances. Mapped to memory. #endif /* #ifdef _AVR_ATTINY817_H_INCLUDED */ - - diff --git a/include/avr/iotn824.h b/include/avr/iotn824.h index 3a9f0e98..d004a4ef 100644 --- a/include/avr/iotn824.h +++ b/include/avr/iotn824.h @@ -1,4 +1,3 @@ - /* This file is part of avr-libc. Automatically created by devtools/gen-ioheader-atdf-avr8x.py @@ -5289,5 +5288,3 @@ IO Module Instances. Mapped to memory. #endif /* #ifdef _AVR_ATTINY824_H_INCLUDED */ - - diff --git a/include/avr/iotn826.h b/include/avr/iotn826.h index 39432b19..b0f032b7 100644 --- a/include/avr/iotn826.h +++ b/include/avr/iotn826.h @@ -1,4 +1,3 @@ - /* This file is part of avr-libc. Automatically created by devtools/gen-ioheader-atdf-avr8x.py @@ -5333,5 +5332,3 @@ IO Module Instances. Mapped to memory. #endif /* #ifdef _AVR_ATTINY826_H_INCLUDED */ - - diff --git a/include/avr/iotn827.h b/include/avr/iotn827.h index f379cba4..0be550cf 100644 --- a/include/avr/iotn827.h +++ b/include/avr/iotn827.h @@ -1,4 +1,3 @@ - /* This file is part of avr-libc. Automatically created by devtools/gen-ioheader-atdf-avr8x.py @@ -5356,5 +5355,3 @@ IO Module Instances. Mapped to memory. #endif /* #ifdef _AVR_ATTINY827_H_INCLUDED */ - - diff --git a/include/avr/iotn828.h b/include/avr/iotn828.h index 016a2c52..1ff1ef64 100644 --- a/include/avr/iotn828.h +++ b/include/avr/iotn828.h @@ -844,4 +844,3 @@ #define SLEEP_MODE_PWR_DOWN (0x02<<1) #endif /* #ifdef _AVR_ATTINY828_H_INCLUDED */ - diff --git a/include/avr/iotn841.h b/include/avr/iotn841.h index d6a4fb18..15984af4 100644 --- a/include/avr/iotn841.h +++ b/include/avr/iotn841.h @@ -1,915 +1,914 @@ -/***************************************************************************** - * - * Copyright (C) 2016 Atmel Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * * Neither the name of the copyright holders nor the names of - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************/ - - -#ifndef _AVR_ATTINY841_H_INCLUDED -#define _AVR_ATTINY841_H_INCLUDED - - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iotn841.h" -#else -# error "Attempt to include more than one file." -#endif - -/* Registers and associated bit numbers */ - -#define ADCSRB _SFR_IO8(0x04) -#define ADTS0 0 -#define ADTS1 1 -#define ADTS2 2 -#define ADLAR 3 - -#define ADCSRA _SFR_IO8(0x05) -#define ADPS0 0 -#define ADPS1 1 -#define ADPS2 2 -#define ADIE 3 -#define ADIF 4 -#define ADATE 5 -#define ADSC 6 -#define ADEN 7 - -/* Combine ADCL and ADCH */ -#ifndef __ASSEMBLER__ -#define ADC _SFR_IO16(0x06) -#endif -#define ADCW _SFR_IO16(0x06) - -#define ADCL _SFR_IO8(0x06) -#define ADCH _SFR_IO8(0x07) - -#define ADMUXB _SFR_IO8(0x08) -#define GSEL0 0 -#define GSEL1 1 -#define REFS0 5 -#define REFS1 6 -#define REFS2 7 - -#define ADMUXA _SFR_IO8(0x09) -#define MUX0 0 -#define MUX1 1 -#define MUX2 2 -#define MUX3 3 -#define MUX4 4 -#define MUX5 5 - -#define ACSR0A _SFR_IO8(0x0A) -#define ACIS00 0 -#define ACIS01 1 -#define ACIC0 2 -#define ACIE0 3 -#define ACI0 4 -#define ACO0 5 -#define ACPMUX2 6 -#define ACD0 7 - -#define ACSR0B _SFR_IO8(0x0B) -#define ACPMUX0 0 -#define ACPMUX1 1 -#define ACNMUX0 2 -#define ACNMUX1 3 -#define ACOE0 4 -#define HLEV0 6 -#define HSEL0 7 - -#define ACSR1A _SFR_IO8(0x0C) -#define ACIS10 0 -#define ACIS11 1 -#define ACIC1 2 -#define ACIE1 3 -#define ACI1 4 -#define ACO1 5 -#define ACBG1 6 -#define ACD1 7 - -#define ACSR1B _SFR_IO8(0x0D) -#define ACME1 2 -#define ACOE1 4 -#define HLEV1 6 -#define HSEL1 7 - -#define TIFR1 _SFR_IO8(0x0E) -#define TOV1 0 -#define OCF1A 1 -#define OCF1B 2 -#define ICF1 5 - -#define TIMSK1 _SFR_IO8(0x0F) -#define TOIE1 0 -#define OCIE1A 1 -#define OCIE1B 2 -#define ICIE1 5 - -#define TIFR2 _SFR_IO8(0x10) -#define TOV2 0 -#define OCF2A 1 -#define OCF2B 2 -#define ICF2 5 - -#define TIMSK2 _SFR_IO8(0x11) -#define TOIE2 0 -#define OCIE2A 1 -#define OCIE2B 2 -#define ICIE2 5 - -#define PCMSK0 _SFR_IO8(0x12) -#define PCINT0 0 -#define PCINT1 1 -#define PCINT2 2 -#define PCINT3 3 -#define PCINT4 4 -#define PCINT5 5 -#define PCINT6 6 -#define PCINT7 7 - -#define GPIOR0 _SFR_IO8(0x13) - -#define GPIOR1 _SFR_IO8(0x14) - -#define GPIOR2 _SFR_IO8(0x15) - -#define PINB _SFR_IO8(0x16) -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -#define DDRB _SFR_IO8(0x17) -#define DDRB3 3 -// Inserted "DDB3" from "DDRB3" due to compatibility -#define DDB3 3 -#define DDRB2 2 -// Inserted "DDB2" from "DDRB2" due to compatibility -#define DDB2 2 -#define DDRB1 1 -// Inserted "DDB1" from "DDRB1" due to compatibility -#define DDB1 1 -#define DDRB0 0 -// Inserted "DDB0" from "DDRB0" due to compatibility -#define DDB0 0 - -#define PORTB _SFR_IO8(0x18) -#define PORTB3 3 -#define PORTB2 2 -#define PORTB1 1 -#define PORTB0 0 - -#define PINA _SFR_IO8(0x19) -#define PINA7 7 -#define PINA6 6 -#define PINA5 5 -#define PINA4 4 -#define PINA3 3 -#define PINA2 2 -#define PINA1 1 -#define PINA0 0 - -#define DDRA _SFR_IO8(0x1A) -#define DDRA7 7 -// Inserted "DDA7" from "DDRA7" due to compatibility -#define DDA7 7 -#define DDRA6 6 -// Inserted "DDA6" from "DDRA6" due to compatibility -#define DDA6 6 -#define DDRA5 5 -// Inserted "DDA5" from "DDRA5" due to compatibility -#define DDA5 5 -#define DDRA4 4 -// Inserted "DDA4" from "DDRA4" due to compatibility -#define DDA4 4 -#define DDRA3 3 -// Inserted "DDA3" from "DDRA3" due to compatibility -#define DDA3 3 -#define DDRA2 2 -// Inserted "DDA2" from "DDRA2" due to compatibility -#define DDA2 2 -#define DDRA1 1 -// Inserted "DDA1" from "DDRA1" due to compatibility -#define DDA1 1 -#define DDRA0 0 -// Inserted "DDA0" from "DDRA0" due to compatibility -#define DDA0 0 - -#define PORTA _SFR_IO8(0x1B) -#define PORTA7 7 -#define PORTA6 6 -#define PORTA5 5 -#define PORTA4 4 -#define PORTA3 3 -#define PORTA2 2 -#define PORTA1 1 -#define PORTA0 0 - -#define EECR _SFR_IO8(0x1C) -#define EERE 0 -#define EEPE 1 -#define EEMPE 2 -#define EERIE 3 -#define EEPM0 4 -#define EEPM1 5 - -#define EEDR _SFR_IO8(0x1D) - -/* Combine EEARL and EEARH */ -#define EEAR _SFR_IO16(0x1E) - -#define EEARL _SFR_IO8(0x1E) -#define EEARH _SFR_IO8(0x1F) - -#define PCMSK1 _SFR_IO8(0x20) -#define PCINT8 0 -#define PCINT9 1 -#define PCINT10 2 -#define PCINT11 3 - -#define WDTCSR _SFR_IO8(0x21) -#define WDE 3 -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDP3 5 -#define WDIE 6 -#define WDIF 7 - -#define TCCR1C _SFR_IO8(0x22) -#define FOC1B 6 -#define FOC1A 7 - -#define GTCCR _SFR_IO8(0x23) -#define PSR 0 -#define TSM 7 - -/* Combine ICR1L and ICR1H */ -#define ICR1 _SFR_IO16(0x24) - -#define ICR1L _SFR_IO8(0x24) -#define ICR1H _SFR_IO8(0x25) - -/* Reserved [0x26..0x27] */ - -/* Combine OCR1BL and OCR1BH */ -#define OCR1B _SFR_IO16(0x28) - -#define OCR1BL _SFR_IO8(0x28) -#define OCR1BH _SFR_IO8(0x29) - -/* Combine OCR1AL and OCR1AH */ -#define OCR1A _SFR_IO16(0x2A) - -#define OCR1AL _SFR_IO8(0x2A) -#define OCR1AH _SFR_IO8(0x2B) - -/* Combine TCNT1L and TCNT1H */ -#define TCNT1 _SFR_IO16(0x2C) - -#define TCNT1L _SFR_IO8(0x2C) -#define TCNT1H _SFR_IO8(0x2D) - -#define TCCR1B _SFR_IO8(0x2E) -#define CS10 0 -#define CS11 1 -#define CS12 2 -#define WGM12 3 -#define WGM13 4 -#define ICES1 6 -#define ICNC1 7 - -#define TCCR1A _SFR_IO8(0x2F) -#define WGM10 0 -#define WGM11 1 -#define COM1B0 4 -#define COM1B1 5 -#define COM1A0 6 -#define COM1A1 7 - -#define TCCR0A _SFR_IO8(0x30) -#define WGM00 0 -#define WGM01 1 -#define COM0B0 4 -#define COM0B1 5 -#define COM0A0 6 -#define COM0A1 7 - -/* Reserved [0x31] */ - -#define TCNT0 _SFR_IO8(0x32) - -#define TCCR0B _SFR_IO8(0x33) -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define WGM02 3 -#define FOC0B 6 -#define FOC0A 7 - -#define MCUSR _SFR_IO8(0x34) -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 - -#define MCUCR _SFR_IO8(0x35) -#define ISC00 0 -#define ISC01 1 -#define SM0 3 -#define SM1 4 -#define SE 5 - -#define OCR0A _SFR_IO8(0x36) - -#define SPMCSR _SFR_IO8(0x37) -#define SPMEN 0 -#define PGERS 1 -#define PGWRT 2 -#define RFLB 3 -#define CTPB 4 -#define RSIG 5 - -#define TIFR0 _SFR_IO8(0x38) -#define TOV0 0 -#define OCF0A 1 -#define OCF0B 2 - -#define TIMSK0 _SFR_IO8(0x39) -#define TOIE0 0 -#define OCIE0A 1 -#define OCIE0B 2 - -#define GIFR _SFR_IO8(0x3A) -#define PCIF0 4 -#define PCIF1 5 -#define INTF0 6 - -#define GIMSK _SFR_IO8(0x3B) -#define PCIE0 4 -#define PCIE1 5 -#define INT0 6 - -#define OCR0B _SFR_IO8(0x3C) - -/* SP [0x3D..0x3E] */ - -/* SREG [0x3F] */ - -#define DIDR0 _SFR_MEM8(0x60) -#define ADC0D 0 -#define ADC1D 1 -#define ADC2D 2 -#define ADC3D 3 -#define ADC4D 4 -#define ADC5D 5 -#define ADC6D 6 -#define ADC7D 7 - -#define DIDR1 _SFR_MEM8(0x61) -#define ADC11D 0 -#define ADC10D 1 -#define ADC8D 2 -#define ADC9D 3 - -#define PUEB _SFR_MEM8(0x62) -#define PUEB3 3 -#define PUEB2 2 -#define PUEB1 1 -#define PUEB0 0 - -#define PUEA _SFR_MEM8(0x63) -#define PUEA7 7 -#define PUEA6 6 -#define PUEA5 5 -#define PUEA4 4 -#define PUEA3 3 -#define PUEA2 2 -#define PUEA1 1 -#define PUEA0 0 - -#define PORTCR _SFR_MEM8(0x64) -#define BBMB 1 -#define BBMA 0 - -#define REMAP _SFR_MEM8(0x65) -#define U0MAP 0 -#define SPIMAP 1 - -#define TOCPMCOE _SFR_MEM8(0x66) -#define TOCC0OE 0 -#define TOCC1OE 1 -#define TOCC2OE 2 -#define TOCC3OE 3 -#define TOCC4OE 4 -#define TOCC5OE 5 -#define TOCC6OE 6 -#define TOCC7OE 7 - -#define TOCPMSA0 _SFR_MEM8(0x67) -#define TOCC0S0 0 -#define TOCC0S1 1 -#define TOCC1S0 2 -#define TOCC1S1 3 -#define TOCC2S0 4 -#define TOCC2S1 5 -#define TOCC3S0 6 -#define TOCC3S1 7 - -#define TOCPMSA1 _SFR_MEM8(0x68) -#define TOCC4S0 0 -#define TOCC4S1 1 -#define TOCC5S0 2 -#define TOCC5S1 3 -#define TOCC6S0 4 -#define TOCC6S1 5 -#define TOCC7S0 6 -#define TOCC7S1 7 - -/* Reserved [0x69] */ - -#define PHDE _SFR_MEM8(0x6A) -#define PHDEA0 0 -#define PHDEA1 1 - -/* Reserved [0x6B..0x6F] */ - -#define PRR _SFR_MEM8(0x70) -#define PRADC 0 -#define PRTIM0 1 -#define PRTIM1 2 -#define PRTIM2 3 -#define PRSPI 4 -#define PRUSART0 5 -#define PRUSART1 6 -#define PRTWI 7 - -#define __AVR_HAVE_PRR ((1< instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iotn841.h" +#else +# error "Attempt to include more than one file." +#endif + +/* Registers and associated bit numbers */ + +#define ADCSRB _SFR_IO8(0x04) +#define ADTS0 0 +#define ADTS1 1 +#define ADTS2 2 +#define ADLAR 3 + +#define ADCSRA _SFR_IO8(0x05) +#define ADPS0 0 +#define ADPS1 1 +#define ADPS2 2 +#define ADIE 3 +#define ADIF 4 +#define ADATE 5 +#define ADSC 6 +#define ADEN 7 + +/* Combine ADCL and ADCH */ +#ifndef __ASSEMBLER__ +#define ADC _SFR_IO16(0x06) +#endif +#define ADCW _SFR_IO16(0x06) + +#define ADCL _SFR_IO8(0x06) +#define ADCH _SFR_IO8(0x07) + +#define ADMUXB _SFR_IO8(0x08) +#define GSEL0 0 +#define GSEL1 1 +#define REFS0 5 +#define REFS1 6 +#define REFS2 7 + +#define ADMUXA _SFR_IO8(0x09) +#define MUX0 0 +#define MUX1 1 +#define MUX2 2 +#define MUX3 3 +#define MUX4 4 +#define MUX5 5 + +#define ACSR0A _SFR_IO8(0x0A) +#define ACIS00 0 +#define ACIS01 1 +#define ACIC0 2 +#define ACIE0 3 +#define ACI0 4 +#define ACO0 5 +#define ACPMUX2 6 +#define ACD0 7 + +#define ACSR0B _SFR_IO8(0x0B) +#define ACPMUX0 0 +#define ACPMUX1 1 +#define ACNMUX0 2 +#define ACNMUX1 3 +#define ACOE0 4 +#define HLEV0 6 +#define HSEL0 7 + +#define ACSR1A _SFR_IO8(0x0C) +#define ACIS10 0 +#define ACIS11 1 +#define ACIC1 2 +#define ACIE1 3 +#define ACI1 4 +#define ACO1 5 +#define ACBG1 6 +#define ACD1 7 + +#define ACSR1B _SFR_IO8(0x0D) +#define ACME1 2 +#define ACOE1 4 +#define HLEV1 6 +#define HSEL1 7 + +#define TIFR1 _SFR_IO8(0x0E) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define ICF1 5 + +#define TIMSK1 _SFR_IO8(0x0F) +#define TOIE1 0 +#define OCIE1A 1 +#define OCIE1B 2 +#define ICIE1 5 + +#define TIFR2 _SFR_IO8(0x10) +#define TOV2 0 +#define OCF2A 1 +#define OCF2B 2 +#define ICF2 5 + +#define TIMSK2 _SFR_IO8(0x11) +#define TOIE2 0 +#define OCIE2A 1 +#define OCIE2B 2 +#define ICIE2 5 + +#define PCMSK0 _SFR_IO8(0x12) +#define PCINT0 0 +#define PCINT1 1 +#define PCINT2 2 +#define PCINT3 3 +#define PCINT4 4 +#define PCINT5 5 +#define PCINT6 6 +#define PCINT7 7 + +#define GPIOR0 _SFR_IO8(0x13) + +#define GPIOR1 _SFR_IO8(0x14) + +#define GPIOR2 _SFR_IO8(0x15) + +#define PINB _SFR_IO8(0x16) +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +#define DDRB _SFR_IO8(0x17) +#define DDRB3 3 +// Inserted "DDB3" from "DDRB3" due to compatibility +#define DDB3 3 +#define DDRB2 2 +// Inserted "DDB2" from "DDRB2" due to compatibility +#define DDB2 2 +#define DDRB1 1 +// Inserted "DDB1" from "DDRB1" due to compatibility +#define DDB1 1 +#define DDRB0 0 +// Inserted "DDB0" from "DDRB0" due to compatibility +#define DDB0 0 + +#define PORTB _SFR_IO8(0x18) +#define PORTB3 3 +#define PORTB2 2 +#define PORTB1 1 +#define PORTB0 0 + +#define PINA _SFR_IO8(0x19) +#define PINA7 7 +#define PINA6 6 +#define PINA5 5 +#define PINA4 4 +#define PINA3 3 +#define PINA2 2 +#define PINA1 1 +#define PINA0 0 + +#define DDRA _SFR_IO8(0x1A) +#define DDRA7 7 +// Inserted "DDA7" from "DDRA7" due to compatibility +#define DDA7 7 +#define DDRA6 6 +// Inserted "DDA6" from "DDRA6" due to compatibility +#define DDA6 6 +#define DDRA5 5 +// Inserted "DDA5" from "DDRA5" due to compatibility +#define DDA5 5 +#define DDRA4 4 +// Inserted "DDA4" from "DDRA4" due to compatibility +#define DDA4 4 +#define DDRA3 3 +// Inserted "DDA3" from "DDRA3" due to compatibility +#define DDA3 3 +#define DDRA2 2 +// Inserted "DDA2" from "DDRA2" due to compatibility +#define DDA2 2 +#define DDRA1 1 +// Inserted "DDA1" from "DDRA1" due to compatibility +#define DDA1 1 +#define DDRA0 0 +// Inserted "DDA0" from "DDRA0" due to compatibility +#define DDA0 0 + +#define PORTA _SFR_IO8(0x1B) +#define PORTA7 7 +#define PORTA6 6 +#define PORTA5 5 +#define PORTA4 4 +#define PORTA3 3 +#define PORTA2 2 +#define PORTA1 1 +#define PORTA0 0 + +#define EECR _SFR_IO8(0x1C) +#define EERE 0 +#define EEPE 1 +#define EEMPE 2 +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 + +#define EEDR _SFR_IO8(0x1D) + +/* Combine EEARL and EEARH */ +#define EEAR _SFR_IO16(0x1E) + +#define EEARL _SFR_IO8(0x1E) +#define EEARH _SFR_IO8(0x1F) + +#define PCMSK1 _SFR_IO8(0x20) +#define PCINT8 0 +#define PCINT9 1 +#define PCINT10 2 +#define PCINT11 3 + +#define WDTCSR _SFR_IO8(0x21) +#define WDE 3 +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDP3 5 +#define WDIE 6 +#define WDIF 7 + +#define TCCR1C _SFR_IO8(0x22) +#define FOC1B 6 +#define FOC1A 7 + +#define GTCCR _SFR_IO8(0x23) +#define PSR 0 +#define TSM 7 + +/* Combine ICR1L and ICR1H */ +#define ICR1 _SFR_IO16(0x24) + +#define ICR1L _SFR_IO8(0x24) +#define ICR1H _SFR_IO8(0x25) + +/* Reserved [0x26..0x27] */ + +/* Combine OCR1BL and OCR1BH */ +#define OCR1B _SFR_IO16(0x28) + +#define OCR1BL _SFR_IO8(0x28) +#define OCR1BH _SFR_IO8(0x29) + +/* Combine OCR1AL and OCR1AH */ +#define OCR1A _SFR_IO16(0x2A) + +#define OCR1AL _SFR_IO8(0x2A) +#define OCR1AH _SFR_IO8(0x2B) + +/* Combine TCNT1L and TCNT1H */ +#define TCNT1 _SFR_IO16(0x2C) + +#define TCNT1L _SFR_IO8(0x2C) +#define TCNT1H _SFR_IO8(0x2D) + +#define TCCR1B _SFR_IO8(0x2E) +#define CS10 0 +#define CS11 1 +#define CS12 2 +#define WGM12 3 +#define WGM13 4 +#define ICES1 6 +#define ICNC1 7 + +#define TCCR1A _SFR_IO8(0x2F) +#define WGM10 0 +#define WGM11 1 +#define COM1B0 4 +#define COM1B1 5 +#define COM1A0 6 +#define COM1A1 7 + +#define TCCR0A _SFR_IO8(0x30) +#define WGM00 0 +#define WGM01 1 +#define COM0B0 4 +#define COM0B1 5 +#define COM0A0 6 +#define COM0A1 7 + +/* Reserved [0x31] */ + +#define TCNT0 _SFR_IO8(0x32) + +#define TCCR0B _SFR_IO8(0x33) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define WGM02 3 +#define FOC0B 6 +#define FOC0A 7 + +#define MCUSR _SFR_IO8(0x34) +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 + +#define MCUCR _SFR_IO8(0x35) +#define ISC00 0 +#define ISC01 1 +#define SM0 3 +#define SM1 4 +#define SE 5 + +#define OCR0A _SFR_IO8(0x36) + +#define SPMCSR _SFR_IO8(0x37) +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define RFLB 3 +#define CTPB 4 +#define RSIG 5 + +#define TIFR0 _SFR_IO8(0x38) +#define TOV0 0 +#define OCF0A 1 +#define OCF0B 2 + +#define TIMSK0 _SFR_IO8(0x39) +#define TOIE0 0 +#define OCIE0A 1 +#define OCIE0B 2 + +#define GIFR _SFR_IO8(0x3A) +#define PCIF0 4 +#define PCIF1 5 +#define INTF0 6 + +#define GIMSK _SFR_IO8(0x3B) +#define PCIE0 4 +#define PCIE1 5 +#define INT0 6 + +#define OCR0B _SFR_IO8(0x3C) + +/* SP [0x3D..0x3E] */ + +/* SREG [0x3F] */ + +#define DIDR0 _SFR_MEM8(0x60) +#define ADC0D 0 +#define ADC1D 1 +#define ADC2D 2 +#define ADC3D 3 +#define ADC4D 4 +#define ADC5D 5 +#define ADC6D 6 +#define ADC7D 7 + +#define DIDR1 _SFR_MEM8(0x61) +#define ADC11D 0 +#define ADC10D 1 +#define ADC8D 2 +#define ADC9D 3 + +#define PUEB _SFR_MEM8(0x62) +#define PUEB3 3 +#define PUEB2 2 +#define PUEB1 1 +#define PUEB0 0 + +#define PUEA _SFR_MEM8(0x63) +#define PUEA7 7 +#define PUEA6 6 +#define PUEA5 5 +#define PUEA4 4 +#define PUEA3 3 +#define PUEA2 2 +#define PUEA1 1 +#define PUEA0 0 + +#define PORTCR _SFR_MEM8(0x64) +#define BBMB 1 +#define BBMA 0 + +#define REMAP _SFR_MEM8(0x65) +#define U0MAP 0 +#define SPIMAP 1 + +#define TOCPMCOE _SFR_MEM8(0x66) +#define TOCC0OE 0 +#define TOCC1OE 1 +#define TOCC2OE 2 +#define TOCC3OE 3 +#define TOCC4OE 4 +#define TOCC5OE 5 +#define TOCC6OE 6 +#define TOCC7OE 7 + +#define TOCPMSA0 _SFR_MEM8(0x67) +#define TOCC0S0 0 +#define TOCC0S1 1 +#define TOCC1S0 2 +#define TOCC1S1 3 +#define TOCC2S0 4 +#define TOCC2S1 5 +#define TOCC3S0 6 +#define TOCC3S1 7 + +#define TOCPMSA1 _SFR_MEM8(0x68) +#define TOCC4S0 0 +#define TOCC4S1 1 +#define TOCC5S0 2 +#define TOCC5S1 3 +#define TOCC6S0 4 +#define TOCC6S1 5 +#define TOCC7S0 6 +#define TOCC7S1 7 + +/* Reserved [0x69] */ + +#define PHDE _SFR_MEM8(0x6A) +#define PHDEA0 0 +#define PHDEA1 1 + +/* Reserved [0x6B..0x6F] */ + +#define PRR _SFR_MEM8(0x70) +#define PRADC 0 +#define PRTIM0 1 +#define PRTIM1 2 +#define PRTIM2 3 +#define PRSPI 4 +#define PRUSART0 5 +#define PRUSART1 6 +#define PRTWI 7 + +#define __AVR_HAVE_PRR ((1< file." -#endif +#endif #ifndef _AVR_ATtiny84A_H_ @@ -842,4 +842,3 @@ #define SLEEP_MODE_STANDBY (0x03<<3) #endif /* _AVR_ATtiny84A_H_ */ - diff --git a/include/avr/iotn861a.h b/include/avr/iotn861a.h index 8a043217..c51611c6 100644 --- a/include/avr/iotn861a.h +++ b/include/avr/iotn861a.h @@ -42,7 +42,7 @@ # define _AVR_IOXXX_H_ "iotn861a.h" #else # error "Attempt to include more than one file." -#endif +#endif #ifndef _AVR_ATtiny861A_H_ @@ -985,4 +985,3 @@ #define SLEEP_MODE_STANDBY (0x03<<3) #endif /* _AVR_ATtiny861A_H_ */ - diff --git a/include/avr/iotn87.h b/include/avr/iotn87.h index 70cab443..04da5586 100644 --- a/include/avr/iotn87.h +++ b/include/avr/iotn87.h @@ -42,7 +42,7 @@ # define _AVR_IOXXX_H_ "iotn87.h" #else # error "Attempt to include more than one file." -#endif +#endif #ifndef _AVR_ATtiny87_H_ @@ -857,4 +857,3 @@ #define SLEEP_MODE_PWR_DOWN (0x02<<1) #endif /* _AVR_ATtiny87_H_ */ - diff --git a/include/avr/iotn88.h b/include/avr/iotn88.h index 5d620939..875f9961 100644 --- a/include/avr/iotn88.h +++ b/include/avr/iotn88.h @@ -26,7 +26,7 @@ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. + POSSIBILITY OF SUCH DAMAGE. */ /* $Id$ */ @@ -43,7 +43,7 @@ # define _AVR_IOXXX_H_ "iotn88.h" #else # error "Attempt to include more than one file." -#endif +#endif #ifndef _AVR_IOTN88_H_ @@ -782,7 +782,7 @@ #define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ #define FUSE_DWEN (unsigned char)~_BV(6) /* debugWIRE Enable */ #define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External reset disable */ -#define HFUSE_DEFAULT (FUSE_SPIEN) +#define HFUSE_DEFAULT (FUSE_SPIEN) /* Extended Fuse Byte */ #define FUSE_SELFPRGEN ~_BV(0) /* Self Programming Enable */ diff --git a/include/avr/iotn9.h b/include/avr/iotn9.h index c01dac80..74720056 100644 --- a/include/avr/iotn9.h +++ b/include/avr/iotn9.h @@ -42,7 +42,7 @@ # define _AVR_IOXXX_H_ "iotn9.h" #else # error "Attempt to include more than one file." -#endif +#endif #ifndef _AVR_ATtiny9_H_ @@ -475,4 +475,3 @@ #define SLEEP_MODE_STANDBY (0x04<<1) #endif /* _AVR_ATtiny9_H_ */ - diff --git a/include/avr/iotnx4.h b/include/avr/iotnx4.h index cb95b6f9..52fa788e 100644 --- a/include/avr/iotnx4.h +++ b/include/avr/iotnx4.h @@ -45,7 +45,7 @@ # define _AVR_IOXXX_H_ "iotnx4.h" #else # error "Attempt to include more than one file." -#endif +#endif /* I/O registers */ @@ -68,7 +68,7 @@ #define ADC4D 4 #define ADC3D 3 #define ADC2D 2 -#define ADC1D 1 +#define ADC1D 1 #define ADC0D 0 /* Reserved [0x02] */ @@ -143,7 +143,7 @@ #define USITC 0 #define USISR _SFR_IO8(0x0E) -#define USISIF 7 +#define USISIF 7 #define USIOIF 6 #define USIPF 5 #define USIDC 4 diff --git a/include/avr/iotnx5.h b/include/avr/iotnx5.h index 4965b12b..d1d9cc9d 100644 --- a/include/avr/iotnx5.h +++ b/include/avr/iotnx5.h @@ -45,7 +45,7 @@ # define _AVR_IOXXX_H_ "iotnx5.h" #else # error "Attempt to include more than one file." -#endif +#endif /* I/O registers */ @@ -108,7 +108,7 @@ #define USITC 0 #define USISR _SFR_IO8(0x0E) -#define USISIF 7 +#define USISIF 7 #define USIOIF 6 #define USIPF 5 #define USIDC 4 @@ -129,7 +129,7 @@ #define ADC2D 4 #define ADC3D 3 #define ADC1D 2 -#define AIN1D 1 +#define AIN1D 1 #define AIN0D 0 #define PCMSK _SFR_IO8(0x15) diff --git a/include/avr/iotnx61.h b/include/avr/iotnx61.h index 346ac3a2..c9acf721 100644 --- a/include/avr/iotnx61.h +++ b/include/avr/iotnx61.h @@ -42,7 +42,7 @@ # define _AVR_IOXXX_H_ "iotnx61.h" #else # error "Attempt to include more than one file." -#endif +#endif #ifndef _AVR_IOTNx61_H_ #define _AVR_IOTNx61_H_ 1 diff --git a/include/avr/iousb1286.h b/include/avr/iousb1286.h index d1fb7803..4dea32d6 100644 --- a/include/avr/iousb1286.h +++ b/include/avr/iousb1286.h @@ -1,4 +1,4 @@ -/* Copyright (c) 2006 Anatoly Sokolov +/* Copyright (c) 2006 Anatoly Sokolov All rights reserved. Redistribution and use in source and binary forms, with or without @@ -83,7 +83,7 @@ /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST -#define __BOOT_LOCK_BITS_1_EXIST +#define __BOOT_LOCK_BITS_1_EXIST /* Signature */ diff --git a/include/avr/iousb1287.h b/include/avr/iousb1287.h index 8a10b386..b45c3d91 100644 --- a/include/avr/iousb1287.h +++ b/include/avr/iousb1287.h @@ -1,4 +1,4 @@ -/* Copyright (c) 2006 Anatoly Sokolov +/* Copyright (c) 2006 Anatoly Sokolov All rights reserved. Redistribution and use in source and binary forms, with or without @@ -83,7 +83,7 @@ /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST -#define __BOOT_LOCK_BITS_1_EXIST +#define __BOOT_LOCK_BITS_1_EXIST /* Signature */ diff --git a/include/avr/iousb162.h b/include/avr/iousb162.h index e774f95f..1d322be8 100644 --- a/include/avr/iousb162.h +++ b/include/avr/iousb162.h @@ -84,7 +84,7 @@ /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST -#define __BOOT_LOCK_BITS_1_EXIST +#define __BOOT_LOCK_BITS_1_EXIST /* Signature */ diff --git a/include/avr/iousb646.h b/include/avr/iousb646.h index 54978fdb..642a1a57 100644 --- a/include/avr/iousb646.h +++ b/include/avr/iousb646.h @@ -84,7 +84,7 @@ /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST -#define __BOOT_LOCK_BITS_1_EXIST +#define __BOOT_LOCK_BITS_1_EXIST /* Signature */ diff --git a/include/avr/iousb647.h b/include/avr/iousb647.h index 1a6ba4d3..518dd027 100644 --- a/include/avr/iousb647.h +++ b/include/avr/iousb647.h @@ -1,5 +1,5 @@ /* Copyright (c) 2006 Anatoly Sokolov - Copyright (c) 2010 Atmel Corporation + Copyright (c) 2010 Atmel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without @@ -84,7 +84,7 @@ /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST -#define __BOOT_LOCK_BITS_1_EXIST +#define __BOOT_LOCK_BITS_1_EXIST /* Signature */ diff --git a/include/avr/iousb82.h b/include/avr/iousb82.h index c6e826f8..055beed2 100644 --- a/include/avr/iousb82.h +++ b/include/avr/iousb82.h @@ -84,7 +84,7 @@ /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST -#define __BOOT_LOCK_BITS_1_EXIST +#define __BOOT_LOCK_BITS_1_EXIST #define SLEEP_MODE_IDLE (0x00<<1) diff --git a/include/avr/iousbxx2.h b/include/avr/iousbxx2.h index 19de21cf..e03dbfbf 100644 --- a/include/avr/iousbxx2.h +++ b/include/avr/iousbxx2.h @@ -1,4 +1,4 @@ -/* Copyright (c) 2007 Anatoly Sokolov +/* Copyright (c) 2007 Anatoly Sokolov All rights reserved. Redistribution and use in source and binary forms, with or without @@ -45,7 +45,7 @@ # define _AVR_IOXXX_H_ "iousbxx2.h" #else # error "Attempt to include more than one file." -#endif +#endif /* Registers and associated bit numbers */ @@ -175,7 +175,7 @@ #define INT4 4 #define INT3 3 #define INT2 2 -#define INT1 1 +#define INT1 1 #define INT0 0 #define GPIOR0 _SFR_IO8(0x1E) diff --git a/include/avr/iousbxx6_7.h b/include/avr/iousbxx6_7.h index 050538d3..f5b8e60c 100644 --- a/include/avr/iousbxx6_7.h +++ b/include/avr/iousbxx6_7.h @@ -1,4 +1,4 @@ -/* Copyright (c) 2006, Anatoly Sokolov +/* Copyright (c) 2006, Anatoly Sokolov All rights reserved. Redistribution and use in source and binary forms, with or without @@ -30,7 +30,7 @@ /* $Id$ */ -/* iousbxx6_7.h - definitions for AT90USB646, AT90USB647, AT90USB1286 +/* iousbxx6_7.h - definitions for AT90USB646, AT90USB647, AT90USB1286 and AT90USB1287 */ #ifndef _AVR_IOUSBXX6_7_H_ @@ -46,7 +46,7 @@ # define _AVR_IOXXX_H_ "iousbxx6_7.h" #else # error "Attempt to include more than one file." -#endif +#endif #if defined(__AVR_AT90USB646__) || defined(__AVR_AT90USB1286__) # define __AT90USBxx6__ 1 @@ -284,7 +284,7 @@ #define INT4 4 #define INT3 3 #define INT2 2 -#define INT1 1 +#define INT1 1 #define INT0 0 #define GPIOR0 _SFR_IO8(0x1E) diff --git a/include/avr/iox128a1.h b/include/avr/iox128a1.h index 2cef5ed4..906178e0 100644 --- a/include/avr/iox128a1.h +++ b/include/avr/iox128a1.h @@ -42,7 +42,7 @@ # define _AVR_IOXXX_H_ "iox128a1.h" #else # error "Attempt to include more than one file." -#endif +#endif #ifndef _AVR_ATxmega128A1_H_ @@ -6659,21 +6659,21 @@ IO Module Instances. Mapped to memory. // Generic Port Pins -#define PIN0_bm 0x01 +#define PIN0_bm 0x01 #define PIN0_bp 0 #define PIN1_bm 0x02 #define PIN1_bp 1 -#define PIN2_bm 0x04 +#define PIN2_bm 0x04 #define PIN2_bp 2 -#define PIN3_bm 0x08 +#define PIN3_bm 0x08 #define PIN3_bp 3 -#define PIN4_bm 0x10 +#define PIN4_bm 0x10 #define PIN4_bp 4 -#define PIN5_bm 0x20 +#define PIN5_bm 0x20 #define PIN5_bp 5 -#define PIN6_bm 0x40 +#define PIN6_bm 0x40 #define PIN6_bp 6 -#define PIN7_bm 0x80 +#define PIN7_bm 0x80 #define PIN7_bp 7 @@ -7233,4 +7233,3 @@ IO Module Instances. Mapped to memory. #endif /* _AVR_ATxmega128A1_H_ */ - diff --git a/include/avr/iox128a1u.h b/include/avr/iox128a1u.h index 419528a8..80cba65e 100644 --- a/include/avr/iox128a1u.h +++ b/include/avr/iox128a1u.h @@ -42,7 +42,7 @@ # define _AVR_IOXXX_H_ "iox128a1u.h" #else # error "Attempt to include more than one file." -#endif +#endif #ifndef _AVR_ATxmega128A1U_H_ @@ -7345,21 +7345,21 @@ IO Module Instances. Mapped to memory. // Generic Port Pins -#define PIN0_bm 0x01 +#define PIN0_bm 0x01 #define PIN0_bp 0 #define PIN1_bm 0x02 #define PIN1_bp 1 -#define PIN2_bm 0x04 +#define PIN2_bm 0x04 #define PIN2_bp 2 -#define PIN3_bm 0x08 +#define PIN3_bm 0x08 #define PIN3_bp 3 -#define PIN4_bm 0x10 +#define PIN4_bm 0x10 #define PIN4_bp 4 -#define PIN5_bm 0x20 +#define PIN5_bm 0x20 #define PIN5_bp 5 -#define PIN6_bm 0x40 +#define PIN6_bm 0x40 #define PIN6_bp 6 -#define PIN7_bm 0x80 +#define PIN7_bm 0x80 #define PIN7_bp 7 @@ -7877,4 +7877,3 @@ IO Module Instances. Mapped to memory. #define __AVR_HAVE_PRPF_TC0 #endif /* _AVR_ATxmega128A1U_H_ */ - diff --git a/include/avr/iox128a3.h b/include/avr/iox128a3.h index 1ab13723..e3e54bbd 100644 --- a/include/avr/iox128a3.h +++ b/include/avr/iox128a3.h @@ -42,7 +42,7 @@ # define _AVR_IOXXX_H_ "iox128a3.h" #else # error "Attempt to include more than one file." -#endif +#endif #ifndef _AVR_ATxmega128A3_H_ @@ -6473,21 +6473,21 @@ IO Module Instances. Mapped to memory. // Generic Port Pins -#define PIN0_bm 0x01 +#define PIN0_bm 0x01 #define PIN0_bp 0 #define PIN1_bm 0x02 #define PIN1_bp 1 -#define PIN2_bm 0x04 +#define PIN2_bm 0x04 #define PIN2_bp 2 -#define PIN3_bm 0x08 +#define PIN3_bm 0x08 #define PIN3_bp 3 -#define PIN4_bm 0x10 +#define PIN4_bm 0x10 #define PIN4_bp 4 -#define PIN5_bm 0x20 +#define PIN5_bm 0x20 #define PIN5_bp 5 -#define PIN6_bm 0x40 +#define PIN6_bm 0x40 #define PIN6_bp 6 -#define PIN7_bm 0x80 +#define PIN7_bm 0x80 #define PIN7_bp 7 @@ -6984,4 +6984,3 @@ IO Module Instances. Mapped to memory. #endif /* _AVR_ATxmega128A3_H_ */ - diff --git a/include/avr/iox128a3u.h b/include/avr/iox128a3u.h index f4f750c4..c925bc83 100644 --- a/include/avr/iox128a3u.h +++ b/include/avr/iox128a3u.h @@ -7697,4 +7697,3 @@ IO Module Instances. Mapped to memory. #endif /* #ifdef _AVR_ATXMEGA128A3U_H_INCLUDED */ - diff --git a/include/avr/iox128a4u.h b/include/avr/iox128a4u.h index 5ea5be93..e4ee3643 100644 --- a/include/avr/iox128a4u.h +++ b/include/avr/iox128a4u.h @@ -7309,4 +7309,3 @@ IO Module Instances. Mapped to memory. #endif /* #ifdef _AVR_ATXMEGA128A4U_H_INCLUDED */ - diff --git a/include/avr/iox128b1.h b/include/avr/iox128b1.h index b6ecb37d..68196712 100644 --- a/include/avr/iox128b1.h +++ b/include/avr/iox128b1.h @@ -6872,4 +6872,3 @@ IO Module Instances. Mapped to memory. #endif /* #ifdef _AVR_ATXMEGA128B1_H_INCLUDED */ - diff --git a/include/avr/iox128b3.h b/include/avr/iox128b3.h index 6dd20376..01f3f958 100644 --- a/include/avr/iox128b3.h +++ b/include/avr/iox128b3.h @@ -6288,4 +6288,3 @@ IO Module Instances. Mapped to memory. #endif /* #ifdef _AVR_ATXMEGA128B3_H_INCLUDED */ - diff --git a/include/avr/iox128c3.h b/include/avr/iox128c3.h index d660747d..17e018bc 100644 --- a/include/avr/iox128c3.h +++ b/include/avr/iox128c3.h @@ -6264,4 +6264,3 @@ IO Module Instances. Mapped to memory. #endif /* #ifdef _AVR_ATXMEGA128C3_H_INCLUDED */ - diff --git a/include/avr/iox128d3.h b/include/avr/iox128d3.h index 8ecd6482..b9069469 100644 --- a/include/avr/iox128d3.h +++ b/include/avr/iox128d3.h @@ -42,7 +42,7 @@ # define _AVR_IOXXX_H_ "iox128d3.h" #else # error "Attempt to include more than one file." -#endif +#endif #ifndef _AVR_ATxmega128D3_H_ @@ -1114,7 +1114,7 @@ typedef enum ADC_CH_GAIN_enum ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ - ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ + ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ } ADC_CH_GAIN_t; /* Conversion result resolution */ @@ -5353,21 +5353,21 @@ IO Module Instances. Mapped to memory. // Generic Port Pins -#define PIN0_bm 0x01 +#define PIN0_bm 0x01 #define PIN0_bp 0 #define PIN1_bm 0x02 #define PIN1_bp 1 -#define PIN2_bm 0x04 +#define PIN2_bm 0x04 #define PIN2_bp 2 -#define PIN3_bm 0x08 +#define PIN3_bm 0x08 #define PIN3_bp 3 -#define PIN4_bm 0x10 +#define PIN4_bm 0x10 #define PIN4_bp 4 -#define PIN5_bm 0x20 +#define PIN5_bm 0x20 #define PIN5_bp 5 -#define PIN6_bm 0x40 +#define PIN6_bm 0x40 #define PIN6_bp 6 -#define PIN7_bm 0x80 +#define PIN7_bm 0x80 #define PIN7_bp 7 @@ -5745,4 +5745,3 @@ IO Module Instances. Mapped to memory. #endif /* _AVR_ATxmega128D3_H_ */ - diff --git a/include/avr/iox128d4.h b/include/avr/iox128d4.h index 92979b7a..eb769256 100644 --- a/include/avr/iox128d4.h +++ b/include/avr/iox128d4.h @@ -5555,4 +5555,3 @@ IO Module Instances. Mapped to memory. #endif /* #ifdef _AVR_ATXMEGA128D4_H_INCLUDED */ - diff --git a/include/avr/iox16a4.h b/include/avr/iox16a4.h index af6e3823..44edadc4 100644 --- a/include/avr/iox16a4.h +++ b/include/avr/iox16a4.h @@ -42,7 +42,7 @@ # define _AVR_IOXXX_H_ "iox16a4.h" #else # error "Attempt to include more than one file." -#endif +#endif #ifndef _AVR_ATxmega16A4_H_ @@ -6292,21 +6292,21 @@ IO Module Instances. Mapped to memory. // Generic Port Pins -#define PIN0_bm 0x01 +#define PIN0_bm 0x01 #define PIN0_bp 0 #define PIN1_bm 0x02 #define PIN1_bp 1 -#define PIN2_bm 0x04 +#define PIN2_bm 0x04 #define PIN2_bp 2 -#define PIN3_bm 0x08 +#define PIN3_bm 0x08 #define PIN3_bp 3 -#define PIN4_bm 0x10 +#define PIN4_bm 0x10 #define PIN4_bp 4 -#define PIN5_bm 0x20 +#define PIN5_bm 0x20 #define PIN5_bp 5 -#define PIN6_bm 0x40 +#define PIN6_bm 0x40 #define PIN6_bp 6 -#define PIN7_bm 0x80 +#define PIN7_bm 0x80 #define PIN7_bp 7 @@ -6744,4 +6744,3 @@ IO Module Instances. Mapped to memory. #endif /* _AVR_ATxmega16A4_H_ */ - diff --git a/include/avr/iox16a4u.h b/include/avr/iox16a4u.h index 8e2a93d3..e86ce066 100644 --- a/include/avr/iox16a4u.h +++ b/include/avr/iox16a4u.h @@ -7309,4 +7309,3 @@ IO Module Instances. Mapped to memory. #endif /* #ifdef _AVR_ATXMEGA16A4U_H_INCLUDED */ - diff --git a/include/avr/iox16c4.h b/include/avr/iox16c4.h index cb1f476a..1567c7ec 100644 --- a/include/avr/iox16c4.h +++ b/include/avr/iox16c4.h @@ -6078,4 +6078,3 @@ IO Module Instances. Mapped to memory. #endif /* #ifdef _AVR_ATXMEGA16C4_H_INCLUDED */ - diff --git a/include/avr/iox16d4.h b/include/avr/iox16d4.h index 735f9554..ea869c9e 100644 --- a/include/avr/iox16d4.h +++ b/include/avr/iox16d4.h @@ -42,7 +42,7 @@ # define _AVR_IOXXX_H_ "iox16d4.h" #else # error "Attempt to include more than one file." -#endif +#endif #ifndef _AVR_ATxmega16D4_H_ @@ -1123,7 +1123,7 @@ typedef enum ADC_CH_GAIN_enum ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ - ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ + ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ } ADC_CH_GAIN_t; /* Conversion result resolution */ @@ -5349,21 +5349,21 @@ IO Module Instances. Mapped to memory. // Generic Port Pins -#define PIN0_bm 0x01 +#define PIN0_bm 0x01 #define PIN0_bp 0 #define PIN1_bm 0x02 #define PIN1_bp 1 -#define PIN2_bm 0x04 +#define PIN2_bm 0x04 #define PIN2_bp 2 -#define PIN3_bm 0x08 +#define PIN3_bm 0x08 #define PIN3_bp 3 -#define PIN4_bm 0x10 +#define PIN4_bm 0x10 #define PIN4_bp 4 -#define PIN5_bm 0x20 +#define PIN5_bm 0x20 #define PIN5_bp 5 -#define PIN6_bm 0x40 +#define PIN6_bm 0x40 #define PIN6_bp 6 -#define PIN7_bm 0x80 +#define PIN7_bm 0x80 #define PIN7_bp 7 @@ -5713,4 +5713,3 @@ IO Module Instances. Mapped to memory. #endif /* _AVR_ATxmega16D4_H_ */ - diff --git a/include/avr/iox192a3.h b/include/avr/iox192a3.h index 6ccc46ba..5383e231 100644 --- a/include/avr/iox192a3.h +++ b/include/avr/iox192a3.h @@ -42,7 +42,7 @@ # define _AVR_IOXXX_H_ "iox192a3.h" #else # error "Attempt to include more than one file." -#endif +#endif #ifndef _AVR_ATxmega192A3_H_ @@ -6473,21 +6473,21 @@ IO Module Instances. Mapped to memory. // Generic Port Pins -#define PIN0_bm 0x01 +#define PIN0_bm 0x01 #define PIN0_bp 0 #define PIN1_bm 0x02 #define PIN1_bp 1 -#define PIN2_bm 0x04 +#define PIN2_bm 0x04 #define PIN2_bp 2 -#define PIN3_bm 0x08 +#define PIN3_bm 0x08 #define PIN3_bp 3 -#define PIN4_bm 0x10 +#define PIN4_bm 0x10 #define PIN4_bp 4 -#define PIN5_bm 0x20 +#define PIN5_bm 0x20 #define PIN5_bp 5 -#define PIN6_bm 0x40 +#define PIN6_bm 0x40 #define PIN6_bp 6 -#define PIN7_bm 0x80 +#define PIN7_bm 0x80 #define PIN7_bp 7 @@ -6984,4 +6984,3 @@ IO Module Instances. Mapped to memory. #endif /* _AVR_ATxmega192A3_H_ */ - diff --git a/include/avr/iox192a3u.h b/include/avr/iox192a3u.h index ad412b69..0c13e360 100644 --- a/include/avr/iox192a3u.h +++ b/include/avr/iox192a3u.h @@ -7697,4 +7697,3 @@ IO Module Instances. Mapped to memory. #endif /* #ifdef _AVR_ATXMEGA192A3U_H_INCLUDED */ - diff --git a/include/avr/iox192c3.h b/include/avr/iox192c3.h index e15a914b..a5a93ef7 100644 --- a/include/avr/iox192c3.h +++ b/include/avr/iox192c3.h @@ -6264,4 +6264,3 @@ IO Module Instances. Mapped to memory. #endif /* #ifdef _AVR_ATXMEGA192C3_H_INCLUDED */ - diff --git a/include/avr/iox192d3.h b/include/avr/iox192d3.h index 401511ab..a3daa4b1 100644 --- a/include/avr/iox192d3.h +++ b/include/avr/iox192d3.h @@ -42,7 +42,7 @@ # define _AVR_IOXXX_H_ "iox192d3.h" #else # error "Attempt to include more than one file." -#endif +#endif #ifndef _AVR_ATxmega192D3_H_ @@ -1114,7 +1114,7 @@ typedef enum ADC_CH_GAIN_enum ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ - ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ + ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ } ADC_CH_GAIN_t; /* Conversion result resolution */ @@ -5353,21 +5353,21 @@ IO Module Instances. Mapped to memory. // Generic Port Pins -#define PIN0_bm 0x01 +#define PIN0_bm 0x01 #define PIN0_bp 0 #define PIN1_bm 0x02 #define PIN1_bp 1 -#define PIN2_bm 0x04 +#define PIN2_bm 0x04 #define PIN2_bp 2 -#define PIN3_bm 0x08 +#define PIN3_bm 0x08 #define PIN3_bp 3 -#define PIN4_bm 0x10 +#define PIN4_bm 0x10 #define PIN4_bp 4 -#define PIN5_bm 0x20 +#define PIN5_bm 0x20 #define PIN5_bp 5 -#define PIN6_bm 0x40 +#define PIN6_bm 0x40 #define PIN6_bp 6 -#define PIN7_bm 0x80 +#define PIN7_bm 0x80 #define PIN7_bp 7 @@ -5745,4 +5745,3 @@ IO Module Instances. Mapped to memory. #endif /* _AVR_ATxmega192D3_H_ */ - diff --git a/include/avr/iox256a3.h b/include/avr/iox256a3.h index 050bd210..9810044e 100644 --- a/include/avr/iox256a3.h +++ b/include/avr/iox256a3.h @@ -42,7 +42,7 @@ # define _AVR_IOXXX_H_ "iox256a3.h" #else # error "Attempt to include more than one file." -#endif +#endif #ifndef _AVR_ATxmega256A3_H_ @@ -6473,21 +6473,21 @@ IO Module Instances. Mapped to memory. // Generic Port Pins -#define PIN0_bm 0x01 +#define PIN0_bm 0x01 #define PIN0_bp 0 #define PIN1_bm 0x02 #define PIN1_bp 1 -#define PIN2_bm 0x04 +#define PIN2_bm 0x04 #define PIN2_bp 2 -#define PIN3_bm 0x08 +#define PIN3_bm 0x08 #define PIN3_bp 3 -#define PIN4_bm 0x10 +#define PIN4_bm 0x10 #define PIN4_bp 4 -#define PIN5_bm 0x20 +#define PIN5_bm 0x20 #define PIN5_bp 5 -#define PIN6_bm 0x40 +#define PIN6_bm 0x40 #define PIN6_bp 6 -#define PIN7_bm 0x80 +#define PIN7_bm 0x80 #define PIN7_bp 7 @@ -6984,4 +6984,3 @@ IO Module Instances. Mapped to memory. #endif /* _AVR_ATxmega256A3_H_ */ - diff --git a/include/avr/iox256a3b.h b/include/avr/iox256a3b.h index 5d08f783..bd3979e8 100644 --- a/include/avr/iox256a3b.h +++ b/include/avr/iox256a3b.h @@ -42,7 +42,7 @@ # define _AVR_IOXXX_H_ "iox256a3b.h" #else # error "Attempt to include more than one file." -#endif +#endif #ifndef _AVR_ATxmega256A3B_H_ @@ -6481,21 +6481,21 @@ IO Module Instances. Mapped to memory. // Generic Port Pins -#define PIN0_bm 0x01 +#define PIN0_bm 0x01 #define PIN0_bp 0 #define PIN1_bm 0x02 #define PIN1_bp 1 -#define PIN2_bm 0x04 +#define PIN2_bm 0x04 #define PIN2_bp 2 -#define PIN3_bm 0x08 +#define PIN3_bm 0x08 #define PIN3_bp 3 -#define PIN4_bm 0x10 +#define PIN4_bm 0x10 #define PIN4_bp 4 -#define PIN5_bm 0x20 +#define PIN5_bm 0x20 #define PIN5_bp 5 -#define PIN6_bm 0x40 +#define PIN6_bm 0x40 #define PIN6_bp 6 -#define PIN7_bm 0x80 +#define PIN7_bm 0x80 #define PIN7_bp 7 @@ -6980,4 +6980,3 @@ IO Module Instances. Mapped to memory. #endif /* _AVR_ATxmega256A3B_H_ */ - diff --git a/include/avr/iox256a3bu.h b/include/avr/iox256a3bu.h index 3d8efe00..858bc1b3 100644 --- a/include/avr/iox256a3bu.h +++ b/include/avr/iox256a3bu.h @@ -7706,4 +7706,3 @@ IO Module Instances. Mapped to memory. #endif /* #ifdef _AVR_ATXMEGA256A3BU_H_INCLUDED */ - diff --git a/include/avr/iox256a3u.h b/include/avr/iox256a3u.h index 8c55a333..b2c23f19 100644 --- a/include/avr/iox256a3u.h +++ b/include/avr/iox256a3u.h @@ -7697,4 +7697,3 @@ IO Module Instances. Mapped to memory. #endif /* #ifdef _AVR_ATXMEGA256A3U_H_INCLUDED */ - diff --git a/include/avr/iox256c3.h b/include/avr/iox256c3.h index 761213f8..f38d63b9 100644 --- a/include/avr/iox256c3.h +++ b/include/avr/iox256c3.h @@ -6264,4 +6264,3 @@ IO Module Instances. Mapped to memory. #endif /* #ifdef _AVR_ATXMEGA256C3_H_INCLUDED */ - diff --git a/include/avr/iox256d3.h b/include/avr/iox256d3.h index 7be60c22..c5252e84 100644 --- a/include/avr/iox256d3.h +++ b/include/avr/iox256d3.h @@ -42,7 +42,7 @@ # define _AVR_IOXXX_H_ "iox256d3.h" #else # error "Attempt to include more than one file." -#endif +#endif #ifndef _AVR_ATxmega256D3_H_ @@ -1099,7 +1099,7 @@ typedef enum ADC_CH_GAIN_enum ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ - ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ + ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ } ADC_CH_GAIN_t; /* Conversion result resolution */ @@ -5312,21 +5312,21 @@ IO Module Instances. Mapped to memory. // Generic Port Pins -#define PIN0_bm 0x01 +#define PIN0_bm 0x01 #define PIN0_bp 0 #define PIN1_bm 0x02 #define PIN1_bp 1 -#define PIN2_bm 0x04 +#define PIN2_bm 0x04 #define PIN2_bp 2 -#define PIN3_bm 0x08 +#define PIN3_bm 0x08 #define PIN3_bp 3 -#define PIN4_bm 0x10 +#define PIN4_bm 0x10 #define PIN4_bp 4 -#define PIN5_bm 0x20 +#define PIN5_bm 0x20 #define PIN5_bp 5 -#define PIN6_bm 0x40 +#define PIN6_bm 0x40 #define PIN6_bp 6 -#define PIN7_bm 0x80 +#define PIN7_bm 0x80 #define PIN7_bp 7 @@ -5705,4 +5705,3 @@ IO Module Instances. Mapped to memory. #endif /* _AVR_ATxmega256D3_H_ */ - diff --git a/include/avr/iox32a4.h b/include/avr/iox32a4.h index 05184462..2a7af1db 100644 --- a/include/avr/iox32a4.h +++ b/include/avr/iox32a4.h @@ -42,7 +42,7 @@ # define _AVR_IOXXX_H_ "iox32a4.h" #else # error "Attempt to include more than one file." -#endif +#endif #ifndef _AVR_ATxmega32A4_H_ @@ -6291,21 +6291,21 @@ IO Module Instances. Mapped to memory. // Generic Port Pins -#define PIN0_bm 0x01 +#define PIN0_bm 0x01 #define PIN0_bp 0 #define PIN1_bm 0x02 #define PIN1_bp 1 -#define PIN2_bm 0x04 +#define PIN2_bm 0x04 #define PIN2_bp 2 -#define PIN3_bm 0x08 +#define PIN3_bm 0x08 #define PIN3_bp 3 -#define PIN4_bm 0x10 +#define PIN4_bm 0x10 #define PIN4_bp 4 -#define PIN5_bm 0x20 +#define PIN5_bm 0x20 #define PIN5_bp 5 -#define PIN6_bm 0x40 +#define PIN6_bm 0x40 #define PIN6_bp 6 -#define PIN7_bm 0x80 +#define PIN7_bm 0x80 #define PIN7_bp 7 @@ -6743,4 +6743,3 @@ IO Module Instances. Mapped to memory. #endif /* _AVR_ATxmega32A4_H_ */ - diff --git a/include/avr/iox32a4u.h b/include/avr/iox32a4u.h index 8e83e442..78972fe8 100644 --- a/include/avr/iox32a4u.h +++ b/include/avr/iox32a4u.h @@ -7309,4 +7309,3 @@ IO Module Instances. Mapped to memory. #endif /* #ifdef _AVR_ATXMEGA32A4U_H_INCLUDED */ - diff --git a/include/avr/iox32c3.h b/include/avr/iox32c3.h index 96457898..56fffe8b 100644 --- a/include/avr/iox32c3.h +++ b/include/avr/iox32c3.h @@ -1,6264 +1,6263 @@ -/***************************************************************************** - * - * Copyright (C) 2016 Atmel Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * * Neither the name of the copyright holders nor the names of - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************/ - - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iox32c3.h" -#else -# error "Attempt to include more than one file." -#endif - -#ifndef _AVR_ATXMEGA32C3_H_INCLUDED -#define _AVR_ATXMEGA32C3_H_INCLUDED - -/* Ungrouped common registers */ -#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ - -/* Deprecated */ -#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ - -#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ -#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ -#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ -#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ -#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ -#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ -#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ -#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ -#define SREG _SFR_MEM8(0x003F) /* Status Register */ - -/* C Language Only */ -#if !defined (__ASSEMBLER__) - -#include - -typedef volatile uint8_t register8_t; -typedef volatile uint16_t register16_t; -typedef volatile uint32_t register32_t; - - -#ifdef _WORDREGISTER -#undef _WORDREGISTER -#endif -#define _WORDREGISTER(regname) \ - __extension__ union \ - { \ - register16_t regname; \ - struct \ - { \ - register8_t regname ## L; \ - register8_t regname ## H; \ - }; \ - } - -#ifdef _DWORDREGISTER -#undef _DWORDREGISTER -#endif -#define _DWORDREGISTER(regname) \ - __extension__ union \ - { \ - register32_t regname; \ - struct \ - { \ - register8_t regname ## 0; \ - register8_t regname ## 1; \ - register8_t regname ## 2; \ - register8_t regname ## 3; \ - }; \ - } - - -/* -========================================================================== -IO Module Structures -========================================================================== -*/ - - -/* --------------------------------------------------------------------------- -VPORT - Virtual Ports --------------------------------------------------------------------------- -*/ - -/* Virtual Port */ -typedef struct VPORT_struct -{ - register8_t DIR; /* I/O Port Data Direction */ - register8_t OUT; /* I/O Port Output */ - register8_t IN; /* I/O Port Input */ - register8_t INTFLAGS; /* Interrupt Flag Register */ -} VPORT_t; - - -/* --------------------------------------------------------------------------- -XOCD - On-Chip Debug System --------------------------------------------------------------------------- -*/ - -/* On-Chip Debug System */ -typedef struct OCD_struct -{ - register8_t OCDR0; /* OCD Register 0 */ - register8_t OCDR1; /* OCD Register 1 */ -} OCD_t; - - -/* --------------------------------------------------------------------------- -CPU - CPU --------------------------------------------------------------------------- -*/ - -/* CCP signatures */ -typedef enum CCP_enum -{ - CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ - CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ -} CCP_t; - - -/* --------------------------------------------------------------------------- -CLK - Clock System --------------------------------------------------------------------------- -*/ - -/* Clock System */ -typedef struct CLK_struct -{ - register8_t CTRL; /* Control Register */ - register8_t PSCTRL; /* Prescaler Control Register */ - register8_t LOCK; /* Lock register */ - register8_t RTCCTRL; /* RTC Control Register */ - register8_t USBCTRL; /* USB Control Register */ -} CLK_t; - - -/* Power Reduction */ -typedef struct PR_struct -{ - register8_t PRGEN; /* General Power Reduction */ - register8_t PRPA; /* Power Reduction Port A */ - register8_t reserved_0x02; - register8_t PRPC; /* Power Reduction Port C */ - register8_t PRPD; /* Power Reduction Port D */ - register8_t PRPE; /* Power Reduction Port E */ - register8_t PRPF; /* Power Reduction Port F */ -} PR_t; - -/* System Clock Selection */ -typedef enum CLK_SCLKSEL_enum -{ - CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ - CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ - CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ - CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ - CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ -} CLK_SCLKSEL_t; - -/* Prescaler A Division Factor */ -typedef enum CLK_PSADIV_enum -{ - CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ - CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ - CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ - CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ - CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ - CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ - CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ - CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ - CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ - CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ -} CLK_PSADIV_t; - -/* Prescaler B and C Division Factor */ -typedef enum CLK_PSBCDIV_enum -{ - CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ - CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ - CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ - CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ -} CLK_PSBCDIV_t; - -/* RTC Clock Source */ -typedef enum CLK_RTCSRC_enum -{ - CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ - CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ - CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ - CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ - CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ - CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ -} CLK_RTCSRC_t; - -/* USB Prescaler Division Factor */ -typedef enum CLK_USBPSDIV_enum -{ - CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */ - CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */ - CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */ - CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */ - CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */ - CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */ -} CLK_USBPSDIV_t; - -/* USB Clock Source */ -typedef enum CLK_USBSRC_enum -{ - CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */ - CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */ -} CLK_USBSRC_t; - - -/* --------------------------------------------------------------------------- -SLEEP - Sleep Controller --------------------------------------------------------------------------- -*/ - -/* Sleep Controller */ -typedef struct SLEEP_struct -{ - register8_t CTRL; /* Control Register */ -} SLEEP_t; - -/* Sleep Mode */ -typedef enum SLEEP_SMODE_enum -{ - SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ - SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ - SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ - SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ - SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ -} SLEEP_SMODE_t; - - - -#define SLEEP_MODE_IDLE (0x00<<1) -#define SLEEP_MODE_PWR_DOWN (0x02<<1) -#define SLEEP_MODE_PWR_SAVE (0x03<<1) -#define SLEEP_MODE_STANDBY (0x06<<1) -#define SLEEP_MODE_EXT_STANDBY (0x07<<1) -/* --------------------------------------------------------------------------- -OSC - Oscillator --------------------------------------------------------------------------- -*/ - -/* Oscillator */ -typedef struct OSC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t XOSCCTRL; /* External Oscillator Control Register */ - register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ - register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ - register8_t PLLCTRL; /* PLL Control Register */ - register8_t DFLLCTRL; /* DFLL Control Register */ -} OSC_t; - -/* Oscillator Frequency Range */ -typedef enum OSC_FRQRANGE_enum -{ - OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ - OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ - OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ - OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ -} OSC_FRQRANGE_t; - -/* External Oscillator Selection and Startup Time */ -typedef enum OSC_XOSCSEL_enum -{ - OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ - OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ - OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ - OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ - OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ -} OSC_XOSCSEL_t; - -/* PLL Clock Source */ -typedef enum OSC_PLLSRC_enum -{ - OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ - OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ - OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ -} OSC_PLLSRC_t; - -/* 2 MHz DFLL Calibration Reference */ -typedef enum OSC_RC2MCREF_enum -{ - OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ - OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ -} OSC_RC2MCREF_t; - -/* 32 MHz DFLL Calibration Reference */ -typedef enum OSC_RC32MCREF_enum -{ - OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ - OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ - OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */ -} OSC_RC32MCREF_t; - - -/* --------------------------------------------------------------------------- -DFLL - DFLL --------------------------------------------------------------------------- -*/ - -/* DFLL */ -typedef struct DFLL_struct -{ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x01; - register8_t CALA; /* Calibration Register A */ - register8_t CALB; /* Calibration Register B */ - register8_t COMP0; /* Oscillator Compare Register 0 */ - register8_t COMP1; /* Oscillator Compare Register 1 */ - register8_t COMP2; /* Oscillator Compare Register 2 */ - register8_t reserved_0x07; -} DFLL_t; - - -/* --------------------------------------------------------------------------- -RST - Reset --------------------------------------------------------------------------- -*/ - -/* Reset */ -typedef struct RST_struct -{ - register8_t STATUS; /* Status Register */ - register8_t CTRL; /* Control Register */ -} RST_t; - - -/* --------------------------------------------------------------------------- -WDT - Watch-Dog Timer --------------------------------------------------------------------------- -*/ - -/* Watch-Dog Timer */ -typedef struct WDT_struct -{ - register8_t CTRL; /* Control */ - register8_t WINCTRL; /* Windowed Mode Control */ - register8_t STATUS; /* Status */ -} WDT_t; - -/* Period setting */ -typedef enum WDT_PER_enum -{ - WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ - WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ - WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ - WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ - WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ - WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ - WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ - WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ - WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ - WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -} WDT_PER_t; - -/* Closed window period */ -typedef enum WDT_WPER_enum -{ - WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ - WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ - WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ - WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ - WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ - WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ - WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ - WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ - WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ - WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -} WDT_WPER_t; - - -/* --------------------------------------------------------------------------- -MCU - MCU Control --------------------------------------------------------------------------- -*/ - -/* MCU Control */ -typedef struct MCU_struct -{ - register8_t DEVID0; /* Device ID byte 0 */ - register8_t DEVID1; /* Device ID byte 1 */ - register8_t DEVID2; /* Device ID byte 2 */ - register8_t REVID; /* Revision ID */ - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t ANAINIT; /* Analog Startup Delay */ - register8_t EVSYSLOCK; /* Event System Lock */ - register8_t AWEXLOCK; /* AWEX Lock */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; -} MCU_t; - - -/* --------------------------------------------------------------------------- -PMIC - Programmable Multi-level Interrupt Controller --------------------------------------------------------------------------- -*/ - -/* Programmable Multi-level Interrupt Controller */ -typedef struct PMIC_struct -{ - register8_t STATUS; /* Status Register */ - register8_t INTPRI; /* Interrupt Priority */ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x03; - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; -} PMIC_t; - - -/* --------------------------------------------------------------------------- -PORTCFG - Port Configuration --------------------------------------------------------------------------- -*/ - -/* I/O port Configuration */ -typedef struct PORTCFG_struct -{ - register8_t MPCMASK; /* Multi-pin Configuration Mask */ - register8_t reserved_0x01; - register8_t VPCTRLA; /* Virtual Port Control Register A */ - register8_t VPCTRLB; /* Virtual Port Control Register B */ - register8_t CLKEVOUT; /* Clock and Event Out Register */ - register8_t reserved_0x05; - register8_t EVOUTSEL; /* Event Output Select */ -} PORTCFG_t; - -/* Virtual Port Mapping */ -typedef enum PORTCFG_VP02MAP_enum -{ - PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ - PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ - PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ - PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ - PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ - PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ - PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ - PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ - PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ - PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ - PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ - PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ - PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ - PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ - PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ - PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ -} PORTCFG_VP02MAP_t; - -/* Virtual Port Mapping */ -typedef enum PORTCFG_VP13MAP_enum -{ - PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ - PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ - PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ - PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ - PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ - PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ - PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ - PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ - PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ - PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ - PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ - PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ - PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ - PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ - PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ - PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ -} PORTCFG_VP13MAP_t; - -/* System Clock Output Port */ -typedef enum PORTCFG_CLKOUT_enum -{ - PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ - PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ - PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ - PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */ -} PORTCFG_CLKOUT_t; - -/* Peripheral Clock Output Select */ -typedef enum PORTCFG_CLKOUTSEL_enum -{ - PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ - PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ - PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ -} PORTCFG_CLKOUTSEL_t; - -/* Event Output Port */ -typedef enum PORTCFG_EVOUT_enum -{ - PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ - PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ - PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ - PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ -} PORTCFG_EVOUT_t; - -/* Event Output Select */ -typedef enum PORTCFG_EVOUTSEL_enum -{ - PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ - PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ - PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ - PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ -} PORTCFG_EVOUTSEL_t; - - -/* --------------------------------------------------------------------------- -CRC - Cyclic Redundancy Checker --------------------------------------------------------------------------- -*/ - -/* Cyclic Redundancy Checker */ -typedef struct CRC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t reserved_0x02; - register8_t DATAIN; /* Data Input */ - register8_t CHECKSUM0; /* Checksum byte 0 */ - register8_t CHECKSUM1; /* Checksum byte 1 */ - register8_t CHECKSUM2; /* Checksum byte 2 */ - register8_t CHECKSUM3; /* Checksum byte 3 */ -} CRC_t; - -/* Reset */ -typedef enum CRC_RESET_enum -{ - CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ - CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ - CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ -} CRC_RESET_t; - -/* Input Source */ -typedef enum CRC_SOURCE_enum -{ - CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ - CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ - CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ -} CRC_SOURCE_t; - - -/* --------------------------------------------------------------------------- -EVSYS - Event System --------------------------------------------------------------------------- -*/ - -/* Event System */ -typedef struct EVSYS_struct -{ - register8_t CH0MUX; /* Event Channel 0 Multiplexer */ - register8_t CH1MUX; /* Event Channel 1 Multiplexer */ - register8_t CH2MUX; /* Event Channel 2 Multiplexer */ - register8_t CH3MUX; /* Event Channel 3 Multiplexer */ - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t CH0CTRL; /* Channel 0 Control Register */ - register8_t CH1CTRL; /* Channel 1 Control Register */ - register8_t CH2CTRL; /* Channel 2 Control Register */ - register8_t CH3CTRL; /* Channel 3 Control Register */ - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t STROBE; /* Event Strobe */ - register8_t DATA; /* Event Data */ -} EVSYS_t; - -/* Quadrature Decoder Index Recognition Mode */ -typedef enum EVSYS_QDIRM_enum -{ - EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ - EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ - EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ - EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ -} EVSYS_QDIRM_t; - -/* Digital filter coefficient */ -typedef enum EVSYS_DIGFILT_enum -{ - EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ - EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ - EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ - EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ - EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ - EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ - EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ - EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ -} EVSYS_DIGFILT_t; - -/* Event Channel multiplexer input selection */ -typedef enum EVSYS_CHMUX_enum -{ - EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ - EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ - EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ - EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */ - EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ - EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ - EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ - EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel */ - EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ - EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ - EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ - EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ - EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ - EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ - EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ - EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ - EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ - EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ - EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ - EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ - EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ - EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ - EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ - EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ - EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ - EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ - EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ - EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ - EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ - EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ - EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ - EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ - EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ - EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ - EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ - EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ - EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ - EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ - EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ - EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ - EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ - EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ - EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ - EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ - EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ - EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ - EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ - EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ - EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ - EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ - EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ - EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ - EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ - EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ - EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ - EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ - EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ - EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ - EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ - EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ - EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ - EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ - EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ - EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ - EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ - EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ - EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ - EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ - EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ - EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ - EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ - EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ - EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ - EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ - EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ - EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ - EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ - EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ - EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ - EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ - EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ - EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ - EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ - EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ - EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ - EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ - EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ - EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ - EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ - EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ - EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ - EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ - EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ - EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ - EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ - EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ - EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ - EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ - EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ - EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ -} EVSYS_CHMUX_t; - - -/* --------------------------------------------------------------------------- -NVM - Non Volatile Memory Controller --------------------------------------------------------------------------- -*/ - -/* Non-volatile Memory Controller */ -typedef struct NVM_struct -{ - register8_t ADDR0; /* Address Register 0 */ - register8_t ADDR1; /* Address Register 1 */ - register8_t ADDR2; /* Address Register 2 */ - register8_t reserved_0x03; - register8_t DATA0; /* Data Register 0 */ - register8_t DATA1; /* Data Register 1 */ - register8_t DATA2; /* Data Register 2 */ - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t CMD; /* Command */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t INTCTRL; /* Interrupt Control */ - register8_t reserved_0x0E; - register8_t STATUS; /* Status */ - register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ -} NVM_t; - -/* NVM Command */ -typedef enum NVM_CMD_enum -{ - NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ - NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ - NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ - NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ - NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ - NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ - NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ - NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ - NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ - NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ - NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ - NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ - NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ - NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ - NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ - NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ - NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ - NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ - NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ - NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ - NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ - NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ - NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ - NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ - NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ - NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ - NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ - NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ - NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ - NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ - NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ - NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ - NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ - NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ -} NVM_CMD_t; - -/* SPM ready interrupt level */ -typedef enum NVM_SPMLVL_enum -{ - NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ - NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ - NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ - NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ -} NVM_SPMLVL_t; - -/* EEPROM ready interrupt level */ -typedef enum NVM_EELVL_enum -{ - NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ - NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ - NVM_EELVL_HI_gc = (0x03<<0), /* High level */ -} NVM_EELVL_t; - -/* Boot lock bits - boot setcion */ -typedef enum NVM_BLBB_enum -{ - NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ - NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ - NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ - NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -} NVM_BLBB_t; - -/* Boot lock bits - application section */ -typedef enum NVM_BLBA_enum -{ - NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ - NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ - NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ - NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -} NVM_BLBA_t; - -/* Boot lock bits - application table section */ -typedef enum NVM_BLBAT_enum -{ - NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ - NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ - NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ - NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -} NVM_BLBAT_t; - -/* Lock bits */ -typedef enum NVM_LB_enum -{ - NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ - NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ - NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -} NVM_LB_t; - - -/* --------------------------------------------------------------------------- -ADC - Analog/Digital Converter --------------------------------------------------------------------------- -*/ - -/* ADC Channel */ -typedef struct ADC_CH_struct -{ - register8_t CTRL; /* Control Register */ - register8_t MUXCTRL; /* MUX Control */ - register8_t INTCTRL; /* Channel Interrupt Control Register */ - register8_t INTFLAGS; /* Interrupt Flags */ - _WORDREGISTER(RES); /* Channel Result */ - register8_t SCAN; /* Input Channel Scan */ - register8_t reserved_0x07; -} ADC_CH_t; - - -/* Analog-to-Digital Converter */ -typedef struct ADC_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t REFCTRL; /* Reference Control */ - register8_t EVCTRL; /* Event Control */ - register8_t PRESCALER; /* Clock Prescaler */ - register8_t reserved_0x05; - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t TEMP; /* Temporary Register */ - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - _WORDREGISTER(CAL); /* Calibration Value */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - _WORDREGISTER(CH0RES); /* Channel 0 Result */ - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - _WORDREGISTER(CMP); /* Compare Value */ - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - ADC_CH_t CH0; /* ADC Channel 0 */ -} ADC_t; - -/* Current Limitation */ -typedef enum ADC_CURRLIMIT_enum -{ - ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ - ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 250ksps max sampling rate */ - ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ - ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 50ksps max sampling rate */ -} ADC_CURRLIMIT_t; - -/* Positive input multiplexer selection */ -typedef enum ADC_CH_MUXPOS_enum -{ - ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ - ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ - ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ - ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ - ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ - ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ - ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ - ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ - ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ - ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ - ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ - ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ - ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ - ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ - ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ - ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ -} ADC_CH_MUXPOS_t; - -/* Internal input multiplexer selections */ -typedef enum ADC_CH_MUXINT_enum -{ - ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ - ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ - ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ -} ADC_CH_MUXINT_t; - -/* Negative input multiplexer selection */ -typedef enum ADC_CH_MUXNEG_enum -{ - ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ - ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ - ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ - ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ - ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */ - ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */ - ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */ - ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */ -} ADC_CH_MUXNEG_t; - -/* Input mode */ -typedef enum ADC_CH_INPUTMODE_enum -{ - ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ - ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ - ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ - ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ -} ADC_CH_INPUTMODE_t; - -/* Gain factor */ -typedef enum ADC_CH_GAIN_enum -{ - ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ - ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ - ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ - ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ - ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ - ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ - ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ - ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ -} ADC_CH_GAIN_t; - -/* Conversion result resolution */ -typedef enum ADC_RESOLUTION_enum -{ - ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ - ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ - ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ -} ADC_RESOLUTION_t; - -/* Voltage reference selection */ -typedef enum ADC_REFSEL_enum -{ - ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ - ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ - ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ - ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ - ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ -} ADC_REFSEL_t; - -/* Event channel input selection */ -typedef enum ADC_EVSEL_enum -{ - ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */ - ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */ - ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */ - ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */ -} ADC_EVSEL_t; - -/* Event action selection */ -typedef enum ADC_EVACT_enum -{ - ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ - ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ - ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ -} ADC_EVACT_t; - -/* Interupt mode */ -typedef enum ADC_CH_INTMODE_enum -{ - ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ - ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ - ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ -} ADC_CH_INTMODE_t; - -/* Interrupt level */ -typedef enum ADC_CH_INTLVL_enum -{ - ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ - ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ - ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ -} ADC_CH_INTLVL_t; - -/* Clock prescaler */ -typedef enum ADC_PRESCALER_enum -{ - ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ - ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ - ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ - ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ - ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ - ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ - ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ - ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ -} ADC_PRESCALER_t; - - -/* --------------------------------------------------------------------------- -AC - Analog Comparator --------------------------------------------------------------------------- -*/ - -/* Analog Comparator */ -typedef struct AC_struct -{ - register8_t AC0CTRL; /* Analog Comparator 0 Control */ - register8_t AC1CTRL; /* Analog Comparator 1 Control */ - register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ - register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t WINCTRL; /* Window Mode Control */ - register8_t STATUS; /* Status */ -} AC_t; - -/* Interrupt mode */ -typedef enum AC_INTMODE_enum -{ - AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ - AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ - AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ -} AC_INTMODE_t; - -/* Interrupt level */ -typedef enum AC_INTLVL_enum -{ - AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ - AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ - AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ - AC_INTLVL_HI_gc = (0x03<<4), /* High level */ -} AC_INTLVL_t; - -/* Hysteresis mode selection */ -typedef enum AC_HYSMODE_enum -{ - AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ - AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ - AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ -} AC_HYSMODE_t; - -/* Positive input multiplexer selection */ -typedef enum AC_MUXPOS_enum -{ - AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ - AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ - AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ - AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ - AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ - AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ - AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ -} AC_MUXPOS_t; - -/* Negative input multiplexer selection */ -typedef enum AC_MUXNEG_enum -{ - AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ - AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ - AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ - AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ - AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ - AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ - AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ -} AC_MUXNEG_t; - -/* Windows interrupt mode */ -typedef enum AC_WINTMODE_enum -{ - AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ - AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ - AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ - AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ -} AC_WINTMODE_t; - -/* Window interrupt level */ -typedef enum AC_WINTLVL_enum -{ - AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ - AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ - AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ -} AC_WINTLVL_t; - -/* Window mode state */ -typedef enum AC_WSTATE_enum -{ - AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ - AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ - AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ -} AC_WSTATE_t; - - -/* --------------------------------------------------------------------------- -RTC - Real-Time Counter --------------------------------------------------------------------------- -*/ - -/* Real-Time Counter */ -typedef struct RTC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t TEMP; /* Temporary register */ - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - _WORDREGISTER(CNT); /* Count Register */ - _WORDREGISTER(PER); /* Period Register */ - _WORDREGISTER(COMP); /* Compare Register */ -} RTC_t; - -/* Prescaler Factor */ -typedef enum RTC_PRESCALER_enum -{ - RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ - RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ - RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ - RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ - RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ - RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ - RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ - RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ -} RTC_PRESCALER_t; - -/* Compare Interrupt level */ -typedef enum RTC_COMPINTLVL_enum -{ - RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ - RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ -} RTC_COMPINTLVL_t; - -/* Overflow Interrupt level */ -typedef enum RTC_OVFINTLVL_enum -{ - RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} RTC_OVFINTLVL_t; - - -/* --------------------------------------------------------------------------- -TWI - Two-Wire Interface --------------------------------------------------------------------------- -*/ - -/* */ -typedef struct TWI_MASTER_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t STATUS; /* Status Register */ - register8_t BAUD; /* Baurd Rate Control Register */ - register8_t ADDR; /* Address Register */ - register8_t DATA; /* Data Register */ -} TWI_MASTER_t; - - -/* */ -typedef struct TWI_SLAVE_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t STATUS; /* Status Register */ - register8_t ADDR; /* Address Register */ - register8_t DATA; /* Data Register */ - register8_t ADDRMASK; /* Address Mask Register */ -} TWI_SLAVE_t; - - -/* Two-Wire Interface */ -typedef struct TWI_struct -{ - register8_t CTRL; /* TWI Common Control Register */ - TWI_MASTER_t MASTER; /* TWI master module */ - TWI_SLAVE_t SLAVE; /* TWI slave module */ -} TWI_t; - -/* SDA Hold Time */ -typedef enum TWI_SDAHOLD_enum -{ - TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */ - TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */ - TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */ - TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */ -} TWI_SDAHOLD_t; - -/* Master Interrupt Level */ -typedef enum TWI_MASTER_INTLVL_enum -{ - TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ - TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ -} TWI_MASTER_INTLVL_t; - -/* Inactive Timeout */ -typedef enum TWI_MASTER_TIMEOUT_enum -{ - TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ - TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ - TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ - TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ -} TWI_MASTER_TIMEOUT_t; - -/* Master Command */ -typedef enum TWI_MASTER_CMD_enum -{ - TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ - TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ - TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ -} TWI_MASTER_CMD_t; - -/* Master Bus State */ -typedef enum TWI_MASTER_BUSSTATE_enum -{ - TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ - TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ - TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ - TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ -} TWI_MASTER_BUSSTATE_t; - -/* Slave Interrupt Level */ -typedef enum TWI_SLAVE_INTLVL_enum -{ - TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ - TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ -} TWI_SLAVE_INTLVL_t; - -/* Slave Command */ -typedef enum TWI_SLAVE_CMD_enum -{ - TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ - TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ -} TWI_SLAVE_CMD_t; - - -/* --------------------------------------------------------------------------- -USB - USB --------------------------------------------------------------------------- -*/ - -/* USB Endpoint */ -typedef struct USB_EP_struct -{ - register8_t STATUS; /* Endpoint Status */ - register8_t CTRL; /* Endpoint Control */ - _WORDREGISTER(CNT); /* USB Endpoint Counter */ - _WORDREGISTER(DATAPTR); /* Data Pointer */ - _WORDREGISTER(AUXDATA); /* Auxiliary Data */ -} USB_EP_t; - - -/* Universal Serial Bus */ -typedef struct USB_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t STATUS; /* Status Register */ - register8_t ADDR; /* Address Register */ - register8_t FIFOWP; /* FIFO Write Pointer Register */ - register8_t FIFORP; /* FIFO Read Pointer Register */ - _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */ - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */ - register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */ - register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */ - register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t reserved_0x20; - register8_t reserved_0x21; - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - register8_t reserved_0x26; - register8_t reserved_0x27; - register8_t reserved_0x28; - register8_t reserved_0x29; - register8_t reserved_0x2A; - register8_t reserved_0x2B; - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t reserved_0x2E; - register8_t reserved_0x2F; - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - register8_t reserved_0x36; - register8_t reserved_0x37; - register8_t reserved_0x38; - register8_t reserved_0x39; - register8_t CAL0; /* Calibration Byte 0 */ - register8_t CAL1; /* Calibration Byte 1 */ -} USB_t; - - -/* USB Endpoint Table */ -typedef struct USB_EP_TABLE_struct -{ - USB_EP_t EP0OUT; /* Endpoint 0 */ - USB_EP_t EP0IN; /* Endpoint 0 */ - USB_EP_t EP1OUT; /* Endpoint 1 */ - USB_EP_t EP1IN; /* Endpoint 1 */ - USB_EP_t EP2OUT; /* Endpoint 2 */ - USB_EP_t EP2IN; /* Endpoint 2 */ - USB_EP_t EP3OUT; /* Endpoint 3 */ - USB_EP_t EP3IN; /* Endpoint 3 */ - USB_EP_t EP4OUT; /* Endpoint 4 */ - USB_EP_t EP4IN; /* Endpoint 4 */ - USB_EP_t EP5OUT; /* Endpoint 5 */ - USB_EP_t EP5IN; /* Endpoint 5 */ - USB_EP_t EP6OUT; /* Endpoint 6 */ - USB_EP_t EP6IN; /* Endpoint 6 */ - USB_EP_t EP7OUT; /* Endpoint 7 */ - USB_EP_t EP7IN; /* Endpoint 7 */ - USB_EP_t EP8OUT; /* Endpoint 8 */ - USB_EP_t EP8IN; /* Endpoint 8 */ - USB_EP_t EP9OUT; /* Endpoint 9 */ - USB_EP_t EP9IN; /* Endpoint 9 */ - USB_EP_t EP10OUT; /* Endpoint 10 */ - USB_EP_t EP10IN; /* Endpoint 10 */ - USB_EP_t EP11OUT; /* Endpoint 11 */ - USB_EP_t EP11IN; /* Endpoint 11 */ - USB_EP_t EP12OUT; /* Endpoint 12 */ - USB_EP_t EP12IN; /* Endpoint 12 */ - USB_EP_t EP13OUT; /* Endpoint 13 */ - USB_EP_t EP13IN; /* Endpoint 13 */ - USB_EP_t EP14OUT; /* Endpoint 14 */ - USB_EP_t EP14IN; /* Endpoint 14 */ - USB_EP_t EP15OUT; /* Endpoint 15 */ - USB_EP_t EP15IN; /* Endpoint 15 */ - register8_t reserved_0x100; - register8_t reserved_0x101; - register8_t reserved_0x102; - register8_t reserved_0x103; - register8_t reserved_0x104; - register8_t reserved_0x105; - register8_t reserved_0x106; - register8_t reserved_0x107; - register8_t reserved_0x108; - register8_t reserved_0x109; - register8_t reserved_0x10A; - register8_t reserved_0x10B; - register8_t reserved_0x10C; - register8_t reserved_0x10D; - register8_t reserved_0x10E; - register8_t reserved_0x10F; - register8_t FRAMENUML; /* Frame Number Low Byte */ - register8_t FRAMENUMH; /* Frame Number High Byte */ -} USB_EP_TABLE_t; - -/* Interrupt level */ -typedef enum USB_INTLVL_enum -{ - USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - USB_INTLVL_LO_gc = (0x01<<0), /* Low level */ - USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */ - USB_INTLVL_HI_gc = (0x03<<0), /* High level */ -} USB_INTLVL_t; - -/* USB Endpoint Type */ -typedef enum USB_EP_TYPE_enum -{ - USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */ - USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */ - USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */ - USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */ -} USB_EP_TYPE_t; - -/* USB Endpoint Buffersize */ -typedef enum USB_EP_BUFSIZE_enum -{ - USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */ - USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */ - USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */ - USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */ - USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */ - USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */ - USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */ - USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */ -} USB_EP_BUFSIZE_t; - - -/* --------------------------------------------------------------------------- -PORT - I/O Port Configuration --------------------------------------------------------------------------- -*/ - -/* I/O Ports */ -typedef struct PORT_struct -{ - register8_t DIR; /* I/O Port Data Direction */ - register8_t DIRSET; /* I/O Port Data Direction Set */ - register8_t DIRCLR; /* I/O Port Data Direction Clear */ - register8_t DIRTGL; /* I/O Port Data Direction Toggle */ - register8_t OUT; /* I/O Port Output */ - register8_t OUTSET; /* I/O Port Output Set */ - register8_t OUTCLR; /* I/O Port Output Clear */ - register8_t OUTTGL; /* I/O Port Output Toggle */ - register8_t IN; /* I/O port Input */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INT0MASK; /* Port Interrupt 0 Mask */ - register8_t INT1MASK; /* Port Interrupt 1 Mask */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t REMAP; /* I/O Port Pin Remap Register */ - register8_t reserved_0x0F; - register8_t PIN0CTRL; /* Pin 0 Control Register */ - register8_t PIN1CTRL; /* Pin 1 Control Register */ - register8_t PIN2CTRL; /* Pin 2 Control Register */ - register8_t PIN3CTRL; /* Pin 3 Control Register */ - register8_t PIN4CTRL; /* Pin 4 Control Register */ - register8_t PIN5CTRL; /* Pin 5 Control Register */ - register8_t PIN6CTRL; /* Pin 6 Control Register */ - register8_t PIN7CTRL; /* Pin 7 Control Register */ -} PORT_t; - -/* Port Interrupt 0 Level */ -typedef enum PORT_INT0LVL_enum -{ - PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ - PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ - PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ -} PORT_INT0LVL_t; - -/* Port Interrupt 1 Level */ -typedef enum PORT_INT1LVL_enum -{ - PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ - PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ - PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ -} PORT_INT1LVL_t; - -/* Output/Pull Configuration */ -typedef enum PORT_OPC_enum -{ - PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ - PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ - PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ - PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ - PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ - PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ - PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ - PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ -} PORT_OPC_t; - -/* Input/Sense Configuration */ -typedef enum PORT_ISC_enum -{ - PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ - PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ - PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ - PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ - PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ -} PORT_ISC_t; - - -/* --------------------------------------------------------------------------- -TC - 16-bit Timer/Counter With PWM --------------------------------------------------------------------------- -*/ - -/* 16-bit Timer/Counter 0 */ -typedef struct TC0_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t CTRLFCLR; /* Control Register F Clear */ - register8_t CTRLFSET; /* Control Register F Set */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G Set */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - _WORDREGISTER(CNT); /* Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CCA); /* Compare or Capture A */ - _WORDREGISTER(CCB); /* Compare or Capture B */ - _WORDREGISTER(CCC); /* Compare or Capture C */ - _WORDREGISTER(CCD); /* Compare or Capture D */ - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - _WORDREGISTER(PERBUF); /* Period Buffer */ - _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ - _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ - _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ - _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ -} TC0_t; - - -/* 16-bit Timer/Counter 1 */ -typedef struct TC1_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t CTRLFCLR; /* Control Register F Clear */ - register8_t CTRLFSET; /* Control Register F Set */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G Set */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - _WORDREGISTER(CNT); /* Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CCA); /* Compare or Capture A */ - _WORDREGISTER(CCB); /* Compare or Capture B */ - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t reserved_0x2E; - register8_t reserved_0x2F; - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - _WORDREGISTER(PERBUF); /* Period Buffer */ - _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ - _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ -} TC1_t; - -/* Clock Selection */ -typedef enum TC_CLKSEL_enum -{ - TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ - TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ - TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ - TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ - TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ - TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ - TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ - TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ - TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ - TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ - TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ -} TC_CLKSEL_t; - -/* Waveform Generation Mode */ -typedef enum TC_WGMODE_enum -{ - TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ - TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ - TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ - TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ - TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ - TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ - TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ - TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ - TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ - TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ -} TC_WGMODE_t; - -/* Byte Mode */ -typedef enum TC_BYTEM_enum -{ - TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ - TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ - TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */ -} TC_BYTEM_t; - -/* Event Action */ -typedef enum TC_EVACT_enum -{ - TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ - TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ - TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ - TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ - TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ - TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ - TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ -} TC_EVACT_t; - -/* Event Selection */ -typedef enum TC_EVSEL_enum -{ - TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ - TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ - TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ - TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ -} TC_EVSEL_t; - -/* Error Interrupt Level */ -typedef enum TC_ERRINTLVL_enum -{ - TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC_ERRINTLVL_t; - -/* Overflow Interrupt Level */ -typedef enum TC_OVFINTLVL_enum -{ - TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC_OVFINTLVL_t; - -/* Compare or Capture D Interrupt Level */ -typedef enum TC_CCDINTLVL_enum -{ - TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ - TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ -} TC_CCDINTLVL_t; - -/* Compare or Capture C Interrupt Level */ -typedef enum TC_CCCINTLVL_enum -{ - TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} TC_CCCINTLVL_t; - -/* Compare or Capture B Interrupt Level */ -typedef enum TC_CCBINTLVL_enum -{ - TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC_CCBINTLVL_t; - -/* Compare or Capture A Interrupt Level */ -typedef enum TC_CCAINTLVL_enum -{ - TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC_CCAINTLVL_t; - -/* Timer/Counter Command */ -typedef enum TC_CMD_enum -{ - TC_CMD_NONE_gc = (0x00<<2), /* No Command */ - TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ - TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ - TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -} TC_CMD_t; - - -/* --------------------------------------------------------------------------- -TC2 - 16-bit Timer/Counter type 2 --------------------------------------------------------------------------- -*/ - -/* 16-bit Timer/Counter type 2 */ -typedef struct TC2_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t reserved_0x03; - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t reserved_0x08; - register8_t CTRLF; /* Control Register F */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t LCNT; /* Low Byte Count */ - register8_t HCNT; /* High Byte Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - register8_t LPER; /* Low Byte Period */ - register8_t HPER; /* High Byte Period */ - register8_t LCMPA; /* Low Byte Compare A */ - register8_t HCMPA; /* High Byte Compare A */ - register8_t LCMPB; /* Low Byte Compare B */ - register8_t HCMPB; /* High Byte Compare B */ - register8_t LCMPC; /* Low Byte Compare C */ - register8_t HCMPC; /* High Byte Compare C */ - register8_t LCMPD; /* Low Byte Compare D */ - register8_t HCMPD; /* High Byte Compare D */ -} TC2_t; - -/* Clock Selection */ -typedef enum TC2_CLKSEL_enum -{ - TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ - TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ - TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ - TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ - TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ - TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ - TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ - TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ - TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ - TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ - TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ -} TC2_CLKSEL_t; - -/* Byte Mode */ -typedef enum TC2_BYTEM_enum -{ - TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ - TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */ - TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ -} TC2_BYTEM_t; - -/* High Byte Underflow Interrupt Level */ -typedef enum TC2_HUNFINTLVL_enum -{ - TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC2_HUNFINTLVL_t; - -/* Low Byte Underflow Interrupt Level */ -typedef enum TC2_LUNFINTLVL_enum -{ - TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC2_LUNFINTLVL_t; - -/* Low Byte Compare D Interrupt Level */ -typedef enum TC2_LCMPDINTLVL_enum -{ - TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */ - TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */ -} TC2_LCMPDINTLVL_t; - -/* Low Byte Compare C Interrupt Level */ -typedef enum TC2_LCMPCINTLVL_enum -{ - TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} TC2_LCMPCINTLVL_t; - -/* Low Byte Compare B Interrupt Level */ -typedef enum TC2_LCMPBINTLVL_enum -{ - TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC2_LCMPBINTLVL_t; - -/* Low Byte Compare A Interrupt Level */ -typedef enum TC2_LCMPAINTLVL_enum -{ - TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC2_LCMPAINTLVL_t; - -/* Timer/Counter Command */ -typedef enum TC2_CMD_enum -{ - TC2_CMD_NONE_gc = (0x00<<2), /* No Command */ - TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ - TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -} TC2_CMD_t; - -/* Timer/Counter Command */ -typedef enum TC2_CMDEN_enum -{ - TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */ - TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */ - TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */ -} TC2_CMDEN_t; - - -/* --------------------------------------------------------------------------- -AWEX - Timer/Counter Advanced Waveform Extension --------------------------------------------------------------------------- -*/ - -/* Advanced Waveform Extension */ -typedef struct AWEX_struct -{ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x01; - register8_t FDEMASK; /* Fault Detection Event Mask */ - register8_t FDCTRL; /* Fault Detection Control Register */ - register8_t STATUS; /* Status Register */ - register8_t STATUSSET; /* Status Set Register */ - register8_t DTBOTH; /* Dead Time Both Sides */ - register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ - register8_t DTLS; /* Dead Time Low Side */ - register8_t DTHS; /* Dead Time High Side */ - register8_t DTLSBUF; /* Dead Time Low Side Buffer */ - register8_t DTHSBUF; /* Dead Time High Side Buffer */ - register8_t OUTOVEN; /* Output Override Enable */ -} AWEX_t; - -/* Fault Detect Action */ -typedef enum AWEX_FDACT_enum -{ - AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ - AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ - AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ -} AWEX_FDACT_t; - - -/* --------------------------------------------------------------------------- -HIRES - Timer/Counter High-Resolution Extension --------------------------------------------------------------------------- -*/ - -/* High-Resolution Extension */ -typedef struct HIRES_struct -{ - register8_t CTRLA; /* Control Register */ -} HIRES_t; - -/* High Resolution Enable */ -typedef enum HIRES_HREN_enum -{ - HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ - HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ - HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ - HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ -} HIRES_HREN_t; - - -/* --------------------------------------------------------------------------- -USART - Universal Asynchronous Receiver-Transmitter --------------------------------------------------------------------------- -*/ - -/* Universal Synchronous/Asynchronous Receiver/Transmitter */ -typedef struct USART_struct -{ - register8_t DATA; /* Data Register */ - register8_t STATUS; /* Status Register */ - register8_t reserved_0x02; - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t BAUDCTRLA; /* Baud Rate Control Register A */ - register8_t BAUDCTRLB; /* Baud Rate Control Register B */ -} USART_t; - -/* Receive Complete Interrupt level */ -typedef enum USART_RXCINTLVL_enum -{ - USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} USART_RXCINTLVL_t; - -/* Transmit Complete Interrupt level */ -typedef enum USART_TXCINTLVL_enum -{ - USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ - USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ -} USART_TXCINTLVL_t; - -/* Data Register Empty Interrupt level */ -typedef enum USART_DREINTLVL_enum -{ - USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ - USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ -} USART_DREINTLVL_t; - -/* Character Size */ -typedef enum USART_CHSIZE_enum -{ - USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ - USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ - USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ - USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ - USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ -} USART_CHSIZE_t; - -/* Communication Mode */ -typedef enum USART_CMODE_enum -{ - USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ - USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ - USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ - USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ -} USART_CMODE_t; - -/* Parity Mode */ -typedef enum USART_PMODE_enum -{ - USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ - USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ - USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ -} USART_PMODE_t; - - -/* --------------------------------------------------------------------------- -SPI - Serial Peripheral Interface --------------------------------------------------------------------------- -*/ - -/* Serial Peripheral Interface */ -typedef struct SPI_struct -{ - register8_t CTRL; /* Control Register */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t STATUS; /* Status Register */ - register8_t DATA; /* Data Register */ -} SPI_t; - -/* SPI Mode */ -typedef enum SPI_MODE_enum -{ - SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ - SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ - SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ - SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ -} SPI_MODE_t; - -/* Prescaler setting */ -typedef enum SPI_PRESCALER_enum -{ - SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ - SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ - SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ - SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ -} SPI_PRESCALER_t; - -/* Interrupt level */ -typedef enum SPI_INTLVL_enum -{ - SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ - SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ - SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ -} SPI_INTLVL_t; - - -/* --------------------------------------------------------------------------- -IRCOM - IR Communication Module --------------------------------------------------------------------------- -*/ - -/* IR Communication Module */ -typedef struct IRCOM_struct -{ - register8_t CTRL; /* Control Register */ - register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ - register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ -} IRCOM_t; - -/* Event channel selection */ -typedef enum IRDA_EVSEL_enum -{ - IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ - IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ - IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ - IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ - IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ -} IRDA_EVSEL_t; - - -/* --------------------------------------------------------------------------- -FUSE - Fuses and Lockbits --------------------------------------------------------------------------- -*/ - -/* Fuses */ -typedef struct NVM_FUSES_struct -{ - register8_t reserved_0x00; - register8_t FUSEBYTE1; /* Watchdog Configuration */ - register8_t FUSEBYTE2; /* Reset Configuration */ - register8_t reserved_0x03; - register8_t FUSEBYTE4; /* Start-up Configuration */ - register8_t FUSEBYTE5; /* EESAVE and BOD Level */ -} NVM_FUSES_t; - -/* Boot Loader Section Reset Vector */ -typedef enum BOOTRST_enum -{ - BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ - BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ -} BOOTRST_t; - -/* Timer Oscillator pin location */ -typedef enum TOSCSEL_enum -{ - TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ - TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ -} TOSCSEL_t; - -/* BOD operation */ -typedef enum BOD_enum -{ - BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ - BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ - BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ -} BOD_t; - -/* BOD operation */ -typedef enum BODACT_enum -{ - BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ - BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ - BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ -} BODACT_t; - -/* Watchdog (Window) Timeout Period */ -typedef enum WD_enum -{ - WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ - WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ - WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ - WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ - WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ - WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ - WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ - WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ - WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ - WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ - WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ -} WD_t; - -/* Watchdog (Window) Timeout Period */ -typedef enum WDP_enum -{ - WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ - WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ - WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ - WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ - WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ - WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ - WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ - WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ - WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ - WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ - WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ -} WDP_t; - -/* Start-up Time */ -typedef enum SUT_enum -{ - SUT_0MS_gc = (0x03<<2), /* 0 ms */ - SUT_4MS_gc = (0x01<<2), /* 4 ms */ - SUT_64MS_gc = (0x00<<2), /* 64 ms */ -} SUT_t; - -/* Brownout Detection Voltage Level */ -typedef enum BODLVL_enum -{ - BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ - BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ - BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ - BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ - BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ - BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ - BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ - BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ -} BODLVL_t; - - -/* --------------------------------------------------------------------------- -LOCKBIT - Fuses and Lockbits --------------------------------------------------------------------------- -*/ - -/* Lock Bits */ -typedef struct NVM_LOCKBITS_struct -{ - register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ -} NVM_LOCKBITS_t; - -/* Boot lock bits - boot setcion */ -typedef enum FUSE_BLBB_enum -{ - FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ - FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ - FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ - FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -} FUSE_BLBB_t; - -/* Boot lock bits - application section */ -typedef enum FUSE_BLBA_enum -{ - FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ - FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ - FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ - FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -} FUSE_BLBA_t; - -/* Boot lock bits - application table section */ -typedef enum FUSE_BLBAT_enum -{ - FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ - FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ - FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ - FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -} FUSE_BLBAT_t; - -/* Lock bits */ -typedef enum FUSE_LB_enum -{ - FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ - FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ - FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -} FUSE_LB_t; - - -/* --------------------------------------------------------------------------- -SIGROW - Signature Row --------------------------------------------------------------------------- -*/ - -/* Production Signatures */ -typedef struct NVM_PROD_SIGNATURES_struct -{ - register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ - register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ - register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ - register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ - register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ - register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ - register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ - register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ - register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ - register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t WAFNUM; /* Wafer Number */ - register8_t reserved_0x11; - register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ - register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ - register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ - register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t USBCAL0; /* USB Calibration Byte 0 */ - register8_t USBCAL1; /* USB Calibration Byte 1 */ - register8_t USBRCOSC; /* USB RCOSC Calibration Value B */ - register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */ - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ - register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - register8_t reserved_0x26; - register8_t reserved_0x27; - register8_t reserved_0x28; - register8_t reserved_0x29; - register8_t reserved_0x2A; - register8_t reserved_0x2B; - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ - register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - register8_t reserved_0x36; - register8_t reserved_0x37; - register8_t reserved_0x38; - register8_t reserved_0x39; - register8_t reserved_0x3A; - register8_t reserved_0x3B; - register8_t reserved_0x3C; - register8_t reserved_0x3D; - register8_t reserved_0x3E; - register8_t reserved_0x3F; -} NVM_PROD_SIGNATURES_t; - -/* -========================================================================== -IO Module Instances. Mapped to memory. -========================================================================== -*/ - -#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ -#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ -#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ -#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ -#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ -#define CLK (*(CLK_t *) 0x0040) /* Clock System */ -#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ -#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ -#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ -#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ -#define PR (*(PR_t *) 0x0070) /* Power Reduction */ -#define RST (*(RST_t *) 0x0078) /* Reset */ -#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ -#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ -#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ -#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ -#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ -#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ -#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ -#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ -#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ -#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ -#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ -#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */ -#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */ -#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ -#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ -#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ -#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ -#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ -#define PORTF (*(PORT_t *) 0x06A0) /* I/O Ports */ -#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ -#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ -#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */ -#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ -#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ -#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ -#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ -#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ -#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */ -#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */ -#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */ -#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ -#define TCE2 (*(TC2_t *) 0x0A00) /* 16-bit Timer/Counter type 2 */ -#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define TCF0 (*(TC0_t *) 0x0B00) /* 16-bit Timer/Counter 0 */ -#define TCF2 (*(TC2_t *) 0x0B00) /* 16-bit Timer/Counter type 2 */ - - -#endif /* !defined (__ASSEMBLER__) */ - - -/* ========== Flattened fully qualified IO register names ========== */ - -/* GPIO - General Purpose IO Registers */ -#define GPIO_GPIOR0 _SFR_MEM8(0x0000) -#define GPIO_GPIOR1 _SFR_MEM8(0x0001) -#define GPIO_GPIOR2 _SFR_MEM8(0x0002) -#define GPIO_GPIOR3 _SFR_MEM8(0x0003) - -/* Deprecated */ -#define GPIO_GPIO0 _SFR_MEM8(0x0000) -#define GPIO_GPIO1 _SFR_MEM8(0x0001) -#define GPIO_GPIO2 _SFR_MEM8(0x0002) -#define GPIO_GPIO3 _SFR_MEM8(0x0003) - -/* NVM_FUSES - Fuses */ -#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) -#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) -#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) -#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) - -/* NVM_LOCKBITS - Lock Bits */ -#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) - -/* NVM_PROD_SIGNATURES - Production Signatures */ -#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) -#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) -#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) -#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) -#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) -#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) -#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) -#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) -#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) -#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) -#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) -#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) -#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) -#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) -#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) -#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) -#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A) -#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B) -#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C) -#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D) -#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) -#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) -#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) -#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) - -/* VPORT - Virtual Port */ -#define VPORT0_DIR _SFR_MEM8(0x0010) -#define VPORT0_OUT _SFR_MEM8(0x0011) -#define VPORT0_IN _SFR_MEM8(0x0012) -#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) - -/* VPORT - Virtual Port */ -#define VPORT1_DIR _SFR_MEM8(0x0014) -#define VPORT1_OUT _SFR_MEM8(0x0015) -#define VPORT1_IN _SFR_MEM8(0x0016) -#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) - -/* VPORT - Virtual Port */ -#define VPORT2_DIR _SFR_MEM8(0x0018) -#define VPORT2_OUT _SFR_MEM8(0x0019) -#define VPORT2_IN _SFR_MEM8(0x001A) -#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) - -/* VPORT - Virtual Port */ -#define VPORT3_DIR _SFR_MEM8(0x001C) -#define VPORT3_OUT _SFR_MEM8(0x001D) -#define VPORT3_IN _SFR_MEM8(0x001E) -#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) - -/* OCD - On-Chip Debug System */ -#define OCD_OCDR0 _SFR_MEM8(0x002E) -#define OCD_OCDR1 _SFR_MEM8(0x002F) - -/* CPU - CPU registers */ -#define CPU_CCP _SFR_MEM8(0x0034) -#define CPU_RAMPD _SFR_MEM8(0x0038) -#define CPU_RAMPX _SFR_MEM8(0x0039) -#define CPU_RAMPY _SFR_MEM8(0x003A) -#define CPU_RAMPZ _SFR_MEM8(0x003B) -#define CPU_EIND _SFR_MEM8(0x003C) -#define CPU_SPL _SFR_MEM8(0x003D) -#define CPU_SPH _SFR_MEM8(0x003E) -#define CPU_SREG _SFR_MEM8(0x003F) - -/* CLK - Clock System */ -#define CLK_CTRL _SFR_MEM8(0x0040) -#define CLK_PSCTRL _SFR_MEM8(0x0041) -#define CLK_LOCK _SFR_MEM8(0x0042) -#define CLK_RTCCTRL _SFR_MEM8(0x0043) -#define CLK_USBCTRL _SFR_MEM8(0x0044) - -/* SLEEP - Sleep Controller */ -#define SLEEP_CTRL _SFR_MEM8(0x0048) - -/* OSC - Oscillator */ -#define OSC_CTRL _SFR_MEM8(0x0050) -#define OSC_STATUS _SFR_MEM8(0x0051) -#define OSC_XOSCCTRL _SFR_MEM8(0x0052) -#define OSC_XOSCFAIL _SFR_MEM8(0x0053) -#define OSC_RC32KCAL _SFR_MEM8(0x0054) -#define OSC_PLLCTRL _SFR_MEM8(0x0055) -#define OSC_DFLLCTRL _SFR_MEM8(0x0056) - -/* DFLL - DFLL */ -#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) -#define DFLLRC32M_CALA _SFR_MEM8(0x0062) -#define DFLLRC32M_CALB _SFR_MEM8(0x0063) -#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) -#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) -#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) - -/* DFLL - DFLL */ -#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) -#define DFLLRC2M_CALA _SFR_MEM8(0x006A) -#define DFLLRC2M_CALB _SFR_MEM8(0x006B) -#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) -#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) -#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) - -/* PR - Power Reduction */ -#define PR_PRGEN _SFR_MEM8(0x0070) -#define PR_PRPA _SFR_MEM8(0x0071) -#define PR_PRPC _SFR_MEM8(0x0073) -#define PR_PRPD _SFR_MEM8(0x0074) -#define PR_PRPE _SFR_MEM8(0x0075) -#define PR_PRPF _SFR_MEM8(0x0076) - -/* RST - Reset */ -#define RST_STATUS _SFR_MEM8(0x0078) -#define RST_CTRL _SFR_MEM8(0x0079) - -/* WDT - Watch-Dog Timer */ -#define WDT_CTRL _SFR_MEM8(0x0080) -#define WDT_WINCTRL _SFR_MEM8(0x0081) -#define WDT_STATUS _SFR_MEM8(0x0082) - -/* MCU - MCU Control */ -#define MCU_DEVID0 _SFR_MEM8(0x0090) -#define MCU_DEVID1 _SFR_MEM8(0x0091) -#define MCU_DEVID2 _SFR_MEM8(0x0092) -#define MCU_REVID _SFR_MEM8(0x0093) -#define MCU_ANAINIT _SFR_MEM8(0x0097) -#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) -#define MCU_AWEXLOCK _SFR_MEM8(0x0099) - -/* PMIC - Programmable Multi-level Interrupt Controller */ -#define PMIC_STATUS _SFR_MEM8(0x00A0) -#define PMIC_INTPRI _SFR_MEM8(0x00A1) -#define PMIC_CTRL _SFR_MEM8(0x00A2) - -/* PORTCFG - I/O port Configuration */ -#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) -#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) -#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) -#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) -#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) - -/* CRC - Cyclic Redundancy Checker */ -#define CRC_CTRL _SFR_MEM8(0x00D0) -#define CRC_STATUS _SFR_MEM8(0x00D1) -#define CRC_DATAIN _SFR_MEM8(0x00D3) -#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) -#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) -#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) -#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) - -/* EVSYS - Event System */ -#define EVSYS_CH0MUX _SFR_MEM8(0x0180) -#define EVSYS_CH1MUX _SFR_MEM8(0x0181) -#define EVSYS_CH2MUX _SFR_MEM8(0x0182) -#define EVSYS_CH3MUX _SFR_MEM8(0x0183) -#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) -#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) -#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) -#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) -#define EVSYS_STROBE _SFR_MEM8(0x0190) -#define EVSYS_DATA _SFR_MEM8(0x0191) - -/* NVM - Non-volatile Memory Controller */ -#define NVM_ADDR0 _SFR_MEM8(0x01C0) -#define NVM_ADDR1 _SFR_MEM8(0x01C1) -#define NVM_ADDR2 _SFR_MEM8(0x01C2) -#define NVM_DATA0 _SFR_MEM8(0x01C4) -#define NVM_DATA1 _SFR_MEM8(0x01C5) -#define NVM_DATA2 _SFR_MEM8(0x01C6) -#define NVM_CMD _SFR_MEM8(0x01CA) -#define NVM_CTRLA _SFR_MEM8(0x01CB) -#define NVM_CTRLB _SFR_MEM8(0x01CC) -#define NVM_INTCTRL _SFR_MEM8(0x01CD) -#define NVM_STATUS _SFR_MEM8(0x01CF) -#define NVM_LOCKBITS _SFR_MEM8(0x01D0) - -/* ADC - Analog-to-Digital Converter */ -#define ADCA_CTRLA _SFR_MEM8(0x0200) -#define ADCA_CTRLB _SFR_MEM8(0x0201) -#define ADCA_REFCTRL _SFR_MEM8(0x0202) -#define ADCA_EVCTRL _SFR_MEM8(0x0203) -#define ADCA_PRESCALER _SFR_MEM8(0x0204) -#define ADCA_INTFLAGS _SFR_MEM8(0x0206) -#define ADCA_TEMP _SFR_MEM8(0x0207) -#define ADCA_CAL _SFR_MEM16(0x020C) -#define ADCA_CH0RES _SFR_MEM16(0x0210) -#define ADCA_CMP _SFR_MEM16(0x0218) -#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) -#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) -#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) -#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) -#define ADCA_CH0_RES _SFR_MEM16(0x0224) -#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) - -/* AC - Analog Comparator */ -#define ACA_AC0CTRL _SFR_MEM8(0x0380) -#define ACA_AC1CTRL _SFR_MEM8(0x0381) -#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) -#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) -#define ACA_CTRLA _SFR_MEM8(0x0384) -#define ACA_CTRLB _SFR_MEM8(0x0385) -#define ACA_WINCTRL _SFR_MEM8(0x0386) -#define ACA_STATUS _SFR_MEM8(0x0387) - -/* RTC - Real-Time Counter */ -#define RTC_CTRL _SFR_MEM8(0x0400) -#define RTC_STATUS _SFR_MEM8(0x0401) -#define RTC_INTCTRL _SFR_MEM8(0x0402) -#define RTC_INTFLAGS _SFR_MEM8(0x0403) -#define RTC_TEMP _SFR_MEM8(0x0404) -#define RTC_CNT _SFR_MEM16(0x0408) -#define RTC_PER _SFR_MEM16(0x040A) -#define RTC_COMP _SFR_MEM16(0x040C) - -/* TWI - Two-Wire Interface */ -#define TWIC_CTRL _SFR_MEM8(0x0480) -#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) -#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) -#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) -#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) -#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) -#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) -#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) -#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) -#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) -#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) -#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) -#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) -#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) - -/* TWI - Two-Wire Interface */ -#define TWIE_CTRL _SFR_MEM8(0x04A0) -#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) -#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) -#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) -#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) -#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) -#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) -#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) -#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) -#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) -#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) -#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) -#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) -#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) - -/* USB - Universal Serial Bus */ -#define USB_CTRLA _SFR_MEM8(0x04C0) -#define USB_CTRLB _SFR_MEM8(0x04C1) -#define USB_STATUS _SFR_MEM8(0x04C2) -#define USB_ADDR _SFR_MEM8(0x04C3) -#define USB_FIFOWP _SFR_MEM8(0x04C4) -#define USB_FIFORP _SFR_MEM8(0x04C5) -#define USB_EPPTR _SFR_MEM16(0x04C6) -#define USB_INTCTRLA _SFR_MEM8(0x04C8) -#define USB_INTCTRLB _SFR_MEM8(0x04C9) -#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA) -#define USB_INTFLAGSASET _SFR_MEM8(0x04CB) -#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC) -#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD) -#define USB_CAL0 _SFR_MEM8(0x04FA) -#define USB_CAL1 _SFR_MEM8(0x04FB) - -/* PORT - I/O Ports */ -#define PORTA_DIR _SFR_MEM8(0x0600) -#define PORTA_DIRSET _SFR_MEM8(0x0601) -#define PORTA_DIRCLR _SFR_MEM8(0x0602) -#define PORTA_DIRTGL _SFR_MEM8(0x0603) -#define PORTA_OUT _SFR_MEM8(0x0604) -#define PORTA_OUTSET _SFR_MEM8(0x0605) -#define PORTA_OUTCLR _SFR_MEM8(0x0606) -#define PORTA_OUTTGL _SFR_MEM8(0x0607) -#define PORTA_IN _SFR_MEM8(0x0608) -#define PORTA_INTCTRL _SFR_MEM8(0x0609) -#define PORTA_INT0MASK _SFR_MEM8(0x060A) -#define PORTA_INT1MASK _SFR_MEM8(0x060B) -#define PORTA_INTFLAGS _SFR_MEM8(0x060C) -#define PORTA_REMAP _SFR_MEM8(0x060E) -#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) -#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) -#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) -#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) -#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) -#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) -#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) -#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) - -/* PORT - I/O Ports */ -#define PORTB_DIR _SFR_MEM8(0x0620) -#define PORTB_DIRSET _SFR_MEM8(0x0621) -#define PORTB_DIRCLR _SFR_MEM8(0x0622) -#define PORTB_DIRTGL _SFR_MEM8(0x0623) -#define PORTB_OUT _SFR_MEM8(0x0624) -#define PORTB_OUTSET _SFR_MEM8(0x0625) -#define PORTB_OUTCLR _SFR_MEM8(0x0626) -#define PORTB_OUTTGL _SFR_MEM8(0x0627) -#define PORTB_IN _SFR_MEM8(0x0628) -#define PORTB_INTCTRL _SFR_MEM8(0x0629) -#define PORTB_INT0MASK _SFR_MEM8(0x062A) -#define PORTB_INT1MASK _SFR_MEM8(0x062B) -#define PORTB_INTFLAGS _SFR_MEM8(0x062C) -#define PORTB_REMAP _SFR_MEM8(0x062E) -#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) -#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) -#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) -#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) -#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) -#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) -#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) -#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) - -/* PORT - I/O Ports */ -#define PORTC_DIR _SFR_MEM8(0x0640) -#define PORTC_DIRSET _SFR_MEM8(0x0641) -#define PORTC_DIRCLR _SFR_MEM8(0x0642) -#define PORTC_DIRTGL _SFR_MEM8(0x0643) -#define PORTC_OUT _SFR_MEM8(0x0644) -#define PORTC_OUTSET _SFR_MEM8(0x0645) -#define PORTC_OUTCLR _SFR_MEM8(0x0646) -#define PORTC_OUTTGL _SFR_MEM8(0x0647) -#define PORTC_IN _SFR_MEM8(0x0648) -#define PORTC_INTCTRL _SFR_MEM8(0x0649) -#define PORTC_INT0MASK _SFR_MEM8(0x064A) -#define PORTC_INT1MASK _SFR_MEM8(0x064B) -#define PORTC_INTFLAGS _SFR_MEM8(0x064C) -#define PORTC_REMAP _SFR_MEM8(0x064E) -#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) -#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) -#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) -#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) -#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) -#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) -#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) -#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) - -/* PORT - I/O Ports */ -#define PORTD_DIR _SFR_MEM8(0x0660) -#define PORTD_DIRSET _SFR_MEM8(0x0661) -#define PORTD_DIRCLR _SFR_MEM8(0x0662) -#define PORTD_DIRTGL _SFR_MEM8(0x0663) -#define PORTD_OUT _SFR_MEM8(0x0664) -#define PORTD_OUTSET _SFR_MEM8(0x0665) -#define PORTD_OUTCLR _SFR_MEM8(0x0666) -#define PORTD_OUTTGL _SFR_MEM8(0x0667) -#define PORTD_IN _SFR_MEM8(0x0668) -#define PORTD_INTCTRL _SFR_MEM8(0x0669) -#define PORTD_INT0MASK _SFR_MEM8(0x066A) -#define PORTD_INT1MASK _SFR_MEM8(0x066B) -#define PORTD_INTFLAGS _SFR_MEM8(0x066C) -#define PORTD_REMAP _SFR_MEM8(0x066E) -#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) -#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) -#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) -#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) -#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) -#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) -#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) -#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) - -/* PORT - I/O Ports */ -#define PORTE_DIR _SFR_MEM8(0x0680) -#define PORTE_DIRSET _SFR_MEM8(0x0681) -#define PORTE_DIRCLR _SFR_MEM8(0x0682) -#define PORTE_DIRTGL _SFR_MEM8(0x0683) -#define PORTE_OUT _SFR_MEM8(0x0684) -#define PORTE_OUTSET _SFR_MEM8(0x0685) -#define PORTE_OUTCLR _SFR_MEM8(0x0686) -#define PORTE_OUTTGL _SFR_MEM8(0x0687) -#define PORTE_IN _SFR_MEM8(0x0688) -#define PORTE_INTCTRL _SFR_MEM8(0x0689) -#define PORTE_INT0MASK _SFR_MEM8(0x068A) -#define PORTE_INT1MASK _SFR_MEM8(0x068B) -#define PORTE_INTFLAGS _SFR_MEM8(0x068C) -#define PORTE_REMAP _SFR_MEM8(0x068E) -#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) -#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) -#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) -#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) -#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) -#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) -#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) -#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) - -/* PORT - I/O Ports */ -#define PORTF_DIR _SFR_MEM8(0x06A0) -#define PORTF_DIRSET _SFR_MEM8(0x06A1) -#define PORTF_DIRCLR _SFR_MEM8(0x06A2) -#define PORTF_DIRTGL _SFR_MEM8(0x06A3) -#define PORTF_OUT _SFR_MEM8(0x06A4) -#define PORTF_OUTSET _SFR_MEM8(0x06A5) -#define PORTF_OUTCLR _SFR_MEM8(0x06A6) -#define PORTF_OUTTGL _SFR_MEM8(0x06A7) -#define PORTF_IN _SFR_MEM8(0x06A8) -#define PORTF_INTCTRL _SFR_MEM8(0x06A9) -#define PORTF_INT0MASK _SFR_MEM8(0x06AA) -#define PORTF_INT1MASK _SFR_MEM8(0x06AB) -#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) -#define PORTF_REMAP _SFR_MEM8(0x06AE) -#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) -#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) -#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) -#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) -#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) -#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) -#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) -#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) - -/* PORT - I/O Ports */ -#define PORTR_DIR _SFR_MEM8(0x07E0) -#define PORTR_DIRSET _SFR_MEM8(0x07E1) -#define PORTR_DIRCLR _SFR_MEM8(0x07E2) -#define PORTR_DIRTGL _SFR_MEM8(0x07E3) -#define PORTR_OUT _SFR_MEM8(0x07E4) -#define PORTR_OUTSET _SFR_MEM8(0x07E5) -#define PORTR_OUTCLR _SFR_MEM8(0x07E6) -#define PORTR_OUTTGL _SFR_MEM8(0x07E7) -#define PORTR_IN _SFR_MEM8(0x07E8) -#define PORTR_INTCTRL _SFR_MEM8(0x07E9) -#define PORTR_INT0MASK _SFR_MEM8(0x07EA) -#define PORTR_INT1MASK _SFR_MEM8(0x07EB) -#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) -#define PORTR_REMAP _SFR_MEM8(0x07EE) -#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) -#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) -#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) -#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) -#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) -#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) -#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) -#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) - -/* TC0 - 16-bit Timer/Counter 0 */ -#define TCC0_CTRLA _SFR_MEM8(0x0800) -#define TCC0_CTRLB _SFR_MEM8(0x0801) -#define TCC0_CTRLC _SFR_MEM8(0x0802) -#define TCC0_CTRLD _SFR_MEM8(0x0803) -#define TCC0_CTRLE _SFR_MEM8(0x0804) -#define TCC0_INTCTRLA _SFR_MEM8(0x0806) -#define TCC0_INTCTRLB _SFR_MEM8(0x0807) -#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) -#define TCC0_CTRLFSET _SFR_MEM8(0x0809) -#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) -#define TCC0_CTRLGSET _SFR_MEM8(0x080B) -#define TCC0_INTFLAGS _SFR_MEM8(0x080C) -#define TCC0_TEMP _SFR_MEM8(0x080F) -#define TCC0_CNT _SFR_MEM16(0x0820) -#define TCC0_PER _SFR_MEM16(0x0826) -#define TCC0_CCA _SFR_MEM16(0x0828) -#define TCC0_CCB _SFR_MEM16(0x082A) -#define TCC0_CCC _SFR_MEM16(0x082C) -#define TCC0_CCD _SFR_MEM16(0x082E) -#define TCC0_PERBUF _SFR_MEM16(0x0836) -#define TCC0_CCABUF _SFR_MEM16(0x0838) -#define TCC0_CCBBUF _SFR_MEM16(0x083A) -#define TCC0_CCCBUF _SFR_MEM16(0x083C) -#define TCC0_CCDBUF _SFR_MEM16(0x083E) - -/* TC2 - 16-bit Timer/Counter type 2 */ -#define TCC2_CTRLA _SFR_MEM8(0x0800) -#define TCC2_CTRLB _SFR_MEM8(0x0801) -#define TCC2_CTRLC _SFR_MEM8(0x0802) -#define TCC2_CTRLE _SFR_MEM8(0x0804) -#define TCC2_INTCTRLA _SFR_MEM8(0x0806) -#define TCC2_INTCTRLB _SFR_MEM8(0x0807) -#define TCC2_CTRLF _SFR_MEM8(0x0809) -#define TCC2_INTFLAGS _SFR_MEM8(0x080C) -#define TCC2_LCNT _SFR_MEM8(0x0820) -#define TCC2_HCNT _SFR_MEM8(0x0821) -#define TCC2_LPER _SFR_MEM8(0x0826) -#define TCC2_HPER _SFR_MEM8(0x0827) -#define TCC2_LCMPA _SFR_MEM8(0x0828) -#define TCC2_HCMPA _SFR_MEM8(0x0829) -#define TCC2_LCMPB _SFR_MEM8(0x082A) -#define TCC2_HCMPB _SFR_MEM8(0x082B) -#define TCC2_LCMPC _SFR_MEM8(0x082C) -#define TCC2_HCMPC _SFR_MEM8(0x082D) -#define TCC2_LCMPD _SFR_MEM8(0x082E) -#define TCC2_HCMPD _SFR_MEM8(0x082F) - -/* TC1 - 16-bit Timer/Counter 1 */ -#define TCC1_CTRLA _SFR_MEM8(0x0840) -#define TCC1_CTRLB _SFR_MEM8(0x0841) -#define TCC1_CTRLC _SFR_MEM8(0x0842) -#define TCC1_CTRLD _SFR_MEM8(0x0843) -#define TCC1_CTRLE _SFR_MEM8(0x0844) -#define TCC1_INTCTRLA _SFR_MEM8(0x0846) -#define TCC1_INTCTRLB _SFR_MEM8(0x0847) -#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) -#define TCC1_CTRLFSET _SFR_MEM8(0x0849) -#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) -#define TCC1_CTRLGSET _SFR_MEM8(0x084B) -#define TCC1_INTFLAGS _SFR_MEM8(0x084C) -#define TCC1_TEMP _SFR_MEM8(0x084F) -#define TCC1_CNT _SFR_MEM16(0x0860) -#define TCC1_PER _SFR_MEM16(0x0866) -#define TCC1_CCA _SFR_MEM16(0x0868) -#define TCC1_CCB _SFR_MEM16(0x086A) -#define TCC1_PERBUF _SFR_MEM16(0x0876) -#define TCC1_CCABUF _SFR_MEM16(0x0878) -#define TCC1_CCBBUF _SFR_MEM16(0x087A) - -/* AWEX - Advanced Waveform Extension */ -#define AWEXC_CTRL _SFR_MEM8(0x0880) -#define AWEXC_FDEMASK _SFR_MEM8(0x0882) -#define AWEXC_FDCTRL _SFR_MEM8(0x0883) -#define AWEXC_STATUS _SFR_MEM8(0x0884) -#define AWEXC_STATUSSET _SFR_MEM8(0x0885) -#define AWEXC_DTBOTH _SFR_MEM8(0x0886) -#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) -#define AWEXC_DTLS _SFR_MEM8(0x0888) -#define AWEXC_DTHS _SFR_MEM8(0x0889) -#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) -#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) -#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) - -/* HIRES - High-Resolution Extension */ -#define HIRESC_CTRLA _SFR_MEM8(0x0890) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTC0_DATA _SFR_MEM8(0x08A0) -#define USARTC0_STATUS _SFR_MEM8(0x08A1) -#define USARTC0_CTRLA _SFR_MEM8(0x08A3) -#define USARTC0_CTRLB _SFR_MEM8(0x08A4) -#define USARTC0_CTRLC _SFR_MEM8(0x08A5) -#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) -#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) - -/* SPI - Serial Peripheral Interface */ -#define SPIC_CTRL _SFR_MEM8(0x08C0) -#define SPIC_INTCTRL _SFR_MEM8(0x08C1) -#define SPIC_STATUS _SFR_MEM8(0x08C2) -#define SPIC_DATA _SFR_MEM8(0x08C3) - -/* IRCOM - IR Communication Module */ -#define IRCOM_CTRL _SFR_MEM8(0x08F8) -#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) -#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) - -/* TC0 - 16-bit Timer/Counter 0 */ -#define TCD0_CTRLA _SFR_MEM8(0x0900) -#define TCD0_CTRLB _SFR_MEM8(0x0901) -#define TCD0_CTRLC _SFR_MEM8(0x0902) -#define TCD0_CTRLD _SFR_MEM8(0x0903) -#define TCD0_CTRLE _SFR_MEM8(0x0904) -#define TCD0_INTCTRLA _SFR_MEM8(0x0906) -#define TCD0_INTCTRLB _SFR_MEM8(0x0907) -#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) -#define TCD0_CTRLFSET _SFR_MEM8(0x0909) -#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) -#define TCD0_CTRLGSET _SFR_MEM8(0x090B) -#define TCD0_INTFLAGS _SFR_MEM8(0x090C) -#define TCD0_TEMP _SFR_MEM8(0x090F) -#define TCD0_CNT _SFR_MEM16(0x0920) -#define TCD0_PER _SFR_MEM16(0x0926) -#define TCD0_CCA _SFR_MEM16(0x0928) -#define TCD0_CCB _SFR_MEM16(0x092A) -#define TCD0_CCC _SFR_MEM16(0x092C) -#define TCD0_CCD _SFR_MEM16(0x092E) -#define TCD0_PERBUF _SFR_MEM16(0x0936) -#define TCD0_CCABUF _SFR_MEM16(0x0938) -#define TCD0_CCBBUF _SFR_MEM16(0x093A) -#define TCD0_CCCBUF _SFR_MEM16(0x093C) -#define TCD0_CCDBUF _SFR_MEM16(0x093E) - -/* TC2 - 16-bit Timer/Counter type 2 */ -#define TCD2_CTRLA _SFR_MEM8(0x0900) -#define TCD2_CTRLB _SFR_MEM8(0x0901) -#define TCD2_CTRLC _SFR_MEM8(0x0902) -#define TCD2_CTRLE _SFR_MEM8(0x0904) -#define TCD2_INTCTRLA _SFR_MEM8(0x0906) -#define TCD2_INTCTRLB _SFR_MEM8(0x0907) -#define TCD2_CTRLF _SFR_MEM8(0x0909) -#define TCD2_INTFLAGS _SFR_MEM8(0x090C) -#define TCD2_LCNT _SFR_MEM8(0x0920) -#define TCD2_HCNT _SFR_MEM8(0x0921) -#define TCD2_LPER _SFR_MEM8(0x0926) -#define TCD2_HPER _SFR_MEM8(0x0927) -#define TCD2_LCMPA _SFR_MEM8(0x0928) -#define TCD2_HCMPA _SFR_MEM8(0x0929) -#define TCD2_LCMPB _SFR_MEM8(0x092A) -#define TCD2_HCMPB _SFR_MEM8(0x092B) -#define TCD2_LCMPC _SFR_MEM8(0x092C) -#define TCD2_HCMPC _SFR_MEM8(0x092D) -#define TCD2_LCMPD _SFR_MEM8(0x092E) -#define TCD2_HCMPD _SFR_MEM8(0x092F) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTD0_DATA _SFR_MEM8(0x09A0) -#define USARTD0_STATUS _SFR_MEM8(0x09A1) -#define USARTD0_CTRLA _SFR_MEM8(0x09A3) -#define USARTD0_CTRLB _SFR_MEM8(0x09A4) -#define USARTD0_CTRLC _SFR_MEM8(0x09A5) -#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) -#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) - -/* SPI - Serial Peripheral Interface */ -#define SPID_CTRL _SFR_MEM8(0x09C0) -#define SPID_INTCTRL _SFR_MEM8(0x09C1) -#define SPID_STATUS _SFR_MEM8(0x09C2) -#define SPID_DATA _SFR_MEM8(0x09C3) - -/* TC0 - 16-bit Timer/Counter 0 */ -#define TCE0_CTRLA _SFR_MEM8(0x0A00) -#define TCE0_CTRLB _SFR_MEM8(0x0A01) -#define TCE0_CTRLC _SFR_MEM8(0x0A02) -#define TCE0_CTRLD _SFR_MEM8(0x0A03) -#define TCE0_CTRLE _SFR_MEM8(0x0A04) -#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) -#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) -#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) -#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) -#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) -#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) -#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) -#define TCE0_TEMP _SFR_MEM8(0x0A0F) -#define TCE0_CNT _SFR_MEM16(0x0A20) -#define TCE0_PER _SFR_MEM16(0x0A26) -#define TCE0_CCA _SFR_MEM16(0x0A28) -#define TCE0_CCB _SFR_MEM16(0x0A2A) -#define TCE0_CCC _SFR_MEM16(0x0A2C) -#define TCE0_CCD _SFR_MEM16(0x0A2E) -#define TCE0_PERBUF _SFR_MEM16(0x0A36) -#define TCE0_CCABUF _SFR_MEM16(0x0A38) -#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) -#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) -#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) - -/* TC2 - 16-bit Timer/Counter type 2 */ -#define TCE2_CTRLA _SFR_MEM8(0x0A00) -#define TCE2_CTRLB _SFR_MEM8(0x0A01) -#define TCE2_CTRLC _SFR_MEM8(0x0A02) -#define TCE2_CTRLE _SFR_MEM8(0x0A04) -#define TCE2_INTCTRLA _SFR_MEM8(0x0A06) -#define TCE2_INTCTRLB _SFR_MEM8(0x0A07) -#define TCE2_CTRLF _SFR_MEM8(0x0A09) -#define TCE2_INTFLAGS _SFR_MEM8(0x0A0C) -#define TCE2_LCNT _SFR_MEM8(0x0A20) -#define TCE2_HCNT _SFR_MEM8(0x0A21) -#define TCE2_LPER _SFR_MEM8(0x0A26) -#define TCE2_HPER _SFR_MEM8(0x0A27) -#define TCE2_LCMPA _SFR_MEM8(0x0A28) -#define TCE2_HCMPA _SFR_MEM8(0x0A29) -#define TCE2_LCMPB _SFR_MEM8(0x0A2A) -#define TCE2_HCMPB _SFR_MEM8(0x0A2B) -#define TCE2_LCMPC _SFR_MEM8(0x0A2C) -#define TCE2_HCMPC _SFR_MEM8(0x0A2D) -#define TCE2_LCMPD _SFR_MEM8(0x0A2E) -#define TCE2_HCMPD _SFR_MEM8(0x0A2F) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTE0_DATA _SFR_MEM8(0x0AA0) -#define USARTE0_STATUS _SFR_MEM8(0x0AA1) -#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) -#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) -#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) -#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) -#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) - -/* TC0 - 16-bit Timer/Counter 0 */ -#define TCF0_CTRLA _SFR_MEM8(0x0B00) -#define TCF0_CTRLB _SFR_MEM8(0x0B01) -#define TCF0_CTRLC _SFR_MEM8(0x0B02) -#define TCF0_CTRLD _SFR_MEM8(0x0B03) -#define TCF0_CTRLE _SFR_MEM8(0x0B04) -#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) -#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) -#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) -#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) -#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) -#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) -#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) -#define TCF0_TEMP _SFR_MEM8(0x0B0F) -#define TCF0_CNT _SFR_MEM16(0x0B20) -#define TCF0_PER _SFR_MEM16(0x0B26) -#define TCF0_CCA _SFR_MEM16(0x0B28) -#define TCF0_CCB _SFR_MEM16(0x0B2A) -#define TCF0_CCC _SFR_MEM16(0x0B2C) -#define TCF0_CCD _SFR_MEM16(0x0B2E) -#define TCF0_PERBUF _SFR_MEM16(0x0B36) -#define TCF0_CCABUF _SFR_MEM16(0x0B38) -#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) -#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) -#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) - -/* TC2 - 16-bit Timer/Counter type 2 */ -#define TCF2_CTRLA _SFR_MEM8(0x0B00) -#define TCF2_CTRLB _SFR_MEM8(0x0B01) -#define TCF2_CTRLC _SFR_MEM8(0x0B02) -#define TCF2_CTRLE _SFR_MEM8(0x0B04) -#define TCF2_INTCTRLA _SFR_MEM8(0x0B06) -#define TCF2_INTCTRLB _SFR_MEM8(0x0B07) -#define TCF2_CTRLF _SFR_MEM8(0x0B09) -#define TCF2_INTFLAGS _SFR_MEM8(0x0B0C) -#define TCF2_LCNT _SFR_MEM8(0x0B20) -#define TCF2_HCNT _SFR_MEM8(0x0B21) -#define TCF2_LPER _SFR_MEM8(0x0B26) -#define TCF2_HPER _SFR_MEM8(0x0B27) -#define TCF2_LCMPA _SFR_MEM8(0x0B28) -#define TCF2_HCMPA _SFR_MEM8(0x0B29) -#define TCF2_LCMPB _SFR_MEM8(0x0B2A) -#define TCF2_HCMPB _SFR_MEM8(0x0B2B) -#define TCF2_LCMPC _SFR_MEM8(0x0B2C) -#define TCF2_HCMPC _SFR_MEM8(0x0B2D) -#define TCF2_LCMPD _SFR_MEM8(0x0B2E) -#define TCF2_HCMPD _SFR_MEM8(0x0B2F) - - - -/*================== Bitfield Definitions ================== */ - -/* VPORT - Virtual Ports */ -/* VPORT.INTFLAGS bit masks and bit positions */ -#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ - -#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ - -/* XOCD - On-Chip Debug System */ -/* OCD.OCDR0 bit masks and bit positions */ -#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ -#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ -#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ -#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ -#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ -#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ -#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ -#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ -#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ -#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ -#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ -#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ -#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ -#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ -#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ -#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ -#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ -#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ - -/* OCD.OCDR1 bit masks and bit positions */ -/* OCD_OCDRD Predefined. */ -/* OCD_OCDRD Predefined. */ - -/* CPU - CPU */ -/* CPU.CCP bit masks and bit positions */ -#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ -#define CPU_CCP_gp 0 /* CCP signature group position. */ -#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ -#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ -#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ -#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ -#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ -#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ -#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ -#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ -#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ -#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ -#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ -#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ -#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ -#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ -#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ -#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ - -/* CPU.SREG bit masks and bit positions */ -#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ -#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ - -#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ -#define CPU_T_bp 6 /* Transfer Bit bit position. */ - -#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ -#define CPU_H_bp 5 /* Half Carry Flag bit position. */ - -#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ -#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ - -#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ -#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ - -#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ -#define CPU_N_bp 2 /* Negative Flag bit position. */ - -#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ -#define CPU_Z_bp 1 /* Zero Flag bit position. */ - -#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ -#define CPU_C_bp 0 /* Carry Flag bit position. */ - -/* CLK - Clock System */ -/* CLK.CTRL bit masks and bit positions */ -#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ -#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ -#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ -#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ -#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ -#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ -#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ -#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ - -/* CLK.PSCTRL bit masks and bit positions */ -#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ -#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ -#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ -#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ -#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ -#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ -#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ -#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ -#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ -#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ -#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ -#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ - -#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ -#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ -#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ -#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ -#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ -#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ - -/* CLK.LOCK bit masks and bit positions */ -#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ -#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ - -/* CLK.RTCCTRL bit masks and bit positions */ -#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ -#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ -#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ -#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ -#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ -#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ - -#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ -#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ - -/* CLK.USBCTRL bit masks and bit positions */ -#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */ -#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */ -#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */ -#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */ -#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */ -#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */ -#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */ -#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */ - -#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */ -#define CLK_USBSRC_gp 1 /* Clock Source group position. */ -#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */ -#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */ - -#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */ -#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */ - -/* PR.PRGEN bit masks and bit positions */ -#define PR_USB_bm 0x40 /* USB bit mask. */ -#define PR_USB_bp 6 /* USB bit position. */ - -#define PR_AES_bm 0x10 /* AES bit mask. */ -#define PR_AES_bp 4 /* AES bit position. */ - -#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ -#define PR_RTC_bp 2 /* Real-time Counter bit position. */ - -#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ -#define PR_EVSYS_bp 1 /* Event System bit position. */ - -#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ -#define PR_DMA_bp 0 /* DMA-Controller bit position. */ - -/* PR.PRPA bit masks and bit positions */ -#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ -#define PR_ADC_bp 1 /* Port A ADC bit position. */ - -#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ -#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ - -/* PR.PRPC bit masks and bit positions */ -#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ -#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ - -#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ -#define PR_USART1_bp 5 /* Port C USART1 bit position. */ - -#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ -#define PR_USART0_bp 4 /* Port C USART0 bit position. */ - -#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ -#define PR_SPI_bp 3 /* Port C SPI bit position. */ - -#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ -#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ - -#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ -#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ - -#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ -#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ - -/* PR.PRPD bit masks and bit positions */ -/* PR_USART0 Predefined. */ -/* PR_USART0 Predefined. */ - -/* PR_SPI Predefined. */ -/* PR_SPI Predefined. */ - -/* PR_TC0 Predefined. */ -/* PR_TC0 Predefined. */ - -/* PR.PRPE bit masks and bit positions */ -/* PR_TWI Predefined. */ -/* PR_TWI Predefined. */ - -/* PR_USART0 Predefined. */ -/* PR_USART0 Predefined. */ - -/* PR_TC0 Predefined. */ -/* PR_TC0 Predefined. */ - -/* PR.PRPF bit masks and bit positions */ -/* PR_USART0 Predefined. */ -/* PR_USART0 Predefined. */ - -/* PR_TC0 Predefined. */ -/* PR_TC0 Predefined. */ - -/* SLEEP - Sleep Controller */ -/* SLEEP.CTRL bit masks and bit positions */ -#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ -#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ -#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ -#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ -#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ -#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ -#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ -#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ - -#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ -#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ - -/* OSC - Oscillator */ -/* OSC.CTRL bit masks and bit positions */ -#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ -#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ - -#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ -#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ - -#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ -#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ - -#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ -#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ - -#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ -#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ - -/* OSC.STATUS bit masks and bit positions */ -#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ -#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ - -#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ -#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ - -#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ -#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ - -#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ -#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ - -#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ -#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ - -/* OSC.XOSCCTRL bit masks and bit positions */ -#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ -#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ -#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ -#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ -#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ -#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ - -#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ -#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ - -#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ -#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ - -#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ -#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ -#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ -#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ -#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ -#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ -#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ -#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ -#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ -#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ - -/* OSC.XOSCFAIL bit masks and bit positions */ -#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ -#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ - -#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ -#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ - -#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ -#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ - -#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ -#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ - -/* OSC.PLLCTRL bit masks and bit positions */ -#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ -#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ -#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ -#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ -#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ -#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ - -#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ -#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ - -#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ -#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ -#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ -#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ -#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ -#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ -#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ -#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ -#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ -#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ -#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ -#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ - -/* OSC.DFLLCTRL bit masks and bit positions */ -#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ -#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ -#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ -#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ -#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ -#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ - -#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ -#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ - -/* DFLL - DFLL */ -/* DFLL.CTRL bit masks and bit positions */ -#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ -#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ - -/* DFLL.CALA bit masks and bit positions */ -#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ -#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ -#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ -#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ -#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ -#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ -#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ -#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ -#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ -#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ -#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ -#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ -#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ -#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ -#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ -#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ - -/* DFLL.CALB bit masks and bit positions */ -#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ -#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ -#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ -#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ -#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ -#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ -#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ -#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ -#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ -#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ -#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ -#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ -#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ -#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ - -/* RST - Reset */ -/* RST.STATUS bit masks and bit positions */ -#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ -#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ - -#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ -#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ - -#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ -#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ - -#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ -#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ - -#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ -#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ - -#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ -#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ - -#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ -#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ - -/* RST.CTRL bit masks and bit positions */ -#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ -#define RST_SWRST_bp 0 /* Software Reset bit position. */ - -/* WDT - Watch-Dog Timer */ -/* WDT.CTRL bit masks and bit positions */ -#define WDT_PER_gm 0x3C /* Period group mask. */ -#define WDT_PER_gp 2 /* Period group position. */ -#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ -#define WDT_PER0_bp 2 /* Period bit 0 position. */ -#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ -#define WDT_PER1_bp 3 /* Period bit 1 position. */ -#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ -#define WDT_PER2_bp 4 /* Period bit 2 position. */ -#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ -#define WDT_PER3_bp 5 /* Period bit 3 position. */ - -#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ -#define WDT_ENABLE_bp 1 /* Enable bit position. */ - -#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ -#define WDT_CEN_bp 0 /* Change Enable bit position. */ - -/* WDT.WINCTRL bit masks and bit positions */ -#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ -#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ -#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ -#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ -#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ -#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ -#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ -#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ -#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ -#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ - -#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ -#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ - -#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ -#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ - -/* WDT.STATUS bit masks and bit positions */ -#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ -#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ - -/* MCU - MCU Control */ -/* MCU.ANAINIT bit masks and bit positions */ -#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ -#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ -#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ -#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ -#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ -#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ - -/* MCU.EVSYSLOCK bit masks and bit positions */ -#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ -#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ - -/* MCU.AWEXLOCK bit masks and bit positions */ -#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ -#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ - -/* PMIC - Programmable Multi-level Interrupt Controller */ -/* PMIC.STATUS bit masks and bit positions */ -#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ -#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ - -#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ -#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ - -#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ -#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ - -#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ -#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ - -/* PMIC.INTPRI bit masks and bit positions */ -#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ -#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ -#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ -#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ -#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ -#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ -#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ -#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ -#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ -#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ -#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ -#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ -#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ -#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ -#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ -#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ -#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ -#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ - -/* PMIC.CTRL bit masks and bit positions */ -#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ -#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ - -#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ -#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ - -#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ -#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ - -#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ -#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ - -#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ -#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ - -/* PORTCFG - Port Configuration */ -/* PORTCFG.VPCTRLA bit masks and bit positions */ -#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ -#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ -#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ -#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ -#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ -#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ -#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ -#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ -#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ -#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ - -#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ -#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ -#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ -#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ -#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ -#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ -#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ -#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ -#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ -#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ - -/* PORTCFG.VPCTRLB bit masks and bit positions */ -#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ -#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ -#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ -#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ -#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ -#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ -#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ -#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ -#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ -#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ - -#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ -#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ -#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ -#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ -#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ -#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ -#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ -#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ -#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ -#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ - -/* PORTCFG.CLKEVOUT bit masks and bit positions */ -#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ -#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ -#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ -#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ -#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ -#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ - -#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ -#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ -#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ -#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ -#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ -#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ - -#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ -#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ -#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ -#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ -#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ -#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ - -#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ -#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ - -#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ -#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ - -/* PORTCFG.EVOUTSEL bit masks and bit positions */ -#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */ -#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */ -#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */ -#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */ -#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */ -#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */ -#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */ -#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */ - -/* CRC - Cyclic Redundancy Checker */ -/* CRC.CTRL bit masks and bit positions */ -#define CRC_RESET_gm 0xC0 /* Reset group mask. */ -#define CRC_RESET_gp 6 /* Reset group position. */ -#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ -#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ -#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ -#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ - -#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ -#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ - -#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ -#define CRC_SOURCE_gp 0 /* Input Source group position. */ -#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ -#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ -#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ -#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ -#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ -#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ -#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ -#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ - -/* CRC.STATUS bit masks and bit positions */ -#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ -#define CRC_ZERO_bp 1 /* Zero detection bit position. */ - -#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ -#define CRC_BUSY_bp 0 /* Busy bit position. */ - -/* EVSYS - Event System */ -/* EVSYS.CH0MUX bit masks and bit positions */ -#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ -#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ -#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ -#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ -#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ -#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ -#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ -#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ -#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ -#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ -#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ -#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ -#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ -#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ -#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ -#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ -#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ -#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ - -/* EVSYS.CH1MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH2MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH3MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH0CTRL bit masks and bit positions */ -#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ -#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ -#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ -#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ -#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ -#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ - -#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ -#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ - -#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ -#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ - -#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ -#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ -#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ -#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ -#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ -#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ -#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ -#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ - -/* EVSYS.CH1CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH2CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH3CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* NVM - Non Volatile Memory Controller */ -/* NVM.CMD bit masks and bit positions */ -#define NVM_CMD_gm 0x7F /* Command group mask. */ -#define NVM_CMD_gp 0 /* Command group position. */ -#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define NVM_CMD0_bp 0 /* Command bit 0 position. */ -#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define NVM_CMD1_bp 1 /* Command bit 1 position. */ -#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ -#define NVM_CMD2_bp 2 /* Command bit 2 position. */ -#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ -#define NVM_CMD3_bp 3 /* Command bit 3 position. */ -#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ -#define NVM_CMD4_bp 4 /* Command bit 4 position. */ -#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ -#define NVM_CMD5_bp 5 /* Command bit 5 position. */ -#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ -#define NVM_CMD6_bp 6 /* Command bit 6 position. */ - -/* NVM.CTRLA bit masks and bit positions */ -#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ -#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ - -/* NVM.CTRLB bit masks and bit positions */ -#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ -#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ - -#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ -#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ - -#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ -#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ - -#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ -#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ - -/* NVM.INTCTRL bit masks and bit positions */ -#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ -#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ -#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ -#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ -#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ -#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ - -#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ -#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ -#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ -#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ -#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ -#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ - -/* NVM.STATUS bit masks and bit positions */ -#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ -#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ - -#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ -#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ - -#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ -#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ - -#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ -#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ - -/* NVM.LOCKBITS bit masks and bit positions */ -#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ - -#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ - -#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ - -#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ -#define NVM_LB_gp 0 /* Lock Bits group position. */ -#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ -#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ - -/* ADC - Analog/Digital Converter */ -/* ADC_CH.CTRL bit masks and bit positions */ -#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ -#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ - -#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ -#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ -#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ -#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ -#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ -#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ -#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ -#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ - -#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ -#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ -#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ -#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ -#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ -#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ - -/* ADC_CH.MUXCTRL bit masks and bit positions */ -#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ -#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ -#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ -#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ -#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ -#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ -#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ -#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ -#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ -#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ - -#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ -#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ -#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ -#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ -#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ -#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ -#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ -#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ -#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ -#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ - -#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC input group mask. */ -#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ -#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ -#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ -#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ -#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ - -/* ADC_CH.INTCTRL bit masks and bit positions */ -#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ -#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ -#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ -#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ -#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ -#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ - -#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ -#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ - -/* ADC_CH.INTFLAGS bit masks and bit positions */ -#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ -#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ - -/* ADC_CH.SCAN bit masks and bit positions */ -#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ -#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ -#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ -#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ -#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ -#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ -#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ -#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ -#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ -#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ - -#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */ -#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */ -#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ -#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */ -#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ -#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */ -#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ -#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */ -#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ -#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */ - -/* ADC.CTRLA bit masks and bit positions */ -#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ -#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ - -#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ -#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ - -#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ -#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ - -/* ADC.CTRLB bit masks and bit positions */ -#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ -#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ -#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ -#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ -#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ -#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ - -#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ -#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ - -#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ -#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ - -#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ -#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ -#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ -#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ -#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ -#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ - -/* ADC.REFCTRL bit masks and bit positions */ -#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ -#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ -#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ -#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ -#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ -#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ -#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ -#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ - -#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ -#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ - -#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ -#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ - -/* ADC.EVCTRL bit masks and bit positions */ -#define ADC_EVSEL_gm 0x18 /* Event Input Select group mask. */ -#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ -#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ -#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ -#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ -#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ - -#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ -#define ADC_EVACT_gp 0 /* Event Action Select group position. */ -#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ -#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ -#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ -#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ -#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ -#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ - -/* ADC.PRESCALER bit masks and bit positions */ -#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ -#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ -#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ -#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ -#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ -#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ -#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ -#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ - -/* ADC.INTFLAGS bit masks and bit positions */ -#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ -#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ - -/* AC - Analog Comparator */ -/* AC.AC0CTRL bit masks and bit positions */ -#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ -#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ -#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ -#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ -#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ -#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ - -#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ -#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ -#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ -#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ -#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ -#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ - -#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ -#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ -#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ -#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ -#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ -#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ - -#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ -#define AC_ENABLE_bp 0 /* Enable bit position. */ - -/* AC.AC1CTRL bit masks and bit positions */ -/* AC_INTMODE Predefined. */ -/* AC_INTMODE Predefined. */ - -/* AC_INTLVL Predefined. */ -/* AC_INTLVL Predefined. */ - -/* AC_HYSMODE Predefined. */ -/* AC_HYSMODE Predefined. */ - -/* AC_ENABLE Predefined. */ -/* AC_ENABLE Predefined. */ - -/* AC.AC0MUXCTRL bit masks and bit positions */ -#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ -#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ -#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ -#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ -#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ -#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ -#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ -#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ - -#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ -#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ -#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ -#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ -#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ -#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ -#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ -#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ - -/* AC.AC1MUXCTRL bit masks and bit positions */ -/* AC_MUXPOS Predefined. */ -/* AC_MUXPOS Predefined. */ - -/* AC_MUXNEG Predefined. */ -/* AC_MUXNEG Predefined. */ - -/* AC.CTRLA bit masks and bit positions */ -#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ -#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ - -#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ -#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ - -/* AC.CTRLB bit masks and bit positions */ -#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ -#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ -#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ -#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ -#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ -#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ -#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ -#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ -#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ -#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ -#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ -#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ -#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ -#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ - -/* AC.WINCTRL bit masks and bit positions */ -#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ -#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ - -#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ -#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ -#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ -#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ -#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ -#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ - -#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ -#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ -#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ -#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ -#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ -#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ - -/* AC.STATUS bit masks and bit positions */ -#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ -#define AC_WSTATE_gp 6 /* Window Mode State group position. */ -#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ -#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ -#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ -#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ - -#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ -#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ - -#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ -#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ - -#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ -#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ - -#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ -#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ - -#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ -#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ - -/* RTC - Real-Time Counter */ -/* RTC.CTRL bit masks and bit positions */ -#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ -#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ -#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ -#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ -#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ -#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ -#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ -#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ - -/* RTC.STATUS bit masks and bit positions */ -#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ -#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ - -/* RTC.INTCTRL bit masks and bit positions */ -#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ -#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ -#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ -#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ -#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ -#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ - -#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ -#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ -#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ -#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ -#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ -#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ - -/* RTC.INTFLAGS bit masks and bit positions */ -#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ -#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ - -#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - -/* TWI - Two-Wire Interface */ -/* TWI_MASTER.CTRLA bit masks and bit positions */ -#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ -#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ - -#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ -#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ - -#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ -#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ - -#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ -#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ - -/* TWI_MASTER.CTRLB bit masks and bit positions */ -#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ -#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ -#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ -#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ -#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ -#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ - -#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ -#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ - -#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ - -/* TWI_MASTER.CTRLC bit masks and bit positions */ -#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ - -#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ -#define TWI_MASTER_CMD_gp 0 /* Command group position. */ -#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ -#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ - -/* TWI_MASTER.STATUS bit masks and bit positions */ -#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ -#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ - -#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ -#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ - -#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ - -#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ - -#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ -#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ - -#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ -#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ - -#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ -#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ -#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ -#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ -#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ -#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ - -/* TWI_SLAVE.CTRLA bit masks and bit positions */ -#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ -#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ - -#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ -#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ - -#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ -#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ - -#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ -#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ - -#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ -#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ - -#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ -#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ - -#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ - -/* TWI_SLAVE.CTRLB bit masks and bit positions */ -#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ - -#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ -#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ -#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ -#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ - -/* TWI_SLAVE.STATUS bit masks and bit positions */ -#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ -#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ - -#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ -#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ - -#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ - -#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ - -#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ -#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ - -#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ -#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ - -#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ -#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ - -#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ -#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ - -/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ -#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ -#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ -#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ -#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ -#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ -#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ -#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ -#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ -#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ -#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ -#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ -#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ -#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ -#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ -#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ -#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ - -#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ -#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ - -/* TWI.CTRL bit masks and bit positions */ -#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ -#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ -#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ -#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ -#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ -#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ - -#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ -#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ - -/* USB - USB */ -/* USB_EP.STATUS bit masks and bit positions */ -#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */ -#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */ - -#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */ -#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */ - -#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */ -#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */ - -#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */ -#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */ - -#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */ -#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */ - -#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */ -#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */ - -#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */ -#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */ - -#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */ -#define USB_EP_BANK_bp 3 /* Bank Select bit position. */ - -#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */ -#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */ - -#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */ -#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */ - -#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */ -#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */ - -/* USB_EP.CTRL bit masks and bit positions */ -#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */ -#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */ -#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */ -#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */ -#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */ -#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */ - -#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */ -#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */ - -#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */ -#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */ - -#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */ -#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */ - -#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */ -#define USB_EP_STALL_bp 2 /* Data Stall bit position. */ - -#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */ -#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */ -#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */ -#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */ -#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */ -#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */ -#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */ -#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */ - -/* USB_EP.CNT bit masks and bit positions */ -#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */ -#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */ - -/* USB.CTRLA bit masks and bit positions */ -#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */ -#define USB_ENABLE_bp 7 /* USB Enable bit position. */ - -#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */ -#define USB_SPEED_bp 6 /* Speed Select bit position. */ - -#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */ -#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */ - -#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */ -#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */ - -#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */ -#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */ -#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */ -#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */ -#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */ -#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */ -#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */ -#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */ -#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */ -#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */ - -/* USB.CTRLB bit masks and bit positions */ -#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */ -#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */ - -#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */ -#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */ - -#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */ -#define USB_GNACK_bp 1 /* Global NACK bit position. */ - -#define USB_ATTACH_bm 0x01 /* Attach bit mask. */ -#define USB_ATTACH_bp 0 /* Attach bit position. */ - -/* USB.STATUS bit masks and bit positions */ -#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */ -#define USB_URESUME_bp 3 /* Upstream Resume bit position. */ - -#define USB_RESUME_bm 0x04 /* Resume bit mask. */ -#define USB_RESUME_bp 2 /* Resume bit position. */ - -#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */ -#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */ - -#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */ -#define USB_BUSRST_bp 0 /* Bus Reset bit position. */ - -/* USB.ADDR bit masks and bit positions */ -#define USB_ADDR_gm 0x7F /* Device Address group mask. */ -#define USB_ADDR_gp 0 /* Device Address group position. */ -#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */ -#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */ -#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */ -#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */ -#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */ -#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */ -#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */ -#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */ -#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */ -#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */ -#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */ -#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */ -#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */ -#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */ - -/* USB.FIFOWP bit masks and bit positions */ -#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */ -#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */ -#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */ -#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */ -#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */ -#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */ -#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */ -#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */ -#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */ -#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */ -#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */ -#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */ - -/* USB.FIFORP bit masks and bit positions */ -#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */ -#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */ -#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */ -#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */ -#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */ -#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */ -#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */ -#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */ -#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */ -#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */ -#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */ -#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */ - -/* USB.INTCTRLA bit masks and bit positions */ -#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */ -#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */ - -#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */ -#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */ - -#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */ -#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */ - -#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */ -#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */ - -#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -#define USB_INTLVL_gp 0 /* Interrupt Level group position. */ -#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ - -/* USB.INTCTRLB bit masks and bit positions */ -#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */ -#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */ - -#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */ -#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */ - -/* USB.INTFLAGSACLR bit masks and bit positions */ -#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */ -#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */ - -#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */ -#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */ - -#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */ -#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */ - -#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */ -#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */ - -#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */ -#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */ - -#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */ -#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */ - -#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */ -#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */ - -#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */ -#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */ - -/* USB.INTFLAGSASET bit masks and bit positions */ -/* USB_SOFIF Predefined. */ -/* USB_SOFIF Predefined. */ - -/* USB_SUSPENDIF Predefined. */ -/* USB_SUSPENDIF Predefined. */ - -/* USB_RESUMEIF Predefined. */ -/* USB_RESUMEIF Predefined. */ - -/* USB_RSTIF Predefined. */ -/* USB_RSTIF Predefined. */ - -/* USB_CRCIF Predefined. */ -/* USB_CRCIF Predefined. */ - -/* USB_UNFIF Predefined. */ -/* USB_UNFIF Predefined. */ - -/* USB_OVFIF Predefined. */ -/* USB_OVFIF Predefined. */ - -/* USB_STALLIF Predefined. */ -/* USB_STALLIF Predefined. */ - -/* USB.INTFLAGSBCLR bit masks and bit positions */ -#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */ -#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */ - -#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */ -#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */ - -/* USB.INTFLAGSBSET bit masks and bit positions */ -/* USB_TRNIF Predefined. */ -/* USB_TRNIF Predefined. */ - -/* USB_SETUPIF Predefined. */ -/* USB_SETUPIF Predefined. */ - -/* PORT - I/O Port Configuration */ -/* PORT.INTCTRL bit masks and bit positions */ -#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ -#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ -#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ -#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ -#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ -#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ - -#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ -#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ -#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ -#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ -#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ -#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ - -/* PORT.INTFLAGS bit masks and bit positions */ -#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ - -#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ - -/* PORT.REMAP bit masks and bit positions */ -#define PORT_SPI_bm 0x20 /* SPI bit mask. */ -#define PORT_SPI_bp 5 /* SPI bit position. */ - -#define PORT_USART0_bm 0x10 /* USART0 bit mask. */ -#define PORT_USART0_bp 4 /* USART0 bit position. */ - -#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ -#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ - -#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ -#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ - -#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ -#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ - -#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ -#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ - -/* PORT.PIN0CTRL bit masks and bit positions */ -#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ -#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ - -#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ -#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ - -#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ -#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ -#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ -#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ -#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ -#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ -#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ -#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ - -#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ -#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ -#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ -#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ -#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ -#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ -#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ -#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ - -/* PORT.PIN1CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN2CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN3CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN4CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN5CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN6CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN7CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* TC - 16-bit Timer/Counter With PWM */ -/* TC0.CTRLA bit masks and bit positions */ -#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - -/* TC0.CTRLB bit masks and bit positions */ -#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ -#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ - -#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ -#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ - -#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ - -#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ - -#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ -#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ - -/* TC0.CTRLC bit masks and bit positions */ -#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ -#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ - -#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ -#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ - -#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ - -#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ - -/* TC0.CTRLD bit masks and bit positions */ -#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ -#define TC0_EVACT_gp 5 /* Event Action group position. */ -#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ -#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ -#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ - -#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ -#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ - -#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ -#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ -#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - -/* TC0.CTRLE bit masks and bit positions */ -#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ -#define TC0_BYTEM_gp 0 /* Byte Mode group position. */ -#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ -#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ -#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ -#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ - -/* TC0.INTCTRLA bit masks and bit positions */ -#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ - -#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ - -/* TC0.INTCTRLB bit masks and bit positions */ -#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ -#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ -#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ -#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ -#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ -#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ - -#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ -#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ -#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ -#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ -#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ -#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ - -#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ - -#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ - -/* TC0.CTRLFCLR bit masks and bit positions */ -#define TC0_CMD_gm 0x0C /* Command group mask. */ -#define TC0_CMD_gp 2 /* Command group position. */ -#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC0_CMD0_bp 2 /* Command bit 0 position. */ -#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC0_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ -#define TC0_LUPD_bp 1 /* Lock Update bit position. */ - -#define TC0_DIR_bm 0x01 /* Direction bit mask. */ -#define TC0_DIR_bp 0 /* Direction bit position. */ - -/* TC0.CTRLFSET bit masks and bit positions */ -/* TC0_CMD Predefined. */ -/* TC0_CMD Predefined. */ - -/* TC0_LUPD Predefined. */ -/* TC0_LUPD Predefined. */ - -/* TC0_DIR Predefined. */ -/* TC0_DIR Predefined. */ - -/* TC0.CTRLGCLR bit masks and bit positions */ -#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ -#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ - -#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ -#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ - -#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ - -#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ - -#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ - -/* TC0.CTRLGSET bit masks and bit positions */ -/* TC0_CCDBV Predefined. */ -/* TC0_CCDBV Predefined. */ - -/* TC0_CCCBV Predefined. */ -/* TC0_CCCBV Predefined. */ - -/* TC0_CCBBV Predefined. */ -/* TC0_CCBBV Predefined. */ - -/* TC0_CCABV Predefined. */ -/* TC0_CCABV Predefined. */ - -/* TC0_PERBV Predefined. */ -/* TC0_PERBV Predefined. */ - -/* TC0.INTFLAGS bit masks and bit positions */ -#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ -#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ - -#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ -#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ - -#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ - -#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ - -#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ - -#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - -/* TC1.CTRLA bit masks and bit positions */ -#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - -/* TC1.CTRLB bit masks and bit positions */ -#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ - -#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ - -#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ -#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ - -/* TC1.CTRLC bit masks and bit positions */ -#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ - -#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ - -/* TC1.CTRLD bit masks and bit positions */ -#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ -#define TC1_EVACT_gp 5 /* Event Action group position. */ -#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ -#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ -#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ - -#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ -#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ - -#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ -#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ -#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - -/* TC1.CTRLE bit masks and bit positions */ -#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ -#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ - -/* TC1.INTCTRLA bit masks and bit positions */ -#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ - -#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ - -/* TC1.INTCTRLB bit masks and bit positions */ -#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ - -#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ - -/* TC1.CTRLFCLR bit masks and bit positions */ -#define TC1_CMD_gm 0x0C /* Command group mask. */ -#define TC1_CMD_gp 2 /* Command group position. */ -#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC1_CMD0_bp 2 /* Command bit 0 position. */ -#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC1_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ -#define TC1_LUPD_bp 1 /* Lock Update bit position. */ - -#define TC1_DIR_bm 0x01 /* Direction bit mask. */ -#define TC1_DIR_bp 0 /* Direction bit position. */ - -/* TC1.CTRLFSET bit masks and bit positions */ -/* TC1_CMD Predefined. */ -/* TC1_CMD Predefined. */ - -/* TC1_LUPD Predefined. */ -/* TC1_LUPD Predefined. */ - -/* TC1_DIR Predefined. */ -/* TC1_DIR Predefined. */ - -/* TC1.CTRLGCLR bit masks and bit positions */ -#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ - -#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ - -#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ - -/* TC1.CTRLGSET bit masks and bit positions */ -/* TC1_CCBBV Predefined. */ -/* TC1_CCBBV Predefined. */ - -/* TC1_CCABV Predefined. */ -/* TC1_CCABV Predefined. */ - -/* TC1_PERBV Predefined. */ -/* TC1_PERBV Predefined. */ - -/* TC1.INTFLAGS bit masks and bit positions */ -#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ - -#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ - -#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ - -#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - -/* TC2 - 16-bit Timer/Counter type 2 */ -/* TC2.CTRLA bit masks and bit positions */ -#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - -/* TC2.CTRLB bit masks and bit positions */ -#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */ -#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */ - -#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */ -#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */ - -#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */ -#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */ - -#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */ -#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */ - -#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */ -#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */ - -#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */ -#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */ - -#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */ -#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */ - -#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */ -#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */ - -/* TC2.CTRLC bit masks and bit positions */ -#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */ -#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */ - -#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */ -#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */ - -#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */ -#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */ - -#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */ -#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */ - -#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */ -#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */ - -#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */ -#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */ - -#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */ -#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */ - -#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */ -#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */ - -/* TC2.CTRLE bit masks and bit positions */ -#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */ -#define TC2_BYTEM_gp 0 /* Byte Mode group position. */ -#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ -#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ -#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ -#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ - -/* TC2.INTCTRLA bit masks and bit positions */ -#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */ -#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */ -#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */ -#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */ -#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */ -#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */ - -#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */ -#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */ -#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */ -#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */ -#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */ -#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */ - -/* TC2.INTCTRLB bit masks and bit positions */ -#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */ -#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */ -#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */ -#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */ -#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */ -#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */ - -#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */ -#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */ -#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */ -#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */ -#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */ -#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */ - -#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */ -#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */ -#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */ -#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */ -#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */ -#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */ - -#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */ -#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */ -#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */ -#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */ -#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */ -#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */ - -/* TC2.CTRLF bit masks and bit positions */ -#define TC2_CMD_gm 0x0C /* Command group mask. */ -#define TC2_CMD_gp 2 /* Command group position. */ -#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC2_CMD0_bp 2 /* Command bit 0 position. */ -#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC2_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */ -#define TC2_CMDEN_gp 0 /* Command Enable group position. */ -#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */ -#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */ -#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */ -#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */ - -/* TC2.INTFLAGS bit masks and bit positions */ -#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */ -#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */ - -#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */ -#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */ - -#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */ -#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */ - -#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */ -#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */ - -#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */ -#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */ - -#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */ -#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */ - -/* AWEX - Timer/Counter Advanced Waveform Extension */ -/* AWEX.CTRL bit masks and bit positions */ -#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ -#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ - -#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ -#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ - -#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ -#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ - -#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ -#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ - -#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ -#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ - -#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ -#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ - -/* AWEX.FDCTRL bit masks and bit positions */ -#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ -#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ - -#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ -#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ - -#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ -#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ -#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ -#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ -#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ -#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ - -/* AWEX.STATUS bit masks and bit positions */ -#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ -#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ - -#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ -#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ - -#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ -#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ - -/* AWEX.STATUSSET bit masks and bit positions */ -/* AWEX_FDF Predefined. */ -/* AWEX_FDF Predefined. */ - -/* AWEX_DTHSBUFV Predefined. */ -/* AWEX_DTHSBUFV Predefined. */ - -/* AWEX_DTLSBUFV Predefined. */ -/* AWEX_DTLSBUFV Predefined. */ - -/* HIRES - Timer/Counter High-Resolution Extension */ -/* HIRES.CTRLA bit masks and bit positions */ -#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ -#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ -#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ -#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ -#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ -#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ - -/* USART - Universal Asynchronous Receiver-Transmitter */ -/* USART.STATUS bit masks and bit positions */ -#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ -#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ - -#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ -#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ - -#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ -#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ - -#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ -#define USART_FERR_bp 4 /* Frame Error bit position. */ - -#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ -#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ - -#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ -#define USART_PERR_bp 2 /* Parity Error bit position. */ - -#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ -#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ - -/* USART.CTRLA bit masks and bit positions */ -#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ -#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ -#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ -#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ -#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ -#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ - -#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ -#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ -#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ -#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ -#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ -#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ - -#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ -#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ -#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ -#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ -#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ -#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ - -/* USART.CTRLB bit masks and bit positions */ -#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ -#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ - -#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ -#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ - -#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ -#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ - -#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ -#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ - -#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ -#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ - -/* USART.CTRLC bit masks and bit positions */ -#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ -#define USART_CMODE_gp 6 /* Communication Mode group position. */ -#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ -#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ -#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ -#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ - -#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ -#define USART_PMODE_gp 4 /* Parity Mode group position. */ -#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ -#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ -#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ -#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ - -#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ -#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ - -#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ -#define USART_CHSIZE_gp 0 /* Character Size group position. */ -#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ -#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ -#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ -#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ -#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ -#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ - -/* USART.BAUDCTRLA bit masks and bit positions */ -#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ -#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ -#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ -#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ -#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ -#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ -#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ -#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ -#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ -#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ -#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ -#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ -#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ -#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ -#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ -#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ -#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ -#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ - -/* USART.BAUDCTRLB bit masks and bit positions */ -#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ -#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ -#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ -#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ -#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ -#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ -#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ -#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ -#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ -#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ - -/* USART_BSEL Predefined. */ -/* USART_BSEL Predefined. */ - -/* SPI - Serial Peripheral Interface */ -/* SPI.CTRL bit masks and bit positions */ -#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ -#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ - -#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ -#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ - -#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ -#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ - -#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ -#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ - -#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ -#define SPI_MODE_gp 2 /* SPI Mode group position. */ -#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ -#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ -#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ -#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ - -#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ -#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ -#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ -#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ -#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ -#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ - -/* SPI.INTCTRL bit masks and bit positions */ -#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ -#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ -#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ - -/* SPI.STATUS bit masks and bit positions */ -#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ -#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ - -#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ -#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ - -/* IRCOM - IR Communication Module */ -/* IRCOM.CTRL bit masks and bit positions */ -#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ -#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ -#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ -#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ -#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ -#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ -#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ -#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ -#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ -#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ - -/* FUSE - Fuses and Lockbits */ -/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ -#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ -#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ -#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ -#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ -#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ -#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ -#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ -#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ -#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ -#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ - -#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ -#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ -#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ -#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ -#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ -#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ -#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ -#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ -#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ -#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ - -/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ -#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ -#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ - -#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ -#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ - -#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ -#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ -#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ -#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ -#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ -#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ - -/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ -#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ -#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ - -#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ -#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ -#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ -#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ -#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ -#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ - -#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ -#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ - -/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ -#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ -#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ -#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ -#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ -#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ -#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ - -#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ -#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ - -#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ -#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ -#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ -#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ -#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ -#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ -#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ -#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ - -/* LOCKBIT - Fuses and Lockbits */ -/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ -#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ - -#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ - -#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ - -#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ -#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ -#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ -#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ - - - -// Generic Port Pins - -#define PIN0_bm 0x01 -#define PIN0_bp 0 -#define PIN1_bm 0x02 -#define PIN1_bp 1 -#define PIN2_bm 0x04 -#define PIN2_bp 2 -#define PIN3_bm 0x08 -#define PIN3_bp 3 -#define PIN4_bm 0x10 -#define PIN4_bp 4 -#define PIN5_bm 0x20 -#define PIN5_bp 5 -#define PIN6_bm 0x40 -#define PIN6_bp 6 -#define PIN7_bm 0x80 -#define PIN7_bp 7 - -/* ========== Interrupt Vector Definitions ========== */ -/* Vector 0 is the reset vector */ - -/* OSC interrupt vectors */ -#define OSC_OSCF_vect_num 1 -#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ - -/* PORTC interrupt vectors */ -#define PORTC_INT0_vect_num 2 -#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ -#define PORTC_INT1_vect_num 3 -#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ - -/* PORTR interrupt vectors */ -#define PORTR_INT0_vect_num 4 -#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ -#define PORTR_INT1_vect_num 5 -#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ - -/* RTC interrupt vectors */ -#define RTC_OVF_vect_num 10 -#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ -#define RTC_COMP_vect_num 11 -#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ - -/* TWIC interrupt vectors */ -#define TWIC_TWIS_vect_num 12 -#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ -#define TWIC_TWIM_vect_num 13 -#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_OVF_vect_num 14 -#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LUNF_vect_num 14 -#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_ERR_vect_num 15 -#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_HUNF_vect_num 15 -#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_CCA_vect_num 16 -#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LCMPA_vect_num 16 -#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_CCB_vect_num 17 -#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LCMPB_vect_num 17 -#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_CCC_vect_num 18 -#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LCMPC_vect_num 18 -#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_CCD_vect_num 19 -#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LCMPD_vect_num 19 -#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */ - -/* TCC1 interrupt vectors */ -#define TCC1_OVF_vect_num 20 -#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ -#define TCC1_ERR_vect_num 21 -#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ -#define TCC1_CCA_vect_num 22 -#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ -#define TCC1_CCB_vect_num 23 -#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ - -/* SPIC interrupt vectors */ -#define SPIC_INT_vect_num 24 -#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ - -/* USARTC0 interrupt vectors */ -#define USARTC0_RXC_vect_num 25 -#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ -#define USARTC0_DRE_vect_num 26 -#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ -#define USARTC0_TXC_vect_num 27 -#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ - -/* NVM interrupt vectors */ -#define NVM_EE_vect_num 32 -#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ -#define NVM_SPM_vect_num 33 -#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ - -/* PORTB interrupt vectors */ -#define PORTB_INT0_vect_num 34 -#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ -#define PORTB_INT1_vect_num 35 -#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ - -/* PORTE interrupt vectors */ -#define PORTE_INT0_vect_num 43 -#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ -#define PORTE_INT1_vect_num 44 -#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ - -/* TWIE interrupt vectors */ -#define TWIE_TWIS_vect_num 45 -#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ -#define TWIE_TWIM_vect_num 46 -#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_OVF_vect_num 47 -#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ - -/* TCE2 interrupt vectors */ -#define TCE2_LUNF_vect_num 47 -#define TCE2_LUNF_vect _VECTOR(47) /* Low Byte Underflow Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_ERR_vect_num 48 -#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ - -/* TCE2 interrupt vectors */ -#define TCE2_HUNF_vect_num 48 -#define TCE2_HUNF_vect _VECTOR(48) /* High Byte Underflow Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_CCA_vect_num 49 -#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ - -/* TCE2 interrupt vectors */ -#define TCE2_LCMPA_vect_num 49 -#define TCE2_LCMPA_vect _VECTOR(49) /* Low Byte Compare A Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_CCB_vect_num 50 -#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ - -/* TCE2 interrupt vectors */ -#define TCE2_LCMPB_vect_num 50 -#define TCE2_LCMPB_vect _VECTOR(50) /* Low Byte Compare B Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_CCC_vect_num 51 -#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ - -/* TCE2 interrupt vectors */ -#define TCE2_LCMPC_vect_num 51 -#define TCE2_LCMPC_vect _VECTOR(51) /* Low Byte Compare C Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_CCD_vect_num 52 -#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ - -/* TCE2 interrupt vectors */ -#define TCE2_LCMPD_vect_num 52 -#define TCE2_LCMPD_vect _VECTOR(52) /* Low Byte Compare D Interrupt */ - -/* USARTE0 interrupt vectors */ -#define USARTE0_RXC_vect_num 58 -#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ -#define USARTE0_DRE_vect_num 59 -#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ -#define USARTE0_TXC_vect_num 60 -#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ - -/* PORTD interrupt vectors */ -#define PORTD_INT0_vect_num 64 -#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ -#define PORTD_INT1_vect_num 65 -#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ - -/* PORTA interrupt vectors */ -#define PORTA_INT0_vect_num 66 -#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ -#define PORTA_INT1_vect_num 67 -#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ - -/* ACA interrupt vectors */ -#define ACA_AC0_vect_num 68 -#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ -#define ACA_AC1_vect_num 69 -#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ -#define ACA_ACW_vect_num 70 -#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ - -/* ADCA interrupt vectors */ -#define ADCA_CH0_vect_num 71 -#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ - -/* TCD0 interrupt vectors */ -#define TCD0_OVF_vect_num 77 -#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LUNF_vect_num 77 -#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_ERR_vect_num 78 -#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_HUNF_vect_num 78 -#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_CCA_vect_num 79 -#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LCMPA_vect_num 79 -#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_CCB_vect_num 80 -#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LCMPB_vect_num 80 -#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_CCC_vect_num 81 -#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LCMPC_vect_num 81 -#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_CCD_vect_num 82 -#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LCMPD_vect_num 82 -#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */ - -/* SPID interrupt vectors */ -#define SPID_INT_vect_num 87 -#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ - -/* USARTD0 interrupt vectors */ -#define USARTD0_RXC_vect_num 88 -#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ -#define USARTD0_DRE_vect_num 89 -#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ -#define USARTD0_TXC_vect_num 90 -#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ - -/* PORTF interrupt vectors */ -#define PORTF_INT0_vect_num 104 -#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ -#define PORTF_INT1_vect_num 105 -#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ - -/* TCF0 interrupt vectors */ -#define TCF0_OVF_vect_num 108 -#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ - -/* TCF2 interrupt vectors */ -#define TCF2_LUNF_vect_num 108 -#define TCF2_LUNF_vect _VECTOR(108) /* Low Byte Underflow Interrupt */ - -/* TCF0 interrupt vectors */ -#define TCF0_ERR_vect_num 109 -#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ - -/* TCF2 interrupt vectors */ -#define TCF2_HUNF_vect_num 109 -#define TCF2_HUNF_vect _VECTOR(109) /* High Byte Underflow Interrupt */ - -/* TCF0 interrupt vectors */ -#define TCF0_CCA_vect_num 110 -#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ - -/* TCF2 interrupt vectors */ -#define TCF2_LCMPA_vect_num 110 -#define TCF2_LCMPA_vect _VECTOR(110) /* Low Byte Compare A Interrupt */ - -/* TCF0 interrupt vectors */ -#define TCF0_CCB_vect_num 111 -#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ - -/* TCF2 interrupt vectors */ -#define TCF2_LCMPB_vect_num 111 -#define TCF2_LCMPB_vect _VECTOR(111) /* Low Byte Compare B Interrupt */ - -/* TCF0 interrupt vectors */ -#define TCF0_CCC_vect_num 112 -#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ - -/* TCF2 interrupt vectors */ -#define TCF2_LCMPC_vect_num 112 -#define TCF2_LCMPC_vect _VECTOR(112) /* Low Byte Compare C Interrupt */ - -/* TCF0 interrupt vectors */ -#define TCF0_CCD_vect_num 113 -#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ - -/* TCF2 interrupt vectors */ -#define TCF2_LCMPD_vect_num 113 -#define TCF2_LCMPD_vect _VECTOR(113) /* Low Byte Compare D Interrupt */ - -/* USB interrupt vectors */ -#define USB_BUSEVENT_vect_num 125 -#define USB_BUSEVENT_vect _VECTOR(125) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */ -#define USB_TRNCOMPL_vect_num 126 -#define USB_TRNCOMPL_vect _VECTOR(126) /* Transaction complete interrupt */ - -#define _VECTOR_SIZE 4 /* Size of individual vector. */ -#define _VECTORS_SIZE (127 * _VECTOR_SIZE) - - -/* ========== Constants ========== */ - -#define PROGMEM_START (0x0000) -#define PROGMEM_SIZE (36864) -#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) - -#define APP_SECTION_START (0x0000) -#define APP_SECTION_SIZE (32768) -#define APP_SECTION_PAGE_SIZE (256) -#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) - -#define APPTABLE_SECTION_START (0x7000) -#define APPTABLE_SECTION_SIZE (4096) -#define APPTABLE_SECTION_PAGE_SIZE (256) -#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) - -#define BOOT_SECTION_START (0x8000) -#define BOOT_SECTION_SIZE (4096) -#define BOOT_SECTION_PAGE_SIZE (256) -#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) - -#define DATAMEM_START (0x0000) -#define DATAMEM_SIZE (12288) -#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) - -#define IO_START (0x0000) -#define IO_SIZE (4096) -#define IO_PAGE_SIZE (0) -#define IO_END (IO_START + IO_SIZE - 1) - -#define MAPPED_EEPROM_START (0x1000) -#define MAPPED_EEPROM_SIZE (1024) -#define MAPPED_EEPROM_PAGE_SIZE (0) -#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) - -#define INTERNAL_SRAM_START (0x2000) -#define INTERNAL_SRAM_SIZE (4096) -#define INTERNAL_SRAM_PAGE_SIZE (0) -#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) - -#define EEPROM_START (0x0000) -#define EEPROM_SIZE (1024) -#define EEPROM_PAGE_SIZE (32) -#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) - -#define SIGNATURES_START (0x0000) -#define SIGNATURES_SIZE (3) -#define SIGNATURES_PAGE_SIZE (0) -#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) - -#define FUSES_START (0x0000) -#define FUSES_SIZE (6) -#define FUSES_PAGE_SIZE (0) -#define FUSES_END (FUSES_START + FUSES_SIZE - 1) - -#define LOCKBITS_START (0x0000) -#define LOCKBITS_SIZE (1) -#define LOCKBITS_PAGE_SIZE (0) -#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) - -#define USER_SIGNATURES_START (0x0000) -#define USER_SIGNATURES_SIZE (256) -#define USER_SIGNATURES_PAGE_SIZE (256) -#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) - -#define PROD_SIGNATURES_START (0x0000) -#define PROD_SIGNATURES_SIZE (64) -#define PROD_SIGNATURES_PAGE_SIZE (256) -#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) - -#define FLASHSTART PROGMEM_START -#define FLASHEND PROGMEM_END -#define SPM_PAGESIZE 256 -#define RAMSTART INTERNAL_SRAM_START -#define RAMSIZE INTERNAL_SRAM_SIZE -#define RAMEND INTERNAL_SRAM_END -#define E2END EEPROM_END -#define E2PAGESIZE EEPROM_PAGE_SIZE - - -/* ========== Fuses ========== */ -#define FUSE_MEMORY_SIZE 6 - -/* Fuse Byte 0 Reserved */ - -/* Fuse Byte 1 */ -#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ -#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ -#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ -#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ -#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ -#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ -#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ -#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ -#define FUSE1_DEFAULT (0xFF) - -/* Fuse Byte 2 */ -#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ -#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ -#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ -#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ -#define FUSE2_DEFAULT (0xFF) - -/* Fuse Byte 3 Reserved */ - -/* Fuse Byte 4 */ -#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ -#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ -#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ -#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ -#define FUSE4_DEFAULT (0xFF) - -/* Fuse Byte 5 */ -#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ -#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ -#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ -#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ -#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ -#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ -#define FUSE5_DEFAULT (0xFF) - -/* ========== Lock Bits ========== */ -#define __LOCK_BITS_EXIST -#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST -#define __BOOT_LOCK_APPLICATION_BITS_EXIST -#define __BOOT_LOCK_BOOT_BITS_EXIST - -/* ========== Signature ========== */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x95 -#define SIGNATURE_2 0x49 - -/* ========== Power Reduction Condition Definitions ========== */ - -/* PR.PRGEN */ -#define __AVR_HAVE_PRGEN (PR_USB_bm|PR_AES_bm|PR_RTC_bm|PR_EVSYS_bm|PR_DMA_bm) -#define __AVR_HAVE_PRGEN_USB -#define __AVR_HAVE_PRGEN_AES -#define __AVR_HAVE_PRGEN_RTC -#define __AVR_HAVE_PRGEN_EVSYS -#define __AVR_HAVE_PRGEN_DMA - -/* PR.PRPA */ -#define __AVR_HAVE_PRPA (PR_ADC_bm|PR_AC_bm) -#define __AVR_HAVE_PRPA_ADC -#define __AVR_HAVE_PRPA_AC - -/* PR.PRPC */ -#define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPC_TWI -#define __AVR_HAVE_PRPC_USART1 -#define __AVR_HAVE_PRPC_USART0 -#define __AVR_HAVE_PRPC_SPI -#define __AVR_HAVE_PRPC_HIRES -#define __AVR_HAVE_PRPC_TC1 -#define __AVR_HAVE_PRPC_TC0 - -/* PR.PRPD */ -#define __AVR_HAVE_PRPD (PR_USART0_bm|PR_SPI_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPD_USART0 -#define __AVR_HAVE_PRPD_SPI -#define __AVR_HAVE_PRPD_TC0 - -/* PR.PRPE */ -#define __AVR_HAVE_PRPE (PR_TWI_bm|PR_USART0_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPE_TWI -#define __AVR_HAVE_PRPE_USART0 -#define __AVR_HAVE_PRPE_TC0 - -/* PR.PRPF */ -#define __AVR_HAVE_PRPF (PR_USART0_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPF_USART0 -#define __AVR_HAVE_PRPF_TC0 - - -#endif /* #ifdef _AVR_ATXMEGA32C3_H_INCLUDED */ - +/***************************************************************************** + * + * Copyright (C) 2016 Atmel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * * Neither the name of the copyright holders nor the names of + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ****************************************************************************/ + + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iox32c3.h" +#else +# error "Attempt to include more than one file." +#endif + +#ifndef _AVR_ATXMEGA32C3_H_INCLUDED +#define _AVR_ATXMEGA32C3_H_INCLUDED + +/* Ungrouped common registers */ +#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ + +/* Deprecated */ +#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ + +#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ +#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ +#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ +#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ +#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ +#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +#define SREG _SFR_MEM8(0x003F) /* Status Register */ + +/* C Language Only */ +#if !defined (__ASSEMBLER__) + +#include + +typedef volatile uint8_t register8_t; +typedef volatile uint16_t register16_t; +typedef volatile uint32_t register32_t; + + +#ifdef _WORDREGISTER +#undef _WORDREGISTER +#endif +#define _WORDREGISTER(regname) \ + __extension__ union \ + { \ + register16_t regname; \ + struct \ + { \ + register8_t regname ## L; \ + register8_t regname ## H; \ + }; \ + } + +#ifdef _DWORDREGISTER +#undef _DWORDREGISTER +#endif +#define _DWORDREGISTER(regname) \ + __extension__ union \ + { \ + register32_t regname; \ + struct \ + { \ + register8_t regname ## 0; \ + register8_t regname ## 1; \ + register8_t regname ## 2; \ + register8_t regname ## 3; \ + }; \ + } + + +/* +========================================================================== +IO Module Structures +========================================================================== +*/ + + +/* +-------------------------------------------------------------------------- +VPORT - Virtual Ports +-------------------------------------------------------------------------- +*/ + +/* Virtual Port */ +typedef struct VPORT_struct +{ + register8_t DIR; /* I/O Port Data Direction */ + register8_t OUT; /* I/O Port Output */ + register8_t IN; /* I/O Port Input */ + register8_t INTFLAGS; /* Interrupt Flag Register */ +} VPORT_t; + + +/* +-------------------------------------------------------------------------- +XOCD - On-Chip Debug System +-------------------------------------------------------------------------- +*/ + +/* On-Chip Debug System */ +typedef struct OCD_struct +{ + register8_t OCDR0; /* OCD Register 0 */ + register8_t OCDR1; /* OCD Register 1 */ +} OCD_t; + + +/* +-------------------------------------------------------------------------- +CPU - CPU +-------------------------------------------------------------------------- +*/ + +/* CCP signatures */ +typedef enum CCP_enum +{ + CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ + CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +} CCP_t; + + +/* +-------------------------------------------------------------------------- +CLK - Clock System +-------------------------------------------------------------------------- +*/ + +/* Clock System */ +typedef struct CLK_struct +{ + register8_t CTRL; /* Control Register */ + register8_t PSCTRL; /* Prescaler Control Register */ + register8_t LOCK; /* Lock register */ + register8_t RTCCTRL; /* RTC Control Register */ + register8_t USBCTRL; /* USB Control Register */ +} CLK_t; + + +/* Power Reduction */ +typedef struct PR_struct +{ + register8_t PRGEN; /* General Power Reduction */ + register8_t PRPA; /* Power Reduction Port A */ + register8_t reserved_0x02; + register8_t PRPC; /* Power Reduction Port C */ + register8_t PRPD; /* Power Reduction Port D */ + register8_t PRPE; /* Power Reduction Port E */ + register8_t PRPF; /* Power Reduction Port F */ +} PR_t; + +/* System Clock Selection */ +typedef enum CLK_SCLKSEL_enum +{ + CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ + CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ + CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ + CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ + CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ +} CLK_SCLKSEL_t; + +/* Prescaler A Division Factor */ +typedef enum CLK_PSADIV_enum +{ + CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ + CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ + CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ + CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ + CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ + CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ + CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ + CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ + CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ + CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ +} CLK_PSADIV_t; + +/* Prescaler B and C Division Factor */ +typedef enum CLK_PSBCDIV_enum +{ + CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ + CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ + CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ + CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ +} CLK_PSBCDIV_t; + +/* RTC Clock Source */ +typedef enum CLK_RTCSRC_enum +{ + CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ + CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ + CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ + CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ + CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ + CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ +} CLK_RTCSRC_t; + +/* USB Prescaler Division Factor */ +typedef enum CLK_USBPSDIV_enum +{ + CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */ + CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */ + CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */ + CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */ + CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */ + CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */ +} CLK_USBPSDIV_t; + +/* USB Clock Source */ +typedef enum CLK_USBSRC_enum +{ + CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */ + CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */ +} CLK_USBSRC_t; + + +/* +-------------------------------------------------------------------------- +SLEEP - Sleep Controller +-------------------------------------------------------------------------- +*/ + +/* Sleep Controller */ +typedef struct SLEEP_struct +{ + register8_t CTRL; /* Control Register */ +} SLEEP_t; + +/* Sleep Mode */ +typedef enum SLEEP_SMODE_enum +{ + SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ + SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ + SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ + SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ + SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ +} SLEEP_SMODE_t; + + + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +#define SLEEP_MODE_PWR_SAVE (0x03<<1) +#define SLEEP_MODE_STANDBY (0x06<<1) +#define SLEEP_MODE_EXT_STANDBY (0x07<<1) +/* +-------------------------------------------------------------------------- +OSC - Oscillator +-------------------------------------------------------------------------- +*/ + +/* Oscillator */ +typedef struct OSC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t XOSCCTRL; /* External Oscillator Control Register */ + register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ + register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ + register8_t PLLCTRL; /* PLL Control Register */ + register8_t DFLLCTRL; /* DFLL Control Register */ +} OSC_t; + +/* Oscillator Frequency Range */ +typedef enum OSC_FRQRANGE_enum +{ + OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ + OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ + OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ + OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ +} OSC_FRQRANGE_t; + +/* External Oscillator Selection and Startup Time */ +typedef enum OSC_XOSCSEL_enum +{ + OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ + OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ + OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ + OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ + OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ +} OSC_XOSCSEL_t; + +/* PLL Clock Source */ +typedef enum OSC_PLLSRC_enum +{ + OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ + OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ + OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ +} OSC_PLLSRC_t; + +/* 2 MHz DFLL Calibration Reference */ +typedef enum OSC_RC2MCREF_enum +{ + OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ + OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ +} OSC_RC2MCREF_t; + +/* 32 MHz DFLL Calibration Reference */ +typedef enum OSC_RC32MCREF_enum +{ + OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ + OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ + OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */ +} OSC_RC32MCREF_t; + + +/* +-------------------------------------------------------------------------- +DFLL - DFLL +-------------------------------------------------------------------------- +*/ + +/* DFLL */ +typedef struct DFLL_struct +{ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x01; + register8_t CALA; /* Calibration Register A */ + register8_t CALB; /* Calibration Register B */ + register8_t COMP0; /* Oscillator Compare Register 0 */ + register8_t COMP1; /* Oscillator Compare Register 1 */ + register8_t COMP2; /* Oscillator Compare Register 2 */ + register8_t reserved_0x07; +} DFLL_t; + + +/* +-------------------------------------------------------------------------- +RST - Reset +-------------------------------------------------------------------------- +*/ + +/* Reset */ +typedef struct RST_struct +{ + register8_t STATUS; /* Status Register */ + register8_t CTRL; /* Control Register */ +} RST_t; + + +/* +-------------------------------------------------------------------------- +WDT - Watch-Dog Timer +-------------------------------------------------------------------------- +*/ + +/* Watch-Dog Timer */ +typedef struct WDT_struct +{ + register8_t CTRL; /* Control */ + register8_t WINCTRL; /* Windowed Mode Control */ + register8_t STATUS; /* Status */ +} WDT_t; + +/* Period setting */ +typedef enum WDT_PER_enum +{ + WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ + WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ + WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ + WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ + WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ + WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ + WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ + WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ + WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ + WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ + WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +} WDT_PER_t; + +/* Closed window period */ +typedef enum WDT_WPER_enum +{ + WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ + WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ + WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ + WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ + WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ + WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ + WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ + WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ + WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ + WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ + WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +} WDT_WPER_t; + + +/* +-------------------------------------------------------------------------- +MCU - MCU Control +-------------------------------------------------------------------------- +*/ + +/* MCU Control */ +typedef struct MCU_struct +{ + register8_t DEVID0; /* Device ID byte 0 */ + register8_t DEVID1; /* Device ID byte 1 */ + register8_t DEVID2; /* Device ID byte 2 */ + register8_t REVID; /* Revision ID */ + register8_t reserved_0x04; + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t ANAINIT; /* Analog Startup Delay */ + register8_t EVSYSLOCK; /* Event System Lock */ + register8_t AWEXLOCK; /* AWEX Lock */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; +} MCU_t; + + +/* +-------------------------------------------------------------------------- +PMIC - Programmable Multi-level Interrupt Controller +-------------------------------------------------------------------------- +*/ + +/* Programmable Multi-level Interrupt Controller */ +typedef struct PMIC_struct +{ + register8_t STATUS; /* Status Register */ + register8_t INTPRI; /* Interrupt Priority */ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x03; + register8_t reserved_0x04; + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; +} PMIC_t; + + +/* +-------------------------------------------------------------------------- +PORTCFG - Port Configuration +-------------------------------------------------------------------------- +*/ + +/* I/O port Configuration */ +typedef struct PORTCFG_struct +{ + register8_t MPCMASK; /* Multi-pin Configuration Mask */ + register8_t reserved_0x01; + register8_t VPCTRLA; /* Virtual Port Control Register A */ + register8_t VPCTRLB; /* Virtual Port Control Register B */ + register8_t CLKEVOUT; /* Clock and Event Out Register */ + register8_t reserved_0x05; + register8_t EVOUTSEL; /* Event Output Select */ +} PORTCFG_t; + +/* Virtual Port Mapping */ +typedef enum PORTCFG_VP02MAP_enum +{ + PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ + PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ + PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ + PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ + PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ + PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ + PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ + PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ + PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ + PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ + PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ + PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ + PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ + PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ + PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ + PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ +} PORTCFG_VP02MAP_t; + +/* Virtual Port Mapping */ +typedef enum PORTCFG_VP13MAP_enum +{ + PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ + PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ + PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ + PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ + PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ + PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ + PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ + PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ + PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ + PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ + PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ + PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ + PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ + PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ + PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ + PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ +} PORTCFG_VP13MAP_t; + +/* System Clock Output Port */ +typedef enum PORTCFG_CLKOUT_enum +{ + PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ + PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ + PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ + PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */ +} PORTCFG_CLKOUT_t; + +/* Peripheral Clock Output Select */ +typedef enum PORTCFG_CLKOUTSEL_enum +{ + PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ + PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ + PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ +} PORTCFG_CLKOUTSEL_t; + +/* Event Output Port */ +typedef enum PORTCFG_EVOUT_enum +{ + PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ + PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ + PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ + PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ +} PORTCFG_EVOUT_t; + +/* Event Output Select */ +typedef enum PORTCFG_EVOUTSEL_enum +{ + PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ + PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ + PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ + PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ +} PORTCFG_EVOUTSEL_t; + + +/* +-------------------------------------------------------------------------- +CRC - Cyclic Redundancy Checker +-------------------------------------------------------------------------- +*/ + +/* Cyclic Redundancy Checker */ +typedef struct CRC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t reserved_0x02; + register8_t DATAIN; /* Data Input */ + register8_t CHECKSUM0; /* Checksum byte 0 */ + register8_t CHECKSUM1; /* Checksum byte 1 */ + register8_t CHECKSUM2; /* Checksum byte 2 */ + register8_t CHECKSUM3; /* Checksum byte 3 */ +} CRC_t; + +/* Reset */ +typedef enum CRC_RESET_enum +{ + CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ + CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ + CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ +} CRC_RESET_t; + +/* Input Source */ +typedef enum CRC_SOURCE_enum +{ + CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ + CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ + CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ +} CRC_SOURCE_t; + + +/* +-------------------------------------------------------------------------- +EVSYS - Event System +-------------------------------------------------------------------------- +*/ + +/* Event System */ +typedef struct EVSYS_struct +{ + register8_t CH0MUX; /* Event Channel 0 Multiplexer */ + register8_t CH1MUX; /* Event Channel 1 Multiplexer */ + register8_t CH2MUX; /* Event Channel 2 Multiplexer */ + register8_t CH3MUX; /* Event Channel 3 Multiplexer */ + register8_t reserved_0x04; + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t CH0CTRL; /* Channel 0 Control Register */ + register8_t CH1CTRL; /* Channel 1 Control Register */ + register8_t CH2CTRL; /* Channel 2 Control Register */ + register8_t CH3CTRL; /* Channel 3 Control Register */ + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t STROBE; /* Event Strobe */ + register8_t DATA; /* Event Data */ +} EVSYS_t; + +/* Quadrature Decoder Index Recognition Mode */ +typedef enum EVSYS_QDIRM_enum +{ + EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ + EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ + EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ + EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ +} EVSYS_QDIRM_t; + +/* Digital filter coefficient */ +typedef enum EVSYS_DIGFILT_enum +{ + EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ + EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ + EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ + EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ + EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ + EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ + EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ + EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ +} EVSYS_DIGFILT_t; + +/* Event Channel multiplexer input selection */ +typedef enum EVSYS_CHMUX_enum +{ + EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ + EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ + EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */ + EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ + EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ + EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ + EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel */ + EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ + EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ + EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ + EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ + EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ + EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ + EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ + EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ + EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ + EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ + EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ + EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ + EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ + EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ + EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ + EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ + EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ + EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ + EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ + EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ + EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ + EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ + EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ + EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ + EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ + EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ + EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ + EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ + EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ + EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ + EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ + EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ + EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ + EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ + EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ + EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ + EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ + EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ + EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ + EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ + EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ + EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ + EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ + EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ + EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ + EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ + EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ + EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ + EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ + EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ + EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ + EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ + EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ + EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ + EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ + EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ + EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ + EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ + EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ + EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ + EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ + EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ + EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ + EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ + EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ + EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ + EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ + EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ + EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ + EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ + EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ + EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ + EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ + EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ + EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ + EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ + EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ + EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ + EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ + EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ + EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ + EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ + EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ + EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ + EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ + EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ + EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ + EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ + EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ + EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ + EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ + EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ +} EVSYS_CHMUX_t; + + +/* +-------------------------------------------------------------------------- +NVM - Non Volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Non-volatile Memory Controller */ +typedef struct NVM_struct +{ + register8_t ADDR0; /* Address Register 0 */ + register8_t ADDR1; /* Address Register 1 */ + register8_t ADDR2; /* Address Register 2 */ + register8_t reserved_0x03; + register8_t DATA0; /* Data Register 0 */ + register8_t DATA1; /* Data Register 1 */ + register8_t DATA2; /* Data Register 2 */ + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t CMD; /* Command */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t reserved_0x0E; + register8_t STATUS; /* Status */ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ +} NVM_t; + +/* NVM Command */ +typedef enum NVM_CMD_enum +{ + NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ + NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ + NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ + NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ + NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ + NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ + NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ + NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ + NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ + NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ + NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ + NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ + NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ + NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ + NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ + NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ + NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ + NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ + NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ + NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ + NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ + NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ + NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ + NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ + NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ + NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ + NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ + NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ + NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ + NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ + NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ + NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ + NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ + NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ +} NVM_CMD_t; + +/* SPM ready interrupt level */ +typedef enum NVM_SPMLVL_enum +{ + NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ + NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ + NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ + NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ +} NVM_SPMLVL_t; + +/* EEPROM ready interrupt level */ +typedef enum NVM_EELVL_enum +{ + NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ + NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ + NVM_EELVL_HI_gc = (0x03<<0), /* High level */ +} NVM_EELVL_t; + +/* Boot lock bits - boot setcion */ +typedef enum NVM_BLBB_enum +{ + NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ + NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ + NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ + NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ +} NVM_BLBB_t; + +/* Boot lock bits - application section */ +typedef enum NVM_BLBA_enum +{ + NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ + NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ + NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ + NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ +} NVM_BLBA_t; + +/* Boot lock bits - application table section */ +typedef enum NVM_BLBAT_enum +{ + NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ + NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ + NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ + NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ +} NVM_BLBAT_t; + +/* Lock bits */ +typedef enum NVM_LB_enum +{ + NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ + NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ + NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ +} NVM_LB_t; + + +/* +-------------------------------------------------------------------------- +ADC - Analog/Digital Converter +-------------------------------------------------------------------------- +*/ + +/* ADC Channel */ +typedef struct ADC_CH_struct +{ + register8_t CTRL; /* Control Register */ + register8_t MUXCTRL; /* MUX Control */ + register8_t INTCTRL; /* Channel Interrupt Control Register */ + register8_t INTFLAGS; /* Interrupt Flags */ + _WORDREGISTER(RES); /* Channel Result */ + register8_t SCAN; /* Input Channel Scan */ + register8_t reserved_0x07; +} ADC_CH_t; + + +/* Analog-to-Digital Converter */ +typedef struct ADC_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t REFCTRL; /* Reference Control */ + register8_t EVCTRL; /* Event Control */ + register8_t PRESCALER; /* Clock Prescaler */ + register8_t reserved_0x05; + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary Register */ + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + _WORDREGISTER(CAL); /* Calibration Value */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + _WORDREGISTER(CH0RES); /* Channel 0 Result */ + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + _WORDREGISTER(CMP); /* Compare Value */ + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + ADC_CH_t CH0; /* ADC Channel 0 */ +} ADC_t; + +/* Current Limitation */ +typedef enum ADC_CURRLIMIT_enum +{ + ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ + ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 250ksps max sampling rate */ + ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ + ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 50ksps max sampling rate */ +} ADC_CURRLIMIT_t; + +/* Positive input multiplexer selection */ +typedef enum ADC_CH_MUXPOS_enum +{ + ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ + ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ + ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ + ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ + ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ + ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ + ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ + ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ + ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ + ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ + ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ + ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ + ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ + ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ + ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ + ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ +} ADC_CH_MUXPOS_t; + +/* Internal input multiplexer selections */ +typedef enum ADC_CH_MUXINT_enum +{ + ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ + ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ + ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ +} ADC_CH_MUXINT_t; + +/* Negative input multiplexer selection */ +typedef enum ADC_CH_MUXNEG_enum +{ + ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ + ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ + ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ + ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ + ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */ + ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */ + ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */ + ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */ +} ADC_CH_MUXNEG_t; + +/* Input mode */ +typedef enum ADC_CH_INPUTMODE_enum +{ + ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ + ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ + ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ + ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ +} ADC_CH_INPUTMODE_t; + +/* Gain factor */ +typedef enum ADC_CH_GAIN_enum +{ + ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ + ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ + ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ + ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ + ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ + ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ + ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ + ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ +} ADC_CH_GAIN_t; + +/* Conversion result resolution */ +typedef enum ADC_RESOLUTION_enum +{ + ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ + ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ + ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ +} ADC_RESOLUTION_t; + +/* Voltage reference selection */ +typedef enum ADC_REFSEL_enum +{ + ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ + ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ + ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ + ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ + ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ +} ADC_REFSEL_t; + +/* Event channel input selection */ +typedef enum ADC_EVSEL_enum +{ + ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */ + ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */ + ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */ + ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */ +} ADC_EVSEL_t; + +/* Event action selection */ +typedef enum ADC_EVACT_enum +{ + ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ + ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ + ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ +} ADC_EVACT_t; + +/* Interupt mode */ +typedef enum ADC_CH_INTMODE_enum +{ + ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ + ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ + ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ +} ADC_CH_INTMODE_t; + +/* Interrupt level */ +typedef enum ADC_CH_INTLVL_enum +{ + ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ + ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ + ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ +} ADC_CH_INTLVL_t; + +/* Clock prescaler */ +typedef enum ADC_PRESCALER_enum +{ + ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ + ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ + ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ + ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ + ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ + ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ + ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ + ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ +} ADC_PRESCALER_t; + + +/* +-------------------------------------------------------------------------- +AC - Analog Comparator +-------------------------------------------------------------------------- +*/ + +/* Analog Comparator */ +typedef struct AC_struct +{ + register8_t AC0CTRL; /* Analog Comparator 0 Control */ + register8_t AC1CTRL; /* Analog Comparator 1 Control */ + register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ + register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t WINCTRL; /* Window Mode Control */ + register8_t STATUS; /* Status */ +} AC_t; + +/* Interrupt mode */ +typedef enum AC_INTMODE_enum +{ + AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ + AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ + AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ +} AC_INTMODE_t; + +/* Interrupt level */ +typedef enum AC_INTLVL_enum +{ + AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ + AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ + AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ + AC_INTLVL_HI_gc = (0x03<<4), /* High level */ +} AC_INTLVL_t; + +/* Hysteresis mode selection */ +typedef enum AC_HYSMODE_enum +{ + AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ + AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ + AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ +} AC_HYSMODE_t; + +/* Positive input multiplexer selection */ +typedef enum AC_MUXPOS_enum +{ + AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ + AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ + AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ + AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ + AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ + AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ + AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ +} AC_MUXPOS_t; + +/* Negative input multiplexer selection */ +typedef enum AC_MUXNEG_enum +{ + AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ + AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ + AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ + AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ + AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ + AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ + AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ +} AC_MUXNEG_t; + +/* Windows interrupt mode */ +typedef enum AC_WINTMODE_enum +{ + AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ + AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ + AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ + AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ +} AC_WINTMODE_t; + +/* Window interrupt level */ +typedef enum AC_WINTLVL_enum +{ + AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ + AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ + AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ +} AC_WINTLVL_t; + +/* Window mode state */ +typedef enum AC_WSTATE_enum +{ + AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ + AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ + AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ +} AC_WSTATE_t; + + +/* +-------------------------------------------------------------------------- +RTC - Real-Time Counter +-------------------------------------------------------------------------- +*/ + +/* Real-Time Counter */ +typedef struct RTC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary register */ + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + _WORDREGISTER(CNT); /* Count Register */ + _WORDREGISTER(PER); /* Period Register */ + _WORDREGISTER(COMP); /* Compare Register */ +} RTC_t; + +/* Prescaler Factor */ +typedef enum RTC_PRESCALER_enum +{ + RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ + RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ + RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ + RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ + RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ + RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ + RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ + RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ +} RTC_PRESCALER_t; + +/* Compare Interrupt level */ +typedef enum RTC_COMPINTLVL_enum +{ + RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ + RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ +} RTC_COMPINTLVL_t; + +/* Overflow Interrupt level */ +typedef enum RTC_OVFINTLVL_enum +{ + RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} RTC_OVFINTLVL_t; + + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* */ +typedef struct TWI_MASTER_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t STATUS; /* Status Register */ + register8_t BAUD; /* Baurd Rate Control Register */ + register8_t ADDR; /* Address Register */ + register8_t DATA; /* Data Register */ +} TWI_MASTER_t; + + +/* */ +typedef struct TWI_SLAVE_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t STATUS; /* Status Register */ + register8_t ADDR; /* Address Register */ + register8_t DATA; /* Data Register */ + register8_t ADDRMASK; /* Address Mask Register */ +} TWI_SLAVE_t; + + +/* Two-Wire Interface */ +typedef struct TWI_struct +{ + register8_t CTRL; /* TWI Common Control Register */ + TWI_MASTER_t MASTER; /* TWI master module */ + TWI_SLAVE_t SLAVE; /* TWI slave module */ +} TWI_t; + +/* SDA Hold Time */ +typedef enum TWI_SDAHOLD_enum +{ + TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */ + TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */ + TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */ + TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */ +} TWI_SDAHOLD_t; + +/* Master Interrupt Level */ +typedef enum TWI_MASTER_INTLVL_enum +{ + TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ + TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ +} TWI_MASTER_INTLVL_t; + +/* Inactive Timeout */ +typedef enum TWI_MASTER_TIMEOUT_enum +{ + TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ + TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ + TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ + TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +} TWI_MASTER_TIMEOUT_t; + +/* Master Command */ +typedef enum TWI_MASTER_CMD_enum +{ + TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ + TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ + TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +} TWI_MASTER_CMD_t; + +/* Master Bus State */ +typedef enum TWI_MASTER_BUSSTATE_enum +{ + TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ + TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ + TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ + TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +} TWI_MASTER_BUSSTATE_t; + +/* Slave Interrupt Level */ +typedef enum TWI_SLAVE_INTLVL_enum +{ + TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ + TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ +} TWI_SLAVE_INTLVL_t; + +/* Slave Command */ +typedef enum TWI_SLAVE_CMD_enum +{ + TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ + TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +} TWI_SLAVE_CMD_t; + + +/* +-------------------------------------------------------------------------- +USB - USB +-------------------------------------------------------------------------- +*/ + +/* USB Endpoint */ +typedef struct USB_EP_struct +{ + register8_t STATUS; /* Endpoint Status */ + register8_t CTRL; /* Endpoint Control */ + _WORDREGISTER(CNT); /* USB Endpoint Counter */ + _WORDREGISTER(DATAPTR); /* Data Pointer */ + _WORDREGISTER(AUXDATA); /* Auxiliary Data */ +} USB_EP_t; + + +/* Universal Serial Bus */ +typedef struct USB_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t STATUS; /* Status Register */ + register8_t ADDR; /* Address Register */ + register8_t FIFOWP; /* FIFO Write Pointer Register */ + register8_t FIFORP; /* FIFO Read Pointer Register */ + _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */ + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */ + register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */ + register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */ + register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + register8_t reserved_0x20; + register8_t reserved_0x21; + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + register8_t reserved_0x26; + register8_t reserved_0x27; + register8_t reserved_0x28; + register8_t reserved_0x29; + register8_t reserved_0x2A; + register8_t reserved_0x2B; + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t reserved_0x2E; + register8_t reserved_0x2F; + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + register8_t reserved_0x36; + register8_t reserved_0x37; + register8_t reserved_0x38; + register8_t reserved_0x39; + register8_t CAL0; /* Calibration Byte 0 */ + register8_t CAL1; /* Calibration Byte 1 */ +} USB_t; + + +/* USB Endpoint Table */ +typedef struct USB_EP_TABLE_struct +{ + USB_EP_t EP0OUT; /* Endpoint 0 */ + USB_EP_t EP0IN; /* Endpoint 0 */ + USB_EP_t EP1OUT; /* Endpoint 1 */ + USB_EP_t EP1IN; /* Endpoint 1 */ + USB_EP_t EP2OUT; /* Endpoint 2 */ + USB_EP_t EP2IN; /* Endpoint 2 */ + USB_EP_t EP3OUT; /* Endpoint 3 */ + USB_EP_t EP3IN; /* Endpoint 3 */ + USB_EP_t EP4OUT; /* Endpoint 4 */ + USB_EP_t EP4IN; /* Endpoint 4 */ + USB_EP_t EP5OUT; /* Endpoint 5 */ + USB_EP_t EP5IN; /* Endpoint 5 */ + USB_EP_t EP6OUT; /* Endpoint 6 */ + USB_EP_t EP6IN; /* Endpoint 6 */ + USB_EP_t EP7OUT; /* Endpoint 7 */ + USB_EP_t EP7IN; /* Endpoint 7 */ + USB_EP_t EP8OUT; /* Endpoint 8 */ + USB_EP_t EP8IN; /* Endpoint 8 */ + USB_EP_t EP9OUT; /* Endpoint 9 */ + USB_EP_t EP9IN; /* Endpoint 9 */ + USB_EP_t EP10OUT; /* Endpoint 10 */ + USB_EP_t EP10IN; /* Endpoint 10 */ + USB_EP_t EP11OUT; /* Endpoint 11 */ + USB_EP_t EP11IN; /* Endpoint 11 */ + USB_EP_t EP12OUT; /* Endpoint 12 */ + USB_EP_t EP12IN; /* Endpoint 12 */ + USB_EP_t EP13OUT; /* Endpoint 13 */ + USB_EP_t EP13IN; /* Endpoint 13 */ + USB_EP_t EP14OUT; /* Endpoint 14 */ + USB_EP_t EP14IN; /* Endpoint 14 */ + USB_EP_t EP15OUT; /* Endpoint 15 */ + USB_EP_t EP15IN; /* Endpoint 15 */ + register8_t reserved_0x100; + register8_t reserved_0x101; + register8_t reserved_0x102; + register8_t reserved_0x103; + register8_t reserved_0x104; + register8_t reserved_0x105; + register8_t reserved_0x106; + register8_t reserved_0x107; + register8_t reserved_0x108; + register8_t reserved_0x109; + register8_t reserved_0x10A; + register8_t reserved_0x10B; + register8_t reserved_0x10C; + register8_t reserved_0x10D; + register8_t reserved_0x10E; + register8_t reserved_0x10F; + register8_t FRAMENUML; /* Frame Number Low Byte */ + register8_t FRAMENUMH; /* Frame Number High Byte */ +} USB_EP_TABLE_t; + +/* Interrupt level */ +typedef enum USB_INTLVL_enum +{ + USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + USB_INTLVL_LO_gc = (0x01<<0), /* Low level */ + USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */ + USB_INTLVL_HI_gc = (0x03<<0), /* High level */ +} USB_INTLVL_t; + +/* USB Endpoint Type */ +typedef enum USB_EP_TYPE_enum +{ + USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */ + USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */ + USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */ + USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */ +} USB_EP_TYPE_t; + +/* USB Endpoint Buffersize */ +typedef enum USB_EP_BUFSIZE_enum +{ + USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */ + USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */ + USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */ + USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */ + USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */ + USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */ + USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */ + USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */ +} USB_EP_BUFSIZE_t; + + +/* +-------------------------------------------------------------------------- +PORT - I/O Port Configuration +-------------------------------------------------------------------------- +*/ + +/* I/O Ports */ +typedef struct PORT_struct +{ + register8_t DIR; /* I/O Port Data Direction */ + register8_t DIRSET; /* I/O Port Data Direction Set */ + register8_t DIRCLR; /* I/O Port Data Direction Clear */ + register8_t DIRTGL; /* I/O Port Data Direction Toggle */ + register8_t OUT; /* I/O Port Output */ + register8_t OUTSET; /* I/O Port Output Set */ + register8_t OUTCLR; /* I/O Port Output Clear */ + register8_t OUTTGL; /* I/O Port Output Toggle */ + register8_t IN; /* I/O port Input */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INT0MASK; /* Port Interrupt 0 Mask */ + register8_t INT1MASK; /* Port Interrupt 1 Mask */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t REMAP; /* I/O Port Pin Remap Register */ + register8_t reserved_0x0F; + register8_t PIN0CTRL; /* Pin 0 Control Register */ + register8_t PIN1CTRL; /* Pin 1 Control Register */ + register8_t PIN2CTRL; /* Pin 2 Control Register */ + register8_t PIN3CTRL; /* Pin 3 Control Register */ + register8_t PIN4CTRL; /* Pin 4 Control Register */ + register8_t PIN5CTRL; /* Pin 5 Control Register */ + register8_t PIN6CTRL; /* Pin 6 Control Register */ + register8_t PIN7CTRL; /* Pin 7 Control Register */ +} PORT_t; + +/* Port Interrupt 0 Level */ +typedef enum PORT_INT0LVL_enum +{ + PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ + PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ + PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ +} PORT_INT0LVL_t; + +/* Port Interrupt 1 Level */ +typedef enum PORT_INT1LVL_enum +{ + PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ + PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ + PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ +} PORT_INT1LVL_t; + +/* Output/Pull Configuration */ +typedef enum PORT_OPC_enum +{ + PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ + PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ + PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ + PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ + PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ + PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ + PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ + PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ +} PORT_OPC_t; + +/* Input/Sense Configuration */ +typedef enum PORT_ISC_enum +{ + PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ + PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ + PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ + PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ + PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ +} PORT_ISC_t; + + +/* +-------------------------------------------------------------------------- +TC - 16-bit Timer/Counter With PWM +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter 0 */ +typedef struct TC0_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t CTRLFCLR; /* Control Register F Clear */ + register8_t CTRLFSET; /* Control Register F Set */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G Set */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CCA); /* Compare or Capture A */ + _WORDREGISTER(CCB); /* Compare or Capture B */ + _WORDREGISTER(CCC); /* Compare or Capture C */ + _WORDREGISTER(CCD); /* Compare or Capture D */ + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ + _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ + _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ + _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ +} TC0_t; + + +/* 16-bit Timer/Counter 1 */ +typedef struct TC1_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t CTRLFCLR; /* Control Register F Clear */ + register8_t CTRLFSET; /* Control Register F Set */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G Set */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CCA); /* Compare or Capture A */ + _WORDREGISTER(CCB); /* Compare or Capture B */ + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t reserved_0x2E; + register8_t reserved_0x2F; + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ + _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ +} TC1_t; + +/* Clock Selection */ +typedef enum TC_CLKSEL_enum +{ + TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ + TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ + TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ + TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ + TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ + TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ + TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ + TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ + TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ + TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ + TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ +} TC_CLKSEL_t; + +/* Waveform Generation Mode */ +typedef enum TC_WGMODE_enum +{ + TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ + TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ + TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ + TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ + TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ + TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ + TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ + TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ + TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ + TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ +} TC_WGMODE_t; + +/* Byte Mode */ +typedef enum TC_BYTEM_enum +{ + TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ + TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ + TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */ +} TC_BYTEM_t; + +/* Event Action */ +typedef enum TC_EVACT_enum +{ + TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ + TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ + TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ + TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ + TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ + TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ + TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ +} TC_EVACT_t; + +/* Event Selection */ +typedef enum TC_EVSEL_enum +{ + TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ + TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ + TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ + TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ +} TC_EVSEL_t; + +/* Error Interrupt Level */ +typedef enum TC_ERRINTLVL_enum +{ + TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC_ERRINTLVL_t; + +/* Overflow Interrupt Level */ +typedef enum TC_OVFINTLVL_enum +{ + TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC_OVFINTLVL_t; + +/* Compare or Capture D Interrupt Level */ +typedef enum TC_CCDINTLVL_enum +{ + TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ + TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ +} TC_CCDINTLVL_t; + +/* Compare or Capture C Interrupt Level */ +typedef enum TC_CCCINTLVL_enum +{ + TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} TC_CCCINTLVL_t; + +/* Compare or Capture B Interrupt Level */ +typedef enum TC_CCBINTLVL_enum +{ + TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC_CCBINTLVL_t; + +/* Compare or Capture A Interrupt Level */ +typedef enum TC_CCAINTLVL_enum +{ + TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC_CCAINTLVL_t; + +/* Timer/Counter Command */ +typedef enum TC_CMD_enum +{ + TC_CMD_NONE_gc = (0x00<<2), /* No Command */ + TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TC_CMD_t; + + +/* +-------------------------------------------------------------------------- +TC2 - 16-bit Timer/Counter type 2 +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter type 2 */ +typedef struct TC2_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t reserved_0x03; + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t reserved_0x08; + register8_t CTRLF; /* Control Register F */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + register8_t LCNT; /* Low Byte Count */ + register8_t HCNT; /* High Byte Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + register8_t LPER; /* Low Byte Period */ + register8_t HPER; /* High Byte Period */ + register8_t LCMPA; /* Low Byte Compare A */ + register8_t HCMPA; /* High Byte Compare A */ + register8_t LCMPB; /* Low Byte Compare B */ + register8_t HCMPB; /* High Byte Compare B */ + register8_t LCMPC; /* Low Byte Compare C */ + register8_t HCMPC; /* High Byte Compare C */ + register8_t LCMPD; /* Low Byte Compare D */ + register8_t HCMPD; /* High Byte Compare D */ +} TC2_t; + +/* Clock Selection */ +typedef enum TC2_CLKSEL_enum +{ + TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ + TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ + TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ + TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ + TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ + TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ + TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ + TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ + TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ + TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ + TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ +} TC2_CLKSEL_t; + +/* Byte Mode */ +typedef enum TC2_BYTEM_enum +{ + TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ + TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */ + TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ +} TC2_BYTEM_t; + +/* High Byte Underflow Interrupt Level */ +typedef enum TC2_HUNFINTLVL_enum +{ + TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC2_HUNFINTLVL_t; + +/* Low Byte Underflow Interrupt Level */ +typedef enum TC2_LUNFINTLVL_enum +{ + TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC2_LUNFINTLVL_t; + +/* Low Byte Compare D Interrupt Level */ +typedef enum TC2_LCMPDINTLVL_enum +{ + TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */ + TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */ +} TC2_LCMPDINTLVL_t; + +/* Low Byte Compare C Interrupt Level */ +typedef enum TC2_LCMPCINTLVL_enum +{ + TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} TC2_LCMPCINTLVL_t; + +/* Low Byte Compare B Interrupt Level */ +typedef enum TC2_LCMPBINTLVL_enum +{ + TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC2_LCMPBINTLVL_t; + +/* Low Byte Compare A Interrupt Level */ +typedef enum TC2_LCMPAINTLVL_enum +{ + TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC2_LCMPAINTLVL_t; + +/* Timer/Counter Command */ +typedef enum TC2_CMD_enum +{ + TC2_CMD_NONE_gc = (0x00<<2), /* No Command */ + TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TC2_CMD_t; + +/* Timer/Counter Command */ +typedef enum TC2_CMDEN_enum +{ + TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */ + TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */ + TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */ +} TC2_CMDEN_t; + + +/* +-------------------------------------------------------------------------- +AWEX - Timer/Counter Advanced Waveform Extension +-------------------------------------------------------------------------- +*/ + +/* Advanced Waveform Extension */ +typedef struct AWEX_struct +{ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x01; + register8_t FDEMASK; /* Fault Detection Event Mask */ + register8_t FDCTRL; /* Fault Detection Control Register */ + register8_t STATUS; /* Status Register */ + register8_t STATUSSET; /* Status Set Register */ + register8_t DTBOTH; /* Dead Time Both Sides */ + register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ + register8_t DTLS; /* Dead Time Low Side */ + register8_t DTHS; /* Dead Time High Side */ + register8_t DTLSBUF; /* Dead Time Low Side Buffer */ + register8_t DTHSBUF; /* Dead Time High Side Buffer */ + register8_t OUTOVEN; /* Output Override Enable */ +} AWEX_t; + +/* Fault Detect Action */ +typedef enum AWEX_FDACT_enum +{ + AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ + AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ + AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ +} AWEX_FDACT_t; + + +/* +-------------------------------------------------------------------------- +HIRES - Timer/Counter High-Resolution Extension +-------------------------------------------------------------------------- +*/ + +/* High-Resolution Extension */ +typedef struct HIRES_struct +{ + register8_t CTRLA; /* Control Register */ +} HIRES_t; + +/* High Resolution Enable */ +typedef enum HIRES_HREN_enum +{ + HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ + HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ + HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ + HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ +} HIRES_HREN_t; + + +/* +-------------------------------------------------------------------------- +USART - Universal Asynchronous Receiver-Transmitter +-------------------------------------------------------------------------- +*/ + +/* Universal Synchronous/Asynchronous Receiver/Transmitter */ +typedef struct USART_struct +{ + register8_t DATA; /* Data Register */ + register8_t STATUS; /* Status Register */ + register8_t reserved_0x02; + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t BAUDCTRLA; /* Baud Rate Control Register A */ + register8_t BAUDCTRLB; /* Baud Rate Control Register B */ +} USART_t; + +/* Receive Complete Interrupt level */ +typedef enum USART_RXCINTLVL_enum +{ + USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} USART_RXCINTLVL_t; + +/* Transmit Complete Interrupt level */ +typedef enum USART_TXCINTLVL_enum +{ + USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ + USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ +} USART_TXCINTLVL_t; + +/* Data Register Empty Interrupt level */ +typedef enum USART_DREINTLVL_enum +{ + USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ + USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ +} USART_DREINTLVL_t; + +/* Character Size */ +typedef enum USART_CHSIZE_enum +{ + USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ + USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ + USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ + USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ + USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ +} USART_CHSIZE_t; + +/* Communication Mode */ +typedef enum USART_CMODE_enum +{ + USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ + USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ + USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ + USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +} USART_CMODE_t; + +/* Parity Mode */ +typedef enum USART_PMODE_enum +{ + USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ + USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ + USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +} USART_PMODE_t; + + +/* +-------------------------------------------------------------------------- +SPI - Serial Peripheral Interface +-------------------------------------------------------------------------- +*/ + +/* Serial Peripheral Interface */ +typedef struct SPI_struct +{ + register8_t CTRL; /* Control Register */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t STATUS; /* Status Register */ + register8_t DATA; /* Data Register */ +} SPI_t; + +/* SPI Mode */ +typedef enum SPI_MODE_enum +{ + SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ + SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ + SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ + SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ +} SPI_MODE_t; + +/* Prescaler setting */ +typedef enum SPI_PRESCALER_enum +{ + SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ + SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ + SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ + SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ +} SPI_PRESCALER_t; + +/* Interrupt level */ +typedef enum SPI_INTLVL_enum +{ + SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ + SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ + SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ +} SPI_INTLVL_t; + + +/* +-------------------------------------------------------------------------- +IRCOM - IR Communication Module +-------------------------------------------------------------------------- +*/ + +/* IR Communication Module */ +typedef struct IRCOM_struct +{ + register8_t CTRL; /* Control Register */ + register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ + register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ +} IRCOM_t; + +/* Event channel selection */ +typedef enum IRDA_EVSEL_enum +{ + IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ + IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ + IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ + IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ + IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ +} IRDA_EVSEL_t; + + +/* +-------------------------------------------------------------------------- +FUSE - Fuses and Lockbits +-------------------------------------------------------------------------- +*/ + +/* Fuses */ +typedef struct NVM_FUSES_struct +{ + register8_t reserved_0x00; + register8_t FUSEBYTE1; /* Watchdog Configuration */ + register8_t FUSEBYTE2; /* Reset Configuration */ + register8_t reserved_0x03; + register8_t FUSEBYTE4; /* Start-up Configuration */ + register8_t FUSEBYTE5; /* EESAVE and BOD Level */ +} NVM_FUSES_t; + +/* Boot Loader Section Reset Vector */ +typedef enum BOOTRST_enum +{ + BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ + BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ +} BOOTRST_t; + +/* Timer Oscillator pin location */ +typedef enum TOSCSEL_enum +{ + TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ + TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ +} TOSCSEL_t; + +/* BOD operation */ +typedef enum BOD_enum +{ + BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ + BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ + BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ +} BOD_t; + +/* BOD operation */ +typedef enum BODACT_enum +{ + BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ + BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ + BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ +} BODACT_t; + +/* Watchdog (Window) Timeout Period */ +typedef enum WD_enum +{ + WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ + WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ + WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ + WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ + WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ + WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ + WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ + WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ + WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ + WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ + WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ +} WD_t; + +/* Watchdog (Window) Timeout Period */ +typedef enum WDP_enum +{ + WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ + WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ + WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ + WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ + WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ + WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ + WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ + WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ + WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ + WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ + WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ +} WDP_t; + +/* Start-up Time */ +typedef enum SUT_enum +{ + SUT_0MS_gc = (0x03<<2), /* 0 ms */ + SUT_4MS_gc = (0x01<<2), /* 4 ms */ + SUT_64MS_gc = (0x00<<2), /* 64 ms */ +} SUT_t; + +/* Brownout Detection Voltage Level */ +typedef enum BODLVL_enum +{ + BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ + BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ + BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ + BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ + BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ + BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ + BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ + BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ +} BODLVL_t; + + +/* +-------------------------------------------------------------------------- +LOCKBIT - Fuses and Lockbits +-------------------------------------------------------------------------- +*/ + +/* Lock Bits */ +typedef struct NVM_LOCKBITS_struct +{ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ +} NVM_LOCKBITS_t; + +/* Boot lock bits - boot setcion */ +typedef enum FUSE_BLBB_enum +{ + FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ + FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ + FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ + FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ +} FUSE_BLBB_t; + +/* Boot lock bits - application section */ +typedef enum FUSE_BLBA_enum +{ + FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ + FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ + FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ + FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ +} FUSE_BLBA_t; + +/* Boot lock bits - application table section */ +typedef enum FUSE_BLBAT_enum +{ + FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ + FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ + FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ + FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ +} FUSE_BLBAT_t; + +/* Lock bits */ +typedef enum FUSE_LB_enum +{ + FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ + FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ + FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ +} FUSE_LB_t; + + +/* +-------------------------------------------------------------------------- +SIGROW - Signature Row +-------------------------------------------------------------------------- +*/ + +/* Production Signatures */ +typedef struct NVM_PROD_SIGNATURES_struct +{ + register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ + register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ + register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ + register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ + register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ + register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ + register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ + register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ + register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ + register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t WAFNUM; /* Wafer Number */ + register8_t reserved_0x11; + register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ + register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ + register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ + register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t USBCAL0; /* USB Calibration Byte 0 */ + register8_t USBCAL1; /* USB Calibration Byte 1 */ + register8_t USBRCOSC; /* USB RCOSC Calibration Value B */ + register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */ + register8_t reserved_0x1E; + register8_t reserved_0x1F; + register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ + register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + register8_t reserved_0x26; + register8_t reserved_0x27; + register8_t reserved_0x28; + register8_t reserved_0x29; + register8_t reserved_0x2A; + register8_t reserved_0x2B; + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ + register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + register8_t reserved_0x36; + register8_t reserved_0x37; + register8_t reserved_0x38; + register8_t reserved_0x39; + register8_t reserved_0x3A; + register8_t reserved_0x3B; + register8_t reserved_0x3C; + register8_t reserved_0x3D; + register8_t reserved_0x3E; + register8_t reserved_0x3F; +} NVM_PROD_SIGNATURES_t; + +/* +========================================================================== +IO Module Instances. Mapped to memory. +========================================================================== +*/ + +#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ +#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ +#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ +#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ +#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ +#define CLK (*(CLK_t *) 0x0040) /* Clock System */ +#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ +#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ +#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ +#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ +#define PR (*(PR_t *) 0x0070) /* Power Reduction */ +#define RST (*(RST_t *) 0x0078) /* Reset */ +#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ +#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ +#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ +#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ +#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ +#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ +#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ +#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ +#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ +#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ +#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */ +#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */ +#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ +#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ +#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ +#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ +#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ +#define PORTF (*(PORT_t *) 0x06A0) /* I/O Ports */ +#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ +#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ +#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */ +#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ +#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ +#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ +#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ +#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ +#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */ +#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */ +#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */ +#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ +#define TCE2 (*(TC2_t *) 0x0A00) /* 16-bit Timer/Counter type 2 */ +#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define TCF0 (*(TC0_t *) 0x0B00) /* 16-bit Timer/Counter 0 */ +#define TCF2 (*(TC2_t *) 0x0B00) /* 16-bit Timer/Counter type 2 */ + + +#endif /* !defined (__ASSEMBLER__) */ + + +/* ========== Flattened fully qualified IO register names ========== */ + +/* GPIO - General Purpose IO Registers */ +#define GPIO_GPIOR0 _SFR_MEM8(0x0000) +#define GPIO_GPIOR1 _SFR_MEM8(0x0001) +#define GPIO_GPIOR2 _SFR_MEM8(0x0002) +#define GPIO_GPIOR3 _SFR_MEM8(0x0003) + +/* Deprecated */ +#define GPIO_GPIO0 _SFR_MEM8(0x0000) +#define GPIO_GPIO1 _SFR_MEM8(0x0001) +#define GPIO_GPIO2 _SFR_MEM8(0x0002) +#define GPIO_GPIO3 _SFR_MEM8(0x0003) + +/* NVM_FUSES - Fuses */ +#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) +#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) +#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) +#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) + +/* NVM_LOCKBITS - Lock Bits */ +#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) + +/* NVM_PROD_SIGNATURES - Production Signatures */ +#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) +#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) +#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) +#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) +#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) +#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) +#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) +#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) +#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) +#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) +#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) +#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) +#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) +#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) +#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) +#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) +#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A) +#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B) +#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C) +#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D) +#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) +#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) +#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) +#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) + +/* VPORT - Virtual Port */ +#define VPORT0_DIR _SFR_MEM8(0x0010) +#define VPORT0_OUT _SFR_MEM8(0x0011) +#define VPORT0_IN _SFR_MEM8(0x0012) +#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) + +/* VPORT - Virtual Port */ +#define VPORT1_DIR _SFR_MEM8(0x0014) +#define VPORT1_OUT _SFR_MEM8(0x0015) +#define VPORT1_IN _SFR_MEM8(0x0016) +#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) + +/* VPORT - Virtual Port */ +#define VPORT2_DIR _SFR_MEM8(0x0018) +#define VPORT2_OUT _SFR_MEM8(0x0019) +#define VPORT2_IN _SFR_MEM8(0x001A) +#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) + +/* VPORT - Virtual Port */ +#define VPORT3_DIR _SFR_MEM8(0x001C) +#define VPORT3_OUT _SFR_MEM8(0x001D) +#define VPORT3_IN _SFR_MEM8(0x001E) +#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) + +/* OCD - On-Chip Debug System */ +#define OCD_OCDR0 _SFR_MEM8(0x002E) +#define OCD_OCDR1 _SFR_MEM8(0x002F) + +/* CPU - CPU registers */ +#define CPU_CCP _SFR_MEM8(0x0034) +#define CPU_RAMPD _SFR_MEM8(0x0038) +#define CPU_RAMPX _SFR_MEM8(0x0039) +#define CPU_RAMPY _SFR_MEM8(0x003A) +#define CPU_RAMPZ _SFR_MEM8(0x003B) +#define CPU_EIND _SFR_MEM8(0x003C) +#define CPU_SPL _SFR_MEM8(0x003D) +#define CPU_SPH _SFR_MEM8(0x003E) +#define CPU_SREG _SFR_MEM8(0x003F) + +/* CLK - Clock System */ +#define CLK_CTRL _SFR_MEM8(0x0040) +#define CLK_PSCTRL _SFR_MEM8(0x0041) +#define CLK_LOCK _SFR_MEM8(0x0042) +#define CLK_RTCCTRL _SFR_MEM8(0x0043) +#define CLK_USBCTRL _SFR_MEM8(0x0044) + +/* SLEEP - Sleep Controller */ +#define SLEEP_CTRL _SFR_MEM8(0x0048) + +/* OSC - Oscillator */ +#define OSC_CTRL _SFR_MEM8(0x0050) +#define OSC_STATUS _SFR_MEM8(0x0051) +#define OSC_XOSCCTRL _SFR_MEM8(0x0052) +#define OSC_XOSCFAIL _SFR_MEM8(0x0053) +#define OSC_RC32KCAL _SFR_MEM8(0x0054) +#define OSC_PLLCTRL _SFR_MEM8(0x0055) +#define OSC_DFLLCTRL _SFR_MEM8(0x0056) + +/* DFLL - DFLL */ +#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) +#define DFLLRC32M_CALA _SFR_MEM8(0x0062) +#define DFLLRC32M_CALB _SFR_MEM8(0x0063) +#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) +#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) +#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) + +/* DFLL - DFLL */ +#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) +#define DFLLRC2M_CALA _SFR_MEM8(0x006A) +#define DFLLRC2M_CALB _SFR_MEM8(0x006B) +#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) +#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) +#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) + +/* PR - Power Reduction */ +#define PR_PRGEN _SFR_MEM8(0x0070) +#define PR_PRPA _SFR_MEM8(0x0071) +#define PR_PRPC _SFR_MEM8(0x0073) +#define PR_PRPD _SFR_MEM8(0x0074) +#define PR_PRPE _SFR_MEM8(0x0075) +#define PR_PRPF _SFR_MEM8(0x0076) + +/* RST - Reset */ +#define RST_STATUS _SFR_MEM8(0x0078) +#define RST_CTRL _SFR_MEM8(0x0079) + +/* WDT - Watch-Dog Timer */ +#define WDT_CTRL _SFR_MEM8(0x0080) +#define WDT_WINCTRL _SFR_MEM8(0x0081) +#define WDT_STATUS _SFR_MEM8(0x0082) + +/* MCU - MCU Control */ +#define MCU_DEVID0 _SFR_MEM8(0x0090) +#define MCU_DEVID1 _SFR_MEM8(0x0091) +#define MCU_DEVID2 _SFR_MEM8(0x0092) +#define MCU_REVID _SFR_MEM8(0x0093) +#define MCU_ANAINIT _SFR_MEM8(0x0097) +#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) +#define MCU_AWEXLOCK _SFR_MEM8(0x0099) + +/* PMIC - Programmable Multi-level Interrupt Controller */ +#define PMIC_STATUS _SFR_MEM8(0x00A0) +#define PMIC_INTPRI _SFR_MEM8(0x00A1) +#define PMIC_CTRL _SFR_MEM8(0x00A2) + +/* PORTCFG - I/O port Configuration */ +#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) +#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) +#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) +#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) +#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) + +/* CRC - Cyclic Redundancy Checker */ +#define CRC_CTRL _SFR_MEM8(0x00D0) +#define CRC_STATUS _SFR_MEM8(0x00D1) +#define CRC_DATAIN _SFR_MEM8(0x00D3) +#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) +#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) +#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) +#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) + +/* EVSYS - Event System */ +#define EVSYS_CH0MUX _SFR_MEM8(0x0180) +#define EVSYS_CH1MUX _SFR_MEM8(0x0181) +#define EVSYS_CH2MUX _SFR_MEM8(0x0182) +#define EVSYS_CH3MUX _SFR_MEM8(0x0183) +#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) +#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) +#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) +#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) +#define EVSYS_STROBE _SFR_MEM8(0x0190) +#define EVSYS_DATA _SFR_MEM8(0x0191) + +/* NVM - Non-volatile Memory Controller */ +#define NVM_ADDR0 _SFR_MEM8(0x01C0) +#define NVM_ADDR1 _SFR_MEM8(0x01C1) +#define NVM_ADDR2 _SFR_MEM8(0x01C2) +#define NVM_DATA0 _SFR_MEM8(0x01C4) +#define NVM_DATA1 _SFR_MEM8(0x01C5) +#define NVM_DATA2 _SFR_MEM8(0x01C6) +#define NVM_CMD _SFR_MEM8(0x01CA) +#define NVM_CTRLA _SFR_MEM8(0x01CB) +#define NVM_CTRLB _SFR_MEM8(0x01CC) +#define NVM_INTCTRL _SFR_MEM8(0x01CD) +#define NVM_STATUS _SFR_MEM8(0x01CF) +#define NVM_LOCKBITS _SFR_MEM8(0x01D0) + +/* ADC - Analog-to-Digital Converter */ +#define ADCA_CTRLA _SFR_MEM8(0x0200) +#define ADCA_CTRLB _SFR_MEM8(0x0201) +#define ADCA_REFCTRL _SFR_MEM8(0x0202) +#define ADCA_EVCTRL _SFR_MEM8(0x0203) +#define ADCA_PRESCALER _SFR_MEM8(0x0204) +#define ADCA_INTFLAGS _SFR_MEM8(0x0206) +#define ADCA_TEMP _SFR_MEM8(0x0207) +#define ADCA_CAL _SFR_MEM16(0x020C) +#define ADCA_CH0RES _SFR_MEM16(0x0210) +#define ADCA_CMP _SFR_MEM16(0x0218) +#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) +#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) +#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) +#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) +#define ADCA_CH0_RES _SFR_MEM16(0x0224) +#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) + +/* AC - Analog Comparator */ +#define ACA_AC0CTRL _SFR_MEM8(0x0380) +#define ACA_AC1CTRL _SFR_MEM8(0x0381) +#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) +#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) +#define ACA_CTRLA _SFR_MEM8(0x0384) +#define ACA_CTRLB _SFR_MEM8(0x0385) +#define ACA_WINCTRL _SFR_MEM8(0x0386) +#define ACA_STATUS _SFR_MEM8(0x0387) + +/* RTC - Real-Time Counter */ +#define RTC_CTRL _SFR_MEM8(0x0400) +#define RTC_STATUS _SFR_MEM8(0x0401) +#define RTC_INTCTRL _SFR_MEM8(0x0402) +#define RTC_INTFLAGS _SFR_MEM8(0x0403) +#define RTC_TEMP _SFR_MEM8(0x0404) +#define RTC_CNT _SFR_MEM16(0x0408) +#define RTC_PER _SFR_MEM16(0x040A) +#define RTC_COMP _SFR_MEM16(0x040C) + +/* TWI - Two-Wire Interface */ +#define TWIC_CTRL _SFR_MEM8(0x0480) +#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) +#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) +#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) +#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) +#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) +#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) +#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) +#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) +#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) +#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) +#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) +#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) +#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) + +/* TWI - Two-Wire Interface */ +#define TWIE_CTRL _SFR_MEM8(0x04A0) +#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) +#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) +#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) +#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) +#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) +#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) +#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) +#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) +#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) +#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) +#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) +#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) +#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) + +/* USB - Universal Serial Bus */ +#define USB_CTRLA _SFR_MEM8(0x04C0) +#define USB_CTRLB _SFR_MEM8(0x04C1) +#define USB_STATUS _SFR_MEM8(0x04C2) +#define USB_ADDR _SFR_MEM8(0x04C3) +#define USB_FIFOWP _SFR_MEM8(0x04C4) +#define USB_FIFORP _SFR_MEM8(0x04C5) +#define USB_EPPTR _SFR_MEM16(0x04C6) +#define USB_INTCTRLA _SFR_MEM8(0x04C8) +#define USB_INTCTRLB _SFR_MEM8(0x04C9) +#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA) +#define USB_INTFLAGSASET _SFR_MEM8(0x04CB) +#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC) +#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD) +#define USB_CAL0 _SFR_MEM8(0x04FA) +#define USB_CAL1 _SFR_MEM8(0x04FB) + +/* PORT - I/O Ports */ +#define PORTA_DIR _SFR_MEM8(0x0600) +#define PORTA_DIRSET _SFR_MEM8(0x0601) +#define PORTA_DIRCLR _SFR_MEM8(0x0602) +#define PORTA_DIRTGL _SFR_MEM8(0x0603) +#define PORTA_OUT _SFR_MEM8(0x0604) +#define PORTA_OUTSET _SFR_MEM8(0x0605) +#define PORTA_OUTCLR _SFR_MEM8(0x0606) +#define PORTA_OUTTGL _SFR_MEM8(0x0607) +#define PORTA_IN _SFR_MEM8(0x0608) +#define PORTA_INTCTRL _SFR_MEM8(0x0609) +#define PORTA_INT0MASK _SFR_MEM8(0x060A) +#define PORTA_INT1MASK _SFR_MEM8(0x060B) +#define PORTA_INTFLAGS _SFR_MEM8(0x060C) +#define PORTA_REMAP _SFR_MEM8(0x060E) +#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) +#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) +#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) +#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) +#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) +#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) +#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) +#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) + +/* PORT - I/O Ports */ +#define PORTB_DIR _SFR_MEM8(0x0620) +#define PORTB_DIRSET _SFR_MEM8(0x0621) +#define PORTB_DIRCLR _SFR_MEM8(0x0622) +#define PORTB_DIRTGL _SFR_MEM8(0x0623) +#define PORTB_OUT _SFR_MEM8(0x0624) +#define PORTB_OUTSET _SFR_MEM8(0x0625) +#define PORTB_OUTCLR _SFR_MEM8(0x0626) +#define PORTB_OUTTGL _SFR_MEM8(0x0627) +#define PORTB_IN _SFR_MEM8(0x0628) +#define PORTB_INTCTRL _SFR_MEM8(0x0629) +#define PORTB_INT0MASK _SFR_MEM8(0x062A) +#define PORTB_INT1MASK _SFR_MEM8(0x062B) +#define PORTB_INTFLAGS _SFR_MEM8(0x062C) +#define PORTB_REMAP _SFR_MEM8(0x062E) +#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) +#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) +#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) +#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) +#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) +#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) +#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) +#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) + +/* PORT - I/O Ports */ +#define PORTC_DIR _SFR_MEM8(0x0640) +#define PORTC_DIRSET _SFR_MEM8(0x0641) +#define PORTC_DIRCLR _SFR_MEM8(0x0642) +#define PORTC_DIRTGL _SFR_MEM8(0x0643) +#define PORTC_OUT _SFR_MEM8(0x0644) +#define PORTC_OUTSET _SFR_MEM8(0x0645) +#define PORTC_OUTCLR _SFR_MEM8(0x0646) +#define PORTC_OUTTGL _SFR_MEM8(0x0647) +#define PORTC_IN _SFR_MEM8(0x0648) +#define PORTC_INTCTRL _SFR_MEM8(0x0649) +#define PORTC_INT0MASK _SFR_MEM8(0x064A) +#define PORTC_INT1MASK _SFR_MEM8(0x064B) +#define PORTC_INTFLAGS _SFR_MEM8(0x064C) +#define PORTC_REMAP _SFR_MEM8(0x064E) +#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) +#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) +#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) +#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) +#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) +#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) +#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) +#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) + +/* PORT - I/O Ports */ +#define PORTD_DIR _SFR_MEM8(0x0660) +#define PORTD_DIRSET _SFR_MEM8(0x0661) +#define PORTD_DIRCLR _SFR_MEM8(0x0662) +#define PORTD_DIRTGL _SFR_MEM8(0x0663) +#define PORTD_OUT _SFR_MEM8(0x0664) +#define PORTD_OUTSET _SFR_MEM8(0x0665) +#define PORTD_OUTCLR _SFR_MEM8(0x0666) +#define PORTD_OUTTGL _SFR_MEM8(0x0667) +#define PORTD_IN _SFR_MEM8(0x0668) +#define PORTD_INTCTRL _SFR_MEM8(0x0669) +#define PORTD_INT0MASK _SFR_MEM8(0x066A) +#define PORTD_INT1MASK _SFR_MEM8(0x066B) +#define PORTD_INTFLAGS _SFR_MEM8(0x066C) +#define PORTD_REMAP _SFR_MEM8(0x066E) +#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) +#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) +#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) +#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) +#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) +#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) +#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) +#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) + +/* PORT - I/O Ports */ +#define PORTE_DIR _SFR_MEM8(0x0680) +#define PORTE_DIRSET _SFR_MEM8(0x0681) +#define PORTE_DIRCLR _SFR_MEM8(0x0682) +#define PORTE_DIRTGL _SFR_MEM8(0x0683) +#define PORTE_OUT _SFR_MEM8(0x0684) +#define PORTE_OUTSET _SFR_MEM8(0x0685) +#define PORTE_OUTCLR _SFR_MEM8(0x0686) +#define PORTE_OUTTGL _SFR_MEM8(0x0687) +#define PORTE_IN _SFR_MEM8(0x0688) +#define PORTE_INTCTRL _SFR_MEM8(0x0689) +#define PORTE_INT0MASK _SFR_MEM8(0x068A) +#define PORTE_INT1MASK _SFR_MEM8(0x068B) +#define PORTE_INTFLAGS _SFR_MEM8(0x068C) +#define PORTE_REMAP _SFR_MEM8(0x068E) +#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) +#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) +#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) +#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) +#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) +#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) +#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) +#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) + +/* PORT - I/O Ports */ +#define PORTF_DIR _SFR_MEM8(0x06A0) +#define PORTF_DIRSET _SFR_MEM8(0x06A1) +#define PORTF_DIRCLR _SFR_MEM8(0x06A2) +#define PORTF_DIRTGL _SFR_MEM8(0x06A3) +#define PORTF_OUT _SFR_MEM8(0x06A4) +#define PORTF_OUTSET _SFR_MEM8(0x06A5) +#define PORTF_OUTCLR _SFR_MEM8(0x06A6) +#define PORTF_OUTTGL _SFR_MEM8(0x06A7) +#define PORTF_IN _SFR_MEM8(0x06A8) +#define PORTF_INTCTRL _SFR_MEM8(0x06A9) +#define PORTF_INT0MASK _SFR_MEM8(0x06AA) +#define PORTF_INT1MASK _SFR_MEM8(0x06AB) +#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) +#define PORTF_REMAP _SFR_MEM8(0x06AE) +#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) +#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) +#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) +#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) +#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) +#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) +#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) +#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) + +/* PORT - I/O Ports */ +#define PORTR_DIR _SFR_MEM8(0x07E0) +#define PORTR_DIRSET _SFR_MEM8(0x07E1) +#define PORTR_DIRCLR _SFR_MEM8(0x07E2) +#define PORTR_DIRTGL _SFR_MEM8(0x07E3) +#define PORTR_OUT _SFR_MEM8(0x07E4) +#define PORTR_OUTSET _SFR_MEM8(0x07E5) +#define PORTR_OUTCLR _SFR_MEM8(0x07E6) +#define PORTR_OUTTGL _SFR_MEM8(0x07E7) +#define PORTR_IN _SFR_MEM8(0x07E8) +#define PORTR_INTCTRL _SFR_MEM8(0x07E9) +#define PORTR_INT0MASK _SFR_MEM8(0x07EA) +#define PORTR_INT1MASK _SFR_MEM8(0x07EB) +#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) +#define PORTR_REMAP _SFR_MEM8(0x07EE) +#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) +#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) +#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) +#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) +#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) +#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) +#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) +#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) + +/* TC0 - 16-bit Timer/Counter 0 */ +#define TCC0_CTRLA _SFR_MEM8(0x0800) +#define TCC0_CTRLB _SFR_MEM8(0x0801) +#define TCC0_CTRLC _SFR_MEM8(0x0802) +#define TCC0_CTRLD _SFR_MEM8(0x0803) +#define TCC0_CTRLE _SFR_MEM8(0x0804) +#define TCC0_INTCTRLA _SFR_MEM8(0x0806) +#define TCC0_INTCTRLB _SFR_MEM8(0x0807) +#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) +#define TCC0_CTRLFSET _SFR_MEM8(0x0809) +#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) +#define TCC0_CTRLGSET _SFR_MEM8(0x080B) +#define TCC0_INTFLAGS _SFR_MEM8(0x080C) +#define TCC0_TEMP _SFR_MEM8(0x080F) +#define TCC0_CNT _SFR_MEM16(0x0820) +#define TCC0_PER _SFR_MEM16(0x0826) +#define TCC0_CCA _SFR_MEM16(0x0828) +#define TCC0_CCB _SFR_MEM16(0x082A) +#define TCC0_CCC _SFR_MEM16(0x082C) +#define TCC0_CCD _SFR_MEM16(0x082E) +#define TCC0_PERBUF _SFR_MEM16(0x0836) +#define TCC0_CCABUF _SFR_MEM16(0x0838) +#define TCC0_CCBBUF _SFR_MEM16(0x083A) +#define TCC0_CCCBUF _SFR_MEM16(0x083C) +#define TCC0_CCDBUF _SFR_MEM16(0x083E) + +/* TC2 - 16-bit Timer/Counter type 2 */ +#define TCC2_CTRLA _SFR_MEM8(0x0800) +#define TCC2_CTRLB _SFR_MEM8(0x0801) +#define TCC2_CTRLC _SFR_MEM8(0x0802) +#define TCC2_CTRLE _SFR_MEM8(0x0804) +#define TCC2_INTCTRLA _SFR_MEM8(0x0806) +#define TCC2_INTCTRLB _SFR_MEM8(0x0807) +#define TCC2_CTRLF _SFR_MEM8(0x0809) +#define TCC2_INTFLAGS _SFR_MEM8(0x080C) +#define TCC2_LCNT _SFR_MEM8(0x0820) +#define TCC2_HCNT _SFR_MEM8(0x0821) +#define TCC2_LPER _SFR_MEM8(0x0826) +#define TCC2_HPER _SFR_MEM8(0x0827) +#define TCC2_LCMPA _SFR_MEM8(0x0828) +#define TCC2_HCMPA _SFR_MEM8(0x0829) +#define TCC2_LCMPB _SFR_MEM8(0x082A) +#define TCC2_HCMPB _SFR_MEM8(0x082B) +#define TCC2_LCMPC _SFR_MEM8(0x082C) +#define TCC2_HCMPC _SFR_MEM8(0x082D) +#define TCC2_LCMPD _SFR_MEM8(0x082E) +#define TCC2_HCMPD _SFR_MEM8(0x082F) + +/* TC1 - 16-bit Timer/Counter 1 */ +#define TCC1_CTRLA _SFR_MEM8(0x0840) +#define TCC1_CTRLB _SFR_MEM8(0x0841) +#define TCC1_CTRLC _SFR_MEM8(0x0842) +#define TCC1_CTRLD _SFR_MEM8(0x0843) +#define TCC1_CTRLE _SFR_MEM8(0x0844) +#define TCC1_INTCTRLA _SFR_MEM8(0x0846) +#define TCC1_INTCTRLB _SFR_MEM8(0x0847) +#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) +#define TCC1_CTRLFSET _SFR_MEM8(0x0849) +#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) +#define TCC1_CTRLGSET _SFR_MEM8(0x084B) +#define TCC1_INTFLAGS _SFR_MEM8(0x084C) +#define TCC1_TEMP _SFR_MEM8(0x084F) +#define TCC1_CNT _SFR_MEM16(0x0860) +#define TCC1_PER _SFR_MEM16(0x0866) +#define TCC1_CCA _SFR_MEM16(0x0868) +#define TCC1_CCB _SFR_MEM16(0x086A) +#define TCC1_PERBUF _SFR_MEM16(0x0876) +#define TCC1_CCABUF _SFR_MEM16(0x0878) +#define TCC1_CCBBUF _SFR_MEM16(0x087A) + +/* AWEX - Advanced Waveform Extension */ +#define AWEXC_CTRL _SFR_MEM8(0x0880) +#define AWEXC_FDEMASK _SFR_MEM8(0x0882) +#define AWEXC_FDCTRL _SFR_MEM8(0x0883) +#define AWEXC_STATUS _SFR_MEM8(0x0884) +#define AWEXC_STATUSSET _SFR_MEM8(0x0885) +#define AWEXC_DTBOTH _SFR_MEM8(0x0886) +#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) +#define AWEXC_DTLS _SFR_MEM8(0x0888) +#define AWEXC_DTHS _SFR_MEM8(0x0889) +#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) +#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) +#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) + +/* HIRES - High-Resolution Extension */ +#define HIRESC_CTRLA _SFR_MEM8(0x0890) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTC0_DATA _SFR_MEM8(0x08A0) +#define USARTC0_STATUS _SFR_MEM8(0x08A1) +#define USARTC0_CTRLA _SFR_MEM8(0x08A3) +#define USARTC0_CTRLB _SFR_MEM8(0x08A4) +#define USARTC0_CTRLC _SFR_MEM8(0x08A5) +#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) +#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) + +/* SPI - Serial Peripheral Interface */ +#define SPIC_CTRL _SFR_MEM8(0x08C0) +#define SPIC_INTCTRL _SFR_MEM8(0x08C1) +#define SPIC_STATUS _SFR_MEM8(0x08C2) +#define SPIC_DATA _SFR_MEM8(0x08C3) + +/* IRCOM - IR Communication Module */ +#define IRCOM_CTRL _SFR_MEM8(0x08F8) +#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) +#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) + +/* TC0 - 16-bit Timer/Counter 0 */ +#define TCD0_CTRLA _SFR_MEM8(0x0900) +#define TCD0_CTRLB _SFR_MEM8(0x0901) +#define TCD0_CTRLC _SFR_MEM8(0x0902) +#define TCD0_CTRLD _SFR_MEM8(0x0903) +#define TCD0_CTRLE _SFR_MEM8(0x0904) +#define TCD0_INTCTRLA _SFR_MEM8(0x0906) +#define TCD0_INTCTRLB _SFR_MEM8(0x0907) +#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) +#define TCD0_CTRLFSET _SFR_MEM8(0x0909) +#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) +#define TCD0_CTRLGSET _SFR_MEM8(0x090B) +#define TCD0_INTFLAGS _SFR_MEM8(0x090C) +#define TCD0_TEMP _SFR_MEM8(0x090F) +#define TCD0_CNT _SFR_MEM16(0x0920) +#define TCD0_PER _SFR_MEM16(0x0926) +#define TCD0_CCA _SFR_MEM16(0x0928) +#define TCD0_CCB _SFR_MEM16(0x092A) +#define TCD0_CCC _SFR_MEM16(0x092C) +#define TCD0_CCD _SFR_MEM16(0x092E) +#define TCD0_PERBUF _SFR_MEM16(0x0936) +#define TCD0_CCABUF _SFR_MEM16(0x0938) +#define TCD0_CCBBUF _SFR_MEM16(0x093A) +#define TCD0_CCCBUF _SFR_MEM16(0x093C) +#define TCD0_CCDBUF _SFR_MEM16(0x093E) + +/* TC2 - 16-bit Timer/Counter type 2 */ +#define TCD2_CTRLA _SFR_MEM8(0x0900) +#define TCD2_CTRLB _SFR_MEM8(0x0901) +#define TCD2_CTRLC _SFR_MEM8(0x0902) +#define TCD2_CTRLE _SFR_MEM8(0x0904) +#define TCD2_INTCTRLA _SFR_MEM8(0x0906) +#define TCD2_INTCTRLB _SFR_MEM8(0x0907) +#define TCD2_CTRLF _SFR_MEM8(0x0909) +#define TCD2_INTFLAGS _SFR_MEM8(0x090C) +#define TCD2_LCNT _SFR_MEM8(0x0920) +#define TCD2_HCNT _SFR_MEM8(0x0921) +#define TCD2_LPER _SFR_MEM8(0x0926) +#define TCD2_HPER _SFR_MEM8(0x0927) +#define TCD2_LCMPA _SFR_MEM8(0x0928) +#define TCD2_HCMPA _SFR_MEM8(0x0929) +#define TCD2_LCMPB _SFR_MEM8(0x092A) +#define TCD2_HCMPB _SFR_MEM8(0x092B) +#define TCD2_LCMPC _SFR_MEM8(0x092C) +#define TCD2_HCMPC _SFR_MEM8(0x092D) +#define TCD2_LCMPD _SFR_MEM8(0x092E) +#define TCD2_HCMPD _SFR_MEM8(0x092F) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTD0_DATA _SFR_MEM8(0x09A0) +#define USARTD0_STATUS _SFR_MEM8(0x09A1) +#define USARTD0_CTRLA _SFR_MEM8(0x09A3) +#define USARTD0_CTRLB _SFR_MEM8(0x09A4) +#define USARTD0_CTRLC _SFR_MEM8(0x09A5) +#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) +#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) + +/* SPI - Serial Peripheral Interface */ +#define SPID_CTRL _SFR_MEM8(0x09C0) +#define SPID_INTCTRL _SFR_MEM8(0x09C1) +#define SPID_STATUS _SFR_MEM8(0x09C2) +#define SPID_DATA _SFR_MEM8(0x09C3) + +/* TC0 - 16-bit Timer/Counter 0 */ +#define TCE0_CTRLA _SFR_MEM8(0x0A00) +#define TCE0_CTRLB _SFR_MEM8(0x0A01) +#define TCE0_CTRLC _SFR_MEM8(0x0A02) +#define TCE0_CTRLD _SFR_MEM8(0x0A03) +#define TCE0_CTRLE _SFR_MEM8(0x0A04) +#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) +#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) +#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) +#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) +#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) +#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) +#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) +#define TCE0_TEMP _SFR_MEM8(0x0A0F) +#define TCE0_CNT _SFR_MEM16(0x0A20) +#define TCE0_PER _SFR_MEM16(0x0A26) +#define TCE0_CCA _SFR_MEM16(0x0A28) +#define TCE0_CCB _SFR_MEM16(0x0A2A) +#define TCE0_CCC _SFR_MEM16(0x0A2C) +#define TCE0_CCD _SFR_MEM16(0x0A2E) +#define TCE0_PERBUF _SFR_MEM16(0x0A36) +#define TCE0_CCABUF _SFR_MEM16(0x0A38) +#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) +#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) +#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) + +/* TC2 - 16-bit Timer/Counter type 2 */ +#define TCE2_CTRLA _SFR_MEM8(0x0A00) +#define TCE2_CTRLB _SFR_MEM8(0x0A01) +#define TCE2_CTRLC _SFR_MEM8(0x0A02) +#define TCE2_CTRLE _SFR_MEM8(0x0A04) +#define TCE2_INTCTRLA _SFR_MEM8(0x0A06) +#define TCE2_INTCTRLB _SFR_MEM8(0x0A07) +#define TCE2_CTRLF _SFR_MEM8(0x0A09) +#define TCE2_INTFLAGS _SFR_MEM8(0x0A0C) +#define TCE2_LCNT _SFR_MEM8(0x0A20) +#define TCE2_HCNT _SFR_MEM8(0x0A21) +#define TCE2_LPER _SFR_MEM8(0x0A26) +#define TCE2_HPER _SFR_MEM8(0x0A27) +#define TCE2_LCMPA _SFR_MEM8(0x0A28) +#define TCE2_HCMPA _SFR_MEM8(0x0A29) +#define TCE2_LCMPB _SFR_MEM8(0x0A2A) +#define TCE2_HCMPB _SFR_MEM8(0x0A2B) +#define TCE2_LCMPC _SFR_MEM8(0x0A2C) +#define TCE2_HCMPC _SFR_MEM8(0x0A2D) +#define TCE2_LCMPD _SFR_MEM8(0x0A2E) +#define TCE2_HCMPD _SFR_MEM8(0x0A2F) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTE0_DATA _SFR_MEM8(0x0AA0) +#define USARTE0_STATUS _SFR_MEM8(0x0AA1) +#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) +#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) +#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) +#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) +#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) + +/* TC0 - 16-bit Timer/Counter 0 */ +#define TCF0_CTRLA _SFR_MEM8(0x0B00) +#define TCF0_CTRLB _SFR_MEM8(0x0B01) +#define TCF0_CTRLC _SFR_MEM8(0x0B02) +#define TCF0_CTRLD _SFR_MEM8(0x0B03) +#define TCF0_CTRLE _SFR_MEM8(0x0B04) +#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) +#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) +#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) +#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) +#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) +#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) +#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) +#define TCF0_TEMP _SFR_MEM8(0x0B0F) +#define TCF0_CNT _SFR_MEM16(0x0B20) +#define TCF0_PER _SFR_MEM16(0x0B26) +#define TCF0_CCA _SFR_MEM16(0x0B28) +#define TCF0_CCB _SFR_MEM16(0x0B2A) +#define TCF0_CCC _SFR_MEM16(0x0B2C) +#define TCF0_CCD _SFR_MEM16(0x0B2E) +#define TCF0_PERBUF _SFR_MEM16(0x0B36) +#define TCF0_CCABUF _SFR_MEM16(0x0B38) +#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) +#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) +#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) + +/* TC2 - 16-bit Timer/Counter type 2 */ +#define TCF2_CTRLA _SFR_MEM8(0x0B00) +#define TCF2_CTRLB _SFR_MEM8(0x0B01) +#define TCF2_CTRLC _SFR_MEM8(0x0B02) +#define TCF2_CTRLE _SFR_MEM8(0x0B04) +#define TCF2_INTCTRLA _SFR_MEM8(0x0B06) +#define TCF2_INTCTRLB _SFR_MEM8(0x0B07) +#define TCF2_CTRLF _SFR_MEM8(0x0B09) +#define TCF2_INTFLAGS _SFR_MEM8(0x0B0C) +#define TCF2_LCNT _SFR_MEM8(0x0B20) +#define TCF2_HCNT _SFR_MEM8(0x0B21) +#define TCF2_LPER _SFR_MEM8(0x0B26) +#define TCF2_HPER _SFR_MEM8(0x0B27) +#define TCF2_LCMPA _SFR_MEM8(0x0B28) +#define TCF2_HCMPA _SFR_MEM8(0x0B29) +#define TCF2_LCMPB _SFR_MEM8(0x0B2A) +#define TCF2_HCMPB _SFR_MEM8(0x0B2B) +#define TCF2_LCMPC _SFR_MEM8(0x0B2C) +#define TCF2_HCMPC _SFR_MEM8(0x0B2D) +#define TCF2_LCMPD _SFR_MEM8(0x0B2E) +#define TCF2_HCMPD _SFR_MEM8(0x0B2F) + + + +/*================== Bitfield Definitions ================== */ + +/* VPORT - Virtual Ports */ +/* VPORT.INTFLAGS bit masks and bit positions */ +#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ + +#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ + +/* XOCD - On-Chip Debug System */ +/* OCD.OCDR0 bit masks and bit positions */ +#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ +#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ +#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ +#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ +#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ +#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ +#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ +#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ +#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ +#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ +#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ +#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ +#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ +#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ +#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ +#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ +#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ +#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ + +/* OCD.OCDR1 bit masks and bit positions */ +/* OCD_OCDRD Predefined. */ +/* OCD_OCDRD Predefined. */ + +/* CPU - CPU */ +/* CPU.CCP bit masks and bit positions */ +#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +#define CPU_CCP_gp 0 /* CCP signature group position. */ +#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ + +/* CPU.SREG bit masks and bit positions */ +#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ + +#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +#define CPU_T_bp 6 /* Transfer Bit bit position. */ + +#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +#define CPU_H_bp 5 /* Half Carry Flag bit position. */ + +#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ + +#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ + +#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +#define CPU_N_bp 2 /* Negative Flag bit position. */ + +#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +#define CPU_Z_bp 1 /* Zero Flag bit position. */ + +#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +#define CPU_C_bp 0 /* Carry Flag bit position. */ + +/* CLK - Clock System */ +/* CLK.CTRL bit masks and bit positions */ +#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ +#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ +#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ +#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ +#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ +#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ +#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ +#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ + +/* CLK.PSCTRL bit masks and bit positions */ +#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ +#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ +#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ +#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ +#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ +#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ +#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ +#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ +#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ +#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ +#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ +#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ + +#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ +#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ +#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ +#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ +#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ +#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ + +/* CLK.LOCK bit masks and bit positions */ +#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ +#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ + +/* CLK.RTCCTRL bit masks and bit positions */ +#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ +#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ +#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ +#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ +#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ +#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ +#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ +#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ + +#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ +#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ + +/* CLK.USBCTRL bit masks and bit positions */ +#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */ +#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */ +#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */ +#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */ +#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */ +#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */ +#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */ +#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */ + +#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */ +#define CLK_USBSRC_gp 1 /* Clock Source group position. */ +#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ +#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */ +#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ +#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */ + +#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */ +#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */ + +/* PR.PRGEN bit masks and bit positions */ +#define PR_USB_bm 0x40 /* USB bit mask. */ +#define PR_USB_bp 6 /* USB bit position. */ + +#define PR_AES_bm 0x10 /* AES bit mask. */ +#define PR_AES_bp 4 /* AES bit position. */ + +#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ +#define PR_RTC_bp 2 /* Real-time Counter bit position. */ + +#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ +#define PR_EVSYS_bp 1 /* Event System bit position. */ + +#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ +#define PR_DMA_bp 0 /* DMA-Controller bit position. */ + +/* PR.PRPA bit masks and bit positions */ +#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ +#define PR_ADC_bp 1 /* Port A ADC bit position. */ + +#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ +#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ + +/* PR.PRPC bit masks and bit positions */ +#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ +#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ + +#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ +#define PR_USART1_bp 5 /* Port C USART1 bit position. */ + +#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ +#define PR_USART0_bp 4 /* Port C USART0 bit position. */ + +#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ +#define PR_SPI_bp 3 /* Port C SPI bit position. */ + +#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ +#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ + +#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ +#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ + +#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ +#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ + +/* PR.PRPD bit masks and bit positions */ +/* PR_USART0 Predefined. */ +/* PR_USART0 Predefined. */ + +/* PR_SPI Predefined. */ +/* PR_SPI Predefined. */ + +/* PR_TC0 Predefined. */ +/* PR_TC0 Predefined. */ + +/* PR.PRPE bit masks and bit positions */ +/* PR_TWI Predefined. */ +/* PR_TWI Predefined. */ + +/* PR_USART0 Predefined. */ +/* PR_USART0 Predefined. */ + +/* PR_TC0 Predefined. */ +/* PR_TC0 Predefined. */ + +/* PR.PRPF bit masks and bit positions */ +/* PR_USART0 Predefined. */ +/* PR_USART0 Predefined. */ + +/* PR_TC0 Predefined. */ +/* PR_TC0 Predefined. */ + +/* SLEEP - Sleep Controller */ +/* SLEEP.CTRL bit masks and bit positions */ +#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ +#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ +#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ +#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ +#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ +#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ +#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ +#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ + +#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ +#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ + +/* OSC - Oscillator */ +/* OSC.CTRL bit masks and bit positions */ +#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ +#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ + +#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ +#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ + +#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ +#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ + +#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ +#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ + +#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ +#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ + +/* OSC.STATUS bit masks and bit positions */ +#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ +#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ + +#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ +#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ + +#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ +#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ + +#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ +#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ + +#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ +#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ + +/* OSC.XOSCCTRL bit masks and bit positions */ +#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ +#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ +#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ +#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ +#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ +#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ + +#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ +#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ + +#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ +#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ + +#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ +#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ +#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ +#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ +#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ +#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ +#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ +#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ +#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ +#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ + +/* OSC.XOSCFAIL bit masks and bit positions */ +#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ +#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ + +#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ +#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ + +#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ +#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ + +#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ +#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ + +/* OSC.PLLCTRL bit masks and bit positions */ +#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ +#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ +#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ +#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ +#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ +#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ + +#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ +#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ + +#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ +#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ +#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ +#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ +#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ +#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ +#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ +#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ +#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ +#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ +#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ +#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ + +/* OSC.DFLLCTRL bit masks and bit positions */ +#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ +#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ +#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ +#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ +#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ +#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ + +#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ +#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ + +/* DFLL - DFLL */ +/* DFLL.CTRL bit masks and bit positions */ +#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ +#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ + +/* DFLL.CALA bit masks and bit positions */ +#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ +#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ +#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ +#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ +#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ +#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ +#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ +#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ +#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ +#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ +#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ +#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ +#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ +#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ +#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ +#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ + +/* DFLL.CALB bit masks and bit positions */ +#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ +#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ +#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ +#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ +#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ +#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ +#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ +#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ +#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ +#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ +#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ +#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ +#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ +#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ + +/* RST - Reset */ +/* RST.STATUS bit masks and bit positions */ +#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ +#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ + +#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ +#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ + +#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ +#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ + +#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ +#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ + +#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ +#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ + +#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ +#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ + +#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ +#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ + +/* RST.CTRL bit masks and bit positions */ +#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ +#define RST_SWRST_bp 0 /* Software Reset bit position. */ + +/* WDT - Watch-Dog Timer */ +/* WDT.CTRL bit masks and bit positions */ +#define WDT_PER_gm 0x3C /* Period group mask. */ +#define WDT_PER_gp 2 /* Period group position. */ +#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ +#define WDT_PER0_bp 2 /* Period bit 0 position. */ +#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ +#define WDT_PER1_bp 3 /* Period bit 1 position. */ +#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ +#define WDT_PER2_bp 4 /* Period bit 2 position. */ +#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ +#define WDT_PER3_bp 5 /* Period bit 3 position. */ + +#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ +#define WDT_ENABLE_bp 1 /* Enable bit position. */ + +#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ +#define WDT_CEN_bp 0 /* Change Enable bit position. */ + +/* WDT.WINCTRL bit masks and bit positions */ +#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ +#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ +#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ +#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ +#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ +#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ +#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ +#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ +#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ +#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ + +#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ +#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ + +#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ +#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ + +/* WDT.STATUS bit masks and bit positions */ +#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ + +/* MCU - MCU Control */ +/* MCU.ANAINIT bit masks and bit positions */ +#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ +#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ +#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ +#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ +#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ +#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ + +/* MCU.EVSYSLOCK bit masks and bit positions */ +#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ +#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ + +/* MCU.AWEXLOCK bit masks and bit positions */ +#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ +#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ + +/* PMIC - Programmable Multi-level Interrupt Controller */ +/* PMIC.STATUS bit masks and bit positions */ +#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ + +#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ +#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ + +#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ +#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ + +#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ +#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ + +/* PMIC.INTPRI bit masks and bit positions */ +#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ +#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ +#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ +#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ +#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ +#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ +#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ +#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ +#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ +#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ +#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ +#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ +#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ +#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ +#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ +#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ +#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ +#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ + +/* PMIC.CTRL bit masks and bit positions */ +#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ +#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ + +#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ + +#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ +#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ + +#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ +#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ + +#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ +#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ + +/* PORTCFG - Port Configuration */ +/* PORTCFG.VPCTRLA bit masks and bit positions */ +#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ +#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ +#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ +#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ +#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ +#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ +#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ +#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ +#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ +#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ + +#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ +#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ +#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ +#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ +#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ +#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ +#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ +#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ +#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ +#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ + +/* PORTCFG.VPCTRLB bit masks and bit positions */ +#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ +#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ +#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ +#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ +#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ +#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ +#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ +#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ +#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ +#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ + +#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ +#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ +#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ +#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ +#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ +#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ +#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ +#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ +#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ +#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ + +/* PORTCFG.CLKEVOUT bit masks and bit positions */ +#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ +#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ +#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ +#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ +#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ +#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ + +#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ +#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ +#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ +#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ +#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ +#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ + +#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ +#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ +#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ +#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ +#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ +#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ + +#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ +#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ + +#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ +#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ + +/* PORTCFG.EVOUTSEL bit masks and bit positions */ +#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */ +#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */ +#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */ +#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */ +#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */ +#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */ +#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */ +#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */ + +/* CRC - Cyclic Redundancy Checker */ +/* CRC.CTRL bit masks and bit positions */ +#define CRC_RESET_gm 0xC0 /* Reset group mask. */ +#define CRC_RESET_gp 6 /* Reset group position. */ +#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ +#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ +#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ +#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ + +#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ +#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ + +#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ +#define CRC_SOURCE_gp 0 /* Input Source group position. */ +#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ +#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ +#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ +#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ +#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ +#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ +#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ +#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ + +/* CRC.STATUS bit masks and bit positions */ +#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ +#define CRC_ZERO_bp 1 /* Zero detection bit position. */ + +#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ +#define CRC_BUSY_bp 0 /* Busy bit position. */ + +/* EVSYS - Event System */ +/* EVSYS.CH0MUX bit masks and bit positions */ +#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ +#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ +#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ +#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ +#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ +#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ +#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ +#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ +#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ +#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ +#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ +#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ +#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ +#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ +#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ +#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ +#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ +#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ + +/* EVSYS.CH1MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH2MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH3MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH0CTRL bit masks and bit positions */ +#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ +#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ +#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ +#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ +#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ +#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ + +#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ +#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ + +#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ +#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ + +#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ +#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ +#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ +#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ +#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ +#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ +#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ +#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ + +/* EVSYS.CH1CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH2CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH3CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* NVM - Non Volatile Memory Controller */ +/* NVM.CMD bit masks and bit positions */ +#define NVM_CMD_gm 0x7F /* Command group mask. */ +#define NVM_CMD_gp 0 /* Command group position. */ +#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define NVM_CMD0_bp 0 /* Command bit 0 position. */ +#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define NVM_CMD1_bp 1 /* Command bit 1 position. */ +#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ +#define NVM_CMD2_bp 2 /* Command bit 2 position. */ +#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ +#define NVM_CMD3_bp 3 /* Command bit 3 position. */ +#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ +#define NVM_CMD4_bp 4 /* Command bit 4 position. */ +#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ +#define NVM_CMD5_bp 5 /* Command bit 5 position. */ +#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ +#define NVM_CMD6_bp 6 /* Command bit 6 position. */ + +/* NVM.CTRLA bit masks and bit positions */ +#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ +#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ + +/* NVM.CTRLB bit masks and bit positions */ +#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ +#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ + +#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ +#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ + +#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ +#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ + +#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ +#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ + +/* NVM.INTCTRL bit masks and bit positions */ +#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ +#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ +#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ +#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ +#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ +#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ + +#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ +#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ +#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ +#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ +#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ +#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ + +/* NVM.STATUS bit masks and bit positions */ +#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ +#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ + +#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ +#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ + +#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ +#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ + +#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ +#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ + +/* NVM.LOCKBITS bit masks and bit positions */ +#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ + +#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ + +#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ + +#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ +#define NVM_LB_gp 0 /* Lock Bits group position. */ +#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ + +/* ADC - Analog/Digital Converter */ +/* ADC_CH.CTRL bit masks and bit positions */ +#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ +#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ + +#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ +#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ +#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ +#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ +#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ +#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ +#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ +#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ + +#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ +#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ +#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ +#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ +#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ +#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ + +/* ADC_CH.MUXCTRL bit masks and bit positions */ +#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ +#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ +#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ +#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ +#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ +#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ +#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ +#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ +#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ +#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ + +#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ +#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ +#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ +#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ +#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ +#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ +#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ +#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ +#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ +#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ + +#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC input group mask. */ +#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ +#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ +#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ +#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ +#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ + +/* ADC_CH.INTCTRL bit masks and bit positions */ +#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ +#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ +#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ +#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ +#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ +#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ + +#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ +#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ +#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ +#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ +#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ +#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ + +/* ADC_CH.INTFLAGS bit masks and bit positions */ +#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ +#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ + +/* ADC_CH.SCAN bit masks and bit positions */ +#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ +#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ +#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ +#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ +#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ +#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ +#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ +#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ +#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ +#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ + +#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */ +#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */ +#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ +#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */ +#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ +#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */ +#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ +#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */ +#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ +#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */ + +/* ADC.CTRLA bit masks and bit positions */ +#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ +#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ + +#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ +#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ + +#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ +#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ + +/* ADC.CTRLB bit masks and bit positions */ +#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ +#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ +#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ +#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ +#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ +#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ + +#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ +#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ + +#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ +#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ + +#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ +#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ +#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ +#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ +#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ +#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ + +/* ADC.REFCTRL bit masks and bit positions */ +#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ +#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ +#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ +#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ + +#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ +#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ + +#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ +#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ + +/* ADC.EVCTRL bit masks and bit positions */ +#define ADC_EVSEL_gm 0x18 /* Event Input Select group mask. */ +#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ +#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ +#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ +#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ +#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ + +#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ +#define ADC_EVACT_gp 0 /* Event Action Select group position. */ +#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ +#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ +#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ +#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ +#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ +#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ + +/* ADC.PRESCALER bit masks and bit positions */ +#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ +#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ +#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ +#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ +#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ +#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ +#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ +#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ + +/* ADC.INTFLAGS bit masks and bit positions */ +#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ +#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ + +/* AC - Analog Comparator */ +/* AC.AC0CTRL bit masks and bit positions */ +#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ +#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ +#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ +#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ +#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ +#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ + +#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ +#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ +#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ +#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ +#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ +#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ + +#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ + +#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define AC_ENABLE_bp 0 /* Enable bit position. */ + +/* AC.AC1CTRL bit masks and bit positions */ +/* AC_INTMODE Predefined. */ +/* AC_INTMODE Predefined. */ + +/* AC_INTLVL Predefined. */ +/* AC_INTLVL Predefined. */ + +/* AC_HYSMODE Predefined. */ +/* AC_HYSMODE Predefined. */ + +/* AC_ENABLE Predefined. */ +/* AC_ENABLE Predefined. */ + +/* AC.AC0MUXCTRL bit masks and bit positions */ +#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ +#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ +#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ +#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ +#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ +#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ +#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ +#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ + +#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ +#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ +#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ +#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ +#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ +#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ +#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ +#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ + +/* AC.AC1MUXCTRL bit masks and bit positions */ +/* AC_MUXPOS Predefined. */ +/* AC_MUXPOS Predefined. */ + +/* AC_MUXNEG Predefined. */ +/* AC_MUXNEG Predefined. */ + +/* AC.CTRLA bit masks and bit positions */ +#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ +#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ + +#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ +#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ + +/* AC.CTRLB bit masks and bit positions */ +#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ +#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ +#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ +#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ +#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ +#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ +#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ +#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ +#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ +#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ +#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ +#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ +#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ +#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ + +/* AC.WINCTRL bit masks and bit positions */ +#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ +#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ + +#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ +#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ +#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ +#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ +#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ +#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ + +#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ +#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ +#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ +#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ +#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ +#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ + +/* AC.STATUS bit masks and bit positions */ +#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ +#define AC_WSTATE_gp 6 /* Window Mode State group position. */ +#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ +#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ +#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ +#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ + +#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ +#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ + +#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ +#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ + +#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ +#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ + +#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ +#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ + +#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ +#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ + +/* RTC - Real-Time Counter */ +/* RTC.CTRL bit masks and bit positions */ +#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ +#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ +#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ +#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ +#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ +#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ +#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ +#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ + +/* RTC.STATUS bit masks and bit positions */ +#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ +#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ + +/* RTC.INTCTRL bit masks and bit positions */ +#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ +#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ +#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ +#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ +#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ +#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ + +#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ +#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ +#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ +#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ +#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ +#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ + +/* RTC.INTFLAGS bit masks and bit positions */ +#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ +#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ + +#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + +/* TWI - Two-Wire Interface */ +/* TWI_MASTER.CTRLA bit masks and bit positions */ +#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ +#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ + +#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ +#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ + +#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ +#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ + +#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ +#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ + +/* TWI_MASTER.CTRLB bit masks and bit positions */ +#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ + +#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ +#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ + +#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ + +/* TWI_MASTER.CTRLC bit masks and bit positions */ +#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ + +#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ +#define TWI_MASTER_CMD_gp 0 /* Command group position. */ +#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ +#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ + +/* TWI_MASTER.STATUS bit masks and bit positions */ +#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ + +#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ + +#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ + +#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ + +#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ + +#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ + +#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ +#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ +#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ + +/* TWI_SLAVE.CTRLA bit masks and bit positions */ +#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ +#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ + +#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ +#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ + +#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ +#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ + +#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ +#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ + +#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ +#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ + +#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ +#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ + +#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ + +/* TWI_SLAVE.CTRLB bit masks and bit positions */ +#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ + +#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ +#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ +#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ +#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ + +/* TWI_SLAVE.STATUS bit masks and bit positions */ +#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ + +#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ + +#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ + +#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ + +#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ +#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ + +#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ + +#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ + +#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ + +/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ +#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ +#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ + +#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ +#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ + +/* TWI.CTRL bit masks and bit positions */ +#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ +#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ +#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ +#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ +#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ +#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ + +#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ +#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ + +/* USB - USB */ +/* USB_EP.STATUS bit masks and bit positions */ +#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */ +#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */ + +#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */ +#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */ + +#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */ +#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */ + +#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */ +#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */ + +#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */ +#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */ + +#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */ +#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */ + +#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */ +#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */ + +#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */ +#define USB_EP_BANK_bp 3 /* Bank Select bit position. */ + +#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */ +#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */ + +#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */ +#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */ + +#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */ +#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */ + +/* USB_EP.CTRL bit masks and bit positions */ +#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */ +#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */ +#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */ +#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */ +#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */ +#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */ + +#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */ +#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */ + +#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */ +#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */ + +#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */ +#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */ + +#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */ +#define USB_EP_STALL_bp 2 /* Data Stall bit position. */ + +#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */ +#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */ +#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */ +#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */ +#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */ +#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */ +#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */ +#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */ + +/* USB_EP.CNT bit masks and bit positions */ +#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */ +#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */ + +/* USB.CTRLA bit masks and bit positions */ +#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */ +#define USB_ENABLE_bp 7 /* USB Enable bit position. */ + +#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */ +#define USB_SPEED_bp 6 /* Speed Select bit position. */ + +#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */ +#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */ + +#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */ +#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */ + +#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */ +#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */ +#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */ +#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */ +#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */ +#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */ +#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */ +#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */ +#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */ +#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */ + +/* USB.CTRLB bit masks and bit positions */ +#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */ +#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */ + +#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */ +#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */ + +#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */ +#define USB_GNACK_bp 1 /* Global NACK bit position. */ + +#define USB_ATTACH_bm 0x01 /* Attach bit mask. */ +#define USB_ATTACH_bp 0 /* Attach bit position. */ + +/* USB.STATUS bit masks and bit positions */ +#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */ +#define USB_URESUME_bp 3 /* Upstream Resume bit position. */ + +#define USB_RESUME_bm 0x04 /* Resume bit mask. */ +#define USB_RESUME_bp 2 /* Resume bit position. */ + +#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */ +#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */ + +#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */ +#define USB_BUSRST_bp 0 /* Bus Reset bit position. */ + +/* USB.ADDR bit masks and bit positions */ +#define USB_ADDR_gm 0x7F /* Device Address group mask. */ +#define USB_ADDR_gp 0 /* Device Address group position. */ +#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */ +#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */ +#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */ +#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */ +#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */ +#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */ +#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */ +#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */ +#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */ +#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */ +#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */ +#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */ +#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */ +#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */ + +/* USB.FIFOWP bit masks and bit positions */ +#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */ +#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */ +#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */ +#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */ +#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */ +#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */ +#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */ +#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */ +#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */ +#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */ +#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */ +#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */ + +/* USB.FIFORP bit masks and bit positions */ +#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */ +#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */ +#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */ +#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */ +#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */ +#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */ +#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */ +#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */ +#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */ +#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */ +#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */ +#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */ + +/* USB.INTCTRLA bit masks and bit positions */ +#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */ +#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */ + +#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */ +#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */ + +#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */ +#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */ + +#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */ +#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */ + +#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */ +#define USB_INTLVL_gp 0 /* Interrupt Level group position. */ +#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ +#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ +#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ +#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ + +/* USB.INTCTRLB bit masks and bit positions */ +#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */ +#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */ + +#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */ +#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */ + +/* USB.INTFLAGSACLR bit masks and bit positions */ +#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */ +#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */ + +#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */ +#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */ + +#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */ +#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */ + +#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */ +#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */ + +#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */ +#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */ + +#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */ +#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */ + +#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */ +#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */ + +#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */ +#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */ + +/* USB.INTFLAGSASET bit masks and bit positions */ +/* USB_SOFIF Predefined. */ +/* USB_SOFIF Predefined. */ + +/* USB_SUSPENDIF Predefined. */ +/* USB_SUSPENDIF Predefined. */ + +/* USB_RESUMEIF Predefined. */ +/* USB_RESUMEIF Predefined. */ + +/* USB_RSTIF Predefined. */ +/* USB_RSTIF Predefined. */ + +/* USB_CRCIF Predefined. */ +/* USB_CRCIF Predefined. */ + +/* USB_UNFIF Predefined. */ +/* USB_UNFIF Predefined. */ + +/* USB_OVFIF Predefined. */ +/* USB_OVFIF Predefined. */ + +/* USB_STALLIF Predefined. */ +/* USB_STALLIF Predefined. */ + +/* USB.INTFLAGSBCLR bit masks and bit positions */ +#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */ +#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */ + +#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */ +#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */ + +/* USB.INTFLAGSBSET bit masks and bit positions */ +/* USB_TRNIF Predefined. */ +/* USB_TRNIF Predefined. */ + +/* USB_SETUPIF Predefined. */ +/* USB_SETUPIF Predefined. */ + +/* PORT - I/O Port Configuration */ +/* PORT.INTCTRL bit masks and bit positions */ +#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ +#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ +#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ +#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ +#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ +#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ + +#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ +#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ +#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ +#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ +#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ +#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ + +/* PORT.INTFLAGS bit masks and bit positions */ +#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ + +#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ + +/* PORT.REMAP bit masks and bit positions */ +#define PORT_SPI_bm 0x20 /* SPI bit mask. */ +#define PORT_SPI_bp 5 /* SPI bit position. */ + +#define PORT_USART0_bm 0x10 /* USART0 bit mask. */ +#define PORT_USART0_bp 4 /* USART0 bit position. */ + +#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ +#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ + +#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ +#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ + +#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ +#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ + +#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ +#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ + +/* PORT.PIN0CTRL bit masks and bit positions */ +#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ +#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ + +#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ +#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ + +#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ +#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ +#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ +#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ +#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ +#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ +#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ +#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ + +#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ + +/* PORT.PIN1CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN2CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN3CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN4CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN5CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN6CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN7CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* TC - 16-bit Timer/Counter With PWM */ +/* TC0.CTRLA bit masks and bit positions */ +#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + +/* TC0.CTRLB bit masks and bit positions */ +#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ +#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ + +#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ +#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ + +#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ + +#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ + +#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ + +/* TC0.CTRLC bit masks and bit positions */ +#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ +#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ + +#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ +#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ + +#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ + +#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ + +/* TC0.CTRLD bit masks and bit positions */ +#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ +#define TC0_EVACT_gp 5 /* Event Action group position. */ +#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ +#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ +#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ + +#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ +#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ + +#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ +#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ +#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ + +/* TC0.CTRLE bit masks and bit positions */ +#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ +#define TC0_BYTEM_gp 0 /* Byte Mode group position. */ +#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ +#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ +#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ +#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ + +/* TC0.INTCTRLA bit masks and bit positions */ +#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ + +#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ + +/* TC0.INTCTRLB bit masks and bit positions */ +#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ +#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ +#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ +#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ +#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ +#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ + +#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ +#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ +#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ +#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ +#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ +#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ + +#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ + +#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ + +/* TC0.CTRLFCLR bit masks and bit positions */ +#define TC0_CMD_gm 0x0C /* Command group mask. */ +#define TC0_CMD_gp 2 /* Command group position. */ +#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC0_CMD0_bp 2 /* Command bit 0 position. */ +#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC0_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TC0_LUPD_bp 1 /* Lock Update bit position. */ + +#define TC0_DIR_bm 0x01 /* Direction bit mask. */ +#define TC0_DIR_bp 0 /* Direction bit position. */ + +/* TC0.CTRLFSET bit masks and bit positions */ +/* TC0_CMD Predefined. */ +/* TC0_CMD Predefined. */ + +/* TC0_LUPD Predefined. */ +/* TC0_LUPD Predefined. */ + +/* TC0_DIR Predefined. */ +/* TC0_DIR Predefined. */ + +/* TC0.CTRLGCLR bit masks and bit positions */ +#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ +#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ + +#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ +#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ + +#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ + +#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ + +#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ + +/* TC0.CTRLGSET bit masks and bit positions */ +/* TC0_CCDBV Predefined. */ +/* TC0_CCDBV Predefined. */ + +/* TC0_CCCBV Predefined. */ +/* TC0_CCCBV Predefined. */ + +/* TC0_CCBBV Predefined. */ +/* TC0_CCBBV Predefined. */ + +/* TC0_CCABV Predefined. */ +/* TC0_CCABV Predefined. */ + +/* TC0_PERBV Predefined. */ +/* TC0_PERBV Predefined. */ + +/* TC0.INTFLAGS bit masks and bit positions */ +#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ +#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ + +#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ +#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ + +#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ + +#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ + +#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ + +#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + +/* TC1.CTRLA bit masks and bit positions */ +#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + +/* TC1.CTRLB bit masks and bit positions */ +#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ + +#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ + +#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ + +/* TC1.CTRLC bit masks and bit positions */ +#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ + +#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ + +/* TC1.CTRLD bit masks and bit positions */ +#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ +#define TC1_EVACT_gp 5 /* Event Action group position. */ +#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ +#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ +#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ + +#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ +#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ + +#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ +#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ +#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ + +/* TC1.CTRLE bit masks and bit positions */ +#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ +#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ + +/* TC1.INTCTRLA bit masks and bit positions */ +#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ + +#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ + +/* TC1.INTCTRLB bit masks and bit positions */ +#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ + +#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ + +/* TC1.CTRLFCLR bit masks and bit positions */ +#define TC1_CMD_gm 0x0C /* Command group mask. */ +#define TC1_CMD_gp 2 /* Command group position. */ +#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC1_CMD0_bp 2 /* Command bit 0 position. */ +#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC1_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TC1_LUPD_bp 1 /* Lock Update bit position. */ + +#define TC1_DIR_bm 0x01 /* Direction bit mask. */ +#define TC1_DIR_bp 0 /* Direction bit position. */ + +/* TC1.CTRLFSET bit masks and bit positions */ +/* TC1_CMD Predefined. */ +/* TC1_CMD Predefined. */ + +/* TC1_LUPD Predefined. */ +/* TC1_LUPD Predefined. */ + +/* TC1_DIR Predefined. */ +/* TC1_DIR Predefined. */ + +/* TC1.CTRLGCLR bit masks and bit positions */ +#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ + +#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ + +#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ + +/* TC1.CTRLGSET bit masks and bit positions */ +/* TC1_CCBBV Predefined. */ +/* TC1_CCBBV Predefined. */ + +/* TC1_CCABV Predefined. */ +/* TC1_CCABV Predefined. */ + +/* TC1_PERBV Predefined. */ +/* TC1_PERBV Predefined. */ + +/* TC1.INTFLAGS bit masks and bit positions */ +#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ + +#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ + +#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ + +#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + +/* TC2 - 16-bit Timer/Counter type 2 */ +/* TC2.CTRLA bit masks and bit positions */ +#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + +/* TC2.CTRLB bit masks and bit positions */ +#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */ +#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */ + +#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */ +#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */ + +#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */ +#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */ + +#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */ +#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */ + +#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */ +#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */ + +#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */ +#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */ + +#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */ +#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */ + +#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */ +#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */ + +/* TC2.CTRLC bit masks and bit positions */ +#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */ +#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */ + +#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */ +#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */ + +#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */ +#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */ + +#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */ +#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */ + +#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */ +#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */ + +#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */ +#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */ + +#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */ +#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */ + +#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */ +#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */ + +/* TC2.CTRLE bit masks and bit positions */ +#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */ +#define TC2_BYTEM_gp 0 /* Byte Mode group position. */ +#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ +#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ +#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ +#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ + +/* TC2.INTCTRLA bit masks and bit positions */ +#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */ +#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */ +#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */ +#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */ +#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */ +#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */ + +#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */ +#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */ +#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */ +#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */ +#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */ +#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */ + +/* TC2.INTCTRLB bit masks and bit positions */ +#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */ +#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */ +#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */ +#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */ +#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */ +#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */ + +#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */ +#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */ +#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */ +#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */ +#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */ +#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */ + +#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */ +#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */ +#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */ +#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */ +#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */ +#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */ + +#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */ +#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */ +#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */ +#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */ +#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */ +#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */ + +/* TC2.CTRLF bit masks and bit positions */ +#define TC2_CMD_gm 0x0C /* Command group mask. */ +#define TC2_CMD_gp 2 /* Command group position. */ +#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC2_CMD0_bp 2 /* Command bit 0 position. */ +#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC2_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */ +#define TC2_CMDEN_gp 0 /* Command Enable group position. */ +#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */ +#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */ +#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */ +#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */ + +/* TC2.INTFLAGS bit masks and bit positions */ +#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */ +#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */ + +#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */ +#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */ + +#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */ +#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */ + +#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */ +#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */ + +#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */ +#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */ + +#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */ +#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */ + +/* AWEX - Timer/Counter Advanced Waveform Extension */ +/* AWEX.CTRL bit masks and bit positions */ +#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ +#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ + +#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ +#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ + +#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ +#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ + +#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ +#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ + +#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ +#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ + +#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ +#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ + +/* AWEX.FDCTRL bit masks and bit positions */ +#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ +#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ + +#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ +#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ + +#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ +#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ +#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ +#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ +#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ +#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ + +/* AWEX.STATUS bit masks and bit positions */ +#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ +#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ + +#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ +#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ + +#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ +#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ + +/* AWEX.STATUSSET bit masks and bit positions */ +/* AWEX_FDF Predefined. */ +/* AWEX_FDF Predefined. */ + +/* AWEX_DTHSBUFV Predefined. */ +/* AWEX_DTHSBUFV Predefined. */ + +/* AWEX_DTLSBUFV Predefined. */ +/* AWEX_DTLSBUFV Predefined. */ + +/* HIRES - Timer/Counter High-Resolution Extension */ +/* HIRES.CTRLA bit masks and bit positions */ +#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ +#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ +#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ +#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ +#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ +#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ + +/* USART - Universal Asynchronous Receiver-Transmitter */ +/* USART.STATUS bit masks and bit positions */ +#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ +#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ + +#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ + +#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ + +#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ +#define USART_FERR_bp 4 /* Frame Error bit position. */ + +#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ +#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ + +#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ +#define USART_PERR_bp 2 /* Parity Error bit position. */ + +#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ +#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ + +/* USART.CTRLA bit masks and bit positions */ +#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ +#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ +#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ +#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ +#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ +#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ + +#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ +#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ +#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ +#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ +#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ +#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ + +#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ +#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ +#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ +#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ +#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ +#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ + +/* USART.CTRLB bit masks and bit positions */ +#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ +#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ + +#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ +#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ + +#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ +#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ + +#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ +#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ + +#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ +#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ + +/* USART.CTRLC bit masks and bit positions */ +#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +#define USART_CMODE_gp 6 /* Communication Mode group position. */ +#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ + +#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +#define USART_PMODE_gp 4 /* Parity Mode group position. */ +#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ + +#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ + +#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +#define USART_CHSIZE_gp 0 /* Character Size group position. */ +#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ + +/* USART.BAUDCTRLA bit masks and bit positions */ +#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ +#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ +#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ +#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ +#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ +#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ +#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ +#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ +#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ +#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ +#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ +#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ +#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ +#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ +#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ +#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ +#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ +#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ + +/* USART.BAUDCTRLB bit masks and bit positions */ +#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ +#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ +#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ +#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ +#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ +#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ +#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ +#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ +#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ +#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ + +/* USART_BSEL Predefined. */ +/* USART_BSEL Predefined. */ + +/* SPI - Serial Peripheral Interface */ +/* SPI.CTRL bit masks and bit positions */ +#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ +#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ + +#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ +#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ + +#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ +#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ + +#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ +#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ + +#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ +#define SPI_MODE_gp 2 /* SPI Mode group position. */ +#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ +#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ +#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ +#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ + +#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ +#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ +#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ +#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ +#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ +#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ + +/* SPI.INTCTRL bit masks and bit positions */ +#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ +#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ +#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ +#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ +#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ +#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ + +/* SPI.STATUS bit masks and bit positions */ +#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ +#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ + +#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ +#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ + +/* IRCOM - IR Communication Module */ +/* IRCOM.CTRL bit masks and bit positions */ +#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ +#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ +#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ +#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ +#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ +#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ +#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ +#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ +#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ +#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ + +/* FUSE - Fuses and Lockbits */ +/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ +#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ +#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ + +#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ +#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ +#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ + +/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ +#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ +#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ + +#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ +#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ + +#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ +#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ +#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ +#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ +#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ +#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ + +/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ +#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ +#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ + +#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ +#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ +#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ +#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ +#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ +#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ + +#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ +#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ + +/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ +#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ +#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ +#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ +#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ +#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ +#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ + +#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ +#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ + +#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ +#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ +#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ +#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ +#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ +#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ +#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ +#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ + +/* LOCKBIT - Fuses and Lockbits */ +/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ +#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ + +#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ +#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ +#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ + + + +// Generic Port Pins + +#define PIN0_bm 0x01 +#define PIN0_bp 0 +#define PIN1_bm 0x02 +#define PIN1_bp 1 +#define PIN2_bm 0x04 +#define PIN2_bp 2 +#define PIN3_bm 0x08 +#define PIN3_bp 3 +#define PIN4_bm 0x10 +#define PIN4_bp 4 +#define PIN5_bm 0x20 +#define PIN5_bp 5 +#define PIN6_bm 0x40 +#define PIN6_bp 6 +#define PIN7_bm 0x80 +#define PIN7_bp 7 + +/* ========== Interrupt Vector Definitions ========== */ +/* Vector 0 is the reset vector */ + +/* OSC interrupt vectors */ +#define OSC_OSCF_vect_num 1 +#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ + +/* PORTC interrupt vectors */ +#define PORTC_INT0_vect_num 2 +#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ +#define PORTC_INT1_vect_num 3 +#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ + +/* PORTR interrupt vectors */ +#define PORTR_INT0_vect_num 4 +#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ +#define PORTR_INT1_vect_num 5 +#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ + +/* RTC interrupt vectors */ +#define RTC_OVF_vect_num 10 +#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ +#define RTC_COMP_vect_num 11 +#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ + +/* TWIC interrupt vectors */ +#define TWIC_TWIS_vect_num 12 +#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ +#define TWIC_TWIM_vect_num 13 +#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_OVF_vect_num 14 +#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LUNF_vect_num 14 +#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_ERR_vect_num 15 +#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_HUNF_vect_num 15 +#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_CCA_vect_num 16 +#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LCMPA_vect_num 16 +#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_CCB_vect_num 17 +#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LCMPB_vect_num 17 +#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_CCC_vect_num 18 +#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LCMPC_vect_num 18 +#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_CCD_vect_num 19 +#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LCMPD_vect_num 19 +#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */ + +/* TCC1 interrupt vectors */ +#define TCC1_OVF_vect_num 20 +#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ +#define TCC1_ERR_vect_num 21 +#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ +#define TCC1_CCA_vect_num 22 +#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ +#define TCC1_CCB_vect_num 23 +#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ + +/* SPIC interrupt vectors */ +#define SPIC_INT_vect_num 24 +#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ + +/* USARTC0 interrupt vectors */ +#define USARTC0_RXC_vect_num 25 +#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ +#define USARTC0_DRE_vect_num 26 +#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ +#define USARTC0_TXC_vect_num 27 +#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ + +/* NVM interrupt vectors */ +#define NVM_EE_vect_num 32 +#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ +#define NVM_SPM_vect_num 33 +#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ + +/* PORTB interrupt vectors */ +#define PORTB_INT0_vect_num 34 +#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ +#define PORTB_INT1_vect_num 35 +#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ + +/* PORTE interrupt vectors */ +#define PORTE_INT0_vect_num 43 +#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ +#define PORTE_INT1_vect_num 44 +#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ + +/* TWIE interrupt vectors */ +#define TWIE_TWIS_vect_num 45 +#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ +#define TWIE_TWIM_vect_num 46 +#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_OVF_vect_num 47 +#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_LUNF_vect_num 47 +#define TCE2_LUNF_vect _VECTOR(47) /* Low Byte Underflow Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_ERR_vect_num 48 +#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_HUNF_vect_num 48 +#define TCE2_HUNF_vect _VECTOR(48) /* High Byte Underflow Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_CCA_vect_num 49 +#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_LCMPA_vect_num 49 +#define TCE2_LCMPA_vect _VECTOR(49) /* Low Byte Compare A Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_CCB_vect_num 50 +#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_LCMPB_vect_num 50 +#define TCE2_LCMPB_vect _VECTOR(50) /* Low Byte Compare B Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_CCC_vect_num 51 +#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_LCMPC_vect_num 51 +#define TCE2_LCMPC_vect _VECTOR(51) /* Low Byte Compare C Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_CCD_vect_num 52 +#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_LCMPD_vect_num 52 +#define TCE2_LCMPD_vect _VECTOR(52) /* Low Byte Compare D Interrupt */ + +/* USARTE0 interrupt vectors */ +#define USARTE0_RXC_vect_num 58 +#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ +#define USARTE0_DRE_vect_num 59 +#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ +#define USARTE0_TXC_vect_num 60 +#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ + +/* PORTD interrupt vectors */ +#define PORTD_INT0_vect_num 64 +#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ +#define PORTD_INT1_vect_num 65 +#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ + +/* PORTA interrupt vectors */ +#define PORTA_INT0_vect_num 66 +#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ +#define PORTA_INT1_vect_num 67 +#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ + +/* ACA interrupt vectors */ +#define ACA_AC0_vect_num 68 +#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ +#define ACA_AC1_vect_num 69 +#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ +#define ACA_ACW_vect_num 70 +#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ + +/* ADCA interrupt vectors */ +#define ADCA_CH0_vect_num 71 +#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ + +/* TCD0 interrupt vectors */ +#define TCD0_OVF_vect_num 77 +#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LUNF_vect_num 77 +#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_ERR_vect_num 78 +#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_HUNF_vect_num 78 +#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_CCA_vect_num 79 +#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LCMPA_vect_num 79 +#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_CCB_vect_num 80 +#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LCMPB_vect_num 80 +#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_CCC_vect_num 81 +#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LCMPC_vect_num 81 +#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_CCD_vect_num 82 +#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LCMPD_vect_num 82 +#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */ + +/* SPID interrupt vectors */ +#define SPID_INT_vect_num 87 +#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ + +/* USARTD0 interrupt vectors */ +#define USARTD0_RXC_vect_num 88 +#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ +#define USARTD0_DRE_vect_num 89 +#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ +#define USARTD0_TXC_vect_num 90 +#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ + +/* PORTF interrupt vectors */ +#define PORTF_INT0_vect_num 104 +#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ +#define PORTF_INT1_vect_num 105 +#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ + +/* TCF0 interrupt vectors */ +#define TCF0_OVF_vect_num 108 +#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ + +/* TCF2 interrupt vectors */ +#define TCF2_LUNF_vect_num 108 +#define TCF2_LUNF_vect _VECTOR(108) /* Low Byte Underflow Interrupt */ + +/* TCF0 interrupt vectors */ +#define TCF0_ERR_vect_num 109 +#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ + +/* TCF2 interrupt vectors */ +#define TCF2_HUNF_vect_num 109 +#define TCF2_HUNF_vect _VECTOR(109) /* High Byte Underflow Interrupt */ + +/* TCF0 interrupt vectors */ +#define TCF0_CCA_vect_num 110 +#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ + +/* TCF2 interrupt vectors */ +#define TCF2_LCMPA_vect_num 110 +#define TCF2_LCMPA_vect _VECTOR(110) /* Low Byte Compare A Interrupt */ + +/* TCF0 interrupt vectors */ +#define TCF0_CCB_vect_num 111 +#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ + +/* TCF2 interrupt vectors */ +#define TCF2_LCMPB_vect_num 111 +#define TCF2_LCMPB_vect _VECTOR(111) /* Low Byte Compare B Interrupt */ + +/* TCF0 interrupt vectors */ +#define TCF0_CCC_vect_num 112 +#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ + +/* TCF2 interrupt vectors */ +#define TCF2_LCMPC_vect_num 112 +#define TCF2_LCMPC_vect _VECTOR(112) /* Low Byte Compare C Interrupt */ + +/* TCF0 interrupt vectors */ +#define TCF0_CCD_vect_num 113 +#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ + +/* TCF2 interrupt vectors */ +#define TCF2_LCMPD_vect_num 113 +#define TCF2_LCMPD_vect _VECTOR(113) /* Low Byte Compare D Interrupt */ + +/* USB interrupt vectors */ +#define USB_BUSEVENT_vect_num 125 +#define USB_BUSEVENT_vect _VECTOR(125) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */ +#define USB_TRNCOMPL_vect_num 126 +#define USB_TRNCOMPL_vect _VECTOR(126) /* Transaction complete interrupt */ + +#define _VECTOR_SIZE 4 /* Size of individual vector. */ +#define _VECTORS_SIZE (127 * _VECTOR_SIZE) + + +/* ========== Constants ========== */ + +#define PROGMEM_START (0x0000) +#define PROGMEM_SIZE (36864) +#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) + +#define APP_SECTION_START (0x0000) +#define APP_SECTION_SIZE (32768) +#define APP_SECTION_PAGE_SIZE (256) +#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) + +#define APPTABLE_SECTION_START (0x7000) +#define APPTABLE_SECTION_SIZE (4096) +#define APPTABLE_SECTION_PAGE_SIZE (256) +#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) + +#define BOOT_SECTION_START (0x8000) +#define BOOT_SECTION_SIZE (4096) +#define BOOT_SECTION_PAGE_SIZE (256) +#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) + +#define DATAMEM_START (0x0000) +#define DATAMEM_SIZE (12288) +#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) + +#define IO_START (0x0000) +#define IO_SIZE (4096) +#define IO_PAGE_SIZE (0) +#define IO_END (IO_START + IO_SIZE - 1) + +#define MAPPED_EEPROM_START (0x1000) +#define MAPPED_EEPROM_SIZE (1024) +#define MAPPED_EEPROM_PAGE_SIZE (0) +#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) + +#define INTERNAL_SRAM_START (0x2000) +#define INTERNAL_SRAM_SIZE (4096) +#define INTERNAL_SRAM_PAGE_SIZE (0) +#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) + +#define EEPROM_START (0x0000) +#define EEPROM_SIZE (1024) +#define EEPROM_PAGE_SIZE (32) +#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) + +#define SIGNATURES_START (0x0000) +#define SIGNATURES_SIZE (3) +#define SIGNATURES_PAGE_SIZE (0) +#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) + +#define FUSES_START (0x0000) +#define FUSES_SIZE (6) +#define FUSES_PAGE_SIZE (0) +#define FUSES_END (FUSES_START + FUSES_SIZE - 1) + +#define LOCKBITS_START (0x0000) +#define LOCKBITS_SIZE (1) +#define LOCKBITS_PAGE_SIZE (0) +#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) + +#define USER_SIGNATURES_START (0x0000) +#define USER_SIGNATURES_SIZE (256) +#define USER_SIGNATURES_PAGE_SIZE (256) +#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) + +#define PROD_SIGNATURES_START (0x0000) +#define PROD_SIGNATURES_SIZE (64) +#define PROD_SIGNATURES_PAGE_SIZE (256) +#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) + +#define FLASHSTART PROGMEM_START +#define FLASHEND PROGMEM_END +#define SPM_PAGESIZE 256 +#define RAMSTART INTERNAL_SRAM_START +#define RAMSIZE INTERNAL_SRAM_SIZE +#define RAMEND INTERNAL_SRAM_END +#define E2END EEPROM_END +#define E2PAGESIZE EEPROM_PAGE_SIZE + + +/* ========== Fuses ========== */ +#define FUSE_MEMORY_SIZE 6 + +/* Fuse Byte 0 Reserved */ + +/* Fuse Byte 1 */ +#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ +#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ +#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ +#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ +#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +#define FUSE1_DEFAULT (0xFF) + +/* Fuse Byte 2 */ +#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ +#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ +#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ +#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ +#define FUSE2_DEFAULT (0xFF) + +/* Fuse Byte 3 Reserved */ + +/* Fuse Byte 4 */ +#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ +#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ +#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ +#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ +#define FUSE4_DEFAULT (0xFF) + +/* Fuse Byte 5 */ +#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ +#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ +#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ +#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ +#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ +#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ +#define FUSE5_DEFAULT (0xFF) + +/* ========== Lock Bits ========== */ +#define __LOCK_BITS_EXIST +#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST +#define __BOOT_LOCK_APPLICATION_BITS_EXIST +#define __BOOT_LOCK_BOOT_BITS_EXIST + +/* ========== Signature ========== */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x95 +#define SIGNATURE_2 0x49 + +/* ========== Power Reduction Condition Definitions ========== */ + +/* PR.PRGEN */ +#define __AVR_HAVE_PRGEN (PR_USB_bm|PR_AES_bm|PR_RTC_bm|PR_EVSYS_bm|PR_DMA_bm) +#define __AVR_HAVE_PRGEN_USB +#define __AVR_HAVE_PRGEN_AES +#define __AVR_HAVE_PRGEN_RTC +#define __AVR_HAVE_PRGEN_EVSYS +#define __AVR_HAVE_PRGEN_DMA + +/* PR.PRPA */ +#define __AVR_HAVE_PRPA (PR_ADC_bm|PR_AC_bm) +#define __AVR_HAVE_PRPA_ADC +#define __AVR_HAVE_PRPA_AC + +/* PR.PRPC */ +#define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPC_TWI +#define __AVR_HAVE_PRPC_USART1 +#define __AVR_HAVE_PRPC_USART0 +#define __AVR_HAVE_PRPC_SPI +#define __AVR_HAVE_PRPC_HIRES +#define __AVR_HAVE_PRPC_TC1 +#define __AVR_HAVE_PRPC_TC0 + +/* PR.PRPD */ +#define __AVR_HAVE_PRPD (PR_USART0_bm|PR_SPI_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPD_USART0 +#define __AVR_HAVE_PRPD_SPI +#define __AVR_HAVE_PRPD_TC0 + +/* PR.PRPE */ +#define __AVR_HAVE_PRPE (PR_TWI_bm|PR_USART0_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPE_TWI +#define __AVR_HAVE_PRPE_USART0 +#define __AVR_HAVE_PRPE_TC0 + +/* PR.PRPF */ +#define __AVR_HAVE_PRPF (PR_USART0_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPF_USART0 +#define __AVR_HAVE_PRPF_TC0 + + +#endif /* #ifdef _AVR_ATXMEGA32C3_H_INCLUDED */ diff --git a/include/avr/iox32c4.h b/include/avr/iox32c4.h index 0a8f92a1..806d7178 100644 --- a/include/avr/iox32c4.h +++ b/include/avr/iox32c4.h @@ -6078,4 +6078,3 @@ IO Module Instances. Mapped to memory. #endif /* #ifdef _AVR_ATXMEGA32C4_H_INCLUDED */ - diff --git a/include/avr/iox32d3.h b/include/avr/iox32d3.h index 85df1686..173814e9 100644 --- a/include/avr/iox32d3.h +++ b/include/avr/iox32d3.h @@ -1,5105 +1,5104 @@ -/***************************************************************************** - * - * Copyright (C) 2016 Atmel Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * * Neither the name of the copyright holders nor the names of - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************/ - - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iox32d3.h" -#else -# error "Attempt to include more than one file." -#endif - -#ifndef _AVR_ATXMEGA32D3_H_INCLUDED -#define _AVR_ATXMEGA32D3_H_INCLUDED - -/* Ungrouped common registers */ -#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ - -/* Deprecated */ -#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ - -#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ -#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ -#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ -#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ -#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ -#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ -#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ -#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ -#define SREG _SFR_MEM8(0x003F) /* Status Register */ - -/* C Language Only */ -#if !defined (__ASSEMBLER__) - -#include - -typedef volatile uint8_t register8_t; -typedef volatile uint16_t register16_t; -typedef volatile uint32_t register32_t; - - -#ifdef _WORDREGISTER -#undef _WORDREGISTER -#endif -#define _WORDREGISTER(regname) \ - __extension__ union \ - { \ - register16_t regname; \ - struct \ - { \ - register8_t regname ## L; \ - register8_t regname ## H; \ - }; \ - } - -#ifdef _DWORDREGISTER -#undef _DWORDREGISTER -#endif -#define _DWORDREGISTER(regname) \ - __extension__ union \ - { \ - register32_t regname; \ - struct \ - { \ - register8_t regname ## 0; \ - register8_t regname ## 1; \ - register8_t regname ## 2; \ - register8_t regname ## 3; \ - }; \ - } - - -/* -========================================================================== -IO Module Structures -========================================================================== -*/ - - -/* --------------------------------------------------------------------------- -XOCD - On-Chip Debug System --------------------------------------------------------------------------- -*/ - -/* On-Chip Debug System */ -typedef struct OCD_struct -{ - register8_t OCDR0; /* OCD Register 0 */ - register8_t OCDR1; /* OCD Register 1 */ -} OCD_t; - - -/* --------------------------------------------------------------------------- -CPU - CPU --------------------------------------------------------------------------- -*/ - -/* CCP signatures */ -typedef enum CCP_enum -{ - CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ - CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ -} CCP_t; - - -/* --------------------------------------------------------------------------- -CLK - Clock System --------------------------------------------------------------------------- -*/ - -/* Clock System */ -typedef struct CLK_struct -{ - register8_t CTRL; /* Control Register */ - register8_t PSCTRL; /* Prescaler Control Register */ - register8_t LOCK; /* Lock register */ - register8_t RTCCTRL; /* RTC Control Register */ - register8_t reserved_0x04; -} CLK_t; - - -/* Power Reduction */ -typedef struct PR_struct -{ - register8_t PRGEN; /* General Power Reduction */ - register8_t PRPA; /* Power Reduction Port A */ - register8_t reserved_0x02; - register8_t PRPC; /* Power Reduction Port C */ - register8_t PRPD; /* Power Reduction Port D */ - register8_t PRPE; /* Power Reduction Port E */ - register8_t PRPF; /* Power Reduction Port F */ -} PR_t; - -/* System Clock Selection */ -typedef enum CLK_SCLKSEL_enum -{ - CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ - CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ - CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ - CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ - CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ -} CLK_SCLKSEL_t; - -/* Prescaler A Division Factor */ -typedef enum CLK_PSADIV_enum -{ - CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ - CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ - CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ - CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ - CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ - CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ - CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ - CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ - CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ - CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ -} CLK_PSADIV_t; - -/* Prescaler B and C Division Factor */ -typedef enum CLK_PSBCDIV_enum -{ - CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ - CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ - CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ - CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ -} CLK_PSBCDIV_t; - -/* RTC Clock Source */ -typedef enum CLK_RTCSRC_enum -{ - CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1 kHz from internal 32kHz ULP */ - CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ - CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from 32.768 kHz internal oscillator */ - CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ - CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from 32.768 kHz internal oscillator */ - CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ -} CLK_RTCSRC_t; - - -/* --------------------------------------------------------------------------- -SLEEP - Sleep Controller --------------------------------------------------------------------------- -*/ - -/* Sleep Controller */ -typedef struct SLEEP_struct -{ - register8_t CTRL; /* Control Register */ -} SLEEP_t; - -/* Sleep Mode */ -typedef enum SLEEP_SMODE_enum -{ - SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ - SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ - SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ - SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ - SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ -} SLEEP_SMODE_t; - - - -#define SLEEP_MODE_IDLE (0x00<<1) -#define SLEEP_MODE_PWR_DOWN (0x02<<1) -#define SLEEP_MODE_PWR_SAVE (0x03<<1) -#define SLEEP_MODE_STANDBY (0x06<<1) -#define SLEEP_MODE_EXT_STANDBY (0x07<<1) -/* --------------------------------------------------------------------------- -OSC - Oscillator --------------------------------------------------------------------------- -*/ - -/* Oscillator */ -typedef struct OSC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t XOSCCTRL; /* External Oscillator Control Register */ - register8_t XOSCFAIL; /* External Oscillator Failure Detection Register */ - register8_t RC32KCAL; /* 32kHz Internal Oscillator Calibration Register */ - register8_t PLLCTRL; /* PLL Control REgister */ - register8_t DFLLCTRL; /* DFLL Control Register */ -} OSC_t; - -/* Oscillator Frequency Range */ -typedef enum OSC_FRQRANGE_enum -{ - OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ - OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ - OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ - OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ -} OSC_FRQRANGE_t; - -/* External Oscillator Selection and Startup Time */ -typedef enum OSC_XOSCSEL_enum -{ - OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ - OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */ - OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */ - OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */ - OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */ -} OSC_XOSCSEL_t; - -/* PLL Clock Source */ -typedef enum OSC_PLLSRC_enum -{ - OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2MHz RC Oscillator */ - OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32MHz RC Oscillator */ - OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ -} OSC_PLLSRC_t; - - -/* --------------------------------------------------------------------------- -DFLL - DFLL --------------------------------------------------------------------------- -*/ - -/* DFLL */ -typedef struct DFLL_struct -{ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x01; - register8_t CALA; /* Calibration Register A */ - register8_t CALB; /* Calibration Register B */ - register8_t COMP0; /* Oscillator Compare Register 0 */ - register8_t COMP1; /* Oscillator Compare Register 1 */ - register8_t COMP2; /* Oscillator Compare Register 2 */ - register8_t reserved_0x07; -} DFLL_t; - - -/* --------------------------------------------------------------------------- -RST - Reset --------------------------------------------------------------------------- -*/ - -/* Reset */ -typedef struct RST_struct -{ - register8_t STATUS; /* Status Register */ - register8_t CTRL; /* Control Register */ -} RST_t; - - -/* --------------------------------------------------------------------------- -WDT - Watch-Dog Timer --------------------------------------------------------------------------- -*/ - -/* Watch-Dog Timer */ -typedef struct WDT_struct -{ - register8_t CTRL; /* Control */ - register8_t WINCTRL; /* Windowed Mode Control */ - register8_t STATUS; /* Status */ -} WDT_t; - -/* Period setting */ -typedef enum WDT_PER_enum -{ - WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ - WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ - WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ - WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ - WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ - WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ - WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ - WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ - WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ - WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -} WDT_PER_t; - -/* Closed window period */ -typedef enum WDT_WPER_enum -{ - WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ - WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ - WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ - WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ - WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ - WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ - WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ - WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ - WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ - WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -} WDT_WPER_t; - - -/* --------------------------------------------------------------------------- -MCU - MCU Control --------------------------------------------------------------------------- -*/ - -/* MCU Control */ -typedef struct MCU_struct -{ - register8_t DEVID0; /* Device ID byte 0 */ - register8_t DEVID1; /* Device ID byte 1 */ - register8_t DEVID2; /* Device ID byte 2 */ - register8_t REVID; /* Revision ID */ - register8_t JTAGUID; /* JTAG User ID */ - register8_t reserved_0x05; - register8_t MCUCR; /* MCU Control */ - register8_t reserved_0x07; - register8_t EVSYSLOCK; /* Event System Lock */ - register8_t AWEXLOCK; /* AWEX Lock */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; -} MCU_t; - - -/* --------------------------------------------------------------------------- -PMIC - Programmable Multi-level Interrupt Controller --------------------------------------------------------------------------- -*/ - -/* Programmable Multi-level Interrupt Controller */ -typedef struct PMIC_struct -{ - register8_t STATUS; /* Status Register */ - register8_t INTPRI; /* Interrupt Priority */ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x03; - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; -} PMIC_t; - - -/* --------------------------------------------------------------------------- -CRC - Cyclic Redundancy Checker --------------------------------------------------------------------------- -*/ - -/* Cyclic Redundancy Checker */ -typedef struct CRC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t reserved_0x02; - register8_t DATAIN; /* Data Input */ - register8_t CHECKSUM0; /* Checksum byte 0 */ - register8_t CHECKSUM1; /* Checksum byte 1 */ - register8_t CHECKSUM2; /* Checksum byte 2 */ - register8_t CHECKSUM3; /* Checksum byte 3 */ -} CRC_t; - -/* Reset */ -typedef enum CRC_RESET_enum -{ - CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ - CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ - CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ -} CRC_RESET_t; - -/* Input Source */ -typedef enum CRC_SOURCE_enum -{ - CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ - CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ - CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ -} CRC_SOURCE_t; - - -/* --------------------------------------------------------------------------- -EVSYS - Event System --------------------------------------------------------------------------- -*/ - -/* Event System */ -typedef struct EVSYS_struct -{ - register8_t CH0MUX; /* Event Channel 0 Multiplexer */ - register8_t CH1MUX; /* Event Channel 1 Multiplexer */ - register8_t CH2MUX; /* Event Channel 2 Multiplexer */ - register8_t CH3MUX; /* Event Channel 3 Multiplexer */ - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t CH0CTRL; /* Channel 0 Control Register */ - register8_t CH1CTRL; /* Channel 1 Control Register */ - register8_t CH2CTRL; /* Channel 2 Control Register */ - register8_t CH3CTRL; /* Channel 3 Control Register */ - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t STROBE; /* Event Strobe */ - register8_t DATA; /* Event Data */ -} EVSYS_t; - -/* Quadrature Decoder Index Recognition Mode */ -typedef enum EVSYS_QDIRM_enum -{ - EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ - EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ - EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ - EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ -} EVSYS_QDIRM_t; - -/* Digital filter coefficient */ -typedef enum EVSYS_DIGFILT_enum -{ - EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ - EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ - EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ - EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ - EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ - EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ - EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ - EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ -} EVSYS_DIGFILT_t; - -/* Event Channel multiplexer input selection */ -typedef enum EVSYS_CHMUX_enum -{ - EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ - EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ - EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ - EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ - EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ - EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ - EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ - EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ - EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ - EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ - EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ - EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ - EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ - EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ - EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ - EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ - EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ - EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ - EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ - EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ - EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ - EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ - EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ - EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ - EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ - EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ - EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ - EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ - EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ - EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ - EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ - EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ - EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ - EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ - EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ - EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ - EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ - EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ - EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ - EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ - EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ - EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ - EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ - EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ - EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ - EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ - EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ - EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ - EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ - EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ - EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ - EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ - EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ - EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ - EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ - EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ - EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ - EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ - EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ - EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ - EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ - EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ - EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ - EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ - EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ - EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ - EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ - EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ - EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ - EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ - EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ - EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ - EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ - EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ - EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ - EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ - EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ - EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ - EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ - EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ - EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ - EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ - EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ - EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ - EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ - EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ - EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ - EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ - EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ - EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ - EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ - EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ - EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ - EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ - EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ - EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ - EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ - EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ - EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ -} EVSYS_CHMUX_t; - - -/* --------------------------------------------------------------------------- -NVM - Non Volatile Memory Controller --------------------------------------------------------------------------- -*/ - -/* Non-volatile Memory Controller */ -typedef struct NVM_struct -{ - register8_t ADDR0; /* Address Register 0 */ - register8_t ADDR1; /* Address Register 1 */ - register8_t ADDR2; /* Address Register 2 */ - register8_t reserved_0x03; - register8_t DATA0; /* Data Register 0 */ - register8_t DATA1; /* Data Register 1 */ - register8_t DATA2; /* Data Register 2 */ - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t CMD; /* Command */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t INTCTRL; /* Interrupt Control */ - register8_t reserved_0x0E; - register8_t STATUS; /* Status */ - register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ -} NVM_t; - - -/* Lock Bits */ -typedef struct NVM_LOCKBITS_struct -{ - register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ -} NVM_LOCKBITS_t; - - -/* Fuses */ -typedef struct NVM_FUSES_struct -{ - register8_t reserved_0x00; - register8_t FUSEBYTE1; /* Watchdog Configuration */ - register8_t FUSEBYTE2; /* Reset Configuration */ - register8_t reserved_0x03; - register8_t FUSEBYTE4; /* Start-up Configuration */ - register8_t FUSEBYTE5; /* EESAVE and BOD Level */ -} NVM_FUSES_t; - - -/* Production Signatures */ -typedef struct NVM_PROD_SIGNATURES_struct -{ - register8_t RCOSC2M; /* RCOSC 2MHz Calibration Value */ - register8_t reserved_0x01; - register8_t RCOSC32K; /* RCOSC 32kHz Calibration Value */ - register8_t RCOSC32M; /* RCOSC 32MHz Calibration Value */ - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ - register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ - register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ - register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ - register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ - register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t WAFNUM; /* Wafer Number */ - register8_t reserved_0x11; - register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ - register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ - register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ - register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ - register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ - register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ - register8_t reserved_0x26; - register8_t reserved_0x27; - register8_t reserved_0x28; - register8_t reserved_0x29; - register8_t reserved_0x2A; - register8_t reserved_0x2B; - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ - register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 0 */ - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - register8_t reserved_0x36; - register8_t reserved_0x37; - register8_t reserved_0x38; - register8_t reserved_0x39; - register8_t reserved_0x3A; - register8_t reserved_0x3B; - register8_t reserved_0x3C; - register8_t reserved_0x3D; - register8_t reserved_0x3E; -} NVM_PROD_SIGNATURES_t; - -/* NVM Command */ -typedef enum NVM_CMD_enum -{ - NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ - NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ - NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ - NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ - NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ - NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ - NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ - NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ - NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ - NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ - NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ - NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ - NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ - NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ - NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ - NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash page */ - NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ - NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ - NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash page */ - NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase and Write Flash page */ - NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ - NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ - NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ - NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ - NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ - NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ - NVM_CMD_APP_CRC_gc = (0x38<<0), /* Generate Application section CRC */ - NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Generate Boot Section CRC */ - NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Generate Flash Range CRC */ -} NVM_CMD_t; - -/* SPM ready interrupt level */ -typedef enum NVM_SPMLVL_enum -{ - NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ - NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ - NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ - NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ -} NVM_SPMLVL_t; - -/* EEPROM ready interrupt level */ -typedef enum NVM_EELVL_enum -{ - NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ - NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ - NVM_EELVL_HI_gc = (0x03<<0), /* High level */ -} NVM_EELVL_t; - -/* Boot lock bits - boot setcion */ -typedef enum NVM_BLBB_enum -{ - NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ - NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ - NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ - NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ -} NVM_BLBB_t; - -/* Boot lock bits - application section */ -typedef enum NVM_BLBA_enum -{ - NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ - NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ - NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ - NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ -} NVM_BLBA_t; - -/* Boot lock bits - application table section */ -typedef enum NVM_BLBAT_enum -{ - NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ - NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ - NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ - NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ -} NVM_BLBAT_t; - -/* Lock bits */ -typedef enum NVM_LB_enum -{ - NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ - NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ - NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ -} NVM_LB_t; - -/* Boot Loader Section Reset Vector */ -typedef enum BOOTRST_enum -{ - BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ - BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ -} BOOTRST_t; - -/* 32.768kHz Timer Oscillator Pin Selection */ -typedef enum TOSCSEL_enum -{ - TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1/2 on separate pins */ - TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1/2 shared with XTAL */ -} TOSCSEL_t; - -/* BOD operation */ -typedef enum BOD_enum -{ - BOD_INSAMPLEDMODE_gc = (0x01<<4), /* BOD enabled in sampled mode */ - BOD_CONTINOUSLY_gc = (0x02<<4), /* BOD enabled continuously */ - BOD_DISABLED_gc = (0x03<<4), /* BOD Disabled */ -} BOD_t; - -/* Watchdog (Window) Timeout Period */ -typedef enum WD_enum -{ - WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ - WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ - WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ - WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ - WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ - WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ - WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ - WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ - WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ - WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ - WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ -} WD_t; - -/* Start-up Time */ -typedef enum SUT_enum -{ - SUT_0MS_gc = (0x03<<2), /* 0 ms */ - SUT_4MS_gc = (0x01<<2), /* 4 ms */ - SUT_64MS_gc = (0x00<<2), /* 64 ms */ -} SUT_t; - -/* Brownout Detection Voltage Level */ -typedef enum BODLVL_enum -{ - BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ - BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ - BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ - BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ - BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ - BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ - BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ - BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ -} BODLVL_t; - - -/* --------------------------------------------------------------------------- -AC - Analog Comparator --------------------------------------------------------------------------- -*/ - -/* Analog Comparator */ -typedef struct AC_struct -{ - register8_t AC0CTRL; /* Analog Comparator 0 Control */ - register8_t AC1CTRL; /* Analog Comparator 1 Control */ - register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ - register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t WINCTRL; /* Window Mode Control */ - register8_t STATUS; /* Status */ -} AC_t; - -/* Interrupt mode */ -typedef enum AC_INTMODE_enum -{ - AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ - AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ - AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ -} AC_INTMODE_t; - -/* Interrupt level */ -typedef enum AC_INTLVL_enum -{ - AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ - AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ - AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ - AC_INTLVL_HI_gc = (0x03<<4), /* High level */ -} AC_INTLVL_t; - -/* Hysteresis mode selection */ -typedef enum AC_HYSMODE_enum -{ - AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ - AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ - AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ -} AC_HYSMODE_t; - -/* Positive input multiplexer selection */ -typedef enum AC_MUXPOS_enum -{ - AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ - AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ - AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ - AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ - AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ - AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ - AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ - AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ -} AC_MUXPOS_t; - -/* Negative input multiplexer selection */ -typedef enum AC_MUXNEG_enum -{ - AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ - AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ - AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ - AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ - AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ - AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ - AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ - AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ -} AC_MUXNEG_t; - -/* Windows interrupt mode */ -typedef enum AC_WINTMODE_enum -{ - AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ - AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ - AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ - AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ -} AC_WINTMODE_t; - -/* Window interrupt level */ -typedef enum AC_WINTLVL_enum -{ - AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ - AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ - AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ -} AC_WINTLVL_t; - -/* Window mode state */ -typedef enum AC_WSTATE_enum -{ - AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ - AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ - AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ -} AC_WSTATE_t; - - -/* --------------------------------------------------------------------------- -ADC - Analog/Digital Converter --------------------------------------------------------------------------- -*/ - -/* ADC Channel */ -typedef struct ADC_CH_struct -{ - register8_t CTRL; /* Control Register */ - register8_t MUXCTRL; /* MUX Control */ - register8_t INTCTRL; /* Channel Interrupt Control Register */ - register8_t INTFLAGS; /* Interrupt Flags */ - _WORDREGISTER(RES); /* Channel Result */ - register8_t SCAN; /* Input Channel Scan */ - register8_t reserved_0x07; -} ADC_CH_t; - - -/* Analog-to-Digital Converter */ -typedef struct ADC_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t REFCTRL; /* Reference Control */ - register8_t EVCTRL; /* Event Control */ - register8_t PRESCALER; /* Clock Prescaler */ - register8_t reserved_0x05; - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t TEMP; /* Temporary Register */ - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - _WORDREGISTER(CAL); /* Calibration Value */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - _WORDREGISTER(CH0RES); /* Channel 0 Result */ - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - _WORDREGISTER(CMP); /* Compare Value */ - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - ADC_CH_t CH0; /* ADC Channel 0 */ -} ADC_t; - -/* Current Limitation */ -typedef enum ADC_CURRLIMIT_enum -{ - ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ - ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 250ksps max sampling rate */ - ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ - ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 50ksps max sampling rate */ -} ADC_CURRLIMIT_t; - -/* Positive input multiplexer selection */ -typedef enum ADC_CH_MUXPOS_enum -{ - ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ - ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ - ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ - ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ - ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ - ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ - ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ - ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ - ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ - ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ - ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ - ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ - ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ - ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ - ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ - ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ -} ADC_CH_MUXPOS_t; - -/* Internal input multiplexer selections */ -typedef enum ADC_CH_MUXINT_enum -{ - ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ - ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ - ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ -} ADC_CH_MUXINT_t; - -/* Negative input multiplexer selection */ -typedef enum ADC_CH_MUXNEG_enum -{ - ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ - ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ - ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ - ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ - ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */ - ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */ - ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */ - ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */ -} ADC_CH_MUXNEG_t; - -/* Input mode */ -typedef enum ADC_CH_INPUTMODE_enum -{ - ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ - ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ - ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ - ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ -} ADC_CH_INPUTMODE_t; - -/* Gain factor */ -typedef enum ADC_CH_GAIN_enum -{ - ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ - ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ - ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ - ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ - ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ - ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ - ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ - ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ -} ADC_CH_GAIN_t; - -/* Conversion result resolution */ -typedef enum ADC_RESOLUTION_enum -{ - ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ - ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ - ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ -} ADC_RESOLUTION_t; - -/* Voltage reference selection */ -typedef enum ADC_REFSEL_enum -{ - ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ - ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ - ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ - ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ - ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ -} ADC_REFSEL_t; - -/* Event channel input selection */ -typedef enum ADC_EVSEL_enum -{ - ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */ - ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */ - ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */ - ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */ -} ADC_EVSEL_t; - -/* Event action selection */ -typedef enum ADC_EVACT_enum -{ - ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ - ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ - ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ -} ADC_EVACT_t; - -/* Interupt mode */ -typedef enum ADC_CH_INTMODE_enum -{ - ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ - ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ - ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ -} ADC_CH_INTMODE_t; - -/* Interrupt level */ -typedef enum ADC_CH_INTLVL_enum -{ - ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ - ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ - ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ -} ADC_CH_INTLVL_t; - -/* Clock prescaler */ -typedef enum ADC_PRESCALER_enum -{ - ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ - ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ - ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ - ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ - ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ - ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ - ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ - ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ -} ADC_PRESCALER_t; - - -/* --------------------------------------------------------------------------- -RTC - Real-Time Counter --------------------------------------------------------------------------- -*/ - -/* Real-Time Counter */ -typedef struct RTC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t TEMP; /* Temporary register */ - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - _WORDREGISTER(CNT); /* Count Register */ - _WORDREGISTER(PER); /* Period Register */ - _WORDREGISTER(COMP); /* Compare Register */ -} RTC_t; - -/* Prescaler Factor */ -typedef enum RTC_PRESCALER_enum -{ - RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ - RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ - RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ - RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ - RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ - RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ - RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ - RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ -} RTC_PRESCALER_t; - -/* Compare Interrupt level */ -typedef enum RTC_COMPINTLVL_enum -{ - RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ - RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ -} RTC_COMPINTLVL_t; - -/* Overflow Interrupt level */ -typedef enum RTC_OVFINTLVL_enum -{ - RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} RTC_OVFINTLVL_t; - - -/* --------------------------------------------------------------------------- -TWI - Two-Wire Interface --------------------------------------------------------------------------- -*/ - -/* */ -typedef struct TWI_MASTER_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t STATUS; /* Status Register */ - register8_t BAUD; /* Baurd Rate Control Register */ - register8_t ADDR; /* Address Register */ - register8_t DATA; /* Data Register */ -} TWI_MASTER_t; - - -/* */ -typedef struct TWI_SLAVE_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t STATUS; /* Status Register */ - register8_t ADDR; /* Address Register */ - register8_t DATA; /* Data Register */ - register8_t ADDRMASK; /* Address Mask Register */ -} TWI_SLAVE_t; - - -/* Two-Wire Interface */ -typedef struct TWI_struct -{ - register8_t CTRL; /* TWI Common Control Register */ - TWI_MASTER_t MASTER; /* TWI master module */ - TWI_SLAVE_t SLAVE; /* TWI slave module */ -} TWI_t; - -/* Master Interrupt Level */ -typedef enum TWI_MASTER_INTLVL_enum -{ - TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ - TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ -} TWI_MASTER_INTLVL_t; - -/* Inactive Timeout */ -typedef enum TWI_MASTER_TIMEOUT_enum -{ - TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ - TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ - TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ - TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ -} TWI_MASTER_TIMEOUT_t; - -/* Master Command */ -typedef enum TWI_MASTER_CMD_enum -{ - TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ - TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ - TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ -} TWI_MASTER_CMD_t; - -/* Master Bus State */ -typedef enum TWI_MASTER_BUSSTATE_enum -{ - TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ - TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ - TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ - TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ -} TWI_MASTER_BUSSTATE_t; - -/* Slave Interrupt Level */ -typedef enum TWI_SLAVE_INTLVL_enum -{ - TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ - TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ -} TWI_SLAVE_INTLVL_t; - -/* Slave Command */ -typedef enum TWI_SLAVE_CMD_enum -{ - TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ - TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ -} TWI_SLAVE_CMD_t; - -/* SDA hold time */ -typedef enum SDA_HOLD_TIME_enum -{ - SDA_HOLD_TIME_OFF_gc = (0x00<<1), /* SDA hold time off */ - SDA_HOLD_TIME_50NS_gc = (0x01<<1), /* Typical 50ns hold time */ - SDA_HOLD_TIME_300NS_gc = (0x02<<1), /* Typical 300ns hold time */ - SDA_HOLD_TIME_400NS_gc = (0x03<<1), /* Typical 400ns hold time */ -} SDA_HOLD_TIME_t; - - -/* --------------------------------------------------------------------------- -PORT - Port Configuration --------------------------------------------------------------------------- -*/ - -/* I/O port Configuration */ -typedef struct PORTCFG_struct -{ - register8_t MPCMASK; /* Multi-pin Configuration Mask */ - register8_t reserved_0x01; - register8_t VPCTRLA; /* Virtual Port Control Register A */ - register8_t VPCTRLB; /* Virtual Port Control Register B */ - register8_t CLKEVOUT; /* Clock and Event Out Register */ -} PORTCFG_t; - - -/* Virtual Port */ -typedef struct VPORT_struct -{ - register8_t DIR; /* I/O Port Data Direction */ - register8_t OUT; /* I/O Port Output */ - register8_t IN; /* I/O Port Input */ - register8_t INTFLAGS; /* Interrupt Flag Register */ -} VPORT_t; - - -/* I/O Ports */ -typedef struct PORT_struct -{ - register8_t DIR; /* I/O Port Data Direction */ - register8_t DIRSET; /* I/O Port Data Direction Set */ - register8_t DIRCLR; /* I/O Port Data Direction Clear */ - register8_t DIRTGL; /* I/O Port Data Direction Toggle */ - register8_t OUT; /* I/O Port Output */ - register8_t OUTSET; /* I/O Port Output Set */ - register8_t OUTCLR; /* I/O Port Output Clear */ - register8_t OUTTGL; /* I/O Port Output Toggle */ - register8_t IN; /* I/O port Input */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INT0MASK; /* Port Interrupt 0 Mask */ - register8_t INT1MASK; /* Port Interrupt 1 Mask */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t REMAP; /* Pin Remap Register (available for PORTC to PORTF only) */ - register8_t reserved_0x0F; - register8_t PIN0CTRL; /* Pin 0 Control Register */ - register8_t PIN1CTRL; /* Pin 1 Control Register */ - register8_t PIN2CTRL; /* Pin 2 Control Register */ - register8_t PIN3CTRL; /* Pin 3 Control Register */ - register8_t PIN4CTRL; /* Pin 4 Control Register */ - register8_t PIN5CTRL; /* Pin 5 Control Register */ - register8_t PIN6CTRL; /* Pin 6 Control Register */ - register8_t PIN7CTRL; /* Pin 7 Control Register */ -} PORT_t; - -/* Virtual Port 0 Mapping */ -typedef enum PORTCFG_VP0MAP_enum -{ - PORTCFG_VP0MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ - PORTCFG_VP0MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ - PORTCFG_VP0MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ - PORTCFG_VP0MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ - PORTCFG_VP0MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ - PORTCFG_VP0MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ - PORTCFG_VP0MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ - PORTCFG_VP0MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ - PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ - PORTCFG_VP0MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ - PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ - PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ - PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ - PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ - PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ - PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ -} PORTCFG_VP0MAP_t; - -/* Virtual Port 1 Mapping */ -typedef enum PORTCFG_VP1MAP_enum -{ - PORTCFG_VP1MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ - PORTCFG_VP1MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ - PORTCFG_VP1MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ - PORTCFG_VP1MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ - PORTCFG_VP1MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ - PORTCFG_VP1MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ - PORTCFG_VP1MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ - PORTCFG_VP1MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ - PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ - PORTCFG_VP1MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ - PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ - PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ - PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ - PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ - PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ - PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ -} PORTCFG_VP1MAP_t; - -/* Virtual Port 2 Mapping */ -typedef enum PORTCFG_VP2MAP_enum -{ - PORTCFG_VP2MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ - PORTCFG_VP2MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ - PORTCFG_VP2MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ - PORTCFG_VP2MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ - PORTCFG_VP2MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ - PORTCFG_VP2MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ - PORTCFG_VP2MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ - PORTCFG_VP2MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ - PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ - PORTCFG_VP2MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ - PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ - PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ - PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ - PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ - PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ - PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ -} PORTCFG_VP2MAP_t; - -/* Virtual Port 3 Mapping */ -typedef enum PORTCFG_VP3MAP_enum -{ - PORTCFG_VP3MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ - PORTCFG_VP3MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ - PORTCFG_VP3MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ - PORTCFG_VP3MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ - PORTCFG_VP3MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ - PORTCFG_VP3MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ - PORTCFG_VP3MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ - PORTCFG_VP3MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ - PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ - PORTCFG_VP3MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ - PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ - PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ - PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ - PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ - PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ - PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ -} PORTCFG_VP3MAP_t; - -/* Clock Output Port */ -typedef enum PORTCFG_CLKOUT_enum -{ - PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* Clock Output Disabled */ - PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* Clock Output on Port C pin 7 */ - PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* Clock Output on Port D pin 7 */ - PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* Clock Output on Port E pin 7 */ -} PORTCFG_CLKOUT_t; - -/* Event Output Port */ -typedef enum PORTCFG_EVOUT_enum -{ - PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ - PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ - PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ - PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ -} PORTCFG_EVOUT_t; - -/* Port Interrupt 0 Level */ -typedef enum PORT_INT0LVL_enum -{ - PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ - PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ - PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ -} PORT_INT0LVL_t; - -/* Port Interrupt 1 Level */ -typedef enum PORT_INT1LVL_enum -{ - PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ - PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ - PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ -} PORT_INT1LVL_t; - -/* Output/Pull Configuration */ -typedef enum PORT_OPC_enum -{ - PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ - PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ - PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ - PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ - PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ - PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ - PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ - PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ -} PORT_OPC_t; - -/* Input/Sense Configuration */ -typedef enum PORT_ISC_enum -{ - PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ - PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ - PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ - PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ - PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ -} PORT_ISC_t; - - -/* --------------------------------------------------------------------------- -TC - 16-bit Timer/Counter With PWM --------------------------------------------------------------------------- -*/ - -/* 16-bit Timer/Counter 0 */ -typedef struct TC0_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t CTRLFCLR; /* Control Register F Clear */ - register8_t CTRLFSET; /* Control Register F Set */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G Set */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - _WORDREGISTER(CNT); /* Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CCA); /* Compare or Capture A */ - _WORDREGISTER(CCB); /* Compare or Capture B */ - _WORDREGISTER(CCC); /* Compare or Capture C */ - _WORDREGISTER(CCD); /* Compare or Capture D */ - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - _WORDREGISTER(PERBUF); /* Period Buffer */ - _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ - _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ - _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ - _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ -} TC0_t; - - -/* 16-bit Timer/Counter 1 */ -typedef struct TC1_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t CTRLFCLR; /* Control Register F Clear */ - register8_t CTRLFSET; /* Control Register F Set */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G Set */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - _WORDREGISTER(CNT); /* Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CCA); /* Compare or Capture A */ - _WORDREGISTER(CCB); /* Compare or Capture B */ - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t reserved_0x2E; - register8_t reserved_0x2F; - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - _WORDREGISTER(PERBUF); /* Period Buffer */ - _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ - _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ -} TC1_t; - - -/* Advanced Waveform Extension */ -typedef struct AWEX_struct -{ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x01; - register8_t FDEMASK; /* Fault Detection Event Mask */ - register8_t FDCTRL; /* Fault Detection Control Register */ - register8_t STATUS; /* Status Register */ - register8_t reserved_0x05; - register8_t DTBOTH; /* Dead Time Both Sides */ - register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ - register8_t DTLS; /* Dead Time Low Side */ - register8_t DTHS; /* Dead Time High Side */ - register8_t DTLSBUF; /* Dead Time Low Side Buffer */ - register8_t DTHSBUF; /* Dead Time High Side Buffer */ - register8_t OUTOVEN; /* Output Override Enable */ -} AWEX_t; - - -/* High-Resolution Extension */ -typedef struct HIRES_struct -{ - register8_t CTRLA; /* Control Register */ -} HIRES_t; - -/* Clock Selection */ -typedef enum TC_CLKSEL_enum -{ - TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ - TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ - TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ - TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ - TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ - TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ - TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ - TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ - TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ - TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ - TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ - TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ - TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ - TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ - TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ -} TC_CLKSEL_t; - -/* Waveform Generation Mode */ -typedef enum TC_WGMODE_enum -{ - TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ - TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ - TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ - TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ - TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on TOP and BOTTOM */ - TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ -} TC_WGMODE_t; - -/* Event Action */ -typedef enum TC_EVACT_enum -{ - TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ - TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ - TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ - TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ - TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ - TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ - TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ -} TC_EVACT_t; - -/* Event Selection */ -typedef enum TC_EVSEL_enum -{ - TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ - TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ - TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ - TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ - TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ - TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ - TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ - TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ -} TC_EVSEL_t; - -/* Error Interrupt Level */ -typedef enum TC_ERRINTLVL_enum -{ - TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC_ERRINTLVL_t; - -/* Overflow Interrupt Level */ -typedef enum TC_OVFINTLVL_enum -{ - TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC_OVFINTLVL_t; - -/* Compare or Capture D Interrupt Level */ -typedef enum TC_CCDINTLVL_enum -{ - TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ - TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ -} TC_CCDINTLVL_t; - -/* Compare or Capture C Interrupt Level */ -typedef enum TC_CCCINTLVL_enum -{ - TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} TC_CCCINTLVL_t; - -/* Compare or Capture B Interrupt Level */ -typedef enum TC_CCBINTLVL_enum -{ - TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC_CCBINTLVL_t; - -/* Compare or Capture A Interrupt Level */ -typedef enum TC_CCAINTLVL_enum -{ - TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC_CCAINTLVL_t; - -/* Timer/Counter Command */ -typedef enum TC_CMD_enum -{ - TC_CMD_NONE_gc = (0x00<<2), /* No Command */ - TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ - TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ - TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -} TC_CMD_t; - -/* Fault Detect Action */ -typedef enum AWEX_FDACT_enum -{ - AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ - AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ - AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ -} AWEX_FDACT_t; - -/* High Resolution Enable */ -typedef enum HIRES_HREN_enum -{ - HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ - HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ - HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ - HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ -} HIRES_HREN_t; - - -/* --------------------------------------------------------------------------- -USART - Universal Asynchronous Receiver-Transmitter --------------------------------------------------------------------------- -*/ - -/* Universal Synchronous/Asynchronous Receiver/Transmitter */ -typedef struct USART_struct -{ - register8_t DATA; /* Data Register */ - register8_t STATUS; /* Status Register */ - register8_t reserved_0x02; - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t BAUDCTRLA; /* Baud Rate Control Register A */ - register8_t BAUDCTRLB; /* Baud Rate Control Register B */ -} USART_t; - -/* Receive Complete Interrupt level */ -typedef enum USART_RXCINTLVL_enum -{ - USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} USART_RXCINTLVL_t; - -/* Transmit Complete Interrupt level */ -typedef enum USART_TXCINTLVL_enum -{ - USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ - USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ -} USART_TXCINTLVL_t; - -/* Data Register Empty Interrupt level */ -typedef enum USART_DREINTLVL_enum -{ - USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ - USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ -} USART_DREINTLVL_t; - -/* Character Size */ -typedef enum USART_CHSIZE_enum -{ - USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ - USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ - USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ - USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ - USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ -} USART_CHSIZE_t; - -/* Communication Mode */ -typedef enum USART_CMODE_enum -{ - USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ - USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ - USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ - USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ -} USART_CMODE_t; - -/* Parity Mode */ -typedef enum USART_PMODE_enum -{ - USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ - USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ - USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ -} USART_PMODE_t; - - -/* --------------------------------------------------------------------------- -SPI - Serial Peripheral Interface --------------------------------------------------------------------------- -*/ - -/* Serial Peripheral Interface */ -typedef struct SPI_struct -{ - register8_t CTRL; /* Control Register */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t STATUS; /* Status Register */ - register8_t DATA; /* Data Register */ -} SPI_t; - -/* SPI Mode */ -typedef enum SPI_MODE_enum -{ - SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ - SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ - SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ - SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ -} SPI_MODE_t; - -/* Prescaler setting */ -typedef enum SPI_PRESCALER_enum -{ - SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ - SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ - SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ - SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ -} SPI_PRESCALER_t; - -/* Interrupt level */ -typedef enum SPI_INTLVL_enum -{ - SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ - SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ - SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ -} SPI_INTLVL_t; - - -/* --------------------------------------------------------------------------- -IRCOM - IR Communication Module --------------------------------------------------------------------------- -*/ - -/* IR Communication Module */ -typedef struct IRCOM_struct -{ - register8_t CTRL; /* Control Register */ - register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ - register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ -} IRCOM_t; - -/* Event channel selection */ -typedef enum IRDA_EVSEL_enum -{ - IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ - IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ - IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ - IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ - IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ - IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ - IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ - IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ - IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ -} IRDA_EVSEL_t; - -/* -========================================================================== -IO Module Instances. Mapped to memory. -========================================================================== -*/ - -#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ -#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ -#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ -#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ -#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ -#define CLK (*(CLK_t *) 0x0040) /* Clock System */ -#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ -#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ -#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ -#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ -#define PR (*(PR_t *) 0x0070) /* Power Reduction */ -#define RST (*(RST_t *) 0x0078) /* Reset */ -#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ -#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ -#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ -#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ -#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ -#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ -#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ -#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ -#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ -#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ -#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ -#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */ -#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ -#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ -#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ -#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ -#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ -#define PORTF (*(PORT_t *) 0x06A0) /* I/O Ports */ -#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ -#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ -#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ -#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ -#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ -#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ -#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ -#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */ -#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */ -#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ -#define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension */ -#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define SPIE (*(SPI_t *) 0x0AC0) /* Serial Peripheral Interface */ -#define TCF0 (*(TC0_t *) 0x0B00) /* 16-bit Timer/Counter 0 */ - - -#endif /* !defined (__ASSEMBLER__) */ - - -/* ========== Flattened fully qualified IO register names ========== */ - -/* GPIO - General Purpose IO Registers */ -#define GPIO_GPIOR0 _SFR_MEM8(0x0000) -#define GPIO_GPIOR1 _SFR_MEM8(0x0001) -#define GPIO_GPIOR2 _SFR_MEM8(0x0002) -#define GPIO_GPIOR3 _SFR_MEM8(0x0003) - -/* Deprecated */ -#define GPIO_GPIO0 _SFR_MEM8(0x0000) -#define GPIO_GPIO1 _SFR_MEM8(0x0001) -#define GPIO_GPIO2 _SFR_MEM8(0x0002) -#define GPIO_GPIO3 _SFR_MEM8(0x0003) - -/* NVM_FUSES - Fuses */ -#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) -#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) -#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) -#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) - -/* NVM_LOCKBITS - Lock Bits */ -#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) - -/* NVM_PROD_SIGNATURES - Production Signatures */ -#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) -#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) -#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) -#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) -#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) -#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) -#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) -#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) -#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) -#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) -#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) -#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) -#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) -#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) -#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) -#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) -#define PRODSIGNATURES_ADCBCAL0 _SFR_MEM8(0x0024) -#define PRODSIGNATURES_ADCBCAL1 _SFR_MEM8(0x0025) -#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) -#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) - -/* VPORT - Virtual Port */ -#define VPORT0_DIR _SFR_MEM8(0x0010) -#define VPORT0_OUT _SFR_MEM8(0x0011) -#define VPORT0_IN _SFR_MEM8(0x0012) -#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) - -/* VPORT - Virtual Port */ -#define VPORT1_DIR _SFR_MEM8(0x0014) -#define VPORT1_OUT _SFR_MEM8(0x0015) -#define VPORT1_IN _SFR_MEM8(0x0016) -#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) - -/* VPORT - Virtual Port */ -#define VPORT2_DIR _SFR_MEM8(0x0018) -#define VPORT2_OUT _SFR_MEM8(0x0019) -#define VPORT2_IN _SFR_MEM8(0x001A) -#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) - -/* VPORT - Virtual Port */ -#define VPORT3_DIR _SFR_MEM8(0x001C) -#define VPORT3_OUT _SFR_MEM8(0x001D) -#define VPORT3_IN _SFR_MEM8(0x001E) -#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) - -/* OCD - On-Chip Debug System */ -#define OCD_OCDR0 _SFR_MEM8(0x002E) -#define OCD_OCDR1 _SFR_MEM8(0x002F) - -/* CPU - CPU registers */ -#define CPU_CCP _SFR_MEM8(0x0034) -#define CPU_RAMPD _SFR_MEM8(0x0038) -#define CPU_RAMPX _SFR_MEM8(0x0039) -#define CPU_RAMPY _SFR_MEM8(0x003A) -#define CPU_RAMPZ _SFR_MEM8(0x003B) -#define CPU_EIND _SFR_MEM8(0x003C) -#define CPU_SPL _SFR_MEM8(0x003D) -#define CPU_SPH _SFR_MEM8(0x003E) -#define CPU_SREG _SFR_MEM8(0x003F) - -/* CLK - Clock System */ -#define CLK_CTRL _SFR_MEM8(0x0040) -#define CLK_PSCTRL _SFR_MEM8(0x0041) -#define CLK_LOCK _SFR_MEM8(0x0042) -#define CLK_RTCCTRL _SFR_MEM8(0x0043) - -/* SLEEP - Sleep Controller */ -#define SLEEP_CTRL _SFR_MEM8(0x0048) - -/* OSC - Oscillator */ -#define OSC_CTRL _SFR_MEM8(0x0050) -#define OSC_STATUS _SFR_MEM8(0x0051) -#define OSC_XOSCCTRL _SFR_MEM8(0x0052) -#define OSC_XOSCFAIL _SFR_MEM8(0x0053) -#define OSC_RC32KCAL _SFR_MEM8(0x0054) -#define OSC_PLLCTRL _SFR_MEM8(0x0055) -#define OSC_DFLLCTRL _SFR_MEM8(0x0056) - -/* DFLL - DFLL */ -#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) -#define DFLLRC32M_CALA _SFR_MEM8(0x0062) -#define DFLLRC32M_CALB _SFR_MEM8(0x0063) -#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) -#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) -#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) - -/* DFLL - DFLL */ -#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) -#define DFLLRC2M_CALA _SFR_MEM8(0x006A) -#define DFLLRC2M_CALB _SFR_MEM8(0x006B) -#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) -#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) -#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) - -/* PR - Power Reduction */ -#define PR_PRGEN _SFR_MEM8(0x0070) -#define PR_PRPA _SFR_MEM8(0x0071) -#define PR_PRPC _SFR_MEM8(0x0073) -#define PR_PRPD _SFR_MEM8(0x0074) -#define PR_PRPE _SFR_MEM8(0x0075) -#define PR_PRPF _SFR_MEM8(0x0076) - -/* RST - Reset */ -#define RST_STATUS _SFR_MEM8(0x0078) -#define RST_CTRL _SFR_MEM8(0x0079) - -/* WDT - Watch-Dog Timer */ -#define WDT_CTRL _SFR_MEM8(0x0080) -#define WDT_WINCTRL _SFR_MEM8(0x0081) -#define WDT_STATUS _SFR_MEM8(0x0082) - -/* MCU - MCU Control */ -#define MCU_DEVID0 _SFR_MEM8(0x0090) -#define MCU_DEVID1 _SFR_MEM8(0x0091) -#define MCU_DEVID2 _SFR_MEM8(0x0092) -#define MCU_REVID _SFR_MEM8(0x0093) -#define MCU_JTAGUID _SFR_MEM8(0x0094) -#define MCU_MCUCR _SFR_MEM8(0x0096) -#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) -#define MCU_AWEXLOCK _SFR_MEM8(0x0099) - -/* PMIC - Programmable Multi-level Interrupt Controller */ -#define PMIC_STATUS _SFR_MEM8(0x00A0) -#define PMIC_INTPRI _SFR_MEM8(0x00A1) -#define PMIC_CTRL _SFR_MEM8(0x00A2) - -/* PORTCFG - I/O port Configuration */ -#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) -#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) -#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) -#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) - -/* CRC - Cyclic Redundancy Checker */ -#define CRC_CTRL _SFR_MEM8(0x00D0) -#define CRC_STATUS _SFR_MEM8(0x00D1) -#define CRC_DATAIN _SFR_MEM8(0x00D3) -#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) -#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) -#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) -#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) - -/* EVSYS - Event System */ -#define EVSYS_CH0MUX _SFR_MEM8(0x0180) -#define EVSYS_CH1MUX _SFR_MEM8(0x0181) -#define EVSYS_CH2MUX _SFR_MEM8(0x0182) -#define EVSYS_CH3MUX _SFR_MEM8(0x0183) -#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) -#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) -#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) -#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) -#define EVSYS_STROBE _SFR_MEM8(0x0190) -#define EVSYS_DATA _SFR_MEM8(0x0191) - -/* NVM - Non-volatile Memory Controller */ -#define NVM_ADDR0 _SFR_MEM8(0x01C0) -#define NVM_ADDR1 _SFR_MEM8(0x01C1) -#define NVM_ADDR2 _SFR_MEM8(0x01C2) -#define NVM_DATA0 _SFR_MEM8(0x01C4) -#define NVM_DATA1 _SFR_MEM8(0x01C5) -#define NVM_DATA2 _SFR_MEM8(0x01C6) -#define NVM_CMD _SFR_MEM8(0x01CA) -#define NVM_CTRLA _SFR_MEM8(0x01CB) -#define NVM_CTRLB _SFR_MEM8(0x01CC) -#define NVM_INTCTRL _SFR_MEM8(0x01CD) -#define NVM_STATUS _SFR_MEM8(0x01CF) -#define NVM_LOCKBITS _SFR_MEM8(0x01D0) - -/* ADC - Analog-to-Digital Converter */ -#define ADCA_CTRLA _SFR_MEM8(0x0200) -#define ADCA_CTRLB _SFR_MEM8(0x0201) -#define ADCA_REFCTRL _SFR_MEM8(0x0202) -#define ADCA_EVCTRL _SFR_MEM8(0x0203) -#define ADCA_PRESCALER _SFR_MEM8(0x0204) -#define ADCA_INTFLAGS _SFR_MEM8(0x0206) -#define ADCA_TEMP _SFR_MEM8(0x0207) -#define ADCA_CAL _SFR_MEM16(0x020C) -#define ADCA_CH0RES _SFR_MEM16(0x0210) -#define ADCA_CMP _SFR_MEM16(0x0218) -#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) -#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) -#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) -#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) -#define ADCA_CH0_RES _SFR_MEM16(0x0224) -#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) - -/* AC - Analog Comparator */ -#define ACA_AC0CTRL _SFR_MEM8(0x0380) -#define ACA_AC1CTRL _SFR_MEM8(0x0381) -#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) -#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) -#define ACA_CTRLA _SFR_MEM8(0x0384) -#define ACA_CTRLB _SFR_MEM8(0x0385) -#define ACA_WINCTRL _SFR_MEM8(0x0386) -#define ACA_STATUS _SFR_MEM8(0x0387) - -/* RTC - Real-Time Counter */ -#define RTC_CTRL _SFR_MEM8(0x0400) -#define RTC_STATUS _SFR_MEM8(0x0401) -#define RTC_INTCTRL _SFR_MEM8(0x0402) -#define RTC_INTFLAGS _SFR_MEM8(0x0403) -#define RTC_TEMP _SFR_MEM8(0x0404) -#define RTC_CNT _SFR_MEM16(0x0408) -#define RTC_PER _SFR_MEM16(0x040A) -#define RTC_COMP _SFR_MEM16(0x040C) - -/* TWI - Two-Wire Interface */ -#define TWIC_CTRL _SFR_MEM8(0x0480) -#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) -#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) -#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) -#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) -#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) -#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) -#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) -#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) -#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) -#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) -#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) -#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) -#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) - -/* TWI - Two-Wire Interface */ -#define TWIE_CTRL _SFR_MEM8(0x04A0) -#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) -#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) -#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) -#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) -#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) -#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) -#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) -#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) -#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) -#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) -#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) -#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) -#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) - -/* PORT - I/O Ports */ -#define PORTA_DIR _SFR_MEM8(0x0600) -#define PORTA_DIRSET _SFR_MEM8(0x0601) -#define PORTA_DIRCLR _SFR_MEM8(0x0602) -#define PORTA_DIRTGL _SFR_MEM8(0x0603) -#define PORTA_OUT _SFR_MEM8(0x0604) -#define PORTA_OUTSET _SFR_MEM8(0x0605) -#define PORTA_OUTCLR _SFR_MEM8(0x0606) -#define PORTA_OUTTGL _SFR_MEM8(0x0607) -#define PORTA_IN _SFR_MEM8(0x0608) -#define PORTA_INTCTRL _SFR_MEM8(0x0609) -#define PORTA_INT0MASK _SFR_MEM8(0x060A) -#define PORTA_INT1MASK _SFR_MEM8(0x060B) -#define PORTA_INTFLAGS _SFR_MEM8(0x060C) -#define PORTA_REMAP _SFR_MEM8(0x060E) -#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) -#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) -#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) -#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) -#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) -#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) -#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) -#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) - -/* PORT - I/O Ports */ -#define PORTB_DIR _SFR_MEM8(0x0620) -#define PORTB_DIRSET _SFR_MEM8(0x0621) -#define PORTB_DIRCLR _SFR_MEM8(0x0622) -#define PORTB_DIRTGL _SFR_MEM8(0x0623) -#define PORTB_OUT _SFR_MEM8(0x0624) -#define PORTB_OUTSET _SFR_MEM8(0x0625) -#define PORTB_OUTCLR _SFR_MEM8(0x0626) -#define PORTB_OUTTGL _SFR_MEM8(0x0627) -#define PORTB_IN _SFR_MEM8(0x0628) -#define PORTB_INTCTRL _SFR_MEM8(0x0629) -#define PORTB_INT0MASK _SFR_MEM8(0x062A) -#define PORTB_INT1MASK _SFR_MEM8(0x062B) -#define PORTB_INTFLAGS _SFR_MEM8(0x062C) -#define PORTB_REMAP _SFR_MEM8(0x062E) -#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) -#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) -#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) -#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) -#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) -#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) -#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) -#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) - -/* PORT - I/O Ports */ -#define PORTC_DIR _SFR_MEM8(0x0640) -#define PORTC_DIRSET _SFR_MEM8(0x0641) -#define PORTC_DIRCLR _SFR_MEM8(0x0642) -#define PORTC_DIRTGL _SFR_MEM8(0x0643) -#define PORTC_OUT _SFR_MEM8(0x0644) -#define PORTC_OUTSET _SFR_MEM8(0x0645) -#define PORTC_OUTCLR _SFR_MEM8(0x0646) -#define PORTC_OUTTGL _SFR_MEM8(0x0647) -#define PORTC_IN _SFR_MEM8(0x0648) -#define PORTC_INTCTRL _SFR_MEM8(0x0649) -#define PORTC_INT0MASK _SFR_MEM8(0x064A) -#define PORTC_INT1MASK _SFR_MEM8(0x064B) -#define PORTC_INTFLAGS _SFR_MEM8(0x064C) -#define PORTC_REMAP _SFR_MEM8(0x064E) -#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) -#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) -#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) -#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) -#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) -#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) -#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) -#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) - -/* PORT - I/O Ports */ -#define PORTD_DIR _SFR_MEM8(0x0660) -#define PORTD_DIRSET _SFR_MEM8(0x0661) -#define PORTD_DIRCLR _SFR_MEM8(0x0662) -#define PORTD_DIRTGL _SFR_MEM8(0x0663) -#define PORTD_OUT _SFR_MEM8(0x0664) -#define PORTD_OUTSET _SFR_MEM8(0x0665) -#define PORTD_OUTCLR _SFR_MEM8(0x0666) -#define PORTD_OUTTGL _SFR_MEM8(0x0667) -#define PORTD_IN _SFR_MEM8(0x0668) -#define PORTD_INTCTRL _SFR_MEM8(0x0669) -#define PORTD_INT0MASK _SFR_MEM8(0x066A) -#define PORTD_INT1MASK _SFR_MEM8(0x066B) -#define PORTD_INTFLAGS _SFR_MEM8(0x066C) -#define PORTD_REMAP _SFR_MEM8(0x066E) -#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) -#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) -#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) -#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) -#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) -#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) -#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) -#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) - -/* PORT - I/O Ports */ -#define PORTE_DIR _SFR_MEM8(0x0680) -#define PORTE_DIRSET _SFR_MEM8(0x0681) -#define PORTE_DIRCLR _SFR_MEM8(0x0682) -#define PORTE_DIRTGL _SFR_MEM8(0x0683) -#define PORTE_OUT _SFR_MEM8(0x0684) -#define PORTE_OUTSET _SFR_MEM8(0x0685) -#define PORTE_OUTCLR _SFR_MEM8(0x0686) -#define PORTE_OUTTGL _SFR_MEM8(0x0687) -#define PORTE_IN _SFR_MEM8(0x0688) -#define PORTE_INTCTRL _SFR_MEM8(0x0689) -#define PORTE_INT0MASK _SFR_MEM8(0x068A) -#define PORTE_INT1MASK _SFR_MEM8(0x068B) -#define PORTE_INTFLAGS _SFR_MEM8(0x068C) -#define PORTE_REMAP _SFR_MEM8(0x068E) -#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) -#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) -#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) -#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) -#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) -#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) -#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) -#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) - -/* PORT - I/O Ports */ -#define PORTF_DIR _SFR_MEM8(0x06A0) -#define PORTF_DIRSET _SFR_MEM8(0x06A1) -#define PORTF_DIRCLR _SFR_MEM8(0x06A2) -#define PORTF_DIRTGL _SFR_MEM8(0x06A3) -#define PORTF_OUT _SFR_MEM8(0x06A4) -#define PORTF_OUTSET _SFR_MEM8(0x06A5) -#define PORTF_OUTCLR _SFR_MEM8(0x06A6) -#define PORTF_OUTTGL _SFR_MEM8(0x06A7) -#define PORTF_IN _SFR_MEM8(0x06A8) -#define PORTF_INTCTRL _SFR_MEM8(0x06A9) -#define PORTF_INT0MASK _SFR_MEM8(0x06AA) -#define PORTF_INT1MASK _SFR_MEM8(0x06AB) -#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) -#define PORTF_REMAP _SFR_MEM8(0x06AE) -#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) -#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) -#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) -#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) -#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) -#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) -#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) -#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) - -/* PORT - I/O Ports */ -#define PORTR_DIR _SFR_MEM8(0x07E0) -#define PORTR_DIRSET _SFR_MEM8(0x07E1) -#define PORTR_DIRCLR _SFR_MEM8(0x07E2) -#define PORTR_DIRTGL _SFR_MEM8(0x07E3) -#define PORTR_OUT _SFR_MEM8(0x07E4) -#define PORTR_OUTSET _SFR_MEM8(0x07E5) -#define PORTR_OUTCLR _SFR_MEM8(0x07E6) -#define PORTR_OUTTGL _SFR_MEM8(0x07E7) -#define PORTR_IN _SFR_MEM8(0x07E8) -#define PORTR_INTCTRL _SFR_MEM8(0x07E9) -#define PORTR_INT0MASK _SFR_MEM8(0x07EA) -#define PORTR_INT1MASK _SFR_MEM8(0x07EB) -#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) -#define PORTR_REMAP _SFR_MEM8(0x07EE) -#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) -#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) -#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) -#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) -#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) -#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) -#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) -#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) - -/* TC0 - 16-bit Timer/Counter 0 */ -#define TCC0_CTRLA _SFR_MEM8(0x0800) -#define TCC0_CTRLB _SFR_MEM8(0x0801) -#define TCC0_CTRLC _SFR_MEM8(0x0802) -#define TCC0_CTRLD _SFR_MEM8(0x0803) -#define TCC0_CTRLE _SFR_MEM8(0x0804) -#define TCC0_INTCTRLA _SFR_MEM8(0x0806) -#define TCC0_INTCTRLB _SFR_MEM8(0x0807) -#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) -#define TCC0_CTRLFSET _SFR_MEM8(0x0809) -#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) -#define TCC0_CTRLGSET _SFR_MEM8(0x080B) -#define TCC0_INTFLAGS _SFR_MEM8(0x080C) -#define TCC0_TEMP _SFR_MEM8(0x080F) -#define TCC0_CNT _SFR_MEM16(0x0820) -#define TCC0_PER _SFR_MEM16(0x0826) -#define TCC0_CCA _SFR_MEM16(0x0828) -#define TCC0_CCB _SFR_MEM16(0x082A) -#define TCC0_CCC _SFR_MEM16(0x082C) -#define TCC0_CCD _SFR_MEM16(0x082E) -#define TCC0_PERBUF _SFR_MEM16(0x0836) -#define TCC0_CCABUF _SFR_MEM16(0x0838) -#define TCC0_CCBBUF _SFR_MEM16(0x083A) -#define TCC0_CCCBUF _SFR_MEM16(0x083C) -#define TCC0_CCDBUF _SFR_MEM16(0x083E) - -/* TC1 - 16-bit Timer/Counter 1 */ -#define TCC1_CTRLA _SFR_MEM8(0x0840) -#define TCC1_CTRLB _SFR_MEM8(0x0841) -#define TCC1_CTRLC _SFR_MEM8(0x0842) -#define TCC1_CTRLD _SFR_MEM8(0x0843) -#define TCC1_CTRLE _SFR_MEM8(0x0844) -#define TCC1_INTCTRLA _SFR_MEM8(0x0846) -#define TCC1_INTCTRLB _SFR_MEM8(0x0847) -#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) -#define TCC1_CTRLFSET _SFR_MEM8(0x0849) -#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) -#define TCC1_CTRLGSET _SFR_MEM8(0x084B) -#define TCC1_INTFLAGS _SFR_MEM8(0x084C) -#define TCC1_TEMP _SFR_MEM8(0x084F) -#define TCC1_CNT _SFR_MEM16(0x0860) -#define TCC1_PER _SFR_MEM16(0x0866) -#define TCC1_CCA _SFR_MEM16(0x0868) -#define TCC1_CCB _SFR_MEM16(0x086A) -#define TCC1_PERBUF _SFR_MEM16(0x0876) -#define TCC1_CCABUF _SFR_MEM16(0x0878) -#define TCC1_CCBBUF _SFR_MEM16(0x087A) - -/* AWEX - Advanced Waveform Extension */ -#define AWEXC_CTRL _SFR_MEM8(0x0880) -#define AWEXC_FDEMASK _SFR_MEM8(0x0882) -#define AWEXC_FDCTRL _SFR_MEM8(0x0883) -#define AWEXC_STATUS _SFR_MEM8(0x0884) -#define AWEXC_DTBOTH _SFR_MEM8(0x0886) -#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) -#define AWEXC_DTLS _SFR_MEM8(0x0888) -#define AWEXC_DTHS _SFR_MEM8(0x0889) -#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) -#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) -#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) - -/* HIRES - High-Resolution Extension */ -#define HIRESC_CTRLA _SFR_MEM8(0x0890) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTC0_DATA _SFR_MEM8(0x08A0) -#define USARTC0_STATUS _SFR_MEM8(0x08A1) -#define USARTC0_CTRLA _SFR_MEM8(0x08A3) -#define USARTC0_CTRLB _SFR_MEM8(0x08A4) -#define USARTC0_CTRLC _SFR_MEM8(0x08A5) -#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) -#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) - -/* SPI - Serial Peripheral Interface */ -#define SPIC_CTRL _SFR_MEM8(0x08C0) -#define SPIC_INTCTRL _SFR_MEM8(0x08C1) -#define SPIC_STATUS _SFR_MEM8(0x08C2) -#define SPIC_DATA _SFR_MEM8(0x08C3) - -/* IRCOM - IR Communication Module */ -#define IRCOM_CTRL _SFR_MEM8(0x08F8) -#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) -#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) - -/* TC0 - 16-bit Timer/Counter 0 */ -#define TCD0_CTRLA _SFR_MEM8(0x0900) -#define TCD0_CTRLB _SFR_MEM8(0x0901) -#define TCD0_CTRLC _SFR_MEM8(0x0902) -#define TCD0_CTRLD _SFR_MEM8(0x0903) -#define TCD0_CTRLE _SFR_MEM8(0x0904) -#define TCD0_INTCTRLA _SFR_MEM8(0x0906) -#define TCD0_INTCTRLB _SFR_MEM8(0x0907) -#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) -#define TCD0_CTRLFSET _SFR_MEM8(0x0909) -#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) -#define TCD0_CTRLGSET _SFR_MEM8(0x090B) -#define TCD0_INTFLAGS _SFR_MEM8(0x090C) -#define TCD0_TEMP _SFR_MEM8(0x090F) -#define TCD0_CNT _SFR_MEM16(0x0920) -#define TCD0_PER _SFR_MEM16(0x0926) -#define TCD0_CCA _SFR_MEM16(0x0928) -#define TCD0_CCB _SFR_MEM16(0x092A) -#define TCD0_CCC _SFR_MEM16(0x092C) -#define TCD0_CCD _SFR_MEM16(0x092E) -#define TCD0_PERBUF _SFR_MEM16(0x0936) -#define TCD0_CCABUF _SFR_MEM16(0x0938) -#define TCD0_CCBBUF _SFR_MEM16(0x093A) -#define TCD0_CCCBUF _SFR_MEM16(0x093C) -#define TCD0_CCDBUF _SFR_MEM16(0x093E) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTD0_DATA _SFR_MEM8(0x09A0) -#define USARTD0_STATUS _SFR_MEM8(0x09A1) -#define USARTD0_CTRLA _SFR_MEM8(0x09A3) -#define USARTD0_CTRLB _SFR_MEM8(0x09A4) -#define USARTD0_CTRLC _SFR_MEM8(0x09A5) -#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) -#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) - -/* SPI - Serial Peripheral Interface */ -#define SPID_CTRL _SFR_MEM8(0x09C0) -#define SPID_INTCTRL _SFR_MEM8(0x09C1) -#define SPID_STATUS _SFR_MEM8(0x09C2) -#define SPID_DATA _SFR_MEM8(0x09C3) - -/* TC0 - 16-bit Timer/Counter 0 */ -#define TCE0_CTRLA _SFR_MEM8(0x0A00) -#define TCE0_CTRLB _SFR_MEM8(0x0A01) -#define TCE0_CTRLC _SFR_MEM8(0x0A02) -#define TCE0_CTRLD _SFR_MEM8(0x0A03) -#define TCE0_CTRLE _SFR_MEM8(0x0A04) -#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) -#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) -#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) -#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) -#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) -#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) -#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) -#define TCE0_TEMP _SFR_MEM8(0x0A0F) -#define TCE0_CNT _SFR_MEM16(0x0A20) -#define TCE0_PER _SFR_MEM16(0x0A26) -#define TCE0_CCA _SFR_MEM16(0x0A28) -#define TCE0_CCB _SFR_MEM16(0x0A2A) -#define TCE0_CCC _SFR_MEM16(0x0A2C) -#define TCE0_CCD _SFR_MEM16(0x0A2E) -#define TCE0_PERBUF _SFR_MEM16(0x0A36) -#define TCE0_CCABUF _SFR_MEM16(0x0A38) -#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) -#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) -#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) - -/* AWEX - Advanced Waveform Extension */ -#define AWEXE_CTRL _SFR_MEM8(0x0A80) -#define AWEXE_FDEMASK _SFR_MEM8(0x0A82) -#define AWEXE_FDCTRL _SFR_MEM8(0x0A83) -#define AWEXE_STATUS _SFR_MEM8(0x0A84) -#define AWEXE_DTBOTH _SFR_MEM8(0x0A86) -#define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87) -#define AWEXE_DTLS _SFR_MEM8(0x0A88) -#define AWEXE_DTHS _SFR_MEM8(0x0A89) -#define AWEXE_DTLSBUF _SFR_MEM8(0x0A8A) -#define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B) -#define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTE0_DATA _SFR_MEM8(0x0AA0) -#define USARTE0_STATUS _SFR_MEM8(0x0AA1) -#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) -#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) -#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) -#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) -#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) - -/* SPI - Serial Peripheral Interface */ -#define SPIE_CTRL _SFR_MEM8(0x0AC0) -#define SPIE_INTCTRL _SFR_MEM8(0x0AC1) -#define SPIE_STATUS _SFR_MEM8(0x0AC2) -#define SPIE_DATA _SFR_MEM8(0x0AC3) - -/* TC0 - 16-bit Timer/Counter 0 */ -#define TCF0_CTRLA _SFR_MEM8(0x0B00) -#define TCF0_CTRLB _SFR_MEM8(0x0B01) -#define TCF0_CTRLC _SFR_MEM8(0x0B02) -#define TCF0_CTRLD _SFR_MEM8(0x0B03) -#define TCF0_CTRLE _SFR_MEM8(0x0B04) -#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) -#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) -#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) -#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) -#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) -#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) -#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) -#define TCF0_TEMP _SFR_MEM8(0x0B0F) -#define TCF0_CNT _SFR_MEM16(0x0B20) -#define TCF0_PER _SFR_MEM16(0x0B26) -#define TCF0_CCA _SFR_MEM16(0x0B28) -#define TCF0_CCB _SFR_MEM16(0x0B2A) -#define TCF0_CCC _SFR_MEM16(0x0B2C) -#define TCF0_CCD _SFR_MEM16(0x0B2E) -#define TCF0_PERBUF _SFR_MEM16(0x0B36) -#define TCF0_CCABUF _SFR_MEM16(0x0B38) -#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) -#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) -#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) - - - -/*================== Bitfield Definitions ================== */ - -/* XOCD - On-Chip Debug System */ -/* OCD.OCDR0 bit masks and bit positions */ -#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ -#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ -#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ -#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ -#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ -#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ -#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ -#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ -#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ -#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ -#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ -#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ -#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ -#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ -#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ -#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ -#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ -#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ - -/* OCD.OCDR1 bit masks and bit positions */ -/* OCD_OCDRD Predefined. */ -/* OCD_OCDRD Predefined. */ - -/* CPU - CPU */ -/* CPU.CCP bit masks and bit positions */ -#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ -#define CPU_CCP_gp 0 /* CCP signature group position. */ -#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ -#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ -#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ -#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ -#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ -#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ -#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ -#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ -#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ -#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ -#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ -#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ -#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ -#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ -#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ -#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ - -/* CPU.SREG bit masks and bit positions */ -#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ -#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ - -#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ -#define CPU_T_bp 6 /* Transfer Bit bit position. */ - -#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ -#define CPU_H_bp 5 /* Half Carry Flag bit position. */ - -#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ -#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ - -#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ -#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ - -#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ -#define CPU_N_bp 2 /* Negative Flag bit position. */ - -#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ -#define CPU_Z_bp 1 /* Zero Flag bit position. */ - -#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ -#define CPU_C_bp 0 /* Carry Flag bit position. */ - -/* CLK - Clock System */ -/* CLK.CTRL bit masks and bit positions */ -#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ -#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ -#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ -#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ -#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ -#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ -#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ -#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ - -/* CLK.PSCTRL bit masks and bit positions */ -#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ -#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ -#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ -#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ -#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ -#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ -#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ -#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ -#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ -#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ -#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ -#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ - -#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ -#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ -#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ -#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ -#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ -#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ - -/* CLK.LOCK bit masks and bit positions */ -#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ -#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ - -/* CLK.RTCCTRL bit masks and bit positions */ -#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ -#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ -#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ -#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ -#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ -#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ - -#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ -#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ - -/* PR.PRGEN bit masks and bit positions */ -#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ -#define PR_RTC_bp 2 /* Real-time Counter bit position. */ - -#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ -#define PR_EVSYS_bp 1 /* Event System bit position. */ - -/* PR.PRPA bit masks and bit positions */ -#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ -#define PR_ADC_bp 1 /* Port A ADC bit position. */ - -#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ -#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ - -/* PR.PRPC bit masks and bit positions */ -#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ -#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ - -#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ -#define PR_USART0_bp 4 /* Port C USART0 bit position. */ - -#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ -#define PR_SPI_bp 3 /* Port C SPI bit position. */ - -#define PR_HIRES_bm 0x04 /* Port C HIRES bit mask. */ -#define PR_HIRES_bp 2 /* Port C HIRES bit position. */ - -#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ -#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ - -#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ -#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ - -/* PR.PRPD bit masks and bit positions */ -/* PR_USART0 Predefined. */ -/* PR_USART0 Predefined. */ - -/* PR_SPI Predefined. */ -/* PR_SPI Predefined. */ - -/* PR_TC0 Predefined. */ -/* PR_TC0 Predefined. */ - -/* PR.PRPE bit masks and bit positions */ -/* PR_TWI Predefined. */ -/* PR_TWI Predefined. */ - -/* PR_USART0 Predefined. */ -/* PR_USART0 Predefined. */ - -/* PR_TC0 Predefined. */ -/* PR_TC0 Predefined. */ - -/* PR.PRPF bit masks and bit positions */ -/* PR_USART0 Predefined. */ -/* PR_USART0 Predefined. */ - -/* PR_TC0 Predefined. */ -/* PR_TC0 Predefined. */ - -/* SLEEP - Sleep Controller */ -/* SLEEP.CTRL bit masks and bit positions */ -#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ -#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ -#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ -#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ -#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ -#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ -#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ -#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ - -#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ -#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ - -/* OSC - Oscillator */ -/* OSC.CTRL bit masks and bit positions */ -#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ -#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ - -#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ -#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ - -#define OSC_RC32KEN_bm 0x04 /* Internal 32kHz RC Oscillator Enable bit mask. */ -#define OSC_RC32KEN_bp 2 /* Internal 32kHz RC Oscillator Enable bit position. */ - -#define OSC_RC32MEN_bm 0x02 /* Internal 32MHz RC Oscillator Enable bit mask. */ -#define OSC_RC32MEN_bp 1 /* Internal 32MHz RC Oscillator Enable bit position. */ - -#define OSC_RC2MEN_bm 0x01 /* Internal 2MHz RC Oscillator Enable bit mask. */ -#define OSC_RC2MEN_bp 0 /* Internal 2MHz RC Oscillator Enable bit position. */ - -/* OSC.STATUS bit masks and bit positions */ -#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ -#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ - -#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ -#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ - -#define OSC_RC32KRDY_bm 0x04 /* Internal 32kHz RC Oscillator Ready bit mask. */ -#define OSC_RC32KRDY_bp 2 /* Internal 32kHz RC Oscillator Ready bit position. */ - -#define OSC_RC32MRDY_bm 0x02 /* Internal 32MHz RC Oscillator Ready bit mask. */ -#define OSC_RC32MRDY_bp 1 /* Internal 32MHz RC Oscillator Ready bit position. */ - -#define OSC_RC2MRDY_bm 0x01 /* Internal 2MHz RC Oscillator Ready bit mask. */ -#define OSC_RC2MRDY_bp 0 /* Internal 2MHz RC Oscillator Ready bit position. */ - -/* OSC.XOSCCTRL bit masks and bit positions */ -#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ -#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ -#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ -#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ -#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ -#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ - -#define OSC_X32KLPM_bm 0x20 /* 32kHz XTAL OSC Low-power Mode bit mask. */ -#define OSC_X32KLPM_bp 5 /* 32kHz XTAL OSC Low-power Mode bit position. */ - -#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ -#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ -#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ -#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ -#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ -#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ -#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ -#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ -#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ -#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ - -/* OSC.XOSCFAIL bit masks and bit positions */ -#define OSC_XOSCFDIF_bm 0x02 /* Failure Detection Interrupt Flag bit mask. */ -#define OSC_XOSCFDIF_bp 1 /* Failure Detection Interrupt Flag bit position. */ - -#define OSC_XOSCFDEN_bm 0x01 /* Failure Detection Enable bit mask. */ -#define OSC_XOSCFDEN_bp 0 /* Failure Detection Enable bit position. */ - -/* OSC.PLLCTRL bit masks and bit positions */ -#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ -#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ -#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ -#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ -#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ -#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ - -#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ -#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ -#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ -#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ -#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ -#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ -#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ -#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ -#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ -#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ -#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ -#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ - -/* OSC.DFLLCTRL bit masks and bit positions */ -#define OSC_RC32MCREF_bm 0x02 /* 32MHz Calibration Reference bit mask. */ -#define OSC_RC32MCREF_bp 1 /* 32MHz Calibration Reference bit position. */ - -#define OSC_RC2MCREF_bm 0x01 /* 2MHz Calibration Reference bit mask. */ -#define OSC_RC2MCREF_bp 0 /* 2MHz Calibration Reference bit position. */ - -/* DFLL - DFLL */ -/* DFLL.CTRL bit masks and bit positions */ -#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ -#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ - -/* DFLL.CALA bit masks and bit positions */ -#define DFLL_CALL_gm 0x7F /* DFLL Calibration bits [6:0] group mask. */ -#define DFLL_CALL_gp 0 /* DFLL Calibration bits [6:0] group position. */ -#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration bits [6:0] bit 0 mask. */ -#define DFLL_CALL0_bp 0 /* DFLL Calibration bits [6:0] bit 0 position. */ -#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration bits [6:0] bit 1 mask. */ -#define DFLL_CALL1_bp 1 /* DFLL Calibration bits [6:0] bit 1 position. */ -#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration bits [6:0] bit 2 mask. */ -#define DFLL_CALL2_bp 2 /* DFLL Calibration bits [6:0] bit 2 position. */ -#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration bits [6:0] bit 3 mask. */ -#define DFLL_CALL3_bp 3 /* DFLL Calibration bits [6:0] bit 3 position. */ -#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration bits [6:0] bit 4 mask. */ -#define DFLL_CALL4_bp 4 /* DFLL Calibration bits [6:0] bit 4 position. */ -#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration bits [6:0] bit 5 mask. */ -#define DFLL_CALL5_bp 5 /* DFLL Calibration bits [6:0] bit 5 position. */ -#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration bits [6:0] bit 6 mask. */ -#define DFLL_CALL6_bp 6 /* DFLL Calibration bits [6:0] bit 6 position. */ - -/* DFLL.CALB bit masks and bit positions */ -#define DFLL_CALH_gm 0x3F /* DFLL Calibration bits [12:7] group mask. */ -#define DFLL_CALH_gp 0 /* DFLL Calibration bits [12:7] group position. */ -#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration bits [12:7] bit 0 mask. */ -#define DFLL_CALH0_bp 0 /* DFLL Calibration bits [12:7] bit 0 position. */ -#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration bits [12:7] bit 1 mask. */ -#define DFLL_CALH1_bp 1 /* DFLL Calibration bits [12:7] bit 1 position. */ -#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration bits [12:7] bit 2 mask. */ -#define DFLL_CALH2_bp 2 /* DFLL Calibration bits [12:7] bit 2 position. */ -#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration bits [12:7] bit 3 mask. */ -#define DFLL_CALH3_bp 3 /* DFLL Calibration bits [12:7] bit 3 position. */ -#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration bits [12:7] bit 4 mask. */ -#define DFLL_CALH4_bp 4 /* DFLL Calibration bits [12:7] bit 4 position. */ -#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration bits [12:7] bit 5 mask. */ -#define DFLL_CALH5_bp 5 /* DFLL Calibration bits [12:7] bit 5 position. */ - -/* RST - Reset */ -/* RST.STATUS bit masks and bit positions */ -#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ -#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ - -#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ -#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ - -#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ -#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ - -#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ -#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ - -#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ -#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ - -#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ -#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ - -#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ -#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ - -/* RST.CTRL bit masks and bit positions */ -#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ -#define RST_SWRST_bp 0 /* Software Reset bit position. */ - -/* WDT - Watch-Dog Timer */ -/* WDT.CTRL bit masks and bit positions */ -#define WDT_PER_gm 0x3C /* Period group mask. */ -#define WDT_PER_gp 2 /* Period group position. */ -#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ -#define WDT_PER0_bp 2 /* Period bit 0 position. */ -#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ -#define WDT_PER1_bp 3 /* Period bit 1 position. */ -#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ -#define WDT_PER2_bp 4 /* Period bit 2 position. */ -#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ -#define WDT_PER3_bp 5 /* Period bit 3 position. */ - -#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ -#define WDT_ENABLE_bp 1 /* Enable bit position. */ - -#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ -#define WDT_CEN_bp 0 /* Change Enable bit position. */ - -/* WDT.WINCTRL bit masks and bit positions */ -#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ -#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ -#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ -#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ -#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ -#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ -#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ -#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ -#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ -#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ - -#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ -#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ - -#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ -#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ - -/* WDT.STATUS bit masks and bit positions */ -#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ -#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ - -/* MCU - MCU Control */ -/* MCU.MCUCR bit masks and bit positions */ -#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ -#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ - -/* MCU.EVSYSLOCK bit masks and bit positions */ -#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ -#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ - -#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ -#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ - -/* MCU.AWEXLOCK bit masks and bit positions */ -#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ -#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ - -#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ -#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ - -/* PMIC - Programmable Multi-level Interrupt Controller */ -/* PMIC.STATUS bit masks and bit positions */ -#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ -#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ - -#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ -#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ - -#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ -#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ - -#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ -#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ - -/* PMIC.INTPRI bit masks and bit positions */ -#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ -#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ -#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ -#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ -#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ -#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ -#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ -#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ -#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ -#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ -#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ -#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ -#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ -#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ -#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ -#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ -#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ -#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ - -/* PMIC.CTRL bit masks and bit positions */ -#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ -#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ - -#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ -#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ - -#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ -#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ - -#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ -#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ - -#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ -#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ - -/* CRC - Cyclic Redundancy Checker */ -/* CRC.CTRL bit masks and bit positions */ -#define CRC_RESET_gm 0xC0 /* Reset group mask. */ -#define CRC_RESET_gp 6 /* Reset group position. */ -#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ -#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ -#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ -#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ - -#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ -#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ - -#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ -#define CRC_SOURCE_gp 0 /* Input Source group position. */ -#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ -#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ -#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ -#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ -#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ -#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ -#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ -#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ - -/* CRC.STATUS bit masks and bit positions */ -#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ -#define CRC_ZERO_bp 1 /* Zero detection bit position. */ - -#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ -#define CRC_BUSY_bp 0 /* Busy bit position. */ - -/* EVSYS - Event System */ -/* EVSYS.CH0MUX bit masks and bit positions */ -#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ -#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ -#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ -#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ -#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ -#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ -#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ -#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ -#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ -#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ -#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ -#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ -#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ -#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ -#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ -#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ -#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ -#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ - -/* EVSYS.CH1MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH2MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH3MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH0CTRL bit masks and bit positions */ -#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ -#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ -#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ -#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ -#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ -#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ - -#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ -#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ - -#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ -#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ - -#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ -#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ -#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ -#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ -#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ -#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ -#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ -#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ - -/* EVSYS.CH1CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH2CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH3CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* NVM - Non Volatile Memory Controller */ -/* NVM.CMD bit masks and bit positions */ -#define NVM_CMD_gm 0xFF /* Command group mask. */ -#define NVM_CMD_gp 0 /* Command group position. */ -#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define NVM_CMD0_bp 0 /* Command bit 0 position. */ -#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define NVM_CMD1_bp 1 /* Command bit 1 position. */ -#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ -#define NVM_CMD2_bp 2 /* Command bit 2 position. */ -#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ -#define NVM_CMD3_bp 3 /* Command bit 3 position. */ -#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ -#define NVM_CMD4_bp 4 /* Command bit 4 position. */ -#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ -#define NVM_CMD5_bp 5 /* Command bit 5 position. */ -#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ -#define NVM_CMD6_bp 6 /* Command bit 6 position. */ -#define NVM_CMD7_bm (1<<7) /* Command bit 7 mask. */ -#define NVM_CMD7_bp 7 /* Command bit 7 position. */ - -/* NVM.CTRLA bit masks and bit positions */ -#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ -#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ - -/* NVM.CTRLB bit masks and bit positions */ -#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ -#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ - -#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ -#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ - -#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ -#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ - -#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ -#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ - -/* NVM.INTCTRL bit masks and bit positions */ -#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ -#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ -#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ -#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ -#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ -#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ - -#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ -#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ -#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ -#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ -#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ -#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ - -/* NVM.STATUS bit masks and bit positions */ -#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ -#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ - -#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ -#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ - -#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ -#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ - -#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ -#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ - -/* NVM.LOCKBITS bit masks and bit positions */ -#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ - -#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ - -#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ - -#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ -#define NVM_LB_gp 0 /* Lock Bits group position. */ -#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ -#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ - -/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ -#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ - -#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ - -#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ - -#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ -#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ -#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ -#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ - -/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ -#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ -#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ -#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ -#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ -#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ -#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ -#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ -#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ -#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ -#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ - -#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ -#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ -#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ -#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ -#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ -#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ -#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ -#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ -#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ -#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ - -/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ -#define NVM_FUSES_DVSDON_bm 0x80 /* Spike Detector Enable bit mask. */ -#define NVM_FUSES_DVSDON_bp 7 /* Spike Detector Enable bit position. */ - -#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ -#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ - -#define NVM_FUSES_TOSCSEL_bm 0x20 /* 32.768kHz Timer Oscillator Pin Selection bit mask. */ -#define NVM_FUSES_TOSCSEL_bp 5 /* 32.768kHz Timer Oscillator Pin Selection bit position. */ - -#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ -#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ -#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ -#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ -#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ -#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ - -/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ -#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ -#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ - -#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ -#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ -#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ -#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ -#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ -#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ - -#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ -#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ - -/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ -#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ -#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ -#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ -#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ -#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ -#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ - -#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ -#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ - -#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ -#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ -#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ -#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ -#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ -#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ -#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ -#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ - -/* AC - Analog Comparator */ -/* AC.AC0CTRL bit masks and bit positions */ -#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ -#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ -#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ -#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ -#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ -#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ - -#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ -#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ -#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ -#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ -#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ -#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ - -#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ -#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ - -#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ -#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ -#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ -#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ -#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ -#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ - -#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ -#define AC_ENABLE_bp 0 /* Enable bit position. */ - -/* AC.AC1CTRL bit masks and bit positions */ -/* AC_INTMODE Predefined. */ -/* AC_INTMODE Predefined. */ - -/* AC_INTLVL Predefined. */ -/* AC_INTLVL Predefined. */ - -/* AC_HSMODE Predefined. */ -/* AC_HSMODE Predefined. */ - -/* AC_HYSMODE Predefined. */ -/* AC_HYSMODE Predefined. */ - -/* AC_ENABLE Predefined. */ -/* AC_ENABLE Predefined. */ - -/* AC.AC0MUXCTRL bit masks and bit positions */ -#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ -#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ -#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ -#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ -#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ -#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ -#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ -#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ - -#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ -#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ -#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ -#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ -#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ -#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ -#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ -#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ - -/* AC.AC1MUXCTRL bit masks and bit positions */ -/* AC_MUXPOS Predefined. */ -/* AC_MUXPOS Predefined. */ - -/* AC_MUXNEG Predefined. */ -/* AC_MUXNEG Predefined. */ - -/* AC.CTRLA bit masks and bit positions */ -#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ -#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ - -/* AC.CTRLB bit masks and bit positions */ -#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ -#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ -#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ -#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ -#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ -#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ -#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ -#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ -#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ -#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ -#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ -#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ -#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ -#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ - -/* AC.WINCTRL bit masks and bit positions */ -#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ -#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ - -#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ -#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ -#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ -#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ -#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ -#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ - -#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ -#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ -#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ -#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ -#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ -#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ - -/* AC.STATUS bit masks and bit positions */ -#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ -#define AC_WSTATE_gp 6 /* Window Mode State group position. */ -#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ -#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ -#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ -#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ - -#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ -#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ - -#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ -#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ - -#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ -#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ - -#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ -#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ - -#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ -#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ - -/* ADC - Analog/Digital Converter */ -/* ADC_CH.CTRL bit masks and bit positions */ -#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ -#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ - -#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ -#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ -#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ -#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ -#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ -#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ -#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ -#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ - -#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ -#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ -#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ -#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ -#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ -#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ - -/* ADC_CH.MUXCTRL bit masks and bit positions */ -#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ -#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ -#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ -#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ -#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ -#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ -#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ -#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ -#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ -#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ - -#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ -#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ -#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ -#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ -#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ -#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ -#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ -#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ -#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ -#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ - -#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC input group mask. */ -#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ -#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ -#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ -#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ -#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ - -/* ADC_CH.INTCTRL bit masks and bit positions */ -#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ -#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ -#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ -#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ -#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ -#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ - -#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ -#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ - -/* ADC_CH.INTFLAGS bit masks and bit positions */ -#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ -#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ - -/* ADC_CH.SCAN bit masks and bit positions */ -#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ -#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ -#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ -#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ -#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ -#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ -#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ -#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ -#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ -#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ - -#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */ -#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */ -#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ -#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */ -#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ -#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */ -#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ -#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */ -#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ -#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */ - -/* ADC.CTRLA bit masks and bit positions */ -#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ -#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ - -#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ -#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ - -#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ -#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ - -/* ADC.CTRLB bit masks and bit positions */ -#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ -#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ -#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ -#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ -#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ -#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ - -#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ -#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ - -#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ -#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ - -#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ -#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ -#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ -#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ -#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ -#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ - -/* ADC.REFCTRL bit masks and bit positions */ -#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ -#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ -#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ -#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ -#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ -#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ -#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ -#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ - -#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ -#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ - -#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ -#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ - -/* ADC.EVCTRL bit masks and bit positions */ -#define ADC_EVSEL_gm 0x18 /* Event Input Select group mask. */ -#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ -#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ -#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ -#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ -#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ - -#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ -#define ADC_EVACT_gp 0 /* Event Action Select group position. */ -#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ -#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ -#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ -#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ -#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ -#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ - -/* ADC.PRESCALER bit masks and bit positions */ -#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ -#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ -#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ -#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ -#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ -#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ -#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ -#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ - -/* ADC.INTFLAGS bit masks and bit positions */ -#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ -#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ - -/* RTC - Real-Time Counter */ -/* RTC.CTRL bit masks and bit positions */ -#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ -#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ -#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ -#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ -#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ -#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ -#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ -#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ - -/* RTC.STATUS bit masks and bit positions */ -#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ -#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ - -/* RTC.INTCTRL bit masks and bit positions */ -#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ -#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ -#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ -#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ -#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ -#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ - -#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ -#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ -#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ -#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ -#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ -#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ - -/* RTC.INTFLAGS bit masks and bit positions */ -#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ -#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ - -#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - -/* TWI - Two-Wire Interface */ -/* TWI_MASTER.CTRLA bit masks and bit positions */ -#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ -#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ - -#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ -#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ - -#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ -#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ - -#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ -#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ - -/* TWI_MASTER.CTRLB bit masks and bit positions */ -#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Tisdahmeout group mask. */ -#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Tisdahmeout group position. */ -#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Tisdahmeout bit 0 mask. */ -#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Tisdahmeout bit 0 position. */ -#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Tisdahmeout bit 1 mask. */ -#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Tisdahmeout bit 1 position. */ - -#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ -#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ - -#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ - -/* TWI_MASTER.CTRLC bit masks and bit positions */ -#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ - -#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ -#define TWI_MASTER_CMD_gp 0 /* Command group position. */ -#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ -#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ - -/* TWI_MASTER.STATUS bit masks and bit positions */ -#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ -#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ - -#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ -#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ - -#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ - -#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ - -#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ -#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ - -#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ -#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ - -#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ -#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ -#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ -#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ -#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ -#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ - -/* TWI_SLAVE.CTRLA bit masks and bit positions */ -#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ -#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ - -#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ -#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ - -#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ -#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ - -#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ -#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ - -#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ -#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ - -#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ -#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ - -#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ - -/* TWI_SLAVE.CTRLB bit masks and bit positions */ -#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ - -#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ -#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ -#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ -#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ - -/* TWI_SLAVE.STATUS bit masks and bit positions */ -#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ -#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ - -#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ -#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ - -#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ - -#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ - -#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ -#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ - -#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ -#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ - -#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ -#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ - -#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ -#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ - -/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ -#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ -#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ -#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ -#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ -#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ -#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ -#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ -#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ -#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ -#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ -#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ -#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ -#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ -#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ -#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ -#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ - -#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ -#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ - -/* TWI.CTRL bit masks and bit positions */ -#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ -#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ -#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ -#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ -#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ -#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ - -#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ -#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ - -/* PORT - Port Configuration */ -/* PORTCFG.VPCTRLA bit masks and bit positions */ -#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ -#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ -#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ -#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ -#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ -#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ -#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ -#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ -#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ -#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ - -#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ -#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ -#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ -#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ -#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ -#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ -#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ -#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ -#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ -#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ - -/* PORTCFG.VPCTRLB bit masks and bit positions */ -#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ -#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ -#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ -#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ -#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ -#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ -#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ -#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ -#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ -#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ - -#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ -#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ -#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ -#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ -#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ -#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ -#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ -#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ -#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ -#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ - -/* PORTCFG.CLKEVOUT bit masks and bit positions */ -#define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */ -#define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */ -#define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */ -#define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */ -#define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */ -#define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */ - -#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ -#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ -#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ -#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ -#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ -#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ - -/* VPORT.INTFLAGS bit masks and bit positions */ -#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ - -#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ - -/* PORT.INTCTRL bit masks and bit positions */ -#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ -#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ -#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ -#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ -#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ -#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ - -#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ -#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ -#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ -#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ -#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ -#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ - -/* PORT.INTFLAGS bit masks and bit positions */ -#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ - -#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ - -/* PORT.REMAP bit masks and bit positions */ -#define PORT_SPI_bm 0x20 /* SPI Remap bit mask. */ -#define PORT_SPI_bp 5 /* SPI Remap bit position. */ - -#define PORT_USART0_bm 0x10 /* USART0 Remap bit mask. */ -#define PORT_USART0_bp 4 /* USART0 Remap bit position. */ - -#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ -#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ - -#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ -#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ - -#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ -#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ - -#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ -#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ - -/* PORT.PIN0CTRL bit masks and bit positions */ -#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ -#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ - -#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ -#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ - -#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ -#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ -#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ -#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ -#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ -#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ -#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ -#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ - -#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ -#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ -#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ -#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ -#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ -#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ -#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ -#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ - -/* PORT.PIN1CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN2CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN3CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN4CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN5CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN6CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN7CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* TC - 16-bit Timer/Counter With PWM */ -/* TC0.CTRLA bit masks and bit positions */ -#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - -/* TC0.CTRLB bit masks and bit positions */ -#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ -#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ - -#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ -#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ - -#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ - -#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ - -#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ -#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ - -/* TC0.CTRLC bit masks and bit positions */ -#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ -#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ - -#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ -#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ - -#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ - -#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ - -/* TC0.CTRLD bit masks and bit positions */ -#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ -#define TC0_EVACT_gp 5 /* Event Action group position. */ -#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ -#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ -#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ - -#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ -#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ - -#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ -#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ -#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - -/* TC0.CTRLE bit masks and bit positions */ -#define TC0_BYTEM_bm 0x01 /* Byte Mode bit mask. */ -#define TC0_BYTEM_bp 0 /* Byte Mode bit position. */ - -/* TC0.INTCTRLA bit masks and bit positions */ -#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ - -#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ - -/* TC0.INTCTRLB bit masks and bit positions */ -#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ -#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ -#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ -#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ -#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ -#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ - -#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ -#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ -#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ -#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ -#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ -#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ - -#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ - -#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ - -/* TC0.CTRLFCLR bit masks and bit positions */ -#define TC0_CMD_gm 0x0C /* Command group mask. */ -#define TC0_CMD_gp 2 /* Command group position. */ -#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC0_CMD0_bp 2 /* Command bit 0 position. */ -#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC0_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ -#define TC0_LUPD_bp 1 /* Lock Update bit position. */ - -#define TC0_DIR_bm 0x01 /* Direction bit mask. */ -#define TC0_DIR_bp 0 /* Direction bit position. */ - -/* TC0.CTRLFSET bit masks and bit positions */ -/* TC0_CMD Predefined. */ -/* TC0_CMD Predefined. */ - -/* TC0_LUPD Predefined. */ -/* TC0_LUPD Predefined. */ - -/* TC0_DIR Predefined. */ -/* TC0_DIR Predefined. */ - -/* TC0.CTRLGCLR bit masks and bit positions */ -#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ -#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ - -#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ -#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ - -#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ - -#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ - -#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ - -/* TC0.CTRLGSET bit masks and bit positions */ -/* TC0_CCDBV Predefined. */ -/* TC0_CCDBV Predefined. */ - -/* TC0_CCCBV Predefined. */ -/* TC0_CCCBV Predefined. */ - -/* TC0_CCBBV Predefined. */ -/* TC0_CCBBV Predefined. */ - -/* TC0_CCABV Predefined. */ -/* TC0_CCABV Predefined. */ - -/* TC0_PERBV Predefined. */ -/* TC0_PERBV Predefined. */ - -/* TC0.INTFLAGS bit masks and bit positions */ -#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ -#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ - -#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ -#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ - -#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ - -#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ - -#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ - -#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - -/* TC1.CTRLA bit masks and bit positions */ -#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - -/* TC1.CTRLB bit masks and bit positions */ -#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ - -#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ - -#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ -#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ - -/* TC1.CTRLC bit masks and bit positions */ -#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ - -#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ - -/* TC1.CTRLD bit masks and bit positions */ -#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ -#define TC1_EVACT_gp 5 /* Event Action group position. */ -#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ -#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ -#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ - -#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ -#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ - -#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ -#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ -#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - -/* TC1.CTRLE bit masks and bit positions */ -#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ -#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ - -/* TC1.INTCTRLA bit masks and bit positions */ -#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ - -#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ - -/* TC1.INTCTRLB bit masks and bit positions */ -#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ - -#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ - -/* TC1.CTRLFCLR bit masks and bit positions */ -#define TC1_CMD_gm 0x0C /* Command group mask. */ -#define TC1_CMD_gp 2 /* Command group position. */ -#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC1_CMD0_bp 2 /* Command bit 0 position. */ -#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC1_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ -#define TC1_LUPD_bp 1 /* Lock Update bit position. */ - -#define TC1_DIR_bm 0x01 /* Direction bit mask. */ -#define TC1_DIR_bp 0 /* Direction bit position. */ - -/* TC1.CTRLFSET bit masks and bit positions */ -/* TC1_CMD Predefined. */ -/* TC1_CMD Predefined. */ - -/* TC1_LUPD Predefined. */ -/* TC1_LUPD Predefined. */ - -/* TC1_DIR Predefined. */ -/* TC1_DIR Predefined. */ - -/* TC1.CTRLGCLR bit masks and bit positions */ -#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ - -#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ - -#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ - -/* TC1.CTRLGSET bit masks and bit positions */ -/* TC1_CCBBV Predefined. */ -/* TC1_CCBBV Predefined. */ - -/* TC1_CCABV Predefined. */ -/* TC1_CCABV Predefined. */ - -/* TC1_PERBV Predefined. */ -/* TC1_PERBV Predefined. */ - -/* TC1.INTFLAGS bit masks and bit positions */ -#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ - -#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ - -#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ - -#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - -/* AWEX.CTRL bit masks and bit positions */ -#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ -#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ - -#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ -#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ - -#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ -#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ - -#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ -#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ - -#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ -#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ - -#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ -#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ - -/* AWEX.FDCTRL bit masks and bit positions */ -#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ -#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ - -#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ -#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ - -#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ -#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ -#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ -#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ -#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ -#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ - -/* AWEX.STATUS bit masks and bit positions */ -#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ -#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ - -#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ -#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ - -#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ -#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ - -/* HIRES.CTRLA bit masks and bit positions */ -#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ -#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ -#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ -#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ -#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ -#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ - -/* USART - Universal Asynchronous Receiver-Transmitter */ -/* USART.STATUS bit masks and bit positions */ -#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ -#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ - -#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ -#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ - -#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ -#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ - -#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ -#define USART_FERR_bp 4 /* Frame Error bit position. */ - -#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ -#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ - -#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ -#define USART_PERR_bp 2 /* Parity Error bit position. */ - -#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ -#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ - -/* USART.CTRLA bit masks and bit positions */ -#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ -#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ -#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ -#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ -#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ -#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ - -#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ -#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ -#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ -#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ -#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ -#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ - -#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ -#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ -#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ -#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ -#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ -#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ - -/* USART.CTRLB bit masks and bit positions */ -#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ -#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ - -#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ -#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ - -#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ -#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ - -#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ -#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ - -#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ -#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ - -/* USART.CTRLC bit masks and bit positions */ -#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ -#define USART_CMODE_gp 6 /* Communication Mode group position. */ -#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ -#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ -#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ -#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ - -#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ -#define USART_PMODE_gp 4 /* Parity Mode group position. */ -#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ -#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ -#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ -#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ - -#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ -#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ - -#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ -#define USART_CHSIZE_gp 0 /* Character Size group position. */ -#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ -#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ -#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ -#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ -#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ -#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ - -#define USART_UDORD_bm 0x04 /* SPI Master Mode, Data Order bit mask. */ -#define USART_UDORD_bp 2 /* SPI Master Mode, Data Order bit position. */ - -#define USART_UCPHA_bm 0x02 /* SPI Master Mode, Clock Phase bit mask. */ -#define USART_UCPHA_bp 1 /* SPI Master Mode, Clock Phase bit position. */ - -/* USART.BAUDCTRLA bit masks and bit positions */ -#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ -#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ -#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ -#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ -#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ -#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ -#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ -#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ -#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ -#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ -#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ -#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ -#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ -#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ -#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ -#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ -#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ -#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ - -/* USART.BAUDCTRLB bit masks and bit positions */ -#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ -#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ -#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ -#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ -#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ -#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ -#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ -#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ -#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ -#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ - -/* USART_BSEL Predefined. */ -/* USART_BSEL Predefined. */ - -/* SPI - Serial Peripheral Interface */ -/* SPI.CTRL bit masks and bit positions */ -#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ -#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ - -#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ -#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ - -#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ -#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ - -#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ -#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ - -#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ -#define SPI_MODE_gp 2 /* SPI Mode group position. */ -#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ -#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ -#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ -#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ - -#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ -#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ -#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ -#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ -#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ -#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ - -/* SPI.INTCTRL bit masks and bit positions */ -#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ -#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ -#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ - -/* SPI.STATUS bit masks and bit positions */ -#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ -#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ - -#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ -#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ - -/* IRCOM - IR Communication Module */ -/* IRCOM.CTRL bit masks and bit positions */ -#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ -#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ -#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ -#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ -#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ -#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ -#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ -#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ -#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ -#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ - - - -// Generic Port Pins - -#define PIN0_bm 0x01 -#define PIN0_bp 0 -#define PIN1_bm 0x02 -#define PIN1_bp 1 -#define PIN2_bm 0x04 -#define PIN2_bp 2 -#define PIN3_bm 0x08 -#define PIN3_bp 3 -#define PIN4_bm 0x10 -#define PIN4_bp 4 -#define PIN5_bm 0x20 -#define PIN5_bp 5 -#define PIN6_bm 0x40 -#define PIN6_bp 6 -#define PIN7_bm 0x80 -#define PIN7_bp 7 - -/* ========== Interrupt Vector Definitions ========== */ -/* Vector 0 is the reset vector */ - -/* OSC interrupt vectors */ -#define OSC_OSCF_vect_num 1 -#define OSC_OSCF_vect _VECTOR(1) /* External Oscillator Failure Interrupt (NMI) */ - -/* PORTC interrupt vectors */ -#define PORTC_INT0_vect_num 2 -#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ -#define PORTC_INT1_vect_num 3 -#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ - -/* PORTR interrupt vectors */ -#define PORTR_INT0_vect_num 4 -#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ -#define PORTR_INT1_vect_num 5 -#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ - -/* RTC interrupt vectors */ -#define RTC_OVF_vect_num 10 -#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ -#define RTC_COMP_vect_num 11 -#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ - -/* TWIC interrupt vectors */ -#define TWIC_TWIS_vect_num 12 -#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ -#define TWIC_TWIM_vect_num 13 -#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_OVF_vect_num 14 -#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ -#define TCC0_ERR_vect_num 15 -#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ -#define TCC0_CCA_vect_num 16 -#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ -#define TCC0_CCB_vect_num 17 -#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ -#define TCC0_CCC_vect_num 18 -#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ -#define TCC0_CCD_vect_num 19 -#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ - -/* TCC1 interrupt vectors */ -#define TCC1_OVF_vect_num 20 -#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ -#define TCC1_ERR_vect_num 21 -#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ -#define TCC1_CCA_vect_num 22 -#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ -#define TCC1_CCB_vect_num 23 -#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ - -/* SPIC interrupt vectors */ -#define SPIC_INT_vect_num 24 -#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ - -/* USARTC0 interrupt vectors */ -#define USARTC0_RXC_vect_num 25 -#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ -#define USARTC0_DRE_vect_num 26 -#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ -#define USARTC0_TXC_vect_num 27 -#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ - -/* NVM interrupt vectors */ -#define NVM_EE_vect_num 32 -#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ -#define NVM_SPM_vect_num 33 -#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ - -/* PORTB interrupt vectors */ -#define PORTB_INT0_vect_num 34 -#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ -#define PORTB_INT1_vect_num 35 -#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ - -/* PORTE interrupt vectors */ -#define PORTE_INT0_vect_num 43 -#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ -#define PORTE_INT1_vect_num 44 -#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ - -/* TWIE interrupt vectors */ -#define TWIE_TWIS_vect_num 45 -#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ -#define TWIE_TWIM_vect_num 46 -#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_OVF_vect_num 47 -#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ -#define TCE0_ERR_vect_num 48 -#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ -#define TCE0_CCA_vect_num 49 -#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ -#define TCE0_CCB_vect_num 50 -#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ -#define TCE0_CCC_vect_num 51 -#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ -#define TCE0_CCD_vect_num 52 -#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ - -/* USARTE0 interrupt vectors */ -#define USARTE0_RXC_vect_num 58 -#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ -#define USARTE0_DRE_vect_num 59 -#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ -#define USARTE0_TXC_vect_num 60 -#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ - -/* PORTD interrupt vectors */ -#define PORTD_INT0_vect_num 64 -#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ -#define PORTD_INT1_vect_num 65 -#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ - -/* PORTA interrupt vectors */ -#define PORTA_INT0_vect_num 66 -#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ -#define PORTA_INT1_vect_num 67 -#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ - -/* ACA interrupt vectors */ -#define ACA_AC0_vect_num 68 -#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ -#define ACA_AC1_vect_num 69 -#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ -#define ACA_ACW_vect_num 70 -#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ - -/* ADCA interrupt vectors */ -#define ADCA_CH0_vect_num 71 -#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ - -/* TCD0 interrupt vectors */ -#define TCD0_OVF_vect_num 77 -#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ -#define TCD0_ERR_vect_num 78 -#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ -#define TCD0_CCA_vect_num 79 -#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ -#define TCD0_CCB_vect_num 80 -#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ -#define TCD0_CCC_vect_num 81 -#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ -#define TCD0_CCD_vect_num 82 -#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ - -/* SPID interrupt vectors */ -#define SPID_INT_vect_num 87 -#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ - -/* USARTD0 interrupt vectors */ -#define USARTD0_RXC_vect_num 88 -#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ -#define USARTD0_DRE_vect_num 89 -#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ -#define USARTD0_TXC_vect_num 90 -#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ - -/* PORTF interrupt vectors */ -#define PORTF_INT0_vect_num 104 -#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ -#define PORTF_INT1_vect_num 105 -#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ - -/* TCF0 interrupt vectors */ -#define TCF0_OVF_vect_num 108 -#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ -#define TCF0_ERR_vect_num 109 -#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ -#define TCF0_CCA_vect_num 110 -#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ -#define TCF0_CCB_vect_num 111 -#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ -#define TCF0_CCC_vect_num 112 -#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ -#define TCF0_CCD_vect_num 113 -#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ - -#define _VECTOR_SIZE 4 /* Size of individual vector. */ -#define _VECTORS_SIZE (114 * _VECTOR_SIZE) - - -/* ========== Constants ========== */ - -#define PROGMEM_START (0x0000) -#define PROGMEM_SIZE (36864) -#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) - -#define APP_SECTION_START (0x0000) -#define APP_SECTION_SIZE (32768) -#define APP_SECTION_PAGE_SIZE (256) -#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) - -#define APPTABLE_SECTION_START (0x7000) -#define APPTABLE_SECTION_SIZE (4096) -#define APPTABLE_SECTION_PAGE_SIZE (256) -#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) - -#define BOOT_SECTION_START (0x8000) -#define BOOT_SECTION_SIZE (4096) -#define BOOT_SECTION_PAGE_SIZE (256) -#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) - -#define DATAMEM_START (0x0000) -#define DATAMEM_SIZE (12288) -#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) - -#define IO_START (0x0000) -#define IO_SIZE (4096) -#define IO_PAGE_SIZE (0) -#define IO_END (IO_START + IO_SIZE - 1) - -#define MAPPED_EEPROM_START (0x1000) -#define MAPPED_EEPROM_SIZE (1024) -#define MAPPED_EEPROM_PAGE_SIZE (0) -#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) - -#define INTERNAL_SRAM_START (0x2000) -#define INTERNAL_SRAM_SIZE (4096) -#define INTERNAL_SRAM_PAGE_SIZE (0) -#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) - -#define EEPROM_START (0x0000) -#define EEPROM_SIZE (1024) -#define EEPROM_PAGE_SIZE (32) -#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) - -#define SIGNATURES_START (0x0000) -#define SIGNATURES_SIZE (3) -#define SIGNATURES_PAGE_SIZE (0) -#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) - -#define FUSES_START (0x0000) -#define FUSES_SIZE (6) -#define FUSES_PAGE_SIZE (0) -#define FUSES_END (FUSES_START + FUSES_SIZE - 1) - -#define LOCKBITS_START (0x0000) -#define LOCKBITS_SIZE (1) -#define LOCKBITS_PAGE_SIZE (0) -#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) - -#define USER_SIGNATURES_START (0x0000) -#define USER_SIGNATURES_SIZE (256) -#define USER_SIGNATURES_PAGE_SIZE (256) -#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) - -#define PROD_SIGNATURES_START (0x0000) -#define PROD_SIGNATURES_SIZE (52) -#define PROD_SIGNATURES_PAGE_SIZE (256) -#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) - -#define FLASHSTART PROGMEM_START -#define FLASHEND PROGMEM_END -#define SPM_PAGESIZE 256 -#define RAMSTART INTERNAL_SRAM_START -#define RAMSIZE INTERNAL_SRAM_SIZE -#define RAMEND INTERNAL_SRAM_END -#define E2END EEPROM_END -#define E2PAGESIZE EEPROM_PAGE_SIZE - - -/* ========== Fuses ========== */ -#define FUSE_MEMORY_SIZE 6 - -/* Fuse Byte 0 Reserved */ - -/* Fuse Byte 1 */ -#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ -#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ -#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ -#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ -#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ -#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ -#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ -#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ -#define FUSE1_DEFAULT (0xFF) - -/* Fuse Byte 2 */ -#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ -#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ -#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* 32.768kHz Timer Oscillator Pin Selection */ -#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ -#define FUSE_DVSDON (unsigned char)~_BV(7) /* Spike Detector Enable */ -#define FUSE2_DEFAULT (0xFF) - -/* Fuse Byte 3 Reserved */ - -/* Fuse Byte 4 */ -#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ -#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ -#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ -#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ -#define FUSE4_DEFAULT (0xFF) - -/* Fuse Byte 5 */ -#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ -#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ -#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ -#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ -#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ -#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ -#define FUSE5_DEFAULT (0xFF) - -/* ========== Lock Bits ========== */ -#define __LOCK_BITS_EXIST -#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST -#define __BOOT_LOCK_APPLICATION_BITS_EXIST -#define __BOOT_LOCK_BOOT_BITS_EXIST - -/* ========== Signature ========== */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x95 -#define SIGNATURE_2 0x4A - -/* ========== Power Reduction Condition Definitions ========== */ - -/* PR.PRGEN */ -#define __AVR_HAVE_PRGEN (PR_RTC_bm|PR_EVSYS_bm) -#define __AVR_HAVE_PRGEN_RTC -#define __AVR_HAVE_PRGEN_EVSYS - -/* PR.PRPA */ -#define __AVR_HAVE_PRPA (PR_ADC_bm|PR_AC_bm) -#define __AVR_HAVE_PRPA_ADC -#define __AVR_HAVE_PRPA_AC - -/* PR.PRPC */ -#define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPC_TWI -#define __AVR_HAVE_PRPC_USART0 -#define __AVR_HAVE_PRPC_SPI -#define __AVR_HAVE_PRPC_HIRES -#define __AVR_HAVE_PRPC_TC1 -#define __AVR_HAVE_PRPC_TC0 - -/* PR.PRPD */ -#define __AVR_HAVE_PRPD (PR_USART0_bm|PR_SPI_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPD_USART0 -#define __AVR_HAVE_PRPD_SPI -#define __AVR_HAVE_PRPD_TC0 - -/* PR.PRPE */ -#define __AVR_HAVE_PRPE (PR_TWI_bm|PR_USART0_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPE_TWI -#define __AVR_HAVE_PRPE_USART0 -#define __AVR_HAVE_PRPE_TC0 - -/* PR.PRPF */ -#define __AVR_HAVE_PRPF (PR_USART0_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPF_USART0 -#define __AVR_HAVE_PRPF_TC0 - - -#endif /* #ifdef _AVR_ATXMEGA32D3_H_INCLUDED */ - +/***************************************************************************** + * + * Copyright (C) 2016 Atmel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * * Neither the name of the copyright holders nor the names of + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ****************************************************************************/ + + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iox32d3.h" +#else +# error "Attempt to include more than one file." +#endif + +#ifndef _AVR_ATXMEGA32D3_H_INCLUDED +#define _AVR_ATXMEGA32D3_H_INCLUDED + +/* Ungrouped common registers */ +#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ + +/* Deprecated */ +#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ + +#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ +#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ +#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ +#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ +#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ +#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +#define SREG _SFR_MEM8(0x003F) /* Status Register */ + +/* C Language Only */ +#if !defined (__ASSEMBLER__) + +#include + +typedef volatile uint8_t register8_t; +typedef volatile uint16_t register16_t; +typedef volatile uint32_t register32_t; + + +#ifdef _WORDREGISTER +#undef _WORDREGISTER +#endif +#define _WORDREGISTER(regname) \ + __extension__ union \ + { \ + register16_t regname; \ + struct \ + { \ + register8_t regname ## L; \ + register8_t regname ## H; \ + }; \ + } + +#ifdef _DWORDREGISTER +#undef _DWORDREGISTER +#endif +#define _DWORDREGISTER(regname) \ + __extension__ union \ + { \ + register32_t regname; \ + struct \ + { \ + register8_t regname ## 0; \ + register8_t regname ## 1; \ + register8_t regname ## 2; \ + register8_t regname ## 3; \ + }; \ + } + + +/* +========================================================================== +IO Module Structures +========================================================================== +*/ + + +/* +-------------------------------------------------------------------------- +XOCD - On-Chip Debug System +-------------------------------------------------------------------------- +*/ + +/* On-Chip Debug System */ +typedef struct OCD_struct +{ + register8_t OCDR0; /* OCD Register 0 */ + register8_t OCDR1; /* OCD Register 1 */ +} OCD_t; + + +/* +-------------------------------------------------------------------------- +CPU - CPU +-------------------------------------------------------------------------- +*/ + +/* CCP signatures */ +typedef enum CCP_enum +{ + CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ + CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +} CCP_t; + + +/* +-------------------------------------------------------------------------- +CLK - Clock System +-------------------------------------------------------------------------- +*/ + +/* Clock System */ +typedef struct CLK_struct +{ + register8_t CTRL; /* Control Register */ + register8_t PSCTRL; /* Prescaler Control Register */ + register8_t LOCK; /* Lock register */ + register8_t RTCCTRL; /* RTC Control Register */ + register8_t reserved_0x04; +} CLK_t; + + +/* Power Reduction */ +typedef struct PR_struct +{ + register8_t PRGEN; /* General Power Reduction */ + register8_t PRPA; /* Power Reduction Port A */ + register8_t reserved_0x02; + register8_t PRPC; /* Power Reduction Port C */ + register8_t PRPD; /* Power Reduction Port D */ + register8_t PRPE; /* Power Reduction Port E */ + register8_t PRPF; /* Power Reduction Port F */ +} PR_t; + +/* System Clock Selection */ +typedef enum CLK_SCLKSEL_enum +{ + CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ + CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ + CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ + CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ + CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ +} CLK_SCLKSEL_t; + +/* Prescaler A Division Factor */ +typedef enum CLK_PSADIV_enum +{ + CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ + CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ + CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ + CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ + CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ + CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ + CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ + CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ + CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ + CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ +} CLK_PSADIV_t; + +/* Prescaler B and C Division Factor */ +typedef enum CLK_PSBCDIV_enum +{ + CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ + CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ + CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ + CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ +} CLK_PSBCDIV_t; + +/* RTC Clock Source */ +typedef enum CLK_RTCSRC_enum +{ + CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1 kHz from internal 32kHz ULP */ + CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ + CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from 32.768 kHz internal oscillator */ + CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ + CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from 32.768 kHz internal oscillator */ + CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ +} CLK_RTCSRC_t; + + +/* +-------------------------------------------------------------------------- +SLEEP - Sleep Controller +-------------------------------------------------------------------------- +*/ + +/* Sleep Controller */ +typedef struct SLEEP_struct +{ + register8_t CTRL; /* Control Register */ +} SLEEP_t; + +/* Sleep Mode */ +typedef enum SLEEP_SMODE_enum +{ + SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ + SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ + SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ + SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ + SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ +} SLEEP_SMODE_t; + + + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +#define SLEEP_MODE_PWR_SAVE (0x03<<1) +#define SLEEP_MODE_STANDBY (0x06<<1) +#define SLEEP_MODE_EXT_STANDBY (0x07<<1) +/* +-------------------------------------------------------------------------- +OSC - Oscillator +-------------------------------------------------------------------------- +*/ + +/* Oscillator */ +typedef struct OSC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t XOSCCTRL; /* External Oscillator Control Register */ + register8_t XOSCFAIL; /* External Oscillator Failure Detection Register */ + register8_t RC32KCAL; /* 32kHz Internal Oscillator Calibration Register */ + register8_t PLLCTRL; /* PLL Control REgister */ + register8_t DFLLCTRL; /* DFLL Control Register */ +} OSC_t; + +/* Oscillator Frequency Range */ +typedef enum OSC_FRQRANGE_enum +{ + OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ + OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ + OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ + OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ +} OSC_FRQRANGE_t; + +/* External Oscillator Selection and Startup Time */ +typedef enum OSC_XOSCSEL_enum +{ + OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ + OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */ + OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */ + OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */ + OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */ +} OSC_XOSCSEL_t; + +/* PLL Clock Source */ +typedef enum OSC_PLLSRC_enum +{ + OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2MHz RC Oscillator */ + OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32MHz RC Oscillator */ + OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ +} OSC_PLLSRC_t; + + +/* +-------------------------------------------------------------------------- +DFLL - DFLL +-------------------------------------------------------------------------- +*/ + +/* DFLL */ +typedef struct DFLL_struct +{ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x01; + register8_t CALA; /* Calibration Register A */ + register8_t CALB; /* Calibration Register B */ + register8_t COMP0; /* Oscillator Compare Register 0 */ + register8_t COMP1; /* Oscillator Compare Register 1 */ + register8_t COMP2; /* Oscillator Compare Register 2 */ + register8_t reserved_0x07; +} DFLL_t; + + +/* +-------------------------------------------------------------------------- +RST - Reset +-------------------------------------------------------------------------- +*/ + +/* Reset */ +typedef struct RST_struct +{ + register8_t STATUS; /* Status Register */ + register8_t CTRL; /* Control Register */ +} RST_t; + + +/* +-------------------------------------------------------------------------- +WDT - Watch-Dog Timer +-------------------------------------------------------------------------- +*/ + +/* Watch-Dog Timer */ +typedef struct WDT_struct +{ + register8_t CTRL; /* Control */ + register8_t WINCTRL; /* Windowed Mode Control */ + register8_t STATUS; /* Status */ +} WDT_t; + +/* Period setting */ +typedef enum WDT_PER_enum +{ + WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ + WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ + WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ + WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ + WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ + WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ + WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ + WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ + WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ + WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ + WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +} WDT_PER_t; + +/* Closed window period */ +typedef enum WDT_WPER_enum +{ + WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ + WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ + WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ + WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ + WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ + WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ + WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ + WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ + WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ + WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ + WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +} WDT_WPER_t; + + +/* +-------------------------------------------------------------------------- +MCU - MCU Control +-------------------------------------------------------------------------- +*/ + +/* MCU Control */ +typedef struct MCU_struct +{ + register8_t DEVID0; /* Device ID byte 0 */ + register8_t DEVID1; /* Device ID byte 1 */ + register8_t DEVID2; /* Device ID byte 2 */ + register8_t REVID; /* Revision ID */ + register8_t JTAGUID; /* JTAG User ID */ + register8_t reserved_0x05; + register8_t MCUCR; /* MCU Control */ + register8_t reserved_0x07; + register8_t EVSYSLOCK; /* Event System Lock */ + register8_t AWEXLOCK; /* AWEX Lock */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; +} MCU_t; + + +/* +-------------------------------------------------------------------------- +PMIC - Programmable Multi-level Interrupt Controller +-------------------------------------------------------------------------- +*/ + +/* Programmable Multi-level Interrupt Controller */ +typedef struct PMIC_struct +{ + register8_t STATUS; /* Status Register */ + register8_t INTPRI; /* Interrupt Priority */ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x03; + register8_t reserved_0x04; + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; +} PMIC_t; + + +/* +-------------------------------------------------------------------------- +CRC - Cyclic Redundancy Checker +-------------------------------------------------------------------------- +*/ + +/* Cyclic Redundancy Checker */ +typedef struct CRC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t reserved_0x02; + register8_t DATAIN; /* Data Input */ + register8_t CHECKSUM0; /* Checksum byte 0 */ + register8_t CHECKSUM1; /* Checksum byte 1 */ + register8_t CHECKSUM2; /* Checksum byte 2 */ + register8_t CHECKSUM3; /* Checksum byte 3 */ +} CRC_t; + +/* Reset */ +typedef enum CRC_RESET_enum +{ + CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ + CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ + CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ +} CRC_RESET_t; + +/* Input Source */ +typedef enum CRC_SOURCE_enum +{ + CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ + CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ + CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ +} CRC_SOURCE_t; + + +/* +-------------------------------------------------------------------------- +EVSYS - Event System +-------------------------------------------------------------------------- +*/ + +/* Event System */ +typedef struct EVSYS_struct +{ + register8_t CH0MUX; /* Event Channel 0 Multiplexer */ + register8_t CH1MUX; /* Event Channel 1 Multiplexer */ + register8_t CH2MUX; /* Event Channel 2 Multiplexer */ + register8_t CH3MUX; /* Event Channel 3 Multiplexer */ + register8_t reserved_0x04; + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t CH0CTRL; /* Channel 0 Control Register */ + register8_t CH1CTRL; /* Channel 1 Control Register */ + register8_t CH2CTRL; /* Channel 2 Control Register */ + register8_t CH3CTRL; /* Channel 3 Control Register */ + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t STROBE; /* Event Strobe */ + register8_t DATA; /* Event Data */ +} EVSYS_t; + +/* Quadrature Decoder Index Recognition Mode */ +typedef enum EVSYS_QDIRM_enum +{ + EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ + EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ + EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ + EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ +} EVSYS_QDIRM_t; + +/* Digital filter coefficient */ +typedef enum EVSYS_DIGFILT_enum +{ + EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ + EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ + EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ + EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ + EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ + EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ + EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ + EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ +} EVSYS_DIGFILT_t; + +/* Event Channel multiplexer input selection */ +typedef enum EVSYS_CHMUX_enum +{ + EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ + EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ + EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ + EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ + EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ + EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ + EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ + EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ + EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ + EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ + EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ + EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ + EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ + EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ + EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ + EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ + EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ + EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ + EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ + EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ + EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ + EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ + EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ + EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ + EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ + EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ + EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ + EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ + EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ + EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ + EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ + EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ + EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ + EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ + EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ + EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ + EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ + EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ + EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ + EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ + EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ + EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ + EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ + EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ + EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ + EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ + EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ + EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ + EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ + EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ + EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ + EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ + EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ + EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ + EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ + EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ + EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ + EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ + EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ + EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ + EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ + EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ + EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ + EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ + EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ + EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ + EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ + EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ + EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ + EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ + EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ + EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ + EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ + EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ + EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ + EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ + EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ + EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ + EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ + EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ + EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ + EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ + EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ + EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ + EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ + EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ + EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ + EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ + EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ + EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ + EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ + EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ + EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ + EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ + EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ + EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ + EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ + EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ +} EVSYS_CHMUX_t; + + +/* +-------------------------------------------------------------------------- +NVM - Non Volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Non-volatile Memory Controller */ +typedef struct NVM_struct +{ + register8_t ADDR0; /* Address Register 0 */ + register8_t ADDR1; /* Address Register 1 */ + register8_t ADDR2; /* Address Register 2 */ + register8_t reserved_0x03; + register8_t DATA0; /* Data Register 0 */ + register8_t DATA1; /* Data Register 1 */ + register8_t DATA2; /* Data Register 2 */ + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t CMD; /* Command */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t reserved_0x0E; + register8_t STATUS; /* Status */ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ +} NVM_t; + + +/* Lock Bits */ +typedef struct NVM_LOCKBITS_struct +{ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ +} NVM_LOCKBITS_t; + + +/* Fuses */ +typedef struct NVM_FUSES_struct +{ + register8_t reserved_0x00; + register8_t FUSEBYTE1; /* Watchdog Configuration */ + register8_t FUSEBYTE2; /* Reset Configuration */ + register8_t reserved_0x03; + register8_t FUSEBYTE4; /* Start-up Configuration */ + register8_t FUSEBYTE5; /* EESAVE and BOD Level */ +} NVM_FUSES_t; + + +/* Production Signatures */ +typedef struct NVM_PROD_SIGNATURES_struct +{ + register8_t RCOSC2M; /* RCOSC 2MHz Calibration Value */ + register8_t reserved_0x01; + register8_t RCOSC32K; /* RCOSC 32kHz Calibration Value */ + register8_t RCOSC32M; /* RCOSC 32MHz Calibration Value */ + register8_t reserved_0x04; + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ + register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ + register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ + register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ + register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ + register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t WAFNUM; /* Wafer Number */ + register8_t reserved_0x11; + register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ + register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ + register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ + register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ + register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ + register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ + register8_t reserved_0x26; + register8_t reserved_0x27; + register8_t reserved_0x28; + register8_t reserved_0x29; + register8_t reserved_0x2A; + register8_t reserved_0x2B; + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ + register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 0 */ + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + register8_t reserved_0x36; + register8_t reserved_0x37; + register8_t reserved_0x38; + register8_t reserved_0x39; + register8_t reserved_0x3A; + register8_t reserved_0x3B; + register8_t reserved_0x3C; + register8_t reserved_0x3D; + register8_t reserved_0x3E; +} NVM_PROD_SIGNATURES_t; + +/* NVM Command */ +typedef enum NVM_CMD_enum +{ + NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ + NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ + NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ + NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ + NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ + NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ + NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ + NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ + NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ + NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ + NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ + NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ + NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ + NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ + NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ + NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash page */ + NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ + NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ + NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash page */ + NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase and Write Flash page */ + NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ + NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ + NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ + NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ + NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ + NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ + NVM_CMD_APP_CRC_gc = (0x38<<0), /* Generate Application section CRC */ + NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Generate Boot Section CRC */ + NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Generate Flash Range CRC */ +} NVM_CMD_t; + +/* SPM ready interrupt level */ +typedef enum NVM_SPMLVL_enum +{ + NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ + NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ + NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ + NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ +} NVM_SPMLVL_t; + +/* EEPROM ready interrupt level */ +typedef enum NVM_EELVL_enum +{ + NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ + NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ + NVM_EELVL_HI_gc = (0x03<<0), /* High level */ +} NVM_EELVL_t; + +/* Boot lock bits - boot setcion */ +typedef enum NVM_BLBB_enum +{ + NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ + NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ + NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ + NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ +} NVM_BLBB_t; + +/* Boot lock bits - application section */ +typedef enum NVM_BLBA_enum +{ + NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ + NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ + NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ + NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ +} NVM_BLBA_t; + +/* Boot lock bits - application table section */ +typedef enum NVM_BLBAT_enum +{ + NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ + NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ + NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ + NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ +} NVM_BLBAT_t; + +/* Lock bits */ +typedef enum NVM_LB_enum +{ + NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ + NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ + NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ +} NVM_LB_t; + +/* Boot Loader Section Reset Vector */ +typedef enum BOOTRST_enum +{ + BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ + BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ +} BOOTRST_t; + +/* 32.768kHz Timer Oscillator Pin Selection */ +typedef enum TOSCSEL_enum +{ + TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1/2 on separate pins */ + TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1/2 shared with XTAL */ +} TOSCSEL_t; + +/* BOD operation */ +typedef enum BOD_enum +{ + BOD_INSAMPLEDMODE_gc = (0x01<<4), /* BOD enabled in sampled mode */ + BOD_CONTINOUSLY_gc = (0x02<<4), /* BOD enabled continuously */ + BOD_DISABLED_gc = (0x03<<4), /* BOD Disabled */ +} BOD_t; + +/* Watchdog (Window) Timeout Period */ +typedef enum WD_enum +{ + WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ + WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ + WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ + WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ + WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ + WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ + WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ + WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ + WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ + WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ + WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ +} WD_t; + +/* Start-up Time */ +typedef enum SUT_enum +{ + SUT_0MS_gc = (0x03<<2), /* 0 ms */ + SUT_4MS_gc = (0x01<<2), /* 4 ms */ + SUT_64MS_gc = (0x00<<2), /* 64 ms */ +} SUT_t; + +/* Brownout Detection Voltage Level */ +typedef enum BODLVL_enum +{ + BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ + BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ + BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ + BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ + BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ + BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ + BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ + BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ +} BODLVL_t; + + +/* +-------------------------------------------------------------------------- +AC - Analog Comparator +-------------------------------------------------------------------------- +*/ + +/* Analog Comparator */ +typedef struct AC_struct +{ + register8_t AC0CTRL; /* Analog Comparator 0 Control */ + register8_t AC1CTRL; /* Analog Comparator 1 Control */ + register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ + register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t WINCTRL; /* Window Mode Control */ + register8_t STATUS; /* Status */ +} AC_t; + +/* Interrupt mode */ +typedef enum AC_INTMODE_enum +{ + AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ + AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ + AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ +} AC_INTMODE_t; + +/* Interrupt level */ +typedef enum AC_INTLVL_enum +{ + AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ + AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ + AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ + AC_INTLVL_HI_gc = (0x03<<4), /* High level */ +} AC_INTLVL_t; + +/* Hysteresis mode selection */ +typedef enum AC_HYSMODE_enum +{ + AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ + AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ + AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ +} AC_HYSMODE_t; + +/* Positive input multiplexer selection */ +typedef enum AC_MUXPOS_enum +{ + AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ + AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ + AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ + AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ + AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ + AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ + AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ + AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ +} AC_MUXPOS_t; + +/* Negative input multiplexer selection */ +typedef enum AC_MUXNEG_enum +{ + AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ + AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ + AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ + AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ + AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ + AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ + AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ + AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ +} AC_MUXNEG_t; + +/* Windows interrupt mode */ +typedef enum AC_WINTMODE_enum +{ + AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ + AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ + AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ + AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ +} AC_WINTMODE_t; + +/* Window interrupt level */ +typedef enum AC_WINTLVL_enum +{ + AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ + AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ + AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ +} AC_WINTLVL_t; + +/* Window mode state */ +typedef enum AC_WSTATE_enum +{ + AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ + AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ + AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ +} AC_WSTATE_t; + + +/* +-------------------------------------------------------------------------- +ADC - Analog/Digital Converter +-------------------------------------------------------------------------- +*/ + +/* ADC Channel */ +typedef struct ADC_CH_struct +{ + register8_t CTRL; /* Control Register */ + register8_t MUXCTRL; /* MUX Control */ + register8_t INTCTRL; /* Channel Interrupt Control Register */ + register8_t INTFLAGS; /* Interrupt Flags */ + _WORDREGISTER(RES); /* Channel Result */ + register8_t SCAN; /* Input Channel Scan */ + register8_t reserved_0x07; +} ADC_CH_t; + + +/* Analog-to-Digital Converter */ +typedef struct ADC_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t REFCTRL; /* Reference Control */ + register8_t EVCTRL; /* Event Control */ + register8_t PRESCALER; /* Clock Prescaler */ + register8_t reserved_0x05; + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary Register */ + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + _WORDREGISTER(CAL); /* Calibration Value */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + _WORDREGISTER(CH0RES); /* Channel 0 Result */ + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + _WORDREGISTER(CMP); /* Compare Value */ + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + ADC_CH_t CH0; /* ADC Channel 0 */ +} ADC_t; + +/* Current Limitation */ +typedef enum ADC_CURRLIMIT_enum +{ + ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ + ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 250ksps max sampling rate */ + ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ + ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 50ksps max sampling rate */ +} ADC_CURRLIMIT_t; + +/* Positive input multiplexer selection */ +typedef enum ADC_CH_MUXPOS_enum +{ + ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ + ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ + ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ + ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ + ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ + ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ + ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ + ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ + ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ + ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ + ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ + ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ + ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ + ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ + ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ + ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ +} ADC_CH_MUXPOS_t; + +/* Internal input multiplexer selections */ +typedef enum ADC_CH_MUXINT_enum +{ + ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ + ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ + ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ +} ADC_CH_MUXINT_t; + +/* Negative input multiplexer selection */ +typedef enum ADC_CH_MUXNEG_enum +{ + ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ + ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ + ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ + ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ + ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */ + ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */ + ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */ + ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */ +} ADC_CH_MUXNEG_t; + +/* Input mode */ +typedef enum ADC_CH_INPUTMODE_enum +{ + ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ + ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ + ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ + ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ +} ADC_CH_INPUTMODE_t; + +/* Gain factor */ +typedef enum ADC_CH_GAIN_enum +{ + ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ + ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ + ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ + ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ + ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ + ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ + ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ + ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ +} ADC_CH_GAIN_t; + +/* Conversion result resolution */ +typedef enum ADC_RESOLUTION_enum +{ + ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ + ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ + ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ +} ADC_RESOLUTION_t; + +/* Voltage reference selection */ +typedef enum ADC_REFSEL_enum +{ + ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ + ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ + ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ + ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ + ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ +} ADC_REFSEL_t; + +/* Event channel input selection */ +typedef enum ADC_EVSEL_enum +{ + ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */ + ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */ + ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */ + ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */ +} ADC_EVSEL_t; + +/* Event action selection */ +typedef enum ADC_EVACT_enum +{ + ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ + ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ + ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ +} ADC_EVACT_t; + +/* Interupt mode */ +typedef enum ADC_CH_INTMODE_enum +{ + ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ + ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ + ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ +} ADC_CH_INTMODE_t; + +/* Interrupt level */ +typedef enum ADC_CH_INTLVL_enum +{ + ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ + ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ + ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ +} ADC_CH_INTLVL_t; + +/* Clock prescaler */ +typedef enum ADC_PRESCALER_enum +{ + ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ + ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ + ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ + ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ + ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ + ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ + ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ + ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ +} ADC_PRESCALER_t; + + +/* +-------------------------------------------------------------------------- +RTC - Real-Time Counter +-------------------------------------------------------------------------- +*/ + +/* Real-Time Counter */ +typedef struct RTC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary register */ + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + _WORDREGISTER(CNT); /* Count Register */ + _WORDREGISTER(PER); /* Period Register */ + _WORDREGISTER(COMP); /* Compare Register */ +} RTC_t; + +/* Prescaler Factor */ +typedef enum RTC_PRESCALER_enum +{ + RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ + RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ + RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ + RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ + RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ + RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ + RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ + RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ +} RTC_PRESCALER_t; + +/* Compare Interrupt level */ +typedef enum RTC_COMPINTLVL_enum +{ + RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ + RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ +} RTC_COMPINTLVL_t; + +/* Overflow Interrupt level */ +typedef enum RTC_OVFINTLVL_enum +{ + RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} RTC_OVFINTLVL_t; + + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* */ +typedef struct TWI_MASTER_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t STATUS; /* Status Register */ + register8_t BAUD; /* Baurd Rate Control Register */ + register8_t ADDR; /* Address Register */ + register8_t DATA; /* Data Register */ +} TWI_MASTER_t; + + +/* */ +typedef struct TWI_SLAVE_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t STATUS; /* Status Register */ + register8_t ADDR; /* Address Register */ + register8_t DATA; /* Data Register */ + register8_t ADDRMASK; /* Address Mask Register */ +} TWI_SLAVE_t; + + +/* Two-Wire Interface */ +typedef struct TWI_struct +{ + register8_t CTRL; /* TWI Common Control Register */ + TWI_MASTER_t MASTER; /* TWI master module */ + TWI_SLAVE_t SLAVE; /* TWI slave module */ +} TWI_t; + +/* Master Interrupt Level */ +typedef enum TWI_MASTER_INTLVL_enum +{ + TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ + TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ +} TWI_MASTER_INTLVL_t; + +/* Inactive Timeout */ +typedef enum TWI_MASTER_TIMEOUT_enum +{ + TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ + TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ + TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ + TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +} TWI_MASTER_TIMEOUT_t; + +/* Master Command */ +typedef enum TWI_MASTER_CMD_enum +{ + TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ + TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ + TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +} TWI_MASTER_CMD_t; + +/* Master Bus State */ +typedef enum TWI_MASTER_BUSSTATE_enum +{ + TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ + TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ + TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ + TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +} TWI_MASTER_BUSSTATE_t; + +/* Slave Interrupt Level */ +typedef enum TWI_SLAVE_INTLVL_enum +{ + TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ + TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ +} TWI_SLAVE_INTLVL_t; + +/* Slave Command */ +typedef enum TWI_SLAVE_CMD_enum +{ + TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ + TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +} TWI_SLAVE_CMD_t; + +/* SDA hold time */ +typedef enum SDA_HOLD_TIME_enum +{ + SDA_HOLD_TIME_OFF_gc = (0x00<<1), /* SDA hold time off */ + SDA_HOLD_TIME_50NS_gc = (0x01<<1), /* Typical 50ns hold time */ + SDA_HOLD_TIME_300NS_gc = (0x02<<1), /* Typical 300ns hold time */ + SDA_HOLD_TIME_400NS_gc = (0x03<<1), /* Typical 400ns hold time */ +} SDA_HOLD_TIME_t; + + +/* +-------------------------------------------------------------------------- +PORT - Port Configuration +-------------------------------------------------------------------------- +*/ + +/* I/O port Configuration */ +typedef struct PORTCFG_struct +{ + register8_t MPCMASK; /* Multi-pin Configuration Mask */ + register8_t reserved_0x01; + register8_t VPCTRLA; /* Virtual Port Control Register A */ + register8_t VPCTRLB; /* Virtual Port Control Register B */ + register8_t CLKEVOUT; /* Clock and Event Out Register */ +} PORTCFG_t; + + +/* Virtual Port */ +typedef struct VPORT_struct +{ + register8_t DIR; /* I/O Port Data Direction */ + register8_t OUT; /* I/O Port Output */ + register8_t IN; /* I/O Port Input */ + register8_t INTFLAGS; /* Interrupt Flag Register */ +} VPORT_t; + + +/* I/O Ports */ +typedef struct PORT_struct +{ + register8_t DIR; /* I/O Port Data Direction */ + register8_t DIRSET; /* I/O Port Data Direction Set */ + register8_t DIRCLR; /* I/O Port Data Direction Clear */ + register8_t DIRTGL; /* I/O Port Data Direction Toggle */ + register8_t OUT; /* I/O Port Output */ + register8_t OUTSET; /* I/O Port Output Set */ + register8_t OUTCLR; /* I/O Port Output Clear */ + register8_t OUTTGL; /* I/O Port Output Toggle */ + register8_t IN; /* I/O port Input */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INT0MASK; /* Port Interrupt 0 Mask */ + register8_t INT1MASK; /* Port Interrupt 1 Mask */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t REMAP; /* Pin Remap Register (available for PORTC to PORTF only) */ + register8_t reserved_0x0F; + register8_t PIN0CTRL; /* Pin 0 Control Register */ + register8_t PIN1CTRL; /* Pin 1 Control Register */ + register8_t PIN2CTRL; /* Pin 2 Control Register */ + register8_t PIN3CTRL; /* Pin 3 Control Register */ + register8_t PIN4CTRL; /* Pin 4 Control Register */ + register8_t PIN5CTRL; /* Pin 5 Control Register */ + register8_t PIN6CTRL; /* Pin 6 Control Register */ + register8_t PIN7CTRL; /* Pin 7 Control Register */ +} PORT_t; + +/* Virtual Port 0 Mapping */ +typedef enum PORTCFG_VP0MAP_enum +{ + PORTCFG_VP0MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ + PORTCFG_VP0MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ + PORTCFG_VP0MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ + PORTCFG_VP0MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ + PORTCFG_VP0MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ + PORTCFG_VP0MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ + PORTCFG_VP0MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ + PORTCFG_VP0MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ + PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ + PORTCFG_VP0MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ + PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ + PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ + PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ + PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ + PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ + PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ +} PORTCFG_VP0MAP_t; + +/* Virtual Port 1 Mapping */ +typedef enum PORTCFG_VP1MAP_enum +{ + PORTCFG_VP1MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ + PORTCFG_VP1MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ + PORTCFG_VP1MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ + PORTCFG_VP1MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ + PORTCFG_VP1MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ + PORTCFG_VP1MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ + PORTCFG_VP1MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ + PORTCFG_VP1MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ + PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ + PORTCFG_VP1MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ + PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ + PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ + PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ + PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ + PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ + PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ +} PORTCFG_VP1MAP_t; + +/* Virtual Port 2 Mapping */ +typedef enum PORTCFG_VP2MAP_enum +{ + PORTCFG_VP2MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ + PORTCFG_VP2MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ + PORTCFG_VP2MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ + PORTCFG_VP2MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ + PORTCFG_VP2MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ + PORTCFG_VP2MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ + PORTCFG_VP2MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ + PORTCFG_VP2MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ + PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ + PORTCFG_VP2MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ + PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ + PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ + PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ + PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ + PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ + PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ +} PORTCFG_VP2MAP_t; + +/* Virtual Port 3 Mapping */ +typedef enum PORTCFG_VP3MAP_enum +{ + PORTCFG_VP3MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ + PORTCFG_VP3MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ + PORTCFG_VP3MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ + PORTCFG_VP3MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ + PORTCFG_VP3MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ + PORTCFG_VP3MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ + PORTCFG_VP3MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ + PORTCFG_VP3MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ + PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ + PORTCFG_VP3MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ + PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ + PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ + PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ + PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ + PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ + PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ +} PORTCFG_VP3MAP_t; + +/* Clock Output Port */ +typedef enum PORTCFG_CLKOUT_enum +{ + PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* Clock Output Disabled */ + PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* Clock Output on Port C pin 7 */ + PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* Clock Output on Port D pin 7 */ + PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* Clock Output on Port E pin 7 */ +} PORTCFG_CLKOUT_t; + +/* Event Output Port */ +typedef enum PORTCFG_EVOUT_enum +{ + PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ + PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ + PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ + PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ +} PORTCFG_EVOUT_t; + +/* Port Interrupt 0 Level */ +typedef enum PORT_INT0LVL_enum +{ + PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ + PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ + PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ +} PORT_INT0LVL_t; + +/* Port Interrupt 1 Level */ +typedef enum PORT_INT1LVL_enum +{ + PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ + PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ + PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ +} PORT_INT1LVL_t; + +/* Output/Pull Configuration */ +typedef enum PORT_OPC_enum +{ + PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ + PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ + PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ + PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ + PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ + PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ + PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ + PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ +} PORT_OPC_t; + +/* Input/Sense Configuration */ +typedef enum PORT_ISC_enum +{ + PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ + PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ + PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ + PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ + PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ +} PORT_ISC_t; + + +/* +-------------------------------------------------------------------------- +TC - 16-bit Timer/Counter With PWM +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter 0 */ +typedef struct TC0_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t CTRLFCLR; /* Control Register F Clear */ + register8_t CTRLFSET; /* Control Register F Set */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G Set */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CCA); /* Compare or Capture A */ + _WORDREGISTER(CCB); /* Compare or Capture B */ + _WORDREGISTER(CCC); /* Compare or Capture C */ + _WORDREGISTER(CCD); /* Compare or Capture D */ + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ + _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ + _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ + _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ +} TC0_t; + + +/* 16-bit Timer/Counter 1 */ +typedef struct TC1_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t CTRLFCLR; /* Control Register F Clear */ + register8_t CTRLFSET; /* Control Register F Set */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G Set */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CCA); /* Compare or Capture A */ + _WORDREGISTER(CCB); /* Compare or Capture B */ + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t reserved_0x2E; + register8_t reserved_0x2F; + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ + _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ +} TC1_t; + + +/* Advanced Waveform Extension */ +typedef struct AWEX_struct +{ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x01; + register8_t FDEMASK; /* Fault Detection Event Mask */ + register8_t FDCTRL; /* Fault Detection Control Register */ + register8_t STATUS; /* Status Register */ + register8_t reserved_0x05; + register8_t DTBOTH; /* Dead Time Both Sides */ + register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ + register8_t DTLS; /* Dead Time Low Side */ + register8_t DTHS; /* Dead Time High Side */ + register8_t DTLSBUF; /* Dead Time Low Side Buffer */ + register8_t DTHSBUF; /* Dead Time High Side Buffer */ + register8_t OUTOVEN; /* Output Override Enable */ +} AWEX_t; + + +/* High-Resolution Extension */ +typedef struct HIRES_struct +{ + register8_t CTRLA; /* Control Register */ +} HIRES_t; + +/* Clock Selection */ +typedef enum TC_CLKSEL_enum +{ + TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ + TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ + TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ + TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ + TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ + TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ + TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ + TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ + TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ + TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ + TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ + TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ + TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ + TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ + TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ +} TC_CLKSEL_t; + +/* Waveform Generation Mode */ +typedef enum TC_WGMODE_enum +{ + TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ + TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ + TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ + TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ + TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on TOP and BOTTOM */ + TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ +} TC_WGMODE_t; + +/* Event Action */ +typedef enum TC_EVACT_enum +{ + TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ + TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ + TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ + TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ + TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ + TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ + TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ +} TC_EVACT_t; + +/* Event Selection */ +typedef enum TC_EVSEL_enum +{ + TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ + TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ + TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ + TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ + TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ + TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ + TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ + TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ +} TC_EVSEL_t; + +/* Error Interrupt Level */ +typedef enum TC_ERRINTLVL_enum +{ + TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC_ERRINTLVL_t; + +/* Overflow Interrupt Level */ +typedef enum TC_OVFINTLVL_enum +{ + TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC_OVFINTLVL_t; + +/* Compare or Capture D Interrupt Level */ +typedef enum TC_CCDINTLVL_enum +{ + TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ + TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ +} TC_CCDINTLVL_t; + +/* Compare or Capture C Interrupt Level */ +typedef enum TC_CCCINTLVL_enum +{ + TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} TC_CCCINTLVL_t; + +/* Compare or Capture B Interrupt Level */ +typedef enum TC_CCBINTLVL_enum +{ + TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC_CCBINTLVL_t; + +/* Compare or Capture A Interrupt Level */ +typedef enum TC_CCAINTLVL_enum +{ + TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC_CCAINTLVL_t; + +/* Timer/Counter Command */ +typedef enum TC_CMD_enum +{ + TC_CMD_NONE_gc = (0x00<<2), /* No Command */ + TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TC_CMD_t; + +/* Fault Detect Action */ +typedef enum AWEX_FDACT_enum +{ + AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ + AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ + AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ +} AWEX_FDACT_t; + +/* High Resolution Enable */ +typedef enum HIRES_HREN_enum +{ + HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ + HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ + HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ + HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ +} HIRES_HREN_t; + + +/* +-------------------------------------------------------------------------- +USART - Universal Asynchronous Receiver-Transmitter +-------------------------------------------------------------------------- +*/ + +/* Universal Synchronous/Asynchronous Receiver/Transmitter */ +typedef struct USART_struct +{ + register8_t DATA; /* Data Register */ + register8_t STATUS; /* Status Register */ + register8_t reserved_0x02; + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t BAUDCTRLA; /* Baud Rate Control Register A */ + register8_t BAUDCTRLB; /* Baud Rate Control Register B */ +} USART_t; + +/* Receive Complete Interrupt level */ +typedef enum USART_RXCINTLVL_enum +{ + USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} USART_RXCINTLVL_t; + +/* Transmit Complete Interrupt level */ +typedef enum USART_TXCINTLVL_enum +{ + USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ + USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ +} USART_TXCINTLVL_t; + +/* Data Register Empty Interrupt level */ +typedef enum USART_DREINTLVL_enum +{ + USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ + USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ +} USART_DREINTLVL_t; + +/* Character Size */ +typedef enum USART_CHSIZE_enum +{ + USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ + USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ + USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ + USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ + USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ +} USART_CHSIZE_t; + +/* Communication Mode */ +typedef enum USART_CMODE_enum +{ + USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ + USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ + USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ + USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +} USART_CMODE_t; + +/* Parity Mode */ +typedef enum USART_PMODE_enum +{ + USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ + USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ + USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +} USART_PMODE_t; + + +/* +-------------------------------------------------------------------------- +SPI - Serial Peripheral Interface +-------------------------------------------------------------------------- +*/ + +/* Serial Peripheral Interface */ +typedef struct SPI_struct +{ + register8_t CTRL; /* Control Register */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t STATUS; /* Status Register */ + register8_t DATA; /* Data Register */ +} SPI_t; + +/* SPI Mode */ +typedef enum SPI_MODE_enum +{ + SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ + SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ + SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ + SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ +} SPI_MODE_t; + +/* Prescaler setting */ +typedef enum SPI_PRESCALER_enum +{ + SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ + SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ + SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ + SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ +} SPI_PRESCALER_t; + +/* Interrupt level */ +typedef enum SPI_INTLVL_enum +{ + SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ + SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ + SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ +} SPI_INTLVL_t; + + +/* +-------------------------------------------------------------------------- +IRCOM - IR Communication Module +-------------------------------------------------------------------------- +*/ + +/* IR Communication Module */ +typedef struct IRCOM_struct +{ + register8_t CTRL; /* Control Register */ + register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ + register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ +} IRCOM_t; + +/* Event channel selection */ +typedef enum IRDA_EVSEL_enum +{ + IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ + IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ + IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ + IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ + IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ + IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ + IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ + IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ + IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ +} IRDA_EVSEL_t; + +/* +========================================================================== +IO Module Instances. Mapped to memory. +========================================================================== +*/ + +#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ +#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ +#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ +#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ +#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ +#define CLK (*(CLK_t *) 0x0040) /* Clock System */ +#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ +#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ +#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ +#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ +#define PR (*(PR_t *) 0x0070) /* Power Reduction */ +#define RST (*(RST_t *) 0x0078) /* Reset */ +#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ +#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ +#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ +#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ +#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ +#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ +#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ +#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ +#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ +#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ +#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */ +#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ +#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ +#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ +#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ +#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ +#define PORTF (*(PORT_t *) 0x06A0) /* I/O Ports */ +#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ +#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ +#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ +#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ +#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ +#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ +#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ +#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */ +#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */ +#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ +#define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension */ +#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define SPIE (*(SPI_t *) 0x0AC0) /* Serial Peripheral Interface */ +#define TCF0 (*(TC0_t *) 0x0B00) /* 16-bit Timer/Counter 0 */ + + +#endif /* !defined (__ASSEMBLER__) */ + + +/* ========== Flattened fully qualified IO register names ========== */ + +/* GPIO - General Purpose IO Registers */ +#define GPIO_GPIOR0 _SFR_MEM8(0x0000) +#define GPIO_GPIOR1 _SFR_MEM8(0x0001) +#define GPIO_GPIOR2 _SFR_MEM8(0x0002) +#define GPIO_GPIOR3 _SFR_MEM8(0x0003) + +/* Deprecated */ +#define GPIO_GPIO0 _SFR_MEM8(0x0000) +#define GPIO_GPIO1 _SFR_MEM8(0x0001) +#define GPIO_GPIO2 _SFR_MEM8(0x0002) +#define GPIO_GPIO3 _SFR_MEM8(0x0003) + +/* NVM_FUSES - Fuses */ +#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) +#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) +#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) +#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) + +/* NVM_LOCKBITS - Lock Bits */ +#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) + +/* NVM_PROD_SIGNATURES - Production Signatures */ +#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) +#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) +#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) +#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) +#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) +#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) +#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) +#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) +#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) +#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) +#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) +#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) +#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) +#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) +#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) +#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) +#define PRODSIGNATURES_ADCBCAL0 _SFR_MEM8(0x0024) +#define PRODSIGNATURES_ADCBCAL1 _SFR_MEM8(0x0025) +#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) +#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) + +/* VPORT - Virtual Port */ +#define VPORT0_DIR _SFR_MEM8(0x0010) +#define VPORT0_OUT _SFR_MEM8(0x0011) +#define VPORT0_IN _SFR_MEM8(0x0012) +#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) + +/* VPORT - Virtual Port */ +#define VPORT1_DIR _SFR_MEM8(0x0014) +#define VPORT1_OUT _SFR_MEM8(0x0015) +#define VPORT1_IN _SFR_MEM8(0x0016) +#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) + +/* VPORT - Virtual Port */ +#define VPORT2_DIR _SFR_MEM8(0x0018) +#define VPORT2_OUT _SFR_MEM8(0x0019) +#define VPORT2_IN _SFR_MEM8(0x001A) +#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) + +/* VPORT - Virtual Port */ +#define VPORT3_DIR _SFR_MEM8(0x001C) +#define VPORT3_OUT _SFR_MEM8(0x001D) +#define VPORT3_IN _SFR_MEM8(0x001E) +#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) + +/* OCD - On-Chip Debug System */ +#define OCD_OCDR0 _SFR_MEM8(0x002E) +#define OCD_OCDR1 _SFR_MEM8(0x002F) + +/* CPU - CPU registers */ +#define CPU_CCP _SFR_MEM8(0x0034) +#define CPU_RAMPD _SFR_MEM8(0x0038) +#define CPU_RAMPX _SFR_MEM8(0x0039) +#define CPU_RAMPY _SFR_MEM8(0x003A) +#define CPU_RAMPZ _SFR_MEM8(0x003B) +#define CPU_EIND _SFR_MEM8(0x003C) +#define CPU_SPL _SFR_MEM8(0x003D) +#define CPU_SPH _SFR_MEM8(0x003E) +#define CPU_SREG _SFR_MEM8(0x003F) + +/* CLK - Clock System */ +#define CLK_CTRL _SFR_MEM8(0x0040) +#define CLK_PSCTRL _SFR_MEM8(0x0041) +#define CLK_LOCK _SFR_MEM8(0x0042) +#define CLK_RTCCTRL _SFR_MEM8(0x0043) + +/* SLEEP - Sleep Controller */ +#define SLEEP_CTRL _SFR_MEM8(0x0048) + +/* OSC - Oscillator */ +#define OSC_CTRL _SFR_MEM8(0x0050) +#define OSC_STATUS _SFR_MEM8(0x0051) +#define OSC_XOSCCTRL _SFR_MEM8(0x0052) +#define OSC_XOSCFAIL _SFR_MEM8(0x0053) +#define OSC_RC32KCAL _SFR_MEM8(0x0054) +#define OSC_PLLCTRL _SFR_MEM8(0x0055) +#define OSC_DFLLCTRL _SFR_MEM8(0x0056) + +/* DFLL - DFLL */ +#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) +#define DFLLRC32M_CALA _SFR_MEM8(0x0062) +#define DFLLRC32M_CALB _SFR_MEM8(0x0063) +#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) +#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) +#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) + +/* DFLL - DFLL */ +#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) +#define DFLLRC2M_CALA _SFR_MEM8(0x006A) +#define DFLLRC2M_CALB _SFR_MEM8(0x006B) +#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) +#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) +#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) + +/* PR - Power Reduction */ +#define PR_PRGEN _SFR_MEM8(0x0070) +#define PR_PRPA _SFR_MEM8(0x0071) +#define PR_PRPC _SFR_MEM8(0x0073) +#define PR_PRPD _SFR_MEM8(0x0074) +#define PR_PRPE _SFR_MEM8(0x0075) +#define PR_PRPF _SFR_MEM8(0x0076) + +/* RST - Reset */ +#define RST_STATUS _SFR_MEM8(0x0078) +#define RST_CTRL _SFR_MEM8(0x0079) + +/* WDT - Watch-Dog Timer */ +#define WDT_CTRL _SFR_MEM8(0x0080) +#define WDT_WINCTRL _SFR_MEM8(0x0081) +#define WDT_STATUS _SFR_MEM8(0x0082) + +/* MCU - MCU Control */ +#define MCU_DEVID0 _SFR_MEM8(0x0090) +#define MCU_DEVID1 _SFR_MEM8(0x0091) +#define MCU_DEVID2 _SFR_MEM8(0x0092) +#define MCU_REVID _SFR_MEM8(0x0093) +#define MCU_JTAGUID _SFR_MEM8(0x0094) +#define MCU_MCUCR _SFR_MEM8(0x0096) +#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) +#define MCU_AWEXLOCK _SFR_MEM8(0x0099) + +/* PMIC - Programmable Multi-level Interrupt Controller */ +#define PMIC_STATUS _SFR_MEM8(0x00A0) +#define PMIC_INTPRI _SFR_MEM8(0x00A1) +#define PMIC_CTRL _SFR_MEM8(0x00A2) + +/* PORTCFG - I/O port Configuration */ +#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) +#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) +#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) +#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) + +/* CRC - Cyclic Redundancy Checker */ +#define CRC_CTRL _SFR_MEM8(0x00D0) +#define CRC_STATUS _SFR_MEM8(0x00D1) +#define CRC_DATAIN _SFR_MEM8(0x00D3) +#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) +#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) +#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) +#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) + +/* EVSYS - Event System */ +#define EVSYS_CH0MUX _SFR_MEM8(0x0180) +#define EVSYS_CH1MUX _SFR_MEM8(0x0181) +#define EVSYS_CH2MUX _SFR_MEM8(0x0182) +#define EVSYS_CH3MUX _SFR_MEM8(0x0183) +#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) +#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) +#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) +#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) +#define EVSYS_STROBE _SFR_MEM8(0x0190) +#define EVSYS_DATA _SFR_MEM8(0x0191) + +/* NVM - Non-volatile Memory Controller */ +#define NVM_ADDR0 _SFR_MEM8(0x01C0) +#define NVM_ADDR1 _SFR_MEM8(0x01C1) +#define NVM_ADDR2 _SFR_MEM8(0x01C2) +#define NVM_DATA0 _SFR_MEM8(0x01C4) +#define NVM_DATA1 _SFR_MEM8(0x01C5) +#define NVM_DATA2 _SFR_MEM8(0x01C6) +#define NVM_CMD _SFR_MEM8(0x01CA) +#define NVM_CTRLA _SFR_MEM8(0x01CB) +#define NVM_CTRLB _SFR_MEM8(0x01CC) +#define NVM_INTCTRL _SFR_MEM8(0x01CD) +#define NVM_STATUS _SFR_MEM8(0x01CF) +#define NVM_LOCKBITS _SFR_MEM8(0x01D0) + +/* ADC - Analog-to-Digital Converter */ +#define ADCA_CTRLA _SFR_MEM8(0x0200) +#define ADCA_CTRLB _SFR_MEM8(0x0201) +#define ADCA_REFCTRL _SFR_MEM8(0x0202) +#define ADCA_EVCTRL _SFR_MEM8(0x0203) +#define ADCA_PRESCALER _SFR_MEM8(0x0204) +#define ADCA_INTFLAGS _SFR_MEM8(0x0206) +#define ADCA_TEMP _SFR_MEM8(0x0207) +#define ADCA_CAL _SFR_MEM16(0x020C) +#define ADCA_CH0RES _SFR_MEM16(0x0210) +#define ADCA_CMP _SFR_MEM16(0x0218) +#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) +#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) +#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) +#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) +#define ADCA_CH0_RES _SFR_MEM16(0x0224) +#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) + +/* AC - Analog Comparator */ +#define ACA_AC0CTRL _SFR_MEM8(0x0380) +#define ACA_AC1CTRL _SFR_MEM8(0x0381) +#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) +#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) +#define ACA_CTRLA _SFR_MEM8(0x0384) +#define ACA_CTRLB _SFR_MEM8(0x0385) +#define ACA_WINCTRL _SFR_MEM8(0x0386) +#define ACA_STATUS _SFR_MEM8(0x0387) + +/* RTC - Real-Time Counter */ +#define RTC_CTRL _SFR_MEM8(0x0400) +#define RTC_STATUS _SFR_MEM8(0x0401) +#define RTC_INTCTRL _SFR_MEM8(0x0402) +#define RTC_INTFLAGS _SFR_MEM8(0x0403) +#define RTC_TEMP _SFR_MEM8(0x0404) +#define RTC_CNT _SFR_MEM16(0x0408) +#define RTC_PER _SFR_MEM16(0x040A) +#define RTC_COMP _SFR_MEM16(0x040C) + +/* TWI - Two-Wire Interface */ +#define TWIC_CTRL _SFR_MEM8(0x0480) +#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) +#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) +#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) +#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) +#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) +#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) +#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) +#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) +#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) +#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) +#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) +#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) +#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) + +/* TWI - Two-Wire Interface */ +#define TWIE_CTRL _SFR_MEM8(0x04A0) +#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) +#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) +#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) +#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) +#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) +#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) +#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) +#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) +#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) +#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) +#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) +#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) +#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) + +/* PORT - I/O Ports */ +#define PORTA_DIR _SFR_MEM8(0x0600) +#define PORTA_DIRSET _SFR_MEM8(0x0601) +#define PORTA_DIRCLR _SFR_MEM8(0x0602) +#define PORTA_DIRTGL _SFR_MEM8(0x0603) +#define PORTA_OUT _SFR_MEM8(0x0604) +#define PORTA_OUTSET _SFR_MEM8(0x0605) +#define PORTA_OUTCLR _SFR_MEM8(0x0606) +#define PORTA_OUTTGL _SFR_MEM8(0x0607) +#define PORTA_IN _SFR_MEM8(0x0608) +#define PORTA_INTCTRL _SFR_MEM8(0x0609) +#define PORTA_INT0MASK _SFR_MEM8(0x060A) +#define PORTA_INT1MASK _SFR_MEM8(0x060B) +#define PORTA_INTFLAGS _SFR_MEM8(0x060C) +#define PORTA_REMAP _SFR_MEM8(0x060E) +#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) +#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) +#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) +#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) +#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) +#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) +#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) +#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) + +/* PORT - I/O Ports */ +#define PORTB_DIR _SFR_MEM8(0x0620) +#define PORTB_DIRSET _SFR_MEM8(0x0621) +#define PORTB_DIRCLR _SFR_MEM8(0x0622) +#define PORTB_DIRTGL _SFR_MEM8(0x0623) +#define PORTB_OUT _SFR_MEM8(0x0624) +#define PORTB_OUTSET _SFR_MEM8(0x0625) +#define PORTB_OUTCLR _SFR_MEM8(0x0626) +#define PORTB_OUTTGL _SFR_MEM8(0x0627) +#define PORTB_IN _SFR_MEM8(0x0628) +#define PORTB_INTCTRL _SFR_MEM8(0x0629) +#define PORTB_INT0MASK _SFR_MEM8(0x062A) +#define PORTB_INT1MASK _SFR_MEM8(0x062B) +#define PORTB_INTFLAGS _SFR_MEM8(0x062C) +#define PORTB_REMAP _SFR_MEM8(0x062E) +#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) +#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) +#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) +#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) +#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) +#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) +#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) +#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) + +/* PORT - I/O Ports */ +#define PORTC_DIR _SFR_MEM8(0x0640) +#define PORTC_DIRSET _SFR_MEM8(0x0641) +#define PORTC_DIRCLR _SFR_MEM8(0x0642) +#define PORTC_DIRTGL _SFR_MEM8(0x0643) +#define PORTC_OUT _SFR_MEM8(0x0644) +#define PORTC_OUTSET _SFR_MEM8(0x0645) +#define PORTC_OUTCLR _SFR_MEM8(0x0646) +#define PORTC_OUTTGL _SFR_MEM8(0x0647) +#define PORTC_IN _SFR_MEM8(0x0648) +#define PORTC_INTCTRL _SFR_MEM8(0x0649) +#define PORTC_INT0MASK _SFR_MEM8(0x064A) +#define PORTC_INT1MASK _SFR_MEM8(0x064B) +#define PORTC_INTFLAGS _SFR_MEM8(0x064C) +#define PORTC_REMAP _SFR_MEM8(0x064E) +#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) +#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) +#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) +#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) +#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) +#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) +#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) +#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) + +/* PORT - I/O Ports */ +#define PORTD_DIR _SFR_MEM8(0x0660) +#define PORTD_DIRSET _SFR_MEM8(0x0661) +#define PORTD_DIRCLR _SFR_MEM8(0x0662) +#define PORTD_DIRTGL _SFR_MEM8(0x0663) +#define PORTD_OUT _SFR_MEM8(0x0664) +#define PORTD_OUTSET _SFR_MEM8(0x0665) +#define PORTD_OUTCLR _SFR_MEM8(0x0666) +#define PORTD_OUTTGL _SFR_MEM8(0x0667) +#define PORTD_IN _SFR_MEM8(0x0668) +#define PORTD_INTCTRL _SFR_MEM8(0x0669) +#define PORTD_INT0MASK _SFR_MEM8(0x066A) +#define PORTD_INT1MASK _SFR_MEM8(0x066B) +#define PORTD_INTFLAGS _SFR_MEM8(0x066C) +#define PORTD_REMAP _SFR_MEM8(0x066E) +#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) +#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) +#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) +#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) +#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) +#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) +#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) +#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) + +/* PORT - I/O Ports */ +#define PORTE_DIR _SFR_MEM8(0x0680) +#define PORTE_DIRSET _SFR_MEM8(0x0681) +#define PORTE_DIRCLR _SFR_MEM8(0x0682) +#define PORTE_DIRTGL _SFR_MEM8(0x0683) +#define PORTE_OUT _SFR_MEM8(0x0684) +#define PORTE_OUTSET _SFR_MEM8(0x0685) +#define PORTE_OUTCLR _SFR_MEM8(0x0686) +#define PORTE_OUTTGL _SFR_MEM8(0x0687) +#define PORTE_IN _SFR_MEM8(0x0688) +#define PORTE_INTCTRL _SFR_MEM8(0x0689) +#define PORTE_INT0MASK _SFR_MEM8(0x068A) +#define PORTE_INT1MASK _SFR_MEM8(0x068B) +#define PORTE_INTFLAGS _SFR_MEM8(0x068C) +#define PORTE_REMAP _SFR_MEM8(0x068E) +#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) +#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) +#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) +#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) +#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) +#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) +#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) +#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) + +/* PORT - I/O Ports */ +#define PORTF_DIR _SFR_MEM8(0x06A0) +#define PORTF_DIRSET _SFR_MEM8(0x06A1) +#define PORTF_DIRCLR _SFR_MEM8(0x06A2) +#define PORTF_DIRTGL _SFR_MEM8(0x06A3) +#define PORTF_OUT _SFR_MEM8(0x06A4) +#define PORTF_OUTSET _SFR_MEM8(0x06A5) +#define PORTF_OUTCLR _SFR_MEM8(0x06A6) +#define PORTF_OUTTGL _SFR_MEM8(0x06A7) +#define PORTF_IN _SFR_MEM8(0x06A8) +#define PORTF_INTCTRL _SFR_MEM8(0x06A9) +#define PORTF_INT0MASK _SFR_MEM8(0x06AA) +#define PORTF_INT1MASK _SFR_MEM8(0x06AB) +#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) +#define PORTF_REMAP _SFR_MEM8(0x06AE) +#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) +#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) +#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) +#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) +#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) +#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) +#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) +#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) + +/* PORT - I/O Ports */ +#define PORTR_DIR _SFR_MEM8(0x07E0) +#define PORTR_DIRSET _SFR_MEM8(0x07E1) +#define PORTR_DIRCLR _SFR_MEM8(0x07E2) +#define PORTR_DIRTGL _SFR_MEM8(0x07E3) +#define PORTR_OUT _SFR_MEM8(0x07E4) +#define PORTR_OUTSET _SFR_MEM8(0x07E5) +#define PORTR_OUTCLR _SFR_MEM8(0x07E6) +#define PORTR_OUTTGL _SFR_MEM8(0x07E7) +#define PORTR_IN _SFR_MEM8(0x07E8) +#define PORTR_INTCTRL _SFR_MEM8(0x07E9) +#define PORTR_INT0MASK _SFR_MEM8(0x07EA) +#define PORTR_INT1MASK _SFR_MEM8(0x07EB) +#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) +#define PORTR_REMAP _SFR_MEM8(0x07EE) +#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) +#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) +#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) +#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) +#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) +#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) +#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) +#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) + +/* TC0 - 16-bit Timer/Counter 0 */ +#define TCC0_CTRLA _SFR_MEM8(0x0800) +#define TCC0_CTRLB _SFR_MEM8(0x0801) +#define TCC0_CTRLC _SFR_MEM8(0x0802) +#define TCC0_CTRLD _SFR_MEM8(0x0803) +#define TCC0_CTRLE _SFR_MEM8(0x0804) +#define TCC0_INTCTRLA _SFR_MEM8(0x0806) +#define TCC0_INTCTRLB _SFR_MEM8(0x0807) +#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) +#define TCC0_CTRLFSET _SFR_MEM8(0x0809) +#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) +#define TCC0_CTRLGSET _SFR_MEM8(0x080B) +#define TCC0_INTFLAGS _SFR_MEM8(0x080C) +#define TCC0_TEMP _SFR_MEM8(0x080F) +#define TCC0_CNT _SFR_MEM16(0x0820) +#define TCC0_PER _SFR_MEM16(0x0826) +#define TCC0_CCA _SFR_MEM16(0x0828) +#define TCC0_CCB _SFR_MEM16(0x082A) +#define TCC0_CCC _SFR_MEM16(0x082C) +#define TCC0_CCD _SFR_MEM16(0x082E) +#define TCC0_PERBUF _SFR_MEM16(0x0836) +#define TCC0_CCABUF _SFR_MEM16(0x0838) +#define TCC0_CCBBUF _SFR_MEM16(0x083A) +#define TCC0_CCCBUF _SFR_MEM16(0x083C) +#define TCC0_CCDBUF _SFR_MEM16(0x083E) + +/* TC1 - 16-bit Timer/Counter 1 */ +#define TCC1_CTRLA _SFR_MEM8(0x0840) +#define TCC1_CTRLB _SFR_MEM8(0x0841) +#define TCC1_CTRLC _SFR_MEM8(0x0842) +#define TCC1_CTRLD _SFR_MEM8(0x0843) +#define TCC1_CTRLE _SFR_MEM8(0x0844) +#define TCC1_INTCTRLA _SFR_MEM8(0x0846) +#define TCC1_INTCTRLB _SFR_MEM8(0x0847) +#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) +#define TCC1_CTRLFSET _SFR_MEM8(0x0849) +#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) +#define TCC1_CTRLGSET _SFR_MEM8(0x084B) +#define TCC1_INTFLAGS _SFR_MEM8(0x084C) +#define TCC1_TEMP _SFR_MEM8(0x084F) +#define TCC1_CNT _SFR_MEM16(0x0860) +#define TCC1_PER _SFR_MEM16(0x0866) +#define TCC1_CCA _SFR_MEM16(0x0868) +#define TCC1_CCB _SFR_MEM16(0x086A) +#define TCC1_PERBUF _SFR_MEM16(0x0876) +#define TCC1_CCABUF _SFR_MEM16(0x0878) +#define TCC1_CCBBUF _SFR_MEM16(0x087A) + +/* AWEX - Advanced Waveform Extension */ +#define AWEXC_CTRL _SFR_MEM8(0x0880) +#define AWEXC_FDEMASK _SFR_MEM8(0x0882) +#define AWEXC_FDCTRL _SFR_MEM8(0x0883) +#define AWEXC_STATUS _SFR_MEM8(0x0884) +#define AWEXC_DTBOTH _SFR_MEM8(0x0886) +#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) +#define AWEXC_DTLS _SFR_MEM8(0x0888) +#define AWEXC_DTHS _SFR_MEM8(0x0889) +#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) +#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) +#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) + +/* HIRES - High-Resolution Extension */ +#define HIRESC_CTRLA _SFR_MEM8(0x0890) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTC0_DATA _SFR_MEM8(0x08A0) +#define USARTC0_STATUS _SFR_MEM8(0x08A1) +#define USARTC0_CTRLA _SFR_MEM8(0x08A3) +#define USARTC0_CTRLB _SFR_MEM8(0x08A4) +#define USARTC0_CTRLC _SFR_MEM8(0x08A5) +#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) +#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) + +/* SPI - Serial Peripheral Interface */ +#define SPIC_CTRL _SFR_MEM8(0x08C0) +#define SPIC_INTCTRL _SFR_MEM8(0x08C1) +#define SPIC_STATUS _SFR_MEM8(0x08C2) +#define SPIC_DATA _SFR_MEM8(0x08C3) + +/* IRCOM - IR Communication Module */ +#define IRCOM_CTRL _SFR_MEM8(0x08F8) +#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) +#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) + +/* TC0 - 16-bit Timer/Counter 0 */ +#define TCD0_CTRLA _SFR_MEM8(0x0900) +#define TCD0_CTRLB _SFR_MEM8(0x0901) +#define TCD0_CTRLC _SFR_MEM8(0x0902) +#define TCD0_CTRLD _SFR_MEM8(0x0903) +#define TCD0_CTRLE _SFR_MEM8(0x0904) +#define TCD0_INTCTRLA _SFR_MEM8(0x0906) +#define TCD0_INTCTRLB _SFR_MEM8(0x0907) +#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) +#define TCD0_CTRLFSET _SFR_MEM8(0x0909) +#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) +#define TCD0_CTRLGSET _SFR_MEM8(0x090B) +#define TCD0_INTFLAGS _SFR_MEM8(0x090C) +#define TCD0_TEMP _SFR_MEM8(0x090F) +#define TCD0_CNT _SFR_MEM16(0x0920) +#define TCD0_PER _SFR_MEM16(0x0926) +#define TCD0_CCA _SFR_MEM16(0x0928) +#define TCD0_CCB _SFR_MEM16(0x092A) +#define TCD0_CCC _SFR_MEM16(0x092C) +#define TCD0_CCD _SFR_MEM16(0x092E) +#define TCD0_PERBUF _SFR_MEM16(0x0936) +#define TCD0_CCABUF _SFR_MEM16(0x0938) +#define TCD0_CCBBUF _SFR_MEM16(0x093A) +#define TCD0_CCCBUF _SFR_MEM16(0x093C) +#define TCD0_CCDBUF _SFR_MEM16(0x093E) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTD0_DATA _SFR_MEM8(0x09A0) +#define USARTD0_STATUS _SFR_MEM8(0x09A1) +#define USARTD0_CTRLA _SFR_MEM8(0x09A3) +#define USARTD0_CTRLB _SFR_MEM8(0x09A4) +#define USARTD0_CTRLC _SFR_MEM8(0x09A5) +#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) +#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) + +/* SPI - Serial Peripheral Interface */ +#define SPID_CTRL _SFR_MEM8(0x09C0) +#define SPID_INTCTRL _SFR_MEM8(0x09C1) +#define SPID_STATUS _SFR_MEM8(0x09C2) +#define SPID_DATA _SFR_MEM8(0x09C3) + +/* TC0 - 16-bit Timer/Counter 0 */ +#define TCE0_CTRLA _SFR_MEM8(0x0A00) +#define TCE0_CTRLB _SFR_MEM8(0x0A01) +#define TCE0_CTRLC _SFR_MEM8(0x0A02) +#define TCE0_CTRLD _SFR_MEM8(0x0A03) +#define TCE0_CTRLE _SFR_MEM8(0x0A04) +#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) +#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) +#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) +#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) +#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) +#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) +#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) +#define TCE0_TEMP _SFR_MEM8(0x0A0F) +#define TCE0_CNT _SFR_MEM16(0x0A20) +#define TCE0_PER _SFR_MEM16(0x0A26) +#define TCE0_CCA _SFR_MEM16(0x0A28) +#define TCE0_CCB _SFR_MEM16(0x0A2A) +#define TCE0_CCC _SFR_MEM16(0x0A2C) +#define TCE0_CCD _SFR_MEM16(0x0A2E) +#define TCE0_PERBUF _SFR_MEM16(0x0A36) +#define TCE0_CCABUF _SFR_MEM16(0x0A38) +#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) +#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) +#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) + +/* AWEX - Advanced Waveform Extension */ +#define AWEXE_CTRL _SFR_MEM8(0x0A80) +#define AWEXE_FDEMASK _SFR_MEM8(0x0A82) +#define AWEXE_FDCTRL _SFR_MEM8(0x0A83) +#define AWEXE_STATUS _SFR_MEM8(0x0A84) +#define AWEXE_DTBOTH _SFR_MEM8(0x0A86) +#define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87) +#define AWEXE_DTLS _SFR_MEM8(0x0A88) +#define AWEXE_DTHS _SFR_MEM8(0x0A89) +#define AWEXE_DTLSBUF _SFR_MEM8(0x0A8A) +#define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B) +#define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTE0_DATA _SFR_MEM8(0x0AA0) +#define USARTE0_STATUS _SFR_MEM8(0x0AA1) +#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) +#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) +#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) +#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) +#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) + +/* SPI - Serial Peripheral Interface */ +#define SPIE_CTRL _SFR_MEM8(0x0AC0) +#define SPIE_INTCTRL _SFR_MEM8(0x0AC1) +#define SPIE_STATUS _SFR_MEM8(0x0AC2) +#define SPIE_DATA _SFR_MEM8(0x0AC3) + +/* TC0 - 16-bit Timer/Counter 0 */ +#define TCF0_CTRLA _SFR_MEM8(0x0B00) +#define TCF0_CTRLB _SFR_MEM8(0x0B01) +#define TCF0_CTRLC _SFR_MEM8(0x0B02) +#define TCF0_CTRLD _SFR_MEM8(0x0B03) +#define TCF0_CTRLE _SFR_MEM8(0x0B04) +#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) +#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) +#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) +#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) +#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) +#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) +#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) +#define TCF0_TEMP _SFR_MEM8(0x0B0F) +#define TCF0_CNT _SFR_MEM16(0x0B20) +#define TCF0_PER _SFR_MEM16(0x0B26) +#define TCF0_CCA _SFR_MEM16(0x0B28) +#define TCF0_CCB _SFR_MEM16(0x0B2A) +#define TCF0_CCC _SFR_MEM16(0x0B2C) +#define TCF0_CCD _SFR_MEM16(0x0B2E) +#define TCF0_PERBUF _SFR_MEM16(0x0B36) +#define TCF0_CCABUF _SFR_MEM16(0x0B38) +#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) +#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) +#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) + + + +/*================== Bitfield Definitions ================== */ + +/* XOCD - On-Chip Debug System */ +/* OCD.OCDR0 bit masks and bit positions */ +#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ +#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ +#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ +#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ +#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ +#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ +#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ +#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ +#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ +#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ +#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ +#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ +#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ +#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ +#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ +#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ +#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ +#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ + +/* OCD.OCDR1 bit masks and bit positions */ +/* OCD_OCDRD Predefined. */ +/* OCD_OCDRD Predefined. */ + +/* CPU - CPU */ +/* CPU.CCP bit masks and bit positions */ +#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +#define CPU_CCP_gp 0 /* CCP signature group position. */ +#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ + +/* CPU.SREG bit masks and bit positions */ +#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ + +#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +#define CPU_T_bp 6 /* Transfer Bit bit position. */ + +#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +#define CPU_H_bp 5 /* Half Carry Flag bit position. */ + +#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ + +#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ + +#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +#define CPU_N_bp 2 /* Negative Flag bit position. */ + +#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +#define CPU_Z_bp 1 /* Zero Flag bit position. */ + +#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +#define CPU_C_bp 0 /* Carry Flag bit position. */ + +/* CLK - Clock System */ +/* CLK.CTRL bit masks and bit positions */ +#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ +#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ +#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ +#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ +#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ +#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ +#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ +#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ + +/* CLK.PSCTRL bit masks and bit positions */ +#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ +#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ +#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ +#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ +#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ +#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ +#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ +#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ +#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ +#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ +#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ +#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ + +#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ +#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ +#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ +#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ +#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ +#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ + +/* CLK.LOCK bit masks and bit positions */ +#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ +#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ + +/* CLK.RTCCTRL bit masks and bit positions */ +#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ +#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ +#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ +#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ +#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ +#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ +#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ +#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ + +#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ +#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ + +/* PR.PRGEN bit masks and bit positions */ +#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ +#define PR_RTC_bp 2 /* Real-time Counter bit position. */ + +#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ +#define PR_EVSYS_bp 1 /* Event System bit position. */ + +/* PR.PRPA bit masks and bit positions */ +#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ +#define PR_ADC_bp 1 /* Port A ADC bit position. */ + +#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ +#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ + +/* PR.PRPC bit masks and bit positions */ +#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ +#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ + +#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ +#define PR_USART0_bp 4 /* Port C USART0 bit position. */ + +#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ +#define PR_SPI_bp 3 /* Port C SPI bit position. */ + +#define PR_HIRES_bm 0x04 /* Port C HIRES bit mask. */ +#define PR_HIRES_bp 2 /* Port C HIRES bit position. */ + +#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ +#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ + +#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ +#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ + +/* PR.PRPD bit masks and bit positions */ +/* PR_USART0 Predefined. */ +/* PR_USART0 Predefined. */ + +/* PR_SPI Predefined. */ +/* PR_SPI Predefined. */ + +/* PR_TC0 Predefined. */ +/* PR_TC0 Predefined. */ + +/* PR.PRPE bit masks and bit positions */ +/* PR_TWI Predefined. */ +/* PR_TWI Predefined. */ + +/* PR_USART0 Predefined. */ +/* PR_USART0 Predefined. */ + +/* PR_TC0 Predefined. */ +/* PR_TC0 Predefined. */ + +/* PR.PRPF bit masks and bit positions */ +/* PR_USART0 Predefined. */ +/* PR_USART0 Predefined. */ + +/* PR_TC0 Predefined. */ +/* PR_TC0 Predefined. */ + +/* SLEEP - Sleep Controller */ +/* SLEEP.CTRL bit masks and bit positions */ +#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ +#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ +#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ +#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ +#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ +#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ +#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ +#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ + +#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ +#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ + +/* OSC - Oscillator */ +/* OSC.CTRL bit masks and bit positions */ +#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ +#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ + +#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ +#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ + +#define OSC_RC32KEN_bm 0x04 /* Internal 32kHz RC Oscillator Enable bit mask. */ +#define OSC_RC32KEN_bp 2 /* Internal 32kHz RC Oscillator Enable bit position. */ + +#define OSC_RC32MEN_bm 0x02 /* Internal 32MHz RC Oscillator Enable bit mask. */ +#define OSC_RC32MEN_bp 1 /* Internal 32MHz RC Oscillator Enable bit position. */ + +#define OSC_RC2MEN_bm 0x01 /* Internal 2MHz RC Oscillator Enable bit mask. */ +#define OSC_RC2MEN_bp 0 /* Internal 2MHz RC Oscillator Enable bit position. */ + +/* OSC.STATUS bit masks and bit positions */ +#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ +#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ + +#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ +#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ + +#define OSC_RC32KRDY_bm 0x04 /* Internal 32kHz RC Oscillator Ready bit mask. */ +#define OSC_RC32KRDY_bp 2 /* Internal 32kHz RC Oscillator Ready bit position. */ + +#define OSC_RC32MRDY_bm 0x02 /* Internal 32MHz RC Oscillator Ready bit mask. */ +#define OSC_RC32MRDY_bp 1 /* Internal 32MHz RC Oscillator Ready bit position. */ + +#define OSC_RC2MRDY_bm 0x01 /* Internal 2MHz RC Oscillator Ready bit mask. */ +#define OSC_RC2MRDY_bp 0 /* Internal 2MHz RC Oscillator Ready bit position. */ + +/* OSC.XOSCCTRL bit masks and bit positions */ +#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ +#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ +#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ +#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ +#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ +#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ + +#define OSC_X32KLPM_bm 0x20 /* 32kHz XTAL OSC Low-power Mode bit mask. */ +#define OSC_X32KLPM_bp 5 /* 32kHz XTAL OSC Low-power Mode bit position. */ + +#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ +#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ +#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ +#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ +#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ +#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ +#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ +#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ +#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ +#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ + +/* OSC.XOSCFAIL bit masks and bit positions */ +#define OSC_XOSCFDIF_bm 0x02 /* Failure Detection Interrupt Flag bit mask. */ +#define OSC_XOSCFDIF_bp 1 /* Failure Detection Interrupt Flag bit position. */ + +#define OSC_XOSCFDEN_bm 0x01 /* Failure Detection Enable bit mask. */ +#define OSC_XOSCFDEN_bp 0 /* Failure Detection Enable bit position. */ + +/* OSC.PLLCTRL bit masks and bit positions */ +#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ +#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ +#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ +#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ +#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ +#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ + +#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ +#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ +#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ +#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ +#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ +#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ +#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ +#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ +#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ +#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ +#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ +#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ + +/* OSC.DFLLCTRL bit masks and bit positions */ +#define OSC_RC32MCREF_bm 0x02 /* 32MHz Calibration Reference bit mask. */ +#define OSC_RC32MCREF_bp 1 /* 32MHz Calibration Reference bit position. */ + +#define OSC_RC2MCREF_bm 0x01 /* 2MHz Calibration Reference bit mask. */ +#define OSC_RC2MCREF_bp 0 /* 2MHz Calibration Reference bit position. */ + +/* DFLL - DFLL */ +/* DFLL.CTRL bit masks and bit positions */ +#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ +#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ + +/* DFLL.CALA bit masks and bit positions */ +#define DFLL_CALL_gm 0x7F /* DFLL Calibration bits [6:0] group mask. */ +#define DFLL_CALL_gp 0 /* DFLL Calibration bits [6:0] group position. */ +#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration bits [6:0] bit 0 mask. */ +#define DFLL_CALL0_bp 0 /* DFLL Calibration bits [6:0] bit 0 position. */ +#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration bits [6:0] bit 1 mask. */ +#define DFLL_CALL1_bp 1 /* DFLL Calibration bits [6:0] bit 1 position. */ +#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration bits [6:0] bit 2 mask. */ +#define DFLL_CALL2_bp 2 /* DFLL Calibration bits [6:0] bit 2 position. */ +#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration bits [6:0] bit 3 mask. */ +#define DFLL_CALL3_bp 3 /* DFLL Calibration bits [6:0] bit 3 position. */ +#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration bits [6:0] bit 4 mask. */ +#define DFLL_CALL4_bp 4 /* DFLL Calibration bits [6:0] bit 4 position. */ +#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration bits [6:0] bit 5 mask. */ +#define DFLL_CALL5_bp 5 /* DFLL Calibration bits [6:0] bit 5 position. */ +#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration bits [6:0] bit 6 mask. */ +#define DFLL_CALL6_bp 6 /* DFLL Calibration bits [6:0] bit 6 position. */ + +/* DFLL.CALB bit masks and bit positions */ +#define DFLL_CALH_gm 0x3F /* DFLL Calibration bits [12:7] group mask. */ +#define DFLL_CALH_gp 0 /* DFLL Calibration bits [12:7] group position. */ +#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration bits [12:7] bit 0 mask. */ +#define DFLL_CALH0_bp 0 /* DFLL Calibration bits [12:7] bit 0 position. */ +#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration bits [12:7] bit 1 mask. */ +#define DFLL_CALH1_bp 1 /* DFLL Calibration bits [12:7] bit 1 position. */ +#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration bits [12:7] bit 2 mask. */ +#define DFLL_CALH2_bp 2 /* DFLL Calibration bits [12:7] bit 2 position. */ +#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration bits [12:7] bit 3 mask. */ +#define DFLL_CALH3_bp 3 /* DFLL Calibration bits [12:7] bit 3 position. */ +#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration bits [12:7] bit 4 mask. */ +#define DFLL_CALH4_bp 4 /* DFLL Calibration bits [12:7] bit 4 position. */ +#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration bits [12:7] bit 5 mask. */ +#define DFLL_CALH5_bp 5 /* DFLL Calibration bits [12:7] bit 5 position. */ + +/* RST - Reset */ +/* RST.STATUS bit masks and bit positions */ +#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ +#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ + +#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ +#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ + +#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ +#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ + +#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ +#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ + +#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ +#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ + +#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ +#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ + +#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ +#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ + +/* RST.CTRL bit masks and bit positions */ +#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ +#define RST_SWRST_bp 0 /* Software Reset bit position. */ + +/* WDT - Watch-Dog Timer */ +/* WDT.CTRL bit masks and bit positions */ +#define WDT_PER_gm 0x3C /* Period group mask. */ +#define WDT_PER_gp 2 /* Period group position. */ +#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ +#define WDT_PER0_bp 2 /* Period bit 0 position. */ +#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ +#define WDT_PER1_bp 3 /* Period bit 1 position. */ +#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ +#define WDT_PER2_bp 4 /* Period bit 2 position. */ +#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ +#define WDT_PER3_bp 5 /* Period bit 3 position. */ + +#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ +#define WDT_ENABLE_bp 1 /* Enable bit position. */ + +#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ +#define WDT_CEN_bp 0 /* Change Enable bit position. */ + +/* WDT.WINCTRL bit masks and bit positions */ +#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ +#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ +#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ +#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ +#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ +#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ +#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ +#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ +#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ +#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ + +#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ +#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ + +#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ +#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ + +/* WDT.STATUS bit masks and bit positions */ +#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ + +/* MCU - MCU Control */ +/* MCU.MCUCR bit masks and bit positions */ +#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ +#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ + +/* MCU.EVSYSLOCK bit masks and bit positions */ +#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ +#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ + +#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ +#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ + +/* MCU.AWEXLOCK bit masks and bit positions */ +#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ +#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ + +#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ +#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ + +/* PMIC - Programmable Multi-level Interrupt Controller */ +/* PMIC.STATUS bit masks and bit positions */ +#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ + +#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ +#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ + +#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ +#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ + +#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ +#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ + +/* PMIC.INTPRI bit masks and bit positions */ +#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ +#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ +#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ +#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ +#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ +#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ +#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ +#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ +#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ +#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ +#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ +#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ +#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ +#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ +#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ +#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ +#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ +#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ + +/* PMIC.CTRL bit masks and bit positions */ +#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ +#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ + +#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ + +#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ +#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ + +#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ +#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ + +#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ +#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ + +/* CRC - Cyclic Redundancy Checker */ +/* CRC.CTRL bit masks and bit positions */ +#define CRC_RESET_gm 0xC0 /* Reset group mask. */ +#define CRC_RESET_gp 6 /* Reset group position. */ +#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ +#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ +#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ +#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ + +#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ +#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ + +#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ +#define CRC_SOURCE_gp 0 /* Input Source group position. */ +#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ +#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ +#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ +#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ +#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ +#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ +#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ +#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ + +/* CRC.STATUS bit masks and bit positions */ +#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ +#define CRC_ZERO_bp 1 /* Zero detection bit position. */ + +#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ +#define CRC_BUSY_bp 0 /* Busy bit position. */ + +/* EVSYS - Event System */ +/* EVSYS.CH0MUX bit masks and bit positions */ +#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ +#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ +#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ +#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ +#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ +#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ +#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ +#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ +#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ +#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ +#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ +#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ +#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ +#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ +#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ +#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ +#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ +#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ + +/* EVSYS.CH1MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH2MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH3MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH0CTRL bit masks and bit positions */ +#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ +#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ +#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ +#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ +#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ +#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ + +#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ +#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ + +#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ +#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ + +#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ +#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ +#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ +#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ +#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ +#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ +#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ +#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ + +/* EVSYS.CH1CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH2CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH3CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* NVM - Non Volatile Memory Controller */ +/* NVM.CMD bit masks and bit positions */ +#define NVM_CMD_gm 0xFF /* Command group mask. */ +#define NVM_CMD_gp 0 /* Command group position. */ +#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define NVM_CMD0_bp 0 /* Command bit 0 position. */ +#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define NVM_CMD1_bp 1 /* Command bit 1 position. */ +#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ +#define NVM_CMD2_bp 2 /* Command bit 2 position. */ +#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ +#define NVM_CMD3_bp 3 /* Command bit 3 position. */ +#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ +#define NVM_CMD4_bp 4 /* Command bit 4 position. */ +#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ +#define NVM_CMD5_bp 5 /* Command bit 5 position. */ +#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ +#define NVM_CMD6_bp 6 /* Command bit 6 position. */ +#define NVM_CMD7_bm (1<<7) /* Command bit 7 mask. */ +#define NVM_CMD7_bp 7 /* Command bit 7 position. */ + +/* NVM.CTRLA bit masks and bit positions */ +#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ +#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ + +/* NVM.CTRLB bit masks and bit positions */ +#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ +#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ + +#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ +#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ + +#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ +#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ + +#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ +#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ + +/* NVM.INTCTRL bit masks and bit positions */ +#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ +#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ +#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ +#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ +#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ +#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ + +#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ +#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ +#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ +#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ +#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ +#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ + +/* NVM.STATUS bit masks and bit positions */ +#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ +#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ + +#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ +#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ + +#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ +#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ + +#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ +#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ + +/* NVM.LOCKBITS bit masks and bit positions */ +#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ + +#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ + +#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ + +#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ +#define NVM_LB_gp 0 /* Lock Bits group position. */ +#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ + +/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ +#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ + +#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ +#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ +#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ + +/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ +#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ +#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ + +#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ +#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ +#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ + +/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ +#define NVM_FUSES_DVSDON_bm 0x80 /* Spike Detector Enable bit mask. */ +#define NVM_FUSES_DVSDON_bp 7 /* Spike Detector Enable bit position. */ + +#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ +#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ + +#define NVM_FUSES_TOSCSEL_bm 0x20 /* 32.768kHz Timer Oscillator Pin Selection bit mask. */ +#define NVM_FUSES_TOSCSEL_bp 5 /* 32.768kHz Timer Oscillator Pin Selection bit position. */ + +#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ +#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ +#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ +#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ +#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ +#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ + +/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ +#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ +#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ + +#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ +#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ +#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ +#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ +#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ +#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ + +#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ +#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ + +/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ +#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ +#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ +#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ +#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ +#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ +#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ + +#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ +#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ + +#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ +#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ +#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ +#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ +#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ +#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ +#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ +#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ + +/* AC - Analog Comparator */ +/* AC.AC0CTRL bit masks and bit positions */ +#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ +#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ +#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ +#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ +#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ +#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ + +#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ +#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ +#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ +#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ +#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ +#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ + +#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ +#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ + +#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ + +#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define AC_ENABLE_bp 0 /* Enable bit position. */ + +/* AC.AC1CTRL bit masks and bit positions */ +/* AC_INTMODE Predefined. */ +/* AC_INTMODE Predefined. */ + +/* AC_INTLVL Predefined. */ +/* AC_INTLVL Predefined. */ + +/* AC_HSMODE Predefined. */ +/* AC_HSMODE Predefined. */ + +/* AC_HYSMODE Predefined. */ +/* AC_HYSMODE Predefined. */ + +/* AC_ENABLE Predefined. */ +/* AC_ENABLE Predefined. */ + +/* AC.AC0MUXCTRL bit masks and bit positions */ +#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ +#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ +#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ +#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ +#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ +#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ +#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ +#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ + +#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ +#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ +#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ +#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ +#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ +#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ +#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ +#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ + +/* AC.AC1MUXCTRL bit masks and bit positions */ +/* AC_MUXPOS Predefined. */ +/* AC_MUXPOS Predefined. */ + +/* AC_MUXNEG Predefined. */ +/* AC_MUXNEG Predefined. */ + +/* AC.CTRLA bit masks and bit positions */ +#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ +#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ + +/* AC.CTRLB bit masks and bit positions */ +#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ +#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ +#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ +#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ +#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ +#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ +#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ +#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ +#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ +#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ +#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ +#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ +#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ +#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ + +/* AC.WINCTRL bit masks and bit positions */ +#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ +#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ + +#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ +#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ +#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ +#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ +#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ +#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ + +#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ +#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ +#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ +#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ +#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ +#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ + +/* AC.STATUS bit masks and bit positions */ +#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ +#define AC_WSTATE_gp 6 /* Window Mode State group position. */ +#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ +#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ +#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ +#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ + +#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ +#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ + +#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ +#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ + +#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ +#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ + +#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ +#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ + +#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ +#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ + +/* ADC - Analog/Digital Converter */ +/* ADC_CH.CTRL bit masks and bit positions */ +#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ +#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ + +#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ +#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ +#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ +#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ +#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ +#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ +#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ +#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ + +#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ +#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ +#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ +#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ +#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ +#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ + +/* ADC_CH.MUXCTRL bit masks and bit positions */ +#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ +#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ +#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ +#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ +#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ +#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ +#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ +#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ +#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ +#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ + +#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ +#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ +#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ +#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ +#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ +#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ +#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ +#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ +#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ +#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ + +#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC input group mask. */ +#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ +#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ +#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ +#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ +#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ + +/* ADC_CH.INTCTRL bit masks and bit positions */ +#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ +#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ +#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ +#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ +#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ +#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ + +#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ +#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ +#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ +#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ +#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ +#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ + +/* ADC_CH.INTFLAGS bit masks and bit positions */ +#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ +#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ + +/* ADC_CH.SCAN bit masks and bit positions */ +#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ +#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ +#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ +#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ +#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ +#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ +#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ +#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ +#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ +#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ + +#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */ +#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */ +#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ +#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */ +#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ +#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */ +#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ +#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */ +#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ +#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */ + +/* ADC.CTRLA bit masks and bit positions */ +#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ +#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ + +#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ +#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ + +#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ +#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ + +/* ADC.CTRLB bit masks and bit positions */ +#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ +#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ +#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ +#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ +#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ +#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ + +#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ +#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ + +#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ +#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ + +#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ +#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ +#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ +#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ +#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ +#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ + +/* ADC.REFCTRL bit masks and bit positions */ +#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ +#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ +#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ +#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ + +#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ +#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ + +#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ +#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ + +/* ADC.EVCTRL bit masks and bit positions */ +#define ADC_EVSEL_gm 0x18 /* Event Input Select group mask. */ +#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ +#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ +#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ +#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ +#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ + +#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ +#define ADC_EVACT_gp 0 /* Event Action Select group position. */ +#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ +#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ +#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ +#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ +#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ +#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ + +/* ADC.PRESCALER bit masks and bit positions */ +#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ +#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ +#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ +#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ +#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ +#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ +#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ +#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ + +/* ADC.INTFLAGS bit masks and bit positions */ +#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ +#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ + +/* RTC - Real-Time Counter */ +/* RTC.CTRL bit masks and bit positions */ +#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ +#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ +#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ +#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ +#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ +#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ +#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ +#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ + +/* RTC.STATUS bit masks and bit positions */ +#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ +#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ + +/* RTC.INTCTRL bit masks and bit positions */ +#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ +#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ +#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ +#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ +#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ +#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ + +#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ +#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ +#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ +#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ +#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ +#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ + +/* RTC.INTFLAGS bit masks and bit positions */ +#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ +#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ + +#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + +/* TWI - Two-Wire Interface */ +/* TWI_MASTER.CTRLA bit masks and bit positions */ +#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ +#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ + +#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ +#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ + +#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ +#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ + +#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ +#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ + +/* TWI_MASTER.CTRLB bit masks and bit positions */ +#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Tisdahmeout group mask. */ +#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Tisdahmeout group position. */ +#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Tisdahmeout bit 0 mask. */ +#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Tisdahmeout bit 0 position. */ +#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Tisdahmeout bit 1 mask. */ +#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Tisdahmeout bit 1 position. */ + +#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ +#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ + +#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ + +/* TWI_MASTER.CTRLC bit masks and bit positions */ +#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ + +#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ +#define TWI_MASTER_CMD_gp 0 /* Command group position. */ +#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ +#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ + +/* TWI_MASTER.STATUS bit masks and bit positions */ +#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ + +#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ + +#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ + +#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ + +#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ + +#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ + +#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ +#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ +#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ + +/* TWI_SLAVE.CTRLA bit masks and bit positions */ +#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ +#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ + +#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ +#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ + +#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ +#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ + +#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ +#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ + +#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ +#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ + +#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ +#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ + +#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ + +/* TWI_SLAVE.CTRLB bit masks and bit positions */ +#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ + +#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ +#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ +#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ +#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ + +/* TWI_SLAVE.STATUS bit masks and bit positions */ +#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ + +#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ + +#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ + +#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ + +#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ +#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ + +#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ + +#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ + +#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ + +/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ +#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ +#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ + +#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ +#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ + +/* TWI.CTRL bit masks and bit positions */ +#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ +#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ +#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ +#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ +#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ +#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ + +#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ +#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ + +/* PORT - Port Configuration */ +/* PORTCFG.VPCTRLA bit masks and bit positions */ +#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ +#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ +#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ +#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ +#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ +#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ +#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ +#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ +#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ +#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ + +#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ +#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ +#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ +#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ +#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ +#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ +#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ +#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ +#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ +#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ + +/* PORTCFG.VPCTRLB bit masks and bit positions */ +#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ +#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ +#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ +#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ +#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ +#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ +#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ +#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ +#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ +#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ + +#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ +#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ +#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ +#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ +#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ +#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ +#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ +#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ +#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ +#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ + +/* PORTCFG.CLKEVOUT bit masks and bit positions */ +#define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */ +#define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */ +#define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */ +#define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */ +#define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */ +#define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */ + +#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ +#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ +#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ +#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ +#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ +#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ + +/* VPORT.INTFLAGS bit masks and bit positions */ +#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ + +#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ + +/* PORT.INTCTRL bit masks and bit positions */ +#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ +#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ +#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ +#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ +#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ +#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ + +#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ +#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ +#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ +#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ +#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ +#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ + +/* PORT.INTFLAGS bit masks and bit positions */ +#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ + +#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ + +/* PORT.REMAP bit masks and bit positions */ +#define PORT_SPI_bm 0x20 /* SPI Remap bit mask. */ +#define PORT_SPI_bp 5 /* SPI Remap bit position. */ + +#define PORT_USART0_bm 0x10 /* USART0 Remap bit mask. */ +#define PORT_USART0_bp 4 /* USART0 Remap bit position. */ + +#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ +#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ + +#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ +#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ + +#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ +#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ + +#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ +#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ + +/* PORT.PIN0CTRL bit masks and bit positions */ +#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ +#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ + +#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ +#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ + +#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ +#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ +#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ +#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ +#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ +#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ +#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ +#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ + +#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ + +/* PORT.PIN1CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN2CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN3CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN4CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN5CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN6CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN7CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* TC - 16-bit Timer/Counter With PWM */ +/* TC0.CTRLA bit masks and bit positions */ +#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + +/* TC0.CTRLB bit masks and bit positions */ +#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ +#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ + +#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ +#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ + +#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ + +#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ + +#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ + +/* TC0.CTRLC bit masks and bit positions */ +#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ +#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ + +#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ +#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ + +#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ + +#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ + +/* TC0.CTRLD bit masks and bit positions */ +#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ +#define TC0_EVACT_gp 5 /* Event Action group position. */ +#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ +#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ +#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ + +#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ +#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ + +#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ +#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ +#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ + +/* TC0.CTRLE bit masks and bit positions */ +#define TC0_BYTEM_bm 0x01 /* Byte Mode bit mask. */ +#define TC0_BYTEM_bp 0 /* Byte Mode bit position. */ + +/* TC0.INTCTRLA bit masks and bit positions */ +#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ + +#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ + +/* TC0.INTCTRLB bit masks and bit positions */ +#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ +#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ +#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ +#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ +#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ +#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ + +#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ +#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ +#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ +#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ +#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ +#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ + +#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ + +#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ + +/* TC0.CTRLFCLR bit masks and bit positions */ +#define TC0_CMD_gm 0x0C /* Command group mask. */ +#define TC0_CMD_gp 2 /* Command group position. */ +#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC0_CMD0_bp 2 /* Command bit 0 position. */ +#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC0_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TC0_LUPD_bp 1 /* Lock Update bit position. */ + +#define TC0_DIR_bm 0x01 /* Direction bit mask. */ +#define TC0_DIR_bp 0 /* Direction bit position. */ + +/* TC0.CTRLFSET bit masks and bit positions */ +/* TC0_CMD Predefined. */ +/* TC0_CMD Predefined. */ + +/* TC0_LUPD Predefined. */ +/* TC0_LUPD Predefined. */ + +/* TC0_DIR Predefined. */ +/* TC0_DIR Predefined. */ + +/* TC0.CTRLGCLR bit masks and bit positions */ +#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ +#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ + +#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ +#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ + +#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ + +#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ + +#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ + +/* TC0.CTRLGSET bit masks and bit positions */ +/* TC0_CCDBV Predefined. */ +/* TC0_CCDBV Predefined. */ + +/* TC0_CCCBV Predefined. */ +/* TC0_CCCBV Predefined. */ + +/* TC0_CCBBV Predefined. */ +/* TC0_CCBBV Predefined. */ + +/* TC0_CCABV Predefined. */ +/* TC0_CCABV Predefined. */ + +/* TC0_PERBV Predefined. */ +/* TC0_PERBV Predefined. */ + +/* TC0.INTFLAGS bit masks and bit positions */ +#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ +#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ + +#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ +#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ + +#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ + +#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ + +#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ + +#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + +/* TC1.CTRLA bit masks and bit positions */ +#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + +/* TC1.CTRLB bit masks and bit positions */ +#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ + +#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ + +#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ + +/* TC1.CTRLC bit masks and bit positions */ +#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ + +#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ + +/* TC1.CTRLD bit masks and bit positions */ +#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ +#define TC1_EVACT_gp 5 /* Event Action group position. */ +#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ +#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ +#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ + +#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ +#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ + +#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ +#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ +#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ + +/* TC1.CTRLE bit masks and bit positions */ +#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ +#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ + +/* TC1.INTCTRLA bit masks and bit positions */ +#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ + +#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ + +/* TC1.INTCTRLB bit masks and bit positions */ +#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ + +#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ + +/* TC1.CTRLFCLR bit masks and bit positions */ +#define TC1_CMD_gm 0x0C /* Command group mask. */ +#define TC1_CMD_gp 2 /* Command group position. */ +#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC1_CMD0_bp 2 /* Command bit 0 position. */ +#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC1_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TC1_LUPD_bp 1 /* Lock Update bit position. */ + +#define TC1_DIR_bm 0x01 /* Direction bit mask. */ +#define TC1_DIR_bp 0 /* Direction bit position. */ + +/* TC1.CTRLFSET bit masks and bit positions */ +/* TC1_CMD Predefined. */ +/* TC1_CMD Predefined. */ + +/* TC1_LUPD Predefined. */ +/* TC1_LUPD Predefined. */ + +/* TC1_DIR Predefined. */ +/* TC1_DIR Predefined. */ + +/* TC1.CTRLGCLR bit masks and bit positions */ +#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ + +#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ + +#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ + +/* TC1.CTRLGSET bit masks and bit positions */ +/* TC1_CCBBV Predefined. */ +/* TC1_CCBBV Predefined. */ + +/* TC1_CCABV Predefined. */ +/* TC1_CCABV Predefined. */ + +/* TC1_PERBV Predefined. */ +/* TC1_PERBV Predefined. */ + +/* TC1.INTFLAGS bit masks and bit positions */ +#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ + +#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ + +#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ + +#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + +/* AWEX.CTRL bit masks and bit positions */ +#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ +#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ + +#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ +#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ + +#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ +#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ + +#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ +#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ + +#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ +#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ + +#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ +#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ + +/* AWEX.FDCTRL bit masks and bit positions */ +#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ +#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ + +#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ +#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ + +#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ +#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ +#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ +#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ +#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ +#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ + +/* AWEX.STATUS bit masks and bit positions */ +#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ +#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ + +#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ +#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ + +#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ +#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ + +/* HIRES.CTRLA bit masks and bit positions */ +#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ +#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ +#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ +#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ +#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ +#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ + +/* USART - Universal Asynchronous Receiver-Transmitter */ +/* USART.STATUS bit masks and bit positions */ +#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ +#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ + +#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ + +#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ + +#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ +#define USART_FERR_bp 4 /* Frame Error bit position. */ + +#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ +#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ + +#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ +#define USART_PERR_bp 2 /* Parity Error bit position. */ + +#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ +#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ + +/* USART.CTRLA bit masks and bit positions */ +#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ +#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ +#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ +#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ +#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ +#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ + +#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ +#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ +#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ +#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ +#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ +#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ + +#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ +#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ +#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ +#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ +#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ +#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ + +/* USART.CTRLB bit masks and bit positions */ +#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ +#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ + +#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ +#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ + +#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ +#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ + +#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ +#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ + +#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ +#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ + +/* USART.CTRLC bit masks and bit positions */ +#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +#define USART_CMODE_gp 6 /* Communication Mode group position. */ +#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ + +#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +#define USART_PMODE_gp 4 /* Parity Mode group position. */ +#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ + +#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ + +#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +#define USART_CHSIZE_gp 0 /* Character Size group position. */ +#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ + +#define USART_UDORD_bm 0x04 /* SPI Master Mode, Data Order bit mask. */ +#define USART_UDORD_bp 2 /* SPI Master Mode, Data Order bit position. */ + +#define USART_UCPHA_bm 0x02 /* SPI Master Mode, Clock Phase bit mask. */ +#define USART_UCPHA_bp 1 /* SPI Master Mode, Clock Phase bit position. */ + +/* USART.BAUDCTRLA bit masks and bit positions */ +#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ +#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ +#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ +#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ +#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ +#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ +#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ +#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ +#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ +#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ +#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ +#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ +#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ +#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ +#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ +#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ +#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ +#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ + +/* USART.BAUDCTRLB bit masks and bit positions */ +#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ +#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ +#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ +#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ +#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ +#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ +#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ +#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ +#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ +#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ + +/* USART_BSEL Predefined. */ +/* USART_BSEL Predefined. */ + +/* SPI - Serial Peripheral Interface */ +/* SPI.CTRL bit masks and bit positions */ +#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ +#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ + +#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ +#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ + +#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ +#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ + +#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ +#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ + +#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ +#define SPI_MODE_gp 2 /* SPI Mode group position. */ +#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ +#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ +#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ +#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ + +#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ +#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ +#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ +#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ +#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ +#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ + +/* SPI.INTCTRL bit masks and bit positions */ +#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ +#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ +#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ +#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ +#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ +#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ + +/* SPI.STATUS bit masks and bit positions */ +#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ +#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ + +#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ +#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ + +/* IRCOM - IR Communication Module */ +/* IRCOM.CTRL bit masks and bit positions */ +#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ +#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ +#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ +#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ +#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ +#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ +#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ +#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ +#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ +#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ + + + +// Generic Port Pins + +#define PIN0_bm 0x01 +#define PIN0_bp 0 +#define PIN1_bm 0x02 +#define PIN1_bp 1 +#define PIN2_bm 0x04 +#define PIN2_bp 2 +#define PIN3_bm 0x08 +#define PIN3_bp 3 +#define PIN4_bm 0x10 +#define PIN4_bp 4 +#define PIN5_bm 0x20 +#define PIN5_bp 5 +#define PIN6_bm 0x40 +#define PIN6_bp 6 +#define PIN7_bm 0x80 +#define PIN7_bp 7 + +/* ========== Interrupt Vector Definitions ========== */ +/* Vector 0 is the reset vector */ + +/* OSC interrupt vectors */ +#define OSC_OSCF_vect_num 1 +#define OSC_OSCF_vect _VECTOR(1) /* External Oscillator Failure Interrupt (NMI) */ + +/* PORTC interrupt vectors */ +#define PORTC_INT0_vect_num 2 +#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ +#define PORTC_INT1_vect_num 3 +#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ + +/* PORTR interrupt vectors */ +#define PORTR_INT0_vect_num 4 +#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ +#define PORTR_INT1_vect_num 5 +#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ + +/* RTC interrupt vectors */ +#define RTC_OVF_vect_num 10 +#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ +#define RTC_COMP_vect_num 11 +#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ + +/* TWIC interrupt vectors */ +#define TWIC_TWIS_vect_num 12 +#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ +#define TWIC_TWIM_vect_num 13 +#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_OVF_vect_num 14 +#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ +#define TCC0_ERR_vect_num 15 +#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ +#define TCC0_CCA_vect_num 16 +#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ +#define TCC0_CCB_vect_num 17 +#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ +#define TCC0_CCC_vect_num 18 +#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ +#define TCC0_CCD_vect_num 19 +#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ + +/* TCC1 interrupt vectors */ +#define TCC1_OVF_vect_num 20 +#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ +#define TCC1_ERR_vect_num 21 +#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ +#define TCC1_CCA_vect_num 22 +#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ +#define TCC1_CCB_vect_num 23 +#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ + +/* SPIC interrupt vectors */ +#define SPIC_INT_vect_num 24 +#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ + +/* USARTC0 interrupt vectors */ +#define USARTC0_RXC_vect_num 25 +#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ +#define USARTC0_DRE_vect_num 26 +#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ +#define USARTC0_TXC_vect_num 27 +#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ + +/* NVM interrupt vectors */ +#define NVM_EE_vect_num 32 +#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ +#define NVM_SPM_vect_num 33 +#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ + +/* PORTB interrupt vectors */ +#define PORTB_INT0_vect_num 34 +#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ +#define PORTB_INT1_vect_num 35 +#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ + +/* PORTE interrupt vectors */ +#define PORTE_INT0_vect_num 43 +#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ +#define PORTE_INT1_vect_num 44 +#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ + +/* TWIE interrupt vectors */ +#define TWIE_TWIS_vect_num 45 +#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ +#define TWIE_TWIM_vect_num 46 +#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_OVF_vect_num 47 +#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ +#define TCE0_ERR_vect_num 48 +#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ +#define TCE0_CCA_vect_num 49 +#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ +#define TCE0_CCB_vect_num 50 +#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ +#define TCE0_CCC_vect_num 51 +#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ +#define TCE0_CCD_vect_num 52 +#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ + +/* USARTE0 interrupt vectors */ +#define USARTE0_RXC_vect_num 58 +#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ +#define USARTE0_DRE_vect_num 59 +#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ +#define USARTE0_TXC_vect_num 60 +#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ + +/* PORTD interrupt vectors */ +#define PORTD_INT0_vect_num 64 +#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ +#define PORTD_INT1_vect_num 65 +#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ + +/* PORTA interrupt vectors */ +#define PORTA_INT0_vect_num 66 +#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ +#define PORTA_INT1_vect_num 67 +#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ + +/* ACA interrupt vectors */ +#define ACA_AC0_vect_num 68 +#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ +#define ACA_AC1_vect_num 69 +#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ +#define ACA_ACW_vect_num 70 +#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ + +/* ADCA interrupt vectors */ +#define ADCA_CH0_vect_num 71 +#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ + +/* TCD0 interrupt vectors */ +#define TCD0_OVF_vect_num 77 +#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ +#define TCD0_ERR_vect_num 78 +#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ +#define TCD0_CCA_vect_num 79 +#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ +#define TCD0_CCB_vect_num 80 +#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ +#define TCD0_CCC_vect_num 81 +#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ +#define TCD0_CCD_vect_num 82 +#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ + +/* SPID interrupt vectors */ +#define SPID_INT_vect_num 87 +#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ + +/* USARTD0 interrupt vectors */ +#define USARTD0_RXC_vect_num 88 +#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ +#define USARTD0_DRE_vect_num 89 +#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ +#define USARTD0_TXC_vect_num 90 +#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ + +/* PORTF interrupt vectors */ +#define PORTF_INT0_vect_num 104 +#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ +#define PORTF_INT1_vect_num 105 +#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ + +/* TCF0 interrupt vectors */ +#define TCF0_OVF_vect_num 108 +#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ +#define TCF0_ERR_vect_num 109 +#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ +#define TCF0_CCA_vect_num 110 +#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ +#define TCF0_CCB_vect_num 111 +#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ +#define TCF0_CCC_vect_num 112 +#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ +#define TCF0_CCD_vect_num 113 +#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ + +#define _VECTOR_SIZE 4 /* Size of individual vector. */ +#define _VECTORS_SIZE (114 * _VECTOR_SIZE) + + +/* ========== Constants ========== */ + +#define PROGMEM_START (0x0000) +#define PROGMEM_SIZE (36864) +#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) + +#define APP_SECTION_START (0x0000) +#define APP_SECTION_SIZE (32768) +#define APP_SECTION_PAGE_SIZE (256) +#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) + +#define APPTABLE_SECTION_START (0x7000) +#define APPTABLE_SECTION_SIZE (4096) +#define APPTABLE_SECTION_PAGE_SIZE (256) +#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) + +#define BOOT_SECTION_START (0x8000) +#define BOOT_SECTION_SIZE (4096) +#define BOOT_SECTION_PAGE_SIZE (256) +#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) + +#define DATAMEM_START (0x0000) +#define DATAMEM_SIZE (12288) +#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) + +#define IO_START (0x0000) +#define IO_SIZE (4096) +#define IO_PAGE_SIZE (0) +#define IO_END (IO_START + IO_SIZE - 1) + +#define MAPPED_EEPROM_START (0x1000) +#define MAPPED_EEPROM_SIZE (1024) +#define MAPPED_EEPROM_PAGE_SIZE (0) +#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) + +#define INTERNAL_SRAM_START (0x2000) +#define INTERNAL_SRAM_SIZE (4096) +#define INTERNAL_SRAM_PAGE_SIZE (0) +#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) + +#define EEPROM_START (0x0000) +#define EEPROM_SIZE (1024) +#define EEPROM_PAGE_SIZE (32) +#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) + +#define SIGNATURES_START (0x0000) +#define SIGNATURES_SIZE (3) +#define SIGNATURES_PAGE_SIZE (0) +#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) + +#define FUSES_START (0x0000) +#define FUSES_SIZE (6) +#define FUSES_PAGE_SIZE (0) +#define FUSES_END (FUSES_START + FUSES_SIZE - 1) + +#define LOCKBITS_START (0x0000) +#define LOCKBITS_SIZE (1) +#define LOCKBITS_PAGE_SIZE (0) +#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) + +#define USER_SIGNATURES_START (0x0000) +#define USER_SIGNATURES_SIZE (256) +#define USER_SIGNATURES_PAGE_SIZE (256) +#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) + +#define PROD_SIGNATURES_START (0x0000) +#define PROD_SIGNATURES_SIZE (52) +#define PROD_SIGNATURES_PAGE_SIZE (256) +#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) + +#define FLASHSTART PROGMEM_START +#define FLASHEND PROGMEM_END +#define SPM_PAGESIZE 256 +#define RAMSTART INTERNAL_SRAM_START +#define RAMSIZE INTERNAL_SRAM_SIZE +#define RAMEND INTERNAL_SRAM_END +#define E2END EEPROM_END +#define E2PAGESIZE EEPROM_PAGE_SIZE + + +/* ========== Fuses ========== */ +#define FUSE_MEMORY_SIZE 6 + +/* Fuse Byte 0 Reserved */ + +/* Fuse Byte 1 */ +#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ +#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ +#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ +#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ +#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +#define FUSE1_DEFAULT (0xFF) + +/* Fuse Byte 2 */ +#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ +#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ +#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* 32.768kHz Timer Oscillator Pin Selection */ +#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ +#define FUSE_DVSDON (unsigned char)~_BV(7) /* Spike Detector Enable */ +#define FUSE2_DEFAULT (0xFF) + +/* Fuse Byte 3 Reserved */ + +/* Fuse Byte 4 */ +#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ +#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ +#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ +#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ +#define FUSE4_DEFAULT (0xFF) + +/* Fuse Byte 5 */ +#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ +#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ +#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ +#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ +#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ +#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ +#define FUSE5_DEFAULT (0xFF) + +/* ========== Lock Bits ========== */ +#define __LOCK_BITS_EXIST +#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST +#define __BOOT_LOCK_APPLICATION_BITS_EXIST +#define __BOOT_LOCK_BOOT_BITS_EXIST + +/* ========== Signature ========== */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x95 +#define SIGNATURE_2 0x4A + +/* ========== Power Reduction Condition Definitions ========== */ + +/* PR.PRGEN */ +#define __AVR_HAVE_PRGEN (PR_RTC_bm|PR_EVSYS_bm) +#define __AVR_HAVE_PRGEN_RTC +#define __AVR_HAVE_PRGEN_EVSYS + +/* PR.PRPA */ +#define __AVR_HAVE_PRPA (PR_ADC_bm|PR_AC_bm) +#define __AVR_HAVE_PRPA_ADC +#define __AVR_HAVE_PRPA_AC + +/* PR.PRPC */ +#define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPC_TWI +#define __AVR_HAVE_PRPC_USART0 +#define __AVR_HAVE_PRPC_SPI +#define __AVR_HAVE_PRPC_HIRES +#define __AVR_HAVE_PRPC_TC1 +#define __AVR_HAVE_PRPC_TC0 + +/* PR.PRPD */ +#define __AVR_HAVE_PRPD (PR_USART0_bm|PR_SPI_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPD_USART0 +#define __AVR_HAVE_PRPD_SPI +#define __AVR_HAVE_PRPD_TC0 + +/* PR.PRPE */ +#define __AVR_HAVE_PRPE (PR_TWI_bm|PR_USART0_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPE_TWI +#define __AVR_HAVE_PRPE_USART0 +#define __AVR_HAVE_PRPE_TC0 + +/* PR.PRPF */ +#define __AVR_HAVE_PRPF (PR_USART0_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPF_USART0 +#define __AVR_HAVE_PRPF_TC0 + + +#endif /* #ifdef _AVR_ATXMEGA32D3_H_INCLUDED */ diff --git a/include/avr/iox32d4.h b/include/avr/iox32d4.h index 1e7be8e3..a7d73d9e 100644 --- a/include/avr/iox32d4.h +++ b/include/avr/iox32d4.h @@ -42,7 +42,7 @@ # define _AVR_IOXXX_H_ "iox32d4.h" #else # error "Attempt to include more than one file." -#endif +#endif #ifndef _AVR_ATxmega32D4_H_ @@ -1106,7 +1106,7 @@ typedef enum ADC_CH_GAIN_enum ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ - ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ + ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ } ADC_CH_GAIN_t; /* Conversion result resolution */ @@ -5317,21 +5317,21 @@ IO Module Instances. Mapped to memory. // Generic Port Pins -#define PIN0_bm 0x01 +#define PIN0_bm 0x01 #define PIN0_bp 0 #define PIN1_bm 0x02 #define PIN1_bp 1 -#define PIN2_bm 0x04 +#define PIN2_bm 0x04 #define PIN2_bp 2 -#define PIN3_bm 0x08 +#define PIN3_bm 0x08 #define PIN3_bp 3 -#define PIN4_bm 0x10 +#define PIN4_bm 0x10 #define PIN4_bp 4 -#define PIN5_bm 0x20 +#define PIN5_bm 0x20 #define PIN5_bp 5 -#define PIN6_bm 0x40 +#define PIN6_bm 0x40 #define PIN6_bp 6 -#define PIN7_bm 0x80 +#define PIN7_bm 0x80 #define PIN7_bp 7 @@ -5681,4 +5681,3 @@ IO Module Instances. Mapped to memory. #endif /* _AVR_ATxmega32D4_H_ */ - diff --git a/include/avr/iox32e5.h b/include/avr/iox32e5.h index 2e3a4ad3..be22f9e8 100644 --- a/include/avr/iox32e5.h +++ b/include/avr/iox32e5.h @@ -1,7699 +1,7698 @@ -/***************************************************************************** - * - * Copyright (C) 2016 Atmel Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * * Neither the name of the copyright holders nor the names of - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************/ - - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iox32e5.h" -#else -# error "Attempt to include more than one file." -#endif - -#ifndef _AVR_ATXMEGA32E5_H_INCLUDED -#define _AVR_ATXMEGA32E5_H_INCLUDED - -/* Ungrouped common registers */ -#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ - -/* Deprecated */ -#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ - -#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ -#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ -#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ -#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ -#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ -#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ -#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ -#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ -#define SREG _SFR_MEM8(0x003F) /* Status Register */ - -/* C Language Only */ -#if !defined (__ASSEMBLER__) - -#include - -typedef volatile uint8_t register8_t; -typedef volatile uint16_t register16_t; -typedef volatile uint32_t register32_t; - - -#ifdef _WORDREGISTER -#undef _WORDREGISTER -#endif -#define _WORDREGISTER(regname) \ - __extension__ union \ - { \ - register16_t regname; \ - struct \ - { \ - register8_t regname ## L; \ - register8_t regname ## H; \ - }; \ - } - -#ifdef _DWORDREGISTER -#undef _DWORDREGISTER -#endif -#define _DWORDREGISTER(regname) \ - __extension__ union \ - { \ - register32_t regname; \ - struct \ - { \ - register8_t regname ## 0; \ - register8_t regname ## 1; \ - register8_t regname ## 2; \ - register8_t regname ## 3; \ - }; \ - } - - -/* -========================================================================== -IO Module Structures -========================================================================== -*/ - - -/* --------------------------------------------------------------------------- -VPORT - Virtual Ports --------------------------------------------------------------------------- -*/ - -/* Virtual Port */ -typedef struct VPORT_struct -{ - register8_t DIR; /* I/O Port Data Direction */ - register8_t OUT; /* I/O Port Output */ - register8_t IN; /* I/O Port Input */ - register8_t INTFLAGS; /* Interrupt Flag Register */ -} VPORT_t; - - -/* --------------------------------------------------------------------------- -XOCD - On-Chip Debug System --------------------------------------------------------------------------- -*/ - -/* On-Chip Debug System */ -typedef struct OCD_struct -{ - register8_t OCDR0; /* OCD Register 0 */ - register8_t OCDR1; /* OCD Register 1 */ -} OCD_t; - - -/* --------------------------------------------------------------------------- -CPU - CPU --------------------------------------------------------------------------- -*/ - -/* CCP signatures */ -typedef enum CCP_enum -{ - CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ - CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ -} CCP_t; - - -/* --------------------------------------------------------------------------- -CLK - Clock System --------------------------------------------------------------------------- -*/ - -/* Clock System */ -typedef struct CLK_struct -{ - register8_t CTRL; /* Control Register */ - register8_t PSCTRL; /* Prescaler Control Register */ - register8_t LOCK; /* Lock register */ - register8_t RTCCTRL; /* RTC Control Register */ - register8_t reserved_0x04; -} CLK_t; - - -/* Power Reduction */ -typedef struct PR_struct -{ - register8_t PRGEN; /* General Power Reduction */ - register8_t PRPA; /* Power Reduction Port A */ - register8_t reserved_0x02; - register8_t PRPC; /* Power Reduction Port C */ - register8_t PRPD; /* Power Reduction Port D */ - register8_t reserved_0x05; - register8_t reserved_0x06; -} PR_t; - -/* System Clock Selection */ -typedef enum CLK_SCLKSEL_enum -{ - CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ - CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ - CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ - CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ - CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ - CLK_SCLKSEL_RC8M_gc = (0x05<<0), /* Internal 8 MHz RC Oscillator */ -} CLK_SCLKSEL_t; - -/* Prescaler A Division Factor */ -typedef enum CLK_PSADIV_enum -{ - CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ - CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ - CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ - CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ - CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ - CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ - CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ - CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ - CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ - CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ - CLK_PSADIV_6_gc = (0x13<<2), /* Divide by 6 */ - CLK_PSADIV_10_gc = (0x15<<2), /* Divide by 10 */ - CLK_PSADIV_12_gc = (0x17<<2), /* Divide by 12 */ - CLK_PSADIV_24_gc = (0x19<<2), /* Divide by 24 */ - CLK_PSADIV_48_gc = (0x1B<<2), /* Divide by 48 */ -} CLK_PSADIV_t; - -/* Prescaler B and C Division Factor */ -typedef enum CLK_PSBCDIV_enum -{ - CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ - CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ - CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ - CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ -} CLK_PSBCDIV_t; - -/* RTC Clock Source */ -typedef enum CLK_RTCSRC_enum -{ - CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ - CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ - CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ - CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ - CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ - CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ -} CLK_RTCSRC_t; - - -/* --------------------------------------------------------------------------- -SLEEP - Sleep Controller --------------------------------------------------------------------------- -*/ - -/* Sleep Controller */ -typedef struct SLEEP_struct -{ - register8_t CTRL; /* Control Register */ -} SLEEP_t; - -/* Sleep Mode */ -typedef enum SLEEP_SMODE_enum -{ - SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ - SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ - SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ - SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ - SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ -} SLEEP_SMODE_t; - - - -#define SLEEP_MODE_IDLE (0x00<<1) -#define SLEEP_MODE_PWR_DOWN (0x02<<1) -#define SLEEP_MODE_PWR_SAVE (0x03<<1) -#define SLEEP_MODE_STANDBY (0x06<<1) -#define SLEEP_MODE_EXT_STANDBY (0x07<<1) -/* --------------------------------------------------------------------------- -OSC - Oscillator --------------------------------------------------------------------------- -*/ - -/* Oscillator */ -typedef struct OSC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t XOSCCTRL; /* External Oscillator Control Register */ - register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ - register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ - register8_t PLLCTRL; /* PLL Control Register */ - register8_t DFLLCTRL; /* DFLL Control Register */ - register8_t RC8MCAL; /* Internal 8 MHz RC Oscillator Calibration Register */ -} OSC_t; - -/* Oscillator Frequency Range */ -typedef enum OSC_FRQRANGE_enum -{ - OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ - OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ - OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ - OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ -} OSC_FRQRANGE_t; - -/* External Oscillator Selection and Startup Time */ -typedef enum OSC_XOSCSEL_enum -{ - OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock on port R1 - 6 CLK */ - OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ - OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ - OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ - OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ - OSC_XOSCSEL_EXTCLK_C4_gc = (0x14<<0), /* External Clock on port C4 - 6 CLK */ -} OSC_XOSCSEL_t; - -/* PLL Clock Source */ -typedef enum OSC_PLLSRC_enum -{ - OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ - OSC_PLLSRC_RC8M_gc = (0x01<<6), /* Internal 8 MHz RC Oscillator */ - OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ - OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ -} OSC_PLLSRC_t; - -/* 32 MHz DFLL Calibration Reference */ -typedef enum OSC_RC32MCREF_enum -{ - OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ - OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ -} OSC_RC32MCREF_t; - - -/* --------------------------------------------------------------------------- -DFLL - DFLL --------------------------------------------------------------------------- -*/ - -/* DFLL */ -typedef struct DFLL_struct -{ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x01; - register8_t CALA; /* Calibration Register A */ - register8_t CALB; /* Calibration Register B */ - register8_t COMP0; /* Oscillator Compare Register 0 */ - register8_t COMP1; /* Oscillator Compare Register 1 */ - register8_t COMP2; /* Oscillator Compare Register 2 */ - register8_t reserved_0x07; -} DFLL_t; - - -/* --------------------------------------------------------------------------- -RST - Reset --------------------------------------------------------------------------- -*/ - -/* Reset */ -typedef struct RST_struct -{ - register8_t STATUS; /* Status Register */ - register8_t CTRL; /* Control Register */ -} RST_t; - - -/* --------------------------------------------------------------------------- -WDT - Watch-Dog Timer --------------------------------------------------------------------------- -*/ - -/* Watch-Dog Timer */ -typedef struct WDT_struct -{ - register8_t CTRL; /* Control */ - register8_t WINCTRL; /* Windowed Mode Control */ - register8_t STATUS; /* Status */ -} WDT_t; - -/* Period setting */ -typedef enum WDT_PER_enum -{ - WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ - WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ - WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ - WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ - WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ - WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ - WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ - WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ - WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ - WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -} WDT_PER_t; - -/* Closed window period */ -typedef enum WDT_WPER_enum -{ - WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ - WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ - WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ - WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ - WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ - WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ - WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ - WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ - WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ - WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -} WDT_WPER_t; - - -/* --------------------------------------------------------------------------- -MCU - MCU Control --------------------------------------------------------------------------- -*/ - -/* MCU Control */ -typedef struct MCU_struct -{ - register8_t DEVID0; /* Device ID byte 0 */ - register8_t DEVID1; /* Device ID byte 1 */ - register8_t DEVID2; /* Device ID byte 2 */ - register8_t REVID; /* Revision ID */ - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t ANAINIT; /* Analog Startup Delay */ - register8_t EVSYSLOCK; /* Event System Lock */ - register8_t WEXLOCK; /* WEX Lock */ - register8_t FAULTLOCK; /* FAULT Lock */ - register8_t reserved_0x0B; -} MCU_t; - - -/* --------------------------------------------------------------------------- -PMIC - Programmable Multi-level Interrupt Controller --------------------------------------------------------------------------- -*/ - -/* Programmable Multi-level Interrupt Controller */ -typedef struct PMIC_struct -{ - register8_t STATUS; /* Status Register */ - register8_t INTPRI; /* Interrupt Priority */ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x03; - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; -} PMIC_t; - - -/* --------------------------------------------------------------------------- -PORTCFG - Port Configuration --------------------------------------------------------------------------- -*/ - -/* I/O port Configuration */ -typedef struct PORTCFG_struct -{ - register8_t MPCMASK; /* Multi-pin Configuration Mask */ - register8_t reserved_0x01; - register8_t reserved_0x02; - register8_t reserved_0x03; - register8_t CLKOUT; /* Clock Out Register */ - register8_t reserved_0x05; - register8_t ACEVOUT; /* Analog Comparator and Event Out Register */ - register8_t SRLCTRL; /* Slew Rate Limit Control Register */ -} PORTCFG_t; - -/* Clock and Event Output Port */ -typedef enum PORTCFG_CLKEVPIN_enum -{ - PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */ - PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */ -} PORTCFG_CLKEVPIN_t; - -/* RTC Clock Output Port */ -typedef enum PORTCFG_RTCCLKOUT_enum -{ - PORTCFG_RTCCLKOUT_OFF_gc = (0x00<<5), /* System Clock Output Disabled */ - PORTCFG_RTCCLKOUT_PC6_gc = (0x01<<5), /* System Clock Output on Port C pin 6 */ - PORTCFG_RTCCLKOUT_PD6_gc = (0x02<<5), /* System Clock Output on Port D pin 6 */ - PORTCFG_RTCCLKOUT_PR0_gc = (0x03<<5), /* System Clock Output on Port R pin 0 */ -} PORTCFG_RTCCLKOUT_t; - -/* Peripheral Clock Output Select */ -typedef enum PORTCFG_CLKOUTSEL_enum -{ - PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ - PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ - PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ -} PORTCFG_CLKOUTSEL_t; - -/* System Clock Output Port */ -typedef enum PORTCFG_CLKOUT_enum -{ - PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ - PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ - PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ - PORTCFG_CLKOUT_PR0_gc = (0x03<<0), /* System Clock Output on Port R pin 0 */ -} PORTCFG_CLKOUT_t; - -/* Analog Comparator Output Port */ -typedef enum PORTCFG_ACOUT_enum -{ - PORTCFG_ACOUT_PA_gc = (0x00<<6), /* Analog Comparator Outputs on Port A, Pin 6-7 */ - PORTCFG_ACOUT_PC_gc = (0x01<<6), /* Analog Comparator Outputs on Port C, Pin 6-7 */ - PORTCFG_ACOUT_PD_gc = (0x02<<6), /* Analog Comparator Outputs on Port D, Pin 6-7 */ - PORTCFG_ACOUT_PR_gc = (0x03<<6), /* Analog Comparator Outputs on Port R, Pin 0-1 */ -} PORTCFG_ACOUT_t; - -/* Event Output Port */ -typedef enum PORTCFG_EVOUT_enum -{ - PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ - PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel n Output on Port C pin 7 */ - PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel n Output on Port D pin 7 */ - PORTCFG_EVOUT_PR0_gc = (0x03<<4), /* Event Channel n Output on Port R pin 0 */ -} PORTCFG_EVOUT_t; - -/* Event Output Select */ -typedef enum PORTCFG_EVOUTSEL_enum -{ - PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ - PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ - PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ - PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ - PORTCFG_EVOUTSEL_4_gc = (0x04<<0), /* Event Channel 4 output to pin */ - PORTCFG_EVOUTSEL_5_gc = (0x05<<0), /* Event Channel 5 output to pin */ - PORTCFG_EVOUTSEL_6_gc = (0x06<<0), /* Event Channel 6 output to pin */ - PORTCFG_EVOUTSEL_7_gc = (0x07<<0), /* Event Channel 7 output to pin */ -} PORTCFG_EVOUTSEL_t; - - -/* --------------------------------------------------------------------------- -CRC - Cyclic Redundancy Checker --------------------------------------------------------------------------- -*/ - -/* Cyclic Redundancy Checker */ -typedef struct CRC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t reserved_0x02; - register8_t DATAIN; /* Data Input */ - register8_t CHECKSUM0; /* Checksum byte 0 */ - register8_t CHECKSUM1; /* Checksum byte 1 */ - register8_t CHECKSUM2; /* Checksum byte 2 */ - register8_t CHECKSUM3; /* Checksum byte 3 */ -} CRC_t; - -/* Reset */ -typedef enum CRC_RESET_enum -{ - CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ - CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ - CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ -} CRC_RESET_t; - -/* Input Source */ -typedef enum CRC_SOURCE_enum -{ - CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ - CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ - CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ - CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */ - CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */ - CRC_SOURCE_DMAC2_gc = (0x06<<0), /* DMAC Channel 2 */ - CRC_SOURCE_DMAC3_gc = (0x07<<0), /* DMAC Channel 3 */ -} CRC_SOURCE_t; - - -/* --------------------------------------------------------------------------- -EDMA - Enhanced DMA Controller --------------------------------------------------------------------------- -*/ - -/* EDMA Channel */ -typedef struct EDMA_CH_struct -{ - register8_t CTRLA; /* Channel Control A */ - register8_t CTRLB; /* Channel Control */ - register8_t ADDRCTRL; /* Memory Address Control for Peripheral Ch., or Source Address Control for Standard Ch. */ - register8_t DESTADDRCTRL; /* Destination Address Control for Standard Channels Only. */ - register8_t TRIGSRC; /* Channel Trigger Source */ - register8_t reserved_0x05; - _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count for Peripheral Ch., or Channel Block Transfer Count Low for Standard Ch. */ - _WORDREGISTER(ADDR); /* Channel Memory Address for Peripheral Ch., or Channel Source Address Low for Standard Ch. */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; - _WORDREGISTER(DESTADDR); /* Channel Destination Address for Standard Channels Only. */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; -} EDMA_CH_t; - - -/* Enhanced DMA Controller */ -typedef struct EDMA_struct -{ - register8_t CTRL; /* Control */ - register8_t reserved_0x01; - register8_t reserved_0x02; - register8_t INTFLAGS; /* Transfer Interrupt Status */ - register8_t STATUS; /* Status */ - register8_t reserved_0x05; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - EDMA_CH_t CH0; /* EDMA Channel 0 */ - EDMA_CH_t CH1; /* EDMA Channel 1 */ - EDMA_CH_t CH2; /* EDMA Channel 2 */ - EDMA_CH_t CH3; /* EDMA Channel 3 */ -} EDMA_t; - -/* Channel mode */ -typedef enum EDMA_CHMODE_enum -{ - EDMA_CHMODE_PER0123_gc = (0x00<<4), /* Channels 0, 1, 2 and 3 in peripheal conf. */ - EDMA_CHMODE_STD0_gc = (0x01<<4), /* Channel 0 in standard conf.; channels 2 and 3 in peripheral conf. */ - EDMA_CHMODE_STD2_gc = (0x02<<4), /* Channel 2 in standard conf.; channels 0 and 1 in peripheral conf. */ - EDMA_CHMODE_STD02_gc = (0x03<<4), /* Channels 0 and 2 in standard conf. */ -} EDMA_CHMODE_t; - -/* Double buffer mode */ -typedef enum EDMA_DBUFMODE_enum -{ - EDMA_DBUFMODE_DISABLE_gc = (0x00<<2), /* No double buffer enabled */ - EDMA_DBUFMODE_BUF01_gc = (0x01<<2), /* Double buffer enabled on peripheral channels 0/1 (if exist) */ - EDMA_DBUFMODE_BUF23_gc = (0x02<<2), /* Double buffer enabled on peripheral channels 2/3 (if exist) */ - EDMA_DBUFMODE_BUF0123_gc = (0x03<<2), /* Double buffer enabled on peripheral channels 0/1 and 2/3 or standard channels 0/2 */ -} EDMA_DBUFMODE_t; - -/* Priority mode */ -typedef enum EDMA_PRIMODE_enum -{ - EDMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round robin on all channels */ - EDMA_PRIMODE_RR123_gc = (0x01<<0), /* Ch0 > round robin (Ch 1 ch2 Ch3) */ - EDMA_PRIMODE_RR23_gc = (0x02<<0), /* Ch0 > Ch 1 > round robin (Ch2 Ch3) */ - EDMA_PRIMODE_CH0123_gc = (0x03<<0), /* Ch0 > Ch1 > Ch2 > Ch3 */ -} EDMA_PRIMODE_t; - -/* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. */ -typedef enum EDMA_CH_RELOAD_enum -{ - EDMA_CH_RELOAD_NONE_gc = (0x00<<4), /* No reload */ - EDMA_CH_RELOAD_BLOCK_gc = (0x01<<4), /* Reload at end of each block transfer */ - EDMA_CH_RELOAD_BURST_gc = (0x02<<4), /* Reload at end of each burst transfer */ - EDMA_CH_RELOAD_TRANSACTION_gc = (0x03<<4), /* Reload at end of each transaction */ -} EDMA_CH_RELOAD_t; - -/* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. */ -typedef enum EDMA_CH_DIR_enum -{ - EDMA_CH_DIR_FIXED_gc = (0x00<<0), /* Fixed */ - EDMA_CH_DIR_INC_gc = (0x01<<0), /* Increment */ - EDMA_CH_DIR_MP1_gc = (0x04<<0), /* If Peripheral Ch. (Per ==> Mem), 1-byte 'mask-match' (data: ADDRL, mask: ADDRH), else reserved conf. */ - EDMA_CH_DIR_MP2_gc = (0x05<<0), /* If Peripheral Ch. (Per ==> Mem), 1-byte 'OR-match' (data-1: ADDRL OR data-2: ADDRH), else reserved conf. */ - EDMA_CH_DIR_MP3_gc = (0x06<<0), /* If Peripheral Ch. (Per ==> Mem), 2-byte 'match' (data-1: ADDRL followed by data-2: ADDRH), else reserved conf. */ -} EDMA_CH_DIR_t; - -/* Destination addressing mode */ -typedef enum EDMA_CH_DESTDIR_enum -{ - EDMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ - EDMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ - EDMA_CH_DESTDIR_MP1_gc = (0x04<<0), /* 1-byte 'mask-match' (data: ADDRL, mask: ADDRH) */ - EDMA_CH_DESTDIR_MP2_gc = (0x05<<0), /* 1-byte 'OR-match' (data-1: ADDRL OR data-2: ADDRH) */ - EDMA_CH_DESTDIR_MP3_gc = (0x06<<0), /* 2-byte 'match' (data1: ADDRL followed by data2: ADDRH) */ -} EDMA_CH_DESTDIR_t; - -/* Transfer trigger source */ -typedef enum EDMA_CH_TRIGSRC_enum -{ - EDMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Software triggers only */ - EDMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event CH0 as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event CH1 as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event CH2 as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA CH0 as trigger */ - EDMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA CH0 as trigger */ - EDMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA CH1 as trigger */ - EDMA_CH_TRIGSRC_TCC4_OVF_gc = (0x40<<0), /* TCC4 overflow/underflow as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_TCC4_ERR_gc = (0x41<<0), /* TCC4 error as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_TCC4_CCA_gc = (0x42<<0), /* TCC4 compare or capture channel A as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_TCC4_CCB_gc = (0x43<<0), /* TCC4 compare or capture channel B as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_TCC4_CCC_gc = (0x44<<0), /* TCC4 compare or capture channel C as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_TCC4_CCD_gc = (0x45<<0), /* TCC4 compare or capture channel D as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_TCC5_OVF_gc = (0x46<<0), /* TCC5 overflow/underflow as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_TCC5_ERR_gc = (0x47<<0), /* TCC5 error as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_TCC5_CCA_gc = (0x48<<0), /* TCC5 compare or capture channel A as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_TCC5_CCB_gc = (0x49<<0), /* TCC5 compare or capture channel B as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_SPIC_RXC_gc = (0x4A<<0), /* SPI C transfer complete (SPI Standard Mode) or SPI C receive complete as trigger (SPI Buffer Modes) */ - EDMA_CH_TRIGSRC_SPIC_DRE_gc = (0x4B<<0), /* SPI C transfer complete (SPI Standard Mode) or SPI C data register empty as trigger (SPI Buffer modes) */ - EDMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4C<<0), /* USART C0 receive complete as trigger */ - EDMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4D<<0), /* USART C0 data register empty as trigger */ - EDMA_CH_TRIGSRC_TCD5_OVF_gc = (0x66<<0), /* TCD5 overflow/underflow as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_TCD5_ERR_gc = (0x67<<0), /* TCD5 error as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_TCD5_CCA_gc = (0x68<<0), /* TCD5 compare or capture channel A as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_TCD5_CCB_gc = (0x69<<0), /* TCD5 compare or capture channel B as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6C<<0), /* USART D0 receive complete as trigger */ - EDMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6D<<0), /* USART D0 data register empty as trigger */ -} EDMA_CH_TRIGSRC_t; - -/* Interrupt level */ -typedef enum EDMA_CH_INTLVL_enum -{ - EDMA_CH_INTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ - EDMA_CH_INTLVL_LO_gc = (0x01<<2), /* Low level */ - EDMA_CH_INTLVL_MED_gc = (0x02<<2), /* Medium level */ - EDMA_CH_INTLVL_HI_gc = (0x03<<2), /* High level */ -} EDMA_CH_INTLVL_t; - - -/* --------------------------------------------------------------------------- -EVSYS - Event System --------------------------------------------------------------------------- -*/ - -/* Event System */ -typedef struct EVSYS_struct -{ - register8_t CH0MUX; /* Event Channel 0 Multiplexer */ - register8_t CH1MUX; /* Event Channel 1 Multiplexer */ - register8_t CH2MUX; /* Event Channel 2 Multiplexer */ - register8_t CH3MUX; /* Event Channel 3 Multiplexer */ - register8_t CH4MUX; /* Event Channel 4 Multiplexer */ - register8_t CH5MUX; /* Event Channel 5 Multiplexer */ - register8_t CH6MUX; /* Event Channel 6 Multiplexer */ - register8_t CH7MUX; /* Event Channel 7 Multiplexer */ - register8_t CH0CTRL; /* Channel 0 Control Register */ - register8_t CH1CTRL; /* Channel 1 Control Register */ - register8_t CH2CTRL; /* Channel 2 Control Register */ - register8_t CH3CTRL; /* Channel 3 Control Register */ - register8_t CH4CTRL; /* Channel 4 Control Register */ - register8_t CH5CTRL; /* Channel 5 Control Register */ - register8_t CH6CTRL; /* Channel 6 Control Register */ - register8_t CH7CTRL; /* Channel 7 Control Register */ - register8_t STROBE; /* Event Strobe */ - register8_t DATA; /* Event Data */ - register8_t DFCTRL; /* Digital Filter Control Register */ -} EVSYS_t; - -/* Event Channel multiplexer input selection */ -typedef enum EVSYS_CHMUX_enum -{ - EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ - EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ - EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ - EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ - EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ - EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ - EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ - EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ - EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ - EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ - EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ - EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ - EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ - EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ - EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ - EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ - EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ - EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ - EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ - EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ - EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ - EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ - EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ - EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ - EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ - EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ - EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ - EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ - EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ - EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ - EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ - EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ - EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ - EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ - EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ - EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ - EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ - EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ - EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ - EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ - EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ - EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ - EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ - EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ - EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ - EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ - EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ - EVSYS_CHMUX_XCL_UNF0_gc = (0xB0<<0), /* XCL BTC0 underflow */ - EVSYS_CHMUX_XCL_UNF1_gc = (0xB1<<0), /* XCL BTC1 underflow */ - EVSYS_CHMUX_XCL_CC0_gc = (0xB2<<0), /* XCL BTC0 capture or compare */ - EVSYS_CHMUX_XCL_CC1_gc = (0xB3<<0), /* XCL BTC0 capture or compare */ - EVSYS_CHMUX_XCL_PEC0_gc = (0xB4<<0), /* XCL PEC0 restart */ - EVSYS_CHMUX_XCL_PEC1_gc = (0xB5<<0), /* XCL PEC1 restart */ - EVSYS_CHMUX_XCL_LUT0_gc = (0xB6<<0), /* XCL LUT0 output */ - EVSYS_CHMUX_XCL_LUT1_gc = (0xB7<<0), /* XCL LUT1 output */ - EVSYS_CHMUX_TCC4_OVF_gc = (0xC0<<0), /* Timer/Counter C4 Overflow */ - EVSYS_CHMUX_TCC4_ERR_gc = (0xC1<<0), /* Timer/Counter C4 Error */ - EVSYS_CHMUX_TCC4_CCA_gc = (0xC4<<0), /* Timer/Counter C4 Compare or Capture A */ - EVSYS_CHMUX_TCC4_CCB_gc = (0xC5<<0), /* Timer/Counter C4 Compare or Capture B */ - EVSYS_CHMUX_TCC4_CCC_gc = (0xC6<<0), /* Timer/Counter C4 Compare or Capture C */ - EVSYS_CHMUX_TCC4_CCD_gc = (0xC7<<0), /* Timer/Counter C4 Compare or Capture D */ - EVSYS_CHMUX_TCC5_OVF_gc = (0xC8<<0), /* Timer/Counter C5 Overflow */ - EVSYS_CHMUX_TCC5_ERR_gc = (0xC9<<0), /* Timer/Counter C5 Error */ - EVSYS_CHMUX_TCC5_CCA_gc = (0xCC<<0), /* Timer/Counter C5 Compare or Capture A */ - EVSYS_CHMUX_TCC5_CCB_gc = (0xCD<<0), /* Timer/Counter C5 Compare or Capture B */ - EVSYS_CHMUX_TCD5_OVF_gc = (0xD8<<0), /* Timer/Counter D5 Overflow */ - EVSYS_CHMUX_TCD5_ERR_gc = (0xD9<<0), /* Timer/Counter D5 Error */ - EVSYS_CHMUX_TCD5_CCA_gc = (0xDC<<0), /* Timer/Counter D5 Compare or Capture A */ - EVSYS_CHMUX_TCD5_CCB_gc = (0xDD<<0), /* Timer/Counter D5 Compare or Capture B */ -} EVSYS_CHMUX_t; - -/* Quadrature Decoder Index Recognition Mode */ -typedef enum EVSYS_QDIRM_enum -{ - EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ - EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ - EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ - EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ -} EVSYS_QDIRM_t; - -/* Digital filter coefficient */ -typedef enum EVSYS_DIGFILT_enum -{ - EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ - EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ - EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ - EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ - EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ - EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ - EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ - EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ -} EVSYS_DIGFILT_t; - -/* Prescaler Filter */ -typedef enum EVSYS_PRESCFILT_enum -{ - EVSYS_PRESCFILT_CH04_gc = (0x01<<4), /* Enable prescaler filter for either channel 0 or 4 */ - EVSYS_PRESCFILT_CH15_gc = (0x02<<4), /* Enable prescaler filter for either channel 1 or 5 */ - EVSYS_PRESCFILT_CH26_gc = (0x04<<4), /* Enable prescaler filter for either channel 2 or 6 */ - EVSYS_PRESCFILT_CH37_gc = (0x08<<4), /* Enable prescaler filter for either channel 3 or 7 */ -} EVSYS_PRESCFILT_t; - -/* Prescaler */ -typedef enum EVSYS_PRESCALER_enum -{ - EVSYS_PRESCALER_CLKPER_8_gc = (0x00<<0), /* CLKPER, divide by 8 */ - EVSYS_PRESCALER_CLKPER_64_gc = (0x01<<0), /* CLKPER, divide by 64 */ - EVSYS_PRESCALER_CLKPER_512_gc = (0x02<<0), /* CLKPER, divide by 512 */ - EVSYS_PRESCALER_CLKPER_4096_gc = (0x03<<0), /* CLKPER, divide by 4096 */ - EVSYS_PRESCALER_CLKPER_32768_gc = (0x04<<0), /* CLKPER, divide by 32768 */ -} EVSYS_PRESCALER_t; - - -/* --------------------------------------------------------------------------- -NVM - Non Volatile Memory Controller --------------------------------------------------------------------------- -*/ - -/* Non-volatile Memory Controller */ -typedef struct NVM_struct -{ - register8_t ADDR0; /* Address Register 0 */ - register8_t ADDR1; /* Address Register 1 */ - register8_t ADDR2; /* Address Register 2 */ - register8_t reserved_0x03; - register8_t DATA0; /* Data Register 0 */ - register8_t DATA1; /* Data Register 1 */ - register8_t DATA2; /* Data Register 2 */ - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t CMD; /* Command */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t INTCTRL; /* Interrupt Control */ - register8_t reserved_0x0E; - register8_t STATUS; /* Status */ - register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ -} NVM_t; - -/* NVM Command */ -typedef enum NVM_CMD_enum -{ - NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ - NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ - NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ - NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ - NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ - NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ - NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ - NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ - NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ - NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ - NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ - NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ - NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ - NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ - NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ - NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ - NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ - NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ - NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ - NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ - NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ - NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ - NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ - NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ - NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ - NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ - NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ - NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ - NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ - NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ - NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ - NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ -} NVM_CMD_t; - -/* SPM ready interrupt level */ -typedef enum NVM_SPMLVL_enum -{ - NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ - NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ - NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ - NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ -} NVM_SPMLVL_t; - -/* EEPROM ready interrupt level */ -typedef enum NVM_EELVL_enum -{ - NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ - NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ - NVM_EELVL_HI_gc = (0x03<<0), /* High level */ -} NVM_EELVL_t; - -/* Boot lock bits - boot setcion */ -typedef enum NVM_BLBB_enum -{ - NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ - NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ - NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ - NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -} NVM_BLBB_t; - -/* Boot lock bits - application section */ -typedef enum NVM_BLBA_enum -{ - NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ - NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ - NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ - NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -} NVM_BLBA_t; - -/* Boot lock bits - application table section */ -typedef enum NVM_BLBAT_enum -{ - NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ - NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ - NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ - NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -} NVM_BLBAT_t; - -/* Lock bits */ -typedef enum NVM_LB_enum -{ - NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ - NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ - NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -} NVM_LB_t; - - -/* --------------------------------------------------------------------------- -ADC - Analog/Digital Converter --------------------------------------------------------------------------- -*/ - -/* ADC Channel */ -typedef struct ADC_CH_struct -{ - register8_t CTRL; /* Control Register */ - register8_t MUXCTRL; /* MUX Control */ - register8_t INTCTRL; /* Channel Interrupt Control Register */ - register8_t INTFLAGS; /* Interrupt Flags */ - _WORDREGISTER(RES); /* Channel Result */ - register8_t SCAN; /* Input Channel Scan */ - register8_t CORRCTRL; /* Correction Control Register */ - register8_t OFFSETCORR0; /* Offset Correction Register 0 */ - register8_t OFFSETCORR1; /* Offset Correction Register 1 */ - register8_t GAINCORR0; /* Gain Correction Register 0 */ - register8_t GAINCORR1; /* Gain Correction Register 1 */ - register8_t AVGCTRL; /* Average Control Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; -} ADC_CH_t; - - -/* Analog-to-Digital Converter */ -typedef struct ADC_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t REFCTRL; /* Reference Control */ - register8_t EVCTRL; /* Event Control */ - register8_t PRESCALER; /* Clock Prescaler */ - register8_t reserved_0x05; - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t TEMP; /* Temporary Register */ - register8_t SAMPCTRL; /* ADC Sampling Time Control Register */ - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - _WORDREGISTER(CAL); /* Calibration Value */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - _WORDREGISTER(CH0RES); /* Channel 0 Result */ - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - _WORDREGISTER(CMP); /* Compare Value */ - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - ADC_CH_t CH0; /* ADC Channel 0 */ -} ADC_t; - -/* Current Limitation */ -typedef enum ADC_CURRLIMIT_enum -{ - ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ - ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 250ksps max sampling rate */ - ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ - ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 50ksps max sampling rate */ -} ADC_CURRLIMIT_t; - -/* Conversion result resolution */ -typedef enum ADC_RESOLUTION_enum -{ - ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ - ADC_RESOLUTION_MT12BIT_gc = (0x01<<1), /* More than 12-bit (oversapling) right-adjusted result */ - ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ - ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ -} ADC_RESOLUTION_t; - -/* Voltage reference selection */ -typedef enum ADC_REFSEL_enum -{ - ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ - ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ - ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ - ADC_REFSEL_AREFD_gc = (0x03<<4), /* External reference on PORT D */ - ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ -} ADC_REFSEL_t; - -/* Event channel input selection */ -typedef enum ADC_EVSEL_enum -{ - ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */ - ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */ - ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */ - ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */ - ADC_EVSEL_4_gc = (0x04<<3), /* Event Channel 4 */ - ADC_EVSEL_5_gc = (0x05<<3), /* Event Channel 5 */ - ADC_EVSEL_6_gc = (0x06<<3), /* Event Channel 6 */ - ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ -} ADC_EVSEL_t; - -/* Event action selection */ -typedef enum ADC_EVACT_enum -{ - ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ - ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel conversion */ - ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ -} ADC_EVACT_t; - -/* Clock prescaler */ -typedef enum ADC_PRESCALER_enum -{ - ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ - ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ - ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ - ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ - ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ - ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ - ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ - ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ -} ADC_PRESCALER_t; - -/* Gain factor */ -typedef enum ADC_CH_GAIN_enum -{ - ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ - ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ - ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ - ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ - ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ - ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ - ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ - ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ -} ADC_CH_GAIN_t; - -/* Input mode */ -typedef enum ADC_CH_INPUTMODE_enum -{ - ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ - ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ - ADC_CH_INPUTMODE_DIFFWGAINL_gc = (0x02<<0), /* Differential input, gain with 4 LSB pins selection */ - ADC_CH_INPUTMODE_DIFFWGAINH_gc = (0x03<<0), /* Differential input, gain with 4 MSB pins selection */ -} ADC_CH_INPUTMODE_t; - -/* Positive input multiplexer selection */ -typedef enum ADC_CH_MUXPOS_enum -{ - ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ - ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ - ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ - ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ - ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ - ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ - ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ - ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ - ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ - ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ - ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ - ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ - ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ - ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ - ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ - ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ -} ADC_CH_MUXPOS_t; - -/* Internal input multiplexer selections */ -typedef enum ADC_CH_MUXINT_enum -{ - ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ - ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ - ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 Scaled VCC */ - ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC Output */ -} ADC_CH_MUXINT_t; - -/* Negative input multiplexer selection when gain on 4 LSB pins */ -typedef enum ADC_CH_MUXNEGL_enum -{ - ADC_CH_MUXNEGL_PIN0_gc = (0x00<<0), /* Input pin 0 */ - ADC_CH_MUXNEGL_PIN1_gc = (0x01<<0), /* Input pin 1 */ - ADC_CH_MUXNEGL_PIN2_gc = (0x02<<0), /* Input pin 2 */ - ADC_CH_MUXNEGL_PIN3_gc = (0x03<<0), /* Input pin 3 */ - ADC_CH_MUXNEGL_GND_gc = (0x05<<0), /* PAD ground */ - ADC_CH_MUXNEGL_INTGND_gc = (0x07<<0), /* Internal ground */ -} ADC_CH_MUXNEGL_t; - -/* Negative input multiplexer selection when gain on 4 MSB pins */ -typedef enum ADC_CH_MUXNEGH_enum -{ - ADC_CH_MUXNEGH_PIN4_gc = (0x00<<0), /* Input pin 4 */ - ADC_CH_MUXNEGH_PIN5_gc = (0x01<<0), /* Input pin 5 */ - ADC_CH_MUXNEGH_PIN6_gc = (0x02<<0), /* Input pin 6 */ - ADC_CH_MUXNEGH_PIN7_gc = (0x03<<0), /* Input pin 7 */ - ADC_CH_MUXNEGH_GND_gc = (0x05<<0), /* PAD ground */ -} ADC_CH_MUXNEGH_t; - -/* Negative input multiplexer selection */ -typedef enum ADC_CH_MUXNEG_enum -{ - ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ -} ADC_CH_MUXNEG_t; - -/* Interupt mode */ -typedef enum ADC_CH_INTMODE_enum -{ - ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ - ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ - ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ -} ADC_CH_INTMODE_t; - -/* Interrupt level */ -typedef enum ADC_CH_INTLVL_enum -{ - ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ - ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ - ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ -} ADC_CH_INTLVL_t; - -/* Averaged Number of Samples */ -typedef enum ADC_SAMPNUM_enum -{ - ADC_SAMPNUM_1X_gc = (0x00<<0), /* 1 Sample */ - ADC_SAMPNUM_2X_gc = (0x01<<0), /* 2 Samples */ - ADC_SAMPNUM_4X_gc = (0x02<<0), /* 4 Samples */ - ADC_SAMPNUM_8X_gc = (0x03<<0), /* 8 Samples */ - ADC_SAMPNUM_16X_gc = (0x04<<0), /* 16 Samples */ - ADC_SAMPNUM_32X_gc = (0x05<<0), /* 32 Samples */ - ADC_SAMPNUM_64X_gc = (0x06<<0), /* 64 Samples */ - ADC_SAMPNUM_128X_gc = (0x07<<0), /* 128 Samples */ - ADC_SAMPNUM_256X_gc = (0x08<<0), /* 256 Samples */ - ADC_SAMPNUM_512X_gc = (0x09<<0), /* 512 Samples */ - ADC_SAMPNUM_1024X_gc = (0x0A<<0), /* 1024 Samples */ -} ADC_SAMPNUM_t; - - -/* --------------------------------------------------------------------------- -DAC - Digital/Analog Converter --------------------------------------------------------------------------- -*/ - -/* Digital-to-Analog Converter */ -typedef struct DAC_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t EVCTRL; /* Event Input Control */ - register8_t reserved_0x04; - register8_t STATUS; /* Status */ - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t CH0GAINCAL; /* Gain Calibration */ - register8_t CH0OFFSETCAL; /* Offset Calibration */ - register8_t CH1GAINCAL; /* Gain Calibration */ - register8_t CH1OFFSETCAL; /* Offset Calibration */ - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - _WORDREGISTER(CH0DATA); /* Channel 0 Data */ - _WORDREGISTER(CH1DATA); /* Channel 1 Data */ -} DAC_t; - -/* Output channel selection */ -typedef enum DAC_CHSEL_enum -{ - DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel 0 only) */ - DAC_CHSEL_SINGLE1_gc = (0x01<<5), /* Single channel operation (Channel 1 only) */ - DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (Channel 0 and channel 1) */ -} DAC_CHSEL_t; - -/* Reference voltage selection */ -typedef enum DAC_REFSEL_enum -{ - DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ - DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ - DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ - DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ -} DAC_REFSEL_t; - -/* Event channel selection */ -typedef enum DAC_EVSEL_enum -{ - DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ - DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ - DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ - DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ - DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ - DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ - DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ - DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ -} DAC_EVSEL_t; - - -/* --------------------------------------------------------------------------- -AC - Analog Comparator --------------------------------------------------------------------------- -*/ - -/* Analog Comparator */ -typedef struct AC_struct -{ - register8_t AC0CTRL; /* Analog Comparator 0 Control */ - register8_t AC1CTRL; /* Analog Comparator 1 Control */ - register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ - register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t WINCTRL; /* Window Mode Control */ - register8_t STATUS; /* Status */ - register8_t CURRCTRL; /* Current Source Control Register */ - register8_t CURRCALIB; /* Current Source Calibration Register */ -} AC_t; - -/* Interrupt mode */ -typedef enum AC_INTMODE_enum -{ - AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ - AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ - AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ -} AC_INTMODE_t; - -/* Interrupt level */ -typedef enum AC_INTLVL_enum -{ - AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ - AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ - AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ - AC_INTLVL_HI_gc = (0x03<<4), /* High level */ -} AC_INTLVL_t; - -/* Hysteresis mode selection */ -typedef enum AC_HYSMODE_enum -{ - AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ - AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ - AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ -} AC_HYSMODE_t; - -/* Positive input multiplexer selection */ -typedef enum AC_MUXPOS_enum -{ - AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ - AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ - AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ - AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ - AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ - AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ - AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ - AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ -} AC_MUXPOS_t; - -/* Negative input multiplexer selection */ -typedef enum AC_MUXNEG_enum -{ - AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ - AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ - AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ - AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ - AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ - AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ - AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ - AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ -} AC_MUXNEG_t; - -/* Windows interrupt mode */ -typedef enum AC_WINTMODE_enum -{ - AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ - AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ - AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ - AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ -} AC_WINTMODE_t; - -/* Window interrupt level */ -typedef enum AC_WINTLVL_enum -{ - AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ - AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ - AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ -} AC_WINTLVL_t; - -/* Window mode state */ -typedef enum AC_WSTATE_enum -{ - AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ - AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ - AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ -} AC_WSTATE_t; - - -/* --------------------------------------------------------------------------- -RTC - Real-Time Clounter --------------------------------------------------------------------------- -*/ - -/* Real-Time Counter */ -typedef struct RTC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t TEMP; /* Temporary register */ - register8_t reserved_0x05; - register8_t CALIB; /* Calibration Register */ - register8_t reserved_0x07; - _WORDREGISTER(CNT); /* Count Register */ - _WORDREGISTER(PER); /* Period Register */ - _WORDREGISTER(COMP); /* Compare Register */ -} RTC_t; - -/* Prescaler Factor */ -typedef enum RTC_PRESCALER_enum -{ - RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ - RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ - RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ - RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ - RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ - RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ - RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ - RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ -} RTC_PRESCALER_t; - -/* Compare Interrupt level */ -typedef enum RTC_COMPINTLVL_enum -{ - RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ - RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ -} RTC_COMPINTLVL_t; - -/* Overflow Interrupt level */ -typedef enum RTC_OVFINTLVL_enum -{ - RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} RTC_OVFINTLVL_t; - - -/* --------------------------------------------------------------------------- -XCL - XMEGA Custom Logic --------------------------------------------------------------------------- -*/ - -/* XMEGA Custom Logic */ -typedef struct XCL_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t CTRLF; /* Control Register F */ - register8_t CTRLG; /* Control Register G */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t PLC; /* Peripheral Lenght Control Register */ - register8_t CNTL; /* Counter Register Low */ - register8_t CNTH; /* Counter Register High */ - register8_t CMPL; /* Compare Register Low */ - register8_t CMPH; /* Compare Register High */ - register8_t PERCAPTL; /* Period or Capture Register Low */ - register8_t PERCAPTH; /* Period or Capture Register High */ -} XCL_t; - -/* LUT0 Output Enable */ -typedef enum XCL_LUTOUTEN_enum -{ - XCL_LUTOUTEN_DISABLE_gc = (0x00<<6), /* LUT0 output disabled */ - XCL_LUTOUTEN_PIN0_gc = (0x01<<6), /* LUT0 Output to pin 0 */ - XCL_LUTOUTEN_PIN4_gc = (0x02<<6), /* LUT0 Output to pin 4 */ -} XCL_LUTOUTEN_t; - -/* Port Selection */ -typedef enum XCL_PORTSEL_enum -{ - XCL_PORTSEL_PC_gc = (0x00<<4), /* Port C for LUT or USARTC0 for PEC */ - XCL_PORTSEL_PD_gc = (0x01<<4), /* Port D for LUT or USARTD0 for PEC */ -} XCL_PORTSEL_t; - -/* LUT Configuration */ -typedef enum XCL_LUTCONF_enum -{ - XCL_LUTCONF_2LUT2IN_gc = (0x00<<0), /* 2-Input two LUT */ - XCL_LUTCONF_2LUT1IN_gc = (0x01<<0), /* Two LUT with duplicated input */ - XCL_LUTCONF_2LUT3IN_gc = (0x02<<0), /* Two LUT with one common input */ - XCL_LUTCONF_1LUT3IN_gc = (0x03<<0), /* 3-Input LUT */ - XCL_LUTCONF_MUX_gc = (0x04<<0), /* One LUT Mux */ - XCL_LUTCONF_DLATCH_gc = (0x05<<0), /* One D-Latch LUT */ - XCL_LUTCONF_RSLATCH_gc = (0x06<<0), /* One RS-Latch LUT */ - XCL_LUTCONF_DFF_gc = (0x07<<0), /* One DFF LUT */ -} XCL_LUTCONF_t; - -/* Input Selection */ -typedef enum XCL_INSEL_enum -{ - XCL_INSEL_EVSYS_gc = (0x00<<6), /* Event system selected as source */ - XCL_INSEL_XCL_gc = (0x01<<6), /* XCL selected as source */ - XCL_INSEL_PINL_gc = (0x02<<6), /* LSB port pin selected as source */ - XCL_INSEL_PINH_gc = (0x03<<6), /* MSB port pin selected as source */ -} XCL_INSEL_t; - -/* Delay Configuration on LUT */ -typedef enum XCL_DLYCONF_enum -{ - XCL_DLYCONF_DISABLE_gc = (0x00<<2), /* Delay element disabled */ - XCL_DLYCONF_IN_gc = (0x01<<2), /* Delay enabled on LUT input */ - XCL_DLYCONF_OUT_gc = (0x02<<2), /* Delay enabled on LUT output */ -} XCL_DLYCONF_t; - -/* Delay Selection */ -typedef enum XCL_DLYSEL_enum -{ - XCL_DLYSEL_DLY11_gc = (0x00<<4), /* One cycle delay for each LUT1 and LUT0 */ - XCL_DLYSEL_DLY12_gc = (0x01<<4), /* One cycle delay for LUT1 and two cycles for LUT0 */ - XCL_DLYSEL_DLY21_gc = (0x02<<4), /* Two cycles delay for LUT1 and one cycle for LUT0 */ - XCL_DLYSEL_DLY22_gc = (0x03<<4), /* Two cycle delays for each LUT1 and LUT0 */ -} XCL_DLYSEL_t; - -/* Clock Selection */ -typedef enum XCL_CLKSEL_enum -{ - XCL_CLKSEL_OFF_gc = (0x00<<0), /* OFF */ - XCL_CLKSEL_DIV1_gc = (0x01<<0), /* Prescaler clk */ - XCL_CLKSEL_DIV2_gc = (0x02<<0), /* Prescaler clk/2 */ - XCL_CLKSEL_DIV4_gc = (0x03<<0), /* Prescaler clk/4 */ - XCL_CLKSEL_DIV8_gc = (0x04<<0), /* Prescaler clk/8 */ - XCL_CLKSEL_DIV64_gc = (0x05<<0), /* Prescaler clk/64 */ - XCL_CLKSEL_DIV256_gc = (0x06<<0), /* Prescaler clk/256 */ - XCL_CLKSEL_DIV1024_gc = (0x07<<0), /* Prescaler clk/1024 */ - XCL_CLKSEL_EVCH0_gc = (0x08<<0), /* Event channel 0 */ - XCL_CLKSEL_EVCH1_gc = (0x09<<0), /* Event channel 1 */ - XCL_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event channel 2 */ - XCL_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event channel 3 */ - XCL_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event channel 4 */ - XCL_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event channel 5 */ - XCL_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event channel 6 */ - XCL_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event channel 7 */ -} XCL_CLKSEL_t; - -/* Timer/Counter Command Selection */ -typedef enum XCL_CMDSEL_enum -{ - XCL_CMDSEL_NONE_gc = (0x00<<7), /* None */ - XCL_CMDSEL_RESTART_gc = (0x01<<7), /* Force restart */ -} XCL_CMDSEL_t; - -/* Timer/Counter Selection */ -typedef enum XCL_TCSEL_enum -{ - XCL_TCSEL_TC16_gc = (0x00<<4), /* 16-bit timer/counter */ - XCL_TCSEL_BTC0_gc = (0x01<<4), /* One 8-bit timer/counter */ - XCL_TCSEL_BTC01_gc = (0x02<<4), /* Two 8-bit timer/counters */ - XCL_TCSEL_BTC0PEC1_gc = (0x03<<4), /* One 8-bit timer/counter and one 8-bit peripheral counter */ - XCL_TCSEL_PEC0BTC1_gc = (0x04<<4), /* One 8-bit timer/counter and one 8-bit peripheral counter */ - XCL_TCSEL_PEC01_gc = (0x05<<4), /* Two 8-bit peripheral counters */ - XCL_TCSEL_BTC0PEC2_gc = (0x06<<4), /* One 8-bit timer/counter and two 4-bit peripheral counters */ -} XCL_TCSEL_t; - -/* Timer/Counter Mode */ -typedef enum XCL_TCMODE_enum -{ - XCL_TCMODE_NORMAL_gc = (0x00<<0), /* Normal mode with compare/period */ - XCL_TCMODE_CAPT_gc = (0x01<<0), /* Capture mode */ - XCL_TCMODE_PWM_gc = (0x02<<0), /* Single Slope PWM */ -} XCL_TCMODE_t; - -/* Compare Output Value Timer */ -typedef enum XCL_CMPEN_enum -{ - XCL_CMPEN_CLEAR_gc = (0x00<<5), /* Clear WG Output */ - XCL_CMPEN_SET_gc = (0x01<<5), /* Set WG Output */ -} XCL_CMPEN_t; - -/* Command Enable */ -typedef enum XCL_CMDEN_enum -{ - XCL_CMDEN_DISABLE_gc = (0x00<<6), /* Command Ignored */ - XCL_CMDEN_CMD0_gc = (0x01<<6), /* Command valid for timer/counter 0 */ - XCL_CMDEN_CMD1_gc = (0x02<<6), /* Command valid for timer/counter 1 */ - XCL_CMDEN_CMD01_gc = (0x03<<6), /* Command valid for both timer/counter 0 and 1 */ -} XCL_CMDEN_t; - -/* Timer/Counter Event Source Selection */ -typedef enum XCL_EVSRC_enum -{ - XCL_EVSRC_EVCH0_gc = (0x00<<0), /* Event channel 0 */ - XCL_EVSRC_EVCH1_gc = (0x01<<0), /* Event channel 1 */ - XCL_EVSRC_EVCH2_gc = (0x02<<0), /* Event channel 2 */ - XCL_EVSRC_EVCH3_gc = (0x03<<0), /* Event channel 3 */ - XCL_EVSRC_EVCH4_gc = (0x04<<0), /* Event channel 4 */ - XCL_EVSRC_EVCH5_gc = (0x05<<0), /* Event channel 5 */ - XCL_EVSRC_EVCH6_gc = (0x06<<0), /* Event channel 6 */ - XCL_EVSRC_EVCH7_gc = (0x07<<0), /* Event channel 7 */ -} XCL_EVSRC_t; - -/* Timer/Counter Event Action Selection */ -typedef enum XCL_EVACT_enum -{ - XCL_EVACT_INPUT_gc = (0x00<<5), /* Input Capture */ - XCL_EVACT_FREQ_gc = (0x01<<5), /* Frequency Capture */ - XCL_EVACT_PW_gc = (0x02<<5), /* Pulse Width Capture */ - XCL_EVACT_RESTART_gc = (0x03<<5), /* Restart timer/counter */ -} XCL_EVACT_t; - -/* Underflow Interrupt level */ -typedef enum XCL_UNF_INTLVL_enum -{ - XCL_UNF_INTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - XCL_UNF_INTLVL_LO_gc = (0x01<<2), /* Low Level */ - XCL_UNF_INTLVL_MED_gc = (0x02<<2), /* Medium Level */ - XCL_UNF_INTLVL_HI_gc = (0x03<<2), /* High Level */ -} XCL_UNF_INTLVL_t; - -/* Compare/Capture Interrupt level */ -typedef enum XCL_CC_INTLVL_enum -{ - XCL_CC_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - XCL_CC_INTLVL_LO_gc = (0x01<<0), /* Low Level */ - XCL_CC_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ - XCL_CC_INTLVL_HI_gc = (0x03<<0), /* High Level */ -} XCL_CC_INTLVL_t; - - -/* --------------------------------------------------------------------------- -TWI - Two-Wire Interface --------------------------------------------------------------------------- -*/ - -/* */ -typedef struct TWI_MASTER_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t STATUS; /* Status Register */ - register8_t BAUD; /* Baurd Rate Control Register */ - register8_t ADDR; /* Address Register */ - register8_t DATA; /* Data Register */ -} TWI_MASTER_t; - - -/* */ -typedef struct TWI_SLAVE_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t STATUS; /* Status Register */ - register8_t ADDR; /* Address Register */ - register8_t DATA; /* Data Register */ - register8_t ADDRMASK; /* Address Mask Register */ -} TWI_SLAVE_t; - - -/* */ -typedef struct TWI_TIMEOUT_struct -{ - register8_t TOS; /* Timeout Status Register */ - register8_t TOCONF; /* Timeout Configuration Register */ -} TWI_TIMEOUT_t; - - -/* Two-Wire Interface */ -typedef struct TWI_struct -{ - register8_t CTRL; /* TWI Common Control Register */ - TWI_MASTER_t MASTER; /* TWI master module */ - TWI_SLAVE_t SLAVE; /* TWI slave module */ - TWI_TIMEOUT_t TIMEOUT; /* TWI SMBUS timeout module */ -} TWI_t; - -/* SDA Hold Time */ -typedef enum TWI_SDAHOLD_enum -{ - TWI_SDAHOLD_OFF_gc = (0x00<<4), /* SDA Hold Time off */ - TWI_SDAHOLD_50NS_gc = (0x01<<4), /* SDA Hold Time 50 ns */ - TWI_SDAHOLD_300NS_gc = (0x02<<4), /* SDA Hold Time 300 ns */ - TWI_SDAHOLD_400NS_gc = (0x03<<4), /* SDA Hold Time 400 ns */ -} TWI_SDAHOLD_t; - -/* Master Interrupt Level */ -typedef enum TWI_MASTER_INTLVL_enum -{ - TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ - TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ -} TWI_MASTER_INTLVL_t; - -/* Inactive Timeout */ -typedef enum TWI_MASTER_TIMEOUT_enum -{ - TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ - TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ - TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ - TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ -} TWI_MASTER_TIMEOUT_t; - -/* Master Command */ -typedef enum TWI_MASTER_CMD_enum -{ - TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ - TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ - TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ -} TWI_MASTER_CMD_t; - -/* Master Bus State */ -typedef enum TWI_MASTER_BUSSTATE_enum -{ - TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ - TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ - TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ - TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ -} TWI_MASTER_BUSSTATE_t; - -/* Slave Interrupt Level */ -typedef enum TWI_SLAVE_INTLVL_enum -{ - TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ - TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ -} TWI_SLAVE_INTLVL_t; - -/* Slave Command */ -typedef enum TWI_SLAVE_CMD_enum -{ - TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ - TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ -} TWI_SLAVE_CMD_t; - -/* Master Timeout */ -typedef enum TWI_MASTER_TTIMEOUT_enum -{ - TWI_MASTER_TTIMEOUT_25MS_gc = (0x00<<0), /* 25 Milliseconds */ - TWI_MASTER_TTIMEOUT_24MS_gc = (0x01<<0), /* 24 Milliseconds */ - TWI_MASTER_TTIMEOUT_23MS_gc = (0x02<<0), /* 23 Milliseconds */ - TWI_MASTER_TTIMEOUT_22MS_gc = (0x03<<0), /* 22 Milliseconds */ - TWI_MASTER_TTIMEOUT_26MS_gc = (0x04<<0), /* 26 Milliseconds */ - TWI_MASTER_TTIMEOUT_27MS_gc = (0x05<<0), /* 27 Milliseconds */ - TWI_MASTER_TTIMEOUT_28MS_gc = (0x06<<0), /* 28 Milliseconds */ - TWI_MASTER_TTIMEOUT_29MS_gc = (0x07<<0), /* 29 Milliseconds */ -} TWI_MASTER_TTIMEOUT_t; - -/* Slave Ttimeout */ -typedef enum TWI_SLAVE_TTIMEOUT_enum -{ - TWI_SLAVE_TTIMEOUT_25MS_gc = (0x00<<5), /* 25 Milliseconds */ - TWI_SLAVE_TTIMEOUT_24MS_gc = (0x01<<5), /* 24 Milliseconds */ - TWI_SLAVE_TTIMEOUT_23MS_gc = (0x02<<5), /* 23 Milliseconds */ - TWI_SLAVE_TTIMEOUT_22MS_gc = (0x03<<5), /* 22 Milliseconds */ - TWI_SLAVE_TTIMEOUT_26MS_gc = (0x04<<5), /* 26 Milliseconds */ - TWI_SLAVE_TTIMEOUT_27MS_gc = (0x05<<5), /* 27 Milliseconds */ - TWI_SLAVE_TTIMEOUT_28MS_gc = (0x06<<5), /* 28 Milliseconds */ - TWI_SLAVE_TTIMEOUT_29MS_gc = (0x07<<5), /* 29 Milliseconds */ -} TWI_SLAVE_TTIMEOUT_t; - -/* Master/Slave Extend Timeout */ -typedef enum TWI_MASTER_TMSEXT_enum -{ - TWI_MASTER_TMSEXT_10MS25MS_gc = (0x00<<3), /* Tmext 10ms Tsext 25ms */ - TWI_MASTER_TMSEXT_9MS24MS_gc = (0x01<<3), /* Tmext 9ms Tsext 24ms */ - TWI_MASTER_TMSEXT_11MS26MS_gc = (0x02<<3), /* Tmext 11ms Tsext 26ms */ - TWI_MASTER_TMSEXT_12MS27MS_gc = (0x03<<3), /* Tmext 12ms Tsext 27ms */ -} TWI_MASTER_TMSEXT_t; - - -/* --------------------------------------------------------------------------- -PORT - Port Configuration --------------------------------------------------------------------------- -*/ - -/* I/O Ports */ -typedef struct PORT_struct -{ - register8_t DIR; /* I/O Port Data Direction */ - register8_t DIRSET; /* I/O Port Data Direction Set */ - register8_t DIRCLR; /* I/O Port Data Direction Clear */ - register8_t DIRTGL; /* I/O Port Data Direction Toggle */ - register8_t OUT; /* I/O Port Output */ - register8_t OUTSET; /* I/O Port Output Set */ - register8_t OUTCLR; /* I/O Port Output Clear */ - register8_t OUTTGL; /* I/O Port Output Toggle */ - register8_t IN; /* I/O port Input */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INTMASK; /* Port Interrupt Mask */ - register8_t reserved_0x0B; - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t REMAP; /* Pin Remap Register */ - register8_t reserved_0x0F; - register8_t PIN0CTRL; /* Pin 0 Control Register */ - register8_t PIN1CTRL; /* Pin 1 Control Register */ - register8_t PIN2CTRL; /* Pin 2 Control Register */ - register8_t PIN3CTRL; /* Pin 3 Control Register */ - register8_t PIN4CTRL; /* Pin 4 Control Register */ - register8_t PIN5CTRL; /* Pin 5 Control Register */ - register8_t PIN6CTRL; /* Pin 6 Control Register */ - register8_t PIN7CTRL; /* Pin 7 Control Register */ -} PORT_t; - -/* Port Interrupt Level */ -typedef enum PORT_INTLVL_enum -{ - PORT_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - PORT_INTLVL_LO_gc = (0x01<<0), /* Low Level */ - PORT_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ - PORT_INTLVL_HI_gc = (0x03<<0), /* High Level */ -} PORT_INTLVL_t; - -/* Output/Pull Configuration */ -typedef enum PORT_OPC_enum -{ - PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ - PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ - PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ - PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ - PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ - PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ - PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ - PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ -} PORT_OPC_t; - -/* Input/Sense Configuration */ -typedef enum PORT_ISC_enum -{ - PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ - PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ - PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ - PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ - PORT_ISC_FORCE_ENABLE_gc = (0x06<<0), /* Digital Input Buffer Forced Enable */ - PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ -} PORT_ISC_t; - - -/* --------------------------------------------------------------------------- -TC - 16-bit Timer/Counter With PWM --------------------------------------------------------------------------- -*/ - -/* 16-bit Timer/Counter 4 */ -typedef struct TC4_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t CTRLF; /* Control Register F */ - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G Set */ - register8_t CTRLHCLR; /* Control Register H Clear */ - register8_t CTRLHSET; /* Control Register H Set */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - _WORDREGISTER(CNT); /* Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CCA); /* Compare or Capture A */ - _WORDREGISTER(CCB); /* Compare or Capture B */ - _WORDREGISTER(CCC); /* Compare or Capture C */ - _WORDREGISTER(CCD); /* Compare or Capture D */ - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - _WORDREGISTER(PERBUF); /* Period Buffer */ - _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ - _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ - _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ - _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ -} TC4_t; - - -/* 16-bit Timer/Counter 5 */ -typedef struct TC5_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t CTRLF; /* Control Register F */ - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G Set */ - register8_t CTRLHCLR; /* Control Register H Clear */ - register8_t CTRLHSET; /* Control Register H Set */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - _WORDREGISTER(CNT); /* Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CCA); /* Compare or Capture A */ - _WORDREGISTER(CCB); /* Compare or Capture B */ - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t reserved_0x2E; - register8_t reserved_0x2F; - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - _WORDREGISTER(PERBUF); /* Period Buffer */ - _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ - _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ - register8_t reserved_0x3C; - register8_t reserved_0x3D; - register8_t reserved_0x3E; - register8_t reserved_0x3F; -} TC5_t; - -/* Clock Selection */ -typedef enum TC45_CLKSEL_enum -{ - TC45_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ - TC45_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ - TC45_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ - TC45_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ - TC45_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ - TC45_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ - TC45_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ - TC45_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ - TC45_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ - TC45_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ - TC45_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC45_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ - TC45_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ - TC45_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ - TC45_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ - TC45_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ -} TC45_CLKSEL_t; - -/* Byte Mode */ -typedef enum TC45_BYTEM_enum -{ - TC45_BYTEM_NORMAL_gc = (0x00<<6), /* 16-bit mode */ - TC45_BYTEM_BYTEMODE_gc = (0x01<<6), /* Timer/Counter Operating in Byte Mode Only */ -} TC45_BYTEM_t; - -/* Circular Enable Mode */ -typedef enum TC45_CIRCEN_enum -{ - TC45_CIRCEN_DISABLE_gc = (0x00<<4), /* Circular Buffer Disabled */ - TC45_CIRCEN_PER_gc = (0x01<<4), /* Circular Buffer Enabled on PER/PERBUF */ - TC45_CIRCEN_CCA_gc = (0x02<<4), /* Circular Buffer Enabled on CCA/CCABUF */ - TC45_CIRCEN_BOTH_gc = (0x03<<4), /* Circular Buffer Enabled on All Buffered Registers */ -} TC45_CIRCEN_t; - -/* Waveform Generation Mode */ -typedef enum TC45_WGMODE_enum -{ - TC45_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ - TC45_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ - TC45_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ - TC45_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ - TC45_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Both */ - TC45_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ -} TC45_WGMODE_t; - -/* Event Action */ -typedef enum TC45_EVACT_enum -{ - TC45_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ - TC45_EVACT_FMODE1_gc = (0x01<<5), /* Fault Mode 1 capture */ - TC45_EVACT_FMODE2_gc = (0x02<<5), /* Fault Mode 2 capture */ - TC45_EVACT_UPDOWN_gc = (0x03<<5), /* Up/down count */ - TC45_EVACT_QDEC_gc = (0x04<<5), /* Quadrature decode */ - TC45_EVACT_RESTART_gc = (0x05<<5), /* Restart */ - TC45_EVACT_PWF_gc = (0x06<<5), /* Pulse-width Capture */ -} TC45_EVACT_t; - -/* Event Selection */ -typedef enum TC45_EVSEL_enum -{ - TC45_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ - TC45_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ - TC45_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ - TC45_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC45_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ - TC45_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ - TC45_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ - TC45_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ - TC45_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ -} TC45_EVSEL_t; - -/* Compare or Capture Channel A Mode */ -typedef enum TC45_CCAMODE_enum -{ - TC45_CCAMODE_DISABLE_gc = (0x00<<0), /* Channel Disabled */ - TC45_CCAMODE_COMP_gc = (0x01<<0), /* Ouput Compare enabled */ - TC45_CCAMODE_CAPT_gc = (0x02<<0), /* Input Capture enabled */ - TC45_CCAMODE_BOTHCC_gc = (0x03<<0), /* Both Compare and Capture enabled */ -} TC45_CCAMODE_t; - -/* Compare or Capture Channel B Mode */ -typedef enum TC45_CCBMODE_enum -{ - TC45_CCBMODE_DISABLE_gc = (0x00<<2), /* Channel Disabled */ - TC45_CCBMODE_COMP_gc = (0x01<<2), /* Ouput Compare enabled */ - TC45_CCBMODE_CAPT_gc = (0x02<<2), /* Input Capture enabled */ - TC45_CCBMODE_BOTHCC_gc = (0x03<<2), /* Both Compare and Capture enabled */ -} TC45_CCBMODE_t; - -/* Compare or Capture Channel C Mode */ -typedef enum TC45_CCCMODE_enum -{ - TC45_CCCMODE_DISABLE_gc = (0x00<<4), /* Channel Disabled */ - TC45_CCCMODE_COMP_gc = (0x01<<4), /* Ouput Compare enabled */ - TC45_CCCMODE_CAPT_gc = (0x02<<4), /* Input Capture enabled */ - TC45_CCCMODE_BOTHCC_gc = (0x03<<4), /* Both Compare and Capture enabled */ -} TC45_CCCMODE_t; - -/* Compare or Capture Channel D Mode */ -typedef enum TC45_CCDMODE_enum -{ - TC45_CCDMODE_DISABLE_gc = (0x00<<6), /* Channel Disabled */ - TC45_CCDMODE_COMP_gc = (0x01<<6), /* Ouput Compare enabled */ - TC45_CCDMODE_CAPT_gc = (0x02<<6), /* Input Capture enabled */ - TC45_CCDMODE_BOTHCC_gc = (0x03<<6), /* Both Compare and Capture enabled */ -} TC45_CCDMODE_t; - -/* Compare or Capture Low Channel A Mode */ -typedef enum TC45_LCCAMODE_enum -{ - TC45_LCCAMODE_DISABLE_gc = (0x00<<0), /* Channel Disabled */ - TC45_LCCAMODE_COMP_gc = (0x01<<0), /* Ouput Compare enabled */ - TC45_LCCAMODE_CAPT_gc = (0x02<<0), /* Input Capture enabled */ - TC45_LCCAMODE_BOTHCC_gc = (0x03<<0), /* Both Compare and Capture enabled */ -} TC45_LCCAMODE_t; - -/* Compare or Capture Low Channel B Mode */ -typedef enum TC45_LCCBMODE_enum -{ - TC45_LCCBMODE_DISABLE_gc = (0x00<<2), /* Channel Disabled */ - TC45_LCCBMODE_COMP_gc = (0x01<<2), /* Ouput Compare enabled */ - TC45_LCCBMODE_CAPT_gc = (0x02<<2), /* Input Capture enabled */ - TC45_LCCBMODE_BOTHCC_gc = (0x03<<2), /* Both Compare and Capture enabled */ -} TC45_LCCBMODE_t; - -/* Compare or Capture Low Channel C Mode */ -typedef enum TC45_LCCCMODE_enum -{ - TC45_LCCCMODE_DISABLE_gc = (0x00<<4), /* Channel Disabled */ - TC45_LCCCMODE_COMP_gc = (0x01<<4), /* Ouput Compare enabled */ - TC45_LCCCMODE_CAPT_gc = (0x02<<4), /* Input Capture enabled */ - TC45_LCCCMODE_BOTHCC_gc = (0x03<<4), /* Both Compare and Capture enabled */ -} TC45_LCCCMODE_t; - -/* Compare or Capture Low Channel D Mode */ -typedef enum TC45_LCCDMODE_enum -{ - TC45_LCCDMODE_DISABLE_gc = (0x00<<6), /* Channel Disabled */ - TC45_LCCDMODE_COMP_gc = (0x01<<6), /* Ouput Compare enabled */ - TC45_LCCDMODE_CAPT_gc = (0x02<<6), /* Input Capture enabled */ - TC45_LCCDMODE_BOTHCC_gc = (0x03<<6), /* Both Compare and Capture enabled */ -} TC45_LCCDMODE_t; - -/* Compare or Capture High Channel A Mode */ -typedef enum TC45_HCCAMODE_enum -{ - TC45_HCCAMODE_DISABLE_gc = (0x00<<0), /* Channel Disabled */ - TC45_HCCAMODE_COMP_gc = (0x01<<0), /* Ouput Compare enabled */ - TC45_HCCAMODE_CAPT_gc = (0x02<<0), /* Input Capture enabled */ - TC45_HCCAMODE_BOTHCC_gc = (0x03<<0), /* Both Compare and Capture enabled */ -} TC45_HCCAMODE_t; - -/* Compare or Capture High Channel B Mode */ -typedef enum TC45_HCCBMODE_enum -{ - TC45_HCCBMODE_DISABLE_gc = (0x00<<2), /* Channel Disabled */ - TC45_HCCBMODE_COMP_gc = (0x01<<2), /* Ouput Compare enabled */ - TC45_HCCBMODE_CAPT_gc = (0x02<<2), /* Input Capture enabled */ - TC45_HCCBMODE_BOTHCC_gc = (0x03<<2), /* Both Compare and Capture enabled */ -} TC45_HCCBMODE_t; - -/* Compare or Capture High Channel C Mode */ -typedef enum TC45_HCCCMODE_enum -{ - TC45_HCCCMODE_DISABLE_gc = (0x00<<4), /* Channel Disabled */ - TC45_HCCCMODE_COMP_gc = (0x01<<4), /* Ouput Compare enabled */ - TC45_HCCCMODE_CAPT_gc = (0x02<<4), /* Input Capture enabled */ - TC45_HCCCMODE_BOTHCC_gc = (0x03<<4), /* Both Compare and Capture enabled */ -} TC45_HCCCMODE_t; - -/* Compare or Capture High Channel D Mode */ -typedef enum TC45_HCCDMODE_enum -{ - TC45_HCCDMODE_DISABLE_gc = (0x00<<6), /* Channel Disabled */ - TC45_HCCDMODE_COMP_gc = (0x01<<6), /* Ouput Compare enabled */ - TC45_HCCDMODE_CAPT_gc = (0x02<<6), /* Input Capture enabled */ - TC45_HCCDMODE_BOTHCC_gc = (0x03<<6), /* Both Compare and Capture enabled */ -} TC45_HCCDMODE_t; - -/* Timer Trigger Restart Interrupt Level */ -typedef enum TC45_TRGINTLVL_enum -{ - TC45_TRGINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - TC45_TRGINTLVL_LO_gc = (0x01<<4), /* Low Level */ - TC45_TRGINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - TC45_TRGINTLVL_HI_gc = (0x03<<4), /* High Level */ -} TC45_TRGINTLVL_t; - -/* Error Interrupt Level */ -typedef enum TC45_ERRINTLVL_enum -{ - TC45_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC45_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC45_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC45_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC45_ERRINTLVL_t; - -/* Overflow Interrupt Level */ -typedef enum TC45_OVFINTLVL_enum -{ - TC45_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC45_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC45_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC45_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC45_OVFINTLVL_t; - -/* Compare or Capture Channel A Interrupt Level */ -typedef enum TC45_CCAINTLVL_enum -{ - TC45_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC45_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC45_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC45_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC45_CCAINTLVL_t; - -/* Compare or Capture Channel B Interrupt Level */ -typedef enum TC45_CCBINTLVL_enum -{ - TC45_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC45_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC45_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC45_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC45_CCBINTLVL_t; - -/* Compare or Capture Channel C Interrupt Level */ -typedef enum TC45_CCCINTLVL_enum -{ - TC45_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - TC45_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - TC45_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - TC45_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} TC45_CCCINTLVL_t; - -/* Compare or Capture Channel D Interrupt Level */ -typedef enum TC45_CCDINTLVL_enum -{ - TC45_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TC45_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ - TC45_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TC45_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ -} TC45_CCDINTLVL_t; - -/* Compare or Capture Low Channel A Interrupt Level */ -typedef enum TC45_LCCAINTLVL_enum -{ - TC45_LCCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC45_LCCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC45_LCCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC45_LCCAINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC45_LCCAINTLVL_t; - -/* Compare or Capture Low Channel B Interrupt Level */ -typedef enum TC45_LCCBINTLVL_enum -{ - TC45_LCCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC45_LCCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC45_LCCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC45_LCCBINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC45_LCCBINTLVL_t; - -/* Compare or Capture Low Channel C Interrupt Level */ -typedef enum TC45_LCCCINTLVL_enum -{ - TC45_LCCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - TC45_LCCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - TC45_LCCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - TC45_LCCCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} TC45_LCCCINTLVL_t; - -/* Compare or Capture Low Channel D Interrupt Level */ -typedef enum TC45_LCCDINTLVL_enum -{ - TC45_LCCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TC45_LCCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ - TC45_LCCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TC45_LCCDINTLVL_HI_gc = (0x03<<6), /* High Level */ -} TC45_LCCDINTLVL_t; - -/* Timer/Counter Command */ -typedef enum TC45_CMD_enum -{ - TC45_CMD_NONE_gc = (0x00<<2), /* No Command */ - TC45_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ - TC45_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ - TC45_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -} TC45_CMD_t; - - -/* --------------------------------------------------------------------------- -FAULT - Fault Extension --------------------------------------------------------------------------- -*/ - -/* Fault Extension */ -typedef struct FAULT_struct -{ - register8_t CTRLA; /* Control A Register */ - register8_t CTRLB; /* Control B Register */ - register8_t CTRLC; /* Control C Register */ - register8_t CTRLD; /* Control D Register */ - register8_t CTRLE; /* Control E Register */ - register8_t STATUS; /* Status Register */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G set */ -} FAULT_t; - -/* Ramp Mode Selection */ -typedef enum FAULT_RAMP_enum -{ - FAULT_RAMP_RAMP1_gc = (0x00<<6), /* Normal Mode */ - FAULT_RAMP_RAMP2_gc = (0x02<<6), /* RAMP2 Mode */ -} FAULT_RAMP_t; - -/* Fault E Input Source Selection */ -typedef enum FAULT_SRCE_enum -{ - FAULT_SRCE_DISABLE_gc = (0x00<<0), /* Fault Protection Disabled */ - FAULT_SRCE_CHN_gc = (0x01<<0), /* Event Channel n */ - FAULT_SRCE_CHN1_gc = (0x02<<0), /* Event Channel n+1 */ - FAULT_SRCE_CHN2_gc = (0x03<<0), /* Event Channel n+2 */ -} FAULT_SRCE_t; - -/* Fault A Halt Action Selection */ -typedef enum FAULT_HALTA_enum -{ - FAULT_HALTA_DISABLE_gc = (0x00<<5), /* Halt Action Disabled */ - FAULT_HALTA_HW_gc = (0x01<<5), /* Hardware Halt Action */ - FAULT_HALTA_SW_gc = (0x02<<5), /* Software Halt Action */ -} FAULT_HALTA_t; - -/* Fault A Source Selection */ -typedef enum FAULT_SRCA_enum -{ - FAULT_SRCA_DISABLE_gc = (0x00<<0), /* Fault A Disabled */ - FAULT_SRCA_CHN_gc = (0x01<<0), /* Event Channel n */ - FAULT_SRCA_CHN1_gc = (0x02<<0), /* Event Channel n+1 */ - FAULT_SRCA_LINK_gc = (0x03<<0), /* Fault A linked to Fault B State from previous cycle */ -} FAULT_SRCA_t; - -/* Fault B Halt Action Selection */ -typedef enum FAULT_HALTB_enum -{ - FAULT_HALTB_DISABLE_gc = (0x00<<5), /* Halt Action Disabled */ - FAULT_HALTB_HW_gc = (0x01<<5), /* Hardware Halt Action */ - FAULT_HALTB_SW_gc = (0x02<<5), /* Software Halt Action */ -} FAULT_HALTB_t; - -/* Fault B Source Selection */ -typedef enum FAULT_SRCB_enum -{ - FAULT_SRCB_DISABLE_gc = (0x00<<0), /* Fault B disabled */ - FAULT_SRCB_CHN_gc = (0x01<<0), /* Event Channel n */ - FAULT_SRCB_CHN1_gc = (0x02<<0), /* Event Channel n+1 */ - FAULT_SRCB_LINK_gc = (0x03<<0), /* Fault B linked to Fault A State from previous cycle */ -} FAULT_SRCB_t; - -/* Channel index Command */ -typedef enum FAULT_IDXCMD_enum -{ - FAULT_IDXCMD_DISABLE_gc = (0x00<<3), /* Command Disabled */ - FAULT_IDXCMD_SET_gc = (0x01<<3), /* Force Cycle B in Next Cycle */ - FAULT_IDXCMD_CLEAR_gc = (0x02<<3), /* Force Cycle A in Next Cycle */ - FAULT_IDXCMD_HOLD_gc = (0x03<<3), /* Hold Current Cycle Index in Next Cycle */ -} FAULT_IDXCMD_t; - - -/* --------------------------------------------------------------------------- -WEX - Waveform Extension --------------------------------------------------------------------------- -*/ - -/* Waveform Extension */ -typedef struct WEX_struct -{ - register8_t CTRL; /* Control Register */ - register8_t DTBOTH; /* Dead-time Concurrent Write to Both Sides Register */ - register8_t DTLS; /* Dead-time Low Side Register */ - register8_t DTHS; /* Dead-time High Side Register */ - register8_t STATUSCLR; /* Status Clear Register */ - register8_t STATUSSET; /* Status Set Register */ - register8_t SWAP; /* Swap Register */ - register8_t PGO; /* Pattern Generation Override Register */ - register8_t PGV; /* Pattern Generation Value Register */ - register8_t reserved_0x09; - register8_t SWAPBUF; /* Dead Time Low Side Buffer */ - register8_t PGOBUF; /* Pattern Generation Overwrite Buffer Register */ - register8_t PGVBUF; /* Pattern Generation Value Buffer Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t OUTOVDIS; /* Output Override Disable Register */ -} WEX_t; - -/* Output Matrix Mode */ -typedef enum WEX_OTMX_enum -{ - WEX_OTMX_DEFAULT_gc = (0x00<<4), /* Default Ouput Matrix Mode */ - WEX_OTMX_FIRST_gc = (0x01<<4), /* First Output matrix Mode */ - WEX_OTMX_SECOND_gc = (0x02<<4), /* Second Output matrix Mode */ - WEX_OTMX_THIRD_gc = (0x03<<4), /* Third Output matrix Mode */ - WEX_OTMX_FOURTH_gc = (0x04<<4), /* Fourth Output matrix Mode */ -} WEX_OTMX_t; - - -/* --------------------------------------------------------------------------- -HIRES - High-Resolution Extension --------------------------------------------------------------------------- -*/ - -/* High-Resolution Extension */ -typedef struct HIRES_struct -{ - register8_t CTRLA; /* Control Register A */ -} HIRES_t; - -/* High Resolution Plus Mode */ -typedef enum HIRES_HRPLUS_enum -{ - HIRES_HRPLUS_NONE_gc = (0x00<<2), /* No Hi-Res Plus */ - HIRES_HRPLUS_HRP4_gc = (0x01<<2), /* Hi-Res Plus enabled on Timer 4 */ - HIRES_HRPLUS_HRP5_gc = (0x02<<2), /* Hi-Res Plus enabled on Timer 5 */ - HIRES_HRPLUS_BOTH_gc = (0x03<<2), /* Hi-Res Plus enabled on Timer 4 and 5 */ -} HIRES_HRPLUS_t; - -/* High Resolution Mode */ -typedef enum HIRES_HREN_enum -{ - HIRES_HREN_NONE_gc = (0x00<<0), /* No Hi-Res */ - HIRES_HREN_HRP4_gc = (0x01<<0), /* Hi-Res enabled on Timer 4 */ - HIRES_HREN_HRP5_gc = (0x02<<0), /* Hi-Res enabled on Timer 5 */ - HIRES_HREN_BOTH_gc = (0x03<<0), /* Hi-Res enabled on Timer 4 and 5 */ -} HIRES_HREN_t; - - -/* --------------------------------------------------------------------------- -USART - Universal Asynchronous Receiver-Transmitter --------------------------------------------------------------------------- -*/ - -/* Universal Synchronous/Asynchronous Receiver/Transmitter */ -typedef struct USART_struct -{ - register8_t DATA; /* Data Register */ - register8_t STATUS; /* Status Register */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t CTRLD; /* Control Register D */ - register8_t BAUDCTRLA; /* Baud Rate Control Register A */ - register8_t BAUDCTRLB; /* Baud Rate Control Register B */ -} USART_t; - -/* Receive Start Interrupt level */ -typedef enum USART_RXSINTLVL_enum -{ - USART_RXSINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - USART_RXSINTLVL_LO_gc = (0x01<<0), /* Low Level */ - USART_RXSINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - USART_RXSINTLVL_HI_gc = (0x03<<0), /* High Level */ -} USART_RXSINTLVL_t; - -/* Receive Complete Interrupt level */ -typedef enum USART_RXCINTLVL_enum -{ - USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} USART_RXCINTLVL_t; - -/* Transmit Complete Interrupt level */ -typedef enum USART_TXCINTLVL_enum -{ - USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ - USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ -} USART_TXCINTLVL_t; - -/* Data Register Empty Interrupt level */ -typedef enum USART_DREINTLVL_enum -{ - USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ - USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ -} USART_DREINTLVL_t; - -/* Character Size */ -typedef enum USART_CHSIZE_enum -{ - USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ - USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ - USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ - USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ - USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ -} USART_CHSIZE_t; - -/* Communication Mode */ -typedef enum USART_CMODE_enum -{ - USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ - USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ - USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ - USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ -} USART_CMODE_t; - -/* Parity Mode */ -typedef enum USART_PMODE_enum -{ - USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ - USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ - USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ -} USART_PMODE_t; - -/* Encoding and Decoding Type */ -typedef enum USART_DECTYPE_enum -{ - USART_DECTYPE_DATA_gc = (0x00<<4), /* DATA Field Encoding */ - USART_DECTYPE_SDATA_gc = (0x02<<4), /* Start and Data Fields Encoding */ - USART_DECTYPE_NOTSDATA_gc = (0x03<<4), /* Start and Data Fields Encoding, with invertion in START field */ -} USART_DECTYPE_t; - -/* XCL LUT Action */ -typedef enum USART_LUTACT_enum -{ - USART_LUTACT_OFF_gc = (0x00<<2), /* Standard Frame Configuration */ - USART_LUTACT_RX_gc = (0x01<<2), /* Receiver Decoding Enabled */ - USART_LUTACT_TX_gc = (0x02<<2), /* Transmitter Encoding Enabled */ - USART_LUTACT_BOTH_gc = (0x03<<2), /* Both Encoding and Decoding Enabled */ -} USART_LUTACT_t; - -/* XCL Peripheral Counter Action */ -typedef enum USART_PECACT_enum -{ - USART_PECACT_OFF_gc = (0x00<<0), /* Standard Mode */ - USART_PECACT_PEC0_gc = (0x01<<0), /* Variable Data Lenght in Reception */ - USART_PECACT_PEC1_gc = (0x02<<0), /* Variable Data Lenght in Transmission */ - USART_PECACT_PERC01_gc = (0x03<<0), /* Variable Data Lenght in both Reception and Transmission */ -} USART_PECACT_t; - - -/* --------------------------------------------------------------------------- -SPI - Serial Peripheral Interface --------------------------------------------------------------------------- -*/ - -/* Serial Peripheral Interface with Buffer Modes */ -typedef struct SPI_struct -{ - register8_t CTRL; /* Control Register */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t STATUS; /* Status Register */ - register8_t DATA; /* Data Register */ - register8_t CTRLB; /* Control Register B */ -} SPI_t; - -/* SPI Mode */ -typedef enum SPI_MODE_enum -{ - SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0, base clock at "0", sampling on leading edge (rising) & set-up on trailling edge (falling). */ - SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1, base clock at "0", set-up on leading edge (rising) & sampling on trailling edge (falling). */ - SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2, base clock at "1", sampling on leading edge (falling) & set-up on trailling edge (rising). */ - SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3, base clock at "1", set-up on leading edge (falling) & sampling on trailling edge (rising). */ -} SPI_MODE_t; - -/* Prescaler setting */ -typedef enum SPI_PRESCALER_enum -{ - SPI_PRESCALER_DIV4_gc = (0x00<<0), /* If CLK2X=1 CLKper/2, else (CLK2X=0) CLKper/4. */ - SPI_PRESCALER_DIV16_gc = (0x01<<0), /* If CLK2X=1 CLKper/8, else (CLK2X=0) CLKper/16. */ - SPI_PRESCALER_DIV64_gc = (0x02<<0), /* If CLK2X=1 CLKper/32, else (CLK2X=0) CLKper/64. */ - SPI_PRESCALER_DIV128_gc = (0x03<<0), /* If CLK2X=1 CLKper/64, else (CLK2X=0) CLKper/128. */ -} SPI_PRESCALER_t; - -/* Interrupt level */ -typedef enum SPI_INTLVL_enum -{ - SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ - SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ - SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ -} SPI_INTLVL_t; - -/* Buffer Modes */ -typedef enum SPI_BUFMODE_enum -{ - SPI_BUFMODE_OFF_gc = (0x00<<6), /* SPI Unbuffered Mode */ - SPI_BUFMODE_BUFMODE1_gc = (0x02<<6), /* Buffer Mode 1 (with dummy byte) */ - SPI_BUFMODE_BUFMODE2_gc = (0x03<<6), /* Buffer Mode 2 (no dummy byte) */ -} SPI_BUFMODE_t; - - -/* --------------------------------------------------------------------------- -IRCOM - IR Communication Module --------------------------------------------------------------------------- -*/ - -/* IR Communication Module */ -typedef struct IRCOM_struct -{ - register8_t CTRL; /* Control Register */ - register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ - register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ -} IRCOM_t; - -/* Event channel selection */ -typedef enum IRDA_EVSEL_enum -{ - IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ - IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ - IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ - IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ - IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ - IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ - IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ - IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ - IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ -} IRDA_EVSEL_t; - - -/* --------------------------------------------------------------------------- -FUSE - Fuses and Lockbits --------------------------------------------------------------------------- -*/ - -/* Lock Bits */ -typedef struct NVM_LOCKBITS_struct -{ - register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ -} NVM_LOCKBITS_t; - - -/* Fuses */ -typedef struct NVM_FUSES_struct -{ - register8_t reserved_0x00; - register8_t FUSEBYTE1; /* Watchdog Configuration */ - register8_t FUSEBYTE2; /* Reset Configuration */ - register8_t reserved_0x03; - register8_t FUSEBYTE4; /* Start-up Configuration */ - register8_t FUSEBYTE5; /* EESAVE and BOD Level */ - register8_t FUSEBYTE6; /* Fault State */ -} NVM_FUSES_t; - -/* Boot lock bits - boot setcion */ -typedef enum FUSE_BLBB_enum -{ - FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ - FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ - FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ - FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -} FUSE_BLBB_t; - -/* Boot lock bits - application section */ -typedef enum FUSE_BLBA_enum -{ - FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ - FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ - FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ - FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -} FUSE_BLBA_t; - -/* Boot lock bits - application table section */ -typedef enum FUSE_BLBAT_enum -{ - FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ - FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ - FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ - FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -} FUSE_BLBAT_t; - -/* Lock bits */ -typedef enum FUSE_LB_enum -{ - FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ - FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ - FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -} FUSE_LB_t; - -/* Boot Loader Section Reset Vector */ -typedef enum BOOTRST_enum -{ - BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ - BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ -} BOOTRST_t; - -/* BOD operation */ -typedef enum BOD_enum -{ - BOD_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ - BOD_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ - BOD_DISABLED_gc = (0x03<<4), /* BOD Disabled */ -} BOD_t; - -/* Watchdog (Window) Timeout Period */ -typedef enum WD_enum -{ - WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ - WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ - WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ - WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ - WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ - WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ - WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ - WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ - WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ - WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ - WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ -} WD_t; - -/* Start-up Time */ -typedef enum SUT_enum -{ - SUT_0MS_gc = (0x03<<2), /* 0 ms */ - SUT_4MS_gc = (0x01<<2), /* 4 ms */ - SUT_64MS_gc = (0x00<<2), /* 64 ms */ -} SUT_t; - -/* Brownout Detection Voltage Level */ -typedef enum BODLVL_enum -{ - BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ - BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ - BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ - BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ - BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ - BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ - BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ - BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ -} BODLVL_t; - - -/* --------------------------------------------------------------------------- -SIGROW - Signature Row --------------------------------------------------------------------------- -*/ - -/* Production Signatures */ -typedef struct NVM_PROD_SIGNATURES_struct -{ - register8_t RCOSC8M; /* RCOSC 8MHz Calibration Value */ - register8_t reserved_0x01; - register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ - register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ - register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ - register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ - register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ - register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ - register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ - register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t WAFNUM; /* Wafer Number */ - register8_t reserved_0x11; - register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ - register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ - register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ - register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t ROOMTEMP; /* Temperature corresponds to TEMPSENSE3/2 */ - register8_t HOTTEMP; /* Temperature corresponds to TEMPSENSE1/0 */ - register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ - register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - register8_t reserved_0x26; - register8_t reserved_0x27; - register8_t ACACURRCAL; /* ACA Current Calibration Byte */ - register8_t reserved_0x29; - register8_t reserved_0x2A; - register8_t reserved_0x2B; - register8_t TEMPSENSE2; /* Temperature Sensor Calibration Byte 2 */ - register8_t TEMPSENSE3; /* Temperature Sensor Calibration Byte 3 */ - register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ - register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ - register8_t DACA0OFFCAL; /* DACA0 Calibration Byte 0 */ - register8_t DACA0GAINCAL; /* DACA0 Calibration Byte 1 */ - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t DACA1OFFCAL; /* DACA1 Calibration Byte 0 */ - register8_t DACA1GAINCAL; /* DACA1 Calibration Byte 1 */ - register8_t reserved_0x36; - register8_t reserved_0x37; - register8_t reserved_0x38; - register8_t reserved_0x39; - register8_t reserved_0x3A; - register8_t reserved_0x3B; - register8_t reserved_0x3C; - register8_t reserved_0x3D; - register8_t reserved_0x3E; - register8_t reserved_0x3F; -} NVM_PROD_SIGNATURES_t; - -/* -========================================================================== -IO Module Instances. Mapped to memory. -========================================================================== -*/ - -#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ -#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ -#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ -#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ -#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ -#define CLK (*(CLK_t *) 0x0040) /* Clock System */ -#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ -#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ -#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ -#define PR (*(PR_t *) 0x0070) /* Power Reduction */ -#define RST (*(RST_t *) 0x0078) /* Reset */ -#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ -#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ -#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ -#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ -#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ -#define EDMA (*(EDMA_t *) 0x0100) /* Enhanced DMA Controller */ -#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ -#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ -#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ -#define DACA (*(DAC_t *) 0x0300) /* Digital-to-Analog Converter */ -#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ -#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ -#define XCL (*(XCL_t *) 0x0460) /* XMEGA Custom Logic */ -#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ -#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ -#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ -#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ -#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ -#define TCC4 (*(TC4_t *) 0x0800) /* 16-bit Timer/Counter 4 */ -#define TCC5 (*(TC5_t *) 0x0840) /* 16-bit Timer/Counter 5 */ -#define FAULTC4 (*(FAULT_t *) 0x0880) /* Fault Extension */ -#define FAULTC5 (*(FAULT_t *) 0x0890) /* Fault Extension */ -#define WEXC (*(WEX_t *) 0x08A0) /* Waveform Extension */ -#define HIRESC (*(HIRES_t *) 0x08B0) /* High-Resolution Extension */ -#define USARTC0 (*(USART_t *) 0x08C0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define SPIC (*(SPI_t *) 0x08E0) /* Serial Peripheral Interface with Buffer Modes */ -#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ -#define TCD5 (*(TC5_t *) 0x0940) /* 16-bit Timer/Counter 5 */ -#define USARTD0 (*(USART_t *) 0x09C0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ - - -#endif /* !defined (__ASSEMBLER__) */ - - -/* ========== Flattened fully qualified IO register names ========== */ - -/* GPIO - General Purpose IO Registers */ -#define GPIO_GPIOR0 _SFR_MEM8(0x0000) -#define GPIO_GPIOR1 _SFR_MEM8(0x0001) -#define GPIO_GPIOR2 _SFR_MEM8(0x0002) -#define GPIO_GPIOR3 _SFR_MEM8(0x0003) - -/* Deprecated */ -#define GPIO_GPIO0 _SFR_MEM8(0x0000) -#define GPIO_GPIO1 _SFR_MEM8(0x0001) -#define GPIO_GPIO2 _SFR_MEM8(0x0002) -#define GPIO_GPIO3 _SFR_MEM8(0x0003) - -/* NVM_FUSES - Fuses */ -#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) -#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) -#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) -#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) -#define FUSE_FUSEBYTE6 _SFR_MEM8(0x0006) - -/* NVM_LOCKBITS - Lock Bits */ -#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) - -/* NVM_PROD_SIGNATURES - Production Signatures */ -#define PRODSIGNATURES_RCOSC8M _SFR_MEM8(0x0000) -#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) -#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) -#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) -#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) -#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) -#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) -#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) -#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) -#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) -#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) -#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) -#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) -#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) -#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) -#define PRODSIGNATURES_ROOMTEMP _SFR_MEM8(0x001E) -#define PRODSIGNATURES_HOTTEMP _SFR_MEM8(0x001F) -#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) -#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) -#define PRODSIGNATURES_ACACURRCAL _SFR_MEM8(0x0028) -#define PRODSIGNATURES_TEMPSENSE2 _SFR_MEM8(0x002C) -#define PRODSIGNATURES_TEMPSENSE3 _SFR_MEM8(0x002D) -#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) -#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) -#define PRODSIGNATURES_DACA0OFFCAL _SFR_MEM8(0x0030) -#define PRODSIGNATURES_DACA0GAINCAL _SFR_MEM8(0x0031) -#define PRODSIGNATURES_DACA1OFFCAL _SFR_MEM8(0x0034) -#define PRODSIGNATURES_DACA1GAINCAL _SFR_MEM8(0x0035) - -/* VPORT - Virtual Port */ -#define VPORT0_DIR _SFR_MEM8(0x0010) -#define VPORT0_OUT _SFR_MEM8(0x0011) -#define VPORT0_IN _SFR_MEM8(0x0012) -#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) - -/* VPORT - Virtual Port */ -#define VPORT1_DIR _SFR_MEM8(0x0014) -#define VPORT1_OUT _SFR_MEM8(0x0015) -#define VPORT1_IN _SFR_MEM8(0x0016) -#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) - -/* VPORT - Virtual Port */ -#define VPORT2_DIR _SFR_MEM8(0x0018) -#define VPORT2_OUT _SFR_MEM8(0x0019) -#define VPORT2_IN _SFR_MEM8(0x001A) -#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) - -/* VPORT - Virtual Port */ -#define VPORT3_DIR _SFR_MEM8(0x001C) -#define VPORT3_OUT _SFR_MEM8(0x001D) -#define VPORT3_IN _SFR_MEM8(0x001E) -#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) - -/* OCD - On-Chip Debug System */ -#define OCD_OCDR0 _SFR_MEM8(0x002E) -#define OCD_OCDR1 _SFR_MEM8(0x002F) - -/* CPU - CPU registers */ -#define CPU_CCP _SFR_MEM8(0x0034) -#define CPU_RAMPD _SFR_MEM8(0x0038) -#define CPU_RAMPX _SFR_MEM8(0x0039) -#define CPU_RAMPY _SFR_MEM8(0x003A) -#define CPU_RAMPZ _SFR_MEM8(0x003B) -#define CPU_EIND _SFR_MEM8(0x003C) -#define CPU_SPL _SFR_MEM8(0x003D) -#define CPU_SPH _SFR_MEM8(0x003E) -#define CPU_SREG _SFR_MEM8(0x003F) - -/* CLK - Clock System */ -#define CLK_CTRL _SFR_MEM8(0x0040) -#define CLK_PSCTRL _SFR_MEM8(0x0041) -#define CLK_LOCK _SFR_MEM8(0x0042) -#define CLK_RTCCTRL _SFR_MEM8(0x0043) - -/* SLEEP - Sleep Controller */ -#define SLEEP_CTRL _SFR_MEM8(0x0048) - -/* OSC - Oscillator */ -#define OSC_CTRL _SFR_MEM8(0x0050) -#define OSC_STATUS _SFR_MEM8(0x0051) -#define OSC_XOSCCTRL _SFR_MEM8(0x0052) -#define OSC_XOSCFAIL _SFR_MEM8(0x0053) -#define OSC_RC32KCAL _SFR_MEM8(0x0054) -#define OSC_PLLCTRL _SFR_MEM8(0x0055) -#define OSC_DFLLCTRL _SFR_MEM8(0x0056) -#define OSC_RC8MCAL _SFR_MEM8(0x0057) - -/* DFLL - DFLL */ -#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) -#define DFLLRC32M_CALA _SFR_MEM8(0x0062) -#define DFLLRC32M_CALB _SFR_MEM8(0x0063) -#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) -#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) -#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) - -/* PR - Power Reduction */ -#define PR_PRGEN _SFR_MEM8(0x0070) -#define PR_PRPA _SFR_MEM8(0x0071) -#define PR_PRPC _SFR_MEM8(0x0073) -#define PR_PRPD _SFR_MEM8(0x0074) - -/* RST - Reset */ -#define RST_STATUS _SFR_MEM8(0x0078) -#define RST_CTRL _SFR_MEM8(0x0079) - -/* WDT - Watch-Dog Timer */ -#define WDT_CTRL _SFR_MEM8(0x0080) -#define WDT_WINCTRL _SFR_MEM8(0x0081) -#define WDT_STATUS _SFR_MEM8(0x0082) - -/* MCU - MCU Control */ -#define MCU_DEVID0 _SFR_MEM8(0x0090) -#define MCU_DEVID1 _SFR_MEM8(0x0091) -#define MCU_DEVID2 _SFR_MEM8(0x0092) -#define MCU_REVID _SFR_MEM8(0x0093) -#define MCU_ANAINIT _SFR_MEM8(0x0097) -#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) -#define MCU_WEXLOCK _SFR_MEM8(0x0099) -#define MCU_FAULTLOCK _SFR_MEM8(0x009A) - -/* PMIC - Programmable Multi-level Interrupt Controller */ -#define PMIC_STATUS _SFR_MEM8(0x00A0) -#define PMIC_INTPRI _SFR_MEM8(0x00A1) -#define PMIC_CTRL _SFR_MEM8(0x00A2) - -/* PORTCFG - I/O port Configuration */ -#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) -#define PORTCFG_CLKOUT _SFR_MEM8(0x00B4) -#define PORTCFG_ACEVOUT _SFR_MEM8(0x00B6) -#define PORTCFG_SRLCTRL _SFR_MEM8(0x00B7) - -/* CRC - Cyclic Redundancy Checker */ -#define CRC_CTRL _SFR_MEM8(0x00D0) -#define CRC_STATUS _SFR_MEM8(0x00D1) -#define CRC_DATAIN _SFR_MEM8(0x00D3) -#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) -#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) -#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) -#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) - -/* EDMA - Enhanced DMA Controller */ -#define EDMA_CTRL _SFR_MEM8(0x0100) -#define EDMA_INTFLAGS _SFR_MEM8(0x0103) -#define EDMA_STATUS _SFR_MEM8(0x0104) -#define EDMA_TEMP _SFR_MEM8(0x0106) -#define EDMA_CH0_CTRLA _SFR_MEM8(0x0110) -#define EDMA_CH0_CTRLB _SFR_MEM8(0x0111) -#define EDMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) -#define EDMA_CH0_DESTADDRCTRL _SFR_MEM8(0x0113) -#define EDMA_CH0_TRIGSRC _SFR_MEM8(0x0114) -#define EDMA_CH0_TRFCNT _SFR_MEM16(0x0116) -#define EDMA_CH0_ADDR _SFR_MEM16(0x0118) -#define EDMA_CH0_DESTADDR _SFR_MEM16(0x011C) -#define EDMA_CH1_CTRLA _SFR_MEM8(0x0120) -#define EDMA_CH1_CTRLB _SFR_MEM8(0x0121) -#define EDMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) -#define EDMA_CH1_DESTADDRCTRL _SFR_MEM8(0x0123) -#define EDMA_CH1_TRIGSRC _SFR_MEM8(0x0124) -#define EDMA_CH1_TRFCNT _SFR_MEM16(0x0126) -#define EDMA_CH1_ADDR _SFR_MEM16(0x0128) -#define EDMA_CH1_DESTADDR _SFR_MEM16(0x012C) -#define EDMA_CH2_CTRLA _SFR_MEM8(0x0130) -#define EDMA_CH2_CTRLB _SFR_MEM8(0x0131) -#define EDMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) -#define EDMA_CH2_DESTADDRCTRL _SFR_MEM8(0x0133) -#define EDMA_CH2_TRIGSRC _SFR_MEM8(0x0134) -#define EDMA_CH2_TRFCNT _SFR_MEM16(0x0136) -#define EDMA_CH2_ADDR _SFR_MEM16(0x0138) -#define EDMA_CH2_DESTADDR _SFR_MEM16(0x013C) -#define EDMA_CH3_CTRLA _SFR_MEM8(0x0140) -#define EDMA_CH3_CTRLB _SFR_MEM8(0x0141) -#define EDMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) -#define EDMA_CH3_DESTADDRCTRL _SFR_MEM8(0x0143) -#define EDMA_CH3_TRIGSRC _SFR_MEM8(0x0144) -#define EDMA_CH3_TRFCNT _SFR_MEM16(0x0146) -#define EDMA_CH3_ADDR _SFR_MEM16(0x0148) -#define EDMA_CH3_DESTADDR _SFR_MEM16(0x014C) - -/* EVSYS - Event System */ -#define EVSYS_CH0MUX _SFR_MEM8(0x0180) -#define EVSYS_CH1MUX _SFR_MEM8(0x0181) -#define EVSYS_CH2MUX _SFR_MEM8(0x0182) -#define EVSYS_CH3MUX _SFR_MEM8(0x0183) -#define EVSYS_CH4MUX _SFR_MEM8(0x0184) -#define EVSYS_CH5MUX _SFR_MEM8(0x0185) -#define EVSYS_CH6MUX _SFR_MEM8(0x0186) -#define EVSYS_CH7MUX _SFR_MEM8(0x0187) -#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) -#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) -#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) -#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) -#define EVSYS_CH4CTRL _SFR_MEM8(0x018C) -#define EVSYS_CH5CTRL _SFR_MEM8(0x018D) -#define EVSYS_CH6CTRL _SFR_MEM8(0x018E) -#define EVSYS_CH7CTRL _SFR_MEM8(0x018F) -#define EVSYS_STROBE _SFR_MEM8(0x0190) -#define EVSYS_DATA _SFR_MEM8(0x0191) -#define EVSYS_DFCTRL _SFR_MEM8(0x0192) - -/* NVM - Non-volatile Memory Controller */ -#define NVM_ADDR0 _SFR_MEM8(0x01C0) -#define NVM_ADDR1 _SFR_MEM8(0x01C1) -#define NVM_ADDR2 _SFR_MEM8(0x01C2) -#define NVM_DATA0 _SFR_MEM8(0x01C4) -#define NVM_DATA1 _SFR_MEM8(0x01C5) -#define NVM_DATA2 _SFR_MEM8(0x01C6) -#define NVM_CMD _SFR_MEM8(0x01CA) -#define NVM_CTRLA _SFR_MEM8(0x01CB) -#define NVM_CTRLB _SFR_MEM8(0x01CC) -#define NVM_INTCTRL _SFR_MEM8(0x01CD) -#define NVM_STATUS _SFR_MEM8(0x01CF) -#define NVM_LOCKBITS _SFR_MEM8(0x01D0) - -/* ADC - Analog-to-Digital Converter */ -#define ADCA_CTRLA _SFR_MEM8(0x0200) -#define ADCA_CTRLB _SFR_MEM8(0x0201) -#define ADCA_REFCTRL _SFR_MEM8(0x0202) -#define ADCA_EVCTRL _SFR_MEM8(0x0203) -#define ADCA_PRESCALER _SFR_MEM8(0x0204) -#define ADCA_INTFLAGS _SFR_MEM8(0x0206) -#define ADCA_TEMP _SFR_MEM8(0x0207) -#define ADCA_SAMPCTRL _SFR_MEM8(0x0208) -#define ADCA_CAL _SFR_MEM16(0x020C) -#define ADCA_CH0RES _SFR_MEM16(0x0210) -#define ADCA_CMP _SFR_MEM16(0x0218) -#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) -#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) -#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) -#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) -#define ADCA_CH0_RES _SFR_MEM16(0x0224) -#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) -#define ADCA_CH0_CORRCTRL _SFR_MEM8(0x0227) -#define ADCA_CH0_OFFSETCORR0 _SFR_MEM8(0x0228) -#define ADCA_CH0_OFFSETCORR1 _SFR_MEM8(0x0229) -#define ADCA_CH0_GAINCORR0 _SFR_MEM8(0x022A) -#define ADCA_CH0_GAINCORR1 _SFR_MEM8(0x022B) -#define ADCA_CH0_AVGCTRL _SFR_MEM8(0x022C) - -/* DAC - Digital-to-Analog Converter */ -#define DACA_CTRLA _SFR_MEM8(0x0300) -#define DACA_CTRLB _SFR_MEM8(0x0301) -#define DACA_CTRLC _SFR_MEM8(0x0302) -#define DACA_EVCTRL _SFR_MEM8(0x0303) -#define DACA_STATUS _SFR_MEM8(0x0305) -#define DACA_CH0GAINCAL _SFR_MEM8(0x0308) -#define DACA_CH0OFFSETCAL _SFR_MEM8(0x0309) -#define DACA_CH1GAINCAL _SFR_MEM8(0x030A) -#define DACA_CH1OFFSETCAL _SFR_MEM8(0x030B) -#define DACA_CH0DATA _SFR_MEM16(0x0318) -#define DACA_CH1DATA _SFR_MEM16(0x031A) - -/* AC - Analog Comparator */ -#define ACA_AC0CTRL _SFR_MEM8(0x0380) -#define ACA_AC1CTRL _SFR_MEM8(0x0381) -#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) -#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) -#define ACA_CTRLA _SFR_MEM8(0x0384) -#define ACA_CTRLB _SFR_MEM8(0x0385) -#define ACA_WINCTRL _SFR_MEM8(0x0386) -#define ACA_STATUS _SFR_MEM8(0x0387) -#define ACA_CURRCTRL _SFR_MEM8(0x0388) -#define ACA_CURRCALIB _SFR_MEM8(0x0389) - -/* RTC - Real-Time Counter */ -#define RTC_CTRL _SFR_MEM8(0x0400) -#define RTC_STATUS _SFR_MEM8(0x0401) -#define RTC_INTCTRL _SFR_MEM8(0x0402) -#define RTC_INTFLAGS _SFR_MEM8(0x0403) -#define RTC_TEMP _SFR_MEM8(0x0404) -#define RTC_CALIB _SFR_MEM8(0x0406) -#define RTC_CNT _SFR_MEM16(0x0408) -#define RTC_PER _SFR_MEM16(0x040A) -#define RTC_COMP _SFR_MEM16(0x040C) - -/* XCL - XMEGA Custom Logic */ -#define XCL_CTRLA _SFR_MEM8(0x0460) -#define XCL_CTRLB _SFR_MEM8(0x0461) -#define XCL_CTRLC _SFR_MEM8(0x0462) -#define XCL_CTRLD _SFR_MEM8(0x0463) -#define XCL_CTRLE _SFR_MEM8(0x0464) -#define XCL_CTRLF _SFR_MEM8(0x0465) -#define XCL_CTRLG _SFR_MEM8(0x0466) -#define XCL_INTCTRL _SFR_MEM8(0x0467) -#define XCL_INTFLAGS _SFR_MEM8(0x0468) -#define XCL_PLC _SFR_MEM8(0x0469) -#define XCL_CNTL _SFR_MEM8(0x046A) -#define XCL_CNTH _SFR_MEM8(0x046B) -#define XCL_CMPL _SFR_MEM8(0x046C) -#define XCL_CMPH _SFR_MEM8(0x046D) -#define XCL_PERCAPTL _SFR_MEM8(0x046E) -#define XCL_PERCAPTH _SFR_MEM8(0x046F) - -/* TWI - Two-Wire Interface */ -#define TWIC_CTRL _SFR_MEM8(0x0480) -#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) -#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) -#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) -#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) -#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) -#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) -#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) -#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) -#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) -#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) -#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) -#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) -#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) -#define TWIC_TIMEOUT_TOS _SFR_MEM8(0x048E) -#define TWIC_TIMEOUT_TOCONF _SFR_MEM8(0x048F) - -/* PORT - I/O Ports */ -#define PORTA_DIR _SFR_MEM8(0x0600) -#define PORTA_DIRSET _SFR_MEM8(0x0601) -#define PORTA_DIRCLR _SFR_MEM8(0x0602) -#define PORTA_DIRTGL _SFR_MEM8(0x0603) -#define PORTA_OUT _SFR_MEM8(0x0604) -#define PORTA_OUTSET _SFR_MEM8(0x0605) -#define PORTA_OUTCLR _SFR_MEM8(0x0606) -#define PORTA_OUTTGL _SFR_MEM8(0x0607) -#define PORTA_IN _SFR_MEM8(0x0608) -#define PORTA_INTCTRL _SFR_MEM8(0x0609) -#define PORTA_INTMASK _SFR_MEM8(0x060A) -#define PORTA_INTFLAGS _SFR_MEM8(0x060C) -#define PORTA_REMAP _SFR_MEM8(0x060E) -#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) -#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) -#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) -#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) -#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) -#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) -#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) -#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) - -/* PORT - I/O Ports */ -#define PORTC_DIR _SFR_MEM8(0x0640) -#define PORTC_DIRSET _SFR_MEM8(0x0641) -#define PORTC_DIRCLR _SFR_MEM8(0x0642) -#define PORTC_DIRTGL _SFR_MEM8(0x0643) -#define PORTC_OUT _SFR_MEM8(0x0644) -#define PORTC_OUTSET _SFR_MEM8(0x0645) -#define PORTC_OUTCLR _SFR_MEM8(0x0646) -#define PORTC_OUTTGL _SFR_MEM8(0x0647) -#define PORTC_IN _SFR_MEM8(0x0648) -#define PORTC_INTCTRL _SFR_MEM8(0x0649) -#define PORTC_INTMASK _SFR_MEM8(0x064A) -#define PORTC_INTFLAGS _SFR_MEM8(0x064C) -#define PORTC_REMAP _SFR_MEM8(0x064E) -#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) -#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) -#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) -#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) -#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) -#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) -#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) -#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) - -/* PORT - I/O Ports */ -#define PORTD_DIR _SFR_MEM8(0x0660) -#define PORTD_DIRSET _SFR_MEM8(0x0661) -#define PORTD_DIRCLR _SFR_MEM8(0x0662) -#define PORTD_DIRTGL _SFR_MEM8(0x0663) -#define PORTD_OUT _SFR_MEM8(0x0664) -#define PORTD_OUTSET _SFR_MEM8(0x0665) -#define PORTD_OUTCLR _SFR_MEM8(0x0666) -#define PORTD_OUTTGL _SFR_MEM8(0x0667) -#define PORTD_IN _SFR_MEM8(0x0668) -#define PORTD_INTCTRL _SFR_MEM8(0x0669) -#define PORTD_INTMASK _SFR_MEM8(0x066A) -#define PORTD_INTFLAGS _SFR_MEM8(0x066C) -#define PORTD_REMAP _SFR_MEM8(0x066E) -#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) -#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) -#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) -#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) -#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) -#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) -#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) -#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) - -/* PORT - I/O Ports */ -#define PORTR_DIR _SFR_MEM8(0x07E0) -#define PORTR_DIRSET _SFR_MEM8(0x07E1) -#define PORTR_DIRCLR _SFR_MEM8(0x07E2) -#define PORTR_DIRTGL _SFR_MEM8(0x07E3) -#define PORTR_OUT _SFR_MEM8(0x07E4) -#define PORTR_OUTSET _SFR_MEM8(0x07E5) -#define PORTR_OUTCLR _SFR_MEM8(0x07E6) -#define PORTR_OUTTGL _SFR_MEM8(0x07E7) -#define PORTR_IN _SFR_MEM8(0x07E8) -#define PORTR_INTCTRL _SFR_MEM8(0x07E9) -#define PORTR_INTMASK _SFR_MEM8(0x07EA) -#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) -#define PORTR_REMAP _SFR_MEM8(0x07EE) -#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) -#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) -#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) -#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) -#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) -#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) -#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) -#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) - -/* TC4 - 16-bit Timer/Counter 4 */ -#define TCC4_CTRLA _SFR_MEM8(0x0800) -#define TCC4_CTRLB _SFR_MEM8(0x0801) -#define TCC4_CTRLC _SFR_MEM8(0x0802) -#define TCC4_CTRLD _SFR_MEM8(0x0803) -#define TCC4_CTRLE _SFR_MEM8(0x0804) -#define TCC4_CTRLF _SFR_MEM8(0x0805) -#define TCC4_INTCTRLA _SFR_MEM8(0x0806) -#define TCC4_INTCTRLB _SFR_MEM8(0x0807) -#define TCC4_CTRLGCLR _SFR_MEM8(0x0808) -#define TCC4_CTRLGSET _SFR_MEM8(0x0809) -#define TCC4_CTRLHCLR _SFR_MEM8(0x080A) -#define TCC4_CTRLHSET _SFR_MEM8(0x080B) -#define TCC4_INTFLAGS _SFR_MEM8(0x080C) -#define TCC4_TEMP _SFR_MEM8(0x080F) -#define TCC4_CNT _SFR_MEM16(0x0820) -#define TCC4_PER _SFR_MEM16(0x0826) -#define TCC4_CCA _SFR_MEM16(0x0828) -#define TCC4_CCB _SFR_MEM16(0x082A) -#define TCC4_CCC _SFR_MEM16(0x082C) -#define TCC4_CCD _SFR_MEM16(0x082E) -#define TCC4_PERBUF _SFR_MEM16(0x0836) -#define TCC4_CCABUF _SFR_MEM16(0x0838) -#define TCC4_CCBBUF _SFR_MEM16(0x083A) -#define TCC4_CCCBUF _SFR_MEM16(0x083C) -#define TCC4_CCDBUF _SFR_MEM16(0x083E) - -/* TC5 - 16-bit Timer/Counter 5 */ -#define TCC5_CTRLA _SFR_MEM8(0x0840) -#define TCC5_CTRLB _SFR_MEM8(0x0841) -#define TCC5_CTRLC _SFR_MEM8(0x0842) -#define TCC5_CTRLD _SFR_MEM8(0x0843) -#define TCC5_CTRLE _SFR_MEM8(0x0844) -#define TCC5_CTRLF _SFR_MEM8(0x0845) -#define TCC5_INTCTRLA _SFR_MEM8(0x0846) -#define TCC5_INTCTRLB _SFR_MEM8(0x0847) -#define TCC5_CTRLGCLR _SFR_MEM8(0x0848) -#define TCC5_CTRLGSET _SFR_MEM8(0x0849) -#define TCC5_CTRLHCLR _SFR_MEM8(0x084A) -#define TCC5_CTRLHSET _SFR_MEM8(0x084B) -#define TCC5_INTFLAGS _SFR_MEM8(0x084C) -#define TCC5_TEMP _SFR_MEM8(0x084F) -#define TCC5_CNT _SFR_MEM16(0x0860) -#define TCC5_PER _SFR_MEM16(0x0866) -#define TCC5_CCA _SFR_MEM16(0x0868) -#define TCC5_CCB _SFR_MEM16(0x086A) -#define TCC5_PERBUF _SFR_MEM16(0x0876) -#define TCC5_CCABUF _SFR_MEM16(0x0878) -#define TCC5_CCBBUF _SFR_MEM16(0x087A) - -/* FAULT - Fault Extension */ -#define FAULTC4_CTRLA _SFR_MEM8(0x0880) -#define FAULTC4_CTRLB _SFR_MEM8(0x0881) -#define FAULTC4_CTRLC _SFR_MEM8(0x0882) -#define FAULTC4_CTRLD _SFR_MEM8(0x0883) -#define FAULTC4_CTRLE _SFR_MEM8(0x0884) -#define FAULTC4_STATUS _SFR_MEM8(0x0885) -#define FAULTC4_CTRLGCLR _SFR_MEM8(0x0886) -#define FAULTC4_CTRLGSET _SFR_MEM8(0x0887) - -/* FAULT - Fault Extension */ -#define FAULTC5_CTRLA _SFR_MEM8(0x0890) -#define FAULTC5_CTRLB _SFR_MEM8(0x0891) -#define FAULTC5_CTRLC _SFR_MEM8(0x0892) -#define FAULTC5_CTRLD _SFR_MEM8(0x0893) -#define FAULTC5_CTRLE _SFR_MEM8(0x0894) -#define FAULTC5_STATUS _SFR_MEM8(0x0895) -#define FAULTC5_CTRLGCLR _SFR_MEM8(0x0896) -#define FAULTC5_CTRLGSET _SFR_MEM8(0x0897) - -/* WEX - Waveform Extension */ -#define WEXC_CTRL _SFR_MEM8(0x08A0) -#define WEXC_DTBOTH _SFR_MEM8(0x08A1) -#define WEXC_DTLS _SFR_MEM8(0x08A2) -#define WEXC_DTHS _SFR_MEM8(0x08A3) -#define WEXC_STATUSCLR _SFR_MEM8(0x08A4) -#define WEXC_STATUSSET _SFR_MEM8(0x08A5) -#define WEXC_SWAP _SFR_MEM8(0x08A6) -#define WEXC_PGO _SFR_MEM8(0x08A7) -#define WEXC_PGV _SFR_MEM8(0x08A8) -#define WEXC_SWAPBUF _SFR_MEM8(0x08AA) -#define WEXC_PGOBUF _SFR_MEM8(0x08AB) -#define WEXC_PGVBUF _SFR_MEM8(0x08AC) -#define WEXC_OUTOVDIS _SFR_MEM8(0x08AF) - -/* HIRES - High-Resolution Extension */ -#define HIRESC_CTRLA _SFR_MEM8(0x08B0) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTC0_DATA _SFR_MEM8(0x08C0) -#define USARTC0_STATUS _SFR_MEM8(0x08C1) -#define USARTC0_CTRLA _SFR_MEM8(0x08C2) -#define USARTC0_CTRLB _SFR_MEM8(0x08C3) -#define USARTC0_CTRLC _SFR_MEM8(0x08C4) -#define USARTC0_CTRLD _SFR_MEM8(0x08C5) -#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08C6) -#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08C7) - -/* SPI - Serial Peripheral Interface with Buffer Modes */ -#define SPIC_CTRL _SFR_MEM8(0x08E0) -#define SPIC_INTCTRL _SFR_MEM8(0x08E1) -#define SPIC_STATUS _SFR_MEM8(0x08E2) -#define SPIC_DATA _SFR_MEM8(0x08E3) -#define SPIC_CTRLB _SFR_MEM8(0x08E4) - -/* IRCOM - IR Communication Module */ -#define IRCOM_CTRL _SFR_MEM8(0x08F8) -#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) -#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) - -/* TC5 - 16-bit Timer/Counter 5 */ -#define TCD5_CTRLA _SFR_MEM8(0x0940) -#define TCD5_CTRLB _SFR_MEM8(0x0941) -#define TCD5_CTRLC _SFR_MEM8(0x0942) -#define TCD5_CTRLD _SFR_MEM8(0x0943) -#define TCD5_CTRLE _SFR_MEM8(0x0944) -#define TCD5_CTRLF _SFR_MEM8(0x0945) -#define TCD5_INTCTRLA _SFR_MEM8(0x0946) -#define TCD5_INTCTRLB _SFR_MEM8(0x0947) -#define TCD5_CTRLGCLR _SFR_MEM8(0x0948) -#define TCD5_CTRLGSET _SFR_MEM8(0x0949) -#define TCD5_CTRLHCLR _SFR_MEM8(0x094A) -#define TCD5_CTRLHSET _SFR_MEM8(0x094B) -#define TCD5_INTFLAGS _SFR_MEM8(0x094C) -#define TCD5_TEMP _SFR_MEM8(0x094F) -#define TCD5_CNT _SFR_MEM16(0x0960) -#define TCD5_PER _SFR_MEM16(0x0966) -#define TCD5_CCA _SFR_MEM16(0x0968) -#define TCD5_CCB _SFR_MEM16(0x096A) -#define TCD5_PERBUF _SFR_MEM16(0x0976) -#define TCD5_CCABUF _SFR_MEM16(0x0978) -#define TCD5_CCBBUF _SFR_MEM16(0x097A) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTD0_DATA _SFR_MEM8(0x09C0) -#define USARTD0_STATUS _SFR_MEM8(0x09C1) -#define USARTD0_CTRLA _SFR_MEM8(0x09C2) -#define USARTD0_CTRLB _SFR_MEM8(0x09C3) -#define USARTD0_CTRLC _SFR_MEM8(0x09C4) -#define USARTD0_CTRLD _SFR_MEM8(0x09C5) -#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09C6) -#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09C7) - - - -/*================== Bitfield Definitions ================== */ - -/* VPORT - Virtual Ports */ -/* VPORT.INTFLAGS bit masks and bit positions */ -#define VPORT_INT7IF_bm 0x80 /* Interrupt Pin 7 Flag bit mask. */ -#define VPORT_INT7IF_bp 7 /* Interrupt Pin 7 Flag bit position. */ - -#define VPORT_INT6IF_bm 0x40 /* Interrupt Pin 6 Flag bit mask. */ -#define VPORT_INT6IF_bp 6 /* Interrupt Pin 6 Flag bit position. */ - -#define VPORT_INT5IF_bm 0x20 /* Interrupt Pin 5 Flag bit mask. */ -#define VPORT_INT5IF_bp 5 /* Interrupt Pin 5 Flag bit position. */ - -#define VPORT_INT4IF_bm 0x10 /* Interrupt Pin 4 Flag bit mask. */ -#define VPORT_INT4IF_bp 4 /* Interrupt Pin 4 Flag bit position. */ - -#define VPORT_INT3IF_bm 0x08 /* Interrupt Pin 3 Flag bit mask. */ -#define VPORT_INT3IF_bp 3 /* Interrupt Pin 3 Flag bit position. */ - -#define VPORT_INT2IF_bm 0x04 /* Interrupt Pin 2 Flag bit mask. */ -#define VPORT_INT2IF_bp 2 /* Interrupt Pin 2 Flag bit position. */ - -#define VPORT_INT1IF_bm 0x02 /* Interrupt Pin 1 Flag bit mask. */ -#define VPORT_INT1IF_bp 1 /* Interrupt Pin 1 Flag bit position. */ - -#define VPORT_INT0IF_bm 0x01 /* Interrupt Pin 0 Flag bit mask. */ -#define VPORT_INT0IF_bp 0 /* Interrupt Pin 0 Flag bit position. */ - -/* XOCD - On-Chip Debug System */ -/* OCD.OCDR0 bit masks and bit positions */ -#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ -#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ -#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ -#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ -#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ -#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ -#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ -#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ -#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ -#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ -#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ -#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ -#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ -#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ -#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ -#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ -#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ -#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ - -/* OCD.OCDR1 bit masks and bit positions */ -/* OCD_OCDRD Predefined. */ -/* OCD_OCDRD Predefined. */ - -/* CPU - CPU */ -/* CPU.CCP bit masks and bit positions */ -#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ -#define CPU_CCP_gp 0 /* CCP signature group position. */ -#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ -#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ -#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ -#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ -#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ -#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ -#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ -#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ -#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ -#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ -#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ -#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ -#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ -#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ -#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ -#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ - -/* CPU.SREG bit masks and bit positions */ -#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ -#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ - -#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ -#define CPU_T_bp 6 /* Transfer Bit bit position. */ - -#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ -#define CPU_H_bp 5 /* Half Carry Flag bit position. */ - -#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ -#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ - -#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ -#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ - -#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ -#define CPU_N_bp 2 /* Negative Flag bit position. */ - -#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ -#define CPU_Z_bp 1 /* Zero Flag bit position. */ - -#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ -#define CPU_C_bp 0 /* Carry Flag bit position. */ - -/* CLK - Clock System */ -/* CLK.CTRL bit masks and bit positions */ -#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ -#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ -#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ -#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ -#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ -#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ -#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ -#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ - -/* CLK.PSCTRL bit masks and bit positions */ -#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ -#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ -#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ -#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ -#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ -#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ -#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ -#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ -#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ -#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ -#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ -#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ - -#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ -#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ -#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ -#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ -#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ -#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ - -/* CLK.LOCK bit masks and bit positions */ -#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ -#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ - -/* CLK.RTCCTRL bit masks and bit positions */ -#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ -#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ -#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ -#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ -#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ -#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ - -#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ -#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ - -/* PR.PRGEN bit masks and bit positions */ -#define PR_XCL_bm 0x80 /* XMEGA Custom Logic bit mask. */ -#define PR_XCL_bp 7 /* XMEGA Custom Logic bit position. */ - -#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ -#define PR_RTC_bp 2 /* Real-time Counter bit position. */ - -#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ -#define PR_EVSYS_bp 1 /* Event System bit position. */ - -#define PR_EDMA_bm 0x01 /* Enhanced DMA-Controller bit mask. */ -#define PR_EDMA_bp 0 /* Enhanced DMA-Controller bit position. */ - -/* PR.PRPA bit masks and bit positions */ -#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ -#define PR_DAC_bp 2 /* Port A DAC bit position. */ - -#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ -#define PR_ADC_bp 1 /* Port A ADC bit position. */ - -#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ -#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ - -/* PR.PRPC bit masks and bit positions */ -#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ -#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ - -#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ -#define PR_USART0_bp 4 /* Port C USART0 bit position. */ - -#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ -#define PR_SPI_bp 3 /* Port C SPI bit position. */ - -#define PR_HIRES_bm 0x04 /* Port C WEX bit mask. */ -#define PR_HIRES_bp 2 /* Port C WEX bit position. */ - -#define PR_TC5_bm 0x02 /* Port C Timer/Counter5 bit mask. */ -#define PR_TC5_bp 1 /* Port C Timer/Counter5 bit position. */ - -#define PR_TC4_bm 0x01 /* Port C Timer/Counter4 bit mask. */ -#define PR_TC4_bp 0 /* Port C Timer/Counter4 bit position. */ - -/* PR.PRPD bit masks and bit positions */ -/* PR_USART0 Predefined. */ -/* PR_USART0 Predefined. */ - -/* PR_TC5 Predefined. */ -/* PR_TC5 Predefined. */ - -/* SLEEP - Sleep Controller */ -/* SLEEP.CTRL bit masks and bit positions */ -#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ -#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ -#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ -#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ -#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ -#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ -#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ -#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ - -#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ -#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ - -/* OSC - Oscillator */ -/* OSC.CTRL bit masks and bit positions */ -#define OSC_RC8MLPM_bm 0x40 /* Internal 8 MHz RC Low Power Mode Enable bit mask. */ -#define OSC_RC8MLPM_bp 6 /* Internal 8 MHz RC Low Power Mode Enable bit position. */ - -#define OSC_RC8MEN_bm 0x20 /* Internal 8 MHz RC Oscillator Enable bit mask. */ -#define OSC_RC8MEN_bp 5 /* Internal 8 MHz RC Oscillator Enable bit position. */ - -#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ -#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ - -#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ -#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ - -#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ -#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ - -#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ -#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ - -#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ -#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ - -/* OSC.STATUS bit masks and bit positions */ -#define OSC_RC8MRDY_bm 0x20 /* Internal 8 MHz RC Oscillator Ready bit mask. */ -#define OSC_RC8MRDY_bp 5 /* Internal 8 MHz RC Oscillator Ready bit position. */ - -#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ -#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ - -#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ -#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ - -#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ -#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ - -#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ -#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ - -#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ -#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ - -/* OSC.XOSCCTRL bit masks and bit positions */ -#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ -#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ -#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ -#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ -#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ -#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ - -#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ -#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ - -#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ -#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ - -#define OSC_XOSCSEL_gm 0x1F /* External Oscillator Selection and Startup Time group mask. */ -#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ -#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ -#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ -#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ -#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ -#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ -#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ -#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ -#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ -#define OSC_XOSCSEL4_bm (1<<4) /* External Oscillator Selection and Startup Time bit 4 mask. */ -#define OSC_XOSCSEL4_bp 4 /* External Oscillator Selection and Startup Time bit 4 position. */ - -/* OSC.XOSCFAIL bit masks and bit positions */ -#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ -#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ - -#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ -#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ - -#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ -#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ - -#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ -#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ - -/* OSC.PLLCTRL bit masks and bit positions */ -#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ -#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ -#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ -#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ -#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ -#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ - -#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ -#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ - -#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ -#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ -#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ -#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ -#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ -#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ -#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ -#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ -#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ -#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ -#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ -#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ - -/* OSC.DFLLCTRL bit masks and bit positions */ -#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ -#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ -#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ -#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ -#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ -#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ - -/* OSC.RC8MCAL bit masks and bit positions */ -#define OSC_RC8MCAL_gm 0xFF /* Calibration Bits group mask. */ -#define OSC_RC8MCAL_gp 0 /* Calibration Bits group position. */ -#define OSC_RC8MCAL0_bm (1<<0) /* Calibration Bits bit 0 mask. */ -#define OSC_RC8MCAL0_bp 0 /* Calibration Bits bit 0 position. */ -#define OSC_RC8MCAL1_bm (1<<1) /* Calibration Bits bit 1 mask. */ -#define OSC_RC8MCAL1_bp 1 /* Calibration Bits bit 1 position. */ -#define OSC_RC8MCAL2_bm (1<<2) /* Calibration Bits bit 2 mask. */ -#define OSC_RC8MCAL2_bp 2 /* Calibration Bits bit 2 position. */ -#define OSC_RC8MCAL3_bm (1<<3) /* Calibration Bits bit 3 mask. */ -#define OSC_RC8MCAL3_bp 3 /* Calibration Bits bit 3 position. */ -#define OSC_RC8MCAL4_bm (1<<4) /* Calibration Bits bit 4 mask. */ -#define OSC_RC8MCAL4_bp 4 /* Calibration Bits bit 4 position. */ -#define OSC_RC8MCAL5_bm (1<<5) /* Calibration Bits bit 5 mask. */ -#define OSC_RC8MCAL5_bp 5 /* Calibration Bits bit 5 position. */ -#define OSC_RC8MCAL6_bm (1<<6) /* Calibration Bits bit 6 mask. */ -#define OSC_RC8MCAL6_bp 6 /* Calibration Bits bit 6 position. */ -#define OSC_RC8MCAL7_bm (1<<7) /* Calibration Bits bit 7 mask. */ -#define OSC_RC8MCAL7_bp 7 /* Calibration Bits bit 7 position. */ - -/* DFLL - DFLL */ -/* DFLL.CTRL bit masks and bit positions */ -#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ -#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ - -/* DFLL.CALA bit masks and bit positions */ -#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ -#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ -#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ -#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ -#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ -#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ -#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ -#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ -#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ -#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ -#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ -#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ -#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ -#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ -#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ -#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ - -/* DFLL.CALB bit masks and bit positions */ -#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ -#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ -#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ -#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ -#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ -#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ -#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ -#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ -#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ -#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ -#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ -#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ -#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ -#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ - -/* RST - Reset */ -/* RST.STATUS bit masks and bit positions */ -#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ -#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ - -#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ -#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ - -#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ -#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ - -#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ -#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ - -#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ -#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ - -#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ -#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ - -#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ -#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ - -/* RST.CTRL bit masks and bit positions */ -#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ -#define RST_SWRST_bp 0 /* Software Reset bit position. */ - -/* WDT - Watch-Dog Timer */ -/* WDT.CTRL bit masks and bit positions */ -#define WDT_PER_gm 0x3C /* Period group mask. */ -#define WDT_PER_gp 2 /* Period group position. */ -#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ -#define WDT_PER0_bp 2 /* Period bit 0 position. */ -#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ -#define WDT_PER1_bp 3 /* Period bit 1 position. */ -#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ -#define WDT_PER2_bp 4 /* Period bit 2 position. */ -#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ -#define WDT_PER3_bp 5 /* Period bit 3 position. */ - -#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ -#define WDT_ENABLE_bp 1 /* Enable bit position. */ - -#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ -#define WDT_CEN_bp 0 /* Change Enable bit position. */ - -/* WDT.WINCTRL bit masks and bit positions */ -#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ -#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ -#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ -#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ -#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ -#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ -#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ -#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ -#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ -#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ - -#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ -#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ - -#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ -#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ - -/* WDT.STATUS bit masks and bit positions */ -#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ -#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ - -/* MCU - MCU Control */ -/* MCU.ANAINIT bit masks and bit positions */ -#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ -#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ -#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ -#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ -#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ -#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ - -/* MCU.EVSYSLOCK bit masks and bit positions */ -#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ -#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ - -#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ -#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ - -/* MCU.WEXLOCK bit masks and bit positions */ -#define MCU_WEXCLOCK_bm 0x01 /* WeX on T/C C4 Lock bit mask. */ -#define MCU_WEXCLOCK_bp 0 /* WeX on T/C C4 Lock bit position. */ - -/* MCU.FAULTLOCK bit masks and bit positions */ -#define MCU_FAULTC5LOCK_bm 0x02 /* Fault on T/C C5 Lock bit mask. */ -#define MCU_FAULTC5LOCK_bp 1 /* Fault on T/C C5 Lock bit position. */ - -#define MCU_FAULTC4LOCK_bm 0x01 /* Fault on T/C C4 Lock bit mask. */ -#define MCU_FAULTC4LOCK_bp 0 /* Fault on T/C C4 Lock bit position. */ - -/* PMIC - Programmable Multi-level Interrupt Controller */ -/* PMIC.STATUS bit masks and bit positions */ -#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ -#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ - -#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ -#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ - -#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ -#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ - -#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ -#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ - -/* PMIC.INTPRI bit masks and bit positions */ -#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ -#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ -#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ -#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ -#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ -#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ -#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ -#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ -#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ -#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ -#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ -#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ -#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ -#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ -#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ -#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ -#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ -#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ - -/* PMIC.CTRL bit masks and bit positions */ -#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ -#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ - -#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ -#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ - -#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ -#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ - -#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ -#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ - -#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ -#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ - -/* PORTCFG - Port Configuration */ -/* PORTCFG.CLKOUT bit masks and bit positions */ -#define PORTCFG_CLKEVPIN_bm 0x80 /* Clock and Event Output Pin Select bit mask. */ -#define PORTCFG_CLKEVPIN_bp 7 /* Clock and Event Output Pin Select bit position. */ - -#define PORTCFG_RTCOUT_gm 0x60 /* RTC Clock Output Enable group mask. */ -#define PORTCFG_RTCOUT_gp 5 /* RTC Clock Output Enable group position. */ -#define PORTCFG_RTCOUT0_bm (1<<5) /* RTC Clock Output Enable bit 0 mask. */ -#define PORTCFG_RTCOUT0_bp 5 /* RTC Clock Output Enable bit 0 position. */ -#define PORTCFG_RTCOUT1_bm (1<<6) /* RTC Clock Output Enable bit 1 mask. */ -#define PORTCFG_RTCOUT1_bp 6 /* RTC Clock Output Enable bit 1 position. */ - -#define PORTCFG_CLKOUTSEL_gm 0x0C /* Clock Output Select group mask. */ -#define PORTCFG_CLKOUTSEL_gp 2 /* Clock Output Select group position. */ -#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Clock Output Select bit 0 mask. */ -#define PORTCFG_CLKOUTSEL0_bp 2 /* Clock Output Select bit 0 position. */ -#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Clock Output Select bit 1 mask. */ -#define PORTCFG_CLKOUTSEL1_bp 3 /* Clock Output Select bit 1 position. */ - -#define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */ -#define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */ -#define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */ -#define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */ -#define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */ -#define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */ - -/* PORTCFG.ACEVOUT bit masks and bit positions */ -#define PORTCFG_ACOUT_gm 0xC0 /* Analog Comparator Output Port group mask. */ -#define PORTCFG_ACOUT_gp 6 /* Analog Comparator Output Port group position. */ -#define PORTCFG_ACOUT0_bm (1<<6) /* Analog Comparator Output Port bit 0 mask. */ -#define PORTCFG_ACOUT0_bp 6 /* Analog Comparator Output Port bit 0 position. */ -#define PORTCFG_ACOUT1_bm (1<<7) /* Analog Comparator Output Port bit 1 mask. */ -#define PORTCFG_ACOUT1_bp 7 /* Analog Comparator Output Port bit 1 position. */ - -#define PORTCFG_EVOUT_gm 0x30 /* Event Channel Output Port group mask. */ -#define PORTCFG_EVOUT_gp 4 /* Event Channel Output Port group position. */ -#define PORTCFG_EVOUT0_bm (1<<4) /* Event Channel Output Port bit 0 mask. */ -#define PORTCFG_EVOUT0_bp 4 /* Event Channel Output Port bit 0 position. */ -#define PORTCFG_EVOUT1_bm (1<<5) /* Event Channel Output Port bit 1 mask. */ -#define PORTCFG_EVOUT1_bp 5 /* Event Channel Output Port bit 1 position. */ - -#define PORTCFG_EVASYEN_bm 0x08 /* Asynchronous Event Enabled bit mask. */ -#define PORTCFG_EVASYEN_bp 3 /* Asynchronous Event Enabled bit position. */ - -#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Channel Output Selection group mask. */ -#define PORTCFG_EVOUTSEL_gp 0 /* Event Channel Output Selection group position. */ -#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Channel Output Selection bit 0 mask. */ -#define PORTCFG_EVOUTSEL0_bp 0 /* Event Channel Output Selection bit 0 position. */ -#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Channel Output Selection bit 1 mask. */ -#define PORTCFG_EVOUTSEL1_bp 1 /* Event Channel Output Selection bit 1 position. */ -#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Channel Output Selection bit 2 mask. */ -#define PORTCFG_EVOUTSEL2_bp 2 /* Event Channel Output Selection bit 2 position. */ - -/* PORTCFG.SRLCTRL bit masks and bit positions */ -#define PORTCFG_SRLENRA_bm 0x01 /* Slew Rate Limit Enable on PORTA bit mask. */ -#define PORTCFG_SRLENRA_bp 0 /* Slew Rate Limit Enable on PORTA bit position. */ - -#define PORTCFG_SRLENRC_bm 0x04 /* Slew Rate Limit Enable on PORTC bit mask. */ -#define PORTCFG_SRLENRC_bp 2 /* Slew Rate Limit Enable on PORTC bit position. */ - -#define PORTCFG_SRLENRD_bm 0x08 /* Slew Rate Limit Enable on PORTD bit mask. */ -#define PORTCFG_SRLENRD_bp 3 /* Slew Rate Limit Enable on PORTD bit position. */ - -#define PORTCFG_SRLENRR_bm 0x80 /* Slew Rate Limit Enable on PORTR bit mask. */ -#define PORTCFG_SRLENRR_bp 7 /* Slew Rate Limit Enable on PORTR bit position. */ - -/* CRC - Cyclic Redundancy Checker */ -/* CRC.CTRL bit masks and bit positions */ -#define CRC_RESET_gm 0xC0 /* Reset group mask. */ -#define CRC_RESET_gp 6 /* Reset group position. */ -#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ -#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ -#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ -#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ - -#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ -#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ - -#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ -#define CRC_SOURCE_gp 0 /* Input Source group position. */ -#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ -#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ -#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ -#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ -#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ -#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ -#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ -#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ - -/* CRC.STATUS bit masks and bit positions */ -#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ -#define CRC_ZERO_bp 1 /* Zero detection bit position. */ - -#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ -#define CRC_BUSY_bp 0 /* Busy bit position. */ - -/* EDMA - Enhanced DMA Controller */ -/* EDMA.CTRL bit masks and bit positions */ -#define EDMA_ENABLE_bm 0x80 /* Enable bit mask. */ -#define EDMA_ENABLE_bp 7 /* Enable bit position. */ - -#define EDMA_RESET_bm 0x40 /* Software Reset bit mask. */ -#define EDMA_RESET_bp 6 /* Software Reset bit position. */ - -#define EDMA_CHMODE_gm 0x30 /* Channel Mode group mask. */ -#define EDMA_CHMODE_gp 4 /* Channel Mode group position. */ -#define EDMA_CHMODE0_bm (1<<4) /* Channel Mode bit 0 mask. */ -#define EDMA_CHMODE0_bp 4 /* Channel Mode bit 0 position. */ -#define EDMA_CHMODE1_bm (1<<5) /* Channel Mode bit 1 mask. */ -#define EDMA_CHMODE1_bp 5 /* Channel Mode bit 1 position. */ - -#define EDMA_DBUFMODE_gm 0x0C /* Double Buffer Mode group mask. */ -#define EDMA_DBUFMODE_gp 2 /* Double Buffer Mode group position. */ -#define EDMA_DBUFMODE0_bm (1<<2) /* Double Buffer Mode bit 0 mask. */ -#define EDMA_DBUFMODE0_bp 2 /* Double Buffer Mode bit 0 position. */ -#define EDMA_DBUFMODE1_bm (1<<3) /* Double Buffer Mode bit 1 mask. */ -#define EDMA_DBUFMODE1_bp 3 /* Double Buffer Mode bit 1 position. */ - -#define EDMA_PRIMODE_gm 0x03 /* Priority Mode group mask. */ -#define EDMA_PRIMODE_gp 0 /* Priority Mode group position. */ -#define EDMA_PRIMODE0_bm (1<<0) /* Priority Mode bit 0 mask. */ -#define EDMA_PRIMODE0_bp 0 /* Priority Mode bit 0 position. */ -#define EDMA_PRIMODE1_bm (1<<1) /* Priority Mode bit 1 mask. */ -#define EDMA_PRIMODE1_bp 1 /* Priority Mode bit 1 position. */ - -/* EDMA.INTFLAGS bit masks and bit positions */ -#define EDMA_CH3ERRIF_bm 0x80 /* Channel 3 Transaction Error Interrupt Flag bit mask. */ -#define EDMA_CH3ERRIF_bp 7 /* Channel 3 Transaction Error Interrupt Flag bit position. */ - -#define EDMA_CH2ERRIF_bm 0x40 /* Channel 2 Transaction Error Interrupt Flag bit mask. */ -#define EDMA_CH2ERRIF_bp 6 /* Channel 2 Transaction Error Interrupt Flag bit position. */ - -#define EDMA_CH1ERRIF_bm 0x20 /* Channel 1 Transaction Error Interrupt Flag bit mask. */ -#define EDMA_CH1ERRIF_bp 5 /* Channel 1 Transaction Error Interrupt Flag bit position. */ - -#define EDMA_CH0ERRIF_bm 0x10 /* Channel 0 Transaction Error Interrupt Flag bit mask. */ -#define EDMA_CH0ERRIF_bp 4 /* Channel 0 Transaction Error Interrupt Flag bit position. */ - -#define EDMA_CH3TRNFIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ -#define EDMA_CH3TRNFIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ - -#define EDMA_CH2TRNFIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ -#define EDMA_CH2TRNFIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ - -#define EDMA_CH1TRNFIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ -#define EDMA_CH1TRNFIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ - -#define EDMA_CH0TRNFIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ -#define EDMA_CH0TRNFIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ - -/* EDMA.STATUS bit masks and bit positions */ -#define EDMA_CH3BUSY_bm 0x80 /* Channel 3 Busy Flag bit mask. */ -#define EDMA_CH3BUSY_bp 7 /* Channel 3 Busy Flag bit position. */ - -#define EDMA_CH2BUSY_bm 0x40 /* Channel 2 Busy Flag bit mask. */ -#define EDMA_CH2BUSY_bp 6 /* Channel 2 Busy Flag bit position. */ - -#define EDMA_CH1BUSY_bm 0x20 /* Channel 1 Busy Flag bit mask. */ -#define EDMA_CH1BUSY_bp 5 /* Channel 1 Busy Flag bit position. */ - -#define EDMA_CH0BUSY_bm 0x10 /* Channel 0 Busy Flag bit mask. */ -#define EDMA_CH0BUSY_bp 4 /* Channel 0 Busy Flag bit position. */ - -#define EDMA_CH3PEND_bm 0x08 /* Channel 3 Pending Flag bit mask. */ -#define EDMA_CH3PEND_bp 3 /* Channel 3 Pending Flag bit position. */ - -#define EDMA_CH2PEND_bm 0x04 /* Channel 2 Pending Flag bit mask. */ -#define EDMA_CH2PEND_bp 2 /* Channel 2 Pending Flag bit position. */ - -#define EDMA_CH1PEND_bm 0x02 /* Channel 1 Pending Flag bit mask. */ -#define EDMA_CH1PEND_bp 1 /* Channel 1 Pending Flag bit position. */ - -#define EDMA_CH0PEND_bm 0x01 /* Channel 0 Pending Flag bit mask. */ -#define EDMA_CH0PEND_bp 0 /* Channel 0 Pending Flag bit position. */ - -/* EDMA_CH.CTRLA bit masks and bit positions */ -#define EDMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ -#define EDMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ - -#define EDMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ -#define EDMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ - -#define EDMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ -#define EDMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ - -#define EDMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ -#define EDMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ - -#define EDMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ -#define EDMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ - -#define EDMA_CH_BURSTLEN_bm 0x01 /* Channel 2-bytes Burst Length bit mask. */ -#define EDMA_CH_BURSTLEN_bp 0 /* Channel 2-bytes Burst Length bit position. */ - -/* EDMA_CH.CTRLB bit masks and bit positions */ -#define EDMA_CH_CHBUSY_bm 0x80 /* Channel Block Transfer Busy bit mask. */ -#define EDMA_CH_CHBUSY_bp 7 /* Channel Block Transfer Busy bit position. */ - -#define EDMA_CH_CHPEND_bm 0x40 /* Channel Block Transfer Pending bit mask. */ -#define EDMA_CH_CHPEND_bp 6 /* Channel Block Transfer Pending bit position. */ - -#define EDMA_CH_ERRIF_bm 0x20 /* Channel Transaction Error Interrupt Flag bit mask. */ -#define EDMA_CH_ERRIF_bp 5 /* Channel Transaction Error Interrupt Flag bit position. */ - -#define EDMA_CH_TRNIF_bm 0x10 /* Channel Transaction Complete Interrup Flag bit mask. */ -#define EDMA_CH_TRNIF_bp 4 /* Channel Transaction Complete Interrup Flag bit position. */ - -#define EDMA_CH_ERRINTLVL_gm 0x0C /* Channel Transaction Error Interrupt Level group mask. */ -#define EDMA_CH_ERRINTLVL_gp 2 /* Channel Transaction Error Interrupt Level group position. */ -#define EDMA_CH_ERRINTLVL0_bm (1<<2) /* Channel Transaction Error Interrupt Level bit 0 mask. */ -#define EDMA_CH_ERRINTLVL0_bp 2 /* Channel Transaction Error Interrupt Level bit 0 position. */ -#define EDMA_CH_ERRINTLVL1_bm (1<<3) /* Channel Transaction Error Interrupt Level bit 1 mask. */ -#define EDMA_CH_ERRINTLVL1_bp 3 /* Channel Transaction Error Interrupt Level bit 1 position. */ - -#define EDMA_CH_TRNINTLVL_gm 0x03 /* Channel Transaction Complete Interrupt Level group mask. */ -#define EDMA_CH_TRNINTLVL_gp 0 /* Channel Transaction Complete Interrupt Level group position. */ -#define EDMA_CH_TRNINTLVL0_bm (1<<0) /* Channel Transaction Complete Interrupt Level bit 0 mask. */ -#define EDMA_CH_TRNINTLVL0_bp 0 /* Channel Transaction Complete Interrupt Level bit 0 position. */ -#define EDMA_CH_TRNINTLVL1_bm (1<<1) /* Channel Transaction Complete Interrupt Level bit 1 mask. */ -#define EDMA_CH_TRNINTLVL1_bp 1 /* Channel Transaction Complete Interrupt Level bit 1 position. */ - -/* EDMA_CH.ADDRCTRL bit masks and bit positions */ -#define EDMA_CH_RELOAD_gm 0x30 /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. group mask. */ -#define EDMA_CH_RELOAD_gp 4 /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. group position. */ -#define EDMA_CH_RELOAD0_bm (1<<4) /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. bit 0 mask. */ -#define EDMA_CH_RELOAD0_bp 4 /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. bit 0 position. */ -#define EDMA_CH_RELOAD1_bm (1<<5) /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. bit 1 mask. */ -#define EDMA_CH_RELOAD1_bp 5 /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. bit 1 position. */ - -#define EDMA_CH_DIR_gm 0x07 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. group mask. */ -#define EDMA_CH_DIR_gp 0 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. group position. */ -#define EDMA_CH_DIR0_bm (1<<0) /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 0 mask. */ -#define EDMA_CH_DIR0_bp 0 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 0 position. */ -#define EDMA_CH_DIR1_bm (1<<1) /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 1 mask. */ -#define EDMA_CH_DIR1_bp 1 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 1 position. */ -#define EDMA_CH_DIR2_bm (1<<2) /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 2 mask. */ -#define EDMA_CH_DIR2_bp 2 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 2 position. */ - -/* EDMA_CH.DESTADDRCTRL bit masks and bit positions */ -#define EDMA_CH_DESTRELOAD_gm 0x30 /* Destination Address Reload for Standard Channels Only. group mask. */ -#define EDMA_CH_DESTRELOAD_gp 4 /* Destination Address Reload for Standard Channels Only. group position. */ -#define EDMA_CH_DESTRELOAD0_bm (1<<4) /* Destination Address Reload for Standard Channels Only. bit 0 mask. */ -#define EDMA_CH_DESTRELOAD0_bp 4 /* Destination Address Reload for Standard Channels Only. bit 0 position. */ -#define EDMA_CH_DESTRELOAD1_bm (1<<5) /* Destination Address Reload for Standard Channels Only. bit 1 mask. */ -#define EDMA_CH_DESTRELOAD1_bp 5 /* Destination Address Reload for Standard Channels Only. bit 1 position. */ - -#define EDMA_CH_DESTDIR_gm 0x07 /* Destination Address Mode for Standard Channels Only. group mask. */ -#define EDMA_CH_DESTDIR_gp 0 /* Destination Address Mode for Standard Channels Only. group position. */ -#define EDMA_CH_DESTDIR0_bm (1<<0) /* Destination Address Mode for Standard Channels Only. bit 0 mask. */ -#define EDMA_CH_DESTDIR0_bp 0 /* Destination Address Mode for Standard Channels Only. bit 0 position. */ -#define EDMA_CH_DESTDIR1_bm (1<<1) /* Destination Address Mode for Standard Channels Only. bit 1 mask. */ -#define EDMA_CH_DESTDIR1_bp 1 /* Destination Address Mode for Standard Channels Only. bit 1 position. */ -#define EDMA_CH_DESTDIR2_bm (1<<2) /* Destination Address Mode for Standard Channels Only. bit 2 mask. */ -#define EDMA_CH_DESTDIR2_bp 2 /* Destination Address Mode for Standard Channels Only. bit 2 position. */ - -/* EDMA_CH.TRIGSRC bit masks and bit positions */ -#define EDMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ -#define EDMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ -#define EDMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ -#define EDMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ -#define EDMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ -#define EDMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ -#define EDMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ -#define EDMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ -#define EDMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ -#define EDMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ -#define EDMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ -#define EDMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ -#define EDMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ -#define EDMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ -#define EDMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ -#define EDMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ -#define EDMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ -#define EDMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ - -/* EVSYS - Event System */ -/* EVSYS.CH0MUX bit masks and bit positions */ -#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ -#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ -#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ -#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ -#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ -#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ -#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ -#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ -#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ -#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ -#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ -#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ -#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ -#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ -#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ -#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ -#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ -#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ - -/* EVSYS.CH1MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH2MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH3MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH4MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH5MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH6MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH7MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH0CTRL bit masks and bit positions */ -#define EVSYS_ROTARY_bm 0x80 /* Rotary Decoder Enable bit mask. */ -#define EVSYS_ROTARY_bp 7 /* Rotary Decoder Enable bit position. */ - -#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ -#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ -#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ -#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ -#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ -#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ - -#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ -#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ - -#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ -#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ - -#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ -#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ -#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ -#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ -#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ -#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ -#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ -#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ - -/* EVSYS.CH1CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH2CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH3CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH4CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH5CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH6CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH7CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.DFCTRL bit masks and bit positions */ -#define EVSYS_PRESCFILT_gm 0xF0 /* Prescaler Filter group mask. */ -#define EVSYS_PRESCFILT_gp 4 /* Prescaler Filter group position. */ -#define EVSYS_PRESCFILT0_bm (1<<4) /* Prescaler Filter bit 0 mask. */ -#define EVSYS_PRESCFILT0_bp 4 /* Prescaler Filter bit 0 position. */ -#define EVSYS_PRESCFILT1_bm (1<<5) /* Prescaler Filter bit 1 mask. */ -#define EVSYS_PRESCFILT1_bp 5 /* Prescaler Filter bit 1 position. */ -#define EVSYS_PRESCFILT2_bm (1<<6) /* Prescaler Filter bit 2 mask. */ -#define EVSYS_PRESCFILT2_bp 6 /* Prescaler Filter bit 2 position. */ -#define EVSYS_PRESCFILT3_bm (1<<7) /* Prescaler Filter bit 3 mask. */ -#define EVSYS_PRESCFILT3_bp 7 /* Prescaler Filter bit 3 position. */ - -#define EVSYS_FILTSEL_bm 0x08 /* Prescaler Filter Select bit mask. */ -#define EVSYS_FILTSEL_bp 3 /* Prescaler Filter Select bit position. */ - -#define EVSYS_PRESC_gm 0x07 /* Prescaler group mask. */ -#define EVSYS_PRESC_gp 0 /* Prescaler group position. */ -#define EVSYS_PRESC0_bm (1<<0) /* Prescaler bit 0 mask. */ -#define EVSYS_PRESC0_bp 0 /* Prescaler bit 0 position. */ -#define EVSYS_PRESC1_bm (1<<1) /* Prescaler bit 1 mask. */ -#define EVSYS_PRESC1_bp 1 /* Prescaler bit 1 position. */ -#define EVSYS_PRESC2_bm (1<<2) /* Prescaler bit 2 mask. */ -#define EVSYS_PRESC2_bp 2 /* Prescaler bit 2 position. */ - -/* NVM - Non Volatile Memory Controller */ -/* NVM.CMD bit masks and bit positions */ -#define NVM_CMD_gm 0x7F /* Command group mask. */ -#define NVM_CMD_gp 0 /* Command group position. */ -#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define NVM_CMD0_bp 0 /* Command bit 0 position. */ -#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define NVM_CMD1_bp 1 /* Command bit 1 position. */ -#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ -#define NVM_CMD2_bp 2 /* Command bit 2 position. */ -#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ -#define NVM_CMD3_bp 3 /* Command bit 3 position. */ -#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ -#define NVM_CMD4_bp 4 /* Command bit 4 position. */ -#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ -#define NVM_CMD5_bp 5 /* Command bit 5 position. */ -#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ -#define NVM_CMD6_bp 6 /* Command bit 6 position. */ - -/* NVM.CTRLA bit masks and bit positions */ -#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ -#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ - -/* NVM.CTRLB bit masks and bit positions */ -#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ -#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ - -#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ -#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ - -/* NVM.INTCTRL bit masks and bit positions */ -#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ -#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ -#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ -#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ -#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ -#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ - -#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ -#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ -#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ -#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ -#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ -#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ - -/* NVM.STATUS bit masks and bit positions */ -#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ -#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ - -#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ -#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ - -#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ -#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ - -#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ -#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ - -/* NVM.LOCKBITS bit masks and bit positions */ -#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ - -#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ - -#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ - -#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ -#define NVM_LB_gp 0 /* Lock Bits group position. */ -#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ -#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ - -/* ADC - Analog/Digital Converter */ -/* ADC_CH.CTRL bit masks and bit positions */ -#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ -#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ - -#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ -#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ -#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ -#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ -#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ -#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ -#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ -#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ - -#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ -#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ -#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ -#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ -#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ -#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ - -/* ADC_CH.MUXCTRL bit masks and bit positions */ -#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC Input group mask. */ -#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC Input group position. */ -#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC Input bit 0 mask. */ -#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC Input bit 0 position. */ -#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC Input bit 1 mask. */ -#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC Input bit 1 position. */ -#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC Input bit 2 mask. */ -#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC Input bit 2 position. */ -#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC Input bit 3 mask. */ -#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC Input bit 3 position. */ - -#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC Input group mask. */ -#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC Input group position. */ -#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC Input bit 0 mask. */ -#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC Input bit 0 position. */ -#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC Input bit 1 mask. */ -#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC Input bit 1 position. */ -#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC Input bit 2 mask. */ -#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC Input bit 2 position. */ -#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC Input bit 3 mask. */ -#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC Input bit 3 position. */ - -#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC Input group mask. */ -#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC Input group position. */ -#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC Input bit 0 mask. */ -#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC Input bit 0 position. */ -#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC Input bit 1 mask. */ -#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC Input bit 1 position. */ - -#define ADC_CH_MUXNEGL_gm 0x03 /* MUX selection on Negative ADC Input Gain on 4 LSB pins group mask. */ -#define ADC_CH_MUXNEGL_gp 0 /* MUX selection on Negative ADC Input Gain on 4 LSB pins group position. */ -#define ADC_CH_MUXNEGL0_bm (1<<0) /* MUX selection on Negative ADC Input Gain on 4 LSB pins bit 0 mask. */ -#define ADC_CH_MUXNEGL0_bp 0 /* MUX selection on Negative ADC Input Gain on 4 LSB pins bit 0 position. */ -#define ADC_CH_MUXNEGL1_bm (1<<1) /* MUX selection on Negative ADC Input Gain on 4 LSB pins bit 1 mask. */ -#define ADC_CH_MUXNEGL1_bp 1 /* MUX selection on Negative ADC Input Gain on 4 LSB pins bit 1 position. */ - -#define ADC_CH_MUXNEGH_gm 0x03 /* MUX selection on Negative ADC Input Gain on 4 MSB pins group mask. */ -#define ADC_CH_MUXNEGH_gp 0 /* MUX selection on Negative ADC Input Gain on 4 MSB pins group position. */ -#define ADC_CH_MUXNEGH0_bm (1<<0) /* MUX selection on Negative ADC Input Gain on 4 MSB pins bit 0 mask. */ -#define ADC_CH_MUXNEGH0_bp 0 /* MUX selection on Negative ADC Input Gain on 4 MSB pins bit 0 position. */ -#define ADC_CH_MUXNEGH1_bm (1<<1) /* MUX selection on Negative ADC Input Gain on 4 MSB pins bit 1 mask. */ -#define ADC_CH_MUXNEGH1_bp 1 /* MUX selection on Negative ADC Input Gain on 4 MSB pins bit 1 position. */ - -/* ADC_CH.INTCTRL bit masks and bit positions */ -#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ -#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ -#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ -#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ -#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ -#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ - -#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ -#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ - -/* ADC_CH.INTFLAGS bit masks and bit positions */ -#define ADC_CH_IF_bm 0x01 /* Channel Interrupt Flag bit mask. */ -#define ADC_CH_IF_bp 0 /* Channel Interrupt Flag bit position. */ - -/* ADC_CH.SCAN bit masks and bit positions */ -#define ADC_CH_INPUTOFFSET_gm 0xF0 /* Positive MUX Setting Offset group mask. */ -#define ADC_CH_INPUTOFFSET_gp 4 /* Positive MUX Setting Offset group position. */ -#define ADC_CH_INPUTOFFSET0_bm (1<<4) /* Positive MUX Setting Offset bit 0 mask. */ -#define ADC_CH_INPUTOFFSET0_bp 4 /* Positive MUX Setting Offset bit 0 position. */ -#define ADC_CH_INPUTOFFSET1_bm (1<<5) /* Positive MUX Setting Offset bit 1 mask. */ -#define ADC_CH_INPUTOFFSET1_bp 5 /* Positive MUX Setting Offset bit 1 position. */ -#define ADC_CH_INPUTOFFSET2_bm (1<<6) /* Positive MUX Setting Offset bit 2 mask. */ -#define ADC_CH_INPUTOFFSET2_bp 6 /* Positive MUX Setting Offset bit 2 position. */ -#define ADC_CH_INPUTOFFSET3_bm (1<<7) /* Positive MUX Setting Offset bit 3 mask. */ -#define ADC_CH_INPUTOFFSET3_bp 7 /* Positive MUX Setting Offset bit 3 position. */ - -#define ADC_CH_INPUTSCAN_gm 0x0F /* Number of Channels Included in Scan group mask. */ -#define ADC_CH_INPUTSCAN_gp 0 /* Number of Channels Included in Scan group position. */ -#define ADC_CH_INPUTSCAN0_bm (1<<0) /* Number of Channels Included in Scan bit 0 mask. */ -#define ADC_CH_INPUTSCAN0_bp 0 /* Number of Channels Included in Scan bit 0 position. */ -#define ADC_CH_INPUTSCAN1_bm (1<<1) /* Number of Channels Included in Scan bit 1 mask. */ -#define ADC_CH_INPUTSCAN1_bp 1 /* Number of Channels Included in Scan bit 1 position. */ -#define ADC_CH_INPUTSCAN2_bm (1<<2) /* Number of Channels Included in Scan bit 2 mask. */ -#define ADC_CH_INPUTSCAN2_bp 2 /* Number of Channels Included in Scan bit 2 position. */ -#define ADC_CH_INPUTSCAN3_bm (1<<3) /* Number of Channels Included in Scan bit 3 mask. */ -#define ADC_CH_INPUTSCAN3_bp 3 /* Number of Channels Included in Scan bit 3 position. */ - -/* ADC_CH.CORRCTRL bit masks and bit positions */ -#define ADC_CH_CORREN_bm 0x01 /* Correction Enable bit mask. */ -#define ADC_CH_CORREN_bp 0 /* Correction Enable bit position. */ - -/* ADC_CH.OFFSETCORR1 bit masks and bit positions */ -#define ADC_CH_OFFSETCORR_gm 0x0F /* Offset Correction Byte 1 group mask. */ -#define ADC_CH_OFFSETCORR_gp 0 /* Offset Correction Byte 1 group position. */ -#define ADC_CH_OFFSETCORR0_bm (1<<0) /* Offset Correction Byte 1 bit 0 mask. */ -#define ADC_CH_OFFSETCORR0_bp 0 /* Offset Correction Byte 1 bit 0 position. */ -#define ADC_CH_OFFSETCORR1_bm (1<<1) /* Offset Correction Byte 1 bit 1 mask. */ -#define ADC_CH_OFFSETCORR1_bp 1 /* Offset Correction Byte 1 bit 1 position. */ -#define ADC_CH_OFFSETCORR2_bm (1<<2) /* Offset Correction Byte 1 bit 2 mask. */ -#define ADC_CH_OFFSETCORR2_bp 2 /* Offset Correction Byte 1 bit 2 position. */ -#define ADC_CH_OFFSETCORR3_bm (1<<3) /* Offset Correction Byte 1 bit 3 mask. */ -#define ADC_CH_OFFSETCORR3_bp 3 /* Offset Correction Byte 1 bit 3 position. */ - -/* ADC_CH.GAINCORR1 bit masks and bit positions */ -#define ADC_CH_GAINCORR_gm 0x0F /* Gain Correction Byte 1 group mask. */ -#define ADC_CH_GAINCORR_gp 0 /* Gain Correction Byte 1 group position. */ -#define ADC_CH_GAINCORR0_bm (1<<0) /* Gain Correction Byte 1 bit 0 mask. */ -#define ADC_CH_GAINCORR0_bp 0 /* Gain Correction Byte 1 bit 0 position. */ -#define ADC_CH_GAINCORR1_bm (1<<1) /* Gain Correction Byte 1 bit 1 mask. */ -#define ADC_CH_GAINCORR1_bp 1 /* Gain Correction Byte 1 bit 1 position. */ -#define ADC_CH_GAINCORR2_bm (1<<2) /* Gain Correction Byte 1 bit 2 mask. */ -#define ADC_CH_GAINCORR2_bp 2 /* Gain Correction Byte 1 bit 2 position. */ -#define ADC_CH_GAINCORR3_bm (1<<3) /* Gain Correction Byte 1 bit 3 mask. */ -#define ADC_CH_GAINCORR3_bp 3 /* Gain Correction Byte 1 bit 3 position. */ - -/* ADC_CH.AVGCTRL bit masks and bit positions */ -#define ADC_CH_RIGHTSHIFT_gm 0x70 /* Right Shift group mask. */ -#define ADC_CH_RIGHTSHIFT_gp 4 /* Right Shift group position. */ -#define ADC_CH_RIGHTSHIFT0_bm (1<<4) /* Right Shift bit 0 mask. */ -#define ADC_CH_RIGHTSHIFT0_bp 4 /* Right Shift bit 0 position. */ -#define ADC_CH_RIGHTSHIFT1_bm (1<<5) /* Right Shift bit 1 mask. */ -#define ADC_CH_RIGHTSHIFT1_bp 5 /* Right Shift bit 1 position. */ -#define ADC_CH_RIGHTSHIFT2_bm (1<<6) /* Right Shift bit 2 mask. */ -#define ADC_CH_RIGHTSHIFT2_bp 6 /* Right Shift bit 2 position. */ - -#define ADC_CH_SAMPNUM_gm 0x0F /* Averaged Number of Samples group mask. */ -#define ADC_CH_SAMPNUM_gp 0 /* Averaged Number of Samples group position. */ -#define ADC_CH_SAMPNUM0_bm (1<<0) /* Averaged Number of Samples bit 0 mask. */ -#define ADC_CH_SAMPNUM0_bp 0 /* Averaged Number of Samples bit 0 position. */ -#define ADC_CH_SAMPNUM1_bm (1<<1) /* Averaged Number of Samples bit 1 mask. */ -#define ADC_CH_SAMPNUM1_bp 1 /* Averaged Number of Samples bit 1 position. */ -#define ADC_CH_SAMPNUM2_bm (1<<2) /* Averaged Number of Samples bit 2 mask. */ -#define ADC_CH_SAMPNUM2_bp 2 /* Averaged Number of Samples bit 2 position. */ -#define ADC_CH_SAMPNUM3_bm (1<<3) /* Averaged Number of Samples bit 3 mask. */ -#define ADC_CH_SAMPNUM3_bp 3 /* Averaged Number of Samples bit 3 position. */ - -/* ADC.CTRLA bit masks and bit positions */ -#define ADC_START_bm 0x04 /* Start Conversion bit mask. */ -#define ADC_START_bp 2 /* Start Conversion bit position. */ - -#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ -#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ - -#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ -#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ - -/* ADC.CTRLB bit masks and bit positions */ -#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ -#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ -#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ -#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ -#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ -#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ - -#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ -#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ - -#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ -#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ - -#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ -#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ -#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ -#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ -#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ -#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ - -/* ADC.REFCTRL bit masks and bit positions */ -#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ -#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ -#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ -#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ -#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ -#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ -#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ -#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ - -#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ -#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ - -#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ -#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ - -/* ADC.EVCTRL bit masks and bit positions */ -#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ -#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ -#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ -#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ -#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ -#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ -#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ -#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ - -#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ -#define ADC_EVACT_gp 0 /* Event Action Select group position. */ -#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ -#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ -#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ -#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ -#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ -#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ - -/* ADC.PRESCALER bit masks and bit positions */ -#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ -#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ -#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ -#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ -#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ -#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ -#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ -#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ - -/* ADC.INTFLAGS bit masks and bit positions */ -#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ -#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ - -/* ADC.SAMPCTRL bit masks and bit positions */ -#define ADC_SAMPVAL_gm 0x3F /* Sampling time control register group mask. */ -#define ADC_SAMPVAL_gp 0 /* Sampling time control register group position. */ -#define ADC_SAMPVAL0_bm (1<<0) /* Sampling time control register bit 0 mask. */ -#define ADC_SAMPVAL0_bp 0 /* Sampling time control register bit 0 position. */ -#define ADC_SAMPVAL1_bm (1<<1) /* Sampling time control register bit 1 mask. */ -#define ADC_SAMPVAL1_bp 1 /* Sampling time control register bit 1 position. */ -#define ADC_SAMPVAL2_bm (1<<2) /* Sampling time control register bit 2 mask. */ -#define ADC_SAMPVAL2_bp 2 /* Sampling time control register bit 2 position. */ -#define ADC_SAMPVAL3_bm (1<<3) /* Sampling time control register bit 3 mask. */ -#define ADC_SAMPVAL3_bp 3 /* Sampling time control register bit 3 position. */ -#define ADC_SAMPVAL4_bm (1<<4) /* Sampling time control register bit 4 mask. */ -#define ADC_SAMPVAL4_bp 4 /* Sampling time control register bit 4 position. */ -#define ADC_SAMPVAL5_bm (1<<5) /* Sampling time control register bit 5 mask. */ -#define ADC_SAMPVAL5_bp 5 /* Sampling time control register bit 5 position. */ - -/* DAC - Digital/Analog Converter */ -/* DAC.CTRLA bit masks and bit positions */ -#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ -#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ - -#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ -#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ - -#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ -#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ - -#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ -#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ - -#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ -#define DAC_ENABLE_bp 0 /* Enable bit position. */ - -/* DAC.CTRLB bit masks and bit positions */ -#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ -#define DAC_CHSEL_gp 5 /* Channel Select group position. */ -#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ -#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ -#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ -#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ - -#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ -#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ - -#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ -#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ - -/* DAC.CTRLC bit masks and bit positions */ -#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ -#define DAC_REFSEL_gp 3 /* Reference Select group position. */ -#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ -#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ -#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ -#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ - -#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ -#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ - -/* DAC.EVCTRL bit masks and bit positions */ -#define DAC_EVSPLIT_bm 0x08 /* Separate Event Channel Input for Channel 1 bit mask. */ -#define DAC_EVSPLIT_bp 3 /* Separate Event Channel Input for Channel 1 bit position. */ - -#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ -#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ -#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ -#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ -#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ -#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ -#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ -#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ - -/* DAC.STATUS bit masks and bit positions */ -#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ -#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ - -#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ -#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ - -/* DAC.CH0GAINCAL bit masks and bit positions */ -#define DAC_CH0GAINCAL_gm 0x7F /* Gain Calibration group mask. */ -#define DAC_CH0GAINCAL_gp 0 /* Gain Calibration group position. */ -#define DAC_CH0GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ -#define DAC_CH0GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ -#define DAC_CH0GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ -#define DAC_CH0GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ -#define DAC_CH0GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ -#define DAC_CH0GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ -#define DAC_CH0GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ -#define DAC_CH0GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ -#define DAC_CH0GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ -#define DAC_CH0GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ -#define DAC_CH0GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ -#define DAC_CH0GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ -#define DAC_CH0GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ -#define DAC_CH0GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ - -/* DAC.CH0OFFSETCAL bit masks and bit positions */ -#define DAC_CH0OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ -#define DAC_CH0OFFSETCAL_gp 0 /* Offset Calibration group position. */ -#define DAC_CH0OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ -#define DAC_CH0OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ -#define DAC_CH0OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ -#define DAC_CH0OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ -#define DAC_CH0OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ -#define DAC_CH0OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ -#define DAC_CH0OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ -#define DAC_CH0OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ -#define DAC_CH0OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ -#define DAC_CH0OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ -#define DAC_CH0OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ -#define DAC_CH0OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ -#define DAC_CH0OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ -#define DAC_CH0OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ - -/* DAC.CH1GAINCAL bit masks and bit positions */ -#define DAC_CH1GAINCAL_gm 0x7F /* Gain Calibration group mask. */ -#define DAC_CH1GAINCAL_gp 0 /* Gain Calibration group position. */ -#define DAC_CH1GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ -#define DAC_CH1GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ -#define DAC_CH1GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ -#define DAC_CH1GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ -#define DAC_CH1GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ -#define DAC_CH1GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ -#define DAC_CH1GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ -#define DAC_CH1GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ -#define DAC_CH1GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ -#define DAC_CH1GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ -#define DAC_CH1GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ -#define DAC_CH1GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ -#define DAC_CH1GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ -#define DAC_CH1GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ - -/* DAC.CH1OFFSETCAL bit masks and bit positions */ -#define DAC_CH1OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ -#define DAC_CH1OFFSETCAL_gp 0 /* Offset Calibration group position. */ -#define DAC_CH1OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ -#define DAC_CH1OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ -#define DAC_CH1OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ -#define DAC_CH1OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ -#define DAC_CH1OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ -#define DAC_CH1OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ -#define DAC_CH1OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ -#define DAC_CH1OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ -#define DAC_CH1OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ -#define DAC_CH1OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ -#define DAC_CH1OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ -#define DAC_CH1OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ -#define DAC_CH1OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ -#define DAC_CH1OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ - -/* AC - Analog Comparator */ -/* AC.AC0CTRL bit masks and bit positions */ -#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ -#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ -#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ -#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ -#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ -#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ - -#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ -#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ -#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ -#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ -#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ -#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ - -#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ -#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ -#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ -#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ -#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ -#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ - -#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ -#define AC_ENABLE_bp 0 /* Enable bit position. */ - -/* AC.AC1CTRL bit masks and bit positions */ -/* AC_INTMODE Predefined. */ -/* AC_INTMODE Predefined. */ - -/* AC_INTLVL Predefined. */ -/* AC_INTLVL Predefined. */ - -/* AC_HYSMODE Predefined. */ -/* AC_HYSMODE Predefined. */ - -/* AC_ENABLE Predefined. */ -/* AC_ENABLE Predefined. */ - -/* AC.AC0MUXCTRL bit masks and bit positions */ -#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ -#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ -#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ -#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ -#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ -#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ -#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ -#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ - -#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ -#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ -#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ -#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ -#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ -#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ -#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ -#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ - -/* AC.AC1MUXCTRL bit masks and bit positions */ -/* AC_MUXPOS Predefined. */ -/* AC_MUXPOS Predefined. */ - -/* AC_MUXNEG Predefined. */ -/* AC_MUXNEG Predefined. */ - -/* AC.CTRLA bit masks and bit positions */ -#define AC_AC1INVEN_bm 0x08 /* Analog Comparator 1 Output Invert Enable bit mask. */ -#define AC_AC1INVEN_bp 3 /* Analog Comparator 1 Output Invert Enable bit position. */ - -#define AC_AC0INVEN_bm 0x04 /* Analog Comparator 0 Output Invert Enable bit mask. */ -#define AC_AC0INVEN_bp 2 /* Analog Comparator 0 Output Invert Enable bit position. */ - -#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ -#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ - -#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ -#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ - -/* AC.CTRLB bit masks and bit positions */ -#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ -#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ -#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ -#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ -#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ -#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ -#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ -#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ -#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ -#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ -#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ -#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ -#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ -#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ - -/* AC.WINCTRL bit masks and bit positions */ -#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ -#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ - -#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ -#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ -#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ -#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ -#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ -#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ - -#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ -#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ -#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ -#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ -#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ -#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ - -/* AC.STATUS bit masks and bit positions */ -#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ -#define AC_WSTATE_gp 6 /* Window Mode State group position. */ -#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ -#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ -#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ -#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ - -#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ -#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ - -#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ -#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ - -#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ -#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ - -#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ -#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ - -#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ -#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ - -/* AC.CURRCTRL bit masks and bit positions */ -#define AC_CURREN_bm 0x80 /* Current Source Enable bit mask. */ -#define AC_CURREN_bp 7 /* Current Source Enable bit position. */ - -#define AC_CURRMODE_bm 0x40 /* Current Mode bit mask. */ -#define AC_CURRMODE_bp 6 /* Current Mode bit position. */ - -#define AC_AC1CURR_bm 0x02 /* Analog Comparator 1 current source output bit mask. */ -#define AC_AC1CURR_bp 1 /* Analog Comparator 1 current source output bit position. */ - -#define AC_AC0CURR_bm 0x01 /* Analog Comparator 0 current source output bit mask. */ -#define AC_AC0CURR_bp 0 /* Analog Comparator 0 current source output bit position. */ - -/* AC.CURRCALIB bit masks and bit positions */ -#define AC_CALIB_gm 0x0F /* Current Source Calibration group mask. */ -#define AC_CALIB_gp 0 /* Current Source Calibration group position. */ -#define AC_CALIB0_bm (1<<0) /* Current Source Calibration bit 0 mask. */ -#define AC_CALIB0_bp 0 /* Current Source Calibration bit 0 position. */ -#define AC_CALIB1_bm (1<<1) /* Current Source Calibration bit 1 mask. */ -#define AC_CALIB1_bp 1 /* Current Source Calibration bit 1 position. */ -#define AC_CALIB2_bm (1<<2) /* Current Source Calibration bit 2 mask. */ -#define AC_CALIB2_bp 2 /* Current Source Calibration bit 2 position. */ -#define AC_CALIB3_bm (1<<3) /* Current Source Calibration bit 3 mask. */ -#define AC_CALIB3_bp 3 /* Current Source Calibration bit 3 position. */ - -/* RTC - Real-Time Clounter */ -/* RTC.CTRL bit masks and bit positions */ -#define RTC_CORREN_bm 0x08 /* Correction Enable bit mask. */ -#define RTC_CORREN_bp 3 /* Correction Enable bit position. */ - -#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ -#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ -#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ -#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ -#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ -#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ -#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ -#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ - -/* RTC.STATUS bit masks and bit positions */ -#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ -#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ - -/* RTC.INTCTRL bit masks and bit positions */ -#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ -#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ -#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ -#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ -#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ -#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ - -#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ -#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ -#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ -#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ -#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ -#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ - -/* RTC.INTFLAGS bit masks and bit positions */ -#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ -#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ - -#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - -/* RTC.CALIB bit masks and bit positions */ -#define RTC_SIGN_bm 0x80 /* Correction Sign bit mask. */ -#define RTC_SIGN_bp 7 /* Correction Sign bit position. */ - -#define RTC_ERROR_gm 0x7F /* Error Value group mask. */ -#define RTC_ERROR_gp 0 /* Error Value group position. */ -#define RTC_ERROR0_bm (1<<0) /* Error Value bit 0 mask. */ -#define RTC_ERROR0_bp 0 /* Error Value bit 0 position. */ -#define RTC_ERROR1_bm (1<<1) /* Error Value bit 1 mask. */ -#define RTC_ERROR1_bp 1 /* Error Value bit 1 position. */ -#define RTC_ERROR2_bm (1<<2) /* Error Value bit 2 mask. */ -#define RTC_ERROR2_bp 2 /* Error Value bit 2 position. */ -#define RTC_ERROR3_bm (1<<3) /* Error Value bit 3 mask. */ -#define RTC_ERROR3_bp 3 /* Error Value bit 3 position. */ -#define RTC_ERROR4_bm (1<<4) /* Error Value bit 4 mask. */ -#define RTC_ERROR4_bp 4 /* Error Value bit 4 position. */ -#define RTC_ERROR5_bm (1<<5) /* Error Value bit 5 mask. */ -#define RTC_ERROR5_bp 5 /* Error Value bit 5 position. */ -#define RTC_ERROR6_bm (1<<6) /* Error Value bit 6 mask. */ -#define RTC_ERROR6_bp 6 /* Error Value bit 6 position. */ - -/* XCL - XMEGA Custom Logic */ -/* XCL.CTRLA bit masks and bit positions */ -#define XCL_LUT0OUTEN_gm 0xC0 /* LUT0 Output Enable group mask. */ -#define XCL_LUT0OUTEN_gp 6 /* LUT0 Output Enable group position. */ -#define XCL_LUT0OUTEN0_bm (1<<6) /* LUT0 Output Enable bit 0 mask. */ -#define XCL_LUT0OUTEN0_bp 6 /* LUT0 Output Enable bit 0 position. */ -#define XCL_LUT0OUTEN1_bm (1<<7) /* LUT0 Output Enable bit 1 mask. */ -#define XCL_LUT0OUTEN1_bp 7 /* LUT0 Output Enable bit 1 position. */ - -#define XCL_PORTSEL_gm 0x30 /* Port Selection group mask. */ -#define XCL_PORTSEL_gp 4 /* Port Selection group position. */ -#define XCL_PORTSEL0_bm (1<<4) /* Port Selection bit 0 mask. */ -#define XCL_PORTSEL0_bp 4 /* Port Selection bit 0 position. */ -#define XCL_PORTSEL1_bm (1<<5) /* Port Selection bit 1 mask. */ -#define XCL_PORTSEL1_bp 5 /* Port Selection bit 1 position. */ - -#define XCL_LUTCONF_gm 0x07 /* LUT Configuration group mask. */ -#define XCL_LUTCONF_gp 0 /* LUT Configuration group position. */ -#define XCL_LUTCONF0_bm (1<<0) /* LUT Configuration bit 0 mask. */ -#define XCL_LUTCONF0_bp 0 /* LUT Configuration bit 0 position. */ -#define XCL_LUTCONF1_bm (1<<1) /* LUT Configuration bit 1 mask. */ -#define XCL_LUTCONF1_bp 1 /* LUT Configuration bit 1 position. */ -#define XCL_LUTCONF2_bm (1<<2) /* LUT Configuration bit 2 mask. */ -#define XCL_LUTCONF2_bp 2 /* LUT Configuration bit 2 position. */ - -/* XCL.CTRLB bit masks and bit positions */ -#define XCL_IN3SEL_gm 0xC0 /* Input Selection 3 group mask. */ -#define XCL_IN3SEL_gp 6 /* Input Selection 3 group position. */ -#define XCL_IN3SEL0_bm (1<<6) /* Input Selection 3 bit 0 mask. */ -#define XCL_IN3SEL0_bp 6 /* Input Selection 3 bit 0 position. */ -#define XCL_IN3SEL1_bm (1<<7) /* Input Selection 3 bit 1 mask. */ -#define XCL_IN3SEL1_bp 7 /* Input Selection 3 bit 1 position. */ - -#define XCL_IN2SEL_gm 0x30 /* Input Selection 2 group mask. */ -#define XCL_IN2SEL_gp 4 /* Input Selection 2 group position. */ -#define XCL_IN2SEL0_bm (1<<4) /* Input Selection 2 bit 0 mask. */ -#define XCL_IN2SEL0_bp 4 /* Input Selection 2 bit 0 position. */ -#define XCL_IN2SEL1_bm (1<<5) /* Input Selection 2 bit 1 mask. */ -#define XCL_IN2SEL1_bp 5 /* Input Selection 2 bit 1 position. */ - -#define XCL_IN1SEL_gm 0x0C /* Input Selection 1 group mask. */ -#define XCL_IN1SEL_gp 2 /* Input Selection 1 group position. */ -#define XCL_IN1SEL0_bm (1<<2) /* Input Selection 1 bit 0 mask. */ -#define XCL_IN1SEL0_bp 2 /* Input Selection 1 bit 0 position. */ -#define XCL_IN1SEL1_bm (1<<3) /* Input Selection 1 bit 1 mask. */ -#define XCL_IN1SEL1_bp 3 /* Input Selection 1 bit 1 position. */ - -#define XCL_IN0SEL_gm 0x03 /* Input Selection 0 group mask. */ -#define XCL_IN0SEL_gp 0 /* Input Selection 0 group position. */ -#define XCL_IN0SEL0_bm (1<<0) /* Input Selection 0 bit 0 mask. */ -#define XCL_IN0SEL0_bp 0 /* Input Selection 0 bit 0 position. */ -#define XCL_IN0SEL1_bm (1<<1) /* Input Selection 0 bit 1 mask. */ -#define XCL_IN0SEL1_bp 1 /* Input Selection 0 bit 1 position. */ - -/* XCL.CTRLC bit masks and bit positions */ -#define XCL_EVASYSEL1_bm 0x80 /* Asynchronous Event Line Selection for LUT1 bit mask. */ -#define XCL_EVASYSEL1_bp 7 /* Asynchronous Event Line Selection for LUT1 bit position. */ - -#define XCL_EVASYSEL0_bm 0x40 /* Asynchronous Event Line Selection for LUT0 bit mask. */ -#define XCL_EVASYSEL0_bp 6 /* Asynchronous Event Line Selection for LUT0 bit position. */ - -#define XCL_DLYSEL_gm 0x30 /* Delay Selection group mask. */ -#define XCL_DLYSEL_gp 4 /* Delay Selection group position. */ -#define XCL_DLYSEL0_bm (1<<4) /* Delay Selection bit 0 mask. */ -#define XCL_DLYSEL0_bp 4 /* Delay Selection bit 0 position. */ -#define XCL_DLYSEL1_bm (1<<5) /* Delay Selection bit 1 mask. */ -#define XCL_DLYSEL1_bp 5 /* Delay Selection bit 1 position. */ - -#define XCL_DLY1CONF_gm 0x0C /* Delay Configuration on LUT1 group mask. */ -#define XCL_DLY1CONF_gp 2 /* Delay Configuration on LUT1 group position. */ -#define XCL_DLY1CONF0_bm (1<<2) /* Delay Configuration on LUT1 bit 0 mask. */ -#define XCL_DLY1CONF0_bp 2 /* Delay Configuration on LUT1 bit 0 position. */ -#define XCL_DLY1CONF1_bm (1<<3) /* Delay Configuration on LUT1 bit 1 mask. */ -#define XCL_DLY1CONF1_bp 3 /* Delay Configuration on LUT1 bit 1 position. */ - -#define XCL_DLY0CONF_gm 0x03 /* Delay Configuration on LUT0 group mask. */ -#define XCL_DLY0CONF_gp 0 /* Delay Configuration on LUT0 group position. */ -#define XCL_DLY0CONF0_bm (1<<0) /* Delay Configuration on LUT0 bit 0 mask. */ -#define XCL_DLY0CONF0_bp 0 /* Delay Configuration on LUT0 bit 0 position. */ -#define XCL_DLY0CONF1_bm (1<<1) /* Delay Configuration on LUT0 bit 1 mask. */ -#define XCL_DLY0CONF1_bp 1 /* Delay Configuration on LUT0 bit 1 position. */ - -/* XCL.CTRLD bit masks and bit positions */ -#define XCL_TRUTH1_gm 0xF0 /* Truth Table of LUT1 group mask. */ -#define XCL_TRUTH1_gp 4 /* Truth Table of LUT1 group position. */ -#define XCL_TRUTH10_bm (1<<4) /* Truth Table of LUT1 bit 0 mask. */ -#define XCL_TRUTH10_bp 4 /* Truth Table of LUT1 bit 0 position. */ -#define XCL_TRUTH11_bm (1<<5) /* Truth Table of LUT1 bit 1 mask. */ -#define XCL_TRUTH11_bp 5 /* Truth Table of LUT1 bit 1 position. */ -#define XCL_TRUTH12_bm (1<<6) /* Truth Table of LUT1 bit 2 mask. */ -#define XCL_TRUTH12_bp 6 /* Truth Table of LUT1 bit 2 position. */ -#define XCL_TRUTH13_bm (1<<7) /* Truth Table of LUT1 bit 3 mask. */ -#define XCL_TRUTH13_bp 7 /* Truth Table of LUT1 bit 3 position. */ - -#define XCL_TRUTH0_gm 0x0F /* Truth Table of LUT0 group mask. */ -#define XCL_TRUTH0_gp 0 /* Truth Table of LUT0 group position. */ -#define XCL_TRUTH00_bm (1<<0) /* Truth Table of LUT0 bit 0 mask. */ -#define XCL_TRUTH00_bp 0 /* Truth Table of LUT0 bit 0 position. */ -#define XCL_TRUTH01_bm (1<<1) /* Truth Table of LUT0 bit 1 mask. */ -#define XCL_TRUTH01_bp 1 /* Truth Table of LUT0 bit 1 position. */ -#define XCL_TRUTH02_bm (1<<2) /* Truth Table of LUT0 bit 2 mask. */ -#define XCL_TRUTH02_bp 2 /* Truth Table of LUT0 bit 2 position. */ -#define XCL_TRUTH03_bm (1<<3) /* Truth Table of LUT0 bit 3 mask. */ -#define XCL_TRUTH03_bp 3 /* Truth Table of LUT0 bit 3 position. */ - -/* XCL.CTRLE bit masks and bit positions */ -#define XCL_CMDSEL_bm 0x80 /* Timer/Counter Command Selection bit mask. */ -#define XCL_CMDSEL_bp 7 /* Timer/Counter Command Selection bit position. */ - -#define XCL_TCSEL_gm 0x70 /* Timer/Counter Selection group mask. */ -#define XCL_TCSEL_gp 4 /* Timer/Counter Selection group position. */ -#define XCL_TCSEL0_bm (1<<4) /* Timer/Counter Selection bit 0 mask. */ -#define XCL_TCSEL0_bp 4 /* Timer/Counter Selection bit 0 position. */ -#define XCL_TCSEL1_bm (1<<5) /* Timer/Counter Selection bit 1 mask. */ -#define XCL_TCSEL1_bp 5 /* Timer/Counter Selection bit 1 position. */ -#define XCL_TCSEL2_bm (1<<6) /* Timer/Counter Selection bit 2 mask. */ -#define XCL_TCSEL2_bp 6 /* Timer/Counter Selection bit 2 position. */ - -#define XCL_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define XCL_CLKSEL_gp 0 /* Clock Selection group position. */ -#define XCL_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define XCL_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define XCL_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define XCL_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define XCL_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define XCL_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define XCL_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define XCL_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - -/* XCL.CTRLF bit masks and bit positions */ -#define XCL_CMDEN_gm 0xC0 /* Command Enable group mask. */ -#define XCL_CMDEN_gp 6 /* Command Enable group position. */ -#define XCL_CMDEN0_bm (1<<6) /* Command Enable bit 0 mask. */ -#define XCL_CMDEN0_bp 6 /* Command Enable bit 0 position. */ -#define XCL_CMDEN1_bm (1<<7) /* Command Enable bit 1 mask. */ -#define XCL_CMDEN1_bp 7 /* Command Enable bit 1 position. */ - -#define XCL_CMP1_bm 0x20 /* Compare Channel 1 Output Value bit mask. */ -#define XCL_CMP1_bp 5 /* Compare Channel 1 Output Value bit position. */ - -#define XCL_CMP0_bm 0x10 /* Compare Channel 0 Output Value bit mask. */ -#define XCL_CMP0_bp 4 /* Compare Channel 0 Output Value bit position. */ - -#define XCL_CCEN1_bm 0x08 /* Compare or Capture Channel 1 Enable bit mask. */ -#define XCL_CCEN1_bp 3 /* Compare or Capture Channel 1 Enable bit position. */ - -#define XCL_CCEN0_bm 0x04 /* Compare or Capture Channel 0 Enable bit mask. */ -#define XCL_CCEN0_bp 2 /* Compare or Capture Channel 0 Enable bit position. */ - -#define XCL_MODE_gm 0x03 /* Timer/Counter Mode group mask. */ -#define XCL_MODE_gp 0 /* Timer/Counter Mode group position. */ -#define XCL_MODE0_bm (1<<0) /* Timer/Counter Mode bit 0 mask. */ -#define XCL_MODE0_bp 0 /* Timer/Counter Mode bit 0 position. */ -#define XCL_MODE1_bm (1<<1) /* Timer/Counter Mode bit 1 mask. */ -#define XCL_MODE1_bp 1 /* Timer/Counter Mode bit 1 position. */ - -/* XCL.CTRLG bit masks and bit positions */ -#define XCL_EVACTEN_bm 0x80 /* Event Action Enable bit mask. */ -#define XCL_EVACTEN_bp 7 /* Event Action Enable bit position. */ - -#define XCL_EVACT1_gm 0x60 /* Event Action Selection on Timer/Counter 1 group mask. */ -#define XCL_EVACT1_gp 5 /* Event Action Selection on Timer/Counter 1 group position. */ -#define XCL_EVACT10_bm (1<<5) /* Event Action Selection on Timer/Counter 1 bit 0 mask. */ -#define XCL_EVACT10_bp 5 /* Event Action Selection on Timer/Counter 1 bit 0 position. */ -#define XCL_EVACT11_bm (1<<6) /* Event Action Selection on Timer/Counter 1 bit 1 mask. */ -#define XCL_EVACT11_bp 6 /* Event Action Selection on Timer/Counter 1 bit 1 position. */ - -#define XCL_EVACT0_gm 0x18 /* Event Action Selection on Timer/Counter 0 group mask. */ -#define XCL_EVACT0_gp 3 /* Event Action Selection on Timer/Counter 0 group position. */ -#define XCL_EVACT00_bm (1<<3) /* Event Action Selection on Timer/Counter 0 bit 0 mask. */ -#define XCL_EVACT00_bp 3 /* Event Action Selection on Timer/Counter 0 bit 0 position. */ -#define XCL_EVACT01_bm (1<<4) /* Event Action Selection on Timer/Counter 0 bit 1 mask. */ -#define XCL_EVACT01_bp 4 /* Event Action Selection on Timer/Counter 0 bit 1 position. */ - -#define XCL_EVSRC_gm 0x07 /* Event Source Selection group mask. */ -#define XCL_EVSRC_gp 0 /* Event Source Selection group position. */ -#define XCL_EVSRC0_bm (1<<0) /* Event Source Selection bit 0 mask. */ -#define XCL_EVSRC0_bp 0 /* Event Source Selection bit 0 position. */ -#define XCL_EVSRC1_bm (1<<1) /* Event Source Selection bit 1 mask. */ -#define XCL_EVSRC1_bp 1 /* Event Source Selection bit 1 position. */ -#define XCL_EVSRC2_bm (1<<2) /* Event Source Selection bit 2 mask. */ -#define XCL_EVSRC2_bp 2 /* Event Source Selection bit 2 position. */ - -/* XCL.INTCTRL bit masks and bit positions */ -#define XCL_UNF1IE_bm 0x80 /* Underflow 1 Interrupt Enable bit mask. */ -#define XCL_UNF1IE_bp 7 /* Underflow 1 Interrupt Enable bit position. */ - -#define XCL_PEC1IE_bm 0x80 /* Peripheral Counter 1 Interrupt Enable bit mask. */ -#define XCL_PEC1IE_bp 7 /* Peripheral Counter 1 Interrupt Enable bit position. */ - -#define XCL_PEC21IE_bm 0x80 /* Peripheral High Counter 2 Interrupt Enable bit mask. */ -#define XCL_PEC21IE_bp 7 /* Peripheral High Counter 2 Interrupt Enable bit position. */ - -#define XCL_UNF0IE_bm 0x40 /* Underflow 0 Interrupt Enable bit mask. */ -#define XCL_UNF0IE_bp 6 /* Underflow 0 Interrupt Enable bit position. */ - -#define XCL_PEC0IE_bm 0x40 /* Peripheral Counter 0 Interrupt Enable bit mask. */ -#define XCL_PEC0IE_bp 6 /* Peripheral Counter 0 Interrupt Enable bit position. */ - -#define XCL_CC1IE_bm 0x20 /* Compare Or Capture 1 Interrupt Enable bit mask. */ -#define XCL_CC1IE_bp 5 /* Compare Or Capture 1 Interrupt Enable bit position. */ - -#define XCL_PEC20IE_bm 0x20 /* Peripheral Low Counter 2 Interrupt Enable bit mask. */ -#define XCL_PEC20IE_bp 5 /* Peripheral Low Counter 2 Interrupt Enable bit position. */ - -#define XCL_CC0IE_bm 0x10 /* Compare Or Capture 0 Interrupt Enable bit mask. */ -#define XCL_CC0IE_bp 4 /* Compare Or Capture 0 Interrupt Enable bit position. */ - -#define XCL_UNFINTLVL_gm 0x0C /* Timer Underflow Interrupt Level group mask. */ -#define XCL_UNFINTLVL_gp 2 /* Timer Underflow Interrupt Level group position. */ -#define XCL_UNFINTLVL0_bm (1<<2) /* Timer Underflow Interrupt Level bit 0 mask. */ -#define XCL_UNFINTLVL0_bp 2 /* Timer Underflow Interrupt Level bit 0 position. */ -#define XCL_UNFINTLVL1_bm (1<<3) /* Timer Underflow Interrupt Level bit 1 mask. */ -#define XCL_UNFINTLVL1_bp 3 /* Timer Underflow Interrupt Level bit 1 position. */ - -#define XCL_CCINTLVL_gm 0x03 /* Timer Compare or Capture Interrupt Level group mask. */ -#define XCL_CCINTLVL_gp 0 /* Timer Compare or Capture Interrupt Level group position. */ -#define XCL_CCINTLVL0_bm (1<<0) /* Timer Compare or Capture Interrupt Level bit 0 mask. */ -#define XCL_CCINTLVL0_bp 0 /* Timer Compare or Capture Interrupt Level bit 0 position. */ -#define XCL_CCINTLVL1_bm (1<<1) /* Timer Compare or Capture Interrupt Level bit 1 mask. */ -#define XCL_CCINTLVL1_bp 1 /* Timer Compare or Capture Interrupt Level bit 1 position. */ - -/* XCL.INTFLAGS bit masks and bit positions */ -#define XCL_UNF1IF_bm 0x80 /* Timer/Counter 1 Underflow Interrupt Flag bit mask. */ -#define XCL_UNF1IF_bp 7 /* Timer/Counter 1 Underflow Interrupt Flag bit position. */ - -#define XCL_PEC1IF_bm 0x80 /* Peripheral Counter 1 Interrupt Flag bit mask. */ -#define XCL_PEC1IF_bp 7 /* Peripheral Counter 1 Interrupt Flag bit position. */ - -#define XCL_PEC21IF_bm 0x80 /* Peripheral High Counter 2 Interrupt Flag bit mask. */ -#define XCL_PEC21IF_bp 7 /* Peripheral High Counter 2 Interrupt Flag bit position. */ - -#define XCL_UNF0IF_bm 0x40 /* Timer/Counter 0 Underflow Interrupt Flag bit mask. */ -#define XCL_UNF0IF_bp 6 /* Timer/Counter 0 Underflow Interrupt Flag bit position. */ - -#define XCL_PEC0IF_bm 0x40 /* Peripheral Counter 0 Interrupt Flag bit mask. */ -#define XCL_PEC0IF_bp 6 /* Peripheral Counter 0 Interrupt Flag bit position. */ - -#define XCL_CC1IF_bm 0x20 /* Compare or Capture Channel 1 Interrupt Flag bit mask. */ -#define XCL_CC1IF_bp 5 /* Compare or Capture Channel 1 Interrupt Flag bit position. */ - -#define XCL_PEC20IF_bm 0x20 /* Peripheral Low Counter 2 Interrupt Flag bit mask. */ -#define XCL_PEC20IF_bp 5 /* Peripheral Low Counter 2 Interrupt Flag bit position. */ - -#define XCL_CC0IF_bm 0x10 /* Compare or Capture Channel 0 Interrupt Flag bit mask. */ -#define XCL_CC0IF_bp 4 /* Compare or Capture Channel 0 Interrupt Flag bit position. */ - -/* XCL.PLC bit masks and bit positions */ -#define XCL_PLC_gm 0xFF /* Peripheral Lenght Control Bits group mask. */ -#define XCL_PLC_gp 0 /* Peripheral Lenght Control Bits group position. */ -#define XCL_PLC0_bm (1<<0) /* Peripheral Lenght Control Bits bit 0 mask. */ -#define XCL_PLC0_bp 0 /* Peripheral Lenght Control Bits bit 0 position. */ -#define XCL_PLC1_bm (1<<1) /* Peripheral Lenght Control Bits bit 1 mask. */ -#define XCL_PLC1_bp 1 /* Peripheral Lenght Control Bits bit 1 position. */ -#define XCL_PLC2_bm (1<<2) /* Peripheral Lenght Control Bits bit 2 mask. */ -#define XCL_PLC2_bp 2 /* Peripheral Lenght Control Bits bit 2 position. */ -#define XCL_PLC3_bm (1<<3) /* Peripheral Lenght Control Bits bit 3 mask. */ -#define XCL_PLC3_bp 3 /* Peripheral Lenght Control Bits bit 3 position. */ -#define XCL_PLC4_bm (1<<4) /* Peripheral Lenght Control Bits bit 4 mask. */ -#define XCL_PLC4_bp 4 /* Peripheral Lenght Control Bits bit 4 position. */ -#define XCL_PLC5_bm (1<<5) /* Peripheral Lenght Control Bits bit 5 mask. */ -#define XCL_PLC5_bp 5 /* Peripheral Lenght Control Bits bit 5 position. */ -#define XCL_PLC6_bm (1<<6) /* Peripheral Lenght Control Bits bit 6 mask. */ -#define XCL_PLC6_bp 6 /* Peripheral Lenght Control Bits bit 6 position. */ -#define XCL_PLC7_bm (1<<7) /* Peripheral Lenght Control Bits bit 7 mask. */ -#define XCL_PLC7_bp 7 /* Peripheral Lenght Control Bits bit 7 position. */ - -/* XCL.CNTL bit masks and bit positions */ -#define XCL_BCNTO_gm 0xFF /* BTC0 Counter Byte group mask. */ -#define XCL_BCNTO_gp 0 /* BTC0 Counter Byte group position. */ -#define XCL_BCNTO0_bm (1<<0) /* BTC0 Counter Byte bit 0 mask. */ -#define XCL_BCNTO0_bp 0 /* BTC0 Counter Byte bit 0 position. */ -#define XCL_BCNTO1_bm (1<<1) /* BTC0 Counter Byte bit 1 mask. */ -#define XCL_BCNTO1_bp 1 /* BTC0 Counter Byte bit 1 position. */ -#define XCL_BCNTO2_bm (1<<2) /* BTC0 Counter Byte bit 2 mask. */ -#define XCL_BCNTO2_bp 2 /* BTC0 Counter Byte bit 2 position. */ -#define XCL_BCNTO3_bm (1<<3) /* BTC0 Counter Byte bit 3 mask. */ -#define XCL_BCNTO3_bp 3 /* BTC0 Counter Byte bit 3 position. */ -#define XCL_BCNTO4_bm (1<<4) /* BTC0 Counter Byte bit 4 mask. */ -#define XCL_BCNTO4_bp 4 /* BTC0 Counter Byte bit 4 position. */ -#define XCL_BCNTO5_bm (1<<5) /* BTC0 Counter Byte bit 5 mask. */ -#define XCL_BCNTO5_bp 5 /* BTC0 Counter Byte bit 5 position. */ -#define XCL_BCNTO6_bm (1<<6) /* BTC0 Counter Byte bit 6 mask. */ -#define XCL_BCNTO6_bp 6 /* BTC0 Counter Byte bit 6 position. */ -#define XCL_BCNTO7_bm (1<<7) /* BTC0 Counter Byte bit 7 mask. */ -#define XCL_BCNTO7_bp 7 /* BTC0 Counter Byte bit 7 position. */ - -#define XCL_CNTL_gm 0xFF /* TC16 Counter Low Byte group mask. */ -#define XCL_CNTL_gp 0 /* TC16 Counter Low Byte group position. */ -#define XCL_CNTL0_bm (1<<0) /* TC16 Counter Low Byte bit 0 mask. */ -#define XCL_CNTL0_bp 0 /* TC16 Counter Low Byte bit 0 position. */ -#define XCL_CNTL1_bm (1<<1) /* TC16 Counter Low Byte bit 1 mask. */ -#define XCL_CNTL1_bp 1 /* TC16 Counter Low Byte bit 1 position. */ -#define XCL_CNTL2_bm (1<<2) /* TC16 Counter Low Byte bit 2 mask. */ -#define XCL_CNTL2_bp 2 /* TC16 Counter Low Byte bit 2 position. */ -#define XCL_CNTL3_bm (1<<3) /* TC16 Counter Low Byte bit 3 mask. */ -#define XCL_CNTL3_bp 3 /* TC16 Counter Low Byte bit 3 position. */ -#define XCL_CNTL4_bm (1<<4) /* TC16 Counter Low Byte bit 4 mask. */ -#define XCL_CNTL4_bp 4 /* TC16 Counter Low Byte bit 4 position. */ -#define XCL_CNTL5_bm (1<<5) /* TC16 Counter Low Byte bit 5 mask. */ -#define XCL_CNTL5_bp 5 /* TC16 Counter Low Byte bit 5 position. */ -#define XCL_CNTL6_bm (1<<6) /* TC16 Counter Low Byte bit 6 mask. */ -#define XCL_CNTL6_bp 6 /* TC16 Counter Low Byte bit 6 position. */ -#define XCL_CNTL7_bm (1<<7) /* TC16 Counter Low Byte bit 7 mask. */ -#define XCL_CNTL7_bp 7 /* TC16 Counter Low Byte bit 7 position. */ - -#define XCL_PCNTO_gm 0xFF /* Peripheral Counter 0 Byte group mask. */ -#define XCL_PCNTO_gp 0 /* Peripheral Counter 0 Byte group position. */ -#define XCL_PCNTO0_bm (1<<0) /* Peripheral Counter 0 Byte bit 0 mask. */ -#define XCL_PCNTO0_bp 0 /* Peripheral Counter 0 Byte bit 0 position. */ -#define XCL_PCNTO1_bm (1<<1) /* Peripheral Counter 0 Byte bit 1 mask. */ -#define XCL_PCNTO1_bp 1 /* Peripheral Counter 0 Byte bit 1 position. */ -#define XCL_PCNTO2_bm (1<<2) /* Peripheral Counter 0 Byte bit 2 mask. */ -#define XCL_PCNTO2_bp 2 /* Peripheral Counter 0 Byte bit 2 position. */ -#define XCL_PCNTO3_bm (1<<3) /* Peripheral Counter 0 Byte bit 3 mask. */ -#define XCL_PCNTO3_bp 3 /* Peripheral Counter 0 Byte bit 3 position. */ -#define XCL_PCNTO4_bm (1<<4) /* Peripheral Counter 0 Byte bit 4 mask. */ -#define XCL_PCNTO4_bp 4 /* Peripheral Counter 0 Byte bit 4 position. */ -#define XCL_PCNTO5_bm (1<<5) /* Peripheral Counter 0 Byte bit 5 mask. */ -#define XCL_PCNTO5_bp 5 /* Peripheral Counter 0 Byte bit 5 position. */ -#define XCL_PCNTO6_bm (1<<6) /* Peripheral Counter 0 Byte bit 6 mask. */ -#define XCL_PCNTO6_bp 6 /* Peripheral Counter 0 Byte bit 6 position. */ -#define XCL_PCNTO7_bm (1<<7) /* Peripheral Counter 0 Byte bit 7 mask. */ -#define XCL_PCNTO7_bp 7 /* Peripheral Counter 0 Byte bit 7 position. */ - -/* XCL.CNTH bit masks and bit positions */ -#define XCL_BCNT1_gm 0xFF /* BTC1 Counter Byte group mask. */ -#define XCL_BCNT1_gp 0 /* BTC1 Counter Byte group position. */ -#define XCL_BCNT10_bm (1<<0) /* BTC1 Counter Byte bit 0 mask. */ -#define XCL_BCNT10_bp 0 /* BTC1 Counter Byte bit 0 position. */ -#define XCL_BCNT11_bm (1<<1) /* BTC1 Counter Byte bit 1 mask. */ -#define XCL_BCNT11_bp 1 /* BTC1 Counter Byte bit 1 position. */ -#define XCL_BCNT12_bm (1<<2) /* BTC1 Counter Byte bit 2 mask. */ -#define XCL_BCNT12_bp 2 /* BTC1 Counter Byte bit 2 position. */ -#define XCL_BCNT13_bm (1<<3) /* BTC1 Counter Byte bit 3 mask. */ -#define XCL_BCNT13_bp 3 /* BTC1 Counter Byte bit 3 position. */ -#define XCL_BCNT14_bm (1<<4) /* BTC1 Counter Byte bit 4 mask. */ -#define XCL_BCNT14_bp 4 /* BTC1 Counter Byte bit 4 position. */ -#define XCL_BCNT15_bm (1<<5) /* BTC1 Counter Byte bit 5 mask. */ -#define XCL_BCNT15_bp 5 /* BTC1 Counter Byte bit 5 position. */ -#define XCL_BCNT16_bm (1<<6) /* BTC1 Counter Byte bit 6 mask. */ -#define XCL_BCNT16_bp 6 /* BTC1 Counter Byte bit 6 position. */ -#define XCL_BCNT17_bm (1<<7) /* BTC1 Counter Byte bit 7 mask. */ -#define XCL_BCNT17_bp 7 /* BTC1 Counter Byte bit 7 position. */ - -#define XCL_CNTH_gm 0xFF /* TC16 Counter High Byte group mask. */ -#define XCL_CNTH_gp 0 /* TC16 Counter High Byte group position. */ -#define XCL_CNTH0_bm (1<<0) /* TC16 Counter High Byte bit 0 mask. */ -#define XCL_CNTH0_bp 0 /* TC16 Counter High Byte bit 0 position. */ -#define XCL_CNTH1_bm (1<<1) /* TC16 Counter High Byte bit 1 mask. */ -#define XCL_CNTH1_bp 1 /* TC16 Counter High Byte bit 1 position. */ -#define XCL_CNTH2_bm (1<<2) /* TC16 Counter High Byte bit 2 mask. */ -#define XCL_CNTH2_bp 2 /* TC16 Counter High Byte bit 2 position. */ -#define XCL_CNTH3_bm (1<<3) /* TC16 Counter High Byte bit 3 mask. */ -#define XCL_CNTH3_bp 3 /* TC16 Counter High Byte bit 3 position. */ -#define XCL_CNTH4_bm (1<<4) /* TC16 Counter High Byte bit 4 mask. */ -#define XCL_CNTH4_bp 4 /* TC16 Counter High Byte bit 4 position. */ -#define XCL_CNTH5_bm (1<<5) /* TC16 Counter High Byte bit 5 mask. */ -#define XCL_CNTH5_bp 5 /* TC16 Counter High Byte bit 5 position. */ -#define XCL_CNTH6_bm (1<<6) /* TC16 Counter High Byte bit 6 mask. */ -#define XCL_CNTH6_bp 6 /* TC16 Counter High Byte bit 6 position. */ -#define XCL_CNTH7_bm (1<<7) /* TC16 Counter High Byte bit 7 mask. */ -#define XCL_CNTH7_bp 7 /* TC16 Counter High Byte bit 7 position. */ - -#define XCL_PCNT1_gm 0xFF /* Peripheral Counter 1 Byte group mask. */ -#define XCL_PCNT1_gp 0 /* Peripheral Counter 1 Byte group position. */ -#define XCL_PCNT10_bm (1<<0) /* Peripheral Counter 1 Byte bit 0 mask. */ -#define XCL_PCNT10_bp 0 /* Peripheral Counter 1 Byte bit 0 position. */ -#define XCL_PCNT11_bm (1<<1) /* Peripheral Counter 1 Byte bit 1 mask. */ -#define XCL_PCNT11_bp 1 /* Peripheral Counter 1 Byte bit 1 position. */ -#define XCL_PCNT12_bm (1<<2) /* Peripheral Counter 1 Byte bit 2 mask. */ -#define XCL_PCNT12_bp 2 /* Peripheral Counter 1 Byte bit 2 position. */ -#define XCL_PCNT13_bm (1<<3) /* Peripheral Counter 1 Byte bit 3 mask. */ -#define XCL_PCNT13_bp 3 /* Peripheral Counter 1 Byte bit 3 position. */ -#define XCL_PCNT14_bm (1<<4) /* Peripheral Counter 1 Byte bit 4 mask. */ -#define XCL_PCNT14_bp 4 /* Peripheral Counter 1 Byte bit 4 position. */ -#define XCL_PCNT15_bm (1<<5) /* Peripheral Counter 1 Byte bit 5 mask. */ -#define XCL_PCNT15_bp 5 /* Peripheral Counter 1 Byte bit 5 position. */ -#define XCL_PCNT16_bm (1<<6) /* Peripheral Counter 1 Byte bit 6 mask. */ -#define XCL_PCNT16_bp 6 /* Peripheral Counter 1 Byte bit 6 position. */ -#define XCL_PCNT17_bm (1<<7) /* Peripheral Counter 1 Byte bit 7 mask. */ -#define XCL_PCNT17_bp 7 /* Peripheral Counter 1 Byte bit 7 position. */ - -#define XCL_PCNT21_gm 0xF0 /* Peripheral High Counter 2 Bits group mask. */ -#define XCL_PCNT21_gp 4 /* Peripheral High Counter 2 Bits group position. */ -#define XCL_PCNT210_bm (1<<4) /* Peripheral High Counter 2 Bits bit 0 mask. */ -#define XCL_PCNT210_bp 4 /* Peripheral High Counter 2 Bits bit 0 position. */ -#define XCL_PCNT211_bm (1<<5) /* Peripheral High Counter 2 Bits bit 1 mask. */ -#define XCL_PCNT211_bp 5 /* Peripheral High Counter 2 Bits bit 1 position. */ -#define XCL_PCNT212_bm (1<<6) /* Peripheral High Counter 2 Bits bit 2 mask. */ -#define XCL_PCNT212_bp 6 /* Peripheral High Counter 2 Bits bit 2 position. */ -#define XCL_PCNT213_bm (1<<7) /* Peripheral High Counter 2 Bits bit 3 mask. */ -#define XCL_PCNT213_bp 7 /* Peripheral High Counter 2 Bits bit 3 position. */ - -#define XCL_PCNT20_gm 0x0F /* Peripheral Low Counter 2 Bits group mask. */ -#define XCL_PCNT20_gp 0 /* Peripheral Low Counter 2 Bits group position. */ -#define XCL_PCNT200_bm (1<<0) /* Peripheral Low Counter 2 Bits bit 0 mask. */ -#define XCL_PCNT200_bp 0 /* Peripheral Low Counter 2 Bits bit 0 position. */ -#define XCL_PCNT201_bm (1<<1) /* Peripheral Low Counter 2 Bits bit 1 mask. */ -#define XCL_PCNT201_bp 1 /* Peripheral Low Counter 2 Bits bit 1 position. */ -#define XCL_PCNT202_bm (1<<2) /* Peripheral Low Counter 2 Bits bit 2 mask. */ -#define XCL_PCNT202_bp 2 /* Peripheral Low Counter 2 Bits bit 2 position. */ -#define XCL_PCNT203_bm (1<<3) /* Peripheral Low Counter 2 Bits bit 3 mask. */ -#define XCL_PCNT203_bp 3 /* Peripheral Low Counter 2 Bits bit 3 position. */ - -/* XCL.CMPL bit masks and bit positions */ -#define XCL_CMPL_gm 0xFF /* TC16 Compare Low Byte group mask. */ -#define XCL_CMPL_gp 0 /* TC16 Compare Low Byte group position. */ -#define XCL_CMPL0_bm (1<<0) /* TC16 Compare Low Byte bit 0 mask. */ -#define XCL_CMPL0_bp 0 /* TC16 Compare Low Byte bit 0 position. */ -#define XCL_CMPL1_bm (1<<1) /* TC16 Compare Low Byte bit 1 mask. */ -#define XCL_CMPL1_bp 1 /* TC16 Compare Low Byte bit 1 position. */ -#define XCL_CMPL2_bm (1<<2) /* TC16 Compare Low Byte bit 2 mask. */ -#define XCL_CMPL2_bp 2 /* TC16 Compare Low Byte bit 2 position. */ -#define XCL_CMPL3_bm (1<<3) /* TC16 Compare Low Byte bit 3 mask. */ -#define XCL_CMPL3_bp 3 /* TC16 Compare Low Byte bit 3 position. */ -#define XCL_CMPL4_bm (1<<4) /* TC16 Compare Low Byte bit 4 mask. */ -#define XCL_CMPL4_bp 4 /* TC16 Compare Low Byte bit 4 position. */ -#define XCL_CMPL5_bm (1<<5) /* TC16 Compare Low Byte bit 5 mask. */ -#define XCL_CMPL5_bp 5 /* TC16 Compare Low Byte bit 5 position. */ -#define XCL_CMPL6_bm (1<<6) /* TC16 Compare Low Byte bit 6 mask. */ -#define XCL_CMPL6_bp 6 /* TC16 Compare Low Byte bit 6 position. */ -#define XCL_CMPL7_bm (1<<7) /* TC16 Compare Low Byte bit 7 mask. */ -#define XCL_CMPL7_bp 7 /* TC16 Compare Low Byte bit 7 position. */ - -#define XCL_BCMP0_gm 0xFF /* BTC0 Compare Byte group mask. */ -#define XCL_BCMP0_gp 0 /* BTC0 Compare Byte group position. */ -#define XCL_BCMP00_bm (1<<0) /* BTC0 Compare Byte bit 0 mask. */ -#define XCL_BCMP00_bp 0 /* BTC0 Compare Byte bit 0 position. */ -#define XCL_BCMP01_bm (1<<1) /* BTC0 Compare Byte bit 1 mask. */ -#define XCL_BCMP01_bp 1 /* BTC0 Compare Byte bit 1 position. */ -#define XCL_BCMP02_bm (1<<2) /* BTC0 Compare Byte bit 2 mask. */ -#define XCL_BCMP02_bp 2 /* BTC0 Compare Byte bit 2 position. */ -#define XCL_BCMP03_bm (1<<3) /* BTC0 Compare Byte bit 3 mask. */ -#define XCL_BCMP03_bp 3 /* BTC0 Compare Byte bit 3 position. */ -#define XCL_BCMP04_bm (1<<4) /* BTC0 Compare Byte bit 4 mask. */ -#define XCL_BCMP04_bp 4 /* BTC0 Compare Byte bit 4 position. */ -#define XCL_BCMP05_bm (1<<5) /* BTC0 Compare Byte bit 5 mask. */ -#define XCL_BCMP05_bp 5 /* BTC0 Compare Byte bit 5 position. */ -#define XCL_BCMP06_bm (1<<6) /* BTC0 Compare Byte bit 6 mask. */ -#define XCL_BCMP06_bp 6 /* BTC0 Compare Byte bit 6 position. */ -#define XCL_BCMP07_bm (1<<7) /* BTC0 Compare Byte bit 7 mask. */ -#define XCL_BCMP07_bp 7 /* BTC0 Compare Byte bit 7 position. */ - -/* XCL.CMPH bit masks and bit positions */ -#define XCL_CMPH_gm 0xFF /* TC16 Compare High Byte group mask. */ -#define XCL_CMPH_gp 0 /* TC16 Compare High Byte group position. */ -#define XCL_CMPH0_bm (1<<0) /* TC16 Compare High Byte bit 0 mask. */ -#define XCL_CMPH0_bp 0 /* TC16 Compare High Byte bit 0 position. */ -#define XCL_CMPH1_bm (1<<1) /* TC16 Compare High Byte bit 1 mask. */ -#define XCL_CMPH1_bp 1 /* TC16 Compare High Byte bit 1 position. */ -#define XCL_CMPH2_bm (1<<2) /* TC16 Compare High Byte bit 2 mask. */ -#define XCL_CMPH2_bp 2 /* TC16 Compare High Byte bit 2 position. */ -#define XCL_CMPH3_bm (1<<3) /* TC16 Compare High Byte bit 3 mask. */ -#define XCL_CMPH3_bp 3 /* TC16 Compare High Byte bit 3 position. */ -#define XCL_CMPH4_bm (1<<4) /* TC16 Compare High Byte bit 4 mask. */ -#define XCL_CMPH4_bp 4 /* TC16 Compare High Byte bit 4 position. */ -#define XCL_CMPH5_bm (1<<5) /* TC16 Compare High Byte bit 5 mask. */ -#define XCL_CMPH5_bp 5 /* TC16 Compare High Byte bit 5 position. */ -#define XCL_CMPH6_bm (1<<6) /* TC16 Compare High Byte bit 6 mask. */ -#define XCL_CMPH6_bp 6 /* TC16 Compare High Byte bit 6 position. */ -#define XCL_CMPH7_bm (1<<7) /* TC16 Compare High Byte bit 7 mask. */ -#define XCL_CMPH7_bp 7 /* TC16 Compare High Byte bit 7 position. */ - -#define XCL_BCMP1_gm 0xFF /* BTC1 Compare Byte group mask. */ -#define XCL_BCMP1_gp 0 /* BTC1 Compare Byte group position. */ -#define XCL_BCMP10_bm (1<<0) /* BTC1 Compare Byte bit 0 mask. */ -#define XCL_BCMP10_bp 0 /* BTC1 Compare Byte bit 0 position. */ -#define XCL_BCMP11_bm (1<<1) /* BTC1 Compare Byte bit 1 mask. */ -#define XCL_BCMP11_bp 1 /* BTC1 Compare Byte bit 1 position. */ -#define XCL_BCMP12_bm (1<<2) /* BTC1 Compare Byte bit 2 mask. */ -#define XCL_BCMP12_bp 2 /* BTC1 Compare Byte bit 2 position. */ -#define XCL_BCMP13_bm (1<<3) /* BTC1 Compare Byte bit 3 mask. */ -#define XCL_BCMP13_bp 3 /* BTC1 Compare Byte bit 3 position. */ -#define XCL_BCMP14_bm (1<<4) /* BTC1 Compare Byte bit 4 mask. */ -#define XCL_BCMP14_bp 4 /* BTC1 Compare Byte bit 4 position. */ -#define XCL_BCMP15_bm (1<<5) /* BTC1 Compare Byte bit 5 mask. */ -#define XCL_BCMP15_bp 5 /* BTC1 Compare Byte bit 5 position. */ -#define XCL_BCMP16_bm (1<<6) /* BTC1 Compare Byte bit 6 mask. */ -#define XCL_BCMP16_bp 6 /* BTC1 Compare Byte bit 6 position. */ -#define XCL_BCMP17_bm (1<<7) /* BTC1 Compare Byte bit 7 mask. */ -#define XCL_BCMP17_bp 7 /* BTC1 Compare Byte bit 7 position. */ - -/* XCL.PERCAPTL bit masks and bit positions */ -#define XCL_PERL_gm 0xFF /* TC16 Low Byte Period group mask. */ -#define XCL_PERL_gp 0 /* TC16 Low Byte Period group position. */ -#define XCL_PERL0_bm (1<<0) /* TC16 Low Byte Period bit 0 mask. */ -#define XCL_PERL0_bp 0 /* TC16 Low Byte Period bit 0 position. */ -#define XCL_PERL1_bm (1<<1) /* TC16 Low Byte Period bit 1 mask. */ -#define XCL_PERL1_bp 1 /* TC16 Low Byte Period bit 1 position. */ -#define XCL_PERL2_bm (1<<2) /* TC16 Low Byte Period bit 2 mask. */ -#define XCL_PERL2_bp 2 /* TC16 Low Byte Period bit 2 position. */ -#define XCL_PERL3_bm (1<<3) /* TC16 Low Byte Period bit 3 mask. */ -#define XCL_PERL3_bp 3 /* TC16 Low Byte Period bit 3 position. */ -#define XCL_PERL4_bm (1<<4) /* TC16 Low Byte Period bit 4 mask. */ -#define XCL_PERL4_bp 4 /* TC16 Low Byte Period bit 4 position. */ -#define XCL_PERL5_bm (1<<5) /* TC16 Low Byte Period bit 5 mask. */ -#define XCL_PERL5_bp 5 /* TC16 Low Byte Period bit 5 position. */ -#define XCL_PERL6_bm (1<<6) /* TC16 Low Byte Period bit 6 mask. */ -#define XCL_PERL6_bp 6 /* TC16 Low Byte Period bit 6 position. */ -#define XCL_PERL7_bm (1<<7) /* TC16 Low Byte Period bit 7 mask. */ -#define XCL_PERL7_bp 7 /* TC16 Low Byte Period bit 7 position. */ - -#define XCL_CAPTL_gm 0xFF /* TC16 Capture Value Low Byte group mask. */ -#define XCL_CAPTL_gp 0 /* TC16 Capture Value Low Byte group position. */ -#define XCL_CAPTL0_bm (1<<0) /* TC16 Capture Value Low Byte bit 0 mask. */ -#define XCL_CAPTL0_bp 0 /* TC16 Capture Value Low Byte bit 0 position. */ -#define XCL_CAPTL1_bm (1<<1) /* TC16 Capture Value Low Byte bit 1 mask. */ -#define XCL_CAPTL1_bp 1 /* TC16 Capture Value Low Byte bit 1 position. */ -#define XCL_CAPTL2_bm (1<<2) /* TC16 Capture Value Low Byte bit 2 mask. */ -#define XCL_CAPTL2_bp 2 /* TC16 Capture Value Low Byte bit 2 position. */ -#define XCL_CAPTL3_bm (1<<3) /* TC16 Capture Value Low Byte bit 3 mask. */ -#define XCL_CAPTL3_bp 3 /* TC16 Capture Value Low Byte bit 3 position. */ -#define XCL_CAPTL4_bm (1<<4) /* TC16 Capture Value Low Byte bit 4 mask. */ -#define XCL_CAPTL4_bp 4 /* TC16 Capture Value Low Byte bit 4 position. */ -#define XCL_CAPTL5_bm (1<<5) /* TC16 Capture Value Low Byte bit 5 mask. */ -#define XCL_CAPTL5_bp 5 /* TC16 Capture Value Low Byte bit 5 position. */ -#define XCL_CAPTL6_bm (1<<6) /* TC16 Capture Value Low Byte bit 6 mask. */ -#define XCL_CAPTL6_bp 6 /* TC16 Capture Value Low Byte bit 6 position. */ -#define XCL_CAPTL7_bm (1<<7) /* TC16 Capture Value Low Byte bit 7 mask. */ -#define XCL_CAPTL7_bp 7 /* TC16 Capture Value Low Byte bit 7 position. */ - -#define XCL_BPER0_gm 0xFF /* BTC0 Period group mask. */ -#define XCL_BPER0_gp 0 /* BTC0 Period group position. */ -#define XCL_BPER00_bm (1<<0) /* BTC0 Period bit 0 mask. */ -#define XCL_BPER00_bp 0 /* BTC0 Period bit 0 position. */ -#define XCL_BPER01_bm (1<<1) /* BTC0 Period bit 1 mask. */ -#define XCL_BPER01_bp 1 /* BTC0 Period bit 1 position. */ -#define XCL_BPER02_bm (1<<2) /* BTC0 Period bit 2 mask. */ -#define XCL_BPER02_bp 2 /* BTC0 Period bit 2 position. */ -#define XCL_BPER03_bm (1<<3) /* BTC0 Period bit 3 mask. */ -#define XCL_BPER03_bp 3 /* BTC0 Period bit 3 position. */ -#define XCL_BPER04_bm (1<<4) /* BTC0 Period bit 4 mask. */ -#define XCL_BPER04_bp 4 /* BTC0 Period bit 4 position. */ -#define XCL_BPER05_bm (1<<5) /* BTC0 Period bit 5 mask. */ -#define XCL_BPER05_bp 5 /* BTC0 Period bit 5 position. */ -#define XCL_BPER06_bm (1<<6) /* BTC0 Period bit 6 mask. */ -#define XCL_BPER06_bp 6 /* BTC0 Period bit 6 position. */ -#define XCL_BPER07_bm (1<<7) /* BTC0 Period bit 7 mask. */ -#define XCL_BPER07_bp 7 /* BTC0 Period bit 7 position. */ - -#define XCL_BCAPT0_gm 0xFF /* BTC0 Capture Value Byte group mask. */ -#define XCL_BCAPT0_gp 0 /* BTC0 Capture Value Byte group position. */ -#define XCL_BCAPT00_bm (1<<0) /* BTC0 Capture Value Byte bit 0 mask. */ -#define XCL_BCAPT00_bp 0 /* BTC0 Capture Value Byte bit 0 position. */ -#define XCL_BCAPT01_bm (1<<1) /* BTC0 Capture Value Byte bit 1 mask. */ -#define XCL_BCAPT01_bp 1 /* BTC0 Capture Value Byte bit 1 position. */ -#define XCL_BCAPT02_bm (1<<2) /* BTC0 Capture Value Byte bit 2 mask. */ -#define XCL_BCAPT02_bp 2 /* BTC0 Capture Value Byte bit 2 position. */ -#define XCL_BCAPT03_bm (1<<3) /* BTC0 Capture Value Byte bit 3 mask. */ -#define XCL_BCAPT03_bp 3 /* BTC0 Capture Value Byte bit 3 position. */ -#define XCL_BCAPT04_bm (1<<4) /* BTC0 Capture Value Byte bit 4 mask. */ -#define XCL_BCAPT04_bp 4 /* BTC0 Capture Value Byte bit 4 position. */ -#define XCL_BCAPT05_bm (1<<5) /* BTC0 Capture Value Byte bit 5 mask. */ -#define XCL_BCAPT05_bp 5 /* BTC0 Capture Value Byte bit 5 position. */ -#define XCL_BCAPT06_bm (1<<6) /* BTC0 Capture Value Byte bit 6 mask. */ -#define XCL_BCAPT06_bp 6 /* BTC0 Capture Value Byte bit 6 position. */ -#define XCL_BCAPT07_bm (1<<7) /* BTC0 Capture Value Byte bit 7 mask. */ -#define XCL_BCAPT07_bp 7 /* BTC0 Capture Value Byte bit 7 position. */ - -/* XCL.PERCAPTH bit masks and bit positions */ -#define XCL_PERH_gm 0xFF /* TC16 High Byte Period group mask. */ -#define XCL_PERH_gp 0 /* TC16 High Byte Period group position. */ -#define XCL_PERH0_bm (1<<0) /* TC16 High Byte Period bit 0 mask. */ -#define XCL_PERH0_bp 0 /* TC16 High Byte Period bit 0 position. */ -#define XCL_PERH1_bm (1<<1) /* TC16 High Byte Period bit 1 mask. */ -#define XCL_PERH1_bp 1 /* TC16 High Byte Period bit 1 position. */ -#define XCL_PERH2_bm (1<<2) /* TC16 High Byte Period bit 2 mask. */ -#define XCL_PERH2_bp 2 /* TC16 High Byte Period bit 2 position. */ -#define XCL_PERH3_bm (1<<3) /* TC16 High Byte Period bit 3 mask. */ -#define XCL_PERH3_bp 3 /* TC16 High Byte Period bit 3 position. */ -#define XCL_PERH4_bm (1<<4) /* TC16 High Byte Period bit 4 mask. */ -#define XCL_PERH4_bp 4 /* TC16 High Byte Period bit 4 position. */ -#define XCL_PERH5_bm (1<<5) /* TC16 High Byte Period bit 5 mask. */ -#define XCL_PERH5_bp 5 /* TC16 High Byte Period bit 5 position. */ -#define XCL_PERH6_bm (1<<6) /* TC16 High Byte Period bit 6 mask. */ -#define XCL_PERH6_bp 6 /* TC16 High Byte Period bit 6 position. */ -#define XCL_PERH7_bm (1<<7) /* TC16 High Byte Period bit 7 mask. */ -#define XCL_PERH7_bp 7 /* TC16 High Byte Period bit 7 position. */ - -#define XCL_CAPTH_gm 0xFF /* TC16 Capture Value High Byte group mask. */ -#define XCL_CAPTH_gp 0 /* TC16 Capture Value High Byte group position. */ -#define XCL_CAPTH0_bm (1<<0) /* TC16 Capture Value High Byte bit 0 mask. */ -#define XCL_CAPTH0_bp 0 /* TC16 Capture Value High Byte bit 0 position. */ -#define XCL_CAPTH1_bm (1<<1) /* TC16 Capture Value High Byte bit 1 mask. */ -#define XCL_CAPTH1_bp 1 /* TC16 Capture Value High Byte bit 1 position. */ -#define XCL_CAPTH2_bm (1<<2) /* TC16 Capture Value High Byte bit 2 mask. */ -#define XCL_CAPTH2_bp 2 /* TC16 Capture Value High Byte bit 2 position. */ -#define XCL_CAPTH3_bm (1<<3) /* TC16 Capture Value High Byte bit 3 mask. */ -#define XCL_CAPTH3_bp 3 /* TC16 Capture Value High Byte bit 3 position. */ -#define XCL_CAPTH4_bm (1<<4) /* TC16 Capture Value High Byte bit 4 mask. */ -#define XCL_CAPTH4_bp 4 /* TC16 Capture Value High Byte bit 4 position. */ -#define XCL_CAPTH5_bm (1<<5) /* TC16 Capture Value High Byte bit 5 mask. */ -#define XCL_CAPTH5_bp 5 /* TC16 Capture Value High Byte bit 5 position. */ -#define XCL_CAPTH6_bm (1<<6) /* TC16 Capture Value High Byte bit 6 mask. */ -#define XCL_CAPTH6_bp 6 /* TC16 Capture Value High Byte bit 6 position. */ -#define XCL_CAPTH7_bm (1<<7) /* TC16 Capture Value High Byte bit 7 mask. */ -#define XCL_CAPTH7_bp 7 /* TC16 Capture Value High Byte bit 7 position. */ - -#define XCL_BPER1_gm 0xFF /* BTC1 Period group mask. */ -#define XCL_BPER1_gp 0 /* BTC1 Period group position. */ -#define XCL_BPER10_bm (1<<0) /* BTC1 Period bit 0 mask. */ -#define XCL_BPER10_bp 0 /* BTC1 Period bit 0 position. */ -#define XCL_BPER11_bm (1<<1) /* BTC1 Period bit 1 mask. */ -#define XCL_BPER11_bp 1 /* BTC1 Period bit 1 position. */ -#define XCL_BPER12_bm (1<<2) /* BTC1 Period bit 2 mask. */ -#define XCL_BPER12_bp 2 /* BTC1 Period bit 2 position. */ -#define XCL_BPER13_bm (1<<3) /* BTC1 Period bit 3 mask. */ -#define XCL_BPER13_bp 3 /* BTC1 Period bit 3 position. */ -#define XCL_BPER14_bm (1<<4) /* BTC1 Period bit 4 mask. */ -#define XCL_BPER14_bp 4 /* BTC1 Period bit 4 position. */ -#define XCL_BPER15_bm (1<<5) /* BTC1 Period bit 5 mask. */ -#define XCL_BPER15_bp 5 /* BTC1 Period bit 5 position. */ -#define XCL_BPER16_bm (1<<6) /* BTC1 Period bit 6 mask. */ -#define XCL_BPER16_bp 6 /* BTC1 Period bit 6 position. */ -#define XCL_BPER17_bm (1<<7) /* BTC1 Period bit 7 mask. */ -#define XCL_BPER17_bp 7 /* BTC1 Period bit 7 position. */ - -#define XCL_BCAPT1_gm 0xFF /* BTC1 Capture Value Byte group mask. */ -#define XCL_BCAPT1_gp 0 /* BTC1 Capture Value Byte group position. */ -#define XCL_BCAPT10_bm (1<<0) /* BTC1 Capture Value Byte bit 0 mask. */ -#define XCL_BCAPT10_bp 0 /* BTC1 Capture Value Byte bit 0 position. */ -#define XCL_BCAPT11_bm (1<<1) /* BTC1 Capture Value Byte bit 1 mask. */ -#define XCL_BCAPT11_bp 1 /* BTC1 Capture Value Byte bit 1 position. */ -#define XCL_BCAPT12_bm (1<<2) /* BTC1 Capture Value Byte bit 2 mask. */ -#define XCL_BCAPT12_bp 2 /* BTC1 Capture Value Byte bit 2 position. */ -#define XCL_BCAPT13_bm (1<<3) /* BTC1 Capture Value Byte bit 3 mask. */ -#define XCL_BCAPT13_bp 3 /* BTC1 Capture Value Byte bit 3 position. */ -#define XCL_BCAPT14_bm (1<<4) /* BTC1 Capture Value Byte bit 4 mask. */ -#define XCL_BCAPT14_bp 4 /* BTC1 Capture Value Byte bit 4 position. */ -#define XCL_BCAPT15_bm (1<<5) /* BTC1 Capture Value Byte bit 5 mask. */ -#define XCL_BCAPT15_bp 5 /* BTC1 Capture Value Byte bit 5 position. */ -#define XCL_BCAPT16_bm (1<<6) /* BTC1 Capture Value Byte bit 6 mask. */ -#define XCL_BCAPT16_bp 6 /* BTC1 Capture Value Byte bit 6 position. */ -#define XCL_BCAPT17_bm (1<<7) /* BTC1 Capture Value Byte bit 7 mask. */ -#define XCL_BCAPT17_bp 7 /* BTC1 Capture Value Byte bit 7 position. */ - -/* TWI - Two-Wire Interface */ -/* TWI.CTRL bit masks and bit positions */ -#define TWI_BRIDGEEN_bm 0x80 /* Bridge Enable bit mask. */ -#define TWI_BRIDGEEN_bp 7 /* Bridge Enable bit position. */ - -#define TWI_SFMPEN_bm 0x40 /* Slave Fast Mode Plus Enable bit mask. */ -#define TWI_SFMPEN_bp 6 /* Slave Fast Mode Plus Enable bit position. */ - -#define TWI_SSDAHOLD_gm 0x30 /* Slave SDA Hold Time Enable group mask. */ -#define TWI_SSDAHOLD_gp 4 /* Slave SDA Hold Time Enable group position. */ -#define TWI_SSDAHOLD0_bm (1<<4) /* Slave SDA Hold Time Enable bit 0 mask. */ -#define TWI_SSDAHOLD0_bp 4 /* Slave SDA Hold Time Enable bit 0 position. */ -#define TWI_SSDAHOLD1_bm (1<<5) /* Slave SDA Hold Time Enable bit 1 mask. */ -#define TWI_SSDAHOLD1_bp 5 /* Slave SDA Hold Time Enable bit 1 position. */ - -#define TWI_FMPEN_bm 0x08 /* FMPLUS Enable bit mask. */ -#define TWI_FMPEN_bp 3 /* FMPLUS Enable bit position. */ - -#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ -#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ -#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ -#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ -#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ -#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ - -#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ -#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ - -/* TWI_MASTER.CTRLA bit masks and bit positions */ -#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ -#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ - -#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ -#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ - -#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ -#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ - -#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ -#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ - -/* TWI_MASTER.CTRLB bit masks and bit positions */ -#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ -#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ -#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ -#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ -#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ -#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ - -#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ -#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ - -#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ - -#define TWI_MASTER_TTOUTEN_bm 0x10 /* Ttimeout Enable bit mask. */ -#define TWI_MASTER_TTOUTEN_bp 4 /* Ttimeout Enable bit position. */ - -#define TWI_MASTER_TSEXTEN_bm 0x20 /* Slave Extend Timeout Enable bit mask. */ -#define TWI_MASTER_TSEXTEN_bp 5 /* Slave Extend Timeout Enable bit position. */ - -#define TWI_MASTER_TMEXTEN_bm 0x40 /* Master Extend Timeout Enable bit mask. */ -#define TWI_MASTER_TMEXTEN_bp 6 /* Master Extend Timeout Enable bit position. */ - -#define TWI_MASTER_TOIE_bm 0x80 /* Timeout Interrupt Enable bit mask. */ -#define TWI_MASTER_TOIE_bp 7 /* Timeout Interrupt Enable bit position. */ - -/* TWI_MASTER.CTRLC bit masks and bit positions */ -#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ - -#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ -#define TWI_MASTER_CMD_gp 0 /* Command group position. */ -#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ -#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ - -/* TWI_MASTER.STATUS bit masks and bit positions */ -#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ -#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ - -#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ -#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ - -#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ - -#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ - -#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ -#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ - -#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ -#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ - -#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ -#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ -#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ -#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ -#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ -#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ - -/* TWI_SLAVE.CTRLA bit masks and bit positions */ -#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ -#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ - -#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ -#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ - -#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ -#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ - -#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ -#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ - -#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ -#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ - -#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ -#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ - -#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ - -/* TWI_SLAVE.CTRLB bit masks and bit positions */ -#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ - -#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ -#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ -#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ -#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ - -#define TWI_SLAVE_TTOUTEN_bm 0x10 /* Ttimeout Enable bit mask. */ -#define TWI_SLAVE_TTOUTEN_bp 4 /* Ttimeout Enable bit position. */ - -#define TWI_SLAVE_TOIE_bm 0x80 /* Timeout Interrupt Enable bit mask. */ -#define TWI_SLAVE_TOIE_bp 7 /* Timeout Interrupt Enable bit position. */ - -/* TWI_SLAVE.STATUS bit masks and bit positions */ -#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ -#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ - -#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ -#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ - -#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ - -#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ - -#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ -#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ - -#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ -#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ - -#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ -#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ - -#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ -#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ - -/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ -#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ -#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ -#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ -#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ -#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ -#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ -#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ -#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ -#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ -#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ -#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ -#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ -#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ -#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ -#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ -#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ - -#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ -#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ - -/* TWI_TIMEOUT.TOS bit masks and bit positions */ -#define TWI_TIMEOUT_TTOUTMIF_bm 0x01 /* Master Ttimeout Interrupt Flag bit mask. */ -#define TWI_TIMEOUT_TTOUTMIF_bp 0 /* Master Ttimeout Interrupt Flag bit position. */ - -#define TWI_TIMEOUT_TSEXTIF_bm 0x02 /* Slave Extend Interrupt Flag bit mask. */ -#define TWI_TIMEOUT_TSEXTIF_bp 1 /* Slave Extend Interrupt Flag bit position. */ - -#define TWI_TIMEOUT_TMEXTIF_bm 0x04 /* Master Extend Interrupt Flag bit mask. */ -#define TWI_TIMEOUT_TMEXTIF_bp 2 /* Master Extend Interrupt Flag bit position. */ - -#define TWI_TIMEOUT_TTOUTSIF_bm 0x10 /* Slave Ttimeout Interrupt Flag bit mask. */ -#define TWI_TIMEOUT_TTOUTSIF_bp 4 /* Slave Ttimeout Interrupt Flag bit position. */ - -/* TWI_TIMEOUT.TOCONF bit masks and bit positions */ -#define TWI_TIMEOUT_TTOUTMSEL_gm 0x07 /* Master Ttimeout Select group mask. */ -#define TWI_TIMEOUT_TTOUTMSEL_gp 0 /* Master Ttimeout Select group position. */ -#define TWI_TIMEOUT_TTOUTMSEL0_bm (1<<0) /* Master Ttimeout Select bit 0 mask. */ -#define TWI_TIMEOUT_TTOUTMSEL0_bp 0 /* Master Ttimeout Select bit 0 position. */ -#define TWI_TIMEOUT_TTOUTMSEL1_bm (1<<1) /* Master Ttimeout Select bit 1 mask. */ -#define TWI_TIMEOUT_TTOUTMSEL1_bp 1 /* Master Ttimeout Select bit 1 position. */ -#define TWI_TIMEOUT_TTOUTMSEL2_bm (1<<2) /* Master Ttimeout Select bit 2 mask. */ -#define TWI_TIMEOUT_TTOUTMSEL2_bp 2 /* Master Ttimeout Select bit 2 position. */ - -#define TWI_TIMEOUT_TMSEXTSEL_gm 0x18 /* Master/Slave Timeout Select group mask. */ -#define TWI_TIMEOUT_TMSEXTSEL_gp 3 /* Master/Slave Timeout Select group position. */ -#define TWI_TIMEOUT_TMSEXTSEL0_bm (1<<3) /* Master/Slave Timeout Select bit 0 mask. */ -#define TWI_TIMEOUT_TMSEXTSEL0_bp 3 /* Master/Slave Timeout Select bit 0 position. */ -#define TWI_TIMEOUT_TMSEXTSEL1_bm (1<<4) /* Master/Slave Timeout Select bit 1 mask. */ -#define TWI_TIMEOUT_TMSEXTSEL1_bp 4 /* Master/Slave Timeout Select bit 1 position. */ - -#define TWI_TIMEOUT_TTOUTSSEL_gm 0xE0 /* Slave Ttimeout Select group mask. */ -#define TWI_TIMEOUT_TTOUTSSEL_gp 5 /* Slave Ttimeout Select group position. */ -#define TWI_TIMEOUT_TTOUTSSEL0_bm (1<<5) /* Slave Ttimeout Select bit 0 mask. */ -#define TWI_TIMEOUT_TTOUTSSEL0_bp 5 /* Slave Ttimeout Select bit 0 position. */ -#define TWI_TIMEOUT_TTOUTSSEL1_bm (1<<6) /* Slave Ttimeout Select bit 1 mask. */ -#define TWI_TIMEOUT_TTOUTSSEL1_bp 6 /* Slave Ttimeout Select bit 1 position. */ -#define TWI_TIMEOUT_TTOUTSSEL2_bm (1<<7) /* Slave Ttimeout Select bit 2 mask. */ -#define TWI_TIMEOUT_TTOUTSSEL2_bp 7 /* Slave Ttimeout Select bit 2 position. */ - -/* PORT - Port Configuration */ -/* PORT.INTCTRL bit masks and bit positions */ -#define PORT_INTLVL_gm 0x03 /* Port Interrupt Level group mask. */ -#define PORT_INTLVL_gp 0 /* Port Interrupt Level group position. */ -#define PORT_INTLVL0_bm (1<<0) /* Port Interrupt Level bit 0 mask. */ -#define PORT_INTLVL0_bp 0 /* Port Interrupt Level bit 0 position. */ -#define PORT_INTLVL1_bm (1<<1) /* Port Interrupt Level bit 1 mask. */ -#define PORT_INTLVL1_bp 1 /* Port Interrupt Level bit 1 position. */ - -/* PORT.INTFLAGS bit masks and bit positions */ -#define PORT_INT7IF_bm 0x80 /* Pin 7 Interrupt Flag bit mask. */ -#define PORT_INT7IF_bp 7 /* Pin 7 Interrupt Flag bit position. */ - -#define PORT_INT6IF_bm 0x40 /* Pin 6 Interrupt Flag bit mask. */ -#define PORT_INT6IF_bp 6 /* Pin 6 Interrupt Flag bit position. */ - -#define PORT_INT5IF_bm 0x20 /* Pin 5 Interrupt Flag bit mask. */ -#define PORT_INT5IF_bp 5 /* Pin 5 Interrupt Flag bit position. */ - -#define PORT_INT4IF_bm 0x10 /* Pin 4 Interrupt Flag bit mask. */ -#define PORT_INT4IF_bp 4 /* Pin 4 Interrupt Flag bit position. */ - -#define PORT_INT3IF_bm 0x08 /* Pin 3 Interrupt Flag bit mask. */ -#define PORT_INT3IF_bp 3 /* Pin 3 Interrupt Flag bit position. */ - -#define PORT_INT2IF_bm 0x04 /* Pin 2 Interrupt Flag bit mask. */ -#define PORT_INT2IF_bp 2 /* Pin 2 Interrupt Flag bit position. */ - -#define PORT_INT1IF_bm 0x02 /* Pin 1 Interrupt Flag bit mask. */ -#define PORT_INT1IF_bp 1 /* Pin 1 Interrupt Flag bit position. */ - -#define PORT_INT0IF_bm 0x01 /* Pin 0 Interrupt Flag bit mask. */ -#define PORT_INT0IF_bp 0 /* Pin 0 Interrupt Flag bit position. */ - -/* PORT.REMAP bit masks and bit positions */ -#define PORT_USART0_bm 0x10 /* Usart0 bit mask. */ -#define PORT_USART0_bp 4 /* Usart0 bit position. */ - -#define PORT_TC4D_bm 0x08 /* Timer/Counter 4 Output Compare D bit mask. */ -#define PORT_TC4D_bp 3 /* Timer/Counter 4 Output Compare D bit position. */ - -#define PORT_TC4C_bm 0x04 /* Timer/Counter 4 Output Compare C bit mask. */ -#define PORT_TC4C_bp 2 /* Timer/Counter 4 Output Compare C bit position. */ - -#define PORT_TC4B_bm 0x02 /* Timer/Counter 4 Output Compare B bit mask. */ -#define PORT_TC4B_bp 1 /* Timer/Counter 4 Output Compare B bit position. */ - -#define PORT_TC4A_bm 0x01 /* Timer/Counter 4 Output Compare A bit mask. */ -#define PORT_TC4A_bp 0 /* Timer/Counter 4 Output Compare A bit position. */ - -/* PORT.PIN0CTRL bit masks and bit positions */ -#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ -#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ - -#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ -#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ -#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ -#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ -#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ -#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ -#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ -#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ - -#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ -#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ -#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ -#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ -#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ -#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ -#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ -#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ - -/* PORT.PIN1CTRL bit masks and bit positions */ -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN2CTRL bit masks and bit positions */ -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN3CTRL bit masks and bit positions */ -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN4CTRL bit masks and bit positions */ -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN5CTRL bit masks and bit positions */ -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN6CTRL bit masks and bit positions */ -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN7CTRL bit masks and bit positions */ -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* TC - 16-bit Timer/Counter With PWM */ -/* TC4.CTRLA bit masks and bit positions */ -#define TC4_SYNCHEN_bm 0x40 /* Synchronization Enabled bit mask. */ -#define TC4_SYNCHEN_bp 6 /* Synchronization Enabled bit position. */ - -#define TC4_EVSTART_bm 0x20 /* Start on Next Event bit mask. */ -#define TC4_EVSTART_bp 5 /* Start on Next Event bit position. */ - -#define TC4_UPSTOP_bm 0x10 /* Stop on Next Update bit mask. */ -#define TC4_UPSTOP_bp 4 /* Stop on Next Update bit position. */ - -#define TC4_CLKSEL_gm 0x0F /* Clock Select group mask. */ -#define TC4_CLKSEL_gp 0 /* Clock Select group position. */ -#define TC4_CLKSEL0_bm (1<<0) /* Clock Select bit 0 mask. */ -#define TC4_CLKSEL0_bp 0 /* Clock Select bit 0 position. */ -#define TC4_CLKSEL1_bm (1<<1) /* Clock Select bit 1 mask. */ -#define TC4_CLKSEL1_bp 1 /* Clock Select bit 1 position. */ -#define TC4_CLKSEL2_bm (1<<2) /* Clock Select bit 2 mask. */ -#define TC4_CLKSEL2_bp 2 /* Clock Select bit 2 position. */ -#define TC4_CLKSEL3_bm (1<<3) /* Clock Select bit 3 mask. */ -#define TC4_CLKSEL3_bp 3 /* Clock Select bit 3 position. */ - -/* TC4.CTRLB bit masks and bit positions */ -#define TC4_BYTEM_gm 0xC0 /* Byte Mode group mask. */ -#define TC4_BYTEM_gp 6 /* Byte Mode group position. */ -#define TC4_BYTEM0_bm (1<<6) /* Byte Mode bit 0 mask. */ -#define TC4_BYTEM0_bp 6 /* Byte Mode bit 0 position. */ -#define TC4_BYTEM1_bm (1<<7) /* Byte Mode bit 1 mask. */ -#define TC4_BYTEM1_bp 7 /* Byte Mode bit 1 position. */ - -#define TC4_CIRCEN_gm 0x30 /* Circular Buffer Enable group mask. */ -#define TC4_CIRCEN_gp 4 /* Circular Buffer Enable group position. */ -#define TC4_CIRCEN0_bm (1<<4) /* Circular Buffer Enable bit 0 mask. */ -#define TC4_CIRCEN0_bp 4 /* Circular Buffer Enable bit 0 position. */ -#define TC4_CIRCEN1_bm (1<<5) /* Circular Buffer Enable bit 1 mask. */ -#define TC4_CIRCEN1_bp 5 /* Circular Buffer Enable bit 1 position. */ - -#define TC4_WGMODE_gm 0x07 /* Waveform Generation Mode group mask. */ -#define TC4_WGMODE_gp 0 /* Waveform Generation Mode group position. */ -#define TC4_WGMODE0_bm (1<<0) /* Waveform Generation Mode bit 0 mask. */ -#define TC4_WGMODE0_bp 0 /* Waveform Generation Mode bit 0 position. */ -#define TC4_WGMODE1_bm (1<<1) /* Waveform Generation Mode bit 1 mask. */ -#define TC4_WGMODE1_bp 1 /* Waveform Generation Mode bit 1 position. */ -#define TC4_WGMODE2_bm (1<<2) /* Waveform Generation Mode bit 2 mask. */ -#define TC4_WGMODE2_bp 2 /* Waveform Generation Mode bit 2 position. */ - -/* TC4.CTRLC bit masks and bit positions */ -#define TC4_POLD_bm 0x80 /* Channel D Output Polarity bit mask. */ -#define TC4_POLD_bp 7 /* Channel D Output Polarity bit position. */ - -#define TC4_POLC_bm 0x40 /* Channel C Output Polarity bit mask. */ -#define TC4_POLC_bp 6 /* Channel C Output Polarity bit position. */ - -#define TC4_POLB_bm 0x20 /* Channel B Output Polarity bit mask. */ -#define TC4_POLB_bp 5 /* Channel B Output Polarity bit position. */ - -#define TC4_POLA_bm 0x10 /* Channel A Output Polarity bit mask. */ -#define TC4_POLA_bp 4 /* Channel A Output Polarity bit position. */ - -#define TC4_CMPD_bm 0x08 /* Channel D Compare Output Value bit mask. */ -#define TC4_CMPD_bp 3 /* Channel D Compare Output Value bit position. */ - -#define TC4_CMPC_bm 0x04 /* Channel C Compare Output Value bit mask. */ -#define TC4_CMPC_bp 2 /* Channel C Compare Output Value bit position. */ - -#define TC4_CMPB_bm 0x02 /* Channel B Compare Output Value bit mask. */ -#define TC4_CMPB_bp 1 /* Channel B Compare Output Value bit position. */ - -#define TC4_CMPA_bm 0x01 /* Channel A Compare Output Value bit mask. */ -#define TC4_CMPA_bp 0 /* Channel A Compare Output Value bit position. */ - -#define TC4_HCMPD_bm 0x80 /* High Channel D Compare Output Value bit mask. */ -#define TC4_HCMPD_bp 7 /* High Channel D Compare Output Value bit position. */ - -#define TC4_HCMPC_bm 0x40 /* High Channel C Compare Output Value bit mask. */ -#define TC4_HCMPC_bp 6 /* High Channel C Compare Output Value bit position. */ - -#define TC4_HCMPB_bm 0x20 /* High Channel B Compare Output Value bit mask. */ -#define TC4_HCMPB_bp 5 /* High Channel B Compare Output Value bit position. */ - -#define TC4_HCMPA_bm 0x10 /* High Channel A Compare Output Value bit mask. */ -#define TC4_HCMPA_bp 4 /* High Channel A Compare Output Value bit position. */ - -#define TC4_LCMPD_bm 0x08 /* Low Channel D Compare Output Value bit mask. */ -#define TC4_LCMPD_bp 3 /* Low Channel D Compare Output Value bit position. */ - -#define TC4_LCMPC_bm 0x04 /* Low Channel C Compare Output Value bit mask. */ -#define TC4_LCMPC_bp 2 /* Low Channel C Compare Output Value bit position. */ - -#define TC4_LCMPB_bm 0x02 /* Low Channel B Compare Output Value bit mask. */ -#define TC4_LCMPB_bp 1 /* Low Channel B Compare Output Value bit position. */ - -#define TC4_LCMPA_bm 0x01 /* Low Channel A Compare Output Value bit mask. */ -#define TC4_LCMPA_bp 0 /* Low Channel A Compare Output Value bit position. */ - -/* TC4.CTRLD bit masks and bit positions */ -#define TC4_EVACT_gm 0xE0 /* Event Action group mask. */ -#define TC4_EVACT_gp 5 /* Event Action group position. */ -#define TC4_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -#define TC4_EVACT0_bp 5 /* Event Action bit 0 position. */ -#define TC4_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -#define TC4_EVACT1_bp 6 /* Event Action bit 1 position. */ -#define TC4_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -#define TC4_EVACT2_bp 7 /* Event Action bit 2 position. */ - -#define TC4_EVDLY_bm 0x10 /* Event Delay bit mask. */ -#define TC4_EVDLY_bp 4 /* Event Delay bit position. */ - -#define TC4_EVSEL_gm 0x0F /* Event Source Select group mask. */ -#define TC4_EVSEL_gp 0 /* Event Source Select group position. */ -#define TC4_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -#define TC4_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -#define TC4_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -#define TC4_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -#define TC4_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -#define TC4_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -#define TC4_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -#define TC4_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - -/* TC4.CTRLE bit masks and bit positions */ -#define TC4_CCDMODE_gm 0xC0 /* Channel D Compare or Capture Mode group mask. */ -#define TC4_CCDMODE_gp 6 /* Channel D Compare or Capture Mode group position. */ -#define TC4_CCDMODE0_bm (1<<6) /* Channel D Compare or Capture Mode bit 0 mask. */ -#define TC4_CCDMODE0_bp 6 /* Channel D Compare or Capture Mode bit 0 position. */ -#define TC4_CCDMODE1_bm (1<<7) /* Channel D Compare or Capture Mode bit 1 mask. */ -#define TC4_CCDMODE1_bp 7 /* Channel D Compare or Capture Mode bit 1 position. */ - -#define TC4_CCCMODE_gm 0x30 /* Channel C Compare or Capture Mode group mask. */ -#define TC4_CCCMODE_gp 4 /* Channel C Compare or Capture Mode group position. */ -#define TC4_CCCMODE0_bm (1<<4) /* Channel C Compare or Capture Mode bit 0 mask. */ -#define TC4_CCCMODE0_bp 4 /* Channel C Compare or Capture Mode bit 0 position. */ -#define TC4_CCCMODE1_bm (1<<5) /* Channel C Compare or Capture Mode bit 1 mask. */ -#define TC4_CCCMODE1_bp 5 /* Channel C Compare or Capture Mode bit 1 position. */ - -#define TC4_CCBMODE_gm 0x0C /* Channel B Compare or Capture Mode group mask. */ -#define TC4_CCBMODE_gp 2 /* Channel B Compare or Capture Mode group position. */ -#define TC4_CCBMODE0_bm (1<<2) /* Channel B Compare or Capture Mode bit 0 mask. */ -#define TC4_CCBMODE0_bp 2 /* Channel B Compare or Capture Mode bit 0 position. */ -#define TC4_CCBMODE1_bm (1<<3) /* Channel B Compare or Capture Mode bit 1 mask. */ -#define TC4_CCBMODE1_bp 3 /* Channel B Compare or Capture Mode bit 1 position. */ - -#define TC4_CCAMODE_gm 0x03 /* Channel A Compare or Capture Mode group mask. */ -#define TC4_CCAMODE_gp 0 /* Channel A Compare or Capture Mode group position. */ -#define TC4_CCAMODE0_bm (1<<0) /* Channel A Compare or Capture Mode bit 0 mask. */ -#define TC4_CCAMODE0_bp 0 /* Channel A Compare or Capture Mode bit 0 position. */ -#define TC4_CCAMODE1_bm (1<<1) /* Channel A Compare or Capture Mode bit 1 mask. */ -#define TC4_CCAMODE1_bp 1 /* Channel A Compare or Capture Mode bit 1 position. */ - -#define TC4_LCCDMODE_gm 0xC0 /* Channel Low D Compare or Capture Mode group mask. */ -#define TC4_LCCDMODE_gp 6 /* Channel Low D Compare or Capture Mode group position. */ -#define TC4_LCCDMODE0_bm (1<<6) /* Channel Low D Compare or Capture Mode bit 0 mask. */ -#define TC4_LCCDMODE0_bp 6 /* Channel Low D Compare or Capture Mode bit 0 position. */ -#define TC4_LCCDMODE1_bm (1<<7) /* Channel Low D Compare or Capture Mode bit 1 mask. */ -#define TC4_LCCDMODE1_bp 7 /* Channel Low D Compare or Capture Mode bit 1 position. */ - -#define TC4_LCCCMODE_gm 0x30 /* Channel Low C Compare or Capture Mode group mask. */ -#define TC4_LCCCMODE_gp 4 /* Channel Low C Compare or Capture Mode group position. */ -#define TC4_LCCCMODE0_bm (1<<4) /* Channel Low C Compare or Capture Mode bit 0 mask. */ -#define TC4_LCCCMODE0_bp 4 /* Channel Low C Compare or Capture Mode bit 0 position. */ -#define TC4_LCCCMODE1_bm (1<<5) /* Channel Low C Compare or Capture Mode bit 1 mask. */ -#define TC4_LCCCMODE1_bp 5 /* Channel Low C Compare or Capture Mode bit 1 position. */ - -#define TC4_LCCBMODE_gm 0x0C /* Channel Low B Compare or Capture Mode group mask. */ -#define TC4_LCCBMODE_gp 2 /* Channel Low B Compare or Capture Mode group position. */ -#define TC4_LCCBMODE0_bm (1<<2) /* Channel Low B Compare or Capture Mode bit 0 mask. */ -#define TC4_LCCBMODE0_bp 2 /* Channel Low B Compare or Capture Mode bit 0 position. */ -#define TC4_LCCBMODE1_bm (1<<3) /* Channel Low B Compare or Capture Mode bit 1 mask. */ -#define TC4_LCCBMODE1_bp 3 /* Channel Low B Compare or Capture Mode bit 1 position. */ - -#define TC4_LCCAMODE_gm 0x03 /* Channel Low A Compare or Capture Mode group mask. */ -#define TC4_LCCAMODE_gp 0 /* Channel Low A Compare or Capture Mode group position. */ -#define TC4_LCCAMODE0_bm (1<<0) /* Channel Low A Compare or Capture Mode bit 0 mask. */ -#define TC4_LCCAMODE0_bp 0 /* Channel Low A Compare or Capture Mode bit 0 position. */ -#define TC4_LCCAMODE1_bm (1<<1) /* Channel Low A Compare or Capture Mode bit 1 mask. */ -#define TC4_LCCAMODE1_bp 1 /* Channel Low A Compare or Capture Mode bit 1 position. */ - -/* TC4.CTRLF bit masks and bit positions */ -#define TC4_HCCDMODE_gm 0xC0 /* Channel High D Compare or Capture Mode group mask. */ -#define TC4_HCCDMODE_gp 6 /* Channel High D Compare or Capture Mode group position. */ -#define TC4_HCCDMODE0_bm (1<<6) /* Channel High D Compare or Capture Mode bit 0 mask. */ -#define TC4_HCCDMODE0_bp 6 /* Channel High D Compare or Capture Mode bit 0 position. */ -#define TC4_HCCDMODE1_bm (1<<7) /* Channel High D Compare or Capture Mode bit 1 mask. */ -#define TC4_HCCDMODE1_bp 7 /* Channel High D Compare or Capture Mode bit 1 position. */ - -#define TC4_HCCCMODE_gm 0x30 /* Channel High C Compare or Capture Mode group mask. */ -#define TC4_HCCCMODE_gp 4 /* Channel High C Compare or Capture Mode group position. */ -#define TC4_HCCCMODE0_bm (1<<4) /* Channel High C Compare or Capture Mode bit 0 mask. */ -#define TC4_HCCCMODE0_bp 4 /* Channel High C Compare or Capture Mode bit 0 position. */ -#define TC4_HCCCMODE1_bm (1<<5) /* Channel High C Compare or Capture Mode bit 1 mask. */ -#define TC4_HCCCMODE1_bp 5 /* Channel High C Compare or Capture Mode bit 1 position. */ - -#define TC4_HCCBMODE_gm 0x0C /* Channel High B Compare or Capture Mode group mask. */ -#define TC4_HCCBMODE_gp 2 /* Channel High B Compare or Capture Mode group position. */ -#define TC4_HCCBMODE0_bm (1<<2) /* Channel High B Compare or Capture Mode bit 0 mask. */ -#define TC4_HCCBMODE0_bp 2 /* Channel High B Compare or Capture Mode bit 0 position. */ -#define TC4_HCCBMODE1_bm (1<<3) /* Channel High B Compare or Capture Mode bit 1 mask. */ -#define TC4_HCCBMODE1_bp 3 /* Channel High B Compare or Capture Mode bit 1 position. */ - -#define TC4_HCCAMODE_gm 0x03 /* Channel High A Compare or Capture Mode group mask. */ -#define TC4_HCCAMODE_gp 0 /* Channel High A Compare or Capture Mode group position. */ -#define TC4_HCCAMODE0_bm (1<<0) /* Channel High A Compare or Capture Mode bit 0 mask. */ -#define TC4_HCCAMODE0_bp 0 /* Channel High A Compare or Capture Mode bit 0 position. */ -#define TC4_HCCAMODE1_bm (1<<1) /* Channel High A Compare or Capture Mode bit 1 mask. */ -#define TC4_HCCAMODE1_bp 1 /* Channel High A Compare or Capture Mode bit 1 position. */ - -/* TC4.INTCTRLA bit masks and bit positions */ -#define TC4_TRGINTLVL_gm 0x30 /* Timer Trigger Restart Interrupt Level group mask. */ -#define TC4_TRGINTLVL_gp 4 /* Timer Trigger Restart Interrupt Level group position. */ -#define TC4_TRGINTLVL0_bm (1<<4) /* Timer Trigger Restart Interrupt Level bit 0 mask. */ -#define TC4_TRGINTLVL0_bp 4 /* Timer Trigger Restart Interrupt Level bit 0 position. */ -#define TC4_TRGINTLVL1_bm (1<<5) /* Timer Trigger Restart Interrupt Level bit 1 mask. */ -#define TC4_TRGINTLVL1_bp 5 /* Timer Trigger Restart Interrupt Level bit 1 position. */ - -#define TC4_ERRINTLVL_gm 0x0C /* Timer Error Interrupt Level group mask. */ -#define TC4_ERRINTLVL_gp 2 /* Timer Error Interrupt Level group position. */ -#define TC4_ERRINTLVL0_bm (1<<2) /* Timer Error Interrupt Level bit 0 mask. */ -#define TC4_ERRINTLVL0_bp 2 /* Timer Error Interrupt Level bit 0 position. */ -#define TC4_ERRINTLVL1_bm (1<<3) /* Timer Error Interrupt Level bit 1 mask. */ -#define TC4_ERRINTLVL1_bp 3 /* Timer Error Interrupt Level bit 1 position. */ - -#define TC4_OVFINTLVL_gm 0x03 /* Timer Overflow/Underflow Interrupt Level group mask. */ -#define TC4_OVFINTLVL_gp 0 /* Timer Overflow/Underflow Interrupt Level group position. */ -#define TC4_OVFINTLVL0_bm (1<<0) /* Timer Overflow/Underflow Interrupt Level bit 0 mask. */ -#define TC4_OVFINTLVL0_bp 0 /* Timer Overflow/Underflow Interrupt Level bit 0 position. */ -#define TC4_OVFINTLVL1_bm (1<<1) /* Timer Overflow/Underflow Interrupt Level bit 1 mask. */ -#define TC4_OVFINTLVL1_bp 1 /* Timer Overflow/Underflow Interrupt Level bit 1 position. */ - -/* TC4.INTCTRLB bit masks and bit positions */ -#define TC4_CCDINTLVL_gm 0xC0 /* Channel D Compare or Capture Interrupt Level group mask. */ -#define TC4_CCDINTLVL_gp 6 /* Channel D Compare or Capture Interrupt Level group position. */ -#define TC4_CCDINTLVL0_bm (1<<6) /* Channel D Compare or Capture Interrupt Level bit 0 mask. */ -#define TC4_CCDINTLVL0_bp 6 /* Channel D Compare or Capture Interrupt Level bit 0 position. */ -#define TC4_CCDINTLVL1_bm (1<<7) /* Channel D Compare or Capture Interrupt Level bit 1 mask. */ -#define TC4_CCDINTLVL1_bp 7 /* Channel D Compare or Capture Interrupt Level bit 1 position. */ - -#define TC4_CCCINTLVL_gm 0x30 /* Channel C Compare or Capture Interrupt Level group mask. */ -#define TC4_CCCINTLVL_gp 4 /* Channel C Compare or Capture Interrupt Level group position. */ -#define TC4_CCCINTLVL0_bm (1<<4) /* Channel C Compare or Capture Interrupt Level bit 0 mask. */ -#define TC4_CCCINTLVL0_bp 4 /* Channel C Compare or Capture Interrupt Level bit 0 position. */ -#define TC4_CCCINTLVL1_bm (1<<5) /* Channel C Compare or Capture Interrupt Level bit 1 mask. */ -#define TC4_CCCINTLVL1_bp 5 /* Channel C Compare or Capture Interrupt Level bit 1 position. */ - -#define TC4_CCBINTLVL_gm 0x0C /* Channel B Compare or Capture Interrupt Level group mask. */ -#define TC4_CCBINTLVL_gp 2 /* Channel B Compare or Capture Interrupt Level group position. */ -#define TC4_CCBINTLVL0_bm (1<<2) /* Channel B Compare or Capture Interrupt Level bit 0 mask. */ -#define TC4_CCBINTLVL0_bp 2 /* Channel B Compare or Capture Interrupt Level bit 0 position. */ -#define TC4_CCBINTLVL1_bm (1<<3) /* Channel B Compare or Capture Interrupt Level bit 1 mask. */ -#define TC4_CCBINTLVL1_bp 3 /* Channel B Compare or Capture Interrupt Level bit 1 position. */ - -#define TC4_CCAINTLVL_gm 0x03 /* Channel A Compare or Capture Interrupt Level group mask. */ -#define TC4_CCAINTLVL_gp 0 /* Channel A Compare or Capture Interrupt Level group position. */ -#define TC4_CCAINTLVL0_bm (1<<0) /* Channel A Compare or Capture Interrupt Level bit 0 mask. */ -#define TC4_CCAINTLVL0_bp 0 /* Channel A Compare or Capture Interrupt Level bit 0 position. */ -#define TC4_CCAINTLVL1_bm (1<<1) /* Channel A Compare or Capture Interrupt Level bit 1 mask. */ -#define TC4_CCAINTLVL1_bp 1 /* Channel A Compare or Capture Interrupt Level bit 1 position. */ - -#define TC4_LCCDINTLVL_gm 0xC0 /* Channel Low D Compare or Capture Interrupt Level group mask. */ -#define TC4_LCCDINTLVL_gp 6 /* Channel Low D Compare or Capture Interrupt Level group position. */ -#define TC4_LCCDINTLVL0_bm (1<<6) /* Channel Low D Compare or Capture Interrupt Level bit 0 mask. */ -#define TC4_LCCDINTLVL0_bp 6 /* Channel Low D Compare or Capture Interrupt Level bit 0 position. */ -#define TC4_LCCDINTLVL1_bm (1<<7) /* Channel Low D Compare or Capture Interrupt Level bit 1 mask. */ -#define TC4_LCCDINTLVL1_bp 7 /* Channel Low D Compare or Capture Interrupt Level bit 1 position. */ - -#define TC4_LCCCINTLVL_gm 0x30 /* Channel Low C Compare or Capture Interrupt Level group mask. */ -#define TC4_LCCCINTLVL_gp 4 /* Channel Low C Compare or Capture Interrupt Level group position. */ -#define TC4_LCCCINTLVL0_bm (1<<4) /* Channel Low C Compare or Capture Interrupt Level bit 0 mask. */ -#define TC4_LCCCINTLVL0_bp 4 /* Channel Low C Compare or Capture Interrupt Level bit 0 position. */ -#define TC4_LCCCINTLVL1_bm (1<<5) /* Channel Low C Compare or Capture Interrupt Level bit 1 mask. */ -#define TC4_LCCCINTLVL1_bp 5 /* Channel Low C Compare or Capture Interrupt Level bit 1 position. */ - -#define TC4_LCCBINTLVL_gm 0x0C /* Channel Low B Compare or Capture Interrupt Level group mask. */ -#define TC4_LCCBINTLVL_gp 2 /* Channel Low B Compare or Capture Interrupt Level group position. */ -#define TC4_LCCBINTLVL0_bm (1<<2) /* Channel Low B Compare or Capture Interrupt Level bit 0 mask. */ -#define TC4_LCCBINTLVL0_bp 2 /* Channel Low B Compare or Capture Interrupt Level bit 0 position. */ -#define TC4_LCCBINTLVL1_bm (1<<3) /* Channel Low B Compare or Capture Interrupt Level bit 1 mask. */ -#define TC4_LCCBINTLVL1_bp 3 /* Channel Low B Compare or Capture Interrupt Level bit 1 position. */ - -#define TC4_LCCAINTLVL_gm 0x03 /* Channel Low A Compare or Capture Interrupt Level group mask. */ -#define TC4_LCCAINTLVL_gp 0 /* Channel Low A Compare or Capture Interrupt Level group position. */ -#define TC4_LCCAINTLVL0_bm (1<<0) /* Channel Low A Compare or Capture Interrupt Level bit 0 mask. */ -#define TC4_LCCAINTLVL0_bp 0 /* Channel Low A Compare or Capture Interrupt Level bit 0 position. */ -#define TC4_LCCAINTLVL1_bm (1<<1) /* Channel Low A Compare or Capture Interrupt Level bit 1 mask. */ -#define TC4_LCCAINTLVL1_bp 1 /* Channel Low A Compare or Capture Interrupt Level bit 1 position. */ - -/* TC4.CTRLGCLR bit masks and bit positions */ -#define TC4_STOP_bm 0x20 /* Timer/Counter Stop bit mask. */ -#define TC4_STOP_bp 5 /* Timer/Counter Stop bit position. */ - -#define TC4_CMD_gm 0x0C /* Command group mask. */ -#define TC4_CMD_gp 2 /* Command group position. */ -#define TC4_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC4_CMD0_bp 2 /* Command bit 0 position. */ -#define TC4_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC4_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC4_LUPD_bm 0x02 /* Lock Update bit mask. */ -#define TC4_LUPD_bp 1 /* Lock Update bit position. */ - -#define TC4_DIR_bm 0x01 /* Counter Direction bit mask. */ -#define TC4_DIR_bp 0 /* Counter Direction bit position. */ - -/* TC4.CTRLGSET bit masks and bit positions */ -/* TC4_STOP Predefined. */ -/* TC4_STOP Predefined. */ - -/* TC4_CMD Predefined. */ -/* TC4_CMD Predefined. */ - -/* TC4_LUPD Predefined. */ -/* TC4_LUPD Predefined. */ - -/* TC4_DIR Predefined. */ -/* TC4_DIR Predefined. */ - -/* TC4.CTRLHCLR bit masks and bit positions */ -#define TC4_CCDBV_bm 0x10 /* Channel D Compare or Capture Buffer Valid bit mask. */ -#define TC4_CCDBV_bp 4 /* Channel D Compare or Capture Buffer Valid bit position. */ - -#define TC4_CCCBV_bm 0x08 /* Channel C Compare or Capture Buffer Valid bit mask. */ -#define TC4_CCCBV_bp 3 /* Channel C Compare or Capture Buffer Valid bit position. */ - -#define TC4_CCBBV_bm 0x04 /* Channel B Compare or Capture Buffer Valid bit mask. */ -#define TC4_CCBBV_bp 2 /* Channel B Compare or Capture Buffer Valid bit position. */ - -#define TC4_CCABV_bm 0x02 /* Channel A Compare or Capture Buffer Valid bit mask. */ -#define TC4_CCABV_bp 1 /* Channel A Compare or Capture Buffer Valid bit position. */ - -#define TC4_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -#define TC4_PERBV_bp 0 /* Period Buffer Valid bit position. */ - -#define TC4_LCCDBV_bm 0x10 /* Channel Low D Compare or Capture Buffer Valid bit mask. */ -#define TC4_LCCDBV_bp 4 /* Channel Low D Compare or Capture Buffer Valid bit position. */ - -#define TC4_LCCCBV_bm 0x08 /* Channel Low C Compare or Capture Buffer Valid bit mask. */ -#define TC4_LCCCBV_bp 3 /* Channel Low C Compare or Capture Buffer Valid bit position. */ - -#define TC4_LCCBBV_bm 0x04 /* Channel Low B Compare or Capture Buffer Valid bit mask. */ -#define TC4_LCCBBV_bp 2 /* Channel Low B Compare or Capture Buffer Valid bit position. */ - -#define TC4_LCCABV_bm 0x02 /* Channel Low A Compare or Capture Buffer Valid bit mask. */ -#define TC4_LCCABV_bp 1 /* Channel Low A Compare or Capture Buffer Valid bit position. */ - -#define TC4_LPERBV_bm 0x01 /* Period Low Buffer Valid bit mask. */ -#define TC4_LPERBV_bp 0 /* Period Low Buffer Valid bit position. */ - -/* TC4.CTRLHSET bit masks and bit positions */ -/* TC4_CCDBV Predefined. */ -/* TC4_CCDBV Predefined. */ - -/* TC4_CCCBV Predefined. */ -/* TC4_CCCBV Predefined. */ - -/* TC4_CCBBV Predefined. */ -/* TC4_CCBBV Predefined. */ - -/* TC4_CCABV Predefined. */ -/* TC4_CCABV Predefined. */ - -/* TC4_PERBV Predefined. */ -/* TC4_PERBV Predefined. */ - -/* TC4_LCCDBV Predefined. */ -/* TC4_LCCDBV Predefined. */ - -/* TC4_LCCCBV Predefined. */ -/* TC4_LCCCBV Predefined. */ - -/* TC4_LCCBBV Predefined. */ -/* TC4_LCCBBV Predefined. */ - -/* TC4_LCCABV Predefined. */ -/* TC4_LCCABV Predefined. */ - -/* TC4_LPERBV Predefined. */ -/* TC4_LPERBV Predefined. */ - -/* TC4.INTFLAGS bit masks and bit positions */ -#define TC4_CCDIF_bm 0x80 /* Channel D Compare or Capture Interrupt Flag bit mask. */ -#define TC4_CCDIF_bp 7 /* Channel D Compare or Capture Interrupt Flag bit position. */ - -#define TC4_CCCIF_bm 0x40 /* Channel C Compare or Capture Interrupt Flag bit mask. */ -#define TC4_CCCIF_bp 6 /* Channel C Compare or Capture Interrupt Flag bit position. */ - -#define TC4_CCBIF_bm 0x20 /* Channel B Compare or Capture Interrupt Flag bit mask. */ -#define TC4_CCBIF_bp 5 /* Channel B Compare or Capture Interrupt Flag bit position. */ - -#define TC4_CCAIF_bm 0x10 /* Channel A Compare or Capture Interrupt Flag bit mask. */ -#define TC4_CCAIF_bp 4 /* Channel A Compare or Capture Interrupt Flag bit position. */ - -#define TC4_TRGIF_bm 0x04 /* Trigger Restart Interrupt Flag bit mask. */ -#define TC4_TRGIF_bp 2 /* Trigger Restart Interrupt Flag bit position. */ - -#define TC4_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -#define TC4_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ - -#define TC4_OVFIF_bm 0x01 /* Overflow/Underflow Interrupt Flag bit mask. */ -#define TC4_OVFIF_bp 0 /* Overflow/Underflow Interrupt Flag bit position. */ - -#define TC4_LCCDIF_bm 0x80 /* Channel Low D Compare or Capture Interrupt Flag bit mask. */ -#define TC4_LCCDIF_bp 7 /* Channel Low D Compare or Capture Interrupt Flag bit position. */ - -#define TC4_LCCCIF_bm 0x40 /* Channel Low C Compare or Capture Interrupt Flag bit mask. */ -#define TC4_LCCCIF_bp 6 /* Channel Low C Compare or Capture Interrupt Flag bit position. */ - -#define TC4_LCCBIF_bm 0x20 /* Channel Low B Compare or Capture Interrupt Flag bit mask. */ -#define TC4_LCCBIF_bp 5 /* Channel Low B Compare or Capture Interrupt Flag bit position. */ - -#define TC4_LCCAIF_bm 0x10 /* Channel Low A Compare or Capture Interrupt Flag bit mask. */ -#define TC4_LCCAIF_bp 4 /* Channel Low A Compare or Capture Interrupt Flag bit position. */ - -/* TC5.CTRLA bit masks and bit positions */ -#define TC5_SYNCHEN_bm 0x40 /* Synchronization Enabled bit mask. */ -#define TC5_SYNCHEN_bp 6 /* Synchronization Enabled bit position. */ - -#define TC5_EVSTART_bm 0x20 /* Start on Next Event bit mask. */ -#define TC5_EVSTART_bp 5 /* Start on Next Event bit position. */ - -#define TC5_UPSTOP_bm 0x10 /* Stop on Next Update bit mask. */ -#define TC5_UPSTOP_bp 4 /* Stop on Next Update bit position. */ - -#define TC5_CLKSEL_gm 0x0F /* Clock Select group mask. */ -#define TC5_CLKSEL_gp 0 /* Clock Select group position. */ -#define TC5_CLKSEL0_bm (1<<0) /* Clock Select bit 0 mask. */ -#define TC5_CLKSEL0_bp 0 /* Clock Select bit 0 position. */ -#define TC5_CLKSEL1_bm (1<<1) /* Clock Select bit 1 mask. */ -#define TC5_CLKSEL1_bp 1 /* Clock Select bit 1 position. */ -#define TC5_CLKSEL2_bm (1<<2) /* Clock Select bit 2 mask. */ -#define TC5_CLKSEL2_bp 2 /* Clock Select bit 2 position. */ -#define TC5_CLKSEL3_bm (1<<3) /* Clock Select bit 3 mask. */ -#define TC5_CLKSEL3_bp 3 /* Clock Select bit 3 position. */ - -/* TC5.CTRLB bit masks and bit positions */ -#define TC5_BYTEM_gm 0xC0 /* Byte Mode group mask. */ -#define TC5_BYTEM_gp 6 /* Byte Mode group position. */ -#define TC5_BYTEM0_bm (1<<6) /* Byte Mode bit 0 mask. */ -#define TC5_BYTEM0_bp 6 /* Byte Mode bit 0 position. */ -#define TC5_BYTEM1_bm (1<<7) /* Byte Mode bit 1 mask. */ -#define TC5_BYTEM1_bp 7 /* Byte Mode bit 1 position. */ - -#define TC5_CIRCEN_gm 0x30 /* Circular Buffer Enable group mask. */ -#define TC5_CIRCEN_gp 4 /* Circular Buffer Enable group position. */ -#define TC5_CIRCEN0_bm (1<<4) /* Circular Buffer Enable bit 0 mask. */ -#define TC5_CIRCEN0_bp 4 /* Circular Buffer Enable bit 0 position. */ -#define TC5_CIRCEN1_bm (1<<5) /* Circular Buffer Enable bit 1 mask. */ -#define TC5_CIRCEN1_bp 5 /* Circular Buffer Enable bit 1 position. */ - -#define TC5_WGMODE_gm 0x07 /* Waveform Generation Mode group mask. */ -#define TC5_WGMODE_gp 0 /* Waveform Generation Mode group position. */ -#define TC5_WGMODE0_bm (1<<0) /* Waveform Generation Mode bit 0 mask. */ -#define TC5_WGMODE0_bp 0 /* Waveform Generation Mode bit 0 position. */ -#define TC5_WGMODE1_bm (1<<1) /* Waveform Generation Mode bit 1 mask. */ -#define TC5_WGMODE1_bp 1 /* Waveform Generation Mode bit 1 position. */ -#define TC5_WGMODE2_bm (1<<2) /* Waveform Generation Mode bit 2 mask. */ -#define TC5_WGMODE2_bp 2 /* Waveform Generation Mode bit 2 position. */ - -/* TC5.CTRLC bit masks and bit positions */ -#define TC5_POLB_bm 0x20 /* Channel B Output Polarity bit mask. */ -#define TC5_POLB_bp 5 /* Channel B Output Polarity bit position. */ - -#define TC5_POLA_bm 0x10 /* Channel A Output Polarity bit mask. */ -#define TC5_POLA_bp 4 /* Channel A Output Polarity bit position. */ - -#define TC5_CMPB_bm 0x02 /* Channel B Compare Output Value bit mask. */ -#define TC5_CMPB_bp 1 /* Channel B Compare Output Value bit position. */ - -#define TC5_CMPA_bm 0x01 /* Channel A Compare Output Value bit mask. */ -#define TC5_CMPA_bp 0 /* Channel A Compare Output Value bit position. */ - -#define TC5_HCMPB_bm 0x20 /* High Channel B Compare Output Value bit mask. */ -#define TC5_HCMPB_bp 5 /* High Channel B Compare Output Value bit position. */ - -#define TC5_HCMPA_bm 0x10 /* High Channel A Compare Output Value bit mask. */ -#define TC5_HCMPA_bp 4 /* High Channel A Compare Output Value bit position. */ - -#define TC5_LCMPB_bm 0x02 /* Low Channel B Compare Output Value bit mask. */ -#define TC5_LCMPB_bp 1 /* Low Channel B Compare Output Value bit position. */ - -#define TC5_LCMPA_bm 0x01 /* Low Channel A Compare Output Value bit mask. */ -#define TC5_LCMPA_bp 0 /* Low Channel A Compare Output Value bit position. */ - -/* TC5.CTRLD bit masks and bit positions */ -#define TC5_EVACT_gm 0xE0 /* Event Action group mask. */ -#define TC5_EVACT_gp 5 /* Event Action group position. */ -#define TC5_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -#define TC5_EVACT0_bp 5 /* Event Action bit 0 position. */ -#define TC5_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -#define TC5_EVACT1_bp 6 /* Event Action bit 1 position. */ -#define TC5_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -#define TC5_EVACT2_bp 7 /* Event Action bit 2 position. */ - -#define TC5_EVDLY_bm 0x10 /* Event Delay bit mask. */ -#define TC5_EVDLY_bp 4 /* Event Delay bit position. */ - -#define TC5_EVSEL_gm 0x0F /* Event Source Select group mask. */ -#define TC5_EVSEL_gp 0 /* Event Source Select group position. */ -#define TC5_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -#define TC5_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -#define TC5_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -#define TC5_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -#define TC5_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -#define TC5_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -#define TC5_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -#define TC5_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - -/* TC5.CTRLE bit masks and bit positions */ -#define TC5_CCBMODE_gm 0x0C /* Channel B Compare or Capture Mode group mask. */ -#define TC5_CCBMODE_gp 2 /* Channel B Compare or Capture Mode group position. */ -#define TC5_CCBMODE0_bm (1<<2) /* Channel B Compare or Capture Mode bit 0 mask. */ -#define TC5_CCBMODE0_bp 2 /* Channel B Compare or Capture Mode bit 0 position. */ -#define TC5_CCBMODE1_bm (1<<3) /* Channel B Compare or Capture Mode bit 1 mask. */ -#define TC5_CCBMODE1_bp 3 /* Channel B Compare or Capture Mode bit 1 position. */ - -#define TC5_CCAMODE_gm 0x03 /* Channel A Compare or Capture Mode group mask. */ -#define TC5_CCAMODE_gp 0 /* Channel A Compare or Capture Mode group position. */ -#define TC5_CCAMODE0_bm (1<<0) /* Channel A Compare or Capture Mode bit 0 mask. */ -#define TC5_CCAMODE0_bp 0 /* Channel A Compare or Capture Mode bit 0 position. */ -#define TC5_CCAMODE1_bm (1<<1) /* Channel A Compare or Capture Mode bit 1 mask. */ -#define TC5_CCAMODE1_bp 1 /* Channel A Compare or Capture Mode bit 1 position. */ - -#define TC5_LCCBMODE_gm 0x0C /* Channel Low B Compare or Capture Mode group mask. */ -#define TC5_LCCBMODE_gp 2 /* Channel Low B Compare or Capture Mode group position. */ -#define TC5_LCCBMODE0_bm (1<<2) /* Channel Low B Compare or Capture Mode bit 0 mask. */ -#define TC5_LCCBMODE0_bp 2 /* Channel Low B Compare or Capture Mode bit 0 position. */ -#define TC5_LCCBMODE1_bm (1<<3) /* Channel Low B Compare or Capture Mode bit 1 mask. */ -#define TC5_LCCBMODE1_bp 3 /* Channel Low B Compare or Capture Mode bit 1 position. */ - -#define TC5_LCCAMODE_gm 0x03 /* Channel Low A Compare or Capture Mode group mask. */ -#define TC5_LCCAMODE_gp 0 /* Channel Low A Compare or Capture Mode group position. */ -#define TC5_LCCAMODE0_bm (1<<0) /* Channel Low A Compare or Capture Mode bit 0 mask. */ -#define TC5_LCCAMODE0_bp 0 /* Channel Low A Compare or Capture Mode bit 0 position. */ -#define TC5_LCCAMODE1_bm (1<<1) /* Channel Low A Compare or Capture Mode bit 1 mask. */ -#define TC5_LCCAMODE1_bp 1 /* Channel Low A Compare or Capture Mode bit 1 position. */ - -/* TC5.CTRLF bit masks and bit positions */ -#define TC5_HCCBMODE_gm 0x0C /* Channel High B Compare or Capture Mode group mask. */ -#define TC5_HCCBMODE_gp 2 /* Channel High B Compare or Capture Mode group position. */ -#define TC5_HCCBMODE0_bm (1<<2) /* Channel High B Compare or Capture Mode bit 0 mask. */ -#define TC5_HCCBMODE0_bp 2 /* Channel High B Compare or Capture Mode bit 0 position. */ -#define TC5_HCCBMODE1_bm (1<<3) /* Channel High B Compare or Capture Mode bit 1 mask. */ -#define TC5_HCCBMODE1_bp 3 /* Channel High B Compare or Capture Mode bit 1 position. */ - -#define TC5_HCCAMODE_gm 0x03 /* Channel High A Compare or Capture Mode group mask. */ -#define TC5_HCCAMODE_gp 0 /* Channel High A Compare or Capture Mode group position. */ -#define TC5_HCCAMODE0_bm (1<<0) /* Channel High A Compare or Capture Mode bit 0 mask. */ -#define TC5_HCCAMODE0_bp 0 /* Channel High A Compare or Capture Mode bit 0 position. */ -#define TC5_HCCAMODE1_bm (1<<1) /* Channel High A Compare or Capture Mode bit 1 mask. */ -#define TC5_HCCAMODE1_bp 1 /* Channel High A Compare or Capture Mode bit 1 position. */ - -/* TC5.INTCTRLA bit masks and bit positions */ -#define TC5_TRGINTLVL_gm 0x30 /* Timer Trigger Restart Interrupt Level group mask. */ -#define TC5_TRGINTLVL_gp 4 /* Timer Trigger Restart Interrupt Level group position. */ -#define TC5_TRGINTLVL0_bm (1<<4) /* Timer Trigger Restart Interrupt Level bit 0 mask. */ -#define TC5_TRGINTLVL0_bp 4 /* Timer Trigger Restart Interrupt Level bit 0 position. */ -#define TC5_TRGINTLVL1_bm (1<<5) /* Timer Trigger Restart Interrupt Level bit 1 mask. */ -#define TC5_TRGINTLVL1_bp 5 /* Timer Trigger Restart Interrupt Level bit 1 position. */ - -#define TC5_ERRINTLVL_gm 0x0C /* Timer Error Interrupt Level group mask. */ -#define TC5_ERRINTLVL_gp 2 /* Timer Error Interrupt Level group position. */ -#define TC5_ERRINTLVL0_bm (1<<2) /* Timer Error Interrupt Level bit 0 mask. */ -#define TC5_ERRINTLVL0_bp 2 /* Timer Error Interrupt Level bit 0 position. */ -#define TC5_ERRINTLVL1_bm (1<<3) /* Timer Error Interrupt Level bit 1 mask. */ -#define TC5_ERRINTLVL1_bp 3 /* Timer Error Interrupt Level bit 1 position. */ - -#define TC5_OVFINTLVL_gm 0x03 /* Timer Overflow/Underflow Interrupt Level group mask. */ -#define TC5_OVFINTLVL_gp 0 /* Timer Overflow/Underflow Interrupt Level group position. */ -#define TC5_OVFINTLVL0_bm (1<<0) /* Timer Overflow/Underflow Interrupt Level bit 0 mask. */ -#define TC5_OVFINTLVL0_bp 0 /* Timer Overflow/Underflow Interrupt Level bit 0 position. */ -#define TC5_OVFINTLVL1_bm (1<<1) /* Timer Overflow/Underflow Interrupt Level bit 1 mask. */ -#define TC5_OVFINTLVL1_bp 1 /* Timer Overflow/Underflow Interrupt Level bit 1 position. */ - -/* TC5.INTCTRLB bit masks and bit positions */ -#define TC5_CCBINTLVL_gm 0x0C /* Channel B Compare or Capture Interrupt Level group mask. */ -#define TC5_CCBINTLVL_gp 2 /* Channel B Compare or Capture Interrupt Level group position. */ -#define TC5_CCBINTLVL0_bm (1<<2) /* Channel B Compare or Capture Interrupt Level bit 0 mask. */ -#define TC5_CCBINTLVL0_bp 2 /* Channel B Compare or Capture Interrupt Level bit 0 position. */ -#define TC5_CCBINTLVL1_bm (1<<3) /* Channel B Compare or Capture Interrupt Level bit 1 mask. */ -#define TC5_CCBINTLVL1_bp 3 /* Channel B Compare or Capture Interrupt Level bit 1 position. */ - -#define TC5_CCAINTLVL_gm 0x03 /* Channel A Compare or Capture Interrupt Level group mask. */ -#define TC5_CCAINTLVL_gp 0 /* Channel A Compare or Capture Interrupt Level group position. */ -#define TC5_CCAINTLVL0_bm (1<<0) /* Channel A Compare or Capture Interrupt Level bit 0 mask. */ -#define TC5_CCAINTLVL0_bp 0 /* Channel A Compare or Capture Interrupt Level bit 0 position. */ -#define TC5_CCAINTLVL1_bm (1<<1) /* Channel A Compare or Capture Interrupt Level bit 1 mask. */ -#define TC5_CCAINTLVL1_bp 1 /* Channel A Compare or Capture Interrupt Level bit 1 position. */ - -#define TC5_LCCBINTLVL_gm 0x0C /* Channel Low B Compare or Capture Interrupt Level group mask. */ -#define TC5_LCCBINTLVL_gp 2 /* Channel Low B Compare or Capture Interrupt Level group position. */ -#define TC5_LCCBINTLVL0_bm (1<<2) /* Channel Low B Compare or Capture Interrupt Level bit 0 mask. */ -#define TC5_LCCBINTLVL0_bp 2 /* Channel Low B Compare or Capture Interrupt Level bit 0 position. */ -#define TC5_LCCBINTLVL1_bm (1<<3) /* Channel Low B Compare or Capture Interrupt Level bit 1 mask. */ -#define TC5_LCCBINTLVL1_bp 3 /* Channel Low B Compare or Capture Interrupt Level bit 1 position. */ - -#define TC5_LCCAINTLVL_gm 0x03 /* Channel Low A Compare or Capture Interrupt Level group mask. */ -#define TC5_LCCAINTLVL_gp 0 /* Channel Low A Compare or Capture Interrupt Level group position. */ -#define TC5_LCCAINTLVL0_bm (1<<0) /* Channel Low A Compare or Capture Interrupt Level bit 0 mask. */ -#define TC5_LCCAINTLVL0_bp 0 /* Channel Low A Compare or Capture Interrupt Level bit 0 position. */ -#define TC5_LCCAINTLVL1_bm (1<<1) /* Channel Low A Compare or Capture Interrupt Level bit 1 mask. */ -#define TC5_LCCAINTLVL1_bp 1 /* Channel Low A Compare or Capture Interrupt Level bit 1 position. */ - -/* TC5.CTRLGCLR bit masks and bit positions */ -#define TC5_STOP_bm 0x20 /* Timer/Counter Stop bit mask. */ -#define TC5_STOP_bp 5 /* Timer/Counter Stop bit position. */ - -#define TC5_CMD_gm 0x0C /* Command group mask. */ -#define TC5_CMD_gp 2 /* Command group position. */ -#define TC5_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC5_CMD0_bp 2 /* Command bit 0 position. */ -#define TC5_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC5_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC5_LUPD_bm 0x02 /* Lock Update bit mask. */ -#define TC5_LUPD_bp 1 /* Lock Update bit position. */ - -#define TC5_DIR_bm 0x01 /* Counter Direction bit mask. */ -#define TC5_DIR_bp 0 /* Counter Direction bit position. */ - -/* TC5.CTRLGSET bit masks and bit positions */ -/* TC5_STOP Predefined. */ -/* TC5_STOP Predefined. */ - -/* TC5_CMD Predefined. */ -/* TC5_CMD Predefined. */ - -/* TC5_LUPD Predefined. */ -/* TC5_LUPD Predefined. */ - -/* TC5_DIR Predefined. */ -/* TC5_DIR Predefined. */ - -/* TC5.CTRLHCLR bit masks and bit positions */ -#define TC5_CCBBV_bm 0x04 /* Channel B Compare or Capture Buffer Valid bit mask. */ -#define TC5_CCBBV_bp 2 /* Channel B Compare or Capture Buffer Valid bit position. */ - -#define TC5_CCABV_bm 0x02 /* Channel A Compare or Capture Buffer Valid bit mask. */ -#define TC5_CCABV_bp 1 /* Channel A Compare or Capture Buffer Valid bit position. */ - -#define TC5_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -#define TC5_PERBV_bp 0 /* Period Buffer Valid bit position. */ - -#define TC5_LCCBBV_bm 0x04 /* Channel Low B Compare or Capture Buffer Valid bit mask. */ -#define TC5_LCCBBV_bp 2 /* Channel Low B Compare or Capture Buffer Valid bit position. */ - -#define TC5_LCCABV_bm 0x02 /* Channel Low A Compare or Capture Buffer Valid bit mask. */ -#define TC5_LCCABV_bp 1 /* Channel Low A Compare or Capture Buffer Valid bit position. */ - -#define TC5_LPERBV_bm 0x01 /* Period Low Buffer Valid bit mask. */ -#define TC5_LPERBV_bp 0 /* Period Low Buffer Valid bit position. */ - -/* TC5.CTRLHSET bit masks and bit positions */ -/* TC5_CCBBV Predefined. */ -/* TC5_CCBBV Predefined. */ - -/* TC5_CCABV Predefined. */ -/* TC5_CCABV Predefined. */ - -/* TC5_PERBV Predefined. */ -/* TC5_PERBV Predefined. */ - -/* TC5_LCCBBV Predefined. */ -/* TC5_LCCBBV Predefined. */ - -/* TC5_LCCABV Predefined. */ -/* TC5_LCCABV Predefined. */ - -/* TC5_LPERBV Predefined. */ -/* TC5_LPERBV Predefined. */ - -/* TC5.INTFLAGS bit masks and bit positions */ -#define TC5_CCBIF_bm 0x20 /* Channel B Compare or Capture Interrupt Flag bit mask. */ -#define TC5_CCBIF_bp 5 /* Channel B Compare or Capture Interrupt Flag bit position. */ - -#define TC5_CCAIF_bm 0x10 /* Channel A Compare or Capture Interrupt Flag bit mask. */ -#define TC5_CCAIF_bp 4 /* Channel A Compare or Capture Interrupt Flag bit position. */ - -#define TC5_TRGIF_bm 0x04 /* Trigger Restart Interrupt Flag bit mask. */ -#define TC5_TRGIF_bp 2 /* Trigger Restart Interrupt Flag bit position. */ - -#define TC5_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -#define TC5_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ - -#define TC5_OVFIF_bm 0x01 /* Overflow/Underflow Interrupt Flag bit mask. */ -#define TC5_OVFIF_bp 0 /* Overflow/Underflow Interrupt Flag bit position. */ - -#define TC5_LCCBIF_bm 0x20 /* Channel Low B Compare or Capture Interrupt Flag bit mask. */ -#define TC5_LCCBIF_bp 5 /* Channel Low B Compare or Capture Interrupt Flag bit position. */ - -#define TC5_LCCAIF_bm 0x10 /* Channel Low A Compare or Capture Interrupt Flag bit mask. */ -#define TC5_LCCAIF_bp 4 /* Channel Low A Compare or Capture Interrupt Flag bit position. */ - -/* FAULT - Fault Extension */ -/* FAULT.CTRLA bit masks and bit positions */ -#define FAULT_RAMP_gm 0xC0 /* Ramp Mode Selection group mask. */ -#define FAULT_RAMP_gp 6 /* Ramp Mode Selection group position. */ -#define FAULT_RAMP0_bm (1<<6) /* Ramp Mode Selection bit 0 mask. */ -#define FAULT_RAMP0_bp 6 /* Ramp Mode Selection bit 0 position. */ -#define FAULT_RAMP1_bm (1<<7) /* Ramp Mode Selection bit 1 mask. */ -#define FAULT_RAMP1_bp 7 /* Ramp Mode Selection bit 1 position. */ - -#define FAULT_FDDBD_bm 0x20 /* Fault on Debug Break Detection bit mask. */ -#define FAULT_FDDBD_bp 5 /* Fault on Debug Break Detection bit position. */ - -#define FAULT_PORTCTRL_bm 0x10 /* Port Control Mode bit mask. */ -#define FAULT_PORTCTRL_bp 4 /* Port Control Mode bit position. */ - -#define FAULT_FUSE_bm 0x08 /* Fuse State bit mask. */ -#define FAULT_FUSE_bp 3 /* Fuse State bit position. */ - -#define FAULT_FILTERE_bm 0x04 /* Fault E Digital Filter Selection bit mask. */ -#define FAULT_FILTERE_bp 2 /* Fault E Digital Filter Selection bit position. */ - -#define FAULT_SRCE_gm 0x03 /* Fault E Input selection group mask. */ -#define FAULT_SRCE_gp 0 /* Fault E Input selection group position. */ -#define FAULT_SRCE0_bm (1<<0) /* Fault E Input selection bit 0 mask. */ -#define FAULT_SRCE0_bp 0 /* Fault E Input selection bit 0 position. */ -#define FAULT_SRCE1_bm (1<<1) /* Fault E Input selection bit 1 mask. */ -#define FAULT_SRCE1_bp 1 /* Fault E Input selection bit 1 position. */ - -/* FAULT.CTRLB bit masks and bit positions */ -#define FAULT_SOFTA_bm 0x80 /* Fault A Software Mode bit mask. */ -#define FAULT_SOFTA_bp 7 /* Fault A Software Mode bit position. */ - -#define FAULT_HALTA_gm 0x60 /* Fault A Halt Action group mask. */ -#define FAULT_HALTA_gp 5 /* Fault A Halt Action group position. */ -#define FAULT_HALTA0_bm (1<<5) /* Fault A Halt Action bit 0 mask. */ -#define FAULT_HALTA0_bp 5 /* Fault A Halt Action bit 0 position. */ -#define FAULT_HALTA1_bm (1<<6) /* Fault A Halt Action bit 1 mask. */ -#define FAULT_HALTA1_bp 6 /* Fault A Halt Action bit 1 position. */ - -#define FAULT_RESTARTA_bm 0x10 /* Fault A Restart Action bit mask. */ -#define FAULT_RESTARTA_bp 4 /* Fault A Restart Action bit position. */ - -#define FAULT_KEEPA_bm 0x08 /* Fault A Keep Action bit mask. */ -#define FAULT_KEEPA_bp 3 /* Fault A Keep Action bit position. */ - -#define FAULT_SRCA_gm 0x03 /* Fault A Source Selection group mask. */ -#define FAULT_SRCA_gp 0 /* Fault A Source Selection group position. */ -#define FAULT_SRCA0_bm (1<<0) /* Fault A Source Selection bit 0 mask. */ -#define FAULT_SRCA0_bp 0 /* Fault A Source Selection bit 0 position. */ -#define FAULT_SRCA1_bm (1<<1) /* Fault A Source Selection bit 1 mask. */ -#define FAULT_SRCA1_bp 1 /* Fault A Source Selection bit 1 position. */ - -/* FAULT.CTRLC bit masks and bit positions */ -#define FAULT_CAPTA_bm 0x20 /* Fault A Capture bit mask. */ -#define FAULT_CAPTA_bp 5 /* Fault A Capture bit position. */ - -#define FAULT_FILTERA_bm 0x04 /* Fault A Digital Filter Selection bit mask. */ -#define FAULT_FILTERA_bp 2 /* Fault A Digital Filter Selection bit position. */ - -#define FAULT_BLANKA_bm 0x02 /* Fault A Blanking bit mask. */ -#define FAULT_BLANKA_bp 1 /* Fault A Blanking bit position. */ - -#define FAULT_QUALA_bm 0x01 /* Fault A Qualification bit mask. */ -#define FAULT_QUALA_bp 0 /* Fault A Qualification bit position. */ - -/* FAULT.CTRLD bit masks and bit positions */ -#define FAULT_SOFTB_bm 0x80 /* Fault B Software Mode bit mask. */ -#define FAULT_SOFTB_bp 7 /* Fault B Software Mode bit position. */ - -#define FAULT_HALTB_gm 0x60 /* Fault B Halt Action group mask. */ -#define FAULT_HALTB_gp 5 /* Fault B Halt Action group position. */ -#define FAULT_HALTB0_bm (1<<5) /* Fault B Halt Action bit 0 mask. */ -#define FAULT_HALTB0_bp 5 /* Fault B Halt Action bit 0 position. */ -#define FAULT_HALTB1_bm (1<<6) /* Fault B Halt Action bit 1 mask. */ -#define FAULT_HALTB1_bp 6 /* Fault B Halt Action bit 1 position. */ - -#define FAULT_RESTARTB_bm 0x10 /* Fault B Restart Action bit mask. */ -#define FAULT_RESTARTB_bp 4 /* Fault B Restart Action bit position. */ - -#define FAULT_KEEPB_bm 0x08 /* Fault B Keep Action bit mask. */ -#define FAULT_KEEPB_bp 3 /* Fault B Keep Action bit position. */ - -#define FAULT_SRCB_gm 0x03 /* Fault B Source Selection group mask. */ -#define FAULT_SRCB_gp 0 /* Fault B Source Selection group position. */ -#define FAULT_SRCB0_bm (1<<0) /* Fault B Source Selection bit 0 mask. */ -#define FAULT_SRCB0_bp 0 /* Fault B Source Selection bit 0 position. */ -#define FAULT_SRCB1_bm (1<<1) /* Fault B Source Selection bit 1 mask. */ -#define FAULT_SRCB1_bp 1 /* Fault B Source Selection bit 1 position. */ - -/* FAULT.CTRLE bit masks and bit positions */ -#define FAULT_CAPTB_bm 0x20 /* Fault B Capture bit mask. */ -#define FAULT_CAPTB_bp 5 /* Fault B Capture bit position. */ - -#define FAULT_FILTERB_bm 0x04 /* Fault B Digital Filter Selection bit mask. */ -#define FAULT_FILTERB_bp 2 /* Fault B Digital Filter Selection bit position. */ - -#define FAULT_BLANKB_bm 0x02 /* Fault B Blanking bit mask. */ -#define FAULT_BLANKB_bp 1 /* Fault B Blanking bit position. */ - -#define FAULT_QUALB_bm 0x01 /* Fault B Qualification bit mask. */ -#define FAULT_QUALB_bp 0 /* Fault B Qualification bit position. */ - -/* FAULT.STATUS bit masks and bit positions */ -#define FAULT_STATEB_bm 0x80 /* Fault B State bit mask. */ -#define FAULT_STATEB_bp 7 /* Fault B State bit position. */ - -#define FAULT_STATEA_bm 0x40 /* Fault A State bit mask. */ -#define FAULT_STATEA_bp 6 /* Fault A State bit position. */ - -#define FAULT_STATEE_bm 0x20 /* Fault E State bit mask. */ -#define FAULT_STATEE_bp 5 /* Fault E State bit position. */ - -#define FAULT_IDX_bm 0x08 /* Channel Index Flag bit mask. */ -#define FAULT_IDX_bp 3 /* Channel Index Flag bit position. */ - -#define FAULT_FAULTBIN_bm 0x04 /* Fault B Flag bit mask. */ -#define FAULT_FAULTBIN_bp 2 /* Fault B Flag bit position. */ - -#define FAULT_FAULTAIN_bm 0x02 /* Fault A Flag bit mask. */ -#define FAULT_FAULTAIN_bp 1 /* Fault A Flag bit position. */ - -#define FAULT_FAULTEIN_bm 0x01 /* Fault E Flag bit mask. */ -#define FAULT_FAULTEIN_bp 0 /* Fault E Flag bit position. */ - -/* FAULT.CTRLGCLR bit masks and bit positions */ -#define FAULT_HALTBCLR_bm 0x80 /* State B Clear bit mask. */ -#define FAULT_HALTBCLR_bp 7 /* State B Clear bit position. */ - -#define FAULT_HALTACLR_bm 0x40 /* State A Clear bit mask. */ -#define FAULT_HALTACLR_bp 6 /* State A Clear bit position. */ - -#define FAULT_STATEECLR_bm 0x20 /* State E Clear bit mask. */ -#define FAULT_STATEECLR_bp 5 /* State E Clear bit position. */ - -#define FAULT_FAULTB_bm 0x04 /* Fault B Flag bit mask. */ -#define FAULT_FAULTB_bp 2 /* Fault B Flag bit position. */ - -#define FAULT_FAULTA_bm 0x02 /* Fault A Flag bit mask. */ -#define FAULT_FAULTA_bp 1 /* Fault A Flag bit position. */ - -#define FAULT_FAULTE_bm 0x01 /* Fault E Flag bit mask. */ -#define FAULT_FAULTE_bp 0 /* Fault E Flag bit position. */ - -/* FAULT.CTRLGSET bit masks and bit positions */ -#define FAULT_FAULTBSW_bm 0x80 /* Software Fault B bit mask. */ -#define FAULT_FAULTBSW_bp 7 /* Software Fault B bit position. */ - -#define FAULT_FAULTASW_bm 0x40 /* Software Fault A bit mask. */ -#define FAULT_FAULTASW_bp 6 /* Software Fault A bit position. */ - -#define FAULT_FAULTESW_bm 0x20 /* Software Fault E bit mask. */ -#define FAULT_FAULTESW_bp 5 /* Software Fault E bit position. */ - -#define FAULT_IDXCMD_gm 0x18 /* Channel index Command group mask. */ -#define FAULT_IDXCMD_gp 3 /* Channel index Command group position. */ -#define FAULT_IDXCMD0_bm (1<<3) /* Channel index Command bit 0 mask. */ -#define FAULT_IDXCMD0_bp 3 /* Channel index Command bit 0 position. */ -#define FAULT_IDXCMD1_bm (1<<4) /* Channel index Command bit 1 mask. */ -#define FAULT_IDXCMD1_bp 4 /* Channel index Command bit 1 position. */ - -/* WEX - Waveform Extension */ -/* WEX.CTRL bit masks and bit positions */ -#define WEX_UPSEL_bm 0x80 /* Update Source Selection bit mask. */ -#define WEX_UPSEL_bp 7 /* Update Source Selection bit position. */ - -#define WEX_OTMX_gm 0x70 /* Output Matrix group mask. */ -#define WEX_OTMX_gp 4 /* Output Matrix group position. */ -#define WEX_OTMX0_bm (1<<4) /* Output Matrix bit 0 mask. */ -#define WEX_OTMX0_bp 4 /* Output Matrix bit 0 position. */ -#define WEX_OTMX1_bm (1<<5) /* Output Matrix bit 1 mask. */ -#define WEX_OTMX1_bp 5 /* Output Matrix bit 1 position. */ -#define WEX_OTMX2_bm (1<<6) /* Output Matrix bit 2 mask. */ -#define WEX_OTMX2_bp 6 /* Output Matrix bit 2 position. */ - -#define WEX_DTI3EN_bm 0x08 /* Dead-Time Insertion Generator 3 Enable bit mask. */ -#define WEX_DTI3EN_bp 3 /* Dead-Time Insertion Generator 3 Enable bit position. */ - -#define WEX_DTI2EN_bm 0x04 /* Dead-Time Insertion Generator 2 Enable bit mask. */ -#define WEX_DTI2EN_bp 2 /* Dead-Time Insertion Generator 2 Enable bit position. */ - -#define WEX_DTI1EN_bm 0x02 /* Dead-Time Insertion Generator 1 Enable bit mask. */ -#define WEX_DTI1EN_bp 1 /* Dead-Time Insertion Generator 1 Enable bit position. */ - -#define WEX_DTI0EN_bm 0x01 /* Dead-Time Insertion Generator 0 Enable bit mask. */ -#define WEX_DTI0EN_bp 0 /* Dead-Time Insertion Generator 0 Enable bit position. */ - -/* WEX.STATUSCLR bit masks and bit positions */ -#define WEX_SWAPBUF_bm 0x04 /* Swap Buffer Valid bit mask. */ -#define WEX_SWAPBUF_bp 2 /* Swap Buffer Valid bit position. */ - -#define WEX_PGVBUFV_bm 0x02 /* Pattern Generator Value Buffer Valid bit mask. */ -#define WEX_PGVBUFV_bp 1 /* Pattern Generator Value Buffer Valid bit position. */ - -#define WEX_PGOBUFV_bm 0x01 /* Pattern Generator Overwrite Buffer Valid bit mask. */ -#define WEX_PGOBUFV_bp 0 /* Pattern Generator Overwrite Buffer Valid bit position. */ - -/* WEX.STATUSSET bit masks and bit positions */ -/* WEX_SWAPBUF Predefined. */ -/* WEX_SWAPBUF Predefined. */ - -/* WEX_PGVBUFV Predefined. */ -/* WEX_PGVBUFV Predefined. */ - -/* WEX_PGOBUFV Predefined. */ -/* WEX_PGOBUFV Predefined. */ - -/* WEX.SWAP bit masks and bit positions */ -#define WEX_SWAP3_bm 0x08 /* Swap DTI output pair 3 bit mask. */ -#define WEX_SWAP3_bp 3 /* Swap DTI output pair 3 bit position. */ - -#define WEX_SWAP2_bm 0x04 /* Swap DTI output pair 2 bit mask. */ -#define WEX_SWAP2_bp 2 /* Swap DTI output pair 2 bit position. */ - -#define WEX_SWAP1_bm 0x02 /* Swap DTI output pair 1 bit mask. */ -#define WEX_SWAP1_bp 1 /* Swap DTI output pair 1 bit position. */ - -#define WEX_SWAP0_bm 0x01 /* Swap DTI output pair 0 bit mask. */ -#define WEX_SWAP0_bp 0 /* Swap DTI output pair 0 bit position. */ - -/* WEX.SWAPBUF bit masks and bit positions */ -#define WEX_SWAP3BUF_bm 0x08 /* Swap DTI output pair 3 bit mask. */ -#define WEX_SWAP3BUF_bp 3 /* Swap DTI output pair 3 bit position. */ - -#define WEX_SWAP2BUF_bm 0x04 /* Swap DTI output pair 2 bit mask. */ -#define WEX_SWAP2BUF_bp 2 /* Swap DTI output pair 2 bit position. */ - -#define WEX_SWAP1BUF_bm 0x02 /* Swap DTI output pair 1 bit mask. */ -#define WEX_SWAP1BUF_bp 1 /* Swap DTI output pair 1 bit position. */ - -#define WEX_SWAP0BUF_bm 0x01 /* Swap DTI output pair 0 bit mask. */ -#define WEX_SWAP0BUF_bp 0 /* Swap DTI output pair 0 bit position. */ - -/* HIRES - High-Resolution Extension */ -/* HIRES.CTRLA bit masks and bit positions */ -#define HIRES_HRPLUS_gm 0x0C /* High Resolution Plus group mask. */ -#define HIRES_HRPLUS_gp 2 /* High Resolution Plus group position. */ -#define HIRES_HRPLUS0_bm (1<<2) /* High Resolution Plus bit 0 mask. */ -#define HIRES_HRPLUS0_bp 2 /* High Resolution Plus bit 0 position. */ -#define HIRES_HRPLUS1_bm (1<<3) /* High Resolution Plus bit 1 mask. */ -#define HIRES_HRPLUS1_bp 3 /* High Resolution Plus bit 1 position. */ - -#define HIRES_HREN_gm 0x03 /* High Resolution Mode group mask. */ -#define HIRES_HREN_gp 0 /* High Resolution Mode group position. */ -#define HIRES_HREN0_bm (1<<0) /* High Resolution Mode bit 0 mask. */ -#define HIRES_HREN0_bp 0 /* High Resolution Mode bit 0 position. */ -#define HIRES_HREN1_bm (1<<1) /* High Resolution Mode bit 1 mask. */ -#define HIRES_HREN1_bp 1 /* High Resolution Mode bit 1 position. */ - -/* USART - Universal Asynchronous Receiver-Transmitter */ -/* USART.STATUS bit masks and bit positions */ -#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ -#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ - -#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ -#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ - -#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ -#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ - -#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ -#define USART_FERR_bp 4 /* Frame Error bit position. */ - -#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ -#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ - -#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ -#define USART_PERR_bp 2 /* Parity Error bit position. */ - -#define USART_RXSIF_bm 0x02 /* Receive Start Bit Interrupt Flag bit mask. */ -#define USART_RXSIF_bp 1 /* Receive Start Bit Interrupt Flag bit position. */ - -#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ -#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ - -#define USART_DRIF_bm 0x01 /* Data Reception Flag bit mask. */ -#define USART_DRIF_bp 0 /* Data Reception Flag bit position. */ - -/* USART.CTRLA bit masks and bit positions */ -#define USART_RXSIE_bm 0x80 /* Receive Start Interrupt Enable bit mask. */ -#define USART_RXSIE_bp 7 /* Receive Start Interrupt Enable bit position. */ - -#define USART_DRIE_bm 0x40 /* Data Reception Interrupt Enable bit mask. */ -#define USART_DRIE_bp 6 /* Data Reception Interrupt Enable bit position. */ - -#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ -#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ -#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ -#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ -#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ -#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ - -#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ -#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ -#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ -#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ -#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ -#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ - -#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ -#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ -#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ -#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ -#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ -#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ - -/* USART.CTRLB bit masks and bit positions */ -#define USART_ONEWIRE_bm 0x80 /* One Wire Mode bit mask. */ -#define USART_ONEWIRE_bp 7 /* One Wire Mode bit position. */ - -#define USART_SFDEN_bm 0x40 /* Start Frame Detection Enable bit mask. */ -#define USART_SFDEN_bp 6 /* Start Frame Detection Enable bit position. */ - -#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ -#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ - -#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ -#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ - -#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ -#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ - -#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ -#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ - -#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ -#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ - -/* USART.CTRLC bit masks and bit positions */ -#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ -#define USART_CMODE_gp 6 /* Communication Mode group position. */ -#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ -#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ -#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ -#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ - -#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ -#define USART_PMODE_gp 4 /* Parity Mode group position. */ -#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ -#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ -#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ -#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ - -#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ -#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ - -#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ -#define USART_CHSIZE_gp 0 /* Character Size group position. */ -#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ -#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ -#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ -#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ -#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ -#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ - -/* USART.CTRLD bit masks and bit positions */ -#define USART_DECTYPE_gm 0x30 /* Receive Interrupt Level group mask. */ -#define USART_DECTYPE_gp 4 /* Receive Interrupt Level group position. */ -#define USART_DECTYPE0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ -#define USART_DECTYPE0_bp 4 /* Receive Interrupt Level bit 0 position. */ -#define USART_DECTYPE1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ -#define USART_DECTYPE1_bp 5 /* Receive Interrupt Level bit 1 position. */ - -#define USART_LUTACT_gm 0x0C /* Transmit Interrupt Level group mask. */ -#define USART_LUTACT_gp 2 /* Transmit Interrupt Level group position. */ -#define USART_LUTACT0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ -#define USART_LUTACT0_bp 2 /* Transmit Interrupt Level bit 0 position. */ -#define USART_LUTACT1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ -#define USART_LUTACT1_bp 3 /* Transmit Interrupt Level bit 1 position. */ - -#define USART_PECACT_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ -#define USART_PECACT_gp 0 /* Data Register Empty Interrupt Level group position. */ -#define USART_PECACT0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ -#define USART_PECACT0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ -#define USART_PECACT1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ -#define USART_PECACT1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ - -/* USART.BAUDCTRLA bit masks and bit positions */ -#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ -#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ -#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ -#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ -#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ -#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ -#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ -#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ -#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ -#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ -#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ -#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ -#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ -#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ -#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ -#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ -#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ -#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ - -/* USART.BAUDCTRLB bit masks and bit positions */ -#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ -#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ -#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ -#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ -#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ -#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ -#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ -#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ -#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ -#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ - -/* USART_BSEL Predefined. */ -/* USART_BSEL Predefined. */ - -/* SPI - Serial Peripheral Interface */ -/* SPI.CTRL bit masks and bit positions */ -#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ -#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ - -#define SPI_ENABLE_bm 0x40 /* Enable SPI Module bit mask. */ -#define SPI_ENABLE_bp 6 /* Enable SPI Module bit position. */ - -#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ -#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ - -#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ -#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ - -#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ -#define SPI_MODE_gp 2 /* SPI Mode group position. */ -#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ -#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ -#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ -#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ - -#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ -#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ -#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ -#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ -#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ -#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ - -/* SPI.INTCTRL bit masks and bit positions */ -#define SPI_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable (In Buffer Modes Only). bit mask. */ -#define SPI_RXCIE_bp 7 /* Receive Complete Interrupt Enable (In Buffer Modes Only). bit position. */ - -#define SPI_TXCIE_bm 0x40 /* Transmit Complete Interrupt Enable (In Buffer Modes Only). bit mask. */ -#define SPI_TXCIE_bp 6 /* Transmit Complete Interrupt Enable (In Buffer Modes Only). bit position. */ - -#define SPI_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable (In Buffer Modes Only). bit mask. */ -#define SPI_DREIE_bp 5 /* Data Register Empty Interrupt Enable (In Buffer Modes Only). bit position. */ - -#define SPI_SSIE_bm 0x10 /* Slave Select Trigger Interrupt Enable (In Buffer Modes Only). bit mask. */ -#define SPI_SSIE_bp 4 /* Slave Select Trigger Interrupt Enable (In Buffer Modes Only). bit position. */ - -#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ -#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ -#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ - -/* SPI.STATUS bit masks and bit positions */ -#define SPI_IF_bm 0x80 /* Interrupt Flag (In Standard Mode Only). bit mask. */ -#define SPI_IF_bp 7 /* Interrupt Flag (In Standard Mode Only). bit position. */ - -#define SPI_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag (In Buffer Modes Only). bit mask. */ -#define SPI_RXCIF_bp 7 /* Receive Complete Interrupt Flag (In Buffer Modes Only). bit position. */ - -#define SPI_WRCOL_bm 0x40 /* Write Collision Flag (In Standard Mode Only). bit mask. */ -#define SPI_WRCOL_bp 6 /* Write Collision Flag (In Standard Mode Only). bit position. */ - -#define SPI_TXCIF_bm 0x40 /* Transmit Complete Interrupt Flag (In Buffer Modes Only). bit mask. */ -#define SPI_TXCIF_bp 6 /* Transmit Complete Interrupt Flag (In Buffer Modes Only). bit position. */ - -#define SPI_DREIF_bm 0x20 /* Data Register Empty Interrupt Flag (In Buffer Modes Only). bit mask. */ -#define SPI_DREIF_bp 5 /* Data Register Empty Interrupt Flag (In Buffer Modes Only). bit position. */ - -#define SPI_SSIF_bm 0x10 /* Slave Select Trigger Interrupt Flag (In Buffer Modes Only). bit mask. */ -#define SPI_SSIF_bp 4 /* Slave Select Trigger Interrupt Flag (In Buffer Modes Only). bit position. */ - -#define SPI_BUFOVF_bm 0x01 /* Buffer Overflow (In Buffer Modes Only). bit mask. */ -#define SPI_BUFOVF_bp 0 /* Buffer Overflow (In Buffer Modes Only). bit position. */ - -/* SPI.CTRLB bit masks and bit positions */ -#define SPI_BUFMODE_gm 0xC0 /* Buffer Modes group mask. */ -#define SPI_BUFMODE_gp 6 /* Buffer Modes group position. */ -#define SPI_BUFMODE0_bm (1<<6) /* Buffer Modes bit 0 mask. */ -#define SPI_BUFMODE0_bp 6 /* Buffer Modes bit 0 position. */ -#define SPI_BUFMODE1_bm (1<<7) /* Buffer Modes bit 1 mask. */ -#define SPI_BUFMODE1_bp 7 /* Buffer Modes bit 1 position. */ - -#define SPI_SSD_bm 0x04 /* Slave Select Disable bit mask. */ -#define SPI_SSD_bp 2 /* Slave Select Disable bit position. */ - -/* IRCOM - IR Communication Module */ -/* IRCOM.CTRL bit masks and bit positions */ -#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ -#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ -#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ -#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ -#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ -#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ -#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ -#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ -#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ -#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ - -/* FUSE - Fuses and Lockbits */ -/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ -#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ - -#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ - -#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ - -#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ -#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ -#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ -#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ - -/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ -#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ -#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ -#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ -#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ -#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ -#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ -#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ -#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ -#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ -#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ - -#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ -#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ -#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ -#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ -#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ -#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ -#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ -#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ -#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ -#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ - -/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ -#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ -#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ - -#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ -#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ -#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ -#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ -#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ -#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ - -/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ -#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ -#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ - -#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ -#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ -#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ -#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ -#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ -#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ - -#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ -#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ - -/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ -#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ -#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ -#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ -#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ -#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ -#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ - -#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ -#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ - -#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ -#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ -#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ -#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ -#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ -#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ -#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ -#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ - -/* NVM_FUSES.FUSEBYTE6 bit masks and bit positions */ -#define NVM_FUSES_FDACT5_bm 0x80 /* Fault Dectection Action on TC5 bit mask. */ -#define NVM_FUSES_FDACT5_bp 7 /* Fault Dectection Action on TC5 bit position. */ - -#define NVM_FUSES_FDACT4_bm 0x40 /* Fault Dectection Action on TC4 bit mask. */ -#define NVM_FUSES_FDACT4_bp 6 /* Fault Dectection Action on TC4 bit position. */ - -#define NVM_FUSES_VALUE_gm 0x3F /* Port Pin Value group mask. */ -#define NVM_FUSES_VALUE_gp 0 /* Port Pin Value group position. */ -#define NVM_FUSES_VALUE0_bm (1<<0) /* Port Pin Value bit 0 mask. */ -#define NVM_FUSES_VALUE0_bp 0 /* Port Pin Value bit 0 position. */ -#define NVM_FUSES_VALUE1_bm (1<<1) /* Port Pin Value bit 1 mask. */ -#define NVM_FUSES_VALUE1_bp 1 /* Port Pin Value bit 1 position. */ -#define NVM_FUSES_VALUE2_bm (1<<2) /* Port Pin Value bit 2 mask. */ -#define NVM_FUSES_VALUE2_bp 2 /* Port Pin Value bit 2 position. */ -#define NVM_FUSES_VALUE3_bm (1<<3) /* Port Pin Value bit 3 mask. */ -#define NVM_FUSES_VALUE3_bp 3 /* Port Pin Value bit 3 position. */ -#define NVM_FUSES_VALUE4_bm (1<<4) /* Port Pin Value bit 4 mask. */ -#define NVM_FUSES_VALUE4_bp 4 /* Port Pin Value bit 4 position. */ -#define NVM_FUSES_VALUE5_bm (1<<5) /* Port Pin Value bit 5 mask. */ -#define NVM_FUSES_VALUE5_bp 5 /* Port Pin Value bit 5 position. */ - - - -// Generic Port Pins - -#define PIN0_bm 0x01 -#define PIN0_bp 0 -#define PIN1_bm 0x02 -#define PIN1_bp 1 -#define PIN2_bm 0x04 -#define PIN2_bp 2 -#define PIN3_bm 0x08 -#define PIN3_bp 3 -#define PIN4_bm 0x10 -#define PIN4_bp 4 -#define PIN5_bm 0x20 -#define PIN5_bp 5 -#define PIN6_bm 0x40 -#define PIN6_bp 6 -#define PIN7_bm 0x80 -#define PIN7_bp 7 - -/* ========== Interrupt Vector Definitions ========== */ -/* Vector 0 is the reset vector */ - -/* OSC interrupt vectors */ -#define OSC_OSCF_vect_num 1 -#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ - -/* PORTR interrupt vectors */ -#define PORTR_INT_vect_num 2 -#define PORTR_INT_vect _VECTOR(2) /* External Interrupt */ - -/* EDMA interrupt vectors */ -#define EDMA_CH0_vect_num 3 -#define EDMA_CH0_vect _VECTOR(3) /* EDMA Channel 0 Interrupt */ -#define EDMA_CH1_vect_num 4 -#define EDMA_CH1_vect _VECTOR(4) /* EDMA Channel 1 Interrupt */ -#define EDMA_CH2_vect_num 5 -#define EDMA_CH2_vect _VECTOR(5) /* EDMA Channel 2 Interrupt */ -#define EDMA_CH3_vect_num 6 -#define EDMA_CH3_vect _VECTOR(6) /* EDMA Channel 3 Interrupt */ - -/* RTC interrupt vectors */ -#define RTC_OVF_vect_num 7 -#define RTC_OVF_vect _VECTOR(7) /* Overflow Interrupt */ -#define RTC_COMP_vect_num 8 -#define RTC_COMP_vect _VECTOR(8) /* Compare Interrupt */ - -/* PORTC interrupt vectors */ -#define PORTC_INT_vect_num 9 -#define PORTC_INT_vect _VECTOR(9) /* External Interrupt */ - -/* TWIC interrupt vectors */ -#define TWIC_TWIS_vect_num 10 -#define TWIC_TWIS_vect _VECTOR(10) /* TWI Slave Interrupt */ -#define TWIC_TWIM_vect_num 11 -#define TWIC_TWIM_vect _VECTOR(11) /* TWI Master Interrupt */ - -/* TCC4 interrupt vectors */ -#define TCC4_OVF_vect_num 12 -#define TCC4_OVF_vect _VECTOR(12) /* Overflow Interrupt */ -#define TCC4_ERR_vect_num 13 -#define TCC4_ERR_vect _VECTOR(13) /* Error Interrupt */ -#define TCC4_CCA_vect_num 14 -#define TCC4_CCA_vect _VECTOR(14) /* Channel A Compare or Capture Interrupt */ -#define TCC4_CCB_vect_num 15 -#define TCC4_CCB_vect _VECTOR(15) /* Channel B Compare or Capture Interrupt */ -#define TCC4_CCC_vect_num 16 -#define TCC4_CCC_vect _VECTOR(16) /* Channel C Compare or Capture Interrupt */ -#define TCC4_CCD_vect_num 17 -#define TCC4_CCD_vect _VECTOR(17) /* Channel D Compare or Capture Interrupt */ - -/* TCC5 interrupt vectors */ -#define TCC5_OVF_vect_num 18 -#define TCC5_OVF_vect _VECTOR(18) /* Overflow Interrupt */ -#define TCC5_ERR_vect_num 19 -#define TCC5_ERR_vect _VECTOR(19) /* Error Interrupt */ -#define TCC5_CCA_vect_num 20 -#define TCC5_CCA_vect _VECTOR(20) /* Channel A Compare or Capture Interrupt */ -#define TCC5_CCB_vect_num 21 -#define TCC5_CCB_vect _VECTOR(21) /* Channel B Compare or Capture Interrupt */ - -/* SPIC interrupt vectors */ -#define SPIC_INT_vect_num 22 -#define SPIC_INT_vect _VECTOR(22) /* SPI Interrupt */ - -/* USARTC0 interrupt vectors */ -#define USARTC0_RXC_vect_num 23 -#define USARTC0_RXC_vect _VECTOR(23) /* Reception Complete Interrupt */ -#define USARTC0_DRE_vect_num 24 -#define USARTC0_DRE_vect _VECTOR(24) /* Data Register Empty Interrupt */ -#define USARTC0_TXC_vect_num 25 -#define USARTC0_TXC_vect _VECTOR(25) /* Transmission Complete Interrupt */ - -/* NVM interrupt vectors */ -#define NVM_EE_vect_num 26 -#define NVM_EE_vect _VECTOR(26) /* EE Interrupt */ -#define NVM_SPM_vect_num 27 -#define NVM_SPM_vect _VECTOR(27) /* SPM Interrupt */ - -/* XCL interrupt vectors */ -#define XCL_UNF_vect_num 28 -#define XCL_UNF_vect _VECTOR(28) /* Timer/Counter Underflow Interrupt */ -#define XCL_CC_vect_num 29 -#define XCL_CC_vect _VECTOR(29) /* Timer/Counter Compare or Capture Interrupt */ - -/* PORTA interrupt vectors */ -#define PORTA_INT_vect_num 30 -#define PORTA_INT_vect _VECTOR(30) /* External Interrupt */ - -/* ACA interrupt vectors */ -#define ACA_AC0_vect_num 31 -#define ACA_AC0_vect _VECTOR(31) /* AC0 Interrupt */ -#define ACA_AC1_vect_num 32 -#define ACA_AC1_vect _VECTOR(32) /* AC1 Interrupt */ -#define ACA_ACW_vect_num 33 -#define ACA_ACW_vect _VECTOR(33) /* ACW Window Mode Interrupt */ - -/* ADCA interrupt vectors */ -#define ADCA_CH0_vect_num 34 -#define ADCA_CH0_vect _VECTOR(34) /* ADC Channel Interrupt */ - -/* PORTD interrupt vectors */ -#define PORTD_INT_vect_num 35 -#define PORTD_INT_vect _VECTOR(35) /* External Interrupt */ - -/* TCD5 interrupt vectors */ -#define TCD5_OVF_vect_num 36 -#define TCD5_OVF_vect _VECTOR(36) /* Overflow Interrupt */ -#define TCD5_ERR_vect_num 37 -#define TCD5_ERR_vect _VECTOR(37) /* Error Interrupt */ -#define TCD5_CCA_vect_num 38 -#define TCD5_CCA_vect _VECTOR(38) /* Channel A Compare or Capture Interrupt */ -#define TCD5_CCB_vect_num 39 -#define TCD5_CCB_vect _VECTOR(39) /* Channel B Compare or Capture Interrupt */ - -/* USARTD0 interrupt vectors */ -#define USARTD0_RXC_vect_num 40 -#define USARTD0_RXC_vect _VECTOR(40) /* Reception Complete Interrupt */ -#define USARTD0_DRE_vect_num 41 -#define USARTD0_DRE_vect _VECTOR(41) /* Data Register Empty Interrupt */ -#define USARTD0_TXC_vect_num 42 -#define USARTD0_TXC_vect _VECTOR(42) /* Transmission Complete Interrupt */ - -#define _VECTOR_SIZE 4 /* Size of individual vector. */ -#define _VECTORS_SIZE (43 * _VECTOR_SIZE) - - -/* ========== Constants ========== */ - -#define PROGMEM_START (0x0000) -#define PROGMEM_SIZE (36864) -#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) - -#define APP_SECTION_START (0x0000) -#define APP_SECTION_SIZE (32768) -#define APP_SECTION_PAGE_SIZE (128) -#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) - -#define APPTABLE_SECTION_START (0x7000) -#define APPTABLE_SECTION_SIZE (4096) -#define APPTABLE_SECTION_PAGE_SIZE (128) -#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) - -#define BOOT_SECTION_START (0x8000) -#define BOOT_SECTION_SIZE (4096) -#define BOOT_SECTION_PAGE_SIZE (128) -#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) - -#define DATAMEM_START (0x0000) -#define DATAMEM_SIZE (12288) -#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) - -#define IO_START (0x0000) -#define IO_SIZE (4096) -#define IO_PAGE_SIZE (0) -#define IO_END (IO_START + IO_SIZE - 1) - -#define MAPPED_EEPROM_START (0x1000) -#define MAPPED_EEPROM_SIZE (1024) -#define MAPPED_EEPROM_PAGE_SIZE (0) -#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) - -#define INTERNAL_SRAM_START (0x2000) -#define INTERNAL_SRAM_SIZE (4096) -#define INTERNAL_SRAM_PAGE_SIZE (0) -#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) - -#define EEPROM_START (0x0000) -#define EEPROM_SIZE (1024) -#define EEPROM_PAGE_SIZE (32) -#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) - -#define SIGNATURES_START (0x0000) -#define SIGNATURES_SIZE (3) -#define SIGNATURES_PAGE_SIZE (0) -#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) - -#define FUSES_START (0x0000) -#define FUSES_SIZE (7) -#define FUSES_PAGE_SIZE (0) -#define FUSES_END (FUSES_START + FUSES_SIZE - 1) - -#define LOCKBITS_START (0x0000) -#define LOCKBITS_SIZE (1) -#define LOCKBITS_PAGE_SIZE (0) -#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) - -#define USER_SIGNATURES_START (0x0000) -#define USER_SIGNATURES_SIZE (128) -#define USER_SIGNATURES_PAGE_SIZE (128) -#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) - -#define PROD_SIGNATURES_START (0x0000) -#define PROD_SIGNATURES_SIZE (54) -#define PROD_SIGNATURES_PAGE_SIZE (128) -#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) - -#define FLASHSTART PROGMEM_START -#define FLASHEND PROGMEM_END -#define SPM_PAGESIZE 128 -#define RAMSTART INTERNAL_SRAM_START -#define RAMSIZE INTERNAL_SRAM_SIZE -#define RAMEND INTERNAL_SRAM_END -#define E2END EEPROM_END -#define E2PAGESIZE EEPROM_PAGE_SIZE - - -/* ========== Fuses ========== */ -#define FUSE_MEMORY_SIZE 7 - -/* Fuse Byte 0 Reserved */ - -/* Fuse Byte 1 */ -#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ -#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ -#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ -#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ -#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ -#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ -#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ -#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ -#define FUSE1_DEFAULT (0xFF) - -/* Fuse Byte 2 */ -#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ -#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ -#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ -#define FUSE2_DEFAULT (0xFF) - -/* Fuse Byte 3 Reserved */ - -/* Fuse Byte 4 */ -#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ -#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ -#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ -#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ -#define FUSE4_DEFAULT (0xFF) - -/* Fuse Byte 5 */ -#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ -#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ -#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ -#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ -#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ -#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ -#define FUSE5_DEFAULT (0xFF) - -/* Fuse Byte 6 */ -#define FUSE_VALUE0 (unsigned char)~_BV(0) /* Port Pin Value Bit 0 */ -#define FUSE_VALUE1 (unsigned char)~_BV(1) /* Port Pin Value Bit 1 */ -#define FUSE_VALUE2 (unsigned char)~_BV(2) /* Port Pin Value Bit 2 */ -#define FUSE_VALUE3 (unsigned char)~_BV(3) /* Port Pin Value Bit 3 */ -#define FUSE_VALUE4 (unsigned char)~_BV(4) /* Port Pin Value Bit 4 */ -#define FUSE_VALUE5 (unsigned char)~_BV(5) /* Port Pin Value Bit 5 */ -#define FUSE_FDACT4 (unsigned char)~_BV(6) /* Fault Dectection Action on TC4 */ -#define FUSE_FDACT5 (unsigned char)~_BV(7) /* Fault Dectection Action on TC5 */ -#define FUSE6_DEFAULT (0xFF) - -/* ========== Lock Bits ========== */ -#define __LOCK_BITS_EXIST -#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST -#define __BOOT_LOCK_APPLICATION_BITS_EXIST -#define __BOOT_LOCK_BOOT_BITS_EXIST - -/* ========== Signature ========== */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x95 -#define SIGNATURE_2 0x4C - -/* ========== Power Reduction Condition Definitions ========== */ - -/* PR.PRGEN */ -#define __AVR_HAVE_PRGEN (PR_XCL_bm|PR_RTC_bm|PR_EVSYS_bm|PR_EDMA_bm) -#define __AVR_HAVE_PRGEN_XCL -#define __AVR_HAVE_PRGEN_RTC -#define __AVR_HAVE_PRGEN_EVSYS -#define __AVR_HAVE_PRGEN_EDMA - -/* PR.PRPA */ -#define __AVR_HAVE_PRPA (PR_DAC_bm|PR_ADC_bm|PR_AC_bm) -#define __AVR_HAVE_PRPA_DAC -#define __AVR_HAVE_PRPA_ADC -#define __AVR_HAVE_PRPA_AC - -/* PR.PRPC */ -#define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC5_bm|PR_TC4_bm) -#define __AVR_HAVE_PRPC_TWI -#define __AVR_HAVE_PRPC_USART0 -#define __AVR_HAVE_PRPC_SPI -#define __AVR_HAVE_PRPC_HIRES -#define __AVR_HAVE_PRPC_TC5 -#define __AVR_HAVE_PRPC_TC4 - -/* PR.PRPD */ -#define __AVR_HAVE_PRPD (PR_USART0_bm|PR_TC5_bm) -#define __AVR_HAVE_PRPD_USART0 -#define __AVR_HAVE_PRPD_TC5 - - -#endif /* #ifdef _AVR_ATXMEGA32E5_H_INCLUDED */ - +/***************************************************************************** + * + * Copyright (C) 2016 Atmel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * * Neither the name of the copyright holders nor the names of + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ****************************************************************************/ + + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iox32e5.h" +#else +# error "Attempt to include more than one file." +#endif + +#ifndef _AVR_ATXMEGA32E5_H_INCLUDED +#define _AVR_ATXMEGA32E5_H_INCLUDED + +/* Ungrouped common registers */ +#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ + +/* Deprecated */ +#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ + +#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ +#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ +#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ +#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ +#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ +#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +#define SREG _SFR_MEM8(0x003F) /* Status Register */ + +/* C Language Only */ +#if !defined (__ASSEMBLER__) + +#include + +typedef volatile uint8_t register8_t; +typedef volatile uint16_t register16_t; +typedef volatile uint32_t register32_t; + + +#ifdef _WORDREGISTER +#undef _WORDREGISTER +#endif +#define _WORDREGISTER(regname) \ + __extension__ union \ + { \ + register16_t regname; \ + struct \ + { \ + register8_t regname ## L; \ + register8_t regname ## H; \ + }; \ + } + +#ifdef _DWORDREGISTER +#undef _DWORDREGISTER +#endif +#define _DWORDREGISTER(regname) \ + __extension__ union \ + { \ + register32_t regname; \ + struct \ + { \ + register8_t regname ## 0; \ + register8_t regname ## 1; \ + register8_t regname ## 2; \ + register8_t regname ## 3; \ + }; \ + } + + +/* +========================================================================== +IO Module Structures +========================================================================== +*/ + + +/* +-------------------------------------------------------------------------- +VPORT - Virtual Ports +-------------------------------------------------------------------------- +*/ + +/* Virtual Port */ +typedef struct VPORT_struct +{ + register8_t DIR; /* I/O Port Data Direction */ + register8_t OUT; /* I/O Port Output */ + register8_t IN; /* I/O Port Input */ + register8_t INTFLAGS; /* Interrupt Flag Register */ +} VPORT_t; + + +/* +-------------------------------------------------------------------------- +XOCD - On-Chip Debug System +-------------------------------------------------------------------------- +*/ + +/* On-Chip Debug System */ +typedef struct OCD_struct +{ + register8_t OCDR0; /* OCD Register 0 */ + register8_t OCDR1; /* OCD Register 1 */ +} OCD_t; + + +/* +-------------------------------------------------------------------------- +CPU - CPU +-------------------------------------------------------------------------- +*/ + +/* CCP signatures */ +typedef enum CCP_enum +{ + CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ + CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +} CCP_t; + + +/* +-------------------------------------------------------------------------- +CLK - Clock System +-------------------------------------------------------------------------- +*/ + +/* Clock System */ +typedef struct CLK_struct +{ + register8_t CTRL; /* Control Register */ + register8_t PSCTRL; /* Prescaler Control Register */ + register8_t LOCK; /* Lock register */ + register8_t RTCCTRL; /* RTC Control Register */ + register8_t reserved_0x04; +} CLK_t; + + +/* Power Reduction */ +typedef struct PR_struct +{ + register8_t PRGEN; /* General Power Reduction */ + register8_t PRPA; /* Power Reduction Port A */ + register8_t reserved_0x02; + register8_t PRPC; /* Power Reduction Port C */ + register8_t PRPD; /* Power Reduction Port D */ + register8_t reserved_0x05; + register8_t reserved_0x06; +} PR_t; + +/* System Clock Selection */ +typedef enum CLK_SCLKSEL_enum +{ + CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ + CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ + CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ + CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ + CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ + CLK_SCLKSEL_RC8M_gc = (0x05<<0), /* Internal 8 MHz RC Oscillator */ +} CLK_SCLKSEL_t; + +/* Prescaler A Division Factor */ +typedef enum CLK_PSADIV_enum +{ + CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ + CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ + CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ + CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ + CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ + CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ + CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ + CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ + CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ + CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ + CLK_PSADIV_6_gc = (0x13<<2), /* Divide by 6 */ + CLK_PSADIV_10_gc = (0x15<<2), /* Divide by 10 */ + CLK_PSADIV_12_gc = (0x17<<2), /* Divide by 12 */ + CLK_PSADIV_24_gc = (0x19<<2), /* Divide by 24 */ + CLK_PSADIV_48_gc = (0x1B<<2), /* Divide by 48 */ +} CLK_PSADIV_t; + +/* Prescaler B and C Division Factor */ +typedef enum CLK_PSBCDIV_enum +{ + CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ + CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ + CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ + CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ +} CLK_PSBCDIV_t; + +/* RTC Clock Source */ +typedef enum CLK_RTCSRC_enum +{ + CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ + CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ + CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ + CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ + CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ + CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ +} CLK_RTCSRC_t; + + +/* +-------------------------------------------------------------------------- +SLEEP - Sleep Controller +-------------------------------------------------------------------------- +*/ + +/* Sleep Controller */ +typedef struct SLEEP_struct +{ + register8_t CTRL; /* Control Register */ +} SLEEP_t; + +/* Sleep Mode */ +typedef enum SLEEP_SMODE_enum +{ + SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ + SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ + SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ + SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ + SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ +} SLEEP_SMODE_t; + + + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +#define SLEEP_MODE_PWR_SAVE (0x03<<1) +#define SLEEP_MODE_STANDBY (0x06<<1) +#define SLEEP_MODE_EXT_STANDBY (0x07<<1) +/* +-------------------------------------------------------------------------- +OSC - Oscillator +-------------------------------------------------------------------------- +*/ + +/* Oscillator */ +typedef struct OSC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t XOSCCTRL; /* External Oscillator Control Register */ + register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ + register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ + register8_t PLLCTRL; /* PLL Control Register */ + register8_t DFLLCTRL; /* DFLL Control Register */ + register8_t RC8MCAL; /* Internal 8 MHz RC Oscillator Calibration Register */ +} OSC_t; + +/* Oscillator Frequency Range */ +typedef enum OSC_FRQRANGE_enum +{ + OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ + OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ + OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ + OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ +} OSC_FRQRANGE_t; + +/* External Oscillator Selection and Startup Time */ +typedef enum OSC_XOSCSEL_enum +{ + OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock on port R1 - 6 CLK */ + OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ + OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ + OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ + OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ + OSC_XOSCSEL_EXTCLK_C4_gc = (0x14<<0), /* External Clock on port C4 - 6 CLK */ +} OSC_XOSCSEL_t; + +/* PLL Clock Source */ +typedef enum OSC_PLLSRC_enum +{ + OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ + OSC_PLLSRC_RC8M_gc = (0x01<<6), /* Internal 8 MHz RC Oscillator */ + OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ + OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ +} OSC_PLLSRC_t; + +/* 32 MHz DFLL Calibration Reference */ +typedef enum OSC_RC32MCREF_enum +{ + OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ + OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ +} OSC_RC32MCREF_t; + + +/* +-------------------------------------------------------------------------- +DFLL - DFLL +-------------------------------------------------------------------------- +*/ + +/* DFLL */ +typedef struct DFLL_struct +{ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x01; + register8_t CALA; /* Calibration Register A */ + register8_t CALB; /* Calibration Register B */ + register8_t COMP0; /* Oscillator Compare Register 0 */ + register8_t COMP1; /* Oscillator Compare Register 1 */ + register8_t COMP2; /* Oscillator Compare Register 2 */ + register8_t reserved_0x07; +} DFLL_t; + + +/* +-------------------------------------------------------------------------- +RST - Reset +-------------------------------------------------------------------------- +*/ + +/* Reset */ +typedef struct RST_struct +{ + register8_t STATUS; /* Status Register */ + register8_t CTRL; /* Control Register */ +} RST_t; + + +/* +-------------------------------------------------------------------------- +WDT - Watch-Dog Timer +-------------------------------------------------------------------------- +*/ + +/* Watch-Dog Timer */ +typedef struct WDT_struct +{ + register8_t CTRL; /* Control */ + register8_t WINCTRL; /* Windowed Mode Control */ + register8_t STATUS; /* Status */ +} WDT_t; + +/* Period setting */ +typedef enum WDT_PER_enum +{ + WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ + WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ + WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ + WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ + WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ + WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ + WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ + WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ + WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ + WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ + WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +} WDT_PER_t; + +/* Closed window period */ +typedef enum WDT_WPER_enum +{ + WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ + WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ + WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ + WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ + WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ + WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ + WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ + WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ + WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ + WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ + WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +} WDT_WPER_t; + + +/* +-------------------------------------------------------------------------- +MCU - MCU Control +-------------------------------------------------------------------------- +*/ + +/* MCU Control */ +typedef struct MCU_struct +{ + register8_t DEVID0; /* Device ID byte 0 */ + register8_t DEVID1; /* Device ID byte 1 */ + register8_t DEVID2; /* Device ID byte 2 */ + register8_t REVID; /* Revision ID */ + register8_t reserved_0x04; + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t ANAINIT; /* Analog Startup Delay */ + register8_t EVSYSLOCK; /* Event System Lock */ + register8_t WEXLOCK; /* WEX Lock */ + register8_t FAULTLOCK; /* FAULT Lock */ + register8_t reserved_0x0B; +} MCU_t; + + +/* +-------------------------------------------------------------------------- +PMIC - Programmable Multi-level Interrupt Controller +-------------------------------------------------------------------------- +*/ + +/* Programmable Multi-level Interrupt Controller */ +typedef struct PMIC_struct +{ + register8_t STATUS; /* Status Register */ + register8_t INTPRI; /* Interrupt Priority */ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x03; + register8_t reserved_0x04; + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; +} PMIC_t; + + +/* +-------------------------------------------------------------------------- +PORTCFG - Port Configuration +-------------------------------------------------------------------------- +*/ + +/* I/O port Configuration */ +typedef struct PORTCFG_struct +{ + register8_t MPCMASK; /* Multi-pin Configuration Mask */ + register8_t reserved_0x01; + register8_t reserved_0x02; + register8_t reserved_0x03; + register8_t CLKOUT; /* Clock Out Register */ + register8_t reserved_0x05; + register8_t ACEVOUT; /* Analog Comparator and Event Out Register */ + register8_t SRLCTRL; /* Slew Rate Limit Control Register */ +} PORTCFG_t; + +/* Clock and Event Output Port */ +typedef enum PORTCFG_CLKEVPIN_enum +{ + PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */ + PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */ +} PORTCFG_CLKEVPIN_t; + +/* RTC Clock Output Port */ +typedef enum PORTCFG_RTCCLKOUT_enum +{ + PORTCFG_RTCCLKOUT_OFF_gc = (0x00<<5), /* System Clock Output Disabled */ + PORTCFG_RTCCLKOUT_PC6_gc = (0x01<<5), /* System Clock Output on Port C pin 6 */ + PORTCFG_RTCCLKOUT_PD6_gc = (0x02<<5), /* System Clock Output on Port D pin 6 */ + PORTCFG_RTCCLKOUT_PR0_gc = (0x03<<5), /* System Clock Output on Port R pin 0 */ +} PORTCFG_RTCCLKOUT_t; + +/* Peripheral Clock Output Select */ +typedef enum PORTCFG_CLKOUTSEL_enum +{ + PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ + PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ + PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ +} PORTCFG_CLKOUTSEL_t; + +/* System Clock Output Port */ +typedef enum PORTCFG_CLKOUT_enum +{ + PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ + PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ + PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ + PORTCFG_CLKOUT_PR0_gc = (0x03<<0), /* System Clock Output on Port R pin 0 */ +} PORTCFG_CLKOUT_t; + +/* Analog Comparator Output Port */ +typedef enum PORTCFG_ACOUT_enum +{ + PORTCFG_ACOUT_PA_gc = (0x00<<6), /* Analog Comparator Outputs on Port A, Pin 6-7 */ + PORTCFG_ACOUT_PC_gc = (0x01<<6), /* Analog Comparator Outputs on Port C, Pin 6-7 */ + PORTCFG_ACOUT_PD_gc = (0x02<<6), /* Analog Comparator Outputs on Port D, Pin 6-7 */ + PORTCFG_ACOUT_PR_gc = (0x03<<6), /* Analog Comparator Outputs on Port R, Pin 0-1 */ +} PORTCFG_ACOUT_t; + +/* Event Output Port */ +typedef enum PORTCFG_EVOUT_enum +{ + PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ + PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel n Output on Port C pin 7 */ + PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel n Output on Port D pin 7 */ + PORTCFG_EVOUT_PR0_gc = (0x03<<4), /* Event Channel n Output on Port R pin 0 */ +} PORTCFG_EVOUT_t; + +/* Event Output Select */ +typedef enum PORTCFG_EVOUTSEL_enum +{ + PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ + PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ + PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ + PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ + PORTCFG_EVOUTSEL_4_gc = (0x04<<0), /* Event Channel 4 output to pin */ + PORTCFG_EVOUTSEL_5_gc = (0x05<<0), /* Event Channel 5 output to pin */ + PORTCFG_EVOUTSEL_6_gc = (0x06<<0), /* Event Channel 6 output to pin */ + PORTCFG_EVOUTSEL_7_gc = (0x07<<0), /* Event Channel 7 output to pin */ +} PORTCFG_EVOUTSEL_t; + + +/* +-------------------------------------------------------------------------- +CRC - Cyclic Redundancy Checker +-------------------------------------------------------------------------- +*/ + +/* Cyclic Redundancy Checker */ +typedef struct CRC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t reserved_0x02; + register8_t DATAIN; /* Data Input */ + register8_t CHECKSUM0; /* Checksum byte 0 */ + register8_t CHECKSUM1; /* Checksum byte 1 */ + register8_t CHECKSUM2; /* Checksum byte 2 */ + register8_t CHECKSUM3; /* Checksum byte 3 */ +} CRC_t; + +/* Reset */ +typedef enum CRC_RESET_enum +{ + CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ + CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ + CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ +} CRC_RESET_t; + +/* Input Source */ +typedef enum CRC_SOURCE_enum +{ + CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ + CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ + CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ + CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */ + CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */ + CRC_SOURCE_DMAC2_gc = (0x06<<0), /* DMAC Channel 2 */ + CRC_SOURCE_DMAC3_gc = (0x07<<0), /* DMAC Channel 3 */ +} CRC_SOURCE_t; + + +/* +-------------------------------------------------------------------------- +EDMA - Enhanced DMA Controller +-------------------------------------------------------------------------- +*/ + +/* EDMA Channel */ +typedef struct EDMA_CH_struct +{ + register8_t CTRLA; /* Channel Control A */ + register8_t CTRLB; /* Channel Control */ + register8_t ADDRCTRL; /* Memory Address Control for Peripheral Ch., or Source Address Control for Standard Ch. */ + register8_t DESTADDRCTRL; /* Destination Address Control for Standard Channels Only. */ + register8_t TRIGSRC; /* Channel Trigger Source */ + register8_t reserved_0x05; + _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count for Peripheral Ch., or Channel Block Transfer Count Low for Standard Ch. */ + _WORDREGISTER(ADDR); /* Channel Memory Address for Peripheral Ch., or Channel Source Address Low for Standard Ch. */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; + _WORDREGISTER(DESTADDR); /* Channel Destination Address for Standard Channels Only. */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; +} EDMA_CH_t; + + +/* Enhanced DMA Controller */ +typedef struct EDMA_struct +{ + register8_t CTRL; /* Control */ + register8_t reserved_0x01; + register8_t reserved_0x02; + register8_t INTFLAGS; /* Transfer Interrupt Status */ + register8_t STATUS; /* Status */ + register8_t reserved_0x05; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + EDMA_CH_t CH0; /* EDMA Channel 0 */ + EDMA_CH_t CH1; /* EDMA Channel 1 */ + EDMA_CH_t CH2; /* EDMA Channel 2 */ + EDMA_CH_t CH3; /* EDMA Channel 3 */ +} EDMA_t; + +/* Channel mode */ +typedef enum EDMA_CHMODE_enum +{ + EDMA_CHMODE_PER0123_gc = (0x00<<4), /* Channels 0, 1, 2 and 3 in peripheal conf. */ + EDMA_CHMODE_STD0_gc = (0x01<<4), /* Channel 0 in standard conf.; channels 2 and 3 in peripheral conf. */ + EDMA_CHMODE_STD2_gc = (0x02<<4), /* Channel 2 in standard conf.; channels 0 and 1 in peripheral conf. */ + EDMA_CHMODE_STD02_gc = (0x03<<4), /* Channels 0 and 2 in standard conf. */ +} EDMA_CHMODE_t; + +/* Double buffer mode */ +typedef enum EDMA_DBUFMODE_enum +{ + EDMA_DBUFMODE_DISABLE_gc = (0x00<<2), /* No double buffer enabled */ + EDMA_DBUFMODE_BUF01_gc = (0x01<<2), /* Double buffer enabled on peripheral channels 0/1 (if exist) */ + EDMA_DBUFMODE_BUF23_gc = (0x02<<2), /* Double buffer enabled on peripheral channels 2/3 (if exist) */ + EDMA_DBUFMODE_BUF0123_gc = (0x03<<2), /* Double buffer enabled on peripheral channels 0/1 and 2/3 or standard channels 0/2 */ +} EDMA_DBUFMODE_t; + +/* Priority mode */ +typedef enum EDMA_PRIMODE_enum +{ + EDMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round robin on all channels */ + EDMA_PRIMODE_RR123_gc = (0x01<<0), /* Ch0 > round robin (Ch 1 ch2 Ch3) */ + EDMA_PRIMODE_RR23_gc = (0x02<<0), /* Ch0 > Ch 1 > round robin (Ch2 Ch3) */ + EDMA_PRIMODE_CH0123_gc = (0x03<<0), /* Ch0 > Ch1 > Ch2 > Ch3 */ +} EDMA_PRIMODE_t; + +/* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. */ +typedef enum EDMA_CH_RELOAD_enum +{ + EDMA_CH_RELOAD_NONE_gc = (0x00<<4), /* No reload */ + EDMA_CH_RELOAD_BLOCK_gc = (0x01<<4), /* Reload at end of each block transfer */ + EDMA_CH_RELOAD_BURST_gc = (0x02<<4), /* Reload at end of each burst transfer */ + EDMA_CH_RELOAD_TRANSACTION_gc = (0x03<<4), /* Reload at end of each transaction */ +} EDMA_CH_RELOAD_t; + +/* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. */ +typedef enum EDMA_CH_DIR_enum +{ + EDMA_CH_DIR_FIXED_gc = (0x00<<0), /* Fixed */ + EDMA_CH_DIR_INC_gc = (0x01<<0), /* Increment */ + EDMA_CH_DIR_MP1_gc = (0x04<<0), /* If Peripheral Ch. (Per ==> Mem), 1-byte 'mask-match' (data: ADDRL, mask: ADDRH), else reserved conf. */ + EDMA_CH_DIR_MP2_gc = (0x05<<0), /* If Peripheral Ch. (Per ==> Mem), 1-byte 'OR-match' (data-1: ADDRL OR data-2: ADDRH), else reserved conf. */ + EDMA_CH_DIR_MP3_gc = (0x06<<0), /* If Peripheral Ch. (Per ==> Mem), 2-byte 'match' (data-1: ADDRL followed by data-2: ADDRH), else reserved conf. */ +} EDMA_CH_DIR_t; + +/* Destination addressing mode */ +typedef enum EDMA_CH_DESTDIR_enum +{ + EDMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ + EDMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ + EDMA_CH_DESTDIR_MP1_gc = (0x04<<0), /* 1-byte 'mask-match' (data: ADDRL, mask: ADDRH) */ + EDMA_CH_DESTDIR_MP2_gc = (0x05<<0), /* 1-byte 'OR-match' (data-1: ADDRL OR data-2: ADDRH) */ + EDMA_CH_DESTDIR_MP3_gc = (0x06<<0), /* 2-byte 'match' (data1: ADDRL followed by data2: ADDRH) */ +} EDMA_CH_DESTDIR_t; + +/* Transfer trigger source */ +typedef enum EDMA_CH_TRIGSRC_enum +{ + EDMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Software triggers only */ + EDMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event CH0 as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event CH1 as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event CH2 as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA CH0 as trigger */ + EDMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA CH0 as trigger */ + EDMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA CH1 as trigger */ + EDMA_CH_TRIGSRC_TCC4_OVF_gc = (0x40<<0), /* TCC4 overflow/underflow as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_TCC4_ERR_gc = (0x41<<0), /* TCC4 error as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_TCC4_CCA_gc = (0x42<<0), /* TCC4 compare or capture channel A as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_TCC4_CCB_gc = (0x43<<0), /* TCC4 compare or capture channel B as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_TCC4_CCC_gc = (0x44<<0), /* TCC4 compare or capture channel C as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_TCC4_CCD_gc = (0x45<<0), /* TCC4 compare or capture channel D as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_TCC5_OVF_gc = (0x46<<0), /* TCC5 overflow/underflow as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_TCC5_ERR_gc = (0x47<<0), /* TCC5 error as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_TCC5_CCA_gc = (0x48<<0), /* TCC5 compare or capture channel A as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_TCC5_CCB_gc = (0x49<<0), /* TCC5 compare or capture channel B as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_SPIC_RXC_gc = (0x4A<<0), /* SPI C transfer complete (SPI Standard Mode) or SPI C receive complete as trigger (SPI Buffer Modes) */ + EDMA_CH_TRIGSRC_SPIC_DRE_gc = (0x4B<<0), /* SPI C transfer complete (SPI Standard Mode) or SPI C data register empty as trigger (SPI Buffer modes) */ + EDMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4C<<0), /* USART C0 receive complete as trigger */ + EDMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4D<<0), /* USART C0 data register empty as trigger */ + EDMA_CH_TRIGSRC_TCD5_OVF_gc = (0x66<<0), /* TCD5 overflow/underflow as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_TCD5_ERR_gc = (0x67<<0), /* TCD5 error as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_TCD5_CCA_gc = (0x68<<0), /* TCD5 compare or capture channel A as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_TCD5_CCB_gc = (0x69<<0), /* TCD5 compare or capture channel B as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6C<<0), /* USART D0 receive complete as trigger */ + EDMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6D<<0), /* USART D0 data register empty as trigger */ +} EDMA_CH_TRIGSRC_t; + +/* Interrupt level */ +typedef enum EDMA_CH_INTLVL_enum +{ + EDMA_CH_INTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ + EDMA_CH_INTLVL_LO_gc = (0x01<<2), /* Low level */ + EDMA_CH_INTLVL_MED_gc = (0x02<<2), /* Medium level */ + EDMA_CH_INTLVL_HI_gc = (0x03<<2), /* High level */ +} EDMA_CH_INTLVL_t; + + +/* +-------------------------------------------------------------------------- +EVSYS - Event System +-------------------------------------------------------------------------- +*/ + +/* Event System */ +typedef struct EVSYS_struct +{ + register8_t CH0MUX; /* Event Channel 0 Multiplexer */ + register8_t CH1MUX; /* Event Channel 1 Multiplexer */ + register8_t CH2MUX; /* Event Channel 2 Multiplexer */ + register8_t CH3MUX; /* Event Channel 3 Multiplexer */ + register8_t CH4MUX; /* Event Channel 4 Multiplexer */ + register8_t CH5MUX; /* Event Channel 5 Multiplexer */ + register8_t CH6MUX; /* Event Channel 6 Multiplexer */ + register8_t CH7MUX; /* Event Channel 7 Multiplexer */ + register8_t CH0CTRL; /* Channel 0 Control Register */ + register8_t CH1CTRL; /* Channel 1 Control Register */ + register8_t CH2CTRL; /* Channel 2 Control Register */ + register8_t CH3CTRL; /* Channel 3 Control Register */ + register8_t CH4CTRL; /* Channel 4 Control Register */ + register8_t CH5CTRL; /* Channel 5 Control Register */ + register8_t CH6CTRL; /* Channel 6 Control Register */ + register8_t CH7CTRL; /* Channel 7 Control Register */ + register8_t STROBE; /* Event Strobe */ + register8_t DATA; /* Event Data */ + register8_t DFCTRL; /* Digital Filter Control Register */ +} EVSYS_t; + +/* Event Channel multiplexer input selection */ +typedef enum EVSYS_CHMUX_enum +{ + EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ + EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ + EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ + EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ + EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ + EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ + EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ + EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ + EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ + EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ + EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ + EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ + EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ + EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ + EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ + EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ + EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ + EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ + EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ + EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ + EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ + EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ + EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ + EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ + EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ + EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ + EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ + EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ + EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ + EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ + EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ + EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ + EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ + EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ + EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ + EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ + EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ + EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ + EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ + EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ + EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ + EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ + EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ + EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ + EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ + EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ + EVSYS_CHMUX_XCL_UNF0_gc = (0xB0<<0), /* XCL BTC0 underflow */ + EVSYS_CHMUX_XCL_UNF1_gc = (0xB1<<0), /* XCL BTC1 underflow */ + EVSYS_CHMUX_XCL_CC0_gc = (0xB2<<0), /* XCL BTC0 capture or compare */ + EVSYS_CHMUX_XCL_CC1_gc = (0xB3<<0), /* XCL BTC0 capture or compare */ + EVSYS_CHMUX_XCL_PEC0_gc = (0xB4<<0), /* XCL PEC0 restart */ + EVSYS_CHMUX_XCL_PEC1_gc = (0xB5<<0), /* XCL PEC1 restart */ + EVSYS_CHMUX_XCL_LUT0_gc = (0xB6<<0), /* XCL LUT0 output */ + EVSYS_CHMUX_XCL_LUT1_gc = (0xB7<<0), /* XCL LUT1 output */ + EVSYS_CHMUX_TCC4_OVF_gc = (0xC0<<0), /* Timer/Counter C4 Overflow */ + EVSYS_CHMUX_TCC4_ERR_gc = (0xC1<<0), /* Timer/Counter C4 Error */ + EVSYS_CHMUX_TCC4_CCA_gc = (0xC4<<0), /* Timer/Counter C4 Compare or Capture A */ + EVSYS_CHMUX_TCC4_CCB_gc = (0xC5<<0), /* Timer/Counter C4 Compare or Capture B */ + EVSYS_CHMUX_TCC4_CCC_gc = (0xC6<<0), /* Timer/Counter C4 Compare or Capture C */ + EVSYS_CHMUX_TCC4_CCD_gc = (0xC7<<0), /* Timer/Counter C4 Compare or Capture D */ + EVSYS_CHMUX_TCC5_OVF_gc = (0xC8<<0), /* Timer/Counter C5 Overflow */ + EVSYS_CHMUX_TCC5_ERR_gc = (0xC9<<0), /* Timer/Counter C5 Error */ + EVSYS_CHMUX_TCC5_CCA_gc = (0xCC<<0), /* Timer/Counter C5 Compare or Capture A */ + EVSYS_CHMUX_TCC5_CCB_gc = (0xCD<<0), /* Timer/Counter C5 Compare or Capture B */ + EVSYS_CHMUX_TCD5_OVF_gc = (0xD8<<0), /* Timer/Counter D5 Overflow */ + EVSYS_CHMUX_TCD5_ERR_gc = (0xD9<<0), /* Timer/Counter D5 Error */ + EVSYS_CHMUX_TCD5_CCA_gc = (0xDC<<0), /* Timer/Counter D5 Compare or Capture A */ + EVSYS_CHMUX_TCD5_CCB_gc = (0xDD<<0), /* Timer/Counter D5 Compare or Capture B */ +} EVSYS_CHMUX_t; + +/* Quadrature Decoder Index Recognition Mode */ +typedef enum EVSYS_QDIRM_enum +{ + EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ + EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ + EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ + EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ +} EVSYS_QDIRM_t; + +/* Digital filter coefficient */ +typedef enum EVSYS_DIGFILT_enum +{ + EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ + EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ + EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ + EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ + EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ + EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ + EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ + EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ +} EVSYS_DIGFILT_t; + +/* Prescaler Filter */ +typedef enum EVSYS_PRESCFILT_enum +{ + EVSYS_PRESCFILT_CH04_gc = (0x01<<4), /* Enable prescaler filter for either channel 0 or 4 */ + EVSYS_PRESCFILT_CH15_gc = (0x02<<4), /* Enable prescaler filter for either channel 1 or 5 */ + EVSYS_PRESCFILT_CH26_gc = (0x04<<4), /* Enable prescaler filter for either channel 2 or 6 */ + EVSYS_PRESCFILT_CH37_gc = (0x08<<4), /* Enable prescaler filter for either channel 3 or 7 */ +} EVSYS_PRESCFILT_t; + +/* Prescaler */ +typedef enum EVSYS_PRESCALER_enum +{ + EVSYS_PRESCALER_CLKPER_8_gc = (0x00<<0), /* CLKPER, divide by 8 */ + EVSYS_PRESCALER_CLKPER_64_gc = (0x01<<0), /* CLKPER, divide by 64 */ + EVSYS_PRESCALER_CLKPER_512_gc = (0x02<<0), /* CLKPER, divide by 512 */ + EVSYS_PRESCALER_CLKPER_4096_gc = (0x03<<0), /* CLKPER, divide by 4096 */ + EVSYS_PRESCALER_CLKPER_32768_gc = (0x04<<0), /* CLKPER, divide by 32768 */ +} EVSYS_PRESCALER_t; + + +/* +-------------------------------------------------------------------------- +NVM - Non Volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Non-volatile Memory Controller */ +typedef struct NVM_struct +{ + register8_t ADDR0; /* Address Register 0 */ + register8_t ADDR1; /* Address Register 1 */ + register8_t ADDR2; /* Address Register 2 */ + register8_t reserved_0x03; + register8_t DATA0; /* Data Register 0 */ + register8_t DATA1; /* Data Register 1 */ + register8_t DATA2; /* Data Register 2 */ + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t CMD; /* Command */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t reserved_0x0E; + register8_t STATUS; /* Status */ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ +} NVM_t; + +/* NVM Command */ +typedef enum NVM_CMD_enum +{ + NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ + NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ + NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ + NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ + NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ + NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ + NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ + NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ + NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ + NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ + NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ + NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ + NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ + NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ + NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ + NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ + NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ + NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ + NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ + NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ + NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ + NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ + NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ + NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ + NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ + NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ + NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ + NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ + NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ + NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ + NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ + NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ +} NVM_CMD_t; + +/* SPM ready interrupt level */ +typedef enum NVM_SPMLVL_enum +{ + NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ + NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ + NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ + NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ +} NVM_SPMLVL_t; + +/* EEPROM ready interrupt level */ +typedef enum NVM_EELVL_enum +{ + NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ + NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ + NVM_EELVL_HI_gc = (0x03<<0), /* High level */ +} NVM_EELVL_t; + +/* Boot lock bits - boot setcion */ +typedef enum NVM_BLBB_enum +{ + NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ + NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ + NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ + NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ +} NVM_BLBB_t; + +/* Boot lock bits - application section */ +typedef enum NVM_BLBA_enum +{ + NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ + NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ + NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ + NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ +} NVM_BLBA_t; + +/* Boot lock bits - application table section */ +typedef enum NVM_BLBAT_enum +{ + NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ + NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ + NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ + NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ +} NVM_BLBAT_t; + +/* Lock bits */ +typedef enum NVM_LB_enum +{ + NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ + NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ + NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ +} NVM_LB_t; + + +/* +-------------------------------------------------------------------------- +ADC - Analog/Digital Converter +-------------------------------------------------------------------------- +*/ + +/* ADC Channel */ +typedef struct ADC_CH_struct +{ + register8_t CTRL; /* Control Register */ + register8_t MUXCTRL; /* MUX Control */ + register8_t INTCTRL; /* Channel Interrupt Control Register */ + register8_t INTFLAGS; /* Interrupt Flags */ + _WORDREGISTER(RES); /* Channel Result */ + register8_t SCAN; /* Input Channel Scan */ + register8_t CORRCTRL; /* Correction Control Register */ + register8_t OFFSETCORR0; /* Offset Correction Register 0 */ + register8_t OFFSETCORR1; /* Offset Correction Register 1 */ + register8_t GAINCORR0; /* Gain Correction Register 0 */ + register8_t GAINCORR1; /* Gain Correction Register 1 */ + register8_t AVGCTRL; /* Average Control Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; +} ADC_CH_t; + + +/* Analog-to-Digital Converter */ +typedef struct ADC_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t REFCTRL; /* Reference Control */ + register8_t EVCTRL; /* Event Control */ + register8_t PRESCALER; /* Clock Prescaler */ + register8_t reserved_0x05; + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary Register */ + register8_t SAMPCTRL; /* ADC Sampling Time Control Register */ + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + _WORDREGISTER(CAL); /* Calibration Value */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + _WORDREGISTER(CH0RES); /* Channel 0 Result */ + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + _WORDREGISTER(CMP); /* Compare Value */ + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + ADC_CH_t CH0; /* ADC Channel 0 */ +} ADC_t; + +/* Current Limitation */ +typedef enum ADC_CURRLIMIT_enum +{ + ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ + ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 250ksps max sampling rate */ + ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ + ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 50ksps max sampling rate */ +} ADC_CURRLIMIT_t; + +/* Conversion result resolution */ +typedef enum ADC_RESOLUTION_enum +{ + ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ + ADC_RESOLUTION_MT12BIT_gc = (0x01<<1), /* More than 12-bit (oversapling) right-adjusted result */ + ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ + ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ +} ADC_RESOLUTION_t; + +/* Voltage reference selection */ +typedef enum ADC_REFSEL_enum +{ + ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ + ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ + ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ + ADC_REFSEL_AREFD_gc = (0x03<<4), /* External reference on PORT D */ + ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ +} ADC_REFSEL_t; + +/* Event channel input selection */ +typedef enum ADC_EVSEL_enum +{ + ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */ + ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */ + ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */ + ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */ + ADC_EVSEL_4_gc = (0x04<<3), /* Event Channel 4 */ + ADC_EVSEL_5_gc = (0x05<<3), /* Event Channel 5 */ + ADC_EVSEL_6_gc = (0x06<<3), /* Event Channel 6 */ + ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ +} ADC_EVSEL_t; + +/* Event action selection */ +typedef enum ADC_EVACT_enum +{ + ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ + ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel conversion */ + ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ +} ADC_EVACT_t; + +/* Clock prescaler */ +typedef enum ADC_PRESCALER_enum +{ + ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ + ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ + ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ + ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ + ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ + ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ + ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ + ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ +} ADC_PRESCALER_t; + +/* Gain factor */ +typedef enum ADC_CH_GAIN_enum +{ + ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ + ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ + ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ + ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ + ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ + ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ + ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ + ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ +} ADC_CH_GAIN_t; + +/* Input mode */ +typedef enum ADC_CH_INPUTMODE_enum +{ + ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ + ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ + ADC_CH_INPUTMODE_DIFFWGAINL_gc = (0x02<<0), /* Differential input, gain with 4 LSB pins selection */ + ADC_CH_INPUTMODE_DIFFWGAINH_gc = (0x03<<0), /* Differential input, gain with 4 MSB pins selection */ +} ADC_CH_INPUTMODE_t; + +/* Positive input multiplexer selection */ +typedef enum ADC_CH_MUXPOS_enum +{ + ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ + ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ + ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ + ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ + ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ + ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ + ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ + ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ + ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ + ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ + ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ + ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ + ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ + ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ + ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ + ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ +} ADC_CH_MUXPOS_t; + +/* Internal input multiplexer selections */ +typedef enum ADC_CH_MUXINT_enum +{ + ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ + ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ + ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 Scaled VCC */ + ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC Output */ +} ADC_CH_MUXINT_t; + +/* Negative input multiplexer selection when gain on 4 LSB pins */ +typedef enum ADC_CH_MUXNEGL_enum +{ + ADC_CH_MUXNEGL_PIN0_gc = (0x00<<0), /* Input pin 0 */ + ADC_CH_MUXNEGL_PIN1_gc = (0x01<<0), /* Input pin 1 */ + ADC_CH_MUXNEGL_PIN2_gc = (0x02<<0), /* Input pin 2 */ + ADC_CH_MUXNEGL_PIN3_gc = (0x03<<0), /* Input pin 3 */ + ADC_CH_MUXNEGL_GND_gc = (0x05<<0), /* PAD ground */ + ADC_CH_MUXNEGL_INTGND_gc = (0x07<<0), /* Internal ground */ +} ADC_CH_MUXNEGL_t; + +/* Negative input multiplexer selection when gain on 4 MSB pins */ +typedef enum ADC_CH_MUXNEGH_enum +{ + ADC_CH_MUXNEGH_PIN4_gc = (0x00<<0), /* Input pin 4 */ + ADC_CH_MUXNEGH_PIN5_gc = (0x01<<0), /* Input pin 5 */ + ADC_CH_MUXNEGH_PIN6_gc = (0x02<<0), /* Input pin 6 */ + ADC_CH_MUXNEGH_PIN7_gc = (0x03<<0), /* Input pin 7 */ + ADC_CH_MUXNEGH_GND_gc = (0x05<<0), /* PAD ground */ +} ADC_CH_MUXNEGH_t; + +/* Negative input multiplexer selection */ +typedef enum ADC_CH_MUXNEG_enum +{ + ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ +} ADC_CH_MUXNEG_t; + +/* Interupt mode */ +typedef enum ADC_CH_INTMODE_enum +{ + ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ + ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ + ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ +} ADC_CH_INTMODE_t; + +/* Interrupt level */ +typedef enum ADC_CH_INTLVL_enum +{ + ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ + ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ + ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ +} ADC_CH_INTLVL_t; + +/* Averaged Number of Samples */ +typedef enum ADC_SAMPNUM_enum +{ + ADC_SAMPNUM_1X_gc = (0x00<<0), /* 1 Sample */ + ADC_SAMPNUM_2X_gc = (0x01<<0), /* 2 Samples */ + ADC_SAMPNUM_4X_gc = (0x02<<0), /* 4 Samples */ + ADC_SAMPNUM_8X_gc = (0x03<<0), /* 8 Samples */ + ADC_SAMPNUM_16X_gc = (0x04<<0), /* 16 Samples */ + ADC_SAMPNUM_32X_gc = (0x05<<0), /* 32 Samples */ + ADC_SAMPNUM_64X_gc = (0x06<<0), /* 64 Samples */ + ADC_SAMPNUM_128X_gc = (0x07<<0), /* 128 Samples */ + ADC_SAMPNUM_256X_gc = (0x08<<0), /* 256 Samples */ + ADC_SAMPNUM_512X_gc = (0x09<<0), /* 512 Samples */ + ADC_SAMPNUM_1024X_gc = (0x0A<<0), /* 1024 Samples */ +} ADC_SAMPNUM_t; + + +/* +-------------------------------------------------------------------------- +DAC - Digital/Analog Converter +-------------------------------------------------------------------------- +*/ + +/* Digital-to-Analog Converter */ +typedef struct DAC_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t EVCTRL; /* Event Input Control */ + register8_t reserved_0x04; + register8_t STATUS; /* Status */ + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t CH0GAINCAL; /* Gain Calibration */ + register8_t CH0OFFSETCAL; /* Offset Calibration */ + register8_t CH1GAINCAL; /* Gain Calibration */ + register8_t CH1OFFSETCAL; /* Offset Calibration */ + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + _WORDREGISTER(CH0DATA); /* Channel 0 Data */ + _WORDREGISTER(CH1DATA); /* Channel 1 Data */ +} DAC_t; + +/* Output channel selection */ +typedef enum DAC_CHSEL_enum +{ + DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel 0 only) */ + DAC_CHSEL_SINGLE1_gc = (0x01<<5), /* Single channel operation (Channel 1 only) */ + DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (Channel 0 and channel 1) */ +} DAC_CHSEL_t; + +/* Reference voltage selection */ +typedef enum DAC_REFSEL_enum +{ + DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ + DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ + DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ + DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ +} DAC_REFSEL_t; + +/* Event channel selection */ +typedef enum DAC_EVSEL_enum +{ + DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ + DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ + DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ + DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ + DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ + DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ + DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ + DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ +} DAC_EVSEL_t; + + +/* +-------------------------------------------------------------------------- +AC - Analog Comparator +-------------------------------------------------------------------------- +*/ + +/* Analog Comparator */ +typedef struct AC_struct +{ + register8_t AC0CTRL; /* Analog Comparator 0 Control */ + register8_t AC1CTRL; /* Analog Comparator 1 Control */ + register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ + register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t WINCTRL; /* Window Mode Control */ + register8_t STATUS; /* Status */ + register8_t CURRCTRL; /* Current Source Control Register */ + register8_t CURRCALIB; /* Current Source Calibration Register */ +} AC_t; + +/* Interrupt mode */ +typedef enum AC_INTMODE_enum +{ + AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ + AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ + AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ +} AC_INTMODE_t; + +/* Interrupt level */ +typedef enum AC_INTLVL_enum +{ + AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ + AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ + AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ + AC_INTLVL_HI_gc = (0x03<<4), /* High level */ +} AC_INTLVL_t; + +/* Hysteresis mode selection */ +typedef enum AC_HYSMODE_enum +{ + AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ + AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ + AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ +} AC_HYSMODE_t; + +/* Positive input multiplexer selection */ +typedef enum AC_MUXPOS_enum +{ + AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ + AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ + AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ + AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ + AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ + AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ + AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ + AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ +} AC_MUXPOS_t; + +/* Negative input multiplexer selection */ +typedef enum AC_MUXNEG_enum +{ + AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ + AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ + AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ + AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ + AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ + AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ + AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ + AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ +} AC_MUXNEG_t; + +/* Windows interrupt mode */ +typedef enum AC_WINTMODE_enum +{ + AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ + AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ + AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ + AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ +} AC_WINTMODE_t; + +/* Window interrupt level */ +typedef enum AC_WINTLVL_enum +{ + AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ + AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ + AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ +} AC_WINTLVL_t; + +/* Window mode state */ +typedef enum AC_WSTATE_enum +{ + AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ + AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ + AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ +} AC_WSTATE_t; + + +/* +-------------------------------------------------------------------------- +RTC - Real-Time Clounter +-------------------------------------------------------------------------- +*/ + +/* Real-Time Counter */ +typedef struct RTC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary register */ + register8_t reserved_0x05; + register8_t CALIB; /* Calibration Register */ + register8_t reserved_0x07; + _WORDREGISTER(CNT); /* Count Register */ + _WORDREGISTER(PER); /* Period Register */ + _WORDREGISTER(COMP); /* Compare Register */ +} RTC_t; + +/* Prescaler Factor */ +typedef enum RTC_PRESCALER_enum +{ + RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ + RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ + RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ + RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ + RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ + RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ + RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ + RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ +} RTC_PRESCALER_t; + +/* Compare Interrupt level */ +typedef enum RTC_COMPINTLVL_enum +{ + RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ + RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ +} RTC_COMPINTLVL_t; + +/* Overflow Interrupt level */ +typedef enum RTC_OVFINTLVL_enum +{ + RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} RTC_OVFINTLVL_t; + + +/* +-------------------------------------------------------------------------- +XCL - XMEGA Custom Logic +-------------------------------------------------------------------------- +*/ + +/* XMEGA Custom Logic */ +typedef struct XCL_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t CTRLF; /* Control Register F */ + register8_t CTRLG; /* Control Register G */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t PLC; /* Peripheral Lenght Control Register */ + register8_t CNTL; /* Counter Register Low */ + register8_t CNTH; /* Counter Register High */ + register8_t CMPL; /* Compare Register Low */ + register8_t CMPH; /* Compare Register High */ + register8_t PERCAPTL; /* Period or Capture Register Low */ + register8_t PERCAPTH; /* Period or Capture Register High */ +} XCL_t; + +/* LUT0 Output Enable */ +typedef enum XCL_LUTOUTEN_enum +{ + XCL_LUTOUTEN_DISABLE_gc = (0x00<<6), /* LUT0 output disabled */ + XCL_LUTOUTEN_PIN0_gc = (0x01<<6), /* LUT0 Output to pin 0 */ + XCL_LUTOUTEN_PIN4_gc = (0x02<<6), /* LUT0 Output to pin 4 */ +} XCL_LUTOUTEN_t; + +/* Port Selection */ +typedef enum XCL_PORTSEL_enum +{ + XCL_PORTSEL_PC_gc = (0x00<<4), /* Port C for LUT or USARTC0 for PEC */ + XCL_PORTSEL_PD_gc = (0x01<<4), /* Port D for LUT or USARTD0 for PEC */ +} XCL_PORTSEL_t; + +/* LUT Configuration */ +typedef enum XCL_LUTCONF_enum +{ + XCL_LUTCONF_2LUT2IN_gc = (0x00<<0), /* 2-Input two LUT */ + XCL_LUTCONF_2LUT1IN_gc = (0x01<<0), /* Two LUT with duplicated input */ + XCL_LUTCONF_2LUT3IN_gc = (0x02<<0), /* Two LUT with one common input */ + XCL_LUTCONF_1LUT3IN_gc = (0x03<<0), /* 3-Input LUT */ + XCL_LUTCONF_MUX_gc = (0x04<<0), /* One LUT Mux */ + XCL_LUTCONF_DLATCH_gc = (0x05<<0), /* One D-Latch LUT */ + XCL_LUTCONF_RSLATCH_gc = (0x06<<0), /* One RS-Latch LUT */ + XCL_LUTCONF_DFF_gc = (0x07<<0), /* One DFF LUT */ +} XCL_LUTCONF_t; + +/* Input Selection */ +typedef enum XCL_INSEL_enum +{ + XCL_INSEL_EVSYS_gc = (0x00<<6), /* Event system selected as source */ + XCL_INSEL_XCL_gc = (0x01<<6), /* XCL selected as source */ + XCL_INSEL_PINL_gc = (0x02<<6), /* LSB port pin selected as source */ + XCL_INSEL_PINH_gc = (0x03<<6), /* MSB port pin selected as source */ +} XCL_INSEL_t; + +/* Delay Configuration on LUT */ +typedef enum XCL_DLYCONF_enum +{ + XCL_DLYCONF_DISABLE_gc = (0x00<<2), /* Delay element disabled */ + XCL_DLYCONF_IN_gc = (0x01<<2), /* Delay enabled on LUT input */ + XCL_DLYCONF_OUT_gc = (0x02<<2), /* Delay enabled on LUT output */ +} XCL_DLYCONF_t; + +/* Delay Selection */ +typedef enum XCL_DLYSEL_enum +{ + XCL_DLYSEL_DLY11_gc = (0x00<<4), /* One cycle delay for each LUT1 and LUT0 */ + XCL_DLYSEL_DLY12_gc = (0x01<<4), /* One cycle delay for LUT1 and two cycles for LUT0 */ + XCL_DLYSEL_DLY21_gc = (0x02<<4), /* Two cycles delay for LUT1 and one cycle for LUT0 */ + XCL_DLYSEL_DLY22_gc = (0x03<<4), /* Two cycle delays for each LUT1 and LUT0 */ +} XCL_DLYSEL_t; + +/* Clock Selection */ +typedef enum XCL_CLKSEL_enum +{ + XCL_CLKSEL_OFF_gc = (0x00<<0), /* OFF */ + XCL_CLKSEL_DIV1_gc = (0x01<<0), /* Prescaler clk */ + XCL_CLKSEL_DIV2_gc = (0x02<<0), /* Prescaler clk/2 */ + XCL_CLKSEL_DIV4_gc = (0x03<<0), /* Prescaler clk/4 */ + XCL_CLKSEL_DIV8_gc = (0x04<<0), /* Prescaler clk/8 */ + XCL_CLKSEL_DIV64_gc = (0x05<<0), /* Prescaler clk/64 */ + XCL_CLKSEL_DIV256_gc = (0x06<<0), /* Prescaler clk/256 */ + XCL_CLKSEL_DIV1024_gc = (0x07<<0), /* Prescaler clk/1024 */ + XCL_CLKSEL_EVCH0_gc = (0x08<<0), /* Event channel 0 */ + XCL_CLKSEL_EVCH1_gc = (0x09<<0), /* Event channel 1 */ + XCL_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event channel 2 */ + XCL_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event channel 3 */ + XCL_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event channel 4 */ + XCL_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event channel 5 */ + XCL_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event channel 6 */ + XCL_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event channel 7 */ +} XCL_CLKSEL_t; + +/* Timer/Counter Command Selection */ +typedef enum XCL_CMDSEL_enum +{ + XCL_CMDSEL_NONE_gc = (0x00<<7), /* None */ + XCL_CMDSEL_RESTART_gc = (0x01<<7), /* Force restart */ +} XCL_CMDSEL_t; + +/* Timer/Counter Selection */ +typedef enum XCL_TCSEL_enum +{ + XCL_TCSEL_TC16_gc = (0x00<<4), /* 16-bit timer/counter */ + XCL_TCSEL_BTC0_gc = (0x01<<4), /* One 8-bit timer/counter */ + XCL_TCSEL_BTC01_gc = (0x02<<4), /* Two 8-bit timer/counters */ + XCL_TCSEL_BTC0PEC1_gc = (0x03<<4), /* One 8-bit timer/counter and one 8-bit peripheral counter */ + XCL_TCSEL_PEC0BTC1_gc = (0x04<<4), /* One 8-bit timer/counter and one 8-bit peripheral counter */ + XCL_TCSEL_PEC01_gc = (0x05<<4), /* Two 8-bit peripheral counters */ + XCL_TCSEL_BTC0PEC2_gc = (0x06<<4), /* One 8-bit timer/counter and two 4-bit peripheral counters */ +} XCL_TCSEL_t; + +/* Timer/Counter Mode */ +typedef enum XCL_TCMODE_enum +{ + XCL_TCMODE_NORMAL_gc = (0x00<<0), /* Normal mode with compare/period */ + XCL_TCMODE_CAPT_gc = (0x01<<0), /* Capture mode */ + XCL_TCMODE_PWM_gc = (0x02<<0), /* Single Slope PWM */ +} XCL_TCMODE_t; + +/* Compare Output Value Timer */ +typedef enum XCL_CMPEN_enum +{ + XCL_CMPEN_CLEAR_gc = (0x00<<5), /* Clear WG Output */ + XCL_CMPEN_SET_gc = (0x01<<5), /* Set WG Output */ +} XCL_CMPEN_t; + +/* Command Enable */ +typedef enum XCL_CMDEN_enum +{ + XCL_CMDEN_DISABLE_gc = (0x00<<6), /* Command Ignored */ + XCL_CMDEN_CMD0_gc = (0x01<<6), /* Command valid for timer/counter 0 */ + XCL_CMDEN_CMD1_gc = (0x02<<6), /* Command valid for timer/counter 1 */ + XCL_CMDEN_CMD01_gc = (0x03<<6), /* Command valid for both timer/counter 0 and 1 */ +} XCL_CMDEN_t; + +/* Timer/Counter Event Source Selection */ +typedef enum XCL_EVSRC_enum +{ + XCL_EVSRC_EVCH0_gc = (0x00<<0), /* Event channel 0 */ + XCL_EVSRC_EVCH1_gc = (0x01<<0), /* Event channel 1 */ + XCL_EVSRC_EVCH2_gc = (0x02<<0), /* Event channel 2 */ + XCL_EVSRC_EVCH3_gc = (0x03<<0), /* Event channel 3 */ + XCL_EVSRC_EVCH4_gc = (0x04<<0), /* Event channel 4 */ + XCL_EVSRC_EVCH5_gc = (0x05<<0), /* Event channel 5 */ + XCL_EVSRC_EVCH6_gc = (0x06<<0), /* Event channel 6 */ + XCL_EVSRC_EVCH7_gc = (0x07<<0), /* Event channel 7 */ +} XCL_EVSRC_t; + +/* Timer/Counter Event Action Selection */ +typedef enum XCL_EVACT_enum +{ + XCL_EVACT_INPUT_gc = (0x00<<5), /* Input Capture */ + XCL_EVACT_FREQ_gc = (0x01<<5), /* Frequency Capture */ + XCL_EVACT_PW_gc = (0x02<<5), /* Pulse Width Capture */ + XCL_EVACT_RESTART_gc = (0x03<<5), /* Restart timer/counter */ +} XCL_EVACT_t; + +/* Underflow Interrupt level */ +typedef enum XCL_UNF_INTLVL_enum +{ + XCL_UNF_INTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + XCL_UNF_INTLVL_LO_gc = (0x01<<2), /* Low Level */ + XCL_UNF_INTLVL_MED_gc = (0x02<<2), /* Medium Level */ + XCL_UNF_INTLVL_HI_gc = (0x03<<2), /* High Level */ +} XCL_UNF_INTLVL_t; + +/* Compare/Capture Interrupt level */ +typedef enum XCL_CC_INTLVL_enum +{ + XCL_CC_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + XCL_CC_INTLVL_LO_gc = (0x01<<0), /* Low Level */ + XCL_CC_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ + XCL_CC_INTLVL_HI_gc = (0x03<<0), /* High Level */ +} XCL_CC_INTLVL_t; + + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* */ +typedef struct TWI_MASTER_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t STATUS; /* Status Register */ + register8_t BAUD; /* Baurd Rate Control Register */ + register8_t ADDR; /* Address Register */ + register8_t DATA; /* Data Register */ +} TWI_MASTER_t; + + +/* */ +typedef struct TWI_SLAVE_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t STATUS; /* Status Register */ + register8_t ADDR; /* Address Register */ + register8_t DATA; /* Data Register */ + register8_t ADDRMASK; /* Address Mask Register */ +} TWI_SLAVE_t; + + +/* */ +typedef struct TWI_TIMEOUT_struct +{ + register8_t TOS; /* Timeout Status Register */ + register8_t TOCONF; /* Timeout Configuration Register */ +} TWI_TIMEOUT_t; + + +/* Two-Wire Interface */ +typedef struct TWI_struct +{ + register8_t CTRL; /* TWI Common Control Register */ + TWI_MASTER_t MASTER; /* TWI master module */ + TWI_SLAVE_t SLAVE; /* TWI slave module */ + TWI_TIMEOUT_t TIMEOUT; /* TWI SMBUS timeout module */ +} TWI_t; + +/* SDA Hold Time */ +typedef enum TWI_SDAHOLD_enum +{ + TWI_SDAHOLD_OFF_gc = (0x00<<4), /* SDA Hold Time off */ + TWI_SDAHOLD_50NS_gc = (0x01<<4), /* SDA Hold Time 50 ns */ + TWI_SDAHOLD_300NS_gc = (0x02<<4), /* SDA Hold Time 300 ns */ + TWI_SDAHOLD_400NS_gc = (0x03<<4), /* SDA Hold Time 400 ns */ +} TWI_SDAHOLD_t; + +/* Master Interrupt Level */ +typedef enum TWI_MASTER_INTLVL_enum +{ + TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ + TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ +} TWI_MASTER_INTLVL_t; + +/* Inactive Timeout */ +typedef enum TWI_MASTER_TIMEOUT_enum +{ + TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ + TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ + TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ + TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +} TWI_MASTER_TIMEOUT_t; + +/* Master Command */ +typedef enum TWI_MASTER_CMD_enum +{ + TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ + TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ + TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +} TWI_MASTER_CMD_t; + +/* Master Bus State */ +typedef enum TWI_MASTER_BUSSTATE_enum +{ + TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ + TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ + TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ + TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +} TWI_MASTER_BUSSTATE_t; + +/* Slave Interrupt Level */ +typedef enum TWI_SLAVE_INTLVL_enum +{ + TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ + TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ +} TWI_SLAVE_INTLVL_t; + +/* Slave Command */ +typedef enum TWI_SLAVE_CMD_enum +{ + TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ + TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +} TWI_SLAVE_CMD_t; + +/* Master Timeout */ +typedef enum TWI_MASTER_TTIMEOUT_enum +{ + TWI_MASTER_TTIMEOUT_25MS_gc = (0x00<<0), /* 25 Milliseconds */ + TWI_MASTER_TTIMEOUT_24MS_gc = (0x01<<0), /* 24 Milliseconds */ + TWI_MASTER_TTIMEOUT_23MS_gc = (0x02<<0), /* 23 Milliseconds */ + TWI_MASTER_TTIMEOUT_22MS_gc = (0x03<<0), /* 22 Milliseconds */ + TWI_MASTER_TTIMEOUT_26MS_gc = (0x04<<0), /* 26 Milliseconds */ + TWI_MASTER_TTIMEOUT_27MS_gc = (0x05<<0), /* 27 Milliseconds */ + TWI_MASTER_TTIMEOUT_28MS_gc = (0x06<<0), /* 28 Milliseconds */ + TWI_MASTER_TTIMEOUT_29MS_gc = (0x07<<0), /* 29 Milliseconds */ +} TWI_MASTER_TTIMEOUT_t; + +/* Slave Ttimeout */ +typedef enum TWI_SLAVE_TTIMEOUT_enum +{ + TWI_SLAVE_TTIMEOUT_25MS_gc = (0x00<<5), /* 25 Milliseconds */ + TWI_SLAVE_TTIMEOUT_24MS_gc = (0x01<<5), /* 24 Milliseconds */ + TWI_SLAVE_TTIMEOUT_23MS_gc = (0x02<<5), /* 23 Milliseconds */ + TWI_SLAVE_TTIMEOUT_22MS_gc = (0x03<<5), /* 22 Milliseconds */ + TWI_SLAVE_TTIMEOUT_26MS_gc = (0x04<<5), /* 26 Milliseconds */ + TWI_SLAVE_TTIMEOUT_27MS_gc = (0x05<<5), /* 27 Milliseconds */ + TWI_SLAVE_TTIMEOUT_28MS_gc = (0x06<<5), /* 28 Milliseconds */ + TWI_SLAVE_TTIMEOUT_29MS_gc = (0x07<<5), /* 29 Milliseconds */ +} TWI_SLAVE_TTIMEOUT_t; + +/* Master/Slave Extend Timeout */ +typedef enum TWI_MASTER_TMSEXT_enum +{ + TWI_MASTER_TMSEXT_10MS25MS_gc = (0x00<<3), /* Tmext 10ms Tsext 25ms */ + TWI_MASTER_TMSEXT_9MS24MS_gc = (0x01<<3), /* Tmext 9ms Tsext 24ms */ + TWI_MASTER_TMSEXT_11MS26MS_gc = (0x02<<3), /* Tmext 11ms Tsext 26ms */ + TWI_MASTER_TMSEXT_12MS27MS_gc = (0x03<<3), /* Tmext 12ms Tsext 27ms */ +} TWI_MASTER_TMSEXT_t; + + +/* +-------------------------------------------------------------------------- +PORT - Port Configuration +-------------------------------------------------------------------------- +*/ + +/* I/O Ports */ +typedef struct PORT_struct +{ + register8_t DIR; /* I/O Port Data Direction */ + register8_t DIRSET; /* I/O Port Data Direction Set */ + register8_t DIRCLR; /* I/O Port Data Direction Clear */ + register8_t DIRTGL; /* I/O Port Data Direction Toggle */ + register8_t OUT; /* I/O Port Output */ + register8_t OUTSET; /* I/O Port Output Set */ + register8_t OUTCLR; /* I/O Port Output Clear */ + register8_t OUTTGL; /* I/O Port Output Toggle */ + register8_t IN; /* I/O port Input */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INTMASK; /* Port Interrupt Mask */ + register8_t reserved_0x0B; + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t REMAP; /* Pin Remap Register */ + register8_t reserved_0x0F; + register8_t PIN0CTRL; /* Pin 0 Control Register */ + register8_t PIN1CTRL; /* Pin 1 Control Register */ + register8_t PIN2CTRL; /* Pin 2 Control Register */ + register8_t PIN3CTRL; /* Pin 3 Control Register */ + register8_t PIN4CTRL; /* Pin 4 Control Register */ + register8_t PIN5CTRL; /* Pin 5 Control Register */ + register8_t PIN6CTRL; /* Pin 6 Control Register */ + register8_t PIN7CTRL; /* Pin 7 Control Register */ +} PORT_t; + +/* Port Interrupt Level */ +typedef enum PORT_INTLVL_enum +{ + PORT_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + PORT_INTLVL_LO_gc = (0x01<<0), /* Low Level */ + PORT_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ + PORT_INTLVL_HI_gc = (0x03<<0), /* High Level */ +} PORT_INTLVL_t; + +/* Output/Pull Configuration */ +typedef enum PORT_OPC_enum +{ + PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ + PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ + PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ + PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ + PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ + PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ + PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ + PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ +} PORT_OPC_t; + +/* Input/Sense Configuration */ +typedef enum PORT_ISC_enum +{ + PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ + PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ + PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ + PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ + PORT_ISC_FORCE_ENABLE_gc = (0x06<<0), /* Digital Input Buffer Forced Enable */ + PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ +} PORT_ISC_t; + + +/* +-------------------------------------------------------------------------- +TC - 16-bit Timer/Counter With PWM +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter 4 */ +typedef struct TC4_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t CTRLF; /* Control Register F */ + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G Set */ + register8_t CTRLHCLR; /* Control Register H Clear */ + register8_t CTRLHSET; /* Control Register H Set */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CCA); /* Compare or Capture A */ + _WORDREGISTER(CCB); /* Compare or Capture B */ + _WORDREGISTER(CCC); /* Compare or Capture C */ + _WORDREGISTER(CCD); /* Compare or Capture D */ + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ + _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ + _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ + _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ +} TC4_t; + + +/* 16-bit Timer/Counter 5 */ +typedef struct TC5_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t CTRLF; /* Control Register F */ + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G Set */ + register8_t CTRLHCLR; /* Control Register H Clear */ + register8_t CTRLHSET; /* Control Register H Set */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CCA); /* Compare or Capture A */ + _WORDREGISTER(CCB); /* Compare or Capture B */ + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t reserved_0x2E; + register8_t reserved_0x2F; + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ + _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ + register8_t reserved_0x3C; + register8_t reserved_0x3D; + register8_t reserved_0x3E; + register8_t reserved_0x3F; +} TC5_t; + +/* Clock Selection */ +typedef enum TC45_CLKSEL_enum +{ + TC45_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ + TC45_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ + TC45_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ + TC45_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ + TC45_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ + TC45_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ + TC45_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ + TC45_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ + TC45_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ + TC45_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ + TC45_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC45_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ + TC45_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ + TC45_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ + TC45_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ + TC45_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ +} TC45_CLKSEL_t; + +/* Byte Mode */ +typedef enum TC45_BYTEM_enum +{ + TC45_BYTEM_NORMAL_gc = (0x00<<6), /* 16-bit mode */ + TC45_BYTEM_BYTEMODE_gc = (0x01<<6), /* Timer/Counter Operating in Byte Mode Only */ +} TC45_BYTEM_t; + +/* Circular Enable Mode */ +typedef enum TC45_CIRCEN_enum +{ + TC45_CIRCEN_DISABLE_gc = (0x00<<4), /* Circular Buffer Disabled */ + TC45_CIRCEN_PER_gc = (0x01<<4), /* Circular Buffer Enabled on PER/PERBUF */ + TC45_CIRCEN_CCA_gc = (0x02<<4), /* Circular Buffer Enabled on CCA/CCABUF */ + TC45_CIRCEN_BOTH_gc = (0x03<<4), /* Circular Buffer Enabled on All Buffered Registers */ +} TC45_CIRCEN_t; + +/* Waveform Generation Mode */ +typedef enum TC45_WGMODE_enum +{ + TC45_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ + TC45_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ + TC45_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ + TC45_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ + TC45_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Both */ + TC45_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ +} TC45_WGMODE_t; + +/* Event Action */ +typedef enum TC45_EVACT_enum +{ + TC45_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ + TC45_EVACT_FMODE1_gc = (0x01<<5), /* Fault Mode 1 capture */ + TC45_EVACT_FMODE2_gc = (0x02<<5), /* Fault Mode 2 capture */ + TC45_EVACT_UPDOWN_gc = (0x03<<5), /* Up/down count */ + TC45_EVACT_QDEC_gc = (0x04<<5), /* Quadrature decode */ + TC45_EVACT_RESTART_gc = (0x05<<5), /* Restart */ + TC45_EVACT_PWF_gc = (0x06<<5), /* Pulse-width Capture */ +} TC45_EVACT_t; + +/* Event Selection */ +typedef enum TC45_EVSEL_enum +{ + TC45_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ + TC45_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ + TC45_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ + TC45_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC45_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ + TC45_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ + TC45_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ + TC45_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ + TC45_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ +} TC45_EVSEL_t; + +/* Compare or Capture Channel A Mode */ +typedef enum TC45_CCAMODE_enum +{ + TC45_CCAMODE_DISABLE_gc = (0x00<<0), /* Channel Disabled */ + TC45_CCAMODE_COMP_gc = (0x01<<0), /* Ouput Compare enabled */ + TC45_CCAMODE_CAPT_gc = (0x02<<0), /* Input Capture enabled */ + TC45_CCAMODE_BOTHCC_gc = (0x03<<0), /* Both Compare and Capture enabled */ +} TC45_CCAMODE_t; + +/* Compare or Capture Channel B Mode */ +typedef enum TC45_CCBMODE_enum +{ + TC45_CCBMODE_DISABLE_gc = (0x00<<2), /* Channel Disabled */ + TC45_CCBMODE_COMP_gc = (0x01<<2), /* Ouput Compare enabled */ + TC45_CCBMODE_CAPT_gc = (0x02<<2), /* Input Capture enabled */ + TC45_CCBMODE_BOTHCC_gc = (0x03<<2), /* Both Compare and Capture enabled */ +} TC45_CCBMODE_t; + +/* Compare or Capture Channel C Mode */ +typedef enum TC45_CCCMODE_enum +{ + TC45_CCCMODE_DISABLE_gc = (0x00<<4), /* Channel Disabled */ + TC45_CCCMODE_COMP_gc = (0x01<<4), /* Ouput Compare enabled */ + TC45_CCCMODE_CAPT_gc = (0x02<<4), /* Input Capture enabled */ + TC45_CCCMODE_BOTHCC_gc = (0x03<<4), /* Both Compare and Capture enabled */ +} TC45_CCCMODE_t; + +/* Compare or Capture Channel D Mode */ +typedef enum TC45_CCDMODE_enum +{ + TC45_CCDMODE_DISABLE_gc = (0x00<<6), /* Channel Disabled */ + TC45_CCDMODE_COMP_gc = (0x01<<6), /* Ouput Compare enabled */ + TC45_CCDMODE_CAPT_gc = (0x02<<6), /* Input Capture enabled */ + TC45_CCDMODE_BOTHCC_gc = (0x03<<6), /* Both Compare and Capture enabled */ +} TC45_CCDMODE_t; + +/* Compare or Capture Low Channel A Mode */ +typedef enum TC45_LCCAMODE_enum +{ + TC45_LCCAMODE_DISABLE_gc = (0x00<<0), /* Channel Disabled */ + TC45_LCCAMODE_COMP_gc = (0x01<<0), /* Ouput Compare enabled */ + TC45_LCCAMODE_CAPT_gc = (0x02<<0), /* Input Capture enabled */ + TC45_LCCAMODE_BOTHCC_gc = (0x03<<0), /* Both Compare and Capture enabled */ +} TC45_LCCAMODE_t; + +/* Compare or Capture Low Channel B Mode */ +typedef enum TC45_LCCBMODE_enum +{ + TC45_LCCBMODE_DISABLE_gc = (0x00<<2), /* Channel Disabled */ + TC45_LCCBMODE_COMP_gc = (0x01<<2), /* Ouput Compare enabled */ + TC45_LCCBMODE_CAPT_gc = (0x02<<2), /* Input Capture enabled */ + TC45_LCCBMODE_BOTHCC_gc = (0x03<<2), /* Both Compare and Capture enabled */ +} TC45_LCCBMODE_t; + +/* Compare or Capture Low Channel C Mode */ +typedef enum TC45_LCCCMODE_enum +{ + TC45_LCCCMODE_DISABLE_gc = (0x00<<4), /* Channel Disabled */ + TC45_LCCCMODE_COMP_gc = (0x01<<4), /* Ouput Compare enabled */ + TC45_LCCCMODE_CAPT_gc = (0x02<<4), /* Input Capture enabled */ + TC45_LCCCMODE_BOTHCC_gc = (0x03<<4), /* Both Compare and Capture enabled */ +} TC45_LCCCMODE_t; + +/* Compare or Capture Low Channel D Mode */ +typedef enum TC45_LCCDMODE_enum +{ + TC45_LCCDMODE_DISABLE_gc = (0x00<<6), /* Channel Disabled */ + TC45_LCCDMODE_COMP_gc = (0x01<<6), /* Ouput Compare enabled */ + TC45_LCCDMODE_CAPT_gc = (0x02<<6), /* Input Capture enabled */ + TC45_LCCDMODE_BOTHCC_gc = (0x03<<6), /* Both Compare and Capture enabled */ +} TC45_LCCDMODE_t; + +/* Compare or Capture High Channel A Mode */ +typedef enum TC45_HCCAMODE_enum +{ + TC45_HCCAMODE_DISABLE_gc = (0x00<<0), /* Channel Disabled */ + TC45_HCCAMODE_COMP_gc = (0x01<<0), /* Ouput Compare enabled */ + TC45_HCCAMODE_CAPT_gc = (0x02<<0), /* Input Capture enabled */ + TC45_HCCAMODE_BOTHCC_gc = (0x03<<0), /* Both Compare and Capture enabled */ +} TC45_HCCAMODE_t; + +/* Compare or Capture High Channel B Mode */ +typedef enum TC45_HCCBMODE_enum +{ + TC45_HCCBMODE_DISABLE_gc = (0x00<<2), /* Channel Disabled */ + TC45_HCCBMODE_COMP_gc = (0x01<<2), /* Ouput Compare enabled */ + TC45_HCCBMODE_CAPT_gc = (0x02<<2), /* Input Capture enabled */ + TC45_HCCBMODE_BOTHCC_gc = (0x03<<2), /* Both Compare and Capture enabled */ +} TC45_HCCBMODE_t; + +/* Compare or Capture High Channel C Mode */ +typedef enum TC45_HCCCMODE_enum +{ + TC45_HCCCMODE_DISABLE_gc = (0x00<<4), /* Channel Disabled */ + TC45_HCCCMODE_COMP_gc = (0x01<<4), /* Ouput Compare enabled */ + TC45_HCCCMODE_CAPT_gc = (0x02<<4), /* Input Capture enabled */ + TC45_HCCCMODE_BOTHCC_gc = (0x03<<4), /* Both Compare and Capture enabled */ +} TC45_HCCCMODE_t; + +/* Compare or Capture High Channel D Mode */ +typedef enum TC45_HCCDMODE_enum +{ + TC45_HCCDMODE_DISABLE_gc = (0x00<<6), /* Channel Disabled */ + TC45_HCCDMODE_COMP_gc = (0x01<<6), /* Ouput Compare enabled */ + TC45_HCCDMODE_CAPT_gc = (0x02<<6), /* Input Capture enabled */ + TC45_HCCDMODE_BOTHCC_gc = (0x03<<6), /* Both Compare and Capture enabled */ +} TC45_HCCDMODE_t; + +/* Timer Trigger Restart Interrupt Level */ +typedef enum TC45_TRGINTLVL_enum +{ + TC45_TRGINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + TC45_TRGINTLVL_LO_gc = (0x01<<4), /* Low Level */ + TC45_TRGINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + TC45_TRGINTLVL_HI_gc = (0x03<<4), /* High Level */ +} TC45_TRGINTLVL_t; + +/* Error Interrupt Level */ +typedef enum TC45_ERRINTLVL_enum +{ + TC45_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC45_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC45_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC45_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC45_ERRINTLVL_t; + +/* Overflow Interrupt Level */ +typedef enum TC45_OVFINTLVL_enum +{ + TC45_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC45_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC45_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC45_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC45_OVFINTLVL_t; + +/* Compare or Capture Channel A Interrupt Level */ +typedef enum TC45_CCAINTLVL_enum +{ + TC45_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC45_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC45_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC45_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC45_CCAINTLVL_t; + +/* Compare or Capture Channel B Interrupt Level */ +typedef enum TC45_CCBINTLVL_enum +{ + TC45_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC45_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC45_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC45_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC45_CCBINTLVL_t; + +/* Compare or Capture Channel C Interrupt Level */ +typedef enum TC45_CCCINTLVL_enum +{ + TC45_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + TC45_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + TC45_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + TC45_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} TC45_CCCINTLVL_t; + +/* Compare or Capture Channel D Interrupt Level */ +typedef enum TC45_CCDINTLVL_enum +{ + TC45_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TC45_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ + TC45_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TC45_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ +} TC45_CCDINTLVL_t; + +/* Compare or Capture Low Channel A Interrupt Level */ +typedef enum TC45_LCCAINTLVL_enum +{ + TC45_LCCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC45_LCCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC45_LCCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC45_LCCAINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC45_LCCAINTLVL_t; + +/* Compare or Capture Low Channel B Interrupt Level */ +typedef enum TC45_LCCBINTLVL_enum +{ + TC45_LCCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC45_LCCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC45_LCCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC45_LCCBINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC45_LCCBINTLVL_t; + +/* Compare or Capture Low Channel C Interrupt Level */ +typedef enum TC45_LCCCINTLVL_enum +{ + TC45_LCCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + TC45_LCCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + TC45_LCCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + TC45_LCCCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} TC45_LCCCINTLVL_t; + +/* Compare or Capture Low Channel D Interrupt Level */ +typedef enum TC45_LCCDINTLVL_enum +{ + TC45_LCCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TC45_LCCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ + TC45_LCCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TC45_LCCDINTLVL_HI_gc = (0x03<<6), /* High Level */ +} TC45_LCCDINTLVL_t; + +/* Timer/Counter Command */ +typedef enum TC45_CMD_enum +{ + TC45_CMD_NONE_gc = (0x00<<2), /* No Command */ + TC45_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TC45_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TC45_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TC45_CMD_t; + + +/* +-------------------------------------------------------------------------- +FAULT - Fault Extension +-------------------------------------------------------------------------- +*/ + +/* Fault Extension */ +typedef struct FAULT_struct +{ + register8_t CTRLA; /* Control A Register */ + register8_t CTRLB; /* Control B Register */ + register8_t CTRLC; /* Control C Register */ + register8_t CTRLD; /* Control D Register */ + register8_t CTRLE; /* Control E Register */ + register8_t STATUS; /* Status Register */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G set */ +} FAULT_t; + +/* Ramp Mode Selection */ +typedef enum FAULT_RAMP_enum +{ + FAULT_RAMP_RAMP1_gc = (0x00<<6), /* Normal Mode */ + FAULT_RAMP_RAMP2_gc = (0x02<<6), /* RAMP2 Mode */ +} FAULT_RAMP_t; + +/* Fault E Input Source Selection */ +typedef enum FAULT_SRCE_enum +{ + FAULT_SRCE_DISABLE_gc = (0x00<<0), /* Fault Protection Disabled */ + FAULT_SRCE_CHN_gc = (0x01<<0), /* Event Channel n */ + FAULT_SRCE_CHN1_gc = (0x02<<0), /* Event Channel n+1 */ + FAULT_SRCE_CHN2_gc = (0x03<<0), /* Event Channel n+2 */ +} FAULT_SRCE_t; + +/* Fault A Halt Action Selection */ +typedef enum FAULT_HALTA_enum +{ + FAULT_HALTA_DISABLE_gc = (0x00<<5), /* Halt Action Disabled */ + FAULT_HALTA_HW_gc = (0x01<<5), /* Hardware Halt Action */ + FAULT_HALTA_SW_gc = (0x02<<5), /* Software Halt Action */ +} FAULT_HALTA_t; + +/* Fault A Source Selection */ +typedef enum FAULT_SRCA_enum +{ + FAULT_SRCA_DISABLE_gc = (0x00<<0), /* Fault A Disabled */ + FAULT_SRCA_CHN_gc = (0x01<<0), /* Event Channel n */ + FAULT_SRCA_CHN1_gc = (0x02<<0), /* Event Channel n+1 */ + FAULT_SRCA_LINK_gc = (0x03<<0), /* Fault A linked to Fault B State from previous cycle */ +} FAULT_SRCA_t; + +/* Fault B Halt Action Selection */ +typedef enum FAULT_HALTB_enum +{ + FAULT_HALTB_DISABLE_gc = (0x00<<5), /* Halt Action Disabled */ + FAULT_HALTB_HW_gc = (0x01<<5), /* Hardware Halt Action */ + FAULT_HALTB_SW_gc = (0x02<<5), /* Software Halt Action */ +} FAULT_HALTB_t; + +/* Fault B Source Selection */ +typedef enum FAULT_SRCB_enum +{ + FAULT_SRCB_DISABLE_gc = (0x00<<0), /* Fault B disabled */ + FAULT_SRCB_CHN_gc = (0x01<<0), /* Event Channel n */ + FAULT_SRCB_CHN1_gc = (0x02<<0), /* Event Channel n+1 */ + FAULT_SRCB_LINK_gc = (0x03<<0), /* Fault B linked to Fault A State from previous cycle */ +} FAULT_SRCB_t; + +/* Channel index Command */ +typedef enum FAULT_IDXCMD_enum +{ + FAULT_IDXCMD_DISABLE_gc = (0x00<<3), /* Command Disabled */ + FAULT_IDXCMD_SET_gc = (0x01<<3), /* Force Cycle B in Next Cycle */ + FAULT_IDXCMD_CLEAR_gc = (0x02<<3), /* Force Cycle A in Next Cycle */ + FAULT_IDXCMD_HOLD_gc = (0x03<<3), /* Hold Current Cycle Index in Next Cycle */ +} FAULT_IDXCMD_t; + + +/* +-------------------------------------------------------------------------- +WEX - Waveform Extension +-------------------------------------------------------------------------- +*/ + +/* Waveform Extension */ +typedef struct WEX_struct +{ + register8_t CTRL; /* Control Register */ + register8_t DTBOTH; /* Dead-time Concurrent Write to Both Sides Register */ + register8_t DTLS; /* Dead-time Low Side Register */ + register8_t DTHS; /* Dead-time High Side Register */ + register8_t STATUSCLR; /* Status Clear Register */ + register8_t STATUSSET; /* Status Set Register */ + register8_t SWAP; /* Swap Register */ + register8_t PGO; /* Pattern Generation Override Register */ + register8_t PGV; /* Pattern Generation Value Register */ + register8_t reserved_0x09; + register8_t SWAPBUF; /* Dead Time Low Side Buffer */ + register8_t PGOBUF; /* Pattern Generation Overwrite Buffer Register */ + register8_t PGVBUF; /* Pattern Generation Value Buffer Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t OUTOVDIS; /* Output Override Disable Register */ +} WEX_t; + +/* Output Matrix Mode */ +typedef enum WEX_OTMX_enum +{ + WEX_OTMX_DEFAULT_gc = (0x00<<4), /* Default Ouput Matrix Mode */ + WEX_OTMX_FIRST_gc = (0x01<<4), /* First Output matrix Mode */ + WEX_OTMX_SECOND_gc = (0x02<<4), /* Second Output matrix Mode */ + WEX_OTMX_THIRD_gc = (0x03<<4), /* Third Output matrix Mode */ + WEX_OTMX_FOURTH_gc = (0x04<<4), /* Fourth Output matrix Mode */ +} WEX_OTMX_t; + + +/* +-------------------------------------------------------------------------- +HIRES - High-Resolution Extension +-------------------------------------------------------------------------- +*/ + +/* High-Resolution Extension */ +typedef struct HIRES_struct +{ + register8_t CTRLA; /* Control Register A */ +} HIRES_t; + +/* High Resolution Plus Mode */ +typedef enum HIRES_HRPLUS_enum +{ + HIRES_HRPLUS_NONE_gc = (0x00<<2), /* No Hi-Res Plus */ + HIRES_HRPLUS_HRP4_gc = (0x01<<2), /* Hi-Res Plus enabled on Timer 4 */ + HIRES_HRPLUS_HRP5_gc = (0x02<<2), /* Hi-Res Plus enabled on Timer 5 */ + HIRES_HRPLUS_BOTH_gc = (0x03<<2), /* Hi-Res Plus enabled on Timer 4 and 5 */ +} HIRES_HRPLUS_t; + +/* High Resolution Mode */ +typedef enum HIRES_HREN_enum +{ + HIRES_HREN_NONE_gc = (0x00<<0), /* No Hi-Res */ + HIRES_HREN_HRP4_gc = (0x01<<0), /* Hi-Res enabled on Timer 4 */ + HIRES_HREN_HRP5_gc = (0x02<<0), /* Hi-Res enabled on Timer 5 */ + HIRES_HREN_BOTH_gc = (0x03<<0), /* Hi-Res enabled on Timer 4 and 5 */ +} HIRES_HREN_t; + + +/* +-------------------------------------------------------------------------- +USART - Universal Asynchronous Receiver-Transmitter +-------------------------------------------------------------------------- +*/ + +/* Universal Synchronous/Asynchronous Receiver/Transmitter */ +typedef struct USART_struct +{ + register8_t DATA; /* Data Register */ + register8_t STATUS; /* Status Register */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t CTRLD; /* Control Register D */ + register8_t BAUDCTRLA; /* Baud Rate Control Register A */ + register8_t BAUDCTRLB; /* Baud Rate Control Register B */ +} USART_t; + +/* Receive Start Interrupt level */ +typedef enum USART_RXSINTLVL_enum +{ + USART_RXSINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + USART_RXSINTLVL_LO_gc = (0x01<<0), /* Low Level */ + USART_RXSINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + USART_RXSINTLVL_HI_gc = (0x03<<0), /* High Level */ +} USART_RXSINTLVL_t; + +/* Receive Complete Interrupt level */ +typedef enum USART_RXCINTLVL_enum +{ + USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} USART_RXCINTLVL_t; + +/* Transmit Complete Interrupt level */ +typedef enum USART_TXCINTLVL_enum +{ + USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ + USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ +} USART_TXCINTLVL_t; + +/* Data Register Empty Interrupt level */ +typedef enum USART_DREINTLVL_enum +{ + USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ + USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ +} USART_DREINTLVL_t; + +/* Character Size */ +typedef enum USART_CHSIZE_enum +{ + USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ + USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ + USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ + USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ + USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ +} USART_CHSIZE_t; + +/* Communication Mode */ +typedef enum USART_CMODE_enum +{ + USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ + USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ + USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ + USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +} USART_CMODE_t; + +/* Parity Mode */ +typedef enum USART_PMODE_enum +{ + USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ + USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ + USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +} USART_PMODE_t; + +/* Encoding and Decoding Type */ +typedef enum USART_DECTYPE_enum +{ + USART_DECTYPE_DATA_gc = (0x00<<4), /* DATA Field Encoding */ + USART_DECTYPE_SDATA_gc = (0x02<<4), /* Start and Data Fields Encoding */ + USART_DECTYPE_NOTSDATA_gc = (0x03<<4), /* Start and Data Fields Encoding, with invertion in START field */ +} USART_DECTYPE_t; + +/* XCL LUT Action */ +typedef enum USART_LUTACT_enum +{ + USART_LUTACT_OFF_gc = (0x00<<2), /* Standard Frame Configuration */ + USART_LUTACT_RX_gc = (0x01<<2), /* Receiver Decoding Enabled */ + USART_LUTACT_TX_gc = (0x02<<2), /* Transmitter Encoding Enabled */ + USART_LUTACT_BOTH_gc = (0x03<<2), /* Both Encoding and Decoding Enabled */ +} USART_LUTACT_t; + +/* XCL Peripheral Counter Action */ +typedef enum USART_PECACT_enum +{ + USART_PECACT_OFF_gc = (0x00<<0), /* Standard Mode */ + USART_PECACT_PEC0_gc = (0x01<<0), /* Variable Data Lenght in Reception */ + USART_PECACT_PEC1_gc = (0x02<<0), /* Variable Data Lenght in Transmission */ + USART_PECACT_PERC01_gc = (0x03<<0), /* Variable Data Lenght in both Reception and Transmission */ +} USART_PECACT_t; + + +/* +-------------------------------------------------------------------------- +SPI - Serial Peripheral Interface +-------------------------------------------------------------------------- +*/ + +/* Serial Peripheral Interface with Buffer Modes */ +typedef struct SPI_struct +{ + register8_t CTRL; /* Control Register */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t STATUS; /* Status Register */ + register8_t DATA; /* Data Register */ + register8_t CTRLB; /* Control Register B */ +} SPI_t; + +/* SPI Mode */ +typedef enum SPI_MODE_enum +{ + SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0, base clock at "0", sampling on leading edge (rising) & set-up on trailling edge (falling). */ + SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1, base clock at "0", set-up on leading edge (rising) & sampling on trailling edge (falling). */ + SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2, base clock at "1", sampling on leading edge (falling) & set-up on trailling edge (rising). */ + SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3, base clock at "1", set-up on leading edge (falling) & sampling on trailling edge (rising). */ +} SPI_MODE_t; + +/* Prescaler setting */ +typedef enum SPI_PRESCALER_enum +{ + SPI_PRESCALER_DIV4_gc = (0x00<<0), /* If CLK2X=1 CLKper/2, else (CLK2X=0) CLKper/4. */ + SPI_PRESCALER_DIV16_gc = (0x01<<0), /* If CLK2X=1 CLKper/8, else (CLK2X=0) CLKper/16. */ + SPI_PRESCALER_DIV64_gc = (0x02<<0), /* If CLK2X=1 CLKper/32, else (CLK2X=0) CLKper/64. */ + SPI_PRESCALER_DIV128_gc = (0x03<<0), /* If CLK2X=1 CLKper/64, else (CLK2X=0) CLKper/128. */ +} SPI_PRESCALER_t; + +/* Interrupt level */ +typedef enum SPI_INTLVL_enum +{ + SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ + SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ + SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ +} SPI_INTLVL_t; + +/* Buffer Modes */ +typedef enum SPI_BUFMODE_enum +{ + SPI_BUFMODE_OFF_gc = (0x00<<6), /* SPI Unbuffered Mode */ + SPI_BUFMODE_BUFMODE1_gc = (0x02<<6), /* Buffer Mode 1 (with dummy byte) */ + SPI_BUFMODE_BUFMODE2_gc = (0x03<<6), /* Buffer Mode 2 (no dummy byte) */ +} SPI_BUFMODE_t; + + +/* +-------------------------------------------------------------------------- +IRCOM - IR Communication Module +-------------------------------------------------------------------------- +*/ + +/* IR Communication Module */ +typedef struct IRCOM_struct +{ + register8_t CTRL; /* Control Register */ + register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ + register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ +} IRCOM_t; + +/* Event channel selection */ +typedef enum IRDA_EVSEL_enum +{ + IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ + IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ + IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ + IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ + IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ + IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ + IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ + IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ + IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ +} IRDA_EVSEL_t; + + +/* +-------------------------------------------------------------------------- +FUSE - Fuses and Lockbits +-------------------------------------------------------------------------- +*/ + +/* Lock Bits */ +typedef struct NVM_LOCKBITS_struct +{ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ +} NVM_LOCKBITS_t; + + +/* Fuses */ +typedef struct NVM_FUSES_struct +{ + register8_t reserved_0x00; + register8_t FUSEBYTE1; /* Watchdog Configuration */ + register8_t FUSEBYTE2; /* Reset Configuration */ + register8_t reserved_0x03; + register8_t FUSEBYTE4; /* Start-up Configuration */ + register8_t FUSEBYTE5; /* EESAVE and BOD Level */ + register8_t FUSEBYTE6; /* Fault State */ +} NVM_FUSES_t; + +/* Boot lock bits - boot setcion */ +typedef enum FUSE_BLBB_enum +{ + FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ + FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ + FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ + FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ +} FUSE_BLBB_t; + +/* Boot lock bits - application section */ +typedef enum FUSE_BLBA_enum +{ + FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ + FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ + FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ + FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ +} FUSE_BLBA_t; + +/* Boot lock bits - application table section */ +typedef enum FUSE_BLBAT_enum +{ + FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ + FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ + FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ + FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ +} FUSE_BLBAT_t; + +/* Lock bits */ +typedef enum FUSE_LB_enum +{ + FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ + FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ + FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ +} FUSE_LB_t; + +/* Boot Loader Section Reset Vector */ +typedef enum BOOTRST_enum +{ + BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ + BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ +} BOOTRST_t; + +/* BOD operation */ +typedef enum BOD_enum +{ + BOD_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ + BOD_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ + BOD_DISABLED_gc = (0x03<<4), /* BOD Disabled */ +} BOD_t; + +/* Watchdog (Window) Timeout Period */ +typedef enum WD_enum +{ + WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ + WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ + WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ + WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ + WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ + WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ + WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ + WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ + WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ + WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ + WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ +} WD_t; + +/* Start-up Time */ +typedef enum SUT_enum +{ + SUT_0MS_gc = (0x03<<2), /* 0 ms */ + SUT_4MS_gc = (0x01<<2), /* 4 ms */ + SUT_64MS_gc = (0x00<<2), /* 64 ms */ +} SUT_t; + +/* Brownout Detection Voltage Level */ +typedef enum BODLVL_enum +{ + BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ + BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ + BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ + BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ + BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ + BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ + BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ + BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ +} BODLVL_t; + + +/* +-------------------------------------------------------------------------- +SIGROW - Signature Row +-------------------------------------------------------------------------- +*/ + +/* Production Signatures */ +typedef struct NVM_PROD_SIGNATURES_struct +{ + register8_t RCOSC8M; /* RCOSC 8MHz Calibration Value */ + register8_t reserved_0x01; + register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ + register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ + register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ + register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ + register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ + register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ + register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ + register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t WAFNUM; /* Wafer Number */ + register8_t reserved_0x11; + register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ + register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ + register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ + register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t ROOMTEMP; /* Temperature corresponds to TEMPSENSE3/2 */ + register8_t HOTTEMP; /* Temperature corresponds to TEMPSENSE1/0 */ + register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ + register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + register8_t reserved_0x26; + register8_t reserved_0x27; + register8_t ACACURRCAL; /* ACA Current Calibration Byte */ + register8_t reserved_0x29; + register8_t reserved_0x2A; + register8_t reserved_0x2B; + register8_t TEMPSENSE2; /* Temperature Sensor Calibration Byte 2 */ + register8_t TEMPSENSE3; /* Temperature Sensor Calibration Byte 3 */ + register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ + register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ + register8_t DACA0OFFCAL; /* DACA0 Calibration Byte 0 */ + register8_t DACA0GAINCAL; /* DACA0 Calibration Byte 1 */ + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t DACA1OFFCAL; /* DACA1 Calibration Byte 0 */ + register8_t DACA1GAINCAL; /* DACA1 Calibration Byte 1 */ + register8_t reserved_0x36; + register8_t reserved_0x37; + register8_t reserved_0x38; + register8_t reserved_0x39; + register8_t reserved_0x3A; + register8_t reserved_0x3B; + register8_t reserved_0x3C; + register8_t reserved_0x3D; + register8_t reserved_0x3E; + register8_t reserved_0x3F; +} NVM_PROD_SIGNATURES_t; + +/* +========================================================================== +IO Module Instances. Mapped to memory. +========================================================================== +*/ + +#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ +#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ +#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ +#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ +#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ +#define CLK (*(CLK_t *) 0x0040) /* Clock System */ +#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ +#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ +#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ +#define PR (*(PR_t *) 0x0070) /* Power Reduction */ +#define RST (*(RST_t *) 0x0078) /* Reset */ +#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ +#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ +#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ +#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ +#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ +#define EDMA (*(EDMA_t *) 0x0100) /* Enhanced DMA Controller */ +#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ +#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ +#define DACA (*(DAC_t *) 0x0300) /* Digital-to-Analog Converter */ +#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ +#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ +#define XCL (*(XCL_t *) 0x0460) /* XMEGA Custom Logic */ +#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ +#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ +#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ +#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ +#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ +#define TCC4 (*(TC4_t *) 0x0800) /* 16-bit Timer/Counter 4 */ +#define TCC5 (*(TC5_t *) 0x0840) /* 16-bit Timer/Counter 5 */ +#define FAULTC4 (*(FAULT_t *) 0x0880) /* Fault Extension */ +#define FAULTC5 (*(FAULT_t *) 0x0890) /* Fault Extension */ +#define WEXC (*(WEX_t *) 0x08A0) /* Waveform Extension */ +#define HIRESC (*(HIRES_t *) 0x08B0) /* High-Resolution Extension */ +#define USARTC0 (*(USART_t *) 0x08C0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define SPIC (*(SPI_t *) 0x08E0) /* Serial Peripheral Interface with Buffer Modes */ +#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ +#define TCD5 (*(TC5_t *) 0x0940) /* 16-bit Timer/Counter 5 */ +#define USARTD0 (*(USART_t *) 0x09C0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ + + +#endif /* !defined (__ASSEMBLER__) */ + + +/* ========== Flattened fully qualified IO register names ========== */ + +/* GPIO - General Purpose IO Registers */ +#define GPIO_GPIOR0 _SFR_MEM8(0x0000) +#define GPIO_GPIOR1 _SFR_MEM8(0x0001) +#define GPIO_GPIOR2 _SFR_MEM8(0x0002) +#define GPIO_GPIOR3 _SFR_MEM8(0x0003) + +/* Deprecated */ +#define GPIO_GPIO0 _SFR_MEM8(0x0000) +#define GPIO_GPIO1 _SFR_MEM8(0x0001) +#define GPIO_GPIO2 _SFR_MEM8(0x0002) +#define GPIO_GPIO3 _SFR_MEM8(0x0003) + +/* NVM_FUSES - Fuses */ +#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) +#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) +#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) +#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) +#define FUSE_FUSEBYTE6 _SFR_MEM8(0x0006) + +/* NVM_LOCKBITS - Lock Bits */ +#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) + +/* NVM_PROD_SIGNATURES - Production Signatures */ +#define PRODSIGNATURES_RCOSC8M _SFR_MEM8(0x0000) +#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) +#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) +#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) +#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) +#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) +#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) +#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) +#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) +#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) +#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) +#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) +#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) +#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) +#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) +#define PRODSIGNATURES_ROOMTEMP _SFR_MEM8(0x001E) +#define PRODSIGNATURES_HOTTEMP _SFR_MEM8(0x001F) +#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) +#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) +#define PRODSIGNATURES_ACACURRCAL _SFR_MEM8(0x0028) +#define PRODSIGNATURES_TEMPSENSE2 _SFR_MEM8(0x002C) +#define PRODSIGNATURES_TEMPSENSE3 _SFR_MEM8(0x002D) +#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) +#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) +#define PRODSIGNATURES_DACA0OFFCAL _SFR_MEM8(0x0030) +#define PRODSIGNATURES_DACA0GAINCAL _SFR_MEM8(0x0031) +#define PRODSIGNATURES_DACA1OFFCAL _SFR_MEM8(0x0034) +#define PRODSIGNATURES_DACA1GAINCAL _SFR_MEM8(0x0035) + +/* VPORT - Virtual Port */ +#define VPORT0_DIR _SFR_MEM8(0x0010) +#define VPORT0_OUT _SFR_MEM8(0x0011) +#define VPORT0_IN _SFR_MEM8(0x0012) +#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) + +/* VPORT - Virtual Port */ +#define VPORT1_DIR _SFR_MEM8(0x0014) +#define VPORT1_OUT _SFR_MEM8(0x0015) +#define VPORT1_IN _SFR_MEM8(0x0016) +#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) + +/* VPORT - Virtual Port */ +#define VPORT2_DIR _SFR_MEM8(0x0018) +#define VPORT2_OUT _SFR_MEM8(0x0019) +#define VPORT2_IN _SFR_MEM8(0x001A) +#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) + +/* VPORT - Virtual Port */ +#define VPORT3_DIR _SFR_MEM8(0x001C) +#define VPORT3_OUT _SFR_MEM8(0x001D) +#define VPORT3_IN _SFR_MEM8(0x001E) +#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) + +/* OCD - On-Chip Debug System */ +#define OCD_OCDR0 _SFR_MEM8(0x002E) +#define OCD_OCDR1 _SFR_MEM8(0x002F) + +/* CPU - CPU registers */ +#define CPU_CCP _SFR_MEM8(0x0034) +#define CPU_RAMPD _SFR_MEM8(0x0038) +#define CPU_RAMPX _SFR_MEM8(0x0039) +#define CPU_RAMPY _SFR_MEM8(0x003A) +#define CPU_RAMPZ _SFR_MEM8(0x003B) +#define CPU_EIND _SFR_MEM8(0x003C) +#define CPU_SPL _SFR_MEM8(0x003D) +#define CPU_SPH _SFR_MEM8(0x003E) +#define CPU_SREG _SFR_MEM8(0x003F) + +/* CLK - Clock System */ +#define CLK_CTRL _SFR_MEM8(0x0040) +#define CLK_PSCTRL _SFR_MEM8(0x0041) +#define CLK_LOCK _SFR_MEM8(0x0042) +#define CLK_RTCCTRL _SFR_MEM8(0x0043) + +/* SLEEP - Sleep Controller */ +#define SLEEP_CTRL _SFR_MEM8(0x0048) + +/* OSC - Oscillator */ +#define OSC_CTRL _SFR_MEM8(0x0050) +#define OSC_STATUS _SFR_MEM8(0x0051) +#define OSC_XOSCCTRL _SFR_MEM8(0x0052) +#define OSC_XOSCFAIL _SFR_MEM8(0x0053) +#define OSC_RC32KCAL _SFR_MEM8(0x0054) +#define OSC_PLLCTRL _SFR_MEM8(0x0055) +#define OSC_DFLLCTRL _SFR_MEM8(0x0056) +#define OSC_RC8MCAL _SFR_MEM8(0x0057) + +/* DFLL - DFLL */ +#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) +#define DFLLRC32M_CALA _SFR_MEM8(0x0062) +#define DFLLRC32M_CALB _SFR_MEM8(0x0063) +#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) +#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) +#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) + +/* PR - Power Reduction */ +#define PR_PRGEN _SFR_MEM8(0x0070) +#define PR_PRPA _SFR_MEM8(0x0071) +#define PR_PRPC _SFR_MEM8(0x0073) +#define PR_PRPD _SFR_MEM8(0x0074) + +/* RST - Reset */ +#define RST_STATUS _SFR_MEM8(0x0078) +#define RST_CTRL _SFR_MEM8(0x0079) + +/* WDT - Watch-Dog Timer */ +#define WDT_CTRL _SFR_MEM8(0x0080) +#define WDT_WINCTRL _SFR_MEM8(0x0081) +#define WDT_STATUS _SFR_MEM8(0x0082) + +/* MCU - MCU Control */ +#define MCU_DEVID0 _SFR_MEM8(0x0090) +#define MCU_DEVID1 _SFR_MEM8(0x0091) +#define MCU_DEVID2 _SFR_MEM8(0x0092) +#define MCU_REVID _SFR_MEM8(0x0093) +#define MCU_ANAINIT _SFR_MEM8(0x0097) +#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) +#define MCU_WEXLOCK _SFR_MEM8(0x0099) +#define MCU_FAULTLOCK _SFR_MEM8(0x009A) + +/* PMIC - Programmable Multi-level Interrupt Controller */ +#define PMIC_STATUS _SFR_MEM8(0x00A0) +#define PMIC_INTPRI _SFR_MEM8(0x00A1) +#define PMIC_CTRL _SFR_MEM8(0x00A2) + +/* PORTCFG - I/O port Configuration */ +#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) +#define PORTCFG_CLKOUT _SFR_MEM8(0x00B4) +#define PORTCFG_ACEVOUT _SFR_MEM8(0x00B6) +#define PORTCFG_SRLCTRL _SFR_MEM8(0x00B7) + +/* CRC - Cyclic Redundancy Checker */ +#define CRC_CTRL _SFR_MEM8(0x00D0) +#define CRC_STATUS _SFR_MEM8(0x00D1) +#define CRC_DATAIN _SFR_MEM8(0x00D3) +#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) +#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) +#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) +#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) + +/* EDMA - Enhanced DMA Controller */ +#define EDMA_CTRL _SFR_MEM8(0x0100) +#define EDMA_INTFLAGS _SFR_MEM8(0x0103) +#define EDMA_STATUS _SFR_MEM8(0x0104) +#define EDMA_TEMP _SFR_MEM8(0x0106) +#define EDMA_CH0_CTRLA _SFR_MEM8(0x0110) +#define EDMA_CH0_CTRLB _SFR_MEM8(0x0111) +#define EDMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) +#define EDMA_CH0_DESTADDRCTRL _SFR_MEM8(0x0113) +#define EDMA_CH0_TRIGSRC _SFR_MEM8(0x0114) +#define EDMA_CH0_TRFCNT _SFR_MEM16(0x0116) +#define EDMA_CH0_ADDR _SFR_MEM16(0x0118) +#define EDMA_CH0_DESTADDR _SFR_MEM16(0x011C) +#define EDMA_CH1_CTRLA _SFR_MEM8(0x0120) +#define EDMA_CH1_CTRLB _SFR_MEM8(0x0121) +#define EDMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) +#define EDMA_CH1_DESTADDRCTRL _SFR_MEM8(0x0123) +#define EDMA_CH1_TRIGSRC _SFR_MEM8(0x0124) +#define EDMA_CH1_TRFCNT _SFR_MEM16(0x0126) +#define EDMA_CH1_ADDR _SFR_MEM16(0x0128) +#define EDMA_CH1_DESTADDR _SFR_MEM16(0x012C) +#define EDMA_CH2_CTRLA _SFR_MEM8(0x0130) +#define EDMA_CH2_CTRLB _SFR_MEM8(0x0131) +#define EDMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) +#define EDMA_CH2_DESTADDRCTRL _SFR_MEM8(0x0133) +#define EDMA_CH2_TRIGSRC _SFR_MEM8(0x0134) +#define EDMA_CH2_TRFCNT _SFR_MEM16(0x0136) +#define EDMA_CH2_ADDR _SFR_MEM16(0x0138) +#define EDMA_CH2_DESTADDR _SFR_MEM16(0x013C) +#define EDMA_CH3_CTRLA _SFR_MEM8(0x0140) +#define EDMA_CH3_CTRLB _SFR_MEM8(0x0141) +#define EDMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) +#define EDMA_CH3_DESTADDRCTRL _SFR_MEM8(0x0143) +#define EDMA_CH3_TRIGSRC _SFR_MEM8(0x0144) +#define EDMA_CH3_TRFCNT _SFR_MEM16(0x0146) +#define EDMA_CH3_ADDR _SFR_MEM16(0x0148) +#define EDMA_CH3_DESTADDR _SFR_MEM16(0x014C) + +/* EVSYS - Event System */ +#define EVSYS_CH0MUX _SFR_MEM8(0x0180) +#define EVSYS_CH1MUX _SFR_MEM8(0x0181) +#define EVSYS_CH2MUX _SFR_MEM8(0x0182) +#define EVSYS_CH3MUX _SFR_MEM8(0x0183) +#define EVSYS_CH4MUX _SFR_MEM8(0x0184) +#define EVSYS_CH5MUX _SFR_MEM8(0x0185) +#define EVSYS_CH6MUX _SFR_MEM8(0x0186) +#define EVSYS_CH7MUX _SFR_MEM8(0x0187) +#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) +#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) +#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) +#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) +#define EVSYS_CH4CTRL _SFR_MEM8(0x018C) +#define EVSYS_CH5CTRL _SFR_MEM8(0x018D) +#define EVSYS_CH6CTRL _SFR_MEM8(0x018E) +#define EVSYS_CH7CTRL _SFR_MEM8(0x018F) +#define EVSYS_STROBE _SFR_MEM8(0x0190) +#define EVSYS_DATA _SFR_MEM8(0x0191) +#define EVSYS_DFCTRL _SFR_MEM8(0x0192) + +/* NVM - Non-volatile Memory Controller */ +#define NVM_ADDR0 _SFR_MEM8(0x01C0) +#define NVM_ADDR1 _SFR_MEM8(0x01C1) +#define NVM_ADDR2 _SFR_MEM8(0x01C2) +#define NVM_DATA0 _SFR_MEM8(0x01C4) +#define NVM_DATA1 _SFR_MEM8(0x01C5) +#define NVM_DATA2 _SFR_MEM8(0x01C6) +#define NVM_CMD _SFR_MEM8(0x01CA) +#define NVM_CTRLA _SFR_MEM8(0x01CB) +#define NVM_CTRLB _SFR_MEM8(0x01CC) +#define NVM_INTCTRL _SFR_MEM8(0x01CD) +#define NVM_STATUS _SFR_MEM8(0x01CF) +#define NVM_LOCKBITS _SFR_MEM8(0x01D0) + +/* ADC - Analog-to-Digital Converter */ +#define ADCA_CTRLA _SFR_MEM8(0x0200) +#define ADCA_CTRLB _SFR_MEM8(0x0201) +#define ADCA_REFCTRL _SFR_MEM8(0x0202) +#define ADCA_EVCTRL _SFR_MEM8(0x0203) +#define ADCA_PRESCALER _SFR_MEM8(0x0204) +#define ADCA_INTFLAGS _SFR_MEM8(0x0206) +#define ADCA_TEMP _SFR_MEM8(0x0207) +#define ADCA_SAMPCTRL _SFR_MEM8(0x0208) +#define ADCA_CAL _SFR_MEM16(0x020C) +#define ADCA_CH0RES _SFR_MEM16(0x0210) +#define ADCA_CMP _SFR_MEM16(0x0218) +#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) +#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) +#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) +#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) +#define ADCA_CH0_RES _SFR_MEM16(0x0224) +#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) +#define ADCA_CH0_CORRCTRL _SFR_MEM8(0x0227) +#define ADCA_CH0_OFFSETCORR0 _SFR_MEM8(0x0228) +#define ADCA_CH0_OFFSETCORR1 _SFR_MEM8(0x0229) +#define ADCA_CH0_GAINCORR0 _SFR_MEM8(0x022A) +#define ADCA_CH0_GAINCORR1 _SFR_MEM8(0x022B) +#define ADCA_CH0_AVGCTRL _SFR_MEM8(0x022C) + +/* DAC - Digital-to-Analog Converter */ +#define DACA_CTRLA _SFR_MEM8(0x0300) +#define DACA_CTRLB _SFR_MEM8(0x0301) +#define DACA_CTRLC _SFR_MEM8(0x0302) +#define DACA_EVCTRL _SFR_MEM8(0x0303) +#define DACA_STATUS _SFR_MEM8(0x0305) +#define DACA_CH0GAINCAL _SFR_MEM8(0x0308) +#define DACA_CH0OFFSETCAL _SFR_MEM8(0x0309) +#define DACA_CH1GAINCAL _SFR_MEM8(0x030A) +#define DACA_CH1OFFSETCAL _SFR_MEM8(0x030B) +#define DACA_CH0DATA _SFR_MEM16(0x0318) +#define DACA_CH1DATA _SFR_MEM16(0x031A) + +/* AC - Analog Comparator */ +#define ACA_AC0CTRL _SFR_MEM8(0x0380) +#define ACA_AC1CTRL _SFR_MEM8(0x0381) +#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) +#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) +#define ACA_CTRLA _SFR_MEM8(0x0384) +#define ACA_CTRLB _SFR_MEM8(0x0385) +#define ACA_WINCTRL _SFR_MEM8(0x0386) +#define ACA_STATUS _SFR_MEM8(0x0387) +#define ACA_CURRCTRL _SFR_MEM8(0x0388) +#define ACA_CURRCALIB _SFR_MEM8(0x0389) + +/* RTC - Real-Time Counter */ +#define RTC_CTRL _SFR_MEM8(0x0400) +#define RTC_STATUS _SFR_MEM8(0x0401) +#define RTC_INTCTRL _SFR_MEM8(0x0402) +#define RTC_INTFLAGS _SFR_MEM8(0x0403) +#define RTC_TEMP _SFR_MEM8(0x0404) +#define RTC_CALIB _SFR_MEM8(0x0406) +#define RTC_CNT _SFR_MEM16(0x0408) +#define RTC_PER _SFR_MEM16(0x040A) +#define RTC_COMP _SFR_MEM16(0x040C) + +/* XCL - XMEGA Custom Logic */ +#define XCL_CTRLA _SFR_MEM8(0x0460) +#define XCL_CTRLB _SFR_MEM8(0x0461) +#define XCL_CTRLC _SFR_MEM8(0x0462) +#define XCL_CTRLD _SFR_MEM8(0x0463) +#define XCL_CTRLE _SFR_MEM8(0x0464) +#define XCL_CTRLF _SFR_MEM8(0x0465) +#define XCL_CTRLG _SFR_MEM8(0x0466) +#define XCL_INTCTRL _SFR_MEM8(0x0467) +#define XCL_INTFLAGS _SFR_MEM8(0x0468) +#define XCL_PLC _SFR_MEM8(0x0469) +#define XCL_CNTL _SFR_MEM8(0x046A) +#define XCL_CNTH _SFR_MEM8(0x046B) +#define XCL_CMPL _SFR_MEM8(0x046C) +#define XCL_CMPH _SFR_MEM8(0x046D) +#define XCL_PERCAPTL _SFR_MEM8(0x046E) +#define XCL_PERCAPTH _SFR_MEM8(0x046F) + +/* TWI - Two-Wire Interface */ +#define TWIC_CTRL _SFR_MEM8(0x0480) +#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) +#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) +#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) +#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) +#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) +#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) +#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) +#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) +#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) +#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) +#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) +#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) +#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) +#define TWIC_TIMEOUT_TOS _SFR_MEM8(0x048E) +#define TWIC_TIMEOUT_TOCONF _SFR_MEM8(0x048F) + +/* PORT - I/O Ports */ +#define PORTA_DIR _SFR_MEM8(0x0600) +#define PORTA_DIRSET _SFR_MEM8(0x0601) +#define PORTA_DIRCLR _SFR_MEM8(0x0602) +#define PORTA_DIRTGL _SFR_MEM8(0x0603) +#define PORTA_OUT _SFR_MEM8(0x0604) +#define PORTA_OUTSET _SFR_MEM8(0x0605) +#define PORTA_OUTCLR _SFR_MEM8(0x0606) +#define PORTA_OUTTGL _SFR_MEM8(0x0607) +#define PORTA_IN _SFR_MEM8(0x0608) +#define PORTA_INTCTRL _SFR_MEM8(0x0609) +#define PORTA_INTMASK _SFR_MEM8(0x060A) +#define PORTA_INTFLAGS _SFR_MEM8(0x060C) +#define PORTA_REMAP _SFR_MEM8(0x060E) +#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) +#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) +#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) +#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) +#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) +#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) +#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) +#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) + +/* PORT - I/O Ports */ +#define PORTC_DIR _SFR_MEM8(0x0640) +#define PORTC_DIRSET _SFR_MEM8(0x0641) +#define PORTC_DIRCLR _SFR_MEM8(0x0642) +#define PORTC_DIRTGL _SFR_MEM8(0x0643) +#define PORTC_OUT _SFR_MEM8(0x0644) +#define PORTC_OUTSET _SFR_MEM8(0x0645) +#define PORTC_OUTCLR _SFR_MEM8(0x0646) +#define PORTC_OUTTGL _SFR_MEM8(0x0647) +#define PORTC_IN _SFR_MEM8(0x0648) +#define PORTC_INTCTRL _SFR_MEM8(0x0649) +#define PORTC_INTMASK _SFR_MEM8(0x064A) +#define PORTC_INTFLAGS _SFR_MEM8(0x064C) +#define PORTC_REMAP _SFR_MEM8(0x064E) +#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) +#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) +#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) +#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) +#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) +#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) +#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) +#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) + +/* PORT - I/O Ports */ +#define PORTD_DIR _SFR_MEM8(0x0660) +#define PORTD_DIRSET _SFR_MEM8(0x0661) +#define PORTD_DIRCLR _SFR_MEM8(0x0662) +#define PORTD_DIRTGL _SFR_MEM8(0x0663) +#define PORTD_OUT _SFR_MEM8(0x0664) +#define PORTD_OUTSET _SFR_MEM8(0x0665) +#define PORTD_OUTCLR _SFR_MEM8(0x0666) +#define PORTD_OUTTGL _SFR_MEM8(0x0667) +#define PORTD_IN _SFR_MEM8(0x0668) +#define PORTD_INTCTRL _SFR_MEM8(0x0669) +#define PORTD_INTMASK _SFR_MEM8(0x066A) +#define PORTD_INTFLAGS _SFR_MEM8(0x066C) +#define PORTD_REMAP _SFR_MEM8(0x066E) +#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) +#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) +#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) +#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) +#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) +#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) +#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) +#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) + +/* PORT - I/O Ports */ +#define PORTR_DIR _SFR_MEM8(0x07E0) +#define PORTR_DIRSET _SFR_MEM8(0x07E1) +#define PORTR_DIRCLR _SFR_MEM8(0x07E2) +#define PORTR_DIRTGL _SFR_MEM8(0x07E3) +#define PORTR_OUT _SFR_MEM8(0x07E4) +#define PORTR_OUTSET _SFR_MEM8(0x07E5) +#define PORTR_OUTCLR _SFR_MEM8(0x07E6) +#define PORTR_OUTTGL _SFR_MEM8(0x07E7) +#define PORTR_IN _SFR_MEM8(0x07E8) +#define PORTR_INTCTRL _SFR_MEM8(0x07E9) +#define PORTR_INTMASK _SFR_MEM8(0x07EA) +#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) +#define PORTR_REMAP _SFR_MEM8(0x07EE) +#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) +#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) +#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) +#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) +#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) +#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) +#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) +#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) + +/* TC4 - 16-bit Timer/Counter 4 */ +#define TCC4_CTRLA _SFR_MEM8(0x0800) +#define TCC4_CTRLB _SFR_MEM8(0x0801) +#define TCC4_CTRLC _SFR_MEM8(0x0802) +#define TCC4_CTRLD _SFR_MEM8(0x0803) +#define TCC4_CTRLE _SFR_MEM8(0x0804) +#define TCC4_CTRLF _SFR_MEM8(0x0805) +#define TCC4_INTCTRLA _SFR_MEM8(0x0806) +#define TCC4_INTCTRLB _SFR_MEM8(0x0807) +#define TCC4_CTRLGCLR _SFR_MEM8(0x0808) +#define TCC4_CTRLGSET _SFR_MEM8(0x0809) +#define TCC4_CTRLHCLR _SFR_MEM8(0x080A) +#define TCC4_CTRLHSET _SFR_MEM8(0x080B) +#define TCC4_INTFLAGS _SFR_MEM8(0x080C) +#define TCC4_TEMP _SFR_MEM8(0x080F) +#define TCC4_CNT _SFR_MEM16(0x0820) +#define TCC4_PER _SFR_MEM16(0x0826) +#define TCC4_CCA _SFR_MEM16(0x0828) +#define TCC4_CCB _SFR_MEM16(0x082A) +#define TCC4_CCC _SFR_MEM16(0x082C) +#define TCC4_CCD _SFR_MEM16(0x082E) +#define TCC4_PERBUF _SFR_MEM16(0x0836) +#define TCC4_CCABUF _SFR_MEM16(0x0838) +#define TCC4_CCBBUF _SFR_MEM16(0x083A) +#define TCC4_CCCBUF _SFR_MEM16(0x083C) +#define TCC4_CCDBUF _SFR_MEM16(0x083E) + +/* TC5 - 16-bit Timer/Counter 5 */ +#define TCC5_CTRLA _SFR_MEM8(0x0840) +#define TCC5_CTRLB _SFR_MEM8(0x0841) +#define TCC5_CTRLC _SFR_MEM8(0x0842) +#define TCC5_CTRLD _SFR_MEM8(0x0843) +#define TCC5_CTRLE _SFR_MEM8(0x0844) +#define TCC5_CTRLF _SFR_MEM8(0x0845) +#define TCC5_INTCTRLA _SFR_MEM8(0x0846) +#define TCC5_INTCTRLB _SFR_MEM8(0x0847) +#define TCC5_CTRLGCLR _SFR_MEM8(0x0848) +#define TCC5_CTRLGSET _SFR_MEM8(0x0849) +#define TCC5_CTRLHCLR _SFR_MEM8(0x084A) +#define TCC5_CTRLHSET _SFR_MEM8(0x084B) +#define TCC5_INTFLAGS _SFR_MEM8(0x084C) +#define TCC5_TEMP _SFR_MEM8(0x084F) +#define TCC5_CNT _SFR_MEM16(0x0860) +#define TCC5_PER _SFR_MEM16(0x0866) +#define TCC5_CCA _SFR_MEM16(0x0868) +#define TCC5_CCB _SFR_MEM16(0x086A) +#define TCC5_PERBUF _SFR_MEM16(0x0876) +#define TCC5_CCABUF _SFR_MEM16(0x0878) +#define TCC5_CCBBUF _SFR_MEM16(0x087A) + +/* FAULT - Fault Extension */ +#define FAULTC4_CTRLA _SFR_MEM8(0x0880) +#define FAULTC4_CTRLB _SFR_MEM8(0x0881) +#define FAULTC4_CTRLC _SFR_MEM8(0x0882) +#define FAULTC4_CTRLD _SFR_MEM8(0x0883) +#define FAULTC4_CTRLE _SFR_MEM8(0x0884) +#define FAULTC4_STATUS _SFR_MEM8(0x0885) +#define FAULTC4_CTRLGCLR _SFR_MEM8(0x0886) +#define FAULTC4_CTRLGSET _SFR_MEM8(0x0887) + +/* FAULT - Fault Extension */ +#define FAULTC5_CTRLA _SFR_MEM8(0x0890) +#define FAULTC5_CTRLB _SFR_MEM8(0x0891) +#define FAULTC5_CTRLC _SFR_MEM8(0x0892) +#define FAULTC5_CTRLD _SFR_MEM8(0x0893) +#define FAULTC5_CTRLE _SFR_MEM8(0x0894) +#define FAULTC5_STATUS _SFR_MEM8(0x0895) +#define FAULTC5_CTRLGCLR _SFR_MEM8(0x0896) +#define FAULTC5_CTRLGSET _SFR_MEM8(0x0897) + +/* WEX - Waveform Extension */ +#define WEXC_CTRL _SFR_MEM8(0x08A0) +#define WEXC_DTBOTH _SFR_MEM8(0x08A1) +#define WEXC_DTLS _SFR_MEM8(0x08A2) +#define WEXC_DTHS _SFR_MEM8(0x08A3) +#define WEXC_STATUSCLR _SFR_MEM8(0x08A4) +#define WEXC_STATUSSET _SFR_MEM8(0x08A5) +#define WEXC_SWAP _SFR_MEM8(0x08A6) +#define WEXC_PGO _SFR_MEM8(0x08A7) +#define WEXC_PGV _SFR_MEM8(0x08A8) +#define WEXC_SWAPBUF _SFR_MEM8(0x08AA) +#define WEXC_PGOBUF _SFR_MEM8(0x08AB) +#define WEXC_PGVBUF _SFR_MEM8(0x08AC) +#define WEXC_OUTOVDIS _SFR_MEM8(0x08AF) + +/* HIRES - High-Resolution Extension */ +#define HIRESC_CTRLA _SFR_MEM8(0x08B0) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTC0_DATA _SFR_MEM8(0x08C0) +#define USARTC0_STATUS _SFR_MEM8(0x08C1) +#define USARTC0_CTRLA _SFR_MEM8(0x08C2) +#define USARTC0_CTRLB _SFR_MEM8(0x08C3) +#define USARTC0_CTRLC _SFR_MEM8(0x08C4) +#define USARTC0_CTRLD _SFR_MEM8(0x08C5) +#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08C6) +#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08C7) + +/* SPI - Serial Peripheral Interface with Buffer Modes */ +#define SPIC_CTRL _SFR_MEM8(0x08E0) +#define SPIC_INTCTRL _SFR_MEM8(0x08E1) +#define SPIC_STATUS _SFR_MEM8(0x08E2) +#define SPIC_DATA _SFR_MEM8(0x08E3) +#define SPIC_CTRLB _SFR_MEM8(0x08E4) + +/* IRCOM - IR Communication Module */ +#define IRCOM_CTRL _SFR_MEM8(0x08F8) +#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) +#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) + +/* TC5 - 16-bit Timer/Counter 5 */ +#define TCD5_CTRLA _SFR_MEM8(0x0940) +#define TCD5_CTRLB _SFR_MEM8(0x0941) +#define TCD5_CTRLC _SFR_MEM8(0x0942) +#define TCD5_CTRLD _SFR_MEM8(0x0943) +#define TCD5_CTRLE _SFR_MEM8(0x0944) +#define TCD5_CTRLF _SFR_MEM8(0x0945) +#define TCD5_INTCTRLA _SFR_MEM8(0x0946) +#define TCD5_INTCTRLB _SFR_MEM8(0x0947) +#define TCD5_CTRLGCLR _SFR_MEM8(0x0948) +#define TCD5_CTRLGSET _SFR_MEM8(0x0949) +#define TCD5_CTRLHCLR _SFR_MEM8(0x094A) +#define TCD5_CTRLHSET _SFR_MEM8(0x094B) +#define TCD5_INTFLAGS _SFR_MEM8(0x094C) +#define TCD5_TEMP _SFR_MEM8(0x094F) +#define TCD5_CNT _SFR_MEM16(0x0960) +#define TCD5_PER _SFR_MEM16(0x0966) +#define TCD5_CCA _SFR_MEM16(0x0968) +#define TCD5_CCB _SFR_MEM16(0x096A) +#define TCD5_PERBUF _SFR_MEM16(0x0976) +#define TCD5_CCABUF _SFR_MEM16(0x0978) +#define TCD5_CCBBUF _SFR_MEM16(0x097A) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTD0_DATA _SFR_MEM8(0x09C0) +#define USARTD0_STATUS _SFR_MEM8(0x09C1) +#define USARTD0_CTRLA _SFR_MEM8(0x09C2) +#define USARTD0_CTRLB _SFR_MEM8(0x09C3) +#define USARTD0_CTRLC _SFR_MEM8(0x09C4) +#define USARTD0_CTRLD _SFR_MEM8(0x09C5) +#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09C6) +#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09C7) + + + +/*================== Bitfield Definitions ================== */ + +/* VPORT - Virtual Ports */ +/* VPORT.INTFLAGS bit masks and bit positions */ +#define VPORT_INT7IF_bm 0x80 /* Interrupt Pin 7 Flag bit mask. */ +#define VPORT_INT7IF_bp 7 /* Interrupt Pin 7 Flag bit position. */ + +#define VPORT_INT6IF_bm 0x40 /* Interrupt Pin 6 Flag bit mask. */ +#define VPORT_INT6IF_bp 6 /* Interrupt Pin 6 Flag bit position. */ + +#define VPORT_INT5IF_bm 0x20 /* Interrupt Pin 5 Flag bit mask. */ +#define VPORT_INT5IF_bp 5 /* Interrupt Pin 5 Flag bit position. */ + +#define VPORT_INT4IF_bm 0x10 /* Interrupt Pin 4 Flag bit mask. */ +#define VPORT_INT4IF_bp 4 /* Interrupt Pin 4 Flag bit position. */ + +#define VPORT_INT3IF_bm 0x08 /* Interrupt Pin 3 Flag bit mask. */ +#define VPORT_INT3IF_bp 3 /* Interrupt Pin 3 Flag bit position. */ + +#define VPORT_INT2IF_bm 0x04 /* Interrupt Pin 2 Flag bit mask. */ +#define VPORT_INT2IF_bp 2 /* Interrupt Pin 2 Flag bit position. */ + +#define VPORT_INT1IF_bm 0x02 /* Interrupt Pin 1 Flag bit mask. */ +#define VPORT_INT1IF_bp 1 /* Interrupt Pin 1 Flag bit position. */ + +#define VPORT_INT0IF_bm 0x01 /* Interrupt Pin 0 Flag bit mask. */ +#define VPORT_INT0IF_bp 0 /* Interrupt Pin 0 Flag bit position. */ + +/* XOCD - On-Chip Debug System */ +/* OCD.OCDR0 bit masks and bit positions */ +#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ +#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ +#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ +#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ +#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ +#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ +#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ +#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ +#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ +#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ +#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ +#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ +#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ +#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ +#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ +#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ +#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ +#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ + +/* OCD.OCDR1 bit masks and bit positions */ +/* OCD_OCDRD Predefined. */ +/* OCD_OCDRD Predefined. */ + +/* CPU - CPU */ +/* CPU.CCP bit masks and bit positions */ +#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +#define CPU_CCP_gp 0 /* CCP signature group position. */ +#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ + +/* CPU.SREG bit masks and bit positions */ +#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ + +#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +#define CPU_T_bp 6 /* Transfer Bit bit position. */ + +#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +#define CPU_H_bp 5 /* Half Carry Flag bit position. */ + +#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ + +#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ + +#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +#define CPU_N_bp 2 /* Negative Flag bit position. */ + +#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +#define CPU_Z_bp 1 /* Zero Flag bit position. */ + +#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +#define CPU_C_bp 0 /* Carry Flag bit position. */ + +/* CLK - Clock System */ +/* CLK.CTRL bit masks and bit positions */ +#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ +#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ +#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ +#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ +#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ +#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ +#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ +#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ + +/* CLK.PSCTRL bit masks and bit positions */ +#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ +#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ +#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ +#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ +#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ +#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ +#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ +#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ +#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ +#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ +#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ +#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ + +#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ +#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ +#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ +#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ +#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ +#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ + +/* CLK.LOCK bit masks and bit positions */ +#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ +#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ + +/* CLK.RTCCTRL bit masks and bit positions */ +#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ +#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ +#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ +#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ +#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ +#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ +#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ +#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ + +#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ +#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ + +/* PR.PRGEN bit masks and bit positions */ +#define PR_XCL_bm 0x80 /* XMEGA Custom Logic bit mask. */ +#define PR_XCL_bp 7 /* XMEGA Custom Logic bit position. */ + +#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ +#define PR_RTC_bp 2 /* Real-time Counter bit position. */ + +#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ +#define PR_EVSYS_bp 1 /* Event System bit position. */ + +#define PR_EDMA_bm 0x01 /* Enhanced DMA-Controller bit mask. */ +#define PR_EDMA_bp 0 /* Enhanced DMA-Controller bit position. */ + +/* PR.PRPA bit masks and bit positions */ +#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ +#define PR_DAC_bp 2 /* Port A DAC bit position. */ + +#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ +#define PR_ADC_bp 1 /* Port A ADC bit position. */ + +#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ +#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ + +/* PR.PRPC bit masks and bit positions */ +#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ +#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ + +#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ +#define PR_USART0_bp 4 /* Port C USART0 bit position. */ + +#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ +#define PR_SPI_bp 3 /* Port C SPI bit position. */ + +#define PR_HIRES_bm 0x04 /* Port C WEX bit mask. */ +#define PR_HIRES_bp 2 /* Port C WEX bit position. */ + +#define PR_TC5_bm 0x02 /* Port C Timer/Counter5 bit mask. */ +#define PR_TC5_bp 1 /* Port C Timer/Counter5 bit position. */ + +#define PR_TC4_bm 0x01 /* Port C Timer/Counter4 bit mask. */ +#define PR_TC4_bp 0 /* Port C Timer/Counter4 bit position. */ + +/* PR.PRPD bit masks and bit positions */ +/* PR_USART0 Predefined. */ +/* PR_USART0 Predefined. */ + +/* PR_TC5 Predefined. */ +/* PR_TC5 Predefined. */ + +/* SLEEP - Sleep Controller */ +/* SLEEP.CTRL bit masks and bit positions */ +#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ +#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ +#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ +#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ +#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ +#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ +#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ +#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ + +#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ +#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ + +/* OSC - Oscillator */ +/* OSC.CTRL bit masks and bit positions */ +#define OSC_RC8MLPM_bm 0x40 /* Internal 8 MHz RC Low Power Mode Enable bit mask. */ +#define OSC_RC8MLPM_bp 6 /* Internal 8 MHz RC Low Power Mode Enable bit position. */ + +#define OSC_RC8MEN_bm 0x20 /* Internal 8 MHz RC Oscillator Enable bit mask. */ +#define OSC_RC8MEN_bp 5 /* Internal 8 MHz RC Oscillator Enable bit position. */ + +#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ +#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ + +#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ +#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ + +#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ +#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ + +#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ +#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ + +#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ +#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ + +/* OSC.STATUS bit masks and bit positions */ +#define OSC_RC8MRDY_bm 0x20 /* Internal 8 MHz RC Oscillator Ready bit mask. */ +#define OSC_RC8MRDY_bp 5 /* Internal 8 MHz RC Oscillator Ready bit position. */ + +#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ +#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ + +#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ +#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ + +#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ +#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ + +#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ +#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ + +#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ +#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ + +/* OSC.XOSCCTRL bit masks and bit positions */ +#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ +#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ +#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ +#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ +#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ +#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ + +#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ +#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ + +#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ +#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ + +#define OSC_XOSCSEL_gm 0x1F /* External Oscillator Selection and Startup Time group mask. */ +#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ +#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ +#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ +#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ +#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ +#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ +#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ +#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ +#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ +#define OSC_XOSCSEL4_bm (1<<4) /* External Oscillator Selection and Startup Time bit 4 mask. */ +#define OSC_XOSCSEL4_bp 4 /* External Oscillator Selection and Startup Time bit 4 position. */ + +/* OSC.XOSCFAIL bit masks and bit positions */ +#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ +#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ + +#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ +#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ + +#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ +#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ + +#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ +#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ + +/* OSC.PLLCTRL bit masks and bit positions */ +#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ +#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ +#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ +#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ +#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ +#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ + +#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ +#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ + +#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ +#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ +#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ +#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ +#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ +#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ +#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ +#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ +#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ +#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ +#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ +#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ + +/* OSC.DFLLCTRL bit masks and bit positions */ +#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ +#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ +#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ +#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ +#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ +#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ + +/* OSC.RC8MCAL bit masks and bit positions */ +#define OSC_RC8MCAL_gm 0xFF /* Calibration Bits group mask. */ +#define OSC_RC8MCAL_gp 0 /* Calibration Bits group position. */ +#define OSC_RC8MCAL0_bm (1<<0) /* Calibration Bits bit 0 mask. */ +#define OSC_RC8MCAL0_bp 0 /* Calibration Bits bit 0 position. */ +#define OSC_RC8MCAL1_bm (1<<1) /* Calibration Bits bit 1 mask. */ +#define OSC_RC8MCAL1_bp 1 /* Calibration Bits bit 1 position. */ +#define OSC_RC8MCAL2_bm (1<<2) /* Calibration Bits bit 2 mask. */ +#define OSC_RC8MCAL2_bp 2 /* Calibration Bits bit 2 position. */ +#define OSC_RC8MCAL3_bm (1<<3) /* Calibration Bits bit 3 mask. */ +#define OSC_RC8MCAL3_bp 3 /* Calibration Bits bit 3 position. */ +#define OSC_RC8MCAL4_bm (1<<4) /* Calibration Bits bit 4 mask. */ +#define OSC_RC8MCAL4_bp 4 /* Calibration Bits bit 4 position. */ +#define OSC_RC8MCAL5_bm (1<<5) /* Calibration Bits bit 5 mask. */ +#define OSC_RC8MCAL5_bp 5 /* Calibration Bits bit 5 position. */ +#define OSC_RC8MCAL6_bm (1<<6) /* Calibration Bits bit 6 mask. */ +#define OSC_RC8MCAL6_bp 6 /* Calibration Bits bit 6 position. */ +#define OSC_RC8MCAL7_bm (1<<7) /* Calibration Bits bit 7 mask. */ +#define OSC_RC8MCAL7_bp 7 /* Calibration Bits bit 7 position. */ + +/* DFLL - DFLL */ +/* DFLL.CTRL bit masks and bit positions */ +#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ +#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ + +/* DFLL.CALA bit masks and bit positions */ +#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ +#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ +#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ +#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ +#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ +#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ +#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ +#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ +#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ +#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ +#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ +#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ +#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ +#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ +#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ +#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ + +/* DFLL.CALB bit masks and bit positions */ +#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ +#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ +#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ +#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ +#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ +#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ +#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ +#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ +#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ +#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ +#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ +#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ +#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ +#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ + +/* RST - Reset */ +/* RST.STATUS bit masks and bit positions */ +#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ +#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ + +#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ +#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ + +#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ +#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ + +#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ +#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ + +#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ +#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ + +#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ +#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ + +#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ +#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ + +/* RST.CTRL bit masks and bit positions */ +#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ +#define RST_SWRST_bp 0 /* Software Reset bit position. */ + +/* WDT - Watch-Dog Timer */ +/* WDT.CTRL bit masks and bit positions */ +#define WDT_PER_gm 0x3C /* Period group mask. */ +#define WDT_PER_gp 2 /* Period group position. */ +#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ +#define WDT_PER0_bp 2 /* Period bit 0 position. */ +#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ +#define WDT_PER1_bp 3 /* Period bit 1 position. */ +#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ +#define WDT_PER2_bp 4 /* Period bit 2 position. */ +#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ +#define WDT_PER3_bp 5 /* Period bit 3 position. */ + +#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ +#define WDT_ENABLE_bp 1 /* Enable bit position. */ + +#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ +#define WDT_CEN_bp 0 /* Change Enable bit position. */ + +/* WDT.WINCTRL bit masks and bit positions */ +#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ +#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ +#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ +#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ +#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ +#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ +#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ +#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ +#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ +#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ + +#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ +#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ + +#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ +#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ + +/* WDT.STATUS bit masks and bit positions */ +#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ + +/* MCU - MCU Control */ +/* MCU.ANAINIT bit masks and bit positions */ +#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ +#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ +#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ +#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ +#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ +#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ + +/* MCU.EVSYSLOCK bit masks and bit positions */ +#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ +#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ + +#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ +#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ + +/* MCU.WEXLOCK bit masks and bit positions */ +#define MCU_WEXCLOCK_bm 0x01 /* WeX on T/C C4 Lock bit mask. */ +#define MCU_WEXCLOCK_bp 0 /* WeX on T/C C4 Lock bit position. */ + +/* MCU.FAULTLOCK bit masks and bit positions */ +#define MCU_FAULTC5LOCK_bm 0x02 /* Fault on T/C C5 Lock bit mask. */ +#define MCU_FAULTC5LOCK_bp 1 /* Fault on T/C C5 Lock bit position. */ + +#define MCU_FAULTC4LOCK_bm 0x01 /* Fault on T/C C4 Lock bit mask. */ +#define MCU_FAULTC4LOCK_bp 0 /* Fault on T/C C4 Lock bit position. */ + +/* PMIC - Programmable Multi-level Interrupt Controller */ +/* PMIC.STATUS bit masks and bit positions */ +#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ + +#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ +#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ + +#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ +#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ + +#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ +#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ + +/* PMIC.INTPRI bit masks and bit positions */ +#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ +#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ +#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ +#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ +#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ +#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ +#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ +#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ +#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ +#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ +#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ +#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ +#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ +#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ +#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ +#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ +#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ +#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ + +/* PMIC.CTRL bit masks and bit positions */ +#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ +#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ + +#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ + +#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ +#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ + +#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ +#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ + +#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ +#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ + +/* PORTCFG - Port Configuration */ +/* PORTCFG.CLKOUT bit masks and bit positions */ +#define PORTCFG_CLKEVPIN_bm 0x80 /* Clock and Event Output Pin Select bit mask. */ +#define PORTCFG_CLKEVPIN_bp 7 /* Clock and Event Output Pin Select bit position. */ + +#define PORTCFG_RTCOUT_gm 0x60 /* RTC Clock Output Enable group mask. */ +#define PORTCFG_RTCOUT_gp 5 /* RTC Clock Output Enable group position. */ +#define PORTCFG_RTCOUT0_bm (1<<5) /* RTC Clock Output Enable bit 0 mask. */ +#define PORTCFG_RTCOUT0_bp 5 /* RTC Clock Output Enable bit 0 position. */ +#define PORTCFG_RTCOUT1_bm (1<<6) /* RTC Clock Output Enable bit 1 mask. */ +#define PORTCFG_RTCOUT1_bp 6 /* RTC Clock Output Enable bit 1 position. */ + +#define PORTCFG_CLKOUTSEL_gm 0x0C /* Clock Output Select group mask. */ +#define PORTCFG_CLKOUTSEL_gp 2 /* Clock Output Select group position. */ +#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Clock Output Select bit 0 mask. */ +#define PORTCFG_CLKOUTSEL0_bp 2 /* Clock Output Select bit 0 position. */ +#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Clock Output Select bit 1 mask. */ +#define PORTCFG_CLKOUTSEL1_bp 3 /* Clock Output Select bit 1 position. */ + +#define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */ +#define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */ +#define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */ +#define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */ +#define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */ +#define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */ + +/* PORTCFG.ACEVOUT bit masks and bit positions */ +#define PORTCFG_ACOUT_gm 0xC0 /* Analog Comparator Output Port group mask. */ +#define PORTCFG_ACOUT_gp 6 /* Analog Comparator Output Port group position. */ +#define PORTCFG_ACOUT0_bm (1<<6) /* Analog Comparator Output Port bit 0 mask. */ +#define PORTCFG_ACOUT0_bp 6 /* Analog Comparator Output Port bit 0 position. */ +#define PORTCFG_ACOUT1_bm (1<<7) /* Analog Comparator Output Port bit 1 mask. */ +#define PORTCFG_ACOUT1_bp 7 /* Analog Comparator Output Port bit 1 position. */ + +#define PORTCFG_EVOUT_gm 0x30 /* Event Channel Output Port group mask. */ +#define PORTCFG_EVOUT_gp 4 /* Event Channel Output Port group position. */ +#define PORTCFG_EVOUT0_bm (1<<4) /* Event Channel Output Port bit 0 mask. */ +#define PORTCFG_EVOUT0_bp 4 /* Event Channel Output Port bit 0 position. */ +#define PORTCFG_EVOUT1_bm (1<<5) /* Event Channel Output Port bit 1 mask. */ +#define PORTCFG_EVOUT1_bp 5 /* Event Channel Output Port bit 1 position. */ + +#define PORTCFG_EVASYEN_bm 0x08 /* Asynchronous Event Enabled bit mask. */ +#define PORTCFG_EVASYEN_bp 3 /* Asynchronous Event Enabled bit position. */ + +#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Channel Output Selection group mask. */ +#define PORTCFG_EVOUTSEL_gp 0 /* Event Channel Output Selection group position. */ +#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Channel Output Selection bit 0 mask. */ +#define PORTCFG_EVOUTSEL0_bp 0 /* Event Channel Output Selection bit 0 position. */ +#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Channel Output Selection bit 1 mask. */ +#define PORTCFG_EVOUTSEL1_bp 1 /* Event Channel Output Selection bit 1 position. */ +#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Channel Output Selection bit 2 mask. */ +#define PORTCFG_EVOUTSEL2_bp 2 /* Event Channel Output Selection bit 2 position. */ + +/* PORTCFG.SRLCTRL bit masks and bit positions */ +#define PORTCFG_SRLENRA_bm 0x01 /* Slew Rate Limit Enable on PORTA bit mask. */ +#define PORTCFG_SRLENRA_bp 0 /* Slew Rate Limit Enable on PORTA bit position. */ + +#define PORTCFG_SRLENRC_bm 0x04 /* Slew Rate Limit Enable on PORTC bit mask. */ +#define PORTCFG_SRLENRC_bp 2 /* Slew Rate Limit Enable on PORTC bit position. */ + +#define PORTCFG_SRLENRD_bm 0x08 /* Slew Rate Limit Enable on PORTD bit mask. */ +#define PORTCFG_SRLENRD_bp 3 /* Slew Rate Limit Enable on PORTD bit position. */ + +#define PORTCFG_SRLENRR_bm 0x80 /* Slew Rate Limit Enable on PORTR bit mask. */ +#define PORTCFG_SRLENRR_bp 7 /* Slew Rate Limit Enable on PORTR bit position. */ + +/* CRC - Cyclic Redundancy Checker */ +/* CRC.CTRL bit masks and bit positions */ +#define CRC_RESET_gm 0xC0 /* Reset group mask. */ +#define CRC_RESET_gp 6 /* Reset group position. */ +#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ +#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ +#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ +#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ + +#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ +#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ + +#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ +#define CRC_SOURCE_gp 0 /* Input Source group position. */ +#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ +#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ +#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ +#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ +#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ +#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ +#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ +#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ + +/* CRC.STATUS bit masks and bit positions */ +#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ +#define CRC_ZERO_bp 1 /* Zero detection bit position. */ + +#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ +#define CRC_BUSY_bp 0 /* Busy bit position. */ + +/* EDMA - Enhanced DMA Controller */ +/* EDMA.CTRL bit masks and bit positions */ +#define EDMA_ENABLE_bm 0x80 /* Enable bit mask. */ +#define EDMA_ENABLE_bp 7 /* Enable bit position. */ + +#define EDMA_RESET_bm 0x40 /* Software Reset bit mask. */ +#define EDMA_RESET_bp 6 /* Software Reset bit position. */ + +#define EDMA_CHMODE_gm 0x30 /* Channel Mode group mask. */ +#define EDMA_CHMODE_gp 4 /* Channel Mode group position. */ +#define EDMA_CHMODE0_bm (1<<4) /* Channel Mode bit 0 mask. */ +#define EDMA_CHMODE0_bp 4 /* Channel Mode bit 0 position. */ +#define EDMA_CHMODE1_bm (1<<5) /* Channel Mode bit 1 mask. */ +#define EDMA_CHMODE1_bp 5 /* Channel Mode bit 1 position. */ + +#define EDMA_DBUFMODE_gm 0x0C /* Double Buffer Mode group mask. */ +#define EDMA_DBUFMODE_gp 2 /* Double Buffer Mode group position. */ +#define EDMA_DBUFMODE0_bm (1<<2) /* Double Buffer Mode bit 0 mask. */ +#define EDMA_DBUFMODE0_bp 2 /* Double Buffer Mode bit 0 position. */ +#define EDMA_DBUFMODE1_bm (1<<3) /* Double Buffer Mode bit 1 mask. */ +#define EDMA_DBUFMODE1_bp 3 /* Double Buffer Mode bit 1 position. */ + +#define EDMA_PRIMODE_gm 0x03 /* Priority Mode group mask. */ +#define EDMA_PRIMODE_gp 0 /* Priority Mode group position. */ +#define EDMA_PRIMODE0_bm (1<<0) /* Priority Mode bit 0 mask. */ +#define EDMA_PRIMODE0_bp 0 /* Priority Mode bit 0 position. */ +#define EDMA_PRIMODE1_bm (1<<1) /* Priority Mode bit 1 mask. */ +#define EDMA_PRIMODE1_bp 1 /* Priority Mode bit 1 position. */ + +/* EDMA.INTFLAGS bit masks and bit positions */ +#define EDMA_CH3ERRIF_bm 0x80 /* Channel 3 Transaction Error Interrupt Flag bit mask. */ +#define EDMA_CH3ERRIF_bp 7 /* Channel 3 Transaction Error Interrupt Flag bit position. */ + +#define EDMA_CH2ERRIF_bm 0x40 /* Channel 2 Transaction Error Interrupt Flag bit mask. */ +#define EDMA_CH2ERRIF_bp 6 /* Channel 2 Transaction Error Interrupt Flag bit position. */ + +#define EDMA_CH1ERRIF_bm 0x20 /* Channel 1 Transaction Error Interrupt Flag bit mask. */ +#define EDMA_CH1ERRIF_bp 5 /* Channel 1 Transaction Error Interrupt Flag bit position. */ + +#define EDMA_CH0ERRIF_bm 0x10 /* Channel 0 Transaction Error Interrupt Flag bit mask. */ +#define EDMA_CH0ERRIF_bp 4 /* Channel 0 Transaction Error Interrupt Flag bit position. */ + +#define EDMA_CH3TRNFIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ +#define EDMA_CH3TRNFIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ + +#define EDMA_CH2TRNFIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ +#define EDMA_CH2TRNFIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ + +#define EDMA_CH1TRNFIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ +#define EDMA_CH1TRNFIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ + +#define EDMA_CH0TRNFIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ +#define EDMA_CH0TRNFIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ + +/* EDMA.STATUS bit masks and bit positions */ +#define EDMA_CH3BUSY_bm 0x80 /* Channel 3 Busy Flag bit mask. */ +#define EDMA_CH3BUSY_bp 7 /* Channel 3 Busy Flag bit position. */ + +#define EDMA_CH2BUSY_bm 0x40 /* Channel 2 Busy Flag bit mask. */ +#define EDMA_CH2BUSY_bp 6 /* Channel 2 Busy Flag bit position. */ + +#define EDMA_CH1BUSY_bm 0x20 /* Channel 1 Busy Flag bit mask. */ +#define EDMA_CH1BUSY_bp 5 /* Channel 1 Busy Flag bit position. */ + +#define EDMA_CH0BUSY_bm 0x10 /* Channel 0 Busy Flag bit mask. */ +#define EDMA_CH0BUSY_bp 4 /* Channel 0 Busy Flag bit position. */ + +#define EDMA_CH3PEND_bm 0x08 /* Channel 3 Pending Flag bit mask. */ +#define EDMA_CH3PEND_bp 3 /* Channel 3 Pending Flag bit position. */ + +#define EDMA_CH2PEND_bm 0x04 /* Channel 2 Pending Flag bit mask. */ +#define EDMA_CH2PEND_bp 2 /* Channel 2 Pending Flag bit position. */ + +#define EDMA_CH1PEND_bm 0x02 /* Channel 1 Pending Flag bit mask. */ +#define EDMA_CH1PEND_bp 1 /* Channel 1 Pending Flag bit position. */ + +#define EDMA_CH0PEND_bm 0x01 /* Channel 0 Pending Flag bit mask. */ +#define EDMA_CH0PEND_bp 0 /* Channel 0 Pending Flag bit position. */ + +/* EDMA_CH.CTRLA bit masks and bit positions */ +#define EDMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ +#define EDMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ + +#define EDMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ +#define EDMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ + +#define EDMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ +#define EDMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ + +#define EDMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ +#define EDMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ + +#define EDMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ +#define EDMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ + +#define EDMA_CH_BURSTLEN_bm 0x01 /* Channel 2-bytes Burst Length bit mask. */ +#define EDMA_CH_BURSTLEN_bp 0 /* Channel 2-bytes Burst Length bit position. */ + +/* EDMA_CH.CTRLB bit masks and bit positions */ +#define EDMA_CH_CHBUSY_bm 0x80 /* Channel Block Transfer Busy bit mask. */ +#define EDMA_CH_CHBUSY_bp 7 /* Channel Block Transfer Busy bit position. */ + +#define EDMA_CH_CHPEND_bm 0x40 /* Channel Block Transfer Pending bit mask. */ +#define EDMA_CH_CHPEND_bp 6 /* Channel Block Transfer Pending bit position. */ + +#define EDMA_CH_ERRIF_bm 0x20 /* Channel Transaction Error Interrupt Flag bit mask. */ +#define EDMA_CH_ERRIF_bp 5 /* Channel Transaction Error Interrupt Flag bit position. */ + +#define EDMA_CH_TRNIF_bm 0x10 /* Channel Transaction Complete Interrup Flag bit mask. */ +#define EDMA_CH_TRNIF_bp 4 /* Channel Transaction Complete Interrup Flag bit position. */ + +#define EDMA_CH_ERRINTLVL_gm 0x0C /* Channel Transaction Error Interrupt Level group mask. */ +#define EDMA_CH_ERRINTLVL_gp 2 /* Channel Transaction Error Interrupt Level group position. */ +#define EDMA_CH_ERRINTLVL0_bm (1<<2) /* Channel Transaction Error Interrupt Level bit 0 mask. */ +#define EDMA_CH_ERRINTLVL0_bp 2 /* Channel Transaction Error Interrupt Level bit 0 position. */ +#define EDMA_CH_ERRINTLVL1_bm (1<<3) /* Channel Transaction Error Interrupt Level bit 1 mask. */ +#define EDMA_CH_ERRINTLVL1_bp 3 /* Channel Transaction Error Interrupt Level bit 1 position. */ + +#define EDMA_CH_TRNINTLVL_gm 0x03 /* Channel Transaction Complete Interrupt Level group mask. */ +#define EDMA_CH_TRNINTLVL_gp 0 /* Channel Transaction Complete Interrupt Level group position. */ +#define EDMA_CH_TRNINTLVL0_bm (1<<0) /* Channel Transaction Complete Interrupt Level bit 0 mask. */ +#define EDMA_CH_TRNINTLVL0_bp 0 /* Channel Transaction Complete Interrupt Level bit 0 position. */ +#define EDMA_CH_TRNINTLVL1_bm (1<<1) /* Channel Transaction Complete Interrupt Level bit 1 mask. */ +#define EDMA_CH_TRNINTLVL1_bp 1 /* Channel Transaction Complete Interrupt Level bit 1 position. */ + +/* EDMA_CH.ADDRCTRL bit masks and bit positions */ +#define EDMA_CH_RELOAD_gm 0x30 /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. group mask. */ +#define EDMA_CH_RELOAD_gp 4 /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. group position. */ +#define EDMA_CH_RELOAD0_bm (1<<4) /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. bit 0 mask. */ +#define EDMA_CH_RELOAD0_bp 4 /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. bit 0 position. */ +#define EDMA_CH_RELOAD1_bm (1<<5) /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. bit 1 mask. */ +#define EDMA_CH_RELOAD1_bp 5 /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. bit 1 position. */ + +#define EDMA_CH_DIR_gm 0x07 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. group mask. */ +#define EDMA_CH_DIR_gp 0 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. group position. */ +#define EDMA_CH_DIR0_bm (1<<0) /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 0 mask. */ +#define EDMA_CH_DIR0_bp 0 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 0 position. */ +#define EDMA_CH_DIR1_bm (1<<1) /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 1 mask. */ +#define EDMA_CH_DIR1_bp 1 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 1 position. */ +#define EDMA_CH_DIR2_bm (1<<2) /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 2 mask. */ +#define EDMA_CH_DIR2_bp 2 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 2 position. */ + +/* EDMA_CH.DESTADDRCTRL bit masks and bit positions */ +#define EDMA_CH_DESTRELOAD_gm 0x30 /* Destination Address Reload for Standard Channels Only. group mask. */ +#define EDMA_CH_DESTRELOAD_gp 4 /* Destination Address Reload for Standard Channels Only. group position. */ +#define EDMA_CH_DESTRELOAD0_bm (1<<4) /* Destination Address Reload for Standard Channels Only. bit 0 mask. */ +#define EDMA_CH_DESTRELOAD0_bp 4 /* Destination Address Reload for Standard Channels Only. bit 0 position. */ +#define EDMA_CH_DESTRELOAD1_bm (1<<5) /* Destination Address Reload for Standard Channels Only. bit 1 mask. */ +#define EDMA_CH_DESTRELOAD1_bp 5 /* Destination Address Reload for Standard Channels Only. bit 1 position. */ + +#define EDMA_CH_DESTDIR_gm 0x07 /* Destination Address Mode for Standard Channels Only. group mask. */ +#define EDMA_CH_DESTDIR_gp 0 /* Destination Address Mode for Standard Channels Only. group position. */ +#define EDMA_CH_DESTDIR0_bm (1<<0) /* Destination Address Mode for Standard Channels Only. bit 0 mask. */ +#define EDMA_CH_DESTDIR0_bp 0 /* Destination Address Mode for Standard Channels Only. bit 0 position. */ +#define EDMA_CH_DESTDIR1_bm (1<<1) /* Destination Address Mode for Standard Channels Only. bit 1 mask. */ +#define EDMA_CH_DESTDIR1_bp 1 /* Destination Address Mode for Standard Channels Only. bit 1 position. */ +#define EDMA_CH_DESTDIR2_bm (1<<2) /* Destination Address Mode for Standard Channels Only. bit 2 mask. */ +#define EDMA_CH_DESTDIR2_bp 2 /* Destination Address Mode for Standard Channels Only. bit 2 position. */ + +/* EDMA_CH.TRIGSRC bit masks and bit positions */ +#define EDMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ +#define EDMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ +#define EDMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ +#define EDMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ +#define EDMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ +#define EDMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ +#define EDMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ +#define EDMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ +#define EDMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ +#define EDMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ +#define EDMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ +#define EDMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ +#define EDMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ +#define EDMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ +#define EDMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ +#define EDMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ +#define EDMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ +#define EDMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ + +/* EVSYS - Event System */ +/* EVSYS.CH0MUX bit masks and bit positions */ +#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ +#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ +#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ +#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ +#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ +#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ +#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ +#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ +#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ +#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ +#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ +#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ +#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ +#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ +#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ +#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ +#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ +#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ + +/* EVSYS.CH1MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH2MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH3MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH4MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH5MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH6MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH7MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH0CTRL bit masks and bit positions */ +#define EVSYS_ROTARY_bm 0x80 /* Rotary Decoder Enable bit mask. */ +#define EVSYS_ROTARY_bp 7 /* Rotary Decoder Enable bit position. */ + +#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ +#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ +#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ +#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ +#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ +#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ + +#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ +#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ + +#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ +#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ + +#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ +#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ +#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ +#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ +#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ +#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ +#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ +#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ + +/* EVSYS.CH1CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH2CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH3CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH4CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH5CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH6CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH7CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.DFCTRL bit masks and bit positions */ +#define EVSYS_PRESCFILT_gm 0xF0 /* Prescaler Filter group mask. */ +#define EVSYS_PRESCFILT_gp 4 /* Prescaler Filter group position. */ +#define EVSYS_PRESCFILT0_bm (1<<4) /* Prescaler Filter bit 0 mask. */ +#define EVSYS_PRESCFILT0_bp 4 /* Prescaler Filter bit 0 position. */ +#define EVSYS_PRESCFILT1_bm (1<<5) /* Prescaler Filter bit 1 mask. */ +#define EVSYS_PRESCFILT1_bp 5 /* Prescaler Filter bit 1 position. */ +#define EVSYS_PRESCFILT2_bm (1<<6) /* Prescaler Filter bit 2 mask. */ +#define EVSYS_PRESCFILT2_bp 6 /* Prescaler Filter bit 2 position. */ +#define EVSYS_PRESCFILT3_bm (1<<7) /* Prescaler Filter bit 3 mask. */ +#define EVSYS_PRESCFILT3_bp 7 /* Prescaler Filter bit 3 position. */ + +#define EVSYS_FILTSEL_bm 0x08 /* Prescaler Filter Select bit mask. */ +#define EVSYS_FILTSEL_bp 3 /* Prescaler Filter Select bit position. */ + +#define EVSYS_PRESC_gm 0x07 /* Prescaler group mask. */ +#define EVSYS_PRESC_gp 0 /* Prescaler group position. */ +#define EVSYS_PRESC0_bm (1<<0) /* Prescaler bit 0 mask. */ +#define EVSYS_PRESC0_bp 0 /* Prescaler bit 0 position. */ +#define EVSYS_PRESC1_bm (1<<1) /* Prescaler bit 1 mask. */ +#define EVSYS_PRESC1_bp 1 /* Prescaler bit 1 position. */ +#define EVSYS_PRESC2_bm (1<<2) /* Prescaler bit 2 mask. */ +#define EVSYS_PRESC2_bp 2 /* Prescaler bit 2 position. */ + +/* NVM - Non Volatile Memory Controller */ +/* NVM.CMD bit masks and bit positions */ +#define NVM_CMD_gm 0x7F /* Command group mask. */ +#define NVM_CMD_gp 0 /* Command group position. */ +#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define NVM_CMD0_bp 0 /* Command bit 0 position. */ +#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define NVM_CMD1_bp 1 /* Command bit 1 position. */ +#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ +#define NVM_CMD2_bp 2 /* Command bit 2 position. */ +#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ +#define NVM_CMD3_bp 3 /* Command bit 3 position. */ +#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ +#define NVM_CMD4_bp 4 /* Command bit 4 position. */ +#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ +#define NVM_CMD5_bp 5 /* Command bit 5 position. */ +#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ +#define NVM_CMD6_bp 6 /* Command bit 6 position. */ + +/* NVM.CTRLA bit masks and bit positions */ +#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ +#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ + +/* NVM.CTRLB bit masks and bit positions */ +#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ +#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ + +#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ +#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ + +/* NVM.INTCTRL bit masks and bit positions */ +#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ +#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ +#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ +#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ +#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ +#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ + +#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ +#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ +#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ +#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ +#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ +#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ + +/* NVM.STATUS bit masks and bit positions */ +#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ +#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ + +#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ +#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ + +#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ +#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ + +#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ +#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ + +/* NVM.LOCKBITS bit masks and bit positions */ +#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ + +#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ + +#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ + +#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ +#define NVM_LB_gp 0 /* Lock Bits group position. */ +#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ + +/* ADC - Analog/Digital Converter */ +/* ADC_CH.CTRL bit masks and bit positions */ +#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ +#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ + +#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ +#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ +#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ +#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ +#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ +#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ +#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ +#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ + +#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ +#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ +#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ +#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ +#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ +#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ + +/* ADC_CH.MUXCTRL bit masks and bit positions */ +#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC Input group mask. */ +#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC Input group position. */ +#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC Input bit 0 mask. */ +#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC Input bit 0 position. */ +#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC Input bit 1 mask. */ +#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC Input bit 1 position. */ +#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC Input bit 2 mask. */ +#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC Input bit 2 position. */ +#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC Input bit 3 mask. */ +#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC Input bit 3 position. */ + +#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC Input group mask. */ +#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC Input group position. */ +#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC Input bit 0 mask. */ +#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC Input bit 0 position. */ +#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC Input bit 1 mask. */ +#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC Input bit 1 position. */ +#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC Input bit 2 mask. */ +#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC Input bit 2 position. */ +#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC Input bit 3 mask. */ +#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC Input bit 3 position. */ + +#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC Input group mask. */ +#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC Input group position. */ +#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC Input bit 0 mask. */ +#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC Input bit 0 position. */ +#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC Input bit 1 mask. */ +#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC Input bit 1 position. */ + +#define ADC_CH_MUXNEGL_gm 0x03 /* MUX selection on Negative ADC Input Gain on 4 LSB pins group mask. */ +#define ADC_CH_MUXNEGL_gp 0 /* MUX selection on Negative ADC Input Gain on 4 LSB pins group position. */ +#define ADC_CH_MUXNEGL0_bm (1<<0) /* MUX selection on Negative ADC Input Gain on 4 LSB pins bit 0 mask. */ +#define ADC_CH_MUXNEGL0_bp 0 /* MUX selection on Negative ADC Input Gain on 4 LSB pins bit 0 position. */ +#define ADC_CH_MUXNEGL1_bm (1<<1) /* MUX selection on Negative ADC Input Gain on 4 LSB pins bit 1 mask. */ +#define ADC_CH_MUXNEGL1_bp 1 /* MUX selection on Negative ADC Input Gain on 4 LSB pins bit 1 position. */ + +#define ADC_CH_MUXNEGH_gm 0x03 /* MUX selection on Negative ADC Input Gain on 4 MSB pins group mask. */ +#define ADC_CH_MUXNEGH_gp 0 /* MUX selection on Negative ADC Input Gain on 4 MSB pins group position. */ +#define ADC_CH_MUXNEGH0_bm (1<<0) /* MUX selection on Negative ADC Input Gain on 4 MSB pins bit 0 mask. */ +#define ADC_CH_MUXNEGH0_bp 0 /* MUX selection on Negative ADC Input Gain on 4 MSB pins bit 0 position. */ +#define ADC_CH_MUXNEGH1_bm (1<<1) /* MUX selection on Negative ADC Input Gain on 4 MSB pins bit 1 mask. */ +#define ADC_CH_MUXNEGH1_bp 1 /* MUX selection on Negative ADC Input Gain on 4 MSB pins bit 1 position. */ + +/* ADC_CH.INTCTRL bit masks and bit positions */ +#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ +#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ +#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ +#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ +#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ +#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ + +#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ +#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ +#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ +#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ +#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ +#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ + +/* ADC_CH.INTFLAGS bit masks and bit positions */ +#define ADC_CH_IF_bm 0x01 /* Channel Interrupt Flag bit mask. */ +#define ADC_CH_IF_bp 0 /* Channel Interrupt Flag bit position. */ + +/* ADC_CH.SCAN bit masks and bit positions */ +#define ADC_CH_INPUTOFFSET_gm 0xF0 /* Positive MUX Setting Offset group mask. */ +#define ADC_CH_INPUTOFFSET_gp 4 /* Positive MUX Setting Offset group position. */ +#define ADC_CH_INPUTOFFSET0_bm (1<<4) /* Positive MUX Setting Offset bit 0 mask. */ +#define ADC_CH_INPUTOFFSET0_bp 4 /* Positive MUX Setting Offset bit 0 position. */ +#define ADC_CH_INPUTOFFSET1_bm (1<<5) /* Positive MUX Setting Offset bit 1 mask. */ +#define ADC_CH_INPUTOFFSET1_bp 5 /* Positive MUX Setting Offset bit 1 position. */ +#define ADC_CH_INPUTOFFSET2_bm (1<<6) /* Positive MUX Setting Offset bit 2 mask. */ +#define ADC_CH_INPUTOFFSET2_bp 6 /* Positive MUX Setting Offset bit 2 position. */ +#define ADC_CH_INPUTOFFSET3_bm (1<<7) /* Positive MUX Setting Offset bit 3 mask. */ +#define ADC_CH_INPUTOFFSET3_bp 7 /* Positive MUX Setting Offset bit 3 position. */ + +#define ADC_CH_INPUTSCAN_gm 0x0F /* Number of Channels Included in Scan group mask. */ +#define ADC_CH_INPUTSCAN_gp 0 /* Number of Channels Included in Scan group position. */ +#define ADC_CH_INPUTSCAN0_bm (1<<0) /* Number of Channels Included in Scan bit 0 mask. */ +#define ADC_CH_INPUTSCAN0_bp 0 /* Number of Channels Included in Scan bit 0 position. */ +#define ADC_CH_INPUTSCAN1_bm (1<<1) /* Number of Channels Included in Scan bit 1 mask. */ +#define ADC_CH_INPUTSCAN1_bp 1 /* Number of Channels Included in Scan bit 1 position. */ +#define ADC_CH_INPUTSCAN2_bm (1<<2) /* Number of Channels Included in Scan bit 2 mask. */ +#define ADC_CH_INPUTSCAN2_bp 2 /* Number of Channels Included in Scan bit 2 position. */ +#define ADC_CH_INPUTSCAN3_bm (1<<3) /* Number of Channels Included in Scan bit 3 mask. */ +#define ADC_CH_INPUTSCAN3_bp 3 /* Number of Channels Included in Scan bit 3 position. */ + +/* ADC_CH.CORRCTRL bit masks and bit positions */ +#define ADC_CH_CORREN_bm 0x01 /* Correction Enable bit mask. */ +#define ADC_CH_CORREN_bp 0 /* Correction Enable bit position. */ + +/* ADC_CH.OFFSETCORR1 bit masks and bit positions */ +#define ADC_CH_OFFSETCORR_gm 0x0F /* Offset Correction Byte 1 group mask. */ +#define ADC_CH_OFFSETCORR_gp 0 /* Offset Correction Byte 1 group position. */ +#define ADC_CH_OFFSETCORR0_bm (1<<0) /* Offset Correction Byte 1 bit 0 mask. */ +#define ADC_CH_OFFSETCORR0_bp 0 /* Offset Correction Byte 1 bit 0 position. */ +#define ADC_CH_OFFSETCORR1_bm (1<<1) /* Offset Correction Byte 1 bit 1 mask. */ +#define ADC_CH_OFFSETCORR1_bp 1 /* Offset Correction Byte 1 bit 1 position. */ +#define ADC_CH_OFFSETCORR2_bm (1<<2) /* Offset Correction Byte 1 bit 2 mask. */ +#define ADC_CH_OFFSETCORR2_bp 2 /* Offset Correction Byte 1 bit 2 position. */ +#define ADC_CH_OFFSETCORR3_bm (1<<3) /* Offset Correction Byte 1 bit 3 mask. */ +#define ADC_CH_OFFSETCORR3_bp 3 /* Offset Correction Byte 1 bit 3 position. */ + +/* ADC_CH.GAINCORR1 bit masks and bit positions */ +#define ADC_CH_GAINCORR_gm 0x0F /* Gain Correction Byte 1 group mask. */ +#define ADC_CH_GAINCORR_gp 0 /* Gain Correction Byte 1 group position. */ +#define ADC_CH_GAINCORR0_bm (1<<0) /* Gain Correction Byte 1 bit 0 mask. */ +#define ADC_CH_GAINCORR0_bp 0 /* Gain Correction Byte 1 bit 0 position. */ +#define ADC_CH_GAINCORR1_bm (1<<1) /* Gain Correction Byte 1 bit 1 mask. */ +#define ADC_CH_GAINCORR1_bp 1 /* Gain Correction Byte 1 bit 1 position. */ +#define ADC_CH_GAINCORR2_bm (1<<2) /* Gain Correction Byte 1 bit 2 mask. */ +#define ADC_CH_GAINCORR2_bp 2 /* Gain Correction Byte 1 bit 2 position. */ +#define ADC_CH_GAINCORR3_bm (1<<3) /* Gain Correction Byte 1 bit 3 mask. */ +#define ADC_CH_GAINCORR3_bp 3 /* Gain Correction Byte 1 bit 3 position. */ + +/* ADC_CH.AVGCTRL bit masks and bit positions */ +#define ADC_CH_RIGHTSHIFT_gm 0x70 /* Right Shift group mask. */ +#define ADC_CH_RIGHTSHIFT_gp 4 /* Right Shift group position. */ +#define ADC_CH_RIGHTSHIFT0_bm (1<<4) /* Right Shift bit 0 mask. */ +#define ADC_CH_RIGHTSHIFT0_bp 4 /* Right Shift bit 0 position. */ +#define ADC_CH_RIGHTSHIFT1_bm (1<<5) /* Right Shift bit 1 mask. */ +#define ADC_CH_RIGHTSHIFT1_bp 5 /* Right Shift bit 1 position. */ +#define ADC_CH_RIGHTSHIFT2_bm (1<<6) /* Right Shift bit 2 mask. */ +#define ADC_CH_RIGHTSHIFT2_bp 6 /* Right Shift bit 2 position. */ + +#define ADC_CH_SAMPNUM_gm 0x0F /* Averaged Number of Samples group mask. */ +#define ADC_CH_SAMPNUM_gp 0 /* Averaged Number of Samples group position. */ +#define ADC_CH_SAMPNUM0_bm (1<<0) /* Averaged Number of Samples bit 0 mask. */ +#define ADC_CH_SAMPNUM0_bp 0 /* Averaged Number of Samples bit 0 position. */ +#define ADC_CH_SAMPNUM1_bm (1<<1) /* Averaged Number of Samples bit 1 mask. */ +#define ADC_CH_SAMPNUM1_bp 1 /* Averaged Number of Samples bit 1 position. */ +#define ADC_CH_SAMPNUM2_bm (1<<2) /* Averaged Number of Samples bit 2 mask. */ +#define ADC_CH_SAMPNUM2_bp 2 /* Averaged Number of Samples bit 2 position. */ +#define ADC_CH_SAMPNUM3_bm (1<<3) /* Averaged Number of Samples bit 3 mask. */ +#define ADC_CH_SAMPNUM3_bp 3 /* Averaged Number of Samples bit 3 position. */ + +/* ADC.CTRLA bit masks and bit positions */ +#define ADC_START_bm 0x04 /* Start Conversion bit mask. */ +#define ADC_START_bp 2 /* Start Conversion bit position. */ + +#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ +#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ + +#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ +#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ + +/* ADC.CTRLB bit masks and bit positions */ +#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ +#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ +#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ +#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ +#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ +#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ + +#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ +#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ + +#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ +#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ + +#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ +#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ +#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ +#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ +#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ +#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ + +/* ADC.REFCTRL bit masks and bit positions */ +#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ +#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ +#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ +#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ + +#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ +#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ + +#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ +#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ + +/* ADC.EVCTRL bit masks and bit positions */ +#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ +#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ +#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ +#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ +#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ +#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ +#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ +#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ + +#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ +#define ADC_EVACT_gp 0 /* Event Action Select group position. */ +#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ +#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ +#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ +#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ +#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ +#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ + +/* ADC.PRESCALER bit masks and bit positions */ +#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ +#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ +#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ +#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ +#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ +#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ +#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ +#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ + +/* ADC.INTFLAGS bit masks and bit positions */ +#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ +#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ + +/* ADC.SAMPCTRL bit masks and bit positions */ +#define ADC_SAMPVAL_gm 0x3F /* Sampling time control register group mask. */ +#define ADC_SAMPVAL_gp 0 /* Sampling time control register group position. */ +#define ADC_SAMPVAL0_bm (1<<0) /* Sampling time control register bit 0 mask. */ +#define ADC_SAMPVAL0_bp 0 /* Sampling time control register bit 0 position. */ +#define ADC_SAMPVAL1_bm (1<<1) /* Sampling time control register bit 1 mask. */ +#define ADC_SAMPVAL1_bp 1 /* Sampling time control register bit 1 position. */ +#define ADC_SAMPVAL2_bm (1<<2) /* Sampling time control register bit 2 mask. */ +#define ADC_SAMPVAL2_bp 2 /* Sampling time control register bit 2 position. */ +#define ADC_SAMPVAL3_bm (1<<3) /* Sampling time control register bit 3 mask. */ +#define ADC_SAMPVAL3_bp 3 /* Sampling time control register bit 3 position. */ +#define ADC_SAMPVAL4_bm (1<<4) /* Sampling time control register bit 4 mask. */ +#define ADC_SAMPVAL4_bp 4 /* Sampling time control register bit 4 position. */ +#define ADC_SAMPVAL5_bm (1<<5) /* Sampling time control register bit 5 mask. */ +#define ADC_SAMPVAL5_bp 5 /* Sampling time control register bit 5 position. */ + +/* DAC - Digital/Analog Converter */ +/* DAC.CTRLA bit masks and bit positions */ +#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ +#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ + +#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ +#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ + +#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ +#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ + +#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ +#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ + +#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define DAC_ENABLE_bp 0 /* Enable bit position. */ + +/* DAC.CTRLB bit masks and bit positions */ +#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ +#define DAC_CHSEL_gp 5 /* Channel Select group position. */ +#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ +#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ +#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ +#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ + +#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ +#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ + +#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ +#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ + +/* DAC.CTRLC bit masks and bit positions */ +#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ +#define DAC_REFSEL_gp 3 /* Reference Select group position. */ +#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ +#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ +#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ +#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ + +#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ +#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ + +/* DAC.EVCTRL bit masks and bit positions */ +#define DAC_EVSPLIT_bm 0x08 /* Separate Event Channel Input for Channel 1 bit mask. */ +#define DAC_EVSPLIT_bp 3 /* Separate Event Channel Input for Channel 1 bit position. */ + +#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ +#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ +#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ +#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ +#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ +#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ +#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ +#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ + +/* DAC.STATUS bit masks and bit positions */ +#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ +#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ + +#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ +#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ + +/* DAC.CH0GAINCAL bit masks and bit positions */ +#define DAC_CH0GAINCAL_gm 0x7F /* Gain Calibration group mask. */ +#define DAC_CH0GAINCAL_gp 0 /* Gain Calibration group position. */ +#define DAC_CH0GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ +#define DAC_CH0GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ +#define DAC_CH0GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ +#define DAC_CH0GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ +#define DAC_CH0GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ +#define DAC_CH0GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ +#define DAC_CH0GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ +#define DAC_CH0GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ +#define DAC_CH0GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ +#define DAC_CH0GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ +#define DAC_CH0GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ +#define DAC_CH0GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ +#define DAC_CH0GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ +#define DAC_CH0GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ + +/* DAC.CH0OFFSETCAL bit masks and bit positions */ +#define DAC_CH0OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ +#define DAC_CH0OFFSETCAL_gp 0 /* Offset Calibration group position. */ +#define DAC_CH0OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ +#define DAC_CH0OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ +#define DAC_CH0OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ +#define DAC_CH0OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ +#define DAC_CH0OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ +#define DAC_CH0OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ +#define DAC_CH0OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ +#define DAC_CH0OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ +#define DAC_CH0OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ +#define DAC_CH0OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ +#define DAC_CH0OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ +#define DAC_CH0OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ +#define DAC_CH0OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ +#define DAC_CH0OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ + +/* DAC.CH1GAINCAL bit masks and bit positions */ +#define DAC_CH1GAINCAL_gm 0x7F /* Gain Calibration group mask. */ +#define DAC_CH1GAINCAL_gp 0 /* Gain Calibration group position. */ +#define DAC_CH1GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ +#define DAC_CH1GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ +#define DAC_CH1GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ +#define DAC_CH1GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ +#define DAC_CH1GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ +#define DAC_CH1GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ +#define DAC_CH1GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ +#define DAC_CH1GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ +#define DAC_CH1GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ +#define DAC_CH1GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ +#define DAC_CH1GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ +#define DAC_CH1GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ +#define DAC_CH1GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ +#define DAC_CH1GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ + +/* DAC.CH1OFFSETCAL bit masks and bit positions */ +#define DAC_CH1OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ +#define DAC_CH1OFFSETCAL_gp 0 /* Offset Calibration group position. */ +#define DAC_CH1OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ +#define DAC_CH1OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ +#define DAC_CH1OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ +#define DAC_CH1OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ +#define DAC_CH1OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ +#define DAC_CH1OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ +#define DAC_CH1OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ +#define DAC_CH1OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ +#define DAC_CH1OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ +#define DAC_CH1OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ +#define DAC_CH1OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ +#define DAC_CH1OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ +#define DAC_CH1OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ +#define DAC_CH1OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ + +/* AC - Analog Comparator */ +/* AC.AC0CTRL bit masks and bit positions */ +#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ +#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ +#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ +#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ +#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ +#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ + +#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ +#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ +#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ +#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ +#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ +#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ + +#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ + +#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define AC_ENABLE_bp 0 /* Enable bit position. */ + +/* AC.AC1CTRL bit masks and bit positions */ +/* AC_INTMODE Predefined. */ +/* AC_INTMODE Predefined. */ + +/* AC_INTLVL Predefined. */ +/* AC_INTLVL Predefined. */ + +/* AC_HYSMODE Predefined. */ +/* AC_HYSMODE Predefined. */ + +/* AC_ENABLE Predefined. */ +/* AC_ENABLE Predefined. */ + +/* AC.AC0MUXCTRL bit masks and bit positions */ +#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ +#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ +#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ +#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ +#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ +#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ +#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ +#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ + +#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ +#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ +#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ +#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ +#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ +#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ +#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ +#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ + +/* AC.AC1MUXCTRL bit masks and bit positions */ +/* AC_MUXPOS Predefined. */ +/* AC_MUXPOS Predefined. */ + +/* AC_MUXNEG Predefined. */ +/* AC_MUXNEG Predefined. */ + +/* AC.CTRLA bit masks and bit positions */ +#define AC_AC1INVEN_bm 0x08 /* Analog Comparator 1 Output Invert Enable bit mask. */ +#define AC_AC1INVEN_bp 3 /* Analog Comparator 1 Output Invert Enable bit position. */ + +#define AC_AC0INVEN_bm 0x04 /* Analog Comparator 0 Output Invert Enable bit mask. */ +#define AC_AC0INVEN_bp 2 /* Analog Comparator 0 Output Invert Enable bit position. */ + +#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ +#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ + +#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ +#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ + +/* AC.CTRLB bit masks and bit positions */ +#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ +#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ +#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ +#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ +#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ +#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ +#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ +#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ +#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ +#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ +#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ +#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ +#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ +#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ + +/* AC.WINCTRL bit masks and bit positions */ +#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ +#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ + +#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ +#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ +#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ +#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ +#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ +#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ + +#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ +#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ +#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ +#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ +#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ +#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ + +/* AC.STATUS bit masks and bit positions */ +#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ +#define AC_WSTATE_gp 6 /* Window Mode State group position. */ +#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ +#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ +#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ +#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ + +#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ +#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ + +#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ +#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ + +#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ +#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ + +#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ +#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ + +#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ +#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ + +/* AC.CURRCTRL bit masks and bit positions */ +#define AC_CURREN_bm 0x80 /* Current Source Enable bit mask. */ +#define AC_CURREN_bp 7 /* Current Source Enable bit position. */ + +#define AC_CURRMODE_bm 0x40 /* Current Mode bit mask. */ +#define AC_CURRMODE_bp 6 /* Current Mode bit position. */ + +#define AC_AC1CURR_bm 0x02 /* Analog Comparator 1 current source output bit mask. */ +#define AC_AC1CURR_bp 1 /* Analog Comparator 1 current source output bit position. */ + +#define AC_AC0CURR_bm 0x01 /* Analog Comparator 0 current source output bit mask. */ +#define AC_AC0CURR_bp 0 /* Analog Comparator 0 current source output bit position. */ + +/* AC.CURRCALIB bit masks and bit positions */ +#define AC_CALIB_gm 0x0F /* Current Source Calibration group mask. */ +#define AC_CALIB_gp 0 /* Current Source Calibration group position. */ +#define AC_CALIB0_bm (1<<0) /* Current Source Calibration bit 0 mask. */ +#define AC_CALIB0_bp 0 /* Current Source Calibration bit 0 position. */ +#define AC_CALIB1_bm (1<<1) /* Current Source Calibration bit 1 mask. */ +#define AC_CALIB1_bp 1 /* Current Source Calibration bit 1 position. */ +#define AC_CALIB2_bm (1<<2) /* Current Source Calibration bit 2 mask. */ +#define AC_CALIB2_bp 2 /* Current Source Calibration bit 2 position. */ +#define AC_CALIB3_bm (1<<3) /* Current Source Calibration bit 3 mask. */ +#define AC_CALIB3_bp 3 /* Current Source Calibration bit 3 position. */ + +/* RTC - Real-Time Clounter */ +/* RTC.CTRL bit masks and bit positions */ +#define RTC_CORREN_bm 0x08 /* Correction Enable bit mask. */ +#define RTC_CORREN_bp 3 /* Correction Enable bit position. */ + +#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ +#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ +#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ +#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ +#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ +#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ +#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ +#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ + +/* RTC.STATUS bit masks and bit positions */ +#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ +#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ + +/* RTC.INTCTRL bit masks and bit positions */ +#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ +#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ +#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ +#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ +#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ +#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ + +#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ +#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ +#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ +#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ +#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ +#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ + +/* RTC.INTFLAGS bit masks and bit positions */ +#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ +#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ + +#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + +/* RTC.CALIB bit masks and bit positions */ +#define RTC_SIGN_bm 0x80 /* Correction Sign bit mask. */ +#define RTC_SIGN_bp 7 /* Correction Sign bit position. */ + +#define RTC_ERROR_gm 0x7F /* Error Value group mask. */ +#define RTC_ERROR_gp 0 /* Error Value group position. */ +#define RTC_ERROR0_bm (1<<0) /* Error Value bit 0 mask. */ +#define RTC_ERROR0_bp 0 /* Error Value bit 0 position. */ +#define RTC_ERROR1_bm (1<<1) /* Error Value bit 1 mask. */ +#define RTC_ERROR1_bp 1 /* Error Value bit 1 position. */ +#define RTC_ERROR2_bm (1<<2) /* Error Value bit 2 mask. */ +#define RTC_ERROR2_bp 2 /* Error Value bit 2 position. */ +#define RTC_ERROR3_bm (1<<3) /* Error Value bit 3 mask. */ +#define RTC_ERROR3_bp 3 /* Error Value bit 3 position. */ +#define RTC_ERROR4_bm (1<<4) /* Error Value bit 4 mask. */ +#define RTC_ERROR4_bp 4 /* Error Value bit 4 position. */ +#define RTC_ERROR5_bm (1<<5) /* Error Value bit 5 mask. */ +#define RTC_ERROR5_bp 5 /* Error Value bit 5 position. */ +#define RTC_ERROR6_bm (1<<6) /* Error Value bit 6 mask. */ +#define RTC_ERROR6_bp 6 /* Error Value bit 6 position. */ + +/* XCL - XMEGA Custom Logic */ +/* XCL.CTRLA bit masks and bit positions */ +#define XCL_LUT0OUTEN_gm 0xC0 /* LUT0 Output Enable group mask. */ +#define XCL_LUT0OUTEN_gp 6 /* LUT0 Output Enable group position. */ +#define XCL_LUT0OUTEN0_bm (1<<6) /* LUT0 Output Enable bit 0 mask. */ +#define XCL_LUT0OUTEN0_bp 6 /* LUT0 Output Enable bit 0 position. */ +#define XCL_LUT0OUTEN1_bm (1<<7) /* LUT0 Output Enable bit 1 mask. */ +#define XCL_LUT0OUTEN1_bp 7 /* LUT0 Output Enable bit 1 position. */ + +#define XCL_PORTSEL_gm 0x30 /* Port Selection group mask. */ +#define XCL_PORTSEL_gp 4 /* Port Selection group position. */ +#define XCL_PORTSEL0_bm (1<<4) /* Port Selection bit 0 mask. */ +#define XCL_PORTSEL0_bp 4 /* Port Selection bit 0 position. */ +#define XCL_PORTSEL1_bm (1<<5) /* Port Selection bit 1 mask. */ +#define XCL_PORTSEL1_bp 5 /* Port Selection bit 1 position. */ + +#define XCL_LUTCONF_gm 0x07 /* LUT Configuration group mask. */ +#define XCL_LUTCONF_gp 0 /* LUT Configuration group position. */ +#define XCL_LUTCONF0_bm (1<<0) /* LUT Configuration bit 0 mask. */ +#define XCL_LUTCONF0_bp 0 /* LUT Configuration bit 0 position. */ +#define XCL_LUTCONF1_bm (1<<1) /* LUT Configuration bit 1 mask. */ +#define XCL_LUTCONF1_bp 1 /* LUT Configuration bit 1 position. */ +#define XCL_LUTCONF2_bm (1<<2) /* LUT Configuration bit 2 mask. */ +#define XCL_LUTCONF2_bp 2 /* LUT Configuration bit 2 position. */ + +/* XCL.CTRLB bit masks and bit positions */ +#define XCL_IN3SEL_gm 0xC0 /* Input Selection 3 group mask. */ +#define XCL_IN3SEL_gp 6 /* Input Selection 3 group position. */ +#define XCL_IN3SEL0_bm (1<<6) /* Input Selection 3 bit 0 mask. */ +#define XCL_IN3SEL0_bp 6 /* Input Selection 3 bit 0 position. */ +#define XCL_IN3SEL1_bm (1<<7) /* Input Selection 3 bit 1 mask. */ +#define XCL_IN3SEL1_bp 7 /* Input Selection 3 bit 1 position. */ + +#define XCL_IN2SEL_gm 0x30 /* Input Selection 2 group mask. */ +#define XCL_IN2SEL_gp 4 /* Input Selection 2 group position. */ +#define XCL_IN2SEL0_bm (1<<4) /* Input Selection 2 bit 0 mask. */ +#define XCL_IN2SEL0_bp 4 /* Input Selection 2 bit 0 position. */ +#define XCL_IN2SEL1_bm (1<<5) /* Input Selection 2 bit 1 mask. */ +#define XCL_IN2SEL1_bp 5 /* Input Selection 2 bit 1 position. */ + +#define XCL_IN1SEL_gm 0x0C /* Input Selection 1 group mask. */ +#define XCL_IN1SEL_gp 2 /* Input Selection 1 group position. */ +#define XCL_IN1SEL0_bm (1<<2) /* Input Selection 1 bit 0 mask. */ +#define XCL_IN1SEL0_bp 2 /* Input Selection 1 bit 0 position. */ +#define XCL_IN1SEL1_bm (1<<3) /* Input Selection 1 bit 1 mask. */ +#define XCL_IN1SEL1_bp 3 /* Input Selection 1 bit 1 position. */ + +#define XCL_IN0SEL_gm 0x03 /* Input Selection 0 group mask. */ +#define XCL_IN0SEL_gp 0 /* Input Selection 0 group position. */ +#define XCL_IN0SEL0_bm (1<<0) /* Input Selection 0 bit 0 mask. */ +#define XCL_IN0SEL0_bp 0 /* Input Selection 0 bit 0 position. */ +#define XCL_IN0SEL1_bm (1<<1) /* Input Selection 0 bit 1 mask. */ +#define XCL_IN0SEL1_bp 1 /* Input Selection 0 bit 1 position. */ + +/* XCL.CTRLC bit masks and bit positions */ +#define XCL_EVASYSEL1_bm 0x80 /* Asynchronous Event Line Selection for LUT1 bit mask. */ +#define XCL_EVASYSEL1_bp 7 /* Asynchronous Event Line Selection for LUT1 bit position. */ + +#define XCL_EVASYSEL0_bm 0x40 /* Asynchronous Event Line Selection for LUT0 bit mask. */ +#define XCL_EVASYSEL0_bp 6 /* Asynchronous Event Line Selection for LUT0 bit position. */ + +#define XCL_DLYSEL_gm 0x30 /* Delay Selection group mask. */ +#define XCL_DLYSEL_gp 4 /* Delay Selection group position. */ +#define XCL_DLYSEL0_bm (1<<4) /* Delay Selection bit 0 mask. */ +#define XCL_DLYSEL0_bp 4 /* Delay Selection bit 0 position. */ +#define XCL_DLYSEL1_bm (1<<5) /* Delay Selection bit 1 mask. */ +#define XCL_DLYSEL1_bp 5 /* Delay Selection bit 1 position. */ + +#define XCL_DLY1CONF_gm 0x0C /* Delay Configuration on LUT1 group mask. */ +#define XCL_DLY1CONF_gp 2 /* Delay Configuration on LUT1 group position. */ +#define XCL_DLY1CONF0_bm (1<<2) /* Delay Configuration on LUT1 bit 0 mask. */ +#define XCL_DLY1CONF0_bp 2 /* Delay Configuration on LUT1 bit 0 position. */ +#define XCL_DLY1CONF1_bm (1<<3) /* Delay Configuration on LUT1 bit 1 mask. */ +#define XCL_DLY1CONF1_bp 3 /* Delay Configuration on LUT1 bit 1 position. */ + +#define XCL_DLY0CONF_gm 0x03 /* Delay Configuration on LUT0 group mask. */ +#define XCL_DLY0CONF_gp 0 /* Delay Configuration on LUT0 group position. */ +#define XCL_DLY0CONF0_bm (1<<0) /* Delay Configuration on LUT0 bit 0 mask. */ +#define XCL_DLY0CONF0_bp 0 /* Delay Configuration on LUT0 bit 0 position. */ +#define XCL_DLY0CONF1_bm (1<<1) /* Delay Configuration on LUT0 bit 1 mask. */ +#define XCL_DLY0CONF1_bp 1 /* Delay Configuration on LUT0 bit 1 position. */ + +/* XCL.CTRLD bit masks and bit positions */ +#define XCL_TRUTH1_gm 0xF0 /* Truth Table of LUT1 group mask. */ +#define XCL_TRUTH1_gp 4 /* Truth Table of LUT1 group position. */ +#define XCL_TRUTH10_bm (1<<4) /* Truth Table of LUT1 bit 0 mask. */ +#define XCL_TRUTH10_bp 4 /* Truth Table of LUT1 bit 0 position. */ +#define XCL_TRUTH11_bm (1<<5) /* Truth Table of LUT1 bit 1 mask. */ +#define XCL_TRUTH11_bp 5 /* Truth Table of LUT1 bit 1 position. */ +#define XCL_TRUTH12_bm (1<<6) /* Truth Table of LUT1 bit 2 mask. */ +#define XCL_TRUTH12_bp 6 /* Truth Table of LUT1 bit 2 position. */ +#define XCL_TRUTH13_bm (1<<7) /* Truth Table of LUT1 bit 3 mask. */ +#define XCL_TRUTH13_bp 7 /* Truth Table of LUT1 bit 3 position. */ + +#define XCL_TRUTH0_gm 0x0F /* Truth Table of LUT0 group mask. */ +#define XCL_TRUTH0_gp 0 /* Truth Table of LUT0 group position. */ +#define XCL_TRUTH00_bm (1<<0) /* Truth Table of LUT0 bit 0 mask. */ +#define XCL_TRUTH00_bp 0 /* Truth Table of LUT0 bit 0 position. */ +#define XCL_TRUTH01_bm (1<<1) /* Truth Table of LUT0 bit 1 mask. */ +#define XCL_TRUTH01_bp 1 /* Truth Table of LUT0 bit 1 position. */ +#define XCL_TRUTH02_bm (1<<2) /* Truth Table of LUT0 bit 2 mask. */ +#define XCL_TRUTH02_bp 2 /* Truth Table of LUT0 bit 2 position. */ +#define XCL_TRUTH03_bm (1<<3) /* Truth Table of LUT0 bit 3 mask. */ +#define XCL_TRUTH03_bp 3 /* Truth Table of LUT0 bit 3 position. */ + +/* XCL.CTRLE bit masks and bit positions */ +#define XCL_CMDSEL_bm 0x80 /* Timer/Counter Command Selection bit mask. */ +#define XCL_CMDSEL_bp 7 /* Timer/Counter Command Selection bit position. */ + +#define XCL_TCSEL_gm 0x70 /* Timer/Counter Selection group mask. */ +#define XCL_TCSEL_gp 4 /* Timer/Counter Selection group position. */ +#define XCL_TCSEL0_bm (1<<4) /* Timer/Counter Selection bit 0 mask. */ +#define XCL_TCSEL0_bp 4 /* Timer/Counter Selection bit 0 position. */ +#define XCL_TCSEL1_bm (1<<5) /* Timer/Counter Selection bit 1 mask. */ +#define XCL_TCSEL1_bp 5 /* Timer/Counter Selection bit 1 position. */ +#define XCL_TCSEL2_bm (1<<6) /* Timer/Counter Selection bit 2 mask. */ +#define XCL_TCSEL2_bp 6 /* Timer/Counter Selection bit 2 position. */ + +#define XCL_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define XCL_CLKSEL_gp 0 /* Clock Selection group position. */ +#define XCL_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define XCL_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define XCL_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define XCL_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define XCL_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define XCL_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define XCL_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define XCL_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + +/* XCL.CTRLF bit masks and bit positions */ +#define XCL_CMDEN_gm 0xC0 /* Command Enable group mask. */ +#define XCL_CMDEN_gp 6 /* Command Enable group position. */ +#define XCL_CMDEN0_bm (1<<6) /* Command Enable bit 0 mask. */ +#define XCL_CMDEN0_bp 6 /* Command Enable bit 0 position. */ +#define XCL_CMDEN1_bm (1<<7) /* Command Enable bit 1 mask. */ +#define XCL_CMDEN1_bp 7 /* Command Enable bit 1 position. */ + +#define XCL_CMP1_bm 0x20 /* Compare Channel 1 Output Value bit mask. */ +#define XCL_CMP1_bp 5 /* Compare Channel 1 Output Value bit position. */ + +#define XCL_CMP0_bm 0x10 /* Compare Channel 0 Output Value bit mask. */ +#define XCL_CMP0_bp 4 /* Compare Channel 0 Output Value bit position. */ + +#define XCL_CCEN1_bm 0x08 /* Compare or Capture Channel 1 Enable bit mask. */ +#define XCL_CCEN1_bp 3 /* Compare or Capture Channel 1 Enable bit position. */ + +#define XCL_CCEN0_bm 0x04 /* Compare or Capture Channel 0 Enable bit mask. */ +#define XCL_CCEN0_bp 2 /* Compare or Capture Channel 0 Enable bit position. */ + +#define XCL_MODE_gm 0x03 /* Timer/Counter Mode group mask. */ +#define XCL_MODE_gp 0 /* Timer/Counter Mode group position. */ +#define XCL_MODE0_bm (1<<0) /* Timer/Counter Mode bit 0 mask. */ +#define XCL_MODE0_bp 0 /* Timer/Counter Mode bit 0 position. */ +#define XCL_MODE1_bm (1<<1) /* Timer/Counter Mode bit 1 mask. */ +#define XCL_MODE1_bp 1 /* Timer/Counter Mode bit 1 position. */ + +/* XCL.CTRLG bit masks and bit positions */ +#define XCL_EVACTEN_bm 0x80 /* Event Action Enable bit mask. */ +#define XCL_EVACTEN_bp 7 /* Event Action Enable bit position. */ + +#define XCL_EVACT1_gm 0x60 /* Event Action Selection on Timer/Counter 1 group mask. */ +#define XCL_EVACT1_gp 5 /* Event Action Selection on Timer/Counter 1 group position. */ +#define XCL_EVACT10_bm (1<<5) /* Event Action Selection on Timer/Counter 1 bit 0 mask. */ +#define XCL_EVACT10_bp 5 /* Event Action Selection on Timer/Counter 1 bit 0 position. */ +#define XCL_EVACT11_bm (1<<6) /* Event Action Selection on Timer/Counter 1 bit 1 mask. */ +#define XCL_EVACT11_bp 6 /* Event Action Selection on Timer/Counter 1 bit 1 position. */ + +#define XCL_EVACT0_gm 0x18 /* Event Action Selection on Timer/Counter 0 group mask. */ +#define XCL_EVACT0_gp 3 /* Event Action Selection on Timer/Counter 0 group position. */ +#define XCL_EVACT00_bm (1<<3) /* Event Action Selection on Timer/Counter 0 bit 0 mask. */ +#define XCL_EVACT00_bp 3 /* Event Action Selection on Timer/Counter 0 bit 0 position. */ +#define XCL_EVACT01_bm (1<<4) /* Event Action Selection on Timer/Counter 0 bit 1 mask. */ +#define XCL_EVACT01_bp 4 /* Event Action Selection on Timer/Counter 0 bit 1 position. */ + +#define XCL_EVSRC_gm 0x07 /* Event Source Selection group mask. */ +#define XCL_EVSRC_gp 0 /* Event Source Selection group position. */ +#define XCL_EVSRC0_bm (1<<0) /* Event Source Selection bit 0 mask. */ +#define XCL_EVSRC0_bp 0 /* Event Source Selection bit 0 position. */ +#define XCL_EVSRC1_bm (1<<1) /* Event Source Selection bit 1 mask. */ +#define XCL_EVSRC1_bp 1 /* Event Source Selection bit 1 position. */ +#define XCL_EVSRC2_bm (1<<2) /* Event Source Selection bit 2 mask. */ +#define XCL_EVSRC2_bp 2 /* Event Source Selection bit 2 position. */ + +/* XCL.INTCTRL bit masks and bit positions */ +#define XCL_UNF1IE_bm 0x80 /* Underflow 1 Interrupt Enable bit mask. */ +#define XCL_UNF1IE_bp 7 /* Underflow 1 Interrupt Enable bit position. */ + +#define XCL_PEC1IE_bm 0x80 /* Peripheral Counter 1 Interrupt Enable bit mask. */ +#define XCL_PEC1IE_bp 7 /* Peripheral Counter 1 Interrupt Enable bit position. */ + +#define XCL_PEC21IE_bm 0x80 /* Peripheral High Counter 2 Interrupt Enable bit mask. */ +#define XCL_PEC21IE_bp 7 /* Peripheral High Counter 2 Interrupt Enable bit position. */ + +#define XCL_UNF0IE_bm 0x40 /* Underflow 0 Interrupt Enable bit mask. */ +#define XCL_UNF0IE_bp 6 /* Underflow 0 Interrupt Enable bit position. */ + +#define XCL_PEC0IE_bm 0x40 /* Peripheral Counter 0 Interrupt Enable bit mask. */ +#define XCL_PEC0IE_bp 6 /* Peripheral Counter 0 Interrupt Enable bit position. */ + +#define XCL_CC1IE_bm 0x20 /* Compare Or Capture 1 Interrupt Enable bit mask. */ +#define XCL_CC1IE_bp 5 /* Compare Or Capture 1 Interrupt Enable bit position. */ + +#define XCL_PEC20IE_bm 0x20 /* Peripheral Low Counter 2 Interrupt Enable bit mask. */ +#define XCL_PEC20IE_bp 5 /* Peripheral Low Counter 2 Interrupt Enable bit position. */ + +#define XCL_CC0IE_bm 0x10 /* Compare Or Capture 0 Interrupt Enable bit mask. */ +#define XCL_CC0IE_bp 4 /* Compare Or Capture 0 Interrupt Enable bit position. */ + +#define XCL_UNFINTLVL_gm 0x0C /* Timer Underflow Interrupt Level group mask. */ +#define XCL_UNFINTLVL_gp 2 /* Timer Underflow Interrupt Level group position. */ +#define XCL_UNFINTLVL0_bm (1<<2) /* Timer Underflow Interrupt Level bit 0 mask. */ +#define XCL_UNFINTLVL0_bp 2 /* Timer Underflow Interrupt Level bit 0 position. */ +#define XCL_UNFINTLVL1_bm (1<<3) /* Timer Underflow Interrupt Level bit 1 mask. */ +#define XCL_UNFINTLVL1_bp 3 /* Timer Underflow Interrupt Level bit 1 position. */ + +#define XCL_CCINTLVL_gm 0x03 /* Timer Compare or Capture Interrupt Level group mask. */ +#define XCL_CCINTLVL_gp 0 /* Timer Compare or Capture Interrupt Level group position. */ +#define XCL_CCINTLVL0_bm (1<<0) /* Timer Compare or Capture Interrupt Level bit 0 mask. */ +#define XCL_CCINTLVL0_bp 0 /* Timer Compare or Capture Interrupt Level bit 0 position. */ +#define XCL_CCINTLVL1_bm (1<<1) /* Timer Compare or Capture Interrupt Level bit 1 mask. */ +#define XCL_CCINTLVL1_bp 1 /* Timer Compare or Capture Interrupt Level bit 1 position. */ + +/* XCL.INTFLAGS bit masks and bit positions */ +#define XCL_UNF1IF_bm 0x80 /* Timer/Counter 1 Underflow Interrupt Flag bit mask. */ +#define XCL_UNF1IF_bp 7 /* Timer/Counter 1 Underflow Interrupt Flag bit position. */ + +#define XCL_PEC1IF_bm 0x80 /* Peripheral Counter 1 Interrupt Flag bit mask. */ +#define XCL_PEC1IF_bp 7 /* Peripheral Counter 1 Interrupt Flag bit position. */ + +#define XCL_PEC21IF_bm 0x80 /* Peripheral High Counter 2 Interrupt Flag bit mask. */ +#define XCL_PEC21IF_bp 7 /* Peripheral High Counter 2 Interrupt Flag bit position. */ + +#define XCL_UNF0IF_bm 0x40 /* Timer/Counter 0 Underflow Interrupt Flag bit mask. */ +#define XCL_UNF0IF_bp 6 /* Timer/Counter 0 Underflow Interrupt Flag bit position. */ + +#define XCL_PEC0IF_bm 0x40 /* Peripheral Counter 0 Interrupt Flag bit mask. */ +#define XCL_PEC0IF_bp 6 /* Peripheral Counter 0 Interrupt Flag bit position. */ + +#define XCL_CC1IF_bm 0x20 /* Compare or Capture Channel 1 Interrupt Flag bit mask. */ +#define XCL_CC1IF_bp 5 /* Compare or Capture Channel 1 Interrupt Flag bit position. */ + +#define XCL_PEC20IF_bm 0x20 /* Peripheral Low Counter 2 Interrupt Flag bit mask. */ +#define XCL_PEC20IF_bp 5 /* Peripheral Low Counter 2 Interrupt Flag bit position. */ + +#define XCL_CC0IF_bm 0x10 /* Compare or Capture Channel 0 Interrupt Flag bit mask. */ +#define XCL_CC0IF_bp 4 /* Compare or Capture Channel 0 Interrupt Flag bit position. */ + +/* XCL.PLC bit masks and bit positions */ +#define XCL_PLC_gm 0xFF /* Peripheral Lenght Control Bits group mask. */ +#define XCL_PLC_gp 0 /* Peripheral Lenght Control Bits group position. */ +#define XCL_PLC0_bm (1<<0) /* Peripheral Lenght Control Bits bit 0 mask. */ +#define XCL_PLC0_bp 0 /* Peripheral Lenght Control Bits bit 0 position. */ +#define XCL_PLC1_bm (1<<1) /* Peripheral Lenght Control Bits bit 1 mask. */ +#define XCL_PLC1_bp 1 /* Peripheral Lenght Control Bits bit 1 position. */ +#define XCL_PLC2_bm (1<<2) /* Peripheral Lenght Control Bits bit 2 mask. */ +#define XCL_PLC2_bp 2 /* Peripheral Lenght Control Bits bit 2 position. */ +#define XCL_PLC3_bm (1<<3) /* Peripheral Lenght Control Bits bit 3 mask. */ +#define XCL_PLC3_bp 3 /* Peripheral Lenght Control Bits bit 3 position. */ +#define XCL_PLC4_bm (1<<4) /* Peripheral Lenght Control Bits bit 4 mask. */ +#define XCL_PLC4_bp 4 /* Peripheral Lenght Control Bits bit 4 position. */ +#define XCL_PLC5_bm (1<<5) /* Peripheral Lenght Control Bits bit 5 mask. */ +#define XCL_PLC5_bp 5 /* Peripheral Lenght Control Bits bit 5 position. */ +#define XCL_PLC6_bm (1<<6) /* Peripheral Lenght Control Bits bit 6 mask. */ +#define XCL_PLC6_bp 6 /* Peripheral Lenght Control Bits bit 6 position. */ +#define XCL_PLC7_bm (1<<7) /* Peripheral Lenght Control Bits bit 7 mask. */ +#define XCL_PLC7_bp 7 /* Peripheral Lenght Control Bits bit 7 position. */ + +/* XCL.CNTL bit masks and bit positions */ +#define XCL_BCNTO_gm 0xFF /* BTC0 Counter Byte group mask. */ +#define XCL_BCNTO_gp 0 /* BTC0 Counter Byte group position. */ +#define XCL_BCNTO0_bm (1<<0) /* BTC0 Counter Byte bit 0 mask. */ +#define XCL_BCNTO0_bp 0 /* BTC0 Counter Byte bit 0 position. */ +#define XCL_BCNTO1_bm (1<<1) /* BTC0 Counter Byte bit 1 mask. */ +#define XCL_BCNTO1_bp 1 /* BTC0 Counter Byte bit 1 position. */ +#define XCL_BCNTO2_bm (1<<2) /* BTC0 Counter Byte bit 2 mask. */ +#define XCL_BCNTO2_bp 2 /* BTC0 Counter Byte bit 2 position. */ +#define XCL_BCNTO3_bm (1<<3) /* BTC0 Counter Byte bit 3 mask. */ +#define XCL_BCNTO3_bp 3 /* BTC0 Counter Byte bit 3 position. */ +#define XCL_BCNTO4_bm (1<<4) /* BTC0 Counter Byte bit 4 mask. */ +#define XCL_BCNTO4_bp 4 /* BTC0 Counter Byte bit 4 position. */ +#define XCL_BCNTO5_bm (1<<5) /* BTC0 Counter Byte bit 5 mask. */ +#define XCL_BCNTO5_bp 5 /* BTC0 Counter Byte bit 5 position. */ +#define XCL_BCNTO6_bm (1<<6) /* BTC0 Counter Byte bit 6 mask. */ +#define XCL_BCNTO6_bp 6 /* BTC0 Counter Byte bit 6 position. */ +#define XCL_BCNTO7_bm (1<<7) /* BTC0 Counter Byte bit 7 mask. */ +#define XCL_BCNTO7_bp 7 /* BTC0 Counter Byte bit 7 position. */ + +#define XCL_CNTL_gm 0xFF /* TC16 Counter Low Byte group mask. */ +#define XCL_CNTL_gp 0 /* TC16 Counter Low Byte group position. */ +#define XCL_CNTL0_bm (1<<0) /* TC16 Counter Low Byte bit 0 mask. */ +#define XCL_CNTL0_bp 0 /* TC16 Counter Low Byte bit 0 position. */ +#define XCL_CNTL1_bm (1<<1) /* TC16 Counter Low Byte bit 1 mask. */ +#define XCL_CNTL1_bp 1 /* TC16 Counter Low Byte bit 1 position. */ +#define XCL_CNTL2_bm (1<<2) /* TC16 Counter Low Byte bit 2 mask. */ +#define XCL_CNTL2_bp 2 /* TC16 Counter Low Byte bit 2 position. */ +#define XCL_CNTL3_bm (1<<3) /* TC16 Counter Low Byte bit 3 mask. */ +#define XCL_CNTL3_bp 3 /* TC16 Counter Low Byte bit 3 position. */ +#define XCL_CNTL4_bm (1<<4) /* TC16 Counter Low Byte bit 4 mask. */ +#define XCL_CNTL4_bp 4 /* TC16 Counter Low Byte bit 4 position. */ +#define XCL_CNTL5_bm (1<<5) /* TC16 Counter Low Byte bit 5 mask. */ +#define XCL_CNTL5_bp 5 /* TC16 Counter Low Byte bit 5 position. */ +#define XCL_CNTL6_bm (1<<6) /* TC16 Counter Low Byte bit 6 mask. */ +#define XCL_CNTL6_bp 6 /* TC16 Counter Low Byte bit 6 position. */ +#define XCL_CNTL7_bm (1<<7) /* TC16 Counter Low Byte bit 7 mask. */ +#define XCL_CNTL7_bp 7 /* TC16 Counter Low Byte bit 7 position. */ + +#define XCL_PCNTO_gm 0xFF /* Peripheral Counter 0 Byte group mask. */ +#define XCL_PCNTO_gp 0 /* Peripheral Counter 0 Byte group position. */ +#define XCL_PCNTO0_bm (1<<0) /* Peripheral Counter 0 Byte bit 0 mask. */ +#define XCL_PCNTO0_bp 0 /* Peripheral Counter 0 Byte bit 0 position. */ +#define XCL_PCNTO1_bm (1<<1) /* Peripheral Counter 0 Byte bit 1 mask. */ +#define XCL_PCNTO1_bp 1 /* Peripheral Counter 0 Byte bit 1 position. */ +#define XCL_PCNTO2_bm (1<<2) /* Peripheral Counter 0 Byte bit 2 mask. */ +#define XCL_PCNTO2_bp 2 /* Peripheral Counter 0 Byte bit 2 position. */ +#define XCL_PCNTO3_bm (1<<3) /* Peripheral Counter 0 Byte bit 3 mask. */ +#define XCL_PCNTO3_bp 3 /* Peripheral Counter 0 Byte bit 3 position. */ +#define XCL_PCNTO4_bm (1<<4) /* Peripheral Counter 0 Byte bit 4 mask. */ +#define XCL_PCNTO4_bp 4 /* Peripheral Counter 0 Byte bit 4 position. */ +#define XCL_PCNTO5_bm (1<<5) /* Peripheral Counter 0 Byte bit 5 mask. */ +#define XCL_PCNTO5_bp 5 /* Peripheral Counter 0 Byte bit 5 position. */ +#define XCL_PCNTO6_bm (1<<6) /* Peripheral Counter 0 Byte bit 6 mask. */ +#define XCL_PCNTO6_bp 6 /* Peripheral Counter 0 Byte bit 6 position. */ +#define XCL_PCNTO7_bm (1<<7) /* Peripheral Counter 0 Byte bit 7 mask. */ +#define XCL_PCNTO7_bp 7 /* Peripheral Counter 0 Byte bit 7 position. */ + +/* XCL.CNTH bit masks and bit positions */ +#define XCL_BCNT1_gm 0xFF /* BTC1 Counter Byte group mask. */ +#define XCL_BCNT1_gp 0 /* BTC1 Counter Byte group position. */ +#define XCL_BCNT10_bm (1<<0) /* BTC1 Counter Byte bit 0 mask. */ +#define XCL_BCNT10_bp 0 /* BTC1 Counter Byte bit 0 position. */ +#define XCL_BCNT11_bm (1<<1) /* BTC1 Counter Byte bit 1 mask. */ +#define XCL_BCNT11_bp 1 /* BTC1 Counter Byte bit 1 position. */ +#define XCL_BCNT12_bm (1<<2) /* BTC1 Counter Byte bit 2 mask. */ +#define XCL_BCNT12_bp 2 /* BTC1 Counter Byte bit 2 position. */ +#define XCL_BCNT13_bm (1<<3) /* BTC1 Counter Byte bit 3 mask. */ +#define XCL_BCNT13_bp 3 /* BTC1 Counter Byte bit 3 position. */ +#define XCL_BCNT14_bm (1<<4) /* BTC1 Counter Byte bit 4 mask. */ +#define XCL_BCNT14_bp 4 /* BTC1 Counter Byte bit 4 position. */ +#define XCL_BCNT15_bm (1<<5) /* BTC1 Counter Byte bit 5 mask. */ +#define XCL_BCNT15_bp 5 /* BTC1 Counter Byte bit 5 position. */ +#define XCL_BCNT16_bm (1<<6) /* BTC1 Counter Byte bit 6 mask. */ +#define XCL_BCNT16_bp 6 /* BTC1 Counter Byte bit 6 position. */ +#define XCL_BCNT17_bm (1<<7) /* BTC1 Counter Byte bit 7 mask. */ +#define XCL_BCNT17_bp 7 /* BTC1 Counter Byte bit 7 position. */ + +#define XCL_CNTH_gm 0xFF /* TC16 Counter High Byte group mask. */ +#define XCL_CNTH_gp 0 /* TC16 Counter High Byte group position. */ +#define XCL_CNTH0_bm (1<<0) /* TC16 Counter High Byte bit 0 mask. */ +#define XCL_CNTH0_bp 0 /* TC16 Counter High Byte bit 0 position. */ +#define XCL_CNTH1_bm (1<<1) /* TC16 Counter High Byte bit 1 mask. */ +#define XCL_CNTH1_bp 1 /* TC16 Counter High Byte bit 1 position. */ +#define XCL_CNTH2_bm (1<<2) /* TC16 Counter High Byte bit 2 mask. */ +#define XCL_CNTH2_bp 2 /* TC16 Counter High Byte bit 2 position. */ +#define XCL_CNTH3_bm (1<<3) /* TC16 Counter High Byte bit 3 mask. */ +#define XCL_CNTH3_bp 3 /* TC16 Counter High Byte bit 3 position. */ +#define XCL_CNTH4_bm (1<<4) /* TC16 Counter High Byte bit 4 mask. */ +#define XCL_CNTH4_bp 4 /* TC16 Counter High Byte bit 4 position. */ +#define XCL_CNTH5_bm (1<<5) /* TC16 Counter High Byte bit 5 mask. */ +#define XCL_CNTH5_bp 5 /* TC16 Counter High Byte bit 5 position. */ +#define XCL_CNTH6_bm (1<<6) /* TC16 Counter High Byte bit 6 mask. */ +#define XCL_CNTH6_bp 6 /* TC16 Counter High Byte bit 6 position. */ +#define XCL_CNTH7_bm (1<<7) /* TC16 Counter High Byte bit 7 mask. */ +#define XCL_CNTH7_bp 7 /* TC16 Counter High Byte bit 7 position. */ + +#define XCL_PCNT1_gm 0xFF /* Peripheral Counter 1 Byte group mask. */ +#define XCL_PCNT1_gp 0 /* Peripheral Counter 1 Byte group position. */ +#define XCL_PCNT10_bm (1<<0) /* Peripheral Counter 1 Byte bit 0 mask. */ +#define XCL_PCNT10_bp 0 /* Peripheral Counter 1 Byte bit 0 position. */ +#define XCL_PCNT11_bm (1<<1) /* Peripheral Counter 1 Byte bit 1 mask. */ +#define XCL_PCNT11_bp 1 /* Peripheral Counter 1 Byte bit 1 position. */ +#define XCL_PCNT12_bm (1<<2) /* Peripheral Counter 1 Byte bit 2 mask. */ +#define XCL_PCNT12_bp 2 /* Peripheral Counter 1 Byte bit 2 position. */ +#define XCL_PCNT13_bm (1<<3) /* Peripheral Counter 1 Byte bit 3 mask. */ +#define XCL_PCNT13_bp 3 /* Peripheral Counter 1 Byte bit 3 position. */ +#define XCL_PCNT14_bm (1<<4) /* Peripheral Counter 1 Byte bit 4 mask. */ +#define XCL_PCNT14_bp 4 /* Peripheral Counter 1 Byte bit 4 position. */ +#define XCL_PCNT15_bm (1<<5) /* Peripheral Counter 1 Byte bit 5 mask. */ +#define XCL_PCNT15_bp 5 /* Peripheral Counter 1 Byte bit 5 position. */ +#define XCL_PCNT16_bm (1<<6) /* Peripheral Counter 1 Byte bit 6 mask. */ +#define XCL_PCNT16_bp 6 /* Peripheral Counter 1 Byte bit 6 position. */ +#define XCL_PCNT17_bm (1<<7) /* Peripheral Counter 1 Byte bit 7 mask. */ +#define XCL_PCNT17_bp 7 /* Peripheral Counter 1 Byte bit 7 position. */ + +#define XCL_PCNT21_gm 0xF0 /* Peripheral High Counter 2 Bits group mask. */ +#define XCL_PCNT21_gp 4 /* Peripheral High Counter 2 Bits group position. */ +#define XCL_PCNT210_bm (1<<4) /* Peripheral High Counter 2 Bits bit 0 mask. */ +#define XCL_PCNT210_bp 4 /* Peripheral High Counter 2 Bits bit 0 position. */ +#define XCL_PCNT211_bm (1<<5) /* Peripheral High Counter 2 Bits bit 1 mask. */ +#define XCL_PCNT211_bp 5 /* Peripheral High Counter 2 Bits bit 1 position. */ +#define XCL_PCNT212_bm (1<<6) /* Peripheral High Counter 2 Bits bit 2 mask. */ +#define XCL_PCNT212_bp 6 /* Peripheral High Counter 2 Bits bit 2 position. */ +#define XCL_PCNT213_bm (1<<7) /* Peripheral High Counter 2 Bits bit 3 mask. */ +#define XCL_PCNT213_bp 7 /* Peripheral High Counter 2 Bits bit 3 position. */ + +#define XCL_PCNT20_gm 0x0F /* Peripheral Low Counter 2 Bits group mask. */ +#define XCL_PCNT20_gp 0 /* Peripheral Low Counter 2 Bits group position. */ +#define XCL_PCNT200_bm (1<<0) /* Peripheral Low Counter 2 Bits bit 0 mask. */ +#define XCL_PCNT200_bp 0 /* Peripheral Low Counter 2 Bits bit 0 position. */ +#define XCL_PCNT201_bm (1<<1) /* Peripheral Low Counter 2 Bits bit 1 mask. */ +#define XCL_PCNT201_bp 1 /* Peripheral Low Counter 2 Bits bit 1 position. */ +#define XCL_PCNT202_bm (1<<2) /* Peripheral Low Counter 2 Bits bit 2 mask. */ +#define XCL_PCNT202_bp 2 /* Peripheral Low Counter 2 Bits bit 2 position. */ +#define XCL_PCNT203_bm (1<<3) /* Peripheral Low Counter 2 Bits bit 3 mask. */ +#define XCL_PCNT203_bp 3 /* Peripheral Low Counter 2 Bits bit 3 position. */ + +/* XCL.CMPL bit masks and bit positions */ +#define XCL_CMPL_gm 0xFF /* TC16 Compare Low Byte group mask. */ +#define XCL_CMPL_gp 0 /* TC16 Compare Low Byte group position. */ +#define XCL_CMPL0_bm (1<<0) /* TC16 Compare Low Byte bit 0 mask. */ +#define XCL_CMPL0_bp 0 /* TC16 Compare Low Byte bit 0 position. */ +#define XCL_CMPL1_bm (1<<1) /* TC16 Compare Low Byte bit 1 mask. */ +#define XCL_CMPL1_bp 1 /* TC16 Compare Low Byte bit 1 position. */ +#define XCL_CMPL2_bm (1<<2) /* TC16 Compare Low Byte bit 2 mask. */ +#define XCL_CMPL2_bp 2 /* TC16 Compare Low Byte bit 2 position. */ +#define XCL_CMPL3_bm (1<<3) /* TC16 Compare Low Byte bit 3 mask. */ +#define XCL_CMPL3_bp 3 /* TC16 Compare Low Byte bit 3 position. */ +#define XCL_CMPL4_bm (1<<4) /* TC16 Compare Low Byte bit 4 mask. */ +#define XCL_CMPL4_bp 4 /* TC16 Compare Low Byte bit 4 position. */ +#define XCL_CMPL5_bm (1<<5) /* TC16 Compare Low Byte bit 5 mask. */ +#define XCL_CMPL5_bp 5 /* TC16 Compare Low Byte bit 5 position. */ +#define XCL_CMPL6_bm (1<<6) /* TC16 Compare Low Byte bit 6 mask. */ +#define XCL_CMPL6_bp 6 /* TC16 Compare Low Byte bit 6 position. */ +#define XCL_CMPL7_bm (1<<7) /* TC16 Compare Low Byte bit 7 mask. */ +#define XCL_CMPL7_bp 7 /* TC16 Compare Low Byte bit 7 position. */ + +#define XCL_BCMP0_gm 0xFF /* BTC0 Compare Byte group mask. */ +#define XCL_BCMP0_gp 0 /* BTC0 Compare Byte group position. */ +#define XCL_BCMP00_bm (1<<0) /* BTC0 Compare Byte bit 0 mask. */ +#define XCL_BCMP00_bp 0 /* BTC0 Compare Byte bit 0 position. */ +#define XCL_BCMP01_bm (1<<1) /* BTC0 Compare Byte bit 1 mask. */ +#define XCL_BCMP01_bp 1 /* BTC0 Compare Byte bit 1 position. */ +#define XCL_BCMP02_bm (1<<2) /* BTC0 Compare Byte bit 2 mask. */ +#define XCL_BCMP02_bp 2 /* BTC0 Compare Byte bit 2 position. */ +#define XCL_BCMP03_bm (1<<3) /* BTC0 Compare Byte bit 3 mask. */ +#define XCL_BCMP03_bp 3 /* BTC0 Compare Byte bit 3 position. */ +#define XCL_BCMP04_bm (1<<4) /* BTC0 Compare Byte bit 4 mask. */ +#define XCL_BCMP04_bp 4 /* BTC0 Compare Byte bit 4 position. */ +#define XCL_BCMP05_bm (1<<5) /* BTC0 Compare Byte bit 5 mask. */ +#define XCL_BCMP05_bp 5 /* BTC0 Compare Byte bit 5 position. */ +#define XCL_BCMP06_bm (1<<6) /* BTC0 Compare Byte bit 6 mask. */ +#define XCL_BCMP06_bp 6 /* BTC0 Compare Byte bit 6 position. */ +#define XCL_BCMP07_bm (1<<7) /* BTC0 Compare Byte bit 7 mask. */ +#define XCL_BCMP07_bp 7 /* BTC0 Compare Byte bit 7 position. */ + +/* XCL.CMPH bit masks and bit positions */ +#define XCL_CMPH_gm 0xFF /* TC16 Compare High Byte group mask. */ +#define XCL_CMPH_gp 0 /* TC16 Compare High Byte group position. */ +#define XCL_CMPH0_bm (1<<0) /* TC16 Compare High Byte bit 0 mask. */ +#define XCL_CMPH0_bp 0 /* TC16 Compare High Byte bit 0 position. */ +#define XCL_CMPH1_bm (1<<1) /* TC16 Compare High Byte bit 1 mask. */ +#define XCL_CMPH1_bp 1 /* TC16 Compare High Byte bit 1 position. */ +#define XCL_CMPH2_bm (1<<2) /* TC16 Compare High Byte bit 2 mask. */ +#define XCL_CMPH2_bp 2 /* TC16 Compare High Byte bit 2 position. */ +#define XCL_CMPH3_bm (1<<3) /* TC16 Compare High Byte bit 3 mask. */ +#define XCL_CMPH3_bp 3 /* TC16 Compare High Byte bit 3 position. */ +#define XCL_CMPH4_bm (1<<4) /* TC16 Compare High Byte bit 4 mask. */ +#define XCL_CMPH4_bp 4 /* TC16 Compare High Byte bit 4 position. */ +#define XCL_CMPH5_bm (1<<5) /* TC16 Compare High Byte bit 5 mask. */ +#define XCL_CMPH5_bp 5 /* TC16 Compare High Byte bit 5 position. */ +#define XCL_CMPH6_bm (1<<6) /* TC16 Compare High Byte bit 6 mask. */ +#define XCL_CMPH6_bp 6 /* TC16 Compare High Byte bit 6 position. */ +#define XCL_CMPH7_bm (1<<7) /* TC16 Compare High Byte bit 7 mask. */ +#define XCL_CMPH7_bp 7 /* TC16 Compare High Byte bit 7 position. */ + +#define XCL_BCMP1_gm 0xFF /* BTC1 Compare Byte group mask. */ +#define XCL_BCMP1_gp 0 /* BTC1 Compare Byte group position. */ +#define XCL_BCMP10_bm (1<<0) /* BTC1 Compare Byte bit 0 mask. */ +#define XCL_BCMP10_bp 0 /* BTC1 Compare Byte bit 0 position. */ +#define XCL_BCMP11_bm (1<<1) /* BTC1 Compare Byte bit 1 mask. */ +#define XCL_BCMP11_bp 1 /* BTC1 Compare Byte bit 1 position. */ +#define XCL_BCMP12_bm (1<<2) /* BTC1 Compare Byte bit 2 mask. */ +#define XCL_BCMP12_bp 2 /* BTC1 Compare Byte bit 2 position. */ +#define XCL_BCMP13_bm (1<<3) /* BTC1 Compare Byte bit 3 mask. */ +#define XCL_BCMP13_bp 3 /* BTC1 Compare Byte bit 3 position. */ +#define XCL_BCMP14_bm (1<<4) /* BTC1 Compare Byte bit 4 mask. */ +#define XCL_BCMP14_bp 4 /* BTC1 Compare Byte bit 4 position. */ +#define XCL_BCMP15_bm (1<<5) /* BTC1 Compare Byte bit 5 mask. */ +#define XCL_BCMP15_bp 5 /* BTC1 Compare Byte bit 5 position. */ +#define XCL_BCMP16_bm (1<<6) /* BTC1 Compare Byte bit 6 mask. */ +#define XCL_BCMP16_bp 6 /* BTC1 Compare Byte bit 6 position. */ +#define XCL_BCMP17_bm (1<<7) /* BTC1 Compare Byte bit 7 mask. */ +#define XCL_BCMP17_bp 7 /* BTC1 Compare Byte bit 7 position. */ + +/* XCL.PERCAPTL bit masks and bit positions */ +#define XCL_PERL_gm 0xFF /* TC16 Low Byte Period group mask. */ +#define XCL_PERL_gp 0 /* TC16 Low Byte Period group position. */ +#define XCL_PERL0_bm (1<<0) /* TC16 Low Byte Period bit 0 mask. */ +#define XCL_PERL0_bp 0 /* TC16 Low Byte Period bit 0 position. */ +#define XCL_PERL1_bm (1<<1) /* TC16 Low Byte Period bit 1 mask. */ +#define XCL_PERL1_bp 1 /* TC16 Low Byte Period bit 1 position. */ +#define XCL_PERL2_bm (1<<2) /* TC16 Low Byte Period bit 2 mask. */ +#define XCL_PERL2_bp 2 /* TC16 Low Byte Period bit 2 position. */ +#define XCL_PERL3_bm (1<<3) /* TC16 Low Byte Period bit 3 mask. */ +#define XCL_PERL3_bp 3 /* TC16 Low Byte Period bit 3 position. */ +#define XCL_PERL4_bm (1<<4) /* TC16 Low Byte Period bit 4 mask. */ +#define XCL_PERL4_bp 4 /* TC16 Low Byte Period bit 4 position. */ +#define XCL_PERL5_bm (1<<5) /* TC16 Low Byte Period bit 5 mask. */ +#define XCL_PERL5_bp 5 /* TC16 Low Byte Period bit 5 position. */ +#define XCL_PERL6_bm (1<<6) /* TC16 Low Byte Period bit 6 mask. */ +#define XCL_PERL6_bp 6 /* TC16 Low Byte Period bit 6 position. */ +#define XCL_PERL7_bm (1<<7) /* TC16 Low Byte Period bit 7 mask. */ +#define XCL_PERL7_bp 7 /* TC16 Low Byte Period bit 7 position. */ + +#define XCL_CAPTL_gm 0xFF /* TC16 Capture Value Low Byte group mask. */ +#define XCL_CAPTL_gp 0 /* TC16 Capture Value Low Byte group position. */ +#define XCL_CAPTL0_bm (1<<0) /* TC16 Capture Value Low Byte bit 0 mask. */ +#define XCL_CAPTL0_bp 0 /* TC16 Capture Value Low Byte bit 0 position. */ +#define XCL_CAPTL1_bm (1<<1) /* TC16 Capture Value Low Byte bit 1 mask. */ +#define XCL_CAPTL1_bp 1 /* TC16 Capture Value Low Byte bit 1 position. */ +#define XCL_CAPTL2_bm (1<<2) /* TC16 Capture Value Low Byte bit 2 mask. */ +#define XCL_CAPTL2_bp 2 /* TC16 Capture Value Low Byte bit 2 position. */ +#define XCL_CAPTL3_bm (1<<3) /* TC16 Capture Value Low Byte bit 3 mask. */ +#define XCL_CAPTL3_bp 3 /* TC16 Capture Value Low Byte bit 3 position. */ +#define XCL_CAPTL4_bm (1<<4) /* TC16 Capture Value Low Byte bit 4 mask. */ +#define XCL_CAPTL4_bp 4 /* TC16 Capture Value Low Byte bit 4 position. */ +#define XCL_CAPTL5_bm (1<<5) /* TC16 Capture Value Low Byte bit 5 mask. */ +#define XCL_CAPTL5_bp 5 /* TC16 Capture Value Low Byte bit 5 position. */ +#define XCL_CAPTL6_bm (1<<6) /* TC16 Capture Value Low Byte bit 6 mask. */ +#define XCL_CAPTL6_bp 6 /* TC16 Capture Value Low Byte bit 6 position. */ +#define XCL_CAPTL7_bm (1<<7) /* TC16 Capture Value Low Byte bit 7 mask. */ +#define XCL_CAPTL7_bp 7 /* TC16 Capture Value Low Byte bit 7 position. */ + +#define XCL_BPER0_gm 0xFF /* BTC0 Period group mask. */ +#define XCL_BPER0_gp 0 /* BTC0 Period group position. */ +#define XCL_BPER00_bm (1<<0) /* BTC0 Period bit 0 mask. */ +#define XCL_BPER00_bp 0 /* BTC0 Period bit 0 position. */ +#define XCL_BPER01_bm (1<<1) /* BTC0 Period bit 1 mask. */ +#define XCL_BPER01_bp 1 /* BTC0 Period bit 1 position. */ +#define XCL_BPER02_bm (1<<2) /* BTC0 Period bit 2 mask. */ +#define XCL_BPER02_bp 2 /* BTC0 Period bit 2 position. */ +#define XCL_BPER03_bm (1<<3) /* BTC0 Period bit 3 mask. */ +#define XCL_BPER03_bp 3 /* BTC0 Period bit 3 position. */ +#define XCL_BPER04_bm (1<<4) /* BTC0 Period bit 4 mask. */ +#define XCL_BPER04_bp 4 /* BTC0 Period bit 4 position. */ +#define XCL_BPER05_bm (1<<5) /* BTC0 Period bit 5 mask. */ +#define XCL_BPER05_bp 5 /* BTC0 Period bit 5 position. */ +#define XCL_BPER06_bm (1<<6) /* BTC0 Period bit 6 mask. */ +#define XCL_BPER06_bp 6 /* BTC0 Period bit 6 position. */ +#define XCL_BPER07_bm (1<<7) /* BTC0 Period bit 7 mask. */ +#define XCL_BPER07_bp 7 /* BTC0 Period bit 7 position. */ + +#define XCL_BCAPT0_gm 0xFF /* BTC0 Capture Value Byte group mask. */ +#define XCL_BCAPT0_gp 0 /* BTC0 Capture Value Byte group position. */ +#define XCL_BCAPT00_bm (1<<0) /* BTC0 Capture Value Byte bit 0 mask. */ +#define XCL_BCAPT00_bp 0 /* BTC0 Capture Value Byte bit 0 position. */ +#define XCL_BCAPT01_bm (1<<1) /* BTC0 Capture Value Byte bit 1 mask. */ +#define XCL_BCAPT01_bp 1 /* BTC0 Capture Value Byte bit 1 position. */ +#define XCL_BCAPT02_bm (1<<2) /* BTC0 Capture Value Byte bit 2 mask. */ +#define XCL_BCAPT02_bp 2 /* BTC0 Capture Value Byte bit 2 position. */ +#define XCL_BCAPT03_bm (1<<3) /* BTC0 Capture Value Byte bit 3 mask. */ +#define XCL_BCAPT03_bp 3 /* BTC0 Capture Value Byte bit 3 position. */ +#define XCL_BCAPT04_bm (1<<4) /* BTC0 Capture Value Byte bit 4 mask. */ +#define XCL_BCAPT04_bp 4 /* BTC0 Capture Value Byte bit 4 position. */ +#define XCL_BCAPT05_bm (1<<5) /* BTC0 Capture Value Byte bit 5 mask. */ +#define XCL_BCAPT05_bp 5 /* BTC0 Capture Value Byte bit 5 position. */ +#define XCL_BCAPT06_bm (1<<6) /* BTC0 Capture Value Byte bit 6 mask. */ +#define XCL_BCAPT06_bp 6 /* BTC0 Capture Value Byte bit 6 position. */ +#define XCL_BCAPT07_bm (1<<7) /* BTC0 Capture Value Byte bit 7 mask. */ +#define XCL_BCAPT07_bp 7 /* BTC0 Capture Value Byte bit 7 position. */ + +/* XCL.PERCAPTH bit masks and bit positions */ +#define XCL_PERH_gm 0xFF /* TC16 High Byte Period group mask. */ +#define XCL_PERH_gp 0 /* TC16 High Byte Period group position. */ +#define XCL_PERH0_bm (1<<0) /* TC16 High Byte Period bit 0 mask. */ +#define XCL_PERH0_bp 0 /* TC16 High Byte Period bit 0 position. */ +#define XCL_PERH1_bm (1<<1) /* TC16 High Byte Period bit 1 mask. */ +#define XCL_PERH1_bp 1 /* TC16 High Byte Period bit 1 position. */ +#define XCL_PERH2_bm (1<<2) /* TC16 High Byte Period bit 2 mask. */ +#define XCL_PERH2_bp 2 /* TC16 High Byte Period bit 2 position. */ +#define XCL_PERH3_bm (1<<3) /* TC16 High Byte Period bit 3 mask. */ +#define XCL_PERH3_bp 3 /* TC16 High Byte Period bit 3 position. */ +#define XCL_PERH4_bm (1<<4) /* TC16 High Byte Period bit 4 mask. */ +#define XCL_PERH4_bp 4 /* TC16 High Byte Period bit 4 position. */ +#define XCL_PERH5_bm (1<<5) /* TC16 High Byte Period bit 5 mask. */ +#define XCL_PERH5_bp 5 /* TC16 High Byte Period bit 5 position. */ +#define XCL_PERH6_bm (1<<6) /* TC16 High Byte Period bit 6 mask. */ +#define XCL_PERH6_bp 6 /* TC16 High Byte Period bit 6 position. */ +#define XCL_PERH7_bm (1<<7) /* TC16 High Byte Period bit 7 mask. */ +#define XCL_PERH7_bp 7 /* TC16 High Byte Period bit 7 position. */ + +#define XCL_CAPTH_gm 0xFF /* TC16 Capture Value High Byte group mask. */ +#define XCL_CAPTH_gp 0 /* TC16 Capture Value High Byte group position. */ +#define XCL_CAPTH0_bm (1<<0) /* TC16 Capture Value High Byte bit 0 mask. */ +#define XCL_CAPTH0_bp 0 /* TC16 Capture Value High Byte bit 0 position. */ +#define XCL_CAPTH1_bm (1<<1) /* TC16 Capture Value High Byte bit 1 mask. */ +#define XCL_CAPTH1_bp 1 /* TC16 Capture Value High Byte bit 1 position. */ +#define XCL_CAPTH2_bm (1<<2) /* TC16 Capture Value High Byte bit 2 mask. */ +#define XCL_CAPTH2_bp 2 /* TC16 Capture Value High Byte bit 2 position. */ +#define XCL_CAPTH3_bm (1<<3) /* TC16 Capture Value High Byte bit 3 mask. */ +#define XCL_CAPTH3_bp 3 /* TC16 Capture Value High Byte bit 3 position. */ +#define XCL_CAPTH4_bm (1<<4) /* TC16 Capture Value High Byte bit 4 mask. */ +#define XCL_CAPTH4_bp 4 /* TC16 Capture Value High Byte bit 4 position. */ +#define XCL_CAPTH5_bm (1<<5) /* TC16 Capture Value High Byte bit 5 mask. */ +#define XCL_CAPTH5_bp 5 /* TC16 Capture Value High Byte bit 5 position. */ +#define XCL_CAPTH6_bm (1<<6) /* TC16 Capture Value High Byte bit 6 mask. */ +#define XCL_CAPTH6_bp 6 /* TC16 Capture Value High Byte bit 6 position. */ +#define XCL_CAPTH7_bm (1<<7) /* TC16 Capture Value High Byte bit 7 mask. */ +#define XCL_CAPTH7_bp 7 /* TC16 Capture Value High Byte bit 7 position. */ + +#define XCL_BPER1_gm 0xFF /* BTC1 Period group mask. */ +#define XCL_BPER1_gp 0 /* BTC1 Period group position. */ +#define XCL_BPER10_bm (1<<0) /* BTC1 Period bit 0 mask. */ +#define XCL_BPER10_bp 0 /* BTC1 Period bit 0 position. */ +#define XCL_BPER11_bm (1<<1) /* BTC1 Period bit 1 mask. */ +#define XCL_BPER11_bp 1 /* BTC1 Period bit 1 position. */ +#define XCL_BPER12_bm (1<<2) /* BTC1 Period bit 2 mask. */ +#define XCL_BPER12_bp 2 /* BTC1 Period bit 2 position. */ +#define XCL_BPER13_bm (1<<3) /* BTC1 Period bit 3 mask. */ +#define XCL_BPER13_bp 3 /* BTC1 Period bit 3 position. */ +#define XCL_BPER14_bm (1<<4) /* BTC1 Period bit 4 mask. */ +#define XCL_BPER14_bp 4 /* BTC1 Period bit 4 position. */ +#define XCL_BPER15_bm (1<<5) /* BTC1 Period bit 5 mask. */ +#define XCL_BPER15_bp 5 /* BTC1 Period bit 5 position. */ +#define XCL_BPER16_bm (1<<6) /* BTC1 Period bit 6 mask. */ +#define XCL_BPER16_bp 6 /* BTC1 Period bit 6 position. */ +#define XCL_BPER17_bm (1<<7) /* BTC1 Period bit 7 mask. */ +#define XCL_BPER17_bp 7 /* BTC1 Period bit 7 position. */ + +#define XCL_BCAPT1_gm 0xFF /* BTC1 Capture Value Byte group mask. */ +#define XCL_BCAPT1_gp 0 /* BTC1 Capture Value Byte group position. */ +#define XCL_BCAPT10_bm (1<<0) /* BTC1 Capture Value Byte bit 0 mask. */ +#define XCL_BCAPT10_bp 0 /* BTC1 Capture Value Byte bit 0 position. */ +#define XCL_BCAPT11_bm (1<<1) /* BTC1 Capture Value Byte bit 1 mask. */ +#define XCL_BCAPT11_bp 1 /* BTC1 Capture Value Byte bit 1 position. */ +#define XCL_BCAPT12_bm (1<<2) /* BTC1 Capture Value Byte bit 2 mask. */ +#define XCL_BCAPT12_bp 2 /* BTC1 Capture Value Byte bit 2 position. */ +#define XCL_BCAPT13_bm (1<<3) /* BTC1 Capture Value Byte bit 3 mask. */ +#define XCL_BCAPT13_bp 3 /* BTC1 Capture Value Byte bit 3 position. */ +#define XCL_BCAPT14_bm (1<<4) /* BTC1 Capture Value Byte bit 4 mask. */ +#define XCL_BCAPT14_bp 4 /* BTC1 Capture Value Byte bit 4 position. */ +#define XCL_BCAPT15_bm (1<<5) /* BTC1 Capture Value Byte bit 5 mask. */ +#define XCL_BCAPT15_bp 5 /* BTC1 Capture Value Byte bit 5 position. */ +#define XCL_BCAPT16_bm (1<<6) /* BTC1 Capture Value Byte bit 6 mask. */ +#define XCL_BCAPT16_bp 6 /* BTC1 Capture Value Byte bit 6 position. */ +#define XCL_BCAPT17_bm (1<<7) /* BTC1 Capture Value Byte bit 7 mask. */ +#define XCL_BCAPT17_bp 7 /* BTC1 Capture Value Byte bit 7 position. */ + +/* TWI - Two-Wire Interface */ +/* TWI.CTRL bit masks and bit positions */ +#define TWI_BRIDGEEN_bm 0x80 /* Bridge Enable bit mask. */ +#define TWI_BRIDGEEN_bp 7 /* Bridge Enable bit position. */ + +#define TWI_SFMPEN_bm 0x40 /* Slave Fast Mode Plus Enable bit mask. */ +#define TWI_SFMPEN_bp 6 /* Slave Fast Mode Plus Enable bit position. */ + +#define TWI_SSDAHOLD_gm 0x30 /* Slave SDA Hold Time Enable group mask. */ +#define TWI_SSDAHOLD_gp 4 /* Slave SDA Hold Time Enable group position. */ +#define TWI_SSDAHOLD0_bm (1<<4) /* Slave SDA Hold Time Enable bit 0 mask. */ +#define TWI_SSDAHOLD0_bp 4 /* Slave SDA Hold Time Enable bit 0 position. */ +#define TWI_SSDAHOLD1_bm (1<<5) /* Slave SDA Hold Time Enable bit 1 mask. */ +#define TWI_SSDAHOLD1_bp 5 /* Slave SDA Hold Time Enable bit 1 position. */ + +#define TWI_FMPEN_bm 0x08 /* FMPLUS Enable bit mask. */ +#define TWI_FMPEN_bp 3 /* FMPLUS Enable bit position. */ + +#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ +#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ +#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ +#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ +#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ +#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ + +#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ +#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ + +/* TWI_MASTER.CTRLA bit masks and bit positions */ +#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ +#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ + +#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ +#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ + +#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ +#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ + +#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ +#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ + +/* TWI_MASTER.CTRLB bit masks and bit positions */ +#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ + +#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ +#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ + +#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ + +#define TWI_MASTER_TTOUTEN_bm 0x10 /* Ttimeout Enable bit mask. */ +#define TWI_MASTER_TTOUTEN_bp 4 /* Ttimeout Enable bit position. */ + +#define TWI_MASTER_TSEXTEN_bm 0x20 /* Slave Extend Timeout Enable bit mask. */ +#define TWI_MASTER_TSEXTEN_bp 5 /* Slave Extend Timeout Enable bit position. */ + +#define TWI_MASTER_TMEXTEN_bm 0x40 /* Master Extend Timeout Enable bit mask. */ +#define TWI_MASTER_TMEXTEN_bp 6 /* Master Extend Timeout Enable bit position. */ + +#define TWI_MASTER_TOIE_bm 0x80 /* Timeout Interrupt Enable bit mask. */ +#define TWI_MASTER_TOIE_bp 7 /* Timeout Interrupt Enable bit position. */ + +/* TWI_MASTER.CTRLC bit masks and bit positions */ +#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ + +#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ +#define TWI_MASTER_CMD_gp 0 /* Command group position. */ +#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ +#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ + +/* TWI_MASTER.STATUS bit masks and bit positions */ +#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ + +#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ + +#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ + +#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ + +#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ + +#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ + +#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ +#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ +#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ + +/* TWI_SLAVE.CTRLA bit masks and bit positions */ +#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ +#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ + +#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ +#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ + +#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ +#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ + +#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ +#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ + +#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ +#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ + +#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ +#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ + +#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ + +/* TWI_SLAVE.CTRLB bit masks and bit positions */ +#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ + +#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ +#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ +#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ +#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ + +#define TWI_SLAVE_TTOUTEN_bm 0x10 /* Ttimeout Enable bit mask. */ +#define TWI_SLAVE_TTOUTEN_bp 4 /* Ttimeout Enable bit position. */ + +#define TWI_SLAVE_TOIE_bm 0x80 /* Timeout Interrupt Enable bit mask. */ +#define TWI_SLAVE_TOIE_bp 7 /* Timeout Interrupt Enable bit position. */ + +/* TWI_SLAVE.STATUS bit masks and bit positions */ +#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ + +#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ + +#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ + +#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ + +#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ +#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ + +#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ + +#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ + +#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ + +/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ +#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ +#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ + +#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ +#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ + +/* TWI_TIMEOUT.TOS bit masks and bit positions */ +#define TWI_TIMEOUT_TTOUTMIF_bm 0x01 /* Master Ttimeout Interrupt Flag bit mask. */ +#define TWI_TIMEOUT_TTOUTMIF_bp 0 /* Master Ttimeout Interrupt Flag bit position. */ + +#define TWI_TIMEOUT_TSEXTIF_bm 0x02 /* Slave Extend Interrupt Flag bit mask. */ +#define TWI_TIMEOUT_TSEXTIF_bp 1 /* Slave Extend Interrupt Flag bit position. */ + +#define TWI_TIMEOUT_TMEXTIF_bm 0x04 /* Master Extend Interrupt Flag bit mask. */ +#define TWI_TIMEOUT_TMEXTIF_bp 2 /* Master Extend Interrupt Flag bit position. */ + +#define TWI_TIMEOUT_TTOUTSIF_bm 0x10 /* Slave Ttimeout Interrupt Flag bit mask. */ +#define TWI_TIMEOUT_TTOUTSIF_bp 4 /* Slave Ttimeout Interrupt Flag bit position. */ + +/* TWI_TIMEOUT.TOCONF bit masks and bit positions */ +#define TWI_TIMEOUT_TTOUTMSEL_gm 0x07 /* Master Ttimeout Select group mask. */ +#define TWI_TIMEOUT_TTOUTMSEL_gp 0 /* Master Ttimeout Select group position. */ +#define TWI_TIMEOUT_TTOUTMSEL0_bm (1<<0) /* Master Ttimeout Select bit 0 mask. */ +#define TWI_TIMEOUT_TTOUTMSEL0_bp 0 /* Master Ttimeout Select bit 0 position. */ +#define TWI_TIMEOUT_TTOUTMSEL1_bm (1<<1) /* Master Ttimeout Select bit 1 mask. */ +#define TWI_TIMEOUT_TTOUTMSEL1_bp 1 /* Master Ttimeout Select bit 1 position. */ +#define TWI_TIMEOUT_TTOUTMSEL2_bm (1<<2) /* Master Ttimeout Select bit 2 mask. */ +#define TWI_TIMEOUT_TTOUTMSEL2_bp 2 /* Master Ttimeout Select bit 2 position. */ + +#define TWI_TIMEOUT_TMSEXTSEL_gm 0x18 /* Master/Slave Timeout Select group mask. */ +#define TWI_TIMEOUT_TMSEXTSEL_gp 3 /* Master/Slave Timeout Select group position. */ +#define TWI_TIMEOUT_TMSEXTSEL0_bm (1<<3) /* Master/Slave Timeout Select bit 0 mask. */ +#define TWI_TIMEOUT_TMSEXTSEL0_bp 3 /* Master/Slave Timeout Select bit 0 position. */ +#define TWI_TIMEOUT_TMSEXTSEL1_bm (1<<4) /* Master/Slave Timeout Select bit 1 mask. */ +#define TWI_TIMEOUT_TMSEXTSEL1_bp 4 /* Master/Slave Timeout Select bit 1 position. */ + +#define TWI_TIMEOUT_TTOUTSSEL_gm 0xE0 /* Slave Ttimeout Select group mask. */ +#define TWI_TIMEOUT_TTOUTSSEL_gp 5 /* Slave Ttimeout Select group position. */ +#define TWI_TIMEOUT_TTOUTSSEL0_bm (1<<5) /* Slave Ttimeout Select bit 0 mask. */ +#define TWI_TIMEOUT_TTOUTSSEL0_bp 5 /* Slave Ttimeout Select bit 0 position. */ +#define TWI_TIMEOUT_TTOUTSSEL1_bm (1<<6) /* Slave Ttimeout Select bit 1 mask. */ +#define TWI_TIMEOUT_TTOUTSSEL1_bp 6 /* Slave Ttimeout Select bit 1 position. */ +#define TWI_TIMEOUT_TTOUTSSEL2_bm (1<<7) /* Slave Ttimeout Select bit 2 mask. */ +#define TWI_TIMEOUT_TTOUTSSEL2_bp 7 /* Slave Ttimeout Select bit 2 position. */ + +/* PORT - Port Configuration */ +/* PORT.INTCTRL bit masks and bit positions */ +#define PORT_INTLVL_gm 0x03 /* Port Interrupt Level group mask. */ +#define PORT_INTLVL_gp 0 /* Port Interrupt Level group position. */ +#define PORT_INTLVL0_bm (1<<0) /* Port Interrupt Level bit 0 mask. */ +#define PORT_INTLVL0_bp 0 /* Port Interrupt Level bit 0 position. */ +#define PORT_INTLVL1_bm (1<<1) /* Port Interrupt Level bit 1 mask. */ +#define PORT_INTLVL1_bp 1 /* Port Interrupt Level bit 1 position. */ + +/* PORT.INTFLAGS bit masks and bit positions */ +#define PORT_INT7IF_bm 0x80 /* Pin 7 Interrupt Flag bit mask. */ +#define PORT_INT7IF_bp 7 /* Pin 7 Interrupt Flag bit position. */ + +#define PORT_INT6IF_bm 0x40 /* Pin 6 Interrupt Flag bit mask. */ +#define PORT_INT6IF_bp 6 /* Pin 6 Interrupt Flag bit position. */ + +#define PORT_INT5IF_bm 0x20 /* Pin 5 Interrupt Flag bit mask. */ +#define PORT_INT5IF_bp 5 /* Pin 5 Interrupt Flag bit position. */ + +#define PORT_INT4IF_bm 0x10 /* Pin 4 Interrupt Flag bit mask. */ +#define PORT_INT4IF_bp 4 /* Pin 4 Interrupt Flag bit position. */ + +#define PORT_INT3IF_bm 0x08 /* Pin 3 Interrupt Flag bit mask. */ +#define PORT_INT3IF_bp 3 /* Pin 3 Interrupt Flag bit position. */ + +#define PORT_INT2IF_bm 0x04 /* Pin 2 Interrupt Flag bit mask. */ +#define PORT_INT2IF_bp 2 /* Pin 2 Interrupt Flag bit position. */ + +#define PORT_INT1IF_bm 0x02 /* Pin 1 Interrupt Flag bit mask. */ +#define PORT_INT1IF_bp 1 /* Pin 1 Interrupt Flag bit position. */ + +#define PORT_INT0IF_bm 0x01 /* Pin 0 Interrupt Flag bit mask. */ +#define PORT_INT0IF_bp 0 /* Pin 0 Interrupt Flag bit position. */ + +/* PORT.REMAP bit masks and bit positions */ +#define PORT_USART0_bm 0x10 /* Usart0 bit mask. */ +#define PORT_USART0_bp 4 /* Usart0 bit position. */ + +#define PORT_TC4D_bm 0x08 /* Timer/Counter 4 Output Compare D bit mask. */ +#define PORT_TC4D_bp 3 /* Timer/Counter 4 Output Compare D bit position. */ + +#define PORT_TC4C_bm 0x04 /* Timer/Counter 4 Output Compare C bit mask. */ +#define PORT_TC4C_bp 2 /* Timer/Counter 4 Output Compare C bit position. */ + +#define PORT_TC4B_bm 0x02 /* Timer/Counter 4 Output Compare B bit mask. */ +#define PORT_TC4B_bp 1 /* Timer/Counter 4 Output Compare B bit position. */ + +#define PORT_TC4A_bm 0x01 /* Timer/Counter 4 Output Compare A bit mask. */ +#define PORT_TC4A_bp 0 /* Timer/Counter 4 Output Compare A bit position. */ + +/* PORT.PIN0CTRL bit masks and bit positions */ +#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ +#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ + +#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ +#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ +#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ +#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ +#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ +#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ +#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ +#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ + +#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ + +/* PORT.PIN1CTRL bit masks and bit positions */ +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN2CTRL bit masks and bit positions */ +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN3CTRL bit masks and bit positions */ +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN4CTRL bit masks and bit positions */ +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN5CTRL bit masks and bit positions */ +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN6CTRL bit masks and bit positions */ +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN7CTRL bit masks and bit positions */ +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* TC - 16-bit Timer/Counter With PWM */ +/* TC4.CTRLA bit masks and bit positions */ +#define TC4_SYNCHEN_bm 0x40 /* Synchronization Enabled bit mask. */ +#define TC4_SYNCHEN_bp 6 /* Synchronization Enabled bit position. */ + +#define TC4_EVSTART_bm 0x20 /* Start on Next Event bit mask. */ +#define TC4_EVSTART_bp 5 /* Start on Next Event bit position. */ + +#define TC4_UPSTOP_bm 0x10 /* Stop on Next Update bit mask. */ +#define TC4_UPSTOP_bp 4 /* Stop on Next Update bit position. */ + +#define TC4_CLKSEL_gm 0x0F /* Clock Select group mask. */ +#define TC4_CLKSEL_gp 0 /* Clock Select group position. */ +#define TC4_CLKSEL0_bm (1<<0) /* Clock Select bit 0 mask. */ +#define TC4_CLKSEL0_bp 0 /* Clock Select bit 0 position. */ +#define TC4_CLKSEL1_bm (1<<1) /* Clock Select bit 1 mask. */ +#define TC4_CLKSEL1_bp 1 /* Clock Select bit 1 position. */ +#define TC4_CLKSEL2_bm (1<<2) /* Clock Select bit 2 mask. */ +#define TC4_CLKSEL2_bp 2 /* Clock Select bit 2 position. */ +#define TC4_CLKSEL3_bm (1<<3) /* Clock Select bit 3 mask. */ +#define TC4_CLKSEL3_bp 3 /* Clock Select bit 3 position. */ + +/* TC4.CTRLB bit masks and bit positions */ +#define TC4_BYTEM_gm 0xC0 /* Byte Mode group mask. */ +#define TC4_BYTEM_gp 6 /* Byte Mode group position. */ +#define TC4_BYTEM0_bm (1<<6) /* Byte Mode bit 0 mask. */ +#define TC4_BYTEM0_bp 6 /* Byte Mode bit 0 position. */ +#define TC4_BYTEM1_bm (1<<7) /* Byte Mode bit 1 mask. */ +#define TC4_BYTEM1_bp 7 /* Byte Mode bit 1 position. */ + +#define TC4_CIRCEN_gm 0x30 /* Circular Buffer Enable group mask. */ +#define TC4_CIRCEN_gp 4 /* Circular Buffer Enable group position. */ +#define TC4_CIRCEN0_bm (1<<4) /* Circular Buffer Enable bit 0 mask. */ +#define TC4_CIRCEN0_bp 4 /* Circular Buffer Enable bit 0 position. */ +#define TC4_CIRCEN1_bm (1<<5) /* Circular Buffer Enable bit 1 mask. */ +#define TC4_CIRCEN1_bp 5 /* Circular Buffer Enable bit 1 position. */ + +#define TC4_WGMODE_gm 0x07 /* Waveform Generation Mode group mask. */ +#define TC4_WGMODE_gp 0 /* Waveform Generation Mode group position. */ +#define TC4_WGMODE0_bm (1<<0) /* Waveform Generation Mode bit 0 mask. */ +#define TC4_WGMODE0_bp 0 /* Waveform Generation Mode bit 0 position. */ +#define TC4_WGMODE1_bm (1<<1) /* Waveform Generation Mode bit 1 mask. */ +#define TC4_WGMODE1_bp 1 /* Waveform Generation Mode bit 1 position. */ +#define TC4_WGMODE2_bm (1<<2) /* Waveform Generation Mode bit 2 mask. */ +#define TC4_WGMODE2_bp 2 /* Waveform Generation Mode bit 2 position. */ + +/* TC4.CTRLC bit masks and bit positions */ +#define TC4_POLD_bm 0x80 /* Channel D Output Polarity bit mask. */ +#define TC4_POLD_bp 7 /* Channel D Output Polarity bit position. */ + +#define TC4_POLC_bm 0x40 /* Channel C Output Polarity bit mask. */ +#define TC4_POLC_bp 6 /* Channel C Output Polarity bit position. */ + +#define TC4_POLB_bm 0x20 /* Channel B Output Polarity bit mask. */ +#define TC4_POLB_bp 5 /* Channel B Output Polarity bit position. */ + +#define TC4_POLA_bm 0x10 /* Channel A Output Polarity bit mask. */ +#define TC4_POLA_bp 4 /* Channel A Output Polarity bit position. */ + +#define TC4_CMPD_bm 0x08 /* Channel D Compare Output Value bit mask. */ +#define TC4_CMPD_bp 3 /* Channel D Compare Output Value bit position. */ + +#define TC4_CMPC_bm 0x04 /* Channel C Compare Output Value bit mask. */ +#define TC4_CMPC_bp 2 /* Channel C Compare Output Value bit position. */ + +#define TC4_CMPB_bm 0x02 /* Channel B Compare Output Value bit mask. */ +#define TC4_CMPB_bp 1 /* Channel B Compare Output Value bit position. */ + +#define TC4_CMPA_bm 0x01 /* Channel A Compare Output Value bit mask. */ +#define TC4_CMPA_bp 0 /* Channel A Compare Output Value bit position. */ + +#define TC4_HCMPD_bm 0x80 /* High Channel D Compare Output Value bit mask. */ +#define TC4_HCMPD_bp 7 /* High Channel D Compare Output Value bit position. */ + +#define TC4_HCMPC_bm 0x40 /* High Channel C Compare Output Value bit mask. */ +#define TC4_HCMPC_bp 6 /* High Channel C Compare Output Value bit position. */ + +#define TC4_HCMPB_bm 0x20 /* High Channel B Compare Output Value bit mask. */ +#define TC4_HCMPB_bp 5 /* High Channel B Compare Output Value bit position. */ + +#define TC4_HCMPA_bm 0x10 /* High Channel A Compare Output Value bit mask. */ +#define TC4_HCMPA_bp 4 /* High Channel A Compare Output Value bit position. */ + +#define TC4_LCMPD_bm 0x08 /* Low Channel D Compare Output Value bit mask. */ +#define TC4_LCMPD_bp 3 /* Low Channel D Compare Output Value bit position. */ + +#define TC4_LCMPC_bm 0x04 /* Low Channel C Compare Output Value bit mask. */ +#define TC4_LCMPC_bp 2 /* Low Channel C Compare Output Value bit position. */ + +#define TC4_LCMPB_bm 0x02 /* Low Channel B Compare Output Value bit mask. */ +#define TC4_LCMPB_bp 1 /* Low Channel B Compare Output Value bit position. */ + +#define TC4_LCMPA_bm 0x01 /* Low Channel A Compare Output Value bit mask. */ +#define TC4_LCMPA_bp 0 /* Low Channel A Compare Output Value bit position. */ + +/* TC4.CTRLD bit masks and bit positions */ +#define TC4_EVACT_gm 0xE0 /* Event Action group mask. */ +#define TC4_EVACT_gp 5 /* Event Action group position. */ +#define TC4_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +#define TC4_EVACT0_bp 5 /* Event Action bit 0 position. */ +#define TC4_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +#define TC4_EVACT1_bp 6 /* Event Action bit 1 position. */ +#define TC4_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +#define TC4_EVACT2_bp 7 /* Event Action bit 2 position. */ + +#define TC4_EVDLY_bm 0x10 /* Event Delay bit mask. */ +#define TC4_EVDLY_bp 4 /* Event Delay bit position. */ + +#define TC4_EVSEL_gm 0x0F /* Event Source Select group mask. */ +#define TC4_EVSEL_gp 0 /* Event Source Select group position. */ +#define TC4_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +#define TC4_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +#define TC4_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +#define TC4_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +#define TC4_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +#define TC4_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +#define TC4_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +#define TC4_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ + +/* TC4.CTRLE bit masks and bit positions */ +#define TC4_CCDMODE_gm 0xC0 /* Channel D Compare or Capture Mode group mask. */ +#define TC4_CCDMODE_gp 6 /* Channel D Compare or Capture Mode group position. */ +#define TC4_CCDMODE0_bm (1<<6) /* Channel D Compare or Capture Mode bit 0 mask. */ +#define TC4_CCDMODE0_bp 6 /* Channel D Compare or Capture Mode bit 0 position. */ +#define TC4_CCDMODE1_bm (1<<7) /* Channel D Compare or Capture Mode bit 1 mask. */ +#define TC4_CCDMODE1_bp 7 /* Channel D Compare or Capture Mode bit 1 position. */ + +#define TC4_CCCMODE_gm 0x30 /* Channel C Compare or Capture Mode group mask. */ +#define TC4_CCCMODE_gp 4 /* Channel C Compare or Capture Mode group position. */ +#define TC4_CCCMODE0_bm (1<<4) /* Channel C Compare or Capture Mode bit 0 mask. */ +#define TC4_CCCMODE0_bp 4 /* Channel C Compare or Capture Mode bit 0 position. */ +#define TC4_CCCMODE1_bm (1<<5) /* Channel C Compare or Capture Mode bit 1 mask. */ +#define TC4_CCCMODE1_bp 5 /* Channel C Compare or Capture Mode bit 1 position. */ + +#define TC4_CCBMODE_gm 0x0C /* Channel B Compare or Capture Mode group mask. */ +#define TC4_CCBMODE_gp 2 /* Channel B Compare or Capture Mode group position. */ +#define TC4_CCBMODE0_bm (1<<2) /* Channel B Compare or Capture Mode bit 0 mask. */ +#define TC4_CCBMODE0_bp 2 /* Channel B Compare or Capture Mode bit 0 position. */ +#define TC4_CCBMODE1_bm (1<<3) /* Channel B Compare or Capture Mode bit 1 mask. */ +#define TC4_CCBMODE1_bp 3 /* Channel B Compare or Capture Mode bit 1 position. */ + +#define TC4_CCAMODE_gm 0x03 /* Channel A Compare or Capture Mode group mask. */ +#define TC4_CCAMODE_gp 0 /* Channel A Compare or Capture Mode group position. */ +#define TC4_CCAMODE0_bm (1<<0) /* Channel A Compare or Capture Mode bit 0 mask. */ +#define TC4_CCAMODE0_bp 0 /* Channel A Compare or Capture Mode bit 0 position. */ +#define TC4_CCAMODE1_bm (1<<1) /* Channel A Compare or Capture Mode bit 1 mask. */ +#define TC4_CCAMODE1_bp 1 /* Channel A Compare or Capture Mode bit 1 position. */ + +#define TC4_LCCDMODE_gm 0xC0 /* Channel Low D Compare or Capture Mode group mask. */ +#define TC4_LCCDMODE_gp 6 /* Channel Low D Compare or Capture Mode group position. */ +#define TC4_LCCDMODE0_bm (1<<6) /* Channel Low D Compare or Capture Mode bit 0 mask. */ +#define TC4_LCCDMODE0_bp 6 /* Channel Low D Compare or Capture Mode bit 0 position. */ +#define TC4_LCCDMODE1_bm (1<<7) /* Channel Low D Compare or Capture Mode bit 1 mask. */ +#define TC4_LCCDMODE1_bp 7 /* Channel Low D Compare or Capture Mode bit 1 position. */ + +#define TC4_LCCCMODE_gm 0x30 /* Channel Low C Compare or Capture Mode group mask. */ +#define TC4_LCCCMODE_gp 4 /* Channel Low C Compare or Capture Mode group position. */ +#define TC4_LCCCMODE0_bm (1<<4) /* Channel Low C Compare or Capture Mode bit 0 mask. */ +#define TC4_LCCCMODE0_bp 4 /* Channel Low C Compare or Capture Mode bit 0 position. */ +#define TC4_LCCCMODE1_bm (1<<5) /* Channel Low C Compare or Capture Mode bit 1 mask. */ +#define TC4_LCCCMODE1_bp 5 /* Channel Low C Compare or Capture Mode bit 1 position. */ + +#define TC4_LCCBMODE_gm 0x0C /* Channel Low B Compare or Capture Mode group mask. */ +#define TC4_LCCBMODE_gp 2 /* Channel Low B Compare or Capture Mode group position. */ +#define TC4_LCCBMODE0_bm (1<<2) /* Channel Low B Compare or Capture Mode bit 0 mask. */ +#define TC4_LCCBMODE0_bp 2 /* Channel Low B Compare or Capture Mode bit 0 position. */ +#define TC4_LCCBMODE1_bm (1<<3) /* Channel Low B Compare or Capture Mode bit 1 mask. */ +#define TC4_LCCBMODE1_bp 3 /* Channel Low B Compare or Capture Mode bit 1 position. */ + +#define TC4_LCCAMODE_gm 0x03 /* Channel Low A Compare or Capture Mode group mask. */ +#define TC4_LCCAMODE_gp 0 /* Channel Low A Compare or Capture Mode group position. */ +#define TC4_LCCAMODE0_bm (1<<0) /* Channel Low A Compare or Capture Mode bit 0 mask. */ +#define TC4_LCCAMODE0_bp 0 /* Channel Low A Compare or Capture Mode bit 0 position. */ +#define TC4_LCCAMODE1_bm (1<<1) /* Channel Low A Compare or Capture Mode bit 1 mask. */ +#define TC4_LCCAMODE1_bp 1 /* Channel Low A Compare or Capture Mode bit 1 position. */ + +/* TC4.CTRLF bit masks and bit positions */ +#define TC4_HCCDMODE_gm 0xC0 /* Channel High D Compare or Capture Mode group mask. */ +#define TC4_HCCDMODE_gp 6 /* Channel High D Compare or Capture Mode group position. */ +#define TC4_HCCDMODE0_bm (1<<6) /* Channel High D Compare or Capture Mode bit 0 mask. */ +#define TC4_HCCDMODE0_bp 6 /* Channel High D Compare or Capture Mode bit 0 position. */ +#define TC4_HCCDMODE1_bm (1<<7) /* Channel High D Compare or Capture Mode bit 1 mask. */ +#define TC4_HCCDMODE1_bp 7 /* Channel High D Compare or Capture Mode bit 1 position. */ + +#define TC4_HCCCMODE_gm 0x30 /* Channel High C Compare or Capture Mode group mask. */ +#define TC4_HCCCMODE_gp 4 /* Channel High C Compare or Capture Mode group position. */ +#define TC4_HCCCMODE0_bm (1<<4) /* Channel High C Compare or Capture Mode bit 0 mask. */ +#define TC4_HCCCMODE0_bp 4 /* Channel High C Compare or Capture Mode bit 0 position. */ +#define TC4_HCCCMODE1_bm (1<<5) /* Channel High C Compare or Capture Mode bit 1 mask. */ +#define TC4_HCCCMODE1_bp 5 /* Channel High C Compare or Capture Mode bit 1 position. */ + +#define TC4_HCCBMODE_gm 0x0C /* Channel High B Compare or Capture Mode group mask. */ +#define TC4_HCCBMODE_gp 2 /* Channel High B Compare or Capture Mode group position. */ +#define TC4_HCCBMODE0_bm (1<<2) /* Channel High B Compare or Capture Mode bit 0 mask. */ +#define TC4_HCCBMODE0_bp 2 /* Channel High B Compare or Capture Mode bit 0 position. */ +#define TC4_HCCBMODE1_bm (1<<3) /* Channel High B Compare or Capture Mode bit 1 mask. */ +#define TC4_HCCBMODE1_bp 3 /* Channel High B Compare or Capture Mode bit 1 position. */ + +#define TC4_HCCAMODE_gm 0x03 /* Channel High A Compare or Capture Mode group mask. */ +#define TC4_HCCAMODE_gp 0 /* Channel High A Compare or Capture Mode group position. */ +#define TC4_HCCAMODE0_bm (1<<0) /* Channel High A Compare or Capture Mode bit 0 mask. */ +#define TC4_HCCAMODE0_bp 0 /* Channel High A Compare or Capture Mode bit 0 position. */ +#define TC4_HCCAMODE1_bm (1<<1) /* Channel High A Compare or Capture Mode bit 1 mask. */ +#define TC4_HCCAMODE1_bp 1 /* Channel High A Compare or Capture Mode bit 1 position. */ + +/* TC4.INTCTRLA bit masks and bit positions */ +#define TC4_TRGINTLVL_gm 0x30 /* Timer Trigger Restart Interrupt Level group mask. */ +#define TC4_TRGINTLVL_gp 4 /* Timer Trigger Restart Interrupt Level group position. */ +#define TC4_TRGINTLVL0_bm (1<<4) /* Timer Trigger Restart Interrupt Level bit 0 mask. */ +#define TC4_TRGINTLVL0_bp 4 /* Timer Trigger Restart Interrupt Level bit 0 position. */ +#define TC4_TRGINTLVL1_bm (1<<5) /* Timer Trigger Restart Interrupt Level bit 1 mask. */ +#define TC4_TRGINTLVL1_bp 5 /* Timer Trigger Restart Interrupt Level bit 1 position. */ + +#define TC4_ERRINTLVL_gm 0x0C /* Timer Error Interrupt Level group mask. */ +#define TC4_ERRINTLVL_gp 2 /* Timer Error Interrupt Level group position. */ +#define TC4_ERRINTLVL0_bm (1<<2) /* Timer Error Interrupt Level bit 0 mask. */ +#define TC4_ERRINTLVL0_bp 2 /* Timer Error Interrupt Level bit 0 position. */ +#define TC4_ERRINTLVL1_bm (1<<3) /* Timer Error Interrupt Level bit 1 mask. */ +#define TC4_ERRINTLVL1_bp 3 /* Timer Error Interrupt Level bit 1 position. */ + +#define TC4_OVFINTLVL_gm 0x03 /* Timer Overflow/Underflow Interrupt Level group mask. */ +#define TC4_OVFINTLVL_gp 0 /* Timer Overflow/Underflow Interrupt Level group position. */ +#define TC4_OVFINTLVL0_bm (1<<0) /* Timer Overflow/Underflow Interrupt Level bit 0 mask. */ +#define TC4_OVFINTLVL0_bp 0 /* Timer Overflow/Underflow Interrupt Level bit 0 position. */ +#define TC4_OVFINTLVL1_bm (1<<1) /* Timer Overflow/Underflow Interrupt Level bit 1 mask. */ +#define TC4_OVFINTLVL1_bp 1 /* Timer Overflow/Underflow Interrupt Level bit 1 position. */ + +/* TC4.INTCTRLB bit masks and bit positions */ +#define TC4_CCDINTLVL_gm 0xC0 /* Channel D Compare or Capture Interrupt Level group mask. */ +#define TC4_CCDINTLVL_gp 6 /* Channel D Compare or Capture Interrupt Level group position. */ +#define TC4_CCDINTLVL0_bm (1<<6) /* Channel D Compare or Capture Interrupt Level bit 0 mask. */ +#define TC4_CCDINTLVL0_bp 6 /* Channel D Compare or Capture Interrupt Level bit 0 position. */ +#define TC4_CCDINTLVL1_bm (1<<7) /* Channel D Compare or Capture Interrupt Level bit 1 mask. */ +#define TC4_CCDINTLVL1_bp 7 /* Channel D Compare or Capture Interrupt Level bit 1 position. */ + +#define TC4_CCCINTLVL_gm 0x30 /* Channel C Compare or Capture Interrupt Level group mask. */ +#define TC4_CCCINTLVL_gp 4 /* Channel C Compare or Capture Interrupt Level group position. */ +#define TC4_CCCINTLVL0_bm (1<<4) /* Channel C Compare or Capture Interrupt Level bit 0 mask. */ +#define TC4_CCCINTLVL0_bp 4 /* Channel C Compare or Capture Interrupt Level bit 0 position. */ +#define TC4_CCCINTLVL1_bm (1<<5) /* Channel C Compare or Capture Interrupt Level bit 1 mask. */ +#define TC4_CCCINTLVL1_bp 5 /* Channel C Compare or Capture Interrupt Level bit 1 position. */ + +#define TC4_CCBINTLVL_gm 0x0C /* Channel B Compare or Capture Interrupt Level group mask. */ +#define TC4_CCBINTLVL_gp 2 /* Channel B Compare or Capture Interrupt Level group position. */ +#define TC4_CCBINTLVL0_bm (1<<2) /* Channel B Compare or Capture Interrupt Level bit 0 mask. */ +#define TC4_CCBINTLVL0_bp 2 /* Channel B Compare or Capture Interrupt Level bit 0 position. */ +#define TC4_CCBINTLVL1_bm (1<<3) /* Channel B Compare or Capture Interrupt Level bit 1 mask. */ +#define TC4_CCBINTLVL1_bp 3 /* Channel B Compare or Capture Interrupt Level bit 1 position. */ + +#define TC4_CCAINTLVL_gm 0x03 /* Channel A Compare or Capture Interrupt Level group mask. */ +#define TC4_CCAINTLVL_gp 0 /* Channel A Compare or Capture Interrupt Level group position. */ +#define TC4_CCAINTLVL0_bm (1<<0) /* Channel A Compare or Capture Interrupt Level bit 0 mask. */ +#define TC4_CCAINTLVL0_bp 0 /* Channel A Compare or Capture Interrupt Level bit 0 position. */ +#define TC4_CCAINTLVL1_bm (1<<1) /* Channel A Compare or Capture Interrupt Level bit 1 mask. */ +#define TC4_CCAINTLVL1_bp 1 /* Channel A Compare or Capture Interrupt Level bit 1 position. */ + +#define TC4_LCCDINTLVL_gm 0xC0 /* Channel Low D Compare or Capture Interrupt Level group mask. */ +#define TC4_LCCDINTLVL_gp 6 /* Channel Low D Compare or Capture Interrupt Level group position. */ +#define TC4_LCCDINTLVL0_bm (1<<6) /* Channel Low D Compare or Capture Interrupt Level bit 0 mask. */ +#define TC4_LCCDINTLVL0_bp 6 /* Channel Low D Compare or Capture Interrupt Level bit 0 position. */ +#define TC4_LCCDINTLVL1_bm (1<<7) /* Channel Low D Compare or Capture Interrupt Level bit 1 mask. */ +#define TC4_LCCDINTLVL1_bp 7 /* Channel Low D Compare or Capture Interrupt Level bit 1 position. */ + +#define TC4_LCCCINTLVL_gm 0x30 /* Channel Low C Compare or Capture Interrupt Level group mask. */ +#define TC4_LCCCINTLVL_gp 4 /* Channel Low C Compare or Capture Interrupt Level group position. */ +#define TC4_LCCCINTLVL0_bm (1<<4) /* Channel Low C Compare or Capture Interrupt Level bit 0 mask. */ +#define TC4_LCCCINTLVL0_bp 4 /* Channel Low C Compare or Capture Interrupt Level bit 0 position. */ +#define TC4_LCCCINTLVL1_bm (1<<5) /* Channel Low C Compare or Capture Interrupt Level bit 1 mask. */ +#define TC4_LCCCINTLVL1_bp 5 /* Channel Low C Compare or Capture Interrupt Level bit 1 position. */ + +#define TC4_LCCBINTLVL_gm 0x0C /* Channel Low B Compare or Capture Interrupt Level group mask. */ +#define TC4_LCCBINTLVL_gp 2 /* Channel Low B Compare or Capture Interrupt Level group position. */ +#define TC4_LCCBINTLVL0_bm (1<<2) /* Channel Low B Compare or Capture Interrupt Level bit 0 mask. */ +#define TC4_LCCBINTLVL0_bp 2 /* Channel Low B Compare or Capture Interrupt Level bit 0 position. */ +#define TC4_LCCBINTLVL1_bm (1<<3) /* Channel Low B Compare or Capture Interrupt Level bit 1 mask. */ +#define TC4_LCCBINTLVL1_bp 3 /* Channel Low B Compare or Capture Interrupt Level bit 1 position. */ + +#define TC4_LCCAINTLVL_gm 0x03 /* Channel Low A Compare or Capture Interrupt Level group mask. */ +#define TC4_LCCAINTLVL_gp 0 /* Channel Low A Compare or Capture Interrupt Level group position. */ +#define TC4_LCCAINTLVL0_bm (1<<0) /* Channel Low A Compare or Capture Interrupt Level bit 0 mask. */ +#define TC4_LCCAINTLVL0_bp 0 /* Channel Low A Compare or Capture Interrupt Level bit 0 position. */ +#define TC4_LCCAINTLVL1_bm (1<<1) /* Channel Low A Compare or Capture Interrupt Level bit 1 mask. */ +#define TC4_LCCAINTLVL1_bp 1 /* Channel Low A Compare or Capture Interrupt Level bit 1 position. */ + +/* TC4.CTRLGCLR bit masks and bit positions */ +#define TC4_STOP_bm 0x20 /* Timer/Counter Stop bit mask. */ +#define TC4_STOP_bp 5 /* Timer/Counter Stop bit position. */ + +#define TC4_CMD_gm 0x0C /* Command group mask. */ +#define TC4_CMD_gp 2 /* Command group position. */ +#define TC4_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC4_CMD0_bp 2 /* Command bit 0 position. */ +#define TC4_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC4_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC4_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TC4_LUPD_bp 1 /* Lock Update bit position. */ + +#define TC4_DIR_bm 0x01 /* Counter Direction bit mask. */ +#define TC4_DIR_bp 0 /* Counter Direction bit position. */ + +/* TC4.CTRLGSET bit masks and bit positions */ +/* TC4_STOP Predefined. */ +/* TC4_STOP Predefined. */ + +/* TC4_CMD Predefined. */ +/* TC4_CMD Predefined. */ + +/* TC4_LUPD Predefined. */ +/* TC4_LUPD Predefined. */ + +/* TC4_DIR Predefined. */ +/* TC4_DIR Predefined. */ + +/* TC4.CTRLHCLR bit masks and bit positions */ +#define TC4_CCDBV_bm 0x10 /* Channel D Compare or Capture Buffer Valid bit mask. */ +#define TC4_CCDBV_bp 4 /* Channel D Compare or Capture Buffer Valid bit position. */ + +#define TC4_CCCBV_bm 0x08 /* Channel C Compare or Capture Buffer Valid bit mask. */ +#define TC4_CCCBV_bp 3 /* Channel C Compare or Capture Buffer Valid bit position. */ + +#define TC4_CCBBV_bm 0x04 /* Channel B Compare or Capture Buffer Valid bit mask. */ +#define TC4_CCBBV_bp 2 /* Channel B Compare or Capture Buffer Valid bit position. */ + +#define TC4_CCABV_bm 0x02 /* Channel A Compare or Capture Buffer Valid bit mask. */ +#define TC4_CCABV_bp 1 /* Channel A Compare or Capture Buffer Valid bit position. */ + +#define TC4_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TC4_PERBV_bp 0 /* Period Buffer Valid bit position. */ + +#define TC4_LCCDBV_bm 0x10 /* Channel Low D Compare or Capture Buffer Valid bit mask. */ +#define TC4_LCCDBV_bp 4 /* Channel Low D Compare or Capture Buffer Valid bit position. */ + +#define TC4_LCCCBV_bm 0x08 /* Channel Low C Compare or Capture Buffer Valid bit mask. */ +#define TC4_LCCCBV_bp 3 /* Channel Low C Compare or Capture Buffer Valid bit position. */ + +#define TC4_LCCBBV_bm 0x04 /* Channel Low B Compare or Capture Buffer Valid bit mask. */ +#define TC4_LCCBBV_bp 2 /* Channel Low B Compare or Capture Buffer Valid bit position. */ + +#define TC4_LCCABV_bm 0x02 /* Channel Low A Compare or Capture Buffer Valid bit mask. */ +#define TC4_LCCABV_bp 1 /* Channel Low A Compare or Capture Buffer Valid bit position. */ + +#define TC4_LPERBV_bm 0x01 /* Period Low Buffer Valid bit mask. */ +#define TC4_LPERBV_bp 0 /* Period Low Buffer Valid bit position. */ + +/* TC4.CTRLHSET bit masks and bit positions */ +/* TC4_CCDBV Predefined. */ +/* TC4_CCDBV Predefined. */ + +/* TC4_CCCBV Predefined. */ +/* TC4_CCCBV Predefined. */ + +/* TC4_CCBBV Predefined. */ +/* TC4_CCBBV Predefined. */ + +/* TC4_CCABV Predefined. */ +/* TC4_CCABV Predefined. */ + +/* TC4_PERBV Predefined. */ +/* TC4_PERBV Predefined. */ + +/* TC4_LCCDBV Predefined. */ +/* TC4_LCCDBV Predefined. */ + +/* TC4_LCCCBV Predefined. */ +/* TC4_LCCCBV Predefined. */ + +/* TC4_LCCBBV Predefined. */ +/* TC4_LCCBBV Predefined. */ + +/* TC4_LCCABV Predefined. */ +/* TC4_LCCABV Predefined. */ + +/* TC4_LPERBV Predefined. */ +/* TC4_LPERBV Predefined. */ + +/* TC4.INTFLAGS bit masks and bit positions */ +#define TC4_CCDIF_bm 0x80 /* Channel D Compare or Capture Interrupt Flag bit mask. */ +#define TC4_CCDIF_bp 7 /* Channel D Compare or Capture Interrupt Flag bit position. */ + +#define TC4_CCCIF_bm 0x40 /* Channel C Compare or Capture Interrupt Flag bit mask. */ +#define TC4_CCCIF_bp 6 /* Channel C Compare or Capture Interrupt Flag bit position. */ + +#define TC4_CCBIF_bm 0x20 /* Channel B Compare or Capture Interrupt Flag bit mask. */ +#define TC4_CCBIF_bp 5 /* Channel B Compare or Capture Interrupt Flag bit position. */ + +#define TC4_CCAIF_bm 0x10 /* Channel A Compare or Capture Interrupt Flag bit mask. */ +#define TC4_CCAIF_bp 4 /* Channel A Compare or Capture Interrupt Flag bit position. */ + +#define TC4_TRGIF_bm 0x04 /* Trigger Restart Interrupt Flag bit mask. */ +#define TC4_TRGIF_bp 2 /* Trigger Restart Interrupt Flag bit position. */ + +#define TC4_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +#define TC4_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ + +#define TC4_OVFIF_bm 0x01 /* Overflow/Underflow Interrupt Flag bit mask. */ +#define TC4_OVFIF_bp 0 /* Overflow/Underflow Interrupt Flag bit position. */ + +#define TC4_LCCDIF_bm 0x80 /* Channel Low D Compare or Capture Interrupt Flag bit mask. */ +#define TC4_LCCDIF_bp 7 /* Channel Low D Compare or Capture Interrupt Flag bit position. */ + +#define TC4_LCCCIF_bm 0x40 /* Channel Low C Compare or Capture Interrupt Flag bit mask. */ +#define TC4_LCCCIF_bp 6 /* Channel Low C Compare or Capture Interrupt Flag bit position. */ + +#define TC4_LCCBIF_bm 0x20 /* Channel Low B Compare or Capture Interrupt Flag bit mask. */ +#define TC4_LCCBIF_bp 5 /* Channel Low B Compare or Capture Interrupt Flag bit position. */ + +#define TC4_LCCAIF_bm 0x10 /* Channel Low A Compare or Capture Interrupt Flag bit mask. */ +#define TC4_LCCAIF_bp 4 /* Channel Low A Compare or Capture Interrupt Flag bit position. */ + +/* TC5.CTRLA bit masks and bit positions */ +#define TC5_SYNCHEN_bm 0x40 /* Synchronization Enabled bit mask. */ +#define TC5_SYNCHEN_bp 6 /* Synchronization Enabled bit position. */ + +#define TC5_EVSTART_bm 0x20 /* Start on Next Event bit mask. */ +#define TC5_EVSTART_bp 5 /* Start on Next Event bit position. */ + +#define TC5_UPSTOP_bm 0x10 /* Stop on Next Update bit mask. */ +#define TC5_UPSTOP_bp 4 /* Stop on Next Update bit position. */ + +#define TC5_CLKSEL_gm 0x0F /* Clock Select group mask. */ +#define TC5_CLKSEL_gp 0 /* Clock Select group position. */ +#define TC5_CLKSEL0_bm (1<<0) /* Clock Select bit 0 mask. */ +#define TC5_CLKSEL0_bp 0 /* Clock Select bit 0 position. */ +#define TC5_CLKSEL1_bm (1<<1) /* Clock Select bit 1 mask. */ +#define TC5_CLKSEL1_bp 1 /* Clock Select bit 1 position. */ +#define TC5_CLKSEL2_bm (1<<2) /* Clock Select bit 2 mask. */ +#define TC5_CLKSEL2_bp 2 /* Clock Select bit 2 position. */ +#define TC5_CLKSEL3_bm (1<<3) /* Clock Select bit 3 mask. */ +#define TC5_CLKSEL3_bp 3 /* Clock Select bit 3 position. */ + +/* TC5.CTRLB bit masks and bit positions */ +#define TC5_BYTEM_gm 0xC0 /* Byte Mode group mask. */ +#define TC5_BYTEM_gp 6 /* Byte Mode group position. */ +#define TC5_BYTEM0_bm (1<<6) /* Byte Mode bit 0 mask. */ +#define TC5_BYTEM0_bp 6 /* Byte Mode bit 0 position. */ +#define TC5_BYTEM1_bm (1<<7) /* Byte Mode bit 1 mask. */ +#define TC5_BYTEM1_bp 7 /* Byte Mode bit 1 position. */ + +#define TC5_CIRCEN_gm 0x30 /* Circular Buffer Enable group mask. */ +#define TC5_CIRCEN_gp 4 /* Circular Buffer Enable group position. */ +#define TC5_CIRCEN0_bm (1<<4) /* Circular Buffer Enable bit 0 mask. */ +#define TC5_CIRCEN0_bp 4 /* Circular Buffer Enable bit 0 position. */ +#define TC5_CIRCEN1_bm (1<<5) /* Circular Buffer Enable bit 1 mask. */ +#define TC5_CIRCEN1_bp 5 /* Circular Buffer Enable bit 1 position. */ + +#define TC5_WGMODE_gm 0x07 /* Waveform Generation Mode group mask. */ +#define TC5_WGMODE_gp 0 /* Waveform Generation Mode group position. */ +#define TC5_WGMODE0_bm (1<<0) /* Waveform Generation Mode bit 0 mask. */ +#define TC5_WGMODE0_bp 0 /* Waveform Generation Mode bit 0 position. */ +#define TC5_WGMODE1_bm (1<<1) /* Waveform Generation Mode bit 1 mask. */ +#define TC5_WGMODE1_bp 1 /* Waveform Generation Mode bit 1 position. */ +#define TC5_WGMODE2_bm (1<<2) /* Waveform Generation Mode bit 2 mask. */ +#define TC5_WGMODE2_bp 2 /* Waveform Generation Mode bit 2 position. */ + +/* TC5.CTRLC bit masks and bit positions */ +#define TC5_POLB_bm 0x20 /* Channel B Output Polarity bit mask. */ +#define TC5_POLB_bp 5 /* Channel B Output Polarity bit position. */ + +#define TC5_POLA_bm 0x10 /* Channel A Output Polarity bit mask. */ +#define TC5_POLA_bp 4 /* Channel A Output Polarity bit position. */ + +#define TC5_CMPB_bm 0x02 /* Channel B Compare Output Value bit mask. */ +#define TC5_CMPB_bp 1 /* Channel B Compare Output Value bit position. */ + +#define TC5_CMPA_bm 0x01 /* Channel A Compare Output Value bit mask. */ +#define TC5_CMPA_bp 0 /* Channel A Compare Output Value bit position. */ + +#define TC5_HCMPB_bm 0x20 /* High Channel B Compare Output Value bit mask. */ +#define TC5_HCMPB_bp 5 /* High Channel B Compare Output Value bit position. */ + +#define TC5_HCMPA_bm 0x10 /* High Channel A Compare Output Value bit mask. */ +#define TC5_HCMPA_bp 4 /* High Channel A Compare Output Value bit position. */ + +#define TC5_LCMPB_bm 0x02 /* Low Channel B Compare Output Value bit mask. */ +#define TC5_LCMPB_bp 1 /* Low Channel B Compare Output Value bit position. */ + +#define TC5_LCMPA_bm 0x01 /* Low Channel A Compare Output Value bit mask. */ +#define TC5_LCMPA_bp 0 /* Low Channel A Compare Output Value bit position. */ + +/* TC5.CTRLD bit masks and bit positions */ +#define TC5_EVACT_gm 0xE0 /* Event Action group mask. */ +#define TC5_EVACT_gp 5 /* Event Action group position. */ +#define TC5_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +#define TC5_EVACT0_bp 5 /* Event Action bit 0 position. */ +#define TC5_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +#define TC5_EVACT1_bp 6 /* Event Action bit 1 position. */ +#define TC5_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +#define TC5_EVACT2_bp 7 /* Event Action bit 2 position. */ + +#define TC5_EVDLY_bm 0x10 /* Event Delay bit mask. */ +#define TC5_EVDLY_bp 4 /* Event Delay bit position. */ + +#define TC5_EVSEL_gm 0x0F /* Event Source Select group mask. */ +#define TC5_EVSEL_gp 0 /* Event Source Select group position. */ +#define TC5_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +#define TC5_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +#define TC5_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +#define TC5_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +#define TC5_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +#define TC5_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +#define TC5_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +#define TC5_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ + +/* TC5.CTRLE bit masks and bit positions */ +#define TC5_CCBMODE_gm 0x0C /* Channel B Compare or Capture Mode group mask. */ +#define TC5_CCBMODE_gp 2 /* Channel B Compare or Capture Mode group position. */ +#define TC5_CCBMODE0_bm (1<<2) /* Channel B Compare or Capture Mode bit 0 mask. */ +#define TC5_CCBMODE0_bp 2 /* Channel B Compare or Capture Mode bit 0 position. */ +#define TC5_CCBMODE1_bm (1<<3) /* Channel B Compare or Capture Mode bit 1 mask. */ +#define TC5_CCBMODE1_bp 3 /* Channel B Compare or Capture Mode bit 1 position. */ + +#define TC5_CCAMODE_gm 0x03 /* Channel A Compare or Capture Mode group mask. */ +#define TC5_CCAMODE_gp 0 /* Channel A Compare or Capture Mode group position. */ +#define TC5_CCAMODE0_bm (1<<0) /* Channel A Compare or Capture Mode bit 0 mask. */ +#define TC5_CCAMODE0_bp 0 /* Channel A Compare or Capture Mode bit 0 position. */ +#define TC5_CCAMODE1_bm (1<<1) /* Channel A Compare or Capture Mode bit 1 mask. */ +#define TC5_CCAMODE1_bp 1 /* Channel A Compare or Capture Mode bit 1 position. */ + +#define TC5_LCCBMODE_gm 0x0C /* Channel Low B Compare or Capture Mode group mask. */ +#define TC5_LCCBMODE_gp 2 /* Channel Low B Compare or Capture Mode group position. */ +#define TC5_LCCBMODE0_bm (1<<2) /* Channel Low B Compare or Capture Mode bit 0 mask. */ +#define TC5_LCCBMODE0_bp 2 /* Channel Low B Compare or Capture Mode bit 0 position. */ +#define TC5_LCCBMODE1_bm (1<<3) /* Channel Low B Compare or Capture Mode bit 1 mask. */ +#define TC5_LCCBMODE1_bp 3 /* Channel Low B Compare or Capture Mode bit 1 position. */ + +#define TC5_LCCAMODE_gm 0x03 /* Channel Low A Compare or Capture Mode group mask. */ +#define TC5_LCCAMODE_gp 0 /* Channel Low A Compare or Capture Mode group position. */ +#define TC5_LCCAMODE0_bm (1<<0) /* Channel Low A Compare or Capture Mode bit 0 mask. */ +#define TC5_LCCAMODE0_bp 0 /* Channel Low A Compare or Capture Mode bit 0 position. */ +#define TC5_LCCAMODE1_bm (1<<1) /* Channel Low A Compare or Capture Mode bit 1 mask. */ +#define TC5_LCCAMODE1_bp 1 /* Channel Low A Compare or Capture Mode bit 1 position. */ + +/* TC5.CTRLF bit masks and bit positions */ +#define TC5_HCCBMODE_gm 0x0C /* Channel High B Compare or Capture Mode group mask. */ +#define TC5_HCCBMODE_gp 2 /* Channel High B Compare or Capture Mode group position. */ +#define TC5_HCCBMODE0_bm (1<<2) /* Channel High B Compare or Capture Mode bit 0 mask. */ +#define TC5_HCCBMODE0_bp 2 /* Channel High B Compare or Capture Mode bit 0 position. */ +#define TC5_HCCBMODE1_bm (1<<3) /* Channel High B Compare or Capture Mode bit 1 mask. */ +#define TC5_HCCBMODE1_bp 3 /* Channel High B Compare or Capture Mode bit 1 position. */ + +#define TC5_HCCAMODE_gm 0x03 /* Channel High A Compare or Capture Mode group mask. */ +#define TC5_HCCAMODE_gp 0 /* Channel High A Compare or Capture Mode group position. */ +#define TC5_HCCAMODE0_bm (1<<0) /* Channel High A Compare or Capture Mode bit 0 mask. */ +#define TC5_HCCAMODE0_bp 0 /* Channel High A Compare or Capture Mode bit 0 position. */ +#define TC5_HCCAMODE1_bm (1<<1) /* Channel High A Compare or Capture Mode bit 1 mask. */ +#define TC5_HCCAMODE1_bp 1 /* Channel High A Compare or Capture Mode bit 1 position. */ + +/* TC5.INTCTRLA bit masks and bit positions */ +#define TC5_TRGINTLVL_gm 0x30 /* Timer Trigger Restart Interrupt Level group mask. */ +#define TC5_TRGINTLVL_gp 4 /* Timer Trigger Restart Interrupt Level group position. */ +#define TC5_TRGINTLVL0_bm (1<<4) /* Timer Trigger Restart Interrupt Level bit 0 mask. */ +#define TC5_TRGINTLVL0_bp 4 /* Timer Trigger Restart Interrupt Level bit 0 position. */ +#define TC5_TRGINTLVL1_bm (1<<5) /* Timer Trigger Restart Interrupt Level bit 1 mask. */ +#define TC5_TRGINTLVL1_bp 5 /* Timer Trigger Restart Interrupt Level bit 1 position. */ + +#define TC5_ERRINTLVL_gm 0x0C /* Timer Error Interrupt Level group mask. */ +#define TC5_ERRINTLVL_gp 2 /* Timer Error Interrupt Level group position. */ +#define TC5_ERRINTLVL0_bm (1<<2) /* Timer Error Interrupt Level bit 0 mask. */ +#define TC5_ERRINTLVL0_bp 2 /* Timer Error Interrupt Level bit 0 position. */ +#define TC5_ERRINTLVL1_bm (1<<3) /* Timer Error Interrupt Level bit 1 mask. */ +#define TC5_ERRINTLVL1_bp 3 /* Timer Error Interrupt Level bit 1 position. */ + +#define TC5_OVFINTLVL_gm 0x03 /* Timer Overflow/Underflow Interrupt Level group mask. */ +#define TC5_OVFINTLVL_gp 0 /* Timer Overflow/Underflow Interrupt Level group position. */ +#define TC5_OVFINTLVL0_bm (1<<0) /* Timer Overflow/Underflow Interrupt Level bit 0 mask. */ +#define TC5_OVFINTLVL0_bp 0 /* Timer Overflow/Underflow Interrupt Level bit 0 position. */ +#define TC5_OVFINTLVL1_bm (1<<1) /* Timer Overflow/Underflow Interrupt Level bit 1 mask. */ +#define TC5_OVFINTLVL1_bp 1 /* Timer Overflow/Underflow Interrupt Level bit 1 position. */ + +/* TC5.INTCTRLB bit masks and bit positions */ +#define TC5_CCBINTLVL_gm 0x0C /* Channel B Compare or Capture Interrupt Level group mask. */ +#define TC5_CCBINTLVL_gp 2 /* Channel B Compare or Capture Interrupt Level group position. */ +#define TC5_CCBINTLVL0_bm (1<<2) /* Channel B Compare or Capture Interrupt Level bit 0 mask. */ +#define TC5_CCBINTLVL0_bp 2 /* Channel B Compare or Capture Interrupt Level bit 0 position. */ +#define TC5_CCBINTLVL1_bm (1<<3) /* Channel B Compare or Capture Interrupt Level bit 1 mask. */ +#define TC5_CCBINTLVL1_bp 3 /* Channel B Compare or Capture Interrupt Level bit 1 position. */ + +#define TC5_CCAINTLVL_gm 0x03 /* Channel A Compare or Capture Interrupt Level group mask. */ +#define TC5_CCAINTLVL_gp 0 /* Channel A Compare or Capture Interrupt Level group position. */ +#define TC5_CCAINTLVL0_bm (1<<0) /* Channel A Compare or Capture Interrupt Level bit 0 mask. */ +#define TC5_CCAINTLVL0_bp 0 /* Channel A Compare or Capture Interrupt Level bit 0 position. */ +#define TC5_CCAINTLVL1_bm (1<<1) /* Channel A Compare or Capture Interrupt Level bit 1 mask. */ +#define TC5_CCAINTLVL1_bp 1 /* Channel A Compare or Capture Interrupt Level bit 1 position. */ + +#define TC5_LCCBINTLVL_gm 0x0C /* Channel Low B Compare or Capture Interrupt Level group mask. */ +#define TC5_LCCBINTLVL_gp 2 /* Channel Low B Compare or Capture Interrupt Level group position. */ +#define TC5_LCCBINTLVL0_bm (1<<2) /* Channel Low B Compare or Capture Interrupt Level bit 0 mask. */ +#define TC5_LCCBINTLVL0_bp 2 /* Channel Low B Compare or Capture Interrupt Level bit 0 position. */ +#define TC5_LCCBINTLVL1_bm (1<<3) /* Channel Low B Compare or Capture Interrupt Level bit 1 mask. */ +#define TC5_LCCBINTLVL1_bp 3 /* Channel Low B Compare or Capture Interrupt Level bit 1 position. */ + +#define TC5_LCCAINTLVL_gm 0x03 /* Channel Low A Compare or Capture Interrupt Level group mask. */ +#define TC5_LCCAINTLVL_gp 0 /* Channel Low A Compare or Capture Interrupt Level group position. */ +#define TC5_LCCAINTLVL0_bm (1<<0) /* Channel Low A Compare or Capture Interrupt Level bit 0 mask. */ +#define TC5_LCCAINTLVL0_bp 0 /* Channel Low A Compare or Capture Interrupt Level bit 0 position. */ +#define TC5_LCCAINTLVL1_bm (1<<1) /* Channel Low A Compare or Capture Interrupt Level bit 1 mask. */ +#define TC5_LCCAINTLVL1_bp 1 /* Channel Low A Compare or Capture Interrupt Level bit 1 position. */ + +/* TC5.CTRLGCLR bit masks and bit positions */ +#define TC5_STOP_bm 0x20 /* Timer/Counter Stop bit mask. */ +#define TC5_STOP_bp 5 /* Timer/Counter Stop bit position. */ + +#define TC5_CMD_gm 0x0C /* Command group mask. */ +#define TC5_CMD_gp 2 /* Command group position. */ +#define TC5_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC5_CMD0_bp 2 /* Command bit 0 position. */ +#define TC5_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC5_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC5_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TC5_LUPD_bp 1 /* Lock Update bit position. */ + +#define TC5_DIR_bm 0x01 /* Counter Direction bit mask. */ +#define TC5_DIR_bp 0 /* Counter Direction bit position. */ + +/* TC5.CTRLGSET bit masks and bit positions */ +/* TC5_STOP Predefined. */ +/* TC5_STOP Predefined. */ + +/* TC5_CMD Predefined. */ +/* TC5_CMD Predefined. */ + +/* TC5_LUPD Predefined. */ +/* TC5_LUPD Predefined. */ + +/* TC5_DIR Predefined. */ +/* TC5_DIR Predefined. */ + +/* TC5.CTRLHCLR bit masks and bit positions */ +#define TC5_CCBBV_bm 0x04 /* Channel B Compare or Capture Buffer Valid bit mask. */ +#define TC5_CCBBV_bp 2 /* Channel B Compare or Capture Buffer Valid bit position. */ + +#define TC5_CCABV_bm 0x02 /* Channel A Compare or Capture Buffer Valid bit mask. */ +#define TC5_CCABV_bp 1 /* Channel A Compare or Capture Buffer Valid bit position. */ + +#define TC5_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TC5_PERBV_bp 0 /* Period Buffer Valid bit position. */ + +#define TC5_LCCBBV_bm 0x04 /* Channel Low B Compare or Capture Buffer Valid bit mask. */ +#define TC5_LCCBBV_bp 2 /* Channel Low B Compare or Capture Buffer Valid bit position. */ + +#define TC5_LCCABV_bm 0x02 /* Channel Low A Compare or Capture Buffer Valid bit mask. */ +#define TC5_LCCABV_bp 1 /* Channel Low A Compare or Capture Buffer Valid bit position. */ + +#define TC5_LPERBV_bm 0x01 /* Period Low Buffer Valid bit mask. */ +#define TC5_LPERBV_bp 0 /* Period Low Buffer Valid bit position. */ + +/* TC5.CTRLHSET bit masks and bit positions */ +/* TC5_CCBBV Predefined. */ +/* TC5_CCBBV Predefined. */ + +/* TC5_CCABV Predefined. */ +/* TC5_CCABV Predefined. */ + +/* TC5_PERBV Predefined. */ +/* TC5_PERBV Predefined. */ + +/* TC5_LCCBBV Predefined. */ +/* TC5_LCCBBV Predefined. */ + +/* TC5_LCCABV Predefined. */ +/* TC5_LCCABV Predefined. */ + +/* TC5_LPERBV Predefined. */ +/* TC5_LPERBV Predefined. */ + +/* TC5.INTFLAGS bit masks and bit positions */ +#define TC5_CCBIF_bm 0x20 /* Channel B Compare or Capture Interrupt Flag bit mask. */ +#define TC5_CCBIF_bp 5 /* Channel B Compare or Capture Interrupt Flag bit position. */ + +#define TC5_CCAIF_bm 0x10 /* Channel A Compare or Capture Interrupt Flag bit mask. */ +#define TC5_CCAIF_bp 4 /* Channel A Compare or Capture Interrupt Flag bit position. */ + +#define TC5_TRGIF_bm 0x04 /* Trigger Restart Interrupt Flag bit mask. */ +#define TC5_TRGIF_bp 2 /* Trigger Restart Interrupt Flag bit position. */ + +#define TC5_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +#define TC5_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ + +#define TC5_OVFIF_bm 0x01 /* Overflow/Underflow Interrupt Flag bit mask. */ +#define TC5_OVFIF_bp 0 /* Overflow/Underflow Interrupt Flag bit position. */ + +#define TC5_LCCBIF_bm 0x20 /* Channel Low B Compare or Capture Interrupt Flag bit mask. */ +#define TC5_LCCBIF_bp 5 /* Channel Low B Compare or Capture Interrupt Flag bit position. */ + +#define TC5_LCCAIF_bm 0x10 /* Channel Low A Compare or Capture Interrupt Flag bit mask. */ +#define TC5_LCCAIF_bp 4 /* Channel Low A Compare or Capture Interrupt Flag bit position. */ + +/* FAULT - Fault Extension */ +/* FAULT.CTRLA bit masks and bit positions */ +#define FAULT_RAMP_gm 0xC0 /* Ramp Mode Selection group mask. */ +#define FAULT_RAMP_gp 6 /* Ramp Mode Selection group position. */ +#define FAULT_RAMP0_bm (1<<6) /* Ramp Mode Selection bit 0 mask. */ +#define FAULT_RAMP0_bp 6 /* Ramp Mode Selection bit 0 position. */ +#define FAULT_RAMP1_bm (1<<7) /* Ramp Mode Selection bit 1 mask. */ +#define FAULT_RAMP1_bp 7 /* Ramp Mode Selection bit 1 position. */ + +#define FAULT_FDDBD_bm 0x20 /* Fault on Debug Break Detection bit mask. */ +#define FAULT_FDDBD_bp 5 /* Fault on Debug Break Detection bit position. */ + +#define FAULT_PORTCTRL_bm 0x10 /* Port Control Mode bit mask. */ +#define FAULT_PORTCTRL_bp 4 /* Port Control Mode bit position. */ + +#define FAULT_FUSE_bm 0x08 /* Fuse State bit mask. */ +#define FAULT_FUSE_bp 3 /* Fuse State bit position. */ + +#define FAULT_FILTERE_bm 0x04 /* Fault E Digital Filter Selection bit mask. */ +#define FAULT_FILTERE_bp 2 /* Fault E Digital Filter Selection bit position. */ + +#define FAULT_SRCE_gm 0x03 /* Fault E Input selection group mask. */ +#define FAULT_SRCE_gp 0 /* Fault E Input selection group position. */ +#define FAULT_SRCE0_bm (1<<0) /* Fault E Input selection bit 0 mask. */ +#define FAULT_SRCE0_bp 0 /* Fault E Input selection bit 0 position. */ +#define FAULT_SRCE1_bm (1<<1) /* Fault E Input selection bit 1 mask. */ +#define FAULT_SRCE1_bp 1 /* Fault E Input selection bit 1 position. */ + +/* FAULT.CTRLB bit masks and bit positions */ +#define FAULT_SOFTA_bm 0x80 /* Fault A Software Mode bit mask. */ +#define FAULT_SOFTA_bp 7 /* Fault A Software Mode bit position. */ + +#define FAULT_HALTA_gm 0x60 /* Fault A Halt Action group mask. */ +#define FAULT_HALTA_gp 5 /* Fault A Halt Action group position. */ +#define FAULT_HALTA0_bm (1<<5) /* Fault A Halt Action bit 0 mask. */ +#define FAULT_HALTA0_bp 5 /* Fault A Halt Action bit 0 position. */ +#define FAULT_HALTA1_bm (1<<6) /* Fault A Halt Action bit 1 mask. */ +#define FAULT_HALTA1_bp 6 /* Fault A Halt Action bit 1 position. */ + +#define FAULT_RESTARTA_bm 0x10 /* Fault A Restart Action bit mask. */ +#define FAULT_RESTARTA_bp 4 /* Fault A Restart Action bit position. */ + +#define FAULT_KEEPA_bm 0x08 /* Fault A Keep Action bit mask. */ +#define FAULT_KEEPA_bp 3 /* Fault A Keep Action bit position. */ + +#define FAULT_SRCA_gm 0x03 /* Fault A Source Selection group mask. */ +#define FAULT_SRCA_gp 0 /* Fault A Source Selection group position. */ +#define FAULT_SRCA0_bm (1<<0) /* Fault A Source Selection bit 0 mask. */ +#define FAULT_SRCA0_bp 0 /* Fault A Source Selection bit 0 position. */ +#define FAULT_SRCA1_bm (1<<1) /* Fault A Source Selection bit 1 mask. */ +#define FAULT_SRCA1_bp 1 /* Fault A Source Selection bit 1 position. */ + +/* FAULT.CTRLC bit masks and bit positions */ +#define FAULT_CAPTA_bm 0x20 /* Fault A Capture bit mask. */ +#define FAULT_CAPTA_bp 5 /* Fault A Capture bit position. */ + +#define FAULT_FILTERA_bm 0x04 /* Fault A Digital Filter Selection bit mask. */ +#define FAULT_FILTERA_bp 2 /* Fault A Digital Filter Selection bit position. */ + +#define FAULT_BLANKA_bm 0x02 /* Fault A Blanking bit mask. */ +#define FAULT_BLANKA_bp 1 /* Fault A Blanking bit position. */ + +#define FAULT_QUALA_bm 0x01 /* Fault A Qualification bit mask. */ +#define FAULT_QUALA_bp 0 /* Fault A Qualification bit position. */ + +/* FAULT.CTRLD bit masks and bit positions */ +#define FAULT_SOFTB_bm 0x80 /* Fault B Software Mode bit mask. */ +#define FAULT_SOFTB_bp 7 /* Fault B Software Mode bit position. */ + +#define FAULT_HALTB_gm 0x60 /* Fault B Halt Action group mask. */ +#define FAULT_HALTB_gp 5 /* Fault B Halt Action group position. */ +#define FAULT_HALTB0_bm (1<<5) /* Fault B Halt Action bit 0 mask. */ +#define FAULT_HALTB0_bp 5 /* Fault B Halt Action bit 0 position. */ +#define FAULT_HALTB1_bm (1<<6) /* Fault B Halt Action bit 1 mask. */ +#define FAULT_HALTB1_bp 6 /* Fault B Halt Action bit 1 position. */ + +#define FAULT_RESTARTB_bm 0x10 /* Fault B Restart Action bit mask. */ +#define FAULT_RESTARTB_bp 4 /* Fault B Restart Action bit position. */ + +#define FAULT_KEEPB_bm 0x08 /* Fault B Keep Action bit mask. */ +#define FAULT_KEEPB_bp 3 /* Fault B Keep Action bit position. */ + +#define FAULT_SRCB_gm 0x03 /* Fault B Source Selection group mask. */ +#define FAULT_SRCB_gp 0 /* Fault B Source Selection group position. */ +#define FAULT_SRCB0_bm (1<<0) /* Fault B Source Selection bit 0 mask. */ +#define FAULT_SRCB0_bp 0 /* Fault B Source Selection bit 0 position. */ +#define FAULT_SRCB1_bm (1<<1) /* Fault B Source Selection bit 1 mask. */ +#define FAULT_SRCB1_bp 1 /* Fault B Source Selection bit 1 position. */ + +/* FAULT.CTRLE bit masks and bit positions */ +#define FAULT_CAPTB_bm 0x20 /* Fault B Capture bit mask. */ +#define FAULT_CAPTB_bp 5 /* Fault B Capture bit position. */ + +#define FAULT_FILTERB_bm 0x04 /* Fault B Digital Filter Selection bit mask. */ +#define FAULT_FILTERB_bp 2 /* Fault B Digital Filter Selection bit position. */ + +#define FAULT_BLANKB_bm 0x02 /* Fault B Blanking bit mask. */ +#define FAULT_BLANKB_bp 1 /* Fault B Blanking bit position. */ + +#define FAULT_QUALB_bm 0x01 /* Fault B Qualification bit mask. */ +#define FAULT_QUALB_bp 0 /* Fault B Qualification bit position. */ + +/* FAULT.STATUS bit masks and bit positions */ +#define FAULT_STATEB_bm 0x80 /* Fault B State bit mask. */ +#define FAULT_STATEB_bp 7 /* Fault B State bit position. */ + +#define FAULT_STATEA_bm 0x40 /* Fault A State bit mask. */ +#define FAULT_STATEA_bp 6 /* Fault A State bit position. */ + +#define FAULT_STATEE_bm 0x20 /* Fault E State bit mask. */ +#define FAULT_STATEE_bp 5 /* Fault E State bit position. */ + +#define FAULT_IDX_bm 0x08 /* Channel Index Flag bit mask. */ +#define FAULT_IDX_bp 3 /* Channel Index Flag bit position. */ + +#define FAULT_FAULTBIN_bm 0x04 /* Fault B Flag bit mask. */ +#define FAULT_FAULTBIN_bp 2 /* Fault B Flag bit position. */ + +#define FAULT_FAULTAIN_bm 0x02 /* Fault A Flag bit mask. */ +#define FAULT_FAULTAIN_bp 1 /* Fault A Flag bit position. */ + +#define FAULT_FAULTEIN_bm 0x01 /* Fault E Flag bit mask. */ +#define FAULT_FAULTEIN_bp 0 /* Fault E Flag bit position. */ + +/* FAULT.CTRLGCLR bit masks and bit positions */ +#define FAULT_HALTBCLR_bm 0x80 /* State B Clear bit mask. */ +#define FAULT_HALTBCLR_bp 7 /* State B Clear bit position. */ + +#define FAULT_HALTACLR_bm 0x40 /* State A Clear bit mask. */ +#define FAULT_HALTACLR_bp 6 /* State A Clear bit position. */ + +#define FAULT_STATEECLR_bm 0x20 /* State E Clear bit mask. */ +#define FAULT_STATEECLR_bp 5 /* State E Clear bit position. */ + +#define FAULT_FAULTB_bm 0x04 /* Fault B Flag bit mask. */ +#define FAULT_FAULTB_bp 2 /* Fault B Flag bit position. */ + +#define FAULT_FAULTA_bm 0x02 /* Fault A Flag bit mask. */ +#define FAULT_FAULTA_bp 1 /* Fault A Flag bit position. */ + +#define FAULT_FAULTE_bm 0x01 /* Fault E Flag bit mask. */ +#define FAULT_FAULTE_bp 0 /* Fault E Flag bit position. */ + +/* FAULT.CTRLGSET bit masks and bit positions */ +#define FAULT_FAULTBSW_bm 0x80 /* Software Fault B bit mask. */ +#define FAULT_FAULTBSW_bp 7 /* Software Fault B bit position. */ + +#define FAULT_FAULTASW_bm 0x40 /* Software Fault A bit mask. */ +#define FAULT_FAULTASW_bp 6 /* Software Fault A bit position. */ + +#define FAULT_FAULTESW_bm 0x20 /* Software Fault E bit mask. */ +#define FAULT_FAULTESW_bp 5 /* Software Fault E bit position. */ + +#define FAULT_IDXCMD_gm 0x18 /* Channel index Command group mask. */ +#define FAULT_IDXCMD_gp 3 /* Channel index Command group position. */ +#define FAULT_IDXCMD0_bm (1<<3) /* Channel index Command bit 0 mask. */ +#define FAULT_IDXCMD0_bp 3 /* Channel index Command bit 0 position. */ +#define FAULT_IDXCMD1_bm (1<<4) /* Channel index Command bit 1 mask. */ +#define FAULT_IDXCMD1_bp 4 /* Channel index Command bit 1 position. */ + +/* WEX - Waveform Extension */ +/* WEX.CTRL bit masks and bit positions */ +#define WEX_UPSEL_bm 0x80 /* Update Source Selection bit mask. */ +#define WEX_UPSEL_bp 7 /* Update Source Selection bit position. */ + +#define WEX_OTMX_gm 0x70 /* Output Matrix group mask. */ +#define WEX_OTMX_gp 4 /* Output Matrix group position. */ +#define WEX_OTMX0_bm (1<<4) /* Output Matrix bit 0 mask. */ +#define WEX_OTMX0_bp 4 /* Output Matrix bit 0 position. */ +#define WEX_OTMX1_bm (1<<5) /* Output Matrix bit 1 mask. */ +#define WEX_OTMX1_bp 5 /* Output Matrix bit 1 position. */ +#define WEX_OTMX2_bm (1<<6) /* Output Matrix bit 2 mask. */ +#define WEX_OTMX2_bp 6 /* Output Matrix bit 2 position. */ + +#define WEX_DTI3EN_bm 0x08 /* Dead-Time Insertion Generator 3 Enable bit mask. */ +#define WEX_DTI3EN_bp 3 /* Dead-Time Insertion Generator 3 Enable bit position. */ + +#define WEX_DTI2EN_bm 0x04 /* Dead-Time Insertion Generator 2 Enable bit mask. */ +#define WEX_DTI2EN_bp 2 /* Dead-Time Insertion Generator 2 Enable bit position. */ + +#define WEX_DTI1EN_bm 0x02 /* Dead-Time Insertion Generator 1 Enable bit mask. */ +#define WEX_DTI1EN_bp 1 /* Dead-Time Insertion Generator 1 Enable bit position. */ + +#define WEX_DTI0EN_bm 0x01 /* Dead-Time Insertion Generator 0 Enable bit mask. */ +#define WEX_DTI0EN_bp 0 /* Dead-Time Insertion Generator 0 Enable bit position. */ + +/* WEX.STATUSCLR bit masks and bit positions */ +#define WEX_SWAPBUF_bm 0x04 /* Swap Buffer Valid bit mask. */ +#define WEX_SWAPBUF_bp 2 /* Swap Buffer Valid bit position. */ + +#define WEX_PGVBUFV_bm 0x02 /* Pattern Generator Value Buffer Valid bit mask. */ +#define WEX_PGVBUFV_bp 1 /* Pattern Generator Value Buffer Valid bit position. */ + +#define WEX_PGOBUFV_bm 0x01 /* Pattern Generator Overwrite Buffer Valid bit mask. */ +#define WEX_PGOBUFV_bp 0 /* Pattern Generator Overwrite Buffer Valid bit position. */ + +/* WEX.STATUSSET bit masks and bit positions */ +/* WEX_SWAPBUF Predefined. */ +/* WEX_SWAPBUF Predefined. */ + +/* WEX_PGVBUFV Predefined. */ +/* WEX_PGVBUFV Predefined. */ + +/* WEX_PGOBUFV Predefined. */ +/* WEX_PGOBUFV Predefined. */ + +/* WEX.SWAP bit masks and bit positions */ +#define WEX_SWAP3_bm 0x08 /* Swap DTI output pair 3 bit mask. */ +#define WEX_SWAP3_bp 3 /* Swap DTI output pair 3 bit position. */ + +#define WEX_SWAP2_bm 0x04 /* Swap DTI output pair 2 bit mask. */ +#define WEX_SWAP2_bp 2 /* Swap DTI output pair 2 bit position. */ + +#define WEX_SWAP1_bm 0x02 /* Swap DTI output pair 1 bit mask. */ +#define WEX_SWAP1_bp 1 /* Swap DTI output pair 1 bit position. */ + +#define WEX_SWAP0_bm 0x01 /* Swap DTI output pair 0 bit mask. */ +#define WEX_SWAP0_bp 0 /* Swap DTI output pair 0 bit position. */ + +/* WEX.SWAPBUF bit masks and bit positions */ +#define WEX_SWAP3BUF_bm 0x08 /* Swap DTI output pair 3 bit mask. */ +#define WEX_SWAP3BUF_bp 3 /* Swap DTI output pair 3 bit position. */ + +#define WEX_SWAP2BUF_bm 0x04 /* Swap DTI output pair 2 bit mask. */ +#define WEX_SWAP2BUF_bp 2 /* Swap DTI output pair 2 bit position. */ + +#define WEX_SWAP1BUF_bm 0x02 /* Swap DTI output pair 1 bit mask. */ +#define WEX_SWAP1BUF_bp 1 /* Swap DTI output pair 1 bit position. */ + +#define WEX_SWAP0BUF_bm 0x01 /* Swap DTI output pair 0 bit mask. */ +#define WEX_SWAP0BUF_bp 0 /* Swap DTI output pair 0 bit position. */ + +/* HIRES - High-Resolution Extension */ +/* HIRES.CTRLA bit masks and bit positions */ +#define HIRES_HRPLUS_gm 0x0C /* High Resolution Plus group mask. */ +#define HIRES_HRPLUS_gp 2 /* High Resolution Plus group position. */ +#define HIRES_HRPLUS0_bm (1<<2) /* High Resolution Plus bit 0 mask. */ +#define HIRES_HRPLUS0_bp 2 /* High Resolution Plus bit 0 position. */ +#define HIRES_HRPLUS1_bm (1<<3) /* High Resolution Plus bit 1 mask. */ +#define HIRES_HRPLUS1_bp 3 /* High Resolution Plus bit 1 position. */ + +#define HIRES_HREN_gm 0x03 /* High Resolution Mode group mask. */ +#define HIRES_HREN_gp 0 /* High Resolution Mode group position. */ +#define HIRES_HREN0_bm (1<<0) /* High Resolution Mode bit 0 mask. */ +#define HIRES_HREN0_bp 0 /* High Resolution Mode bit 0 position. */ +#define HIRES_HREN1_bm (1<<1) /* High Resolution Mode bit 1 mask. */ +#define HIRES_HREN1_bp 1 /* High Resolution Mode bit 1 position. */ + +/* USART - Universal Asynchronous Receiver-Transmitter */ +/* USART.STATUS bit masks and bit positions */ +#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ +#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ + +#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ + +#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ + +#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ +#define USART_FERR_bp 4 /* Frame Error bit position. */ + +#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ +#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ + +#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ +#define USART_PERR_bp 2 /* Parity Error bit position. */ + +#define USART_RXSIF_bm 0x02 /* Receive Start Bit Interrupt Flag bit mask. */ +#define USART_RXSIF_bp 1 /* Receive Start Bit Interrupt Flag bit position. */ + +#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ +#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ + +#define USART_DRIF_bm 0x01 /* Data Reception Flag bit mask. */ +#define USART_DRIF_bp 0 /* Data Reception Flag bit position. */ + +/* USART.CTRLA bit masks and bit positions */ +#define USART_RXSIE_bm 0x80 /* Receive Start Interrupt Enable bit mask. */ +#define USART_RXSIE_bp 7 /* Receive Start Interrupt Enable bit position. */ + +#define USART_DRIE_bm 0x40 /* Data Reception Interrupt Enable bit mask. */ +#define USART_DRIE_bp 6 /* Data Reception Interrupt Enable bit position. */ + +#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ +#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ +#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ +#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ +#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ +#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ + +#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ +#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ +#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ +#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ +#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ +#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ + +#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ +#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ +#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ +#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ +#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ +#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ + +/* USART.CTRLB bit masks and bit positions */ +#define USART_ONEWIRE_bm 0x80 /* One Wire Mode bit mask. */ +#define USART_ONEWIRE_bp 7 /* One Wire Mode bit position. */ + +#define USART_SFDEN_bm 0x40 /* Start Frame Detection Enable bit mask. */ +#define USART_SFDEN_bp 6 /* Start Frame Detection Enable bit position. */ + +#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ +#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ + +#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ +#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ + +#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ +#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ + +#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ +#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ + +#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ +#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ + +/* USART.CTRLC bit masks and bit positions */ +#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +#define USART_CMODE_gp 6 /* Communication Mode group position. */ +#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ + +#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +#define USART_PMODE_gp 4 /* Parity Mode group position. */ +#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ + +#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ + +#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +#define USART_CHSIZE_gp 0 /* Character Size group position. */ +#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ + +/* USART.CTRLD bit masks and bit positions */ +#define USART_DECTYPE_gm 0x30 /* Receive Interrupt Level group mask. */ +#define USART_DECTYPE_gp 4 /* Receive Interrupt Level group position. */ +#define USART_DECTYPE0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ +#define USART_DECTYPE0_bp 4 /* Receive Interrupt Level bit 0 position. */ +#define USART_DECTYPE1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ +#define USART_DECTYPE1_bp 5 /* Receive Interrupt Level bit 1 position. */ + +#define USART_LUTACT_gm 0x0C /* Transmit Interrupt Level group mask. */ +#define USART_LUTACT_gp 2 /* Transmit Interrupt Level group position. */ +#define USART_LUTACT0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ +#define USART_LUTACT0_bp 2 /* Transmit Interrupt Level bit 0 position. */ +#define USART_LUTACT1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ +#define USART_LUTACT1_bp 3 /* Transmit Interrupt Level bit 1 position. */ + +#define USART_PECACT_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ +#define USART_PECACT_gp 0 /* Data Register Empty Interrupt Level group position. */ +#define USART_PECACT0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ +#define USART_PECACT0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ +#define USART_PECACT1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ +#define USART_PECACT1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ + +/* USART.BAUDCTRLA bit masks and bit positions */ +#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ +#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ +#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ +#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ +#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ +#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ +#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ +#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ +#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ +#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ +#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ +#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ +#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ +#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ +#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ +#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ +#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ +#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ + +/* USART.BAUDCTRLB bit masks and bit positions */ +#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ +#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ +#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ +#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ +#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ +#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ +#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ +#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ +#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ +#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ + +/* USART_BSEL Predefined. */ +/* USART_BSEL Predefined. */ + +/* SPI - Serial Peripheral Interface */ +/* SPI.CTRL bit masks and bit positions */ +#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ +#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ + +#define SPI_ENABLE_bm 0x40 /* Enable SPI Module bit mask. */ +#define SPI_ENABLE_bp 6 /* Enable SPI Module bit position. */ + +#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ +#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ + +#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ +#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ + +#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ +#define SPI_MODE_gp 2 /* SPI Mode group position. */ +#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ +#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ +#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ +#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ + +#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ +#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ +#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ +#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ +#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ +#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ + +/* SPI.INTCTRL bit masks and bit positions */ +#define SPI_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable (In Buffer Modes Only). bit mask. */ +#define SPI_RXCIE_bp 7 /* Receive Complete Interrupt Enable (In Buffer Modes Only). bit position. */ + +#define SPI_TXCIE_bm 0x40 /* Transmit Complete Interrupt Enable (In Buffer Modes Only). bit mask. */ +#define SPI_TXCIE_bp 6 /* Transmit Complete Interrupt Enable (In Buffer Modes Only). bit position. */ + +#define SPI_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable (In Buffer Modes Only). bit mask. */ +#define SPI_DREIE_bp 5 /* Data Register Empty Interrupt Enable (In Buffer Modes Only). bit position. */ + +#define SPI_SSIE_bm 0x10 /* Slave Select Trigger Interrupt Enable (In Buffer Modes Only). bit mask. */ +#define SPI_SSIE_bp 4 /* Slave Select Trigger Interrupt Enable (In Buffer Modes Only). bit position. */ + +#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ +#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ +#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ +#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ +#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ +#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ + +/* SPI.STATUS bit masks and bit positions */ +#define SPI_IF_bm 0x80 /* Interrupt Flag (In Standard Mode Only). bit mask. */ +#define SPI_IF_bp 7 /* Interrupt Flag (In Standard Mode Only). bit position. */ + +#define SPI_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag (In Buffer Modes Only). bit mask. */ +#define SPI_RXCIF_bp 7 /* Receive Complete Interrupt Flag (In Buffer Modes Only). bit position. */ + +#define SPI_WRCOL_bm 0x40 /* Write Collision Flag (In Standard Mode Only). bit mask. */ +#define SPI_WRCOL_bp 6 /* Write Collision Flag (In Standard Mode Only). bit position. */ + +#define SPI_TXCIF_bm 0x40 /* Transmit Complete Interrupt Flag (In Buffer Modes Only). bit mask. */ +#define SPI_TXCIF_bp 6 /* Transmit Complete Interrupt Flag (In Buffer Modes Only). bit position. */ + +#define SPI_DREIF_bm 0x20 /* Data Register Empty Interrupt Flag (In Buffer Modes Only). bit mask. */ +#define SPI_DREIF_bp 5 /* Data Register Empty Interrupt Flag (In Buffer Modes Only). bit position. */ + +#define SPI_SSIF_bm 0x10 /* Slave Select Trigger Interrupt Flag (In Buffer Modes Only). bit mask. */ +#define SPI_SSIF_bp 4 /* Slave Select Trigger Interrupt Flag (In Buffer Modes Only). bit position. */ + +#define SPI_BUFOVF_bm 0x01 /* Buffer Overflow (In Buffer Modes Only). bit mask. */ +#define SPI_BUFOVF_bp 0 /* Buffer Overflow (In Buffer Modes Only). bit position. */ + +/* SPI.CTRLB bit masks and bit positions */ +#define SPI_BUFMODE_gm 0xC0 /* Buffer Modes group mask. */ +#define SPI_BUFMODE_gp 6 /* Buffer Modes group position. */ +#define SPI_BUFMODE0_bm (1<<6) /* Buffer Modes bit 0 mask. */ +#define SPI_BUFMODE0_bp 6 /* Buffer Modes bit 0 position. */ +#define SPI_BUFMODE1_bm (1<<7) /* Buffer Modes bit 1 mask. */ +#define SPI_BUFMODE1_bp 7 /* Buffer Modes bit 1 position. */ + +#define SPI_SSD_bm 0x04 /* Slave Select Disable bit mask. */ +#define SPI_SSD_bp 2 /* Slave Select Disable bit position. */ + +/* IRCOM - IR Communication Module */ +/* IRCOM.CTRL bit masks and bit positions */ +#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ +#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ +#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ +#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ +#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ +#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ +#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ +#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ +#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ +#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ + +/* FUSE - Fuses and Lockbits */ +/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ +#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ + +#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ +#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ +#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ + +/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ +#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ +#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ + +#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ +#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ +#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ + +/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ +#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ +#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ + +#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ +#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ +#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ +#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ +#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ +#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ + +/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ +#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ +#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ + +#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ +#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ +#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ +#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ +#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ +#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ + +#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ +#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ + +/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ +#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ +#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ +#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ +#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ +#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ +#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ + +#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ +#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ + +#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ +#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ +#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ +#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ +#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ +#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ +#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ +#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ + +/* NVM_FUSES.FUSEBYTE6 bit masks and bit positions */ +#define NVM_FUSES_FDACT5_bm 0x80 /* Fault Dectection Action on TC5 bit mask. */ +#define NVM_FUSES_FDACT5_bp 7 /* Fault Dectection Action on TC5 bit position. */ + +#define NVM_FUSES_FDACT4_bm 0x40 /* Fault Dectection Action on TC4 bit mask. */ +#define NVM_FUSES_FDACT4_bp 6 /* Fault Dectection Action on TC4 bit position. */ + +#define NVM_FUSES_VALUE_gm 0x3F /* Port Pin Value group mask. */ +#define NVM_FUSES_VALUE_gp 0 /* Port Pin Value group position. */ +#define NVM_FUSES_VALUE0_bm (1<<0) /* Port Pin Value bit 0 mask. */ +#define NVM_FUSES_VALUE0_bp 0 /* Port Pin Value bit 0 position. */ +#define NVM_FUSES_VALUE1_bm (1<<1) /* Port Pin Value bit 1 mask. */ +#define NVM_FUSES_VALUE1_bp 1 /* Port Pin Value bit 1 position. */ +#define NVM_FUSES_VALUE2_bm (1<<2) /* Port Pin Value bit 2 mask. */ +#define NVM_FUSES_VALUE2_bp 2 /* Port Pin Value bit 2 position. */ +#define NVM_FUSES_VALUE3_bm (1<<3) /* Port Pin Value bit 3 mask. */ +#define NVM_FUSES_VALUE3_bp 3 /* Port Pin Value bit 3 position. */ +#define NVM_FUSES_VALUE4_bm (1<<4) /* Port Pin Value bit 4 mask. */ +#define NVM_FUSES_VALUE4_bp 4 /* Port Pin Value bit 4 position. */ +#define NVM_FUSES_VALUE5_bm (1<<5) /* Port Pin Value bit 5 mask. */ +#define NVM_FUSES_VALUE5_bp 5 /* Port Pin Value bit 5 position. */ + + + +// Generic Port Pins + +#define PIN0_bm 0x01 +#define PIN0_bp 0 +#define PIN1_bm 0x02 +#define PIN1_bp 1 +#define PIN2_bm 0x04 +#define PIN2_bp 2 +#define PIN3_bm 0x08 +#define PIN3_bp 3 +#define PIN4_bm 0x10 +#define PIN4_bp 4 +#define PIN5_bm 0x20 +#define PIN5_bp 5 +#define PIN6_bm 0x40 +#define PIN6_bp 6 +#define PIN7_bm 0x80 +#define PIN7_bp 7 + +/* ========== Interrupt Vector Definitions ========== */ +/* Vector 0 is the reset vector */ + +/* OSC interrupt vectors */ +#define OSC_OSCF_vect_num 1 +#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ + +/* PORTR interrupt vectors */ +#define PORTR_INT_vect_num 2 +#define PORTR_INT_vect _VECTOR(2) /* External Interrupt */ + +/* EDMA interrupt vectors */ +#define EDMA_CH0_vect_num 3 +#define EDMA_CH0_vect _VECTOR(3) /* EDMA Channel 0 Interrupt */ +#define EDMA_CH1_vect_num 4 +#define EDMA_CH1_vect _VECTOR(4) /* EDMA Channel 1 Interrupt */ +#define EDMA_CH2_vect_num 5 +#define EDMA_CH2_vect _VECTOR(5) /* EDMA Channel 2 Interrupt */ +#define EDMA_CH3_vect_num 6 +#define EDMA_CH3_vect _VECTOR(6) /* EDMA Channel 3 Interrupt */ + +/* RTC interrupt vectors */ +#define RTC_OVF_vect_num 7 +#define RTC_OVF_vect _VECTOR(7) /* Overflow Interrupt */ +#define RTC_COMP_vect_num 8 +#define RTC_COMP_vect _VECTOR(8) /* Compare Interrupt */ + +/* PORTC interrupt vectors */ +#define PORTC_INT_vect_num 9 +#define PORTC_INT_vect _VECTOR(9) /* External Interrupt */ + +/* TWIC interrupt vectors */ +#define TWIC_TWIS_vect_num 10 +#define TWIC_TWIS_vect _VECTOR(10) /* TWI Slave Interrupt */ +#define TWIC_TWIM_vect_num 11 +#define TWIC_TWIM_vect _VECTOR(11) /* TWI Master Interrupt */ + +/* TCC4 interrupt vectors */ +#define TCC4_OVF_vect_num 12 +#define TCC4_OVF_vect _VECTOR(12) /* Overflow Interrupt */ +#define TCC4_ERR_vect_num 13 +#define TCC4_ERR_vect _VECTOR(13) /* Error Interrupt */ +#define TCC4_CCA_vect_num 14 +#define TCC4_CCA_vect _VECTOR(14) /* Channel A Compare or Capture Interrupt */ +#define TCC4_CCB_vect_num 15 +#define TCC4_CCB_vect _VECTOR(15) /* Channel B Compare or Capture Interrupt */ +#define TCC4_CCC_vect_num 16 +#define TCC4_CCC_vect _VECTOR(16) /* Channel C Compare or Capture Interrupt */ +#define TCC4_CCD_vect_num 17 +#define TCC4_CCD_vect _VECTOR(17) /* Channel D Compare or Capture Interrupt */ + +/* TCC5 interrupt vectors */ +#define TCC5_OVF_vect_num 18 +#define TCC5_OVF_vect _VECTOR(18) /* Overflow Interrupt */ +#define TCC5_ERR_vect_num 19 +#define TCC5_ERR_vect _VECTOR(19) /* Error Interrupt */ +#define TCC5_CCA_vect_num 20 +#define TCC5_CCA_vect _VECTOR(20) /* Channel A Compare or Capture Interrupt */ +#define TCC5_CCB_vect_num 21 +#define TCC5_CCB_vect _VECTOR(21) /* Channel B Compare or Capture Interrupt */ + +/* SPIC interrupt vectors */ +#define SPIC_INT_vect_num 22 +#define SPIC_INT_vect _VECTOR(22) /* SPI Interrupt */ + +/* USARTC0 interrupt vectors */ +#define USARTC0_RXC_vect_num 23 +#define USARTC0_RXC_vect _VECTOR(23) /* Reception Complete Interrupt */ +#define USARTC0_DRE_vect_num 24 +#define USARTC0_DRE_vect _VECTOR(24) /* Data Register Empty Interrupt */ +#define USARTC0_TXC_vect_num 25 +#define USARTC0_TXC_vect _VECTOR(25) /* Transmission Complete Interrupt */ + +/* NVM interrupt vectors */ +#define NVM_EE_vect_num 26 +#define NVM_EE_vect _VECTOR(26) /* EE Interrupt */ +#define NVM_SPM_vect_num 27 +#define NVM_SPM_vect _VECTOR(27) /* SPM Interrupt */ + +/* XCL interrupt vectors */ +#define XCL_UNF_vect_num 28 +#define XCL_UNF_vect _VECTOR(28) /* Timer/Counter Underflow Interrupt */ +#define XCL_CC_vect_num 29 +#define XCL_CC_vect _VECTOR(29) /* Timer/Counter Compare or Capture Interrupt */ + +/* PORTA interrupt vectors */ +#define PORTA_INT_vect_num 30 +#define PORTA_INT_vect _VECTOR(30) /* External Interrupt */ + +/* ACA interrupt vectors */ +#define ACA_AC0_vect_num 31 +#define ACA_AC0_vect _VECTOR(31) /* AC0 Interrupt */ +#define ACA_AC1_vect_num 32 +#define ACA_AC1_vect _VECTOR(32) /* AC1 Interrupt */ +#define ACA_ACW_vect_num 33 +#define ACA_ACW_vect _VECTOR(33) /* ACW Window Mode Interrupt */ + +/* ADCA interrupt vectors */ +#define ADCA_CH0_vect_num 34 +#define ADCA_CH0_vect _VECTOR(34) /* ADC Channel Interrupt */ + +/* PORTD interrupt vectors */ +#define PORTD_INT_vect_num 35 +#define PORTD_INT_vect _VECTOR(35) /* External Interrupt */ + +/* TCD5 interrupt vectors */ +#define TCD5_OVF_vect_num 36 +#define TCD5_OVF_vect _VECTOR(36) /* Overflow Interrupt */ +#define TCD5_ERR_vect_num 37 +#define TCD5_ERR_vect _VECTOR(37) /* Error Interrupt */ +#define TCD5_CCA_vect_num 38 +#define TCD5_CCA_vect _VECTOR(38) /* Channel A Compare or Capture Interrupt */ +#define TCD5_CCB_vect_num 39 +#define TCD5_CCB_vect _VECTOR(39) /* Channel B Compare or Capture Interrupt */ + +/* USARTD0 interrupt vectors */ +#define USARTD0_RXC_vect_num 40 +#define USARTD0_RXC_vect _VECTOR(40) /* Reception Complete Interrupt */ +#define USARTD0_DRE_vect_num 41 +#define USARTD0_DRE_vect _VECTOR(41) /* Data Register Empty Interrupt */ +#define USARTD0_TXC_vect_num 42 +#define USARTD0_TXC_vect _VECTOR(42) /* Transmission Complete Interrupt */ + +#define _VECTOR_SIZE 4 /* Size of individual vector. */ +#define _VECTORS_SIZE (43 * _VECTOR_SIZE) + + +/* ========== Constants ========== */ + +#define PROGMEM_START (0x0000) +#define PROGMEM_SIZE (36864) +#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) + +#define APP_SECTION_START (0x0000) +#define APP_SECTION_SIZE (32768) +#define APP_SECTION_PAGE_SIZE (128) +#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) + +#define APPTABLE_SECTION_START (0x7000) +#define APPTABLE_SECTION_SIZE (4096) +#define APPTABLE_SECTION_PAGE_SIZE (128) +#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) + +#define BOOT_SECTION_START (0x8000) +#define BOOT_SECTION_SIZE (4096) +#define BOOT_SECTION_PAGE_SIZE (128) +#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) + +#define DATAMEM_START (0x0000) +#define DATAMEM_SIZE (12288) +#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) + +#define IO_START (0x0000) +#define IO_SIZE (4096) +#define IO_PAGE_SIZE (0) +#define IO_END (IO_START + IO_SIZE - 1) + +#define MAPPED_EEPROM_START (0x1000) +#define MAPPED_EEPROM_SIZE (1024) +#define MAPPED_EEPROM_PAGE_SIZE (0) +#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) + +#define INTERNAL_SRAM_START (0x2000) +#define INTERNAL_SRAM_SIZE (4096) +#define INTERNAL_SRAM_PAGE_SIZE (0) +#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) + +#define EEPROM_START (0x0000) +#define EEPROM_SIZE (1024) +#define EEPROM_PAGE_SIZE (32) +#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) + +#define SIGNATURES_START (0x0000) +#define SIGNATURES_SIZE (3) +#define SIGNATURES_PAGE_SIZE (0) +#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) + +#define FUSES_START (0x0000) +#define FUSES_SIZE (7) +#define FUSES_PAGE_SIZE (0) +#define FUSES_END (FUSES_START + FUSES_SIZE - 1) + +#define LOCKBITS_START (0x0000) +#define LOCKBITS_SIZE (1) +#define LOCKBITS_PAGE_SIZE (0) +#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) + +#define USER_SIGNATURES_START (0x0000) +#define USER_SIGNATURES_SIZE (128) +#define USER_SIGNATURES_PAGE_SIZE (128) +#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) + +#define PROD_SIGNATURES_START (0x0000) +#define PROD_SIGNATURES_SIZE (54) +#define PROD_SIGNATURES_PAGE_SIZE (128) +#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) + +#define FLASHSTART PROGMEM_START +#define FLASHEND PROGMEM_END +#define SPM_PAGESIZE 128 +#define RAMSTART INTERNAL_SRAM_START +#define RAMSIZE INTERNAL_SRAM_SIZE +#define RAMEND INTERNAL_SRAM_END +#define E2END EEPROM_END +#define E2PAGESIZE EEPROM_PAGE_SIZE + + +/* ========== Fuses ========== */ +#define FUSE_MEMORY_SIZE 7 + +/* Fuse Byte 0 Reserved */ + +/* Fuse Byte 1 */ +#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ +#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ +#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ +#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ +#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +#define FUSE1_DEFAULT (0xFF) + +/* Fuse Byte 2 */ +#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ +#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ +#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ +#define FUSE2_DEFAULT (0xFF) + +/* Fuse Byte 3 Reserved */ + +/* Fuse Byte 4 */ +#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ +#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ +#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ +#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ +#define FUSE4_DEFAULT (0xFF) + +/* Fuse Byte 5 */ +#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ +#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ +#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ +#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ +#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ +#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ +#define FUSE5_DEFAULT (0xFF) + +/* Fuse Byte 6 */ +#define FUSE_VALUE0 (unsigned char)~_BV(0) /* Port Pin Value Bit 0 */ +#define FUSE_VALUE1 (unsigned char)~_BV(1) /* Port Pin Value Bit 1 */ +#define FUSE_VALUE2 (unsigned char)~_BV(2) /* Port Pin Value Bit 2 */ +#define FUSE_VALUE3 (unsigned char)~_BV(3) /* Port Pin Value Bit 3 */ +#define FUSE_VALUE4 (unsigned char)~_BV(4) /* Port Pin Value Bit 4 */ +#define FUSE_VALUE5 (unsigned char)~_BV(5) /* Port Pin Value Bit 5 */ +#define FUSE_FDACT4 (unsigned char)~_BV(6) /* Fault Dectection Action on TC4 */ +#define FUSE_FDACT5 (unsigned char)~_BV(7) /* Fault Dectection Action on TC5 */ +#define FUSE6_DEFAULT (0xFF) + +/* ========== Lock Bits ========== */ +#define __LOCK_BITS_EXIST +#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST +#define __BOOT_LOCK_APPLICATION_BITS_EXIST +#define __BOOT_LOCK_BOOT_BITS_EXIST + +/* ========== Signature ========== */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x95 +#define SIGNATURE_2 0x4C + +/* ========== Power Reduction Condition Definitions ========== */ + +/* PR.PRGEN */ +#define __AVR_HAVE_PRGEN (PR_XCL_bm|PR_RTC_bm|PR_EVSYS_bm|PR_EDMA_bm) +#define __AVR_HAVE_PRGEN_XCL +#define __AVR_HAVE_PRGEN_RTC +#define __AVR_HAVE_PRGEN_EVSYS +#define __AVR_HAVE_PRGEN_EDMA + +/* PR.PRPA */ +#define __AVR_HAVE_PRPA (PR_DAC_bm|PR_ADC_bm|PR_AC_bm) +#define __AVR_HAVE_PRPA_DAC +#define __AVR_HAVE_PRPA_ADC +#define __AVR_HAVE_PRPA_AC + +/* PR.PRPC */ +#define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC5_bm|PR_TC4_bm) +#define __AVR_HAVE_PRPC_TWI +#define __AVR_HAVE_PRPC_USART0 +#define __AVR_HAVE_PRPC_SPI +#define __AVR_HAVE_PRPC_HIRES +#define __AVR_HAVE_PRPC_TC5 +#define __AVR_HAVE_PRPC_TC4 + +/* PR.PRPD */ +#define __AVR_HAVE_PRPD (PR_USART0_bm|PR_TC5_bm) +#define __AVR_HAVE_PRPD_USART0 +#define __AVR_HAVE_PRPD_TC5 + + +#endif /* #ifdef _AVR_ATXMEGA32E5_H_INCLUDED */ diff --git a/include/avr/iox384c3.h b/include/avr/iox384c3.h index e06ec9d2..36ac0838 100644 --- a/include/avr/iox384c3.h +++ b/include/avr/iox384c3.h @@ -6849,4 +6849,3 @@ IO Module Instances. Mapped to memory. #endif /* #ifdef _AVR_ATXMEGA384C3_H_INCLUDED */ - diff --git a/include/avr/iox384d3.h b/include/avr/iox384d3.h index 503a27ff..b8e3c950 100644 --- a/include/avr/iox384d3.h +++ b/include/avr/iox384d3.h @@ -5833,4 +5833,3 @@ IO Module Instances. Mapped to memory. #endif /* #ifdef _AVR_ATXMEGA384D3_H_INCLUDED */ - diff --git a/include/avr/iox64a1.h b/include/avr/iox64a1.h index 782bb329..b66b07e8 100644 --- a/include/avr/iox64a1.h +++ b/include/avr/iox64a1.h @@ -42,7 +42,7 @@ # define _AVR_IOXXX_H_ "iox64a1.h" #else # error "Attempt to include more than one file." -#endif +#endif #ifndef _AVR_ATxmega64A1_H_ @@ -6659,21 +6659,21 @@ IO Module Instances. Mapped to memory. // Generic Port Pins -#define PIN0_bm 0x01 +#define PIN0_bm 0x01 #define PIN0_bp 0 #define PIN1_bm 0x02 #define PIN1_bp 1 -#define PIN2_bm 0x04 +#define PIN2_bm 0x04 #define PIN2_bp 2 -#define PIN3_bm 0x08 +#define PIN3_bm 0x08 #define PIN3_bp 3 -#define PIN4_bm 0x10 +#define PIN4_bm 0x10 #define PIN4_bp 4 -#define PIN5_bm 0x20 +#define PIN5_bm 0x20 #define PIN5_bp 5 -#define PIN6_bm 0x40 +#define PIN6_bm 0x40 #define PIN6_bp 6 -#define PIN7_bm 0x80 +#define PIN7_bm 0x80 #define PIN7_bp 7 @@ -7233,4 +7233,3 @@ IO Module Instances. Mapped to memory. #endif /* _AVR_ATxmega64A1_H_ */ - diff --git a/include/avr/iox64a1u.h b/include/avr/iox64a1u.h index d479ad74..eac67f86 100644 --- a/include/avr/iox64a1u.h +++ b/include/avr/iox64a1u.h @@ -42,7 +42,7 @@ # define _AVR_IOXXX_H_ "iox64a1u.h" #else # error "Attempt to include more than one file." -#endif +#endif #ifndef _AVR_ATxmega64A1U_H_ @@ -7084,21 +7084,21 @@ IO Module Instances. Mapped to memory. // Generic Port Pins -#define PIN0_bm 0x01 +#define PIN0_bm 0x01 #define PIN0_bp 0 #define PIN1_bm 0x02 #define PIN1_bp 1 -#define PIN2_bm 0x04 +#define PIN2_bm 0x04 #define PIN2_bp 2 -#define PIN3_bm 0x08 +#define PIN3_bm 0x08 #define PIN3_bp 3 -#define PIN4_bm 0x10 +#define PIN4_bm 0x10 #define PIN4_bp 4 -#define PIN5_bm 0x20 +#define PIN5_bm 0x20 #define PIN5_bp 5 -#define PIN6_bm 0x40 +#define PIN6_bm 0x40 #define PIN6_bp 6 -#define PIN7_bm 0x80 +#define PIN7_bm 0x80 #define PIN7_bp 7 @@ -7616,4 +7616,3 @@ IO Module Instances. Mapped to memory. #define __AVR_HAVE_PRPF_TC0 #endif /* _AVR_ATxmega64A1U_H_ */ - diff --git a/include/avr/iox64a3.h b/include/avr/iox64a3.h index 82a5092c..72f7e6bc 100644 --- a/include/avr/iox64a3.h +++ b/include/avr/iox64a3.h @@ -42,7 +42,7 @@ # define _AVR_IOXXX_H_ "iox64a3.h" #else # error "Attempt to include more than one file." -#endif +#endif #ifndef _AVR_ATxmega64A3_H_ @@ -6473,21 +6473,21 @@ IO Module Instances. Mapped to memory. // Generic Port Pins -#define PIN0_bm 0x01 +#define PIN0_bm 0x01 #define PIN0_bp 0 #define PIN1_bm 0x02 #define PIN1_bp 1 -#define PIN2_bm 0x04 +#define PIN2_bm 0x04 #define PIN2_bp 2 -#define PIN3_bm 0x08 +#define PIN3_bm 0x08 #define PIN3_bp 3 -#define PIN4_bm 0x10 +#define PIN4_bm 0x10 #define PIN4_bp 4 -#define PIN5_bm 0x20 +#define PIN5_bm 0x20 #define PIN5_bp 5 -#define PIN6_bm 0x40 +#define PIN6_bm 0x40 #define PIN6_bp 6 -#define PIN7_bm 0x80 +#define PIN7_bm 0x80 #define PIN7_bp 7 @@ -6984,4 +6984,3 @@ IO Module Instances. Mapped to memory. #endif /* _AVR_ATxmega64A3_H_ */ - diff --git a/include/avr/iox64a3u.h b/include/avr/iox64a3u.h index b2f43a88..4c0c6cbe 100644 --- a/include/avr/iox64a3u.h +++ b/include/avr/iox64a3u.h @@ -7697,4 +7697,3 @@ IO Module Instances. Mapped to memory. #endif /* #ifdef _AVR_ATXMEGA64A3U_H_INCLUDED */ - diff --git a/include/avr/iox64a4u.h b/include/avr/iox64a4u.h index 4215eb00..1f4a1e49 100644 --- a/include/avr/iox64a4u.h +++ b/include/avr/iox64a4u.h @@ -7309,4 +7309,3 @@ IO Module Instances. Mapped to memory. #endif /* #ifdef _AVR_ATXMEGA64A4U_H_INCLUDED */ - diff --git a/include/avr/iox64b1.h b/include/avr/iox64b1.h index 94496736..91162fcd 100644 --- a/include/avr/iox64b1.h +++ b/include/avr/iox64b1.h @@ -6454,4 +6454,3 @@ IO Module Instances. Mapped to memory. #endif /* #ifdef _AVR_ATXMEGA64B1_H_INCLUDED */ - diff --git a/include/avr/iox64b3.h b/include/avr/iox64b3.h index 8cf95d7b..98956bb8 100644 --- a/include/avr/iox64b3.h +++ b/include/avr/iox64b3.h @@ -6288,4 +6288,3 @@ IO Module Instances. Mapped to memory. #endif /* #ifdef _AVR_ATXMEGA64B3_H_INCLUDED */ - diff --git a/include/avr/iox64c3.h b/include/avr/iox64c3.h index 1412817d..d2da7478 100644 --- a/include/avr/iox64c3.h +++ b/include/avr/iox64c3.h @@ -6264,4 +6264,3 @@ IO Module Instances. Mapped to memory. #endif /* #ifdef _AVR_ATXMEGA64C3_H_INCLUDED */ - diff --git a/include/avr/iox64d3.h b/include/avr/iox64d3.h index 57972b68..cb68a34a 100644 --- a/include/avr/iox64d3.h +++ b/include/avr/iox64d3.h @@ -42,7 +42,7 @@ # define _AVR_IOXXX_H_ "iox64d3.h" #else # error "Attempt to include more than one file." -#endif +#endif #ifndef _AVR_ATxmega64D3_H_ @@ -1115,7 +1115,7 @@ typedef enum ADC_CH_GAIN_enum ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ - ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ + ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ } ADC_CH_GAIN_t; /* Conversion result resolution */ @@ -5368,21 +5368,21 @@ IO Module Instances. Mapped to memory. // Generic Port Pins -#define PIN0_bm 0x01 +#define PIN0_bm 0x01 #define PIN0_bp 0 #define PIN1_bm 0x02 #define PIN1_bp 1 -#define PIN2_bm 0x04 +#define PIN2_bm 0x04 #define PIN2_bp 2 -#define PIN3_bm 0x08 +#define PIN3_bm 0x08 #define PIN3_bp 3 -#define PIN4_bm 0x10 +#define PIN4_bm 0x10 #define PIN4_bp 4 -#define PIN5_bm 0x20 +#define PIN5_bm 0x20 #define PIN5_bp 5 -#define PIN6_bm 0x40 +#define PIN6_bm 0x40 #define PIN6_bp 6 -#define PIN7_bm 0x80 +#define PIN7_bm 0x80 #define PIN7_bp 7 @@ -5760,4 +5760,3 @@ IO Module Instances. Mapped to memory. #endif /* _AVR_ATxmega64D3_H_ */ - diff --git a/include/avr/iox64d4.h b/include/avr/iox64d4.h index 4359ef78..952f042c 100644 --- a/include/avr/iox64d4.h +++ b/include/avr/iox64d4.h @@ -5555,4 +5555,3 @@ IO Module Instances. Mapped to memory. #endif /* #ifdef _AVR_ATXMEGA64D4_H_INCLUDED */ - diff --git a/include/avr/iox8e5.h b/include/avr/iox8e5.h index 46e801f5..c6fa4952 100644 --- a/include/avr/iox8e5.h +++ b/include/avr/iox8e5.h @@ -1,7699 +1,7698 @@ -/***************************************************************************** - * - * Copyright (C) 2016 Atmel Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * * Neither the name of the copyright holders nor the names of - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************/ - - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iox8e5.h" -#else -# error "Attempt to include more than one file." -#endif - -#ifndef _AVR_ATXMEGA8E5_H_INCLUDED -#define _AVR_ATXMEGA8E5_H_INCLUDED - -/* Ungrouped common registers */ -#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ - -/* Deprecated */ -#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ - -#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ -#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ -#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ -#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ -#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ -#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ -#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ -#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ -#define SREG _SFR_MEM8(0x003F) /* Status Register */ - -/* C Language Only */ -#if !defined (__ASSEMBLER__) - -#include - -typedef volatile uint8_t register8_t; -typedef volatile uint16_t register16_t; -typedef volatile uint32_t register32_t; - - -#ifdef _WORDREGISTER -#undef _WORDREGISTER -#endif -#define _WORDREGISTER(regname) \ - __extension__ union \ - { \ - register16_t regname; \ - struct \ - { \ - register8_t regname ## L; \ - register8_t regname ## H; \ - }; \ - } - -#ifdef _DWORDREGISTER -#undef _DWORDREGISTER -#endif -#define _DWORDREGISTER(regname) \ - __extension__ union \ - { \ - register32_t regname; \ - struct \ - { \ - register8_t regname ## 0; \ - register8_t regname ## 1; \ - register8_t regname ## 2; \ - register8_t regname ## 3; \ - }; \ - } - - -/* -========================================================================== -IO Module Structures -========================================================================== -*/ - - -/* --------------------------------------------------------------------------- -VPORT - Virtual Ports --------------------------------------------------------------------------- -*/ - -/* Virtual Port */ -typedef struct VPORT_struct -{ - register8_t DIR; /* I/O Port Data Direction */ - register8_t OUT; /* I/O Port Output */ - register8_t IN; /* I/O Port Input */ - register8_t INTFLAGS; /* Interrupt Flag Register */ -} VPORT_t; - - -/* --------------------------------------------------------------------------- -XOCD - On-Chip Debug System --------------------------------------------------------------------------- -*/ - -/* On-Chip Debug System */ -typedef struct OCD_struct -{ - register8_t OCDR0; /* OCD Register 0 */ - register8_t OCDR1; /* OCD Register 1 */ -} OCD_t; - - -/* --------------------------------------------------------------------------- -CPU - CPU --------------------------------------------------------------------------- -*/ - -/* CCP signatures */ -typedef enum CCP_enum -{ - CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ - CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ -} CCP_t; - - -/* --------------------------------------------------------------------------- -CLK - Clock System --------------------------------------------------------------------------- -*/ - -/* Clock System */ -typedef struct CLK_struct -{ - register8_t CTRL; /* Control Register */ - register8_t PSCTRL; /* Prescaler Control Register */ - register8_t LOCK; /* Lock register */ - register8_t RTCCTRL; /* RTC Control Register */ - register8_t reserved_0x04; -} CLK_t; - - -/* Power Reduction */ -typedef struct PR_struct -{ - register8_t PRGEN; /* General Power Reduction */ - register8_t PRPA; /* Power Reduction Port A */ - register8_t reserved_0x02; - register8_t PRPC; /* Power Reduction Port C */ - register8_t PRPD; /* Power Reduction Port D */ - register8_t reserved_0x05; - register8_t reserved_0x06; -} PR_t; - -/* System Clock Selection */ -typedef enum CLK_SCLKSEL_enum -{ - CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ - CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ - CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ - CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ - CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ - CLK_SCLKSEL_RC8M_gc = (0x05<<0), /* Internal 8 MHz RC Oscillator */ -} CLK_SCLKSEL_t; - -/* Prescaler A Division Factor */ -typedef enum CLK_PSADIV_enum -{ - CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ - CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ - CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ - CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ - CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ - CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ - CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ - CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ - CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ - CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ - CLK_PSADIV_6_gc = (0x13<<2), /* Divide by 6 */ - CLK_PSADIV_10_gc = (0x15<<2), /* Divide by 10 */ - CLK_PSADIV_12_gc = (0x17<<2), /* Divide by 12 */ - CLK_PSADIV_24_gc = (0x19<<2), /* Divide by 24 */ - CLK_PSADIV_48_gc = (0x1B<<2), /* Divide by 48 */ -} CLK_PSADIV_t; - -/* Prescaler B and C Division Factor */ -typedef enum CLK_PSBCDIV_enum -{ - CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ - CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ - CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ - CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ -} CLK_PSBCDIV_t; - -/* RTC Clock Source */ -typedef enum CLK_RTCSRC_enum -{ - CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ - CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ - CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ - CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ - CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ - CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ -} CLK_RTCSRC_t; - - -/* --------------------------------------------------------------------------- -SLEEP - Sleep Controller --------------------------------------------------------------------------- -*/ - -/* Sleep Controller */ -typedef struct SLEEP_struct -{ - register8_t CTRL; /* Control Register */ -} SLEEP_t; - -/* Sleep Mode */ -typedef enum SLEEP_SMODE_enum -{ - SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ - SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ - SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ - SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ - SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ -} SLEEP_SMODE_t; - - - -#define SLEEP_MODE_IDLE (0x00<<1) -#define SLEEP_MODE_PWR_DOWN (0x02<<1) -#define SLEEP_MODE_PWR_SAVE (0x03<<1) -#define SLEEP_MODE_STANDBY (0x06<<1) -#define SLEEP_MODE_EXT_STANDBY (0x07<<1) -/* --------------------------------------------------------------------------- -OSC - Oscillator --------------------------------------------------------------------------- -*/ - -/* Oscillator */ -typedef struct OSC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t XOSCCTRL; /* External Oscillator Control Register */ - register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ - register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ - register8_t PLLCTRL; /* PLL Control Register */ - register8_t DFLLCTRL; /* DFLL Control Register */ - register8_t RC8MCAL; /* Internal 8 MHz RC Oscillator Calibration Register */ -} OSC_t; - -/* Oscillator Frequency Range */ -typedef enum OSC_FRQRANGE_enum -{ - OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ - OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ - OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ - OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ -} OSC_FRQRANGE_t; - -/* External Oscillator Selection and Startup Time */ -typedef enum OSC_XOSCSEL_enum -{ - OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock on port R1 - 6 CLK */ - OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ - OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ - OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ - OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ - OSC_XOSCSEL_EXTCLK_C4_gc = (0x14<<0), /* External Clock on port C4 - 6 CLK */ -} OSC_XOSCSEL_t; - -/* PLL Clock Source */ -typedef enum OSC_PLLSRC_enum -{ - OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ - OSC_PLLSRC_RC8M_gc = (0x01<<6), /* Internal 8 MHz RC Oscillator */ - OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ - OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ -} OSC_PLLSRC_t; - -/* 32 MHz DFLL Calibration Reference */ -typedef enum OSC_RC32MCREF_enum -{ - OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ - OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ -} OSC_RC32MCREF_t; - - -/* --------------------------------------------------------------------------- -DFLL - DFLL --------------------------------------------------------------------------- -*/ - -/* DFLL */ -typedef struct DFLL_struct -{ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x01; - register8_t CALA; /* Calibration Register A */ - register8_t CALB; /* Calibration Register B */ - register8_t COMP0; /* Oscillator Compare Register 0 */ - register8_t COMP1; /* Oscillator Compare Register 1 */ - register8_t COMP2; /* Oscillator Compare Register 2 */ - register8_t reserved_0x07; -} DFLL_t; - - -/* --------------------------------------------------------------------------- -RST - Reset --------------------------------------------------------------------------- -*/ - -/* Reset */ -typedef struct RST_struct -{ - register8_t STATUS; /* Status Register */ - register8_t CTRL; /* Control Register */ -} RST_t; - - -/* --------------------------------------------------------------------------- -WDT - Watch-Dog Timer --------------------------------------------------------------------------- -*/ - -/* Watch-Dog Timer */ -typedef struct WDT_struct -{ - register8_t CTRL; /* Control */ - register8_t WINCTRL; /* Windowed Mode Control */ - register8_t STATUS; /* Status */ -} WDT_t; - -/* Period setting */ -typedef enum WDT_PER_enum -{ - WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ - WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ - WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ - WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ - WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ - WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ - WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ - WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ - WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ - WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -} WDT_PER_t; - -/* Closed window period */ -typedef enum WDT_WPER_enum -{ - WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ - WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ - WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ - WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ - WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ - WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ - WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ - WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ - WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ - WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -} WDT_WPER_t; - - -/* --------------------------------------------------------------------------- -MCU - MCU Control --------------------------------------------------------------------------- -*/ - -/* MCU Control */ -typedef struct MCU_struct -{ - register8_t DEVID0; /* Device ID byte 0 */ - register8_t DEVID1; /* Device ID byte 1 */ - register8_t DEVID2; /* Device ID byte 2 */ - register8_t REVID; /* Revision ID */ - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t ANAINIT; /* Analog Startup Delay */ - register8_t EVSYSLOCK; /* Event System Lock */ - register8_t WEXLOCK; /* WEX Lock */ - register8_t FAULTLOCK; /* FAULT Lock */ - register8_t reserved_0x0B; -} MCU_t; - - -/* --------------------------------------------------------------------------- -PMIC - Programmable Multi-level Interrupt Controller --------------------------------------------------------------------------- -*/ - -/* Programmable Multi-level Interrupt Controller */ -typedef struct PMIC_struct -{ - register8_t STATUS; /* Status Register */ - register8_t INTPRI; /* Interrupt Priority */ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x03; - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; -} PMIC_t; - - -/* --------------------------------------------------------------------------- -PORTCFG - Port Configuration --------------------------------------------------------------------------- -*/ - -/* I/O port Configuration */ -typedef struct PORTCFG_struct -{ - register8_t MPCMASK; /* Multi-pin Configuration Mask */ - register8_t reserved_0x01; - register8_t reserved_0x02; - register8_t reserved_0x03; - register8_t CLKOUT; /* Clock Out Register */ - register8_t reserved_0x05; - register8_t ACEVOUT; /* Analog Comparator and Event Out Register */ - register8_t SRLCTRL; /* Slew Rate Limit Control Register */ -} PORTCFG_t; - -/* Clock and Event Output Port */ -typedef enum PORTCFG_CLKEVPIN_enum -{ - PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */ - PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */ -} PORTCFG_CLKEVPIN_t; - -/* RTC Clock Output Port */ -typedef enum PORTCFG_RTCCLKOUT_enum -{ - PORTCFG_RTCCLKOUT_OFF_gc = (0x00<<5), /* System Clock Output Disabled */ - PORTCFG_RTCCLKOUT_PC6_gc = (0x01<<5), /* System Clock Output on Port C pin 6 */ - PORTCFG_RTCCLKOUT_PD6_gc = (0x02<<5), /* System Clock Output on Port D pin 6 */ - PORTCFG_RTCCLKOUT_PR0_gc = (0x03<<5), /* System Clock Output on Port R pin 0 */ -} PORTCFG_RTCCLKOUT_t; - -/* Peripheral Clock Output Select */ -typedef enum PORTCFG_CLKOUTSEL_enum -{ - PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ - PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ - PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ -} PORTCFG_CLKOUTSEL_t; - -/* System Clock Output Port */ -typedef enum PORTCFG_CLKOUT_enum -{ - PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ - PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ - PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ - PORTCFG_CLKOUT_PR0_gc = (0x03<<0), /* System Clock Output on Port R pin 0 */ -} PORTCFG_CLKOUT_t; - -/* Analog Comparator Output Port */ -typedef enum PORTCFG_ACOUT_enum -{ - PORTCFG_ACOUT_PA_gc = (0x00<<6), /* Analog Comparator Outputs on Port A, Pin 6-7 */ - PORTCFG_ACOUT_PC_gc = (0x01<<6), /* Analog Comparator Outputs on Port C, Pin 6-7 */ - PORTCFG_ACOUT_PD_gc = (0x02<<6), /* Analog Comparator Outputs on Port D, Pin 6-7 */ - PORTCFG_ACOUT_PR_gc = (0x03<<6), /* Analog Comparator Outputs on Port R, Pin 0-1 */ -} PORTCFG_ACOUT_t; - -/* Event Output Port */ -typedef enum PORTCFG_EVOUT_enum -{ - PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ - PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel n Output on Port C pin 7 */ - PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel n Output on Port D pin 7 */ - PORTCFG_EVOUT_PR0_gc = (0x03<<4), /* Event Channel n Output on Port R pin 0 */ -} PORTCFG_EVOUT_t; - -/* Event Output Select */ -typedef enum PORTCFG_EVOUTSEL_enum -{ - PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ - PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ - PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ - PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ - PORTCFG_EVOUTSEL_4_gc = (0x04<<0), /* Event Channel 4 output to pin */ - PORTCFG_EVOUTSEL_5_gc = (0x05<<0), /* Event Channel 5 output to pin */ - PORTCFG_EVOUTSEL_6_gc = (0x06<<0), /* Event Channel 6 output to pin */ - PORTCFG_EVOUTSEL_7_gc = (0x07<<0), /* Event Channel 7 output to pin */ -} PORTCFG_EVOUTSEL_t; - - -/* --------------------------------------------------------------------------- -CRC - Cyclic Redundancy Checker --------------------------------------------------------------------------- -*/ - -/* Cyclic Redundancy Checker */ -typedef struct CRC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t reserved_0x02; - register8_t DATAIN; /* Data Input */ - register8_t CHECKSUM0; /* Checksum byte 0 */ - register8_t CHECKSUM1; /* Checksum byte 1 */ - register8_t CHECKSUM2; /* Checksum byte 2 */ - register8_t CHECKSUM3; /* Checksum byte 3 */ -} CRC_t; - -/* Reset */ -typedef enum CRC_RESET_enum -{ - CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ - CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ - CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ -} CRC_RESET_t; - -/* Input Source */ -typedef enum CRC_SOURCE_enum -{ - CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ - CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ - CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ - CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */ - CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */ - CRC_SOURCE_DMAC2_gc = (0x06<<0), /* DMAC Channel 2 */ - CRC_SOURCE_DMAC3_gc = (0x07<<0), /* DMAC Channel 3 */ -} CRC_SOURCE_t; - - -/* --------------------------------------------------------------------------- -EDMA - Enhanced DMA Controller --------------------------------------------------------------------------- -*/ - -/* EDMA Channel */ -typedef struct EDMA_CH_struct -{ - register8_t CTRLA; /* Channel Control A */ - register8_t CTRLB; /* Channel Control */ - register8_t ADDRCTRL; /* Memory Address Control for Peripheral Ch., or Source Address Control for Standard Ch. */ - register8_t DESTADDRCTRL; /* Destination Address Control for Standard Channels Only. */ - register8_t TRIGSRC; /* Channel Trigger Source */ - register8_t reserved_0x05; - _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count for Peripheral Ch., or Channel Block Transfer Count Low for Standard Ch. */ - _WORDREGISTER(ADDR); /* Channel Memory Address for Peripheral Ch., or Channel Source Address Low for Standard Ch. */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; - _WORDREGISTER(DESTADDR); /* Channel Destination Address for Standard Channels Only. */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; -} EDMA_CH_t; - - -/* Enhanced DMA Controller */ -typedef struct EDMA_struct -{ - register8_t CTRL; /* Control */ - register8_t reserved_0x01; - register8_t reserved_0x02; - register8_t INTFLAGS; /* Transfer Interrupt Status */ - register8_t STATUS; /* Status */ - register8_t reserved_0x05; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - EDMA_CH_t CH0; /* EDMA Channel 0 */ - EDMA_CH_t CH1; /* EDMA Channel 1 */ - EDMA_CH_t CH2; /* EDMA Channel 2 */ - EDMA_CH_t CH3; /* EDMA Channel 3 */ -} EDMA_t; - -/* Channel mode */ -typedef enum EDMA_CHMODE_enum -{ - EDMA_CHMODE_PER0123_gc = (0x00<<4), /* Channels 0, 1, 2 and 3 in peripheal conf. */ - EDMA_CHMODE_STD0_gc = (0x01<<4), /* Channel 0 in standard conf.; channels 2 and 3 in peripheral conf. */ - EDMA_CHMODE_STD2_gc = (0x02<<4), /* Channel 2 in standard conf.; channels 0 and 1 in peripheral conf. */ - EDMA_CHMODE_STD02_gc = (0x03<<4), /* Channels 0 and 2 in standard conf. */ -} EDMA_CHMODE_t; - -/* Double buffer mode */ -typedef enum EDMA_DBUFMODE_enum -{ - EDMA_DBUFMODE_DISABLE_gc = (0x00<<2), /* No double buffer enabled */ - EDMA_DBUFMODE_BUF01_gc = (0x01<<2), /* Double buffer enabled on peripheral channels 0/1 (if exist) */ - EDMA_DBUFMODE_BUF23_gc = (0x02<<2), /* Double buffer enabled on peripheral channels 2/3 (if exist) */ - EDMA_DBUFMODE_BUF0123_gc = (0x03<<2), /* Double buffer enabled on peripheral channels 0/1 and 2/3 or standard channels 0/2 */ -} EDMA_DBUFMODE_t; - -/* Priority mode */ -typedef enum EDMA_PRIMODE_enum -{ - EDMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round robin on all channels */ - EDMA_PRIMODE_RR123_gc = (0x01<<0), /* Ch0 > round robin (Ch 1 ch2 Ch3) */ - EDMA_PRIMODE_RR23_gc = (0x02<<0), /* Ch0 > Ch 1 > round robin (Ch2 Ch3) */ - EDMA_PRIMODE_CH0123_gc = (0x03<<0), /* Ch0 > Ch1 > Ch2 > Ch3 */ -} EDMA_PRIMODE_t; - -/* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. */ -typedef enum EDMA_CH_RELOAD_enum -{ - EDMA_CH_RELOAD_NONE_gc = (0x00<<4), /* No reload */ - EDMA_CH_RELOAD_BLOCK_gc = (0x01<<4), /* Reload at end of each block transfer */ - EDMA_CH_RELOAD_BURST_gc = (0x02<<4), /* Reload at end of each burst transfer */ - EDMA_CH_RELOAD_TRANSACTION_gc = (0x03<<4), /* Reload at end of each transaction */ -} EDMA_CH_RELOAD_t; - -/* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. */ -typedef enum EDMA_CH_DIR_enum -{ - EDMA_CH_DIR_FIXED_gc = (0x00<<0), /* Fixed */ - EDMA_CH_DIR_INC_gc = (0x01<<0), /* Increment */ - EDMA_CH_DIR_MP1_gc = (0x04<<0), /* If Peripheral Ch. (Per ==> Mem), 1-byte 'mask-match' (data: ADDRL, mask: ADDRH), else reserved conf. */ - EDMA_CH_DIR_MP2_gc = (0x05<<0), /* If Peripheral Ch. (Per ==> Mem), 1-byte 'OR-match' (data-1: ADDRL OR data-2: ADDRH), else reserved conf. */ - EDMA_CH_DIR_MP3_gc = (0x06<<0), /* If Peripheral Ch. (Per ==> Mem), 2-byte 'match' (data-1: ADDRL followed by data-2: ADDRH), else reserved conf. */ -} EDMA_CH_DIR_t; - -/* Destination addressing mode */ -typedef enum EDMA_CH_DESTDIR_enum -{ - EDMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ - EDMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ - EDMA_CH_DESTDIR_MP1_gc = (0x04<<0), /* 1-byte 'mask-match' (data: ADDRL, mask: ADDRH) */ - EDMA_CH_DESTDIR_MP2_gc = (0x05<<0), /* 1-byte 'OR-match' (data-1: ADDRL OR data-2: ADDRH) */ - EDMA_CH_DESTDIR_MP3_gc = (0x06<<0), /* 2-byte 'match' (data1: ADDRL followed by data2: ADDRH) */ -} EDMA_CH_DESTDIR_t; - -/* Transfer trigger source */ -typedef enum EDMA_CH_TRIGSRC_enum -{ - EDMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Software triggers only */ - EDMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event CH0 as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event CH1 as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event CH2 as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA CH0 as trigger */ - EDMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA CH0 as trigger */ - EDMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA CH1 as trigger */ - EDMA_CH_TRIGSRC_TCC4_OVF_gc = (0x40<<0), /* TCC4 overflow/underflow as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_TCC4_ERR_gc = (0x41<<0), /* TCC4 error as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_TCC4_CCA_gc = (0x42<<0), /* TCC4 compare or capture channel A as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_TCC4_CCB_gc = (0x43<<0), /* TCC4 compare or capture channel B as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_TCC4_CCC_gc = (0x44<<0), /* TCC4 compare or capture channel C as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_TCC4_CCD_gc = (0x45<<0), /* TCC4 compare or capture channel D as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_TCC5_OVF_gc = (0x46<<0), /* TCC5 overflow/underflow as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_TCC5_ERR_gc = (0x47<<0), /* TCC5 error as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_TCC5_CCA_gc = (0x48<<0), /* TCC5 compare or capture channel A as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_TCC5_CCB_gc = (0x49<<0), /* TCC5 compare or capture channel B as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_SPIC_RXC_gc = (0x4A<<0), /* SPI C transfer complete (SPI Standard Mode) or SPI C receive complete as trigger (SPI Buffer Modes) */ - EDMA_CH_TRIGSRC_SPIC_DRE_gc = (0x4B<<0), /* SPI C transfer complete (SPI Standard Mode) or SPI C data register empty as trigger (SPI Buffer modes) */ - EDMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4C<<0), /* USART C0 receive complete as trigger */ - EDMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4D<<0), /* USART C0 data register empty as trigger */ - EDMA_CH_TRIGSRC_TCD5_OVF_gc = (0x66<<0), /* TCD5 overflow/underflow as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_TCD5_ERR_gc = (0x67<<0), /* TCD5 error as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_TCD5_CCA_gc = (0x68<<0), /* TCD5 compare or capture channel A as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_TCD5_CCB_gc = (0x69<<0), /* TCD5 compare or capture channel B as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6C<<0), /* USART D0 receive complete as trigger */ - EDMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6D<<0), /* USART D0 data register empty as trigger */ -} EDMA_CH_TRIGSRC_t; - -/* Interrupt level */ -typedef enum EDMA_CH_INTLVL_enum -{ - EDMA_CH_INTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ - EDMA_CH_INTLVL_LO_gc = (0x01<<2), /* Low level */ - EDMA_CH_INTLVL_MED_gc = (0x02<<2), /* Medium level */ - EDMA_CH_INTLVL_HI_gc = (0x03<<2), /* High level */ -} EDMA_CH_INTLVL_t; - - -/* --------------------------------------------------------------------------- -EVSYS - Event System --------------------------------------------------------------------------- -*/ - -/* Event System */ -typedef struct EVSYS_struct -{ - register8_t CH0MUX; /* Event Channel 0 Multiplexer */ - register8_t CH1MUX; /* Event Channel 1 Multiplexer */ - register8_t CH2MUX; /* Event Channel 2 Multiplexer */ - register8_t CH3MUX; /* Event Channel 3 Multiplexer */ - register8_t CH4MUX; /* Event Channel 4 Multiplexer */ - register8_t CH5MUX; /* Event Channel 5 Multiplexer */ - register8_t CH6MUX; /* Event Channel 6 Multiplexer */ - register8_t CH7MUX; /* Event Channel 7 Multiplexer */ - register8_t CH0CTRL; /* Channel 0 Control Register */ - register8_t CH1CTRL; /* Channel 1 Control Register */ - register8_t CH2CTRL; /* Channel 2 Control Register */ - register8_t CH3CTRL; /* Channel 3 Control Register */ - register8_t CH4CTRL; /* Channel 4 Control Register */ - register8_t CH5CTRL; /* Channel 5 Control Register */ - register8_t CH6CTRL; /* Channel 6 Control Register */ - register8_t CH7CTRL; /* Channel 7 Control Register */ - register8_t STROBE; /* Event Strobe */ - register8_t DATA; /* Event Data */ - register8_t DFCTRL; /* Digital Filter Control Register */ -} EVSYS_t; - -/* Event Channel multiplexer input selection */ -typedef enum EVSYS_CHMUX_enum -{ - EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ - EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ - EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ - EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ - EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ - EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ - EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ - EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ - EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ - EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ - EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ - EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ - EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ - EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ - EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ - EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ - EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ - EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ - EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ - EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ - EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ - EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ - EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ - EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ - EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ - EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ - EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ - EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ - EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ - EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ - EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ - EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ - EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ - EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ - EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ - EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ - EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ - EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ - EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ - EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ - EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ - EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ - EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ - EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ - EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ - EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ - EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ - EVSYS_CHMUX_XCL_UNF0_gc = (0xB0<<0), /* XCL BTC0 underflow */ - EVSYS_CHMUX_XCL_UNF1_gc = (0xB1<<0), /* XCL BTC1 underflow */ - EVSYS_CHMUX_XCL_CC0_gc = (0xB2<<0), /* XCL BTC0 capture or compare */ - EVSYS_CHMUX_XCL_CC1_gc = (0xB3<<0), /* XCL BTC0 capture or compare */ - EVSYS_CHMUX_XCL_PEC0_gc = (0xB4<<0), /* XCL PEC0 restart */ - EVSYS_CHMUX_XCL_PEC1_gc = (0xB5<<0), /* XCL PEC1 restart */ - EVSYS_CHMUX_XCL_LUT0_gc = (0xB6<<0), /* XCL LUT0 output */ - EVSYS_CHMUX_XCL_LUT1_gc = (0xB7<<0), /* XCL LUT1 output */ - EVSYS_CHMUX_TCC4_OVF_gc = (0xC0<<0), /* Timer/Counter C4 Overflow */ - EVSYS_CHMUX_TCC4_ERR_gc = (0xC1<<0), /* Timer/Counter C4 Error */ - EVSYS_CHMUX_TCC4_CCA_gc = (0xC4<<0), /* Timer/Counter C4 Compare or Capture A */ - EVSYS_CHMUX_TCC4_CCB_gc = (0xC5<<0), /* Timer/Counter C4 Compare or Capture B */ - EVSYS_CHMUX_TCC4_CCC_gc = (0xC6<<0), /* Timer/Counter C4 Compare or Capture C */ - EVSYS_CHMUX_TCC4_CCD_gc = (0xC7<<0), /* Timer/Counter C4 Compare or Capture D */ - EVSYS_CHMUX_TCC5_OVF_gc = (0xC8<<0), /* Timer/Counter C5 Overflow */ - EVSYS_CHMUX_TCC5_ERR_gc = (0xC9<<0), /* Timer/Counter C5 Error */ - EVSYS_CHMUX_TCC5_CCA_gc = (0xCC<<0), /* Timer/Counter C5 Compare or Capture A */ - EVSYS_CHMUX_TCC5_CCB_gc = (0xCD<<0), /* Timer/Counter C5 Compare or Capture B */ - EVSYS_CHMUX_TCD5_OVF_gc = (0xD8<<0), /* Timer/Counter D5 Overflow */ - EVSYS_CHMUX_TCD5_ERR_gc = (0xD9<<0), /* Timer/Counter D5 Error */ - EVSYS_CHMUX_TCD5_CCA_gc = (0xDC<<0), /* Timer/Counter D5 Compare or Capture A */ - EVSYS_CHMUX_TCD5_CCB_gc = (0xDD<<0), /* Timer/Counter D5 Compare or Capture B */ -} EVSYS_CHMUX_t; - -/* Quadrature Decoder Index Recognition Mode */ -typedef enum EVSYS_QDIRM_enum -{ - EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ - EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ - EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ - EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ -} EVSYS_QDIRM_t; - -/* Digital filter coefficient */ -typedef enum EVSYS_DIGFILT_enum -{ - EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ - EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ - EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ - EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ - EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ - EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ - EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ - EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ -} EVSYS_DIGFILT_t; - -/* Prescaler Filter */ -typedef enum EVSYS_PRESCFILT_enum -{ - EVSYS_PRESCFILT_CH04_gc = (0x01<<4), /* Enable prescaler filter for either channel 0 or 4 */ - EVSYS_PRESCFILT_CH15_gc = (0x02<<4), /* Enable prescaler filter for either channel 1 or 5 */ - EVSYS_PRESCFILT_CH26_gc = (0x04<<4), /* Enable prescaler filter for either channel 2 or 6 */ - EVSYS_PRESCFILT_CH37_gc = (0x08<<4), /* Enable prescaler filter for either channel 3 or 7 */ -} EVSYS_PRESCFILT_t; - -/* Prescaler */ -typedef enum EVSYS_PRESCALER_enum -{ - EVSYS_PRESCALER_CLKPER_8_gc = (0x00<<0), /* CLKPER, divide by 8 */ - EVSYS_PRESCALER_CLKPER_64_gc = (0x01<<0), /* CLKPER, divide by 64 */ - EVSYS_PRESCALER_CLKPER_512_gc = (0x02<<0), /* CLKPER, divide by 512 */ - EVSYS_PRESCALER_CLKPER_4096_gc = (0x03<<0), /* CLKPER, divide by 4096 */ - EVSYS_PRESCALER_CLKPER_32768_gc = (0x04<<0), /* CLKPER, divide by 32768 */ -} EVSYS_PRESCALER_t; - - -/* --------------------------------------------------------------------------- -NVM - Non Volatile Memory Controller --------------------------------------------------------------------------- -*/ - -/* Non-volatile Memory Controller */ -typedef struct NVM_struct -{ - register8_t ADDR0; /* Address Register 0 */ - register8_t ADDR1; /* Address Register 1 */ - register8_t ADDR2; /* Address Register 2 */ - register8_t reserved_0x03; - register8_t DATA0; /* Data Register 0 */ - register8_t DATA1; /* Data Register 1 */ - register8_t DATA2; /* Data Register 2 */ - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t CMD; /* Command */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t INTCTRL; /* Interrupt Control */ - register8_t reserved_0x0E; - register8_t STATUS; /* Status */ - register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ -} NVM_t; - -/* NVM Command */ -typedef enum NVM_CMD_enum -{ - NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ - NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ - NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ - NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ - NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ - NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ - NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ - NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ - NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ - NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ - NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ - NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ - NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ - NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ - NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ - NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ - NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ - NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ - NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ - NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ - NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ - NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ - NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ - NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ - NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ - NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ - NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ - NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ - NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ - NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ - NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ - NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ -} NVM_CMD_t; - -/* SPM ready interrupt level */ -typedef enum NVM_SPMLVL_enum -{ - NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ - NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ - NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ - NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ -} NVM_SPMLVL_t; - -/* EEPROM ready interrupt level */ -typedef enum NVM_EELVL_enum -{ - NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ - NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ - NVM_EELVL_HI_gc = (0x03<<0), /* High level */ -} NVM_EELVL_t; - -/* Boot lock bits - boot setcion */ -typedef enum NVM_BLBB_enum -{ - NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ - NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ - NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ - NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -} NVM_BLBB_t; - -/* Boot lock bits - application section */ -typedef enum NVM_BLBA_enum -{ - NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ - NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ - NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ - NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -} NVM_BLBA_t; - -/* Boot lock bits - application table section */ -typedef enum NVM_BLBAT_enum -{ - NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ - NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ - NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ - NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -} NVM_BLBAT_t; - -/* Lock bits */ -typedef enum NVM_LB_enum -{ - NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ - NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ - NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -} NVM_LB_t; - - -/* --------------------------------------------------------------------------- -ADC - Analog/Digital Converter --------------------------------------------------------------------------- -*/ - -/* ADC Channel */ -typedef struct ADC_CH_struct -{ - register8_t CTRL; /* Control Register */ - register8_t MUXCTRL; /* MUX Control */ - register8_t INTCTRL; /* Channel Interrupt Control Register */ - register8_t INTFLAGS; /* Interrupt Flags */ - _WORDREGISTER(RES); /* Channel Result */ - register8_t SCAN; /* Input Channel Scan */ - register8_t CORRCTRL; /* Correction Control Register */ - register8_t OFFSETCORR0; /* Offset Correction Register 0 */ - register8_t OFFSETCORR1; /* Offset Correction Register 1 */ - register8_t GAINCORR0; /* Gain Correction Register 0 */ - register8_t GAINCORR1; /* Gain Correction Register 1 */ - register8_t AVGCTRL; /* Average Control Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; -} ADC_CH_t; - - -/* Analog-to-Digital Converter */ -typedef struct ADC_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t REFCTRL; /* Reference Control */ - register8_t EVCTRL; /* Event Control */ - register8_t PRESCALER; /* Clock Prescaler */ - register8_t reserved_0x05; - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t TEMP; /* Temporary Register */ - register8_t SAMPCTRL; /* ADC Sampling Time Control Register */ - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - _WORDREGISTER(CAL); /* Calibration Value */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - _WORDREGISTER(CH0RES); /* Channel 0 Result */ - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - _WORDREGISTER(CMP); /* Compare Value */ - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - ADC_CH_t CH0; /* ADC Channel 0 */ -} ADC_t; - -/* Current Limitation */ -typedef enum ADC_CURRLIMIT_enum -{ - ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ - ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 250ksps max sampling rate */ - ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ - ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 50ksps max sampling rate */ -} ADC_CURRLIMIT_t; - -/* Conversion result resolution */ -typedef enum ADC_RESOLUTION_enum -{ - ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ - ADC_RESOLUTION_MT12BIT_gc = (0x01<<1), /* More than 12-bit (oversapling) right-adjusted result */ - ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ - ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ -} ADC_RESOLUTION_t; - -/* Voltage reference selection */ -typedef enum ADC_REFSEL_enum -{ - ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ - ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ - ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ - ADC_REFSEL_AREFD_gc = (0x03<<4), /* External reference on PORT D */ - ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ -} ADC_REFSEL_t; - -/* Event channel input selection */ -typedef enum ADC_EVSEL_enum -{ - ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */ - ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */ - ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */ - ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */ - ADC_EVSEL_4_gc = (0x04<<3), /* Event Channel 4 */ - ADC_EVSEL_5_gc = (0x05<<3), /* Event Channel 5 */ - ADC_EVSEL_6_gc = (0x06<<3), /* Event Channel 6 */ - ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ -} ADC_EVSEL_t; - -/* Event action selection */ -typedef enum ADC_EVACT_enum -{ - ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ - ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel conversion */ - ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ -} ADC_EVACT_t; - -/* Clock prescaler */ -typedef enum ADC_PRESCALER_enum -{ - ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ - ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ - ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ - ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ - ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ - ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ - ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ - ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ -} ADC_PRESCALER_t; - -/* Gain factor */ -typedef enum ADC_CH_GAIN_enum -{ - ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ - ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ - ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ - ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ - ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ - ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ - ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ - ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ -} ADC_CH_GAIN_t; - -/* Input mode */ -typedef enum ADC_CH_INPUTMODE_enum -{ - ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ - ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ - ADC_CH_INPUTMODE_DIFFWGAINL_gc = (0x02<<0), /* Differential input, gain with 4 LSB pins selection */ - ADC_CH_INPUTMODE_DIFFWGAINH_gc = (0x03<<0), /* Differential input, gain with 4 MSB pins selection */ -} ADC_CH_INPUTMODE_t; - -/* Positive input multiplexer selection */ -typedef enum ADC_CH_MUXPOS_enum -{ - ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ - ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ - ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ - ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ - ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ - ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ - ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ - ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ - ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ - ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ - ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ - ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ - ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ - ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ - ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ - ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ -} ADC_CH_MUXPOS_t; - -/* Internal input multiplexer selections */ -typedef enum ADC_CH_MUXINT_enum -{ - ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ - ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ - ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 Scaled VCC */ - ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC Output */ -} ADC_CH_MUXINT_t; - -/* Negative input multiplexer selection when gain on 4 LSB pins */ -typedef enum ADC_CH_MUXNEGL_enum -{ - ADC_CH_MUXNEGL_PIN0_gc = (0x00<<0), /* Input pin 0 */ - ADC_CH_MUXNEGL_PIN1_gc = (0x01<<0), /* Input pin 1 */ - ADC_CH_MUXNEGL_PIN2_gc = (0x02<<0), /* Input pin 2 */ - ADC_CH_MUXNEGL_PIN3_gc = (0x03<<0), /* Input pin 3 */ - ADC_CH_MUXNEGL_GND_gc = (0x05<<0), /* PAD ground */ - ADC_CH_MUXNEGL_INTGND_gc = (0x07<<0), /* Internal ground */ -} ADC_CH_MUXNEGL_t; - -/* Negative input multiplexer selection when gain on 4 MSB pins */ -typedef enum ADC_CH_MUXNEGH_enum -{ - ADC_CH_MUXNEGH_PIN4_gc = (0x00<<0), /* Input pin 4 */ - ADC_CH_MUXNEGH_PIN5_gc = (0x01<<0), /* Input pin 5 */ - ADC_CH_MUXNEGH_PIN6_gc = (0x02<<0), /* Input pin 6 */ - ADC_CH_MUXNEGH_PIN7_gc = (0x03<<0), /* Input pin 7 */ - ADC_CH_MUXNEGH_GND_gc = (0x05<<0), /* PAD ground */ -} ADC_CH_MUXNEGH_t; - -/* Negative input multiplexer selection */ -typedef enum ADC_CH_MUXNEG_enum -{ - ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ -} ADC_CH_MUXNEG_t; - -/* Interupt mode */ -typedef enum ADC_CH_INTMODE_enum -{ - ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ - ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ - ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ -} ADC_CH_INTMODE_t; - -/* Interrupt level */ -typedef enum ADC_CH_INTLVL_enum -{ - ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ - ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ - ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ -} ADC_CH_INTLVL_t; - -/* Averaged Number of Samples */ -typedef enum ADC_SAMPNUM_enum -{ - ADC_SAMPNUM_1X_gc = (0x00<<0), /* 1 Sample */ - ADC_SAMPNUM_2X_gc = (0x01<<0), /* 2 Samples */ - ADC_SAMPNUM_4X_gc = (0x02<<0), /* 4 Samples */ - ADC_SAMPNUM_8X_gc = (0x03<<0), /* 8 Samples */ - ADC_SAMPNUM_16X_gc = (0x04<<0), /* 16 Samples */ - ADC_SAMPNUM_32X_gc = (0x05<<0), /* 32 Samples */ - ADC_SAMPNUM_64X_gc = (0x06<<0), /* 64 Samples */ - ADC_SAMPNUM_128X_gc = (0x07<<0), /* 128 Samples */ - ADC_SAMPNUM_256X_gc = (0x08<<0), /* 256 Samples */ - ADC_SAMPNUM_512X_gc = (0x09<<0), /* 512 Samples */ - ADC_SAMPNUM_1024X_gc = (0x0A<<0), /* 1024 Samples */ -} ADC_SAMPNUM_t; - - -/* --------------------------------------------------------------------------- -DAC - Digital/Analog Converter --------------------------------------------------------------------------- -*/ - -/* Digital-to-Analog Converter */ -typedef struct DAC_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t EVCTRL; /* Event Input Control */ - register8_t reserved_0x04; - register8_t STATUS; /* Status */ - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t CH0GAINCAL; /* Gain Calibration */ - register8_t CH0OFFSETCAL; /* Offset Calibration */ - register8_t CH1GAINCAL; /* Gain Calibration */ - register8_t CH1OFFSETCAL; /* Offset Calibration */ - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - _WORDREGISTER(CH0DATA); /* Channel 0 Data */ - _WORDREGISTER(CH1DATA); /* Channel 1 Data */ -} DAC_t; - -/* Output channel selection */ -typedef enum DAC_CHSEL_enum -{ - DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel 0 only) */ - DAC_CHSEL_SINGLE1_gc = (0x01<<5), /* Single channel operation (Channel 1 only) */ - DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (Channel 0 and channel 1) */ -} DAC_CHSEL_t; - -/* Reference voltage selection */ -typedef enum DAC_REFSEL_enum -{ - DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ - DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ - DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ - DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ -} DAC_REFSEL_t; - -/* Event channel selection */ -typedef enum DAC_EVSEL_enum -{ - DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ - DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ - DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ - DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ - DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ - DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ - DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ - DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ -} DAC_EVSEL_t; - - -/* --------------------------------------------------------------------------- -AC - Analog Comparator --------------------------------------------------------------------------- -*/ - -/* Analog Comparator */ -typedef struct AC_struct -{ - register8_t AC0CTRL; /* Analog Comparator 0 Control */ - register8_t AC1CTRL; /* Analog Comparator 1 Control */ - register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ - register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t WINCTRL; /* Window Mode Control */ - register8_t STATUS; /* Status */ - register8_t CURRCTRL; /* Current Source Control Register */ - register8_t CURRCALIB; /* Current Source Calibration Register */ -} AC_t; - -/* Interrupt mode */ -typedef enum AC_INTMODE_enum -{ - AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ - AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ - AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ -} AC_INTMODE_t; - -/* Interrupt level */ -typedef enum AC_INTLVL_enum -{ - AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ - AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ - AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ - AC_INTLVL_HI_gc = (0x03<<4), /* High level */ -} AC_INTLVL_t; - -/* Hysteresis mode selection */ -typedef enum AC_HYSMODE_enum -{ - AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ - AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ - AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ -} AC_HYSMODE_t; - -/* Positive input multiplexer selection */ -typedef enum AC_MUXPOS_enum -{ - AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ - AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ - AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ - AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ - AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ - AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ - AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ - AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ -} AC_MUXPOS_t; - -/* Negative input multiplexer selection */ -typedef enum AC_MUXNEG_enum -{ - AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ - AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ - AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ - AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ - AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ - AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ - AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ - AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ -} AC_MUXNEG_t; - -/* Windows interrupt mode */ -typedef enum AC_WINTMODE_enum -{ - AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ - AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ - AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ - AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ -} AC_WINTMODE_t; - -/* Window interrupt level */ -typedef enum AC_WINTLVL_enum -{ - AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ - AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ - AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ -} AC_WINTLVL_t; - -/* Window mode state */ -typedef enum AC_WSTATE_enum -{ - AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ - AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ - AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ -} AC_WSTATE_t; - - -/* --------------------------------------------------------------------------- -RTC - Real-Time Clounter --------------------------------------------------------------------------- -*/ - -/* Real-Time Counter */ -typedef struct RTC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t TEMP; /* Temporary register */ - register8_t reserved_0x05; - register8_t CALIB; /* Calibration Register */ - register8_t reserved_0x07; - _WORDREGISTER(CNT); /* Count Register */ - _WORDREGISTER(PER); /* Period Register */ - _WORDREGISTER(COMP); /* Compare Register */ -} RTC_t; - -/* Prescaler Factor */ -typedef enum RTC_PRESCALER_enum -{ - RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ - RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ - RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ - RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ - RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ - RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ - RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ - RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ -} RTC_PRESCALER_t; - -/* Compare Interrupt level */ -typedef enum RTC_COMPINTLVL_enum -{ - RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ - RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ -} RTC_COMPINTLVL_t; - -/* Overflow Interrupt level */ -typedef enum RTC_OVFINTLVL_enum -{ - RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} RTC_OVFINTLVL_t; - - -/* --------------------------------------------------------------------------- -XCL - XMEGA Custom Logic --------------------------------------------------------------------------- -*/ - -/* XMEGA Custom Logic */ -typedef struct XCL_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t CTRLF; /* Control Register F */ - register8_t CTRLG; /* Control Register G */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t PLC; /* Peripheral Lenght Control Register */ - register8_t CNTL; /* Counter Register Low */ - register8_t CNTH; /* Counter Register High */ - register8_t CMPL; /* Compare Register Low */ - register8_t CMPH; /* Compare Register High */ - register8_t PERCAPTL; /* Period or Capture Register Low */ - register8_t PERCAPTH; /* Period or Capture Register High */ -} XCL_t; - -/* LUT0 Output Enable */ -typedef enum XCL_LUTOUTEN_enum -{ - XCL_LUTOUTEN_DISABLE_gc = (0x00<<6), /* LUT0 output disabled */ - XCL_LUTOUTEN_PIN0_gc = (0x01<<6), /* LUT0 Output to pin 0 */ - XCL_LUTOUTEN_PIN4_gc = (0x02<<6), /* LUT0 Output to pin 4 */ -} XCL_LUTOUTEN_t; - -/* Port Selection */ -typedef enum XCL_PORTSEL_enum -{ - XCL_PORTSEL_PC_gc = (0x00<<4), /* Port C for LUT or USARTC0 for PEC */ - XCL_PORTSEL_PD_gc = (0x01<<4), /* Port D for LUT or USARTD0 for PEC */ -} XCL_PORTSEL_t; - -/* LUT Configuration */ -typedef enum XCL_LUTCONF_enum -{ - XCL_LUTCONF_2LUT2IN_gc = (0x00<<0), /* 2-Input two LUT */ - XCL_LUTCONF_2LUT1IN_gc = (0x01<<0), /* Two LUT with duplicated input */ - XCL_LUTCONF_2LUT3IN_gc = (0x02<<0), /* Two LUT with one common input */ - XCL_LUTCONF_1LUT3IN_gc = (0x03<<0), /* 3-Input LUT */ - XCL_LUTCONF_MUX_gc = (0x04<<0), /* One LUT Mux */ - XCL_LUTCONF_DLATCH_gc = (0x05<<0), /* One D-Latch LUT */ - XCL_LUTCONF_RSLATCH_gc = (0x06<<0), /* One RS-Latch LUT */ - XCL_LUTCONF_DFF_gc = (0x07<<0), /* One DFF LUT */ -} XCL_LUTCONF_t; - -/* Input Selection */ -typedef enum XCL_INSEL_enum -{ - XCL_INSEL_EVSYS_gc = (0x00<<6), /* Event system selected as source */ - XCL_INSEL_XCL_gc = (0x01<<6), /* XCL selected as source */ - XCL_INSEL_PINL_gc = (0x02<<6), /* LSB port pin selected as source */ - XCL_INSEL_PINH_gc = (0x03<<6), /* MSB port pin selected as source */ -} XCL_INSEL_t; - -/* Delay Configuration on LUT */ -typedef enum XCL_DLYCONF_enum -{ - XCL_DLYCONF_DISABLE_gc = (0x00<<2), /* Delay element disabled */ - XCL_DLYCONF_IN_gc = (0x01<<2), /* Delay enabled on LUT input */ - XCL_DLYCONF_OUT_gc = (0x02<<2), /* Delay enabled on LUT output */ -} XCL_DLYCONF_t; - -/* Delay Selection */ -typedef enum XCL_DLYSEL_enum -{ - XCL_DLYSEL_DLY11_gc = (0x00<<4), /* One cycle delay for each LUT1 and LUT0 */ - XCL_DLYSEL_DLY12_gc = (0x01<<4), /* One cycle delay for LUT1 and two cycles for LUT0 */ - XCL_DLYSEL_DLY21_gc = (0x02<<4), /* Two cycles delay for LUT1 and one cycle for LUT0 */ - XCL_DLYSEL_DLY22_gc = (0x03<<4), /* Two cycle delays for each LUT1 and LUT0 */ -} XCL_DLYSEL_t; - -/* Clock Selection */ -typedef enum XCL_CLKSEL_enum -{ - XCL_CLKSEL_OFF_gc = (0x00<<0), /* OFF */ - XCL_CLKSEL_DIV1_gc = (0x01<<0), /* Prescaler clk */ - XCL_CLKSEL_DIV2_gc = (0x02<<0), /* Prescaler clk/2 */ - XCL_CLKSEL_DIV4_gc = (0x03<<0), /* Prescaler clk/4 */ - XCL_CLKSEL_DIV8_gc = (0x04<<0), /* Prescaler clk/8 */ - XCL_CLKSEL_DIV64_gc = (0x05<<0), /* Prescaler clk/64 */ - XCL_CLKSEL_DIV256_gc = (0x06<<0), /* Prescaler clk/256 */ - XCL_CLKSEL_DIV1024_gc = (0x07<<0), /* Prescaler clk/1024 */ - XCL_CLKSEL_EVCH0_gc = (0x08<<0), /* Event channel 0 */ - XCL_CLKSEL_EVCH1_gc = (0x09<<0), /* Event channel 1 */ - XCL_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event channel 2 */ - XCL_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event channel 3 */ - XCL_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event channel 4 */ - XCL_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event channel 5 */ - XCL_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event channel 6 */ - XCL_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event channel 7 */ -} XCL_CLKSEL_t; - -/* Timer/Counter Command Selection */ -typedef enum XCL_CMDSEL_enum -{ - XCL_CMDSEL_NONE_gc = (0x00<<7), /* None */ - XCL_CMDSEL_RESTART_gc = (0x01<<7), /* Force restart */ -} XCL_CMDSEL_t; - -/* Timer/Counter Selection */ -typedef enum XCL_TCSEL_enum -{ - XCL_TCSEL_TC16_gc = (0x00<<4), /* 16-bit timer/counter */ - XCL_TCSEL_BTC0_gc = (0x01<<4), /* One 8-bit timer/counter */ - XCL_TCSEL_BTC01_gc = (0x02<<4), /* Two 8-bit timer/counters */ - XCL_TCSEL_BTC0PEC1_gc = (0x03<<4), /* One 8-bit timer/counter and one 8-bit peripheral counter */ - XCL_TCSEL_PEC0BTC1_gc = (0x04<<4), /* One 8-bit timer/counter and one 8-bit peripheral counter */ - XCL_TCSEL_PEC01_gc = (0x05<<4), /* Two 8-bit peripheral counters */ - XCL_TCSEL_BTC0PEC2_gc = (0x06<<4), /* One 8-bit timer/counter and two 4-bit peripheral counters */ -} XCL_TCSEL_t; - -/* Timer/Counter Mode */ -typedef enum XCL_TCMODE_enum -{ - XCL_TCMODE_NORMAL_gc = (0x00<<0), /* Normal mode with compare/period */ - XCL_TCMODE_CAPT_gc = (0x01<<0), /* Capture mode */ - XCL_TCMODE_PWM_gc = (0x02<<0), /* Single Slope PWM */ -} XCL_TCMODE_t; - -/* Compare Output Value Timer */ -typedef enum XCL_CMPEN_enum -{ - XCL_CMPEN_CLEAR_gc = (0x00<<5), /* Clear WG Output */ - XCL_CMPEN_SET_gc = (0x01<<5), /* Set WG Output */ -} XCL_CMPEN_t; - -/* Command Enable */ -typedef enum XCL_CMDEN_enum -{ - XCL_CMDEN_DISABLE_gc = (0x00<<6), /* Command Ignored */ - XCL_CMDEN_CMD0_gc = (0x01<<6), /* Command valid for timer/counter 0 */ - XCL_CMDEN_CMD1_gc = (0x02<<6), /* Command valid for timer/counter 1 */ - XCL_CMDEN_CMD01_gc = (0x03<<6), /* Command valid for both timer/counter 0 and 1 */ -} XCL_CMDEN_t; - -/* Timer/Counter Event Source Selection */ -typedef enum XCL_EVSRC_enum -{ - XCL_EVSRC_EVCH0_gc = (0x00<<0), /* Event channel 0 */ - XCL_EVSRC_EVCH1_gc = (0x01<<0), /* Event channel 1 */ - XCL_EVSRC_EVCH2_gc = (0x02<<0), /* Event channel 2 */ - XCL_EVSRC_EVCH3_gc = (0x03<<0), /* Event channel 3 */ - XCL_EVSRC_EVCH4_gc = (0x04<<0), /* Event channel 4 */ - XCL_EVSRC_EVCH5_gc = (0x05<<0), /* Event channel 5 */ - XCL_EVSRC_EVCH6_gc = (0x06<<0), /* Event channel 6 */ - XCL_EVSRC_EVCH7_gc = (0x07<<0), /* Event channel 7 */ -} XCL_EVSRC_t; - -/* Timer/Counter Event Action Selection */ -typedef enum XCL_EVACT_enum -{ - XCL_EVACT_INPUT_gc = (0x00<<5), /* Input Capture */ - XCL_EVACT_FREQ_gc = (0x01<<5), /* Frequency Capture */ - XCL_EVACT_PW_gc = (0x02<<5), /* Pulse Width Capture */ - XCL_EVACT_RESTART_gc = (0x03<<5), /* Restart timer/counter */ -} XCL_EVACT_t; - -/* Underflow Interrupt level */ -typedef enum XCL_UNF_INTLVL_enum -{ - XCL_UNF_INTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - XCL_UNF_INTLVL_LO_gc = (0x01<<2), /* Low Level */ - XCL_UNF_INTLVL_MED_gc = (0x02<<2), /* Medium Level */ - XCL_UNF_INTLVL_HI_gc = (0x03<<2), /* High Level */ -} XCL_UNF_INTLVL_t; - -/* Compare/Capture Interrupt level */ -typedef enum XCL_CC_INTLVL_enum -{ - XCL_CC_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - XCL_CC_INTLVL_LO_gc = (0x01<<0), /* Low Level */ - XCL_CC_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ - XCL_CC_INTLVL_HI_gc = (0x03<<0), /* High Level */ -} XCL_CC_INTLVL_t; - - -/* --------------------------------------------------------------------------- -TWI - Two-Wire Interface --------------------------------------------------------------------------- -*/ - -/* */ -typedef struct TWI_MASTER_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t STATUS; /* Status Register */ - register8_t BAUD; /* Baurd Rate Control Register */ - register8_t ADDR; /* Address Register */ - register8_t DATA; /* Data Register */ -} TWI_MASTER_t; - - -/* */ -typedef struct TWI_SLAVE_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t STATUS; /* Status Register */ - register8_t ADDR; /* Address Register */ - register8_t DATA; /* Data Register */ - register8_t ADDRMASK; /* Address Mask Register */ -} TWI_SLAVE_t; - - -/* */ -typedef struct TWI_TIMEOUT_struct -{ - register8_t TOS; /* Timeout Status Register */ - register8_t TOCONF; /* Timeout Configuration Register */ -} TWI_TIMEOUT_t; - - -/* Two-Wire Interface */ -typedef struct TWI_struct -{ - register8_t CTRL; /* TWI Common Control Register */ - TWI_MASTER_t MASTER; /* TWI master module */ - TWI_SLAVE_t SLAVE; /* TWI slave module */ - TWI_TIMEOUT_t TIMEOUT; /* TWI SMBUS timeout module */ -} TWI_t; - -/* SDA Hold Time */ -typedef enum TWI_SDAHOLD_enum -{ - TWI_SDAHOLD_OFF_gc = (0x00<<4), /* SDA Hold Time off */ - TWI_SDAHOLD_50NS_gc = (0x01<<4), /* SDA Hold Time 50 ns */ - TWI_SDAHOLD_300NS_gc = (0x02<<4), /* SDA Hold Time 300 ns */ - TWI_SDAHOLD_400NS_gc = (0x03<<4), /* SDA Hold Time 400 ns */ -} TWI_SDAHOLD_t; - -/* Master Interrupt Level */ -typedef enum TWI_MASTER_INTLVL_enum -{ - TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ - TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ -} TWI_MASTER_INTLVL_t; - -/* Inactive Timeout */ -typedef enum TWI_MASTER_TIMEOUT_enum -{ - TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ - TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ - TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ - TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ -} TWI_MASTER_TIMEOUT_t; - -/* Master Command */ -typedef enum TWI_MASTER_CMD_enum -{ - TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ - TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ - TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ -} TWI_MASTER_CMD_t; - -/* Master Bus State */ -typedef enum TWI_MASTER_BUSSTATE_enum -{ - TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ - TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ - TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ - TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ -} TWI_MASTER_BUSSTATE_t; - -/* Slave Interrupt Level */ -typedef enum TWI_SLAVE_INTLVL_enum -{ - TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ - TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ -} TWI_SLAVE_INTLVL_t; - -/* Slave Command */ -typedef enum TWI_SLAVE_CMD_enum -{ - TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ - TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ -} TWI_SLAVE_CMD_t; - -/* Master Timeout */ -typedef enum TWI_MASTER_TTIMEOUT_enum -{ - TWI_MASTER_TTIMEOUT_25MS_gc = (0x00<<0), /* 25 Milliseconds */ - TWI_MASTER_TTIMEOUT_24MS_gc = (0x01<<0), /* 24 Milliseconds */ - TWI_MASTER_TTIMEOUT_23MS_gc = (0x02<<0), /* 23 Milliseconds */ - TWI_MASTER_TTIMEOUT_22MS_gc = (0x03<<0), /* 22 Milliseconds */ - TWI_MASTER_TTIMEOUT_26MS_gc = (0x04<<0), /* 26 Milliseconds */ - TWI_MASTER_TTIMEOUT_27MS_gc = (0x05<<0), /* 27 Milliseconds */ - TWI_MASTER_TTIMEOUT_28MS_gc = (0x06<<0), /* 28 Milliseconds */ - TWI_MASTER_TTIMEOUT_29MS_gc = (0x07<<0), /* 29 Milliseconds */ -} TWI_MASTER_TTIMEOUT_t; - -/* Slave Ttimeout */ -typedef enum TWI_SLAVE_TTIMEOUT_enum -{ - TWI_SLAVE_TTIMEOUT_25MS_gc = (0x00<<5), /* 25 Milliseconds */ - TWI_SLAVE_TTIMEOUT_24MS_gc = (0x01<<5), /* 24 Milliseconds */ - TWI_SLAVE_TTIMEOUT_23MS_gc = (0x02<<5), /* 23 Milliseconds */ - TWI_SLAVE_TTIMEOUT_22MS_gc = (0x03<<5), /* 22 Milliseconds */ - TWI_SLAVE_TTIMEOUT_26MS_gc = (0x04<<5), /* 26 Milliseconds */ - TWI_SLAVE_TTIMEOUT_27MS_gc = (0x05<<5), /* 27 Milliseconds */ - TWI_SLAVE_TTIMEOUT_28MS_gc = (0x06<<5), /* 28 Milliseconds */ - TWI_SLAVE_TTIMEOUT_29MS_gc = (0x07<<5), /* 29 Milliseconds */ -} TWI_SLAVE_TTIMEOUT_t; - -/* Master/Slave Extend Timeout */ -typedef enum TWI_MASTER_TMSEXT_enum -{ - TWI_MASTER_TMSEXT_10MS25MS_gc = (0x00<<3), /* Tmext 10ms Tsext 25ms */ - TWI_MASTER_TMSEXT_9MS24MS_gc = (0x01<<3), /* Tmext 9ms Tsext 24ms */ - TWI_MASTER_TMSEXT_11MS26MS_gc = (0x02<<3), /* Tmext 11ms Tsext 26ms */ - TWI_MASTER_TMSEXT_12MS27MS_gc = (0x03<<3), /* Tmext 12ms Tsext 27ms */ -} TWI_MASTER_TMSEXT_t; - - -/* --------------------------------------------------------------------------- -PORT - Port Configuration --------------------------------------------------------------------------- -*/ - -/* I/O Ports */ -typedef struct PORT_struct -{ - register8_t DIR; /* I/O Port Data Direction */ - register8_t DIRSET; /* I/O Port Data Direction Set */ - register8_t DIRCLR; /* I/O Port Data Direction Clear */ - register8_t DIRTGL; /* I/O Port Data Direction Toggle */ - register8_t OUT; /* I/O Port Output */ - register8_t OUTSET; /* I/O Port Output Set */ - register8_t OUTCLR; /* I/O Port Output Clear */ - register8_t OUTTGL; /* I/O Port Output Toggle */ - register8_t IN; /* I/O port Input */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INTMASK; /* Port Interrupt Mask */ - register8_t reserved_0x0B; - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t REMAP; /* Pin Remap Register */ - register8_t reserved_0x0F; - register8_t PIN0CTRL; /* Pin 0 Control Register */ - register8_t PIN1CTRL; /* Pin 1 Control Register */ - register8_t PIN2CTRL; /* Pin 2 Control Register */ - register8_t PIN3CTRL; /* Pin 3 Control Register */ - register8_t PIN4CTRL; /* Pin 4 Control Register */ - register8_t PIN5CTRL; /* Pin 5 Control Register */ - register8_t PIN6CTRL; /* Pin 6 Control Register */ - register8_t PIN7CTRL; /* Pin 7 Control Register */ -} PORT_t; - -/* Port Interrupt Level */ -typedef enum PORT_INTLVL_enum -{ - PORT_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - PORT_INTLVL_LO_gc = (0x01<<0), /* Low Level */ - PORT_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ - PORT_INTLVL_HI_gc = (0x03<<0), /* High Level */ -} PORT_INTLVL_t; - -/* Output/Pull Configuration */ -typedef enum PORT_OPC_enum -{ - PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ - PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ - PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ - PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ - PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ - PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ - PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ - PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ -} PORT_OPC_t; - -/* Input/Sense Configuration */ -typedef enum PORT_ISC_enum -{ - PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ - PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ - PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ - PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ - PORT_ISC_FORCE_ENABLE_gc = (0x06<<0), /* Digital Input Buffer Forced Enable */ - PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ -} PORT_ISC_t; - - -/* --------------------------------------------------------------------------- -TC - 16-bit Timer/Counter With PWM --------------------------------------------------------------------------- -*/ - -/* 16-bit Timer/Counter 4 */ -typedef struct TC4_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t CTRLF; /* Control Register F */ - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G Set */ - register8_t CTRLHCLR; /* Control Register H Clear */ - register8_t CTRLHSET; /* Control Register H Set */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - _WORDREGISTER(CNT); /* Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CCA); /* Compare or Capture A */ - _WORDREGISTER(CCB); /* Compare or Capture B */ - _WORDREGISTER(CCC); /* Compare or Capture C */ - _WORDREGISTER(CCD); /* Compare or Capture D */ - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - _WORDREGISTER(PERBUF); /* Period Buffer */ - _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ - _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ - _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ - _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ -} TC4_t; - - -/* 16-bit Timer/Counter 5 */ -typedef struct TC5_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t CTRLF; /* Control Register F */ - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G Set */ - register8_t CTRLHCLR; /* Control Register H Clear */ - register8_t CTRLHSET; /* Control Register H Set */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - _WORDREGISTER(CNT); /* Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CCA); /* Compare or Capture A */ - _WORDREGISTER(CCB); /* Compare or Capture B */ - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t reserved_0x2E; - register8_t reserved_0x2F; - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - _WORDREGISTER(PERBUF); /* Period Buffer */ - _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ - _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ - register8_t reserved_0x3C; - register8_t reserved_0x3D; - register8_t reserved_0x3E; - register8_t reserved_0x3F; -} TC5_t; - -/* Clock Selection */ -typedef enum TC45_CLKSEL_enum -{ - TC45_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ - TC45_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ - TC45_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ - TC45_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ - TC45_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ - TC45_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ - TC45_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ - TC45_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ - TC45_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ - TC45_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ - TC45_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC45_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ - TC45_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ - TC45_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ - TC45_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ - TC45_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ -} TC45_CLKSEL_t; - -/* Byte Mode */ -typedef enum TC45_BYTEM_enum -{ - TC45_BYTEM_NORMAL_gc = (0x00<<6), /* 16-bit mode */ - TC45_BYTEM_BYTEMODE_gc = (0x01<<6), /* Timer/Counter Operating in Byte Mode Only */ -} TC45_BYTEM_t; - -/* Circular Enable Mode */ -typedef enum TC45_CIRCEN_enum -{ - TC45_CIRCEN_DISABLE_gc = (0x00<<4), /* Circular Buffer Disabled */ - TC45_CIRCEN_PER_gc = (0x01<<4), /* Circular Buffer Enabled on PER/PERBUF */ - TC45_CIRCEN_CCA_gc = (0x02<<4), /* Circular Buffer Enabled on CCA/CCABUF */ - TC45_CIRCEN_BOTH_gc = (0x03<<4), /* Circular Buffer Enabled on All Buffered Registers */ -} TC45_CIRCEN_t; - -/* Waveform Generation Mode */ -typedef enum TC45_WGMODE_enum -{ - TC45_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ - TC45_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ - TC45_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ - TC45_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ - TC45_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Both */ - TC45_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ -} TC45_WGMODE_t; - -/* Event Action */ -typedef enum TC45_EVACT_enum -{ - TC45_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ - TC45_EVACT_FMODE1_gc = (0x01<<5), /* Fault Mode 1 capture */ - TC45_EVACT_FMODE2_gc = (0x02<<5), /* Fault Mode 2 capture */ - TC45_EVACT_UPDOWN_gc = (0x03<<5), /* Up/down count */ - TC45_EVACT_QDEC_gc = (0x04<<5), /* Quadrature decode */ - TC45_EVACT_RESTART_gc = (0x05<<5), /* Restart */ - TC45_EVACT_PWF_gc = (0x06<<5), /* Pulse-width Capture */ -} TC45_EVACT_t; - -/* Event Selection */ -typedef enum TC45_EVSEL_enum -{ - TC45_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ - TC45_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ - TC45_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ - TC45_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC45_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ - TC45_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ - TC45_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ - TC45_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ - TC45_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ -} TC45_EVSEL_t; - -/* Compare or Capture Channel A Mode */ -typedef enum TC45_CCAMODE_enum -{ - TC45_CCAMODE_DISABLE_gc = (0x00<<0), /* Channel Disabled */ - TC45_CCAMODE_COMP_gc = (0x01<<0), /* Ouput Compare enabled */ - TC45_CCAMODE_CAPT_gc = (0x02<<0), /* Input Capture enabled */ - TC45_CCAMODE_BOTHCC_gc = (0x03<<0), /* Both Compare and Capture enabled */ -} TC45_CCAMODE_t; - -/* Compare or Capture Channel B Mode */ -typedef enum TC45_CCBMODE_enum -{ - TC45_CCBMODE_DISABLE_gc = (0x00<<2), /* Channel Disabled */ - TC45_CCBMODE_COMP_gc = (0x01<<2), /* Ouput Compare enabled */ - TC45_CCBMODE_CAPT_gc = (0x02<<2), /* Input Capture enabled */ - TC45_CCBMODE_BOTHCC_gc = (0x03<<2), /* Both Compare and Capture enabled */ -} TC45_CCBMODE_t; - -/* Compare or Capture Channel C Mode */ -typedef enum TC45_CCCMODE_enum -{ - TC45_CCCMODE_DISABLE_gc = (0x00<<4), /* Channel Disabled */ - TC45_CCCMODE_COMP_gc = (0x01<<4), /* Ouput Compare enabled */ - TC45_CCCMODE_CAPT_gc = (0x02<<4), /* Input Capture enabled */ - TC45_CCCMODE_BOTHCC_gc = (0x03<<4), /* Both Compare and Capture enabled */ -} TC45_CCCMODE_t; - -/* Compare or Capture Channel D Mode */ -typedef enum TC45_CCDMODE_enum -{ - TC45_CCDMODE_DISABLE_gc = (0x00<<6), /* Channel Disabled */ - TC45_CCDMODE_COMP_gc = (0x01<<6), /* Ouput Compare enabled */ - TC45_CCDMODE_CAPT_gc = (0x02<<6), /* Input Capture enabled */ - TC45_CCDMODE_BOTHCC_gc = (0x03<<6), /* Both Compare and Capture enabled */ -} TC45_CCDMODE_t; - -/* Compare or Capture Low Channel A Mode */ -typedef enum TC45_LCCAMODE_enum -{ - TC45_LCCAMODE_DISABLE_gc = (0x00<<0), /* Channel Disabled */ - TC45_LCCAMODE_COMP_gc = (0x01<<0), /* Ouput Compare enabled */ - TC45_LCCAMODE_CAPT_gc = (0x02<<0), /* Input Capture enabled */ - TC45_LCCAMODE_BOTHCC_gc = (0x03<<0), /* Both Compare and Capture enabled */ -} TC45_LCCAMODE_t; - -/* Compare or Capture Low Channel B Mode */ -typedef enum TC45_LCCBMODE_enum -{ - TC45_LCCBMODE_DISABLE_gc = (0x00<<2), /* Channel Disabled */ - TC45_LCCBMODE_COMP_gc = (0x01<<2), /* Ouput Compare enabled */ - TC45_LCCBMODE_CAPT_gc = (0x02<<2), /* Input Capture enabled */ - TC45_LCCBMODE_BOTHCC_gc = (0x03<<2), /* Both Compare and Capture enabled */ -} TC45_LCCBMODE_t; - -/* Compare or Capture Low Channel C Mode */ -typedef enum TC45_LCCCMODE_enum -{ - TC45_LCCCMODE_DISABLE_gc = (0x00<<4), /* Channel Disabled */ - TC45_LCCCMODE_COMP_gc = (0x01<<4), /* Ouput Compare enabled */ - TC45_LCCCMODE_CAPT_gc = (0x02<<4), /* Input Capture enabled */ - TC45_LCCCMODE_BOTHCC_gc = (0x03<<4), /* Both Compare and Capture enabled */ -} TC45_LCCCMODE_t; - -/* Compare or Capture Low Channel D Mode */ -typedef enum TC45_LCCDMODE_enum -{ - TC45_LCCDMODE_DISABLE_gc = (0x00<<6), /* Channel Disabled */ - TC45_LCCDMODE_COMP_gc = (0x01<<6), /* Ouput Compare enabled */ - TC45_LCCDMODE_CAPT_gc = (0x02<<6), /* Input Capture enabled */ - TC45_LCCDMODE_BOTHCC_gc = (0x03<<6), /* Both Compare and Capture enabled */ -} TC45_LCCDMODE_t; - -/* Compare or Capture High Channel A Mode */ -typedef enum TC45_HCCAMODE_enum -{ - TC45_HCCAMODE_DISABLE_gc = (0x00<<0), /* Channel Disabled */ - TC45_HCCAMODE_COMP_gc = (0x01<<0), /* Ouput Compare enabled */ - TC45_HCCAMODE_CAPT_gc = (0x02<<0), /* Input Capture enabled */ - TC45_HCCAMODE_BOTHCC_gc = (0x03<<0), /* Both Compare and Capture enabled */ -} TC45_HCCAMODE_t; - -/* Compare or Capture High Channel B Mode */ -typedef enum TC45_HCCBMODE_enum -{ - TC45_HCCBMODE_DISABLE_gc = (0x00<<2), /* Channel Disabled */ - TC45_HCCBMODE_COMP_gc = (0x01<<2), /* Ouput Compare enabled */ - TC45_HCCBMODE_CAPT_gc = (0x02<<2), /* Input Capture enabled */ - TC45_HCCBMODE_BOTHCC_gc = (0x03<<2), /* Both Compare and Capture enabled */ -} TC45_HCCBMODE_t; - -/* Compare or Capture High Channel C Mode */ -typedef enum TC45_HCCCMODE_enum -{ - TC45_HCCCMODE_DISABLE_gc = (0x00<<4), /* Channel Disabled */ - TC45_HCCCMODE_COMP_gc = (0x01<<4), /* Ouput Compare enabled */ - TC45_HCCCMODE_CAPT_gc = (0x02<<4), /* Input Capture enabled */ - TC45_HCCCMODE_BOTHCC_gc = (0x03<<4), /* Both Compare and Capture enabled */ -} TC45_HCCCMODE_t; - -/* Compare or Capture High Channel D Mode */ -typedef enum TC45_HCCDMODE_enum -{ - TC45_HCCDMODE_DISABLE_gc = (0x00<<6), /* Channel Disabled */ - TC45_HCCDMODE_COMP_gc = (0x01<<6), /* Ouput Compare enabled */ - TC45_HCCDMODE_CAPT_gc = (0x02<<6), /* Input Capture enabled */ - TC45_HCCDMODE_BOTHCC_gc = (0x03<<6), /* Both Compare and Capture enabled */ -} TC45_HCCDMODE_t; - -/* Timer Trigger Restart Interrupt Level */ -typedef enum TC45_TRGINTLVL_enum -{ - TC45_TRGINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - TC45_TRGINTLVL_LO_gc = (0x01<<4), /* Low Level */ - TC45_TRGINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - TC45_TRGINTLVL_HI_gc = (0x03<<4), /* High Level */ -} TC45_TRGINTLVL_t; - -/* Error Interrupt Level */ -typedef enum TC45_ERRINTLVL_enum -{ - TC45_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC45_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC45_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC45_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC45_ERRINTLVL_t; - -/* Overflow Interrupt Level */ -typedef enum TC45_OVFINTLVL_enum -{ - TC45_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC45_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC45_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC45_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC45_OVFINTLVL_t; - -/* Compare or Capture Channel A Interrupt Level */ -typedef enum TC45_CCAINTLVL_enum -{ - TC45_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC45_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC45_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC45_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC45_CCAINTLVL_t; - -/* Compare or Capture Channel B Interrupt Level */ -typedef enum TC45_CCBINTLVL_enum -{ - TC45_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC45_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC45_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC45_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC45_CCBINTLVL_t; - -/* Compare or Capture Channel C Interrupt Level */ -typedef enum TC45_CCCINTLVL_enum -{ - TC45_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - TC45_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - TC45_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - TC45_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} TC45_CCCINTLVL_t; - -/* Compare or Capture Channel D Interrupt Level */ -typedef enum TC45_CCDINTLVL_enum -{ - TC45_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TC45_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ - TC45_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TC45_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ -} TC45_CCDINTLVL_t; - -/* Compare or Capture Low Channel A Interrupt Level */ -typedef enum TC45_LCCAINTLVL_enum -{ - TC45_LCCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC45_LCCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC45_LCCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC45_LCCAINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC45_LCCAINTLVL_t; - -/* Compare or Capture Low Channel B Interrupt Level */ -typedef enum TC45_LCCBINTLVL_enum -{ - TC45_LCCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC45_LCCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC45_LCCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC45_LCCBINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC45_LCCBINTLVL_t; - -/* Compare or Capture Low Channel C Interrupt Level */ -typedef enum TC45_LCCCINTLVL_enum -{ - TC45_LCCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - TC45_LCCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - TC45_LCCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - TC45_LCCCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} TC45_LCCCINTLVL_t; - -/* Compare or Capture Low Channel D Interrupt Level */ -typedef enum TC45_LCCDINTLVL_enum -{ - TC45_LCCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TC45_LCCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ - TC45_LCCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TC45_LCCDINTLVL_HI_gc = (0x03<<6), /* High Level */ -} TC45_LCCDINTLVL_t; - -/* Timer/Counter Command */ -typedef enum TC45_CMD_enum -{ - TC45_CMD_NONE_gc = (0x00<<2), /* No Command */ - TC45_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ - TC45_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ - TC45_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -} TC45_CMD_t; - - -/* --------------------------------------------------------------------------- -FAULT - Fault Extension --------------------------------------------------------------------------- -*/ - -/* Fault Extension */ -typedef struct FAULT_struct -{ - register8_t CTRLA; /* Control A Register */ - register8_t CTRLB; /* Control B Register */ - register8_t CTRLC; /* Control C Register */ - register8_t CTRLD; /* Control D Register */ - register8_t CTRLE; /* Control E Register */ - register8_t STATUS; /* Status Register */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G set */ -} FAULT_t; - -/* Ramp Mode Selection */ -typedef enum FAULT_RAMP_enum -{ - FAULT_RAMP_RAMP1_gc = (0x00<<6), /* Normal Mode */ - FAULT_RAMP_RAMP2_gc = (0x02<<6), /* RAMP2 Mode */ -} FAULT_RAMP_t; - -/* Fault E Input Source Selection */ -typedef enum FAULT_SRCE_enum -{ - FAULT_SRCE_DISABLE_gc = (0x00<<0), /* Fault Protection Disabled */ - FAULT_SRCE_CHN_gc = (0x01<<0), /* Event Channel n */ - FAULT_SRCE_CHN1_gc = (0x02<<0), /* Event Channel n+1 */ - FAULT_SRCE_CHN2_gc = (0x03<<0), /* Event Channel n+2 */ -} FAULT_SRCE_t; - -/* Fault A Halt Action Selection */ -typedef enum FAULT_HALTA_enum -{ - FAULT_HALTA_DISABLE_gc = (0x00<<5), /* Halt Action Disabled */ - FAULT_HALTA_HW_gc = (0x01<<5), /* Hardware Halt Action */ - FAULT_HALTA_SW_gc = (0x02<<5), /* Software Halt Action */ -} FAULT_HALTA_t; - -/* Fault A Source Selection */ -typedef enum FAULT_SRCA_enum -{ - FAULT_SRCA_DISABLE_gc = (0x00<<0), /* Fault A Disabled */ - FAULT_SRCA_CHN_gc = (0x01<<0), /* Event Channel n */ - FAULT_SRCA_CHN1_gc = (0x02<<0), /* Event Channel n+1 */ - FAULT_SRCA_LINK_gc = (0x03<<0), /* Fault A linked to Fault B State from previous cycle */ -} FAULT_SRCA_t; - -/* Fault B Halt Action Selection */ -typedef enum FAULT_HALTB_enum -{ - FAULT_HALTB_DISABLE_gc = (0x00<<5), /* Halt Action Disabled */ - FAULT_HALTB_HW_gc = (0x01<<5), /* Hardware Halt Action */ - FAULT_HALTB_SW_gc = (0x02<<5), /* Software Halt Action */ -} FAULT_HALTB_t; - -/* Fault B Source Selection */ -typedef enum FAULT_SRCB_enum -{ - FAULT_SRCB_DISABLE_gc = (0x00<<0), /* Fault B disabled */ - FAULT_SRCB_CHN_gc = (0x01<<0), /* Event Channel n */ - FAULT_SRCB_CHN1_gc = (0x02<<0), /* Event Channel n+1 */ - FAULT_SRCB_LINK_gc = (0x03<<0), /* Fault B linked to Fault A State from previous cycle */ -} FAULT_SRCB_t; - -/* Channel index Command */ -typedef enum FAULT_IDXCMD_enum -{ - FAULT_IDXCMD_DISABLE_gc = (0x00<<3), /* Command Disabled */ - FAULT_IDXCMD_SET_gc = (0x01<<3), /* Force Cycle B in Next Cycle */ - FAULT_IDXCMD_CLEAR_gc = (0x02<<3), /* Force Cycle A in Next Cycle */ - FAULT_IDXCMD_HOLD_gc = (0x03<<3), /* Hold Current Cycle Index in Next Cycle */ -} FAULT_IDXCMD_t; - - -/* --------------------------------------------------------------------------- -WEX - Waveform Extension --------------------------------------------------------------------------- -*/ - -/* Waveform Extension */ -typedef struct WEX_struct -{ - register8_t CTRL; /* Control Register */ - register8_t DTBOTH; /* Dead-time Concurrent Write to Both Sides Register */ - register8_t DTLS; /* Dead-time Low Side Register */ - register8_t DTHS; /* Dead-time High Side Register */ - register8_t STATUSCLR; /* Status Clear Register */ - register8_t STATUSSET; /* Status Set Register */ - register8_t SWAP; /* Swap Register */ - register8_t PGO; /* Pattern Generation Override Register */ - register8_t PGV; /* Pattern Generation Value Register */ - register8_t reserved_0x09; - register8_t SWAPBUF; /* Dead Time Low Side Buffer */ - register8_t PGOBUF; /* Pattern Generation Overwrite Buffer Register */ - register8_t PGVBUF; /* Pattern Generation Value Buffer Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t OUTOVDIS; /* Output Override Disable Register */ -} WEX_t; - -/* Output Matrix Mode */ -typedef enum WEX_OTMX_enum -{ - WEX_OTMX_DEFAULT_gc = (0x00<<4), /* Default Ouput Matrix Mode */ - WEX_OTMX_FIRST_gc = (0x01<<4), /* First Output matrix Mode */ - WEX_OTMX_SECOND_gc = (0x02<<4), /* Second Output matrix Mode */ - WEX_OTMX_THIRD_gc = (0x03<<4), /* Third Output matrix Mode */ - WEX_OTMX_FOURTH_gc = (0x04<<4), /* Fourth Output matrix Mode */ -} WEX_OTMX_t; - - -/* --------------------------------------------------------------------------- -HIRES - High-Resolution Extension --------------------------------------------------------------------------- -*/ - -/* High-Resolution Extension */ -typedef struct HIRES_struct -{ - register8_t CTRLA; /* Control Register A */ -} HIRES_t; - -/* High Resolution Plus Mode */ -typedef enum HIRES_HRPLUS_enum -{ - HIRES_HRPLUS_NONE_gc = (0x00<<2), /* No Hi-Res Plus */ - HIRES_HRPLUS_HRP4_gc = (0x01<<2), /* Hi-Res Plus enabled on Timer 4 */ - HIRES_HRPLUS_HRP5_gc = (0x02<<2), /* Hi-Res Plus enabled on Timer 5 */ - HIRES_HRPLUS_BOTH_gc = (0x03<<2), /* Hi-Res Plus enabled on Timer 4 and 5 */ -} HIRES_HRPLUS_t; - -/* High Resolution Mode */ -typedef enum HIRES_HREN_enum -{ - HIRES_HREN_NONE_gc = (0x00<<0), /* No Hi-Res */ - HIRES_HREN_HRP4_gc = (0x01<<0), /* Hi-Res enabled on Timer 4 */ - HIRES_HREN_HRP5_gc = (0x02<<0), /* Hi-Res enabled on Timer 5 */ - HIRES_HREN_BOTH_gc = (0x03<<0), /* Hi-Res enabled on Timer 4 and 5 */ -} HIRES_HREN_t; - - -/* --------------------------------------------------------------------------- -USART - Universal Asynchronous Receiver-Transmitter --------------------------------------------------------------------------- -*/ - -/* Universal Synchronous/Asynchronous Receiver/Transmitter */ -typedef struct USART_struct -{ - register8_t DATA; /* Data Register */ - register8_t STATUS; /* Status Register */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t CTRLD; /* Control Register D */ - register8_t BAUDCTRLA; /* Baud Rate Control Register A */ - register8_t BAUDCTRLB; /* Baud Rate Control Register B */ -} USART_t; - -/* Receive Start Interrupt level */ -typedef enum USART_RXSINTLVL_enum -{ - USART_RXSINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - USART_RXSINTLVL_LO_gc = (0x01<<0), /* Low Level */ - USART_RXSINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - USART_RXSINTLVL_HI_gc = (0x03<<0), /* High Level */ -} USART_RXSINTLVL_t; - -/* Receive Complete Interrupt level */ -typedef enum USART_RXCINTLVL_enum -{ - USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} USART_RXCINTLVL_t; - -/* Transmit Complete Interrupt level */ -typedef enum USART_TXCINTLVL_enum -{ - USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ - USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ -} USART_TXCINTLVL_t; - -/* Data Register Empty Interrupt level */ -typedef enum USART_DREINTLVL_enum -{ - USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ - USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ -} USART_DREINTLVL_t; - -/* Character Size */ -typedef enum USART_CHSIZE_enum -{ - USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ - USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ - USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ - USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ - USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ -} USART_CHSIZE_t; - -/* Communication Mode */ -typedef enum USART_CMODE_enum -{ - USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ - USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ - USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ - USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ -} USART_CMODE_t; - -/* Parity Mode */ -typedef enum USART_PMODE_enum -{ - USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ - USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ - USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ -} USART_PMODE_t; - -/* Encoding and Decoding Type */ -typedef enum USART_DECTYPE_enum -{ - USART_DECTYPE_DATA_gc = (0x00<<4), /* DATA Field Encoding */ - USART_DECTYPE_SDATA_gc = (0x02<<4), /* Start and Data Fields Encoding */ - USART_DECTYPE_NOTSDATA_gc = (0x03<<4), /* Start and Data Fields Encoding, with invertion in START field */ -} USART_DECTYPE_t; - -/* XCL LUT Action */ -typedef enum USART_LUTACT_enum -{ - USART_LUTACT_OFF_gc = (0x00<<2), /* Standard Frame Configuration */ - USART_LUTACT_RX_gc = (0x01<<2), /* Receiver Decoding Enabled */ - USART_LUTACT_TX_gc = (0x02<<2), /* Transmitter Encoding Enabled */ - USART_LUTACT_BOTH_gc = (0x03<<2), /* Both Encoding and Decoding Enabled */ -} USART_LUTACT_t; - -/* XCL Peripheral Counter Action */ -typedef enum USART_PECACT_enum -{ - USART_PECACT_OFF_gc = (0x00<<0), /* Standard Mode */ - USART_PECACT_PEC0_gc = (0x01<<0), /* Variable Data Lenght in Reception */ - USART_PECACT_PEC1_gc = (0x02<<0), /* Variable Data Lenght in Transmission */ - USART_PECACT_PERC01_gc = (0x03<<0), /* Variable Data Lenght in both Reception and Transmission */ -} USART_PECACT_t; - - -/* --------------------------------------------------------------------------- -SPI - Serial Peripheral Interface --------------------------------------------------------------------------- -*/ - -/* Serial Peripheral Interface with Buffer Modes */ -typedef struct SPI_struct -{ - register8_t CTRL; /* Control Register */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t STATUS; /* Status Register */ - register8_t DATA; /* Data Register */ - register8_t CTRLB; /* Control Register B */ -} SPI_t; - -/* SPI Mode */ -typedef enum SPI_MODE_enum -{ - SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0, base clock at "0", sampling on leading edge (rising) & set-up on trailling edge (falling). */ - SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1, base clock at "0", set-up on leading edge (rising) & sampling on trailling edge (falling). */ - SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2, base clock at "1", sampling on leading edge (falling) & set-up on trailling edge (rising). */ - SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3, base clock at "1", set-up on leading edge (falling) & sampling on trailling edge (rising). */ -} SPI_MODE_t; - -/* Prescaler setting */ -typedef enum SPI_PRESCALER_enum -{ - SPI_PRESCALER_DIV4_gc = (0x00<<0), /* If CLK2X=1 CLKper/2, else (CLK2X=0) CLKper/4. */ - SPI_PRESCALER_DIV16_gc = (0x01<<0), /* If CLK2X=1 CLKper/8, else (CLK2X=0) CLKper/16. */ - SPI_PRESCALER_DIV64_gc = (0x02<<0), /* If CLK2X=1 CLKper/32, else (CLK2X=0) CLKper/64. */ - SPI_PRESCALER_DIV128_gc = (0x03<<0), /* If CLK2X=1 CLKper/64, else (CLK2X=0) CLKper/128. */ -} SPI_PRESCALER_t; - -/* Interrupt level */ -typedef enum SPI_INTLVL_enum -{ - SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ - SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ - SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ -} SPI_INTLVL_t; - -/* Buffer Modes */ -typedef enum SPI_BUFMODE_enum -{ - SPI_BUFMODE_OFF_gc = (0x00<<6), /* SPI Unbuffered Mode */ - SPI_BUFMODE_BUFMODE1_gc = (0x02<<6), /* Buffer Mode 1 (with dummy byte) */ - SPI_BUFMODE_BUFMODE2_gc = (0x03<<6), /* Buffer Mode 2 (no dummy byte) */ -} SPI_BUFMODE_t; - - -/* --------------------------------------------------------------------------- -IRCOM - IR Communication Module --------------------------------------------------------------------------- -*/ - -/* IR Communication Module */ -typedef struct IRCOM_struct -{ - register8_t CTRL; /* Control Register */ - register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ - register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ -} IRCOM_t; - -/* Event channel selection */ -typedef enum IRDA_EVSEL_enum -{ - IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ - IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ - IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ - IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ - IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ - IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ - IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ - IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ - IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ -} IRDA_EVSEL_t; - - -/* --------------------------------------------------------------------------- -FUSE - Fuses and Lockbits --------------------------------------------------------------------------- -*/ - -/* Lock Bits */ -typedef struct NVM_LOCKBITS_struct -{ - register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ -} NVM_LOCKBITS_t; - - -/* Fuses */ -typedef struct NVM_FUSES_struct -{ - register8_t reserved_0x00; - register8_t FUSEBYTE1; /* Watchdog Configuration */ - register8_t FUSEBYTE2; /* Reset Configuration */ - register8_t reserved_0x03; - register8_t FUSEBYTE4; /* Start-up Configuration */ - register8_t FUSEBYTE5; /* EESAVE and BOD Level */ - register8_t FUSEBYTE6; /* Fault State */ -} NVM_FUSES_t; - -/* Boot lock bits - boot setcion */ -typedef enum FUSE_BLBB_enum -{ - FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ - FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ - FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ - FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -} FUSE_BLBB_t; - -/* Boot lock bits - application section */ -typedef enum FUSE_BLBA_enum -{ - FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ - FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ - FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ - FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -} FUSE_BLBA_t; - -/* Boot lock bits - application table section */ -typedef enum FUSE_BLBAT_enum -{ - FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ - FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ - FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ - FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -} FUSE_BLBAT_t; - -/* Lock bits */ -typedef enum FUSE_LB_enum -{ - FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ - FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ - FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -} FUSE_LB_t; - -/* Boot Loader Section Reset Vector */ -typedef enum BOOTRST_enum -{ - BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ - BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ -} BOOTRST_t; - -/* BOD operation */ -typedef enum BOD_enum -{ - BOD_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ - BOD_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ - BOD_DISABLED_gc = (0x03<<4), /* BOD Disabled */ -} BOD_t; - -/* Watchdog (Window) Timeout Period */ -typedef enum WD_enum -{ - WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ - WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ - WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ - WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ - WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ - WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ - WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ - WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ - WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ - WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ - WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ -} WD_t; - -/* Start-up Time */ -typedef enum SUT_enum -{ - SUT_0MS_gc = (0x03<<2), /* 0 ms */ - SUT_4MS_gc = (0x01<<2), /* 4 ms */ - SUT_64MS_gc = (0x00<<2), /* 64 ms */ -} SUT_t; - -/* Brownout Detection Voltage Level */ -typedef enum BODLVL_enum -{ - BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ - BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ - BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ - BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ - BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ - BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ - BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ - BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ -} BODLVL_t; - - -/* --------------------------------------------------------------------------- -SIGROW - Signature Row --------------------------------------------------------------------------- -*/ - -/* Production Signatures */ -typedef struct NVM_PROD_SIGNATURES_struct -{ - register8_t RCOSC8M; /* RCOSC 8MHz Calibration Value */ - register8_t reserved_0x01; - register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ - register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ - register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ - register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ - register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ - register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ - register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ - register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t WAFNUM; /* Wafer Number */ - register8_t reserved_0x11; - register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ - register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ - register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ - register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t ROOMTEMP; /* Temperature corresponds to TEMPSENSE3/2 */ - register8_t HOTTEMP; /* Temperature corresponds to TEMPSENSE1/0 */ - register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ - register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - register8_t reserved_0x26; - register8_t reserved_0x27; - register8_t ACACURRCAL; /* ACA Current Calibration Byte */ - register8_t reserved_0x29; - register8_t reserved_0x2A; - register8_t reserved_0x2B; - register8_t TEMPSENSE2; /* Temperature Sensor Calibration Byte 2 */ - register8_t TEMPSENSE3; /* Temperature Sensor Calibration Byte 3 */ - register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ - register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ - register8_t DACA0OFFCAL; /* DACA0 Calibration Byte 0 */ - register8_t DACA0GAINCAL; /* DACA0 Calibration Byte 1 */ - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t DACA1OFFCAL; /* DACA1 Calibration Byte 0 */ - register8_t DACA1GAINCAL; /* DACA1 Calibration Byte 1 */ - register8_t reserved_0x36; - register8_t reserved_0x37; - register8_t reserved_0x38; - register8_t reserved_0x39; - register8_t reserved_0x3A; - register8_t reserved_0x3B; - register8_t reserved_0x3C; - register8_t reserved_0x3D; - register8_t reserved_0x3E; - register8_t reserved_0x3F; -} NVM_PROD_SIGNATURES_t; - -/* -========================================================================== -IO Module Instances. Mapped to memory. -========================================================================== -*/ - -#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ -#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ -#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ -#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ -#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ -#define CLK (*(CLK_t *) 0x0040) /* Clock System */ -#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ -#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ -#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ -#define PR (*(PR_t *) 0x0070) /* Power Reduction */ -#define RST (*(RST_t *) 0x0078) /* Reset */ -#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ -#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ -#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ -#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ -#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ -#define EDMA (*(EDMA_t *) 0x0100) /* Enhanced DMA Controller */ -#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ -#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ -#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ -#define DACA (*(DAC_t *) 0x0300) /* Digital-to-Analog Converter */ -#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ -#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ -#define XCL (*(XCL_t *) 0x0460) /* XMEGA Custom Logic */ -#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ -#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ -#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ -#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ -#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ -#define TCC4 (*(TC4_t *) 0x0800) /* 16-bit Timer/Counter 4 */ -#define TCC5 (*(TC5_t *) 0x0840) /* 16-bit Timer/Counter 5 */ -#define FAULTC4 (*(FAULT_t *) 0x0880) /* Fault Extension */ -#define FAULTC5 (*(FAULT_t *) 0x0890) /* Fault Extension */ -#define WEXC (*(WEX_t *) 0x08A0) /* Waveform Extension */ -#define HIRESC (*(HIRES_t *) 0x08B0) /* High-Resolution Extension */ -#define USARTC0 (*(USART_t *) 0x08C0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define SPIC (*(SPI_t *) 0x08E0) /* Serial Peripheral Interface with Buffer Modes */ -#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ -#define TCD5 (*(TC5_t *) 0x0940) /* 16-bit Timer/Counter 5 */ -#define USARTD0 (*(USART_t *) 0x09C0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ - - -#endif /* !defined (__ASSEMBLER__) */ - - -/* ========== Flattened fully qualified IO register names ========== */ - -/* GPIO - General Purpose IO Registers */ -#define GPIO_GPIOR0 _SFR_MEM8(0x0000) -#define GPIO_GPIOR1 _SFR_MEM8(0x0001) -#define GPIO_GPIOR2 _SFR_MEM8(0x0002) -#define GPIO_GPIOR3 _SFR_MEM8(0x0003) - -/* Deprecated */ -#define GPIO_GPIO0 _SFR_MEM8(0x0000) -#define GPIO_GPIO1 _SFR_MEM8(0x0001) -#define GPIO_GPIO2 _SFR_MEM8(0x0002) -#define GPIO_GPIO3 _SFR_MEM8(0x0003) - -/* NVM_FUSES - Fuses */ -#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) -#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) -#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) -#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) -#define FUSE_FUSEBYTE6 _SFR_MEM8(0x0006) - -/* NVM_LOCKBITS - Lock Bits */ -#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) - -/* NVM_PROD_SIGNATURES - Production Signatures */ -#define PRODSIGNATURES_RCOSC8M _SFR_MEM8(0x0000) -#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) -#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) -#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) -#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) -#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) -#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) -#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) -#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) -#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) -#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) -#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) -#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) -#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) -#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) -#define PRODSIGNATURES_ROOMTEMP _SFR_MEM8(0x001E) -#define PRODSIGNATURES_HOTTEMP _SFR_MEM8(0x001F) -#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) -#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) -#define PRODSIGNATURES_ACACURRCAL _SFR_MEM8(0x0028) -#define PRODSIGNATURES_TEMPSENSE2 _SFR_MEM8(0x002C) -#define PRODSIGNATURES_TEMPSENSE3 _SFR_MEM8(0x002D) -#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) -#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) -#define PRODSIGNATURES_DACA0OFFCAL _SFR_MEM8(0x0030) -#define PRODSIGNATURES_DACA0GAINCAL _SFR_MEM8(0x0031) -#define PRODSIGNATURES_DACA1OFFCAL _SFR_MEM8(0x0034) -#define PRODSIGNATURES_DACA1GAINCAL _SFR_MEM8(0x0035) - -/* VPORT - Virtual Port */ -#define VPORT0_DIR _SFR_MEM8(0x0010) -#define VPORT0_OUT _SFR_MEM8(0x0011) -#define VPORT0_IN _SFR_MEM8(0x0012) -#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) - -/* VPORT - Virtual Port */ -#define VPORT1_DIR _SFR_MEM8(0x0014) -#define VPORT1_OUT _SFR_MEM8(0x0015) -#define VPORT1_IN _SFR_MEM8(0x0016) -#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) - -/* VPORT - Virtual Port */ -#define VPORT2_DIR _SFR_MEM8(0x0018) -#define VPORT2_OUT _SFR_MEM8(0x0019) -#define VPORT2_IN _SFR_MEM8(0x001A) -#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) - -/* VPORT - Virtual Port */ -#define VPORT3_DIR _SFR_MEM8(0x001C) -#define VPORT3_OUT _SFR_MEM8(0x001D) -#define VPORT3_IN _SFR_MEM8(0x001E) -#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) - -/* OCD - On-Chip Debug System */ -#define OCD_OCDR0 _SFR_MEM8(0x002E) -#define OCD_OCDR1 _SFR_MEM8(0x002F) - -/* CPU - CPU registers */ -#define CPU_CCP _SFR_MEM8(0x0034) -#define CPU_RAMPD _SFR_MEM8(0x0038) -#define CPU_RAMPX _SFR_MEM8(0x0039) -#define CPU_RAMPY _SFR_MEM8(0x003A) -#define CPU_RAMPZ _SFR_MEM8(0x003B) -#define CPU_EIND _SFR_MEM8(0x003C) -#define CPU_SPL _SFR_MEM8(0x003D) -#define CPU_SPH _SFR_MEM8(0x003E) -#define CPU_SREG _SFR_MEM8(0x003F) - -/* CLK - Clock System */ -#define CLK_CTRL _SFR_MEM8(0x0040) -#define CLK_PSCTRL _SFR_MEM8(0x0041) -#define CLK_LOCK _SFR_MEM8(0x0042) -#define CLK_RTCCTRL _SFR_MEM8(0x0043) - -/* SLEEP - Sleep Controller */ -#define SLEEP_CTRL _SFR_MEM8(0x0048) - -/* OSC - Oscillator */ -#define OSC_CTRL _SFR_MEM8(0x0050) -#define OSC_STATUS _SFR_MEM8(0x0051) -#define OSC_XOSCCTRL _SFR_MEM8(0x0052) -#define OSC_XOSCFAIL _SFR_MEM8(0x0053) -#define OSC_RC32KCAL _SFR_MEM8(0x0054) -#define OSC_PLLCTRL _SFR_MEM8(0x0055) -#define OSC_DFLLCTRL _SFR_MEM8(0x0056) -#define OSC_RC8MCAL _SFR_MEM8(0x0057) - -/* DFLL - DFLL */ -#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) -#define DFLLRC32M_CALA _SFR_MEM8(0x0062) -#define DFLLRC32M_CALB _SFR_MEM8(0x0063) -#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) -#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) -#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) - -/* PR - Power Reduction */ -#define PR_PRGEN _SFR_MEM8(0x0070) -#define PR_PRPA _SFR_MEM8(0x0071) -#define PR_PRPC _SFR_MEM8(0x0073) -#define PR_PRPD _SFR_MEM8(0x0074) - -/* RST - Reset */ -#define RST_STATUS _SFR_MEM8(0x0078) -#define RST_CTRL _SFR_MEM8(0x0079) - -/* WDT - Watch-Dog Timer */ -#define WDT_CTRL _SFR_MEM8(0x0080) -#define WDT_WINCTRL _SFR_MEM8(0x0081) -#define WDT_STATUS _SFR_MEM8(0x0082) - -/* MCU - MCU Control */ -#define MCU_DEVID0 _SFR_MEM8(0x0090) -#define MCU_DEVID1 _SFR_MEM8(0x0091) -#define MCU_DEVID2 _SFR_MEM8(0x0092) -#define MCU_REVID _SFR_MEM8(0x0093) -#define MCU_ANAINIT _SFR_MEM8(0x0097) -#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) -#define MCU_WEXLOCK _SFR_MEM8(0x0099) -#define MCU_FAULTLOCK _SFR_MEM8(0x009A) - -/* PMIC - Programmable Multi-level Interrupt Controller */ -#define PMIC_STATUS _SFR_MEM8(0x00A0) -#define PMIC_INTPRI _SFR_MEM8(0x00A1) -#define PMIC_CTRL _SFR_MEM8(0x00A2) - -/* PORTCFG - I/O port Configuration */ -#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) -#define PORTCFG_CLKOUT _SFR_MEM8(0x00B4) -#define PORTCFG_ACEVOUT _SFR_MEM8(0x00B6) -#define PORTCFG_SRLCTRL _SFR_MEM8(0x00B7) - -/* CRC - Cyclic Redundancy Checker */ -#define CRC_CTRL _SFR_MEM8(0x00D0) -#define CRC_STATUS _SFR_MEM8(0x00D1) -#define CRC_DATAIN _SFR_MEM8(0x00D3) -#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) -#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) -#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) -#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) - -/* EDMA - Enhanced DMA Controller */ -#define EDMA_CTRL _SFR_MEM8(0x0100) -#define EDMA_INTFLAGS _SFR_MEM8(0x0103) -#define EDMA_STATUS _SFR_MEM8(0x0104) -#define EDMA_TEMP _SFR_MEM8(0x0106) -#define EDMA_CH0_CTRLA _SFR_MEM8(0x0110) -#define EDMA_CH0_CTRLB _SFR_MEM8(0x0111) -#define EDMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) -#define EDMA_CH0_DESTADDRCTRL _SFR_MEM8(0x0113) -#define EDMA_CH0_TRIGSRC _SFR_MEM8(0x0114) -#define EDMA_CH0_TRFCNT _SFR_MEM16(0x0116) -#define EDMA_CH0_ADDR _SFR_MEM16(0x0118) -#define EDMA_CH0_DESTADDR _SFR_MEM16(0x011C) -#define EDMA_CH1_CTRLA _SFR_MEM8(0x0120) -#define EDMA_CH1_CTRLB _SFR_MEM8(0x0121) -#define EDMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) -#define EDMA_CH1_DESTADDRCTRL _SFR_MEM8(0x0123) -#define EDMA_CH1_TRIGSRC _SFR_MEM8(0x0124) -#define EDMA_CH1_TRFCNT _SFR_MEM16(0x0126) -#define EDMA_CH1_ADDR _SFR_MEM16(0x0128) -#define EDMA_CH1_DESTADDR _SFR_MEM16(0x012C) -#define EDMA_CH2_CTRLA _SFR_MEM8(0x0130) -#define EDMA_CH2_CTRLB _SFR_MEM8(0x0131) -#define EDMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) -#define EDMA_CH2_DESTADDRCTRL _SFR_MEM8(0x0133) -#define EDMA_CH2_TRIGSRC _SFR_MEM8(0x0134) -#define EDMA_CH2_TRFCNT _SFR_MEM16(0x0136) -#define EDMA_CH2_ADDR _SFR_MEM16(0x0138) -#define EDMA_CH2_DESTADDR _SFR_MEM16(0x013C) -#define EDMA_CH3_CTRLA _SFR_MEM8(0x0140) -#define EDMA_CH3_CTRLB _SFR_MEM8(0x0141) -#define EDMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) -#define EDMA_CH3_DESTADDRCTRL _SFR_MEM8(0x0143) -#define EDMA_CH3_TRIGSRC _SFR_MEM8(0x0144) -#define EDMA_CH3_TRFCNT _SFR_MEM16(0x0146) -#define EDMA_CH3_ADDR _SFR_MEM16(0x0148) -#define EDMA_CH3_DESTADDR _SFR_MEM16(0x014C) - -/* EVSYS - Event System */ -#define EVSYS_CH0MUX _SFR_MEM8(0x0180) -#define EVSYS_CH1MUX _SFR_MEM8(0x0181) -#define EVSYS_CH2MUX _SFR_MEM8(0x0182) -#define EVSYS_CH3MUX _SFR_MEM8(0x0183) -#define EVSYS_CH4MUX _SFR_MEM8(0x0184) -#define EVSYS_CH5MUX _SFR_MEM8(0x0185) -#define EVSYS_CH6MUX _SFR_MEM8(0x0186) -#define EVSYS_CH7MUX _SFR_MEM8(0x0187) -#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) -#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) -#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) -#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) -#define EVSYS_CH4CTRL _SFR_MEM8(0x018C) -#define EVSYS_CH5CTRL _SFR_MEM8(0x018D) -#define EVSYS_CH6CTRL _SFR_MEM8(0x018E) -#define EVSYS_CH7CTRL _SFR_MEM8(0x018F) -#define EVSYS_STROBE _SFR_MEM8(0x0190) -#define EVSYS_DATA _SFR_MEM8(0x0191) -#define EVSYS_DFCTRL _SFR_MEM8(0x0192) - -/* NVM - Non-volatile Memory Controller */ -#define NVM_ADDR0 _SFR_MEM8(0x01C0) -#define NVM_ADDR1 _SFR_MEM8(0x01C1) -#define NVM_ADDR2 _SFR_MEM8(0x01C2) -#define NVM_DATA0 _SFR_MEM8(0x01C4) -#define NVM_DATA1 _SFR_MEM8(0x01C5) -#define NVM_DATA2 _SFR_MEM8(0x01C6) -#define NVM_CMD _SFR_MEM8(0x01CA) -#define NVM_CTRLA _SFR_MEM8(0x01CB) -#define NVM_CTRLB _SFR_MEM8(0x01CC) -#define NVM_INTCTRL _SFR_MEM8(0x01CD) -#define NVM_STATUS _SFR_MEM8(0x01CF) -#define NVM_LOCKBITS _SFR_MEM8(0x01D0) - -/* ADC - Analog-to-Digital Converter */ -#define ADCA_CTRLA _SFR_MEM8(0x0200) -#define ADCA_CTRLB _SFR_MEM8(0x0201) -#define ADCA_REFCTRL _SFR_MEM8(0x0202) -#define ADCA_EVCTRL _SFR_MEM8(0x0203) -#define ADCA_PRESCALER _SFR_MEM8(0x0204) -#define ADCA_INTFLAGS _SFR_MEM8(0x0206) -#define ADCA_TEMP _SFR_MEM8(0x0207) -#define ADCA_SAMPCTRL _SFR_MEM8(0x0208) -#define ADCA_CAL _SFR_MEM16(0x020C) -#define ADCA_CH0RES _SFR_MEM16(0x0210) -#define ADCA_CMP _SFR_MEM16(0x0218) -#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) -#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) -#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) -#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) -#define ADCA_CH0_RES _SFR_MEM16(0x0224) -#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) -#define ADCA_CH0_CORRCTRL _SFR_MEM8(0x0227) -#define ADCA_CH0_OFFSETCORR0 _SFR_MEM8(0x0228) -#define ADCA_CH0_OFFSETCORR1 _SFR_MEM8(0x0229) -#define ADCA_CH0_GAINCORR0 _SFR_MEM8(0x022A) -#define ADCA_CH0_GAINCORR1 _SFR_MEM8(0x022B) -#define ADCA_CH0_AVGCTRL _SFR_MEM8(0x022C) - -/* DAC - Digital-to-Analog Converter */ -#define DACA_CTRLA _SFR_MEM8(0x0300) -#define DACA_CTRLB _SFR_MEM8(0x0301) -#define DACA_CTRLC _SFR_MEM8(0x0302) -#define DACA_EVCTRL _SFR_MEM8(0x0303) -#define DACA_STATUS _SFR_MEM8(0x0305) -#define DACA_CH0GAINCAL _SFR_MEM8(0x0308) -#define DACA_CH0OFFSETCAL _SFR_MEM8(0x0309) -#define DACA_CH1GAINCAL _SFR_MEM8(0x030A) -#define DACA_CH1OFFSETCAL _SFR_MEM8(0x030B) -#define DACA_CH0DATA _SFR_MEM16(0x0318) -#define DACA_CH1DATA _SFR_MEM16(0x031A) - -/* AC - Analog Comparator */ -#define ACA_AC0CTRL _SFR_MEM8(0x0380) -#define ACA_AC1CTRL _SFR_MEM8(0x0381) -#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) -#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) -#define ACA_CTRLA _SFR_MEM8(0x0384) -#define ACA_CTRLB _SFR_MEM8(0x0385) -#define ACA_WINCTRL _SFR_MEM8(0x0386) -#define ACA_STATUS _SFR_MEM8(0x0387) -#define ACA_CURRCTRL _SFR_MEM8(0x0388) -#define ACA_CURRCALIB _SFR_MEM8(0x0389) - -/* RTC - Real-Time Counter */ -#define RTC_CTRL _SFR_MEM8(0x0400) -#define RTC_STATUS _SFR_MEM8(0x0401) -#define RTC_INTCTRL _SFR_MEM8(0x0402) -#define RTC_INTFLAGS _SFR_MEM8(0x0403) -#define RTC_TEMP _SFR_MEM8(0x0404) -#define RTC_CALIB _SFR_MEM8(0x0406) -#define RTC_CNT _SFR_MEM16(0x0408) -#define RTC_PER _SFR_MEM16(0x040A) -#define RTC_COMP _SFR_MEM16(0x040C) - -/* XCL - XMEGA Custom Logic */ -#define XCL_CTRLA _SFR_MEM8(0x0460) -#define XCL_CTRLB _SFR_MEM8(0x0461) -#define XCL_CTRLC _SFR_MEM8(0x0462) -#define XCL_CTRLD _SFR_MEM8(0x0463) -#define XCL_CTRLE _SFR_MEM8(0x0464) -#define XCL_CTRLF _SFR_MEM8(0x0465) -#define XCL_CTRLG _SFR_MEM8(0x0466) -#define XCL_INTCTRL _SFR_MEM8(0x0467) -#define XCL_INTFLAGS _SFR_MEM8(0x0468) -#define XCL_PLC _SFR_MEM8(0x0469) -#define XCL_CNTL _SFR_MEM8(0x046A) -#define XCL_CNTH _SFR_MEM8(0x046B) -#define XCL_CMPL _SFR_MEM8(0x046C) -#define XCL_CMPH _SFR_MEM8(0x046D) -#define XCL_PERCAPTL _SFR_MEM8(0x046E) -#define XCL_PERCAPTH _SFR_MEM8(0x046F) - -/* TWI - Two-Wire Interface */ -#define TWIC_CTRL _SFR_MEM8(0x0480) -#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) -#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) -#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) -#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) -#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) -#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) -#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) -#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) -#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) -#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) -#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) -#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) -#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) -#define TWIC_TIMEOUT_TOS _SFR_MEM8(0x048E) -#define TWIC_TIMEOUT_TOCONF _SFR_MEM8(0x048F) - -/* PORT - I/O Ports */ -#define PORTA_DIR _SFR_MEM8(0x0600) -#define PORTA_DIRSET _SFR_MEM8(0x0601) -#define PORTA_DIRCLR _SFR_MEM8(0x0602) -#define PORTA_DIRTGL _SFR_MEM8(0x0603) -#define PORTA_OUT _SFR_MEM8(0x0604) -#define PORTA_OUTSET _SFR_MEM8(0x0605) -#define PORTA_OUTCLR _SFR_MEM8(0x0606) -#define PORTA_OUTTGL _SFR_MEM8(0x0607) -#define PORTA_IN _SFR_MEM8(0x0608) -#define PORTA_INTCTRL _SFR_MEM8(0x0609) -#define PORTA_INTMASK _SFR_MEM8(0x060A) -#define PORTA_INTFLAGS _SFR_MEM8(0x060C) -#define PORTA_REMAP _SFR_MEM8(0x060E) -#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) -#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) -#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) -#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) -#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) -#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) -#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) -#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) - -/* PORT - I/O Ports */ -#define PORTC_DIR _SFR_MEM8(0x0640) -#define PORTC_DIRSET _SFR_MEM8(0x0641) -#define PORTC_DIRCLR _SFR_MEM8(0x0642) -#define PORTC_DIRTGL _SFR_MEM8(0x0643) -#define PORTC_OUT _SFR_MEM8(0x0644) -#define PORTC_OUTSET _SFR_MEM8(0x0645) -#define PORTC_OUTCLR _SFR_MEM8(0x0646) -#define PORTC_OUTTGL _SFR_MEM8(0x0647) -#define PORTC_IN _SFR_MEM8(0x0648) -#define PORTC_INTCTRL _SFR_MEM8(0x0649) -#define PORTC_INTMASK _SFR_MEM8(0x064A) -#define PORTC_INTFLAGS _SFR_MEM8(0x064C) -#define PORTC_REMAP _SFR_MEM8(0x064E) -#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) -#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) -#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) -#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) -#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) -#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) -#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) -#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) - -/* PORT - I/O Ports */ -#define PORTD_DIR _SFR_MEM8(0x0660) -#define PORTD_DIRSET _SFR_MEM8(0x0661) -#define PORTD_DIRCLR _SFR_MEM8(0x0662) -#define PORTD_DIRTGL _SFR_MEM8(0x0663) -#define PORTD_OUT _SFR_MEM8(0x0664) -#define PORTD_OUTSET _SFR_MEM8(0x0665) -#define PORTD_OUTCLR _SFR_MEM8(0x0666) -#define PORTD_OUTTGL _SFR_MEM8(0x0667) -#define PORTD_IN _SFR_MEM8(0x0668) -#define PORTD_INTCTRL _SFR_MEM8(0x0669) -#define PORTD_INTMASK _SFR_MEM8(0x066A) -#define PORTD_INTFLAGS _SFR_MEM8(0x066C) -#define PORTD_REMAP _SFR_MEM8(0x066E) -#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) -#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) -#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) -#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) -#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) -#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) -#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) -#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) - -/* PORT - I/O Ports */ -#define PORTR_DIR _SFR_MEM8(0x07E0) -#define PORTR_DIRSET _SFR_MEM8(0x07E1) -#define PORTR_DIRCLR _SFR_MEM8(0x07E2) -#define PORTR_DIRTGL _SFR_MEM8(0x07E3) -#define PORTR_OUT _SFR_MEM8(0x07E4) -#define PORTR_OUTSET _SFR_MEM8(0x07E5) -#define PORTR_OUTCLR _SFR_MEM8(0x07E6) -#define PORTR_OUTTGL _SFR_MEM8(0x07E7) -#define PORTR_IN _SFR_MEM8(0x07E8) -#define PORTR_INTCTRL _SFR_MEM8(0x07E9) -#define PORTR_INTMASK _SFR_MEM8(0x07EA) -#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) -#define PORTR_REMAP _SFR_MEM8(0x07EE) -#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) -#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) -#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) -#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) -#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) -#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) -#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) -#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) - -/* TC4 - 16-bit Timer/Counter 4 */ -#define TCC4_CTRLA _SFR_MEM8(0x0800) -#define TCC4_CTRLB _SFR_MEM8(0x0801) -#define TCC4_CTRLC _SFR_MEM8(0x0802) -#define TCC4_CTRLD _SFR_MEM8(0x0803) -#define TCC4_CTRLE _SFR_MEM8(0x0804) -#define TCC4_CTRLF _SFR_MEM8(0x0805) -#define TCC4_INTCTRLA _SFR_MEM8(0x0806) -#define TCC4_INTCTRLB _SFR_MEM8(0x0807) -#define TCC4_CTRLGCLR _SFR_MEM8(0x0808) -#define TCC4_CTRLGSET _SFR_MEM8(0x0809) -#define TCC4_CTRLHCLR _SFR_MEM8(0x080A) -#define TCC4_CTRLHSET _SFR_MEM8(0x080B) -#define TCC4_INTFLAGS _SFR_MEM8(0x080C) -#define TCC4_TEMP _SFR_MEM8(0x080F) -#define TCC4_CNT _SFR_MEM16(0x0820) -#define TCC4_PER _SFR_MEM16(0x0826) -#define TCC4_CCA _SFR_MEM16(0x0828) -#define TCC4_CCB _SFR_MEM16(0x082A) -#define TCC4_CCC _SFR_MEM16(0x082C) -#define TCC4_CCD _SFR_MEM16(0x082E) -#define TCC4_PERBUF _SFR_MEM16(0x0836) -#define TCC4_CCABUF _SFR_MEM16(0x0838) -#define TCC4_CCBBUF _SFR_MEM16(0x083A) -#define TCC4_CCCBUF _SFR_MEM16(0x083C) -#define TCC4_CCDBUF _SFR_MEM16(0x083E) - -/* TC5 - 16-bit Timer/Counter 5 */ -#define TCC5_CTRLA _SFR_MEM8(0x0840) -#define TCC5_CTRLB _SFR_MEM8(0x0841) -#define TCC5_CTRLC _SFR_MEM8(0x0842) -#define TCC5_CTRLD _SFR_MEM8(0x0843) -#define TCC5_CTRLE _SFR_MEM8(0x0844) -#define TCC5_CTRLF _SFR_MEM8(0x0845) -#define TCC5_INTCTRLA _SFR_MEM8(0x0846) -#define TCC5_INTCTRLB _SFR_MEM8(0x0847) -#define TCC5_CTRLGCLR _SFR_MEM8(0x0848) -#define TCC5_CTRLGSET _SFR_MEM8(0x0849) -#define TCC5_CTRLHCLR _SFR_MEM8(0x084A) -#define TCC5_CTRLHSET _SFR_MEM8(0x084B) -#define TCC5_INTFLAGS _SFR_MEM8(0x084C) -#define TCC5_TEMP _SFR_MEM8(0x084F) -#define TCC5_CNT _SFR_MEM16(0x0860) -#define TCC5_PER _SFR_MEM16(0x0866) -#define TCC5_CCA _SFR_MEM16(0x0868) -#define TCC5_CCB _SFR_MEM16(0x086A) -#define TCC5_PERBUF _SFR_MEM16(0x0876) -#define TCC5_CCABUF _SFR_MEM16(0x0878) -#define TCC5_CCBBUF _SFR_MEM16(0x087A) - -/* FAULT - Fault Extension */ -#define FAULTC4_CTRLA _SFR_MEM8(0x0880) -#define FAULTC4_CTRLB _SFR_MEM8(0x0881) -#define FAULTC4_CTRLC _SFR_MEM8(0x0882) -#define FAULTC4_CTRLD _SFR_MEM8(0x0883) -#define FAULTC4_CTRLE _SFR_MEM8(0x0884) -#define FAULTC4_STATUS _SFR_MEM8(0x0885) -#define FAULTC4_CTRLGCLR _SFR_MEM8(0x0886) -#define FAULTC4_CTRLGSET _SFR_MEM8(0x0887) - -/* FAULT - Fault Extension */ -#define FAULTC5_CTRLA _SFR_MEM8(0x0890) -#define FAULTC5_CTRLB _SFR_MEM8(0x0891) -#define FAULTC5_CTRLC _SFR_MEM8(0x0892) -#define FAULTC5_CTRLD _SFR_MEM8(0x0893) -#define FAULTC5_CTRLE _SFR_MEM8(0x0894) -#define FAULTC5_STATUS _SFR_MEM8(0x0895) -#define FAULTC5_CTRLGCLR _SFR_MEM8(0x0896) -#define FAULTC5_CTRLGSET _SFR_MEM8(0x0897) - -/* WEX - Waveform Extension */ -#define WEXC_CTRL _SFR_MEM8(0x08A0) -#define WEXC_DTBOTH _SFR_MEM8(0x08A1) -#define WEXC_DTLS _SFR_MEM8(0x08A2) -#define WEXC_DTHS _SFR_MEM8(0x08A3) -#define WEXC_STATUSCLR _SFR_MEM8(0x08A4) -#define WEXC_STATUSSET _SFR_MEM8(0x08A5) -#define WEXC_SWAP _SFR_MEM8(0x08A6) -#define WEXC_PGO _SFR_MEM8(0x08A7) -#define WEXC_PGV _SFR_MEM8(0x08A8) -#define WEXC_SWAPBUF _SFR_MEM8(0x08AA) -#define WEXC_PGOBUF _SFR_MEM8(0x08AB) -#define WEXC_PGVBUF _SFR_MEM8(0x08AC) -#define WEXC_OUTOVDIS _SFR_MEM8(0x08AF) - -/* HIRES - High-Resolution Extension */ -#define HIRESC_CTRLA _SFR_MEM8(0x08B0) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTC0_DATA _SFR_MEM8(0x08C0) -#define USARTC0_STATUS _SFR_MEM8(0x08C1) -#define USARTC0_CTRLA _SFR_MEM8(0x08C2) -#define USARTC0_CTRLB _SFR_MEM8(0x08C3) -#define USARTC0_CTRLC _SFR_MEM8(0x08C4) -#define USARTC0_CTRLD _SFR_MEM8(0x08C5) -#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08C6) -#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08C7) - -/* SPI - Serial Peripheral Interface with Buffer Modes */ -#define SPIC_CTRL _SFR_MEM8(0x08E0) -#define SPIC_INTCTRL _SFR_MEM8(0x08E1) -#define SPIC_STATUS _SFR_MEM8(0x08E2) -#define SPIC_DATA _SFR_MEM8(0x08E3) -#define SPIC_CTRLB _SFR_MEM8(0x08E4) - -/* IRCOM - IR Communication Module */ -#define IRCOM_CTRL _SFR_MEM8(0x08F8) -#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) -#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) - -/* TC5 - 16-bit Timer/Counter 5 */ -#define TCD5_CTRLA _SFR_MEM8(0x0940) -#define TCD5_CTRLB _SFR_MEM8(0x0941) -#define TCD5_CTRLC _SFR_MEM8(0x0942) -#define TCD5_CTRLD _SFR_MEM8(0x0943) -#define TCD5_CTRLE _SFR_MEM8(0x0944) -#define TCD5_CTRLF _SFR_MEM8(0x0945) -#define TCD5_INTCTRLA _SFR_MEM8(0x0946) -#define TCD5_INTCTRLB _SFR_MEM8(0x0947) -#define TCD5_CTRLGCLR _SFR_MEM8(0x0948) -#define TCD5_CTRLGSET _SFR_MEM8(0x0949) -#define TCD5_CTRLHCLR _SFR_MEM8(0x094A) -#define TCD5_CTRLHSET _SFR_MEM8(0x094B) -#define TCD5_INTFLAGS _SFR_MEM8(0x094C) -#define TCD5_TEMP _SFR_MEM8(0x094F) -#define TCD5_CNT _SFR_MEM16(0x0960) -#define TCD5_PER _SFR_MEM16(0x0966) -#define TCD5_CCA _SFR_MEM16(0x0968) -#define TCD5_CCB _SFR_MEM16(0x096A) -#define TCD5_PERBUF _SFR_MEM16(0x0976) -#define TCD5_CCABUF _SFR_MEM16(0x0978) -#define TCD5_CCBBUF _SFR_MEM16(0x097A) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTD0_DATA _SFR_MEM8(0x09C0) -#define USARTD0_STATUS _SFR_MEM8(0x09C1) -#define USARTD0_CTRLA _SFR_MEM8(0x09C2) -#define USARTD0_CTRLB _SFR_MEM8(0x09C3) -#define USARTD0_CTRLC _SFR_MEM8(0x09C4) -#define USARTD0_CTRLD _SFR_MEM8(0x09C5) -#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09C6) -#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09C7) - - - -/*================== Bitfield Definitions ================== */ - -/* VPORT - Virtual Ports */ -/* VPORT.INTFLAGS bit masks and bit positions */ -#define VPORT_INT7IF_bm 0x80 /* Interrupt Pin 7 Flag bit mask. */ -#define VPORT_INT7IF_bp 7 /* Interrupt Pin 7 Flag bit position. */ - -#define VPORT_INT6IF_bm 0x40 /* Interrupt Pin 6 Flag bit mask. */ -#define VPORT_INT6IF_bp 6 /* Interrupt Pin 6 Flag bit position. */ - -#define VPORT_INT5IF_bm 0x20 /* Interrupt Pin 5 Flag bit mask. */ -#define VPORT_INT5IF_bp 5 /* Interrupt Pin 5 Flag bit position. */ - -#define VPORT_INT4IF_bm 0x10 /* Interrupt Pin 4 Flag bit mask. */ -#define VPORT_INT4IF_bp 4 /* Interrupt Pin 4 Flag bit position. */ - -#define VPORT_INT3IF_bm 0x08 /* Interrupt Pin 3 Flag bit mask. */ -#define VPORT_INT3IF_bp 3 /* Interrupt Pin 3 Flag bit position. */ - -#define VPORT_INT2IF_bm 0x04 /* Interrupt Pin 2 Flag bit mask. */ -#define VPORT_INT2IF_bp 2 /* Interrupt Pin 2 Flag bit position. */ - -#define VPORT_INT1IF_bm 0x02 /* Interrupt Pin 1 Flag bit mask. */ -#define VPORT_INT1IF_bp 1 /* Interrupt Pin 1 Flag bit position. */ - -#define VPORT_INT0IF_bm 0x01 /* Interrupt Pin 0 Flag bit mask. */ -#define VPORT_INT0IF_bp 0 /* Interrupt Pin 0 Flag bit position. */ - -/* XOCD - On-Chip Debug System */ -/* OCD.OCDR0 bit masks and bit positions */ -#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ -#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ -#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ -#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ -#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ -#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ -#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ -#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ -#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ -#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ -#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ -#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ -#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ -#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ -#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ -#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ -#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ -#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ - -/* OCD.OCDR1 bit masks and bit positions */ -/* OCD_OCDRD Predefined. */ -/* OCD_OCDRD Predefined. */ - -/* CPU - CPU */ -/* CPU.CCP bit masks and bit positions */ -#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ -#define CPU_CCP_gp 0 /* CCP signature group position. */ -#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ -#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ -#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ -#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ -#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ -#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ -#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ -#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ -#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ -#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ -#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ -#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ -#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ -#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ -#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ -#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ - -/* CPU.SREG bit masks and bit positions */ -#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ -#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ - -#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ -#define CPU_T_bp 6 /* Transfer Bit bit position. */ - -#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ -#define CPU_H_bp 5 /* Half Carry Flag bit position. */ - -#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ -#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ - -#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ -#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ - -#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ -#define CPU_N_bp 2 /* Negative Flag bit position. */ - -#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ -#define CPU_Z_bp 1 /* Zero Flag bit position. */ - -#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ -#define CPU_C_bp 0 /* Carry Flag bit position. */ - -/* CLK - Clock System */ -/* CLK.CTRL bit masks and bit positions */ -#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ -#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ -#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ -#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ -#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ -#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ -#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ -#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ - -/* CLK.PSCTRL bit masks and bit positions */ -#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ -#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ -#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ -#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ -#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ -#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ -#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ -#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ -#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ -#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ -#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ -#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ - -#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ -#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ -#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ -#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ -#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ -#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ - -/* CLK.LOCK bit masks and bit positions */ -#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ -#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ - -/* CLK.RTCCTRL bit masks and bit positions */ -#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ -#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ -#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ -#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ -#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ -#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ - -#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ -#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ - -/* PR.PRGEN bit masks and bit positions */ -#define PR_XCL_bm 0x80 /* XMEGA Custom Logic bit mask. */ -#define PR_XCL_bp 7 /* XMEGA Custom Logic bit position. */ - -#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ -#define PR_RTC_bp 2 /* Real-time Counter bit position. */ - -#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ -#define PR_EVSYS_bp 1 /* Event System bit position. */ - -#define PR_EDMA_bm 0x01 /* Enhanced DMA-Controller bit mask. */ -#define PR_EDMA_bp 0 /* Enhanced DMA-Controller bit position. */ - -/* PR.PRPA bit masks and bit positions */ -#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ -#define PR_DAC_bp 2 /* Port A DAC bit position. */ - -#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ -#define PR_ADC_bp 1 /* Port A ADC bit position. */ - -#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ -#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ - -/* PR.PRPC bit masks and bit positions */ -#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ -#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ - -#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ -#define PR_USART0_bp 4 /* Port C USART0 bit position. */ - -#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ -#define PR_SPI_bp 3 /* Port C SPI bit position. */ - -#define PR_HIRES_bm 0x04 /* Port C WEX bit mask. */ -#define PR_HIRES_bp 2 /* Port C WEX bit position. */ - -#define PR_TC5_bm 0x02 /* Port C Timer/Counter5 bit mask. */ -#define PR_TC5_bp 1 /* Port C Timer/Counter5 bit position. */ - -#define PR_TC4_bm 0x01 /* Port C Timer/Counter4 bit mask. */ -#define PR_TC4_bp 0 /* Port C Timer/Counter4 bit position. */ - -/* PR.PRPD bit masks and bit positions */ -/* PR_USART0 Predefined. */ -/* PR_USART0 Predefined. */ - -/* PR_TC5 Predefined. */ -/* PR_TC5 Predefined. */ - -/* SLEEP - Sleep Controller */ -/* SLEEP.CTRL bit masks and bit positions */ -#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ -#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ -#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ -#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ -#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ -#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ -#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ -#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ - -#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ -#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ - -/* OSC - Oscillator */ -/* OSC.CTRL bit masks and bit positions */ -#define OSC_RC8MLPM_bm 0x40 /* Internal 8 MHz RC Low Power Mode Enable bit mask. */ -#define OSC_RC8MLPM_bp 6 /* Internal 8 MHz RC Low Power Mode Enable bit position. */ - -#define OSC_RC8MEN_bm 0x20 /* Internal 8 MHz RC Oscillator Enable bit mask. */ -#define OSC_RC8MEN_bp 5 /* Internal 8 MHz RC Oscillator Enable bit position. */ - -#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ -#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ - -#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ -#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ - -#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ -#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ - -#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ -#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ - -#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ -#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ - -/* OSC.STATUS bit masks and bit positions */ -#define OSC_RC8MRDY_bm 0x20 /* Internal 8 MHz RC Oscillator Ready bit mask. */ -#define OSC_RC8MRDY_bp 5 /* Internal 8 MHz RC Oscillator Ready bit position. */ - -#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ -#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ - -#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ -#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ - -#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ -#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ - -#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ -#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ - -#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ -#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ - -/* OSC.XOSCCTRL bit masks and bit positions */ -#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ -#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ -#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ -#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ -#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ -#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ - -#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ -#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ - -#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ -#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ - -#define OSC_XOSCSEL_gm 0x1F /* External Oscillator Selection and Startup Time group mask. */ -#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ -#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ -#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ -#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ -#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ -#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ -#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ -#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ -#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ -#define OSC_XOSCSEL4_bm (1<<4) /* External Oscillator Selection and Startup Time bit 4 mask. */ -#define OSC_XOSCSEL4_bp 4 /* External Oscillator Selection and Startup Time bit 4 position. */ - -/* OSC.XOSCFAIL bit masks and bit positions */ -#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ -#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ - -#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ -#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ - -#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ -#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ - -#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ -#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ - -/* OSC.PLLCTRL bit masks and bit positions */ -#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ -#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ -#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ -#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ -#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ -#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ - -#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ -#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ - -#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ -#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ -#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ -#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ -#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ -#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ -#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ -#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ -#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ -#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ -#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ -#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ - -/* OSC.DFLLCTRL bit masks and bit positions */ -#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ -#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ -#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ -#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ -#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ -#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ - -/* OSC.RC8MCAL bit masks and bit positions */ -#define OSC_RC8MCAL_gm 0xFF /* Calibration Bits group mask. */ -#define OSC_RC8MCAL_gp 0 /* Calibration Bits group position. */ -#define OSC_RC8MCAL0_bm (1<<0) /* Calibration Bits bit 0 mask. */ -#define OSC_RC8MCAL0_bp 0 /* Calibration Bits bit 0 position. */ -#define OSC_RC8MCAL1_bm (1<<1) /* Calibration Bits bit 1 mask. */ -#define OSC_RC8MCAL1_bp 1 /* Calibration Bits bit 1 position. */ -#define OSC_RC8MCAL2_bm (1<<2) /* Calibration Bits bit 2 mask. */ -#define OSC_RC8MCAL2_bp 2 /* Calibration Bits bit 2 position. */ -#define OSC_RC8MCAL3_bm (1<<3) /* Calibration Bits bit 3 mask. */ -#define OSC_RC8MCAL3_bp 3 /* Calibration Bits bit 3 position. */ -#define OSC_RC8MCAL4_bm (1<<4) /* Calibration Bits bit 4 mask. */ -#define OSC_RC8MCAL4_bp 4 /* Calibration Bits bit 4 position. */ -#define OSC_RC8MCAL5_bm (1<<5) /* Calibration Bits bit 5 mask. */ -#define OSC_RC8MCAL5_bp 5 /* Calibration Bits bit 5 position. */ -#define OSC_RC8MCAL6_bm (1<<6) /* Calibration Bits bit 6 mask. */ -#define OSC_RC8MCAL6_bp 6 /* Calibration Bits bit 6 position. */ -#define OSC_RC8MCAL7_bm (1<<7) /* Calibration Bits bit 7 mask. */ -#define OSC_RC8MCAL7_bp 7 /* Calibration Bits bit 7 position. */ - -/* DFLL - DFLL */ -/* DFLL.CTRL bit masks and bit positions */ -#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ -#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ - -/* DFLL.CALA bit masks and bit positions */ -#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ -#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ -#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ -#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ -#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ -#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ -#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ -#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ -#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ -#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ -#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ -#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ -#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ -#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ -#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ -#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ - -/* DFLL.CALB bit masks and bit positions */ -#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ -#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ -#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ -#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ -#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ -#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ -#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ -#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ -#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ -#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ -#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ -#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ -#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ -#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ - -/* RST - Reset */ -/* RST.STATUS bit masks and bit positions */ -#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ -#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ - -#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ -#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ - -#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ -#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ - -#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ -#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ - -#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ -#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ - -#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ -#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ - -#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ -#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ - -/* RST.CTRL bit masks and bit positions */ -#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ -#define RST_SWRST_bp 0 /* Software Reset bit position. */ - -/* WDT - Watch-Dog Timer */ -/* WDT.CTRL bit masks and bit positions */ -#define WDT_PER_gm 0x3C /* Period group mask. */ -#define WDT_PER_gp 2 /* Period group position. */ -#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ -#define WDT_PER0_bp 2 /* Period bit 0 position. */ -#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ -#define WDT_PER1_bp 3 /* Period bit 1 position. */ -#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ -#define WDT_PER2_bp 4 /* Period bit 2 position. */ -#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ -#define WDT_PER3_bp 5 /* Period bit 3 position. */ - -#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ -#define WDT_ENABLE_bp 1 /* Enable bit position. */ - -#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ -#define WDT_CEN_bp 0 /* Change Enable bit position. */ - -/* WDT.WINCTRL bit masks and bit positions */ -#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ -#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ -#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ -#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ -#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ -#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ -#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ -#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ -#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ -#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ - -#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ -#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ - -#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ -#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ - -/* WDT.STATUS bit masks and bit positions */ -#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ -#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ - -/* MCU - MCU Control */ -/* MCU.ANAINIT bit masks and bit positions */ -#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ -#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ -#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ -#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ -#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ -#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ - -/* MCU.EVSYSLOCK bit masks and bit positions */ -#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ -#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ - -#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ -#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ - -/* MCU.WEXLOCK bit masks and bit positions */ -#define MCU_WEXCLOCK_bm 0x01 /* WeX on T/C C4 Lock bit mask. */ -#define MCU_WEXCLOCK_bp 0 /* WeX on T/C C4 Lock bit position. */ - -/* MCU.FAULTLOCK bit masks and bit positions */ -#define MCU_FAULTC5LOCK_bm 0x02 /* Fault on T/C C5 Lock bit mask. */ -#define MCU_FAULTC5LOCK_bp 1 /* Fault on T/C C5 Lock bit position. */ - -#define MCU_FAULTC4LOCK_bm 0x01 /* Fault on T/C C4 Lock bit mask. */ -#define MCU_FAULTC4LOCK_bp 0 /* Fault on T/C C4 Lock bit position. */ - -/* PMIC - Programmable Multi-level Interrupt Controller */ -/* PMIC.STATUS bit masks and bit positions */ -#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ -#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ - -#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ -#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ - -#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ -#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ - -#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ -#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ - -/* PMIC.INTPRI bit masks and bit positions */ -#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ -#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ -#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ -#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ -#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ -#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ -#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ -#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ -#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ -#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ -#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ -#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ -#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ -#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ -#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ -#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ -#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ -#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ - -/* PMIC.CTRL bit masks and bit positions */ -#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ -#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ - -#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ -#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ - -#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ -#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ - -#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ -#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ - -#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ -#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ - -/* PORTCFG - Port Configuration */ -/* PORTCFG.CLKOUT bit masks and bit positions */ -#define PORTCFG_CLKEVPIN_bm 0x80 /* Clock and Event Output Pin Select bit mask. */ -#define PORTCFG_CLKEVPIN_bp 7 /* Clock and Event Output Pin Select bit position. */ - -#define PORTCFG_RTCOUT_gm 0x60 /* RTC Clock Output Enable group mask. */ -#define PORTCFG_RTCOUT_gp 5 /* RTC Clock Output Enable group position. */ -#define PORTCFG_RTCOUT0_bm (1<<5) /* RTC Clock Output Enable bit 0 mask. */ -#define PORTCFG_RTCOUT0_bp 5 /* RTC Clock Output Enable bit 0 position. */ -#define PORTCFG_RTCOUT1_bm (1<<6) /* RTC Clock Output Enable bit 1 mask. */ -#define PORTCFG_RTCOUT1_bp 6 /* RTC Clock Output Enable bit 1 position. */ - -#define PORTCFG_CLKOUTSEL_gm 0x0C /* Clock Output Select group mask. */ -#define PORTCFG_CLKOUTSEL_gp 2 /* Clock Output Select group position. */ -#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Clock Output Select bit 0 mask. */ -#define PORTCFG_CLKOUTSEL0_bp 2 /* Clock Output Select bit 0 position. */ -#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Clock Output Select bit 1 mask. */ -#define PORTCFG_CLKOUTSEL1_bp 3 /* Clock Output Select bit 1 position. */ - -#define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */ -#define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */ -#define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */ -#define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */ -#define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */ -#define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */ - -/* PORTCFG.ACEVOUT bit masks and bit positions */ -#define PORTCFG_ACOUT_gm 0xC0 /* Analog Comparator Output Port group mask. */ -#define PORTCFG_ACOUT_gp 6 /* Analog Comparator Output Port group position. */ -#define PORTCFG_ACOUT0_bm (1<<6) /* Analog Comparator Output Port bit 0 mask. */ -#define PORTCFG_ACOUT0_bp 6 /* Analog Comparator Output Port bit 0 position. */ -#define PORTCFG_ACOUT1_bm (1<<7) /* Analog Comparator Output Port bit 1 mask. */ -#define PORTCFG_ACOUT1_bp 7 /* Analog Comparator Output Port bit 1 position. */ - -#define PORTCFG_EVOUT_gm 0x30 /* Event Channel Output Port group mask. */ -#define PORTCFG_EVOUT_gp 4 /* Event Channel Output Port group position. */ -#define PORTCFG_EVOUT0_bm (1<<4) /* Event Channel Output Port bit 0 mask. */ -#define PORTCFG_EVOUT0_bp 4 /* Event Channel Output Port bit 0 position. */ -#define PORTCFG_EVOUT1_bm (1<<5) /* Event Channel Output Port bit 1 mask. */ -#define PORTCFG_EVOUT1_bp 5 /* Event Channel Output Port bit 1 position. */ - -#define PORTCFG_EVASYEN_bm 0x08 /* Asynchronous Event Enabled bit mask. */ -#define PORTCFG_EVASYEN_bp 3 /* Asynchronous Event Enabled bit position. */ - -#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Channel Output Selection group mask. */ -#define PORTCFG_EVOUTSEL_gp 0 /* Event Channel Output Selection group position. */ -#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Channel Output Selection bit 0 mask. */ -#define PORTCFG_EVOUTSEL0_bp 0 /* Event Channel Output Selection bit 0 position. */ -#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Channel Output Selection bit 1 mask. */ -#define PORTCFG_EVOUTSEL1_bp 1 /* Event Channel Output Selection bit 1 position. */ -#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Channel Output Selection bit 2 mask. */ -#define PORTCFG_EVOUTSEL2_bp 2 /* Event Channel Output Selection bit 2 position. */ - -/* PORTCFG.SRLCTRL bit masks and bit positions */ -#define PORTCFG_SRLENRA_bm 0x01 /* Slew Rate Limit Enable on PORTA bit mask. */ -#define PORTCFG_SRLENRA_bp 0 /* Slew Rate Limit Enable on PORTA bit position. */ - -#define PORTCFG_SRLENRC_bm 0x04 /* Slew Rate Limit Enable on PORTC bit mask. */ -#define PORTCFG_SRLENRC_bp 2 /* Slew Rate Limit Enable on PORTC bit position. */ - -#define PORTCFG_SRLENRD_bm 0x08 /* Slew Rate Limit Enable on PORTD bit mask. */ -#define PORTCFG_SRLENRD_bp 3 /* Slew Rate Limit Enable on PORTD bit position. */ - -#define PORTCFG_SRLENRR_bm 0x80 /* Slew Rate Limit Enable on PORTR bit mask. */ -#define PORTCFG_SRLENRR_bp 7 /* Slew Rate Limit Enable on PORTR bit position. */ - -/* CRC - Cyclic Redundancy Checker */ -/* CRC.CTRL bit masks and bit positions */ -#define CRC_RESET_gm 0xC0 /* Reset group mask. */ -#define CRC_RESET_gp 6 /* Reset group position. */ -#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ -#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ -#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ -#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ - -#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ -#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ - -#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ -#define CRC_SOURCE_gp 0 /* Input Source group position. */ -#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ -#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ -#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ -#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ -#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ -#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ -#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ -#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ - -/* CRC.STATUS bit masks and bit positions */ -#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ -#define CRC_ZERO_bp 1 /* Zero detection bit position. */ - -#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ -#define CRC_BUSY_bp 0 /* Busy bit position. */ - -/* EDMA - Enhanced DMA Controller */ -/* EDMA.CTRL bit masks and bit positions */ -#define EDMA_ENABLE_bm 0x80 /* Enable bit mask. */ -#define EDMA_ENABLE_bp 7 /* Enable bit position. */ - -#define EDMA_RESET_bm 0x40 /* Software Reset bit mask. */ -#define EDMA_RESET_bp 6 /* Software Reset bit position. */ - -#define EDMA_CHMODE_gm 0x30 /* Channel Mode group mask. */ -#define EDMA_CHMODE_gp 4 /* Channel Mode group position. */ -#define EDMA_CHMODE0_bm (1<<4) /* Channel Mode bit 0 mask. */ -#define EDMA_CHMODE0_bp 4 /* Channel Mode bit 0 position. */ -#define EDMA_CHMODE1_bm (1<<5) /* Channel Mode bit 1 mask. */ -#define EDMA_CHMODE1_bp 5 /* Channel Mode bit 1 position. */ - -#define EDMA_DBUFMODE_gm 0x0C /* Double Buffer Mode group mask. */ -#define EDMA_DBUFMODE_gp 2 /* Double Buffer Mode group position. */ -#define EDMA_DBUFMODE0_bm (1<<2) /* Double Buffer Mode bit 0 mask. */ -#define EDMA_DBUFMODE0_bp 2 /* Double Buffer Mode bit 0 position. */ -#define EDMA_DBUFMODE1_bm (1<<3) /* Double Buffer Mode bit 1 mask. */ -#define EDMA_DBUFMODE1_bp 3 /* Double Buffer Mode bit 1 position. */ - -#define EDMA_PRIMODE_gm 0x03 /* Priority Mode group mask. */ -#define EDMA_PRIMODE_gp 0 /* Priority Mode group position. */ -#define EDMA_PRIMODE0_bm (1<<0) /* Priority Mode bit 0 mask. */ -#define EDMA_PRIMODE0_bp 0 /* Priority Mode bit 0 position. */ -#define EDMA_PRIMODE1_bm (1<<1) /* Priority Mode bit 1 mask. */ -#define EDMA_PRIMODE1_bp 1 /* Priority Mode bit 1 position. */ - -/* EDMA.INTFLAGS bit masks and bit positions */ -#define EDMA_CH3ERRIF_bm 0x80 /* Channel 3 Transaction Error Interrupt Flag bit mask. */ -#define EDMA_CH3ERRIF_bp 7 /* Channel 3 Transaction Error Interrupt Flag bit position. */ - -#define EDMA_CH2ERRIF_bm 0x40 /* Channel 2 Transaction Error Interrupt Flag bit mask. */ -#define EDMA_CH2ERRIF_bp 6 /* Channel 2 Transaction Error Interrupt Flag bit position. */ - -#define EDMA_CH1ERRIF_bm 0x20 /* Channel 1 Transaction Error Interrupt Flag bit mask. */ -#define EDMA_CH1ERRIF_bp 5 /* Channel 1 Transaction Error Interrupt Flag bit position. */ - -#define EDMA_CH0ERRIF_bm 0x10 /* Channel 0 Transaction Error Interrupt Flag bit mask. */ -#define EDMA_CH0ERRIF_bp 4 /* Channel 0 Transaction Error Interrupt Flag bit position. */ - -#define EDMA_CH3TRNFIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ -#define EDMA_CH3TRNFIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ - -#define EDMA_CH2TRNFIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ -#define EDMA_CH2TRNFIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ - -#define EDMA_CH1TRNFIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ -#define EDMA_CH1TRNFIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ - -#define EDMA_CH0TRNFIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ -#define EDMA_CH0TRNFIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ - -/* EDMA.STATUS bit masks and bit positions */ -#define EDMA_CH3BUSY_bm 0x80 /* Channel 3 Busy Flag bit mask. */ -#define EDMA_CH3BUSY_bp 7 /* Channel 3 Busy Flag bit position. */ - -#define EDMA_CH2BUSY_bm 0x40 /* Channel 2 Busy Flag bit mask. */ -#define EDMA_CH2BUSY_bp 6 /* Channel 2 Busy Flag bit position. */ - -#define EDMA_CH1BUSY_bm 0x20 /* Channel 1 Busy Flag bit mask. */ -#define EDMA_CH1BUSY_bp 5 /* Channel 1 Busy Flag bit position. */ - -#define EDMA_CH0BUSY_bm 0x10 /* Channel 0 Busy Flag bit mask. */ -#define EDMA_CH0BUSY_bp 4 /* Channel 0 Busy Flag bit position. */ - -#define EDMA_CH3PEND_bm 0x08 /* Channel 3 Pending Flag bit mask. */ -#define EDMA_CH3PEND_bp 3 /* Channel 3 Pending Flag bit position. */ - -#define EDMA_CH2PEND_bm 0x04 /* Channel 2 Pending Flag bit mask. */ -#define EDMA_CH2PEND_bp 2 /* Channel 2 Pending Flag bit position. */ - -#define EDMA_CH1PEND_bm 0x02 /* Channel 1 Pending Flag bit mask. */ -#define EDMA_CH1PEND_bp 1 /* Channel 1 Pending Flag bit position. */ - -#define EDMA_CH0PEND_bm 0x01 /* Channel 0 Pending Flag bit mask. */ -#define EDMA_CH0PEND_bp 0 /* Channel 0 Pending Flag bit position. */ - -/* EDMA_CH.CTRLA bit masks and bit positions */ -#define EDMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ -#define EDMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ - -#define EDMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ -#define EDMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ - -#define EDMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ -#define EDMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ - -#define EDMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ -#define EDMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ - -#define EDMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ -#define EDMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ - -#define EDMA_CH_BURSTLEN_bm 0x01 /* Channel 2-bytes Burst Length bit mask. */ -#define EDMA_CH_BURSTLEN_bp 0 /* Channel 2-bytes Burst Length bit position. */ - -/* EDMA_CH.CTRLB bit masks and bit positions */ -#define EDMA_CH_CHBUSY_bm 0x80 /* Channel Block Transfer Busy bit mask. */ -#define EDMA_CH_CHBUSY_bp 7 /* Channel Block Transfer Busy bit position. */ - -#define EDMA_CH_CHPEND_bm 0x40 /* Channel Block Transfer Pending bit mask. */ -#define EDMA_CH_CHPEND_bp 6 /* Channel Block Transfer Pending bit position. */ - -#define EDMA_CH_ERRIF_bm 0x20 /* Channel Transaction Error Interrupt Flag bit mask. */ -#define EDMA_CH_ERRIF_bp 5 /* Channel Transaction Error Interrupt Flag bit position. */ - -#define EDMA_CH_TRNIF_bm 0x10 /* Channel Transaction Complete Interrup Flag bit mask. */ -#define EDMA_CH_TRNIF_bp 4 /* Channel Transaction Complete Interrup Flag bit position. */ - -#define EDMA_CH_ERRINTLVL_gm 0x0C /* Channel Transaction Error Interrupt Level group mask. */ -#define EDMA_CH_ERRINTLVL_gp 2 /* Channel Transaction Error Interrupt Level group position. */ -#define EDMA_CH_ERRINTLVL0_bm (1<<2) /* Channel Transaction Error Interrupt Level bit 0 mask. */ -#define EDMA_CH_ERRINTLVL0_bp 2 /* Channel Transaction Error Interrupt Level bit 0 position. */ -#define EDMA_CH_ERRINTLVL1_bm (1<<3) /* Channel Transaction Error Interrupt Level bit 1 mask. */ -#define EDMA_CH_ERRINTLVL1_bp 3 /* Channel Transaction Error Interrupt Level bit 1 position. */ - -#define EDMA_CH_TRNINTLVL_gm 0x03 /* Channel Transaction Complete Interrupt Level group mask. */ -#define EDMA_CH_TRNINTLVL_gp 0 /* Channel Transaction Complete Interrupt Level group position. */ -#define EDMA_CH_TRNINTLVL0_bm (1<<0) /* Channel Transaction Complete Interrupt Level bit 0 mask. */ -#define EDMA_CH_TRNINTLVL0_bp 0 /* Channel Transaction Complete Interrupt Level bit 0 position. */ -#define EDMA_CH_TRNINTLVL1_bm (1<<1) /* Channel Transaction Complete Interrupt Level bit 1 mask. */ -#define EDMA_CH_TRNINTLVL1_bp 1 /* Channel Transaction Complete Interrupt Level bit 1 position. */ - -/* EDMA_CH.ADDRCTRL bit masks and bit positions */ -#define EDMA_CH_RELOAD_gm 0x30 /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. group mask. */ -#define EDMA_CH_RELOAD_gp 4 /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. group position. */ -#define EDMA_CH_RELOAD0_bm (1<<4) /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. bit 0 mask. */ -#define EDMA_CH_RELOAD0_bp 4 /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. bit 0 position. */ -#define EDMA_CH_RELOAD1_bm (1<<5) /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. bit 1 mask. */ -#define EDMA_CH_RELOAD1_bp 5 /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. bit 1 position. */ - -#define EDMA_CH_DIR_gm 0x07 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. group mask. */ -#define EDMA_CH_DIR_gp 0 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. group position. */ -#define EDMA_CH_DIR0_bm (1<<0) /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 0 mask. */ -#define EDMA_CH_DIR0_bp 0 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 0 position. */ -#define EDMA_CH_DIR1_bm (1<<1) /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 1 mask. */ -#define EDMA_CH_DIR1_bp 1 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 1 position. */ -#define EDMA_CH_DIR2_bm (1<<2) /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 2 mask. */ -#define EDMA_CH_DIR2_bp 2 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 2 position. */ - -/* EDMA_CH.DESTADDRCTRL bit masks and bit positions */ -#define EDMA_CH_DESTRELOAD_gm 0x30 /* Destination Address Reload for Standard Channels Only. group mask. */ -#define EDMA_CH_DESTRELOAD_gp 4 /* Destination Address Reload for Standard Channels Only. group position. */ -#define EDMA_CH_DESTRELOAD0_bm (1<<4) /* Destination Address Reload for Standard Channels Only. bit 0 mask. */ -#define EDMA_CH_DESTRELOAD0_bp 4 /* Destination Address Reload for Standard Channels Only. bit 0 position. */ -#define EDMA_CH_DESTRELOAD1_bm (1<<5) /* Destination Address Reload for Standard Channels Only. bit 1 mask. */ -#define EDMA_CH_DESTRELOAD1_bp 5 /* Destination Address Reload for Standard Channels Only. bit 1 position. */ - -#define EDMA_CH_DESTDIR_gm 0x07 /* Destination Address Mode for Standard Channels Only. group mask. */ -#define EDMA_CH_DESTDIR_gp 0 /* Destination Address Mode for Standard Channels Only. group position. */ -#define EDMA_CH_DESTDIR0_bm (1<<0) /* Destination Address Mode for Standard Channels Only. bit 0 mask. */ -#define EDMA_CH_DESTDIR0_bp 0 /* Destination Address Mode for Standard Channels Only. bit 0 position. */ -#define EDMA_CH_DESTDIR1_bm (1<<1) /* Destination Address Mode for Standard Channels Only. bit 1 mask. */ -#define EDMA_CH_DESTDIR1_bp 1 /* Destination Address Mode for Standard Channels Only. bit 1 position. */ -#define EDMA_CH_DESTDIR2_bm (1<<2) /* Destination Address Mode for Standard Channels Only. bit 2 mask. */ -#define EDMA_CH_DESTDIR2_bp 2 /* Destination Address Mode for Standard Channels Only. bit 2 position. */ - -/* EDMA_CH.TRIGSRC bit masks and bit positions */ -#define EDMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ -#define EDMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ -#define EDMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ -#define EDMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ -#define EDMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ -#define EDMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ -#define EDMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ -#define EDMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ -#define EDMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ -#define EDMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ -#define EDMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ -#define EDMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ -#define EDMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ -#define EDMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ -#define EDMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ -#define EDMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ -#define EDMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ -#define EDMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ - -/* EVSYS - Event System */ -/* EVSYS.CH0MUX bit masks and bit positions */ -#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ -#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ -#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ -#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ -#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ -#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ -#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ -#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ -#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ -#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ -#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ -#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ -#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ -#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ -#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ -#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ -#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ -#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ - -/* EVSYS.CH1MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH2MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH3MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH4MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH5MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH6MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH7MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH0CTRL bit masks and bit positions */ -#define EVSYS_ROTARY_bm 0x80 /* Rotary Decoder Enable bit mask. */ -#define EVSYS_ROTARY_bp 7 /* Rotary Decoder Enable bit position. */ - -#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ -#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ -#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ -#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ -#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ -#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ - -#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ -#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ - -#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ -#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ - -#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ -#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ -#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ -#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ -#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ -#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ -#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ -#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ - -/* EVSYS.CH1CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH2CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH3CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH4CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH5CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH6CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH7CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.DFCTRL bit masks and bit positions */ -#define EVSYS_PRESCFILT_gm 0xF0 /* Prescaler Filter group mask. */ -#define EVSYS_PRESCFILT_gp 4 /* Prescaler Filter group position. */ -#define EVSYS_PRESCFILT0_bm (1<<4) /* Prescaler Filter bit 0 mask. */ -#define EVSYS_PRESCFILT0_bp 4 /* Prescaler Filter bit 0 position. */ -#define EVSYS_PRESCFILT1_bm (1<<5) /* Prescaler Filter bit 1 mask. */ -#define EVSYS_PRESCFILT1_bp 5 /* Prescaler Filter bit 1 position. */ -#define EVSYS_PRESCFILT2_bm (1<<6) /* Prescaler Filter bit 2 mask. */ -#define EVSYS_PRESCFILT2_bp 6 /* Prescaler Filter bit 2 position. */ -#define EVSYS_PRESCFILT3_bm (1<<7) /* Prescaler Filter bit 3 mask. */ -#define EVSYS_PRESCFILT3_bp 7 /* Prescaler Filter bit 3 position. */ - -#define EVSYS_FILTSEL_bm 0x08 /* Prescaler Filter Select bit mask. */ -#define EVSYS_FILTSEL_bp 3 /* Prescaler Filter Select bit position. */ - -#define EVSYS_PRESC_gm 0x07 /* Prescaler group mask. */ -#define EVSYS_PRESC_gp 0 /* Prescaler group position. */ -#define EVSYS_PRESC0_bm (1<<0) /* Prescaler bit 0 mask. */ -#define EVSYS_PRESC0_bp 0 /* Prescaler bit 0 position. */ -#define EVSYS_PRESC1_bm (1<<1) /* Prescaler bit 1 mask. */ -#define EVSYS_PRESC1_bp 1 /* Prescaler bit 1 position. */ -#define EVSYS_PRESC2_bm (1<<2) /* Prescaler bit 2 mask. */ -#define EVSYS_PRESC2_bp 2 /* Prescaler bit 2 position. */ - -/* NVM - Non Volatile Memory Controller */ -/* NVM.CMD bit masks and bit positions */ -#define NVM_CMD_gm 0x7F /* Command group mask. */ -#define NVM_CMD_gp 0 /* Command group position. */ -#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define NVM_CMD0_bp 0 /* Command bit 0 position. */ -#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define NVM_CMD1_bp 1 /* Command bit 1 position. */ -#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ -#define NVM_CMD2_bp 2 /* Command bit 2 position. */ -#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ -#define NVM_CMD3_bp 3 /* Command bit 3 position. */ -#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ -#define NVM_CMD4_bp 4 /* Command bit 4 position. */ -#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ -#define NVM_CMD5_bp 5 /* Command bit 5 position. */ -#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ -#define NVM_CMD6_bp 6 /* Command bit 6 position. */ - -/* NVM.CTRLA bit masks and bit positions */ -#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ -#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ - -/* NVM.CTRLB bit masks and bit positions */ -#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ -#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ - -#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ -#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ - -/* NVM.INTCTRL bit masks and bit positions */ -#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ -#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ -#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ -#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ -#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ -#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ - -#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ -#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ -#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ -#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ -#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ -#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ - -/* NVM.STATUS bit masks and bit positions */ -#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ -#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ - -#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ -#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ - -#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ -#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ - -#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ -#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ - -/* NVM.LOCKBITS bit masks and bit positions */ -#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ - -#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ - -#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ - -#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ -#define NVM_LB_gp 0 /* Lock Bits group position. */ -#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ -#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ - -/* ADC - Analog/Digital Converter */ -/* ADC_CH.CTRL bit masks and bit positions */ -#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ -#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ - -#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ -#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ -#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ -#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ -#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ -#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ -#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ -#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ - -#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ -#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ -#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ -#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ -#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ -#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ - -/* ADC_CH.MUXCTRL bit masks and bit positions */ -#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC Input group mask. */ -#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC Input group position. */ -#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC Input bit 0 mask. */ -#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC Input bit 0 position. */ -#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC Input bit 1 mask. */ -#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC Input bit 1 position. */ -#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC Input bit 2 mask. */ -#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC Input bit 2 position. */ -#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC Input bit 3 mask. */ -#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC Input bit 3 position. */ - -#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC Input group mask. */ -#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC Input group position. */ -#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC Input bit 0 mask. */ -#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC Input bit 0 position. */ -#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC Input bit 1 mask. */ -#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC Input bit 1 position. */ -#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC Input bit 2 mask. */ -#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC Input bit 2 position. */ -#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC Input bit 3 mask. */ -#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC Input bit 3 position. */ - -#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC Input group mask. */ -#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC Input group position. */ -#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC Input bit 0 mask. */ -#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC Input bit 0 position. */ -#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC Input bit 1 mask. */ -#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC Input bit 1 position. */ - -#define ADC_CH_MUXNEGL_gm 0x03 /* MUX selection on Negative ADC Input Gain on 4 LSB pins group mask. */ -#define ADC_CH_MUXNEGL_gp 0 /* MUX selection on Negative ADC Input Gain on 4 LSB pins group position. */ -#define ADC_CH_MUXNEGL0_bm (1<<0) /* MUX selection on Negative ADC Input Gain on 4 LSB pins bit 0 mask. */ -#define ADC_CH_MUXNEGL0_bp 0 /* MUX selection on Negative ADC Input Gain on 4 LSB pins bit 0 position. */ -#define ADC_CH_MUXNEGL1_bm (1<<1) /* MUX selection on Negative ADC Input Gain on 4 LSB pins bit 1 mask. */ -#define ADC_CH_MUXNEGL1_bp 1 /* MUX selection on Negative ADC Input Gain on 4 LSB pins bit 1 position. */ - -#define ADC_CH_MUXNEGH_gm 0x03 /* MUX selection on Negative ADC Input Gain on 4 MSB pins group mask. */ -#define ADC_CH_MUXNEGH_gp 0 /* MUX selection on Negative ADC Input Gain on 4 MSB pins group position. */ -#define ADC_CH_MUXNEGH0_bm (1<<0) /* MUX selection on Negative ADC Input Gain on 4 MSB pins bit 0 mask. */ -#define ADC_CH_MUXNEGH0_bp 0 /* MUX selection on Negative ADC Input Gain on 4 MSB pins bit 0 position. */ -#define ADC_CH_MUXNEGH1_bm (1<<1) /* MUX selection on Negative ADC Input Gain on 4 MSB pins bit 1 mask. */ -#define ADC_CH_MUXNEGH1_bp 1 /* MUX selection on Negative ADC Input Gain on 4 MSB pins bit 1 position. */ - -/* ADC_CH.INTCTRL bit masks and bit positions */ -#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ -#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ -#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ -#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ -#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ -#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ - -#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ -#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ - -/* ADC_CH.INTFLAGS bit masks and bit positions */ -#define ADC_CH_IF_bm 0x01 /* Channel Interrupt Flag bit mask. */ -#define ADC_CH_IF_bp 0 /* Channel Interrupt Flag bit position. */ - -/* ADC_CH.SCAN bit masks and bit positions */ -#define ADC_CH_INPUTOFFSET_gm 0xF0 /* Positive MUX Setting Offset group mask. */ -#define ADC_CH_INPUTOFFSET_gp 4 /* Positive MUX Setting Offset group position. */ -#define ADC_CH_INPUTOFFSET0_bm (1<<4) /* Positive MUX Setting Offset bit 0 mask. */ -#define ADC_CH_INPUTOFFSET0_bp 4 /* Positive MUX Setting Offset bit 0 position. */ -#define ADC_CH_INPUTOFFSET1_bm (1<<5) /* Positive MUX Setting Offset bit 1 mask. */ -#define ADC_CH_INPUTOFFSET1_bp 5 /* Positive MUX Setting Offset bit 1 position. */ -#define ADC_CH_INPUTOFFSET2_bm (1<<6) /* Positive MUX Setting Offset bit 2 mask. */ -#define ADC_CH_INPUTOFFSET2_bp 6 /* Positive MUX Setting Offset bit 2 position. */ -#define ADC_CH_INPUTOFFSET3_bm (1<<7) /* Positive MUX Setting Offset bit 3 mask. */ -#define ADC_CH_INPUTOFFSET3_bp 7 /* Positive MUX Setting Offset bit 3 position. */ - -#define ADC_CH_INPUTSCAN_gm 0x0F /* Number of Channels Included in Scan group mask. */ -#define ADC_CH_INPUTSCAN_gp 0 /* Number of Channels Included in Scan group position. */ -#define ADC_CH_INPUTSCAN0_bm (1<<0) /* Number of Channels Included in Scan bit 0 mask. */ -#define ADC_CH_INPUTSCAN0_bp 0 /* Number of Channels Included in Scan bit 0 position. */ -#define ADC_CH_INPUTSCAN1_bm (1<<1) /* Number of Channels Included in Scan bit 1 mask. */ -#define ADC_CH_INPUTSCAN1_bp 1 /* Number of Channels Included in Scan bit 1 position. */ -#define ADC_CH_INPUTSCAN2_bm (1<<2) /* Number of Channels Included in Scan bit 2 mask. */ -#define ADC_CH_INPUTSCAN2_bp 2 /* Number of Channels Included in Scan bit 2 position. */ -#define ADC_CH_INPUTSCAN3_bm (1<<3) /* Number of Channels Included in Scan bit 3 mask. */ -#define ADC_CH_INPUTSCAN3_bp 3 /* Number of Channels Included in Scan bit 3 position. */ - -/* ADC_CH.CORRCTRL bit masks and bit positions */ -#define ADC_CH_CORREN_bm 0x01 /* Correction Enable bit mask. */ -#define ADC_CH_CORREN_bp 0 /* Correction Enable bit position. */ - -/* ADC_CH.OFFSETCORR1 bit masks and bit positions */ -#define ADC_CH_OFFSETCORR_gm 0x0F /* Offset Correction Byte 1 group mask. */ -#define ADC_CH_OFFSETCORR_gp 0 /* Offset Correction Byte 1 group position. */ -#define ADC_CH_OFFSETCORR0_bm (1<<0) /* Offset Correction Byte 1 bit 0 mask. */ -#define ADC_CH_OFFSETCORR0_bp 0 /* Offset Correction Byte 1 bit 0 position. */ -#define ADC_CH_OFFSETCORR1_bm (1<<1) /* Offset Correction Byte 1 bit 1 mask. */ -#define ADC_CH_OFFSETCORR1_bp 1 /* Offset Correction Byte 1 bit 1 position. */ -#define ADC_CH_OFFSETCORR2_bm (1<<2) /* Offset Correction Byte 1 bit 2 mask. */ -#define ADC_CH_OFFSETCORR2_bp 2 /* Offset Correction Byte 1 bit 2 position. */ -#define ADC_CH_OFFSETCORR3_bm (1<<3) /* Offset Correction Byte 1 bit 3 mask. */ -#define ADC_CH_OFFSETCORR3_bp 3 /* Offset Correction Byte 1 bit 3 position. */ - -/* ADC_CH.GAINCORR1 bit masks and bit positions */ -#define ADC_CH_GAINCORR_gm 0x0F /* Gain Correction Byte 1 group mask. */ -#define ADC_CH_GAINCORR_gp 0 /* Gain Correction Byte 1 group position. */ -#define ADC_CH_GAINCORR0_bm (1<<0) /* Gain Correction Byte 1 bit 0 mask. */ -#define ADC_CH_GAINCORR0_bp 0 /* Gain Correction Byte 1 bit 0 position. */ -#define ADC_CH_GAINCORR1_bm (1<<1) /* Gain Correction Byte 1 bit 1 mask. */ -#define ADC_CH_GAINCORR1_bp 1 /* Gain Correction Byte 1 bit 1 position. */ -#define ADC_CH_GAINCORR2_bm (1<<2) /* Gain Correction Byte 1 bit 2 mask. */ -#define ADC_CH_GAINCORR2_bp 2 /* Gain Correction Byte 1 bit 2 position. */ -#define ADC_CH_GAINCORR3_bm (1<<3) /* Gain Correction Byte 1 bit 3 mask. */ -#define ADC_CH_GAINCORR3_bp 3 /* Gain Correction Byte 1 bit 3 position. */ - -/* ADC_CH.AVGCTRL bit masks and bit positions */ -#define ADC_CH_RIGHTSHIFT_gm 0x70 /* Right Shift group mask. */ -#define ADC_CH_RIGHTSHIFT_gp 4 /* Right Shift group position. */ -#define ADC_CH_RIGHTSHIFT0_bm (1<<4) /* Right Shift bit 0 mask. */ -#define ADC_CH_RIGHTSHIFT0_bp 4 /* Right Shift bit 0 position. */ -#define ADC_CH_RIGHTSHIFT1_bm (1<<5) /* Right Shift bit 1 mask. */ -#define ADC_CH_RIGHTSHIFT1_bp 5 /* Right Shift bit 1 position. */ -#define ADC_CH_RIGHTSHIFT2_bm (1<<6) /* Right Shift bit 2 mask. */ -#define ADC_CH_RIGHTSHIFT2_bp 6 /* Right Shift bit 2 position. */ - -#define ADC_CH_SAMPNUM_gm 0x0F /* Averaged Number of Samples group mask. */ -#define ADC_CH_SAMPNUM_gp 0 /* Averaged Number of Samples group position. */ -#define ADC_CH_SAMPNUM0_bm (1<<0) /* Averaged Number of Samples bit 0 mask. */ -#define ADC_CH_SAMPNUM0_bp 0 /* Averaged Number of Samples bit 0 position. */ -#define ADC_CH_SAMPNUM1_bm (1<<1) /* Averaged Number of Samples bit 1 mask. */ -#define ADC_CH_SAMPNUM1_bp 1 /* Averaged Number of Samples bit 1 position. */ -#define ADC_CH_SAMPNUM2_bm (1<<2) /* Averaged Number of Samples bit 2 mask. */ -#define ADC_CH_SAMPNUM2_bp 2 /* Averaged Number of Samples bit 2 position. */ -#define ADC_CH_SAMPNUM3_bm (1<<3) /* Averaged Number of Samples bit 3 mask. */ -#define ADC_CH_SAMPNUM3_bp 3 /* Averaged Number of Samples bit 3 position. */ - -/* ADC.CTRLA bit masks and bit positions */ -#define ADC_START_bm 0x04 /* Start Conversion bit mask. */ -#define ADC_START_bp 2 /* Start Conversion bit position. */ - -#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ -#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ - -#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ -#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ - -/* ADC.CTRLB bit masks and bit positions */ -#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ -#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ -#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ -#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ -#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ -#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ - -#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ -#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ - -#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ -#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ - -#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ -#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ -#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ -#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ -#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ -#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ - -/* ADC.REFCTRL bit masks and bit positions */ -#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ -#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ -#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ -#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ -#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ -#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ -#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ -#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ - -#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ -#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ - -#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ -#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ - -/* ADC.EVCTRL bit masks and bit positions */ -#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ -#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ -#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ -#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ -#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ -#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ -#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ -#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ - -#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ -#define ADC_EVACT_gp 0 /* Event Action Select group position. */ -#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ -#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ -#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ -#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ -#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ -#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ - -/* ADC.PRESCALER bit masks and bit positions */ -#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ -#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ -#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ -#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ -#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ -#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ -#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ -#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ - -/* ADC.INTFLAGS bit masks and bit positions */ -#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ -#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ - -/* ADC.SAMPCTRL bit masks and bit positions */ -#define ADC_SAMPVAL_gm 0x3F /* Sampling time control register group mask. */ -#define ADC_SAMPVAL_gp 0 /* Sampling time control register group position. */ -#define ADC_SAMPVAL0_bm (1<<0) /* Sampling time control register bit 0 mask. */ -#define ADC_SAMPVAL0_bp 0 /* Sampling time control register bit 0 position. */ -#define ADC_SAMPVAL1_bm (1<<1) /* Sampling time control register bit 1 mask. */ -#define ADC_SAMPVAL1_bp 1 /* Sampling time control register bit 1 position. */ -#define ADC_SAMPVAL2_bm (1<<2) /* Sampling time control register bit 2 mask. */ -#define ADC_SAMPVAL2_bp 2 /* Sampling time control register bit 2 position. */ -#define ADC_SAMPVAL3_bm (1<<3) /* Sampling time control register bit 3 mask. */ -#define ADC_SAMPVAL3_bp 3 /* Sampling time control register bit 3 position. */ -#define ADC_SAMPVAL4_bm (1<<4) /* Sampling time control register bit 4 mask. */ -#define ADC_SAMPVAL4_bp 4 /* Sampling time control register bit 4 position. */ -#define ADC_SAMPVAL5_bm (1<<5) /* Sampling time control register bit 5 mask. */ -#define ADC_SAMPVAL5_bp 5 /* Sampling time control register bit 5 position. */ - -/* DAC - Digital/Analog Converter */ -/* DAC.CTRLA bit masks and bit positions */ -#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ -#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ - -#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ -#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ - -#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ -#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ - -#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ -#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ - -#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ -#define DAC_ENABLE_bp 0 /* Enable bit position. */ - -/* DAC.CTRLB bit masks and bit positions */ -#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ -#define DAC_CHSEL_gp 5 /* Channel Select group position. */ -#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ -#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ -#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ -#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ - -#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ -#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ - -#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ -#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ - -/* DAC.CTRLC bit masks and bit positions */ -#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ -#define DAC_REFSEL_gp 3 /* Reference Select group position. */ -#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ -#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ -#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ -#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ - -#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ -#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ - -/* DAC.EVCTRL bit masks and bit positions */ -#define DAC_EVSPLIT_bm 0x08 /* Separate Event Channel Input for Channel 1 bit mask. */ -#define DAC_EVSPLIT_bp 3 /* Separate Event Channel Input for Channel 1 bit position. */ - -#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ -#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ -#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ -#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ -#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ -#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ -#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ -#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ - -/* DAC.STATUS bit masks and bit positions */ -#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ -#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ - -#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ -#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ - -/* DAC.CH0GAINCAL bit masks and bit positions */ -#define DAC_CH0GAINCAL_gm 0x7F /* Gain Calibration group mask. */ -#define DAC_CH0GAINCAL_gp 0 /* Gain Calibration group position. */ -#define DAC_CH0GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ -#define DAC_CH0GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ -#define DAC_CH0GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ -#define DAC_CH0GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ -#define DAC_CH0GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ -#define DAC_CH0GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ -#define DAC_CH0GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ -#define DAC_CH0GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ -#define DAC_CH0GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ -#define DAC_CH0GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ -#define DAC_CH0GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ -#define DAC_CH0GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ -#define DAC_CH0GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ -#define DAC_CH0GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ - -/* DAC.CH0OFFSETCAL bit masks and bit positions */ -#define DAC_CH0OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ -#define DAC_CH0OFFSETCAL_gp 0 /* Offset Calibration group position. */ -#define DAC_CH0OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ -#define DAC_CH0OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ -#define DAC_CH0OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ -#define DAC_CH0OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ -#define DAC_CH0OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ -#define DAC_CH0OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ -#define DAC_CH0OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ -#define DAC_CH0OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ -#define DAC_CH0OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ -#define DAC_CH0OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ -#define DAC_CH0OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ -#define DAC_CH0OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ -#define DAC_CH0OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ -#define DAC_CH0OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ - -/* DAC.CH1GAINCAL bit masks and bit positions */ -#define DAC_CH1GAINCAL_gm 0x7F /* Gain Calibration group mask. */ -#define DAC_CH1GAINCAL_gp 0 /* Gain Calibration group position. */ -#define DAC_CH1GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ -#define DAC_CH1GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ -#define DAC_CH1GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ -#define DAC_CH1GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ -#define DAC_CH1GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ -#define DAC_CH1GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ -#define DAC_CH1GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ -#define DAC_CH1GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ -#define DAC_CH1GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ -#define DAC_CH1GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ -#define DAC_CH1GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ -#define DAC_CH1GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ -#define DAC_CH1GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ -#define DAC_CH1GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ - -/* DAC.CH1OFFSETCAL bit masks and bit positions */ -#define DAC_CH1OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ -#define DAC_CH1OFFSETCAL_gp 0 /* Offset Calibration group position. */ -#define DAC_CH1OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ -#define DAC_CH1OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ -#define DAC_CH1OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ -#define DAC_CH1OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ -#define DAC_CH1OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ -#define DAC_CH1OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ -#define DAC_CH1OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ -#define DAC_CH1OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ -#define DAC_CH1OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ -#define DAC_CH1OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ -#define DAC_CH1OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ -#define DAC_CH1OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ -#define DAC_CH1OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ -#define DAC_CH1OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ - -/* AC - Analog Comparator */ -/* AC.AC0CTRL bit masks and bit positions */ -#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ -#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ -#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ -#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ -#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ -#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ - -#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ -#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ -#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ -#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ -#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ -#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ - -#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ -#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ -#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ -#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ -#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ -#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ - -#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ -#define AC_ENABLE_bp 0 /* Enable bit position. */ - -/* AC.AC1CTRL bit masks and bit positions */ -/* AC_INTMODE Predefined. */ -/* AC_INTMODE Predefined. */ - -/* AC_INTLVL Predefined. */ -/* AC_INTLVL Predefined. */ - -/* AC_HYSMODE Predefined. */ -/* AC_HYSMODE Predefined. */ - -/* AC_ENABLE Predefined. */ -/* AC_ENABLE Predefined. */ - -/* AC.AC0MUXCTRL bit masks and bit positions */ -#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ -#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ -#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ -#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ -#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ -#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ -#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ -#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ - -#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ -#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ -#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ -#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ -#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ -#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ -#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ -#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ - -/* AC.AC1MUXCTRL bit masks and bit positions */ -/* AC_MUXPOS Predefined. */ -/* AC_MUXPOS Predefined. */ - -/* AC_MUXNEG Predefined. */ -/* AC_MUXNEG Predefined. */ - -/* AC.CTRLA bit masks and bit positions */ -#define AC_AC1INVEN_bm 0x08 /* Analog Comparator 1 Output Invert Enable bit mask. */ -#define AC_AC1INVEN_bp 3 /* Analog Comparator 1 Output Invert Enable bit position. */ - -#define AC_AC0INVEN_bm 0x04 /* Analog Comparator 0 Output Invert Enable bit mask. */ -#define AC_AC0INVEN_bp 2 /* Analog Comparator 0 Output Invert Enable bit position. */ - -#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ -#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ - -#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ -#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ - -/* AC.CTRLB bit masks and bit positions */ -#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ -#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ -#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ -#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ -#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ -#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ -#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ -#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ -#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ -#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ -#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ -#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ -#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ -#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ - -/* AC.WINCTRL bit masks and bit positions */ -#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ -#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ - -#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ -#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ -#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ -#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ -#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ -#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ - -#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ -#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ -#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ -#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ -#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ -#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ - -/* AC.STATUS bit masks and bit positions */ -#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ -#define AC_WSTATE_gp 6 /* Window Mode State group position. */ -#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ -#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ -#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ -#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ - -#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ -#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ - -#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ -#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ - -#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ -#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ - -#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ -#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ - -#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ -#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ - -/* AC.CURRCTRL bit masks and bit positions */ -#define AC_CURREN_bm 0x80 /* Current Source Enable bit mask. */ -#define AC_CURREN_bp 7 /* Current Source Enable bit position. */ - -#define AC_CURRMODE_bm 0x40 /* Current Mode bit mask. */ -#define AC_CURRMODE_bp 6 /* Current Mode bit position. */ - -#define AC_AC1CURR_bm 0x02 /* Analog Comparator 1 current source output bit mask. */ -#define AC_AC1CURR_bp 1 /* Analog Comparator 1 current source output bit position. */ - -#define AC_AC0CURR_bm 0x01 /* Analog Comparator 0 current source output bit mask. */ -#define AC_AC0CURR_bp 0 /* Analog Comparator 0 current source output bit position. */ - -/* AC.CURRCALIB bit masks and bit positions */ -#define AC_CALIB_gm 0x0F /* Current Source Calibration group mask. */ -#define AC_CALIB_gp 0 /* Current Source Calibration group position. */ -#define AC_CALIB0_bm (1<<0) /* Current Source Calibration bit 0 mask. */ -#define AC_CALIB0_bp 0 /* Current Source Calibration bit 0 position. */ -#define AC_CALIB1_bm (1<<1) /* Current Source Calibration bit 1 mask. */ -#define AC_CALIB1_bp 1 /* Current Source Calibration bit 1 position. */ -#define AC_CALIB2_bm (1<<2) /* Current Source Calibration bit 2 mask. */ -#define AC_CALIB2_bp 2 /* Current Source Calibration bit 2 position. */ -#define AC_CALIB3_bm (1<<3) /* Current Source Calibration bit 3 mask. */ -#define AC_CALIB3_bp 3 /* Current Source Calibration bit 3 position. */ - -/* RTC - Real-Time Clounter */ -/* RTC.CTRL bit masks and bit positions */ -#define RTC_CORREN_bm 0x08 /* Correction Enable bit mask. */ -#define RTC_CORREN_bp 3 /* Correction Enable bit position. */ - -#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ -#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ -#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ -#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ -#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ -#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ -#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ -#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ - -/* RTC.STATUS bit masks and bit positions */ -#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ -#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ - -/* RTC.INTCTRL bit masks and bit positions */ -#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ -#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ -#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ -#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ -#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ -#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ - -#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ -#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ -#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ -#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ -#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ -#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ - -/* RTC.INTFLAGS bit masks and bit positions */ -#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ -#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ - -#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - -/* RTC.CALIB bit masks and bit positions */ -#define RTC_SIGN_bm 0x80 /* Correction Sign bit mask. */ -#define RTC_SIGN_bp 7 /* Correction Sign bit position. */ - -#define RTC_ERROR_gm 0x7F /* Error Value group mask. */ -#define RTC_ERROR_gp 0 /* Error Value group position. */ -#define RTC_ERROR0_bm (1<<0) /* Error Value bit 0 mask. */ -#define RTC_ERROR0_bp 0 /* Error Value bit 0 position. */ -#define RTC_ERROR1_bm (1<<1) /* Error Value bit 1 mask. */ -#define RTC_ERROR1_bp 1 /* Error Value bit 1 position. */ -#define RTC_ERROR2_bm (1<<2) /* Error Value bit 2 mask. */ -#define RTC_ERROR2_bp 2 /* Error Value bit 2 position. */ -#define RTC_ERROR3_bm (1<<3) /* Error Value bit 3 mask. */ -#define RTC_ERROR3_bp 3 /* Error Value bit 3 position. */ -#define RTC_ERROR4_bm (1<<4) /* Error Value bit 4 mask. */ -#define RTC_ERROR4_bp 4 /* Error Value bit 4 position. */ -#define RTC_ERROR5_bm (1<<5) /* Error Value bit 5 mask. */ -#define RTC_ERROR5_bp 5 /* Error Value bit 5 position. */ -#define RTC_ERROR6_bm (1<<6) /* Error Value bit 6 mask. */ -#define RTC_ERROR6_bp 6 /* Error Value bit 6 position. */ - -/* XCL - XMEGA Custom Logic */ -/* XCL.CTRLA bit masks and bit positions */ -#define XCL_LUT0OUTEN_gm 0xC0 /* LUT0 Output Enable group mask. */ -#define XCL_LUT0OUTEN_gp 6 /* LUT0 Output Enable group position. */ -#define XCL_LUT0OUTEN0_bm (1<<6) /* LUT0 Output Enable bit 0 mask. */ -#define XCL_LUT0OUTEN0_bp 6 /* LUT0 Output Enable bit 0 position. */ -#define XCL_LUT0OUTEN1_bm (1<<7) /* LUT0 Output Enable bit 1 mask. */ -#define XCL_LUT0OUTEN1_bp 7 /* LUT0 Output Enable bit 1 position. */ - -#define XCL_PORTSEL_gm 0x30 /* Port Selection group mask. */ -#define XCL_PORTSEL_gp 4 /* Port Selection group position. */ -#define XCL_PORTSEL0_bm (1<<4) /* Port Selection bit 0 mask. */ -#define XCL_PORTSEL0_bp 4 /* Port Selection bit 0 position. */ -#define XCL_PORTSEL1_bm (1<<5) /* Port Selection bit 1 mask. */ -#define XCL_PORTSEL1_bp 5 /* Port Selection bit 1 position. */ - -#define XCL_LUTCONF_gm 0x07 /* LUT Configuration group mask. */ -#define XCL_LUTCONF_gp 0 /* LUT Configuration group position. */ -#define XCL_LUTCONF0_bm (1<<0) /* LUT Configuration bit 0 mask. */ -#define XCL_LUTCONF0_bp 0 /* LUT Configuration bit 0 position. */ -#define XCL_LUTCONF1_bm (1<<1) /* LUT Configuration bit 1 mask. */ -#define XCL_LUTCONF1_bp 1 /* LUT Configuration bit 1 position. */ -#define XCL_LUTCONF2_bm (1<<2) /* LUT Configuration bit 2 mask. */ -#define XCL_LUTCONF2_bp 2 /* LUT Configuration bit 2 position. */ - -/* XCL.CTRLB bit masks and bit positions */ -#define XCL_IN3SEL_gm 0xC0 /* Input Selection 3 group mask. */ -#define XCL_IN3SEL_gp 6 /* Input Selection 3 group position. */ -#define XCL_IN3SEL0_bm (1<<6) /* Input Selection 3 bit 0 mask. */ -#define XCL_IN3SEL0_bp 6 /* Input Selection 3 bit 0 position. */ -#define XCL_IN3SEL1_bm (1<<7) /* Input Selection 3 bit 1 mask. */ -#define XCL_IN3SEL1_bp 7 /* Input Selection 3 bit 1 position. */ - -#define XCL_IN2SEL_gm 0x30 /* Input Selection 2 group mask. */ -#define XCL_IN2SEL_gp 4 /* Input Selection 2 group position. */ -#define XCL_IN2SEL0_bm (1<<4) /* Input Selection 2 bit 0 mask. */ -#define XCL_IN2SEL0_bp 4 /* Input Selection 2 bit 0 position. */ -#define XCL_IN2SEL1_bm (1<<5) /* Input Selection 2 bit 1 mask. */ -#define XCL_IN2SEL1_bp 5 /* Input Selection 2 bit 1 position. */ - -#define XCL_IN1SEL_gm 0x0C /* Input Selection 1 group mask. */ -#define XCL_IN1SEL_gp 2 /* Input Selection 1 group position. */ -#define XCL_IN1SEL0_bm (1<<2) /* Input Selection 1 bit 0 mask. */ -#define XCL_IN1SEL0_bp 2 /* Input Selection 1 bit 0 position. */ -#define XCL_IN1SEL1_bm (1<<3) /* Input Selection 1 bit 1 mask. */ -#define XCL_IN1SEL1_bp 3 /* Input Selection 1 bit 1 position. */ - -#define XCL_IN0SEL_gm 0x03 /* Input Selection 0 group mask. */ -#define XCL_IN0SEL_gp 0 /* Input Selection 0 group position. */ -#define XCL_IN0SEL0_bm (1<<0) /* Input Selection 0 bit 0 mask. */ -#define XCL_IN0SEL0_bp 0 /* Input Selection 0 bit 0 position. */ -#define XCL_IN0SEL1_bm (1<<1) /* Input Selection 0 bit 1 mask. */ -#define XCL_IN0SEL1_bp 1 /* Input Selection 0 bit 1 position. */ - -/* XCL.CTRLC bit masks and bit positions */ -#define XCL_EVASYSEL1_bm 0x80 /* Asynchronous Event Line Selection for LUT1 bit mask. */ -#define XCL_EVASYSEL1_bp 7 /* Asynchronous Event Line Selection for LUT1 bit position. */ - -#define XCL_EVASYSEL0_bm 0x40 /* Asynchronous Event Line Selection for LUT0 bit mask. */ -#define XCL_EVASYSEL0_bp 6 /* Asynchronous Event Line Selection for LUT0 bit position. */ - -#define XCL_DLYSEL_gm 0x30 /* Delay Selection group mask. */ -#define XCL_DLYSEL_gp 4 /* Delay Selection group position. */ -#define XCL_DLYSEL0_bm (1<<4) /* Delay Selection bit 0 mask. */ -#define XCL_DLYSEL0_bp 4 /* Delay Selection bit 0 position. */ -#define XCL_DLYSEL1_bm (1<<5) /* Delay Selection bit 1 mask. */ -#define XCL_DLYSEL1_bp 5 /* Delay Selection bit 1 position. */ - -#define XCL_DLY1CONF_gm 0x0C /* Delay Configuration on LUT1 group mask. */ -#define XCL_DLY1CONF_gp 2 /* Delay Configuration on LUT1 group position. */ -#define XCL_DLY1CONF0_bm (1<<2) /* Delay Configuration on LUT1 bit 0 mask. */ -#define XCL_DLY1CONF0_bp 2 /* Delay Configuration on LUT1 bit 0 position. */ -#define XCL_DLY1CONF1_bm (1<<3) /* Delay Configuration on LUT1 bit 1 mask. */ -#define XCL_DLY1CONF1_bp 3 /* Delay Configuration on LUT1 bit 1 position. */ - -#define XCL_DLY0CONF_gm 0x03 /* Delay Configuration on LUT0 group mask. */ -#define XCL_DLY0CONF_gp 0 /* Delay Configuration on LUT0 group position. */ -#define XCL_DLY0CONF0_bm (1<<0) /* Delay Configuration on LUT0 bit 0 mask. */ -#define XCL_DLY0CONF0_bp 0 /* Delay Configuration on LUT0 bit 0 position. */ -#define XCL_DLY0CONF1_bm (1<<1) /* Delay Configuration on LUT0 bit 1 mask. */ -#define XCL_DLY0CONF1_bp 1 /* Delay Configuration on LUT0 bit 1 position. */ - -/* XCL.CTRLD bit masks and bit positions */ -#define XCL_TRUTH1_gm 0xF0 /* Truth Table of LUT1 group mask. */ -#define XCL_TRUTH1_gp 4 /* Truth Table of LUT1 group position. */ -#define XCL_TRUTH10_bm (1<<4) /* Truth Table of LUT1 bit 0 mask. */ -#define XCL_TRUTH10_bp 4 /* Truth Table of LUT1 bit 0 position. */ -#define XCL_TRUTH11_bm (1<<5) /* Truth Table of LUT1 bit 1 mask. */ -#define XCL_TRUTH11_bp 5 /* Truth Table of LUT1 bit 1 position. */ -#define XCL_TRUTH12_bm (1<<6) /* Truth Table of LUT1 bit 2 mask. */ -#define XCL_TRUTH12_bp 6 /* Truth Table of LUT1 bit 2 position. */ -#define XCL_TRUTH13_bm (1<<7) /* Truth Table of LUT1 bit 3 mask. */ -#define XCL_TRUTH13_bp 7 /* Truth Table of LUT1 bit 3 position. */ - -#define XCL_TRUTH0_gm 0x0F /* Truth Table of LUT0 group mask. */ -#define XCL_TRUTH0_gp 0 /* Truth Table of LUT0 group position. */ -#define XCL_TRUTH00_bm (1<<0) /* Truth Table of LUT0 bit 0 mask. */ -#define XCL_TRUTH00_bp 0 /* Truth Table of LUT0 bit 0 position. */ -#define XCL_TRUTH01_bm (1<<1) /* Truth Table of LUT0 bit 1 mask. */ -#define XCL_TRUTH01_bp 1 /* Truth Table of LUT0 bit 1 position. */ -#define XCL_TRUTH02_bm (1<<2) /* Truth Table of LUT0 bit 2 mask. */ -#define XCL_TRUTH02_bp 2 /* Truth Table of LUT0 bit 2 position. */ -#define XCL_TRUTH03_bm (1<<3) /* Truth Table of LUT0 bit 3 mask. */ -#define XCL_TRUTH03_bp 3 /* Truth Table of LUT0 bit 3 position. */ - -/* XCL.CTRLE bit masks and bit positions */ -#define XCL_CMDSEL_bm 0x80 /* Timer/Counter Command Selection bit mask. */ -#define XCL_CMDSEL_bp 7 /* Timer/Counter Command Selection bit position. */ - -#define XCL_TCSEL_gm 0x70 /* Timer/Counter Selection group mask. */ -#define XCL_TCSEL_gp 4 /* Timer/Counter Selection group position. */ -#define XCL_TCSEL0_bm (1<<4) /* Timer/Counter Selection bit 0 mask. */ -#define XCL_TCSEL0_bp 4 /* Timer/Counter Selection bit 0 position. */ -#define XCL_TCSEL1_bm (1<<5) /* Timer/Counter Selection bit 1 mask. */ -#define XCL_TCSEL1_bp 5 /* Timer/Counter Selection bit 1 position. */ -#define XCL_TCSEL2_bm (1<<6) /* Timer/Counter Selection bit 2 mask. */ -#define XCL_TCSEL2_bp 6 /* Timer/Counter Selection bit 2 position. */ - -#define XCL_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define XCL_CLKSEL_gp 0 /* Clock Selection group position. */ -#define XCL_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define XCL_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define XCL_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define XCL_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define XCL_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define XCL_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define XCL_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define XCL_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - -/* XCL.CTRLF bit masks and bit positions */ -#define XCL_CMDEN_gm 0xC0 /* Command Enable group mask. */ -#define XCL_CMDEN_gp 6 /* Command Enable group position. */ -#define XCL_CMDEN0_bm (1<<6) /* Command Enable bit 0 mask. */ -#define XCL_CMDEN0_bp 6 /* Command Enable bit 0 position. */ -#define XCL_CMDEN1_bm (1<<7) /* Command Enable bit 1 mask. */ -#define XCL_CMDEN1_bp 7 /* Command Enable bit 1 position. */ - -#define XCL_CMP1_bm 0x20 /* Compare Channel 1 Output Value bit mask. */ -#define XCL_CMP1_bp 5 /* Compare Channel 1 Output Value bit position. */ - -#define XCL_CMP0_bm 0x10 /* Compare Channel 0 Output Value bit mask. */ -#define XCL_CMP0_bp 4 /* Compare Channel 0 Output Value bit position. */ - -#define XCL_CCEN1_bm 0x08 /* Compare or Capture Channel 1 Enable bit mask. */ -#define XCL_CCEN1_bp 3 /* Compare or Capture Channel 1 Enable bit position. */ - -#define XCL_CCEN0_bm 0x04 /* Compare or Capture Channel 0 Enable bit mask. */ -#define XCL_CCEN0_bp 2 /* Compare or Capture Channel 0 Enable bit position. */ - -#define XCL_MODE_gm 0x03 /* Timer/Counter Mode group mask. */ -#define XCL_MODE_gp 0 /* Timer/Counter Mode group position. */ -#define XCL_MODE0_bm (1<<0) /* Timer/Counter Mode bit 0 mask. */ -#define XCL_MODE0_bp 0 /* Timer/Counter Mode bit 0 position. */ -#define XCL_MODE1_bm (1<<1) /* Timer/Counter Mode bit 1 mask. */ -#define XCL_MODE1_bp 1 /* Timer/Counter Mode bit 1 position. */ - -/* XCL.CTRLG bit masks and bit positions */ -#define XCL_EVACTEN_bm 0x80 /* Event Action Enable bit mask. */ -#define XCL_EVACTEN_bp 7 /* Event Action Enable bit position. */ - -#define XCL_EVACT1_gm 0x60 /* Event Action Selection on Timer/Counter 1 group mask. */ -#define XCL_EVACT1_gp 5 /* Event Action Selection on Timer/Counter 1 group position. */ -#define XCL_EVACT10_bm (1<<5) /* Event Action Selection on Timer/Counter 1 bit 0 mask. */ -#define XCL_EVACT10_bp 5 /* Event Action Selection on Timer/Counter 1 bit 0 position. */ -#define XCL_EVACT11_bm (1<<6) /* Event Action Selection on Timer/Counter 1 bit 1 mask. */ -#define XCL_EVACT11_bp 6 /* Event Action Selection on Timer/Counter 1 bit 1 position. */ - -#define XCL_EVACT0_gm 0x18 /* Event Action Selection on Timer/Counter 0 group mask. */ -#define XCL_EVACT0_gp 3 /* Event Action Selection on Timer/Counter 0 group position. */ -#define XCL_EVACT00_bm (1<<3) /* Event Action Selection on Timer/Counter 0 bit 0 mask. */ -#define XCL_EVACT00_bp 3 /* Event Action Selection on Timer/Counter 0 bit 0 position. */ -#define XCL_EVACT01_bm (1<<4) /* Event Action Selection on Timer/Counter 0 bit 1 mask. */ -#define XCL_EVACT01_bp 4 /* Event Action Selection on Timer/Counter 0 bit 1 position. */ - -#define XCL_EVSRC_gm 0x07 /* Event Source Selection group mask. */ -#define XCL_EVSRC_gp 0 /* Event Source Selection group position. */ -#define XCL_EVSRC0_bm (1<<0) /* Event Source Selection bit 0 mask. */ -#define XCL_EVSRC0_bp 0 /* Event Source Selection bit 0 position. */ -#define XCL_EVSRC1_bm (1<<1) /* Event Source Selection bit 1 mask. */ -#define XCL_EVSRC1_bp 1 /* Event Source Selection bit 1 position. */ -#define XCL_EVSRC2_bm (1<<2) /* Event Source Selection bit 2 mask. */ -#define XCL_EVSRC2_bp 2 /* Event Source Selection bit 2 position. */ - -/* XCL.INTCTRL bit masks and bit positions */ -#define XCL_UNF1IE_bm 0x80 /* Underflow 1 Interrupt Enable bit mask. */ -#define XCL_UNF1IE_bp 7 /* Underflow 1 Interrupt Enable bit position. */ - -#define XCL_PEC1IE_bm 0x80 /* Peripheral Counter 1 Interrupt Enable bit mask. */ -#define XCL_PEC1IE_bp 7 /* Peripheral Counter 1 Interrupt Enable bit position. */ - -#define XCL_PEC21IE_bm 0x80 /* Peripheral High Counter 2 Interrupt Enable bit mask. */ -#define XCL_PEC21IE_bp 7 /* Peripheral High Counter 2 Interrupt Enable bit position. */ - -#define XCL_UNF0IE_bm 0x40 /* Underflow 0 Interrupt Enable bit mask. */ -#define XCL_UNF0IE_bp 6 /* Underflow 0 Interrupt Enable bit position. */ - -#define XCL_PEC0IE_bm 0x40 /* Peripheral Counter 0 Interrupt Enable bit mask. */ -#define XCL_PEC0IE_bp 6 /* Peripheral Counter 0 Interrupt Enable bit position. */ - -#define XCL_CC1IE_bm 0x20 /* Compare Or Capture 1 Interrupt Enable bit mask. */ -#define XCL_CC1IE_bp 5 /* Compare Or Capture 1 Interrupt Enable bit position. */ - -#define XCL_PEC20IE_bm 0x20 /* Peripheral Low Counter 2 Interrupt Enable bit mask. */ -#define XCL_PEC20IE_bp 5 /* Peripheral Low Counter 2 Interrupt Enable bit position. */ - -#define XCL_CC0IE_bm 0x10 /* Compare Or Capture 0 Interrupt Enable bit mask. */ -#define XCL_CC0IE_bp 4 /* Compare Or Capture 0 Interrupt Enable bit position. */ - -#define XCL_UNFINTLVL_gm 0x0C /* Timer Underflow Interrupt Level group mask. */ -#define XCL_UNFINTLVL_gp 2 /* Timer Underflow Interrupt Level group position. */ -#define XCL_UNFINTLVL0_bm (1<<2) /* Timer Underflow Interrupt Level bit 0 mask. */ -#define XCL_UNFINTLVL0_bp 2 /* Timer Underflow Interrupt Level bit 0 position. */ -#define XCL_UNFINTLVL1_bm (1<<3) /* Timer Underflow Interrupt Level bit 1 mask. */ -#define XCL_UNFINTLVL1_bp 3 /* Timer Underflow Interrupt Level bit 1 position. */ - -#define XCL_CCINTLVL_gm 0x03 /* Timer Compare or Capture Interrupt Level group mask. */ -#define XCL_CCINTLVL_gp 0 /* Timer Compare or Capture Interrupt Level group position. */ -#define XCL_CCINTLVL0_bm (1<<0) /* Timer Compare or Capture Interrupt Level bit 0 mask. */ -#define XCL_CCINTLVL0_bp 0 /* Timer Compare or Capture Interrupt Level bit 0 position. */ -#define XCL_CCINTLVL1_bm (1<<1) /* Timer Compare or Capture Interrupt Level bit 1 mask. */ -#define XCL_CCINTLVL1_bp 1 /* Timer Compare or Capture Interrupt Level bit 1 position. */ - -/* XCL.INTFLAGS bit masks and bit positions */ -#define XCL_UNF1IF_bm 0x80 /* Timer/Counter 1 Underflow Interrupt Flag bit mask. */ -#define XCL_UNF1IF_bp 7 /* Timer/Counter 1 Underflow Interrupt Flag bit position. */ - -#define XCL_PEC1IF_bm 0x80 /* Peripheral Counter 1 Interrupt Flag bit mask. */ -#define XCL_PEC1IF_bp 7 /* Peripheral Counter 1 Interrupt Flag bit position. */ - -#define XCL_PEC21IF_bm 0x80 /* Peripheral High Counter 2 Interrupt Flag bit mask. */ -#define XCL_PEC21IF_bp 7 /* Peripheral High Counter 2 Interrupt Flag bit position. */ - -#define XCL_UNF0IF_bm 0x40 /* Timer/Counter 0 Underflow Interrupt Flag bit mask. */ -#define XCL_UNF0IF_bp 6 /* Timer/Counter 0 Underflow Interrupt Flag bit position. */ - -#define XCL_PEC0IF_bm 0x40 /* Peripheral Counter 0 Interrupt Flag bit mask. */ -#define XCL_PEC0IF_bp 6 /* Peripheral Counter 0 Interrupt Flag bit position. */ - -#define XCL_CC1IF_bm 0x20 /* Compare or Capture Channel 1 Interrupt Flag bit mask. */ -#define XCL_CC1IF_bp 5 /* Compare or Capture Channel 1 Interrupt Flag bit position. */ - -#define XCL_PEC20IF_bm 0x20 /* Peripheral Low Counter 2 Interrupt Flag bit mask. */ -#define XCL_PEC20IF_bp 5 /* Peripheral Low Counter 2 Interrupt Flag bit position. */ - -#define XCL_CC0IF_bm 0x10 /* Compare or Capture Channel 0 Interrupt Flag bit mask. */ -#define XCL_CC0IF_bp 4 /* Compare or Capture Channel 0 Interrupt Flag bit position. */ - -/* XCL.PLC bit masks and bit positions */ -#define XCL_PLC_gm 0xFF /* Peripheral Lenght Control Bits group mask. */ -#define XCL_PLC_gp 0 /* Peripheral Lenght Control Bits group position. */ -#define XCL_PLC0_bm (1<<0) /* Peripheral Lenght Control Bits bit 0 mask. */ -#define XCL_PLC0_bp 0 /* Peripheral Lenght Control Bits bit 0 position. */ -#define XCL_PLC1_bm (1<<1) /* Peripheral Lenght Control Bits bit 1 mask. */ -#define XCL_PLC1_bp 1 /* Peripheral Lenght Control Bits bit 1 position. */ -#define XCL_PLC2_bm (1<<2) /* Peripheral Lenght Control Bits bit 2 mask. */ -#define XCL_PLC2_bp 2 /* Peripheral Lenght Control Bits bit 2 position. */ -#define XCL_PLC3_bm (1<<3) /* Peripheral Lenght Control Bits bit 3 mask. */ -#define XCL_PLC3_bp 3 /* Peripheral Lenght Control Bits bit 3 position. */ -#define XCL_PLC4_bm (1<<4) /* Peripheral Lenght Control Bits bit 4 mask. */ -#define XCL_PLC4_bp 4 /* Peripheral Lenght Control Bits bit 4 position. */ -#define XCL_PLC5_bm (1<<5) /* Peripheral Lenght Control Bits bit 5 mask. */ -#define XCL_PLC5_bp 5 /* Peripheral Lenght Control Bits bit 5 position. */ -#define XCL_PLC6_bm (1<<6) /* Peripheral Lenght Control Bits bit 6 mask. */ -#define XCL_PLC6_bp 6 /* Peripheral Lenght Control Bits bit 6 position. */ -#define XCL_PLC7_bm (1<<7) /* Peripheral Lenght Control Bits bit 7 mask. */ -#define XCL_PLC7_bp 7 /* Peripheral Lenght Control Bits bit 7 position. */ - -/* XCL.CNTL bit masks and bit positions */ -#define XCL_BCNTO_gm 0xFF /* BTC0 Counter Byte group mask. */ -#define XCL_BCNTO_gp 0 /* BTC0 Counter Byte group position. */ -#define XCL_BCNTO0_bm (1<<0) /* BTC0 Counter Byte bit 0 mask. */ -#define XCL_BCNTO0_bp 0 /* BTC0 Counter Byte bit 0 position. */ -#define XCL_BCNTO1_bm (1<<1) /* BTC0 Counter Byte bit 1 mask. */ -#define XCL_BCNTO1_bp 1 /* BTC0 Counter Byte bit 1 position. */ -#define XCL_BCNTO2_bm (1<<2) /* BTC0 Counter Byte bit 2 mask. */ -#define XCL_BCNTO2_bp 2 /* BTC0 Counter Byte bit 2 position. */ -#define XCL_BCNTO3_bm (1<<3) /* BTC0 Counter Byte bit 3 mask. */ -#define XCL_BCNTO3_bp 3 /* BTC0 Counter Byte bit 3 position. */ -#define XCL_BCNTO4_bm (1<<4) /* BTC0 Counter Byte bit 4 mask. */ -#define XCL_BCNTO4_bp 4 /* BTC0 Counter Byte bit 4 position. */ -#define XCL_BCNTO5_bm (1<<5) /* BTC0 Counter Byte bit 5 mask. */ -#define XCL_BCNTO5_bp 5 /* BTC0 Counter Byte bit 5 position. */ -#define XCL_BCNTO6_bm (1<<6) /* BTC0 Counter Byte bit 6 mask. */ -#define XCL_BCNTO6_bp 6 /* BTC0 Counter Byte bit 6 position. */ -#define XCL_BCNTO7_bm (1<<7) /* BTC0 Counter Byte bit 7 mask. */ -#define XCL_BCNTO7_bp 7 /* BTC0 Counter Byte bit 7 position. */ - -#define XCL_CNTL_gm 0xFF /* TC16 Counter Low Byte group mask. */ -#define XCL_CNTL_gp 0 /* TC16 Counter Low Byte group position. */ -#define XCL_CNTL0_bm (1<<0) /* TC16 Counter Low Byte bit 0 mask. */ -#define XCL_CNTL0_bp 0 /* TC16 Counter Low Byte bit 0 position. */ -#define XCL_CNTL1_bm (1<<1) /* TC16 Counter Low Byte bit 1 mask. */ -#define XCL_CNTL1_bp 1 /* TC16 Counter Low Byte bit 1 position. */ -#define XCL_CNTL2_bm (1<<2) /* TC16 Counter Low Byte bit 2 mask. */ -#define XCL_CNTL2_bp 2 /* TC16 Counter Low Byte bit 2 position. */ -#define XCL_CNTL3_bm (1<<3) /* TC16 Counter Low Byte bit 3 mask. */ -#define XCL_CNTL3_bp 3 /* TC16 Counter Low Byte bit 3 position. */ -#define XCL_CNTL4_bm (1<<4) /* TC16 Counter Low Byte bit 4 mask. */ -#define XCL_CNTL4_bp 4 /* TC16 Counter Low Byte bit 4 position. */ -#define XCL_CNTL5_bm (1<<5) /* TC16 Counter Low Byte bit 5 mask. */ -#define XCL_CNTL5_bp 5 /* TC16 Counter Low Byte bit 5 position. */ -#define XCL_CNTL6_bm (1<<6) /* TC16 Counter Low Byte bit 6 mask. */ -#define XCL_CNTL6_bp 6 /* TC16 Counter Low Byte bit 6 position. */ -#define XCL_CNTL7_bm (1<<7) /* TC16 Counter Low Byte bit 7 mask. */ -#define XCL_CNTL7_bp 7 /* TC16 Counter Low Byte bit 7 position. */ - -#define XCL_PCNTO_gm 0xFF /* Peripheral Counter 0 Byte group mask. */ -#define XCL_PCNTO_gp 0 /* Peripheral Counter 0 Byte group position. */ -#define XCL_PCNTO0_bm (1<<0) /* Peripheral Counter 0 Byte bit 0 mask. */ -#define XCL_PCNTO0_bp 0 /* Peripheral Counter 0 Byte bit 0 position. */ -#define XCL_PCNTO1_bm (1<<1) /* Peripheral Counter 0 Byte bit 1 mask. */ -#define XCL_PCNTO1_bp 1 /* Peripheral Counter 0 Byte bit 1 position. */ -#define XCL_PCNTO2_bm (1<<2) /* Peripheral Counter 0 Byte bit 2 mask. */ -#define XCL_PCNTO2_bp 2 /* Peripheral Counter 0 Byte bit 2 position. */ -#define XCL_PCNTO3_bm (1<<3) /* Peripheral Counter 0 Byte bit 3 mask. */ -#define XCL_PCNTO3_bp 3 /* Peripheral Counter 0 Byte bit 3 position. */ -#define XCL_PCNTO4_bm (1<<4) /* Peripheral Counter 0 Byte bit 4 mask. */ -#define XCL_PCNTO4_bp 4 /* Peripheral Counter 0 Byte bit 4 position. */ -#define XCL_PCNTO5_bm (1<<5) /* Peripheral Counter 0 Byte bit 5 mask. */ -#define XCL_PCNTO5_bp 5 /* Peripheral Counter 0 Byte bit 5 position. */ -#define XCL_PCNTO6_bm (1<<6) /* Peripheral Counter 0 Byte bit 6 mask. */ -#define XCL_PCNTO6_bp 6 /* Peripheral Counter 0 Byte bit 6 position. */ -#define XCL_PCNTO7_bm (1<<7) /* Peripheral Counter 0 Byte bit 7 mask. */ -#define XCL_PCNTO7_bp 7 /* Peripheral Counter 0 Byte bit 7 position. */ - -/* XCL.CNTH bit masks and bit positions */ -#define XCL_BCNT1_gm 0xFF /* BTC1 Counter Byte group mask. */ -#define XCL_BCNT1_gp 0 /* BTC1 Counter Byte group position. */ -#define XCL_BCNT10_bm (1<<0) /* BTC1 Counter Byte bit 0 mask. */ -#define XCL_BCNT10_bp 0 /* BTC1 Counter Byte bit 0 position. */ -#define XCL_BCNT11_bm (1<<1) /* BTC1 Counter Byte bit 1 mask. */ -#define XCL_BCNT11_bp 1 /* BTC1 Counter Byte bit 1 position. */ -#define XCL_BCNT12_bm (1<<2) /* BTC1 Counter Byte bit 2 mask. */ -#define XCL_BCNT12_bp 2 /* BTC1 Counter Byte bit 2 position. */ -#define XCL_BCNT13_bm (1<<3) /* BTC1 Counter Byte bit 3 mask. */ -#define XCL_BCNT13_bp 3 /* BTC1 Counter Byte bit 3 position. */ -#define XCL_BCNT14_bm (1<<4) /* BTC1 Counter Byte bit 4 mask. */ -#define XCL_BCNT14_bp 4 /* BTC1 Counter Byte bit 4 position. */ -#define XCL_BCNT15_bm (1<<5) /* BTC1 Counter Byte bit 5 mask. */ -#define XCL_BCNT15_bp 5 /* BTC1 Counter Byte bit 5 position. */ -#define XCL_BCNT16_bm (1<<6) /* BTC1 Counter Byte bit 6 mask. */ -#define XCL_BCNT16_bp 6 /* BTC1 Counter Byte bit 6 position. */ -#define XCL_BCNT17_bm (1<<7) /* BTC1 Counter Byte bit 7 mask. */ -#define XCL_BCNT17_bp 7 /* BTC1 Counter Byte bit 7 position. */ - -#define XCL_CNTH_gm 0xFF /* TC16 Counter High Byte group mask. */ -#define XCL_CNTH_gp 0 /* TC16 Counter High Byte group position. */ -#define XCL_CNTH0_bm (1<<0) /* TC16 Counter High Byte bit 0 mask. */ -#define XCL_CNTH0_bp 0 /* TC16 Counter High Byte bit 0 position. */ -#define XCL_CNTH1_bm (1<<1) /* TC16 Counter High Byte bit 1 mask. */ -#define XCL_CNTH1_bp 1 /* TC16 Counter High Byte bit 1 position. */ -#define XCL_CNTH2_bm (1<<2) /* TC16 Counter High Byte bit 2 mask. */ -#define XCL_CNTH2_bp 2 /* TC16 Counter High Byte bit 2 position. */ -#define XCL_CNTH3_bm (1<<3) /* TC16 Counter High Byte bit 3 mask. */ -#define XCL_CNTH3_bp 3 /* TC16 Counter High Byte bit 3 position. */ -#define XCL_CNTH4_bm (1<<4) /* TC16 Counter High Byte bit 4 mask. */ -#define XCL_CNTH4_bp 4 /* TC16 Counter High Byte bit 4 position. */ -#define XCL_CNTH5_bm (1<<5) /* TC16 Counter High Byte bit 5 mask. */ -#define XCL_CNTH5_bp 5 /* TC16 Counter High Byte bit 5 position. */ -#define XCL_CNTH6_bm (1<<6) /* TC16 Counter High Byte bit 6 mask. */ -#define XCL_CNTH6_bp 6 /* TC16 Counter High Byte bit 6 position. */ -#define XCL_CNTH7_bm (1<<7) /* TC16 Counter High Byte bit 7 mask. */ -#define XCL_CNTH7_bp 7 /* TC16 Counter High Byte bit 7 position. */ - -#define XCL_PCNT1_gm 0xFF /* Peripheral Counter 1 Byte group mask. */ -#define XCL_PCNT1_gp 0 /* Peripheral Counter 1 Byte group position. */ -#define XCL_PCNT10_bm (1<<0) /* Peripheral Counter 1 Byte bit 0 mask. */ -#define XCL_PCNT10_bp 0 /* Peripheral Counter 1 Byte bit 0 position. */ -#define XCL_PCNT11_bm (1<<1) /* Peripheral Counter 1 Byte bit 1 mask. */ -#define XCL_PCNT11_bp 1 /* Peripheral Counter 1 Byte bit 1 position. */ -#define XCL_PCNT12_bm (1<<2) /* Peripheral Counter 1 Byte bit 2 mask. */ -#define XCL_PCNT12_bp 2 /* Peripheral Counter 1 Byte bit 2 position. */ -#define XCL_PCNT13_bm (1<<3) /* Peripheral Counter 1 Byte bit 3 mask. */ -#define XCL_PCNT13_bp 3 /* Peripheral Counter 1 Byte bit 3 position. */ -#define XCL_PCNT14_bm (1<<4) /* Peripheral Counter 1 Byte bit 4 mask. */ -#define XCL_PCNT14_bp 4 /* Peripheral Counter 1 Byte bit 4 position. */ -#define XCL_PCNT15_bm (1<<5) /* Peripheral Counter 1 Byte bit 5 mask. */ -#define XCL_PCNT15_bp 5 /* Peripheral Counter 1 Byte bit 5 position. */ -#define XCL_PCNT16_bm (1<<6) /* Peripheral Counter 1 Byte bit 6 mask. */ -#define XCL_PCNT16_bp 6 /* Peripheral Counter 1 Byte bit 6 position. */ -#define XCL_PCNT17_bm (1<<7) /* Peripheral Counter 1 Byte bit 7 mask. */ -#define XCL_PCNT17_bp 7 /* Peripheral Counter 1 Byte bit 7 position. */ - -#define XCL_PCNT21_gm 0xF0 /* Peripheral High Counter 2 Bits group mask. */ -#define XCL_PCNT21_gp 4 /* Peripheral High Counter 2 Bits group position. */ -#define XCL_PCNT210_bm (1<<4) /* Peripheral High Counter 2 Bits bit 0 mask. */ -#define XCL_PCNT210_bp 4 /* Peripheral High Counter 2 Bits bit 0 position. */ -#define XCL_PCNT211_bm (1<<5) /* Peripheral High Counter 2 Bits bit 1 mask. */ -#define XCL_PCNT211_bp 5 /* Peripheral High Counter 2 Bits bit 1 position. */ -#define XCL_PCNT212_bm (1<<6) /* Peripheral High Counter 2 Bits bit 2 mask. */ -#define XCL_PCNT212_bp 6 /* Peripheral High Counter 2 Bits bit 2 position. */ -#define XCL_PCNT213_bm (1<<7) /* Peripheral High Counter 2 Bits bit 3 mask. */ -#define XCL_PCNT213_bp 7 /* Peripheral High Counter 2 Bits bit 3 position. */ - -#define XCL_PCNT20_gm 0x0F /* Peripheral Low Counter 2 Bits group mask. */ -#define XCL_PCNT20_gp 0 /* Peripheral Low Counter 2 Bits group position. */ -#define XCL_PCNT200_bm (1<<0) /* Peripheral Low Counter 2 Bits bit 0 mask. */ -#define XCL_PCNT200_bp 0 /* Peripheral Low Counter 2 Bits bit 0 position. */ -#define XCL_PCNT201_bm (1<<1) /* Peripheral Low Counter 2 Bits bit 1 mask. */ -#define XCL_PCNT201_bp 1 /* Peripheral Low Counter 2 Bits bit 1 position. */ -#define XCL_PCNT202_bm (1<<2) /* Peripheral Low Counter 2 Bits bit 2 mask. */ -#define XCL_PCNT202_bp 2 /* Peripheral Low Counter 2 Bits bit 2 position. */ -#define XCL_PCNT203_bm (1<<3) /* Peripheral Low Counter 2 Bits bit 3 mask. */ -#define XCL_PCNT203_bp 3 /* Peripheral Low Counter 2 Bits bit 3 position. */ - -/* XCL.CMPL bit masks and bit positions */ -#define XCL_CMPL_gm 0xFF /* TC16 Compare Low Byte group mask. */ -#define XCL_CMPL_gp 0 /* TC16 Compare Low Byte group position. */ -#define XCL_CMPL0_bm (1<<0) /* TC16 Compare Low Byte bit 0 mask. */ -#define XCL_CMPL0_bp 0 /* TC16 Compare Low Byte bit 0 position. */ -#define XCL_CMPL1_bm (1<<1) /* TC16 Compare Low Byte bit 1 mask. */ -#define XCL_CMPL1_bp 1 /* TC16 Compare Low Byte bit 1 position. */ -#define XCL_CMPL2_bm (1<<2) /* TC16 Compare Low Byte bit 2 mask. */ -#define XCL_CMPL2_bp 2 /* TC16 Compare Low Byte bit 2 position. */ -#define XCL_CMPL3_bm (1<<3) /* TC16 Compare Low Byte bit 3 mask. */ -#define XCL_CMPL3_bp 3 /* TC16 Compare Low Byte bit 3 position. */ -#define XCL_CMPL4_bm (1<<4) /* TC16 Compare Low Byte bit 4 mask. */ -#define XCL_CMPL4_bp 4 /* TC16 Compare Low Byte bit 4 position. */ -#define XCL_CMPL5_bm (1<<5) /* TC16 Compare Low Byte bit 5 mask. */ -#define XCL_CMPL5_bp 5 /* TC16 Compare Low Byte bit 5 position. */ -#define XCL_CMPL6_bm (1<<6) /* TC16 Compare Low Byte bit 6 mask. */ -#define XCL_CMPL6_bp 6 /* TC16 Compare Low Byte bit 6 position. */ -#define XCL_CMPL7_bm (1<<7) /* TC16 Compare Low Byte bit 7 mask. */ -#define XCL_CMPL7_bp 7 /* TC16 Compare Low Byte bit 7 position. */ - -#define XCL_BCMP0_gm 0xFF /* BTC0 Compare Byte group mask. */ -#define XCL_BCMP0_gp 0 /* BTC0 Compare Byte group position. */ -#define XCL_BCMP00_bm (1<<0) /* BTC0 Compare Byte bit 0 mask. */ -#define XCL_BCMP00_bp 0 /* BTC0 Compare Byte bit 0 position. */ -#define XCL_BCMP01_bm (1<<1) /* BTC0 Compare Byte bit 1 mask. */ -#define XCL_BCMP01_bp 1 /* BTC0 Compare Byte bit 1 position. */ -#define XCL_BCMP02_bm (1<<2) /* BTC0 Compare Byte bit 2 mask. */ -#define XCL_BCMP02_bp 2 /* BTC0 Compare Byte bit 2 position. */ -#define XCL_BCMP03_bm (1<<3) /* BTC0 Compare Byte bit 3 mask. */ -#define XCL_BCMP03_bp 3 /* BTC0 Compare Byte bit 3 position. */ -#define XCL_BCMP04_bm (1<<4) /* BTC0 Compare Byte bit 4 mask. */ -#define XCL_BCMP04_bp 4 /* BTC0 Compare Byte bit 4 position. */ -#define XCL_BCMP05_bm (1<<5) /* BTC0 Compare Byte bit 5 mask. */ -#define XCL_BCMP05_bp 5 /* BTC0 Compare Byte bit 5 position. */ -#define XCL_BCMP06_bm (1<<6) /* BTC0 Compare Byte bit 6 mask. */ -#define XCL_BCMP06_bp 6 /* BTC0 Compare Byte bit 6 position. */ -#define XCL_BCMP07_bm (1<<7) /* BTC0 Compare Byte bit 7 mask. */ -#define XCL_BCMP07_bp 7 /* BTC0 Compare Byte bit 7 position. */ - -/* XCL.CMPH bit masks and bit positions */ -#define XCL_CMPH_gm 0xFF /* TC16 Compare High Byte group mask. */ -#define XCL_CMPH_gp 0 /* TC16 Compare High Byte group position. */ -#define XCL_CMPH0_bm (1<<0) /* TC16 Compare High Byte bit 0 mask. */ -#define XCL_CMPH0_bp 0 /* TC16 Compare High Byte bit 0 position. */ -#define XCL_CMPH1_bm (1<<1) /* TC16 Compare High Byte bit 1 mask. */ -#define XCL_CMPH1_bp 1 /* TC16 Compare High Byte bit 1 position. */ -#define XCL_CMPH2_bm (1<<2) /* TC16 Compare High Byte bit 2 mask. */ -#define XCL_CMPH2_bp 2 /* TC16 Compare High Byte bit 2 position. */ -#define XCL_CMPH3_bm (1<<3) /* TC16 Compare High Byte bit 3 mask. */ -#define XCL_CMPH3_bp 3 /* TC16 Compare High Byte bit 3 position. */ -#define XCL_CMPH4_bm (1<<4) /* TC16 Compare High Byte bit 4 mask. */ -#define XCL_CMPH4_bp 4 /* TC16 Compare High Byte bit 4 position. */ -#define XCL_CMPH5_bm (1<<5) /* TC16 Compare High Byte bit 5 mask. */ -#define XCL_CMPH5_bp 5 /* TC16 Compare High Byte bit 5 position. */ -#define XCL_CMPH6_bm (1<<6) /* TC16 Compare High Byte bit 6 mask. */ -#define XCL_CMPH6_bp 6 /* TC16 Compare High Byte bit 6 position. */ -#define XCL_CMPH7_bm (1<<7) /* TC16 Compare High Byte bit 7 mask. */ -#define XCL_CMPH7_bp 7 /* TC16 Compare High Byte bit 7 position. */ - -#define XCL_BCMP1_gm 0xFF /* BTC1 Compare Byte group mask. */ -#define XCL_BCMP1_gp 0 /* BTC1 Compare Byte group position. */ -#define XCL_BCMP10_bm (1<<0) /* BTC1 Compare Byte bit 0 mask. */ -#define XCL_BCMP10_bp 0 /* BTC1 Compare Byte bit 0 position. */ -#define XCL_BCMP11_bm (1<<1) /* BTC1 Compare Byte bit 1 mask. */ -#define XCL_BCMP11_bp 1 /* BTC1 Compare Byte bit 1 position. */ -#define XCL_BCMP12_bm (1<<2) /* BTC1 Compare Byte bit 2 mask. */ -#define XCL_BCMP12_bp 2 /* BTC1 Compare Byte bit 2 position. */ -#define XCL_BCMP13_bm (1<<3) /* BTC1 Compare Byte bit 3 mask. */ -#define XCL_BCMP13_bp 3 /* BTC1 Compare Byte bit 3 position. */ -#define XCL_BCMP14_bm (1<<4) /* BTC1 Compare Byte bit 4 mask. */ -#define XCL_BCMP14_bp 4 /* BTC1 Compare Byte bit 4 position. */ -#define XCL_BCMP15_bm (1<<5) /* BTC1 Compare Byte bit 5 mask. */ -#define XCL_BCMP15_bp 5 /* BTC1 Compare Byte bit 5 position. */ -#define XCL_BCMP16_bm (1<<6) /* BTC1 Compare Byte bit 6 mask. */ -#define XCL_BCMP16_bp 6 /* BTC1 Compare Byte bit 6 position. */ -#define XCL_BCMP17_bm (1<<7) /* BTC1 Compare Byte bit 7 mask. */ -#define XCL_BCMP17_bp 7 /* BTC1 Compare Byte bit 7 position. */ - -/* XCL.PERCAPTL bit masks and bit positions */ -#define XCL_PERL_gm 0xFF /* TC16 Low Byte Period group mask. */ -#define XCL_PERL_gp 0 /* TC16 Low Byte Period group position. */ -#define XCL_PERL0_bm (1<<0) /* TC16 Low Byte Period bit 0 mask. */ -#define XCL_PERL0_bp 0 /* TC16 Low Byte Period bit 0 position. */ -#define XCL_PERL1_bm (1<<1) /* TC16 Low Byte Period bit 1 mask. */ -#define XCL_PERL1_bp 1 /* TC16 Low Byte Period bit 1 position. */ -#define XCL_PERL2_bm (1<<2) /* TC16 Low Byte Period bit 2 mask. */ -#define XCL_PERL2_bp 2 /* TC16 Low Byte Period bit 2 position. */ -#define XCL_PERL3_bm (1<<3) /* TC16 Low Byte Period bit 3 mask. */ -#define XCL_PERL3_bp 3 /* TC16 Low Byte Period bit 3 position. */ -#define XCL_PERL4_bm (1<<4) /* TC16 Low Byte Period bit 4 mask. */ -#define XCL_PERL4_bp 4 /* TC16 Low Byte Period bit 4 position. */ -#define XCL_PERL5_bm (1<<5) /* TC16 Low Byte Period bit 5 mask. */ -#define XCL_PERL5_bp 5 /* TC16 Low Byte Period bit 5 position. */ -#define XCL_PERL6_bm (1<<6) /* TC16 Low Byte Period bit 6 mask. */ -#define XCL_PERL6_bp 6 /* TC16 Low Byte Period bit 6 position. */ -#define XCL_PERL7_bm (1<<7) /* TC16 Low Byte Period bit 7 mask. */ -#define XCL_PERL7_bp 7 /* TC16 Low Byte Period bit 7 position. */ - -#define XCL_CAPTL_gm 0xFF /* TC16 Capture Value Low Byte group mask. */ -#define XCL_CAPTL_gp 0 /* TC16 Capture Value Low Byte group position. */ -#define XCL_CAPTL0_bm (1<<0) /* TC16 Capture Value Low Byte bit 0 mask. */ -#define XCL_CAPTL0_bp 0 /* TC16 Capture Value Low Byte bit 0 position. */ -#define XCL_CAPTL1_bm (1<<1) /* TC16 Capture Value Low Byte bit 1 mask. */ -#define XCL_CAPTL1_bp 1 /* TC16 Capture Value Low Byte bit 1 position. */ -#define XCL_CAPTL2_bm (1<<2) /* TC16 Capture Value Low Byte bit 2 mask. */ -#define XCL_CAPTL2_bp 2 /* TC16 Capture Value Low Byte bit 2 position. */ -#define XCL_CAPTL3_bm (1<<3) /* TC16 Capture Value Low Byte bit 3 mask. */ -#define XCL_CAPTL3_bp 3 /* TC16 Capture Value Low Byte bit 3 position. */ -#define XCL_CAPTL4_bm (1<<4) /* TC16 Capture Value Low Byte bit 4 mask. */ -#define XCL_CAPTL4_bp 4 /* TC16 Capture Value Low Byte bit 4 position. */ -#define XCL_CAPTL5_bm (1<<5) /* TC16 Capture Value Low Byte bit 5 mask. */ -#define XCL_CAPTL5_bp 5 /* TC16 Capture Value Low Byte bit 5 position. */ -#define XCL_CAPTL6_bm (1<<6) /* TC16 Capture Value Low Byte bit 6 mask. */ -#define XCL_CAPTL6_bp 6 /* TC16 Capture Value Low Byte bit 6 position. */ -#define XCL_CAPTL7_bm (1<<7) /* TC16 Capture Value Low Byte bit 7 mask. */ -#define XCL_CAPTL7_bp 7 /* TC16 Capture Value Low Byte bit 7 position. */ - -#define XCL_BPER0_gm 0xFF /* BTC0 Period group mask. */ -#define XCL_BPER0_gp 0 /* BTC0 Period group position. */ -#define XCL_BPER00_bm (1<<0) /* BTC0 Period bit 0 mask. */ -#define XCL_BPER00_bp 0 /* BTC0 Period bit 0 position. */ -#define XCL_BPER01_bm (1<<1) /* BTC0 Period bit 1 mask. */ -#define XCL_BPER01_bp 1 /* BTC0 Period bit 1 position. */ -#define XCL_BPER02_bm (1<<2) /* BTC0 Period bit 2 mask. */ -#define XCL_BPER02_bp 2 /* BTC0 Period bit 2 position. */ -#define XCL_BPER03_bm (1<<3) /* BTC0 Period bit 3 mask. */ -#define XCL_BPER03_bp 3 /* BTC0 Period bit 3 position. */ -#define XCL_BPER04_bm (1<<4) /* BTC0 Period bit 4 mask. */ -#define XCL_BPER04_bp 4 /* BTC0 Period bit 4 position. */ -#define XCL_BPER05_bm (1<<5) /* BTC0 Period bit 5 mask. */ -#define XCL_BPER05_bp 5 /* BTC0 Period bit 5 position. */ -#define XCL_BPER06_bm (1<<6) /* BTC0 Period bit 6 mask. */ -#define XCL_BPER06_bp 6 /* BTC0 Period bit 6 position. */ -#define XCL_BPER07_bm (1<<7) /* BTC0 Period bit 7 mask. */ -#define XCL_BPER07_bp 7 /* BTC0 Period bit 7 position. */ - -#define XCL_BCAPT0_gm 0xFF /* BTC0 Capture Value Byte group mask. */ -#define XCL_BCAPT0_gp 0 /* BTC0 Capture Value Byte group position. */ -#define XCL_BCAPT00_bm (1<<0) /* BTC0 Capture Value Byte bit 0 mask. */ -#define XCL_BCAPT00_bp 0 /* BTC0 Capture Value Byte bit 0 position. */ -#define XCL_BCAPT01_bm (1<<1) /* BTC0 Capture Value Byte bit 1 mask. */ -#define XCL_BCAPT01_bp 1 /* BTC0 Capture Value Byte bit 1 position. */ -#define XCL_BCAPT02_bm (1<<2) /* BTC0 Capture Value Byte bit 2 mask. */ -#define XCL_BCAPT02_bp 2 /* BTC0 Capture Value Byte bit 2 position. */ -#define XCL_BCAPT03_bm (1<<3) /* BTC0 Capture Value Byte bit 3 mask. */ -#define XCL_BCAPT03_bp 3 /* BTC0 Capture Value Byte bit 3 position. */ -#define XCL_BCAPT04_bm (1<<4) /* BTC0 Capture Value Byte bit 4 mask. */ -#define XCL_BCAPT04_bp 4 /* BTC0 Capture Value Byte bit 4 position. */ -#define XCL_BCAPT05_bm (1<<5) /* BTC0 Capture Value Byte bit 5 mask. */ -#define XCL_BCAPT05_bp 5 /* BTC0 Capture Value Byte bit 5 position. */ -#define XCL_BCAPT06_bm (1<<6) /* BTC0 Capture Value Byte bit 6 mask. */ -#define XCL_BCAPT06_bp 6 /* BTC0 Capture Value Byte bit 6 position. */ -#define XCL_BCAPT07_bm (1<<7) /* BTC0 Capture Value Byte bit 7 mask. */ -#define XCL_BCAPT07_bp 7 /* BTC0 Capture Value Byte bit 7 position. */ - -/* XCL.PERCAPTH bit masks and bit positions */ -#define XCL_PERH_gm 0xFF /* TC16 High Byte Period group mask. */ -#define XCL_PERH_gp 0 /* TC16 High Byte Period group position. */ -#define XCL_PERH0_bm (1<<0) /* TC16 High Byte Period bit 0 mask. */ -#define XCL_PERH0_bp 0 /* TC16 High Byte Period bit 0 position. */ -#define XCL_PERH1_bm (1<<1) /* TC16 High Byte Period bit 1 mask. */ -#define XCL_PERH1_bp 1 /* TC16 High Byte Period bit 1 position. */ -#define XCL_PERH2_bm (1<<2) /* TC16 High Byte Period bit 2 mask. */ -#define XCL_PERH2_bp 2 /* TC16 High Byte Period bit 2 position. */ -#define XCL_PERH3_bm (1<<3) /* TC16 High Byte Period bit 3 mask. */ -#define XCL_PERH3_bp 3 /* TC16 High Byte Period bit 3 position. */ -#define XCL_PERH4_bm (1<<4) /* TC16 High Byte Period bit 4 mask. */ -#define XCL_PERH4_bp 4 /* TC16 High Byte Period bit 4 position. */ -#define XCL_PERH5_bm (1<<5) /* TC16 High Byte Period bit 5 mask. */ -#define XCL_PERH5_bp 5 /* TC16 High Byte Period bit 5 position. */ -#define XCL_PERH6_bm (1<<6) /* TC16 High Byte Period bit 6 mask. */ -#define XCL_PERH6_bp 6 /* TC16 High Byte Period bit 6 position. */ -#define XCL_PERH7_bm (1<<7) /* TC16 High Byte Period bit 7 mask. */ -#define XCL_PERH7_bp 7 /* TC16 High Byte Period bit 7 position. */ - -#define XCL_CAPTH_gm 0xFF /* TC16 Capture Value High Byte group mask. */ -#define XCL_CAPTH_gp 0 /* TC16 Capture Value High Byte group position. */ -#define XCL_CAPTH0_bm (1<<0) /* TC16 Capture Value High Byte bit 0 mask. */ -#define XCL_CAPTH0_bp 0 /* TC16 Capture Value High Byte bit 0 position. */ -#define XCL_CAPTH1_bm (1<<1) /* TC16 Capture Value High Byte bit 1 mask. */ -#define XCL_CAPTH1_bp 1 /* TC16 Capture Value High Byte bit 1 position. */ -#define XCL_CAPTH2_bm (1<<2) /* TC16 Capture Value High Byte bit 2 mask. */ -#define XCL_CAPTH2_bp 2 /* TC16 Capture Value High Byte bit 2 position. */ -#define XCL_CAPTH3_bm (1<<3) /* TC16 Capture Value High Byte bit 3 mask. */ -#define XCL_CAPTH3_bp 3 /* TC16 Capture Value High Byte bit 3 position. */ -#define XCL_CAPTH4_bm (1<<4) /* TC16 Capture Value High Byte bit 4 mask. */ -#define XCL_CAPTH4_bp 4 /* TC16 Capture Value High Byte bit 4 position. */ -#define XCL_CAPTH5_bm (1<<5) /* TC16 Capture Value High Byte bit 5 mask. */ -#define XCL_CAPTH5_bp 5 /* TC16 Capture Value High Byte bit 5 position. */ -#define XCL_CAPTH6_bm (1<<6) /* TC16 Capture Value High Byte bit 6 mask. */ -#define XCL_CAPTH6_bp 6 /* TC16 Capture Value High Byte bit 6 position. */ -#define XCL_CAPTH7_bm (1<<7) /* TC16 Capture Value High Byte bit 7 mask. */ -#define XCL_CAPTH7_bp 7 /* TC16 Capture Value High Byte bit 7 position. */ - -#define XCL_BPER1_gm 0xFF /* BTC1 Period group mask. */ -#define XCL_BPER1_gp 0 /* BTC1 Period group position. */ -#define XCL_BPER10_bm (1<<0) /* BTC1 Period bit 0 mask. */ -#define XCL_BPER10_bp 0 /* BTC1 Period bit 0 position. */ -#define XCL_BPER11_bm (1<<1) /* BTC1 Period bit 1 mask. */ -#define XCL_BPER11_bp 1 /* BTC1 Period bit 1 position. */ -#define XCL_BPER12_bm (1<<2) /* BTC1 Period bit 2 mask. */ -#define XCL_BPER12_bp 2 /* BTC1 Period bit 2 position. */ -#define XCL_BPER13_bm (1<<3) /* BTC1 Period bit 3 mask. */ -#define XCL_BPER13_bp 3 /* BTC1 Period bit 3 position. */ -#define XCL_BPER14_bm (1<<4) /* BTC1 Period bit 4 mask. */ -#define XCL_BPER14_bp 4 /* BTC1 Period bit 4 position. */ -#define XCL_BPER15_bm (1<<5) /* BTC1 Period bit 5 mask. */ -#define XCL_BPER15_bp 5 /* BTC1 Period bit 5 position. */ -#define XCL_BPER16_bm (1<<6) /* BTC1 Period bit 6 mask. */ -#define XCL_BPER16_bp 6 /* BTC1 Period bit 6 position. */ -#define XCL_BPER17_bm (1<<7) /* BTC1 Period bit 7 mask. */ -#define XCL_BPER17_bp 7 /* BTC1 Period bit 7 position. */ - -#define XCL_BCAPT1_gm 0xFF /* BTC1 Capture Value Byte group mask. */ -#define XCL_BCAPT1_gp 0 /* BTC1 Capture Value Byte group position. */ -#define XCL_BCAPT10_bm (1<<0) /* BTC1 Capture Value Byte bit 0 mask. */ -#define XCL_BCAPT10_bp 0 /* BTC1 Capture Value Byte bit 0 position. */ -#define XCL_BCAPT11_bm (1<<1) /* BTC1 Capture Value Byte bit 1 mask. */ -#define XCL_BCAPT11_bp 1 /* BTC1 Capture Value Byte bit 1 position. */ -#define XCL_BCAPT12_bm (1<<2) /* BTC1 Capture Value Byte bit 2 mask. */ -#define XCL_BCAPT12_bp 2 /* BTC1 Capture Value Byte bit 2 position. */ -#define XCL_BCAPT13_bm (1<<3) /* BTC1 Capture Value Byte bit 3 mask. */ -#define XCL_BCAPT13_bp 3 /* BTC1 Capture Value Byte bit 3 position. */ -#define XCL_BCAPT14_bm (1<<4) /* BTC1 Capture Value Byte bit 4 mask. */ -#define XCL_BCAPT14_bp 4 /* BTC1 Capture Value Byte bit 4 position. */ -#define XCL_BCAPT15_bm (1<<5) /* BTC1 Capture Value Byte bit 5 mask. */ -#define XCL_BCAPT15_bp 5 /* BTC1 Capture Value Byte bit 5 position. */ -#define XCL_BCAPT16_bm (1<<6) /* BTC1 Capture Value Byte bit 6 mask. */ -#define XCL_BCAPT16_bp 6 /* BTC1 Capture Value Byte bit 6 position. */ -#define XCL_BCAPT17_bm (1<<7) /* BTC1 Capture Value Byte bit 7 mask. */ -#define XCL_BCAPT17_bp 7 /* BTC1 Capture Value Byte bit 7 position. */ - -/* TWI - Two-Wire Interface */ -/* TWI.CTRL bit masks and bit positions */ -#define TWI_BRIDGEEN_bm 0x80 /* Bridge Enable bit mask. */ -#define TWI_BRIDGEEN_bp 7 /* Bridge Enable bit position. */ - -#define TWI_SFMPEN_bm 0x40 /* Slave Fast Mode Plus Enable bit mask. */ -#define TWI_SFMPEN_bp 6 /* Slave Fast Mode Plus Enable bit position. */ - -#define TWI_SSDAHOLD_gm 0x30 /* Slave SDA Hold Time Enable group mask. */ -#define TWI_SSDAHOLD_gp 4 /* Slave SDA Hold Time Enable group position. */ -#define TWI_SSDAHOLD0_bm (1<<4) /* Slave SDA Hold Time Enable bit 0 mask. */ -#define TWI_SSDAHOLD0_bp 4 /* Slave SDA Hold Time Enable bit 0 position. */ -#define TWI_SSDAHOLD1_bm (1<<5) /* Slave SDA Hold Time Enable bit 1 mask. */ -#define TWI_SSDAHOLD1_bp 5 /* Slave SDA Hold Time Enable bit 1 position. */ - -#define TWI_FMPEN_bm 0x08 /* FMPLUS Enable bit mask. */ -#define TWI_FMPEN_bp 3 /* FMPLUS Enable bit position. */ - -#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ -#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ -#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ -#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ -#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ -#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ - -#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ -#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ - -/* TWI_MASTER.CTRLA bit masks and bit positions */ -#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ -#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ - -#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ -#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ - -#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ -#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ - -#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ -#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ - -/* TWI_MASTER.CTRLB bit masks and bit positions */ -#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ -#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ -#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ -#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ -#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ -#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ - -#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ -#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ - -#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ - -#define TWI_MASTER_TTOUTEN_bm 0x10 /* Ttimeout Enable bit mask. */ -#define TWI_MASTER_TTOUTEN_bp 4 /* Ttimeout Enable bit position. */ - -#define TWI_MASTER_TSEXTEN_bm 0x20 /* Slave Extend Timeout Enable bit mask. */ -#define TWI_MASTER_TSEXTEN_bp 5 /* Slave Extend Timeout Enable bit position. */ - -#define TWI_MASTER_TMEXTEN_bm 0x40 /* Master Extend Timeout Enable bit mask. */ -#define TWI_MASTER_TMEXTEN_bp 6 /* Master Extend Timeout Enable bit position. */ - -#define TWI_MASTER_TOIE_bm 0x80 /* Timeout Interrupt Enable bit mask. */ -#define TWI_MASTER_TOIE_bp 7 /* Timeout Interrupt Enable bit position. */ - -/* TWI_MASTER.CTRLC bit masks and bit positions */ -#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ - -#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ -#define TWI_MASTER_CMD_gp 0 /* Command group position. */ -#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ -#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ - -/* TWI_MASTER.STATUS bit masks and bit positions */ -#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ -#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ - -#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ -#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ - -#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ - -#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ - -#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ -#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ - -#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ -#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ - -#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ -#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ -#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ -#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ -#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ -#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ - -/* TWI_SLAVE.CTRLA bit masks and bit positions */ -#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ -#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ - -#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ -#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ - -#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ -#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ - -#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ -#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ - -#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ -#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ - -#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ -#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ - -#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ - -/* TWI_SLAVE.CTRLB bit masks and bit positions */ -#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ - -#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ -#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ -#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ -#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ - -#define TWI_SLAVE_TTOUTEN_bm 0x10 /* Ttimeout Enable bit mask. */ -#define TWI_SLAVE_TTOUTEN_bp 4 /* Ttimeout Enable bit position. */ - -#define TWI_SLAVE_TOIE_bm 0x80 /* Timeout Interrupt Enable bit mask. */ -#define TWI_SLAVE_TOIE_bp 7 /* Timeout Interrupt Enable bit position. */ - -/* TWI_SLAVE.STATUS bit masks and bit positions */ -#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ -#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ - -#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ -#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ - -#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ - -#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ - -#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ -#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ - -#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ -#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ - -#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ -#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ - -#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ -#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ - -/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ -#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ -#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ -#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ -#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ -#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ -#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ -#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ -#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ -#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ -#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ -#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ -#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ -#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ -#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ -#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ -#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ - -#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ -#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ - -/* TWI_TIMEOUT.TOS bit masks and bit positions */ -#define TWI_TIMEOUT_TTOUTMIF_bm 0x01 /* Master Ttimeout Interrupt Flag bit mask. */ -#define TWI_TIMEOUT_TTOUTMIF_bp 0 /* Master Ttimeout Interrupt Flag bit position. */ - -#define TWI_TIMEOUT_TSEXTIF_bm 0x02 /* Slave Extend Interrupt Flag bit mask. */ -#define TWI_TIMEOUT_TSEXTIF_bp 1 /* Slave Extend Interrupt Flag bit position. */ - -#define TWI_TIMEOUT_TMEXTIF_bm 0x04 /* Master Extend Interrupt Flag bit mask. */ -#define TWI_TIMEOUT_TMEXTIF_bp 2 /* Master Extend Interrupt Flag bit position. */ - -#define TWI_TIMEOUT_TTOUTSIF_bm 0x10 /* Slave Ttimeout Interrupt Flag bit mask. */ -#define TWI_TIMEOUT_TTOUTSIF_bp 4 /* Slave Ttimeout Interrupt Flag bit position. */ - -/* TWI_TIMEOUT.TOCONF bit masks and bit positions */ -#define TWI_TIMEOUT_TTOUTMSEL_gm 0x07 /* Master Ttimeout Select group mask. */ -#define TWI_TIMEOUT_TTOUTMSEL_gp 0 /* Master Ttimeout Select group position. */ -#define TWI_TIMEOUT_TTOUTMSEL0_bm (1<<0) /* Master Ttimeout Select bit 0 mask. */ -#define TWI_TIMEOUT_TTOUTMSEL0_bp 0 /* Master Ttimeout Select bit 0 position. */ -#define TWI_TIMEOUT_TTOUTMSEL1_bm (1<<1) /* Master Ttimeout Select bit 1 mask. */ -#define TWI_TIMEOUT_TTOUTMSEL1_bp 1 /* Master Ttimeout Select bit 1 position. */ -#define TWI_TIMEOUT_TTOUTMSEL2_bm (1<<2) /* Master Ttimeout Select bit 2 mask. */ -#define TWI_TIMEOUT_TTOUTMSEL2_bp 2 /* Master Ttimeout Select bit 2 position. */ - -#define TWI_TIMEOUT_TMSEXTSEL_gm 0x18 /* Master/Slave Timeout Select group mask. */ -#define TWI_TIMEOUT_TMSEXTSEL_gp 3 /* Master/Slave Timeout Select group position. */ -#define TWI_TIMEOUT_TMSEXTSEL0_bm (1<<3) /* Master/Slave Timeout Select bit 0 mask. */ -#define TWI_TIMEOUT_TMSEXTSEL0_bp 3 /* Master/Slave Timeout Select bit 0 position. */ -#define TWI_TIMEOUT_TMSEXTSEL1_bm (1<<4) /* Master/Slave Timeout Select bit 1 mask. */ -#define TWI_TIMEOUT_TMSEXTSEL1_bp 4 /* Master/Slave Timeout Select bit 1 position. */ - -#define TWI_TIMEOUT_TTOUTSSEL_gm 0xE0 /* Slave Ttimeout Select group mask. */ -#define TWI_TIMEOUT_TTOUTSSEL_gp 5 /* Slave Ttimeout Select group position. */ -#define TWI_TIMEOUT_TTOUTSSEL0_bm (1<<5) /* Slave Ttimeout Select bit 0 mask. */ -#define TWI_TIMEOUT_TTOUTSSEL0_bp 5 /* Slave Ttimeout Select bit 0 position. */ -#define TWI_TIMEOUT_TTOUTSSEL1_bm (1<<6) /* Slave Ttimeout Select bit 1 mask. */ -#define TWI_TIMEOUT_TTOUTSSEL1_bp 6 /* Slave Ttimeout Select bit 1 position. */ -#define TWI_TIMEOUT_TTOUTSSEL2_bm (1<<7) /* Slave Ttimeout Select bit 2 mask. */ -#define TWI_TIMEOUT_TTOUTSSEL2_bp 7 /* Slave Ttimeout Select bit 2 position. */ - -/* PORT - Port Configuration */ -/* PORT.INTCTRL bit masks and bit positions */ -#define PORT_INTLVL_gm 0x03 /* Port Interrupt Level group mask. */ -#define PORT_INTLVL_gp 0 /* Port Interrupt Level group position. */ -#define PORT_INTLVL0_bm (1<<0) /* Port Interrupt Level bit 0 mask. */ -#define PORT_INTLVL0_bp 0 /* Port Interrupt Level bit 0 position. */ -#define PORT_INTLVL1_bm (1<<1) /* Port Interrupt Level bit 1 mask. */ -#define PORT_INTLVL1_bp 1 /* Port Interrupt Level bit 1 position. */ - -/* PORT.INTFLAGS bit masks and bit positions */ -#define PORT_INT7IF_bm 0x80 /* Pin 7 Interrupt Flag bit mask. */ -#define PORT_INT7IF_bp 7 /* Pin 7 Interrupt Flag bit position. */ - -#define PORT_INT6IF_bm 0x40 /* Pin 6 Interrupt Flag bit mask. */ -#define PORT_INT6IF_bp 6 /* Pin 6 Interrupt Flag bit position. */ - -#define PORT_INT5IF_bm 0x20 /* Pin 5 Interrupt Flag bit mask. */ -#define PORT_INT5IF_bp 5 /* Pin 5 Interrupt Flag bit position. */ - -#define PORT_INT4IF_bm 0x10 /* Pin 4 Interrupt Flag bit mask. */ -#define PORT_INT4IF_bp 4 /* Pin 4 Interrupt Flag bit position. */ - -#define PORT_INT3IF_bm 0x08 /* Pin 3 Interrupt Flag bit mask. */ -#define PORT_INT3IF_bp 3 /* Pin 3 Interrupt Flag bit position. */ - -#define PORT_INT2IF_bm 0x04 /* Pin 2 Interrupt Flag bit mask. */ -#define PORT_INT2IF_bp 2 /* Pin 2 Interrupt Flag bit position. */ - -#define PORT_INT1IF_bm 0x02 /* Pin 1 Interrupt Flag bit mask. */ -#define PORT_INT1IF_bp 1 /* Pin 1 Interrupt Flag bit position. */ - -#define PORT_INT0IF_bm 0x01 /* Pin 0 Interrupt Flag bit mask. */ -#define PORT_INT0IF_bp 0 /* Pin 0 Interrupt Flag bit position. */ - -/* PORT.REMAP bit masks and bit positions */ -#define PORT_USART0_bm 0x10 /* Usart0 bit mask. */ -#define PORT_USART0_bp 4 /* Usart0 bit position. */ - -#define PORT_TC4D_bm 0x08 /* Timer/Counter 4 Output Compare D bit mask. */ -#define PORT_TC4D_bp 3 /* Timer/Counter 4 Output Compare D bit position. */ - -#define PORT_TC4C_bm 0x04 /* Timer/Counter 4 Output Compare C bit mask. */ -#define PORT_TC4C_bp 2 /* Timer/Counter 4 Output Compare C bit position. */ - -#define PORT_TC4B_bm 0x02 /* Timer/Counter 4 Output Compare B bit mask. */ -#define PORT_TC4B_bp 1 /* Timer/Counter 4 Output Compare B bit position. */ - -#define PORT_TC4A_bm 0x01 /* Timer/Counter 4 Output Compare A bit mask. */ -#define PORT_TC4A_bp 0 /* Timer/Counter 4 Output Compare A bit position. */ - -/* PORT.PIN0CTRL bit masks and bit positions */ -#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ -#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ - -#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ -#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ -#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ -#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ -#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ -#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ -#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ -#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ - -#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ -#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ -#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ -#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ -#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ -#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ -#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ -#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ - -/* PORT.PIN1CTRL bit masks and bit positions */ -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN2CTRL bit masks and bit positions */ -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN3CTRL bit masks and bit positions */ -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN4CTRL bit masks and bit positions */ -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN5CTRL bit masks and bit positions */ -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN6CTRL bit masks and bit positions */ -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN7CTRL bit masks and bit positions */ -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* TC - 16-bit Timer/Counter With PWM */ -/* TC4.CTRLA bit masks and bit positions */ -#define TC4_SYNCHEN_bm 0x40 /* Synchronization Enabled bit mask. */ -#define TC4_SYNCHEN_bp 6 /* Synchronization Enabled bit position. */ - -#define TC4_EVSTART_bm 0x20 /* Start on Next Event bit mask. */ -#define TC4_EVSTART_bp 5 /* Start on Next Event bit position. */ - -#define TC4_UPSTOP_bm 0x10 /* Stop on Next Update bit mask. */ -#define TC4_UPSTOP_bp 4 /* Stop on Next Update bit position. */ - -#define TC4_CLKSEL_gm 0x0F /* Clock Select group mask. */ -#define TC4_CLKSEL_gp 0 /* Clock Select group position. */ -#define TC4_CLKSEL0_bm (1<<0) /* Clock Select bit 0 mask. */ -#define TC4_CLKSEL0_bp 0 /* Clock Select bit 0 position. */ -#define TC4_CLKSEL1_bm (1<<1) /* Clock Select bit 1 mask. */ -#define TC4_CLKSEL1_bp 1 /* Clock Select bit 1 position. */ -#define TC4_CLKSEL2_bm (1<<2) /* Clock Select bit 2 mask. */ -#define TC4_CLKSEL2_bp 2 /* Clock Select bit 2 position. */ -#define TC4_CLKSEL3_bm (1<<3) /* Clock Select bit 3 mask. */ -#define TC4_CLKSEL3_bp 3 /* Clock Select bit 3 position. */ - -/* TC4.CTRLB bit masks and bit positions */ -#define TC4_BYTEM_gm 0xC0 /* Byte Mode group mask. */ -#define TC4_BYTEM_gp 6 /* Byte Mode group position. */ -#define TC4_BYTEM0_bm (1<<6) /* Byte Mode bit 0 mask. */ -#define TC4_BYTEM0_bp 6 /* Byte Mode bit 0 position. */ -#define TC4_BYTEM1_bm (1<<7) /* Byte Mode bit 1 mask. */ -#define TC4_BYTEM1_bp 7 /* Byte Mode bit 1 position. */ - -#define TC4_CIRCEN_gm 0x30 /* Circular Buffer Enable group mask. */ -#define TC4_CIRCEN_gp 4 /* Circular Buffer Enable group position. */ -#define TC4_CIRCEN0_bm (1<<4) /* Circular Buffer Enable bit 0 mask. */ -#define TC4_CIRCEN0_bp 4 /* Circular Buffer Enable bit 0 position. */ -#define TC4_CIRCEN1_bm (1<<5) /* Circular Buffer Enable bit 1 mask. */ -#define TC4_CIRCEN1_bp 5 /* Circular Buffer Enable bit 1 position. */ - -#define TC4_WGMODE_gm 0x07 /* Waveform Generation Mode group mask. */ -#define TC4_WGMODE_gp 0 /* Waveform Generation Mode group position. */ -#define TC4_WGMODE0_bm (1<<0) /* Waveform Generation Mode bit 0 mask. */ -#define TC4_WGMODE0_bp 0 /* Waveform Generation Mode bit 0 position. */ -#define TC4_WGMODE1_bm (1<<1) /* Waveform Generation Mode bit 1 mask. */ -#define TC4_WGMODE1_bp 1 /* Waveform Generation Mode bit 1 position. */ -#define TC4_WGMODE2_bm (1<<2) /* Waveform Generation Mode bit 2 mask. */ -#define TC4_WGMODE2_bp 2 /* Waveform Generation Mode bit 2 position. */ - -/* TC4.CTRLC bit masks and bit positions */ -#define TC4_POLD_bm 0x80 /* Channel D Output Polarity bit mask. */ -#define TC4_POLD_bp 7 /* Channel D Output Polarity bit position. */ - -#define TC4_POLC_bm 0x40 /* Channel C Output Polarity bit mask. */ -#define TC4_POLC_bp 6 /* Channel C Output Polarity bit position. */ - -#define TC4_POLB_bm 0x20 /* Channel B Output Polarity bit mask. */ -#define TC4_POLB_bp 5 /* Channel B Output Polarity bit position. */ - -#define TC4_POLA_bm 0x10 /* Channel A Output Polarity bit mask. */ -#define TC4_POLA_bp 4 /* Channel A Output Polarity bit position. */ - -#define TC4_CMPD_bm 0x08 /* Channel D Compare Output Value bit mask. */ -#define TC4_CMPD_bp 3 /* Channel D Compare Output Value bit position. */ - -#define TC4_CMPC_bm 0x04 /* Channel C Compare Output Value bit mask. */ -#define TC4_CMPC_bp 2 /* Channel C Compare Output Value bit position. */ - -#define TC4_CMPB_bm 0x02 /* Channel B Compare Output Value bit mask. */ -#define TC4_CMPB_bp 1 /* Channel B Compare Output Value bit position. */ - -#define TC4_CMPA_bm 0x01 /* Channel A Compare Output Value bit mask. */ -#define TC4_CMPA_bp 0 /* Channel A Compare Output Value bit position. */ - -#define TC4_HCMPD_bm 0x80 /* High Channel D Compare Output Value bit mask. */ -#define TC4_HCMPD_bp 7 /* High Channel D Compare Output Value bit position. */ - -#define TC4_HCMPC_bm 0x40 /* High Channel C Compare Output Value bit mask. */ -#define TC4_HCMPC_bp 6 /* High Channel C Compare Output Value bit position. */ - -#define TC4_HCMPB_bm 0x20 /* High Channel B Compare Output Value bit mask. */ -#define TC4_HCMPB_bp 5 /* High Channel B Compare Output Value bit position. */ - -#define TC4_HCMPA_bm 0x10 /* High Channel A Compare Output Value bit mask. */ -#define TC4_HCMPA_bp 4 /* High Channel A Compare Output Value bit position. */ - -#define TC4_LCMPD_bm 0x08 /* Low Channel D Compare Output Value bit mask. */ -#define TC4_LCMPD_bp 3 /* Low Channel D Compare Output Value bit position. */ - -#define TC4_LCMPC_bm 0x04 /* Low Channel C Compare Output Value bit mask. */ -#define TC4_LCMPC_bp 2 /* Low Channel C Compare Output Value bit position. */ - -#define TC4_LCMPB_bm 0x02 /* Low Channel B Compare Output Value bit mask. */ -#define TC4_LCMPB_bp 1 /* Low Channel B Compare Output Value bit position. */ - -#define TC4_LCMPA_bm 0x01 /* Low Channel A Compare Output Value bit mask. */ -#define TC4_LCMPA_bp 0 /* Low Channel A Compare Output Value bit position. */ - -/* TC4.CTRLD bit masks and bit positions */ -#define TC4_EVACT_gm 0xE0 /* Event Action group mask. */ -#define TC4_EVACT_gp 5 /* Event Action group position. */ -#define TC4_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -#define TC4_EVACT0_bp 5 /* Event Action bit 0 position. */ -#define TC4_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -#define TC4_EVACT1_bp 6 /* Event Action bit 1 position. */ -#define TC4_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -#define TC4_EVACT2_bp 7 /* Event Action bit 2 position. */ - -#define TC4_EVDLY_bm 0x10 /* Event Delay bit mask. */ -#define TC4_EVDLY_bp 4 /* Event Delay bit position. */ - -#define TC4_EVSEL_gm 0x0F /* Event Source Select group mask. */ -#define TC4_EVSEL_gp 0 /* Event Source Select group position. */ -#define TC4_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -#define TC4_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -#define TC4_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -#define TC4_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -#define TC4_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -#define TC4_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -#define TC4_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -#define TC4_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - -/* TC4.CTRLE bit masks and bit positions */ -#define TC4_CCDMODE_gm 0xC0 /* Channel D Compare or Capture Mode group mask. */ -#define TC4_CCDMODE_gp 6 /* Channel D Compare or Capture Mode group position. */ -#define TC4_CCDMODE0_bm (1<<6) /* Channel D Compare or Capture Mode bit 0 mask. */ -#define TC4_CCDMODE0_bp 6 /* Channel D Compare or Capture Mode bit 0 position. */ -#define TC4_CCDMODE1_bm (1<<7) /* Channel D Compare or Capture Mode bit 1 mask. */ -#define TC4_CCDMODE1_bp 7 /* Channel D Compare or Capture Mode bit 1 position. */ - -#define TC4_CCCMODE_gm 0x30 /* Channel C Compare or Capture Mode group mask. */ -#define TC4_CCCMODE_gp 4 /* Channel C Compare or Capture Mode group position. */ -#define TC4_CCCMODE0_bm (1<<4) /* Channel C Compare or Capture Mode bit 0 mask. */ -#define TC4_CCCMODE0_bp 4 /* Channel C Compare or Capture Mode bit 0 position. */ -#define TC4_CCCMODE1_bm (1<<5) /* Channel C Compare or Capture Mode bit 1 mask. */ -#define TC4_CCCMODE1_bp 5 /* Channel C Compare or Capture Mode bit 1 position. */ - -#define TC4_CCBMODE_gm 0x0C /* Channel B Compare or Capture Mode group mask. */ -#define TC4_CCBMODE_gp 2 /* Channel B Compare or Capture Mode group position. */ -#define TC4_CCBMODE0_bm (1<<2) /* Channel B Compare or Capture Mode bit 0 mask. */ -#define TC4_CCBMODE0_bp 2 /* Channel B Compare or Capture Mode bit 0 position. */ -#define TC4_CCBMODE1_bm (1<<3) /* Channel B Compare or Capture Mode bit 1 mask. */ -#define TC4_CCBMODE1_bp 3 /* Channel B Compare or Capture Mode bit 1 position. */ - -#define TC4_CCAMODE_gm 0x03 /* Channel A Compare or Capture Mode group mask. */ -#define TC4_CCAMODE_gp 0 /* Channel A Compare or Capture Mode group position. */ -#define TC4_CCAMODE0_bm (1<<0) /* Channel A Compare or Capture Mode bit 0 mask. */ -#define TC4_CCAMODE0_bp 0 /* Channel A Compare or Capture Mode bit 0 position. */ -#define TC4_CCAMODE1_bm (1<<1) /* Channel A Compare or Capture Mode bit 1 mask. */ -#define TC4_CCAMODE1_bp 1 /* Channel A Compare or Capture Mode bit 1 position. */ - -#define TC4_LCCDMODE_gm 0xC0 /* Channel Low D Compare or Capture Mode group mask. */ -#define TC4_LCCDMODE_gp 6 /* Channel Low D Compare or Capture Mode group position. */ -#define TC4_LCCDMODE0_bm (1<<6) /* Channel Low D Compare or Capture Mode bit 0 mask. */ -#define TC4_LCCDMODE0_bp 6 /* Channel Low D Compare or Capture Mode bit 0 position. */ -#define TC4_LCCDMODE1_bm (1<<7) /* Channel Low D Compare or Capture Mode bit 1 mask. */ -#define TC4_LCCDMODE1_bp 7 /* Channel Low D Compare or Capture Mode bit 1 position. */ - -#define TC4_LCCCMODE_gm 0x30 /* Channel Low C Compare or Capture Mode group mask. */ -#define TC4_LCCCMODE_gp 4 /* Channel Low C Compare or Capture Mode group position. */ -#define TC4_LCCCMODE0_bm (1<<4) /* Channel Low C Compare or Capture Mode bit 0 mask. */ -#define TC4_LCCCMODE0_bp 4 /* Channel Low C Compare or Capture Mode bit 0 position. */ -#define TC4_LCCCMODE1_bm (1<<5) /* Channel Low C Compare or Capture Mode bit 1 mask. */ -#define TC4_LCCCMODE1_bp 5 /* Channel Low C Compare or Capture Mode bit 1 position. */ - -#define TC4_LCCBMODE_gm 0x0C /* Channel Low B Compare or Capture Mode group mask. */ -#define TC4_LCCBMODE_gp 2 /* Channel Low B Compare or Capture Mode group position. */ -#define TC4_LCCBMODE0_bm (1<<2) /* Channel Low B Compare or Capture Mode bit 0 mask. */ -#define TC4_LCCBMODE0_bp 2 /* Channel Low B Compare or Capture Mode bit 0 position. */ -#define TC4_LCCBMODE1_bm (1<<3) /* Channel Low B Compare or Capture Mode bit 1 mask. */ -#define TC4_LCCBMODE1_bp 3 /* Channel Low B Compare or Capture Mode bit 1 position. */ - -#define TC4_LCCAMODE_gm 0x03 /* Channel Low A Compare or Capture Mode group mask. */ -#define TC4_LCCAMODE_gp 0 /* Channel Low A Compare or Capture Mode group position. */ -#define TC4_LCCAMODE0_bm (1<<0) /* Channel Low A Compare or Capture Mode bit 0 mask. */ -#define TC4_LCCAMODE0_bp 0 /* Channel Low A Compare or Capture Mode bit 0 position. */ -#define TC4_LCCAMODE1_bm (1<<1) /* Channel Low A Compare or Capture Mode bit 1 mask. */ -#define TC4_LCCAMODE1_bp 1 /* Channel Low A Compare or Capture Mode bit 1 position. */ - -/* TC4.CTRLF bit masks and bit positions */ -#define TC4_HCCDMODE_gm 0xC0 /* Channel High D Compare or Capture Mode group mask. */ -#define TC4_HCCDMODE_gp 6 /* Channel High D Compare or Capture Mode group position. */ -#define TC4_HCCDMODE0_bm (1<<6) /* Channel High D Compare or Capture Mode bit 0 mask. */ -#define TC4_HCCDMODE0_bp 6 /* Channel High D Compare or Capture Mode bit 0 position. */ -#define TC4_HCCDMODE1_bm (1<<7) /* Channel High D Compare or Capture Mode bit 1 mask. */ -#define TC4_HCCDMODE1_bp 7 /* Channel High D Compare or Capture Mode bit 1 position. */ - -#define TC4_HCCCMODE_gm 0x30 /* Channel High C Compare or Capture Mode group mask. */ -#define TC4_HCCCMODE_gp 4 /* Channel High C Compare or Capture Mode group position. */ -#define TC4_HCCCMODE0_bm (1<<4) /* Channel High C Compare or Capture Mode bit 0 mask. */ -#define TC4_HCCCMODE0_bp 4 /* Channel High C Compare or Capture Mode bit 0 position. */ -#define TC4_HCCCMODE1_bm (1<<5) /* Channel High C Compare or Capture Mode bit 1 mask. */ -#define TC4_HCCCMODE1_bp 5 /* Channel High C Compare or Capture Mode bit 1 position. */ - -#define TC4_HCCBMODE_gm 0x0C /* Channel High B Compare or Capture Mode group mask. */ -#define TC4_HCCBMODE_gp 2 /* Channel High B Compare or Capture Mode group position. */ -#define TC4_HCCBMODE0_bm (1<<2) /* Channel High B Compare or Capture Mode bit 0 mask. */ -#define TC4_HCCBMODE0_bp 2 /* Channel High B Compare or Capture Mode bit 0 position. */ -#define TC4_HCCBMODE1_bm (1<<3) /* Channel High B Compare or Capture Mode bit 1 mask. */ -#define TC4_HCCBMODE1_bp 3 /* Channel High B Compare or Capture Mode bit 1 position. */ - -#define TC4_HCCAMODE_gm 0x03 /* Channel High A Compare or Capture Mode group mask. */ -#define TC4_HCCAMODE_gp 0 /* Channel High A Compare or Capture Mode group position. */ -#define TC4_HCCAMODE0_bm (1<<0) /* Channel High A Compare or Capture Mode bit 0 mask. */ -#define TC4_HCCAMODE0_bp 0 /* Channel High A Compare or Capture Mode bit 0 position. */ -#define TC4_HCCAMODE1_bm (1<<1) /* Channel High A Compare or Capture Mode bit 1 mask. */ -#define TC4_HCCAMODE1_bp 1 /* Channel High A Compare or Capture Mode bit 1 position. */ - -/* TC4.INTCTRLA bit masks and bit positions */ -#define TC4_TRGINTLVL_gm 0x30 /* Timer Trigger Restart Interrupt Level group mask. */ -#define TC4_TRGINTLVL_gp 4 /* Timer Trigger Restart Interrupt Level group position. */ -#define TC4_TRGINTLVL0_bm (1<<4) /* Timer Trigger Restart Interrupt Level bit 0 mask. */ -#define TC4_TRGINTLVL0_bp 4 /* Timer Trigger Restart Interrupt Level bit 0 position. */ -#define TC4_TRGINTLVL1_bm (1<<5) /* Timer Trigger Restart Interrupt Level bit 1 mask. */ -#define TC4_TRGINTLVL1_bp 5 /* Timer Trigger Restart Interrupt Level bit 1 position. */ - -#define TC4_ERRINTLVL_gm 0x0C /* Timer Error Interrupt Level group mask. */ -#define TC4_ERRINTLVL_gp 2 /* Timer Error Interrupt Level group position. */ -#define TC4_ERRINTLVL0_bm (1<<2) /* Timer Error Interrupt Level bit 0 mask. */ -#define TC4_ERRINTLVL0_bp 2 /* Timer Error Interrupt Level bit 0 position. */ -#define TC4_ERRINTLVL1_bm (1<<3) /* Timer Error Interrupt Level bit 1 mask. */ -#define TC4_ERRINTLVL1_bp 3 /* Timer Error Interrupt Level bit 1 position. */ - -#define TC4_OVFINTLVL_gm 0x03 /* Timer Overflow/Underflow Interrupt Level group mask. */ -#define TC4_OVFINTLVL_gp 0 /* Timer Overflow/Underflow Interrupt Level group position. */ -#define TC4_OVFINTLVL0_bm (1<<0) /* Timer Overflow/Underflow Interrupt Level bit 0 mask. */ -#define TC4_OVFINTLVL0_bp 0 /* Timer Overflow/Underflow Interrupt Level bit 0 position. */ -#define TC4_OVFINTLVL1_bm (1<<1) /* Timer Overflow/Underflow Interrupt Level bit 1 mask. */ -#define TC4_OVFINTLVL1_bp 1 /* Timer Overflow/Underflow Interrupt Level bit 1 position. */ - -/* TC4.INTCTRLB bit masks and bit positions */ -#define TC4_CCDINTLVL_gm 0xC0 /* Channel D Compare or Capture Interrupt Level group mask. */ -#define TC4_CCDINTLVL_gp 6 /* Channel D Compare or Capture Interrupt Level group position. */ -#define TC4_CCDINTLVL0_bm (1<<6) /* Channel D Compare or Capture Interrupt Level bit 0 mask. */ -#define TC4_CCDINTLVL0_bp 6 /* Channel D Compare or Capture Interrupt Level bit 0 position. */ -#define TC4_CCDINTLVL1_bm (1<<7) /* Channel D Compare or Capture Interrupt Level bit 1 mask. */ -#define TC4_CCDINTLVL1_bp 7 /* Channel D Compare or Capture Interrupt Level bit 1 position. */ - -#define TC4_CCCINTLVL_gm 0x30 /* Channel C Compare or Capture Interrupt Level group mask. */ -#define TC4_CCCINTLVL_gp 4 /* Channel C Compare or Capture Interrupt Level group position. */ -#define TC4_CCCINTLVL0_bm (1<<4) /* Channel C Compare or Capture Interrupt Level bit 0 mask. */ -#define TC4_CCCINTLVL0_bp 4 /* Channel C Compare or Capture Interrupt Level bit 0 position. */ -#define TC4_CCCINTLVL1_bm (1<<5) /* Channel C Compare or Capture Interrupt Level bit 1 mask. */ -#define TC4_CCCINTLVL1_bp 5 /* Channel C Compare or Capture Interrupt Level bit 1 position. */ - -#define TC4_CCBINTLVL_gm 0x0C /* Channel B Compare or Capture Interrupt Level group mask. */ -#define TC4_CCBINTLVL_gp 2 /* Channel B Compare or Capture Interrupt Level group position. */ -#define TC4_CCBINTLVL0_bm (1<<2) /* Channel B Compare or Capture Interrupt Level bit 0 mask. */ -#define TC4_CCBINTLVL0_bp 2 /* Channel B Compare or Capture Interrupt Level bit 0 position. */ -#define TC4_CCBINTLVL1_bm (1<<3) /* Channel B Compare or Capture Interrupt Level bit 1 mask. */ -#define TC4_CCBINTLVL1_bp 3 /* Channel B Compare or Capture Interrupt Level bit 1 position. */ - -#define TC4_CCAINTLVL_gm 0x03 /* Channel A Compare or Capture Interrupt Level group mask. */ -#define TC4_CCAINTLVL_gp 0 /* Channel A Compare or Capture Interrupt Level group position. */ -#define TC4_CCAINTLVL0_bm (1<<0) /* Channel A Compare or Capture Interrupt Level bit 0 mask. */ -#define TC4_CCAINTLVL0_bp 0 /* Channel A Compare or Capture Interrupt Level bit 0 position. */ -#define TC4_CCAINTLVL1_bm (1<<1) /* Channel A Compare or Capture Interrupt Level bit 1 mask. */ -#define TC4_CCAINTLVL1_bp 1 /* Channel A Compare or Capture Interrupt Level bit 1 position. */ - -#define TC4_LCCDINTLVL_gm 0xC0 /* Channel Low D Compare or Capture Interrupt Level group mask. */ -#define TC4_LCCDINTLVL_gp 6 /* Channel Low D Compare or Capture Interrupt Level group position. */ -#define TC4_LCCDINTLVL0_bm (1<<6) /* Channel Low D Compare or Capture Interrupt Level bit 0 mask. */ -#define TC4_LCCDINTLVL0_bp 6 /* Channel Low D Compare or Capture Interrupt Level bit 0 position. */ -#define TC4_LCCDINTLVL1_bm (1<<7) /* Channel Low D Compare or Capture Interrupt Level bit 1 mask. */ -#define TC4_LCCDINTLVL1_bp 7 /* Channel Low D Compare or Capture Interrupt Level bit 1 position. */ - -#define TC4_LCCCINTLVL_gm 0x30 /* Channel Low C Compare or Capture Interrupt Level group mask. */ -#define TC4_LCCCINTLVL_gp 4 /* Channel Low C Compare or Capture Interrupt Level group position. */ -#define TC4_LCCCINTLVL0_bm (1<<4) /* Channel Low C Compare or Capture Interrupt Level bit 0 mask. */ -#define TC4_LCCCINTLVL0_bp 4 /* Channel Low C Compare or Capture Interrupt Level bit 0 position. */ -#define TC4_LCCCINTLVL1_bm (1<<5) /* Channel Low C Compare or Capture Interrupt Level bit 1 mask. */ -#define TC4_LCCCINTLVL1_bp 5 /* Channel Low C Compare or Capture Interrupt Level bit 1 position. */ - -#define TC4_LCCBINTLVL_gm 0x0C /* Channel Low B Compare or Capture Interrupt Level group mask. */ -#define TC4_LCCBINTLVL_gp 2 /* Channel Low B Compare or Capture Interrupt Level group position. */ -#define TC4_LCCBINTLVL0_bm (1<<2) /* Channel Low B Compare or Capture Interrupt Level bit 0 mask. */ -#define TC4_LCCBINTLVL0_bp 2 /* Channel Low B Compare or Capture Interrupt Level bit 0 position. */ -#define TC4_LCCBINTLVL1_bm (1<<3) /* Channel Low B Compare or Capture Interrupt Level bit 1 mask. */ -#define TC4_LCCBINTLVL1_bp 3 /* Channel Low B Compare or Capture Interrupt Level bit 1 position. */ - -#define TC4_LCCAINTLVL_gm 0x03 /* Channel Low A Compare or Capture Interrupt Level group mask. */ -#define TC4_LCCAINTLVL_gp 0 /* Channel Low A Compare or Capture Interrupt Level group position. */ -#define TC4_LCCAINTLVL0_bm (1<<0) /* Channel Low A Compare or Capture Interrupt Level bit 0 mask. */ -#define TC4_LCCAINTLVL0_bp 0 /* Channel Low A Compare or Capture Interrupt Level bit 0 position. */ -#define TC4_LCCAINTLVL1_bm (1<<1) /* Channel Low A Compare or Capture Interrupt Level bit 1 mask. */ -#define TC4_LCCAINTLVL1_bp 1 /* Channel Low A Compare or Capture Interrupt Level bit 1 position. */ - -/* TC4.CTRLGCLR bit masks and bit positions */ -#define TC4_STOP_bm 0x20 /* Timer/Counter Stop bit mask. */ -#define TC4_STOP_bp 5 /* Timer/Counter Stop bit position. */ - -#define TC4_CMD_gm 0x0C /* Command group mask. */ -#define TC4_CMD_gp 2 /* Command group position. */ -#define TC4_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC4_CMD0_bp 2 /* Command bit 0 position. */ -#define TC4_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC4_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC4_LUPD_bm 0x02 /* Lock Update bit mask. */ -#define TC4_LUPD_bp 1 /* Lock Update bit position. */ - -#define TC4_DIR_bm 0x01 /* Counter Direction bit mask. */ -#define TC4_DIR_bp 0 /* Counter Direction bit position. */ - -/* TC4.CTRLGSET bit masks and bit positions */ -/* TC4_STOP Predefined. */ -/* TC4_STOP Predefined. */ - -/* TC4_CMD Predefined. */ -/* TC4_CMD Predefined. */ - -/* TC4_LUPD Predefined. */ -/* TC4_LUPD Predefined. */ - -/* TC4_DIR Predefined. */ -/* TC4_DIR Predefined. */ - -/* TC4.CTRLHCLR bit masks and bit positions */ -#define TC4_CCDBV_bm 0x10 /* Channel D Compare or Capture Buffer Valid bit mask. */ -#define TC4_CCDBV_bp 4 /* Channel D Compare or Capture Buffer Valid bit position. */ - -#define TC4_CCCBV_bm 0x08 /* Channel C Compare or Capture Buffer Valid bit mask. */ -#define TC4_CCCBV_bp 3 /* Channel C Compare or Capture Buffer Valid bit position. */ - -#define TC4_CCBBV_bm 0x04 /* Channel B Compare or Capture Buffer Valid bit mask. */ -#define TC4_CCBBV_bp 2 /* Channel B Compare or Capture Buffer Valid bit position. */ - -#define TC4_CCABV_bm 0x02 /* Channel A Compare or Capture Buffer Valid bit mask. */ -#define TC4_CCABV_bp 1 /* Channel A Compare or Capture Buffer Valid bit position. */ - -#define TC4_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -#define TC4_PERBV_bp 0 /* Period Buffer Valid bit position. */ - -#define TC4_LCCDBV_bm 0x10 /* Channel Low D Compare or Capture Buffer Valid bit mask. */ -#define TC4_LCCDBV_bp 4 /* Channel Low D Compare or Capture Buffer Valid bit position. */ - -#define TC4_LCCCBV_bm 0x08 /* Channel Low C Compare or Capture Buffer Valid bit mask. */ -#define TC4_LCCCBV_bp 3 /* Channel Low C Compare or Capture Buffer Valid bit position. */ - -#define TC4_LCCBBV_bm 0x04 /* Channel Low B Compare or Capture Buffer Valid bit mask. */ -#define TC4_LCCBBV_bp 2 /* Channel Low B Compare or Capture Buffer Valid bit position. */ - -#define TC4_LCCABV_bm 0x02 /* Channel Low A Compare or Capture Buffer Valid bit mask. */ -#define TC4_LCCABV_bp 1 /* Channel Low A Compare or Capture Buffer Valid bit position. */ - -#define TC4_LPERBV_bm 0x01 /* Period Low Buffer Valid bit mask. */ -#define TC4_LPERBV_bp 0 /* Period Low Buffer Valid bit position. */ - -/* TC4.CTRLHSET bit masks and bit positions */ -/* TC4_CCDBV Predefined. */ -/* TC4_CCDBV Predefined. */ - -/* TC4_CCCBV Predefined. */ -/* TC4_CCCBV Predefined. */ - -/* TC4_CCBBV Predefined. */ -/* TC4_CCBBV Predefined. */ - -/* TC4_CCABV Predefined. */ -/* TC4_CCABV Predefined. */ - -/* TC4_PERBV Predefined. */ -/* TC4_PERBV Predefined. */ - -/* TC4_LCCDBV Predefined. */ -/* TC4_LCCDBV Predefined. */ - -/* TC4_LCCCBV Predefined. */ -/* TC4_LCCCBV Predefined. */ - -/* TC4_LCCBBV Predefined. */ -/* TC4_LCCBBV Predefined. */ - -/* TC4_LCCABV Predefined. */ -/* TC4_LCCABV Predefined. */ - -/* TC4_LPERBV Predefined. */ -/* TC4_LPERBV Predefined. */ - -/* TC4.INTFLAGS bit masks and bit positions */ -#define TC4_CCDIF_bm 0x80 /* Channel D Compare or Capture Interrupt Flag bit mask. */ -#define TC4_CCDIF_bp 7 /* Channel D Compare or Capture Interrupt Flag bit position. */ - -#define TC4_CCCIF_bm 0x40 /* Channel C Compare or Capture Interrupt Flag bit mask. */ -#define TC4_CCCIF_bp 6 /* Channel C Compare or Capture Interrupt Flag bit position. */ - -#define TC4_CCBIF_bm 0x20 /* Channel B Compare or Capture Interrupt Flag bit mask. */ -#define TC4_CCBIF_bp 5 /* Channel B Compare or Capture Interrupt Flag bit position. */ - -#define TC4_CCAIF_bm 0x10 /* Channel A Compare or Capture Interrupt Flag bit mask. */ -#define TC4_CCAIF_bp 4 /* Channel A Compare or Capture Interrupt Flag bit position. */ - -#define TC4_TRGIF_bm 0x04 /* Trigger Restart Interrupt Flag bit mask. */ -#define TC4_TRGIF_bp 2 /* Trigger Restart Interrupt Flag bit position. */ - -#define TC4_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -#define TC4_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ - -#define TC4_OVFIF_bm 0x01 /* Overflow/Underflow Interrupt Flag bit mask. */ -#define TC4_OVFIF_bp 0 /* Overflow/Underflow Interrupt Flag bit position. */ - -#define TC4_LCCDIF_bm 0x80 /* Channel Low D Compare or Capture Interrupt Flag bit mask. */ -#define TC4_LCCDIF_bp 7 /* Channel Low D Compare or Capture Interrupt Flag bit position. */ - -#define TC4_LCCCIF_bm 0x40 /* Channel Low C Compare or Capture Interrupt Flag bit mask. */ -#define TC4_LCCCIF_bp 6 /* Channel Low C Compare or Capture Interrupt Flag bit position. */ - -#define TC4_LCCBIF_bm 0x20 /* Channel Low B Compare or Capture Interrupt Flag bit mask. */ -#define TC4_LCCBIF_bp 5 /* Channel Low B Compare or Capture Interrupt Flag bit position. */ - -#define TC4_LCCAIF_bm 0x10 /* Channel Low A Compare or Capture Interrupt Flag bit mask. */ -#define TC4_LCCAIF_bp 4 /* Channel Low A Compare or Capture Interrupt Flag bit position. */ - -/* TC5.CTRLA bit masks and bit positions */ -#define TC5_SYNCHEN_bm 0x40 /* Synchronization Enabled bit mask. */ -#define TC5_SYNCHEN_bp 6 /* Synchronization Enabled bit position. */ - -#define TC5_EVSTART_bm 0x20 /* Start on Next Event bit mask. */ -#define TC5_EVSTART_bp 5 /* Start on Next Event bit position. */ - -#define TC5_UPSTOP_bm 0x10 /* Stop on Next Update bit mask. */ -#define TC5_UPSTOP_bp 4 /* Stop on Next Update bit position. */ - -#define TC5_CLKSEL_gm 0x0F /* Clock Select group mask. */ -#define TC5_CLKSEL_gp 0 /* Clock Select group position. */ -#define TC5_CLKSEL0_bm (1<<0) /* Clock Select bit 0 mask. */ -#define TC5_CLKSEL0_bp 0 /* Clock Select bit 0 position. */ -#define TC5_CLKSEL1_bm (1<<1) /* Clock Select bit 1 mask. */ -#define TC5_CLKSEL1_bp 1 /* Clock Select bit 1 position. */ -#define TC5_CLKSEL2_bm (1<<2) /* Clock Select bit 2 mask. */ -#define TC5_CLKSEL2_bp 2 /* Clock Select bit 2 position. */ -#define TC5_CLKSEL3_bm (1<<3) /* Clock Select bit 3 mask. */ -#define TC5_CLKSEL3_bp 3 /* Clock Select bit 3 position. */ - -/* TC5.CTRLB bit masks and bit positions */ -#define TC5_BYTEM_gm 0xC0 /* Byte Mode group mask. */ -#define TC5_BYTEM_gp 6 /* Byte Mode group position. */ -#define TC5_BYTEM0_bm (1<<6) /* Byte Mode bit 0 mask. */ -#define TC5_BYTEM0_bp 6 /* Byte Mode bit 0 position. */ -#define TC5_BYTEM1_bm (1<<7) /* Byte Mode bit 1 mask. */ -#define TC5_BYTEM1_bp 7 /* Byte Mode bit 1 position. */ - -#define TC5_CIRCEN_gm 0x30 /* Circular Buffer Enable group mask. */ -#define TC5_CIRCEN_gp 4 /* Circular Buffer Enable group position. */ -#define TC5_CIRCEN0_bm (1<<4) /* Circular Buffer Enable bit 0 mask. */ -#define TC5_CIRCEN0_bp 4 /* Circular Buffer Enable bit 0 position. */ -#define TC5_CIRCEN1_bm (1<<5) /* Circular Buffer Enable bit 1 mask. */ -#define TC5_CIRCEN1_bp 5 /* Circular Buffer Enable bit 1 position. */ - -#define TC5_WGMODE_gm 0x07 /* Waveform Generation Mode group mask. */ -#define TC5_WGMODE_gp 0 /* Waveform Generation Mode group position. */ -#define TC5_WGMODE0_bm (1<<0) /* Waveform Generation Mode bit 0 mask. */ -#define TC5_WGMODE0_bp 0 /* Waveform Generation Mode bit 0 position. */ -#define TC5_WGMODE1_bm (1<<1) /* Waveform Generation Mode bit 1 mask. */ -#define TC5_WGMODE1_bp 1 /* Waveform Generation Mode bit 1 position. */ -#define TC5_WGMODE2_bm (1<<2) /* Waveform Generation Mode bit 2 mask. */ -#define TC5_WGMODE2_bp 2 /* Waveform Generation Mode bit 2 position. */ - -/* TC5.CTRLC bit masks and bit positions */ -#define TC5_POLB_bm 0x20 /* Channel B Output Polarity bit mask. */ -#define TC5_POLB_bp 5 /* Channel B Output Polarity bit position. */ - -#define TC5_POLA_bm 0x10 /* Channel A Output Polarity bit mask. */ -#define TC5_POLA_bp 4 /* Channel A Output Polarity bit position. */ - -#define TC5_CMPB_bm 0x02 /* Channel B Compare Output Value bit mask. */ -#define TC5_CMPB_bp 1 /* Channel B Compare Output Value bit position. */ - -#define TC5_CMPA_bm 0x01 /* Channel A Compare Output Value bit mask. */ -#define TC5_CMPA_bp 0 /* Channel A Compare Output Value bit position. */ - -#define TC5_HCMPB_bm 0x20 /* High Channel B Compare Output Value bit mask. */ -#define TC5_HCMPB_bp 5 /* High Channel B Compare Output Value bit position. */ - -#define TC5_HCMPA_bm 0x10 /* High Channel A Compare Output Value bit mask. */ -#define TC5_HCMPA_bp 4 /* High Channel A Compare Output Value bit position. */ - -#define TC5_LCMPB_bm 0x02 /* Low Channel B Compare Output Value bit mask. */ -#define TC5_LCMPB_bp 1 /* Low Channel B Compare Output Value bit position. */ - -#define TC5_LCMPA_bm 0x01 /* Low Channel A Compare Output Value bit mask. */ -#define TC5_LCMPA_bp 0 /* Low Channel A Compare Output Value bit position. */ - -/* TC5.CTRLD bit masks and bit positions */ -#define TC5_EVACT_gm 0xE0 /* Event Action group mask. */ -#define TC5_EVACT_gp 5 /* Event Action group position. */ -#define TC5_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -#define TC5_EVACT0_bp 5 /* Event Action bit 0 position. */ -#define TC5_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -#define TC5_EVACT1_bp 6 /* Event Action bit 1 position. */ -#define TC5_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -#define TC5_EVACT2_bp 7 /* Event Action bit 2 position. */ - -#define TC5_EVDLY_bm 0x10 /* Event Delay bit mask. */ -#define TC5_EVDLY_bp 4 /* Event Delay bit position. */ - -#define TC5_EVSEL_gm 0x0F /* Event Source Select group mask. */ -#define TC5_EVSEL_gp 0 /* Event Source Select group position. */ -#define TC5_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -#define TC5_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -#define TC5_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -#define TC5_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -#define TC5_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -#define TC5_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -#define TC5_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -#define TC5_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - -/* TC5.CTRLE bit masks and bit positions */ -#define TC5_CCBMODE_gm 0x0C /* Channel B Compare or Capture Mode group mask. */ -#define TC5_CCBMODE_gp 2 /* Channel B Compare or Capture Mode group position. */ -#define TC5_CCBMODE0_bm (1<<2) /* Channel B Compare or Capture Mode bit 0 mask. */ -#define TC5_CCBMODE0_bp 2 /* Channel B Compare or Capture Mode bit 0 position. */ -#define TC5_CCBMODE1_bm (1<<3) /* Channel B Compare or Capture Mode bit 1 mask. */ -#define TC5_CCBMODE1_bp 3 /* Channel B Compare or Capture Mode bit 1 position. */ - -#define TC5_CCAMODE_gm 0x03 /* Channel A Compare or Capture Mode group mask. */ -#define TC5_CCAMODE_gp 0 /* Channel A Compare or Capture Mode group position. */ -#define TC5_CCAMODE0_bm (1<<0) /* Channel A Compare or Capture Mode bit 0 mask. */ -#define TC5_CCAMODE0_bp 0 /* Channel A Compare or Capture Mode bit 0 position. */ -#define TC5_CCAMODE1_bm (1<<1) /* Channel A Compare or Capture Mode bit 1 mask. */ -#define TC5_CCAMODE1_bp 1 /* Channel A Compare or Capture Mode bit 1 position. */ - -#define TC5_LCCBMODE_gm 0x0C /* Channel Low B Compare or Capture Mode group mask. */ -#define TC5_LCCBMODE_gp 2 /* Channel Low B Compare or Capture Mode group position. */ -#define TC5_LCCBMODE0_bm (1<<2) /* Channel Low B Compare or Capture Mode bit 0 mask. */ -#define TC5_LCCBMODE0_bp 2 /* Channel Low B Compare or Capture Mode bit 0 position. */ -#define TC5_LCCBMODE1_bm (1<<3) /* Channel Low B Compare or Capture Mode bit 1 mask. */ -#define TC5_LCCBMODE1_bp 3 /* Channel Low B Compare or Capture Mode bit 1 position. */ - -#define TC5_LCCAMODE_gm 0x03 /* Channel Low A Compare or Capture Mode group mask. */ -#define TC5_LCCAMODE_gp 0 /* Channel Low A Compare or Capture Mode group position. */ -#define TC5_LCCAMODE0_bm (1<<0) /* Channel Low A Compare or Capture Mode bit 0 mask. */ -#define TC5_LCCAMODE0_bp 0 /* Channel Low A Compare or Capture Mode bit 0 position. */ -#define TC5_LCCAMODE1_bm (1<<1) /* Channel Low A Compare or Capture Mode bit 1 mask. */ -#define TC5_LCCAMODE1_bp 1 /* Channel Low A Compare or Capture Mode bit 1 position. */ - -/* TC5.CTRLF bit masks and bit positions */ -#define TC5_HCCBMODE_gm 0x0C /* Channel High B Compare or Capture Mode group mask. */ -#define TC5_HCCBMODE_gp 2 /* Channel High B Compare or Capture Mode group position. */ -#define TC5_HCCBMODE0_bm (1<<2) /* Channel High B Compare or Capture Mode bit 0 mask. */ -#define TC5_HCCBMODE0_bp 2 /* Channel High B Compare or Capture Mode bit 0 position. */ -#define TC5_HCCBMODE1_bm (1<<3) /* Channel High B Compare or Capture Mode bit 1 mask. */ -#define TC5_HCCBMODE1_bp 3 /* Channel High B Compare or Capture Mode bit 1 position. */ - -#define TC5_HCCAMODE_gm 0x03 /* Channel High A Compare or Capture Mode group mask. */ -#define TC5_HCCAMODE_gp 0 /* Channel High A Compare or Capture Mode group position. */ -#define TC5_HCCAMODE0_bm (1<<0) /* Channel High A Compare or Capture Mode bit 0 mask. */ -#define TC5_HCCAMODE0_bp 0 /* Channel High A Compare or Capture Mode bit 0 position. */ -#define TC5_HCCAMODE1_bm (1<<1) /* Channel High A Compare or Capture Mode bit 1 mask. */ -#define TC5_HCCAMODE1_bp 1 /* Channel High A Compare or Capture Mode bit 1 position. */ - -/* TC5.INTCTRLA bit masks and bit positions */ -#define TC5_TRGINTLVL_gm 0x30 /* Timer Trigger Restart Interrupt Level group mask. */ -#define TC5_TRGINTLVL_gp 4 /* Timer Trigger Restart Interrupt Level group position. */ -#define TC5_TRGINTLVL0_bm (1<<4) /* Timer Trigger Restart Interrupt Level bit 0 mask. */ -#define TC5_TRGINTLVL0_bp 4 /* Timer Trigger Restart Interrupt Level bit 0 position. */ -#define TC5_TRGINTLVL1_bm (1<<5) /* Timer Trigger Restart Interrupt Level bit 1 mask. */ -#define TC5_TRGINTLVL1_bp 5 /* Timer Trigger Restart Interrupt Level bit 1 position. */ - -#define TC5_ERRINTLVL_gm 0x0C /* Timer Error Interrupt Level group mask. */ -#define TC5_ERRINTLVL_gp 2 /* Timer Error Interrupt Level group position. */ -#define TC5_ERRINTLVL0_bm (1<<2) /* Timer Error Interrupt Level bit 0 mask. */ -#define TC5_ERRINTLVL0_bp 2 /* Timer Error Interrupt Level bit 0 position. */ -#define TC5_ERRINTLVL1_bm (1<<3) /* Timer Error Interrupt Level bit 1 mask. */ -#define TC5_ERRINTLVL1_bp 3 /* Timer Error Interrupt Level bit 1 position. */ - -#define TC5_OVFINTLVL_gm 0x03 /* Timer Overflow/Underflow Interrupt Level group mask. */ -#define TC5_OVFINTLVL_gp 0 /* Timer Overflow/Underflow Interrupt Level group position. */ -#define TC5_OVFINTLVL0_bm (1<<0) /* Timer Overflow/Underflow Interrupt Level bit 0 mask. */ -#define TC5_OVFINTLVL0_bp 0 /* Timer Overflow/Underflow Interrupt Level bit 0 position. */ -#define TC5_OVFINTLVL1_bm (1<<1) /* Timer Overflow/Underflow Interrupt Level bit 1 mask. */ -#define TC5_OVFINTLVL1_bp 1 /* Timer Overflow/Underflow Interrupt Level bit 1 position. */ - -/* TC5.INTCTRLB bit masks and bit positions */ -#define TC5_CCBINTLVL_gm 0x0C /* Channel B Compare or Capture Interrupt Level group mask. */ -#define TC5_CCBINTLVL_gp 2 /* Channel B Compare or Capture Interrupt Level group position. */ -#define TC5_CCBINTLVL0_bm (1<<2) /* Channel B Compare or Capture Interrupt Level bit 0 mask. */ -#define TC5_CCBINTLVL0_bp 2 /* Channel B Compare or Capture Interrupt Level bit 0 position. */ -#define TC5_CCBINTLVL1_bm (1<<3) /* Channel B Compare or Capture Interrupt Level bit 1 mask. */ -#define TC5_CCBINTLVL1_bp 3 /* Channel B Compare or Capture Interrupt Level bit 1 position. */ - -#define TC5_CCAINTLVL_gm 0x03 /* Channel A Compare or Capture Interrupt Level group mask. */ -#define TC5_CCAINTLVL_gp 0 /* Channel A Compare or Capture Interrupt Level group position. */ -#define TC5_CCAINTLVL0_bm (1<<0) /* Channel A Compare or Capture Interrupt Level bit 0 mask. */ -#define TC5_CCAINTLVL0_bp 0 /* Channel A Compare or Capture Interrupt Level bit 0 position. */ -#define TC5_CCAINTLVL1_bm (1<<1) /* Channel A Compare or Capture Interrupt Level bit 1 mask. */ -#define TC5_CCAINTLVL1_bp 1 /* Channel A Compare or Capture Interrupt Level bit 1 position. */ - -#define TC5_LCCBINTLVL_gm 0x0C /* Channel Low B Compare or Capture Interrupt Level group mask. */ -#define TC5_LCCBINTLVL_gp 2 /* Channel Low B Compare or Capture Interrupt Level group position. */ -#define TC5_LCCBINTLVL0_bm (1<<2) /* Channel Low B Compare or Capture Interrupt Level bit 0 mask. */ -#define TC5_LCCBINTLVL0_bp 2 /* Channel Low B Compare or Capture Interrupt Level bit 0 position. */ -#define TC5_LCCBINTLVL1_bm (1<<3) /* Channel Low B Compare or Capture Interrupt Level bit 1 mask. */ -#define TC5_LCCBINTLVL1_bp 3 /* Channel Low B Compare or Capture Interrupt Level bit 1 position. */ - -#define TC5_LCCAINTLVL_gm 0x03 /* Channel Low A Compare or Capture Interrupt Level group mask. */ -#define TC5_LCCAINTLVL_gp 0 /* Channel Low A Compare or Capture Interrupt Level group position. */ -#define TC5_LCCAINTLVL0_bm (1<<0) /* Channel Low A Compare or Capture Interrupt Level bit 0 mask. */ -#define TC5_LCCAINTLVL0_bp 0 /* Channel Low A Compare or Capture Interrupt Level bit 0 position. */ -#define TC5_LCCAINTLVL1_bm (1<<1) /* Channel Low A Compare or Capture Interrupt Level bit 1 mask. */ -#define TC5_LCCAINTLVL1_bp 1 /* Channel Low A Compare or Capture Interrupt Level bit 1 position. */ - -/* TC5.CTRLGCLR bit masks and bit positions */ -#define TC5_STOP_bm 0x20 /* Timer/Counter Stop bit mask. */ -#define TC5_STOP_bp 5 /* Timer/Counter Stop bit position. */ - -#define TC5_CMD_gm 0x0C /* Command group mask. */ -#define TC5_CMD_gp 2 /* Command group position. */ -#define TC5_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC5_CMD0_bp 2 /* Command bit 0 position. */ -#define TC5_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC5_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC5_LUPD_bm 0x02 /* Lock Update bit mask. */ -#define TC5_LUPD_bp 1 /* Lock Update bit position. */ - -#define TC5_DIR_bm 0x01 /* Counter Direction bit mask. */ -#define TC5_DIR_bp 0 /* Counter Direction bit position. */ - -/* TC5.CTRLGSET bit masks and bit positions */ -/* TC5_STOP Predefined. */ -/* TC5_STOP Predefined. */ - -/* TC5_CMD Predefined. */ -/* TC5_CMD Predefined. */ - -/* TC5_LUPD Predefined. */ -/* TC5_LUPD Predefined. */ - -/* TC5_DIR Predefined. */ -/* TC5_DIR Predefined. */ - -/* TC5.CTRLHCLR bit masks and bit positions */ -#define TC5_CCBBV_bm 0x04 /* Channel B Compare or Capture Buffer Valid bit mask. */ -#define TC5_CCBBV_bp 2 /* Channel B Compare or Capture Buffer Valid bit position. */ - -#define TC5_CCABV_bm 0x02 /* Channel A Compare or Capture Buffer Valid bit mask. */ -#define TC5_CCABV_bp 1 /* Channel A Compare or Capture Buffer Valid bit position. */ - -#define TC5_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -#define TC5_PERBV_bp 0 /* Period Buffer Valid bit position. */ - -#define TC5_LCCBBV_bm 0x04 /* Channel Low B Compare or Capture Buffer Valid bit mask. */ -#define TC5_LCCBBV_bp 2 /* Channel Low B Compare or Capture Buffer Valid bit position. */ - -#define TC5_LCCABV_bm 0x02 /* Channel Low A Compare or Capture Buffer Valid bit mask. */ -#define TC5_LCCABV_bp 1 /* Channel Low A Compare or Capture Buffer Valid bit position. */ - -#define TC5_LPERBV_bm 0x01 /* Period Low Buffer Valid bit mask. */ -#define TC5_LPERBV_bp 0 /* Period Low Buffer Valid bit position. */ - -/* TC5.CTRLHSET bit masks and bit positions */ -/* TC5_CCBBV Predefined. */ -/* TC5_CCBBV Predefined. */ - -/* TC5_CCABV Predefined. */ -/* TC5_CCABV Predefined. */ - -/* TC5_PERBV Predefined. */ -/* TC5_PERBV Predefined. */ - -/* TC5_LCCBBV Predefined. */ -/* TC5_LCCBBV Predefined. */ - -/* TC5_LCCABV Predefined. */ -/* TC5_LCCABV Predefined. */ - -/* TC5_LPERBV Predefined. */ -/* TC5_LPERBV Predefined. */ - -/* TC5.INTFLAGS bit masks and bit positions */ -#define TC5_CCBIF_bm 0x20 /* Channel B Compare or Capture Interrupt Flag bit mask. */ -#define TC5_CCBIF_bp 5 /* Channel B Compare or Capture Interrupt Flag bit position. */ - -#define TC5_CCAIF_bm 0x10 /* Channel A Compare or Capture Interrupt Flag bit mask. */ -#define TC5_CCAIF_bp 4 /* Channel A Compare or Capture Interrupt Flag bit position. */ - -#define TC5_TRGIF_bm 0x04 /* Trigger Restart Interrupt Flag bit mask. */ -#define TC5_TRGIF_bp 2 /* Trigger Restart Interrupt Flag bit position. */ - -#define TC5_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -#define TC5_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ - -#define TC5_OVFIF_bm 0x01 /* Overflow/Underflow Interrupt Flag bit mask. */ -#define TC5_OVFIF_bp 0 /* Overflow/Underflow Interrupt Flag bit position. */ - -#define TC5_LCCBIF_bm 0x20 /* Channel Low B Compare or Capture Interrupt Flag bit mask. */ -#define TC5_LCCBIF_bp 5 /* Channel Low B Compare or Capture Interrupt Flag bit position. */ - -#define TC5_LCCAIF_bm 0x10 /* Channel Low A Compare or Capture Interrupt Flag bit mask. */ -#define TC5_LCCAIF_bp 4 /* Channel Low A Compare or Capture Interrupt Flag bit position. */ - -/* FAULT - Fault Extension */ -/* FAULT.CTRLA bit masks and bit positions */ -#define FAULT_RAMP_gm 0xC0 /* Ramp Mode Selection group mask. */ -#define FAULT_RAMP_gp 6 /* Ramp Mode Selection group position. */ -#define FAULT_RAMP0_bm (1<<6) /* Ramp Mode Selection bit 0 mask. */ -#define FAULT_RAMP0_bp 6 /* Ramp Mode Selection bit 0 position. */ -#define FAULT_RAMP1_bm (1<<7) /* Ramp Mode Selection bit 1 mask. */ -#define FAULT_RAMP1_bp 7 /* Ramp Mode Selection bit 1 position. */ - -#define FAULT_FDDBD_bm 0x20 /* Fault on Debug Break Detection bit mask. */ -#define FAULT_FDDBD_bp 5 /* Fault on Debug Break Detection bit position. */ - -#define FAULT_PORTCTRL_bm 0x10 /* Port Control Mode bit mask. */ -#define FAULT_PORTCTRL_bp 4 /* Port Control Mode bit position. */ - -#define FAULT_FUSE_bm 0x08 /* Fuse State bit mask. */ -#define FAULT_FUSE_bp 3 /* Fuse State bit position. */ - -#define FAULT_FILTERE_bm 0x04 /* Fault E Digital Filter Selection bit mask. */ -#define FAULT_FILTERE_bp 2 /* Fault E Digital Filter Selection bit position. */ - -#define FAULT_SRCE_gm 0x03 /* Fault E Input selection group mask. */ -#define FAULT_SRCE_gp 0 /* Fault E Input selection group position. */ -#define FAULT_SRCE0_bm (1<<0) /* Fault E Input selection bit 0 mask. */ -#define FAULT_SRCE0_bp 0 /* Fault E Input selection bit 0 position. */ -#define FAULT_SRCE1_bm (1<<1) /* Fault E Input selection bit 1 mask. */ -#define FAULT_SRCE1_bp 1 /* Fault E Input selection bit 1 position. */ - -/* FAULT.CTRLB bit masks and bit positions */ -#define FAULT_SOFTA_bm 0x80 /* Fault A Software Mode bit mask. */ -#define FAULT_SOFTA_bp 7 /* Fault A Software Mode bit position. */ - -#define FAULT_HALTA_gm 0x60 /* Fault A Halt Action group mask. */ -#define FAULT_HALTA_gp 5 /* Fault A Halt Action group position. */ -#define FAULT_HALTA0_bm (1<<5) /* Fault A Halt Action bit 0 mask. */ -#define FAULT_HALTA0_bp 5 /* Fault A Halt Action bit 0 position. */ -#define FAULT_HALTA1_bm (1<<6) /* Fault A Halt Action bit 1 mask. */ -#define FAULT_HALTA1_bp 6 /* Fault A Halt Action bit 1 position. */ - -#define FAULT_RESTARTA_bm 0x10 /* Fault A Restart Action bit mask. */ -#define FAULT_RESTARTA_bp 4 /* Fault A Restart Action bit position. */ - -#define FAULT_KEEPA_bm 0x08 /* Fault A Keep Action bit mask. */ -#define FAULT_KEEPA_bp 3 /* Fault A Keep Action bit position. */ - -#define FAULT_SRCA_gm 0x03 /* Fault A Source Selection group mask. */ -#define FAULT_SRCA_gp 0 /* Fault A Source Selection group position. */ -#define FAULT_SRCA0_bm (1<<0) /* Fault A Source Selection bit 0 mask. */ -#define FAULT_SRCA0_bp 0 /* Fault A Source Selection bit 0 position. */ -#define FAULT_SRCA1_bm (1<<1) /* Fault A Source Selection bit 1 mask. */ -#define FAULT_SRCA1_bp 1 /* Fault A Source Selection bit 1 position. */ - -/* FAULT.CTRLC bit masks and bit positions */ -#define FAULT_CAPTA_bm 0x20 /* Fault A Capture bit mask. */ -#define FAULT_CAPTA_bp 5 /* Fault A Capture bit position. */ - -#define FAULT_FILTERA_bm 0x04 /* Fault A Digital Filter Selection bit mask. */ -#define FAULT_FILTERA_bp 2 /* Fault A Digital Filter Selection bit position. */ - -#define FAULT_BLANKA_bm 0x02 /* Fault A Blanking bit mask. */ -#define FAULT_BLANKA_bp 1 /* Fault A Blanking bit position. */ - -#define FAULT_QUALA_bm 0x01 /* Fault A Qualification bit mask. */ -#define FAULT_QUALA_bp 0 /* Fault A Qualification bit position. */ - -/* FAULT.CTRLD bit masks and bit positions */ -#define FAULT_SOFTB_bm 0x80 /* Fault B Software Mode bit mask. */ -#define FAULT_SOFTB_bp 7 /* Fault B Software Mode bit position. */ - -#define FAULT_HALTB_gm 0x60 /* Fault B Halt Action group mask. */ -#define FAULT_HALTB_gp 5 /* Fault B Halt Action group position. */ -#define FAULT_HALTB0_bm (1<<5) /* Fault B Halt Action bit 0 mask. */ -#define FAULT_HALTB0_bp 5 /* Fault B Halt Action bit 0 position. */ -#define FAULT_HALTB1_bm (1<<6) /* Fault B Halt Action bit 1 mask. */ -#define FAULT_HALTB1_bp 6 /* Fault B Halt Action bit 1 position. */ - -#define FAULT_RESTARTB_bm 0x10 /* Fault B Restart Action bit mask. */ -#define FAULT_RESTARTB_bp 4 /* Fault B Restart Action bit position. */ - -#define FAULT_KEEPB_bm 0x08 /* Fault B Keep Action bit mask. */ -#define FAULT_KEEPB_bp 3 /* Fault B Keep Action bit position. */ - -#define FAULT_SRCB_gm 0x03 /* Fault B Source Selection group mask. */ -#define FAULT_SRCB_gp 0 /* Fault B Source Selection group position. */ -#define FAULT_SRCB0_bm (1<<0) /* Fault B Source Selection bit 0 mask. */ -#define FAULT_SRCB0_bp 0 /* Fault B Source Selection bit 0 position. */ -#define FAULT_SRCB1_bm (1<<1) /* Fault B Source Selection bit 1 mask. */ -#define FAULT_SRCB1_bp 1 /* Fault B Source Selection bit 1 position. */ - -/* FAULT.CTRLE bit masks and bit positions */ -#define FAULT_CAPTB_bm 0x20 /* Fault B Capture bit mask. */ -#define FAULT_CAPTB_bp 5 /* Fault B Capture bit position. */ - -#define FAULT_FILTERB_bm 0x04 /* Fault B Digital Filter Selection bit mask. */ -#define FAULT_FILTERB_bp 2 /* Fault B Digital Filter Selection bit position. */ - -#define FAULT_BLANKB_bm 0x02 /* Fault B Blanking bit mask. */ -#define FAULT_BLANKB_bp 1 /* Fault B Blanking bit position. */ - -#define FAULT_QUALB_bm 0x01 /* Fault B Qualification bit mask. */ -#define FAULT_QUALB_bp 0 /* Fault B Qualification bit position. */ - -/* FAULT.STATUS bit masks and bit positions */ -#define FAULT_STATEB_bm 0x80 /* Fault B State bit mask. */ -#define FAULT_STATEB_bp 7 /* Fault B State bit position. */ - -#define FAULT_STATEA_bm 0x40 /* Fault A State bit mask. */ -#define FAULT_STATEA_bp 6 /* Fault A State bit position. */ - -#define FAULT_STATEE_bm 0x20 /* Fault E State bit mask. */ -#define FAULT_STATEE_bp 5 /* Fault E State bit position. */ - -#define FAULT_IDX_bm 0x08 /* Channel Index Flag bit mask. */ -#define FAULT_IDX_bp 3 /* Channel Index Flag bit position. */ - -#define FAULT_FAULTBIN_bm 0x04 /* Fault B Flag bit mask. */ -#define FAULT_FAULTBIN_bp 2 /* Fault B Flag bit position. */ - -#define FAULT_FAULTAIN_bm 0x02 /* Fault A Flag bit mask. */ -#define FAULT_FAULTAIN_bp 1 /* Fault A Flag bit position. */ - -#define FAULT_FAULTEIN_bm 0x01 /* Fault E Flag bit mask. */ -#define FAULT_FAULTEIN_bp 0 /* Fault E Flag bit position. */ - -/* FAULT.CTRLGCLR bit masks and bit positions */ -#define FAULT_HALTBCLR_bm 0x80 /* State B Clear bit mask. */ -#define FAULT_HALTBCLR_bp 7 /* State B Clear bit position. */ - -#define FAULT_HALTACLR_bm 0x40 /* State A Clear bit mask. */ -#define FAULT_HALTACLR_bp 6 /* State A Clear bit position. */ - -#define FAULT_STATEECLR_bm 0x20 /* State E Clear bit mask. */ -#define FAULT_STATEECLR_bp 5 /* State E Clear bit position. */ - -#define FAULT_FAULTB_bm 0x04 /* Fault B Flag bit mask. */ -#define FAULT_FAULTB_bp 2 /* Fault B Flag bit position. */ - -#define FAULT_FAULTA_bm 0x02 /* Fault A Flag bit mask. */ -#define FAULT_FAULTA_bp 1 /* Fault A Flag bit position. */ - -#define FAULT_FAULTE_bm 0x01 /* Fault E Flag bit mask. */ -#define FAULT_FAULTE_bp 0 /* Fault E Flag bit position. */ - -/* FAULT.CTRLGSET bit masks and bit positions */ -#define FAULT_FAULTBSW_bm 0x80 /* Software Fault B bit mask. */ -#define FAULT_FAULTBSW_bp 7 /* Software Fault B bit position. */ - -#define FAULT_FAULTASW_bm 0x40 /* Software Fault A bit mask. */ -#define FAULT_FAULTASW_bp 6 /* Software Fault A bit position. */ - -#define FAULT_FAULTESW_bm 0x20 /* Software Fault E bit mask. */ -#define FAULT_FAULTESW_bp 5 /* Software Fault E bit position. */ - -#define FAULT_IDXCMD_gm 0x18 /* Channel index Command group mask. */ -#define FAULT_IDXCMD_gp 3 /* Channel index Command group position. */ -#define FAULT_IDXCMD0_bm (1<<3) /* Channel index Command bit 0 mask. */ -#define FAULT_IDXCMD0_bp 3 /* Channel index Command bit 0 position. */ -#define FAULT_IDXCMD1_bm (1<<4) /* Channel index Command bit 1 mask. */ -#define FAULT_IDXCMD1_bp 4 /* Channel index Command bit 1 position. */ - -/* WEX - Waveform Extension */ -/* WEX.CTRL bit masks and bit positions */ -#define WEX_UPSEL_bm 0x80 /* Update Source Selection bit mask. */ -#define WEX_UPSEL_bp 7 /* Update Source Selection bit position. */ - -#define WEX_OTMX_gm 0x70 /* Output Matrix group mask. */ -#define WEX_OTMX_gp 4 /* Output Matrix group position. */ -#define WEX_OTMX0_bm (1<<4) /* Output Matrix bit 0 mask. */ -#define WEX_OTMX0_bp 4 /* Output Matrix bit 0 position. */ -#define WEX_OTMX1_bm (1<<5) /* Output Matrix bit 1 mask. */ -#define WEX_OTMX1_bp 5 /* Output Matrix bit 1 position. */ -#define WEX_OTMX2_bm (1<<6) /* Output Matrix bit 2 mask. */ -#define WEX_OTMX2_bp 6 /* Output Matrix bit 2 position. */ - -#define WEX_DTI3EN_bm 0x08 /* Dead-Time Insertion Generator 3 Enable bit mask. */ -#define WEX_DTI3EN_bp 3 /* Dead-Time Insertion Generator 3 Enable bit position. */ - -#define WEX_DTI2EN_bm 0x04 /* Dead-Time Insertion Generator 2 Enable bit mask. */ -#define WEX_DTI2EN_bp 2 /* Dead-Time Insertion Generator 2 Enable bit position. */ - -#define WEX_DTI1EN_bm 0x02 /* Dead-Time Insertion Generator 1 Enable bit mask. */ -#define WEX_DTI1EN_bp 1 /* Dead-Time Insertion Generator 1 Enable bit position. */ - -#define WEX_DTI0EN_bm 0x01 /* Dead-Time Insertion Generator 0 Enable bit mask. */ -#define WEX_DTI0EN_bp 0 /* Dead-Time Insertion Generator 0 Enable bit position. */ - -/* WEX.STATUSCLR bit masks and bit positions */ -#define WEX_SWAPBUF_bm 0x04 /* Swap Buffer Valid bit mask. */ -#define WEX_SWAPBUF_bp 2 /* Swap Buffer Valid bit position. */ - -#define WEX_PGVBUFV_bm 0x02 /* Pattern Generator Value Buffer Valid bit mask. */ -#define WEX_PGVBUFV_bp 1 /* Pattern Generator Value Buffer Valid bit position. */ - -#define WEX_PGOBUFV_bm 0x01 /* Pattern Generator Overwrite Buffer Valid bit mask. */ -#define WEX_PGOBUFV_bp 0 /* Pattern Generator Overwrite Buffer Valid bit position. */ - -/* WEX.STATUSSET bit masks and bit positions */ -/* WEX_SWAPBUF Predefined. */ -/* WEX_SWAPBUF Predefined. */ - -/* WEX_PGVBUFV Predefined. */ -/* WEX_PGVBUFV Predefined. */ - -/* WEX_PGOBUFV Predefined. */ -/* WEX_PGOBUFV Predefined. */ - -/* WEX.SWAP bit masks and bit positions */ -#define WEX_SWAP3_bm 0x08 /* Swap DTI output pair 3 bit mask. */ -#define WEX_SWAP3_bp 3 /* Swap DTI output pair 3 bit position. */ - -#define WEX_SWAP2_bm 0x04 /* Swap DTI output pair 2 bit mask. */ -#define WEX_SWAP2_bp 2 /* Swap DTI output pair 2 bit position. */ - -#define WEX_SWAP1_bm 0x02 /* Swap DTI output pair 1 bit mask. */ -#define WEX_SWAP1_bp 1 /* Swap DTI output pair 1 bit position. */ - -#define WEX_SWAP0_bm 0x01 /* Swap DTI output pair 0 bit mask. */ -#define WEX_SWAP0_bp 0 /* Swap DTI output pair 0 bit position. */ - -/* WEX.SWAPBUF bit masks and bit positions */ -#define WEX_SWAP3BUF_bm 0x08 /* Swap DTI output pair 3 bit mask. */ -#define WEX_SWAP3BUF_bp 3 /* Swap DTI output pair 3 bit position. */ - -#define WEX_SWAP2BUF_bm 0x04 /* Swap DTI output pair 2 bit mask. */ -#define WEX_SWAP2BUF_bp 2 /* Swap DTI output pair 2 bit position. */ - -#define WEX_SWAP1BUF_bm 0x02 /* Swap DTI output pair 1 bit mask. */ -#define WEX_SWAP1BUF_bp 1 /* Swap DTI output pair 1 bit position. */ - -#define WEX_SWAP0BUF_bm 0x01 /* Swap DTI output pair 0 bit mask. */ -#define WEX_SWAP0BUF_bp 0 /* Swap DTI output pair 0 bit position. */ - -/* HIRES - High-Resolution Extension */ -/* HIRES.CTRLA bit masks and bit positions */ -#define HIRES_HRPLUS_gm 0x0C /* High Resolution Plus group mask. */ -#define HIRES_HRPLUS_gp 2 /* High Resolution Plus group position. */ -#define HIRES_HRPLUS0_bm (1<<2) /* High Resolution Plus bit 0 mask. */ -#define HIRES_HRPLUS0_bp 2 /* High Resolution Plus bit 0 position. */ -#define HIRES_HRPLUS1_bm (1<<3) /* High Resolution Plus bit 1 mask. */ -#define HIRES_HRPLUS1_bp 3 /* High Resolution Plus bit 1 position. */ - -#define HIRES_HREN_gm 0x03 /* High Resolution Mode group mask. */ -#define HIRES_HREN_gp 0 /* High Resolution Mode group position. */ -#define HIRES_HREN0_bm (1<<0) /* High Resolution Mode bit 0 mask. */ -#define HIRES_HREN0_bp 0 /* High Resolution Mode bit 0 position. */ -#define HIRES_HREN1_bm (1<<1) /* High Resolution Mode bit 1 mask. */ -#define HIRES_HREN1_bp 1 /* High Resolution Mode bit 1 position. */ - -/* USART - Universal Asynchronous Receiver-Transmitter */ -/* USART.STATUS bit masks and bit positions */ -#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ -#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ - -#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ -#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ - -#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ -#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ - -#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ -#define USART_FERR_bp 4 /* Frame Error bit position. */ - -#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ -#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ - -#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ -#define USART_PERR_bp 2 /* Parity Error bit position. */ - -#define USART_RXSIF_bm 0x02 /* Receive Start Bit Interrupt Flag bit mask. */ -#define USART_RXSIF_bp 1 /* Receive Start Bit Interrupt Flag bit position. */ - -#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ -#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ - -#define USART_DRIF_bm 0x01 /* Data Reception Flag bit mask. */ -#define USART_DRIF_bp 0 /* Data Reception Flag bit position. */ - -/* USART.CTRLA bit masks and bit positions */ -#define USART_RXSIE_bm 0x80 /* Receive Start Interrupt Enable bit mask. */ -#define USART_RXSIE_bp 7 /* Receive Start Interrupt Enable bit position. */ - -#define USART_DRIE_bm 0x40 /* Data Reception Interrupt Enable bit mask. */ -#define USART_DRIE_bp 6 /* Data Reception Interrupt Enable bit position. */ - -#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ -#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ -#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ -#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ -#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ -#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ - -#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ -#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ -#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ -#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ -#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ -#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ - -#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ -#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ -#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ -#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ -#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ -#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ - -/* USART.CTRLB bit masks and bit positions */ -#define USART_ONEWIRE_bm 0x80 /* One Wire Mode bit mask. */ -#define USART_ONEWIRE_bp 7 /* One Wire Mode bit position. */ - -#define USART_SFDEN_bm 0x40 /* Start Frame Detection Enable bit mask. */ -#define USART_SFDEN_bp 6 /* Start Frame Detection Enable bit position. */ - -#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ -#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ - -#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ -#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ - -#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ -#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ - -#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ -#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ - -#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ -#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ - -/* USART.CTRLC bit masks and bit positions */ -#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ -#define USART_CMODE_gp 6 /* Communication Mode group position. */ -#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ -#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ -#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ -#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ - -#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ -#define USART_PMODE_gp 4 /* Parity Mode group position. */ -#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ -#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ -#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ -#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ - -#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ -#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ - -#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ -#define USART_CHSIZE_gp 0 /* Character Size group position. */ -#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ -#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ -#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ -#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ -#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ -#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ - -/* USART.CTRLD bit masks and bit positions */ -#define USART_DECTYPE_gm 0x30 /* Receive Interrupt Level group mask. */ -#define USART_DECTYPE_gp 4 /* Receive Interrupt Level group position. */ -#define USART_DECTYPE0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ -#define USART_DECTYPE0_bp 4 /* Receive Interrupt Level bit 0 position. */ -#define USART_DECTYPE1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ -#define USART_DECTYPE1_bp 5 /* Receive Interrupt Level bit 1 position. */ - -#define USART_LUTACT_gm 0x0C /* Transmit Interrupt Level group mask. */ -#define USART_LUTACT_gp 2 /* Transmit Interrupt Level group position. */ -#define USART_LUTACT0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ -#define USART_LUTACT0_bp 2 /* Transmit Interrupt Level bit 0 position. */ -#define USART_LUTACT1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ -#define USART_LUTACT1_bp 3 /* Transmit Interrupt Level bit 1 position. */ - -#define USART_PECACT_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ -#define USART_PECACT_gp 0 /* Data Register Empty Interrupt Level group position. */ -#define USART_PECACT0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ -#define USART_PECACT0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ -#define USART_PECACT1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ -#define USART_PECACT1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ - -/* USART.BAUDCTRLA bit masks and bit positions */ -#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ -#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ -#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ -#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ -#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ -#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ -#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ -#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ -#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ -#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ -#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ -#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ -#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ -#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ -#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ -#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ -#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ -#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ - -/* USART.BAUDCTRLB bit masks and bit positions */ -#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ -#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ -#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ -#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ -#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ -#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ -#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ -#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ -#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ -#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ - -/* USART_BSEL Predefined. */ -/* USART_BSEL Predefined. */ - -/* SPI - Serial Peripheral Interface */ -/* SPI.CTRL bit masks and bit positions */ -#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ -#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ - -#define SPI_ENABLE_bm 0x40 /* Enable SPI Module bit mask. */ -#define SPI_ENABLE_bp 6 /* Enable SPI Module bit position. */ - -#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ -#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ - -#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ -#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ - -#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ -#define SPI_MODE_gp 2 /* SPI Mode group position. */ -#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ -#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ -#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ -#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ - -#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ -#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ -#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ -#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ -#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ -#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ - -/* SPI.INTCTRL bit masks and bit positions */ -#define SPI_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable (In Buffer Modes Only). bit mask. */ -#define SPI_RXCIE_bp 7 /* Receive Complete Interrupt Enable (In Buffer Modes Only). bit position. */ - -#define SPI_TXCIE_bm 0x40 /* Transmit Complete Interrupt Enable (In Buffer Modes Only). bit mask. */ -#define SPI_TXCIE_bp 6 /* Transmit Complete Interrupt Enable (In Buffer Modes Only). bit position. */ - -#define SPI_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable (In Buffer Modes Only). bit mask. */ -#define SPI_DREIE_bp 5 /* Data Register Empty Interrupt Enable (In Buffer Modes Only). bit position. */ - -#define SPI_SSIE_bm 0x10 /* Slave Select Trigger Interrupt Enable (In Buffer Modes Only). bit mask. */ -#define SPI_SSIE_bp 4 /* Slave Select Trigger Interrupt Enable (In Buffer Modes Only). bit position. */ - -#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ -#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ -#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ - -/* SPI.STATUS bit masks and bit positions */ -#define SPI_IF_bm 0x80 /* Interrupt Flag (In Standard Mode Only). bit mask. */ -#define SPI_IF_bp 7 /* Interrupt Flag (In Standard Mode Only). bit position. */ - -#define SPI_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag (In Buffer Modes Only). bit mask. */ -#define SPI_RXCIF_bp 7 /* Receive Complete Interrupt Flag (In Buffer Modes Only). bit position. */ - -#define SPI_WRCOL_bm 0x40 /* Write Collision Flag (In Standard Mode Only). bit mask. */ -#define SPI_WRCOL_bp 6 /* Write Collision Flag (In Standard Mode Only). bit position. */ - -#define SPI_TXCIF_bm 0x40 /* Transmit Complete Interrupt Flag (In Buffer Modes Only). bit mask. */ -#define SPI_TXCIF_bp 6 /* Transmit Complete Interrupt Flag (In Buffer Modes Only). bit position. */ - -#define SPI_DREIF_bm 0x20 /* Data Register Empty Interrupt Flag (In Buffer Modes Only). bit mask. */ -#define SPI_DREIF_bp 5 /* Data Register Empty Interrupt Flag (In Buffer Modes Only). bit position. */ - -#define SPI_SSIF_bm 0x10 /* Slave Select Trigger Interrupt Flag (In Buffer Modes Only). bit mask. */ -#define SPI_SSIF_bp 4 /* Slave Select Trigger Interrupt Flag (In Buffer Modes Only). bit position. */ - -#define SPI_BUFOVF_bm 0x01 /* Buffer Overflow (In Buffer Modes Only). bit mask. */ -#define SPI_BUFOVF_bp 0 /* Buffer Overflow (In Buffer Modes Only). bit position. */ - -/* SPI.CTRLB bit masks and bit positions */ -#define SPI_BUFMODE_gm 0xC0 /* Buffer Modes group mask. */ -#define SPI_BUFMODE_gp 6 /* Buffer Modes group position. */ -#define SPI_BUFMODE0_bm (1<<6) /* Buffer Modes bit 0 mask. */ -#define SPI_BUFMODE0_bp 6 /* Buffer Modes bit 0 position. */ -#define SPI_BUFMODE1_bm (1<<7) /* Buffer Modes bit 1 mask. */ -#define SPI_BUFMODE1_bp 7 /* Buffer Modes bit 1 position. */ - -#define SPI_SSD_bm 0x04 /* Slave Select Disable bit mask. */ -#define SPI_SSD_bp 2 /* Slave Select Disable bit position. */ - -/* IRCOM - IR Communication Module */ -/* IRCOM.CTRL bit masks and bit positions */ -#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ -#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ -#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ -#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ -#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ -#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ -#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ -#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ -#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ -#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ - -/* FUSE - Fuses and Lockbits */ -/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ -#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ - -#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ - -#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ - -#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ -#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ -#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ -#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ - -/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ -#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ -#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ -#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ -#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ -#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ -#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ -#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ -#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ -#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ -#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ - -#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ -#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ -#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ -#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ -#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ -#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ -#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ -#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ -#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ -#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ - -/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ -#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ -#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ - -#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ -#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ -#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ -#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ -#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ -#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ - -/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ -#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ -#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ - -#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ -#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ -#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ -#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ -#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ -#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ - -#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ -#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ - -/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ -#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ -#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ -#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ -#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ -#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ -#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ - -#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ -#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ - -#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ -#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ -#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ -#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ -#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ -#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ -#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ -#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ - -/* NVM_FUSES.FUSEBYTE6 bit masks and bit positions */ -#define NVM_FUSES_FDACT5_bm 0x80 /* Fault Dectection Action on TC5 bit mask. */ -#define NVM_FUSES_FDACT5_bp 7 /* Fault Dectection Action on TC5 bit position. */ - -#define NVM_FUSES_FDACT4_bm 0x40 /* Fault Dectection Action on TC4 bit mask. */ -#define NVM_FUSES_FDACT4_bp 6 /* Fault Dectection Action on TC4 bit position. */ - -#define NVM_FUSES_VALUE_gm 0x3F /* Port Pin Value group mask. */ -#define NVM_FUSES_VALUE_gp 0 /* Port Pin Value group position. */ -#define NVM_FUSES_VALUE0_bm (1<<0) /* Port Pin Value bit 0 mask. */ -#define NVM_FUSES_VALUE0_bp 0 /* Port Pin Value bit 0 position. */ -#define NVM_FUSES_VALUE1_bm (1<<1) /* Port Pin Value bit 1 mask. */ -#define NVM_FUSES_VALUE1_bp 1 /* Port Pin Value bit 1 position. */ -#define NVM_FUSES_VALUE2_bm (1<<2) /* Port Pin Value bit 2 mask. */ -#define NVM_FUSES_VALUE2_bp 2 /* Port Pin Value bit 2 position. */ -#define NVM_FUSES_VALUE3_bm (1<<3) /* Port Pin Value bit 3 mask. */ -#define NVM_FUSES_VALUE3_bp 3 /* Port Pin Value bit 3 position. */ -#define NVM_FUSES_VALUE4_bm (1<<4) /* Port Pin Value bit 4 mask. */ -#define NVM_FUSES_VALUE4_bp 4 /* Port Pin Value bit 4 position. */ -#define NVM_FUSES_VALUE5_bm (1<<5) /* Port Pin Value bit 5 mask. */ -#define NVM_FUSES_VALUE5_bp 5 /* Port Pin Value bit 5 position. */ - - - -// Generic Port Pins - -#define PIN0_bm 0x01 -#define PIN0_bp 0 -#define PIN1_bm 0x02 -#define PIN1_bp 1 -#define PIN2_bm 0x04 -#define PIN2_bp 2 -#define PIN3_bm 0x08 -#define PIN3_bp 3 -#define PIN4_bm 0x10 -#define PIN4_bp 4 -#define PIN5_bm 0x20 -#define PIN5_bp 5 -#define PIN6_bm 0x40 -#define PIN6_bp 6 -#define PIN7_bm 0x80 -#define PIN7_bp 7 - -/* ========== Interrupt Vector Definitions ========== */ -/* Vector 0 is the reset vector */ - -/* OSC interrupt vectors */ -#define OSC_OSCF_vect_num 1 -#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ - -/* PORTR interrupt vectors */ -#define PORTR_INT_vect_num 2 -#define PORTR_INT_vect _VECTOR(2) /* External Interrupt */ - -/* EDMA interrupt vectors */ -#define EDMA_CH0_vect_num 3 -#define EDMA_CH0_vect _VECTOR(3) /* EDMA Channel 0 Interrupt */ -#define EDMA_CH1_vect_num 4 -#define EDMA_CH1_vect _VECTOR(4) /* EDMA Channel 1 Interrupt */ -#define EDMA_CH2_vect_num 5 -#define EDMA_CH2_vect _VECTOR(5) /* EDMA Channel 2 Interrupt */ -#define EDMA_CH3_vect_num 6 -#define EDMA_CH3_vect _VECTOR(6) /* EDMA Channel 3 Interrupt */ - -/* RTC interrupt vectors */ -#define RTC_OVF_vect_num 7 -#define RTC_OVF_vect _VECTOR(7) /* Overflow Interrupt */ -#define RTC_COMP_vect_num 8 -#define RTC_COMP_vect _VECTOR(8) /* Compare Interrupt */ - -/* PORTC interrupt vectors */ -#define PORTC_INT_vect_num 9 -#define PORTC_INT_vect _VECTOR(9) /* External Interrupt */ - -/* TWIC interrupt vectors */ -#define TWIC_TWIS_vect_num 10 -#define TWIC_TWIS_vect _VECTOR(10) /* TWI Slave Interrupt */ -#define TWIC_TWIM_vect_num 11 -#define TWIC_TWIM_vect _VECTOR(11) /* TWI Master Interrupt */ - -/* TCC4 interrupt vectors */ -#define TCC4_OVF_vect_num 12 -#define TCC4_OVF_vect _VECTOR(12) /* Overflow Interrupt */ -#define TCC4_ERR_vect_num 13 -#define TCC4_ERR_vect _VECTOR(13) /* Error Interrupt */ -#define TCC4_CCA_vect_num 14 -#define TCC4_CCA_vect _VECTOR(14) /* Channel A Compare or Capture Interrupt */ -#define TCC4_CCB_vect_num 15 -#define TCC4_CCB_vect _VECTOR(15) /* Channel B Compare or Capture Interrupt */ -#define TCC4_CCC_vect_num 16 -#define TCC4_CCC_vect _VECTOR(16) /* Channel C Compare or Capture Interrupt */ -#define TCC4_CCD_vect_num 17 -#define TCC4_CCD_vect _VECTOR(17) /* Channel D Compare or Capture Interrupt */ - -/* TCC5 interrupt vectors */ -#define TCC5_OVF_vect_num 18 -#define TCC5_OVF_vect _VECTOR(18) /* Overflow Interrupt */ -#define TCC5_ERR_vect_num 19 -#define TCC5_ERR_vect _VECTOR(19) /* Error Interrupt */ -#define TCC5_CCA_vect_num 20 -#define TCC5_CCA_vect _VECTOR(20) /* Channel A Compare or Capture Interrupt */ -#define TCC5_CCB_vect_num 21 -#define TCC5_CCB_vect _VECTOR(21) /* Channel B Compare or Capture Interrupt */ - -/* SPIC interrupt vectors */ -#define SPIC_INT_vect_num 22 -#define SPIC_INT_vect _VECTOR(22) /* SPI Interrupt */ - -/* USARTC0 interrupt vectors */ -#define USARTC0_RXC_vect_num 23 -#define USARTC0_RXC_vect _VECTOR(23) /* Reception Complete Interrupt */ -#define USARTC0_DRE_vect_num 24 -#define USARTC0_DRE_vect _VECTOR(24) /* Data Register Empty Interrupt */ -#define USARTC0_TXC_vect_num 25 -#define USARTC0_TXC_vect _VECTOR(25) /* Transmission Complete Interrupt */ - -/* NVM interrupt vectors */ -#define NVM_EE_vect_num 26 -#define NVM_EE_vect _VECTOR(26) /* EE Interrupt */ -#define NVM_SPM_vect_num 27 -#define NVM_SPM_vect _VECTOR(27) /* SPM Interrupt */ - -/* XCL interrupt vectors */ -#define XCL_UNF_vect_num 28 -#define XCL_UNF_vect _VECTOR(28) /* Timer/Counter Underflow Interrupt */ -#define XCL_CC_vect_num 29 -#define XCL_CC_vect _VECTOR(29) /* Timer/Counter Compare or Capture Interrupt */ - -/* PORTA interrupt vectors */ -#define PORTA_INT_vect_num 30 -#define PORTA_INT_vect _VECTOR(30) /* External Interrupt */ - -/* ACA interrupt vectors */ -#define ACA_AC0_vect_num 31 -#define ACA_AC0_vect _VECTOR(31) /* AC0 Interrupt */ -#define ACA_AC1_vect_num 32 -#define ACA_AC1_vect _VECTOR(32) /* AC1 Interrupt */ -#define ACA_ACW_vect_num 33 -#define ACA_ACW_vect _VECTOR(33) /* ACW Window Mode Interrupt */ - -/* ADCA interrupt vectors */ -#define ADCA_CH0_vect_num 34 -#define ADCA_CH0_vect _VECTOR(34) /* ADC Channel Interrupt */ - -/* PORTD interrupt vectors */ -#define PORTD_INT_vect_num 35 -#define PORTD_INT_vect _VECTOR(35) /* External Interrupt */ - -/* TCD5 interrupt vectors */ -#define TCD5_OVF_vect_num 36 -#define TCD5_OVF_vect _VECTOR(36) /* Overflow Interrupt */ -#define TCD5_ERR_vect_num 37 -#define TCD5_ERR_vect _VECTOR(37) /* Error Interrupt */ -#define TCD5_CCA_vect_num 38 -#define TCD5_CCA_vect _VECTOR(38) /* Channel A Compare or Capture Interrupt */ -#define TCD5_CCB_vect_num 39 -#define TCD5_CCB_vect _VECTOR(39) /* Channel B Compare or Capture Interrupt */ - -/* USARTD0 interrupt vectors */ -#define USARTD0_RXC_vect_num 40 -#define USARTD0_RXC_vect _VECTOR(40) /* Reception Complete Interrupt */ -#define USARTD0_DRE_vect_num 41 -#define USARTD0_DRE_vect _VECTOR(41) /* Data Register Empty Interrupt */ -#define USARTD0_TXC_vect_num 42 -#define USARTD0_TXC_vect _VECTOR(42) /* Transmission Complete Interrupt */ - -#define _VECTOR_SIZE 4 /* Size of individual vector. */ -#define _VECTORS_SIZE (43 * _VECTOR_SIZE) - - -/* ========== Constants ========== */ - -#define PROGMEM_START (0x0000) -#define PROGMEM_SIZE (10240) -#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) - -#define APP_SECTION_START (0x0000) -#define APP_SECTION_SIZE (8192) -#define APP_SECTION_PAGE_SIZE (128) -#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) - -#define APPTABLE_SECTION_START (0x1800) -#define APPTABLE_SECTION_SIZE (2048) -#define APPTABLE_SECTION_PAGE_SIZE (128) -#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) - -#define BOOT_SECTION_START (0x2000) -#define BOOT_SECTION_SIZE (2048) -#define BOOT_SECTION_PAGE_SIZE (128) -#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) - -#define DATAMEM_START (0x0000) -#define DATAMEM_SIZE (9216) -#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) - -#define IO_START (0x0000) -#define IO_SIZE (4096) -#define IO_PAGE_SIZE (0) -#define IO_END (IO_START + IO_SIZE - 1) - -#define MAPPED_EEPROM_START (0x1000) -#define MAPPED_EEPROM_SIZE (512) -#define MAPPED_EEPROM_PAGE_SIZE (0) -#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) - -#define INTERNAL_SRAM_START (0x2000) -#define INTERNAL_SRAM_SIZE (1024) -#define INTERNAL_SRAM_PAGE_SIZE (0) -#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) - -#define EEPROM_START (0x0000) -#define EEPROM_SIZE (512) -#define EEPROM_PAGE_SIZE (32) -#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) - -#define SIGNATURES_START (0x0000) -#define SIGNATURES_SIZE (3) -#define SIGNATURES_PAGE_SIZE (0) -#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) - -#define FUSES_START (0x0000) -#define FUSES_SIZE (7) -#define FUSES_PAGE_SIZE (0) -#define FUSES_END (FUSES_START + FUSES_SIZE - 1) - -#define LOCKBITS_START (0x0000) -#define LOCKBITS_SIZE (1) -#define LOCKBITS_PAGE_SIZE (0) -#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) - -#define USER_SIGNATURES_START (0x0000) -#define USER_SIGNATURES_SIZE (128) -#define USER_SIGNATURES_PAGE_SIZE (128) -#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) - -#define PROD_SIGNATURES_START (0x0000) -#define PROD_SIGNATURES_SIZE (54) -#define PROD_SIGNATURES_PAGE_SIZE (128) -#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) - -#define FLASHSTART PROGMEM_START -#define FLASHEND PROGMEM_END -#define SPM_PAGESIZE 128 -#define RAMSTART INTERNAL_SRAM_START -#define RAMSIZE INTERNAL_SRAM_SIZE -#define RAMEND INTERNAL_SRAM_END -#define E2END EEPROM_END -#define E2PAGESIZE EEPROM_PAGE_SIZE - - -/* ========== Fuses ========== */ -#define FUSE_MEMORY_SIZE 7 - -/* Fuse Byte 0 Reserved */ - -/* Fuse Byte 1 */ -#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ -#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ -#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ -#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ -#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ -#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ -#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ -#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ -#define FUSE1_DEFAULT (0xFF) - -/* Fuse Byte 2 */ -#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ -#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ -#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ -#define FUSE2_DEFAULT (0xFF) - -/* Fuse Byte 3 Reserved */ - -/* Fuse Byte 4 */ -#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ -#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ -#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ -#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ -#define FUSE4_DEFAULT (0xFF) - -/* Fuse Byte 5 */ -#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ -#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ -#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ -#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ -#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ -#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ -#define FUSE5_DEFAULT (0xFF) - -/* Fuse Byte 6 */ -#define FUSE_VALUE0 (unsigned char)~_BV(0) /* Port Pin Value Bit 0 */ -#define FUSE_VALUE1 (unsigned char)~_BV(1) /* Port Pin Value Bit 1 */ -#define FUSE_VALUE2 (unsigned char)~_BV(2) /* Port Pin Value Bit 2 */ -#define FUSE_VALUE3 (unsigned char)~_BV(3) /* Port Pin Value Bit 3 */ -#define FUSE_VALUE4 (unsigned char)~_BV(4) /* Port Pin Value Bit 4 */ -#define FUSE_VALUE5 (unsigned char)~_BV(5) /* Port Pin Value Bit 5 */ -#define FUSE_FDACT4 (unsigned char)~_BV(6) /* Fault Dectection Action on TC4 */ -#define FUSE_FDACT5 (unsigned char)~_BV(7) /* Fault Dectection Action on TC5 */ -#define FUSE6_DEFAULT (0xFF) - -/* ========== Lock Bits ========== */ -#define __LOCK_BITS_EXIST -#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST -#define __BOOT_LOCK_APPLICATION_BITS_EXIST -#define __BOOT_LOCK_BOOT_BITS_EXIST - -/* ========== Signature ========== */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x93 -#define SIGNATURE_2 0x41 - -/* ========== Power Reduction Condition Definitions ========== */ - -/* PR.PRGEN */ -#define __AVR_HAVE_PRGEN (PR_XCL_bm|PR_RTC_bm|PR_EVSYS_bm|PR_EDMA_bm) -#define __AVR_HAVE_PRGEN_XCL -#define __AVR_HAVE_PRGEN_RTC -#define __AVR_HAVE_PRGEN_EVSYS -#define __AVR_HAVE_PRGEN_EDMA - -/* PR.PRPA */ -#define __AVR_HAVE_PRPA (PR_DAC_bm|PR_ADC_bm|PR_AC_bm) -#define __AVR_HAVE_PRPA_DAC -#define __AVR_HAVE_PRPA_ADC -#define __AVR_HAVE_PRPA_AC - -/* PR.PRPC */ -#define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC5_bm|PR_TC4_bm) -#define __AVR_HAVE_PRPC_TWI -#define __AVR_HAVE_PRPC_USART0 -#define __AVR_HAVE_PRPC_SPI -#define __AVR_HAVE_PRPC_HIRES -#define __AVR_HAVE_PRPC_TC5 -#define __AVR_HAVE_PRPC_TC4 - -/* PR.PRPD */ -#define __AVR_HAVE_PRPD (PR_USART0_bm|PR_TC5_bm) -#define __AVR_HAVE_PRPD_USART0 -#define __AVR_HAVE_PRPD_TC5 - - -#endif /* #ifdef _AVR_ATXMEGA8E5_H_INCLUDED */ - +/***************************************************************************** + * + * Copyright (C) 2016 Atmel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * * Neither the name of the copyright holders nor the names of + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ****************************************************************************/ + + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iox8e5.h" +#else +# error "Attempt to include more than one file." +#endif + +#ifndef _AVR_ATXMEGA8E5_H_INCLUDED +#define _AVR_ATXMEGA8E5_H_INCLUDED + +/* Ungrouped common registers */ +#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ + +/* Deprecated */ +#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ + +#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ +#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ +#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ +#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ +#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ +#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +#define SREG _SFR_MEM8(0x003F) /* Status Register */ + +/* C Language Only */ +#if !defined (__ASSEMBLER__) + +#include + +typedef volatile uint8_t register8_t; +typedef volatile uint16_t register16_t; +typedef volatile uint32_t register32_t; + + +#ifdef _WORDREGISTER +#undef _WORDREGISTER +#endif +#define _WORDREGISTER(regname) \ + __extension__ union \ + { \ + register16_t regname; \ + struct \ + { \ + register8_t regname ## L; \ + register8_t regname ## H; \ + }; \ + } + +#ifdef _DWORDREGISTER +#undef _DWORDREGISTER +#endif +#define _DWORDREGISTER(regname) \ + __extension__ union \ + { \ + register32_t regname; \ + struct \ + { \ + register8_t regname ## 0; \ + register8_t regname ## 1; \ + register8_t regname ## 2; \ + register8_t regname ## 3; \ + }; \ + } + + +/* +========================================================================== +IO Module Structures +========================================================================== +*/ + + +/* +-------------------------------------------------------------------------- +VPORT - Virtual Ports +-------------------------------------------------------------------------- +*/ + +/* Virtual Port */ +typedef struct VPORT_struct +{ + register8_t DIR; /* I/O Port Data Direction */ + register8_t OUT; /* I/O Port Output */ + register8_t IN; /* I/O Port Input */ + register8_t INTFLAGS; /* Interrupt Flag Register */ +} VPORT_t; + + +/* +-------------------------------------------------------------------------- +XOCD - On-Chip Debug System +-------------------------------------------------------------------------- +*/ + +/* On-Chip Debug System */ +typedef struct OCD_struct +{ + register8_t OCDR0; /* OCD Register 0 */ + register8_t OCDR1; /* OCD Register 1 */ +} OCD_t; + + +/* +-------------------------------------------------------------------------- +CPU - CPU +-------------------------------------------------------------------------- +*/ + +/* CCP signatures */ +typedef enum CCP_enum +{ + CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ + CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +} CCP_t; + + +/* +-------------------------------------------------------------------------- +CLK - Clock System +-------------------------------------------------------------------------- +*/ + +/* Clock System */ +typedef struct CLK_struct +{ + register8_t CTRL; /* Control Register */ + register8_t PSCTRL; /* Prescaler Control Register */ + register8_t LOCK; /* Lock register */ + register8_t RTCCTRL; /* RTC Control Register */ + register8_t reserved_0x04; +} CLK_t; + + +/* Power Reduction */ +typedef struct PR_struct +{ + register8_t PRGEN; /* General Power Reduction */ + register8_t PRPA; /* Power Reduction Port A */ + register8_t reserved_0x02; + register8_t PRPC; /* Power Reduction Port C */ + register8_t PRPD; /* Power Reduction Port D */ + register8_t reserved_0x05; + register8_t reserved_0x06; +} PR_t; + +/* System Clock Selection */ +typedef enum CLK_SCLKSEL_enum +{ + CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ + CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ + CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ + CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ + CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ + CLK_SCLKSEL_RC8M_gc = (0x05<<0), /* Internal 8 MHz RC Oscillator */ +} CLK_SCLKSEL_t; + +/* Prescaler A Division Factor */ +typedef enum CLK_PSADIV_enum +{ + CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ + CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ + CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ + CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ + CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ + CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ + CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ + CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ + CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ + CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ + CLK_PSADIV_6_gc = (0x13<<2), /* Divide by 6 */ + CLK_PSADIV_10_gc = (0x15<<2), /* Divide by 10 */ + CLK_PSADIV_12_gc = (0x17<<2), /* Divide by 12 */ + CLK_PSADIV_24_gc = (0x19<<2), /* Divide by 24 */ + CLK_PSADIV_48_gc = (0x1B<<2), /* Divide by 48 */ +} CLK_PSADIV_t; + +/* Prescaler B and C Division Factor */ +typedef enum CLK_PSBCDIV_enum +{ + CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ + CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ + CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ + CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ +} CLK_PSBCDIV_t; + +/* RTC Clock Source */ +typedef enum CLK_RTCSRC_enum +{ + CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ + CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ + CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ + CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ + CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ + CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ +} CLK_RTCSRC_t; + + +/* +-------------------------------------------------------------------------- +SLEEP - Sleep Controller +-------------------------------------------------------------------------- +*/ + +/* Sleep Controller */ +typedef struct SLEEP_struct +{ + register8_t CTRL; /* Control Register */ +} SLEEP_t; + +/* Sleep Mode */ +typedef enum SLEEP_SMODE_enum +{ + SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ + SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ + SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ + SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ + SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ +} SLEEP_SMODE_t; + + + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +#define SLEEP_MODE_PWR_SAVE (0x03<<1) +#define SLEEP_MODE_STANDBY (0x06<<1) +#define SLEEP_MODE_EXT_STANDBY (0x07<<1) +/* +-------------------------------------------------------------------------- +OSC - Oscillator +-------------------------------------------------------------------------- +*/ + +/* Oscillator */ +typedef struct OSC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t XOSCCTRL; /* External Oscillator Control Register */ + register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ + register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ + register8_t PLLCTRL; /* PLL Control Register */ + register8_t DFLLCTRL; /* DFLL Control Register */ + register8_t RC8MCAL; /* Internal 8 MHz RC Oscillator Calibration Register */ +} OSC_t; + +/* Oscillator Frequency Range */ +typedef enum OSC_FRQRANGE_enum +{ + OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ + OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ + OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ + OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ +} OSC_FRQRANGE_t; + +/* External Oscillator Selection and Startup Time */ +typedef enum OSC_XOSCSEL_enum +{ + OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock on port R1 - 6 CLK */ + OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ + OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ + OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ + OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ + OSC_XOSCSEL_EXTCLK_C4_gc = (0x14<<0), /* External Clock on port C4 - 6 CLK */ +} OSC_XOSCSEL_t; + +/* PLL Clock Source */ +typedef enum OSC_PLLSRC_enum +{ + OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ + OSC_PLLSRC_RC8M_gc = (0x01<<6), /* Internal 8 MHz RC Oscillator */ + OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ + OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ +} OSC_PLLSRC_t; + +/* 32 MHz DFLL Calibration Reference */ +typedef enum OSC_RC32MCREF_enum +{ + OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ + OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ +} OSC_RC32MCREF_t; + + +/* +-------------------------------------------------------------------------- +DFLL - DFLL +-------------------------------------------------------------------------- +*/ + +/* DFLL */ +typedef struct DFLL_struct +{ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x01; + register8_t CALA; /* Calibration Register A */ + register8_t CALB; /* Calibration Register B */ + register8_t COMP0; /* Oscillator Compare Register 0 */ + register8_t COMP1; /* Oscillator Compare Register 1 */ + register8_t COMP2; /* Oscillator Compare Register 2 */ + register8_t reserved_0x07; +} DFLL_t; + + +/* +-------------------------------------------------------------------------- +RST - Reset +-------------------------------------------------------------------------- +*/ + +/* Reset */ +typedef struct RST_struct +{ + register8_t STATUS; /* Status Register */ + register8_t CTRL; /* Control Register */ +} RST_t; + + +/* +-------------------------------------------------------------------------- +WDT - Watch-Dog Timer +-------------------------------------------------------------------------- +*/ + +/* Watch-Dog Timer */ +typedef struct WDT_struct +{ + register8_t CTRL; /* Control */ + register8_t WINCTRL; /* Windowed Mode Control */ + register8_t STATUS; /* Status */ +} WDT_t; + +/* Period setting */ +typedef enum WDT_PER_enum +{ + WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ + WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ + WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ + WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ + WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ + WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ + WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ + WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ + WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ + WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ + WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +} WDT_PER_t; + +/* Closed window period */ +typedef enum WDT_WPER_enum +{ + WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ + WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ + WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ + WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ + WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ + WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ + WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ + WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ + WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ + WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ + WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +} WDT_WPER_t; + + +/* +-------------------------------------------------------------------------- +MCU - MCU Control +-------------------------------------------------------------------------- +*/ + +/* MCU Control */ +typedef struct MCU_struct +{ + register8_t DEVID0; /* Device ID byte 0 */ + register8_t DEVID1; /* Device ID byte 1 */ + register8_t DEVID2; /* Device ID byte 2 */ + register8_t REVID; /* Revision ID */ + register8_t reserved_0x04; + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t ANAINIT; /* Analog Startup Delay */ + register8_t EVSYSLOCK; /* Event System Lock */ + register8_t WEXLOCK; /* WEX Lock */ + register8_t FAULTLOCK; /* FAULT Lock */ + register8_t reserved_0x0B; +} MCU_t; + + +/* +-------------------------------------------------------------------------- +PMIC - Programmable Multi-level Interrupt Controller +-------------------------------------------------------------------------- +*/ + +/* Programmable Multi-level Interrupt Controller */ +typedef struct PMIC_struct +{ + register8_t STATUS; /* Status Register */ + register8_t INTPRI; /* Interrupt Priority */ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x03; + register8_t reserved_0x04; + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; +} PMIC_t; + + +/* +-------------------------------------------------------------------------- +PORTCFG - Port Configuration +-------------------------------------------------------------------------- +*/ + +/* I/O port Configuration */ +typedef struct PORTCFG_struct +{ + register8_t MPCMASK; /* Multi-pin Configuration Mask */ + register8_t reserved_0x01; + register8_t reserved_0x02; + register8_t reserved_0x03; + register8_t CLKOUT; /* Clock Out Register */ + register8_t reserved_0x05; + register8_t ACEVOUT; /* Analog Comparator and Event Out Register */ + register8_t SRLCTRL; /* Slew Rate Limit Control Register */ +} PORTCFG_t; + +/* Clock and Event Output Port */ +typedef enum PORTCFG_CLKEVPIN_enum +{ + PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */ + PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */ +} PORTCFG_CLKEVPIN_t; + +/* RTC Clock Output Port */ +typedef enum PORTCFG_RTCCLKOUT_enum +{ + PORTCFG_RTCCLKOUT_OFF_gc = (0x00<<5), /* System Clock Output Disabled */ + PORTCFG_RTCCLKOUT_PC6_gc = (0x01<<5), /* System Clock Output on Port C pin 6 */ + PORTCFG_RTCCLKOUT_PD6_gc = (0x02<<5), /* System Clock Output on Port D pin 6 */ + PORTCFG_RTCCLKOUT_PR0_gc = (0x03<<5), /* System Clock Output on Port R pin 0 */ +} PORTCFG_RTCCLKOUT_t; + +/* Peripheral Clock Output Select */ +typedef enum PORTCFG_CLKOUTSEL_enum +{ + PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ + PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ + PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ +} PORTCFG_CLKOUTSEL_t; + +/* System Clock Output Port */ +typedef enum PORTCFG_CLKOUT_enum +{ + PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ + PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ + PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ + PORTCFG_CLKOUT_PR0_gc = (0x03<<0), /* System Clock Output on Port R pin 0 */ +} PORTCFG_CLKOUT_t; + +/* Analog Comparator Output Port */ +typedef enum PORTCFG_ACOUT_enum +{ + PORTCFG_ACOUT_PA_gc = (0x00<<6), /* Analog Comparator Outputs on Port A, Pin 6-7 */ + PORTCFG_ACOUT_PC_gc = (0x01<<6), /* Analog Comparator Outputs on Port C, Pin 6-7 */ + PORTCFG_ACOUT_PD_gc = (0x02<<6), /* Analog Comparator Outputs on Port D, Pin 6-7 */ + PORTCFG_ACOUT_PR_gc = (0x03<<6), /* Analog Comparator Outputs on Port R, Pin 0-1 */ +} PORTCFG_ACOUT_t; + +/* Event Output Port */ +typedef enum PORTCFG_EVOUT_enum +{ + PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ + PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel n Output on Port C pin 7 */ + PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel n Output on Port D pin 7 */ + PORTCFG_EVOUT_PR0_gc = (0x03<<4), /* Event Channel n Output on Port R pin 0 */ +} PORTCFG_EVOUT_t; + +/* Event Output Select */ +typedef enum PORTCFG_EVOUTSEL_enum +{ + PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ + PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ + PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ + PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ + PORTCFG_EVOUTSEL_4_gc = (0x04<<0), /* Event Channel 4 output to pin */ + PORTCFG_EVOUTSEL_5_gc = (0x05<<0), /* Event Channel 5 output to pin */ + PORTCFG_EVOUTSEL_6_gc = (0x06<<0), /* Event Channel 6 output to pin */ + PORTCFG_EVOUTSEL_7_gc = (0x07<<0), /* Event Channel 7 output to pin */ +} PORTCFG_EVOUTSEL_t; + + +/* +-------------------------------------------------------------------------- +CRC - Cyclic Redundancy Checker +-------------------------------------------------------------------------- +*/ + +/* Cyclic Redundancy Checker */ +typedef struct CRC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t reserved_0x02; + register8_t DATAIN; /* Data Input */ + register8_t CHECKSUM0; /* Checksum byte 0 */ + register8_t CHECKSUM1; /* Checksum byte 1 */ + register8_t CHECKSUM2; /* Checksum byte 2 */ + register8_t CHECKSUM3; /* Checksum byte 3 */ +} CRC_t; + +/* Reset */ +typedef enum CRC_RESET_enum +{ + CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ + CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ + CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ +} CRC_RESET_t; + +/* Input Source */ +typedef enum CRC_SOURCE_enum +{ + CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ + CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ + CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ + CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */ + CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */ + CRC_SOURCE_DMAC2_gc = (0x06<<0), /* DMAC Channel 2 */ + CRC_SOURCE_DMAC3_gc = (0x07<<0), /* DMAC Channel 3 */ +} CRC_SOURCE_t; + + +/* +-------------------------------------------------------------------------- +EDMA - Enhanced DMA Controller +-------------------------------------------------------------------------- +*/ + +/* EDMA Channel */ +typedef struct EDMA_CH_struct +{ + register8_t CTRLA; /* Channel Control A */ + register8_t CTRLB; /* Channel Control */ + register8_t ADDRCTRL; /* Memory Address Control for Peripheral Ch., or Source Address Control for Standard Ch. */ + register8_t DESTADDRCTRL; /* Destination Address Control for Standard Channels Only. */ + register8_t TRIGSRC; /* Channel Trigger Source */ + register8_t reserved_0x05; + _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count for Peripheral Ch., or Channel Block Transfer Count Low for Standard Ch. */ + _WORDREGISTER(ADDR); /* Channel Memory Address for Peripheral Ch., or Channel Source Address Low for Standard Ch. */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; + _WORDREGISTER(DESTADDR); /* Channel Destination Address for Standard Channels Only. */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; +} EDMA_CH_t; + + +/* Enhanced DMA Controller */ +typedef struct EDMA_struct +{ + register8_t CTRL; /* Control */ + register8_t reserved_0x01; + register8_t reserved_0x02; + register8_t INTFLAGS; /* Transfer Interrupt Status */ + register8_t STATUS; /* Status */ + register8_t reserved_0x05; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + EDMA_CH_t CH0; /* EDMA Channel 0 */ + EDMA_CH_t CH1; /* EDMA Channel 1 */ + EDMA_CH_t CH2; /* EDMA Channel 2 */ + EDMA_CH_t CH3; /* EDMA Channel 3 */ +} EDMA_t; + +/* Channel mode */ +typedef enum EDMA_CHMODE_enum +{ + EDMA_CHMODE_PER0123_gc = (0x00<<4), /* Channels 0, 1, 2 and 3 in peripheal conf. */ + EDMA_CHMODE_STD0_gc = (0x01<<4), /* Channel 0 in standard conf.; channels 2 and 3 in peripheral conf. */ + EDMA_CHMODE_STD2_gc = (0x02<<4), /* Channel 2 in standard conf.; channels 0 and 1 in peripheral conf. */ + EDMA_CHMODE_STD02_gc = (0x03<<4), /* Channels 0 and 2 in standard conf. */ +} EDMA_CHMODE_t; + +/* Double buffer mode */ +typedef enum EDMA_DBUFMODE_enum +{ + EDMA_DBUFMODE_DISABLE_gc = (0x00<<2), /* No double buffer enabled */ + EDMA_DBUFMODE_BUF01_gc = (0x01<<2), /* Double buffer enabled on peripheral channels 0/1 (if exist) */ + EDMA_DBUFMODE_BUF23_gc = (0x02<<2), /* Double buffer enabled on peripheral channels 2/3 (if exist) */ + EDMA_DBUFMODE_BUF0123_gc = (0x03<<2), /* Double buffer enabled on peripheral channels 0/1 and 2/3 or standard channels 0/2 */ +} EDMA_DBUFMODE_t; + +/* Priority mode */ +typedef enum EDMA_PRIMODE_enum +{ + EDMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round robin on all channels */ + EDMA_PRIMODE_RR123_gc = (0x01<<0), /* Ch0 > round robin (Ch 1 ch2 Ch3) */ + EDMA_PRIMODE_RR23_gc = (0x02<<0), /* Ch0 > Ch 1 > round robin (Ch2 Ch3) */ + EDMA_PRIMODE_CH0123_gc = (0x03<<0), /* Ch0 > Ch1 > Ch2 > Ch3 */ +} EDMA_PRIMODE_t; + +/* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. */ +typedef enum EDMA_CH_RELOAD_enum +{ + EDMA_CH_RELOAD_NONE_gc = (0x00<<4), /* No reload */ + EDMA_CH_RELOAD_BLOCK_gc = (0x01<<4), /* Reload at end of each block transfer */ + EDMA_CH_RELOAD_BURST_gc = (0x02<<4), /* Reload at end of each burst transfer */ + EDMA_CH_RELOAD_TRANSACTION_gc = (0x03<<4), /* Reload at end of each transaction */ +} EDMA_CH_RELOAD_t; + +/* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. */ +typedef enum EDMA_CH_DIR_enum +{ + EDMA_CH_DIR_FIXED_gc = (0x00<<0), /* Fixed */ + EDMA_CH_DIR_INC_gc = (0x01<<0), /* Increment */ + EDMA_CH_DIR_MP1_gc = (0x04<<0), /* If Peripheral Ch. (Per ==> Mem), 1-byte 'mask-match' (data: ADDRL, mask: ADDRH), else reserved conf. */ + EDMA_CH_DIR_MP2_gc = (0x05<<0), /* If Peripheral Ch. (Per ==> Mem), 1-byte 'OR-match' (data-1: ADDRL OR data-2: ADDRH), else reserved conf. */ + EDMA_CH_DIR_MP3_gc = (0x06<<0), /* If Peripheral Ch. (Per ==> Mem), 2-byte 'match' (data-1: ADDRL followed by data-2: ADDRH), else reserved conf. */ +} EDMA_CH_DIR_t; + +/* Destination addressing mode */ +typedef enum EDMA_CH_DESTDIR_enum +{ + EDMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ + EDMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ + EDMA_CH_DESTDIR_MP1_gc = (0x04<<0), /* 1-byte 'mask-match' (data: ADDRL, mask: ADDRH) */ + EDMA_CH_DESTDIR_MP2_gc = (0x05<<0), /* 1-byte 'OR-match' (data-1: ADDRL OR data-2: ADDRH) */ + EDMA_CH_DESTDIR_MP3_gc = (0x06<<0), /* 2-byte 'match' (data1: ADDRL followed by data2: ADDRH) */ +} EDMA_CH_DESTDIR_t; + +/* Transfer trigger source */ +typedef enum EDMA_CH_TRIGSRC_enum +{ + EDMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Software triggers only */ + EDMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event CH0 as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event CH1 as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event CH2 as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA CH0 as trigger */ + EDMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA CH0 as trigger */ + EDMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA CH1 as trigger */ + EDMA_CH_TRIGSRC_TCC4_OVF_gc = (0x40<<0), /* TCC4 overflow/underflow as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_TCC4_ERR_gc = (0x41<<0), /* TCC4 error as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_TCC4_CCA_gc = (0x42<<0), /* TCC4 compare or capture channel A as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_TCC4_CCB_gc = (0x43<<0), /* TCC4 compare or capture channel B as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_TCC4_CCC_gc = (0x44<<0), /* TCC4 compare or capture channel C as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_TCC4_CCD_gc = (0x45<<0), /* TCC4 compare or capture channel D as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_TCC5_OVF_gc = (0x46<<0), /* TCC5 overflow/underflow as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_TCC5_ERR_gc = (0x47<<0), /* TCC5 error as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_TCC5_CCA_gc = (0x48<<0), /* TCC5 compare or capture channel A as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_TCC5_CCB_gc = (0x49<<0), /* TCC5 compare or capture channel B as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_SPIC_RXC_gc = (0x4A<<0), /* SPI C transfer complete (SPI Standard Mode) or SPI C receive complete as trigger (SPI Buffer Modes) */ + EDMA_CH_TRIGSRC_SPIC_DRE_gc = (0x4B<<0), /* SPI C transfer complete (SPI Standard Mode) or SPI C data register empty as trigger (SPI Buffer modes) */ + EDMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4C<<0), /* USART C0 receive complete as trigger */ + EDMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4D<<0), /* USART C0 data register empty as trigger */ + EDMA_CH_TRIGSRC_TCD5_OVF_gc = (0x66<<0), /* TCD5 overflow/underflow as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_TCD5_ERR_gc = (0x67<<0), /* TCD5 error as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_TCD5_CCA_gc = (0x68<<0), /* TCD5 compare or capture channel A as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_TCD5_CCB_gc = (0x69<<0), /* TCD5 compare or capture channel B as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6C<<0), /* USART D0 receive complete as trigger */ + EDMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6D<<0), /* USART D0 data register empty as trigger */ +} EDMA_CH_TRIGSRC_t; + +/* Interrupt level */ +typedef enum EDMA_CH_INTLVL_enum +{ + EDMA_CH_INTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ + EDMA_CH_INTLVL_LO_gc = (0x01<<2), /* Low level */ + EDMA_CH_INTLVL_MED_gc = (0x02<<2), /* Medium level */ + EDMA_CH_INTLVL_HI_gc = (0x03<<2), /* High level */ +} EDMA_CH_INTLVL_t; + + +/* +-------------------------------------------------------------------------- +EVSYS - Event System +-------------------------------------------------------------------------- +*/ + +/* Event System */ +typedef struct EVSYS_struct +{ + register8_t CH0MUX; /* Event Channel 0 Multiplexer */ + register8_t CH1MUX; /* Event Channel 1 Multiplexer */ + register8_t CH2MUX; /* Event Channel 2 Multiplexer */ + register8_t CH3MUX; /* Event Channel 3 Multiplexer */ + register8_t CH4MUX; /* Event Channel 4 Multiplexer */ + register8_t CH5MUX; /* Event Channel 5 Multiplexer */ + register8_t CH6MUX; /* Event Channel 6 Multiplexer */ + register8_t CH7MUX; /* Event Channel 7 Multiplexer */ + register8_t CH0CTRL; /* Channel 0 Control Register */ + register8_t CH1CTRL; /* Channel 1 Control Register */ + register8_t CH2CTRL; /* Channel 2 Control Register */ + register8_t CH3CTRL; /* Channel 3 Control Register */ + register8_t CH4CTRL; /* Channel 4 Control Register */ + register8_t CH5CTRL; /* Channel 5 Control Register */ + register8_t CH6CTRL; /* Channel 6 Control Register */ + register8_t CH7CTRL; /* Channel 7 Control Register */ + register8_t STROBE; /* Event Strobe */ + register8_t DATA; /* Event Data */ + register8_t DFCTRL; /* Digital Filter Control Register */ +} EVSYS_t; + +/* Event Channel multiplexer input selection */ +typedef enum EVSYS_CHMUX_enum +{ + EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ + EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ + EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ + EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ + EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ + EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ + EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ + EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ + EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ + EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ + EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ + EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ + EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ + EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ + EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ + EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ + EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ + EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ + EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ + EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ + EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ + EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ + EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ + EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ + EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ + EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ + EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ + EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ + EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ + EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ + EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ + EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ + EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ + EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ + EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ + EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ + EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ + EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ + EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ + EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ + EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ + EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ + EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ + EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ + EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ + EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ + EVSYS_CHMUX_XCL_UNF0_gc = (0xB0<<0), /* XCL BTC0 underflow */ + EVSYS_CHMUX_XCL_UNF1_gc = (0xB1<<0), /* XCL BTC1 underflow */ + EVSYS_CHMUX_XCL_CC0_gc = (0xB2<<0), /* XCL BTC0 capture or compare */ + EVSYS_CHMUX_XCL_CC1_gc = (0xB3<<0), /* XCL BTC0 capture or compare */ + EVSYS_CHMUX_XCL_PEC0_gc = (0xB4<<0), /* XCL PEC0 restart */ + EVSYS_CHMUX_XCL_PEC1_gc = (0xB5<<0), /* XCL PEC1 restart */ + EVSYS_CHMUX_XCL_LUT0_gc = (0xB6<<0), /* XCL LUT0 output */ + EVSYS_CHMUX_XCL_LUT1_gc = (0xB7<<0), /* XCL LUT1 output */ + EVSYS_CHMUX_TCC4_OVF_gc = (0xC0<<0), /* Timer/Counter C4 Overflow */ + EVSYS_CHMUX_TCC4_ERR_gc = (0xC1<<0), /* Timer/Counter C4 Error */ + EVSYS_CHMUX_TCC4_CCA_gc = (0xC4<<0), /* Timer/Counter C4 Compare or Capture A */ + EVSYS_CHMUX_TCC4_CCB_gc = (0xC5<<0), /* Timer/Counter C4 Compare or Capture B */ + EVSYS_CHMUX_TCC4_CCC_gc = (0xC6<<0), /* Timer/Counter C4 Compare or Capture C */ + EVSYS_CHMUX_TCC4_CCD_gc = (0xC7<<0), /* Timer/Counter C4 Compare or Capture D */ + EVSYS_CHMUX_TCC5_OVF_gc = (0xC8<<0), /* Timer/Counter C5 Overflow */ + EVSYS_CHMUX_TCC5_ERR_gc = (0xC9<<0), /* Timer/Counter C5 Error */ + EVSYS_CHMUX_TCC5_CCA_gc = (0xCC<<0), /* Timer/Counter C5 Compare or Capture A */ + EVSYS_CHMUX_TCC5_CCB_gc = (0xCD<<0), /* Timer/Counter C5 Compare or Capture B */ + EVSYS_CHMUX_TCD5_OVF_gc = (0xD8<<0), /* Timer/Counter D5 Overflow */ + EVSYS_CHMUX_TCD5_ERR_gc = (0xD9<<0), /* Timer/Counter D5 Error */ + EVSYS_CHMUX_TCD5_CCA_gc = (0xDC<<0), /* Timer/Counter D5 Compare or Capture A */ + EVSYS_CHMUX_TCD5_CCB_gc = (0xDD<<0), /* Timer/Counter D5 Compare or Capture B */ +} EVSYS_CHMUX_t; + +/* Quadrature Decoder Index Recognition Mode */ +typedef enum EVSYS_QDIRM_enum +{ + EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ + EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ + EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ + EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ +} EVSYS_QDIRM_t; + +/* Digital filter coefficient */ +typedef enum EVSYS_DIGFILT_enum +{ + EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ + EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ + EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ + EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ + EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ + EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ + EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ + EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ +} EVSYS_DIGFILT_t; + +/* Prescaler Filter */ +typedef enum EVSYS_PRESCFILT_enum +{ + EVSYS_PRESCFILT_CH04_gc = (0x01<<4), /* Enable prescaler filter for either channel 0 or 4 */ + EVSYS_PRESCFILT_CH15_gc = (0x02<<4), /* Enable prescaler filter for either channel 1 or 5 */ + EVSYS_PRESCFILT_CH26_gc = (0x04<<4), /* Enable prescaler filter for either channel 2 or 6 */ + EVSYS_PRESCFILT_CH37_gc = (0x08<<4), /* Enable prescaler filter for either channel 3 or 7 */ +} EVSYS_PRESCFILT_t; + +/* Prescaler */ +typedef enum EVSYS_PRESCALER_enum +{ + EVSYS_PRESCALER_CLKPER_8_gc = (0x00<<0), /* CLKPER, divide by 8 */ + EVSYS_PRESCALER_CLKPER_64_gc = (0x01<<0), /* CLKPER, divide by 64 */ + EVSYS_PRESCALER_CLKPER_512_gc = (0x02<<0), /* CLKPER, divide by 512 */ + EVSYS_PRESCALER_CLKPER_4096_gc = (0x03<<0), /* CLKPER, divide by 4096 */ + EVSYS_PRESCALER_CLKPER_32768_gc = (0x04<<0), /* CLKPER, divide by 32768 */ +} EVSYS_PRESCALER_t; + + +/* +-------------------------------------------------------------------------- +NVM - Non Volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Non-volatile Memory Controller */ +typedef struct NVM_struct +{ + register8_t ADDR0; /* Address Register 0 */ + register8_t ADDR1; /* Address Register 1 */ + register8_t ADDR2; /* Address Register 2 */ + register8_t reserved_0x03; + register8_t DATA0; /* Data Register 0 */ + register8_t DATA1; /* Data Register 1 */ + register8_t DATA2; /* Data Register 2 */ + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t CMD; /* Command */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t reserved_0x0E; + register8_t STATUS; /* Status */ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ +} NVM_t; + +/* NVM Command */ +typedef enum NVM_CMD_enum +{ + NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ + NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ + NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ + NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ + NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ + NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ + NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ + NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ + NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ + NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ + NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ + NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ + NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ + NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ + NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ + NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ + NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ + NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ + NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ + NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ + NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ + NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ + NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ + NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ + NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ + NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ + NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ + NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ + NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ + NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ + NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ + NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ +} NVM_CMD_t; + +/* SPM ready interrupt level */ +typedef enum NVM_SPMLVL_enum +{ + NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ + NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ + NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ + NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ +} NVM_SPMLVL_t; + +/* EEPROM ready interrupt level */ +typedef enum NVM_EELVL_enum +{ + NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ + NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ + NVM_EELVL_HI_gc = (0x03<<0), /* High level */ +} NVM_EELVL_t; + +/* Boot lock bits - boot setcion */ +typedef enum NVM_BLBB_enum +{ + NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ + NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ + NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ + NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ +} NVM_BLBB_t; + +/* Boot lock bits - application section */ +typedef enum NVM_BLBA_enum +{ + NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ + NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ + NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ + NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ +} NVM_BLBA_t; + +/* Boot lock bits - application table section */ +typedef enum NVM_BLBAT_enum +{ + NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ + NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ + NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ + NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ +} NVM_BLBAT_t; + +/* Lock bits */ +typedef enum NVM_LB_enum +{ + NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ + NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ + NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ +} NVM_LB_t; + + +/* +-------------------------------------------------------------------------- +ADC - Analog/Digital Converter +-------------------------------------------------------------------------- +*/ + +/* ADC Channel */ +typedef struct ADC_CH_struct +{ + register8_t CTRL; /* Control Register */ + register8_t MUXCTRL; /* MUX Control */ + register8_t INTCTRL; /* Channel Interrupt Control Register */ + register8_t INTFLAGS; /* Interrupt Flags */ + _WORDREGISTER(RES); /* Channel Result */ + register8_t SCAN; /* Input Channel Scan */ + register8_t CORRCTRL; /* Correction Control Register */ + register8_t OFFSETCORR0; /* Offset Correction Register 0 */ + register8_t OFFSETCORR1; /* Offset Correction Register 1 */ + register8_t GAINCORR0; /* Gain Correction Register 0 */ + register8_t GAINCORR1; /* Gain Correction Register 1 */ + register8_t AVGCTRL; /* Average Control Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; +} ADC_CH_t; + + +/* Analog-to-Digital Converter */ +typedef struct ADC_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t REFCTRL; /* Reference Control */ + register8_t EVCTRL; /* Event Control */ + register8_t PRESCALER; /* Clock Prescaler */ + register8_t reserved_0x05; + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary Register */ + register8_t SAMPCTRL; /* ADC Sampling Time Control Register */ + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + _WORDREGISTER(CAL); /* Calibration Value */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + _WORDREGISTER(CH0RES); /* Channel 0 Result */ + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + _WORDREGISTER(CMP); /* Compare Value */ + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + ADC_CH_t CH0; /* ADC Channel 0 */ +} ADC_t; + +/* Current Limitation */ +typedef enum ADC_CURRLIMIT_enum +{ + ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ + ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 250ksps max sampling rate */ + ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ + ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 50ksps max sampling rate */ +} ADC_CURRLIMIT_t; + +/* Conversion result resolution */ +typedef enum ADC_RESOLUTION_enum +{ + ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ + ADC_RESOLUTION_MT12BIT_gc = (0x01<<1), /* More than 12-bit (oversapling) right-adjusted result */ + ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ + ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ +} ADC_RESOLUTION_t; + +/* Voltage reference selection */ +typedef enum ADC_REFSEL_enum +{ + ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ + ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ + ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ + ADC_REFSEL_AREFD_gc = (0x03<<4), /* External reference on PORT D */ + ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ +} ADC_REFSEL_t; + +/* Event channel input selection */ +typedef enum ADC_EVSEL_enum +{ + ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */ + ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */ + ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */ + ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */ + ADC_EVSEL_4_gc = (0x04<<3), /* Event Channel 4 */ + ADC_EVSEL_5_gc = (0x05<<3), /* Event Channel 5 */ + ADC_EVSEL_6_gc = (0x06<<3), /* Event Channel 6 */ + ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ +} ADC_EVSEL_t; + +/* Event action selection */ +typedef enum ADC_EVACT_enum +{ + ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ + ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel conversion */ + ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ +} ADC_EVACT_t; + +/* Clock prescaler */ +typedef enum ADC_PRESCALER_enum +{ + ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ + ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ + ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ + ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ + ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ + ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ + ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ + ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ +} ADC_PRESCALER_t; + +/* Gain factor */ +typedef enum ADC_CH_GAIN_enum +{ + ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ + ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ + ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ + ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ + ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ + ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ + ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ + ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ +} ADC_CH_GAIN_t; + +/* Input mode */ +typedef enum ADC_CH_INPUTMODE_enum +{ + ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ + ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ + ADC_CH_INPUTMODE_DIFFWGAINL_gc = (0x02<<0), /* Differential input, gain with 4 LSB pins selection */ + ADC_CH_INPUTMODE_DIFFWGAINH_gc = (0x03<<0), /* Differential input, gain with 4 MSB pins selection */ +} ADC_CH_INPUTMODE_t; + +/* Positive input multiplexer selection */ +typedef enum ADC_CH_MUXPOS_enum +{ + ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ + ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ + ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ + ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ + ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ + ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ + ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ + ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ + ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ + ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ + ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ + ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ + ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ + ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ + ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ + ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ +} ADC_CH_MUXPOS_t; + +/* Internal input multiplexer selections */ +typedef enum ADC_CH_MUXINT_enum +{ + ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ + ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ + ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 Scaled VCC */ + ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC Output */ +} ADC_CH_MUXINT_t; + +/* Negative input multiplexer selection when gain on 4 LSB pins */ +typedef enum ADC_CH_MUXNEGL_enum +{ + ADC_CH_MUXNEGL_PIN0_gc = (0x00<<0), /* Input pin 0 */ + ADC_CH_MUXNEGL_PIN1_gc = (0x01<<0), /* Input pin 1 */ + ADC_CH_MUXNEGL_PIN2_gc = (0x02<<0), /* Input pin 2 */ + ADC_CH_MUXNEGL_PIN3_gc = (0x03<<0), /* Input pin 3 */ + ADC_CH_MUXNEGL_GND_gc = (0x05<<0), /* PAD ground */ + ADC_CH_MUXNEGL_INTGND_gc = (0x07<<0), /* Internal ground */ +} ADC_CH_MUXNEGL_t; + +/* Negative input multiplexer selection when gain on 4 MSB pins */ +typedef enum ADC_CH_MUXNEGH_enum +{ + ADC_CH_MUXNEGH_PIN4_gc = (0x00<<0), /* Input pin 4 */ + ADC_CH_MUXNEGH_PIN5_gc = (0x01<<0), /* Input pin 5 */ + ADC_CH_MUXNEGH_PIN6_gc = (0x02<<0), /* Input pin 6 */ + ADC_CH_MUXNEGH_PIN7_gc = (0x03<<0), /* Input pin 7 */ + ADC_CH_MUXNEGH_GND_gc = (0x05<<0), /* PAD ground */ +} ADC_CH_MUXNEGH_t; + +/* Negative input multiplexer selection */ +typedef enum ADC_CH_MUXNEG_enum +{ + ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ +} ADC_CH_MUXNEG_t; + +/* Interupt mode */ +typedef enum ADC_CH_INTMODE_enum +{ + ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ + ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ + ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ +} ADC_CH_INTMODE_t; + +/* Interrupt level */ +typedef enum ADC_CH_INTLVL_enum +{ + ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ + ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ + ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ +} ADC_CH_INTLVL_t; + +/* Averaged Number of Samples */ +typedef enum ADC_SAMPNUM_enum +{ + ADC_SAMPNUM_1X_gc = (0x00<<0), /* 1 Sample */ + ADC_SAMPNUM_2X_gc = (0x01<<0), /* 2 Samples */ + ADC_SAMPNUM_4X_gc = (0x02<<0), /* 4 Samples */ + ADC_SAMPNUM_8X_gc = (0x03<<0), /* 8 Samples */ + ADC_SAMPNUM_16X_gc = (0x04<<0), /* 16 Samples */ + ADC_SAMPNUM_32X_gc = (0x05<<0), /* 32 Samples */ + ADC_SAMPNUM_64X_gc = (0x06<<0), /* 64 Samples */ + ADC_SAMPNUM_128X_gc = (0x07<<0), /* 128 Samples */ + ADC_SAMPNUM_256X_gc = (0x08<<0), /* 256 Samples */ + ADC_SAMPNUM_512X_gc = (0x09<<0), /* 512 Samples */ + ADC_SAMPNUM_1024X_gc = (0x0A<<0), /* 1024 Samples */ +} ADC_SAMPNUM_t; + + +/* +-------------------------------------------------------------------------- +DAC - Digital/Analog Converter +-------------------------------------------------------------------------- +*/ + +/* Digital-to-Analog Converter */ +typedef struct DAC_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t EVCTRL; /* Event Input Control */ + register8_t reserved_0x04; + register8_t STATUS; /* Status */ + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t CH0GAINCAL; /* Gain Calibration */ + register8_t CH0OFFSETCAL; /* Offset Calibration */ + register8_t CH1GAINCAL; /* Gain Calibration */ + register8_t CH1OFFSETCAL; /* Offset Calibration */ + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + _WORDREGISTER(CH0DATA); /* Channel 0 Data */ + _WORDREGISTER(CH1DATA); /* Channel 1 Data */ +} DAC_t; + +/* Output channel selection */ +typedef enum DAC_CHSEL_enum +{ + DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel 0 only) */ + DAC_CHSEL_SINGLE1_gc = (0x01<<5), /* Single channel operation (Channel 1 only) */ + DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (Channel 0 and channel 1) */ +} DAC_CHSEL_t; + +/* Reference voltage selection */ +typedef enum DAC_REFSEL_enum +{ + DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ + DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ + DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ + DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ +} DAC_REFSEL_t; + +/* Event channel selection */ +typedef enum DAC_EVSEL_enum +{ + DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ + DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ + DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ + DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ + DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ + DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ + DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ + DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ +} DAC_EVSEL_t; + + +/* +-------------------------------------------------------------------------- +AC - Analog Comparator +-------------------------------------------------------------------------- +*/ + +/* Analog Comparator */ +typedef struct AC_struct +{ + register8_t AC0CTRL; /* Analog Comparator 0 Control */ + register8_t AC1CTRL; /* Analog Comparator 1 Control */ + register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ + register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t WINCTRL; /* Window Mode Control */ + register8_t STATUS; /* Status */ + register8_t CURRCTRL; /* Current Source Control Register */ + register8_t CURRCALIB; /* Current Source Calibration Register */ +} AC_t; + +/* Interrupt mode */ +typedef enum AC_INTMODE_enum +{ + AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ + AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ + AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ +} AC_INTMODE_t; + +/* Interrupt level */ +typedef enum AC_INTLVL_enum +{ + AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ + AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ + AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ + AC_INTLVL_HI_gc = (0x03<<4), /* High level */ +} AC_INTLVL_t; + +/* Hysteresis mode selection */ +typedef enum AC_HYSMODE_enum +{ + AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ + AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ + AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ +} AC_HYSMODE_t; + +/* Positive input multiplexer selection */ +typedef enum AC_MUXPOS_enum +{ + AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ + AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ + AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ + AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ + AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ + AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ + AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ + AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ +} AC_MUXPOS_t; + +/* Negative input multiplexer selection */ +typedef enum AC_MUXNEG_enum +{ + AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ + AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ + AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ + AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ + AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ + AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ + AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ + AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ +} AC_MUXNEG_t; + +/* Windows interrupt mode */ +typedef enum AC_WINTMODE_enum +{ + AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ + AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ + AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ + AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ +} AC_WINTMODE_t; + +/* Window interrupt level */ +typedef enum AC_WINTLVL_enum +{ + AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ + AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ + AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ +} AC_WINTLVL_t; + +/* Window mode state */ +typedef enum AC_WSTATE_enum +{ + AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ + AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ + AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ +} AC_WSTATE_t; + + +/* +-------------------------------------------------------------------------- +RTC - Real-Time Clounter +-------------------------------------------------------------------------- +*/ + +/* Real-Time Counter */ +typedef struct RTC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary register */ + register8_t reserved_0x05; + register8_t CALIB; /* Calibration Register */ + register8_t reserved_0x07; + _WORDREGISTER(CNT); /* Count Register */ + _WORDREGISTER(PER); /* Period Register */ + _WORDREGISTER(COMP); /* Compare Register */ +} RTC_t; + +/* Prescaler Factor */ +typedef enum RTC_PRESCALER_enum +{ + RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ + RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ + RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ + RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ + RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ + RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ + RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ + RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ +} RTC_PRESCALER_t; + +/* Compare Interrupt level */ +typedef enum RTC_COMPINTLVL_enum +{ + RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ + RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ +} RTC_COMPINTLVL_t; + +/* Overflow Interrupt level */ +typedef enum RTC_OVFINTLVL_enum +{ + RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} RTC_OVFINTLVL_t; + + +/* +-------------------------------------------------------------------------- +XCL - XMEGA Custom Logic +-------------------------------------------------------------------------- +*/ + +/* XMEGA Custom Logic */ +typedef struct XCL_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t CTRLF; /* Control Register F */ + register8_t CTRLG; /* Control Register G */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t PLC; /* Peripheral Lenght Control Register */ + register8_t CNTL; /* Counter Register Low */ + register8_t CNTH; /* Counter Register High */ + register8_t CMPL; /* Compare Register Low */ + register8_t CMPH; /* Compare Register High */ + register8_t PERCAPTL; /* Period or Capture Register Low */ + register8_t PERCAPTH; /* Period or Capture Register High */ +} XCL_t; + +/* LUT0 Output Enable */ +typedef enum XCL_LUTOUTEN_enum +{ + XCL_LUTOUTEN_DISABLE_gc = (0x00<<6), /* LUT0 output disabled */ + XCL_LUTOUTEN_PIN0_gc = (0x01<<6), /* LUT0 Output to pin 0 */ + XCL_LUTOUTEN_PIN4_gc = (0x02<<6), /* LUT0 Output to pin 4 */ +} XCL_LUTOUTEN_t; + +/* Port Selection */ +typedef enum XCL_PORTSEL_enum +{ + XCL_PORTSEL_PC_gc = (0x00<<4), /* Port C for LUT or USARTC0 for PEC */ + XCL_PORTSEL_PD_gc = (0x01<<4), /* Port D for LUT or USARTD0 for PEC */ +} XCL_PORTSEL_t; + +/* LUT Configuration */ +typedef enum XCL_LUTCONF_enum +{ + XCL_LUTCONF_2LUT2IN_gc = (0x00<<0), /* 2-Input two LUT */ + XCL_LUTCONF_2LUT1IN_gc = (0x01<<0), /* Two LUT with duplicated input */ + XCL_LUTCONF_2LUT3IN_gc = (0x02<<0), /* Two LUT with one common input */ + XCL_LUTCONF_1LUT3IN_gc = (0x03<<0), /* 3-Input LUT */ + XCL_LUTCONF_MUX_gc = (0x04<<0), /* One LUT Mux */ + XCL_LUTCONF_DLATCH_gc = (0x05<<0), /* One D-Latch LUT */ + XCL_LUTCONF_RSLATCH_gc = (0x06<<0), /* One RS-Latch LUT */ + XCL_LUTCONF_DFF_gc = (0x07<<0), /* One DFF LUT */ +} XCL_LUTCONF_t; + +/* Input Selection */ +typedef enum XCL_INSEL_enum +{ + XCL_INSEL_EVSYS_gc = (0x00<<6), /* Event system selected as source */ + XCL_INSEL_XCL_gc = (0x01<<6), /* XCL selected as source */ + XCL_INSEL_PINL_gc = (0x02<<6), /* LSB port pin selected as source */ + XCL_INSEL_PINH_gc = (0x03<<6), /* MSB port pin selected as source */ +} XCL_INSEL_t; + +/* Delay Configuration on LUT */ +typedef enum XCL_DLYCONF_enum +{ + XCL_DLYCONF_DISABLE_gc = (0x00<<2), /* Delay element disabled */ + XCL_DLYCONF_IN_gc = (0x01<<2), /* Delay enabled on LUT input */ + XCL_DLYCONF_OUT_gc = (0x02<<2), /* Delay enabled on LUT output */ +} XCL_DLYCONF_t; + +/* Delay Selection */ +typedef enum XCL_DLYSEL_enum +{ + XCL_DLYSEL_DLY11_gc = (0x00<<4), /* One cycle delay for each LUT1 and LUT0 */ + XCL_DLYSEL_DLY12_gc = (0x01<<4), /* One cycle delay for LUT1 and two cycles for LUT0 */ + XCL_DLYSEL_DLY21_gc = (0x02<<4), /* Two cycles delay for LUT1 and one cycle for LUT0 */ + XCL_DLYSEL_DLY22_gc = (0x03<<4), /* Two cycle delays for each LUT1 and LUT0 */ +} XCL_DLYSEL_t; + +/* Clock Selection */ +typedef enum XCL_CLKSEL_enum +{ + XCL_CLKSEL_OFF_gc = (0x00<<0), /* OFF */ + XCL_CLKSEL_DIV1_gc = (0x01<<0), /* Prescaler clk */ + XCL_CLKSEL_DIV2_gc = (0x02<<0), /* Prescaler clk/2 */ + XCL_CLKSEL_DIV4_gc = (0x03<<0), /* Prescaler clk/4 */ + XCL_CLKSEL_DIV8_gc = (0x04<<0), /* Prescaler clk/8 */ + XCL_CLKSEL_DIV64_gc = (0x05<<0), /* Prescaler clk/64 */ + XCL_CLKSEL_DIV256_gc = (0x06<<0), /* Prescaler clk/256 */ + XCL_CLKSEL_DIV1024_gc = (0x07<<0), /* Prescaler clk/1024 */ + XCL_CLKSEL_EVCH0_gc = (0x08<<0), /* Event channel 0 */ + XCL_CLKSEL_EVCH1_gc = (0x09<<0), /* Event channel 1 */ + XCL_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event channel 2 */ + XCL_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event channel 3 */ + XCL_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event channel 4 */ + XCL_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event channel 5 */ + XCL_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event channel 6 */ + XCL_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event channel 7 */ +} XCL_CLKSEL_t; + +/* Timer/Counter Command Selection */ +typedef enum XCL_CMDSEL_enum +{ + XCL_CMDSEL_NONE_gc = (0x00<<7), /* None */ + XCL_CMDSEL_RESTART_gc = (0x01<<7), /* Force restart */ +} XCL_CMDSEL_t; + +/* Timer/Counter Selection */ +typedef enum XCL_TCSEL_enum +{ + XCL_TCSEL_TC16_gc = (0x00<<4), /* 16-bit timer/counter */ + XCL_TCSEL_BTC0_gc = (0x01<<4), /* One 8-bit timer/counter */ + XCL_TCSEL_BTC01_gc = (0x02<<4), /* Two 8-bit timer/counters */ + XCL_TCSEL_BTC0PEC1_gc = (0x03<<4), /* One 8-bit timer/counter and one 8-bit peripheral counter */ + XCL_TCSEL_PEC0BTC1_gc = (0x04<<4), /* One 8-bit timer/counter and one 8-bit peripheral counter */ + XCL_TCSEL_PEC01_gc = (0x05<<4), /* Two 8-bit peripheral counters */ + XCL_TCSEL_BTC0PEC2_gc = (0x06<<4), /* One 8-bit timer/counter and two 4-bit peripheral counters */ +} XCL_TCSEL_t; + +/* Timer/Counter Mode */ +typedef enum XCL_TCMODE_enum +{ + XCL_TCMODE_NORMAL_gc = (0x00<<0), /* Normal mode with compare/period */ + XCL_TCMODE_CAPT_gc = (0x01<<0), /* Capture mode */ + XCL_TCMODE_PWM_gc = (0x02<<0), /* Single Slope PWM */ +} XCL_TCMODE_t; + +/* Compare Output Value Timer */ +typedef enum XCL_CMPEN_enum +{ + XCL_CMPEN_CLEAR_gc = (0x00<<5), /* Clear WG Output */ + XCL_CMPEN_SET_gc = (0x01<<5), /* Set WG Output */ +} XCL_CMPEN_t; + +/* Command Enable */ +typedef enum XCL_CMDEN_enum +{ + XCL_CMDEN_DISABLE_gc = (0x00<<6), /* Command Ignored */ + XCL_CMDEN_CMD0_gc = (0x01<<6), /* Command valid for timer/counter 0 */ + XCL_CMDEN_CMD1_gc = (0x02<<6), /* Command valid for timer/counter 1 */ + XCL_CMDEN_CMD01_gc = (0x03<<6), /* Command valid for both timer/counter 0 and 1 */ +} XCL_CMDEN_t; + +/* Timer/Counter Event Source Selection */ +typedef enum XCL_EVSRC_enum +{ + XCL_EVSRC_EVCH0_gc = (0x00<<0), /* Event channel 0 */ + XCL_EVSRC_EVCH1_gc = (0x01<<0), /* Event channel 1 */ + XCL_EVSRC_EVCH2_gc = (0x02<<0), /* Event channel 2 */ + XCL_EVSRC_EVCH3_gc = (0x03<<0), /* Event channel 3 */ + XCL_EVSRC_EVCH4_gc = (0x04<<0), /* Event channel 4 */ + XCL_EVSRC_EVCH5_gc = (0x05<<0), /* Event channel 5 */ + XCL_EVSRC_EVCH6_gc = (0x06<<0), /* Event channel 6 */ + XCL_EVSRC_EVCH7_gc = (0x07<<0), /* Event channel 7 */ +} XCL_EVSRC_t; + +/* Timer/Counter Event Action Selection */ +typedef enum XCL_EVACT_enum +{ + XCL_EVACT_INPUT_gc = (0x00<<5), /* Input Capture */ + XCL_EVACT_FREQ_gc = (0x01<<5), /* Frequency Capture */ + XCL_EVACT_PW_gc = (0x02<<5), /* Pulse Width Capture */ + XCL_EVACT_RESTART_gc = (0x03<<5), /* Restart timer/counter */ +} XCL_EVACT_t; + +/* Underflow Interrupt level */ +typedef enum XCL_UNF_INTLVL_enum +{ + XCL_UNF_INTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + XCL_UNF_INTLVL_LO_gc = (0x01<<2), /* Low Level */ + XCL_UNF_INTLVL_MED_gc = (0x02<<2), /* Medium Level */ + XCL_UNF_INTLVL_HI_gc = (0x03<<2), /* High Level */ +} XCL_UNF_INTLVL_t; + +/* Compare/Capture Interrupt level */ +typedef enum XCL_CC_INTLVL_enum +{ + XCL_CC_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + XCL_CC_INTLVL_LO_gc = (0x01<<0), /* Low Level */ + XCL_CC_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ + XCL_CC_INTLVL_HI_gc = (0x03<<0), /* High Level */ +} XCL_CC_INTLVL_t; + + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* */ +typedef struct TWI_MASTER_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t STATUS; /* Status Register */ + register8_t BAUD; /* Baurd Rate Control Register */ + register8_t ADDR; /* Address Register */ + register8_t DATA; /* Data Register */ +} TWI_MASTER_t; + + +/* */ +typedef struct TWI_SLAVE_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t STATUS; /* Status Register */ + register8_t ADDR; /* Address Register */ + register8_t DATA; /* Data Register */ + register8_t ADDRMASK; /* Address Mask Register */ +} TWI_SLAVE_t; + + +/* */ +typedef struct TWI_TIMEOUT_struct +{ + register8_t TOS; /* Timeout Status Register */ + register8_t TOCONF; /* Timeout Configuration Register */ +} TWI_TIMEOUT_t; + + +/* Two-Wire Interface */ +typedef struct TWI_struct +{ + register8_t CTRL; /* TWI Common Control Register */ + TWI_MASTER_t MASTER; /* TWI master module */ + TWI_SLAVE_t SLAVE; /* TWI slave module */ + TWI_TIMEOUT_t TIMEOUT; /* TWI SMBUS timeout module */ +} TWI_t; + +/* SDA Hold Time */ +typedef enum TWI_SDAHOLD_enum +{ + TWI_SDAHOLD_OFF_gc = (0x00<<4), /* SDA Hold Time off */ + TWI_SDAHOLD_50NS_gc = (0x01<<4), /* SDA Hold Time 50 ns */ + TWI_SDAHOLD_300NS_gc = (0x02<<4), /* SDA Hold Time 300 ns */ + TWI_SDAHOLD_400NS_gc = (0x03<<4), /* SDA Hold Time 400 ns */ +} TWI_SDAHOLD_t; + +/* Master Interrupt Level */ +typedef enum TWI_MASTER_INTLVL_enum +{ + TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ + TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ +} TWI_MASTER_INTLVL_t; + +/* Inactive Timeout */ +typedef enum TWI_MASTER_TIMEOUT_enum +{ + TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ + TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ + TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ + TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +} TWI_MASTER_TIMEOUT_t; + +/* Master Command */ +typedef enum TWI_MASTER_CMD_enum +{ + TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ + TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ + TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +} TWI_MASTER_CMD_t; + +/* Master Bus State */ +typedef enum TWI_MASTER_BUSSTATE_enum +{ + TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ + TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ + TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ + TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +} TWI_MASTER_BUSSTATE_t; + +/* Slave Interrupt Level */ +typedef enum TWI_SLAVE_INTLVL_enum +{ + TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ + TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ +} TWI_SLAVE_INTLVL_t; + +/* Slave Command */ +typedef enum TWI_SLAVE_CMD_enum +{ + TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ + TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +} TWI_SLAVE_CMD_t; + +/* Master Timeout */ +typedef enum TWI_MASTER_TTIMEOUT_enum +{ + TWI_MASTER_TTIMEOUT_25MS_gc = (0x00<<0), /* 25 Milliseconds */ + TWI_MASTER_TTIMEOUT_24MS_gc = (0x01<<0), /* 24 Milliseconds */ + TWI_MASTER_TTIMEOUT_23MS_gc = (0x02<<0), /* 23 Milliseconds */ + TWI_MASTER_TTIMEOUT_22MS_gc = (0x03<<0), /* 22 Milliseconds */ + TWI_MASTER_TTIMEOUT_26MS_gc = (0x04<<0), /* 26 Milliseconds */ + TWI_MASTER_TTIMEOUT_27MS_gc = (0x05<<0), /* 27 Milliseconds */ + TWI_MASTER_TTIMEOUT_28MS_gc = (0x06<<0), /* 28 Milliseconds */ + TWI_MASTER_TTIMEOUT_29MS_gc = (0x07<<0), /* 29 Milliseconds */ +} TWI_MASTER_TTIMEOUT_t; + +/* Slave Ttimeout */ +typedef enum TWI_SLAVE_TTIMEOUT_enum +{ + TWI_SLAVE_TTIMEOUT_25MS_gc = (0x00<<5), /* 25 Milliseconds */ + TWI_SLAVE_TTIMEOUT_24MS_gc = (0x01<<5), /* 24 Milliseconds */ + TWI_SLAVE_TTIMEOUT_23MS_gc = (0x02<<5), /* 23 Milliseconds */ + TWI_SLAVE_TTIMEOUT_22MS_gc = (0x03<<5), /* 22 Milliseconds */ + TWI_SLAVE_TTIMEOUT_26MS_gc = (0x04<<5), /* 26 Milliseconds */ + TWI_SLAVE_TTIMEOUT_27MS_gc = (0x05<<5), /* 27 Milliseconds */ + TWI_SLAVE_TTIMEOUT_28MS_gc = (0x06<<5), /* 28 Milliseconds */ + TWI_SLAVE_TTIMEOUT_29MS_gc = (0x07<<5), /* 29 Milliseconds */ +} TWI_SLAVE_TTIMEOUT_t; + +/* Master/Slave Extend Timeout */ +typedef enum TWI_MASTER_TMSEXT_enum +{ + TWI_MASTER_TMSEXT_10MS25MS_gc = (0x00<<3), /* Tmext 10ms Tsext 25ms */ + TWI_MASTER_TMSEXT_9MS24MS_gc = (0x01<<3), /* Tmext 9ms Tsext 24ms */ + TWI_MASTER_TMSEXT_11MS26MS_gc = (0x02<<3), /* Tmext 11ms Tsext 26ms */ + TWI_MASTER_TMSEXT_12MS27MS_gc = (0x03<<3), /* Tmext 12ms Tsext 27ms */ +} TWI_MASTER_TMSEXT_t; + + +/* +-------------------------------------------------------------------------- +PORT - Port Configuration +-------------------------------------------------------------------------- +*/ + +/* I/O Ports */ +typedef struct PORT_struct +{ + register8_t DIR; /* I/O Port Data Direction */ + register8_t DIRSET; /* I/O Port Data Direction Set */ + register8_t DIRCLR; /* I/O Port Data Direction Clear */ + register8_t DIRTGL; /* I/O Port Data Direction Toggle */ + register8_t OUT; /* I/O Port Output */ + register8_t OUTSET; /* I/O Port Output Set */ + register8_t OUTCLR; /* I/O Port Output Clear */ + register8_t OUTTGL; /* I/O Port Output Toggle */ + register8_t IN; /* I/O port Input */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INTMASK; /* Port Interrupt Mask */ + register8_t reserved_0x0B; + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t REMAP; /* Pin Remap Register */ + register8_t reserved_0x0F; + register8_t PIN0CTRL; /* Pin 0 Control Register */ + register8_t PIN1CTRL; /* Pin 1 Control Register */ + register8_t PIN2CTRL; /* Pin 2 Control Register */ + register8_t PIN3CTRL; /* Pin 3 Control Register */ + register8_t PIN4CTRL; /* Pin 4 Control Register */ + register8_t PIN5CTRL; /* Pin 5 Control Register */ + register8_t PIN6CTRL; /* Pin 6 Control Register */ + register8_t PIN7CTRL; /* Pin 7 Control Register */ +} PORT_t; + +/* Port Interrupt Level */ +typedef enum PORT_INTLVL_enum +{ + PORT_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + PORT_INTLVL_LO_gc = (0x01<<0), /* Low Level */ + PORT_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ + PORT_INTLVL_HI_gc = (0x03<<0), /* High Level */ +} PORT_INTLVL_t; + +/* Output/Pull Configuration */ +typedef enum PORT_OPC_enum +{ + PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ + PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ + PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ + PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ + PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ + PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ + PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ + PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ +} PORT_OPC_t; + +/* Input/Sense Configuration */ +typedef enum PORT_ISC_enum +{ + PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ + PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ + PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ + PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ + PORT_ISC_FORCE_ENABLE_gc = (0x06<<0), /* Digital Input Buffer Forced Enable */ + PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ +} PORT_ISC_t; + + +/* +-------------------------------------------------------------------------- +TC - 16-bit Timer/Counter With PWM +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter 4 */ +typedef struct TC4_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t CTRLF; /* Control Register F */ + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G Set */ + register8_t CTRLHCLR; /* Control Register H Clear */ + register8_t CTRLHSET; /* Control Register H Set */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CCA); /* Compare or Capture A */ + _WORDREGISTER(CCB); /* Compare or Capture B */ + _WORDREGISTER(CCC); /* Compare or Capture C */ + _WORDREGISTER(CCD); /* Compare or Capture D */ + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ + _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ + _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ + _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ +} TC4_t; + + +/* 16-bit Timer/Counter 5 */ +typedef struct TC5_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t CTRLF; /* Control Register F */ + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G Set */ + register8_t CTRLHCLR; /* Control Register H Clear */ + register8_t CTRLHSET; /* Control Register H Set */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CCA); /* Compare or Capture A */ + _WORDREGISTER(CCB); /* Compare or Capture B */ + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t reserved_0x2E; + register8_t reserved_0x2F; + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ + _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ + register8_t reserved_0x3C; + register8_t reserved_0x3D; + register8_t reserved_0x3E; + register8_t reserved_0x3F; +} TC5_t; + +/* Clock Selection */ +typedef enum TC45_CLKSEL_enum +{ + TC45_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ + TC45_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ + TC45_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ + TC45_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ + TC45_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ + TC45_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ + TC45_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ + TC45_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ + TC45_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ + TC45_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ + TC45_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC45_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ + TC45_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ + TC45_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ + TC45_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ + TC45_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ +} TC45_CLKSEL_t; + +/* Byte Mode */ +typedef enum TC45_BYTEM_enum +{ + TC45_BYTEM_NORMAL_gc = (0x00<<6), /* 16-bit mode */ + TC45_BYTEM_BYTEMODE_gc = (0x01<<6), /* Timer/Counter Operating in Byte Mode Only */ +} TC45_BYTEM_t; + +/* Circular Enable Mode */ +typedef enum TC45_CIRCEN_enum +{ + TC45_CIRCEN_DISABLE_gc = (0x00<<4), /* Circular Buffer Disabled */ + TC45_CIRCEN_PER_gc = (0x01<<4), /* Circular Buffer Enabled on PER/PERBUF */ + TC45_CIRCEN_CCA_gc = (0x02<<4), /* Circular Buffer Enabled on CCA/CCABUF */ + TC45_CIRCEN_BOTH_gc = (0x03<<4), /* Circular Buffer Enabled on All Buffered Registers */ +} TC45_CIRCEN_t; + +/* Waveform Generation Mode */ +typedef enum TC45_WGMODE_enum +{ + TC45_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ + TC45_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ + TC45_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ + TC45_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ + TC45_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Both */ + TC45_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ +} TC45_WGMODE_t; + +/* Event Action */ +typedef enum TC45_EVACT_enum +{ + TC45_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ + TC45_EVACT_FMODE1_gc = (0x01<<5), /* Fault Mode 1 capture */ + TC45_EVACT_FMODE2_gc = (0x02<<5), /* Fault Mode 2 capture */ + TC45_EVACT_UPDOWN_gc = (0x03<<5), /* Up/down count */ + TC45_EVACT_QDEC_gc = (0x04<<5), /* Quadrature decode */ + TC45_EVACT_RESTART_gc = (0x05<<5), /* Restart */ + TC45_EVACT_PWF_gc = (0x06<<5), /* Pulse-width Capture */ +} TC45_EVACT_t; + +/* Event Selection */ +typedef enum TC45_EVSEL_enum +{ + TC45_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ + TC45_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ + TC45_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ + TC45_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC45_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ + TC45_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ + TC45_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ + TC45_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ + TC45_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ +} TC45_EVSEL_t; + +/* Compare or Capture Channel A Mode */ +typedef enum TC45_CCAMODE_enum +{ + TC45_CCAMODE_DISABLE_gc = (0x00<<0), /* Channel Disabled */ + TC45_CCAMODE_COMP_gc = (0x01<<0), /* Ouput Compare enabled */ + TC45_CCAMODE_CAPT_gc = (0x02<<0), /* Input Capture enabled */ + TC45_CCAMODE_BOTHCC_gc = (0x03<<0), /* Both Compare and Capture enabled */ +} TC45_CCAMODE_t; + +/* Compare or Capture Channel B Mode */ +typedef enum TC45_CCBMODE_enum +{ + TC45_CCBMODE_DISABLE_gc = (0x00<<2), /* Channel Disabled */ + TC45_CCBMODE_COMP_gc = (0x01<<2), /* Ouput Compare enabled */ + TC45_CCBMODE_CAPT_gc = (0x02<<2), /* Input Capture enabled */ + TC45_CCBMODE_BOTHCC_gc = (0x03<<2), /* Both Compare and Capture enabled */ +} TC45_CCBMODE_t; + +/* Compare or Capture Channel C Mode */ +typedef enum TC45_CCCMODE_enum +{ + TC45_CCCMODE_DISABLE_gc = (0x00<<4), /* Channel Disabled */ + TC45_CCCMODE_COMP_gc = (0x01<<4), /* Ouput Compare enabled */ + TC45_CCCMODE_CAPT_gc = (0x02<<4), /* Input Capture enabled */ + TC45_CCCMODE_BOTHCC_gc = (0x03<<4), /* Both Compare and Capture enabled */ +} TC45_CCCMODE_t; + +/* Compare or Capture Channel D Mode */ +typedef enum TC45_CCDMODE_enum +{ + TC45_CCDMODE_DISABLE_gc = (0x00<<6), /* Channel Disabled */ + TC45_CCDMODE_COMP_gc = (0x01<<6), /* Ouput Compare enabled */ + TC45_CCDMODE_CAPT_gc = (0x02<<6), /* Input Capture enabled */ + TC45_CCDMODE_BOTHCC_gc = (0x03<<6), /* Both Compare and Capture enabled */ +} TC45_CCDMODE_t; + +/* Compare or Capture Low Channel A Mode */ +typedef enum TC45_LCCAMODE_enum +{ + TC45_LCCAMODE_DISABLE_gc = (0x00<<0), /* Channel Disabled */ + TC45_LCCAMODE_COMP_gc = (0x01<<0), /* Ouput Compare enabled */ + TC45_LCCAMODE_CAPT_gc = (0x02<<0), /* Input Capture enabled */ + TC45_LCCAMODE_BOTHCC_gc = (0x03<<0), /* Both Compare and Capture enabled */ +} TC45_LCCAMODE_t; + +/* Compare or Capture Low Channel B Mode */ +typedef enum TC45_LCCBMODE_enum +{ + TC45_LCCBMODE_DISABLE_gc = (0x00<<2), /* Channel Disabled */ + TC45_LCCBMODE_COMP_gc = (0x01<<2), /* Ouput Compare enabled */ + TC45_LCCBMODE_CAPT_gc = (0x02<<2), /* Input Capture enabled */ + TC45_LCCBMODE_BOTHCC_gc = (0x03<<2), /* Both Compare and Capture enabled */ +} TC45_LCCBMODE_t; + +/* Compare or Capture Low Channel C Mode */ +typedef enum TC45_LCCCMODE_enum +{ + TC45_LCCCMODE_DISABLE_gc = (0x00<<4), /* Channel Disabled */ + TC45_LCCCMODE_COMP_gc = (0x01<<4), /* Ouput Compare enabled */ + TC45_LCCCMODE_CAPT_gc = (0x02<<4), /* Input Capture enabled */ + TC45_LCCCMODE_BOTHCC_gc = (0x03<<4), /* Both Compare and Capture enabled */ +} TC45_LCCCMODE_t; + +/* Compare or Capture Low Channel D Mode */ +typedef enum TC45_LCCDMODE_enum +{ + TC45_LCCDMODE_DISABLE_gc = (0x00<<6), /* Channel Disabled */ + TC45_LCCDMODE_COMP_gc = (0x01<<6), /* Ouput Compare enabled */ + TC45_LCCDMODE_CAPT_gc = (0x02<<6), /* Input Capture enabled */ + TC45_LCCDMODE_BOTHCC_gc = (0x03<<6), /* Both Compare and Capture enabled */ +} TC45_LCCDMODE_t; + +/* Compare or Capture High Channel A Mode */ +typedef enum TC45_HCCAMODE_enum +{ + TC45_HCCAMODE_DISABLE_gc = (0x00<<0), /* Channel Disabled */ + TC45_HCCAMODE_COMP_gc = (0x01<<0), /* Ouput Compare enabled */ + TC45_HCCAMODE_CAPT_gc = (0x02<<0), /* Input Capture enabled */ + TC45_HCCAMODE_BOTHCC_gc = (0x03<<0), /* Both Compare and Capture enabled */ +} TC45_HCCAMODE_t; + +/* Compare or Capture High Channel B Mode */ +typedef enum TC45_HCCBMODE_enum +{ + TC45_HCCBMODE_DISABLE_gc = (0x00<<2), /* Channel Disabled */ + TC45_HCCBMODE_COMP_gc = (0x01<<2), /* Ouput Compare enabled */ + TC45_HCCBMODE_CAPT_gc = (0x02<<2), /* Input Capture enabled */ + TC45_HCCBMODE_BOTHCC_gc = (0x03<<2), /* Both Compare and Capture enabled */ +} TC45_HCCBMODE_t; + +/* Compare or Capture High Channel C Mode */ +typedef enum TC45_HCCCMODE_enum +{ + TC45_HCCCMODE_DISABLE_gc = (0x00<<4), /* Channel Disabled */ + TC45_HCCCMODE_COMP_gc = (0x01<<4), /* Ouput Compare enabled */ + TC45_HCCCMODE_CAPT_gc = (0x02<<4), /* Input Capture enabled */ + TC45_HCCCMODE_BOTHCC_gc = (0x03<<4), /* Both Compare and Capture enabled */ +} TC45_HCCCMODE_t; + +/* Compare or Capture High Channel D Mode */ +typedef enum TC45_HCCDMODE_enum +{ + TC45_HCCDMODE_DISABLE_gc = (0x00<<6), /* Channel Disabled */ + TC45_HCCDMODE_COMP_gc = (0x01<<6), /* Ouput Compare enabled */ + TC45_HCCDMODE_CAPT_gc = (0x02<<6), /* Input Capture enabled */ + TC45_HCCDMODE_BOTHCC_gc = (0x03<<6), /* Both Compare and Capture enabled */ +} TC45_HCCDMODE_t; + +/* Timer Trigger Restart Interrupt Level */ +typedef enum TC45_TRGINTLVL_enum +{ + TC45_TRGINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + TC45_TRGINTLVL_LO_gc = (0x01<<4), /* Low Level */ + TC45_TRGINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + TC45_TRGINTLVL_HI_gc = (0x03<<4), /* High Level */ +} TC45_TRGINTLVL_t; + +/* Error Interrupt Level */ +typedef enum TC45_ERRINTLVL_enum +{ + TC45_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC45_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC45_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC45_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC45_ERRINTLVL_t; + +/* Overflow Interrupt Level */ +typedef enum TC45_OVFINTLVL_enum +{ + TC45_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC45_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC45_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC45_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC45_OVFINTLVL_t; + +/* Compare or Capture Channel A Interrupt Level */ +typedef enum TC45_CCAINTLVL_enum +{ + TC45_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC45_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC45_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC45_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC45_CCAINTLVL_t; + +/* Compare or Capture Channel B Interrupt Level */ +typedef enum TC45_CCBINTLVL_enum +{ + TC45_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC45_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC45_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC45_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC45_CCBINTLVL_t; + +/* Compare or Capture Channel C Interrupt Level */ +typedef enum TC45_CCCINTLVL_enum +{ + TC45_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + TC45_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + TC45_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + TC45_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} TC45_CCCINTLVL_t; + +/* Compare or Capture Channel D Interrupt Level */ +typedef enum TC45_CCDINTLVL_enum +{ + TC45_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TC45_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ + TC45_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TC45_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ +} TC45_CCDINTLVL_t; + +/* Compare or Capture Low Channel A Interrupt Level */ +typedef enum TC45_LCCAINTLVL_enum +{ + TC45_LCCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC45_LCCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC45_LCCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC45_LCCAINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC45_LCCAINTLVL_t; + +/* Compare or Capture Low Channel B Interrupt Level */ +typedef enum TC45_LCCBINTLVL_enum +{ + TC45_LCCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC45_LCCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC45_LCCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC45_LCCBINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC45_LCCBINTLVL_t; + +/* Compare or Capture Low Channel C Interrupt Level */ +typedef enum TC45_LCCCINTLVL_enum +{ + TC45_LCCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + TC45_LCCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + TC45_LCCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + TC45_LCCCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} TC45_LCCCINTLVL_t; + +/* Compare or Capture Low Channel D Interrupt Level */ +typedef enum TC45_LCCDINTLVL_enum +{ + TC45_LCCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TC45_LCCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ + TC45_LCCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TC45_LCCDINTLVL_HI_gc = (0x03<<6), /* High Level */ +} TC45_LCCDINTLVL_t; + +/* Timer/Counter Command */ +typedef enum TC45_CMD_enum +{ + TC45_CMD_NONE_gc = (0x00<<2), /* No Command */ + TC45_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TC45_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TC45_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TC45_CMD_t; + + +/* +-------------------------------------------------------------------------- +FAULT - Fault Extension +-------------------------------------------------------------------------- +*/ + +/* Fault Extension */ +typedef struct FAULT_struct +{ + register8_t CTRLA; /* Control A Register */ + register8_t CTRLB; /* Control B Register */ + register8_t CTRLC; /* Control C Register */ + register8_t CTRLD; /* Control D Register */ + register8_t CTRLE; /* Control E Register */ + register8_t STATUS; /* Status Register */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G set */ +} FAULT_t; + +/* Ramp Mode Selection */ +typedef enum FAULT_RAMP_enum +{ + FAULT_RAMP_RAMP1_gc = (0x00<<6), /* Normal Mode */ + FAULT_RAMP_RAMP2_gc = (0x02<<6), /* RAMP2 Mode */ +} FAULT_RAMP_t; + +/* Fault E Input Source Selection */ +typedef enum FAULT_SRCE_enum +{ + FAULT_SRCE_DISABLE_gc = (0x00<<0), /* Fault Protection Disabled */ + FAULT_SRCE_CHN_gc = (0x01<<0), /* Event Channel n */ + FAULT_SRCE_CHN1_gc = (0x02<<0), /* Event Channel n+1 */ + FAULT_SRCE_CHN2_gc = (0x03<<0), /* Event Channel n+2 */ +} FAULT_SRCE_t; + +/* Fault A Halt Action Selection */ +typedef enum FAULT_HALTA_enum +{ + FAULT_HALTA_DISABLE_gc = (0x00<<5), /* Halt Action Disabled */ + FAULT_HALTA_HW_gc = (0x01<<5), /* Hardware Halt Action */ + FAULT_HALTA_SW_gc = (0x02<<5), /* Software Halt Action */ +} FAULT_HALTA_t; + +/* Fault A Source Selection */ +typedef enum FAULT_SRCA_enum +{ + FAULT_SRCA_DISABLE_gc = (0x00<<0), /* Fault A Disabled */ + FAULT_SRCA_CHN_gc = (0x01<<0), /* Event Channel n */ + FAULT_SRCA_CHN1_gc = (0x02<<0), /* Event Channel n+1 */ + FAULT_SRCA_LINK_gc = (0x03<<0), /* Fault A linked to Fault B State from previous cycle */ +} FAULT_SRCA_t; + +/* Fault B Halt Action Selection */ +typedef enum FAULT_HALTB_enum +{ + FAULT_HALTB_DISABLE_gc = (0x00<<5), /* Halt Action Disabled */ + FAULT_HALTB_HW_gc = (0x01<<5), /* Hardware Halt Action */ + FAULT_HALTB_SW_gc = (0x02<<5), /* Software Halt Action */ +} FAULT_HALTB_t; + +/* Fault B Source Selection */ +typedef enum FAULT_SRCB_enum +{ + FAULT_SRCB_DISABLE_gc = (0x00<<0), /* Fault B disabled */ + FAULT_SRCB_CHN_gc = (0x01<<0), /* Event Channel n */ + FAULT_SRCB_CHN1_gc = (0x02<<0), /* Event Channel n+1 */ + FAULT_SRCB_LINK_gc = (0x03<<0), /* Fault B linked to Fault A State from previous cycle */ +} FAULT_SRCB_t; + +/* Channel index Command */ +typedef enum FAULT_IDXCMD_enum +{ + FAULT_IDXCMD_DISABLE_gc = (0x00<<3), /* Command Disabled */ + FAULT_IDXCMD_SET_gc = (0x01<<3), /* Force Cycle B in Next Cycle */ + FAULT_IDXCMD_CLEAR_gc = (0x02<<3), /* Force Cycle A in Next Cycle */ + FAULT_IDXCMD_HOLD_gc = (0x03<<3), /* Hold Current Cycle Index in Next Cycle */ +} FAULT_IDXCMD_t; + + +/* +-------------------------------------------------------------------------- +WEX - Waveform Extension +-------------------------------------------------------------------------- +*/ + +/* Waveform Extension */ +typedef struct WEX_struct +{ + register8_t CTRL; /* Control Register */ + register8_t DTBOTH; /* Dead-time Concurrent Write to Both Sides Register */ + register8_t DTLS; /* Dead-time Low Side Register */ + register8_t DTHS; /* Dead-time High Side Register */ + register8_t STATUSCLR; /* Status Clear Register */ + register8_t STATUSSET; /* Status Set Register */ + register8_t SWAP; /* Swap Register */ + register8_t PGO; /* Pattern Generation Override Register */ + register8_t PGV; /* Pattern Generation Value Register */ + register8_t reserved_0x09; + register8_t SWAPBUF; /* Dead Time Low Side Buffer */ + register8_t PGOBUF; /* Pattern Generation Overwrite Buffer Register */ + register8_t PGVBUF; /* Pattern Generation Value Buffer Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t OUTOVDIS; /* Output Override Disable Register */ +} WEX_t; + +/* Output Matrix Mode */ +typedef enum WEX_OTMX_enum +{ + WEX_OTMX_DEFAULT_gc = (0x00<<4), /* Default Ouput Matrix Mode */ + WEX_OTMX_FIRST_gc = (0x01<<4), /* First Output matrix Mode */ + WEX_OTMX_SECOND_gc = (0x02<<4), /* Second Output matrix Mode */ + WEX_OTMX_THIRD_gc = (0x03<<4), /* Third Output matrix Mode */ + WEX_OTMX_FOURTH_gc = (0x04<<4), /* Fourth Output matrix Mode */ +} WEX_OTMX_t; + + +/* +-------------------------------------------------------------------------- +HIRES - High-Resolution Extension +-------------------------------------------------------------------------- +*/ + +/* High-Resolution Extension */ +typedef struct HIRES_struct +{ + register8_t CTRLA; /* Control Register A */ +} HIRES_t; + +/* High Resolution Plus Mode */ +typedef enum HIRES_HRPLUS_enum +{ + HIRES_HRPLUS_NONE_gc = (0x00<<2), /* No Hi-Res Plus */ + HIRES_HRPLUS_HRP4_gc = (0x01<<2), /* Hi-Res Plus enabled on Timer 4 */ + HIRES_HRPLUS_HRP5_gc = (0x02<<2), /* Hi-Res Plus enabled on Timer 5 */ + HIRES_HRPLUS_BOTH_gc = (0x03<<2), /* Hi-Res Plus enabled on Timer 4 and 5 */ +} HIRES_HRPLUS_t; + +/* High Resolution Mode */ +typedef enum HIRES_HREN_enum +{ + HIRES_HREN_NONE_gc = (0x00<<0), /* No Hi-Res */ + HIRES_HREN_HRP4_gc = (0x01<<0), /* Hi-Res enabled on Timer 4 */ + HIRES_HREN_HRP5_gc = (0x02<<0), /* Hi-Res enabled on Timer 5 */ + HIRES_HREN_BOTH_gc = (0x03<<0), /* Hi-Res enabled on Timer 4 and 5 */ +} HIRES_HREN_t; + + +/* +-------------------------------------------------------------------------- +USART - Universal Asynchronous Receiver-Transmitter +-------------------------------------------------------------------------- +*/ + +/* Universal Synchronous/Asynchronous Receiver/Transmitter */ +typedef struct USART_struct +{ + register8_t DATA; /* Data Register */ + register8_t STATUS; /* Status Register */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t CTRLD; /* Control Register D */ + register8_t BAUDCTRLA; /* Baud Rate Control Register A */ + register8_t BAUDCTRLB; /* Baud Rate Control Register B */ +} USART_t; + +/* Receive Start Interrupt level */ +typedef enum USART_RXSINTLVL_enum +{ + USART_RXSINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + USART_RXSINTLVL_LO_gc = (0x01<<0), /* Low Level */ + USART_RXSINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + USART_RXSINTLVL_HI_gc = (0x03<<0), /* High Level */ +} USART_RXSINTLVL_t; + +/* Receive Complete Interrupt level */ +typedef enum USART_RXCINTLVL_enum +{ + USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} USART_RXCINTLVL_t; + +/* Transmit Complete Interrupt level */ +typedef enum USART_TXCINTLVL_enum +{ + USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ + USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ +} USART_TXCINTLVL_t; + +/* Data Register Empty Interrupt level */ +typedef enum USART_DREINTLVL_enum +{ + USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ + USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ +} USART_DREINTLVL_t; + +/* Character Size */ +typedef enum USART_CHSIZE_enum +{ + USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ + USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ + USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ + USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ + USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ +} USART_CHSIZE_t; + +/* Communication Mode */ +typedef enum USART_CMODE_enum +{ + USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ + USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ + USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ + USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +} USART_CMODE_t; + +/* Parity Mode */ +typedef enum USART_PMODE_enum +{ + USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ + USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ + USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +} USART_PMODE_t; + +/* Encoding and Decoding Type */ +typedef enum USART_DECTYPE_enum +{ + USART_DECTYPE_DATA_gc = (0x00<<4), /* DATA Field Encoding */ + USART_DECTYPE_SDATA_gc = (0x02<<4), /* Start and Data Fields Encoding */ + USART_DECTYPE_NOTSDATA_gc = (0x03<<4), /* Start and Data Fields Encoding, with invertion in START field */ +} USART_DECTYPE_t; + +/* XCL LUT Action */ +typedef enum USART_LUTACT_enum +{ + USART_LUTACT_OFF_gc = (0x00<<2), /* Standard Frame Configuration */ + USART_LUTACT_RX_gc = (0x01<<2), /* Receiver Decoding Enabled */ + USART_LUTACT_TX_gc = (0x02<<2), /* Transmitter Encoding Enabled */ + USART_LUTACT_BOTH_gc = (0x03<<2), /* Both Encoding and Decoding Enabled */ +} USART_LUTACT_t; + +/* XCL Peripheral Counter Action */ +typedef enum USART_PECACT_enum +{ + USART_PECACT_OFF_gc = (0x00<<0), /* Standard Mode */ + USART_PECACT_PEC0_gc = (0x01<<0), /* Variable Data Lenght in Reception */ + USART_PECACT_PEC1_gc = (0x02<<0), /* Variable Data Lenght in Transmission */ + USART_PECACT_PERC01_gc = (0x03<<0), /* Variable Data Lenght in both Reception and Transmission */ +} USART_PECACT_t; + + +/* +-------------------------------------------------------------------------- +SPI - Serial Peripheral Interface +-------------------------------------------------------------------------- +*/ + +/* Serial Peripheral Interface with Buffer Modes */ +typedef struct SPI_struct +{ + register8_t CTRL; /* Control Register */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t STATUS; /* Status Register */ + register8_t DATA; /* Data Register */ + register8_t CTRLB; /* Control Register B */ +} SPI_t; + +/* SPI Mode */ +typedef enum SPI_MODE_enum +{ + SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0, base clock at "0", sampling on leading edge (rising) & set-up on trailling edge (falling). */ + SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1, base clock at "0", set-up on leading edge (rising) & sampling on trailling edge (falling). */ + SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2, base clock at "1", sampling on leading edge (falling) & set-up on trailling edge (rising). */ + SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3, base clock at "1", set-up on leading edge (falling) & sampling on trailling edge (rising). */ +} SPI_MODE_t; + +/* Prescaler setting */ +typedef enum SPI_PRESCALER_enum +{ + SPI_PRESCALER_DIV4_gc = (0x00<<0), /* If CLK2X=1 CLKper/2, else (CLK2X=0) CLKper/4. */ + SPI_PRESCALER_DIV16_gc = (0x01<<0), /* If CLK2X=1 CLKper/8, else (CLK2X=0) CLKper/16. */ + SPI_PRESCALER_DIV64_gc = (0x02<<0), /* If CLK2X=1 CLKper/32, else (CLK2X=0) CLKper/64. */ + SPI_PRESCALER_DIV128_gc = (0x03<<0), /* If CLK2X=1 CLKper/64, else (CLK2X=0) CLKper/128. */ +} SPI_PRESCALER_t; + +/* Interrupt level */ +typedef enum SPI_INTLVL_enum +{ + SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ + SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ + SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ +} SPI_INTLVL_t; + +/* Buffer Modes */ +typedef enum SPI_BUFMODE_enum +{ + SPI_BUFMODE_OFF_gc = (0x00<<6), /* SPI Unbuffered Mode */ + SPI_BUFMODE_BUFMODE1_gc = (0x02<<6), /* Buffer Mode 1 (with dummy byte) */ + SPI_BUFMODE_BUFMODE2_gc = (0x03<<6), /* Buffer Mode 2 (no dummy byte) */ +} SPI_BUFMODE_t; + + +/* +-------------------------------------------------------------------------- +IRCOM - IR Communication Module +-------------------------------------------------------------------------- +*/ + +/* IR Communication Module */ +typedef struct IRCOM_struct +{ + register8_t CTRL; /* Control Register */ + register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ + register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ +} IRCOM_t; + +/* Event channel selection */ +typedef enum IRDA_EVSEL_enum +{ + IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ + IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ + IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ + IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ + IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ + IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ + IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ + IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ + IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ +} IRDA_EVSEL_t; + + +/* +-------------------------------------------------------------------------- +FUSE - Fuses and Lockbits +-------------------------------------------------------------------------- +*/ + +/* Lock Bits */ +typedef struct NVM_LOCKBITS_struct +{ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ +} NVM_LOCKBITS_t; + + +/* Fuses */ +typedef struct NVM_FUSES_struct +{ + register8_t reserved_0x00; + register8_t FUSEBYTE1; /* Watchdog Configuration */ + register8_t FUSEBYTE2; /* Reset Configuration */ + register8_t reserved_0x03; + register8_t FUSEBYTE4; /* Start-up Configuration */ + register8_t FUSEBYTE5; /* EESAVE and BOD Level */ + register8_t FUSEBYTE6; /* Fault State */ +} NVM_FUSES_t; + +/* Boot lock bits - boot setcion */ +typedef enum FUSE_BLBB_enum +{ + FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ + FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ + FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ + FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ +} FUSE_BLBB_t; + +/* Boot lock bits - application section */ +typedef enum FUSE_BLBA_enum +{ + FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ + FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ + FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ + FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ +} FUSE_BLBA_t; + +/* Boot lock bits - application table section */ +typedef enum FUSE_BLBAT_enum +{ + FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ + FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ + FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ + FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ +} FUSE_BLBAT_t; + +/* Lock bits */ +typedef enum FUSE_LB_enum +{ + FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ + FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ + FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ +} FUSE_LB_t; + +/* Boot Loader Section Reset Vector */ +typedef enum BOOTRST_enum +{ + BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ + BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ +} BOOTRST_t; + +/* BOD operation */ +typedef enum BOD_enum +{ + BOD_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ + BOD_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ + BOD_DISABLED_gc = (0x03<<4), /* BOD Disabled */ +} BOD_t; + +/* Watchdog (Window) Timeout Period */ +typedef enum WD_enum +{ + WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ + WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ + WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ + WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ + WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ + WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ + WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ + WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ + WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ + WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ + WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ +} WD_t; + +/* Start-up Time */ +typedef enum SUT_enum +{ + SUT_0MS_gc = (0x03<<2), /* 0 ms */ + SUT_4MS_gc = (0x01<<2), /* 4 ms */ + SUT_64MS_gc = (0x00<<2), /* 64 ms */ +} SUT_t; + +/* Brownout Detection Voltage Level */ +typedef enum BODLVL_enum +{ + BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ + BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ + BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ + BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ + BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ + BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ + BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ + BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ +} BODLVL_t; + + +/* +-------------------------------------------------------------------------- +SIGROW - Signature Row +-------------------------------------------------------------------------- +*/ + +/* Production Signatures */ +typedef struct NVM_PROD_SIGNATURES_struct +{ + register8_t RCOSC8M; /* RCOSC 8MHz Calibration Value */ + register8_t reserved_0x01; + register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ + register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ + register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ + register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ + register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ + register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ + register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ + register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t WAFNUM; /* Wafer Number */ + register8_t reserved_0x11; + register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ + register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ + register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ + register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t ROOMTEMP; /* Temperature corresponds to TEMPSENSE3/2 */ + register8_t HOTTEMP; /* Temperature corresponds to TEMPSENSE1/0 */ + register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ + register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + register8_t reserved_0x26; + register8_t reserved_0x27; + register8_t ACACURRCAL; /* ACA Current Calibration Byte */ + register8_t reserved_0x29; + register8_t reserved_0x2A; + register8_t reserved_0x2B; + register8_t TEMPSENSE2; /* Temperature Sensor Calibration Byte 2 */ + register8_t TEMPSENSE3; /* Temperature Sensor Calibration Byte 3 */ + register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ + register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ + register8_t DACA0OFFCAL; /* DACA0 Calibration Byte 0 */ + register8_t DACA0GAINCAL; /* DACA0 Calibration Byte 1 */ + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t DACA1OFFCAL; /* DACA1 Calibration Byte 0 */ + register8_t DACA1GAINCAL; /* DACA1 Calibration Byte 1 */ + register8_t reserved_0x36; + register8_t reserved_0x37; + register8_t reserved_0x38; + register8_t reserved_0x39; + register8_t reserved_0x3A; + register8_t reserved_0x3B; + register8_t reserved_0x3C; + register8_t reserved_0x3D; + register8_t reserved_0x3E; + register8_t reserved_0x3F; +} NVM_PROD_SIGNATURES_t; + +/* +========================================================================== +IO Module Instances. Mapped to memory. +========================================================================== +*/ + +#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ +#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ +#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ +#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ +#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ +#define CLK (*(CLK_t *) 0x0040) /* Clock System */ +#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ +#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ +#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ +#define PR (*(PR_t *) 0x0070) /* Power Reduction */ +#define RST (*(RST_t *) 0x0078) /* Reset */ +#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ +#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ +#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ +#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ +#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ +#define EDMA (*(EDMA_t *) 0x0100) /* Enhanced DMA Controller */ +#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ +#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ +#define DACA (*(DAC_t *) 0x0300) /* Digital-to-Analog Converter */ +#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ +#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ +#define XCL (*(XCL_t *) 0x0460) /* XMEGA Custom Logic */ +#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ +#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ +#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ +#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ +#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ +#define TCC4 (*(TC4_t *) 0x0800) /* 16-bit Timer/Counter 4 */ +#define TCC5 (*(TC5_t *) 0x0840) /* 16-bit Timer/Counter 5 */ +#define FAULTC4 (*(FAULT_t *) 0x0880) /* Fault Extension */ +#define FAULTC5 (*(FAULT_t *) 0x0890) /* Fault Extension */ +#define WEXC (*(WEX_t *) 0x08A0) /* Waveform Extension */ +#define HIRESC (*(HIRES_t *) 0x08B0) /* High-Resolution Extension */ +#define USARTC0 (*(USART_t *) 0x08C0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define SPIC (*(SPI_t *) 0x08E0) /* Serial Peripheral Interface with Buffer Modes */ +#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ +#define TCD5 (*(TC5_t *) 0x0940) /* 16-bit Timer/Counter 5 */ +#define USARTD0 (*(USART_t *) 0x09C0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ + + +#endif /* !defined (__ASSEMBLER__) */ + + +/* ========== Flattened fully qualified IO register names ========== */ + +/* GPIO - General Purpose IO Registers */ +#define GPIO_GPIOR0 _SFR_MEM8(0x0000) +#define GPIO_GPIOR1 _SFR_MEM8(0x0001) +#define GPIO_GPIOR2 _SFR_MEM8(0x0002) +#define GPIO_GPIOR3 _SFR_MEM8(0x0003) + +/* Deprecated */ +#define GPIO_GPIO0 _SFR_MEM8(0x0000) +#define GPIO_GPIO1 _SFR_MEM8(0x0001) +#define GPIO_GPIO2 _SFR_MEM8(0x0002) +#define GPIO_GPIO3 _SFR_MEM8(0x0003) + +/* NVM_FUSES - Fuses */ +#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) +#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) +#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) +#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) +#define FUSE_FUSEBYTE6 _SFR_MEM8(0x0006) + +/* NVM_LOCKBITS - Lock Bits */ +#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) + +/* NVM_PROD_SIGNATURES - Production Signatures */ +#define PRODSIGNATURES_RCOSC8M _SFR_MEM8(0x0000) +#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) +#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) +#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) +#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) +#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) +#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) +#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) +#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) +#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) +#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) +#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) +#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) +#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) +#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) +#define PRODSIGNATURES_ROOMTEMP _SFR_MEM8(0x001E) +#define PRODSIGNATURES_HOTTEMP _SFR_MEM8(0x001F) +#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) +#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) +#define PRODSIGNATURES_ACACURRCAL _SFR_MEM8(0x0028) +#define PRODSIGNATURES_TEMPSENSE2 _SFR_MEM8(0x002C) +#define PRODSIGNATURES_TEMPSENSE3 _SFR_MEM8(0x002D) +#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) +#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) +#define PRODSIGNATURES_DACA0OFFCAL _SFR_MEM8(0x0030) +#define PRODSIGNATURES_DACA0GAINCAL _SFR_MEM8(0x0031) +#define PRODSIGNATURES_DACA1OFFCAL _SFR_MEM8(0x0034) +#define PRODSIGNATURES_DACA1GAINCAL _SFR_MEM8(0x0035) + +/* VPORT - Virtual Port */ +#define VPORT0_DIR _SFR_MEM8(0x0010) +#define VPORT0_OUT _SFR_MEM8(0x0011) +#define VPORT0_IN _SFR_MEM8(0x0012) +#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) + +/* VPORT - Virtual Port */ +#define VPORT1_DIR _SFR_MEM8(0x0014) +#define VPORT1_OUT _SFR_MEM8(0x0015) +#define VPORT1_IN _SFR_MEM8(0x0016) +#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) + +/* VPORT - Virtual Port */ +#define VPORT2_DIR _SFR_MEM8(0x0018) +#define VPORT2_OUT _SFR_MEM8(0x0019) +#define VPORT2_IN _SFR_MEM8(0x001A) +#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) + +/* VPORT - Virtual Port */ +#define VPORT3_DIR _SFR_MEM8(0x001C) +#define VPORT3_OUT _SFR_MEM8(0x001D) +#define VPORT3_IN _SFR_MEM8(0x001E) +#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) + +/* OCD - On-Chip Debug System */ +#define OCD_OCDR0 _SFR_MEM8(0x002E) +#define OCD_OCDR1 _SFR_MEM8(0x002F) + +/* CPU - CPU registers */ +#define CPU_CCP _SFR_MEM8(0x0034) +#define CPU_RAMPD _SFR_MEM8(0x0038) +#define CPU_RAMPX _SFR_MEM8(0x0039) +#define CPU_RAMPY _SFR_MEM8(0x003A) +#define CPU_RAMPZ _SFR_MEM8(0x003B) +#define CPU_EIND _SFR_MEM8(0x003C) +#define CPU_SPL _SFR_MEM8(0x003D) +#define CPU_SPH _SFR_MEM8(0x003E) +#define CPU_SREG _SFR_MEM8(0x003F) + +/* CLK - Clock System */ +#define CLK_CTRL _SFR_MEM8(0x0040) +#define CLK_PSCTRL _SFR_MEM8(0x0041) +#define CLK_LOCK _SFR_MEM8(0x0042) +#define CLK_RTCCTRL _SFR_MEM8(0x0043) + +/* SLEEP - Sleep Controller */ +#define SLEEP_CTRL _SFR_MEM8(0x0048) + +/* OSC - Oscillator */ +#define OSC_CTRL _SFR_MEM8(0x0050) +#define OSC_STATUS _SFR_MEM8(0x0051) +#define OSC_XOSCCTRL _SFR_MEM8(0x0052) +#define OSC_XOSCFAIL _SFR_MEM8(0x0053) +#define OSC_RC32KCAL _SFR_MEM8(0x0054) +#define OSC_PLLCTRL _SFR_MEM8(0x0055) +#define OSC_DFLLCTRL _SFR_MEM8(0x0056) +#define OSC_RC8MCAL _SFR_MEM8(0x0057) + +/* DFLL - DFLL */ +#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) +#define DFLLRC32M_CALA _SFR_MEM8(0x0062) +#define DFLLRC32M_CALB _SFR_MEM8(0x0063) +#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) +#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) +#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) + +/* PR - Power Reduction */ +#define PR_PRGEN _SFR_MEM8(0x0070) +#define PR_PRPA _SFR_MEM8(0x0071) +#define PR_PRPC _SFR_MEM8(0x0073) +#define PR_PRPD _SFR_MEM8(0x0074) + +/* RST - Reset */ +#define RST_STATUS _SFR_MEM8(0x0078) +#define RST_CTRL _SFR_MEM8(0x0079) + +/* WDT - Watch-Dog Timer */ +#define WDT_CTRL _SFR_MEM8(0x0080) +#define WDT_WINCTRL _SFR_MEM8(0x0081) +#define WDT_STATUS _SFR_MEM8(0x0082) + +/* MCU - MCU Control */ +#define MCU_DEVID0 _SFR_MEM8(0x0090) +#define MCU_DEVID1 _SFR_MEM8(0x0091) +#define MCU_DEVID2 _SFR_MEM8(0x0092) +#define MCU_REVID _SFR_MEM8(0x0093) +#define MCU_ANAINIT _SFR_MEM8(0x0097) +#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) +#define MCU_WEXLOCK _SFR_MEM8(0x0099) +#define MCU_FAULTLOCK _SFR_MEM8(0x009A) + +/* PMIC - Programmable Multi-level Interrupt Controller */ +#define PMIC_STATUS _SFR_MEM8(0x00A0) +#define PMIC_INTPRI _SFR_MEM8(0x00A1) +#define PMIC_CTRL _SFR_MEM8(0x00A2) + +/* PORTCFG - I/O port Configuration */ +#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) +#define PORTCFG_CLKOUT _SFR_MEM8(0x00B4) +#define PORTCFG_ACEVOUT _SFR_MEM8(0x00B6) +#define PORTCFG_SRLCTRL _SFR_MEM8(0x00B7) + +/* CRC - Cyclic Redundancy Checker */ +#define CRC_CTRL _SFR_MEM8(0x00D0) +#define CRC_STATUS _SFR_MEM8(0x00D1) +#define CRC_DATAIN _SFR_MEM8(0x00D3) +#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) +#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) +#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) +#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) + +/* EDMA - Enhanced DMA Controller */ +#define EDMA_CTRL _SFR_MEM8(0x0100) +#define EDMA_INTFLAGS _SFR_MEM8(0x0103) +#define EDMA_STATUS _SFR_MEM8(0x0104) +#define EDMA_TEMP _SFR_MEM8(0x0106) +#define EDMA_CH0_CTRLA _SFR_MEM8(0x0110) +#define EDMA_CH0_CTRLB _SFR_MEM8(0x0111) +#define EDMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) +#define EDMA_CH0_DESTADDRCTRL _SFR_MEM8(0x0113) +#define EDMA_CH0_TRIGSRC _SFR_MEM8(0x0114) +#define EDMA_CH0_TRFCNT _SFR_MEM16(0x0116) +#define EDMA_CH0_ADDR _SFR_MEM16(0x0118) +#define EDMA_CH0_DESTADDR _SFR_MEM16(0x011C) +#define EDMA_CH1_CTRLA _SFR_MEM8(0x0120) +#define EDMA_CH1_CTRLB _SFR_MEM8(0x0121) +#define EDMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) +#define EDMA_CH1_DESTADDRCTRL _SFR_MEM8(0x0123) +#define EDMA_CH1_TRIGSRC _SFR_MEM8(0x0124) +#define EDMA_CH1_TRFCNT _SFR_MEM16(0x0126) +#define EDMA_CH1_ADDR _SFR_MEM16(0x0128) +#define EDMA_CH1_DESTADDR _SFR_MEM16(0x012C) +#define EDMA_CH2_CTRLA _SFR_MEM8(0x0130) +#define EDMA_CH2_CTRLB _SFR_MEM8(0x0131) +#define EDMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) +#define EDMA_CH2_DESTADDRCTRL _SFR_MEM8(0x0133) +#define EDMA_CH2_TRIGSRC _SFR_MEM8(0x0134) +#define EDMA_CH2_TRFCNT _SFR_MEM16(0x0136) +#define EDMA_CH2_ADDR _SFR_MEM16(0x0138) +#define EDMA_CH2_DESTADDR _SFR_MEM16(0x013C) +#define EDMA_CH3_CTRLA _SFR_MEM8(0x0140) +#define EDMA_CH3_CTRLB _SFR_MEM8(0x0141) +#define EDMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) +#define EDMA_CH3_DESTADDRCTRL _SFR_MEM8(0x0143) +#define EDMA_CH3_TRIGSRC _SFR_MEM8(0x0144) +#define EDMA_CH3_TRFCNT _SFR_MEM16(0x0146) +#define EDMA_CH3_ADDR _SFR_MEM16(0x0148) +#define EDMA_CH3_DESTADDR _SFR_MEM16(0x014C) + +/* EVSYS - Event System */ +#define EVSYS_CH0MUX _SFR_MEM8(0x0180) +#define EVSYS_CH1MUX _SFR_MEM8(0x0181) +#define EVSYS_CH2MUX _SFR_MEM8(0x0182) +#define EVSYS_CH3MUX _SFR_MEM8(0x0183) +#define EVSYS_CH4MUX _SFR_MEM8(0x0184) +#define EVSYS_CH5MUX _SFR_MEM8(0x0185) +#define EVSYS_CH6MUX _SFR_MEM8(0x0186) +#define EVSYS_CH7MUX _SFR_MEM8(0x0187) +#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) +#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) +#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) +#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) +#define EVSYS_CH4CTRL _SFR_MEM8(0x018C) +#define EVSYS_CH5CTRL _SFR_MEM8(0x018D) +#define EVSYS_CH6CTRL _SFR_MEM8(0x018E) +#define EVSYS_CH7CTRL _SFR_MEM8(0x018F) +#define EVSYS_STROBE _SFR_MEM8(0x0190) +#define EVSYS_DATA _SFR_MEM8(0x0191) +#define EVSYS_DFCTRL _SFR_MEM8(0x0192) + +/* NVM - Non-volatile Memory Controller */ +#define NVM_ADDR0 _SFR_MEM8(0x01C0) +#define NVM_ADDR1 _SFR_MEM8(0x01C1) +#define NVM_ADDR2 _SFR_MEM8(0x01C2) +#define NVM_DATA0 _SFR_MEM8(0x01C4) +#define NVM_DATA1 _SFR_MEM8(0x01C5) +#define NVM_DATA2 _SFR_MEM8(0x01C6) +#define NVM_CMD _SFR_MEM8(0x01CA) +#define NVM_CTRLA _SFR_MEM8(0x01CB) +#define NVM_CTRLB _SFR_MEM8(0x01CC) +#define NVM_INTCTRL _SFR_MEM8(0x01CD) +#define NVM_STATUS _SFR_MEM8(0x01CF) +#define NVM_LOCKBITS _SFR_MEM8(0x01D0) + +/* ADC - Analog-to-Digital Converter */ +#define ADCA_CTRLA _SFR_MEM8(0x0200) +#define ADCA_CTRLB _SFR_MEM8(0x0201) +#define ADCA_REFCTRL _SFR_MEM8(0x0202) +#define ADCA_EVCTRL _SFR_MEM8(0x0203) +#define ADCA_PRESCALER _SFR_MEM8(0x0204) +#define ADCA_INTFLAGS _SFR_MEM8(0x0206) +#define ADCA_TEMP _SFR_MEM8(0x0207) +#define ADCA_SAMPCTRL _SFR_MEM8(0x0208) +#define ADCA_CAL _SFR_MEM16(0x020C) +#define ADCA_CH0RES _SFR_MEM16(0x0210) +#define ADCA_CMP _SFR_MEM16(0x0218) +#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) +#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) +#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) +#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) +#define ADCA_CH0_RES _SFR_MEM16(0x0224) +#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) +#define ADCA_CH0_CORRCTRL _SFR_MEM8(0x0227) +#define ADCA_CH0_OFFSETCORR0 _SFR_MEM8(0x0228) +#define ADCA_CH0_OFFSETCORR1 _SFR_MEM8(0x0229) +#define ADCA_CH0_GAINCORR0 _SFR_MEM8(0x022A) +#define ADCA_CH0_GAINCORR1 _SFR_MEM8(0x022B) +#define ADCA_CH0_AVGCTRL _SFR_MEM8(0x022C) + +/* DAC - Digital-to-Analog Converter */ +#define DACA_CTRLA _SFR_MEM8(0x0300) +#define DACA_CTRLB _SFR_MEM8(0x0301) +#define DACA_CTRLC _SFR_MEM8(0x0302) +#define DACA_EVCTRL _SFR_MEM8(0x0303) +#define DACA_STATUS _SFR_MEM8(0x0305) +#define DACA_CH0GAINCAL _SFR_MEM8(0x0308) +#define DACA_CH0OFFSETCAL _SFR_MEM8(0x0309) +#define DACA_CH1GAINCAL _SFR_MEM8(0x030A) +#define DACA_CH1OFFSETCAL _SFR_MEM8(0x030B) +#define DACA_CH0DATA _SFR_MEM16(0x0318) +#define DACA_CH1DATA _SFR_MEM16(0x031A) + +/* AC - Analog Comparator */ +#define ACA_AC0CTRL _SFR_MEM8(0x0380) +#define ACA_AC1CTRL _SFR_MEM8(0x0381) +#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) +#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) +#define ACA_CTRLA _SFR_MEM8(0x0384) +#define ACA_CTRLB _SFR_MEM8(0x0385) +#define ACA_WINCTRL _SFR_MEM8(0x0386) +#define ACA_STATUS _SFR_MEM8(0x0387) +#define ACA_CURRCTRL _SFR_MEM8(0x0388) +#define ACA_CURRCALIB _SFR_MEM8(0x0389) + +/* RTC - Real-Time Counter */ +#define RTC_CTRL _SFR_MEM8(0x0400) +#define RTC_STATUS _SFR_MEM8(0x0401) +#define RTC_INTCTRL _SFR_MEM8(0x0402) +#define RTC_INTFLAGS _SFR_MEM8(0x0403) +#define RTC_TEMP _SFR_MEM8(0x0404) +#define RTC_CALIB _SFR_MEM8(0x0406) +#define RTC_CNT _SFR_MEM16(0x0408) +#define RTC_PER _SFR_MEM16(0x040A) +#define RTC_COMP _SFR_MEM16(0x040C) + +/* XCL - XMEGA Custom Logic */ +#define XCL_CTRLA _SFR_MEM8(0x0460) +#define XCL_CTRLB _SFR_MEM8(0x0461) +#define XCL_CTRLC _SFR_MEM8(0x0462) +#define XCL_CTRLD _SFR_MEM8(0x0463) +#define XCL_CTRLE _SFR_MEM8(0x0464) +#define XCL_CTRLF _SFR_MEM8(0x0465) +#define XCL_CTRLG _SFR_MEM8(0x0466) +#define XCL_INTCTRL _SFR_MEM8(0x0467) +#define XCL_INTFLAGS _SFR_MEM8(0x0468) +#define XCL_PLC _SFR_MEM8(0x0469) +#define XCL_CNTL _SFR_MEM8(0x046A) +#define XCL_CNTH _SFR_MEM8(0x046B) +#define XCL_CMPL _SFR_MEM8(0x046C) +#define XCL_CMPH _SFR_MEM8(0x046D) +#define XCL_PERCAPTL _SFR_MEM8(0x046E) +#define XCL_PERCAPTH _SFR_MEM8(0x046F) + +/* TWI - Two-Wire Interface */ +#define TWIC_CTRL _SFR_MEM8(0x0480) +#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) +#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) +#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) +#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) +#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) +#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) +#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) +#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) +#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) +#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) +#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) +#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) +#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) +#define TWIC_TIMEOUT_TOS _SFR_MEM8(0x048E) +#define TWIC_TIMEOUT_TOCONF _SFR_MEM8(0x048F) + +/* PORT - I/O Ports */ +#define PORTA_DIR _SFR_MEM8(0x0600) +#define PORTA_DIRSET _SFR_MEM8(0x0601) +#define PORTA_DIRCLR _SFR_MEM8(0x0602) +#define PORTA_DIRTGL _SFR_MEM8(0x0603) +#define PORTA_OUT _SFR_MEM8(0x0604) +#define PORTA_OUTSET _SFR_MEM8(0x0605) +#define PORTA_OUTCLR _SFR_MEM8(0x0606) +#define PORTA_OUTTGL _SFR_MEM8(0x0607) +#define PORTA_IN _SFR_MEM8(0x0608) +#define PORTA_INTCTRL _SFR_MEM8(0x0609) +#define PORTA_INTMASK _SFR_MEM8(0x060A) +#define PORTA_INTFLAGS _SFR_MEM8(0x060C) +#define PORTA_REMAP _SFR_MEM8(0x060E) +#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) +#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) +#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) +#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) +#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) +#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) +#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) +#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) + +/* PORT - I/O Ports */ +#define PORTC_DIR _SFR_MEM8(0x0640) +#define PORTC_DIRSET _SFR_MEM8(0x0641) +#define PORTC_DIRCLR _SFR_MEM8(0x0642) +#define PORTC_DIRTGL _SFR_MEM8(0x0643) +#define PORTC_OUT _SFR_MEM8(0x0644) +#define PORTC_OUTSET _SFR_MEM8(0x0645) +#define PORTC_OUTCLR _SFR_MEM8(0x0646) +#define PORTC_OUTTGL _SFR_MEM8(0x0647) +#define PORTC_IN _SFR_MEM8(0x0648) +#define PORTC_INTCTRL _SFR_MEM8(0x0649) +#define PORTC_INTMASK _SFR_MEM8(0x064A) +#define PORTC_INTFLAGS _SFR_MEM8(0x064C) +#define PORTC_REMAP _SFR_MEM8(0x064E) +#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) +#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) +#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) +#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) +#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) +#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) +#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) +#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) + +/* PORT - I/O Ports */ +#define PORTD_DIR _SFR_MEM8(0x0660) +#define PORTD_DIRSET _SFR_MEM8(0x0661) +#define PORTD_DIRCLR _SFR_MEM8(0x0662) +#define PORTD_DIRTGL _SFR_MEM8(0x0663) +#define PORTD_OUT _SFR_MEM8(0x0664) +#define PORTD_OUTSET _SFR_MEM8(0x0665) +#define PORTD_OUTCLR _SFR_MEM8(0x0666) +#define PORTD_OUTTGL _SFR_MEM8(0x0667) +#define PORTD_IN _SFR_MEM8(0x0668) +#define PORTD_INTCTRL _SFR_MEM8(0x0669) +#define PORTD_INTMASK _SFR_MEM8(0x066A) +#define PORTD_INTFLAGS _SFR_MEM8(0x066C) +#define PORTD_REMAP _SFR_MEM8(0x066E) +#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) +#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) +#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) +#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) +#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) +#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) +#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) +#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) + +/* PORT - I/O Ports */ +#define PORTR_DIR _SFR_MEM8(0x07E0) +#define PORTR_DIRSET _SFR_MEM8(0x07E1) +#define PORTR_DIRCLR _SFR_MEM8(0x07E2) +#define PORTR_DIRTGL _SFR_MEM8(0x07E3) +#define PORTR_OUT _SFR_MEM8(0x07E4) +#define PORTR_OUTSET _SFR_MEM8(0x07E5) +#define PORTR_OUTCLR _SFR_MEM8(0x07E6) +#define PORTR_OUTTGL _SFR_MEM8(0x07E7) +#define PORTR_IN _SFR_MEM8(0x07E8) +#define PORTR_INTCTRL _SFR_MEM8(0x07E9) +#define PORTR_INTMASK _SFR_MEM8(0x07EA) +#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) +#define PORTR_REMAP _SFR_MEM8(0x07EE) +#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) +#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) +#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) +#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) +#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) +#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) +#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) +#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) + +/* TC4 - 16-bit Timer/Counter 4 */ +#define TCC4_CTRLA _SFR_MEM8(0x0800) +#define TCC4_CTRLB _SFR_MEM8(0x0801) +#define TCC4_CTRLC _SFR_MEM8(0x0802) +#define TCC4_CTRLD _SFR_MEM8(0x0803) +#define TCC4_CTRLE _SFR_MEM8(0x0804) +#define TCC4_CTRLF _SFR_MEM8(0x0805) +#define TCC4_INTCTRLA _SFR_MEM8(0x0806) +#define TCC4_INTCTRLB _SFR_MEM8(0x0807) +#define TCC4_CTRLGCLR _SFR_MEM8(0x0808) +#define TCC4_CTRLGSET _SFR_MEM8(0x0809) +#define TCC4_CTRLHCLR _SFR_MEM8(0x080A) +#define TCC4_CTRLHSET _SFR_MEM8(0x080B) +#define TCC4_INTFLAGS _SFR_MEM8(0x080C) +#define TCC4_TEMP _SFR_MEM8(0x080F) +#define TCC4_CNT _SFR_MEM16(0x0820) +#define TCC4_PER _SFR_MEM16(0x0826) +#define TCC4_CCA _SFR_MEM16(0x0828) +#define TCC4_CCB _SFR_MEM16(0x082A) +#define TCC4_CCC _SFR_MEM16(0x082C) +#define TCC4_CCD _SFR_MEM16(0x082E) +#define TCC4_PERBUF _SFR_MEM16(0x0836) +#define TCC4_CCABUF _SFR_MEM16(0x0838) +#define TCC4_CCBBUF _SFR_MEM16(0x083A) +#define TCC4_CCCBUF _SFR_MEM16(0x083C) +#define TCC4_CCDBUF _SFR_MEM16(0x083E) + +/* TC5 - 16-bit Timer/Counter 5 */ +#define TCC5_CTRLA _SFR_MEM8(0x0840) +#define TCC5_CTRLB _SFR_MEM8(0x0841) +#define TCC5_CTRLC _SFR_MEM8(0x0842) +#define TCC5_CTRLD _SFR_MEM8(0x0843) +#define TCC5_CTRLE _SFR_MEM8(0x0844) +#define TCC5_CTRLF _SFR_MEM8(0x0845) +#define TCC5_INTCTRLA _SFR_MEM8(0x0846) +#define TCC5_INTCTRLB _SFR_MEM8(0x0847) +#define TCC5_CTRLGCLR _SFR_MEM8(0x0848) +#define TCC5_CTRLGSET _SFR_MEM8(0x0849) +#define TCC5_CTRLHCLR _SFR_MEM8(0x084A) +#define TCC5_CTRLHSET _SFR_MEM8(0x084B) +#define TCC5_INTFLAGS _SFR_MEM8(0x084C) +#define TCC5_TEMP _SFR_MEM8(0x084F) +#define TCC5_CNT _SFR_MEM16(0x0860) +#define TCC5_PER _SFR_MEM16(0x0866) +#define TCC5_CCA _SFR_MEM16(0x0868) +#define TCC5_CCB _SFR_MEM16(0x086A) +#define TCC5_PERBUF _SFR_MEM16(0x0876) +#define TCC5_CCABUF _SFR_MEM16(0x0878) +#define TCC5_CCBBUF _SFR_MEM16(0x087A) + +/* FAULT - Fault Extension */ +#define FAULTC4_CTRLA _SFR_MEM8(0x0880) +#define FAULTC4_CTRLB _SFR_MEM8(0x0881) +#define FAULTC4_CTRLC _SFR_MEM8(0x0882) +#define FAULTC4_CTRLD _SFR_MEM8(0x0883) +#define FAULTC4_CTRLE _SFR_MEM8(0x0884) +#define FAULTC4_STATUS _SFR_MEM8(0x0885) +#define FAULTC4_CTRLGCLR _SFR_MEM8(0x0886) +#define FAULTC4_CTRLGSET _SFR_MEM8(0x0887) + +/* FAULT - Fault Extension */ +#define FAULTC5_CTRLA _SFR_MEM8(0x0890) +#define FAULTC5_CTRLB _SFR_MEM8(0x0891) +#define FAULTC5_CTRLC _SFR_MEM8(0x0892) +#define FAULTC5_CTRLD _SFR_MEM8(0x0893) +#define FAULTC5_CTRLE _SFR_MEM8(0x0894) +#define FAULTC5_STATUS _SFR_MEM8(0x0895) +#define FAULTC5_CTRLGCLR _SFR_MEM8(0x0896) +#define FAULTC5_CTRLGSET _SFR_MEM8(0x0897) + +/* WEX - Waveform Extension */ +#define WEXC_CTRL _SFR_MEM8(0x08A0) +#define WEXC_DTBOTH _SFR_MEM8(0x08A1) +#define WEXC_DTLS _SFR_MEM8(0x08A2) +#define WEXC_DTHS _SFR_MEM8(0x08A3) +#define WEXC_STATUSCLR _SFR_MEM8(0x08A4) +#define WEXC_STATUSSET _SFR_MEM8(0x08A5) +#define WEXC_SWAP _SFR_MEM8(0x08A6) +#define WEXC_PGO _SFR_MEM8(0x08A7) +#define WEXC_PGV _SFR_MEM8(0x08A8) +#define WEXC_SWAPBUF _SFR_MEM8(0x08AA) +#define WEXC_PGOBUF _SFR_MEM8(0x08AB) +#define WEXC_PGVBUF _SFR_MEM8(0x08AC) +#define WEXC_OUTOVDIS _SFR_MEM8(0x08AF) + +/* HIRES - High-Resolution Extension */ +#define HIRESC_CTRLA _SFR_MEM8(0x08B0) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTC0_DATA _SFR_MEM8(0x08C0) +#define USARTC0_STATUS _SFR_MEM8(0x08C1) +#define USARTC0_CTRLA _SFR_MEM8(0x08C2) +#define USARTC0_CTRLB _SFR_MEM8(0x08C3) +#define USARTC0_CTRLC _SFR_MEM8(0x08C4) +#define USARTC0_CTRLD _SFR_MEM8(0x08C5) +#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08C6) +#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08C7) + +/* SPI - Serial Peripheral Interface with Buffer Modes */ +#define SPIC_CTRL _SFR_MEM8(0x08E0) +#define SPIC_INTCTRL _SFR_MEM8(0x08E1) +#define SPIC_STATUS _SFR_MEM8(0x08E2) +#define SPIC_DATA _SFR_MEM8(0x08E3) +#define SPIC_CTRLB _SFR_MEM8(0x08E4) + +/* IRCOM - IR Communication Module */ +#define IRCOM_CTRL _SFR_MEM8(0x08F8) +#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) +#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) + +/* TC5 - 16-bit Timer/Counter 5 */ +#define TCD5_CTRLA _SFR_MEM8(0x0940) +#define TCD5_CTRLB _SFR_MEM8(0x0941) +#define TCD5_CTRLC _SFR_MEM8(0x0942) +#define TCD5_CTRLD _SFR_MEM8(0x0943) +#define TCD5_CTRLE _SFR_MEM8(0x0944) +#define TCD5_CTRLF _SFR_MEM8(0x0945) +#define TCD5_INTCTRLA _SFR_MEM8(0x0946) +#define TCD5_INTCTRLB _SFR_MEM8(0x0947) +#define TCD5_CTRLGCLR _SFR_MEM8(0x0948) +#define TCD5_CTRLGSET _SFR_MEM8(0x0949) +#define TCD5_CTRLHCLR _SFR_MEM8(0x094A) +#define TCD5_CTRLHSET _SFR_MEM8(0x094B) +#define TCD5_INTFLAGS _SFR_MEM8(0x094C) +#define TCD5_TEMP _SFR_MEM8(0x094F) +#define TCD5_CNT _SFR_MEM16(0x0960) +#define TCD5_PER _SFR_MEM16(0x0966) +#define TCD5_CCA _SFR_MEM16(0x0968) +#define TCD5_CCB _SFR_MEM16(0x096A) +#define TCD5_PERBUF _SFR_MEM16(0x0976) +#define TCD5_CCABUF _SFR_MEM16(0x0978) +#define TCD5_CCBBUF _SFR_MEM16(0x097A) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTD0_DATA _SFR_MEM8(0x09C0) +#define USARTD0_STATUS _SFR_MEM8(0x09C1) +#define USARTD0_CTRLA _SFR_MEM8(0x09C2) +#define USARTD0_CTRLB _SFR_MEM8(0x09C3) +#define USARTD0_CTRLC _SFR_MEM8(0x09C4) +#define USARTD0_CTRLD _SFR_MEM8(0x09C5) +#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09C6) +#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09C7) + + + +/*================== Bitfield Definitions ================== */ + +/* VPORT - Virtual Ports */ +/* VPORT.INTFLAGS bit masks and bit positions */ +#define VPORT_INT7IF_bm 0x80 /* Interrupt Pin 7 Flag bit mask. */ +#define VPORT_INT7IF_bp 7 /* Interrupt Pin 7 Flag bit position. */ + +#define VPORT_INT6IF_bm 0x40 /* Interrupt Pin 6 Flag bit mask. */ +#define VPORT_INT6IF_bp 6 /* Interrupt Pin 6 Flag bit position. */ + +#define VPORT_INT5IF_bm 0x20 /* Interrupt Pin 5 Flag bit mask. */ +#define VPORT_INT5IF_bp 5 /* Interrupt Pin 5 Flag bit position. */ + +#define VPORT_INT4IF_bm 0x10 /* Interrupt Pin 4 Flag bit mask. */ +#define VPORT_INT4IF_bp 4 /* Interrupt Pin 4 Flag bit position. */ + +#define VPORT_INT3IF_bm 0x08 /* Interrupt Pin 3 Flag bit mask. */ +#define VPORT_INT3IF_bp 3 /* Interrupt Pin 3 Flag bit position. */ + +#define VPORT_INT2IF_bm 0x04 /* Interrupt Pin 2 Flag bit mask. */ +#define VPORT_INT2IF_bp 2 /* Interrupt Pin 2 Flag bit position. */ + +#define VPORT_INT1IF_bm 0x02 /* Interrupt Pin 1 Flag bit mask. */ +#define VPORT_INT1IF_bp 1 /* Interrupt Pin 1 Flag bit position. */ + +#define VPORT_INT0IF_bm 0x01 /* Interrupt Pin 0 Flag bit mask. */ +#define VPORT_INT0IF_bp 0 /* Interrupt Pin 0 Flag bit position. */ + +/* XOCD - On-Chip Debug System */ +/* OCD.OCDR0 bit masks and bit positions */ +#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ +#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ +#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ +#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ +#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ +#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ +#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ +#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ +#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ +#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ +#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ +#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ +#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ +#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ +#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ +#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ +#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ +#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ + +/* OCD.OCDR1 bit masks and bit positions */ +/* OCD_OCDRD Predefined. */ +/* OCD_OCDRD Predefined. */ + +/* CPU - CPU */ +/* CPU.CCP bit masks and bit positions */ +#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +#define CPU_CCP_gp 0 /* CCP signature group position. */ +#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ + +/* CPU.SREG bit masks and bit positions */ +#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ + +#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +#define CPU_T_bp 6 /* Transfer Bit bit position. */ + +#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +#define CPU_H_bp 5 /* Half Carry Flag bit position. */ + +#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ + +#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ + +#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +#define CPU_N_bp 2 /* Negative Flag bit position. */ + +#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +#define CPU_Z_bp 1 /* Zero Flag bit position. */ + +#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +#define CPU_C_bp 0 /* Carry Flag bit position. */ + +/* CLK - Clock System */ +/* CLK.CTRL bit masks and bit positions */ +#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ +#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ +#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ +#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ +#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ +#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ +#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ +#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ + +/* CLK.PSCTRL bit masks and bit positions */ +#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ +#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ +#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ +#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ +#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ +#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ +#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ +#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ +#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ +#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ +#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ +#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ + +#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ +#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ +#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ +#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ +#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ +#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ + +/* CLK.LOCK bit masks and bit positions */ +#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ +#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ + +/* CLK.RTCCTRL bit masks and bit positions */ +#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ +#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ +#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ +#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ +#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ +#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ +#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ +#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ + +#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ +#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ + +/* PR.PRGEN bit masks and bit positions */ +#define PR_XCL_bm 0x80 /* XMEGA Custom Logic bit mask. */ +#define PR_XCL_bp 7 /* XMEGA Custom Logic bit position. */ + +#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ +#define PR_RTC_bp 2 /* Real-time Counter bit position. */ + +#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ +#define PR_EVSYS_bp 1 /* Event System bit position. */ + +#define PR_EDMA_bm 0x01 /* Enhanced DMA-Controller bit mask. */ +#define PR_EDMA_bp 0 /* Enhanced DMA-Controller bit position. */ + +/* PR.PRPA bit masks and bit positions */ +#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ +#define PR_DAC_bp 2 /* Port A DAC bit position. */ + +#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ +#define PR_ADC_bp 1 /* Port A ADC bit position. */ + +#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ +#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ + +/* PR.PRPC bit masks and bit positions */ +#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ +#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ + +#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ +#define PR_USART0_bp 4 /* Port C USART0 bit position. */ + +#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ +#define PR_SPI_bp 3 /* Port C SPI bit position. */ + +#define PR_HIRES_bm 0x04 /* Port C WEX bit mask. */ +#define PR_HIRES_bp 2 /* Port C WEX bit position. */ + +#define PR_TC5_bm 0x02 /* Port C Timer/Counter5 bit mask. */ +#define PR_TC5_bp 1 /* Port C Timer/Counter5 bit position. */ + +#define PR_TC4_bm 0x01 /* Port C Timer/Counter4 bit mask. */ +#define PR_TC4_bp 0 /* Port C Timer/Counter4 bit position. */ + +/* PR.PRPD bit masks and bit positions */ +/* PR_USART0 Predefined. */ +/* PR_USART0 Predefined. */ + +/* PR_TC5 Predefined. */ +/* PR_TC5 Predefined. */ + +/* SLEEP - Sleep Controller */ +/* SLEEP.CTRL bit masks and bit positions */ +#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ +#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ +#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ +#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ +#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ +#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ +#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ +#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ + +#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ +#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ + +/* OSC - Oscillator */ +/* OSC.CTRL bit masks and bit positions */ +#define OSC_RC8MLPM_bm 0x40 /* Internal 8 MHz RC Low Power Mode Enable bit mask. */ +#define OSC_RC8MLPM_bp 6 /* Internal 8 MHz RC Low Power Mode Enable bit position. */ + +#define OSC_RC8MEN_bm 0x20 /* Internal 8 MHz RC Oscillator Enable bit mask. */ +#define OSC_RC8MEN_bp 5 /* Internal 8 MHz RC Oscillator Enable bit position. */ + +#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ +#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ + +#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ +#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ + +#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ +#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ + +#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ +#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ + +#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ +#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ + +/* OSC.STATUS bit masks and bit positions */ +#define OSC_RC8MRDY_bm 0x20 /* Internal 8 MHz RC Oscillator Ready bit mask. */ +#define OSC_RC8MRDY_bp 5 /* Internal 8 MHz RC Oscillator Ready bit position. */ + +#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ +#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ + +#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ +#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ + +#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ +#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ + +#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ +#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ + +#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ +#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ + +/* OSC.XOSCCTRL bit masks and bit positions */ +#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ +#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ +#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ +#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ +#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ +#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ + +#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ +#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ + +#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ +#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ + +#define OSC_XOSCSEL_gm 0x1F /* External Oscillator Selection and Startup Time group mask. */ +#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ +#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ +#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ +#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ +#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ +#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ +#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ +#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ +#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ +#define OSC_XOSCSEL4_bm (1<<4) /* External Oscillator Selection and Startup Time bit 4 mask. */ +#define OSC_XOSCSEL4_bp 4 /* External Oscillator Selection and Startup Time bit 4 position. */ + +/* OSC.XOSCFAIL bit masks and bit positions */ +#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ +#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ + +#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ +#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ + +#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ +#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ + +#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ +#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ + +/* OSC.PLLCTRL bit masks and bit positions */ +#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ +#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ +#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ +#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ +#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ +#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ + +#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ +#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ + +#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ +#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ +#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ +#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ +#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ +#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ +#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ +#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ +#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ +#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ +#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ +#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ + +/* OSC.DFLLCTRL bit masks and bit positions */ +#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ +#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ +#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ +#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ +#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ +#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ + +/* OSC.RC8MCAL bit masks and bit positions */ +#define OSC_RC8MCAL_gm 0xFF /* Calibration Bits group mask. */ +#define OSC_RC8MCAL_gp 0 /* Calibration Bits group position. */ +#define OSC_RC8MCAL0_bm (1<<0) /* Calibration Bits bit 0 mask. */ +#define OSC_RC8MCAL0_bp 0 /* Calibration Bits bit 0 position. */ +#define OSC_RC8MCAL1_bm (1<<1) /* Calibration Bits bit 1 mask. */ +#define OSC_RC8MCAL1_bp 1 /* Calibration Bits bit 1 position. */ +#define OSC_RC8MCAL2_bm (1<<2) /* Calibration Bits bit 2 mask. */ +#define OSC_RC8MCAL2_bp 2 /* Calibration Bits bit 2 position. */ +#define OSC_RC8MCAL3_bm (1<<3) /* Calibration Bits bit 3 mask. */ +#define OSC_RC8MCAL3_bp 3 /* Calibration Bits bit 3 position. */ +#define OSC_RC8MCAL4_bm (1<<4) /* Calibration Bits bit 4 mask. */ +#define OSC_RC8MCAL4_bp 4 /* Calibration Bits bit 4 position. */ +#define OSC_RC8MCAL5_bm (1<<5) /* Calibration Bits bit 5 mask. */ +#define OSC_RC8MCAL5_bp 5 /* Calibration Bits bit 5 position. */ +#define OSC_RC8MCAL6_bm (1<<6) /* Calibration Bits bit 6 mask. */ +#define OSC_RC8MCAL6_bp 6 /* Calibration Bits bit 6 position. */ +#define OSC_RC8MCAL7_bm (1<<7) /* Calibration Bits bit 7 mask. */ +#define OSC_RC8MCAL7_bp 7 /* Calibration Bits bit 7 position. */ + +/* DFLL - DFLL */ +/* DFLL.CTRL bit masks and bit positions */ +#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ +#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ + +/* DFLL.CALA bit masks and bit positions */ +#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ +#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ +#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ +#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ +#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ +#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ +#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ +#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ +#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ +#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ +#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ +#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ +#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ +#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ +#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ +#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ + +/* DFLL.CALB bit masks and bit positions */ +#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ +#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ +#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ +#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ +#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ +#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ +#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ +#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ +#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ +#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ +#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ +#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ +#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ +#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ + +/* RST - Reset */ +/* RST.STATUS bit masks and bit positions */ +#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ +#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ + +#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ +#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ + +#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ +#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ + +#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ +#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ + +#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ +#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ + +#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ +#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ + +#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ +#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ + +/* RST.CTRL bit masks and bit positions */ +#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ +#define RST_SWRST_bp 0 /* Software Reset bit position. */ + +/* WDT - Watch-Dog Timer */ +/* WDT.CTRL bit masks and bit positions */ +#define WDT_PER_gm 0x3C /* Period group mask. */ +#define WDT_PER_gp 2 /* Period group position. */ +#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ +#define WDT_PER0_bp 2 /* Period bit 0 position. */ +#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ +#define WDT_PER1_bp 3 /* Period bit 1 position. */ +#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ +#define WDT_PER2_bp 4 /* Period bit 2 position. */ +#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ +#define WDT_PER3_bp 5 /* Period bit 3 position. */ + +#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ +#define WDT_ENABLE_bp 1 /* Enable bit position. */ + +#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ +#define WDT_CEN_bp 0 /* Change Enable bit position. */ + +/* WDT.WINCTRL bit masks and bit positions */ +#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ +#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ +#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ +#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ +#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ +#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ +#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ +#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ +#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ +#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ + +#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ +#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ + +#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ +#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ + +/* WDT.STATUS bit masks and bit positions */ +#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ + +/* MCU - MCU Control */ +/* MCU.ANAINIT bit masks and bit positions */ +#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ +#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ +#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ +#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ +#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ +#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ + +/* MCU.EVSYSLOCK bit masks and bit positions */ +#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ +#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ + +#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ +#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ + +/* MCU.WEXLOCK bit masks and bit positions */ +#define MCU_WEXCLOCK_bm 0x01 /* WeX on T/C C4 Lock bit mask. */ +#define MCU_WEXCLOCK_bp 0 /* WeX on T/C C4 Lock bit position. */ + +/* MCU.FAULTLOCK bit masks and bit positions */ +#define MCU_FAULTC5LOCK_bm 0x02 /* Fault on T/C C5 Lock bit mask. */ +#define MCU_FAULTC5LOCK_bp 1 /* Fault on T/C C5 Lock bit position. */ + +#define MCU_FAULTC4LOCK_bm 0x01 /* Fault on T/C C4 Lock bit mask. */ +#define MCU_FAULTC4LOCK_bp 0 /* Fault on T/C C4 Lock bit position. */ + +/* PMIC - Programmable Multi-level Interrupt Controller */ +/* PMIC.STATUS bit masks and bit positions */ +#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ + +#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ +#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ + +#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ +#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ + +#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ +#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ + +/* PMIC.INTPRI bit masks and bit positions */ +#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ +#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ +#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ +#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ +#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ +#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ +#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ +#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ +#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ +#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ +#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ +#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ +#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ +#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ +#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ +#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ +#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ +#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ + +/* PMIC.CTRL bit masks and bit positions */ +#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ +#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ + +#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ + +#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ +#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ + +#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ +#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ + +#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ +#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ + +/* PORTCFG - Port Configuration */ +/* PORTCFG.CLKOUT bit masks and bit positions */ +#define PORTCFG_CLKEVPIN_bm 0x80 /* Clock and Event Output Pin Select bit mask. */ +#define PORTCFG_CLKEVPIN_bp 7 /* Clock and Event Output Pin Select bit position. */ + +#define PORTCFG_RTCOUT_gm 0x60 /* RTC Clock Output Enable group mask. */ +#define PORTCFG_RTCOUT_gp 5 /* RTC Clock Output Enable group position. */ +#define PORTCFG_RTCOUT0_bm (1<<5) /* RTC Clock Output Enable bit 0 mask. */ +#define PORTCFG_RTCOUT0_bp 5 /* RTC Clock Output Enable bit 0 position. */ +#define PORTCFG_RTCOUT1_bm (1<<6) /* RTC Clock Output Enable bit 1 mask. */ +#define PORTCFG_RTCOUT1_bp 6 /* RTC Clock Output Enable bit 1 position. */ + +#define PORTCFG_CLKOUTSEL_gm 0x0C /* Clock Output Select group mask. */ +#define PORTCFG_CLKOUTSEL_gp 2 /* Clock Output Select group position. */ +#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Clock Output Select bit 0 mask. */ +#define PORTCFG_CLKOUTSEL0_bp 2 /* Clock Output Select bit 0 position. */ +#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Clock Output Select bit 1 mask. */ +#define PORTCFG_CLKOUTSEL1_bp 3 /* Clock Output Select bit 1 position. */ + +#define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */ +#define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */ +#define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */ +#define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */ +#define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */ +#define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */ + +/* PORTCFG.ACEVOUT bit masks and bit positions */ +#define PORTCFG_ACOUT_gm 0xC0 /* Analog Comparator Output Port group mask. */ +#define PORTCFG_ACOUT_gp 6 /* Analog Comparator Output Port group position. */ +#define PORTCFG_ACOUT0_bm (1<<6) /* Analog Comparator Output Port bit 0 mask. */ +#define PORTCFG_ACOUT0_bp 6 /* Analog Comparator Output Port bit 0 position. */ +#define PORTCFG_ACOUT1_bm (1<<7) /* Analog Comparator Output Port bit 1 mask. */ +#define PORTCFG_ACOUT1_bp 7 /* Analog Comparator Output Port bit 1 position. */ + +#define PORTCFG_EVOUT_gm 0x30 /* Event Channel Output Port group mask. */ +#define PORTCFG_EVOUT_gp 4 /* Event Channel Output Port group position. */ +#define PORTCFG_EVOUT0_bm (1<<4) /* Event Channel Output Port bit 0 mask. */ +#define PORTCFG_EVOUT0_bp 4 /* Event Channel Output Port bit 0 position. */ +#define PORTCFG_EVOUT1_bm (1<<5) /* Event Channel Output Port bit 1 mask. */ +#define PORTCFG_EVOUT1_bp 5 /* Event Channel Output Port bit 1 position. */ + +#define PORTCFG_EVASYEN_bm 0x08 /* Asynchronous Event Enabled bit mask. */ +#define PORTCFG_EVASYEN_bp 3 /* Asynchronous Event Enabled bit position. */ + +#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Channel Output Selection group mask. */ +#define PORTCFG_EVOUTSEL_gp 0 /* Event Channel Output Selection group position. */ +#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Channel Output Selection bit 0 mask. */ +#define PORTCFG_EVOUTSEL0_bp 0 /* Event Channel Output Selection bit 0 position. */ +#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Channel Output Selection bit 1 mask. */ +#define PORTCFG_EVOUTSEL1_bp 1 /* Event Channel Output Selection bit 1 position. */ +#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Channel Output Selection bit 2 mask. */ +#define PORTCFG_EVOUTSEL2_bp 2 /* Event Channel Output Selection bit 2 position. */ + +/* PORTCFG.SRLCTRL bit masks and bit positions */ +#define PORTCFG_SRLENRA_bm 0x01 /* Slew Rate Limit Enable on PORTA bit mask. */ +#define PORTCFG_SRLENRA_bp 0 /* Slew Rate Limit Enable on PORTA bit position. */ + +#define PORTCFG_SRLENRC_bm 0x04 /* Slew Rate Limit Enable on PORTC bit mask. */ +#define PORTCFG_SRLENRC_bp 2 /* Slew Rate Limit Enable on PORTC bit position. */ + +#define PORTCFG_SRLENRD_bm 0x08 /* Slew Rate Limit Enable on PORTD bit mask. */ +#define PORTCFG_SRLENRD_bp 3 /* Slew Rate Limit Enable on PORTD bit position. */ + +#define PORTCFG_SRLENRR_bm 0x80 /* Slew Rate Limit Enable on PORTR bit mask. */ +#define PORTCFG_SRLENRR_bp 7 /* Slew Rate Limit Enable on PORTR bit position. */ + +/* CRC - Cyclic Redundancy Checker */ +/* CRC.CTRL bit masks and bit positions */ +#define CRC_RESET_gm 0xC0 /* Reset group mask. */ +#define CRC_RESET_gp 6 /* Reset group position. */ +#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ +#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ +#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ +#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ + +#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ +#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ + +#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ +#define CRC_SOURCE_gp 0 /* Input Source group position. */ +#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ +#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ +#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ +#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ +#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ +#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ +#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ +#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ + +/* CRC.STATUS bit masks and bit positions */ +#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ +#define CRC_ZERO_bp 1 /* Zero detection bit position. */ + +#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ +#define CRC_BUSY_bp 0 /* Busy bit position. */ + +/* EDMA - Enhanced DMA Controller */ +/* EDMA.CTRL bit masks and bit positions */ +#define EDMA_ENABLE_bm 0x80 /* Enable bit mask. */ +#define EDMA_ENABLE_bp 7 /* Enable bit position. */ + +#define EDMA_RESET_bm 0x40 /* Software Reset bit mask. */ +#define EDMA_RESET_bp 6 /* Software Reset bit position. */ + +#define EDMA_CHMODE_gm 0x30 /* Channel Mode group mask. */ +#define EDMA_CHMODE_gp 4 /* Channel Mode group position. */ +#define EDMA_CHMODE0_bm (1<<4) /* Channel Mode bit 0 mask. */ +#define EDMA_CHMODE0_bp 4 /* Channel Mode bit 0 position. */ +#define EDMA_CHMODE1_bm (1<<5) /* Channel Mode bit 1 mask. */ +#define EDMA_CHMODE1_bp 5 /* Channel Mode bit 1 position. */ + +#define EDMA_DBUFMODE_gm 0x0C /* Double Buffer Mode group mask. */ +#define EDMA_DBUFMODE_gp 2 /* Double Buffer Mode group position. */ +#define EDMA_DBUFMODE0_bm (1<<2) /* Double Buffer Mode bit 0 mask. */ +#define EDMA_DBUFMODE0_bp 2 /* Double Buffer Mode bit 0 position. */ +#define EDMA_DBUFMODE1_bm (1<<3) /* Double Buffer Mode bit 1 mask. */ +#define EDMA_DBUFMODE1_bp 3 /* Double Buffer Mode bit 1 position. */ + +#define EDMA_PRIMODE_gm 0x03 /* Priority Mode group mask. */ +#define EDMA_PRIMODE_gp 0 /* Priority Mode group position. */ +#define EDMA_PRIMODE0_bm (1<<0) /* Priority Mode bit 0 mask. */ +#define EDMA_PRIMODE0_bp 0 /* Priority Mode bit 0 position. */ +#define EDMA_PRIMODE1_bm (1<<1) /* Priority Mode bit 1 mask. */ +#define EDMA_PRIMODE1_bp 1 /* Priority Mode bit 1 position. */ + +/* EDMA.INTFLAGS bit masks and bit positions */ +#define EDMA_CH3ERRIF_bm 0x80 /* Channel 3 Transaction Error Interrupt Flag bit mask. */ +#define EDMA_CH3ERRIF_bp 7 /* Channel 3 Transaction Error Interrupt Flag bit position. */ + +#define EDMA_CH2ERRIF_bm 0x40 /* Channel 2 Transaction Error Interrupt Flag bit mask. */ +#define EDMA_CH2ERRIF_bp 6 /* Channel 2 Transaction Error Interrupt Flag bit position. */ + +#define EDMA_CH1ERRIF_bm 0x20 /* Channel 1 Transaction Error Interrupt Flag bit mask. */ +#define EDMA_CH1ERRIF_bp 5 /* Channel 1 Transaction Error Interrupt Flag bit position. */ + +#define EDMA_CH0ERRIF_bm 0x10 /* Channel 0 Transaction Error Interrupt Flag bit mask. */ +#define EDMA_CH0ERRIF_bp 4 /* Channel 0 Transaction Error Interrupt Flag bit position. */ + +#define EDMA_CH3TRNFIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ +#define EDMA_CH3TRNFIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ + +#define EDMA_CH2TRNFIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ +#define EDMA_CH2TRNFIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ + +#define EDMA_CH1TRNFIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ +#define EDMA_CH1TRNFIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ + +#define EDMA_CH0TRNFIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ +#define EDMA_CH0TRNFIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ + +/* EDMA.STATUS bit masks and bit positions */ +#define EDMA_CH3BUSY_bm 0x80 /* Channel 3 Busy Flag bit mask. */ +#define EDMA_CH3BUSY_bp 7 /* Channel 3 Busy Flag bit position. */ + +#define EDMA_CH2BUSY_bm 0x40 /* Channel 2 Busy Flag bit mask. */ +#define EDMA_CH2BUSY_bp 6 /* Channel 2 Busy Flag bit position. */ + +#define EDMA_CH1BUSY_bm 0x20 /* Channel 1 Busy Flag bit mask. */ +#define EDMA_CH1BUSY_bp 5 /* Channel 1 Busy Flag bit position. */ + +#define EDMA_CH0BUSY_bm 0x10 /* Channel 0 Busy Flag bit mask. */ +#define EDMA_CH0BUSY_bp 4 /* Channel 0 Busy Flag bit position. */ + +#define EDMA_CH3PEND_bm 0x08 /* Channel 3 Pending Flag bit mask. */ +#define EDMA_CH3PEND_bp 3 /* Channel 3 Pending Flag bit position. */ + +#define EDMA_CH2PEND_bm 0x04 /* Channel 2 Pending Flag bit mask. */ +#define EDMA_CH2PEND_bp 2 /* Channel 2 Pending Flag bit position. */ + +#define EDMA_CH1PEND_bm 0x02 /* Channel 1 Pending Flag bit mask. */ +#define EDMA_CH1PEND_bp 1 /* Channel 1 Pending Flag bit position. */ + +#define EDMA_CH0PEND_bm 0x01 /* Channel 0 Pending Flag bit mask. */ +#define EDMA_CH0PEND_bp 0 /* Channel 0 Pending Flag bit position. */ + +/* EDMA_CH.CTRLA bit masks and bit positions */ +#define EDMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ +#define EDMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ + +#define EDMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ +#define EDMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ + +#define EDMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ +#define EDMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ + +#define EDMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ +#define EDMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ + +#define EDMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ +#define EDMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ + +#define EDMA_CH_BURSTLEN_bm 0x01 /* Channel 2-bytes Burst Length bit mask. */ +#define EDMA_CH_BURSTLEN_bp 0 /* Channel 2-bytes Burst Length bit position. */ + +/* EDMA_CH.CTRLB bit masks and bit positions */ +#define EDMA_CH_CHBUSY_bm 0x80 /* Channel Block Transfer Busy bit mask. */ +#define EDMA_CH_CHBUSY_bp 7 /* Channel Block Transfer Busy bit position. */ + +#define EDMA_CH_CHPEND_bm 0x40 /* Channel Block Transfer Pending bit mask. */ +#define EDMA_CH_CHPEND_bp 6 /* Channel Block Transfer Pending bit position. */ + +#define EDMA_CH_ERRIF_bm 0x20 /* Channel Transaction Error Interrupt Flag bit mask. */ +#define EDMA_CH_ERRIF_bp 5 /* Channel Transaction Error Interrupt Flag bit position. */ + +#define EDMA_CH_TRNIF_bm 0x10 /* Channel Transaction Complete Interrup Flag bit mask. */ +#define EDMA_CH_TRNIF_bp 4 /* Channel Transaction Complete Interrup Flag bit position. */ + +#define EDMA_CH_ERRINTLVL_gm 0x0C /* Channel Transaction Error Interrupt Level group mask. */ +#define EDMA_CH_ERRINTLVL_gp 2 /* Channel Transaction Error Interrupt Level group position. */ +#define EDMA_CH_ERRINTLVL0_bm (1<<2) /* Channel Transaction Error Interrupt Level bit 0 mask. */ +#define EDMA_CH_ERRINTLVL0_bp 2 /* Channel Transaction Error Interrupt Level bit 0 position. */ +#define EDMA_CH_ERRINTLVL1_bm (1<<3) /* Channel Transaction Error Interrupt Level bit 1 mask. */ +#define EDMA_CH_ERRINTLVL1_bp 3 /* Channel Transaction Error Interrupt Level bit 1 position. */ + +#define EDMA_CH_TRNINTLVL_gm 0x03 /* Channel Transaction Complete Interrupt Level group mask. */ +#define EDMA_CH_TRNINTLVL_gp 0 /* Channel Transaction Complete Interrupt Level group position. */ +#define EDMA_CH_TRNINTLVL0_bm (1<<0) /* Channel Transaction Complete Interrupt Level bit 0 mask. */ +#define EDMA_CH_TRNINTLVL0_bp 0 /* Channel Transaction Complete Interrupt Level bit 0 position. */ +#define EDMA_CH_TRNINTLVL1_bm (1<<1) /* Channel Transaction Complete Interrupt Level bit 1 mask. */ +#define EDMA_CH_TRNINTLVL1_bp 1 /* Channel Transaction Complete Interrupt Level bit 1 position. */ + +/* EDMA_CH.ADDRCTRL bit masks and bit positions */ +#define EDMA_CH_RELOAD_gm 0x30 /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. group mask. */ +#define EDMA_CH_RELOAD_gp 4 /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. group position. */ +#define EDMA_CH_RELOAD0_bm (1<<4) /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. bit 0 mask. */ +#define EDMA_CH_RELOAD0_bp 4 /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. bit 0 position. */ +#define EDMA_CH_RELOAD1_bm (1<<5) /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. bit 1 mask. */ +#define EDMA_CH_RELOAD1_bp 5 /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. bit 1 position. */ + +#define EDMA_CH_DIR_gm 0x07 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. group mask. */ +#define EDMA_CH_DIR_gp 0 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. group position. */ +#define EDMA_CH_DIR0_bm (1<<0) /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 0 mask. */ +#define EDMA_CH_DIR0_bp 0 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 0 position. */ +#define EDMA_CH_DIR1_bm (1<<1) /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 1 mask. */ +#define EDMA_CH_DIR1_bp 1 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 1 position. */ +#define EDMA_CH_DIR2_bm (1<<2) /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 2 mask. */ +#define EDMA_CH_DIR2_bp 2 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 2 position. */ + +/* EDMA_CH.DESTADDRCTRL bit masks and bit positions */ +#define EDMA_CH_DESTRELOAD_gm 0x30 /* Destination Address Reload for Standard Channels Only. group mask. */ +#define EDMA_CH_DESTRELOAD_gp 4 /* Destination Address Reload for Standard Channels Only. group position. */ +#define EDMA_CH_DESTRELOAD0_bm (1<<4) /* Destination Address Reload for Standard Channels Only. bit 0 mask. */ +#define EDMA_CH_DESTRELOAD0_bp 4 /* Destination Address Reload for Standard Channels Only. bit 0 position. */ +#define EDMA_CH_DESTRELOAD1_bm (1<<5) /* Destination Address Reload for Standard Channels Only. bit 1 mask. */ +#define EDMA_CH_DESTRELOAD1_bp 5 /* Destination Address Reload for Standard Channels Only. bit 1 position. */ + +#define EDMA_CH_DESTDIR_gm 0x07 /* Destination Address Mode for Standard Channels Only. group mask. */ +#define EDMA_CH_DESTDIR_gp 0 /* Destination Address Mode for Standard Channels Only. group position. */ +#define EDMA_CH_DESTDIR0_bm (1<<0) /* Destination Address Mode for Standard Channels Only. bit 0 mask. */ +#define EDMA_CH_DESTDIR0_bp 0 /* Destination Address Mode for Standard Channels Only. bit 0 position. */ +#define EDMA_CH_DESTDIR1_bm (1<<1) /* Destination Address Mode for Standard Channels Only. bit 1 mask. */ +#define EDMA_CH_DESTDIR1_bp 1 /* Destination Address Mode for Standard Channels Only. bit 1 position. */ +#define EDMA_CH_DESTDIR2_bm (1<<2) /* Destination Address Mode for Standard Channels Only. bit 2 mask. */ +#define EDMA_CH_DESTDIR2_bp 2 /* Destination Address Mode for Standard Channels Only. bit 2 position. */ + +/* EDMA_CH.TRIGSRC bit masks and bit positions */ +#define EDMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ +#define EDMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ +#define EDMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ +#define EDMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ +#define EDMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ +#define EDMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ +#define EDMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ +#define EDMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ +#define EDMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ +#define EDMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ +#define EDMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ +#define EDMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ +#define EDMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ +#define EDMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ +#define EDMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ +#define EDMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ +#define EDMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ +#define EDMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ + +/* EVSYS - Event System */ +/* EVSYS.CH0MUX bit masks and bit positions */ +#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ +#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ +#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ +#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ +#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ +#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ +#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ +#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ +#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ +#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ +#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ +#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ +#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ +#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ +#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ +#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ +#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ +#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ + +/* EVSYS.CH1MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH2MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH3MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH4MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH5MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH6MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH7MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH0CTRL bit masks and bit positions */ +#define EVSYS_ROTARY_bm 0x80 /* Rotary Decoder Enable bit mask. */ +#define EVSYS_ROTARY_bp 7 /* Rotary Decoder Enable bit position. */ + +#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ +#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ +#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ +#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ +#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ +#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ + +#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ +#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ + +#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ +#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ + +#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ +#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ +#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ +#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ +#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ +#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ +#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ +#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ + +/* EVSYS.CH1CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH2CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH3CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH4CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH5CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH6CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH7CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.DFCTRL bit masks and bit positions */ +#define EVSYS_PRESCFILT_gm 0xF0 /* Prescaler Filter group mask. */ +#define EVSYS_PRESCFILT_gp 4 /* Prescaler Filter group position. */ +#define EVSYS_PRESCFILT0_bm (1<<4) /* Prescaler Filter bit 0 mask. */ +#define EVSYS_PRESCFILT0_bp 4 /* Prescaler Filter bit 0 position. */ +#define EVSYS_PRESCFILT1_bm (1<<5) /* Prescaler Filter bit 1 mask. */ +#define EVSYS_PRESCFILT1_bp 5 /* Prescaler Filter bit 1 position. */ +#define EVSYS_PRESCFILT2_bm (1<<6) /* Prescaler Filter bit 2 mask. */ +#define EVSYS_PRESCFILT2_bp 6 /* Prescaler Filter bit 2 position. */ +#define EVSYS_PRESCFILT3_bm (1<<7) /* Prescaler Filter bit 3 mask. */ +#define EVSYS_PRESCFILT3_bp 7 /* Prescaler Filter bit 3 position. */ + +#define EVSYS_FILTSEL_bm 0x08 /* Prescaler Filter Select bit mask. */ +#define EVSYS_FILTSEL_bp 3 /* Prescaler Filter Select bit position. */ + +#define EVSYS_PRESC_gm 0x07 /* Prescaler group mask. */ +#define EVSYS_PRESC_gp 0 /* Prescaler group position. */ +#define EVSYS_PRESC0_bm (1<<0) /* Prescaler bit 0 mask. */ +#define EVSYS_PRESC0_bp 0 /* Prescaler bit 0 position. */ +#define EVSYS_PRESC1_bm (1<<1) /* Prescaler bit 1 mask. */ +#define EVSYS_PRESC1_bp 1 /* Prescaler bit 1 position. */ +#define EVSYS_PRESC2_bm (1<<2) /* Prescaler bit 2 mask. */ +#define EVSYS_PRESC2_bp 2 /* Prescaler bit 2 position. */ + +/* NVM - Non Volatile Memory Controller */ +/* NVM.CMD bit masks and bit positions */ +#define NVM_CMD_gm 0x7F /* Command group mask. */ +#define NVM_CMD_gp 0 /* Command group position. */ +#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define NVM_CMD0_bp 0 /* Command bit 0 position. */ +#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define NVM_CMD1_bp 1 /* Command bit 1 position. */ +#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ +#define NVM_CMD2_bp 2 /* Command bit 2 position. */ +#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ +#define NVM_CMD3_bp 3 /* Command bit 3 position. */ +#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ +#define NVM_CMD4_bp 4 /* Command bit 4 position. */ +#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ +#define NVM_CMD5_bp 5 /* Command bit 5 position. */ +#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ +#define NVM_CMD6_bp 6 /* Command bit 6 position. */ + +/* NVM.CTRLA bit masks and bit positions */ +#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ +#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ + +/* NVM.CTRLB bit masks and bit positions */ +#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ +#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ + +#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ +#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ + +/* NVM.INTCTRL bit masks and bit positions */ +#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ +#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ +#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ +#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ +#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ +#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ + +#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ +#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ +#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ +#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ +#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ +#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ + +/* NVM.STATUS bit masks and bit positions */ +#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ +#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ + +#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ +#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ + +#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ +#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ + +#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ +#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ + +/* NVM.LOCKBITS bit masks and bit positions */ +#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ + +#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ + +#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ + +#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ +#define NVM_LB_gp 0 /* Lock Bits group position. */ +#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ + +/* ADC - Analog/Digital Converter */ +/* ADC_CH.CTRL bit masks and bit positions */ +#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ +#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ + +#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ +#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ +#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ +#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ +#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ +#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ +#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ +#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ + +#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ +#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ +#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ +#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ +#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ +#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ + +/* ADC_CH.MUXCTRL bit masks and bit positions */ +#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC Input group mask. */ +#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC Input group position. */ +#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC Input bit 0 mask. */ +#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC Input bit 0 position. */ +#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC Input bit 1 mask. */ +#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC Input bit 1 position. */ +#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC Input bit 2 mask. */ +#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC Input bit 2 position. */ +#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC Input bit 3 mask. */ +#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC Input bit 3 position. */ + +#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC Input group mask. */ +#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC Input group position. */ +#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC Input bit 0 mask. */ +#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC Input bit 0 position. */ +#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC Input bit 1 mask. */ +#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC Input bit 1 position. */ +#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC Input bit 2 mask. */ +#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC Input bit 2 position. */ +#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC Input bit 3 mask. */ +#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC Input bit 3 position. */ + +#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC Input group mask. */ +#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC Input group position. */ +#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC Input bit 0 mask. */ +#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC Input bit 0 position. */ +#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC Input bit 1 mask. */ +#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC Input bit 1 position. */ + +#define ADC_CH_MUXNEGL_gm 0x03 /* MUX selection on Negative ADC Input Gain on 4 LSB pins group mask. */ +#define ADC_CH_MUXNEGL_gp 0 /* MUX selection on Negative ADC Input Gain on 4 LSB pins group position. */ +#define ADC_CH_MUXNEGL0_bm (1<<0) /* MUX selection on Negative ADC Input Gain on 4 LSB pins bit 0 mask. */ +#define ADC_CH_MUXNEGL0_bp 0 /* MUX selection on Negative ADC Input Gain on 4 LSB pins bit 0 position. */ +#define ADC_CH_MUXNEGL1_bm (1<<1) /* MUX selection on Negative ADC Input Gain on 4 LSB pins bit 1 mask. */ +#define ADC_CH_MUXNEGL1_bp 1 /* MUX selection on Negative ADC Input Gain on 4 LSB pins bit 1 position. */ + +#define ADC_CH_MUXNEGH_gm 0x03 /* MUX selection on Negative ADC Input Gain on 4 MSB pins group mask. */ +#define ADC_CH_MUXNEGH_gp 0 /* MUX selection on Negative ADC Input Gain on 4 MSB pins group position. */ +#define ADC_CH_MUXNEGH0_bm (1<<0) /* MUX selection on Negative ADC Input Gain on 4 MSB pins bit 0 mask. */ +#define ADC_CH_MUXNEGH0_bp 0 /* MUX selection on Negative ADC Input Gain on 4 MSB pins bit 0 position. */ +#define ADC_CH_MUXNEGH1_bm (1<<1) /* MUX selection on Negative ADC Input Gain on 4 MSB pins bit 1 mask. */ +#define ADC_CH_MUXNEGH1_bp 1 /* MUX selection on Negative ADC Input Gain on 4 MSB pins bit 1 position. */ + +/* ADC_CH.INTCTRL bit masks and bit positions */ +#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ +#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ +#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ +#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ +#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ +#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ + +#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ +#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ +#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ +#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ +#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ +#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ + +/* ADC_CH.INTFLAGS bit masks and bit positions */ +#define ADC_CH_IF_bm 0x01 /* Channel Interrupt Flag bit mask. */ +#define ADC_CH_IF_bp 0 /* Channel Interrupt Flag bit position. */ + +/* ADC_CH.SCAN bit masks and bit positions */ +#define ADC_CH_INPUTOFFSET_gm 0xF0 /* Positive MUX Setting Offset group mask. */ +#define ADC_CH_INPUTOFFSET_gp 4 /* Positive MUX Setting Offset group position. */ +#define ADC_CH_INPUTOFFSET0_bm (1<<4) /* Positive MUX Setting Offset bit 0 mask. */ +#define ADC_CH_INPUTOFFSET0_bp 4 /* Positive MUX Setting Offset bit 0 position. */ +#define ADC_CH_INPUTOFFSET1_bm (1<<5) /* Positive MUX Setting Offset bit 1 mask. */ +#define ADC_CH_INPUTOFFSET1_bp 5 /* Positive MUX Setting Offset bit 1 position. */ +#define ADC_CH_INPUTOFFSET2_bm (1<<6) /* Positive MUX Setting Offset bit 2 mask. */ +#define ADC_CH_INPUTOFFSET2_bp 6 /* Positive MUX Setting Offset bit 2 position. */ +#define ADC_CH_INPUTOFFSET3_bm (1<<7) /* Positive MUX Setting Offset bit 3 mask. */ +#define ADC_CH_INPUTOFFSET3_bp 7 /* Positive MUX Setting Offset bit 3 position. */ + +#define ADC_CH_INPUTSCAN_gm 0x0F /* Number of Channels Included in Scan group mask. */ +#define ADC_CH_INPUTSCAN_gp 0 /* Number of Channels Included in Scan group position. */ +#define ADC_CH_INPUTSCAN0_bm (1<<0) /* Number of Channels Included in Scan bit 0 mask. */ +#define ADC_CH_INPUTSCAN0_bp 0 /* Number of Channels Included in Scan bit 0 position. */ +#define ADC_CH_INPUTSCAN1_bm (1<<1) /* Number of Channels Included in Scan bit 1 mask. */ +#define ADC_CH_INPUTSCAN1_bp 1 /* Number of Channels Included in Scan bit 1 position. */ +#define ADC_CH_INPUTSCAN2_bm (1<<2) /* Number of Channels Included in Scan bit 2 mask. */ +#define ADC_CH_INPUTSCAN2_bp 2 /* Number of Channels Included in Scan bit 2 position. */ +#define ADC_CH_INPUTSCAN3_bm (1<<3) /* Number of Channels Included in Scan bit 3 mask. */ +#define ADC_CH_INPUTSCAN3_bp 3 /* Number of Channels Included in Scan bit 3 position. */ + +/* ADC_CH.CORRCTRL bit masks and bit positions */ +#define ADC_CH_CORREN_bm 0x01 /* Correction Enable bit mask. */ +#define ADC_CH_CORREN_bp 0 /* Correction Enable bit position. */ + +/* ADC_CH.OFFSETCORR1 bit masks and bit positions */ +#define ADC_CH_OFFSETCORR_gm 0x0F /* Offset Correction Byte 1 group mask. */ +#define ADC_CH_OFFSETCORR_gp 0 /* Offset Correction Byte 1 group position. */ +#define ADC_CH_OFFSETCORR0_bm (1<<0) /* Offset Correction Byte 1 bit 0 mask. */ +#define ADC_CH_OFFSETCORR0_bp 0 /* Offset Correction Byte 1 bit 0 position. */ +#define ADC_CH_OFFSETCORR1_bm (1<<1) /* Offset Correction Byte 1 bit 1 mask. */ +#define ADC_CH_OFFSETCORR1_bp 1 /* Offset Correction Byte 1 bit 1 position. */ +#define ADC_CH_OFFSETCORR2_bm (1<<2) /* Offset Correction Byte 1 bit 2 mask. */ +#define ADC_CH_OFFSETCORR2_bp 2 /* Offset Correction Byte 1 bit 2 position. */ +#define ADC_CH_OFFSETCORR3_bm (1<<3) /* Offset Correction Byte 1 bit 3 mask. */ +#define ADC_CH_OFFSETCORR3_bp 3 /* Offset Correction Byte 1 bit 3 position. */ + +/* ADC_CH.GAINCORR1 bit masks and bit positions */ +#define ADC_CH_GAINCORR_gm 0x0F /* Gain Correction Byte 1 group mask. */ +#define ADC_CH_GAINCORR_gp 0 /* Gain Correction Byte 1 group position. */ +#define ADC_CH_GAINCORR0_bm (1<<0) /* Gain Correction Byte 1 bit 0 mask. */ +#define ADC_CH_GAINCORR0_bp 0 /* Gain Correction Byte 1 bit 0 position. */ +#define ADC_CH_GAINCORR1_bm (1<<1) /* Gain Correction Byte 1 bit 1 mask. */ +#define ADC_CH_GAINCORR1_bp 1 /* Gain Correction Byte 1 bit 1 position. */ +#define ADC_CH_GAINCORR2_bm (1<<2) /* Gain Correction Byte 1 bit 2 mask. */ +#define ADC_CH_GAINCORR2_bp 2 /* Gain Correction Byte 1 bit 2 position. */ +#define ADC_CH_GAINCORR3_bm (1<<3) /* Gain Correction Byte 1 bit 3 mask. */ +#define ADC_CH_GAINCORR3_bp 3 /* Gain Correction Byte 1 bit 3 position. */ + +/* ADC_CH.AVGCTRL bit masks and bit positions */ +#define ADC_CH_RIGHTSHIFT_gm 0x70 /* Right Shift group mask. */ +#define ADC_CH_RIGHTSHIFT_gp 4 /* Right Shift group position. */ +#define ADC_CH_RIGHTSHIFT0_bm (1<<4) /* Right Shift bit 0 mask. */ +#define ADC_CH_RIGHTSHIFT0_bp 4 /* Right Shift bit 0 position. */ +#define ADC_CH_RIGHTSHIFT1_bm (1<<5) /* Right Shift bit 1 mask. */ +#define ADC_CH_RIGHTSHIFT1_bp 5 /* Right Shift bit 1 position. */ +#define ADC_CH_RIGHTSHIFT2_bm (1<<6) /* Right Shift bit 2 mask. */ +#define ADC_CH_RIGHTSHIFT2_bp 6 /* Right Shift bit 2 position. */ + +#define ADC_CH_SAMPNUM_gm 0x0F /* Averaged Number of Samples group mask. */ +#define ADC_CH_SAMPNUM_gp 0 /* Averaged Number of Samples group position. */ +#define ADC_CH_SAMPNUM0_bm (1<<0) /* Averaged Number of Samples bit 0 mask. */ +#define ADC_CH_SAMPNUM0_bp 0 /* Averaged Number of Samples bit 0 position. */ +#define ADC_CH_SAMPNUM1_bm (1<<1) /* Averaged Number of Samples bit 1 mask. */ +#define ADC_CH_SAMPNUM1_bp 1 /* Averaged Number of Samples bit 1 position. */ +#define ADC_CH_SAMPNUM2_bm (1<<2) /* Averaged Number of Samples bit 2 mask. */ +#define ADC_CH_SAMPNUM2_bp 2 /* Averaged Number of Samples bit 2 position. */ +#define ADC_CH_SAMPNUM3_bm (1<<3) /* Averaged Number of Samples bit 3 mask. */ +#define ADC_CH_SAMPNUM3_bp 3 /* Averaged Number of Samples bit 3 position. */ + +/* ADC.CTRLA bit masks and bit positions */ +#define ADC_START_bm 0x04 /* Start Conversion bit mask. */ +#define ADC_START_bp 2 /* Start Conversion bit position. */ + +#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ +#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ + +#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ +#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ + +/* ADC.CTRLB bit masks and bit positions */ +#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ +#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ +#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ +#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ +#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ +#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ + +#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ +#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ + +#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ +#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ + +#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ +#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ +#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ +#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ +#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ +#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ + +/* ADC.REFCTRL bit masks and bit positions */ +#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ +#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ +#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ +#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ + +#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ +#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ + +#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ +#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ + +/* ADC.EVCTRL bit masks and bit positions */ +#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ +#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ +#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ +#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ +#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ +#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ +#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ +#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ + +#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ +#define ADC_EVACT_gp 0 /* Event Action Select group position. */ +#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ +#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ +#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ +#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ +#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ +#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ + +/* ADC.PRESCALER bit masks and bit positions */ +#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ +#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ +#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ +#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ +#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ +#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ +#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ +#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ + +/* ADC.INTFLAGS bit masks and bit positions */ +#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ +#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ + +/* ADC.SAMPCTRL bit masks and bit positions */ +#define ADC_SAMPVAL_gm 0x3F /* Sampling time control register group mask. */ +#define ADC_SAMPVAL_gp 0 /* Sampling time control register group position. */ +#define ADC_SAMPVAL0_bm (1<<0) /* Sampling time control register bit 0 mask. */ +#define ADC_SAMPVAL0_bp 0 /* Sampling time control register bit 0 position. */ +#define ADC_SAMPVAL1_bm (1<<1) /* Sampling time control register bit 1 mask. */ +#define ADC_SAMPVAL1_bp 1 /* Sampling time control register bit 1 position. */ +#define ADC_SAMPVAL2_bm (1<<2) /* Sampling time control register bit 2 mask. */ +#define ADC_SAMPVAL2_bp 2 /* Sampling time control register bit 2 position. */ +#define ADC_SAMPVAL3_bm (1<<3) /* Sampling time control register bit 3 mask. */ +#define ADC_SAMPVAL3_bp 3 /* Sampling time control register bit 3 position. */ +#define ADC_SAMPVAL4_bm (1<<4) /* Sampling time control register bit 4 mask. */ +#define ADC_SAMPVAL4_bp 4 /* Sampling time control register bit 4 position. */ +#define ADC_SAMPVAL5_bm (1<<5) /* Sampling time control register bit 5 mask. */ +#define ADC_SAMPVAL5_bp 5 /* Sampling time control register bit 5 position. */ + +/* DAC - Digital/Analog Converter */ +/* DAC.CTRLA bit masks and bit positions */ +#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ +#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ + +#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ +#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ + +#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ +#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ + +#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ +#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ + +#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define DAC_ENABLE_bp 0 /* Enable bit position. */ + +/* DAC.CTRLB bit masks and bit positions */ +#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ +#define DAC_CHSEL_gp 5 /* Channel Select group position. */ +#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ +#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ +#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ +#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ + +#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ +#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ + +#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ +#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ + +/* DAC.CTRLC bit masks and bit positions */ +#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ +#define DAC_REFSEL_gp 3 /* Reference Select group position. */ +#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ +#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ +#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ +#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ + +#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ +#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ + +/* DAC.EVCTRL bit masks and bit positions */ +#define DAC_EVSPLIT_bm 0x08 /* Separate Event Channel Input for Channel 1 bit mask. */ +#define DAC_EVSPLIT_bp 3 /* Separate Event Channel Input for Channel 1 bit position. */ + +#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ +#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ +#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ +#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ +#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ +#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ +#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ +#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ + +/* DAC.STATUS bit masks and bit positions */ +#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ +#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ + +#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ +#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ + +/* DAC.CH0GAINCAL bit masks and bit positions */ +#define DAC_CH0GAINCAL_gm 0x7F /* Gain Calibration group mask. */ +#define DAC_CH0GAINCAL_gp 0 /* Gain Calibration group position. */ +#define DAC_CH0GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ +#define DAC_CH0GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ +#define DAC_CH0GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ +#define DAC_CH0GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ +#define DAC_CH0GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ +#define DAC_CH0GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ +#define DAC_CH0GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ +#define DAC_CH0GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ +#define DAC_CH0GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ +#define DAC_CH0GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ +#define DAC_CH0GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ +#define DAC_CH0GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ +#define DAC_CH0GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ +#define DAC_CH0GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ + +/* DAC.CH0OFFSETCAL bit masks and bit positions */ +#define DAC_CH0OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ +#define DAC_CH0OFFSETCAL_gp 0 /* Offset Calibration group position. */ +#define DAC_CH0OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ +#define DAC_CH0OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ +#define DAC_CH0OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ +#define DAC_CH0OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ +#define DAC_CH0OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ +#define DAC_CH0OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ +#define DAC_CH0OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ +#define DAC_CH0OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ +#define DAC_CH0OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ +#define DAC_CH0OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ +#define DAC_CH0OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ +#define DAC_CH0OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ +#define DAC_CH0OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ +#define DAC_CH0OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ + +/* DAC.CH1GAINCAL bit masks and bit positions */ +#define DAC_CH1GAINCAL_gm 0x7F /* Gain Calibration group mask. */ +#define DAC_CH1GAINCAL_gp 0 /* Gain Calibration group position. */ +#define DAC_CH1GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ +#define DAC_CH1GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ +#define DAC_CH1GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ +#define DAC_CH1GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ +#define DAC_CH1GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ +#define DAC_CH1GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ +#define DAC_CH1GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ +#define DAC_CH1GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ +#define DAC_CH1GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ +#define DAC_CH1GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ +#define DAC_CH1GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ +#define DAC_CH1GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ +#define DAC_CH1GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ +#define DAC_CH1GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ + +/* DAC.CH1OFFSETCAL bit masks and bit positions */ +#define DAC_CH1OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ +#define DAC_CH1OFFSETCAL_gp 0 /* Offset Calibration group position. */ +#define DAC_CH1OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ +#define DAC_CH1OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ +#define DAC_CH1OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ +#define DAC_CH1OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ +#define DAC_CH1OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ +#define DAC_CH1OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ +#define DAC_CH1OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ +#define DAC_CH1OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ +#define DAC_CH1OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ +#define DAC_CH1OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ +#define DAC_CH1OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ +#define DAC_CH1OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ +#define DAC_CH1OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ +#define DAC_CH1OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ + +/* AC - Analog Comparator */ +/* AC.AC0CTRL bit masks and bit positions */ +#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ +#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ +#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ +#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ +#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ +#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ + +#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ +#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ +#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ +#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ +#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ +#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ + +#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ + +#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define AC_ENABLE_bp 0 /* Enable bit position. */ + +/* AC.AC1CTRL bit masks and bit positions */ +/* AC_INTMODE Predefined. */ +/* AC_INTMODE Predefined. */ + +/* AC_INTLVL Predefined. */ +/* AC_INTLVL Predefined. */ + +/* AC_HYSMODE Predefined. */ +/* AC_HYSMODE Predefined. */ + +/* AC_ENABLE Predefined. */ +/* AC_ENABLE Predefined. */ + +/* AC.AC0MUXCTRL bit masks and bit positions */ +#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ +#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ +#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ +#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ +#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ +#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ +#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ +#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ + +#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ +#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ +#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ +#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ +#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ +#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ +#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ +#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ + +/* AC.AC1MUXCTRL bit masks and bit positions */ +/* AC_MUXPOS Predefined. */ +/* AC_MUXPOS Predefined. */ + +/* AC_MUXNEG Predefined. */ +/* AC_MUXNEG Predefined. */ + +/* AC.CTRLA bit masks and bit positions */ +#define AC_AC1INVEN_bm 0x08 /* Analog Comparator 1 Output Invert Enable bit mask. */ +#define AC_AC1INVEN_bp 3 /* Analog Comparator 1 Output Invert Enable bit position. */ + +#define AC_AC0INVEN_bm 0x04 /* Analog Comparator 0 Output Invert Enable bit mask. */ +#define AC_AC0INVEN_bp 2 /* Analog Comparator 0 Output Invert Enable bit position. */ + +#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ +#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ + +#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ +#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ + +/* AC.CTRLB bit masks and bit positions */ +#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ +#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ +#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ +#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ +#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ +#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ +#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ +#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ +#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ +#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ +#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ +#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ +#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ +#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ + +/* AC.WINCTRL bit masks and bit positions */ +#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ +#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ + +#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ +#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ +#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ +#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ +#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ +#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ + +#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ +#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ +#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ +#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ +#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ +#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ + +/* AC.STATUS bit masks and bit positions */ +#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ +#define AC_WSTATE_gp 6 /* Window Mode State group position. */ +#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ +#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ +#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ +#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ + +#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ +#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ + +#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ +#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ + +#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ +#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ + +#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ +#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ + +#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ +#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ + +/* AC.CURRCTRL bit masks and bit positions */ +#define AC_CURREN_bm 0x80 /* Current Source Enable bit mask. */ +#define AC_CURREN_bp 7 /* Current Source Enable bit position. */ + +#define AC_CURRMODE_bm 0x40 /* Current Mode bit mask. */ +#define AC_CURRMODE_bp 6 /* Current Mode bit position. */ + +#define AC_AC1CURR_bm 0x02 /* Analog Comparator 1 current source output bit mask. */ +#define AC_AC1CURR_bp 1 /* Analog Comparator 1 current source output bit position. */ + +#define AC_AC0CURR_bm 0x01 /* Analog Comparator 0 current source output bit mask. */ +#define AC_AC0CURR_bp 0 /* Analog Comparator 0 current source output bit position. */ + +/* AC.CURRCALIB bit masks and bit positions */ +#define AC_CALIB_gm 0x0F /* Current Source Calibration group mask. */ +#define AC_CALIB_gp 0 /* Current Source Calibration group position. */ +#define AC_CALIB0_bm (1<<0) /* Current Source Calibration bit 0 mask. */ +#define AC_CALIB0_bp 0 /* Current Source Calibration bit 0 position. */ +#define AC_CALIB1_bm (1<<1) /* Current Source Calibration bit 1 mask. */ +#define AC_CALIB1_bp 1 /* Current Source Calibration bit 1 position. */ +#define AC_CALIB2_bm (1<<2) /* Current Source Calibration bit 2 mask. */ +#define AC_CALIB2_bp 2 /* Current Source Calibration bit 2 position. */ +#define AC_CALIB3_bm (1<<3) /* Current Source Calibration bit 3 mask. */ +#define AC_CALIB3_bp 3 /* Current Source Calibration bit 3 position. */ + +/* RTC - Real-Time Clounter */ +/* RTC.CTRL bit masks and bit positions */ +#define RTC_CORREN_bm 0x08 /* Correction Enable bit mask. */ +#define RTC_CORREN_bp 3 /* Correction Enable bit position. */ + +#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ +#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ +#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ +#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ +#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ +#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ +#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ +#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ + +/* RTC.STATUS bit masks and bit positions */ +#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ +#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ + +/* RTC.INTCTRL bit masks and bit positions */ +#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ +#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ +#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ +#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ +#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ +#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ + +#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ +#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ +#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ +#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ +#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ +#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ + +/* RTC.INTFLAGS bit masks and bit positions */ +#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ +#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ + +#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + +/* RTC.CALIB bit masks and bit positions */ +#define RTC_SIGN_bm 0x80 /* Correction Sign bit mask. */ +#define RTC_SIGN_bp 7 /* Correction Sign bit position. */ + +#define RTC_ERROR_gm 0x7F /* Error Value group mask. */ +#define RTC_ERROR_gp 0 /* Error Value group position. */ +#define RTC_ERROR0_bm (1<<0) /* Error Value bit 0 mask. */ +#define RTC_ERROR0_bp 0 /* Error Value bit 0 position. */ +#define RTC_ERROR1_bm (1<<1) /* Error Value bit 1 mask. */ +#define RTC_ERROR1_bp 1 /* Error Value bit 1 position. */ +#define RTC_ERROR2_bm (1<<2) /* Error Value bit 2 mask. */ +#define RTC_ERROR2_bp 2 /* Error Value bit 2 position. */ +#define RTC_ERROR3_bm (1<<3) /* Error Value bit 3 mask. */ +#define RTC_ERROR3_bp 3 /* Error Value bit 3 position. */ +#define RTC_ERROR4_bm (1<<4) /* Error Value bit 4 mask. */ +#define RTC_ERROR4_bp 4 /* Error Value bit 4 position. */ +#define RTC_ERROR5_bm (1<<5) /* Error Value bit 5 mask. */ +#define RTC_ERROR5_bp 5 /* Error Value bit 5 position. */ +#define RTC_ERROR6_bm (1<<6) /* Error Value bit 6 mask. */ +#define RTC_ERROR6_bp 6 /* Error Value bit 6 position. */ + +/* XCL - XMEGA Custom Logic */ +/* XCL.CTRLA bit masks and bit positions */ +#define XCL_LUT0OUTEN_gm 0xC0 /* LUT0 Output Enable group mask. */ +#define XCL_LUT0OUTEN_gp 6 /* LUT0 Output Enable group position. */ +#define XCL_LUT0OUTEN0_bm (1<<6) /* LUT0 Output Enable bit 0 mask. */ +#define XCL_LUT0OUTEN0_bp 6 /* LUT0 Output Enable bit 0 position. */ +#define XCL_LUT0OUTEN1_bm (1<<7) /* LUT0 Output Enable bit 1 mask. */ +#define XCL_LUT0OUTEN1_bp 7 /* LUT0 Output Enable bit 1 position. */ + +#define XCL_PORTSEL_gm 0x30 /* Port Selection group mask. */ +#define XCL_PORTSEL_gp 4 /* Port Selection group position. */ +#define XCL_PORTSEL0_bm (1<<4) /* Port Selection bit 0 mask. */ +#define XCL_PORTSEL0_bp 4 /* Port Selection bit 0 position. */ +#define XCL_PORTSEL1_bm (1<<5) /* Port Selection bit 1 mask. */ +#define XCL_PORTSEL1_bp 5 /* Port Selection bit 1 position. */ + +#define XCL_LUTCONF_gm 0x07 /* LUT Configuration group mask. */ +#define XCL_LUTCONF_gp 0 /* LUT Configuration group position. */ +#define XCL_LUTCONF0_bm (1<<0) /* LUT Configuration bit 0 mask. */ +#define XCL_LUTCONF0_bp 0 /* LUT Configuration bit 0 position. */ +#define XCL_LUTCONF1_bm (1<<1) /* LUT Configuration bit 1 mask. */ +#define XCL_LUTCONF1_bp 1 /* LUT Configuration bit 1 position. */ +#define XCL_LUTCONF2_bm (1<<2) /* LUT Configuration bit 2 mask. */ +#define XCL_LUTCONF2_bp 2 /* LUT Configuration bit 2 position. */ + +/* XCL.CTRLB bit masks and bit positions */ +#define XCL_IN3SEL_gm 0xC0 /* Input Selection 3 group mask. */ +#define XCL_IN3SEL_gp 6 /* Input Selection 3 group position. */ +#define XCL_IN3SEL0_bm (1<<6) /* Input Selection 3 bit 0 mask. */ +#define XCL_IN3SEL0_bp 6 /* Input Selection 3 bit 0 position. */ +#define XCL_IN3SEL1_bm (1<<7) /* Input Selection 3 bit 1 mask. */ +#define XCL_IN3SEL1_bp 7 /* Input Selection 3 bit 1 position. */ + +#define XCL_IN2SEL_gm 0x30 /* Input Selection 2 group mask. */ +#define XCL_IN2SEL_gp 4 /* Input Selection 2 group position. */ +#define XCL_IN2SEL0_bm (1<<4) /* Input Selection 2 bit 0 mask. */ +#define XCL_IN2SEL0_bp 4 /* Input Selection 2 bit 0 position. */ +#define XCL_IN2SEL1_bm (1<<5) /* Input Selection 2 bit 1 mask. */ +#define XCL_IN2SEL1_bp 5 /* Input Selection 2 bit 1 position. */ + +#define XCL_IN1SEL_gm 0x0C /* Input Selection 1 group mask. */ +#define XCL_IN1SEL_gp 2 /* Input Selection 1 group position. */ +#define XCL_IN1SEL0_bm (1<<2) /* Input Selection 1 bit 0 mask. */ +#define XCL_IN1SEL0_bp 2 /* Input Selection 1 bit 0 position. */ +#define XCL_IN1SEL1_bm (1<<3) /* Input Selection 1 bit 1 mask. */ +#define XCL_IN1SEL1_bp 3 /* Input Selection 1 bit 1 position. */ + +#define XCL_IN0SEL_gm 0x03 /* Input Selection 0 group mask. */ +#define XCL_IN0SEL_gp 0 /* Input Selection 0 group position. */ +#define XCL_IN0SEL0_bm (1<<0) /* Input Selection 0 bit 0 mask. */ +#define XCL_IN0SEL0_bp 0 /* Input Selection 0 bit 0 position. */ +#define XCL_IN0SEL1_bm (1<<1) /* Input Selection 0 bit 1 mask. */ +#define XCL_IN0SEL1_bp 1 /* Input Selection 0 bit 1 position. */ + +/* XCL.CTRLC bit masks and bit positions */ +#define XCL_EVASYSEL1_bm 0x80 /* Asynchronous Event Line Selection for LUT1 bit mask. */ +#define XCL_EVASYSEL1_bp 7 /* Asynchronous Event Line Selection for LUT1 bit position. */ + +#define XCL_EVASYSEL0_bm 0x40 /* Asynchronous Event Line Selection for LUT0 bit mask. */ +#define XCL_EVASYSEL0_bp 6 /* Asynchronous Event Line Selection for LUT0 bit position. */ + +#define XCL_DLYSEL_gm 0x30 /* Delay Selection group mask. */ +#define XCL_DLYSEL_gp 4 /* Delay Selection group position. */ +#define XCL_DLYSEL0_bm (1<<4) /* Delay Selection bit 0 mask. */ +#define XCL_DLYSEL0_bp 4 /* Delay Selection bit 0 position. */ +#define XCL_DLYSEL1_bm (1<<5) /* Delay Selection bit 1 mask. */ +#define XCL_DLYSEL1_bp 5 /* Delay Selection bit 1 position. */ + +#define XCL_DLY1CONF_gm 0x0C /* Delay Configuration on LUT1 group mask. */ +#define XCL_DLY1CONF_gp 2 /* Delay Configuration on LUT1 group position. */ +#define XCL_DLY1CONF0_bm (1<<2) /* Delay Configuration on LUT1 bit 0 mask. */ +#define XCL_DLY1CONF0_bp 2 /* Delay Configuration on LUT1 bit 0 position. */ +#define XCL_DLY1CONF1_bm (1<<3) /* Delay Configuration on LUT1 bit 1 mask. */ +#define XCL_DLY1CONF1_bp 3 /* Delay Configuration on LUT1 bit 1 position. */ + +#define XCL_DLY0CONF_gm 0x03 /* Delay Configuration on LUT0 group mask. */ +#define XCL_DLY0CONF_gp 0 /* Delay Configuration on LUT0 group position. */ +#define XCL_DLY0CONF0_bm (1<<0) /* Delay Configuration on LUT0 bit 0 mask. */ +#define XCL_DLY0CONF0_bp 0 /* Delay Configuration on LUT0 bit 0 position. */ +#define XCL_DLY0CONF1_bm (1<<1) /* Delay Configuration on LUT0 bit 1 mask. */ +#define XCL_DLY0CONF1_bp 1 /* Delay Configuration on LUT0 bit 1 position. */ + +/* XCL.CTRLD bit masks and bit positions */ +#define XCL_TRUTH1_gm 0xF0 /* Truth Table of LUT1 group mask. */ +#define XCL_TRUTH1_gp 4 /* Truth Table of LUT1 group position. */ +#define XCL_TRUTH10_bm (1<<4) /* Truth Table of LUT1 bit 0 mask. */ +#define XCL_TRUTH10_bp 4 /* Truth Table of LUT1 bit 0 position. */ +#define XCL_TRUTH11_bm (1<<5) /* Truth Table of LUT1 bit 1 mask. */ +#define XCL_TRUTH11_bp 5 /* Truth Table of LUT1 bit 1 position. */ +#define XCL_TRUTH12_bm (1<<6) /* Truth Table of LUT1 bit 2 mask. */ +#define XCL_TRUTH12_bp 6 /* Truth Table of LUT1 bit 2 position. */ +#define XCL_TRUTH13_bm (1<<7) /* Truth Table of LUT1 bit 3 mask. */ +#define XCL_TRUTH13_bp 7 /* Truth Table of LUT1 bit 3 position. */ + +#define XCL_TRUTH0_gm 0x0F /* Truth Table of LUT0 group mask. */ +#define XCL_TRUTH0_gp 0 /* Truth Table of LUT0 group position. */ +#define XCL_TRUTH00_bm (1<<0) /* Truth Table of LUT0 bit 0 mask. */ +#define XCL_TRUTH00_bp 0 /* Truth Table of LUT0 bit 0 position. */ +#define XCL_TRUTH01_bm (1<<1) /* Truth Table of LUT0 bit 1 mask. */ +#define XCL_TRUTH01_bp 1 /* Truth Table of LUT0 bit 1 position. */ +#define XCL_TRUTH02_bm (1<<2) /* Truth Table of LUT0 bit 2 mask. */ +#define XCL_TRUTH02_bp 2 /* Truth Table of LUT0 bit 2 position. */ +#define XCL_TRUTH03_bm (1<<3) /* Truth Table of LUT0 bit 3 mask. */ +#define XCL_TRUTH03_bp 3 /* Truth Table of LUT0 bit 3 position. */ + +/* XCL.CTRLE bit masks and bit positions */ +#define XCL_CMDSEL_bm 0x80 /* Timer/Counter Command Selection bit mask. */ +#define XCL_CMDSEL_bp 7 /* Timer/Counter Command Selection bit position. */ + +#define XCL_TCSEL_gm 0x70 /* Timer/Counter Selection group mask. */ +#define XCL_TCSEL_gp 4 /* Timer/Counter Selection group position. */ +#define XCL_TCSEL0_bm (1<<4) /* Timer/Counter Selection bit 0 mask. */ +#define XCL_TCSEL0_bp 4 /* Timer/Counter Selection bit 0 position. */ +#define XCL_TCSEL1_bm (1<<5) /* Timer/Counter Selection bit 1 mask. */ +#define XCL_TCSEL1_bp 5 /* Timer/Counter Selection bit 1 position. */ +#define XCL_TCSEL2_bm (1<<6) /* Timer/Counter Selection bit 2 mask. */ +#define XCL_TCSEL2_bp 6 /* Timer/Counter Selection bit 2 position. */ + +#define XCL_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define XCL_CLKSEL_gp 0 /* Clock Selection group position. */ +#define XCL_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define XCL_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define XCL_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define XCL_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define XCL_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define XCL_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define XCL_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define XCL_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + +/* XCL.CTRLF bit masks and bit positions */ +#define XCL_CMDEN_gm 0xC0 /* Command Enable group mask. */ +#define XCL_CMDEN_gp 6 /* Command Enable group position. */ +#define XCL_CMDEN0_bm (1<<6) /* Command Enable bit 0 mask. */ +#define XCL_CMDEN0_bp 6 /* Command Enable bit 0 position. */ +#define XCL_CMDEN1_bm (1<<7) /* Command Enable bit 1 mask. */ +#define XCL_CMDEN1_bp 7 /* Command Enable bit 1 position. */ + +#define XCL_CMP1_bm 0x20 /* Compare Channel 1 Output Value bit mask. */ +#define XCL_CMP1_bp 5 /* Compare Channel 1 Output Value bit position. */ + +#define XCL_CMP0_bm 0x10 /* Compare Channel 0 Output Value bit mask. */ +#define XCL_CMP0_bp 4 /* Compare Channel 0 Output Value bit position. */ + +#define XCL_CCEN1_bm 0x08 /* Compare or Capture Channel 1 Enable bit mask. */ +#define XCL_CCEN1_bp 3 /* Compare or Capture Channel 1 Enable bit position. */ + +#define XCL_CCEN0_bm 0x04 /* Compare or Capture Channel 0 Enable bit mask. */ +#define XCL_CCEN0_bp 2 /* Compare or Capture Channel 0 Enable bit position. */ + +#define XCL_MODE_gm 0x03 /* Timer/Counter Mode group mask. */ +#define XCL_MODE_gp 0 /* Timer/Counter Mode group position. */ +#define XCL_MODE0_bm (1<<0) /* Timer/Counter Mode bit 0 mask. */ +#define XCL_MODE0_bp 0 /* Timer/Counter Mode bit 0 position. */ +#define XCL_MODE1_bm (1<<1) /* Timer/Counter Mode bit 1 mask. */ +#define XCL_MODE1_bp 1 /* Timer/Counter Mode bit 1 position. */ + +/* XCL.CTRLG bit masks and bit positions */ +#define XCL_EVACTEN_bm 0x80 /* Event Action Enable bit mask. */ +#define XCL_EVACTEN_bp 7 /* Event Action Enable bit position. */ + +#define XCL_EVACT1_gm 0x60 /* Event Action Selection on Timer/Counter 1 group mask. */ +#define XCL_EVACT1_gp 5 /* Event Action Selection on Timer/Counter 1 group position. */ +#define XCL_EVACT10_bm (1<<5) /* Event Action Selection on Timer/Counter 1 bit 0 mask. */ +#define XCL_EVACT10_bp 5 /* Event Action Selection on Timer/Counter 1 bit 0 position. */ +#define XCL_EVACT11_bm (1<<6) /* Event Action Selection on Timer/Counter 1 bit 1 mask. */ +#define XCL_EVACT11_bp 6 /* Event Action Selection on Timer/Counter 1 bit 1 position. */ + +#define XCL_EVACT0_gm 0x18 /* Event Action Selection on Timer/Counter 0 group mask. */ +#define XCL_EVACT0_gp 3 /* Event Action Selection on Timer/Counter 0 group position. */ +#define XCL_EVACT00_bm (1<<3) /* Event Action Selection on Timer/Counter 0 bit 0 mask. */ +#define XCL_EVACT00_bp 3 /* Event Action Selection on Timer/Counter 0 bit 0 position. */ +#define XCL_EVACT01_bm (1<<4) /* Event Action Selection on Timer/Counter 0 bit 1 mask. */ +#define XCL_EVACT01_bp 4 /* Event Action Selection on Timer/Counter 0 bit 1 position. */ + +#define XCL_EVSRC_gm 0x07 /* Event Source Selection group mask. */ +#define XCL_EVSRC_gp 0 /* Event Source Selection group position. */ +#define XCL_EVSRC0_bm (1<<0) /* Event Source Selection bit 0 mask. */ +#define XCL_EVSRC0_bp 0 /* Event Source Selection bit 0 position. */ +#define XCL_EVSRC1_bm (1<<1) /* Event Source Selection bit 1 mask. */ +#define XCL_EVSRC1_bp 1 /* Event Source Selection bit 1 position. */ +#define XCL_EVSRC2_bm (1<<2) /* Event Source Selection bit 2 mask. */ +#define XCL_EVSRC2_bp 2 /* Event Source Selection bit 2 position. */ + +/* XCL.INTCTRL bit masks and bit positions */ +#define XCL_UNF1IE_bm 0x80 /* Underflow 1 Interrupt Enable bit mask. */ +#define XCL_UNF1IE_bp 7 /* Underflow 1 Interrupt Enable bit position. */ + +#define XCL_PEC1IE_bm 0x80 /* Peripheral Counter 1 Interrupt Enable bit mask. */ +#define XCL_PEC1IE_bp 7 /* Peripheral Counter 1 Interrupt Enable bit position. */ + +#define XCL_PEC21IE_bm 0x80 /* Peripheral High Counter 2 Interrupt Enable bit mask. */ +#define XCL_PEC21IE_bp 7 /* Peripheral High Counter 2 Interrupt Enable bit position. */ + +#define XCL_UNF0IE_bm 0x40 /* Underflow 0 Interrupt Enable bit mask. */ +#define XCL_UNF0IE_bp 6 /* Underflow 0 Interrupt Enable bit position. */ + +#define XCL_PEC0IE_bm 0x40 /* Peripheral Counter 0 Interrupt Enable bit mask. */ +#define XCL_PEC0IE_bp 6 /* Peripheral Counter 0 Interrupt Enable bit position. */ + +#define XCL_CC1IE_bm 0x20 /* Compare Or Capture 1 Interrupt Enable bit mask. */ +#define XCL_CC1IE_bp 5 /* Compare Or Capture 1 Interrupt Enable bit position. */ + +#define XCL_PEC20IE_bm 0x20 /* Peripheral Low Counter 2 Interrupt Enable bit mask. */ +#define XCL_PEC20IE_bp 5 /* Peripheral Low Counter 2 Interrupt Enable bit position. */ + +#define XCL_CC0IE_bm 0x10 /* Compare Or Capture 0 Interrupt Enable bit mask. */ +#define XCL_CC0IE_bp 4 /* Compare Or Capture 0 Interrupt Enable bit position. */ + +#define XCL_UNFINTLVL_gm 0x0C /* Timer Underflow Interrupt Level group mask. */ +#define XCL_UNFINTLVL_gp 2 /* Timer Underflow Interrupt Level group position. */ +#define XCL_UNFINTLVL0_bm (1<<2) /* Timer Underflow Interrupt Level bit 0 mask. */ +#define XCL_UNFINTLVL0_bp 2 /* Timer Underflow Interrupt Level bit 0 position. */ +#define XCL_UNFINTLVL1_bm (1<<3) /* Timer Underflow Interrupt Level bit 1 mask. */ +#define XCL_UNFINTLVL1_bp 3 /* Timer Underflow Interrupt Level bit 1 position. */ + +#define XCL_CCINTLVL_gm 0x03 /* Timer Compare or Capture Interrupt Level group mask. */ +#define XCL_CCINTLVL_gp 0 /* Timer Compare or Capture Interrupt Level group position. */ +#define XCL_CCINTLVL0_bm (1<<0) /* Timer Compare or Capture Interrupt Level bit 0 mask. */ +#define XCL_CCINTLVL0_bp 0 /* Timer Compare or Capture Interrupt Level bit 0 position. */ +#define XCL_CCINTLVL1_bm (1<<1) /* Timer Compare or Capture Interrupt Level bit 1 mask. */ +#define XCL_CCINTLVL1_bp 1 /* Timer Compare or Capture Interrupt Level bit 1 position. */ + +/* XCL.INTFLAGS bit masks and bit positions */ +#define XCL_UNF1IF_bm 0x80 /* Timer/Counter 1 Underflow Interrupt Flag bit mask. */ +#define XCL_UNF1IF_bp 7 /* Timer/Counter 1 Underflow Interrupt Flag bit position. */ + +#define XCL_PEC1IF_bm 0x80 /* Peripheral Counter 1 Interrupt Flag bit mask. */ +#define XCL_PEC1IF_bp 7 /* Peripheral Counter 1 Interrupt Flag bit position. */ + +#define XCL_PEC21IF_bm 0x80 /* Peripheral High Counter 2 Interrupt Flag bit mask. */ +#define XCL_PEC21IF_bp 7 /* Peripheral High Counter 2 Interrupt Flag bit position. */ + +#define XCL_UNF0IF_bm 0x40 /* Timer/Counter 0 Underflow Interrupt Flag bit mask. */ +#define XCL_UNF0IF_bp 6 /* Timer/Counter 0 Underflow Interrupt Flag bit position. */ + +#define XCL_PEC0IF_bm 0x40 /* Peripheral Counter 0 Interrupt Flag bit mask. */ +#define XCL_PEC0IF_bp 6 /* Peripheral Counter 0 Interrupt Flag bit position. */ + +#define XCL_CC1IF_bm 0x20 /* Compare or Capture Channel 1 Interrupt Flag bit mask. */ +#define XCL_CC1IF_bp 5 /* Compare or Capture Channel 1 Interrupt Flag bit position. */ + +#define XCL_PEC20IF_bm 0x20 /* Peripheral Low Counter 2 Interrupt Flag bit mask. */ +#define XCL_PEC20IF_bp 5 /* Peripheral Low Counter 2 Interrupt Flag bit position. */ + +#define XCL_CC0IF_bm 0x10 /* Compare or Capture Channel 0 Interrupt Flag bit mask. */ +#define XCL_CC0IF_bp 4 /* Compare or Capture Channel 0 Interrupt Flag bit position. */ + +/* XCL.PLC bit masks and bit positions */ +#define XCL_PLC_gm 0xFF /* Peripheral Lenght Control Bits group mask. */ +#define XCL_PLC_gp 0 /* Peripheral Lenght Control Bits group position. */ +#define XCL_PLC0_bm (1<<0) /* Peripheral Lenght Control Bits bit 0 mask. */ +#define XCL_PLC0_bp 0 /* Peripheral Lenght Control Bits bit 0 position. */ +#define XCL_PLC1_bm (1<<1) /* Peripheral Lenght Control Bits bit 1 mask. */ +#define XCL_PLC1_bp 1 /* Peripheral Lenght Control Bits bit 1 position. */ +#define XCL_PLC2_bm (1<<2) /* Peripheral Lenght Control Bits bit 2 mask. */ +#define XCL_PLC2_bp 2 /* Peripheral Lenght Control Bits bit 2 position. */ +#define XCL_PLC3_bm (1<<3) /* Peripheral Lenght Control Bits bit 3 mask. */ +#define XCL_PLC3_bp 3 /* Peripheral Lenght Control Bits bit 3 position. */ +#define XCL_PLC4_bm (1<<4) /* Peripheral Lenght Control Bits bit 4 mask. */ +#define XCL_PLC4_bp 4 /* Peripheral Lenght Control Bits bit 4 position. */ +#define XCL_PLC5_bm (1<<5) /* Peripheral Lenght Control Bits bit 5 mask. */ +#define XCL_PLC5_bp 5 /* Peripheral Lenght Control Bits bit 5 position. */ +#define XCL_PLC6_bm (1<<6) /* Peripheral Lenght Control Bits bit 6 mask. */ +#define XCL_PLC6_bp 6 /* Peripheral Lenght Control Bits bit 6 position. */ +#define XCL_PLC7_bm (1<<7) /* Peripheral Lenght Control Bits bit 7 mask. */ +#define XCL_PLC7_bp 7 /* Peripheral Lenght Control Bits bit 7 position. */ + +/* XCL.CNTL bit masks and bit positions */ +#define XCL_BCNTO_gm 0xFF /* BTC0 Counter Byte group mask. */ +#define XCL_BCNTO_gp 0 /* BTC0 Counter Byte group position. */ +#define XCL_BCNTO0_bm (1<<0) /* BTC0 Counter Byte bit 0 mask. */ +#define XCL_BCNTO0_bp 0 /* BTC0 Counter Byte bit 0 position. */ +#define XCL_BCNTO1_bm (1<<1) /* BTC0 Counter Byte bit 1 mask. */ +#define XCL_BCNTO1_bp 1 /* BTC0 Counter Byte bit 1 position. */ +#define XCL_BCNTO2_bm (1<<2) /* BTC0 Counter Byte bit 2 mask. */ +#define XCL_BCNTO2_bp 2 /* BTC0 Counter Byte bit 2 position. */ +#define XCL_BCNTO3_bm (1<<3) /* BTC0 Counter Byte bit 3 mask. */ +#define XCL_BCNTO3_bp 3 /* BTC0 Counter Byte bit 3 position. */ +#define XCL_BCNTO4_bm (1<<4) /* BTC0 Counter Byte bit 4 mask. */ +#define XCL_BCNTO4_bp 4 /* BTC0 Counter Byte bit 4 position. */ +#define XCL_BCNTO5_bm (1<<5) /* BTC0 Counter Byte bit 5 mask. */ +#define XCL_BCNTO5_bp 5 /* BTC0 Counter Byte bit 5 position. */ +#define XCL_BCNTO6_bm (1<<6) /* BTC0 Counter Byte bit 6 mask. */ +#define XCL_BCNTO6_bp 6 /* BTC0 Counter Byte bit 6 position. */ +#define XCL_BCNTO7_bm (1<<7) /* BTC0 Counter Byte bit 7 mask. */ +#define XCL_BCNTO7_bp 7 /* BTC0 Counter Byte bit 7 position. */ + +#define XCL_CNTL_gm 0xFF /* TC16 Counter Low Byte group mask. */ +#define XCL_CNTL_gp 0 /* TC16 Counter Low Byte group position. */ +#define XCL_CNTL0_bm (1<<0) /* TC16 Counter Low Byte bit 0 mask. */ +#define XCL_CNTL0_bp 0 /* TC16 Counter Low Byte bit 0 position. */ +#define XCL_CNTL1_bm (1<<1) /* TC16 Counter Low Byte bit 1 mask. */ +#define XCL_CNTL1_bp 1 /* TC16 Counter Low Byte bit 1 position. */ +#define XCL_CNTL2_bm (1<<2) /* TC16 Counter Low Byte bit 2 mask. */ +#define XCL_CNTL2_bp 2 /* TC16 Counter Low Byte bit 2 position. */ +#define XCL_CNTL3_bm (1<<3) /* TC16 Counter Low Byte bit 3 mask. */ +#define XCL_CNTL3_bp 3 /* TC16 Counter Low Byte bit 3 position. */ +#define XCL_CNTL4_bm (1<<4) /* TC16 Counter Low Byte bit 4 mask. */ +#define XCL_CNTL4_bp 4 /* TC16 Counter Low Byte bit 4 position. */ +#define XCL_CNTL5_bm (1<<5) /* TC16 Counter Low Byte bit 5 mask. */ +#define XCL_CNTL5_bp 5 /* TC16 Counter Low Byte bit 5 position. */ +#define XCL_CNTL6_bm (1<<6) /* TC16 Counter Low Byte bit 6 mask. */ +#define XCL_CNTL6_bp 6 /* TC16 Counter Low Byte bit 6 position. */ +#define XCL_CNTL7_bm (1<<7) /* TC16 Counter Low Byte bit 7 mask. */ +#define XCL_CNTL7_bp 7 /* TC16 Counter Low Byte bit 7 position. */ + +#define XCL_PCNTO_gm 0xFF /* Peripheral Counter 0 Byte group mask. */ +#define XCL_PCNTO_gp 0 /* Peripheral Counter 0 Byte group position. */ +#define XCL_PCNTO0_bm (1<<0) /* Peripheral Counter 0 Byte bit 0 mask. */ +#define XCL_PCNTO0_bp 0 /* Peripheral Counter 0 Byte bit 0 position. */ +#define XCL_PCNTO1_bm (1<<1) /* Peripheral Counter 0 Byte bit 1 mask. */ +#define XCL_PCNTO1_bp 1 /* Peripheral Counter 0 Byte bit 1 position. */ +#define XCL_PCNTO2_bm (1<<2) /* Peripheral Counter 0 Byte bit 2 mask. */ +#define XCL_PCNTO2_bp 2 /* Peripheral Counter 0 Byte bit 2 position. */ +#define XCL_PCNTO3_bm (1<<3) /* Peripheral Counter 0 Byte bit 3 mask. */ +#define XCL_PCNTO3_bp 3 /* Peripheral Counter 0 Byte bit 3 position. */ +#define XCL_PCNTO4_bm (1<<4) /* Peripheral Counter 0 Byte bit 4 mask. */ +#define XCL_PCNTO4_bp 4 /* Peripheral Counter 0 Byte bit 4 position. */ +#define XCL_PCNTO5_bm (1<<5) /* Peripheral Counter 0 Byte bit 5 mask. */ +#define XCL_PCNTO5_bp 5 /* Peripheral Counter 0 Byte bit 5 position. */ +#define XCL_PCNTO6_bm (1<<6) /* Peripheral Counter 0 Byte bit 6 mask. */ +#define XCL_PCNTO6_bp 6 /* Peripheral Counter 0 Byte bit 6 position. */ +#define XCL_PCNTO7_bm (1<<7) /* Peripheral Counter 0 Byte bit 7 mask. */ +#define XCL_PCNTO7_bp 7 /* Peripheral Counter 0 Byte bit 7 position. */ + +/* XCL.CNTH bit masks and bit positions */ +#define XCL_BCNT1_gm 0xFF /* BTC1 Counter Byte group mask. */ +#define XCL_BCNT1_gp 0 /* BTC1 Counter Byte group position. */ +#define XCL_BCNT10_bm (1<<0) /* BTC1 Counter Byte bit 0 mask. */ +#define XCL_BCNT10_bp 0 /* BTC1 Counter Byte bit 0 position. */ +#define XCL_BCNT11_bm (1<<1) /* BTC1 Counter Byte bit 1 mask. */ +#define XCL_BCNT11_bp 1 /* BTC1 Counter Byte bit 1 position. */ +#define XCL_BCNT12_bm (1<<2) /* BTC1 Counter Byte bit 2 mask. */ +#define XCL_BCNT12_bp 2 /* BTC1 Counter Byte bit 2 position. */ +#define XCL_BCNT13_bm (1<<3) /* BTC1 Counter Byte bit 3 mask. */ +#define XCL_BCNT13_bp 3 /* BTC1 Counter Byte bit 3 position. */ +#define XCL_BCNT14_bm (1<<4) /* BTC1 Counter Byte bit 4 mask. */ +#define XCL_BCNT14_bp 4 /* BTC1 Counter Byte bit 4 position. */ +#define XCL_BCNT15_bm (1<<5) /* BTC1 Counter Byte bit 5 mask. */ +#define XCL_BCNT15_bp 5 /* BTC1 Counter Byte bit 5 position. */ +#define XCL_BCNT16_bm (1<<6) /* BTC1 Counter Byte bit 6 mask. */ +#define XCL_BCNT16_bp 6 /* BTC1 Counter Byte bit 6 position. */ +#define XCL_BCNT17_bm (1<<7) /* BTC1 Counter Byte bit 7 mask. */ +#define XCL_BCNT17_bp 7 /* BTC1 Counter Byte bit 7 position. */ + +#define XCL_CNTH_gm 0xFF /* TC16 Counter High Byte group mask. */ +#define XCL_CNTH_gp 0 /* TC16 Counter High Byte group position. */ +#define XCL_CNTH0_bm (1<<0) /* TC16 Counter High Byte bit 0 mask. */ +#define XCL_CNTH0_bp 0 /* TC16 Counter High Byte bit 0 position. */ +#define XCL_CNTH1_bm (1<<1) /* TC16 Counter High Byte bit 1 mask. */ +#define XCL_CNTH1_bp 1 /* TC16 Counter High Byte bit 1 position. */ +#define XCL_CNTH2_bm (1<<2) /* TC16 Counter High Byte bit 2 mask. */ +#define XCL_CNTH2_bp 2 /* TC16 Counter High Byte bit 2 position. */ +#define XCL_CNTH3_bm (1<<3) /* TC16 Counter High Byte bit 3 mask. */ +#define XCL_CNTH3_bp 3 /* TC16 Counter High Byte bit 3 position. */ +#define XCL_CNTH4_bm (1<<4) /* TC16 Counter High Byte bit 4 mask. */ +#define XCL_CNTH4_bp 4 /* TC16 Counter High Byte bit 4 position. */ +#define XCL_CNTH5_bm (1<<5) /* TC16 Counter High Byte bit 5 mask. */ +#define XCL_CNTH5_bp 5 /* TC16 Counter High Byte bit 5 position. */ +#define XCL_CNTH6_bm (1<<6) /* TC16 Counter High Byte bit 6 mask. */ +#define XCL_CNTH6_bp 6 /* TC16 Counter High Byte bit 6 position. */ +#define XCL_CNTH7_bm (1<<7) /* TC16 Counter High Byte bit 7 mask. */ +#define XCL_CNTH7_bp 7 /* TC16 Counter High Byte bit 7 position. */ + +#define XCL_PCNT1_gm 0xFF /* Peripheral Counter 1 Byte group mask. */ +#define XCL_PCNT1_gp 0 /* Peripheral Counter 1 Byte group position. */ +#define XCL_PCNT10_bm (1<<0) /* Peripheral Counter 1 Byte bit 0 mask. */ +#define XCL_PCNT10_bp 0 /* Peripheral Counter 1 Byte bit 0 position. */ +#define XCL_PCNT11_bm (1<<1) /* Peripheral Counter 1 Byte bit 1 mask. */ +#define XCL_PCNT11_bp 1 /* Peripheral Counter 1 Byte bit 1 position. */ +#define XCL_PCNT12_bm (1<<2) /* Peripheral Counter 1 Byte bit 2 mask. */ +#define XCL_PCNT12_bp 2 /* Peripheral Counter 1 Byte bit 2 position. */ +#define XCL_PCNT13_bm (1<<3) /* Peripheral Counter 1 Byte bit 3 mask. */ +#define XCL_PCNT13_bp 3 /* Peripheral Counter 1 Byte bit 3 position. */ +#define XCL_PCNT14_bm (1<<4) /* Peripheral Counter 1 Byte bit 4 mask. */ +#define XCL_PCNT14_bp 4 /* Peripheral Counter 1 Byte bit 4 position. */ +#define XCL_PCNT15_bm (1<<5) /* Peripheral Counter 1 Byte bit 5 mask. */ +#define XCL_PCNT15_bp 5 /* Peripheral Counter 1 Byte bit 5 position. */ +#define XCL_PCNT16_bm (1<<6) /* Peripheral Counter 1 Byte bit 6 mask. */ +#define XCL_PCNT16_bp 6 /* Peripheral Counter 1 Byte bit 6 position. */ +#define XCL_PCNT17_bm (1<<7) /* Peripheral Counter 1 Byte bit 7 mask. */ +#define XCL_PCNT17_bp 7 /* Peripheral Counter 1 Byte bit 7 position. */ + +#define XCL_PCNT21_gm 0xF0 /* Peripheral High Counter 2 Bits group mask. */ +#define XCL_PCNT21_gp 4 /* Peripheral High Counter 2 Bits group position. */ +#define XCL_PCNT210_bm (1<<4) /* Peripheral High Counter 2 Bits bit 0 mask. */ +#define XCL_PCNT210_bp 4 /* Peripheral High Counter 2 Bits bit 0 position. */ +#define XCL_PCNT211_bm (1<<5) /* Peripheral High Counter 2 Bits bit 1 mask. */ +#define XCL_PCNT211_bp 5 /* Peripheral High Counter 2 Bits bit 1 position. */ +#define XCL_PCNT212_bm (1<<6) /* Peripheral High Counter 2 Bits bit 2 mask. */ +#define XCL_PCNT212_bp 6 /* Peripheral High Counter 2 Bits bit 2 position. */ +#define XCL_PCNT213_bm (1<<7) /* Peripheral High Counter 2 Bits bit 3 mask. */ +#define XCL_PCNT213_bp 7 /* Peripheral High Counter 2 Bits bit 3 position. */ + +#define XCL_PCNT20_gm 0x0F /* Peripheral Low Counter 2 Bits group mask. */ +#define XCL_PCNT20_gp 0 /* Peripheral Low Counter 2 Bits group position. */ +#define XCL_PCNT200_bm (1<<0) /* Peripheral Low Counter 2 Bits bit 0 mask. */ +#define XCL_PCNT200_bp 0 /* Peripheral Low Counter 2 Bits bit 0 position. */ +#define XCL_PCNT201_bm (1<<1) /* Peripheral Low Counter 2 Bits bit 1 mask. */ +#define XCL_PCNT201_bp 1 /* Peripheral Low Counter 2 Bits bit 1 position. */ +#define XCL_PCNT202_bm (1<<2) /* Peripheral Low Counter 2 Bits bit 2 mask. */ +#define XCL_PCNT202_bp 2 /* Peripheral Low Counter 2 Bits bit 2 position. */ +#define XCL_PCNT203_bm (1<<3) /* Peripheral Low Counter 2 Bits bit 3 mask. */ +#define XCL_PCNT203_bp 3 /* Peripheral Low Counter 2 Bits bit 3 position. */ + +/* XCL.CMPL bit masks and bit positions */ +#define XCL_CMPL_gm 0xFF /* TC16 Compare Low Byte group mask. */ +#define XCL_CMPL_gp 0 /* TC16 Compare Low Byte group position. */ +#define XCL_CMPL0_bm (1<<0) /* TC16 Compare Low Byte bit 0 mask. */ +#define XCL_CMPL0_bp 0 /* TC16 Compare Low Byte bit 0 position. */ +#define XCL_CMPL1_bm (1<<1) /* TC16 Compare Low Byte bit 1 mask. */ +#define XCL_CMPL1_bp 1 /* TC16 Compare Low Byte bit 1 position. */ +#define XCL_CMPL2_bm (1<<2) /* TC16 Compare Low Byte bit 2 mask. */ +#define XCL_CMPL2_bp 2 /* TC16 Compare Low Byte bit 2 position. */ +#define XCL_CMPL3_bm (1<<3) /* TC16 Compare Low Byte bit 3 mask. */ +#define XCL_CMPL3_bp 3 /* TC16 Compare Low Byte bit 3 position. */ +#define XCL_CMPL4_bm (1<<4) /* TC16 Compare Low Byte bit 4 mask. */ +#define XCL_CMPL4_bp 4 /* TC16 Compare Low Byte bit 4 position. */ +#define XCL_CMPL5_bm (1<<5) /* TC16 Compare Low Byte bit 5 mask. */ +#define XCL_CMPL5_bp 5 /* TC16 Compare Low Byte bit 5 position. */ +#define XCL_CMPL6_bm (1<<6) /* TC16 Compare Low Byte bit 6 mask. */ +#define XCL_CMPL6_bp 6 /* TC16 Compare Low Byte bit 6 position. */ +#define XCL_CMPL7_bm (1<<7) /* TC16 Compare Low Byte bit 7 mask. */ +#define XCL_CMPL7_bp 7 /* TC16 Compare Low Byte bit 7 position. */ + +#define XCL_BCMP0_gm 0xFF /* BTC0 Compare Byte group mask. */ +#define XCL_BCMP0_gp 0 /* BTC0 Compare Byte group position. */ +#define XCL_BCMP00_bm (1<<0) /* BTC0 Compare Byte bit 0 mask. */ +#define XCL_BCMP00_bp 0 /* BTC0 Compare Byte bit 0 position. */ +#define XCL_BCMP01_bm (1<<1) /* BTC0 Compare Byte bit 1 mask. */ +#define XCL_BCMP01_bp 1 /* BTC0 Compare Byte bit 1 position. */ +#define XCL_BCMP02_bm (1<<2) /* BTC0 Compare Byte bit 2 mask. */ +#define XCL_BCMP02_bp 2 /* BTC0 Compare Byte bit 2 position. */ +#define XCL_BCMP03_bm (1<<3) /* BTC0 Compare Byte bit 3 mask. */ +#define XCL_BCMP03_bp 3 /* BTC0 Compare Byte bit 3 position. */ +#define XCL_BCMP04_bm (1<<4) /* BTC0 Compare Byte bit 4 mask. */ +#define XCL_BCMP04_bp 4 /* BTC0 Compare Byte bit 4 position. */ +#define XCL_BCMP05_bm (1<<5) /* BTC0 Compare Byte bit 5 mask. */ +#define XCL_BCMP05_bp 5 /* BTC0 Compare Byte bit 5 position. */ +#define XCL_BCMP06_bm (1<<6) /* BTC0 Compare Byte bit 6 mask. */ +#define XCL_BCMP06_bp 6 /* BTC0 Compare Byte bit 6 position. */ +#define XCL_BCMP07_bm (1<<7) /* BTC0 Compare Byte bit 7 mask. */ +#define XCL_BCMP07_bp 7 /* BTC0 Compare Byte bit 7 position. */ + +/* XCL.CMPH bit masks and bit positions */ +#define XCL_CMPH_gm 0xFF /* TC16 Compare High Byte group mask. */ +#define XCL_CMPH_gp 0 /* TC16 Compare High Byte group position. */ +#define XCL_CMPH0_bm (1<<0) /* TC16 Compare High Byte bit 0 mask. */ +#define XCL_CMPH0_bp 0 /* TC16 Compare High Byte bit 0 position. */ +#define XCL_CMPH1_bm (1<<1) /* TC16 Compare High Byte bit 1 mask. */ +#define XCL_CMPH1_bp 1 /* TC16 Compare High Byte bit 1 position. */ +#define XCL_CMPH2_bm (1<<2) /* TC16 Compare High Byte bit 2 mask. */ +#define XCL_CMPH2_bp 2 /* TC16 Compare High Byte bit 2 position. */ +#define XCL_CMPH3_bm (1<<3) /* TC16 Compare High Byte bit 3 mask. */ +#define XCL_CMPH3_bp 3 /* TC16 Compare High Byte bit 3 position. */ +#define XCL_CMPH4_bm (1<<4) /* TC16 Compare High Byte bit 4 mask. */ +#define XCL_CMPH4_bp 4 /* TC16 Compare High Byte bit 4 position. */ +#define XCL_CMPH5_bm (1<<5) /* TC16 Compare High Byte bit 5 mask. */ +#define XCL_CMPH5_bp 5 /* TC16 Compare High Byte bit 5 position. */ +#define XCL_CMPH6_bm (1<<6) /* TC16 Compare High Byte bit 6 mask. */ +#define XCL_CMPH6_bp 6 /* TC16 Compare High Byte bit 6 position. */ +#define XCL_CMPH7_bm (1<<7) /* TC16 Compare High Byte bit 7 mask. */ +#define XCL_CMPH7_bp 7 /* TC16 Compare High Byte bit 7 position. */ + +#define XCL_BCMP1_gm 0xFF /* BTC1 Compare Byte group mask. */ +#define XCL_BCMP1_gp 0 /* BTC1 Compare Byte group position. */ +#define XCL_BCMP10_bm (1<<0) /* BTC1 Compare Byte bit 0 mask. */ +#define XCL_BCMP10_bp 0 /* BTC1 Compare Byte bit 0 position. */ +#define XCL_BCMP11_bm (1<<1) /* BTC1 Compare Byte bit 1 mask. */ +#define XCL_BCMP11_bp 1 /* BTC1 Compare Byte bit 1 position. */ +#define XCL_BCMP12_bm (1<<2) /* BTC1 Compare Byte bit 2 mask. */ +#define XCL_BCMP12_bp 2 /* BTC1 Compare Byte bit 2 position. */ +#define XCL_BCMP13_bm (1<<3) /* BTC1 Compare Byte bit 3 mask. */ +#define XCL_BCMP13_bp 3 /* BTC1 Compare Byte bit 3 position. */ +#define XCL_BCMP14_bm (1<<4) /* BTC1 Compare Byte bit 4 mask. */ +#define XCL_BCMP14_bp 4 /* BTC1 Compare Byte bit 4 position. */ +#define XCL_BCMP15_bm (1<<5) /* BTC1 Compare Byte bit 5 mask. */ +#define XCL_BCMP15_bp 5 /* BTC1 Compare Byte bit 5 position. */ +#define XCL_BCMP16_bm (1<<6) /* BTC1 Compare Byte bit 6 mask. */ +#define XCL_BCMP16_bp 6 /* BTC1 Compare Byte bit 6 position. */ +#define XCL_BCMP17_bm (1<<7) /* BTC1 Compare Byte bit 7 mask. */ +#define XCL_BCMP17_bp 7 /* BTC1 Compare Byte bit 7 position. */ + +/* XCL.PERCAPTL bit masks and bit positions */ +#define XCL_PERL_gm 0xFF /* TC16 Low Byte Period group mask. */ +#define XCL_PERL_gp 0 /* TC16 Low Byte Period group position. */ +#define XCL_PERL0_bm (1<<0) /* TC16 Low Byte Period bit 0 mask. */ +#define XCL_PERL0_bp 0 /* TC16 Low Byte Period bit 0 position. */ +#define XCL_PERL1_bm (1<<1) /* TC16 Low Byte Period bit 1 mask. */ +#define XCL_PERL1_bp 1 /* TC16 Low Byte Period bit 1 position. */ +#define XCL_PERL2_bm (1<<2) /* TC16 Low Byte Period bit 2 mask. */ +#define XCL_PERL2_bp 2 /* TC16 Low Byte Period bit 2 position. */ +#define XCL_PERL3_bm (1<<3) /* TC16 Low Byte Period bit 3 mask. */ +#define XCL_PERL3_bp 3 /* TC16 Low Byte Period bit 3 position. */ +#define XCL_PERL4_bm (1<<4) /* TC16 Low Byte Period bit 4 mask. */ +#define XCL_PERL4_bp 4 /* TC16 Low Byte Period bit 4 position. */ +#define XCL_PERL5_bm (1<<5) /* TC16 Low Byte Period bit 5 mask. */ +#define XCL_PERL5_bp 5 /* TC16 Low Byte Period bit 5 position. */ +#define XCL_PERL6_bm (1<<6) /* TC16 Low Byte Period bit 6 mask. */ +#define XCL_PERL6_bp 6 /* TC16 Low Byte Period bit 6 position. */ +#define XCL_PERL7_bm (1<<7) /* TC16 Low Byte Period bit 7 mask. */ +#define XCL_PERL7_bp 7 /* TC16 Low Byte Period bit 7 position. */ + +#define XCL_CAPTL_gm 0xFF /* TC16 Capture Value Low Byte group mask. */ +#define XCL_CAPTL_gp 0 /* TC16 Capture Value Low Byte group position. */ +#define XCL_CAPTL0_bm (1<<0) /* TC16 Capture Value Low Byte bit 0 mask. */ +#define XCL_CAPTL0_bp 0 /* TC16 Capture Value Low Byte bit 0 position. */ +#define XCL_CAPTL1_bm (1<<1) /* TC16 Capture Value Low Byte bit 1 mask. */ +#define XCL_CAPTL1_bp 1 /* TC16 Capture Value Low Byte bit 1 position. */ +#define XCL_CAPTL2_bm (1<<2) /* TC16 Capture Value Low Byte bit 2 mask. */ +#define XCL_CAPTL2_bp 2 /* TC16 Capture Value Low Byte bit 2 position. */ +#define XCL_CAPTL3_bm (1<<3) /* TC16 Capture Value Low Byte bit 3 mask. */ +#define XCL_CAPTL3_bp 3 /* TC16 Capture Value Low Byte bit 3 position. */ +#define XCL_CAPTL4_bm (1<<4) /* TC16 Capture Value Low Byte bit 4 mask. */ +#define XCL_CAPTL4_bp 4 /* TC16 Capture Value Low Byte bit 4 position. */ +#define XCL_CAPTL5_bm (1<<5) /* TC16 Capture Value Low Byte bit 5 mask. */ +#define XCL_CAPTL5_bp 5 /* TC16 Capture Value Low Byte bit 5 position. */ +#define XCL_CAPTL6_bm (1<<6) /* TC16 Capture Value Low Byte bit 6 mask. */ +#define XCL_CAPTL6_bp 6 /* TC16 Capture Value Low Byte bit 6 position. */ +#define XCL_CAPTL7_bm (1<<7) /* TC16 Capture Value Low Byte bit 7 mask. */ +#define XCL_CAPTL7_bp 7 /* TC16 Capture Value Low Byte bit 7 position. */ + +#define XCL_BPER0_gm 0xFF /* BTC0 Period group mask. */ +#define XCL_BPER0_gp 0 /* BTC0 Period group position. */ +#define XCL_BPER00_bm (1<<0) /* BTC0 Period bit 0 mask. */ +#define XCL_BPER00_bp 0 /* BTC0 Period bit 0 position. */ +#define XCL_BPER01_bm (1<<1) /* BTC0 Period bit 1 mask. */ +#define XCL_BPER01_bp 1 /* BTC0 Period bit 1 position. */ +#define XCL_BPER02_bm (1<<2) /* BTC0 Period bit 2 mask. */ +#define XCL_BPER02_bp 2 /* BTC0 Period bit 2 position. */ +#define XCL_BPER03_bm (1<<3) /* BTC0 Period bit 3 mask. */ +#define XCL_BPER03_bp 3 /* BTC0 Period bit 3 position. */ +#define XCL_BPER04_bm (1<<4) /* BTC0 Period bit 4 mask. */ +#define XCL_BPER04_bp 4 /* BTC0 Period bit 4 position. */ +#define XCL_BPER05_bm (1<<5) /* BTC0 Period bit 5 mask. */ +#define XCL_BPER05_bp 5 /* BTC0 Period bit 5 position. */ +#define XCL_BPER06_bm (1<<6) /* BTC0 Period bit 6 mask. */ +#define XCL_BPER06_bp 6 /* BTC0 Period bit 6 position. */ +#define XCL_BPER07_bm (1<<7) /* BTC0 Period bit 7 mask. */ +#define XCL_BPER07_bp 7 /* BTC0 Period bit 7 position. */ + +#define XCL_BCAPT0_gm 0xFF /* BTC0 Capture Value Byte group mask. */ +#define XCL_BCAPT0_gp 0 /* BTC0 Capture Value Byte group position. */ +#define XCL_BCAPT00_bm (1<<0) /* BTC0 Capture Value Byte bit 0 mask. */ +#define XCL_BCAPT00_bp 0 /* BTC0 Capture Value Byte bit 0 position. */ +#define XCL_BCAPT01_bm (1<<1) /* BTC0 Capture Value Byte bit 1 mask. */ +#define XCL_BCAPT01_bp 1 /* BTC0 Capture Value Byte bit 1 position. */ +#define XCL_BCAPT02_bm (1<<2) /* BTC0 Capture Value Byte bit 2 mask. */ +#define XCL_BCAPT02_bp 2 /* BTC0 Capture Value Byte bit 2 position. */ +#define XCL_BCAPT03_bm (1<<3) /* BTC0 Capture Value Byte bit 3 mask. */ +#define XCL_BCAPT03_bp 3 /* BTC0 Capture Value Byte bit 3 position. */ +#define XCL_BCAPT04_bm (1<<4) /* BTC0 Capture Value Byte bit 4 mask. */ +#define XCL_BCAPT04_bp 4 /* BTC0 Capture Value Byte bit 4 position. */ +#define XCL_BCAPT05_bm (1<<5) /* BTC0 Capture Value Byte bit 5 mask. */ +#define XCL_BCAPT05_bp 5 /* BTC0 Capture Value Byte bit 5 position. */ +#define XCL_BCAPT06_bm (1<<6) /* BTC0 Capture Value Byte bit 6 mask. */ +#define XCL_BCAPT06_bp 6 /* BTC0 Capture Value Byte bit 6 position. */ +#define XCL_BCAPT07_bm (1<<7) /* BTC0 Capture Value Byte bit 7 mask. */ +#define XCL_BCAPT07_bp 7 /* BTC0 Capture Value Byte bit 7 position. */ + +/* XCL.PERCAPTH bit masks and bit positions */ +#define XCL_PERH_gm 0xFF /* TC16 High Byte Period group mask. */ +#define XCL_PERH_gp 0 /* TC16 High Byte Period group position. */ +#define XCL_PERH0_bm (1<<0) /* TC16 High Byte Period bit 0 mask. */ +#define XCL_PERH0_bp 0 /* TC16 High Byte Period bit 0 position. */ +#define XCL_PERH1_bm (1<<1) /* TC16 High Byte Period bit 1 mask. */ +#define XCL_PERH1_bp 1 /* TC16 High Byte Period bit 1 position. */ +#define XCL_PERH2_bm (1<<2) /* TC16 High Byte Period bit 2 mask. */ +#define XCL_PERH2_bp 2 /* TC16 High Byte Period bit 2 position. */ +#define XCL_PERH3_bm (1<<3) /* TC16 High Byte Period bit 3 mask. */ +#define XCL_PERH3_bp 3 /* TC16 High Byte Period bit 3 position. */ +#define XCL_PERH4_bm (1<<4) /* TC16 High Byte Period bit 4 mask. */ +#define XCL_PERH4_bp 4 /* TC16 High Byte Period bit 4 position. */ +#define XCL_PERH5_bm (1<<5) /* TC16 High Byte Period bit 5 mask. */ +#define XCL_PERH5_bp 5 /* TC16 High Byte Period bit 5 position. */ +#define XCL_PERH6_bm (1<<6) /* TC16 High Byte Period bit 6 mask. */ +#define XCL_PERH6_bp 6 /* TC16 High Byte Period bit 6 position. */ +#define XCL_PERH7_bm (1<<7) /* TC16 High Byte Period bit 7 mask. */ +#define XCL_PERH7_bp 7 /* TC16 High Byte Period bit 7 position. */ + +#define XCL_CAPTH_gm 0xFF /* TC16 Capture Value High Byte group mask. */ +#define XCL_CAPTH_gp 0 /* TC16 Capture Value High Byte group position. */ +#define XCL_CAPTH0_bm (1<<0) /* TC16 Capture Value High Byte bit 0 mask. */ +#define XCL_CAPTH0_bp 0 /* TC16 Capture Value High Byte bit 0 position. */ +#define XCL_CAPTH1_bm (1<<1) /* TC16 Capture Value High Byte bit 1 mask. */ +#define XCL_CAPTH1_bp 1 /* TC16 Capture Value High Byte bit 1 position. */ +#define XCL_CAPTH2_bm (1<<2) /* TC16 Capture Value High Byte bit 2 mask. */ +#define XCL_CAPTH2_bp 2 /* TC16 Capture Value High Byte bit 2 position. */ +#define XCL_CAPTH3_bm (1<<3) /* TC16 Capture Value High Byte bit 3 mask. */ +#define XCL_CAPTH3_bp 3 /* TC16 Capture Value High Byte bit 3 position. */ +#define XCL_CAPTH4_bm (1<<4) /* TC16 Capture Value High Byte bit 4 mask. */ +#define XCL_CAPTH4_bp 4 /* TC16 Capture Value High Byte bit 4 position. */ +#define XCL_CAPTH5_bm (1<<5) /* TC16 Capture Value High Byte bit 5 mask. */ +#define XCL_CAPTH5_bp 5 /* TC16 Capture Value High Byte bit 5 position. */ +#define XCL_CAPTH6_bm (1<<6) /* TC16 Capture Value High Byte bit 6 mask. */ +#define XCL_CAPTH6_bp 6 /* TC16 Capture Value High Byte bit 6 position. */ +#define XCL_CAPTH7_bm (1<<7) /* TC16 Capture Value High Byte bit 7 mask. */ +#define XCL_CAPTH7_bp 7 /* TC16 Capture Value High Byte bit 7 position. */ + +#define XCL_BPER1_gm 0xFF /* BTC1 Period group mask. */ +#define XCL_BPER1_gp 0 /* BTC1 Period group position. */ +#define XCL_BPER10_bm (1<<0) /* BTC1 Period bit 0 mask. */ +#define XCL_BPER10_bp 0 /* BTC1 Period bit 0 position. */ +#define XCL_BPER11_bm (1<<1) /* BTC1 Period bit 1 mask. */ +#define XCL_BPER11_bp 1 /* BTC1 Period bit 1 position. */ +#define XCL_BPER12_bm (1<<2) /* BTC1 Period bit 2 mask. */ +#define XCL_BPER12_bp 2 /* BTC1 Period bit 2 position. */ +#define XCL_BPER13_bm (1<<3) /* BTC1 Period bit 3 mask. */ +#define XCL_BPER13_bp 3 /* BTC1 Period bit 3 position. */ +#define XCL_BPER14_bm (1<<4) /* BTC1 Period bit 4 mask. */ +#define XCL_BPER14_bp 4 /* BTC1 Period bit 4 position. */ +#define XCL_BPER15_bm (1<<5) /* BTC1 Period bit 5 mask. */ +#define XCL_BPER15_bp 5 /* BTC1 Period bit 5 position. */ +#define XCL_BPER16_bm (1<<6) /* BTC1 Period bit 6 mask. */ +#define XCL_BPER16_bp 6 /* BTC1 Period bit 6 position. */ +#define XCL_BPER17_bm (1<<7) /* BTC1 Period bit 7 mask. */ +#define XCL_BPER17_bp 7 /* BTC1 Period bit 7 position. */ + +#define XCL_BCAPT1_gm 0xFF /* BTC1 Capture Value Byte group mask. */ +#define XCL_BCAPT1_gp 0 /* BTC1 Capture Value Byte group position. */ +#define XCL_BCAPT10_bm (1<<0) /* BTC1 Capture Value Byte bit 0 mask. */ +#define XCL_BCAPT10_bp 0 /* BTC1 Capture Value Byte bit 0 position. */ +#define XCL_BCAPT11_bm (1<<1) /* BTC1 Capture Value Byte bit 1 mask. */ +#define XCL_BCAPT11_bp 1 /* BTC1 Capture Value Byte bit 1 position. */ +#define XCL_BCAPT12_bm (1<<2) /* BTC1 Capture Value Byte bit 2 mask. */ +#define XCL_BCAPT12_bp 2 /* BTC1 Capture Value Byte bit 2 position. */ +#define XCL_BCAPT13_bm (1<<3) /* BTC1 Capture Value Byte bit 3 mask. */ +#define XCL_BCAPT13_bp 3 /* BTC1 Capture Value Byte bit 3 position. */ +#define XCL_BCAPT14_bm (1<<4) /* BTC1 Capture Value Byte bit 4 mask. */ +#define XCL_BCAPT14_bp 4 /* BTC1 Capture Value Byte bit 4 position. */ +#define XCL_BCAPT15_bm (1<<5) /* BTC1 Capture Value Byte bit 5 mask. */ +#define XCL_BCAPT15_bp 5 /* BTC1 Capture Value Byte bit 5 position. */ +#define XCL_BCAPT16_bm (1<<6) /* BTC1 Capture Value Byte bit 6 mask. */ +#define XCL_BCAPT16_bp 6 /* BTC1 Capture Value Byte bit 6 position. */ +#define XCL_BCAPT17_bm (1<<7) /* BTC1 Capture Value Byte bit 7 mask. */ +#define XCL_BCAPT17_bp 7 /* BTC1 Capture Value Byte bit 7 position. */ + +/* TWI - Two-Wire Interface */ +/* TWI.CTRL bit masks and bit positions */ +#define TWI_BRIDGEEN_bm 0x80 /* Bridge Enable bit mask. */ +#define TWI_BRIDGEEN_bp 7 /* Bridge Enable bit position. */ + +#define TWI_SFMPEN_bm 0x40 /* Slave Fast Mode Plus Enable bit mask. */ +#define TWI_SFMPEN_bp 6 /* Slave Fast Mode Plus Enable bit position. */ + +#define TWI_SSDAHOLD_gm 0x30 /* Slave SDA Hold Time Enable group mask. */ +#define TWI_SSDAHOLD_gp 4 /* Slave SDA Hold Time Enable group position. */ +#define TWI_SSDAHOLD0_bm (1<<4) /* Slave SDA Hold Time Enable bit 0 mask. */ +#define TWI_SSDAHOLD0_bp 4 /* Slave SDA Hold Time Enable bit 0 position. */ +#define TWI_SSDAHOLD1_bm (1<<5) /* Slave SDA Hold Time Enable bit 1 mask. */ +#define TWI_SSDAHOLD1_bp 5 /* Slave SDA Hold Time Enable bit 1 position. */ + +#define TWI_FMPEN_bm 0x08 /* FMPLUS Enable bit mask. */ +#define TWI_FMPEN_bp 3 /* FMPLUS Enable bit position. */ + +#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ +#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ +#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ +#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ +#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ +#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ + +#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ +#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ + +/* TWI_MASTER.CTRLA bit masks and bit positions */ +#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ +#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ + +#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ +#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ + +#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ +#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ + +#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ +#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ + +/* TWI_MASTER.CTRLB bit masks and bit positions */ +#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ + +#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ +#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ + +#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ + +#define TWI_MASTER_TTOUTEN_bm 0x10 /* Ttimeout Enable bit mask. */ +#define TWI_MASTER_TTOUTEN_bp 4 /* Ttimeout Enable bit position. */ + +#define TWI_MASTER_TSEXTEN_bm 0x20 /* Slave Extend Timeout Enable bit mask. */ +#define TWI_MASTER_TSEXTEN_bp 5 /* Slave Extend Timeout Enable bit position. */ + +#define TWI_MASTER_TMEXTEN_bm 0x40 /* Master Extend Timeout Enable bit mask. */ +#define TWI_MASTER_TMEXTEN_bp 6 /* Master Extend Timeout Enable bit position. */ + +#define TWI_MASTER_TOIE_bm 0x80 /* Timeout Interrupt Enable bit mask. */ +#define TWI_MASTER_TOIE_bp 7 /* Timeout Interrupt Enable bit position. */ + +/* TWI_MASTER.CTRLC bit masks and bit positions */ +#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ + +#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ +#define TWI_MASTER_CMD_gp 0 /* Command group position. */ +#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ +#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ + +/* TWI_MASTER.STATUS bit masks and bit positions */ +#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ + +#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ + +#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ + +#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ + +#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ + +#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ + +#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ +#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ +#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ + +/* TWI_SLAVE.CTRLA bit masks and bit positions */ +#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ +#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ + +#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ +#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ + +#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ +#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ + +#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ +#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ + +#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ +#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ + +#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ +#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ + +#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ + +/* TWI_SLAVE.CTRLB bit masks and bit positions */ +#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ + +#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ +#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ +#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ +#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ + +#define TWI_SLAVE_TTOUTEN_bm 0x10 /* Ttimeout Enable bit mask. */ +#define TWI_SLAVE_TTOUTEN_bp 4 /* Ttimeout Enable bit position. */ + +#define TWI_SLAVE_TOIE_bm 0x80 /* Timeout Interrupt Enable bit mask. */ +#define TWI_SLAVE_TOIE_bp 7 /* Timeout Interrupt Enable bit position. */ + +/* TWI_SLAVE.STATUS bit masks and bit positions */ +#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ + +#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ + +#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ + +#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ + +#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ +#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ + +#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ + +#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ + +#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ + +/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ +#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ +#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ + +#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ +#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ + +/* TWI_TIMEOUT.TOS bit masks and bit positions */ +#define TWI_TIMEOUT_TTOUTMIF_bm 0x01 /* Master Ttimeout Interrupt Flag bit mask. */ +#define TWI_TIMEOUT_TTOUTMIF_bp 0 /* Master Ttimeout Interrupt Flag bit position. */ + +#define TWI_TIMEOUT_TSEXTIF_bm 0x02 /* Slave Extend Interrupt Flag bit mask. */ +#define TWI_TIMEOUT_TSEXTIF_bp 1 /* Slave Extend Interrupt Flag bit position. */ + +#define TWI_TIMEOUT_TMEXTIF_bm 0x04 /* Master Extend Interrupt Flag bit mask. */ +#define TWI_TIMEOUT_TMEXTIF_bp 2 /* Master Extend Interrupt Flag bit position. */ + +#define TWI_TIMEOUT_TTOUTSIF_bm 0x10 /* Slave Ttimeout Interrupt Flag bit mask. */ +#define TWI_TIMEOUT_TTOUTSIF_bp 4 /* Slave Ttimeout Interrupt Flag bit position. */ + +/* TWI_TIMEOUT.TOCONF bit masks and bit positions */ +#define TWI_TIMEOUT_TTOUTMSEL_gm 0x07 /* Master Ttimeout Select group mask. */ +#define TWI_TIMEOUT_TTOUTMSEL_gp 0 /* Master Ttimeout Select group position. */ +#define TWI_TIMEOUT_TTOUTMSEL0_bm (1<<0) /* Master Ttimeout Select bit 0 mask. */ +#define TWI_TIMEOUT_TTOUTMSEL0_bp 0 /* Master Ttimeout Select bit 0 position. */ +#define TWI_TIMEOUT_TTOUTMSEL1_bm (1<<1) /* Master Ttimeout Select bit 1 mask. */ +#define TWI_TIMEOUT_TTOUTMSEL1_bp 1 /* Master Ttimeout Select bit 1 position. */ +#define TWI_TIMEOUT_TTOUTMSEL2_bm (1<<2) /* Master Ttimeout Select bit 2 mask. */ +#define TWI_TIMEOUT_TTOUTMSEL2_bp 2 /* Master Ttimeout Select bit 2 position. */ + +#define TWI_TIMEOUT_TMSEXTSEL_gm 0x18 /* Master/Slave Timeout Select group mask. */ +#define TWI_TIMEOUT_TMSEXTSEL_gp 3 /* Master/Slave Timeout Select group position. */ +#define TWI_TIMEOUT_TMSEXTSEL0_bm (1<<3) /* Master/Slave Timeout Select bit 0 mask. */ +#define TWI_TIMEOUT_TMSEXTSEL0_bp 3 /* Master/Slave Timeout Select bit 0 position. */ +#define TWI_TIMEOUT_TMSEXTSEL1_bm (1<<4) /* Master/Slave Timeout Select bit 1 mask. */ +#define TWI_TIMEOUT_TMSEXTSEL1_bp 4 /* Master/Slave Timeout Select bit 1 position. */ + +#define TWI_TIMEOUT_TTOUTSSEL_gm 0xE0 /* Slave Ttimeout Select group mask. */ +#define TWI_TIMEOUT_TTOUTSSEL_gp 5 /* Slave Ttimeout Select group position. */ +#define TWI_TIMEOUT_TTOUTSSEL0_bm (1<<5) /* Slave Ttimeout Select bit 0 mask. */ +#define TWI_TIMEOUT_TTOUTSSEL0_bp 5 /* Slave Ttimeout Select bit 0 position. */ +#define TWI_TIMEOUT_TTOUTSSEL1_bm (1<<6) /* Slave Ttimeout Select bit 1 mask. */ +#define TWI_TIMEOUT_TTOUTSSEL1_bp 6 /* Slave Ttimeout Select bit 1 position. */ +#define TWI_TIMEOUT_TTOUTSSEL2_bm (1<<7) /* Slave Ttimeout Select bit 2 mask. */ +#define TWI_TIMEOUT_TTOUTSSEL2_bp 7 /* Slave Ttimeout Select bit 2 position. */ + +/* PORT - Port Configuration */ +/* PORT.INTCTRL bit masks and bit positions */ +#define PORT_INTLVL_gm 0x03 /* Port Interrupt Level group mask. */ +#define PORT_INTLVL_gp 0 /* Port Interrupt Level group position. */ +#define PORT_INTLVL0_bm (1<<0) /* Port Interrupt Level bit 0 mask. */ +#define PORT_INTLVL0_bp 0 /* Port Interrupt Level bit 0 position. */ +#define PORT_INTLVL1_bm (1<<1) /* Port Interrupt Level bit 1 mask. */ +#define PORT_INTLVL1_bp 1 /* Port Interrupt Level bit 1 position. */ + +/* PORT.INTFLAGS bit masks and bit positions */ +#define PORT_INT7IF_bm 0x80 /* Pin 7 Interrupt Flag bit mask. */ +#define PORT_INT7IF_bp 7 /* Pin 7 Interrupt Flag bit position. */ + +#define PORT_INT6IF_bm 0x40 /* Pin 6 Interrupt Flag bit mask. */ +#define PORT_INT6IF_bp 6 /* Pin 6 Interrupt Flag bit position. */ + +#define PORT_INT5IF_bm 0x20 /* Pin 5 Interrupt Flag bit mask. */ +#define PORT_INT5IF_bp 5 /* Pin 5 Interrupt Flag bit position. */ + +#define PORT_INT4IF_bm 0x10 /* Pin 4 Interrupt Flag bit mask. */ +#define PORT_INT4IF_bp 4 /* Pin 4 Interrupt Flag bit position. */ + +#define PORT_INT3IF_bm 0x08 /* Pin 3 Interrupt Flag bit mask. */ +#define PORT_INT3IF_bp 3 /* Pin 3 Interrupt Flag bit position. */ + +#define PORT_INT2IF_bm 0x04 /* Pin 2 Interrupt Flag bit mask. */ +#define PORT_INT2IF_bp 2 /* Pin 2 Interrupt Flag bit position. */ + +#define PORT_INT1IF_bm 0x02 /* Pin 1 Interrupt Flag bit mask. */ +#define PORT_INT1IF_bp 1 /* Pin 1 Interrupt Flag bit position. */ + +#define PORT_INT0IF_bm 0x01 /* Pin 0 Interrupt Flag bit mask. */ +#define PORT_INT0IF_bp 0 /* Pin 0 Interrupt Flag bit position. */ + +/* PORT.REMAP bit masks and bit positions */ +#define PORT_USART0_bm 0x10 /* Usart0 bit mask. */ +#define PORT_USART0_bp 4 /* Usart0 bit position. */ + +#define PORT_TC4D_bm 0x08 /* Timer/Counter 4 Output Compare D bit mask. */ +#define PORT_TC4D_bp 3 /* Timer/Counter 4 Output Compare D bit position. */ + +#define PORT_TC4C_bm 0x04 /* Timer/Counter 4 Output Compare C bit mask. */ +#define PORT_TC4C_bp 2 /* Timer/Counter 4 Output Compare C bit position. */ + +#define PORT_TC4B_bm 0x02 /* Timer/Counter 4 Output Compare B bit mask. */ +#define PORT_TC4B_bp 1 /* Timer/Counter 4 Output Compare B bit position. */ + +#define PORT_TC4A_bm 0x01 /* Timer/Counter 4 Output Compare A bit mask. */ +#define PORT_TC4A_bp 0 /* Timer/Counter 4 Output Compare A bit position. */ + +/* PORT.PIN0CTRL bit masks and bit positions */ +#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ +#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ + +#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ +#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ +#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ +#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ +#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ +#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ +#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ +#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ + +#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ + +/* PORT.PIN1CTRL bit masks and bit positions */ +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN2CTRL bit masks and bit positions */ +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN3CTRL bit masks and bit positions */ +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN4CTRL bit masks and bit positions */ +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN5CTRL bit masks and bit positions */ +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN6CTRL bit masks and bit positions */ +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN7CTRL bit masks and bit positions */ +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* TC - 16-bit Timer/Counter With PWM */ +/* TC4.CTRLA bit masks and bit positions */ +#define TC4_SYNCHEN_bm 0x40 /* Synchronization Enabled bit mask. */ +#define TC4_SYNCHEN_bp 6 /* Synchronization Enabled bit position. */ + +#define TC4_EVSTART_bm 0x20 /* Start on Next Event bit mask. */ +#define TC4_EVSTART_bp 5 /* Start on Next Event bit position. */ + +#define TC4_UPSTOP_bm 0x10 /* Stop on Next Update bit mask. */ +#define TC4_UPSTOP_bp 4 /* Stop on Next Update bit position. */ + +#define TC4_CLKSEL_gm 0x0F /* Clock Select group mask. */ +#define TC4_CLKSEL_gp 0 /* Clock Select group position. */ +#define TC4_CLKSEL0_bm (1<<0) /* Clock Select bit 0 mask. */ +#define TC4_CLKSEL0_bp 0 /* Clock Select bit 0 position. */ +#define TC4_CLKSEL1_bm (1<<1) /* Clock Select bit 1 mask. */ +#define TC4_CLKSEL1_bp 1 /* Clock Select bit 1 position. */ +#define TC4_CLKSEL2_bm (1<<2) /* Clock Select bit 2 mask. */ +#define TC4_CLKSEL2_bp 2 /* Clock Select bit 2 position. */ +#define TC4_CLKSEL3_bm (1<<3) /* Clock Select bit 3 mask. */ +#define TC4_CLKSEL3_bp 3 /* Clock Select bit 3 position. */ + +/* TC4.CTRLB bit masks and bit positions */ +#define TC4_BYTEM_gm 0xC0 /* Byte Mode group mask. */ +#define TC4_BYTEM_gp 6 /* Byte Mode group position. */ +#define TC4_BYTEM0_bm (1<<6) /* Byte Mode bit 0 mask. */ +#define TC4_BYTEM0_bp 6 /* Byte Mode bit 0 position. */ +#define TC4_BYTEM1_bm (1<<7) /* Byte Mode bit 1 mask. */ +#define TC4_BYTEM1_bp 7 /* Byte Mode bit 1 position. */ + +#define TC4_CIRCEN_gm 0x30 /* Circular Buffer Enable group mask. */ +#define TC4_CIRCEN_gp 4 /* Circular Buffer Enable group position. */ +#define TC4_CIRCEN0_bm (1<<4) /* Circular Buffer Enable bit 0 mask. */ +#define TC4_CIRCEN0_bp 4 /* Circular Buffer Enable bit 0 position. */ +#define TC4_CIRCEN1_bm (1<<5) /* Circular Buffer Enable bit 1 mask. */ +#define TC4_CIRCEN1_bp 5 /* Circular Buffer Enable bit 1 position. */ + +#define TC4_WGMODE_gm 0x07 /* Waveform Generation Mode group mask. */ +#define TC4_WGMODE_gp 0 /* Waveform Generation Mode group position. */ +#define TC4_WGMODE0_bm (1<<0) /* Waveform Generation Mode bit 0 mask. */ +#define TC4_WGMODE0_bp 0 /* Waveform Generation Mode bit 0 position. */ +#define TC4_WGMODE1_bm (1<<1) /* Waveform Generation Mode bit 1 mask. */ +#define TC4_WGMODE1_bp 1 /* Waveform Generation Mode bit 1 position. */ +#define TC4_WGMODE2_bm (1<<2) /* Waveform Generation Mode bit 2 mask. */ +#define TC4_WGMODE2_bp 2 /* Waveform Generation Mode bit 2 position. */ + +/* TC4.CTRLC bit masks and bit positions */ +#define TC4_POLD_bm 0x80 /* Channel D Output Polarity bit mask. */ +#define TC4_POLD_bp 7 /* Channel D Output Polarity bit position. */ + +#define TC4_POLC_bm 0x40 /* Channel C Output Polarity bit mask. */ +#define TC4_POLC_bp 6 /* Channel C Output Polarity bit position. */ + +#define TC4_POLB_bm 0x20 /* Channel B Output Polarity bit mask. */ +#define TC4_POLB_bp 5 /* Channel B Output Polarity bit position. */ + +#define TC4_POLA_bm 0x10 /* Channel A Output Polarity bit mask. */ +#define TC4_POLA_bp 4 /* Channel A Output Polarity bit position. */ + +#define TC4_CMPD_bm 0x08 /* Channel D Compare Output Value bit mask. */ +#define TC4_CMPD_bp 3 /* Channel D Compare Output Value bit position. */ + +#define TC4_CMPC_bm 0x04 /* Channel C Compare Output Value bit mask. */ +#define TC4_CMPC_bp 2 /* Channel C Compare Output Value bit position. */ + +#define TC4_CMPB_bm 0x02 /* Channel B Compare Output Value bit mask. */ +#define TC4_CMPB_bp 1 /* Channel B Compare Output Value bit position. */ + +#define TC4_CMPA_bm 0x01 /* Channel A Compare Output Value bit mask. */ +#define TC4_CMPA_bp 0 /* Channel A Compare Output Value bit position. */ + +#define TC4_HCMPD_bm 0x80 /* High Channel D Compare Output Value bit mask. */ +#define TC4_HCMPD_bp 7 /* High Channel D Compare Output Value bit position. */ + +#define TC4_HCMPC_bm 0x40 /* High Channel C Compare Output Value bit mask. */ +#define TC4_HCMPC_bp 6 /* High Channel C Compare Output Value bit position. */ + +#define TC4_HCMPB_bm 0x20 /* High Channel B Compare Output Value bit mask. */ +#define TC4_HCMPB_bp 5 /* High Channel B Compare Output Value bit position. */ + +#define TC4_HCMPA_bm 0x10 /* High Channel A Compare Output Value bit mask. */ +#define TC4_HCMPA_bp 4 /* High Channel A Compare Output Value bit position. */ + +#define TC4_LCMPD_bm 0x08 /* Low Channel D Compare Output Value bit mask. */ +#define TC4_LCMPD_bp 3 /* Low Channel D Compare Output Value bit position. */ + +#define TC4_LCMPC_bm 0x04 /* Low Channel C Compare Output Value bit mask. */ +#define TC4_LCMPC_bp 2 /* Low Channel C Compare Output Value bit position. */ + +#define TC4_LCMPB_bm 0x02 /* Low Channel B Compare Output Value bit mask. */ +#define TC4_LCMPB_bp 1 /* Low Channel B Compare Output Value bit position. */ + +#define TC4_LCMPA_bm 0x01 /* Low Channel A Compare Output Value bit mask. */ +#define TC4_LCMPA_bp 0 /* Low Channel A Compare Output Value bit position. */ + +/* TC4.CTRLD bit masks and bit positions */ +#define TC4_EVACT_gm 0xE0 /* Event Action group mask. */ +#define TC4_EVACT_gp 5 /* Event Action group position. */ +#define TC4_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +#define TC4_EVACT0_bp 5 /* Event Action bit 0 position. */ +#define TC4_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +#define TC4_EVACT1_bp 6 /* Event Action bit 1 position. */ +#define TC4_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +#define TC4_EVACT2_bp 7 /* Event Action bit 2 position. */ + +#define TC4_EVDLY_bm 0x10 /* Event Delay bit mask. */ +#define TC4_EVDLY_bp 4 /* Event Delay bit position. */ + +#define TC4_EVSEL_gm 0x0F /* Event Source Select group mask. */ +#define TC4_EVSEL_gp 0 /* Event Source Select group position. */ +#define TC4_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +#define TC4_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +#define TC4_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +#define TC4_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +#define TC4_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +#define TC4_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +#define TC4_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +#define TC4_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ + +/* TC4.CTRLE bit masks and bit positions */ +#define TC4_CCDMODE_gm 0xC0 /* Channel D Compare or Capture Mode group mask. */ +#define TC4_CCDMODE_gp 6 /* Channel D Compare or Capture Mode group position. */ +#define TC4_CCDMODE0_bm (1<<6) /* Channel D Compare or Capture Mode bit 0 mask. */ +#define TC4_CCDMODE0_bp 6 /* Channel D Compare or Capture Mode bit 0 position. */ +#define TC4_CCDMODE1_bm (1<<7) /* Channel D Compare or Capture Mode bit 1 mask. */ +#define TC4_CCDMODE1_bp 7 /* Channel D Compare or Capture Mode bit 1 position. */ + +#define TC4_CCCMODE_gm 0x30 /* Channel C Compare or Capture Mode group mask. */ +#define TC4_CCCMODE_gp 4 /* Channel C Compare or Capture Mode group position. */ +#define TC4_CCCMODE0_bm (1<<4) /* Channel C Compare or Capture Mode bit 0 mask. */ +#define TC4_CCCMODE0_bp 4 /* Channel C Compare or Capture Mode bit 0 position. */ +#define TC4_CCCMODE1_bm (1<<5) /* Channel C Compare or Capture Mode bit 1 mask. */ +#define TC4_CCCMODE1_bp 5 /* Channel C Compare or Capture Mode bit 1 position. */ + +#define TC4_CCBMODE_gm 0x0C /* Channel B Compare or Capture Mode group mask. */ +#define TC4_CCBMODE_gp 2 /* Channel B Compare or Capture Mode group position. */ +#define TC4_CCBMODE0_bm (1<<2) /* Channel B Compare or Capture Mode bit 0 mask. */ +#define TC4_CCBMODE0_bp 2 /* Channel B Compare or Capture Mode bit 0 position. */ +#define TC4_CCBMODE1_bm (1<<3) /* Channel B Compare or Capture Mode bit 1 mask. */ +#define TC4_CCBMODE1_bp 3 /* Channel B Compare or Capture Mode bit 1 position. */ + +#define TC4_CCAMODE_gm 0x03 /* Channel A Compare or Capture Mode group mask. */ +#define TC4_CCAMODE_gp 0 /* Channel A Compare or Capture Mode group position. */ +#define TC4_CCAMODE0_bm (1<<0) /* Channel A Compare or Capture Mode bit 0 mask. */ +#define TC4_CCAMODE0_bp 0 /* Channel A Compare or Capture Mode bit 0 position. */ +#define TC4_CCAMODE1_bm (1<<1) /* Channel A Compare or Capture Mode bit 1 mask. */ +#define TC4_CCAMODE1_bp 1 /* Channel A Compare or Capture Mode bit 1 position. */ + +#define TC4_LCCDMODE_gm 0xC0 /* Channel Low D Compare or Capture Mode group mask. */ +#define TC4_LCCDMODE_gp 6 /* Channel Low D Compare or Capture Mode group position. */ +#define TC4_LCCDMODE0_bm (1<<6) /* Channel Low D Compare or Capture Mode bit 0 mask. */ +#define TC4_LCCDMODE0_bp 6 /* Channel Low D Compare or Capture Mode bit 0 position. */ +#define TC4_LCCDMODE1_bm (1<<7) /* Channel Low D Compare or Capture Mode bit 1 mask. */ +#define TC4_LCCDMODE1_bp 7 /* Channel Low D Compare or Capture Mode bit 1 position. */ + +#define TC4_LCCCMODE_gm 0x30 /* Channel Low C Compare or Capture Mode group mask. */ +#define TC4_LCCCMODE_gp 4 /* Channel Low C Compare or Capture Mode group position. */ +#define TC4_LCCCMODE0_bm (1<<4) /* Channel Low C Compare or Capture Mode bit 0 mask. */ +#define TC4_LCCCMODE0_bp 4 /* Channel Low C Compare or Capture Mode bit 0 position. */ +#define TC4_LCCCMODE1_bm (1<<5) /* Channel Low C Compare or Capture Mode bit 1 mask. */ +#define TC4_LCCCMODE1_bp 5 /* Channel Low C Compare or Capture Mode bit 1 position. */ + +#define TC4_LCCBMODE_gm 0x0C /* Channel Low B Compare or Capture Mode group mask. */ +#define TC4_LCCBMODE_gp 2 /* Channel Low B Compare or Capture Mode group position. */ +#define TC4_LCCBMODE0_bm (1<<2) /* Channel Low B Compare or Capture Mode bit 0 mask. */ +#define TC4_LCCBMODE0_bp 2 /* Channel Low B Compare or Capture Mode bit 0 position. */ +#define TC4_LCCBMODE1_bm (1<<3) /* Channel Low B Compare or Capture Mode bit 1 mask. */ +#define TC4_LCCBMODE1_bp 3 /* Channel Low B Compare or Capture Mode bit 1 position. */ + +#define TC4_LCCAMODE_gm 0x03 /* Channel Low A Compare or Capture Mode group mask. */ +#define TC4_LCCAMODE_gp 0 /* Channel Low A Compare or Capture Mode group position. */ +#define TC4_LCCAMODE0_bm (1<<0) /* Channel Low A Compare or Capture Mode bit 0 mask. */ +#define TC4_LCCAMODE0_bp 0 /* Channel Low A Compare or Capture Mode bit 0 position. */ +#define TC4_LCCAMODE1_bm (1<<1) /* Channel Low A Compare or Capture Mode bit 1 mask. */ +#define TC4_LCCAMODE1_bp 1 /* Channel Low A Compare or Capture Mode bit 1 position. */ + +/* TC4.CTRLF bit masks and bit positions */ +#define TC4_HCCDMODE_gm 0xC0 /* Channel High D Compare or Capture Mode group mask. */ +#define TC4_HCCDMODE_gp 6 /* Channel High D Compare or Capture Mode group position. */ +#define TC4_HCCDMODE0_bm (1<<6) /* Channel High D Compare or Capture Mode bit 0 mask. */ +#define TC4_HCCDMODE0_bp 6 /* Channel High D Compare or Capture Mode bit 0 position. */ +#define TC4_HCCDMODE1_bm (1<<7) /* Channel High D Compare or Capture Mode bit 1 mask. */ +#define TC4_HCCDMODE1_bp 7 /* Channel High D Compare or Capture Mode bit 1 position. */ + +#define TC4_HCCCMODE_gm 0x30 /* Channel High C Compare or Capture Mode group mask. */ +#define TC4_HCCCMODE_gp 4 /* Channel High C Compare or Capture Mode group position. */ +#define TC4_HCCCMODE0_bm (1<<4) /* Channel High C Compare or Capture Mode bit 0 mask. */ +#define TC4_HCCCMODE0_bp 4 /* Channel High C Compare or Capture Mode bit 0 position. */ +#define TC4_HCCCMODE1_bm (1<<5) /* Channel High C Compare or Capture Mode bit 1 mask. */ +#define TC4_HCCCMODE1_bp 5 /* Channel High C Compare or Capture Mode bit 1 position. */ + +#define TC4_HCCBMODE_gm 0x0C /* Channel High B Compare or Capture Mode group mask. */ +#define TC4_HCCBMODE_gp 2 /* Channel High B Compare or Capture Mode group position. */ +#define TC4_HCCBMODE0_bm (1<<2) /* Channel High B Compare or Capture Mode bit 0 mask. */ +#define TC4_HCCBMODE0_bp 2 /* Channel High B Compare or Capture Mode bit 0 position. */ +#define TC4_HCCBMODE1_bm (1<<3) /* Channel High B Compare or Capture Mode bit 1 mask. */ +#define TC4_HCCBMODE1_bp 3 /* Channel High B Compare or Capture Mode bit 1 position. */ + +#define TC4_HCCAMODE_gm 0x03 /* Channel High A Compare or Capture Mode group mask. */ +#define TC4_HCCAMODE_gp 0 /* Channel High A Compare or Capture Mode group position. */ +#define TC4_HCCAMODE0_bm (1<<0) /* Channel High A Compare or Capture Mode bit 0 mask. */ +#define TC4_HCCAMODE0_bp 0 /* Channel High A Compare or Capture Mode bit 0 position. */ +#define TC4_HCCAMODE1_bm (1<<1) /* Channel High A Compare or Capture Mode bit 1 mask. */ +#define TC4_HCCAMODE1_bp 1 /* Channel High A Compare or Capture Mode bit 1 position. */ + +/* TC4.INTCTRLA bit masks and bit positions */ +#define TC4_TRGINTLVL_gm 0x30 /* Timer Trigger Restart Interrupt Level group mask. */ +#define TC4_TRGINTLVL_gp 4 /* Timer Trigger Restart Interrupt Level group position. */ +#define TC4_TRGINTLVL0_bm (1<<4) /* Timer Trigger Restart Interrupt Level bit 0 mask. */ +#define TC4_TRGINTLVL0_bp 4 /* Timer Trigger Restart Interrupt Level bit 0 position. */ +#define TC4_TRGINTLVL1_bm (1<<5) /* Timer Trigger Restart Interrupt Level bit 1 mask. */ +#define TC4_TRGINTLVL1_bp 5 /* Timer Trigger Restart Interrupt Level bit 1 position. */ + +#define TC4_ERRINTLVL_gm 0x0C /* Timer Error Interrupt Level group mask. */ +#define TC4_ERRINTLVL_gp 2 /* Timer Error Interrupt Level group position. */ +#define TC4_ERRINTLVL0_bm (1<<2) /* Timer Error Interrupt Level bit 0 mask. */ +#define TC4_ERRINTLVL0_bp 2 /* Timer Error Interrupt Level bit 0 position. */ +#define TC4_ERRINTLVL1_bm (1<<3) /* Timer Error Interrupt Level bit 1 mask. */ +#define TC4_ERRINTLVL1_bp 3 /* Timer Error Interrupt Level bit 1 position. */ + +#define TC4_OVFINTLVL_gm 0x03 /* Timer Overflow/Underflow Interrupt Level group mask. */ +#define TC4_OVFINTLVL_gp 0 /* Timer Overflow/Underflow Interrupt Level group position. */ +#define TC4_OVFINTLVL0_bm (1<<0) /* Timer Overflow/Underflow Interrupt Level bit 0 mask. */ +#define TC4_OVFINTLVL0_bp 0 /* Timer Overflow/Underflow Interrupt Level bit 0 position. */ +#define TC4_OVFINTLVL1_bm (1<<1) /* Timer Overflow/Underflow Interrupt Level bit 1 mask. */ +#define TC4_OVFINTLVL1_bp 1 /* Timer Overflow/Underflow Interrupt Level bit 1 position. */ + +/* TC4.INTCTRLB bit masks and bit positions */ +#define TC4_CCDINTLVL_gm 0xC0 /* Channel D Compare or Capture Interrupt Level group mask. */ +#define TC4_CCDINTLVL_gp 6 /* Channel D Compare or Capture Interrupt Level group position. */ +#define TC4_CCDINTLVL0_bm (1<<6) /* Channel D Compare or Capture Interrupt Level bit 0 mask. */ +#define TC4_CCDINTLVL0_bp 6 /* Channel D Compare or Capture Interrupt Level bit 0 position. */ +#define TC4_CCDINTLVL1_bm (1<<7) /* Channel D Compare or Capture Interrupt Level bit 1 mask. */ +#define TC4_CCDINTLVL1_bp 7 /* Channel D Compare or Capture Interrupt Level bit 1 position. */ + +#define TC4_CCCINTLVL_gm 0x30 /* Channel C Compare or Capture Interrupt Level group mask. */ +#define TC4_CCCINTLVL_gp 4 /* Channel C Compare or Capture Interrupt Level group position. */ +#define TC4_CCCINTLVL0_bm (1<<4) /* Channel C Compare or Capture Interrupt Level bit 0 mask. */ +#define TC4_CCCINTLVL0_bp 4 /* Channel C Compare or Capture Interrupt Level bit 0 position. */ +#define TC4_CCCINTLVL1_bm (1<<5) /* Channel C Compare or Capture Interrupt Level bit 1 mask. */ +#define TC4_CCCINTLVL1_bp 5 /* Channel C Compare or Capture Interrupt Level bit 1 position. */ + +#define TC4_CCBINTLVL_gm 0x0C /* Channel B Compare or Capture Interrupt Level group mask. */ +#define TC4_CCBINTLVL_gp 2 /* Channel B Compare or Capture Interrupt Level group position. */ +#define TC4_CCBINTLVL0_bm (1<<2) /* Channel B Compare or Capture Interrupt Level bit 0 mask. */ +#define TC4_CCBINTLVL0_bp 2 /* Channel B Compare or Capture Interrupt Level bit 0 position. */ +#define TC4_CCBINTLVL1_bm (1<<3) /* Channel B Compare or Capture Interrupt Level bit 1 mask. */ +#define TC4_CCBINTLVL1_bp 3 /* Channel B Compare or Capture Interrupt Level bit 1 position. */ + +#define TC4_CCAINTLVL_gm 0x03 /* Channel A Compare or Capture Interrupt Level group mask. */ +#define TC4_CCAINTLVL_gp 0 /* Channel A Compare or Capture Interrupt Level group position. */ +#define TC4_CCAINTLVL0_bm (1<<0) /* Channel A Compare or Capture Interrupt Level bit 0 mask. */ +#define TC4_CCAINTLVL0_bp 0 /* Channel A Compare or Capture Interrupt Level bit 0 position. */ +#define TC4_CCAINTLVL1_bm (1<<1) /* Channel A Compare or Capture Interrupt Level bit 1 mask. */ +#define TC4_CCAINTLVL1_bp 1 /* Channel A Compare or Capture Interrupt Level bit 1 position. */ + +#define TC4_LCCDINTLVL_gm 0xC0 /* Channel Low D Compare or Capture Interrupt Level group mask. */ +#define TC4_LCCDINTLVL_gp 6 /* Channel Low D Compare or Capture Interrupt Level group position. */ +#define TC4_LCCDINTLVL0_bm (1<<6) /* Channel Low D Compare or Capture Interrupt Level bit 0 mask. */ +#define TC4_LCCDINTLVL0_bp 6 /* Channel Low D Compare or Capture Interrupt Level bit 0 position. */ +#define TC4_LCCDINTLVL1_bm (1<<7) /* Channel Low D Compare or Capture Interrupt Level bit 1 mask. */ +#define TC4_LCCDINTLVL1_bp 7 /* Channel Low D Compare or Capture Interrupt Level bit 1 position. */ + +#define TC4_LCCCINTLVL_gm 0x30 /* Channel Low C Compare or Capture Interrupt Level group mask. */ +#define TC4_LCCCINTLVL_gp 4 /* Channel Low C Compare or Capture Interrupt Level group position. */ +#define TC4_LCCCINTLVL0_bm (1<<4) /* Channel Low C Compare or Capture Interrupt Level bit 0 mask. */ +#define TC4_LCCCINTLVL0_bp 4 /* Channel Low C Compare or Capture Interrupt Level bit 0 position. */ +#define TC4_LCCCINTLVL1_bm (1<<5) /* Channel Low C Compare or Capture Interrupt Level bit 1 mask. */ +#define TC4_LCCCINTLVL1_bp 5 /* Channel Low C Compare or Capture Interrupt Level bit 1 position. */ + +#define TC4_LCCBINTLVL_gm 0x0C /* Channel Low B Compare or Capture Interrupt Level group mask. */ +#define TC4_LCCBINTLVL_gp 2 /* Channel Low B Compare or Capture Interrupt Level group position. */ +#define TC4_LCCBINTLVL0_bm (1<<2) /* Channel Low B Compare or Capture Interrupt Level bit 0 mask. */ +#define TC4_LCCBINTLVL0_bp 2 /* Channel Low B Compare or Capture Interrupt Level bit 0 position. */ +#define TC4_LCCBINTLVL1_bm (1<<3) /* Channel Low B Compare or Capture Interrupt Level bit 1 mask. */ +#define TC4_LCCBINTLVL1_bp 3 /* Channel Low B Compare or Capture Interrupt Level bit 1 position. */ + +#define TC4_LCCAINTLVL_gm 0x03 /* Channel Low A Compare or Capture Interrupt Level group mask. */ +#define TC4_LCCAINTLVL_gp 0 /* Channel Low A Compare or Capture Interrupt Level group position. */ +#define TC4_LCCAINTLVL0_bm (1<<0) /* Channel Low A Compare or Capture Interrupt Level bit 0 mask. */ +#define TC4_LCCAINTLVL0_bp 0 /* Channel Low A Compare or Capture Interrupt Level bit 0 position. */ +#define TC4_LCCAINTLVL1_bm (1<<1) /* Channel Low A Compare or Capture Interrupt Level bit 1 mask. */ +#define TC4_LCCAINTLVL1_bp 1 /* Channel Low A Compare or Capture Interrupt Level bit 1 position. */ + +/* TC4.CTRLGCLR bit masks and bit positions */ +#define TC4_STOP_bm 0x20 /* Timer/Counter Stop bit mask. */ +#define TC4_STOP_bp 5 /* Timer/Counter Stop bit position. */ + +#define TC4_CMD_gm 0x0C /* Command group mask. */ +#define TC4_CMD_gp 2 /* Command group position. */ +#define TC4_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC4_CMD0_bp 2 /* Command bit 0 position. */ +#define TC4_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC4_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC4_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TC4_LUPD_bp 1 /* Lock Update bit position. */ + +#define TC4_DIR_bm 0x01 /* Counter Direction bit mask. */ +#define TC4_DIR_bp 0 /* Counter Direction bit position. */ + +/* TC4.CTRLGSET bit masks and bit positions */ +/* TC4_STOP Predefined. */ +/* TC4_STOP Predefined. */ + +/* TC4_CMD Predefined. */ +/* TC4_CMD Predefined. */ + +/* TC4_LUPD Predefined. */ +/* TC4_LUPD Predefined. */ + +/* TC4_DIR Predefined. */ +/* TC4_DIR Predefined. */ + +/* TC4.CTRLHCLR bit masks and bit positions */ +#define TC4_CCDBV_bm 0x10 /* Channel D Compare or Capture Buffer Valid bit mask. */ +#define TC4_CCDBV_bp 4 /* Channel D Compare or Capture Buffer Valid bit position. */ + +#define TC4_CCCBV_bm 0x08 /* Channel C Compare or Capture Buffer Valid bit mask. */ +#define TC4_CCCBV_bp 3 /* Channel C Compare or Capture Buffer Valid bit position. */ + +#define TC4_CCBBV_bm 0x04 /* Channel B Compare or Capture Buffer Valid bit mask. */ +#define TC4_CCBBV_bp 2 /* Channel B Compare or Capture Buffer Valid bit position. */ + +#define TC4_CCABV_bm 0x02 /* Channel A Compare or Capture Buffer Valid bit mask. */ +#define TC4_CCABV_bp 1 /* Channel A Compare or Capture Buffer Valid bit position. */ + +#define TC4_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TC4_PERBV_bp 0 /* Period Buffer Valid bit position. */ + +#define TC4_LCCDBV_bm 0x10 /* Channel Low D Compare or Capture Buffer Valid bit mask. */ +#define TC4_LCCDBV_bp 4 /* Channel Low D Compare or Capture Buffer Valid bit position. */ + +#define TC4_LCCCBV_bm 0x08 /* Channel Low C Compare or Capture Buffer Valid bit mask. */ +#define TC4_LCCCBV_bp 3 /* Channel Low C Compare or Capture Buffer Valid bit position. */ + +#define TC4_LCCBBV_bm 0x04 /* Channel Low B Compare or Capture Buffer Valid bit mask. */ +#define TC4_LCCBBV_bp 2 /* Channel Low B Compare or Capture Buffer Valid bit position. */ + +#define TC4_LCCABV_bm 0x02 /* Channel Low A Compare or Capture Buffer Valid bit mask. */ +#define TC4_LCCABV_bp 1 /* Channel Low A Compare or Capture Buffer Valid bit position. */ + +#define TC4_LPERBV_bm 0x01 /* Period Low Buffer Valid bit mask. */ +#define TC4_LPERBV_bp 0 /* Period Low Buffer Valid bit position. */ + +/* TC4.CTRLHSET bit masks and bit positions */ +/* TC4_CCDBV Predefined. */ +/* TC4_CCDBV Predefined. */ + +/* TC4_CCCBV Predefined. */ +/* TC4_CCCBV Predefined. */ + +/* TC4_CCBBV Predefined. */ +/* TC4_CCBBV Predefined. */ + +/* TC4_CCABV Predefined. */ +/* TC4_CCABV Predefined. */ + +/* TC4_PERBV Predefined. */ +/* TC4_PERBV Predefined. */ + +/* TC4_LCCDBV Predefined. */ +/* TC4_LCCDBV Predefined. */ + +/* TC4_LCCCBV Predefined. */ +/* TC4_LCCCBV Predefined. */ + +/* TC4_LCCBBV Predefined. */ +/* TC4_LCCBBV Predefined. */ + +/* TC4_LCCABV Predefined. */ +/* TC4_LCCABV Predefined. */ + +/* TC4_LPERBV Predefined. */ +/* TC4_LPERBV Predefined. */ + +/* TC4.INTFLAGS bit masks and bit positions */ +#define TC4_CCDIF_bm 0x80 /* Channel D Compare or Capture Interrupt Flag bit mask. */ +#define TC4_CCDIF_bp 7 /* Channel D Compare or Capture Interrupt Flag bit position. */ + +#define TC4_CCCIF_bm 0x40 /* Channel C Compare or Capture Interrupt Flag bit mask. */ +#define TC4_CCCIF_bp 6 /* Channel C Compare or Capture Interrupt Flag bit position. */ + +#define TC4_CCBIF_bm 0x20 /* Channel B Compare or Capture Interrupt Flag bit mask. */ +#define TC4_CCBIF_bp 5 /* Channel B Compare or Capture Interrupt Flag bit position. */ + +#define TC4_CCAIF_bm 0x10 /* Channel A Compare or Capture Interrupt Flag bit mask. */ +#define TC4_CCAIF_bp 4 /* Channel A Compare or Capture Interrupt Flag bit position. */ + +#define TC4_TRGIF_bm 0x04 /* Trigger Restart Interrupt Flag bit mask. */ +#define TC4_TRGIF_bp 2 /* Trigger Restart Interrupt Flag bit position. */ + +#define TC4_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +#define TC4_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ + +#define TC4_OVFIF_bm 0x01 /* Overflow/Underflow Interrupt Flag bit mask. */ +#define TC4_OVFIF_bp 0 /* Overflow/Underflow Interrupt Flag bit position. */ + +#define TC4_LCCDIF_bm 0x80 /* Channel Low D Compare or Capture Interrupt Flag bit mask. */ +#define TC4_LCCDIF_bp 7 /* Channel Low D Compare or Capture Interrupt Flag bit position. */ + +#define TC4_LCCCIF_bm 0x40 /* Channel Low C Compare or Capture Interrupt Flag bit mask. */ +#define TC4_LCCCIF_bp 6 /* Channel Low C Compare or Capture Interrupt Flag bit position. */ + +#define TC4_LCCBIF_bm 0x20 /* Channel Low B Compare or Capture Interrupt Flag bit mask. */ +#define TC4_LCCBIF_bp 5 /* Channel Low B Compare or Capture Interrupt Flag bit position. */ + +#define TC4_LCCAIF_bm 0x10 /* Channel Low A Compare or Capture Interrupt Flag bit mask. */ +#define TC4_LCCAIF_bp 4 /* Channel Low A Compare or Capture Interrupt Flag bit position. */ + +/* TC5.CTRLA bit masks and bit positions */ +#define TC5_SYNCHEN_bm 0x40 /* Synchronization Enabled bit mask. */ +#define TC5_SYNCHEN_bp 6 /* Synchronization Enabled bit position. */ + +#define TC5_EVSTART_bm 0x20 /* Start on Next Event bit mask. */ +#define TC5_EVSTART_bp 5 /* Start on Next Event bit position. */ + +#define TC5_UPSTOP_bm 0x10 /* Stop on Next Update bit mask. */ +#define TC5_UPSTOP_bp 4 /* Stop on Next Update bit position. */ + +#define TC5_CLKSEL_gm 0x0F /* Clock Select group mask. */ +#define TC5_CLKSEL_gp 0 /* Clock Select group position. */ +#define TC5_CLKSEL0_bm (1<<0) /* Clock Select bit 0 mask. */ +#define TC5_CLKSEL0_bp 0 /* Clock Select bit 0 position. */ +#define TC5_CLKSEL1_bm (1<<1) /* Clock Select bit 1 mask. */ +#define TC5_CLKSEL1_bp 1 /* Clock Select bit 1 position. */ +#define TC5_CLKSEL2_bm (1<<2) /* Clock Select bit 2 mask. */ +#define TC5_CLKSEL2_bp 2 /* Clock Select bit 2 position. */ +#define TC5_CLKSEL3_bm (1<<3) /* Clock Select bit 3 mask. */ +#define TC5_CLKSEL3_bp 3 /* Clock Select bit 3 position. */ + +/* TC5.CTRLB bit masks and bit positions */ +#define TC5_BYTEM_gm 0xC0 /* Byte Mode group mask. */ +#define TC5_BYTEM_gp 6 /* Byte Mode group position. */ +#define TC5_BYTEM0_bm (1<<6) /* Byte Mode bit 0 mask. */ +#define TC5_BYTEM0_bp 6 /* Byte Mode bit 0 position. */ +#define TC5_BYTEM1_bm (1<<7) /* Byte Mode bit 1 mask. */ +#define TC5_BYTEM1_bp 7 /* Byte Mode bit 1 position. */ + +#define TC5_CIRCEN_gm 0x30 /* Circular Buffer Enable group mask. */ +#define TC5_CIRCEN_gp 4 /* Circular Buffer Enable group position. */ +#define TC5_CIRCEN0_bm (1<<4) /* Circular Buffer Enable bit 0 mask. */ +#define TC5_CIRCEN0_bp 4 /* Circular Buffer Enable bit 0 position. */ +#define TC5_CIRCEN1_bm (1<<5) /* Circular Buffer Enable bit 1 mask. */ +#define TC5_CIRCEN1_bp 5 /* Circular Buffer Enable bit 1 position. */ + +#define TC5_WGMODE_gm 0x07 /* Waveform Generation Mode group mask. */ +#define TC5_WGMODE_gp 0 /* Waveform Generation Mode group position. */ +#define TC5_WGMODE0_bm (1<<0) /* Waveform Generation Mode bit 0 mask. */ +#define TC5_WGMODE0_bp 0 /* Waveform Generation Mode bit 0 position. */ +#define TC5_WGMODE1_bm (1<<1) /* Waveform Generation Mode bit 1 mask. */ +#define TC5_WGMODE1_bp 1 /* Waveform Generation Mode bit 1 position. */ +#define TC5_WGMODE2_bm (1<<2) /* Waveform Generation Mode bit 2 mask. */ +#define TC5_WGMODE2_bp 2 /* Waveform Generation Mode bit 2 position. */ + +/* TC5.CTRLC bit masks and bit positions */ +#define TC5_POLB_bm 0x20 /* Channel B Output Polarity bit mask. */ +#define TC5_POLB_bp 5 /* Channel B Output Polarity bit position. */ + +#define TC5_POLA_bm 0x10 /* Channel A Output Polarity bit mask. */ +#define TC5_POLA_bp 4 /* Channel A Output Polarity bit position. */ + +#define TC5_CMPB_bm 0x02 /* Channel B Compare Output Value bit mask. */ +#define TC5_CMPB_bp 1 /* Channel B Compare Output Value bit position. */ + +#define TC5_CMPA_bm 0x01 /* Channel A Compare Output Value bit mask. */ +#define TC5_CMPA_bp 0 /* Channel A Compare Output Value bit position. */ + +#define TC5_HCMPB_bm 0x20 /* High Channel B Compare Output Value bit mask. */ +#define TC5_HCMPB_bp 5 /* High Channel B Compare Output Value bit position. */ + +#define TC5_HCMPA_bm 0x10 /* High Channel A Compare Output Value bit mask. */ +#define TC5_HCMPA_bp 4 /* High Channel A Compare Output Value bit position. */ + +#define TC5_LCMPB_bm 0x02 /* Low Channel B Compare Output Value bit mask. */ +#define TC5_LCMPB_bp 1 /* Low Channel B Compare Output Value bit position. */ + +#define TC5_LCMPA_bm 0x01 /* Low Channel A Compare Output Value bit mask. */ +#define TC5_LCMPA_bp 0 /* Low Channel A Compare Output Value bit position. */ + +/* TC5.CTRLD bit masks and bit positions */ +#define TC5_EVACT_gm 0xE0 /* Event Action group mask. */ +#define TC5_EVACT_gp 5 /* Event Action group position. */ +#define TC5_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +#define TC5_EVACT0_bp 5 /* Event Action bit 0 position. */ +#define TC5_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +#define TC5_EVACT1_bp 6 /* Event Action bit 1 position. */ +#define TC5_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +#define TC5_EVACT2_bp 7 /* Event Action bit 2 position. */ + +#define TC5_EVDLY_bm 0x10 /* Event Delay bit mask. */ +#define TC5_EVDLY_bp 4 /* Event Delay bit position. */ + +#define TC5_EVSEL_gm 0x0F /* Event Source Select group mask. */ +#define TC5_EVSEL_gp 0 /* Event Source Select group position. */ +#define TC5_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +#define TC5_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +#define TC5_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +#define TC5_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +#define TC5_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +#define TC5_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +#define TC5_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +#define TC5_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ + +/* TC5.CTRLE bit masks and bit positions */ +#define TC5_CCBMODE_gm 0x0C /* Channel B Compare or Capture Mode group mask. */ +#define TC5_CCBMODE_gp 2 /* Channel B Compare or Capture Mode group position. */ +#define TC5_CCBMODE0_bm (1<<2) /* Channel B Compare or Capture Mode bit 0 mask. */ +#define TC5_CCBMODE0_bp 2 /* Channel B Compare or Capture Mode bit 0 position. */ +#define TC5_CCBMODE1_bm (1<<3) /* Channel B Compare or Capture Mode bit 1 mask. */ +#define TC5_CCBMODE1_bp 3 /* Channel B Compare or Capture Mode bit 1 position. */ + +#define TC5_CCAMODE_gm 0x03 /* Channel A Compare or Capture Mode group mask. */ +#define TC5_CCAMODE_gp 0 /* Channel A Compare or Capture Mode group position. */ +#define TC5_CCAMODE0_bm (1<<0) /* Channel A Compare or Capture Mode bit 0 mask. */ +#define TC5_CCAMODE0_bp 0 /* Channel A Compare or Capture Mode bit 0 position. */ +#define TC5_CCAMODE1_bm (1<<1) /* Channel A Compare or Capture Mode bit 1 mask. */ +#define TC5_CCAMODE1_bp 1 /* Channel A Compare or Capture Mode bit 1 position. */ + +#define TC5_LCCBMODE_gm 0x0C /* Channel Low B Compare or Capture Mode group mask. */ +#define TC5_LCCBMODE_gp 2 /* Channel Low B Compare or Capture Mode group position. */ +#define TC5_LCCBMODE0_bm (1<<2) /* Channel Low B Compare or Capture Mode bit 0 mask. */ +#define TC5_LCCBMODE0_bp 2 /* Channel Low B Compare or Capture Mode bit 0 position. */ +#define TC5_LCCBMODE1_bm (1<<3) /* Channel Low B Compare or Capture Mode bit 1 mask. */ +#define TC5_LCCBMODE1_bp 3 /* Channel Low B Compare or Capture Mode bit 1 position. */ + +#define TC5_LCCAMODE_gm 0x03 /* Channel Low A Compare or Capture Mode group mask. */ +#define TC5_LCCAMODE_gp 0 /* Channel Low A Compare or Capture Mode group position. */ +#define TC5_LCCAMODE0_bm (1<<0) /* Channel Low A Compare or Capture Mode bit 0 mask. */ +#define TC5_LCCAMODE0_bp 0 /* Channel Low A Compare or Capture Mode bit 0 position. */ +#define TC5_LCCAMODE1_bm (1<<1) /* Channel Low A Compare or Capture Mode bit 1 mask. */ +#define TC5_LCCAMODE1_bp 1 /* Channel Low A Compare or Capture Mode bit 1 position. */ + +/* TC5.CTRLF bit masks and bit positions */ +#define TC5_HCCBMODE_gm 0x0C /* Channel High B Compare or Capture Mode group mask. */ +#define TC5_HCCBMODE_gp 2 /* Channel High B Compare or Capture Mode group position. */ +#define TC5_HCCBMODE0_bm (1<<2) /* Channel High B Compare or Capture Mode bit 0 mask. */ +#define TC5_HCCBMODE0_bp 2 /* Channel High B Compare or Capture Mode bit 0 position. */ +#define TC5_HCCBMODE1_bm (1<<3) /* Channel High B Compare or Capture Mode bit 1 mask. */ +#define TC5_HCCBMODE1_bp 3 /* Channel High B Compare or Capture Mode bit 1 position. */ + +#define TC5_HCCAMODE_gm 0x03 /* Channel High A Compare or Capture Mode group mask. */ +#define TC5_HCCAMODE_gp 0 /* Channel High A Compare or Capture Mode group position. */ +#define TC5_HCCAMODE0_bm (1<<0) /* Channel High A Compare or Capture Mode bit 0 mask. */ +#define TC5_HCCAMODE0_bp 0 /* Channel High A Compare or Capture Mode bit 0 position. */ +#define TC5_HCCAMODE1_bm (1<<1) /* Channel High A Compare or Capture Mode bit 1 mask. */ +#define TC5_HCCAMODE1_bp 1 /* Channel High A Compare or Capture Mode bit 1 position. */ + +/* TC5.INTCTRLA bit masks and bit positions */ +#define TC5_TRGINTLVL_gm 0x30 /* Timer Trigger Restart Interrupt Level group mask. */ +#define TC5_TRGINTLVL_gp 4 /* Timer Trigger Restart Interrupt Level group position. */ +#define TC5_TRGINTLVL0_bm (1<<4) /* Timer Trigger Restart Interrupt Level bit 0 mask. */ +#define TC5_TRGINTLVL0_bp 4 /* Timer Trigger Restart Interrupt Level bit 0 position. */ +#define TC5_TRGINTLVL1_bm (1<<5) /* Timer Trigger Restart Interrupt Level bit 1 mask. */ +#define TC5_TRGINTLVL1_bp 5 /* Timer Trigger Restart Interrupt Level bit 1 position. */ + +#define TC5_ERRINTLVL_gm 0x0C /* Timer Error Interrupt Level group mask. */ +#define TC5_ERRINTLVL_gp 2 /* Timer Error Interrupt Level group position. */ +#define TC5_ERRINTLVL0_bm (1<<2) /* Timer Error Interrupt Level bit 0 mask. */ +#define TC5_ERRINTLVL0_bp 2 /* Timer Error Interrupt Level bit 0 position. */ +#define TC5_ERRINTLVL1_bm (1<<3) /* Timer Error Interrupt Level bit 1 mask. */ +#define TC5_ERRINTLVL1_bp 3 /* Timer Error Interrupt Level bit 1 position. */ + +#define TC5_OVFINTLVL_gm 0x03 /* Timer Overflow/Underflow Interrupt Level group mask. */ +#define TC5_OVFINTLVL_gp 0 /* Timer Overflow/Underflow Interrupt Level group position. */ +#define TC5_OVFINTLVL0_bm (1<<0) /* Timer Overflow/Underflow Interrupt Level bit 0 mask. */ +#define TC5_OVFINTLVL0_bp 0 /* Timer Overflow/Underflow Interrupt Level bit 0 position. */ +#define TC5_OVFINTLVL1_bm (1<<1) /* Timer Overflow/Underflow Interrupt Level bit 1 mask. */ +#define TC5_OVFINTLVL1_bp 1 /* Timer Overflow/Underflow Interrupt Level bit 1 position. */ + +/* TC5.INTCTRLB bit masks and bit positions */ +#define TC5_CCBINTLVL_gm 0x0C /* Channel B Compare or Capture Interrupt Level group mask. */ +#define TC5_CCBINTLVL_gp 2 /* Channel B Compare or Capture Interrupt Level group position. */ +#define TC5_CCBINTLVL0_bm (1<<2) /* Channel B Compare or Capture Interrupt Level bit 0 mask. */ +#define TC5_CCBINTLVL0_bp 2 /* Channel B Compare or Capture Interrupt Level bit 0 position. */ +#define TC5_CCBINTLVL1_bm (1<<3) /* Channel B Compare or Capture Interrupt Level bit 1 mask. */ +#define TC5_CCBINTLVL1_bp 3 /* Channel B Compare or Capture Interrupt Level bit 1 position. */ + +#define TC5_CCAINTLVL_gm 0x03 /* Channel A Compare or Capture Interrupt Level group mask. */ +#define TC5_CCAINTLVL_gp 0 /* Channel A Compare or Capture Interrupt Level group position. */ +#define TC5_CCAINTLVL0_bm (1<<0) /* Channel A Compare or Capture Interrupt Level bit 0 mask. */ +#define TC5_CCAINTLVL0_bp 0 /* Channel A Compare or Capture Interrupt Level bit 0 position. */ +#define TC5_CCAINTLVL1_bm (1<<1) /* Channel A Compare or Capture Interrupt Level bit 1 mask. */ +#define TC5_CCAINTLVL1_bp 1 /* Channel A Compare or Capture Interrupt Level bit 1 position. */ + +#define TC5_LCCBINTLVL_gm 0x0C /* Channel Low B Compare or Capture Interrupt Level group mask. */ +#define TC5_LCCBINTLVL_gp 2 /* Channel Low B Compare or Capture Interrupt Level group position. */ +#define TC5_LCCBINTLVL0_bm (1<<2) /* Channel Low B Compare or Capture Interrupt Level bit 0 mask. */ +#define TC5_LCCBINTLVL0_bp 2 /* Channel Low B Compare or Capture Interrupt Level bit 0 position. */ +#define TC5_LCCBINTLVL1_bm (1<<3) /* Channel Low B Compare or Capture Interrupt Level bit 1 mask. */ +#define TC5_LCCBINTLVL1_bp 3 /* Channel Low B Compare or Capture Interrupt Level bit 1 position. */ + +#define TC5_LCCAINTLVL_gm 0x03 /* Channel Low A Compare or Capture Interrupt Level group mask. */ +#define TC5_LCCAINTLVL_gp 0 /* Channel Low A Compare or Capture Interrupt Level group position. */ +#define TC5_LCCAINTLVL0_bm (1<<0) /* Channel Low A Compare or Capture Interrupt Level bit 0 mask. */ +#define TC5_LCCAINTLVL0_bp 0 /* Channel Low A Compare or Capture Interrupt Level bit 0 position. */ +#define TC5_LCCAINTLVL1_bm (1<<1) /* Channel Low A Compare or Capture Interrupt Level bit 1 mask. */ +#define TC5_LCCAINTLVL1_bp 1 /* Channel Low A Compare or Capture Interrupt Level bit 1 position. */ + +/* TC5.CTRLGCLR bit masks and bit positions */ +#define TC5_STOP_bm 0x20 /* Timer/Counter Stop bit mask. */ +#define TC5_STOP_bp 5 /* Timer/Counter Stop bit position. */ + +#define TC5_CMD_gm 0x0C /* Command group mask. */ +#define TC5_CMD_gp 2 /* Command group position. */ +#define TC5_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC5_CMD0_bp 2 /* Command bit 0 position. */ +#define TC5_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC5_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC5_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TC5_LUPD_bp 1 /* Lock Update bit position. */ + +#define TC5_DIR_bm 0x01 /* Counter Direction bit mask. */ +#define TC5_DIR_bp 0 /* Counter Direction bit position. */ + +/* TC5.CTRLGSET bit masks and bit positions */ +/* TC5_STOP Predefined. */ +/* TC5_STOP Predefined. */ + +/* TC5_CMD Predefined. */ +/* TC5_CMD Predefined. */ + +/* TC5_LUPD Predefined. */ +/* TC5_LUPD Predefined. */ + +/* TC5_DIR Predefined. */ +/* TC5_DIR Predefined. */ + +/* TC5.CTRLHCLR bit masks and bit positions */ +#define TC5_CCBBV_bm 0x04 /* Channel B Compare or Capture Buffer Valid bit mask. */ +#define TC5_CCBBV_bp 2 /* Channel B Compare or Capture Buffer Valid bit position. */ + +#define TC5_CCABV_bm 0x02 /* Channel A Compare or Capture Buffer Valid bit mask. */ +#define TC5_CCABV_bp 1 /* Channel A Compare or Capture Buffer Valid bit position. */ + +#define TC5_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TC5_PERBV_bp 0 /* Period Buffer Valid bit position. */ + +#define TC5_LCCBBV_bm 0x04 /* Channel Low B Compare or Capture Buffer Valid bit mask. */ +#define TC5_LCCBBV_bp 2 /* Channel Low B Compare or Capture Buffer Valid bit position. */ + +#define TC5_LCCABV_bm 0x02 /* Channel Low A Compare or Capture Buffer Valid bit mask. */ +#define TC5_LCCABV_bp 1 /* Channel Low A Compare or Capture Buffer Valid bit position. */ + +#define TC5_LPERBV_bm 0x01 /* Period Low Buffer Valid bit mask. */ +#define TC5_LPERBV_bp 0 /* Period Low Buffer Valid bit position. */ + +/* TC5.CTRLHSET bit masks and bit positions */ +/* TC5_CCBBV Predefined. */ +/* TC5_CCBBV Predefined. */ + +/* TC5_CCABV Predefined. */ +/* TC5_CCABV Predefined. */ + +/* TC5_PERBV Predefined. */ +/* TC5_PERBV Predefined. */ + +/* TC5_LCCBBV Predefined. */ +/* TC5_LCCBBV Predefined. */ + +/* TC5_LCCABV Predefined. */ +/* TC5_LCCABV Predefined. */ + +/* TC5_LPERBV Predefined. */ +/* TC5_LPERBV Predefined. */ + +/* TC5.INTFLAGS bit masks and bit positions */ +#define TC5_CCBIF_bm 0x20 /* Channel B Compare or Capture Interrupt Flag bit mask. */ +#define TC5_CCBIF_bp 5 /* Channel B Compare or Capture Interrupt Flag bit position. */ + +#define TC5_CCAIF_bm 0x10 /* Channel A Compare or Capture Interrupt Flag bit mask. */ +#define TC5_CCAIF_bp 4 /* Channel A Compare or Capture Interrupt Flag bit position. */ + +#define TC5_TRGIF_bm 0x04 /* Trigger Restart Interrupt Flag bit mask. */ +#define TC5_TRGIF_bp 2 /* Trigger Restart Interrupt Flag bit position. */ + +#define TC5_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +#define TC5_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ + +#define TC5_OVFIF_bm 0x01 /* Overflow/Underflow Interrupt Flag bit mask. */ +#define TC5_OVFIF_bp 0 /* Overflow/Underflow Interrupt Flag bit position. */ + +#define TC5_LCCBIF_bm 0x20 /* Channel Low B Compare or Capture Interrupt Flag bit mask. */ +#define TC5_LCCBIF_bp 5 /* Channel Low B Compare or Capture Interrupt Flag bit position. */ + +#define TC5_LCCAIF_bm 0x10 /* Channel Low A Compare or Capture Interrupt Flag bit mask. */ +#define TC5_LCCAIF_bp 4 /* Channel Low A Compare or Capture Interrupt Flag bit position. */ + +/* FAULT - Fault Extension */ +/* FAULT.CTRLA bit masks and bit positions */ +#define FAULT_RAMP_gm 0xC0 /* Ramp Mode Selection group mask. */ +#define FAULT_RAMP_gp 6 /* Ramp Mode Selection group position. */ +#define FAULT_RAMP0_bm (1<<6) /* Ramp Mode Selection bit 0 mask. */ +#define FAULT_RAMP0_bp 6 /* Ramp Mode Selection bit 0 position. */ +#define FAULT_RAMP1_bm (1<<7) /* Ramp Mode Selection bit 1 mask. */ +#define FAULT_RAMP1_bp 7 /* Ramp Mode Selection bit 1 position. */ + +#define FAULT_FDDBD_bm 0x20 /* Fault on Debug Break Detection bit mask. */ +#define FAULT_FDDBD_bp 5 /* Fault on Debug Break Detection bit position. */ + +#define FAULT_PORTCTRL_bm 0x10 /* Port Control Mode bit mask. */ +#define FAULT_PORTCTRL_bp 4 /* Port Control Mode bit position. */ + +#define FAULT_FUSE_bm 0x08 /* Fuse State bit mask. */ +#define FAULT_FUSE_bp 3 /* Fuse State bit position. */ + +#define FAULT_FILTERE_bm 0x04 /* Fault E Digital Filter Selection bit mask. */ +#define FAULT_FILTERE_bp 2 /* Fault E Digital Filter Selection bit position. */ + +#define FAULT_SRCE_gm 0x03 /* Fault E Input selection group mask. */ +#define FAULT_SRCE_gp 0 /* Fault E Input selection group position. */ +#define FAULT_SRCE0_bm (1<<0) /* Fault E Input selection bit 0 mask. */ +#define FAULT_SRCE0_bp 0 /* Fault E Input selection bit 0 position. */ +#define FAULT_SRCE1_bm (1<<1) /* Fault E Input selection bit 1 mask. */ +#define FAULT_SRCE1_bp 1 /* Fault E Input selection bit 1 position. */ + +/* FAULT.CTRLB bit masks and bit positions */ +#define FAULT_SOFTA_bm 0x80 /* Fault A Software Mode bit mask. */ +#define FAULT_SOFTA_bp 7 /* Fault A Software Mode bit position. */ + +#define FAULT_HALTA_gm 0x60 /* Fault A Halt Action group mask. */ +#define FAULT_HALTA_gp 5 /* Fault A Halt Action group position. */ +#define FAULT_HALTA0_bm (1<<5) /* Fault A Halt Action bit 0 mask. */ +#define FAULT_HALTA0_bp 5 /* Fault A Halt Action bit 0 position. */ +#define FAULT_HALTA1_bm (1<<6) /* Fault A Halt Action bit 1 mask. */ +#define FAULT_HALTA1_bp 6 /* Fault A Halt Action bit 1 position. */ + +#define FAULT_RESTARTA_bm 0x10 /* Fault A Restart Action bit mask. */ +#define FAULT_RESTARTA_bp 4 /* Fault A Restart Action bit position. */ + +#define FAULT_KEEPA_bm 0x08 /* Fault A Keep Action bit mask. */ +#define FAULT_KEEPA_bp 3 /* Fault A Keep Action bit position. */ + +#define FAULT_SRCA_gm 0x03 /* Fault A Source Selection group mask. */ +#define FAULT_SRCA_gp 0 /* Fault A Source Selection group position. */ +#define FAULT_SRCA0_bm (1<<0) /* Fault A Source Selection bit 0 mask. */ +#define FAULT_SRCA0_bp 0 /* Fault A Source Selection bit 0 position. */ +#define FAULT_SRCA1_bm (1<<1) /* Fault A Source Selection bit 1 mask. */ +#define FAULT_SRCA1_bp 1 /* Fault A Source Selection bit 1 position. */ + +/* FAULT.CTRLC bit masks and bit positions */ +#define FAULT_CAPTA_bm 0x20 /* Fault A Capture bit mask. */ +#define FAULT_CAPTA_bp 5 /* Fault A Capture bit position. */ + +#define FAULT_FILTERA_bm 0x04 /* Fault A Digital Filter Selection bit mask. */ +#define FAULT_FILTERA_bp 2 /* Fault A Digital Filter Selection bit position. */ + +#define FAULT_BLANKA_bm 0x02 /* Fault A Blanking bit mask. */ +#define FAULT_BLANKA_bp 1 /* Fault A Blanking bit position. */ + +#define FAULT_QUALA_bm 0x01 /* Fault A Qualification bit mask. */ +#define FAULT_QUALA_bp 0 /* Fault A Qualification bit position. */ + +/* FAULT.CTRLD bit masks and bit positions */ +#define FAULT_SOFTB_bm 0x80 /* Fault B Software Mode bit mask. */ +#define FAULT_SOFTB_bp 7 /* Fault B Software Mode bit position. */ + +#define FAULT_HALTB_gm 0x60 /* Fault B Halt Action group mask. */ +#define FAULT_HALTB_gp 5 /* Fault B Halt Action group position. */ +#define FAULT_HALTB0_bm (1<<5) /* Fault B Halt Action bit 0 mask. */ +#define FAULT_HALTB0_bp 5 /* Fault B Halt Action bit 0 position. */ +#define FAULT_HALTB1_bm (1<<6) /* Fault B Halt Action bit 1 mask. */ +#define FAULT_HALTB1_bp 6 /* Fault B Halt Action bit 1 position. */ + +#define FAULT_RESTARTB_bm 0x10 /* Fault B Restart Action bit mask. */ +#define FAULT_RESTARTB_bp 4 /* Fault B Restart Action bit position. */ + +#define FAULT_KEEPB_bm 0x08 /* Fault B Keep Action bit mask. */ +#define FAULT_KEEPB_bp 3 /* Fault B Keep Action bit position. */ + +#define FAULT_SRCB_gm 0x03 /* Fault B Source Selection group mask. */ +#define FAULT_SRCB_gp 0 /* Fault B Source Selection group position. */ +#define FAULT_SRCB0_bm (1<<0) /* Fault B Source Selection bit 0 mask. */ +#define FAULT_SRCB0_bp 0 /* Fault B Source Selection bit 0 position. */ +#define FAULT_SRCB1_bm (1<<1) /* Fault B Source Selection bit 1 mask. */ +#define FAULT_SRCB1_bp 1 /* Fault B Source Selection bit 1 position. */ + +/* FAULT.CTRLE bit masks and bit positions */ +#define FAULT_CAPTB_bm 0x20 /* Fault B Capture bit mask. */ +#define FAULT_CAPTB_bp 5 /* Fault B Capture bit position. */ + +#define FAULT_FILTERB_bm 0x04 /* Fault B Digital Filter Selection bit mask. */ +#define FAULT_FILTERB_bp 2 /* Fault B Digital Filter Selection bit position. */ + +#define FAULT_BLANKB_bm 0x02 /* Fault B Blanking bit mask. */ +#define FAULT_BLANKB_bp 1 /* Fault B Blanking bit position. */ + +#define FAULT_QUALB_bm 0x01 /* Fault B Qualification bit mask. */ +#define FAULT_QUALB_bp 0 /* Fault B Qualification bit position. */ + +/* FAULT.STATUS bit masks and bit positions */ +#define FAULT_STATEB_bm 0x80 /* Fault B State bit mask. */ +#define FAULT_STATEB_bp 7 /* Fault B State bit position. */ + +#define FAULT_STATEA_bm 0x40 /* Fault A State bit mask. */ +#define FAULT_STATEA_bp 6 /* Fault A State bit position. */ + +#define FAULT_STATEE_bm 0x20 /* Fault E State bit mask. */ +#define FAULT_STATEE_bp 5 /* Fault E State bit position. */ + +#define FAULT_IDX_bm 0x08 /* Channel Index Flag bit mask. */ +#define FAULT_IDX_bp 3 /* Channel Index Flag bit position. */ + +#define FAULT_FAULTBIN_bm 0x04 /* Fault B Flag bit mask. */ +#define FAULT_FAULTBIN_bp 2 /* Fault B Flag bit position. */ + +#define FAULT_FAULTAIN_bm 0x02 /* Fault A Flag bit mask. */ +#define FAULT_FAULTAIN_bp 1 /* Fault A Flag bit position. */ + +#define FAULT_FAULTEIN_bm 0x01 /* Fault E Flag bit mask. */ +#define FAULT_FAULTEIN_bp 0 /* Fault E Flag bit position. */ + +/* FAULT.CTRLGCLR bit masks and bit positions */ +#define FAULT_HALTBCLR_bm 0x80 /* State B Clear bit mask. */ +#define FAULT_HALTBCLR_bp 7 /* State B Clear bit position. */ + +#define FAULT_HALTACLR_bm 0x40 /* State A Clear bit mask. */ +#define FAULT_HALTACLR_bp 6 /* State A Clear bit position. */ + +#define FAULT_STATEECLR_bm 0x20 /* State E Clear bit mask. */ +#define FAULT_STATEECLR_bp 5 /* State E Clear bit position. */ + +#define FAULT_FAULTB_bm 0x04 /* Fault B Flag bit mask. */ +#define FAULT_FAULTB_bp 2 /* Fault B Flag bit position. */ + +#define FAULT_FAULTA_bm 0x02 /* Fault A Flag bit mask. */ +#define FAULT_FAULTA_bp 1 /* Fault A Flag bit position. */ + +#define FAULT_FAULTE_bm 0x01 /* Fault E Flag bit mask. */ +#define FAULT_FAULTE_bp 0 /* Fault E Flag bit position. */ + +/* FAULT.CTRLGSET bit masks and bit positions */ +#define FAULT_FAULTBSW_bm 0x80 /* Software Fault B bit mask. */ +#define FAULT_FAULTBSW_bp 7 /* Software Fault B bit position. */ + +#define FAULT_FAULTASW_bm 0x40 /* Software Fault A bit mask. */ +#define FAULT_FAULTASW_bp 6 /* Software Fault A bit position. */ + +#define FAULT_FAULTESW_bm 0x20 /* Software Fault E bit mask. */ +#define FAULT_FAULTESW_bp 5 /* Software Fault E bit position. */ + +#define FAULT_IDXCMD_gm 0x18 /* Channel index Command group mask. */ +#define FAULT_IDXCMD_gp 3 /* Channel index Command group position. */ +#define FAULT_IDXCMD0_bm (1<<3) /* Channel index Command bit 0 mask. */ +#define FAULT_IDXCMD0_bp 3 /* Channel index Command bit 0 position. */ +#define FAULT_IDXCMD1_bm (1<<4) /* Channel index Command bit 1 mask. */ +#define FAULT_IDXCMD1_bp 4 /* Channel index Command bit 1 position. */ + +/* WEX - Waveform Extension */ +/* WEX.CTRL bit masks and bit positions */ +#define WEX_UPSEL_bm 0x80 /* Update Source Selection bit mask. */ +#define WEX_UPSEL_bp 7 /* Update Source Selection bit position. */ + +#define WEX_OTMX_gm 0x70 /* Output Matrix group mask. */ +#define WEX_OTMX_gp 4 /* Output Matrix group position. */ +#define WEX_OTMX0_bm (1<<4) /* Output Matrix bit 0 mask. */ +#define WEX_OTMX0_bp 4 /* Output Matrix bit 0 position. */ +#define WEX_OTMX1_bm (1<<5) /* Output Matrix bit 1 mask. */ +#define WEX_OTMX1_bp 5 /* Output Matrix bit 1 position. */ +#define WEX_OTMX2_bm (1<<6) /* Output Matrix bit 2 mask. */ +#define WEX_OTMX2_bp 6 /* Output Matrix bit 2 position. */ + +#define WEX_DTI3EN_bm 0x08 /* Dead-Time Insertion Generator 3 Enable bit mask. */ +#define WEX_DTI3EN_bp 3 /* Dead-Time Insertion Generator 3 Enable bit position. */ + +#define WEX_DTI2EN_bm 0x04 /* Dead-Time Insertion Generator 2 Enable bit mask. */ +#define WEX_DTI2EN_bp 2 /* Dead-Time Insertion Generator 2 Enable bit position. */ + +#define WEX_DTI1EN_bm 0x02 /* Dead-Time Insertion Generator 1 Enable bit mask. */ +#define WEX_DTI1EN_bp 1 /* Dead-Time Insertion Generator 1 Enable bit position. */ + +#define WEX_DTI0EN_bm 0x01 /* Dead-Time Insertion Generator 0 Enable bit mask. */ +#define WEX_DTI0EN_bp 0 /* Dead-Time Insertion Generator 0 Enable bit position. */ + +/* WEX.STATUSCLR bit masks and bit positions */ +#define WEX_SWAPBUF_bm 0x04 /* Swap Buffer Valid bit mask. */ +#define WEX_SWAPBUF_bp 2 /* Swap Buffer Valid bit position. */ + +#define WEX_PGVBUFV_bm 0x02 /* Pattern Generator Value Buffer Valid bit mask. */ +#define WEX_PGVBUFV_bp 1 /* Pattern Generator Value Buffer Valid bit position. */ + +#define WEX_PGOBUFV_bm 0x01 /* Pattern Generator Overwrite Buffer Valid bit mask. */ +#define WEX_PGOBUFV_bp 0 /* Pattern Generator Overwrite Buffer Valid bit position. */ + +/* WEX.STATUSSET bit masks and bit positions */ +/* WEX_SWAPBUF Predefined. */ +/* WEX_SWAPBUF Predefined. */ + +/* WEX_PGVBUFV Predefined. */ +/* WEX_PGVBUFV Predefined. */ + +/* WEX_PGOBUFV Predefined. */ +/* WEX_PGOBUFV Predefined. */ + +/* WEX.SWAP bit masks and bit positions */ +#define WEX_SWAP3_bm 0x08 /* Swap DTI output pair 3 bit mask. */ +#define WEX_SWAP3_bp 3 /* Swap DTI output pair 3 bit position. */ + +#define WEX_SWAP2_bm 0x04 /* Swap DTI output pair 2 bit mask. */ +#define WEX_SWAP2_bp 2 /* Swap DTI output pair 2 bit position. */ + +#define WEX_SWAP1_bm 0x02 /* Swap DTI output pair 1 bit mask. */ +#define WEX_SWAP1_bp 1 /* Swap DTI output pair 1 bit position. */ + +#define WEX_SWAP0_bm 0x01 /* Swap DTI output pair 0 bit mask. */ +#define WEX_SWAP0_bp 0 /* Swap DTI output pair 0 bit position. */ + +/* WEX.SWAPBUF bit masks and bit positions */ +#define WEX_SWAP3BUF_bm 0x08 /* Swap DTI output pair 3 bit mask. */ +#define WEX_SWAP3BUF_bp 3 /* Swap DTI output pair 3 bit position. */ + +#define WEX_SWAP2BUF_bm 0x04 /* Swap DTI output pair 2 bit mask. */ +#define WEX_SWAP2BUF_bp 2 /* Swap DTI output pair 2 bit position. */ + +#define WEX_SWAP1BUF_bm 0x02 /* Swap DTI output pair 1 bit mask. */ +#define WEX_SWAP1BUF_bp 1 /* Swap DTI output pair 1 bit position. */ + +#define WEX_SWAP0BUF_bm 0x01 /* Swap DTI output pair 0 bit mask. */ +#define WEX_SWAP0BUF_bp 0 /* Swap DTI output pair 0 bit position. */ + +/* HIRES - High-Resolution Extension */ +/* HIRES.CTRLA bit masks and bit positions */ +#define HIRES_HRPLUS_gm 0x0C /* High Resolution Plus group mask. */ +#define HIRES_HRPLUS_gp 2 /* High Resolution Plus group position. */ +#define HIRES_HRPLUS0_bm (1<<2) /* High Resolution Plus bit 0 mask. */ +#define HIRES_HRPLUS0_bp 2 /* High Resolution Plus bit 0 position. */ +#define HIRES_HRPLUS1_bm (1<<3) /* High Resolution Plus bit 1 mask. */ +#define HIRES_HRPLUS1_bp 3 /* High Resolution Plus bit 1 position. */ + +#define HIRES_HREN_gm 0x03 /* High Resolution Mode group mask. */ +#define HIRES_HREN_gp 0 /* High Resolution Mode group position. */ +#define HIRES_HREN0_bm (1<<0) /* High Resolution Mode bit 0 mask. */ +#define HIRES_HREN0_bp 0 /* High Resolution Mode bit 0 position. */ +#define HIRES_HREN1_bm (1<<1) /* High Resolution Mode bit 1 mask. */ +#define HIRES_HREN1_bp 1 /* High Resolution Mode bit 1 position. */ + +/* USART - Universal Asynchronous Receiver-Transmitter */ +/* USART.STATUS bit masks and bit positions */ +#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ +#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ + +#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ + +#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ + +#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ +#define USART_FERR_bp 4 /* Frame Error bit position. */ + +#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ +#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ + +#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ +#define USART_PERR_bp 2 /* Parity Error bit position. */ + +#define USART_RXSIF_bm 0x02 /* Receive Start Bit Interrupt Flag bit mask. */ +#define USART_RXSIF_bp 1 /* Receive Start Bit Interrupt Flag bit position. */ + +#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ +#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ + +#define USART_DRIF_bm 0x01 /* Data Reception Flag bit mask. */ +#define USART_DRIF_bp 0 /* Data Reception Flag bit position. */ + +/* USART.CTRLA bit masks and bit positions */ +#define USART_RXSIE_bm 0x80 /* Receive Start Interrupt Enable bit mask. */ +#define USART_RXSIE_bp 7 /* Receive Start Interrupt Enable bit position. */ + +#define USART_DRIE_bm 0x40 /* Data Reception Interrupt Enable bit mask. */ +#define USART_DRIE_bp 6 /* Data Reception Interrupt Enable bit position. */ + +#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ +#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ +#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ +#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ +#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ +#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ + +#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ +#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ +#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ +#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ +#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ +#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ + +#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ +#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ +#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ +#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ +#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ +#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ + +/* USART.CTRLB bit masks and bit positions */ +#define USART_ONEWIRE_bm 0x80 /* One Wire Mode bit mask. */ +#define USART_ONEWIRE_bp 7 /* One Wire Mode bit position. */ + +#define USART_SFDEN_bm 0x40 /* Start Frame Detection Enable bit mask. */ +#define USART_SFDEN_bp 6 /* Start Frame Detection Enable bit position. */ + +#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ +#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ + +#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ +#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ + +#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ +#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ + +#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ +#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ + +#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ +#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ + +/* USART.CTRLC bit masks and bit positions */ +#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +#define USART_CMODE_gp 6 /* Communication Mode group position. */ +#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ + +#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +#define USART_PMODE_gp 4 /* Parity Mode group position. */ +#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ + +#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ + +#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +#define USART_CHSIZE_gp 0 /* Character Size group position. */ +#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ + +/* USART.CTRLD bit masks and bit positions */ +#define USART_DECTYPE_gm 0x30 /* Receive Interrupt Level group mask. */ +#define USART_DECTYPE_gp 4 /* Receive Interrupt Level group position. */ +#define USART_DECTYPE0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ +#define USART_DECTYPE0_bp 4 /* Receive Interrupt Level bit 0 position. */ +#define USART_DECTYPE1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ +#define USART_DECTYPE1_bp 5 /* Receive Interrupt Level bit 1 position. */ + +#define USART_LUTACT_gm 0x0C /* Transmit Interrupt Level group mask. */ +#define USART_LUTACT_gp 2 /* Transmit Interrupt Level group position. */ +#define USART_LUTACT0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ +#define USART_LUTACT0_bp 2 /* Transmit Interrupt Level bit 0 position. */ +#define USART_LUTACT1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ +#define USART_LUTACT1_bp 3 /* Transmit Interrupt Level bit 1 position. */ + +#define USART_PECACT_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ +#define USART_PECACT_gp 0 /* Data Register Empty Interrupt Level group position. */ +#define USART_PECACT0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ +#define USART_PECACT0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ +#define USART_PECACT1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ +#define USART_PECACT1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ + +/* USART.BAUDCTRLA bit masks and bit positions */ +#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ +#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ +#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ +#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ +#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ +#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ +#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ +#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ +#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ +#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ +#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ +#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ +#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ +#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ +#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ +#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ +#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ +#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ + +/* USART.BAUDCTRLB bit masks and bit positions */ +#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ +#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ +#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ +#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ +#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ +#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ +#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ +#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ +#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ +#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ + +/* USART_BSEL Predefined. */ +/* USART_BSEL Predefined. */ + +/* SPI - Serial Peripheral Interface */ +/* SPI.CTRL bit masks and bit positions */ +#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ +#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ + +#define SPI_ENABLE_bm 0x40 /* Enable SPI Module bit mask. */ +#define SPI_ENABLE_bp 6 /* Enable SPI Module bit position. */ + +#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ +#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ + +#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ +#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ + +#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ +#define SPI_MODE_gp 2 /* SPI Mode group position. */ +#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ +#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ +#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ +#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ + +#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ +#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ +#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ +#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ +#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ +#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ + +/* SPI.INTCTRL bit masks and bit positions */ +#define SPI_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable (In Buffer Modes Only). bit mask. */ +#define SPI_RXCIE_bp 7 /* Receive Complete Interrupt Enable (In Buffer Modes Only). bit position. */ + +#define SPI_TXCIE_bm 0x40 /* Transmit Complete Interrupt Enable (In Buffer Modes Only). bit mask. */ +#define SPI_TXCIE_bp 6 /* Transmit Complete Interrupt Enable (In Buffer Modes Only). bit position. */ + +#define SPI_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable (In Buffer Modes Only). bit mask. */ +#define SPI_DREIE_bp 5 /* Data Register Empty Interrupt Enable (In Buffer Modes Only). bit position. */ + +#define SPI_SSIE_bm 0x10 /* Slave Select Trigger Interrupt Enable (In Buffer Modes Only). bit mask. */ +#define SPI_SSIE_bp 4 /* Slave Select Trigger Interrupt Enable (In Buffer Modes Only). bit position. */ + +#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ +#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ +#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ +#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ +#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ +#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ + +/* SPI.STATUS bit masks and bit positions */ +#define SPI_IF_bm 0x80 /* Interrupt Flag (In Standard Mode Only). bit mask. */ +#define SPI_IF_bp 7 /* Interrupt Flag (In Standard Mode Only). bit position. */ + +#define SPI_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag (In Buffer Modes Only). bit mask. */ +#define SPI_RXCIF_bp 7 /* Receive Complete Interrupt Flag (In Buffer Modes Only). bit position. */ + +#define SPI_WRCOL_bm 0x40 /* Write Collision Flag (In Standard Mode Only). bit mask. */ +#define SPI_WRCOL_bp 6 /* Write Collision Flag (In Standard Mode Only). bit position. */ + +#define SPI_TXCIF_bm 0x40 /* Transmit Complete Interrupt Flag (In Buffer Modes Only). bit mask. */ +#define SPI_TXCIF_bp 6 /* Transmit Complete Interrupt Flag (In Buffer Modes Only). bit position. */ + +#define SPI_DREIF_bm 0x20 /* Data Register Empty Interrupt Flag (In Buffer Modes Only). bit mask. */ +#define SPI_DREIF_bp 5 /* Data Register Empty Interrupt Flag (In Buffer Modes Only). bit position. */ + +#define SPI_SSIF_bm 0x10 /* Slave Select Trigger Interrupt Flag (In Buffer Modes Only). bit mask. */ +#define SPI_SSIF_bp 4 /* Slave Select Trigger Interrupt Flag (In Buffer Modes Only). bit position. */ + +#define SPI_BUFOVF_bm 0x01 /* Buffer Overflow (In Buffer Modes Only). bit mask. */ +#define SPI_BUFOVF_bp 0 /* Buffer Overflow (In Buffer Modes Only). bit position. */ + +/* SPI.CTRLB bit masks and bit positions */ +#define SPI_BUFMODE_gm 0xC0 /* Buffer Modes group mask. */ +#define SPI_BUFMODE_gp 6 /* Buffer Modes group position. */ +#define SPI_BUFMODE0_bm (1<<6) /* Buffer Modes bit 0 mask. */ +#define SPI_BUFMODE0_bp 6 /* Buffer Modes bit 0 position. */ +#define SPI_BUFMODE1_bm (1<<7) /* Buffer Modes bit 1 mask. */ +#define SPI_BUFMODE1_bp 7 /* Buffer Modes bit 1 position. */ + +#define SPI_SSD_bm 0x04 /* Slave Select Disable bit mask. */ +#define SPI_SSD_bp 2 /* Slave Select Disable bit position. */ + +/* IRCOM - IR Communication Module */ +/* IRCOM.CTRL bit masks and bit positions */ +#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ +#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ +#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ +#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ +#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ +#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ +#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ +#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ +#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ +#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ + +/* FUSE - Fuses and Lockbits */ +/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ +#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ + +#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ +#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ +#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ + +/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ +#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ +#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ + +#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ +#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ +#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ + +/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ +#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ +#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ + +#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ +#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ +#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ +#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ +#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ +#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ + +/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ +#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ +#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ + +#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ +#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ +#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ +#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ +#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ +#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ + +#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ +#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ + +/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ +#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ +#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ +#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ +#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ +#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ +#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ + +#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ +#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ + +#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ +#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ +#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ +#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ +#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ +#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ +#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ +#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ + +/* NVM_FUSES.FUSEBYTE6 bit masks and bit positions */ +#define NVM_FUSES_FDACT5_bm 0x80 /* Fault Dectection Action on TC5 bit mask. */ +#define NVM_FUSES_FDACT5_bp 7 /* Fault Dectection Action on TC5 bit position. */ + +#define NVM_FUSES_FDACT4_bm 0x40 /* Fault Dectection Action on TC4 bit mask. */ +#define NVM_FUSES_FDACT4_bp 6 /* Fault Dectection Action on TC4 bit position. */ + +#define NVM_FUSES_VALUE_gm 0x3F /* Port Pin Value group mask. */ +#define NVM_FUSES_VALUE_gp 0 /* Port Pin Value group position. */ +#define NVM_FUSES_VALUE0_bm (1<<0) /* Port Pin Value bit 0 mask. */ +#define NVM_FUSES_VALUE0_bp 0 /* Port Pin Value bit 0 position. */ +#define NVM_FUSES_VALUE1_bm (1<<1) /* Port Pin Value bit 1 mask. */ +#define NVM_FUSES_VALUE1_bp 1 /* Port Pin Value bit 1 position. */ +#define NVM_FUSES_VALUE2_bm (1<<2) /* Port Pin Value bit 2 mask. */ +#define NVM_FUSES_VALUE2_bp 2 /* Port Pin Value bit 2 position. */ +#define NVM_FUSES_VALUE3_bm (1<<3) /* Port Pin Value bit 3 mask. */ +#define NVM_FUSES_VALUE3_bp 3 /* Port Pin Value bit 3 position. */ +#define NVM_FUSES_VALUE4_bm (1<<4) /* Port Pin Value bit 4 mask. */ +#define NVM_FUSES_VALUE4_bp 4 /* Port Pin Value bit 4 position. */ +#define NVM_FUSES_VALUE5_bm (1<<5) /* Port Pin Value bit 5 mask. */ +#define NVM_FUSES_VALUE5_bp 5 /* Port Pin Value bit 5 position. */ + + + +// Generic Port Pins + +#define PIN0_bm 0x01 +#define PIN0_bp 0 +#define PIN1_bm 0x02 +#define PIN1_bp 1 +#define PIN2_bm 0x04 +#define PIN2_bp 2 +#define PIN3_bm 0x08 +#define PIN3_bp 3 +#define PIN4_bm 0x10 +#define PIN4_bp 4 +#define PIN5_bm 0x20 +#define PIN5_bp 5 +#define PIN6_bm 0x40 +#define PIN6_bp 6 +#define PIN7_bm 0x80 +#define PIN7_bp 7 + +/* ========== Interrupt Vector Definitions ========== */ +/* Vector 0 is the reset vector */ + +/* OSC interrupt vectors */ +#define OSC_OSCF_vect_num 1 +#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ + +/* PORTR interrupt vectors */ +#define PORTR_INT_vect_num 2 +#define PORTR_INT_vect _VECTOR(2) /* External Interrupt */ + +/* EDMA interrupt vectors */ +#define EDMA_CH0_vect_num 3 +#define EDMA_CH0_vect _VECTOR(3) /* EDMA Channel 0 Interrupt */ +#define EDMA_CH1_vect_num 4 +#define EDMA_CH1_vect _VECTOR(4) /* EDMA Channel 1 Interrupt */ +#define EDMA_CH2_vect_num 5 +#define EDMA_CH2_vect _VECTOR(5) /* EDMA Channel 2 Interrupt */ +#define EDMA_CH3_vect_num 6 +#define EDMA_CH3_vect _VECTOR(6) /* EDMA Channel 3 Interrupt */ + +/* RTC interrupt vectors */ +#define RTC_OVF_vect_num 7 +#define RTC_OVF_vect _VECTOR(7) /* Overflow Interrupt */ +#define RTC_COMP_vect_num 8 +#define RTC_COMP_vect _VECTOR(8) /* Compare Interrupt */ + +/* PORTC interrupt vectors */ +#define PORTC_INT_vect_num 9 +#define PORTC_INT_vect _VECTOR(9) /* External Interrupt */ + +/* TWIC interrupt vectors */ +#define TWIC_TWIS_vect_num 10 +#define TWIC_TWIS_vect _VECTOR(10) /* TWI Slave Interrupt */ +#define TWIC_TWIM_vect_num 11 +#define TWIC_TWIM_vect _VECTOR(11) /* TWI Master Interrupt */ + +/* TCC4 interrupt vectors */ +#define TCC4_OVF_vect_num 12 +#define TCC4_OVF_vect _VECTOR(12) /* Overflow Interrupt */ +#define TCC4_ERR_vect_num 13 +#define TCC4_ERR_vect _VECTOR(13) /* Error Interrupt */ +#define TCC4_CCA_vect_num 14 +#define TCC4_CCA_vect _VECTOR(14) /* Channel A Compare or Capture Interrupt */ +#define TCC4_CCB_vect_num 15 +#define TCC4_CCB_vect _VECTOR(15) /* Channel B Compare or Capture Interrupt */ +#define TCC4_CCC_vect_num 16 +#define TCC4_CCC_vect _VECTOR(16) /* Channel C Compare or Capture Interrupt */ +#define TCC4_CCD_vect_num 17 +#define TCC4_CCD_vect _VECTOR(17) /* Channel D Compare or Capture Interrupt */ + +/* TCC5 interrupt vectors */ +#define TCC5_OVF_vect_num 18 +#define TCC5_OVF_vect _VECTOR(18) /* Overflow Interrupt */ +#define TCC5_ERR_vect_num 19 +#define TCC5_ERR_vect _VECTOR(19) /* Error Interrupt */ +#define TCC5_CCA_vect_num 20 +#define TCC5_CCA_vect _VECTOR(20) /* Channel A Compare or Capture Interrupt */ +#define TCC5_CCB_vect_num 21 +#define TCC5_CCB_vect _VECTOR(21) /* Channel B Compare or Capture Interrupt */ + +/* SPIC interrupt vectors */ +#define SPIC_INT_vect_num 22 +#define SPIC_INT_vect _VECTOR(22) /* SPI Interrupt */ + +/* USARTC0 interrupt vectors */ +#define USARTC0_RXC_vect_num 23 +#define USARTC0_RXC_vect _VECTOR(23) /* Reception Complete Interrupt */ +#define USARTC0_DRE_vect_num 24 +#define USARTC0_DRE_vect _VECTOR(24) /* Data Register Empty Interrupt */ +#define USARTC0_TXC_vect_num 25 +#define USARTC0_TXC_vect _VECTOR(25) /* Transmission Complete Interrupt */ + +/* NVM interrupt vectors */ +#define NVM_EE_vect_num 26 +#define NVM_EE_vect _VECTOR(26) /* EE Interrupt */ +#define NVM_SPM_vect_num 27 +#define NVM_SPM_vect _VECTOR(27) /* SPM Interrupt */ + +/* XCL interrupt vectors */ +#define XCL_UNF_vect_num 28 +#define XCL_UNF_vect _VECTOR(28) /* Timer/Counter Underflow Interrupt */ +#define XCL_CC_vect_num 29 +#define XCL_CC_vect _VECTOR(29) /* Timer/Counter Compare or Capture Interrupt */ + +/* PORTA interrupt vectors */ +#define PORTA_INT_vect_num 30 +#define PORTA_INT_vect _VECTOR(30) /* External Interrupt */ + +/* ACA interrupt vectors */ +#define ACA_AC0_vect_num 31 +#define ACA_AC0_vect _VECTOR(31) /* AC0 Interrupt */ +#define ACA_AC1_vect_num 32 +#define ACA_AC1_vect _VECTOR(32) /* AC1 Interrupt */ +#define ACA_ACW_vect_num 33 +#define ACA_ACW_vect _VECTOR(33) /* ACW Window Mode Interrupt */ + +/* ADCA interrupt vectors */ +#define ADCA_CH0_vect_num 34 +#define ADCA_CH0_vect _VECTOR(34) /* ADC Channel Interrupt */ + +/* PORTD interrupt vectors */ +#define PORTD_INT_vect_num 35 +#define PORTD_INT_vect _VECTOR(35) /* External Interrupt */ + +/* TCD5 interrupt vectors */ +#define TCD5_OVF_vect_num 36 +#define TCD5_OVF_vect _VECTOR(36) /* Overflow Interrupt */ +#define TCD5_ERR_vect_num 37 +#define TCD5_ERR_vect _VECTOR(37) /* Error Interrupt */ +#define TCD5_CCA_vect_num 38 +#define TCD5_CCA_vect _VECTOR(38) /* Channel A Compare or Capture Interrupt */ +#define TCD5_CCB_vect_num 39 +#define TCD5_CCB_vect _VECTOR(39) /* Channel B Compare or Capture Interrupt */ + +/* USARTD0 interrupt vectors */ +#define USARTD0_RXC_vect_num 40 +#define USARTD0_RXC_vect _VECTOR(40) /* Reception Complete Interrupt */ +#define USARTD0_DRE_vect_num 41 +#define USARTD0_DRE_vect _VECTOR(41) /* Data Register Empty Interrupt */ +#define USARTD0_TXC_vect_num 42 +#define USARTD0_TXC_vect _VECTOR(42) /* Transmission Complete Interrupt */ + +#define _VECTOR_SIZE 4 /* Size of individual vector. */ +#define _VECTORS_SIZE (43 * _VECTOR_SIZE) + + +/* ========== Constants ========== */ + +#define PROGMEM_START (0x0000) +#define PROGMEM_SIZE (10240) +#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) + +#define APP_SECTION_START (0x0000) +#define APP_SECTION_SIZE (8192) +#define APP_SECTION_PAGE_SIZE (128) +#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) + +#define APPTABLE_SECTION_START (0x1800) +#define APPTABLE_SECTION_SIZE (2048) +#define APPTABLE_SECTION_PAGE_SIZE (128) +#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) + +#define BOOT_SECTION_START (0x2000) +#define BOOT_SECTION_SIZE (2048) +#define BOOT_SECTION_PAGE_SIZE (128) +#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) + +#define DATAMEM_START (0x0000) +#define DATAMEM_SIZE (9216) +#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) + +#define IO_START (0x0000) +#define IO_SIZE (4096) +#define IO_PAGE_SIZE (0) +#define IO_END (IO_START + IO_SIZE - 1) + +#define MAPPED_EEPROM_START (0x1000) +#define MAPPED_EEPROM_SIZE (512) +#define MAPPED_EEPROM_PAGE_SIZE (0) +#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) + +#define INTERNAL_SRAM_START (0x2000) +#define INTERNAL_SRAM_SIZE (1024) +#define INTERNAL_SRAM_PAGE_SIZE (0) +#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) + +#define EEPROM_START (0x0000) +#define EEPROM_SIZE (512) +#define EEPROM_PAGE_SIZE (32) +#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) + +#define SIGNATURES_START (0x0000) +#define SIGNATURES_SIZE (3) +#define SIGNATURES_PAGE_SIZE (0) +#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) + +#define FUSES_START (0x0000) +#define FUSES_SIZE (7) +#define FUSES_PAGE_SIZE (0) +#define FUSES_END (FUSES_START + FUSES_SIZE - 1) + +#define LOCKBITS_START (0x0000) +#define LOCKBITS_SIZE (1) +#define LOCKBITS_PAGE_SIZE (0) +#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) + +#define USER_SIGNATURES_START (0x0000) +#define USER_SIGNATURES_SIZE (128) +#define USER_SIGNATURES_PAGE_SIZE (128) +#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) + +#define PROD_SIGNATURES_START (0x0000) +#define PROD_SIGNATURES_SIZE (54) +#define PROD_SIGNATURES_PAGE_SIZE (128) +#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) + +#define FLASHSTART PROGMEM_START +#define FLASHEND PROGMEM_END +#define SPM_PAGESIZE 128 +#define RAMSTART INTERNAL_SRAM_START +#define RAMSIZE INTERNAL_SRAM_SIZE +#define RAMEND INTERNAL_SRAM_END +#define E2END EEPROM_END +#define E2PAGESIZE EEPROM_PAGE_SIZE + + +/* ========== Fuses ========== */ +#define FUSE_MEMORY_SIZE 7 + +/* Fuse Byte 0 Reserved */ + +/* Fuse Byte 1 */ +#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ +#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ +#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ +#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ +#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +#define FUSE1_DEFAULT (0xFF) + +/* Fuse Byte 2 */ +#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ +#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ +#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ +#define FUSE2_DEFAULT (0xFF) + +/* Fuse Byte 3 Reserved */ + +/* Fuse Byte 4 */ +#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ +#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ +#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ +#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ +#define FUSE4_DEFAULT (0xFF) + +/* Fuse Byte 5 */ +#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ +#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ +#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ +#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ +#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ +#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ +#define FUSE5_DEFAULT (0xFF) + +/* Fuse Byte 6 */ +#define FUSE_VALUE0 (unsigned char)~_BV(0) /* Port Pin Value Bit 0 */ +#define FUSE_VALUE1 (unsigned char)~_BV(1) /* Port Pin Value Bit 1 */ +#define FUSE_VALUE2 (unsigned char)~_BV(2) /* Port Pin Value Bit 2 */ +#define FUSE_VALUE3 (unsigned char)~_BV(3) /* Port Pin Value Bit 3 */ +#define FUSE_VALUE4 (unsigned char)~_BV(4) /* Port Pin Value Bit 4 */ +#define FUSE_VALUE5 (unsigned char)~_BV(5) /* Port Pin Value Bit 5 */ +#define FUSE_FDACT4 (unsigned char)~_BV(6) /* Fault Dectection Action on TC4 */ +#define FUSE_FDACT5 (unsigned char)~_BV(7) /* Fault Dectection Action on TC5 */ +#define FUSE6_DEFAULT (0xFF) + +/* ========== Lock Bits ========== */ +#define __LOCK_BITS_EXIST +#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST +#define __BOOT_LOCK_APPLICATION_BITS_EXIST +#define __BOOT_LOCK_BOOT_BITS_EXIST + +/* ========== Signature ========== */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x93 +#define SIGNATURE_2 0x41 + +/* ========== Power Reduction Condition Definitions ========== */ + +/* PR.PRGEN */ +#define __AVR_HAVE_PRGEN (PR_XCL_bm|PR_RTC_bm|PR_EVSYS_bm|PR_EDMA_bm) +#define __AVR_HAVE_PRGEN_XCL +#define __AVR_HAVE_PRGEN_RTC +#define __AVR_HAVE_PRGEN_EVSYS +#define __AVR_HAVE_PRGEN_EDMA + +/* PR.PRPA */ +#define __AVR_HAVE_PRPA (PR_DAC_bm|PR_ADC_bm|PR_AC_bm) +#define __AVR_HAVE_PRPA_DAC +#define __AVR_HAVE_PRPA_ADC +#define __AVR_HAVE_PRPA_AC + +/* PR.PRPC */ +#define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC5_bm|PR_TC4_bm) +#define __AVR_HAVE_PRPC_TWI +#define __AVR_HAVE_PRPC_USART0 +#define __AVR_HAVE_PRPC_SPI +#define __AVR_HAVE_PRPC_HIRES +#define __AVR_HAVE_PRPC_TC5 +#define __AVR_HAVE_PRPC_TC4 + +/* PR.PRPD */ +#define __AVR_HAVE_PRPD (PR_USART0_bm|PR_TC5_bm) +#define __AVR_HAVE_PRPD_USART0 +#define __AVR_HAVE_PRPD_TC5 + + +#endif /* #ifdef _AVR_ATXMEGA8E5_H_INCLUDED */ diff --git a/include/avr/lock.h b/include/avr/lock.h index fa876555..976175df 100644 --- a/include/avr/lock.h +++ b/include/avr/lock.h @@ -41,72 +41,72 @@ \par Introduction - The Lockbit API allows a user to specify the lockbit settings for the - specific AVR device they are compiling for. These lockbit settings will be + The Lockbit API allows a user to specify the lockbit settings for the + specific AVR device they are compiling for. These lockbit settings will be placed in a special section in the ELF output file, after linking. Programming tools can take advantage of the lockbit information embedded in the ELF file, by extracting this information and determining if the lockbits need to be programmed after programming the Flash and EEPROM memories. This also allows a single ELF file to contain all the - information needed to program an AVR. + information needed to program an AVR. To use the Lockbit API, include the header file, which in turn automatically includes the individual I/O header file and the file. These other two files provides everything necessary to set the AVR lockbits. - + \par Lockbit API - + Each I/O header file may define up to 3 macros that controls what kinds of lockbits are available to the user. - + If __LOCK_BITS_EXIST is defined, then two lock bits are available to the user and 3 mode settings are defined for these two bits. - + If __BOOT_LOCK_BITS_0_EXIST is defined, then the two BLB0 lock bits are available to the user and 4 mode settings are defined for these two bits. - + If __BOOT_LOCK_BITS_1_EXIST is defined, then the two BLB1 lock bits are available to the user and 4 mode settings are defined for these two bits. If __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST is defined then two lock bits - are available to set the locking mode for the Application Table Section + are available to set the locking mode for the Application Table Section (which is used in the XMEGA family). - + If __BOOT_LOCK_APPLICATION_BITS_EXIST is defined then two lock bits are available to set the locking mode for the Application Section (which is used in the XMEGA family). - + If __BOOT_LOCK_BOOT_BITS_EXIST is defined then two lock bits are available to set the locking mode for the Boot Loader Section (which is used in the XMEGA family). - The AVR lockbit modes have inverted values, logical 1 for an unprogrammed - (disabled) bit and logical 0 for a programmed (enabled) bit. The defined - macros for each individual lock bit represent this in their definition by a - bit-wise inversion of a mask. For example, the LB_MODE_3 macro is defined + The AVR lockbit modes have inverted values, logical 1 for an unprogrammed + (disabled) bit and logical 0 for a programmed (enabled) bit. The defined + macros for each individual lock bit represent this in their definition by a + bit-wise inversion of a mask. For example, the LB_MODE_3 macro is defined as: \code #define LB_MODE_3 (0xFC) ` \endcode - + To combine the lockbit mode macros together to represent a whole byte, use the bitwise AND operator, like so: \code (LB_MODE_3 & BLB0_MODE_2) \endcode - + also defines a macro that provides a default lockbit value: LOCKBITS_DEFAULT which is defined to be 0xFF. See the AVR device specific datasheet for more details about these lock bits and the available mode settings. - - A convenience macro, LOCKMEM, is defined as a GCC attribute for a + + A convenience macro, LOCKMEM, is defined as a GCC attribute for a custom-named section of ".lock". - - A convenience macro, LOCKBITS, is defined that declares a variable, __lock, + + A convenience macro, LOCKBITS, is defined that declares a variable, __lock, of type unsigned char with the attribute defined by LOCKMEM. This variable allows the end user to easily set the lockbit data. @@ -116,9 +116,9 @@ currently known to be defined in the I/O header files for the XMEGA devices. \par API Usage Example - + Putting all of this together is easy: - + \code #include @@ -129,13 +129,13 @@ return 0; } \endcode - + Or: - + \code #include - unsigned char __lock __attribute__((section (".lock"))) = + unsigned char __lock __attribute__((section (".lock"))) = (LB_MODE_1 & BLB0_MODE_3 & BLB1_MODE_4); int main(void) @@ -143,36 +143,36 @@ return 0; } \endcode - - - + + + However there are a number of caveats that you need to be aware of to use this API properly. - + Be sure to include to get all of the definitions for the API. - The LOCKBITS macro defines a global variable to store the lockbit data. This - variable is assigned to its own linker section. Assign the desired lockbit + The LOCKBITS macro defines a global variable to store the lockbit data. This + variable is assigned to its own linker section. Assign the desired lockbit values immediately in the variable initialization. - - The .lock section in the ELF file will get its values from the initial - variable assignment ONLY. This means that you can NOT assign values to + + The .lock section in the ELF file will get its values from the initial + variable assignment ONLY. This means that you can NOT assign values to this variable in functions and the new values will not be put into the ELF .lock section. - - The global variable is declared in the LOCKBITS macro has two leading + + The global variable is declared in the LOCKBITS macro has two leading underscores, which means that it is reserved for the "implementation", meaning the library, so it will not conflict with a user-named variable. - + You must initialize the lockbit variable to some meaningful value, even - if it is the default value. This is because the lockbits default to a - logical 1, meaning unprogrammed. Normal uninitialized data defaults to all - locgial zeros. So it is vital that all lockbits are initialized, even with - default data. If they are not, then the lockbits may not programmed to the - desired settings and can possibly put your device into an unrecoverable + if it is the default value. This is because the lockbits default to a + logical 1, meaning unprogrammed. Normal uninitialized data defaults to all + locgial zeros. So it is vital that all lockbits are initialized, even with + default data. If they are not, then the lockbits may not programmed to the + desired settings and can possibly put your device into an unrecoverable state. - + Be sure to have the -mmcu=device flag in your compile command line and - your linker command line to have the correct device selected and to have + your linker command line to have the correct device selected and to have the correct I/O header file included when you include . You can print out the contents of the .lock section in the ELF file by diff --git a/include/avr/pgmspace.h b/include/avr/pgmspace.h index f406865d..95b933b9 100644 --- a/include/avr/pgmspace.h +++ b/include/avr/pgmspace.h @@ -128,9 +128,9 @@ extern "C" { \typedef prog_void \note DEPRECATED - This typedef is now deprecated because the usage of the __progmem__ - attribute on a type is not supported in GCC. However, the use of the - __progmem__ attribute on a variable declaration is supported, and this is + This typedef is now deprecated because the usage of the __progmem__ + attribute on a type is not supported in GCC. However, the use of the + __progmem__ attribute on a variable declaration is supported, and this is now the recommended usage. The typedef is only visible if the macro __PROG_TYPES_COMPAT__ @@ -148,9 +148,9 @@ typedef void PROGMEM prog_void; \typedef prog_char \note DEPRECATED - This typedef is now deprecated because the usage of the __progmem__ - attribute on a type is not supported in GCC. However, the use of the - __progmem__ attribute on a variable declaration is supported, and this is + This typedef is now deprecated because the usage of the __progmem__ + attribute on a type is not supported in GCC. However, the use of the + __progmem__ attribute on a variable declaration is supported, and this is now the recommended usage. The typedef is only visible if the macro __PROG_TYPES_COMPAT__ @@ -166,9 +166,9 @@ typedef char PROGMEM prog_char; \typedef prog_uchar \note DEPRECATED - This typedef is now deprecated because the usage of the __progmem__ - attribute on a type is not supported in GCC. However, the use of the - __progmem__ attribute on a variable declaration is supported, and this is + This typedef is now deprecated because the usage of the __progmem__ + attribute on a type is not supported in GCC. However, the use of the + __progmem__ attribute on a variable declaration is supported, and this is now the recommended usage. The typedef is only visible if the macro __PROG_TYPES_COMPAT__ @@ -184,9 +184,9 @@ typedef unsigned char PROGMEM prog_uchar; \typedef prog_int8_t \note DEPRECATED - This typedef is now deprecated because the usage of the __progmem__ - attribute on a type is not supported in GCC. However, the use of the - __progmem__ attribute on a variable declaration is supported, and this is + This typedef is now deprecated because the usage of the __progmem__ + attribute on a type is not supported in GCC. However, the use of the + __progmem__ attribute on a variable declaration is supported, and this is now the recommended usage. The typedef is only visible if the macro __PROG_TYPES_COMPAT__ @@ -202,9 +202,9 @@ typedef int8_t PROGMEM prog_int8_t; \typedef prog_uint8_t \note DEPRECATED - This typedef is now deprecated because the usage of the __progmem__ - attribute on a type is not supported in GCC. However, the use of the - __progmem__ attribute on a variable declaration is supported, and this is + This typedef is now deprecated because the usage of the __progmem__ + attribute on a type is not supported in GCC. However, the use of the + __progmem__ attribute on a variable declaration is supported, and this is now the recommended usage. The typedef is only visible if the macro __PROG_TYPES_COMPAT__ @@ -220,9 +220,9 @@ typedef uint8_t PROGMEM prog_uint8_t; \typedef prog_int16_t \note DEPRECATED - This typedef is now deprecated because the usage of the __progmem__ - attribute on a type is not supported in GCC. However, the use of the - __progmem__ attribute on a variable declaration is supported, and this is + This typedef is now deprecated because the usage of the __progmem__ + attribute on a type is not supported in GCC. However, the use of the + __progmem__ attribute on a variable declaration is supported, and this is now the recommended usage. The typedef is only visible if the macro __PROG_TYPES_COMPAT__ @@ -238,9 +238,9 @@ typedef int16_t PROGMEM prog_int16_t; \typedef prog_uint16_t \note DEPRECATED - This typedef is now deprecated because the usage of the __progmem__ - attribute on a type is not supported in GCC. However, the use of the - __progmem__ attribute on a variable declaration is supported, and this is + This typedef is now deprecated because the usage of the __progmem__ + attribute on a type is not supported in GCC. However, the use of the + __progmem__ attribute on a variable declaration is supported, and this is now the recommended usage. The typedef is only visible if the macro __PROG_TYPES_COMPAT__ @@ -256,9 +256,9 @@ typedef uint16_t PROGMEM prog_uint16_t; \typedef prog_int32_t \note DEPRECATED - This typedef is now deprecated because the usage of the __progmem__ - attribute on a type is not supported in GCC. However, the use of the - __progmem__ attribute on a variable declaration is supported, and this is + This typedef is now deprecated because the usage of the __progmem__ + attribute on a type is not supported in GCC. However, the use of the + __progmem__ attribute on a variable declaration is supported, and this is now the recommended usage. The typedef is only visible if the macro __PROG_TYPES_COMPAT__ @@ -274,9 +274,9 @@ typedef int32_t PROGMEM prog_int32_t; \typedef prog_uint32_t \note DEPRECATED - This typedef is now deprecated because the usage of the __progmem__ - attribute on a type is not supported in GCC. However, the use of the - __progmem__ attribute on a variable declaration is supported, and this is + This typedef is now deprecated because the usage of the __progmem__ + attribute on a type is not supported in GCC. However, the use of the + __progmem__ attribute on a variable declaration is supported, and this is now the recommended usage. The typedef is only visible if the macro __PROG_TYPES_COMPAT__ @@ -292,9 +292,9 @@ typedef uint32_t PROGMEM prog_uint32_t; \typedef prog_int64_t \note DEPRECATED - This typedef is now deprecated because the usage of the __progmem__ - attribute on a type is not supported in GCC. However, the use of the - __progmem__ attribute on a variable declaration is supported, and this is + This typedef is now deprecated because the usage of the __progmem__ + attribute on a type is not supported in GCC. However, the use of the + __progmem__ attribute on a variable declaration is supported, and this is now the recommended usage. The typedef is only visible if the macro __PROG_TYPES_COMPAT__ @@ -313,9 +313,9 @@ typedef int64_t PROGMEM prog_int64_t; \typedef prog_uint64_t \note DEPRECATED - This typedef is now deprecated because the usage of the __progmem__ - attribute on a type is not supported in GCC. However, the use of the - __progmem__ attribute on a variable declaration is supported, and this is + This typedef is now deprecated because the usage of the __progmem__ + attribute on a type is not supported in GCC. However, the use of the + __progmem__ attribute on a variable declaration is supported, and this is now the recommended usage. The typedef is only visible if the macro __PROG_TYPES_COMPAT__ @@ -565,7 +565,7 @@ typedef uint64_t prog_uint64_t __attribute__((__progmem__,deprecated("prog_uint /** \ingroup avr_pgmspace \def pgm_read_byte_near(address_short) - Read a byte from the program space with a 16-bit (near) address. + Read a byte from the program space with a 16-bit (near) address. \note The address is a byte address. The address is in the program space. */ @@ -573,16 +573,16 @@ typedef uint64_t prog_uint64_t __attribute__((__progmem__,deprecated("prog_uint /** \ingroup avr_pgmspace \def pgm_read_word_near(address_short) - Read a word from the program space with a 16-bit (near) address. - \note The address is a byte address. + Read a word from the program space with a 16-bit (near) address. + \note The address is a byte address. The address is in the program space. */ #define pgm_read_word_near(address_short) __LPM_word((uint16_t)(address_short)) /** \ingroup avr_pgmspace \def pgm_read_dword_near(address_short) - Read a double word from the program space with a 16-bit (near) address. - \note The address is a byte address. + Read a double word from the program space with a 16-bit (near) address. + \note The address is a byte address. The address is in the program space. */ #define pgm_read_dword_near(address_short) \ @@ -590,8 +590,8 @@ typedef uint64_t prog_uint64_t __attribute__((__progmem__,deprecated("prog_uint /** \ingroup avr_pgmspace \def pgm_read_float_near(address_short) - Read a float from the program space with a 16-bit (near) address. - \note The address is a byte address. + Read a float from the program space with a 16-bit (near) address. + \note The address is a byte address. The address is in the program space. */ #define pgm_read_float_near(address_short) \ @@ -599,8 +599,8 @@ typedef uint64_t prog_uint64_t __attribute__((__progmem__,deprecated("prog_uint /** \ingroup avr_pgmspace \def pgm_read_ptr_near(address_short) - Read a pointer from the program space with a 16-bit (near) address. - \note The address is a byte address. + Read a pointer from the program space with a 16-bit (near) address. + \note The address is a byte address. The address is in the program space. */ #define pgm_read_ptr_near(address_short) \ @@ -927,16 +927,16 @@ not interfere with data accesses. /** \ingroup avr_pgmspace \def pgm_read_byte_far(address_long) - Read a byte from the program space with a 32-bit (far) address. + Read a byte from the program space with a 32-bit (far) address. - \note The address is a byte address. + \note The address is a byte address. The address is in the program space. */ #define pgm_read_byte_far(address_long) __ELPM((uint32_t)(address_long)) /** \ingroup avr_pgmspace \def pgm_read_word_far(address_long) - Read a word from the program space with a 32-bit (far) address. + Read a word from the program space with a 32-bit (far) address. \note The address is a byte address. The address is in the program space. */ @@ -945,7 +945,7 @@ not interfere with data accesses. /** \ingroup avr_pgmspace \def pgm_read_dword_far(address_long) - Read a double word from the program space with a 32-bit (far) address. + Read a double word from the program space with a 32-bit (far) address. \note The address is a byte address. The address is in the program space. */ @@ -954,7 +954,7 @@ not interfere with data accesses. /** \ingroup avr_pgmspace \def pgm_read_float_far(address_long) - Read a float from the program space with a 32-bit (far) address. + Read a float from the program space with a 32-bit (far) address. \note The address is a byte address. The address is in the program space. */ @@ -963,7 +963,7 @@ not interfere with data accesses. /** \ingroup avr_pgmspace \def pgm_read_ptr_far(address_long) - Read a pointer from the program space with a 32-bit (far) address. + Read a pointer from the program space with a 32-bit (far) address. \note The address is a byte address. The address is in the program space. */ @@ -974,45 +974,45 @@ not interfere with data accesses. /** \ingroup avr_pgmspace \def pgm_read_byte(address_short) - Read a byte from the program space with a 16-bit (near) address. + Read a byte from the program space with a 16-bit (near) address. - \note The address is a byte address. + \note The address is a byte address. The address is in the program space. */ #define pgm_read_byte(address_short) pgm_read_byte_near(address_short) /** \ingroup avr_pgmspace \def pgm_read_word(address_short) - Read a word from the program space with a 16-bit (near) address. + Read a word from the program space with a 16-bit (near) address. - \note The address is a byte address. + \note The address is a byte address. The address is in the program space. */ #define pgm_read_word(address_short) pgm_read_word_near(address_short) /** \ingroup avr_pgmspace \def pgm_read_dword(address_short) - Read a double word from the program space with a 16-bit (near) address. + Read a double word from the program space with a 16-bit (near) address. - \note The address is a byte address. + \note The address is a byte address. The address is in the program space. */ #define pgm_read_dword(address_short) pgm_read_dword_near(address_short) /** \ingroup avr_pgmspace \def pgm_read_float(address_short) - Read a float from the program space with a 16-bit (near) address. + Read a float from the program space with a 16-bit (near) address. - \note The address is a byte address. + \note The address is a byte address. The address is in the program space. */ #define pgm_read_float(address_short) pgm_read_float_near(address_short) /** \ingroup avr_pgmspace \def pgm_read_ptr(address_short) - Read a pointer from the program space with a 16-bit (near) address. + Read a pointer from the program space with a 16-bit (near) address. - \note The address is a byte address. + \note The address is a byte address. The address is in the program space. */ #define pgm_read_ptr(address_short) pgm_read_ptr_near(address_short) diff --git a/include/avr/power.h b/include/avr/power.h index 79cabd87..73b0cb2a 100644 --- a/include/avr/power.h +++ b/include/avr/power.h @@ -1,5 +1,5 @@ /* Copyright (c) 2006, 2007, 2008 Eric B. Weddington - Copyright (c) 2011 Frédéric Nadeau + Copyright (c) 2011 Frédéric Nadeau All rights reserved. Redistribution and use in source and binary forms, with or without @@ -41,8 +41,8 @@ \code #include \endcode -Many AVRs contain a Power Reduction Register (PRR) or Registers (PRRx) that -allow you to reduce power consumption by disabling or enabling various on-board +Many AVRs contain a Power Reduction Register (PRR) or Registers (PRRx) that +allow you to reduce power consumption by disabling or enabling various on-board peripherals as needed. Some devices have the XTAL Divide Control Register (XDIV) which offer similar functionality as System Clock Prescale Register (CLKPR). @@ -55,13 +55,13 @@ the ATmega8). On those devices without a Power Reduction Register, the power reduction macros are not available.. \note Not all AVR devices contain the same peripherals (for example, the LCD -interface), or they will be named differently (for example, USART and -USART0). Please consult your device's datasheet, or the header file, to +interface), or they will be named differently (for example, USART and +USART0). Please consult your device's datasheet, or the header file, to find out which macros are applicable to your device. \note For device using the XTAL Divide Control Register (XDIV), when prescaler is used, Timer/Counter0 can only be used in asynchronous mode. Keep in mind -that Timer/Counter0 source shall be less than ¼th of peripheral clock. +that Timer/Counter0 source shall be less than ¼th of peripheral clock. Therefore, when using a typical 32.768 kHz crystal, one shall not scale the clock below 131.072 kHz. @@ -148,7 +148,7 @@ the clock below 131.072 kHz. power_pga_disable() Disable the Programmable Gain Amplifier module. - + power_pscr_enable() Enable the Reduced Power Stage Controller module. @@ -795,8 +795,8 @@ the clock below 131.072 kHz. #endif #if defined(__AVR_HAVE_PRR1_PRLFR) -#define power_lfreceiver_enable() (PRR1 &= (uint8_t)~(1 << PRLFR)) -#define power_lfreceiver_disable() (PRR1 |= (uint8_t)(1 << PRLFR)) +#define power_lfreceiver_enable() (PRR1 &= (uint8_t)~(1 << PRLFR)) +#define power_lfreceiver_disable() (PRR1 |= (uint8_t)(1 << PRLFR)) #endif #if defined(__AVR_HAVE_PRR1_PRLFTP) @@ -1414,7 +1414,7 @@ macros are not available. /** \addtogroup avr_power -\code +\code typedef enum { clock_div_1 = 0, @@ -1692,7 +1692,7 @@ void timer_clock_prescale_set(timer_clock_div_t __x) : /* no outputs */ : [temp] "r" (__t), [clpr] "I" (_SFR_IO_ADDR(CLKPR)), - [enable] "r" (_BV(CLPCE)), + [enable] "r" (_BV(CLPCE)), [not_CLTPS] "M" (0xFF & (~ ((1 << CLTPS2) | (1 << CLTPS1) | (1 << CLTPS0)))), [set_value] "r" ((__x & 7) << 3) : "r0"); @@ -1842,7 +1842,7 @@ clock_div_t clock_prescale_get(void) return (clock_div_t)(129 - (XDIV & 0x7F)); } } - + #elif defined(__AVR_ATtiny4__) \ || defined(__AVR_ATtiny5__) \ || defined(__AVR_ATtiny9__) \ @@ -1850,18 +1850,18 @@ clock_div_t clock_prescale_get(void) || defined(__AVR_ATtiny20__) \ || defined(__AVR_ATtiny40__) \ -typedef enum -{ - clock_div_1 = 0, - clock_div_2 = 1, - clock_div_4 = 2, - clock_div_8 = 3, - clock_div_16 = 4, - clock_div_32 = 5, - clock_div_64 = 6, - clock_div_128 = 7, - clock_div_256 = 8 -} clock_div_t; +typedef enum +{ + clock_div_1 = 0, + clock_div_2 = 1, + clock_div_4 = 2, + clock_div_8 = 3, + clock_div_16 = 4, + clock_div_32 = 5, + clock_div_64 = 6, + clock_div_128 = 7, + clock_div_256 = 8 +} clock_div_t; static __inline__ void clock_prescale_set(clock_div_t) __attribute__((__always_inline__)); @@ -1883,7 +1883,7 @@ void clock_prescale_set(clock_div_t __x) } #define clock_prescale_get() (clock_div_t)(CLKPSR & (uint8_t)((1<\endcode - Test whether bit \c bit in IO register \c sfr is set. + Test whether bit \c bit in IO register \c sfr is set. This will return a 0 if the bit is clear, and non-zero if the bit is set. */ @@ -238,7 +238,7 @@ \code #include \endcode - Test whether bit \c bit in IO register \c sfr is clear. + Test whether bit \c bit in IO register \c sfr is clear. This will return non-zero if the bit is clear, and a 0 if the bit is set. */ diff --git a/include/avr/signature.h b/include/avr/signature.h index 40fea7b8..8479434f 100644 --- a/include/avr/signature.h +++ b/include/avr/signature.h @@ -43,28 +43,28 @@ The header file allows the user to automatically and easily include the device's signature data in a special section of the final linked ELF file. - + This value can then be used by programming software to compare the on-device signature with the signature recorded in the ELF file to look for a match before programming the device. - + \par API Usage Example Usage is very simple; just include the header file: - + \code #include \endcode - + This will declare a constant unsigned char array and it is initialized with the three signature bytes, MSB first, that are defined in the device I/O header file. This array is then placed in the .signature section in the resulting linked ELF file. - - The three signature bytes that are used to initialize the array are + + The three signature bytes that are used to initialize the array are these defined macros in the device I/O header file, from MSB to LSB: SIGNATURE_2, SIGNATURE_1, SIGNATURE_0. - + This header file should only be included once in an application. */ diff --git a/include/avr/sleep.h b/include/avr/sleep.h index fa0d8f07..034c1686 100644 --- a/include/avr/sleep.h +++ b/include/avr/sleep.h @@ -55,9 +55,9 @@ set the desired sleep mode using \c set_sleep_mode() (it usually defaults to idle mode where the CPU is put on sleep but all peripheral clocks are still running), and then call - \c sleep_mode(). This macro automatically sets the sleep enable bit, goes + \c sleep_mode(). This macro automatically sets the sleep enable bit, goes to sleep, and clears the sleep enable bit. - + Example: \code #include @@ -66,8 +66,8 @@ set_sleep_mode(); sleep_mode(); \endcode - - Note that unless your purpose is to completely lock the CPU (until a + + Note that unless your purpose is to completely lock the CPU (until a hardware reset), interrupts need to be enabled before going to sleep. As the \c sleep_mode() macro might cause race conditions in some @@ -103,7 +103,7 @@ after the \c SEI is guaranteed to be executed before an interrupt could trigger, it is sure the device will really be put to sleep. - Some devices have the ability to disable the Brown Out Detector (BOD) before + Some devices have the ability to disable the Brown Out Detector (BOD) before going to sleep. This will also reduce power while sleeping. If the specific AVR device has this ability then an additional macro is defined: \c sleep_bod_disable(). This macro generates inlined assembly code diff --git a/include/avr/wdt.h b/include/avr/wdt.h index 2b4a02e1..8bcfbad8 100644 --- a/include/avr/wdt.h +++ b/include/avr/wdt.h @@ -84,7 +84,7 @@ \endcode Saving the value of MCUSR in \c mcusr_mirror is only needed if the - application later wants to examine the reset source, but in particular, + application later wants to examine the reset source, but in particular, clearing the watchdog reset flag before disabling the watchdog is required, according to the datasheet. */ @@ -93,7 +93,7 @@ \ingroup avr_watchdog Reset the watchdog timer. When the watchdog timer is enabled, a call to this instruction is required before the timer expires, - otherwise a watchdog-initiated device reset will occur. + otherwise a watchdog-initiated device reset will occur. */ #define wdt_reset() __asm__ __volatile__ ("wdr") @@ -127,8 +127,8 @@ \ingroup avr_watchdog Enable the watchdog timer, configuring it for expiry after \c timeout (which is a combination of the \c WDP0 through - \c WDP2 bits to write into the \c WDTCR register; For those devices - that have a \c WDTCSR register, it uses the combination of the \c WDP0 + \c WDP2 bits to write into the \c WDTCR register; For those devices + that have a \c WDTCSR register, it uses the combination of the \c WDP0 through \c WDP3 bits). See also the symbolic constants \c WDTO_15MS et al. @@ -587,11 +587,11 @@ void wdt_disable (void) /** \ingroup avr_watchdog See \c WDTO_15MS - Note: This is only available on the - ATtiny2313, + Note: This is only available on the + ATtiny2313, ATtiny24, ATtiny44, ATtiny84, ATtiny84A, - ATtiny25, ATtiny45, ATtiny85, - ATtiny261, ATtiny461, ATtiny861, + ATtiny25, ATtiny45, ATtiny85, + ATtiny261, ATtiny461, ATtiny861, ATmega48, ATmega88, ATmega168, ATmega48P, ATmega88P, ATmega168P, ATmega328P, ATmega164P, ATmega324P, ATmega644P, ATmega644, @@ -612,11 +612,11 @@ void wdt_disable (void) /** \ingroup avr_watchdog See \c WDTO_15MS - Note: This is only available on the - ATtiny2313, + Note: This is only available on the + ATtiny2313, ATtiny24, ATtiny44, ATtiny84, ATtiny84A, - ATtiny25, ATtiny45, ATtiny85, - ATtiny261, ATtiny461, ATtiny861, + ATtiny25, ATtiny45, ATtiny85, + ATtiny261, ATtiny461, ATtiny861, ATmega48, ATmega48A, ATmega48PA, ATmega88, ATmega168, ATmega48P, ATmega88P, ATmega168P, ATmega328P, ATmega164P, ATmega324P, ATmega644P, ATmega644, @@ -640,6 +640,6 @@ void wdt_disable (void) #define WDTO_8S 9 #endif /* defined(__DOXYGEN__) || defined(WDP3) */ - + #endif /* _AVR_WDT_H_ */ diff --git a/include/compat/deprecated.h b/include/compat/deprecated.h index a43fe063..f237f686 100644 --- a/include/compat/deprecated.h +++ b/include/compat/deprecated.h @@ -54,7 +54,7 @@ interrupt needs to be enabled separately if interrupts for this device are desired. While some devices maintain their interrupt enable bit inside the device's register set, external and timer interrupts have system-wide - configuration registers. + configuration registers. Example: @@ -81,7 +81,7 @@ This macro gives access to the \c GIMSK register (or \c EIMSK register if using an AVR Mega device or \c GICR register for others). Although this macro is essentially the same as assigning to the register, it does - adapt slightly to the type of device being used. This macro is + adapt slightly to the type of device being used. This macro is unavailable if none of the registers listed above are defined. */ /* Define common register definition if available. */ diff --git a/include/compat/ina90.h b/include/compat/ina90.h index 076593ae..9370a8bd 100644 --- a/include/compat/ina90.h +++ b/include/compat/ina90.h @@ -96,4 +96,3 @@ #define output_block_dec(port, addr, cnt) __out_blk__(port, addr, cnt, --) #endif - diff --git a/include/ctype.h b/include/ctype.h index 6cb03be6..289687f6 100644 --- a/include/ctype.h +++ b/include/ctype.h @@ -48,7 +48,7 @@ extern "C" { /** \defgroup ctype : Character Operations These functions perform various operations on characters. - \code #include \endcode + \code #include \endcode */ @@ -149,7 +149,7 @@ extern int isxdigit(int __c); /* @} */ -/** \name Character convertion routines +/** \name Character convertion routines This realization permits all possible values of integer argument. The toascii() function clears all highest bits. The tolower() and diff --git a/include/errno.h b/include/errno.h index f7c8cc8b..59fac788 100644 --- a/include/errno.h +++ b/include/errno.h @@ -40,7 +40,7 @@ Some functions in the library set the global variable \c errno when an error occurs. The file, \c , provides symbolic names for various - error codes. + error codes. */ #ifdef __cplusplus diff --git a/include/math.h b/include/math.h index 8c857bef..fefb19a5 100644 --- a/include/math.h +++ b/include/math.h @@ -171,7 +171,7 @@ __ATTR_CONST__ extern long double fmodl (long double __x, long double __y); /** The modf() function breaks the argument \a __x into integral and - fractional parts, each of which has the same sign as the argument. + fractional parts, each of which has the same sign as the argument. It stores the integral part as a double in the object pointed to by \a __iptr. diff --git a/include/stdio.h b/include/stdio.h index f15e03e5..a5919e71 100644 --- a/include/stdio.h +++ b/include/stdio.h @@ -493,7 +493,7 @@ extern int fclose(FILE *__stream); signed conversion. A + overrides a space if both are used. - + - An optional decimal digit string specifying a minimum field width. If the converted value has fewer characters than the field width, it will be padded with spaces on the left (or right, if the left-adjustment @@ -536,7 +536,7 @@ extern int fclose(FILE *__stream); - \c % A \c % is written. No argument is converted. The complete conversion specification is "%%". - \c eE The double argument is rounded and converted in the format - \c "[-]d.ddde±dd" where there is one digit before the + \c "[-]d.ddde±dd" where there is one digit before the decimal-point character and the number of digits after it is equal to the precision; if the precision is missing, it is taken as 6; if the precision is zero, no decimal-point @@ -803,7 +803,7 @@ extern int getchar(void); Currently, only a single character can be pushed back onto the stream. - + The ungetc() function returns the character pushed back after the conversion, or \c EOF if the operation fails. If the value of the argument \c c character equals \c EOF, the operation will fail and diff --git a/include/stdlib.h b/include/stdlib.h index c3c493b2..ae4bdaf7 100644 --- a/include/stdlib.h +++ b/include/stdlib.h @@ -124,7 +124,7 @@ static __ATTR_ALWAYS_INLINE__ int abs (int __i) { return __builtin_abs (__i); -} +} #endif /** The abs() function computes the absolute value of the integer \c i. \note The abs() and labs() functions are builtins of gcc. @@ -136,7 +136,7 @@ static __ATTR_ALWAYS_INLINE__ long labs (long __i) { return __builtin_labs (__i); -} +} #endif /** The labs() function computes the absolute value of the long integer \c i. @@ -258,7 +258,7 @@ extern long strtol(const char *__nptr, char **__endptr, int __base); or, if there was a leading minus sign, the negation of the result of the conversion, unless the original (non-negated) value would overflow; in the latter case, strtoul() returns ULONG_MAX, and \c - errno is set to \ref avr_errno "ERANGE". If no conversion could + errno is set to \ref avr_errno "ERANGE". If no conversion could be performed, 0 is returned. */ extern unsigned long strtoul(const char *__nptr, char **__endptr, int __base); @@ -433,7 +433,7 @@ extern int rand_r(unsigned long *__ctx); number between 2 (binary conversion) and up to 36. If \c radix is greater than 10, the next digit after \c '9' will be the letter \c 'a'. - + If radix is 10 and val is negative, a minus sign will be prepended. The itoa() function returns the pointer passed as \c s. @@ -459,7 +459,7 @@ char *itoa (int __val, char *__s, int __radix) /** \ingroup avr_stdlib - + \brief Convert a long integer to a string. The function ltoa() converts the long integer value from \c val into an @@ -646,7 +646,7 @@ extern long random_r(unsigned long *__ctx); an ASCII representation that will be stored under \c s. The caller is responsible for providing sufficient storage in \c s. - Conversion is done in the format \c "[-]d.ddde±dd" where there is + Conversion is done in the format \c "[-]d.ddde±dd" where there is one digit before the decimal-point character and the number of digits after it is equal to the precision \c prec; if the precision is zero, no decimal-point character appears. If \c flags has the diff --git a/include/string.h b/include/string.h index 35d895b6..fe882865 100644 --- a/include/string.h +++ b/include/string.h @@ -63,7 +63,7 @@ extern "C" { \code #include \endcode The string functions perform string operations on NULL terminated - strings. + strings. \note If the strings you are working on resident in program space (flash), you will need to use the string functions described in \ref avr_pgmspace. */ @@ -617,4 +617,3 @@ extern size_t strxfrm(char *dest, const char *src, size_t n); #endif #endif /* _STRING_H_ */ - diff --git a/include/util/crc16.h b/include/util/crc16.h index 630b6fc9..467a1d79 100644 --- a/include/util/crc16.h +++ b/include/util/crc16.h @@ -244,7 +244,7 @@ _crc_xmodem_update(uint16_t __crc, uint8_t __data) data ^= lo8 (crc); data ^= data << 4; - return ((((uint16_t)data << 8) | hi8 (crc)) ^ (uint8_t)(data >> 4) + return ((((uint16_t)data << 8) | hi8 (crc)) ^ (uint8_t)(data >> 4) ^ ((uint16_t)data << 3)); } \endcode */ @@ -338,19 +338,19 @@ _crc_ibutton_update(uint8_t __crc, uint8_t __data) Optimized CRC-8-CCITT calculation. Polynomial: x^8 + x^2 + x + 1 (0xE0)
- + For use with simple CRC-8
Initial value: 0x0 - + For use with CRC-8-ROHC
Initial value: 0xff
Reference: http://tools.ietf.org/html/rfc3095#section-5.9.1 - + For use with CRC-8-ATM/ITU
Initial value: 0xff
Final XOR value: 0x55
Reference: http://www.itu.int/rec/T-REC-I.432.1-199902-I/en - + The C equivalent has been originally written by Dave Hylands. Assembly code is based on _crc_ibutton_update optimization. diff --git a/libc/misc/ccp_write.S b/libc/misc/ccp_write.S index c1aa0c84..9dc1ab69 100644 --- a/libc/misc/ccp_write.S +++ b/libc/misc/ccp_write.S @@ -22,6 +22,5 @@ ENTRY ccp_write_io ret ENDFUNC -#endif /* __AVR_XMEGA__ && CCP_IOREG_gc */ +#endif /* __AVR_XMEGA__ && CCP_IOREG_gc */ #endif /* !__DOXYGEN__ */ - diff --git a/libc/misc/eerd_block.S b/libc/misc/eerd_block.S index ef399378..e6619787 100644 --- a/libc/misc/eerd_block.S +++ b/libc/misc/eerd_block.S @@ -61,14 +61,14 @@ ENTRY eeprom_read_block #if __AVR_XMEGA__ /* -------------------------------------------- */ - + ; It has to be noted that for some Xmega parts (Eg. Xmega E family) EEPROM ; is always memory mapped. So it is not required to enable EEPROM mapping - ; explicitly. + ; explicitly. ; The presence of NVM_EEMAPEN_bm macro (from the part header file) can be ; checked to find out whether the device supports enabling/disabling of ; EEPROM mapping. Absence of NVM_EEMAPEN_bm could be interpreted safely as - ; EEPROM always memory mapped and explicit memory mapping of EEPROM is not + ; EEPROM always memory mapped and explicit memory mapping of EEPROM is not ; required/invalid. #if defined (NVM_EEMAPEN_bm) ; Load base address of NVM. diff --git a/libc/misc/eerd_byte.S b/libc/misc/eerd_byte.S index ee724104..a71f0f7c 100644 --- a/libc/misc/eerd_byte.S +++ b/libc/misc/eerd_byte.S @@ -57,11 +57,11 @@ ENTRY eeprom_mapen ; It has to be noted that for some Xmega parts (Eg. Xmega E family) EEPROM ; is always memory mapped. So it is not required to enable EEPROM mapping - ; explicitly. + ; explicitly. ; The presence of NVM_EEMAPEN_bm macro (from the part header file) can be ; checked to find out whether the device supports enabling/disabling of ; EEPROM mapping. Absence of NVM_EEMAPEN_bm could be interpreted safely as - ; EEPROM always memory mapped and explicit memory mapping of EEPROM is not + ; EEPROM always memory mapped and explicit memory mapping of EEPROM is not ; required/invalid. #if defined (NVM_EEMAPEN_bm) ; Load base address of NVM. diff --git a/libc/misc/eewr_block_xmega.c b/libc/misc/eewr_block_xmega.c index dacb6214..31d48ae1 100644 --- a/libc/misc/eewr_block_xmega.c +++ b/libc/misc/eewr_block_xmega.c @@ -125,4 +125,3 @@ void eeprom_write_block (const void *sram, void *eeprom_addr, size_t length) #endif /* E2END && __AVR_XMEGA__ && E2PAGESIZE */ #endif /* !__DOXYGEN__ */ - diff --git a/libc/misc/eewr_byte.S b/libc/misc/eewr_byte.S index de8f212f..da87d7ea 100644 --- a/libc/misc/eewr_byte.S +++ b/libc/misc/eewr_byte.S @@ -78,11 +78,11 @@ ENTRY eeprom_write_r18 ; It has to be noted that for some Xmega parts (Eg. Xmega E family) EEPROM ; is always memory mapped. So it is not possible to disable EEPROM mapping - ; explicitly. + ; explicitly. ; The presence of NVM_EEMAPEN_bm macro (from the part header file) can be ; checked to find out whether the device supports enabling/disabling of ; EEPROM mapping. Absence of NVM_EEMAPEN_bm could be interpreted safely as - ; EEPROM always memory mapped and explicit memory mapping of EEPROM is not + ; EEPROM always memory mapped and explicit memory mapping of EEPROM is not ; required/invalid. #if defined (NVM_EEMAPEN_bm) ; Disable EEPROM mapping into data space. diff --git a/libc/misc/mul10.S b/libc/misc/mul10.S index 447826da..f033d76c 100644 --- a/libc/misc/mul10.S +++ b/libc/misc/mul10.S @@ -43,7 +43,7 @@ #define r_tmp_lo r22 #define r_tmp_hi r23 -/* +/* r_hi:r_lo *= 10 Optimized version, without calling __mulhi3 (which is slow for @@ -63,7 +63,7 @@ _U(__mulhi_const_10): add r_hi,r1 clr r1 ; __zero_reg__ #else - X_movw r_tmp_lo, r_lo + X_movw r_tmp_lo, r_lo add r_lo,r_lo adc r_hi,r_hi add r_lo,r_lo diff --git a/libc/misc/readme_eeprom.txt b/libc/misc/readme_eeprom.txt index 2b896f85..b25f73aa 100644 --- a/libc/misc/readme_eeprom.txt +++ b/libc/misc/readme_eeprom.txt @@ -56,7 +56,7 @@ Register usage of internally-used functions, common archs: r25,r24 - decremented EEPROM address Scratch: r18,r0 - + eeprom_write_r18: Input: r18 - byte to write @@ -65,7 +65,7 @@ Register usage of internally-used functions, common archs: r25,r24 - incremented EEPROM address Scratch: r0 - + eeprom_write_byte: Input: r22 - byte to write diff --git a/libc/pmstring/memcmp_P.S b/libc/pmstring/memcmp_P.S index 1b800b54..23ce192d 100644 --- a/libc/pmstring/memcmp_P.S +++ b/libc/pmstring/memcmp_P.S @@ -26,7 +26,7 @@ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ - + /* $Id$ */ #if !defined(__AVR_TINY__) diff --git a/libc/pmstring/strncat_P.S b/libc/pmstring/strncat_P.S index 0bf9bcc4..d8a1d9cf 100644 --- a/libc/pmstring/strncat_P.S +++ b/libc/pmstring/strncat_P.S @@ -45,7 +45,7 @@ ASSEMBLY_CLIB_SECTION .global _U(strncat_P) .type _U(strncat_P), @function - + _U(strncat_P): X_movw ZL, src_lo X_movw XL, dest_lo diff --git a/libc/stdio/Rules.am b/libc/stdio/Rules.am index 38937d9f..00a0d0d7 100644 --- a/libc/stdio/Rules.am +++ b/libc/stdio/Rules.am @@ -49,7 +49,7 @@ nodist_libscanf_flt_a_SOURCES= libscanf_flt_a_LIBADD = vfscanf_flt.o -# vfprintf is compiled best with -Os -g -fno-jump-tables (-mno-tablejump), +# vfprintf is compiled best with -Os -g -fno-jump-tables (-mno-tablejump), # this gives the smallest code. PRINTF_CFLAGS = -Os @CDEBUG@ $(FNO_JUMP_TABLES) diff --git a/libc/stdio/clearerr.c b/libc/stdio/clearerr.c index 067bfe1f..f01ce079 100644 --- a/libc/stdio/clearerr.c +++ b/libc/stdio/clearerr.c @@ -36,7 +36,7 @@ #undef clearerr ATTRIBUTE_CLIB_SECTION -void +void clearerr(FILE *stream) { diff --git a/libc/stdio/fgetc.c b/libc/stdio/fgetc.c index c9e39bf5..07ccb7eb 100644 --- a/libc/stdio/fgetc.c +++ b/libc/stdio/fgetc.c @@ -68,4 +68,3 @@ fgetc(FILE *stream) stream->len++; return (unsigned char)rv; } - diff --git a/libc/stdio/ultoa_invert.S b/libc/stdio/ultoa_invert.S index 1c4dc136..e44adc3c 100644 --- a/libc/stdio/ultoa_invert.S +++ b/libc/stdio/ultoa_invert.S @@ -174,7 +174,7 @@ __ultoa_invert: rcall .L_lsr_4 brne .L_hex rjmp .L_eos - + .L_lsr_4: ldi cnt, 4 .L_lsr: diff --git a/libc/stdio/ungetc.c b/libc/stdio/ungetc.c index f649d7f5..4df79ab5 100644 --- a/libc/stdio/ungetc.c +++ b/libc/stdio/ungetc.c @@ -56,4 +56,3 @@ ungetc(int c, FILE *stream) return stream->unget; } - diff --git a/libc/stdio/vfprintf.c b/libc/stdio/vfprintf.c index 411e6f9b..01e7ccf5 100644 --- a/libc/stdio/vfprintf.c +++ b/libc/stdio/vfprintf.c @@ -325,7 +325,7 @@ int vfprintf (FILE * stream, const char *fmt, va_list ap) flags = 0; width = 0; prec = 0; - + do { if (flags < FL_WIDTH) { switch (c) { @@ -375,7 +375,7 @@ int vfprintf (FILE * stream, const char *fmt, va_list ap) if (c == 'h') continue; } - + break; } while ( (c = GETBYTE (stream->flags, __SPGM, fmt)) != 0); @@ -434,7 +434,7 @@ int vfprintf (FILE * stream, const char *fmt, va_list ap) } exp = __ftoa_engine (va_arg(ap,double), (char *)buf, vtype, ndigs); vtype = buf[0]; - + sign = 0; if ((vtype & FTOA_MINUS) && !(vtype & FTOA_NAN)) sign = '-'; @@ -493,7 +493,7 @@ int vfprintf (FILE * stream, const char *fmt, va_list ap) ? prec - exp : 0; /* fractional part length */ } } - + /* Conversion result length, width := free space length */ if (flags & FL_FLTFIX) n = (exp>0 ? exp+1 : 1); @@ -502,7 +502,7 @@ int vfprintf (FILE * stream, const char *fmt, va_list ap) if (sign) n += 1; if (prec) n += prec + 1; width = width > n ? width - n : 0; - + /* Output before first digit */ if (!(flags & (FL_LPAD | FL_ZFILL))) { while (width) { @@ -517,7 +517,7 @@ int vfprintf (FILE * stream, const char *fmt, va_list ap) width--; } } - + if (flags & FL_FLTFIX) { /* 'f' format */ n = exp > 0 ? exp : 0; /* exponent of left digit */ @@ -537,7 +537,7 @@ int vfprintf (FILE * stream, const char *fmt, va_list ap) flags = '1'; } putc (flags, stream); - + } else { /* 'e(E)' format */ /* mantissa */ @@ -709,7 +709,7 @@ int vfprintf (FILE * stream, const char *fmt, va_list ap) len++; } } - + width = (len < width) ? width - len : 0; if (flags & FL_ALT) { @@ -722,17 +722,17 @@ int vfprintf (FILE * stream, const char *fmt, va_list ap) if (flags & FL_NEGATIVE) z = '-'; putc (z, stream); } - + while (prec > c) { putc ('0', stream); prec--; } - + do { putc (buf[--c], stream); } while (c); } - + tail: /* Tail is possible. */ while (width) { diff --git a/libc/stdio/vfscanf.c b/libc/stdio/vfscanf.c index 5f1d9f0e..09ef81be 100644 --- a/libc/stdio/vfscanf.c +++ b/libc/stdio/vfscanf.c @@ -318,12 +318,12 @@ conv_brk (FILE *stream, width_t width, char *addr, const char *fmt) unsigned char frange; unsigned char cabove; int i; - + memset (msk, 0, sizeof(msk)); fnegate = 0; frange = 0; cabove = 0; /* init to avoid compiler warning */ - + for (i = 0; ; i++) { unsigned char c = GETBYTE(stream->flags, __SPGM, fmt); @@ -339,9 +339,9 @@ conv_brk (FILE *stream, width_t width, char *addr, const char *fmt) continue; } } - + if (!frange) cabove = c; - + for (;;) { msk[c >> 3] |= 1 << (c & 7); if (c == cabove) break; @@ -379,7 +379,7 @@ conv_brk (FILE *stream, width_t width, char *addr, const char *fmt) if (addr) *addr++ = i; fnegate = 0; } while (--width); - + if (fnegate) { return 0; } else { @@ -449,13 +449,13 @@ static unsigned char conv_flt (FILE *stream, width_t width, float *addr) operate_pstr: { unsigned char c; - + while ((c = pgm_read_byte (p++)) != 0) { if (!--width || (i = getc (stream)) < 0 || ((unsigned char)tolower(i) != c && (ungetc (i, stream), 1))) - { + { if (p == pstr_nfinity + 3) break; goto err; @@ -471,7 +471,7 @@ static unsigned char conv_flt (FILE *stream, width_t width, float *addr) do { unsigned char c = i - '0'; - + if (c <= 9) { flag |= FL_ANY; if (flag & FL_OVFL) { @@ -491,10 +491,10 @@ static unsigned char conv_flt (FILE *stream, width_t width, float *addr) break; } } while (--width && (i = getc (stream)) >= 0); - + if (!(flag & FL_ANY)) goto err; - + if ((unsigned char)i == 'e' || (unsigned char)i == 'E') { int expacc; @@ -521,7 +521,7 @@ static unsigned char conv_flt (FILE *stream, width_t width, float *addr) } if (width && i >= 0) ungetc (i, stream); - + x.flt = __floatunsisf (x.u32); if (exp < 0) { @@ -731,7 +731,7 @@ int vfscanf (FILE * stream, const char *fmt, va_list ap) ungetc (i, stream); break; } - + } else { flags = 0; @@ -808,7 +808,7 @@ int vfscanf (FILE * stream, const char *fmt, va_list ap) if (skip_spaces (stream) < 0) goto eof; - + switch (c) { case 's': diff --git a/libc/stdlib/atoi.S b/libc/stdlib/atoi.S index 9f95d615..39843a9b 100644 --- a/libc/stdlib/atoi.S +++ b/libc/stdlib/atoi.S @@ -24,7 +24,7 @@ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ + POSSIBILITY OF SUCH DAMAGE. */ /* $Id$ */ @@ -37,7 +37,7 @@ TODO: this implementation uses an inline isspace(). If Avr-libc will use locales other than C/POSIX it is needed to call an external isspace(). - + ATTENTION: an external __mulhi_const_10() function is used: nonstandart call conventions: some registers and bit T must be nochanged. */ @@ -46,7 +46,7 @@ /** \ingroup avr_stdlib \fn int atoi(const char *s) \brief Convert a string to an integer. - + The atoi() function converts the initial portion of the string pointed to by \p s to integer representation. In contrast to @@ -104,7 +104,7 @@ _U(atoi): BRNE .L_atoi_digit SET ; remember number is negative RJMP .L_atoi_loop2 - + 2: XCALL __mulhi_const_10 ; r25:r24 *= 10 ADD num_lo, tmp ; num = (num * 10) + (tmp - '0') ADC num_hi, __zero_reg__ diff --git a/libc/stdlib/atol.S b/libc/stdlib/atol.S index e42e9135..068bde51 100644 --- a/libc/stdlib/atol.S +++ b/libc/stdlib/atol.S @@ -38,7 +38,7 @@ TODO: this implementation uses an inline isspace(). If Avr-libc will use locales other than C/POSIX it is needed to call an external isspace(). - + ATTENTION: an external __mulsi_const_10() function is used: nonstandart call conventions: some registers and bit T must be nochanged. */ diff --git a/libc/stdlib/ctype.S b/libc/stdlib/ctype.S index 9e0ab5be..b468a123 100644 --- a/libc/stdlib/ctype.S +++ b/libc/stdlib/ctype.S @@ -160,7 +160,7 @@ GLOBAL(islower) GLOBAL(isdigit) CPSE rHigh,__zero_reg__ -1: +1: XJMP _U(__ctype_isfalse) SUBI rLow,'0' SUBI rLow,10 diff --git a/libc/stdlib/div.S b/libc/stdlib/div.S index fbdfc7e9..a474b8e6 100644 --- a/libc/stdlib/div.S +++ b/libc/stdlib/div.S @@ -34,4 +34,3 @@ .global div div: XJMP __divmodhi4 - diff --git a/libc/stdlib/dtoa_prf.c b/libc/stdlib/dtoa_prf.c index 1684ef19..70046f9b 100644 --- a/libc/stdlib/dtoa_prf.c +++ b/libc/stdlib/dtoa_prf.c @@ -49,7 +49,7 @@ ftoa_prf (float val, char *s, unsigned char width, unsigned char prec, exp = __ftoa_engine (val, (char *)buf, 7, ndigs); vtype = buf[0]; - sign = 0; + sign = 0; if ((vtype & (FTOA_MINUS | FTOA_NAN)) == FTOA_MINUS) sign = '-'; else if (flags & DTOA_PLUS) @@ -105,7 +105,7 @@ ftoa_prf (float val, char *s, unsigned char width, unsigned char prec, n = (sign ? 1 : 0) + (exp>0 ? exp+1 : 1) + (prec ? prec+1 : 0); width = width > n ? width - n : 0; - + if (!(flags & DTOA_LEFT) && !(flags & DTOA_ZFILL)) { while (width) { *s++ = ' '; @@ -141,7 +141,7 @@ ftoa_prf (float val, char *s, unsigned char width, unsigned char prec, if ( n == exp && (sign > '5' || (sign == '5' && !(vtype & FTOA_CARRY))) ) flags = '1'; *s++ = flags; - + while (width) { *s++ = ' '; width--; diff --git a/libc/stdlib/dtostre.c b/libc/stdlib/dtostre.c index c0581483..67095bf1 100644 --- a/libc/stdlib/dtostre.c +++ b/libc/stdlib/dtostre.c @@ -48,7 +48,7 @@ ftostre (float val, char *sbeg, unsigned char prec, unsigned char flags) unsigned char vtype; if (prec > 7) prec = 7; - + exp = __ftoa_engine (val, sbeg, prec, 0); s = d = sbeg; vtype = *s++; @@ -64,7 +64,7 @@ ftostre (float val, char *sbeg, unsigned char prec, unsigned char flags) s = str_nan[0]; goto copy; } - + if (vtype & FTOA_INF) { s = str_inf[0]; copy: @@ -73,7 +73,7 @@ ftostre (float val, char *sbeg, unsigned char prec, unsigned char flags) strcpy_P (d, s); goto ret; } - + /* mantissa */ if ( (*d++ = *s++) != '1') vtype &= ~FTOA_CARRY; /* for possible exponent "-00" */ @@ -103,7 +103,7 @@ ftostre (float val, char *sbeg, unsigned char prec, unsigned char flags) *d++ = prec; *d++ = '0' + exp; *d = 0; - + ret: return sbeg; } diff --git a/libc/stdlib/ftoa_engine.S b/libc/stdlib/ftoa_engine.S index 9a54866d..af59acb3 100644 --- a/libc/stdlib/ftoa_engine.S +++ b/libc/stdlib/ftoa_engine.S @@ -103,7 +103,7 @@ #define zero r1 ASSEMBLY_CLIB_SECTION - + .global __ftoa_engine .type __ftoa_engine, "function" __ftoa_engine: @@ -395,7 +395,7 @@ __ftoa_engine: brsh 23f mov prec, maxdgs 23: inc prec - mov maxdgs, prec + mov maxdgs, prec ; operate digit 25: cpi digit, '0' + 10 brlo 27f diff --git a/libc/stdlib/ldiv.S b/libc/stdlib/ldiv.S index a53d16bc..d9877f1d 100644 --- a/libc/stdlib/ldiv.S +++ b/libc/stdlib/ldiv.S @@ -26,7 +26,7 @@ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ - + /* ldiv() is the same as __divmodsi4() in libgcc */ #include "macros.inc" @@ -35,4 +35,3 @@ .global ldiv ldiv: XJMP __divmodsi4 - diff --git a/libc/stdlib/malloc.c b/libc/stdlib/malloc.c index 70a847ca..529bbdec 100644 --- a/libc/stdlib/malloc.c +++ b/libc/stdlib/malloc.c @@ -29,8 +29,8 @@ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ - - + + /* $Id$ */ #include @@ -53,7 +53,7 @@ char mymem[256]; * calls must not require more stack space, or they'll risk to collide * with the data segment. */ - + /* May be changed by the user only before the first malloc() call. */ size_t __malloc_margin = 32; @@ -416,4 +416,3 @@ main(void) } #endif /* MALLOC_TEST */ - diff --git a/libc/stdlib/qsort.c b/libc/stdlib/qsort.c index 51a50564..83cdcdc5 100644 --- a/libc/stdlib/qsort.c +++ b/libc/stdlib/qsort.c @@ -149,4 +149,3 @@ qsort(void *a, size_t n, size_t es, cmp_t *cmp) } /* qsort(pn - r, r / es, es, cmp);*/ } - diff --git a/libc/stdlib/rand.c b/libc/stdlib/rand.c index abc20809..5150f56f 100644 --- a/libc/stdlib/rand.c +++ b/libc/stdlib/rand.c @@ -99,4 +99,3 @@ srand(unsigned int seed) { next = seed; } - diff --git a/libc/stdlib/random.c b/libc/stdlib/random.c index 9952f3d9..e48a227d 100644 --- a/libc/stdlib/random.c +++ b/libc/stdlib/random.c @@ -89,4 +89,3 @@ srandom(unsigned long seed) { next = seed; } - diff --git a/libc/stdlib/realloc.c b/libc/stdlib/realloc.c index eeaae4c8..21482e1c 100644 --- a/libc/stdlib/realloc.c +++ b/libc/stdlib/realloc.c @@ -149,4 +149,3 @@ realloc(void *ptr, size_t len) free(ptr); return memp; } - diff --git a/libc/stdlib/setjmp.S b/libc/stdlib/setjmp.S index 9b7e30f4..4140f1c5 100644 --- a/libc/stdlib/setjmp.S +++ b/libc/stdlib/setjmp.S @@ -97,7 +97,7 @@ _U(setjmp): ; save stack pointer (after poping) in ret_lo, AVR_STACK_POINTER_LO_ADDR st X+, ret_lo -#ifdef _HAVE_AVR_STACK_POINTER_HI +#ifdef _HAVE_AVR_STACK_POINTER_HI in ret_lo, AVR_STACK_POINTER_HI_ADDR st X+, ret_lo #else diff --git a/libc/stdlib/stdlib_private.h b/libc/stdlib/stdlib_private.h index 41797018..2c01e116 100644 --- a/libc/stdlib/stdlib_private.h +++ b/libc/stdlib/stdlib_private.h @@ -76,11 +76,11 @@ extern void *myrealloc(void *, size_t); #define __heap_start mymem[0] #define __heap_end mymem[256] -extern char mymem[]; +extern char mymem[]; #define STACK_POINTER() (mymem + 256) #else /* !MALLOC_TEST */ - + extern char __heap_start; extern char __heap_end; diff --git a/libc/stdlib/strtod.c b/libc/stdlib/strtod.c index 021f00aa..3e3006a2 100644 --- a/libc/stdlib/strtod.c +++ b/libc/stdlib/strtod.c @@ -123,7 +123,7 @@ strtof (const char * nptr, char ** endptr) } else if (c == '+') { c = *nptr++; } - + if (!strncasecmp_P (nptr - 1, pstr_inf, 3)) { nptr += 2; if (!strncasecmp_P (nptr, pstr_inity, 5)) @@ -132,7 +132,7 @@ strtof (const char * nptr, char ** endptr) *endptr = (char *)nptr; return flag & FL_MINUS ? -INFINITYf : +INFINITYf; } - + /* NAN() construction is not realised. Length would be 3 characters only. */ if (!strncasecmp_P (nptr - 1, pstr_nan, 3)) { @@ -144,9 +144,9 @@ strtof (const char * nptr, char ** endptr) x.u32 = 0; exp = 0; while (1) { - + c -= '0'; - + if (c <= 9) { flag |= FL_ANY; if (flag & FL_OVFL) { @@ -168,7 +168,7 @@ strtof (const char * nptr, char ** endptr) } c = *nptr++; } - + if (c == (('e'-'0') & 0xff) || c == (('E'-'0') & 0xff)) { int i; @@ -197,14 +197,14 @@ strtof (const char * nptr, char ** endptr) exp += i; } } - + if ((flag & FL_ANY) && endptr) *endptr = (char *)nptr - 1; - + x.flt = __floatunsisf (x.u32); /* manually */ if ((flag & FL_MINUS) && (flag & FL_ANY)) x.flt = -x.flt; - + if (x.flt != 0) { int pwr; if (exp < 0) { diff --git a/libc/string/ffsll.S b/libc/string/ffsll.S index bcba6251..85881cdf 100644 --- a/libc/string/ffsll.S +++ b/libc/string/ffsll.S @@ -68,7 +68,7 @@ _U(ffsll): subi cntr, -16 sbiw wrd_lo, 0 breq 9f - + 1: tst wrd_lo brne 3f subi cntr, -7 @@ -76,11 +76,11 @@ _U(ffsll): 2: inc cntr 3: ror wrd_lo brcc 2b - + mov r24, cntr clr r25 9: ret - + .size _U(ffsll), . - _U(ffsll) .end diff --git a/libc/string/memmem.S b/libc/string/memmem.S index da83c3fd..dd4b0f6d 100644 --- a/libc/string/memmem.S +++ b/libc/string/memmem.S @@ -58,7 +58,7 @@ ENTRY memmem cp len2_lo, __zero_reg__ cpc len2_hi, __zero_reg__ breq .L_ret ; s2[] is empty - + push beg2 push c1 @@ -70,7 +70,7 @@ ENTRY memmem X_movw ZL, s2_lo LOAD beg2, Z+ ; beg2 = s2[0] X_movw s2_lo, ZL ; save: address of s2[1] - + 1: X_movw XL, s1_lo ; goto to begin of s1[] 2: cp XL, len1_lo ; find first char that is matched @@ -94,7 +94,7 @@ ENTRY memmem cp c1, c2 breq 3b rjmp 1b ; no equal - + .L_nomatch: ldi s1_lo, lo8(1) ldi s1_hi, hi8(1) diff --git a/libc/string/strcasestr_P.S b/libc/string/strcasestr_P.S index 970d71e2..f5955a12 100644 --- a/libc/string/strcasestr_P.S +++ b/libc/string/strcasestr_P.S @@ -25,7 +25,7 @@ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ - + /* $Id$ */ #define Lprogmem 1 diff --git a/libc/string/strrev.S b/libc/string/strrev.S index 9437b4f6..2d2928ec 100644 --- a/libc/string/strrev.S +++ b/libc/string/strrev.S @@ -68,7 +68,7 @@ _U(strrev): 3: cp XL, ZL cpc XH, ZH brlo 2b - + ret .size _U(strrev), . - _U(strrev) diff --git a/libm/fplib/Files.am b/libm/fplib/Files.am index e9cb0e8b..b906b8da 100644 --- a/libm/fplib/Files.am +++ b/libm/fplib/Files.am @@ -29,7 +29,7 @@ # $Id$ # -libm_a_c_sources = +libm_a_c_sources = libm_a_asm_sources = \ acos.S \ diff --git a/libm/fplib/acos.S b/libm/fplib/acos.S index db014770..d2a0a441 100644 --- a/libm/fplib/acos.S +++ b/libm/fplib/acos.S @@ -33,10 +33,10 @@ The acosf() function calculates the arc cosine of x; that is the value whose cosine is x. */ - - + + #if !defined(__AVR_TINY__) - + #include "fp32def.h" #include "asmdef.h" diff --git a/libm/fplib/asmdef.h b/libm/fplib/asmdef.h index 76fc7db9..810c0672 100644 --- a/libm/fplib/asmdef.h +++ b/libm/fplib/asmdef.h @@ -204,7 +204,7 @@ _U(\lname): lpm / mov Rd,r0 lpm / adiw ZL,1 lpm / mov Rd,r0 / adiw ZL,1 - + For enhanced chips it is one instruction always. ATTENTION: unlike enhanced chips SREG (S,V,N,Z,C) flags are @@ -218,7 +218,7 @@ _U(\lname): .exitm ; do not multiply errors .endif - /* src evaluation */ + /* src evaluation */ .L__lpm_src = -1 .L__lpm_n = 0 .irp reg, z,Z,z+,Z+ @@ -232,7 +232,7 @@ _U(\lname): .err ; Invalid src arg of 'X_lpm' macro. .endif - /* instruction(s) */ + /* instruction(s) */ .if .L__lpm_src < 2 .if .L__lpm_dst == 0 lpm diff --git a/libm/fplib/atan2.S b/libm/fplib/atan2.S index c0ebfe76..ba44ce37 100644 --- a/libm/fplib/atan2.S +++ b/libm/fplib/atan2.S @@ -35,7 +35,7 @@ that the signs of both arguments are used to determine the quadrant of the result. The atan2f() function returns the result in radians, which is between -PI and PI (inclusive). - + Note: This implementation returns +0.0 in all four cases: +0/+0, +0/-0, -0/+0 and -0/-0. Unlike x86 (GCC/Glibc). diff --git a/libm/fplib/cbrt.S b/libm/fplib/cbrt.S index 4b33cf15..fc448c44 100644 --- a/libm/fplib/cbrt.S +++ b/libm/fplib/cbrt.S @@ -339,7 +339,7 @@ ENTRY_FLOAT cbrtf cbrt cbrtl rol RM6 dec RD0 brne 25b - + dec RCNT breq 26f rjmp .Loop2 diff --git a/libm/fplib/divsf3x.S b/libm/fplib/divsf3x.S index f05e47c1..73597f56 100644 --- a/libm/fplib/divsf3x.S +++ b/libm/fplib/divsf3x.S @@ -67,10 +67,10 @@ ENTRY __divsf3_pse ; post split entry breq 1b tst rB3 breq .L_inf ; finite / 0.0 --> Inf - + sub rA3, rB3 sbc rB3, rB3 - + /* Prepare to division: A: rAE.rA2.rA1.rA0 0x00000001..0x00FFFFFF B: rBE.rB2.rB1.rB0 0x00000002..0x01FFFFFE @@ -119,9 +119,9 @@ ENTRY __divsf3_pse ; post split entry sbc rAE, rAE 4: mov rA2, r0 - X_movw rA0, ZL + X_movw rA0, ZL clr ZH - + ; exponent += 125 subi rA3, lo8(-125) sbci rB3, hi8(-125) diff --git a/libm/fplib/exp.S b/libm/fplib/exp.S index ec9ef92c..a3ba843a 100644 --- a/libm/fplib/exp.S +++ b/libm/fplib/exp.S @@ -109,7 +109,7 @@ ENTRY_FLOAT expf exp expl XJMP _U(inverse) ret ENDFUNC - + PGM_SECTION .L_table: .byte 7 diff --git a/libm/fplib/fixsfdi.S b/libm/fplib/fixsfdi.S index 1d17105c..57002d5c 100644 --- a/libm/fplib/fixsfdi.S +++ b/libm/fplib/fixsfdi.S @@ -55,7 +55,7 @@ ENTRY __fixsfdi or NaN, the 0 is returned. For negative x (if fabs(x) < 2**64, result is corresponded to signed conversion (with possible overflow). This is similar to Gcc+Glibc in 'float --> unsigned long' conversion case. - + Examples: __fixunssfdi(-1.0) --> 0xff..ffLL __fixunssfdi(0x0.ffffffp+63) --> 0x7fffff8000000000LL @@ -63,7 +63,7 @@ ENTRY __fixsfdi __fixunssfdi(0x1.000002p+63) --> 0x8000010000000000LL __fixunssfdi(0x1.fffffep+63) --> 0xffffff0000000000LL __fixunssfdi(0x1.000000p+64) --> 0LL - + Note: Gcc+Glibc give the strange results for negative x in such convers. */ ENTRY __fixunssfdi @@ -132,7 +132,7 @@ ENTRY __fixunssfdi clr rA2 subi rAE, 8 brpl 4b - + 5: subi rAE, -8 ; rAE = 0..7 breq .L_sign ; shift to 1..7 positions diff --git a/libm/fplib/fixunssfsi.S b/libm/fplib/fixunssfsi.S index 8e7fd66b..07d67c93 100644 --- a/libm/fplib/fixunssfsi.S +++ b/libm/fplib/fixunssfsi.S @@ -99,7 +99,7 @@ ENTRY __fixunssfsi ; fabs(A) <= 0x0.ffffffp+23 ; Shift A to right by 1 (rA3==-1) .. 23 (rA3==-23) positions. - + 3: mov rA0, rA1 mov rA1, rA2 clr rA2 @@ -108,7 +108,7 @@ ENTRY __fixunssfsi 4: cpi rAE, -7 brlt 3b ; quick shift is possible - + 5: lsr rA2 ror rA1 ror rA0 diff --git a/libm/fplib/floatsisf.S b/libm/fplib/floatsisf.S index 3e29c247..f487d852 100644 --- a/libm/fplib/floatsisf.S +++ b/libm/fplib/floatsisf.S @@ -41,7 +41,7 @@ ENTRY __floatunsisf clt rjmp 1f - + ENTRY __floatsisf bst rA3, 7 ; sign brtc 1f @@ -91,7 +91,7 @@ ENTRY __floatsisf mov rA2, rA1 mov rA1, rA0 rjmp 7f - + 6: tst rA0 breq 9f ; 0.0 ldi rA3, 127 + 7 diff --git a/libm/fplib/floatundisf.S b/libm/fplib/floatundisf.S index a1c77f93..bc941bbb 100644 --- a/libm/fplib/floatundisf.S +++ b/libm/fplib/floatundisf.S @@ -45,7 +45,7 @@ ENTRY __floatundisf clt ; result sign - + ENTRY __fp_di2sf mov ZH, rA3 ldi rA3, 127 + 55 ; exponent for 00.80.00.00.00.00.00.00 @@ -88,7 +88,7 @@ ENTRY __fp_di2sf mov rB1, rB0 ldi rB0, 0 breq 3b ; Z is result of 'or rA2,rA1' - + /* rA2 is not 0. It is needed shift to left by 0..7 positions. Optimization: rB2..rB0 are not shifted. Instead, save an info about tail in rB2. */ diff --git a/libm/fplib/fma.S b/libm/fplib/fma.S index 5b745a72..3563499c 100644 --- a/libm/fplib/fma.S +++ b/libm/fplib/fma.S @@ -35,8 +35,8 @@ #include "asmdef.h" /* float fmaf (float A, float B, float C) - The `fmaf' function performs floating-point multiply-add. This is the - operation (A * B) + C, but the intermediate result is not rounded to + The `fmaf' function performs floating-point multiply-add. This is the + operation (A * B) + C, but the intermediate result is not rounded to the destination type. This can sometimes improve the precision of a calculation. */ diff --git a/libm/fplib/fp_arccos.S b/libm/fplib/fp_arccos.S index 97b62435..f1e557a8 100644 --- a/libm/fplib/fp_arccos.S +++ b/libm/fplib/fp_arccos.S @@ -78,7 +78,7 @@ ENTRY __fp_arccos movw rB0, rC0 movw rB2, rC2 - + ; restore and multiply pop rC0 pop rC1 @@ -108,7 +108,7 @@ ENTRY __fp_arccos push rA2 push rA1 push rA0 - ; sqrt(1-A) + ; sqrt(1-A) ldi rA0, lo8(FL_1) ldi rA1, hi8(FL_1) ldi rA2, hlo8(FL_1) @@ -124,7 +124,7 @@ ENTRY __fp_arccos #endif ENDFUNC - + PGM_SECTION .L_table: .byte 7 diff --git a/libm/fplib/fp_mintl.S b/libm/fplib/fp_mintl.S index 7b631089..f76fbcea 100644 --- a/libm/fplib/fp_mintl.S +++ b/libm/fplib/fp_mintl.S @@ -68,7 +68,7 @@ ENTRY __fp_mintl brne 2f clr rA3 rjmp .L_sign - ; low mantissa byte != 0 + ; low mantissa byte != 0 2: subi rA3, 16 or rA2, rA0 ; to obtain N flag (rA2 was 0) ldi rA1, 0 diff --git a/libm/fplib/fp_powser.S b/libm/fplib/fp_powser.S index 61a78054..ab19811a 100644 --- a/libm/fplib/fp_powser.S +++ b/libm/fplib/fp_powser.S @@ -72,7 +72,7 @@ ENTRY __fp_powser X_movw rC2, rA2 set ; as flag to return - rjmp .Load5 + rjmp .Load5 1: mov rcntr, rBE .Loop: X_movw YL, ZL @@ -96,7 +96,7 @@ ENTRY __fp_powser X_movw rB2, rC2 dec rcntr brne .Loop - + pop rcntr pop rC0 pop rC1 diff --git a/libm/fplib/fp_powsodd.S b/libm/fplib/fp_powsodd.S index 61d575a8..60e9839b 100644 --- a/libm/fplib/fp_powsodd.S +++ b/libm/fplib/fp_powsodd.S @@ -50,7 +50,7 @@ ENTRY __fp_powsodd push rA2 push rA1 push rA0 - + push ZH push ZL diff --git a/libm/fplib/fp_sinus.S b/libm/fplib/fp_sinus.S index 29f438a6..aa6bed26 100644 --- a/libm/fplib/fp_sinus.S +++ b/libm/fplib/fp_sinus.S @@ -42,7 +42,7 @@ ENTRY __fp_sinus push ZL - + sbrs ZL, 0 rjmp 1f ldi rBE, LO40_PIO2 @@ -63,7 +63,7 @@ ENTRY __fp_sinus ldi ZH, hi8(.L_table) XJMP _U(__fp_powsodd) ENDFUNC - + PGM_SECTION .L_table: .byte 5 @@ -73,6 +73,6 @@ ENDFUNC .byte 0x91,0x86,0x88,0x08,0x3c ; 0.0083333315 .byte 0xa6,0xaa,0xaa,0x2a,0xbe ; -0.1666666664 .byte 0x00,0x00,0x00,0x80,0x3f ; 1.0000000000 - .end + .end #endif /* !defined(__AVR_TINY__) */ diff --git a/libm/fplib/hypot.S b/libm/fplib/hypot.S index 170fe8de..1ce330fa 100644 --- a/libm/fplib/hypot.S +++ b/libm/fplib/hypot.S @@ -162,19 +162,19 @@ ENTRY_FLOAT hypotf hypot hypotl push rC2 push rC1 push rC0 - + movw rC0, rB0 movw rC2, rB2 - + clr rAE mov rBE, rAE movw rB0, rA0 movw rB2, rA2 XCALL _U(__mulsf3_pse) - + movw rB0, rC0 movw rB2, rC2 - + push rAE movw rC0, rA0 movw rC2, rA2 @@ -185,21 +185,21 @@ ENTRY_FLOAT hypotf hypot hypotl movw rA2, rB2 XCALL _U(__mulsf3_pse) - pop rBE + pop rBE movw rB0, rC0 movw rB2, rC2 - + pop rC0 pop rC1 pop rC2 pop rC3 - + #else /* to __AVR_HAVE_MOVW__ */ push rB3 push rB2 push rB1 push rB0 - + clr rAE mov rBE, rAE mov rB0, rA0 @@ -207,7 +207,7 @@ ENTRY_FLOAT hypotf hypot hypotl mov rB2, rA2 mov rB3, rA3 XCALL _U(__mulsf3_pse) - + pop rB0 pop rB1 pop rB2 @@ -218,7 +218,7 @@ ENTRY_FLOAT hypotf hypot hypotl push rA1 push rA0 push rAE - + clr rBE mov rAE, rBE mov rA0, rB0 @@ -226,14 +226,14 @@ ENTRY_FLOAT hypotf hypot hypotl mov rA2, rB2 mov rA3, rB3 XCALL _U(__mulsf3_pse) - + pop rBE pop rB0 pop rB1 pop rB2 pop rB3 #endif /* ! __AVR_HAVE_MOVW__ */ - + XCALL _U(__addsf3x) XCALL _U(__fp_round) XCALL _U(sqrtf) diff --git a/libm/fplib/log.S b/libm/fplib/log.S index fca113e8..6504d289 100644 --- a/libm/fplib/log.S +++ b/libm/fplib/log.S @@ -61,7 +61,7 @@ ENTRY_FLOAT logf log logl tst rA3 breq .L_min ; -Inf brts .L_nan ; log(negative) - + push rC3 push rC2 push rC1 @@ -119,7 +119,7 @@ ENTRY_FLOAT logf log logl ldi rB2, hlo8(LN_2) ldi rB3, hhi8(LN_2) XCALL _U(__mulsf3x) - + mov rBE, rCE X_movw rB0, rC0 X_movw rB2, rC2 @@ -129,11 +129,11 @@ ENTRY_FLOAT logf log logl pop rC1 pop rC2 pop rC3 - + XCALL _U(__addsf3x) XJMP _U(__fp_round) ENDFUNC - + PGM_SECTION .L_tlow: ; __fp_powser() table for small values @@ -159,7 +159,7 @@ ENDFUNC .byte 0x4c,0x80,0xef,0xff,0xbe ; -0.4998741238 .byte 0x01,0xc4,0xff,0x7f,0x3f ; 0.9999964239 .byte 0x00,0x00,0x00,0x00,0x00 ; 0.0000000000 - + .end #endif /* !defined(__AVR_TINY__) */ diff --git a/libm/fplib/pow.S b/libm/fplib/pow.S index ecf8fdc3..88ab6e9b 100644 --- a/libm/fplib/pow.S +++ b/libm/fplib/pow.S @@ -46,56 +46,56 @@ +0 -Inf +Inf exp(log(x)*y) +0 y > 0 +0 exp(log(x)*y) +0 y < 0 +Inf exp(log(x)*y) - + -0 NaN NaN exp(log(x)*y) -0 +0,-0 +1 -0 1,3,5... -0 -exp(log(x)*y) -0 y > 0 +0 exp(log(x)*y) -0 -1,-3,-5... -Inf -exp(log(x)*y) -0 y < 0 +Inf exp(log(x)*y) - + +1 NaN +1 +1 +Inf,-Inf +1 +1 else +1 exp(log(x)*y) - + -1 +0,-0 +1 -1 1,3,5... -1 -1 -1,-3,-5... -1 -1 2,4,6... +1 -1 -2,-4,-6... +1 -1 else NaN exp(log(x)*y) - + +Inf NaN NaN exp(log(x)*y) +Inf +0,-0 +1 +Inf y > 0 +Inf exp(log(x)*y) +Inf y < 0 +0 exp(log(x)*y) - + -Inf NaN NaN exp(log(x)*y) -Inf +0,-0 +1 -Inf 1,3,5... -Inf -Inf y > 0 +Inf -Inf -1,-3,-5... -0 -Inf y < 0 +0 - + NaN +0,-0 +1 NaN else NaN exp(log(x)*y) - + (0,1) NaN NaN exp(log(x)*y) (0,1) +0,-0 +1 exp(log(x)*y) (0,1) +Inf +0 exp(log(x)*y) (0,1) -Inf +Inf exp(log(x)*y) - + (-1,0) NaN NaN (-1,0) +0,-0 +1 (-1,0) +Inf +0 (-1,0) -Inf +Inf (-1,0) nonintegral NaN - + x > 1 NaN NaN x > 1 +0,-0 +1 x > 1 +Inf +Inf x > 1 -Inf +0 - + x < -1 NaN NaN x < -1 +0,-0 +1 x < -1 +Inf +Inf diff --git a/libm/fplib/sinh.S b/libm/fplib/sinh.S index 734ac689..e7ec3a5a 100644 --- a/libm/fplib/sinh.S +++ b/libm/fplib/sinh.S @@ -90,7 +90,7 @@ ENTRY_FLOAT sinhf sinh sinhl ori rA3, 0x80 ret ENDFUNC - + PGM_SECTION .L_table: .byte 2 diff --git a/libm/fplib/sqrt.S b/libm/fplib/sqrt.S index f92b87a8..204b6da0 100644 --- a/libm/fplib/sqrt.S +++ b/libm/fplib/sqrt.S @@ -1,7 +1,7 @@ /* Copyright (c) 2002 Michael Stumpf Copyright (c) 2006 Dmitry Xmelkov Copyright (c) 2008 Ruud v Gessel - + All rights reserved. Redistribution and use in source and binary forms, with or without @@ -111,7 +111,7 @@ ENTRY_FLOAT sqrtf sqrt sqrtl ; Loop for bit 0 and rounding .Loop1: lsl rA0 rol rA1 - rol rA2 ; Shift left remainder argument + rol rA2 ; Shift left remainder argument brcs 4f ; C--> Last bits always 1 cp rB0, rA0 cpc rB1, rA1 diff --git a/libm/fplib/tan.S b/libm/fplib/tan.S index 1f3d3f62..41cf6e02 100644 --- a/libm/fplib/tan.S +++ b/libm/fplib/tan.S @@ -97,7 +97,7 @@ ENTRY_FLOAT tanf tan tanl 3: pop rsign ret ENDFUNC - + PGM_SECTION .L_table: .byte 6 diff --git a/libm/fplib/unordsf2.S b/libm/fplib/unordsf2.S index 354b06ac..3f6e1bf6 100644 --- a/libm/fplib/unordsf2.S +++ b/libm/fplib/unordsf2.S @@ -31,7 +31,7 @@ /* int __unordsf2 (float A, float B) This function returns a nonzero value if either argument is NaN, otherwise 0. - + As this function is not used often, speed is brocken to reduce size. */